diff --git a/.gitmodules b/.gitmodules index 72726db3..4078391d 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,3 @@ [submodule "nf-interpreter"] - path = nf-interpreter + path = source/native/nf-interpreter url = https://github.com/nanoframework/nf-interpreter diff --git a/README.md b/README.md index 2ba6145b..66ff55f6 100644 --- a/README.md +++ b/README.md @@ -10,6 +10,9 @@ This repo contains **nanoFramework** metadata processor tool. It's a console app that performs various tasks when running a build of a C# project, like parsing the PE file generated by Roslyn, generating the PDBX files, generate the stubs for native code. Is part of **nanoFramework** toolbox, along with other various tools that are required in **nanoFramework** development, usage or repository management. +Version 2.0 is a C# application adapted from the original work of [Oleg Rakhmatulin](@OlegRa). +Version 1.0 was a Visual C++ application adapted from .NETMF toolbox. + ## Feedback and documentation To provide feedback, report issues and finding out how to contribute please refer to the [Home repo](https://github.com/nanoframework/Home). diff --git a/azure-pipelines.yml b/azure-pipelines.yml index 3605056a..8b6406b6 100644 --- a/azure-pipelines.yml +++ b/azure-pipelines.yml @@ -115,9 +115,9 @@ jobs: - task: NuGetCommand@2 inputs: command: 'custom' - arguments: 'pack source\Tools.MetaDataProcessor\package.nuspec -Version $(NBGV_NuGetPackageVersion)' + arguments: 'pack source\MetadataProcessor.Console\package.nuspec -Version $(NBGV_NuGetPackageVersion)' condition: succeeded() - displayName: Pack NuGet with MDP tool + displayName: Pack NuGet for MDP tool - task: CopyFiles@1 inputs: @@ -145,6 +145,7 @@ jobs: nuGetFeedType: external packagesToPush: '$(Build.ArtifactStagingDirectory)/*.nupkg' publishFeedCredentials: 'AzureArtifacts' + continueOnError: true condition: succeeded() displayName: Push NuGet packages to Azure Artifacts diff --git a/nf-interpreter b/nf-interpreter deleted file mode 160000 index 73389fad..00000000 --- a/nf-interpreter +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 73389fad32cba0175ccc666f76c6d02c211d594b diff --git a/source/MetadataProcessor.Console/FodyWeavers.xml b/source/MetadataProcessor.Console/FodyWeavers.xml new file mode 100644 index 00000000..0ed55b76 --- /dev/null +++ b/source/MetadataProcessor.Console/FodyWeavers.xml @@ -0,0 +1,10 @@ + + + + + CommandLine + nanoFramework.Tools.MetadataProcessor* + Mono.* + + + diff --git a/source/MetadataProcessor.Console/FodyWeavers.xsd b/source/MetadataProcessor.Console/FodyWeavers.xsd new file mode 100644 index 00000000..44a53744 --- /dev/null +++ b/source/MetadataProcessor.Console/FodyWeavers.xsd @@ -0,0 +1,111 @@ + + + + + + + + + + + + A list of assembly names to exclude from the default action of "embed all Copy Local references", delimited with line breaks + + + + + A list of assembly names to include from the default action of "embed all Copy Local references", delimited with line breaks. + + + + + A list of unmanaged 32 bit assembly names to include, delimited with line breaks. + + + + + A list of unmanaged 64 bit assembly names to include, delimited with line breaks. + + + + + The order of preloaded assemblies, delimited with line breaks. + + + + + + This will copy embedded files to disk before loading them into memory. This is helpful for some scenarios that expected an assembly to be loaded from a physical file. + + + + + Controls if .pdbs for reference assemblies are also embedded. + + + + + Embedded assemblies are compressed by default, and uncompressed when they are loaded. You can turn compression off with this option. + + + + + As part of Costura, embedded assemblies are no longer included as part of the build. This cleanup can be turned off. + + + + + Costura by default will load as part of the module initialization. This flag disables that behavior. Make sure you call CosturaUtility.Initialize() somewhere in your code. + + + + + Costura will by default use assemblies with a name like 'resources.dll' as a satellite resource and prepend the output path. This flag disables that behavior. + + + + + A list of assembly names to exclude from the default action of "embed all Copy Local references", delimited with | + + + + + A list of assembly names to include from the default action of "embed all Copy Local references", delimited with |. + + + + + A list of unmanaged 32 bit assembly names to include, delimited with |. + + + + + A list of unmanaged 64 bit assembly names to include, delimited with |. + + + + + The order of preloaded assemblies, delimited with |. + + + + + + + + 'true' to run assembly verification (PEVerify) on the target assembly after all weavers have been executed. + + + + + A comma-separated list of error codes that can be safely ignored in assembly verification. + + + + + 'false' to turn off automatic generation of the XML Schema file. + + + + + \ No newline at end of file diff --git a/source/MetadataProcessor.Console/MetadataProcessor.Console.csproj b/source/MetadataProcessor.Console/MetadataProcessor.Console.csproj new file mode 100644 index 00000000..c8333759 --- /dev/null +++ b/source/MetadataProcessor.Console/MetadataProcessor.Console.csproj @@ -0,0 +1,88 @@ + + + + + Debug + AnyCPU + {A9E02E14-7321-4B12-8AB5-9A0408ED8FD0} + Exe + nanoFramework.Tools.MetadataProcessor.Console + nanoFramework.Tools.MetadataProcessor + v4.6.1 + + + + + + true + full + false + bin\Debug + DEBUG; + prompt + 4 + true + + + full + true + bin\Release + prompt + 4 + true + + + + ..\packages\CommandLineParser.2.6.0\lib\net461\CommandLine.dll + + + ..\packages\Costura.Fody.3.3.3\lib\net40\Costura.dll + + + ..\packages\Mono.Cecil.0.11.1\lib\net40\Mono.Cecil.dll + + + ..\packages\Mono.Cecil.0.11.1\lib\net40\Mono.Cecil.Mdb.dll + + + ..\packages\Mono.Cecil.0.11.1\lib\net40\Mono.Cecil.Pdb.dll + + + ..\packages\Mono.Cecil.0.11.1\lib\net40\Mono.Cecil.Rocks.dll + + + + + + + + + + + + + + + + + Designer + + + + + {e32f7d15-2499-440c-8026-4d5ee1c5ec3a} + MetadataProcessor.Core + True + + + + + + This project references NuGet package(s) that are missing on this computer. Use NuGet Package Restore to download them. For more information, see http://go.microsoft.com/fwlink/?LinkID=322105. The missing file is {0}. + + + + + + + \ No newline at end of file diff --git a/source/MetadataProcessor.Console/Options.cs b/source/MetadataProcessor.Console/Options.cs new file mode 100644 index 00000000..34d76397 --- /dev/null +++ b/source/MetadataProcessor.Console/Options.cs @@ -0,0 +1,38 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using CommandLine; +using System.Collections.Generic; + +namespace nanoFramework.Tools.MetadataProcessor.Console +{ + public class Options + { + + [Option( + "parse", + Required = false, + Default = null, + HelpText = "Analyses .NET assembly.")] + public string Parse { get; set; } + + [Option( + "compile", + Required = false, + Default = null, + HelpText = "Compiles an assembly into nanoCLR format.")] + public string Compile { get; set; } + + [Option( + "loadhints", + Separator = ' ', + Required = false, + HelpText = "Loads one (or more) assembly file(s) as a dependency(ies).")] + public IEnumerable LoadHints { get; set; } + + + } +} diff --git a/source/MetadataProcessor.Console/Program.cs b/source/MetadataProcessor.Console/Program.cs new file mode 100644 index 00000000..2a100270 --- /dev/null +++ b/source/MetadataProcessor.Console/Program.cs @@ -0,0 +1,172 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using CommandLine; +using CommandLine.Text; +using Mono.Cecil; +using System; +using System.Collections.Generic; +using System.IO; +using System.Linq; +using System.Reflection; +using System.Xml; + +namespace nanoFramework.Tools.MetadataProcessor.Console +{ + internal static class MainClass + { + private sealed class MetadataProcessor + { + private readonly IDictionary _loadHints = + new Dictionary(StringComparer.Ordinal); + + private AssemblyDefinition _assemblyDefinition; + + public void Parse(string fileName) + { + try + { + _assemblyDefinition = AssemblyDefinition.ReadAssembly(fileName, + new ReaderParameters { AssemblyResolver = new LoadHintsAssemblyResolver(_loadHints)}); + } + catch (Exception) + { + System.Console.Error.WriteLine( + "Unable to parse input assembly file '{0}' - check if path and file exists.", fileName); + Environment.Exit(1); + } + } + + public void Compile(string fileName) + { + try + { + var builder = new nanoAssemblyBuilder(_assemblyDefinition); + + using (var stream = File.Open(fileName, FileMode.Create, FileAccess.ReadWrite)) + using (var writer = new BinaryWriter(stream)) + { + builder.Write(GetBinaryWriter(writer)); + } + + using (var writer = XmlWriter.Create(Path.ChangeExtension(fileName, "pdbx"))) + { + builder.Write(writer); + } + } + catch (Exception) + { + System.Console.Error.WriteLine( + "Unable to compile output assembly file '{0}' - check parse command results.", fileName); + throw; + } + } + + private nanoBinaryWriter GetBinaryWriter(BinaryWriter writer) + { + return nanoBinaryWriter.CreateLittleEndianBinaryWriter(writer); + } + + public void AddLoadHint( + string assemblyName, + string assemblyFileName) + { + _loadHints[assemblyName] = assemblyFileName; + } + } + + public static void Main(string[] args) + { + // grab the assembly version + var informationalVersionAttribute = Attribute.GetCustomAttribute( + Assembly.GetEntryAssembly(), + typeof(AssemblyInformationalVersionAttribute)) + as AssemblyInformationalVersionAttribute; + + // build header information + var headerInfo = $"nanoFramework MetadataProcessor Utility v{informationalVersionAttribute.InformationalVersion}"; + var copyrightInfo = new CopyrightInfo(true, $"nanoFramework project contributors", 2019); + + // output header to console + System.Console.WriteLine($"nanoFramework MetadataProcessor Utility v{informationalVersionAttribute.InformationalVersion}"); + System.Console.WriteLine("Copyright (c) 2019 nanoFramework project contributors"); + System.Console.WriteLine(); + System.Console.WriteLine("For documentation, report issues and support visit our GitHub repo: www.github.com\\nanoFramework"); + System.Console.WriteLine(); + System.Console.WriteLine(); + + // check for empty argument collection + if (!args.Any()) + { + // no argument provided, show help text and usage examples + + // because of short-comings in CommandLine parsing + // need to customize the output to provide a consistent output + var parser = new Parser(config => config.HelpWriter = null); + var result = parser.ParseArguments(new string[] { "", "" }); + + var helpText = new HelpText( + new HeadingInfo(headerInfo), + copyrightInfo) + .AddPreOptionsLine("No command was provided.") + .AddPreOptionsLine("") + .AddPreOptionsLine(HelpText.RenderUsageText(result)) + .AddPreOptionsLine("") + .AddOptions(result); + + System.Console.WriteLine(helpText.ToString()); + + return; + } + + var parsedArguments = Parser.Default.ParseArguments(args); + + parsedArguments + .WithParsed(opts => RunOptionsAndReturnExitCode(opts)) + .WithNotParsed(errors => HandleErrors(errors)); + } + + static void RunOptionsAndReturnExitCode(Options o) + { + var md = new MetadataProcessor(); + + // arguments have to be processed in this order, otherwise the parsing will fail + + // load hints + if (o.LoadHints.Any()) + { + // load hints should be provided in the format: AssemblyName FilePath + // like in --loadhints mscorlib e:\folder\where\the\assembly\is\mscorlib.dll + // the LoadHints argument already provides the assembly details separated + + int hintCount = 0; + + do + { + md.AddLoadHint(o.LoadHints.ElementAt(hintCount++), o.LoadHints.ElementAt(hintCount++)); + } + while (hintCount < o.LoadHints.Count()); + } + + // parse assembly + if (!string.IsNullOrEmpty(o.Parse)) + { + md.Parse(o.Parse); + } + + // compile PE + if (!string.IsNullOrEmpty(o.Compile)) + { + md.Compile(o.Compile); + } + } + + static void HandleErrors(IEnumerable errors) + { + // empty on purpose + } + } +} diff --git a/source/MetadataProcessor.Console/Properties/AssemblyInfo.cs b/source/MetadataProcessor.Console/Properties/AssemblyInfo.cs new file mode 100644 index 00000000..bbae2c0a --- /dev/null +++ b/source/MetadataProcessor.Console/Properties/AssemblyInfo.cs @@ -0,0 +1,12 @@ +using System.Reflection; +using System.Runtime.CompilerServices; + +// Information about this assembly is defined by the following attributes. +// Change them to the values specific to your project. + +[assembly: AssemblyTitle ("nanoFramework.MetadataProcessor.Console")] +[assembly: AssemblyDescription("")] +[assembly: AssemblyConfiguration("")] +[assembly: AssemblyCompany("nanoFramework project contributors")] +[assembly: AssemblyProduct("")] +[assembly: AssemblyCopyright("Copyright (c) 2019 The nanoFramework project contributors")] diff --git a/source/MetadataProcessor.Console/app.config b/source/MetadataProcessor.Console/app.config new file mode 100644 index 00000000..3dbff35f --- /dev/null +++ b/source/MetadataProcessor.Console/app.config @@ -0,0 +1,3 @@ + + + diff --git a/source/Tools.MetaDataProcessor/nanoFramework.Tools.MetaDataProcessor.targets b/source/MetadataProcessor.Console/nanoFramework.Tools.MetaDataProcessor.targets similarity index 100% rename from source/Tools.MetaDataProcessor/nanoFramework.Tools.MetaDataProcessor.targets rename to source/MetadataProcessor.Console/nanoFramework.Tools.MetaDataProcessor.targets diff --git a/source/MetadataProcessor.Console/package.nuspec b/source/MetadataProcessor.Console/package.nuspec new file mode 100644 index 00000000..92ce174a --- /dev/null +++ b/source/MetadataProcessor.Console/package.nuspec @@ -0,0 +1,30 @@ + + + + nanoFramework.Tools.MetadataProcessor + nanoFramework.Tools.MetadataProcessor + $version$ + nanoFramework project contributors + nanoFramework project contributors + + Metadata Processor tool to be used internally by the VS nanoFramework extension. + + + + + Metadata Processor tool to be used internally by the VS nanoFramework extension. + + https://github.com/nanoframework/metadata-processor + https://secure.gravatar.com/avatar/97d0e092247f0716db6d4b47b7d1d1ad + false + https://github.com/nanoframework/metadata-processor/LICENSE + Copyright (c) 2019 The nanoFramework project contributors + + + nanoFramework, nano Framework, NETNF, NETMF, Micro Framework, .net + + + + + + diff --git a/source/MetadataProcessor.Console/packages.config b/source/MetadataProcessor.Console/packages.config new file mode 100644 index 00000000..6cd53721 --- /dev/null +++ b/source/MetadataProcessor.Console/packages.config @@ -0,0 +1,8 @@ + + + + + + + + \ No newline at end of file diff --git a/source/MetadataProcessor.Core/Endianness/nanoBinaryWriter.cs b/source/MetadataProcessor.Core/Endianness/nanoBinaryWriter.cs new file mode 100644 index 00000000..05d2ee10 --- /dev/null +++ b/source/MetadataProcessor.Core/Endianness/nanoBinaryWriter.cs @@ -0,0 +1,383 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using System; +using System.IO; +using System.Runtime.InteropServices; +using System.Text; + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Binary writer for .NET nanoFramework assemblies emitting. Supports different endianness. + /// + public abstract class nanoBinaryWriter + { + /// + /// Specialized big endian version of class. + /// + private sealed class BigEndianBinaryWriter : nanoBinaryWriter + { + /// + /// Emulates C++ union using explicit fields layout (with same zero offset) + /// + [StructLayout(LayoutKind.Explicit)] + private struct BytesMappingHelper + { + [FieldOffset(0)] + public ushort uint16Value; + + [FieldOffset(0)] + public uint uint32Value; + + [FieldOffset(0)] + public ulong uint64Value; + + [FieldOffset(0)] + public float singleValue; + + [FieldOffset(0)] + public double doubleValue; + + [FieldOffset(0)] + public unsafe fixed byte bytes[8]; + } + + private BytesMappingHelper _helper; + + /// + /// Creates new instance of object. + /// + /// Base binary writer for operating on stream. + public BigEndianBinaryWriter( + BinaryWriter baseWriter) + : base(baseWriter) + { + } + + /// + public override unsafe void WriteUInt16(ushort value) + { + _helper.uint16Value = value; + fixed (byte* pBytes = _helper.bytes) + { + _baseWriter.Write(pBytes[1]); + _baseWriter.Write(pBytes[0]); + } + } + + /// + public override unsafe void WriteUInt32(uint value) + { + _helper.uint32Value = value; + fixed (byte* pBytes = _helper.bytes) + { + _baseWriter.Write(pBytes[3]); + _baseWriter.Write(pBytes[2]); + _baseWriter.Write(pBytes[1]); + _baseWriter.Write(pBytes[0]); + } + } + + /// + public override unsafe void WriteUInt64(ulong value) + { + _helper.uint64Value = value; + fixed (byte* pBytes = _helper.bytes) + { + _baseWriter.Write(pBytes[7]); + _baseWriter.Write(pBytes[6]); + _baseWriter.Write(pBytes[5]); + _baseWriter.Write(pBytes[4]); + _baseWriter.Write(pBytes[3]); + _baseWriter.Write(pBytes[2]); + _baseWriter.Write(pBytes[1]); + _baseWriter.Write(pBytes[0]); + } + } + + /// + public override unsafe void WriteSingle(float value) + { + _helper.singleValue = value; + fixed (byte* pBytes = _helper.bytes) + { + _baseWriter.Write(pBytes[3]); + _baseWriter.Write(pBytes[2]); + _baseWriter.Write(pBytes[1]); + _baseWriter.Write(pBytes[0]); + } + } + + /// + public override unsafe void WriteDouble(double value) + { + _helper.doubleValue = value; + fixed (byte* pBytes = _helper.bytes) + { + _baseWriter.Write(pBytes[7]); + _baseWriter.Write(pBytes[6]); + _baseWriter.Write(pBytes[5]); + _baseWriter.Write(pBytes[4]); + _baseWriter.Write(pBytes[3]); + _baseWriter.Write(pBytes[2]); + _baseWriter.Write(pBytes[1]); + _baseWriter.Write(pBytes[0]); + } + } + + /// + public override nanoBinaryWriter GetMemoryBasedClone( + MemoryStream stream) + { + return new BigEndianBinaryWriter(new BinaryWriter(stream)); + } + } + + /// + /// Specialized little endian version of class. + /// + private sealed class LittleEndianBinaryWriter : nanoBinaryWriter + { + /// + /// Creates new instance of object. + /// + /// Base binary writer for operating on stream. + public LittleEndianBinaryWriter( + BinaryWriter baseWriter) + : base(baseWriter) + { + } + + /// + public override void WriteUInt16(ushort value) + { + _baseWriter.Write(value); + } + + /// + public override void WriteUInt32(uint value) + { + _baseWriter.Write(value); + } + + /// + public override void WriteUInt64(ulong value) + { + _baseWriter.Write(value); + } + + /// + public override void WriteSingle(float value) + { + _baseWriter.Write(value); + } + + /// + public override void WriteDouble(double value) + { + _baseWriter.Write(value); + } + + /// + public override nanoBinaryWriter GetMemoryBasedClone( + MemoryStream stream) + { + return new LittleEndianBinaryWriter(new BinaryWriter(stream)); + } + } + + /// + /// Base binary writer instance for performing basic operation on underlying byte stream. + /// By design is always little endian regardless of platform. + /// + private readonly BinaryWriter _baseWriter; + + /// + /// Creates new instance of object. + /// + /// Base binary writer for operating on stream. + protected nanoBinaryWriter( + BinaryWriter baseWriter) + { + _baseWriter = baseWriter; + } + + /// + /// Factory mathod for creating little endian version of class. + /// + /// Base binary writer for operating on stream. + /// + /// Instance of which writes bytes in little endian. + /// + public static nanoBinaryWriter CreateLittleEndianBinaryWriter( + BinaryWriter baseWriter) + { + return new LittleEndianBinaryWriter(baseWriter); + } + + /// + /// Factory mathod for creating big endian version of class. + /// + /// Base binary writer for operating on stream. + /// + /// Instance of which writes bytes in big endian. + /// + public static nanoBinaryWriter CreateBigEndianBinaryWriter( + BinaryWriter baseWriter) + { + return new BigEndianBinaryWriter(baseWriter); + } + + /// + /// Write single unsigned byte into underying stream. + /// + /// Unsigned byte value for writing. + public void WriteByte(byte value) + { + _baseWriter.Write(value); + } + + /// + /// Write single signed byte into underying stream. + /// + /// Signed byte value for writing. + public void WriteSByte(sbyte value) + { + _baseWriter.Write(value); + } + + /// + /// Write version information into underying stream. + /// + /// Version information value for writing. + public void WriteVersion(Version value) + { + WriteUInt16((ushort)value.Major); + WriteUInt16((ushort)value.Minor); + WriteUInt16((ushort)value.Build); + WriteUInt16((ushort)value.Revision); + } + + /// + /// Write raw string value (in UTF-8 encoding) into underying stream. + /// + /// String value for writing. + public void WriteString(string value) + { + _baseWriter.Write(Encoding.UTF8.GetBytes(value)); + WriteByte(0); + } + + /// + /// Write raw bytes array into underying stream. + /// + /// Raw bytes array for writing. + public void WriteBytes(byte[] value) + { + _baseWriter.Write(value); + } + + /// + /// Write single signed word into underying stream. + /// + /// Signed word value for writing. + public void WriteInt16(short value) + { + WriteUInt16((ushort)value); + } + + /// + /// Write single signed double word into underying stream. + /// + /// Signed double word value for writing. + public void WriteInt32(int value) + { + WriteUInt32((uint)value); + } + + /// + /// Write single signed quad word into underying stream. + /// + /// Signed quad word value for writing. + public void WriteInt64(long value) + { + WriteUInt64((ulong)value); + } + + /// + /// Write metadata token in packed format (variable length). + /// + /// Metadata tocken in .NET Mico Framework format. + public void WriteMetadataToken(uint value) + { + if (value <= 0x7F) + { + WriteByte((byte) value); + } + else if (value <= 0x3FFF) + { + WriteByte((byte)(value >> 8 | 0x80)); + WriteByte((byte)value); + } + else + { + WriteByte((byte)(value >> 24 | 0xC0)); + WriteByte((byte)(value >> 16)); + WriteByte((byte)(value >> 8)); + WriteByte((byte)value); + } + } + + /// + /// Write single unsigned word into underying stream. + /// + /// Unsigned word value for writing. + public abstract void WriteUInt16(ushort value); + + /// + /// Write single signed double word into underying stream. + /// + /// Unsigned double word value for writing. + public abstract void WriteUInt32(uint value); + + /// + /// Write single signed quad word into underying stream. + /// + /// Unsigned quad word value for writing. + public abstract void WriteUInt64(ulong value); + + /// + /// Write single floating point value (4 bytes) into underying stream. + /// + /// Floating point value for writing. + public abstract void WriteSingle(float value); + + /// + /// Write single floating point value (8 bytes) into underying stream. + /// + /// Floating point value for writing. + public abstract void WriteDouble(double value); + + /// + /// Creates new instance of object with same endiannes + /// as current instance but based on new base stream . + /// + /// Base binary writer for operating on stream for new writer. + /// New instance of object with same endiannes. + public abstract nanoBinaryWriter GetMemoryBasedClone(MemoryStream stream); + + /// + /// Gets base stream for this binary writer object (used for changing stream position). + /// + public Stream BaseStream { get { return _baseWriter.BaseStream; } } + + /// + /// Returns true in case of this binary writer is write data in big endian format. + /// + public bool IsBigEndian { get { return (this is BigEndianBinaryWriter); } } + } +} diff --git a/source/MetadataProcessor.Core/InanoTable.cs b/source/MetadataProcessor.Core/InanoTable.cs new file mode 100644 index 00000000..b4141367 --- /dev/null +++ b/source/MetadataProcessor.Core/InanoTable.cs @@ -0,0 +1,21 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Common interface for all metadata tables in .NET nanoFramework assembly. + /// + public interface InanoTable + { + /// + /// Writes metadata table from memory representation into output stream. + /// + /// Binary writer with correct endianness. + void Write( + nanoBinaryWriter writer); + } +} \ No newline at end of file diff --git a/source/MetadataProcessor.Core/MetadataProcessor.Core.csproj b/source/MetadataProcessor.Core/MetadataProcessor.Core.csproj new file mode 100644 index 00000000..0d6cd659 --- /dev/null +++ b/source/MetadataProcessor.Core/MetadataProcessor.Core.csproj @@ -0,0 +1,100 @@ + + + + Debug + AnyCPU + {E32F7D15-2499-440C-8026-4D5EE1C5EC3A} + Library + nanoFramework.Tools.MetadataProcessor.Core + nanoFramework.Tools.MetadataProcessor.Core + v4.6.1 + + + + + + true + full + false + bin\Debug + DEBUG; + prompt + 4 + false + true + + + full + true + bin\Release + prompt + 4 + false + true + + + + ..\packages\Mono.Cecil.0.11.1\lib\net40\Mono.Cecil.dll + + + ..\packages\Mono.Cecil.0.11.1\lib\net40\Mono.Cecil.Mdb.dll + + + ..\packages\Mono.Cecil.0.11.1\lib\net40\Mono.Cecil.Pdb.dll + + + ..\packages\Mono.Cecil.0.11.1\lib\net40\Mono.Cecil.Rocks.dll + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This project references NuGet package(s) that are missing on this computer. Use NuGet Package Restore to download them. For more information, see http://go.microsoft.com/fwlink/?LinkID=322105. The missing file is {0}. + + + + \ No newline at end of file diff --git a/source/MetadataProcessor.Core/Mono.Cecil/CodeWriter.cs b/source/MetadataProcessor.Core/Mono.Cecil/CodeWriter.cs new file mode 100644 index 00000000..cb63a734 --- /dev/null +++ b/source/MetadataProcessor.Core/Mono.Cecil/CodeWriter.cs @@ -0,0 +1,518 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using Mono.Cecil; +using Mono.Cecil.Cil; +using System; +using System.Collections.Generic; +using System.Linq; + +namespace nanoFramework.Tools.MetadataProcessor +{ + + /// + /// Encapsulates logic related for writing correct byte code and calculating stack size. + /// + /// + /// This class initially copy-pasted from Mono.Cecil codebase but changed a lot. + /// + internal sealed class CodeWriter + { + /// + /// Original method body information in Mono.Cecil format. + /// + private readonly MethodBody _body; + + /// + /// Binary writer for writing byte code in correct endianess. + /// + private readonly nanoBinaryWriter _writer; + + /// + /// String literals table (used for obtaining string literal ID). + /// + private readonly nanoStringTable _stringTable; + + /// + /// Assembly tables context - contains all tables used for building target assembly. + /// + private readonly nanoTablesContext _context; + + /// + /// Creates new instance of object. + /// + /// Original method body in Mono.Cecil format. + /// Binary writer for writing byte code in correct endianess. + /// String references table (for obtaining string ID). + /// + /// Assembly tables context - contains all tables used for building target assembly. + /// + public CodeWriter( + MethodDefinition method, + nanoBinaryWriter writer, + nanoStringTable stringTable, + nanoTablesContext context) + { + _stringTable = stringTable; + + _body = method.Body; + _context = context; + _writer = writer; + } + + /// + /// Writes method body into binary writer originally passed into constructor. + /// + public void WriteMethodBody() + { + foreach (var instruction in _body.Instructions) + { + WriteOpCode(instruction.OpCode); + WriteOperand(instruction); + } + + WriteExceptionsTable(); + } + + /// + /// Fixes instructions offsets according .NET nanoFramework operands sizes. + /// + /// Target method for fixing offsets + /// String table for populating strings from method. + public static IEnumerable> PreProcessMethod( + MethodDefinition methodDefinition, + nanoStringTable stringTable) + { + if (!methodDefinition.HasBody) + { + yield break; + } + + var offset = 0; + var offsetChanged = true; + foreach (var instruction in methodDefinition.Body.Instructions) + { + if (offset != 0) + { + if (offsetChanged) + { + yield return new Tuple( + (uint)instruction.Offset, (uint)(instruction.Offset + offset)); + offsetChanged = false; + } + instruction.Offset += offset; + } + + switch (instruction.OpCode.OperandType) + { + case OperandType.InlineSwitch: + var targets = (Instruction[]) instruction.Operand; + offset -= 3; // One bye used instead of Int32 + offset -= 2 * targets.Length; // each target use Int16 instead of Int32 + offsetChanged = true; + break; + case OperandType.InlineString: + stringTable.GetOrCreateStringId((string) instruction.Operand, false); + offset -= 2; + offsetChanged = true; + break; + case OperandType.InlineMethod: + case OperandType.InlineField: + case OperandType.InlineType: + case OperandType.InlineBrTarget: + // In full .NET these instructions followed by double word operand + // but in .NET nanoFramework these instruction's operand are word + offset -= 2; + offsetChanged = true; + break; + } + } + } + + /// + /// Calculates method stack size for passed method. + /// + /// Method body in Mono.Cecil format. + /// Maximal evaluated stack size for passed method body. + public static byte CalculateStackSize( + MethodBody methodBody) + { + if (methodBody == null) + { + return 0; + } + + IDictionary offsets = new Dictionary(); + + var size = 0; + var maxSize = 0; + foreach (var instruction in methodBody.Instructions) + { + int correctedStackSize; + if (offsets.TryGetValue(instruction.Offset, out correctedStackSize)) + { + size = correctedStackSize; + } + + switch (instruction.OpCode.Code) + { + case Code.Throw: + case Code.Endfinally: + case Code.Endfilter: + case Code.Leave_S: + case Code.Br_S: + case Code.Leave: + size = 0; + continue; + + case Code.Newobj: + { + var method = (MethodReference)instruction.Operand; + size -= method.Parameters.Count; + } + break; + + case Code.Callvirt: + case Code.Call: + { + var method = (MethodReference)instruction.Operand; + if (method.HasThis) + { + --size; + } + size -= method.Parameters.Count; + if (method.ReturnType.FullName != "System.Void") + { + ++size; + } + } + break; + } + + size = CorrectStackDepthByPushes(instruction, size); + size = CorrectStackDepthByPops(instruction, size); + + if (instruction.OpCode.OperandType == OperandType.ShortInlineBrTarget || + instruction.OpCode.OperandType == OperandType.InlineBrTarget) + { + int stackSize; + var target = (Instruction)instruction.Operand; + offsets.TryGetValue(target.Offset, out stackSize); + offsets[target.Offset] = Math.Max(stackSize, size); + } + + maxSize = Math.Max(maxSize, size); + } + + return (byte)maxSize; + } + + private static int CorrectStackDepthByPushes( + Instruction instruction, + int size) + { + switch (instruction.OpCode.StackBehaviourPush) + { + case StackBehaviour.Push1: + case StackBehaviour.Pushi: + case StackBehaviour.Pushi8: + case StackBehaviour.Pushr4: + case StackBehaviour.Pushr8: + case StackBehaviour.Pushref: + ++size; + break; + case StackBehaviour.Push1_push1: + size += 2; + break; + } + return size; + } + + private static int CorrectStackDepthByPops( + Instruction instruction, + int size) + { + switch (instruction.OpCode.StackBehaviourPop) + { + case StackBehaviour.Pop1: + case StackBehaviour.Popi: + case StackBehaviour.Popref: + --size; + break; + case StackBehaviour.Pop1_pop1: + case StackBehaviour.Popi_pop1: + case StackBehaviour.Popi_popi: + case StackBehaviour.Popi_popi8: + case StackBehaviour.Popi_popr4: + case StackBehaviour.Popi_popr8: + case StackBehaviour.Popref_pop1: + case StackBehaviour.Popref_popi: + size -= 2; + break; + case StackBehaviour.Popi_popi_popi: + case StackBehaviour.Popref_popi_popi: + case StackBehaviour.Popref_popi_popi8: + case StackBehaviour.Popref_popi_popr4: + case StackBehaviour.Popref_popi_popr8: + case StackBehaviour.Popref_popi_popref: + size -= 3; + break; + } + return size; + } + + private void WriteExceptionsTable() + { + if (!_body.HasExceptionHandlers) + { + return; + } + + foreach (var handler in _body.ExceptionHandlers + .OrderBy(item => item.HandlerStart.Offset)) + { + switch (handler.HandlerType) + { + case ExceptionHandlerType.Catch: + _writer.WriteUInt16(0x0000); + _writer.WriteUInt16(GetTypeReferenceId(handler.CatchType, 0x8000)); + break; + case ExceptionHandlerType.Fault: + _writer.WriteUInt16(0x0001); + _writer.WriteUInt16(0x0000); + break; + case ExceptionHandlerType.Finally: + _writer.WriteUInt16(0x0002); + _writer.WriteUInt16(0x0000); + break; + case ExceptionHandlerType.Filter: + _writer.WriteUInt16(0x0003); + _writer.WriteUInt16((ushort)handler.FilterStart.Offset); + break; + } + + _writer.WriteUInt16((ushort)handler.TryStart.Offset); + _writer.WriteUInt16((ushort)handler.TryEnd.Offset); + _writer.WriteUInt16((ushort)handler.HandlerStart.Offset); + if (handler.HandlerEnd == null) + { + _writer.WriteUInt16((ushort)_body.Instructions.Last().Offset); + } + else + { + _writer.WriteUInt16((ushort)handler.HandlerEnd.Offset); + } + } + + _writer.WriteByte((byte)_body.ExceptionHandlers.Count); + } + + private void WriteOpCode ( + OpCode opcode) + { + if (opcode.Size == 1) + { + _writer.WriteByte(opcode.Op2); + } + else + { + _writer.WriteByte(opcode.Op1); + _writer.WriteByte(opcode.Op2); + } + } + + private void WriteOperand ( + Instruction instruction) + { + var opcode = instruction.OpCode; + var operandType = opcode.OperandType; + + if (operandType == OperandType.InlineNone) + { + return; + } + + var operand = instruction.Operand; + if (operand == null) + { + throw new ArgumentException(); + } + + switch (operandType) + { + case OperandType.InlineSwitch: + { + var targets = (Instruction[]) operand; + _writer.WriteByte((byte)targets.Length); + var diff = instruction.Offset + opcode.Size + 2 * targets.Length + 1; + foreach (var item in targets) + { + _writer.WriteInt16((short)(GetTargetOffset(item) - diff)); + } + break; + } + case OperandType.ShortInlineBrTarget: + { + var target = (Instruction) operand; + _writer.WriteSByte((sbyte) + (GetTargetOffset(target) - (instruction.Offset + opcode.Size + 1))); + break; + } + case OperandType.InlineBrTarget: + { + var target = (Instruction) operand; + _writer.WriteInt16((short) + (GetTargetOffset(target) - (instruction.Offset + opcode.Size + 2))); + break; + } + case OperandType.ShortInlineVar: + _writer.WriteByte((byte)GetVariableIndex((VariableDefinition)operand)); + break; + case OperandType.ShortInlineArg: + _writer.WriteByte((byte)GetParameterIndex((ParameterDefinition)operand)); + break; + case OperandType.InlineVar: + _writer.WriteInt16((short)GetVariableIndex((VariableDefinition)operand)); + break; + case OperandType.InlineArg: + _writer.WriteInt16((short)GetParameterIndex((ParameterDefinition)operand)); + break; + case OperandType.InlineSig: + // TODO: implement this properly after finding when such code is generated + //WriteMetadataToken (GetStandAloneSignature ((CallSite) operand)); + break; + case OperandType.ShortInlineI: + if (opcode == OpCodes.Ldc_I4_S) + { + _writer.WriteSByte((sbyte)operand); + } + else + { + _writer.WriteByte((byte)operand); + } + break; + case OperandType.InlineI: + _writer.WriteInt32((int)operand); + break; + case OperandType.InlineI8: + _writer.WriteInt64((long)operand); + break; + case OperandType.ShortInlineR: + _writer.WriteSingle((float)operand); + break; + case OperandType.InlineR: + _writer.WriteDouble((double)operand); + break; + case OperandType.InlineString: + var stringReferenceId = _stringTable.GetOrCreateStringId((string) operand, false); + _writer.WriteUInt16(stringReferenceId); + break; + case OperandType.InlineMethod: + _writer.WriteUInt16(_context.GetMethodReferenceId((MethodReference)operand)); + break; + case OperandType.InlineType: + _writer.WriteUInt16(GetTypeReferenceId((TypeReference)operand)); + break; + case OperandType.InlineField: + _writer.WriteUInt16(GetFieldReferenceId((FieldReference)operand)); + break; + case OperandType.InlineTok: + _writer.WriteUInt32(GetMetadataToken((IMetadataTokenProvider)operand)); + break; + default: + throw new ArgumentException(); + } + } + + private uint GetMetadataToken( + IMetadataTokenProvider token) + { + ushort referenceId; + switch (token.MetadataToken.TokenType) + { + case TokenType.TypeRef: + _context.TypeReferencesTable.TryGetTypeReferenceId((TypeReference)token, out referenceId); + return (uint)0x01000000 | referenceId; + case TokenType.TypeDef: + _context.TypeDefinitionTable.TryGetTypeReferenceId((TypeDefinition)token, out referenceId); + return (uint)0x04000000 | referenceId; + case TokenType.TypeSpec: + _context.TypeSpecificationsTable.TryGetTypeReferenceId((TypeReference) token, out referenceId); + return (uint)0x08000000 | referenceId; + case TokenType.Field: + _context.FieldsTable.TryGetFieldReferenceId((FieldDefinition) token, false, out referenceId); + return (uint)0x05000000 | referenceId; + } + return 0U; + } + + private ushort GetFieldReferenceId( + FieldReference fieldReference) + { + ushort referenceId; + if (_context.FieldReferencesTable.TryGetFieldReferenceId(fieldReference, out referenceId)) + { + referenceId |= 0x8000; // External field reference + } + else + { + _context.FieldsTable.TryGetFieldReferenceId(fieldReference.Resolve(), false, out referenceId); + } + return referenceId; + } + + private ushort GetTypeReferenceId( + TypeReference typeReference, + ushort typeReferenceMask = 0x4000) + { + ushort referenceId; + if (_context.TypeReferencesTable.TryGetTypeReferenceId(typeReference, out referenceId)) + { + referenceId |= typeReferenceMask; // External type reference + } + else + { + if (!_context.TypeDefinitionTable.TryGetTypeReferenceId(typeReference.Resolve(), out referenceId)) + { + return 0x8000; + } + + } + return referenceId; + } + + private int GetTargetOffset ( + Instruction instruction) + { + if (instruction == null) + { + var last = _body.Instructions[_body.Instructions.Count - 1]; + return last.Offset + last.GetSize (); + } + + return instruction.Offset; + } + + private static int GetVariableIndex ( + VariableDefinition variable) + { + return variable.Index; + } + + private int GetParameterIndex ( + ParameterDefinition parameter) + { + if (_body.Method.HasThis) { + if (parameter == _body.ThisParameter) + return 0; + + return parameter.Index + 1; + } + + return parameter.Index; + } + } +} \ No newline at end of file diff --git a/source/MetadataProcessor.Core/Properties/AssemblyInfo.cs b/source/MetadataProcessor.Core/Properties/AssemblyInfo.cs new file mode 100644 index 00000000..63eaadf5 --- /dev/null +++ b/source/MetadataProcessor.Core/Properties/AssemblyInfo.cs @@ -0,0 +1,11 @@ +using System.Reflection; +using System.Runtime.CompilerServices; + +// Information about this assembly is defined by the following attributes. +// Change them to the values specific to your project. +[assembly: AssemblyTitle ("nanoFramework.MetadataProcessor.Core")] +[assembly: AssemblyDescription ("")] +[assembly: AssemblyConfiguration ("")] +[assembly: AssemblyCompany ("nanoFramework project contributors")] +[assembly: AssemblyProduct ("")] +[assembly: AssemblyCopyright ("Copyright (c) 2019 The nanoFramework project contributors")] diff --git a/source/MetadataProcessor.Core/Tables/ICustomStringSorter.cs b/source/MetadataProcessor.Core/Tables/ICustomStringSorter.cs new file mode 100644 index 00000000..d2da7c92 --- /dev/null +++ b/source/MetadataProcessor.Core/Tables/ICustomStringSorter.cs @@ -0,0 +1,24 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using System.Collections.Generic; + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Helper class for sorting string literals before merging (solve strings order problem). + /// + public interface ICustomStringSorter + { + /// + /// Sorts input sequence according needed logic. + /// + /// Existing string listerals list. + /// Original string listerals list sorted according test pattern. + IEnumerable Sort( + ICollection strings); + } +} \ No newline at end of file diff --git a/source/MetadataProcessor.Core/Tables/nanoAssemblyReferenceTable.cs b/source/MetadataProcessor.Core/Tables/nanoAssemblyReferenceTable.cs new file mode 100644 index 00000000..285231c4 --- /dev/null +++ b/source/MetadataProcessor.Core/Tables/nanoAssemblyReferenceTable.cs @@ -0,0 +1,84 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using Mono.Cecil; +using System; +using System.Collections.Generic; + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Encapsulates logic for storing external assembly references list and writing + /// this collected list into target assembly in .NET nanoFramework format. + /// + public sealed class nanoAssemblyReferenceTable : + nanoReferenceTableBase + { + /// + /// Helper class for comparing two instances of objects + /// using property as unique key for comparison. + /// + private sealed class AssemblyNameReferenceComparer : IEqualityComparer + { + /// + public bool Equals(AssemblyNameReference lhs, AssemblyNameReference rhs) + { + return string.Equals(lhs.FullName, rhs.FullName, StringComparison.Ordinal); + } + + /// + public int GetHashCode(AssemblyNameReference item) + { + return item.FullName.GetHashCode(); + } + } + + /// + /// Creates new instance of object. + /// + /// List of assembly references in Mono.Cecil format. + /// + /// Assembly tables context - contains all tables used for building target assembly. + /// + public nanoAssemblyReferenceTable( + IEnumerable items, + nanoTablesContext context) + : base(items, new AssemblyNameReferenceComparer(), context) + { + } + + /// + protected override void WriteSingleItem( + nanoBinaryWriter writer, + AssemblyNameReference item) + { + WriteStringReference(writer, item.Name); + writer.WriteUInt16(0); // padding + + writer.WriteVersion(item.Version); + } + + /// + protected override void AllocateSingleItemStrings( + AssemblyNameReference item) + { + GetOrCreateStringId(item.Name); + } + + /// + /// Gets assembly reference ID by assembly name reference in Mono.Cecil format. + /// + /// Assembly name reference in Mono.Cecil format. + /// Refernce ID for passed item. + public ushort GetReferenceId( + AssemblyNameReference assemblyNameReference) + { + ushort referenceId; + TryGetIdByValue(assemblyNameReference, out referenceId); + return referenceId; + } + } +} diff --git a/source/MetadataProcessor.Core/Tables/nanoAttributesTable.cs b/source/MetadataProcessor.Core/Tables/nanoAttributesTable.cs new file mode 100644 index 00000000..16353ee5 --- /dev/null +++ b/source/MetadataProcessor.Core/Tables/nanoAttributesTable.cs @@ -0,0 +1,96 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using Mono.Cecil; +using System; +using System.Collections.Generic; +using System.Linq; + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Encapsulates logic for storing attributes for types/methods/fields list and writing + /// this collected list into target assembly in .NET nanoFramework format. + /// + public sealed class nanoAttributesTable : InanoTable + { + /// + /// List of custom attributes in Mono.Cecil format for all internal types. + /// + private readonly IEnumerable> _typesAttributes; + + /// + /// List of custom attributes in Mono.Cecil format for all internal fields. + /// + /// + private readonly IEnumerable> _fieldsAttributes; + + /// + /// List of custom attributes in Mono.Cecil format for all internal methods. + /// + private readonly IEnumerable> _methodsAttributes; + + /// + /// Assembly tables context - contains all tables used for building target assembly. + /// + private readonly nanoTablesContext _context; + + /// + /// Creates new instance of object. + /// + /// + /// List of custom attributes in Mono.Cecil format for all internal types. + /// + /// + /// List of custom attributes in Mono.Cecil format for all internal fields. + /// + /// + /// List of custom attributes in Mono.Cecil format for all internal methods. + /// + /// + /// Assembly tables context - contains all tables used for building target assembly. + /// + public nanoAttributesTable( + IEnumerable> typesAttributes, + IEnumerable> fieldsAttributes, + IEnumerable> methodsAttributes, + nanoTablesContext context) + { + _typesAttributes = typesAttributes.ToList(); + _fieldsAttributes = fieldsAttributes.ToList(); + _methodsAttributes = methodsAttributes.ToList(); + + _context = context; + } + + /// + public void Write( + nanoBinaryWriter writer) + { + WriteAttributes(writer, 0x0004, _typesAttributes); + WriteAttributes(writer, 0x0005, _fieldsAttributes); + WriteAttributes(writer, 0x0006, _methodsAttributes); + } + + private void WriteAttributes( + nanoBinaryWriter writer, + ushort tableNumber, + IEnumerable> attributes) + { + foreach (var item in attributes) + { + var attribute = item.Item1; + var targetIdentifier = item.Item2; + + writer.WriteUInt16(tableNumber); + writer.WriteUInt16(targetIdentifier); + + writer.WriteUInt16(_context.GetMethodReferenceId(attribute.Constructor)); + writer.WriteUInt16(_context.SignaturesTable.GetOrCreateSignatureId(attribute)); + } + } + } +} \ No newline at end of file diff --git a/source/MetadataProcessor.Core/Tables/nanoByteCodeTable.cs b/source/MetadataProcessor.Core/Tables/nanoByteCodeTable.cs new file mode 100644 index 00000000..b659ff59 --- /dev/null +++ b/source/MetadataProcessor.Core/Tables/nanoByteCodeTable.cs @@ -0,0 +1,161 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using Mono.Cecil; +using System; +using System.Collections.Generic; +using System.IO; + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Encapsulates logic for storing method bodies (byte code) list and writing + /// this collected list into target assembly in .NET nanoFramework format. + /// + public sealed class nanoByteCodeTable : InanoTable + { + /// + /// Maps method bodies (in form of byte array) to method identifiers. + /// + private readonly IList _methods = new List(); + + /// + /// Maps method full names to method RVAs (offsets in resutling table). + /// + private readonly IDictionary _rvasByMethodNames = + new Dictionary(StringComparer.Ordinal); + + /// + /// Temprorary string table for code generators used duing initial load. + /// + private readonly nanoStringTable _fakeStringTable = new nanoStringTable(); + + /// + /// Assembly tables context - contains all tables used for building target assembly. + /// + private readonly nanoTablesContext _context; + + /// + /// Last available method RVA. + /// + private ushort _lastAvailableRva; + + /// + /// Creates new instance of object. + /// + /// + /// Assembly tables context - contains all tables used for building target assembly. + /// + public nanoByteCodeTable( + nanoTablesContext context) + { + _context = context; + } + + /// + /// Next method identifier. Used for reproducing strange original MetadataProcessor behavior. + /// + public ushort NextMethodId { get { return (ushort)_methods.Count; } } + + /// + /// Temprorary string table for code generators used duing initial load. + /// + public nanoStringTable FakeStringTable { get { return _fakeStringTable; } } + + /// + /// Returns method reference ID (index in methods definitions table) for passed method definition. + /// + /// Method definition in Mono.Cecil format. + /// + /// New method reference ID (byte code also prepared for writing as part of process). + /// + public ushort GetMethodId( + MethodDefinition method) + { + var rva = method.HasBody ? _lastAvailableRva : (ushort)0xFFFF; + var id = (ushort)_methods.Count; + + _context.NativeMethodsCrc.UpdateCrc(method); + var byteCode = CreateByteCode(method); + + _methods.Add(method); + _lastAvailableRva += (ushort)byteCode.Length; + + _rvasByMethodNames.Add(method.FullName, rva); + return id; + } + + /// + /// Returns method RVA (offset in byte code table) for passed method reference. + /// + /// Method reference in Mono.Cecil format. + /// + /// Method RVA (method should be generated using before this call. + /// + public ushort GetMethodRva( + MethodReference method) + { + ushort rva; + return (_rvasByMethodNames.TryGetValue(method.FullName, out rva) ? rva : (ushort)0xFFFF); + } + + /// + public void Write( + nanoBinaryWriter writer) + { + foreach (var method in _methods) + { + writer.WriteBytes(CreateByteCode(method, writer)); + } + } + + /// + /// Updates main string table with strings stored in temp string table before code generation. + /// + internal void UpdateStringTable() + { + _context.StringTable.MergeValues(_fakeStringTable); + } + + private byte[] CreateByteCode( + MethodDefinition method) + { + if (!method.HasBody) + { + return new byte[0]; + } + + using (var stream = new MemoryStream()) + using (var writer = new BinaryWriter(stream)) + { + var codeWriter = new CodeWriter( + method, nanoBinaryWriter.CreateBigEndianBinaryWriter(writer), + _fakeStringTable, _context); + codeWriter.WriteMethodBody(); + return stream.ToArray(); + } + } + + private byte[] CreateByteCode( + MethodDefinition method, + nanoBinaryWriter writer) + { + if (!method.HasBody) + { + return new byte[0]; + } + + using(var stream = new MemoryStream()) + { + var codeWriter = new CodeWriter( + method, writer.GetMemoryBasedClone(stream), + _context.StringTable, _context); + codeWriter.WriteMethodBody(); + return stream.ToArray(); + } + } + } +} diff --git a/source/MetadataProcessor.Core/Tables/nanoEmptyTable.cs b/source/MetadataProcessor.Core/Tables/nanoEmptyTable.cs new file mode 100644 index 00000000..fb441522 --- /dev/null +++ b/source/MetadataProcessor.Core/Tables/nanoEmptyTable.cs @@ -0,0 +1,36 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Default implementation of interface. Do nothing and + /// used for emulating temporary not supported metadata tables and for last fake table. + /// + public sealed class nanoEmptyTable : InanoTable + { + /// + /// Singleton pattern - single unique instance of object. + /// + private static readonly InanoTable _instance = new nanoEmptyTable(); + + /// + /// Singleton pattern - private constructor prevents direct instantiation. + /// + private nanoEmptyTable() { } + + /// + public void Write( + nanoBinaryWriter writer) + { + } + + /// + /// Singleton pattern - gets single unique instance of object. + /// + public static InanoTable Instance { get { return _instance; } } + } +} diff --git a/source/MetadataProcessor.Core/Tables/nanoFieldDefinitionTable.cs b/source/MetadataProcessor.Core/Tables/nanoFieldDefinitionTable.cs new file mode 100644 index 00000000..3d6baea0 --- /dev/null +++ b/source/MetadataProcessor.Core/Tables/nanoFieldDefinitionTable.cs @@ -0,0 +1,189 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using Mono.Cecil; +using System; +using System.Collections.Generic; + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Encapsulates logic for storing fields definitions list and writing + /// this collected list into target assembly in .NET nanoFramework format. + /// + public sealed class nanoFieldDefinitionTable : + nanoReferenceTableBase + { + /// + /// Helper class for comparing two instances of objects + /// using property as unique key for comparison. + /// + private sealed class FieldDefinitionComparer : IEqualityComparer + { + /// + public bool Equals(FieldDefinition lhs, FieldDefinition rhs) + { + return string.Equals(lhs.FullName, rhs.FullName, StringComparison.Ordinal); + } + + /// + public int GetHashCode(FieldDefinition that) + { + return that.FullName.GetHashCode(); + } + } + + /// + /// Maximal returned field reference id - used for emulating old MetadataProcessor behavior. + /// + private int _maxReferenceId; + + /// + /// Creates new instance of object. + /// + /// List of field definitions in Mono.Cecil format. + /// + /// Assembly tables context - contains all tables used for building target assembly. + /// + public nanoFieldDefinitionTable( + IEnumerable items, + nanoTablesContext context) + : base(items, new FieldDefinitionComparer(), context) + { + } + + /// + /// Gets maximal returned field reference id - used for emulating old MetadataProcessor behavior. + /// + public ushort MaxFieldId { get { return (ushort)_maxReferenceId; } } + + /// + protected override void WriteSingleItem( + nanoBinaryWriter writer, + FieldDefinition item) + { + WriteStringReference(writer, item.Name); + writer.WriteUInt16(_context.SignaturesTable.GetOrCreateSignatureId(item)); + + writer.WriteUInt16(_context.SignaturesTable.GetOrCreateSignatureId(item.InitialValue)); + writer.WriteUInt16(GetFlags(item)); + } + + /// + /// Gets field reference identifier (if field is defined inside target assembly). + /// + /// Field definition in Mono.Cecil format. + /// If set to true we should track max ID value. + /// Field reference identifier for filling. + /// Returns true if item found, otherwise returns false. + public bool TryGetFieldReferenceId( + FieldDefinition field, + bool trackMaxReferenceId, + out ushort referenceId) + { + var found = TryGetIdByValue(field, out referenceId); + if (trackMaxReferenceId && found) + { + _maxReferenceId = Math.Max(_maxReferenceId, referenceId + 1); + } + return found; + } + + private ushort GetFlags( + FieldDefinition field) + { + const ushort FD_Scope_Private = 0x0001; // Accessible only by the parent type. + const ushort FD_Scope_FamANDAssem = 0x0002; // Accessible by sub-types only in this Assembly. + const ushort FD_Scope_Assembly = 0x0003; // Accessibly by anyone in the Assembly. + const ushort FD_Scope_Family = 0x0004; // Accessible only by type and sub-types. + const ushort FD_Scope_FamORAssem = 0x0005; // Accessibly by sub-types anywhere, plus anyone in assembly. + const ushort FD_Scope_Public = 0x0006; // Accessibly by anyone who has visibility to this scope. + + const ushort FD_NotSerialized = 0x0008; // Field does not have to be serialized when type is remoted. + + const ushort FD_Static = 0x0010; // Defined on type, else per instance. + const ushort FD_InitOnly = 0x0020; // Field may only be initialized, not written to after init. + const ushort FD_Literal = 0x0040; // Value is compile time constant. + + const ushort FD_SpecialName = 0x0100; // field is special. Name describes how. + const ushort FD_HasDefault = 0x0200; // Field has default. + const ushort FD_HasFieldRVA = 0x0400; // Field has RVA. + + const ushort FD_NoReflection = 0x0800; // field does not allow reflection + + const ushort FD_HasAttributes = 0x8000; + + ushort flag = 0; + + if (field.IsPrivate) + { + flag = FD_Scope_Private; + } + else if (field.IsFamilyAndAssembly) + { + flag = FD_Scope_FamANDAssem; + } + else if (field.IsFamilyOrAssembly) + { + flag = FD_Scope_FamORAssem; + } + else if (field.IsAssembly) + { + flag = FD_Scope_Assembly; + } + else if (field.IsFamily) + { + flag = FD_Scope_Family; + } + else if (field.IsPublic) + { + flag = FD_Scope_Public; + } + + if (field.IsNotSerialized) + { + flag |= FD_NotSerialized; + } + + if (field.IsStatic) + { + flag |= FD_Static; + } + + if (field.IsInitOnly) + { + flag |= FD_InitOnly; + } + + if (field.IsLiteral) + { + flag |= FD_Literal; + } + + if (field.IsSpecialName) + { + flag |= FD_SpecialName; + } + + if (field.HasDefault) + { + flag |= FD_HasDefault; + } + + if (field.HasCustomAttributes) + { + flag |= FD_HasAttributes; + } + + if (field.RVA != 0) + { + flag |= FD_HasFieldRVA; + } + + return flag; + } + } +} diff --git a/source/MetadataProcessor.Core/Tables/nanoFieldReferenceTable.cs b/source/MetadataProcessor.Core/Tables/nanoFieldReferenceTable.cs new file mode 100644 index 00000000..3be40f05 --- /dev/null +++ b/source/MetadataProcessor.Core/Tables/nanoFieldReferenceTable.cs @@ -0,0 +1,81 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using Mono.Cecil; +using System; +using System.Collections.Generic; + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Encapsulates logic for storing member (methods or fields) references list and writing + /// this collected list into target assembly in .NET nanoFramework format. + /// + public sealed class nanoFieldReferenceTable : + nanoReferenceTableBase + { + /// + /// Helper class for comparing two instances of objects + /// using property as unique key for comparison. + /// + private sealed class MemberReferenceComparer : IEqualityComparer + { + /// + public bool Equals(FieldReference lhs, FieldReference rhs) + { + return string.Equals(lhs.FullName, rhs.FullName, StringComparison.Ordinal); + } + + /// + public int GetHashCode(FieldReference that) + { + return that.FullName.GetHashCode(); + } + } + + /// + /// Creates new instance of object. + /// + /// List of member references in Mono.Cecil format. + /// + /// Assembly tables context - contains all tables used for building target assembly. + /// + public nanoFieldReferenceTable( + IEnumerable items, + nanoTablesContext context) + : base(items, new MemberReferenceComparer(), context) + { + } + + /// + /// Gets field reference ID if possible (if field is external and stored in this table). + /// + /// Field reference metadata in Mono.Cecil format. + /// Field reference ID in .NET nanoFramework format. + /// Returns true if reference found, otherwise returns false. + public bool TryGetFieldReferenceId( + FieldReference fieldReference, + out ushort referenceId) + { + return TryGetIdByValue(fieldReference, out referenceId); + } + + /// + protected override void WriteSingleItem( + nanoBinaryWriter writer, + FieldReference item) + { + ushort referenceId; + _context.TypeReferencesTable.TryGetTypeReferenceId(item.DeclaringType, out referenceId); + + WriteStringReference(writer, item.Name); + writer.WriteUInt16(referenceId); + + writer.WriteUInt16(_context.SignaturesTable.GetOrCreateSignatureId(item)); + writer.WriteUInt16(0); // padding + } + } +} diff --git a/source/MetadataProcessor.Core/Tables/nanoMethodDefinitionTable.cs b/source/MetadataProcessor.Core/Tables/nanoMethodDefinitionTable.cs new file mode 100644 index 00000000..0d4d1267 --- /dev/null +++ b/source/MetadataProcessor.Core/Tables/nanoMethodDefinitionTable.cs @@ -0,0 +1,244 @@ +using System; +using System.Collections.Generic; +using Mono.Cecil; + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Encapsulates logic for storing methods definitions list and writing + /// this collected list into target assembly in .NET nanoFramework format. + /// + public sealed class nanoMethodDefinitionTable : + nanoReferenceTableBase + { + /// + /// Helper class for comparing two instances of objects + /// using property as unique key for comparison. + /// + private sealed class MethodDefinitionComparer : IEqualityComparer + { + /// + public bool Equals(MethodDefinition lhs, MethodDefinition rhs) + { + return string.Equals(lhs.FullName, rhs.FullName, StringComparison.Ordinal); + } + + /// + public int GetHashCode(MethodDefinition that) + { + return that.FullName.GetHashCode(); + } + } + + /// + /// Creates new instance of object. + /// + /// List of methods definitions in Mono.Cecil format. + /// + /// Assembly tables context - contains all tables used for building target assembly. + /// + public nanoMethodDefinitionTable( + IEnumerable items, + nanoTablesContext context) + :base(items, new MethodDefinitionComparer(), context) + { + } + + /// + /// Gets method reference identifier (if method is defined inside target assembly). + /// + /// Method definition in Mono.Cecil format. + /// Method definition reference identifier for filling. + /// Returns true if item found, otherwise returns false. + public bool TryGetMethodReferenceId( + MethodDefinition methodDefinition, + out ushort referenceId) + { + return TryGetIdByValue(methodDefinition, out referenceId); + } + + /// + protected override void WriteSingleItem( + nanoBinaryWriter writer, + MethodDefinition item) + { + WriteStringReference(writer, item.Name); + writer.WriteUInt16(_context.ByteCodeTable.GetMethodRva(item)); + + writer.WriteUInt32(GetFlags(item)); + + var parametersCount = (byte)item.Parameters.Count; + if (!item.IsStatic) + { + ++parametersCount; // add implicit 'this' pointer into non-static methods + } + + _context.SignaturesTable.WriteDataType(item.ReturnType, writer, false, false); + if (item.ReturnType is TypeSpecification) + { + _context.TypeSpecificationsTable + .GetOrCreateTypeSpecificationId(item.ReturnType); + } + + writer.WriteByte(parametersCount); + writer.WriteByte((byte)(item.HasBody ? item.Body.Variables.Count : 0)); + writer.WriteByte(CodeWriter.CalculateStackSize(item.Body)); + + var methodSignature = _context.SignaturesTable.GetOrCreateSignatureId(item); + writer.WriteUInt16(item.HasBody ? + _context.SignaturesTable.GetOrCreateSignatureId(item.Body.Variables) : + (item.IsAbstract || item.IsRuntime ? (ushort)0x0000 : (ushort)0xFFFF)); + writer.WriteUInt16(methodSignature); + } + + private uint GetFlags( + MethodDefinition method) + { + const uint MD_Scope_Private = 0x00000001; // Accessible only by the parent type. + const uint MD_Scope_FamANDAssem = 0x00000002; // Accessible by sub-types only in this Assembly. + const uint MD_Scope_Assem = 0x00000003; // Accessibly by anyone in the Assembly. + const uint MD_Scope_Family = 0x00000004; // Accessible only by type and sub-types. + const uint MD_Scope_FamORAssem = 0x00000005; // Accessibly by sub-types anywhere, plus anyone in assembly. + const uint MD_Scope_Public = 0x00000006; // Accessibly by anyone who has visibility to this scope. + + const uint MD_Static = 0x00000010; // Defined on type, else per instance. + const uint MD_Final = 0x00000020; // Method may not be overridden. + const uint MD_Virtual = 0x00000040; // Method virtual. + const uint MD_HideBySig = 0x00000080; // Method hides by name+sig, else just by name. + + const uint MD_ReuseSlot = 0x00000000; // The default. + const uint MD_NewSlot = 0x00000100; // Method always gets a new slot in the vtable. + const uint MD_Abstract = 0x00000200; // Method does not provide an implementation. + const uint MD_SpecialName = 0x00000400; // Method is special. Name describes how. + const uint MD_NativeProfiled = 0x00000800; + + const uint MD_Constructor = 0x00001000; + const uint MD_StaticConstructor = 0x00002000; + const uint MD_Finalizer = 0x00004000; + + const uint MD_DelegateConstructor = 0x00010000; + const uint MD_DelegateInvoke = 0x00020000; + const uint MD_DelegateBeginInvoke = 0x00040000; + const uint MD_DelegateEndInvoke = 0x00080000; + + const uint MD_Synchronized = 0x01000000; + const uint MD_GloballySynchronized = 0x02000000; + const uint MD_Patched = 0x04000000; + const uint MD_EntryPoint = 0x08000000; + const uint MD_RequireSecObject = 0x10000000; // Method calls another method containing security code. + const uint MD_HasSecurity = 0x20000000; // Method has security associate with it. + const uint MD_HasExceptionHandlers = 0x40000000; + const uint MD_HasAttributes = 0x80000000; + + uint flag = 0; + if (method.IsPrivate) + { + flag = MD_Scope_Private; + } + else if (method.IsFamilyAndAssembly) + { + flag = MD_Scope_FamANDAssem; + } + else if (method.IsFamilyOrAssembly) + { + flag = MD_Scope_FamORAssem; + } + else if (method.IsAssembly) + { + flag = MD_Scope_Assem; + } + else if (method.IsFamily) + { + flag = MD_Scope_Family; + } + else if (method.IsPublic) + { + flag = MD_Scope_Public; + } + + if (method.IsStatic) + { + flag |= MD_Static; + } + if (method.IsFinal) + { + flag |= MD_Final; + } + if (method.IsVirtual) + { + flag |= MD_Virtual; + } + if (method.IsHideBySig) + { + flag |= MD_HideBySig; + } + + if (method.IsReuseSlot) + { + flag |= MD_ReuseSlot; + } + if (method.IsNewSlot) + { + flag |= MD_NewSlot; + } + if (method.IsAbstract) + { + flag |= MD_Abstract; + } + if (method.IsSpecialName) + { + flag |= MD_SpecialName; + } + if (method.IsNative) + { + flag |= MD_NativeProfiled; // ??? + } + + if (method.IsConstructor) + { + flag |= (method.IsStatic ? MD_StaticConstructor : MD_Constructor); + } + + if (method.IsSynchronized) + { + flag |= MD_Synchronized; + } + if (method.HasCustomAttributes) + { + flag |= MD_HasAttributes; // ??? + } + + if (method == method.Module.EntryPoint) + { + flag |= MD_EntryPoint; + } + + if (method.HasBody && method.Body.HasExceptionHandlers) + { + flag |= MD_HasExceptionHandlers; + } + + var baseType = method.DeclaringType.BaseType; + if (baseType != null && baseType.FullName == "System.MulticastDelegate") + { + if (method.IsConstructor) + { + flag |= MD_DelegateConstructor; + } + else if (method.Name == "Invoke") + { + flag |= MD_DelegateInvoke; + } + else if (method.Name == "BeginInvoke") + { + flag |= MD_DelegateBeginInvoke; + } + else if (method.Name == "EndInvoke") + { + flag |= MD_DelegateEndInvoke; + } + } + return flag; + } + } +} diff --git a/source/MetadataProcessor.Core/Tables/nanoMethodReferenceTable.cs b/source/MetadataProcessor.Core/Tables/nanoMethodReferenceTable.cs new file mode 100644 index 00000000..324bdabe --- /dev/null +++ b/source/MetadataProcessor.Core/Tables/nanoMethodReferenceTable.cs @@ -0,0 +1,81 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using Mono.Cecil; +using System; +using System.Collections.Generic; + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Encapsulates logic for storing methods references list and writing + /// this collected list into target assembly in .NET nanoFramework format. + /// + public sealed class nanoMethodReferenceTable : + nanoReferenceTableBase + { + /// + /// Helper class for comparing two instances of objects + /// using property as unique key for comparison. + /// + private sealed class MemberReferenceComparer : IEqualityComparer + { + /// + public bool Equals(MethodReference lhs, MethodReference rhs) + { + return string.Equals(lhs.FullName, rhs.FullName, StringComparison.Ordinal); + } + + /// + public int GetHashCode(MethodReference that) + { + return that.FullName.GetHashCode(); + } + } + + /// + /// Creates new instance of object. + /// + /// List of member references in Mono.Cecil format. + /// + /// Assembly tables context - contains all tables used for building target assembly. + /// + public nanoMethodReferenceTable( + IEnumerable items, + nanoTablesContext context) + : base(items, new MemberReferenceComparer(), context) + { + } + + /// + /// Gets method reference ID if possible (if method is external and stored in this table). + /// + /// Method reference metadata in Mono.Cecil format. + /// Method reference ID in .NET nanoFramework format. + /// Returns true if reference found, otherwise returns false. + public bool TryGetMethodReferenceId( + MethodReference methodReference, + out ushort referenceId) + { + return TryGetIdByValue(methodReference, out referenceId); + } + + /// + protected override void WriteSingleItem( + nanoBinaryWriter writer, + MethodReference item) + { + ushort referenceId; + _context.TypeReferencesTable.TryGetTypeReferenceId(item.DeclaringType, out referenceId); + + WriteStringReference(writer, item.Name); + writer.WriteUInt16(referenceId); + + writer.WriteUInt16(_context.SignaturesTable.GetOrCreateSignatureId(item)); + writer.WriteUInt16(0); // padding + } + } +} diff --git a/source/MetadataProcessor.Core/Tables/nanoReferenceTableBase.cs b/source/MetadataProcessor.Core/Tables/nanoReferenceTableBase.cs new file mode 100644 index 00000000..b61de963 --- /dev/null +++ b/source/MetadataProcessor.Core/Tables/nanoReferenceTableBase.cs @@ -0,0 +1,139 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using System; +using System.Collections.Generic; +using System.Linq; + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Base class for all metadata tables with lookup functionality. Stores items in Mono.Cecil + /// format in dictionary and allows to get item ID by item value (using custom comparer). + /// + /// Type of stored metadata item (in Mono.Cecil format). + public abstract class nanoReferenceTableBase : InanoTable + { + /// + /// Lookup table for finding item ID by item value. + /// + private readonly Dictionary _idsByItemsDictionary; + + /// + /// Assembly tables context - contains all tables used for building target assembly. + /// + protected readonly nanoTablesContext _context; + + /// + /// Creates new instance of object. + /// + /// List of items for initial loading. + /// Custom comparer for items (type-specific). + /// + /// Assembly tables context - contains all tables used for building target assembly. + /// + protected nanoReferenceTableBase( + IEnumerable tinyTableItems, + IEqualityComparer comparer, + nanoTablesContext context) + { + _idsByItemsDictionary = tinyTableItems + .Select((reference, index) => new { reference, index }) + .ToDictionary(item => item.reference, item => (ushort)item.index, + comparer); + + _context = context; + } + + /// + public void Write( + nanoBinaryWriter writer) + { + foreach (var item in _idsByItemsDictionary + .OrderBy(item => item.Value) + .Select(item => item.Key)) + { + WriteSingleItem(writer, item); + } + } + + public void ForEachItems(Action action) + { + foreach (var item in _idsByItemsDictionary + .OrderBy(item => item.Value)) + { + action(item.Value, item.Key); + } + } + + /// + /// Helper method for allocating strings from table before table will be written. + /// + public void AllocateStrings() + { + foreach (var item in _idsByItemsDictionary + .OrderBy(item => item.Value) + .Select(item => item.Key)) + { + AllocateSingleItemStrings(item); + } + } + + /// + /// Writes string reference ID related to passed string value into output stream. + /// + /// Target binary writer for writing reference ID. + /// String value for obtaining reference and writing. + protected void WriteStringReference( + nanoBinaryWriter writer, + string value) + { + writer.WriteUInt16(GetOrCreateStringId(value)); + } + + /// + /// Gets existing or creates new string reference ID for provided string value. + /// + /// String value for lookup in string literals table. + /// String reference ID which can be used for filling metadata and byte code. + protected ushort GetOrCreateStringId( + string value) + { + return _context.StringTable.GetOrCreateStringId(value); + } + + /// + /// Helper method for lookup in internal dictionary. Wraps + /// method. + /// + /// Key value for lookup. + /// Item reference identifier. + /// Returns true if item found, otherwise returns false. + protected bool TryGetIdByValue( + T key, + out ushort id) + { + return _idsByItemsDictionary.TryGetValue(key, out id); + } + + /// + /// Provides concrete implementation for string allocation method in this table. + /// + /// Table item for allocating strings. + protected virtual void AllocateSingleItemStrings(T item) + { + } + + /// + /// Inherited class should provides concrete implementation for writing single table item here. + /// + /// Target binary writer for writing item data. + /// Single table item for writing into ouptut stream. + protected abstract void WriteSingleItem( + nanoBinaryWriter writer, + T item); + } +} diff --git a/source/MetadataProcessor.Core/Tables/nanoResourceDataTable.cs b/source/MetadataProcessor.Core/Tables/nanoResourceDataTable.cs new file mode 100644 index 00000000..fa131284 --- /dev/null +++ b/source/MetadataProcessor.Core/Tables/nanoResourceDataTable.cs @@ -0,0 +1,62 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using System.Collections.Generic; + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Encapsulates logic for storing concrete resource data items list and writing + /// this collected list into target assembly in .NET nanoFramework format. + /// + public sealed class nanoResourceDataTable : InanoTable + { + /// + /// List of registered resouce data for writing into output stream "as is". + /// + private readonly IList _dataByteArrays = new List(); + + /// + /// Gets current offset in resrouces data table (total size of all data blocks). + /// + public int CurrentOffset { get; private set; } + + /// + /// Adds new chunk of binary data for resouces into list of resources. + /// + /// Resouce data in binary format. + public void AddResourceData( + byte[] resourceData) + { + _dataByteArrays.Add(resourceData); + CurrentOffset += resourceData.Length; + } + + /// + public void Write( + nanoBinaryWriter writer) + { + foreach (var item in _dataByteArrays) + { + writer.WriteBytes(item); + } + } + + /// + /// Aligns current data in table by word boundary and return size of alignment. + /// + /// Number of bytes added into bytes block for proper data alignment. + public int AlignToWord() + { + var padding = (4 - (CurrentOffset % 4)) % 4; + if (padding != 0) + { + AddResourceData(new byte[padding]); + } + return padding; + } + } +} diff --git a/source/MetadataProcessor.Core/Tables/nanoResourceFileTable.cs b/source/MetadataProcessor.Core/Tables/nanoResourceFileTable.cs new file mode 100644 index 00000000..01f77ab9 --- /dev/null +++ b/source/MetadataProcessor.Core/Tables/nanoResourceFileTable.cs @@ -0,0 +1,79 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using Mono.Cecil; +using System; +using System.Collections.Generic; +using System.IO; + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Encapsulates logic for storing resource files definitions list and writing + /// this collected list into target assembly in .NET nanoFramework format. + /// + public sealed class nanoResourceFileTable : InanoTable + { + /// + /// Assembly tables context - contains all tables used for building target assembly. + /// + private readonly nanoTablesContext _context; + + /// + /// List of resource fiels data for producing correct output records. + /// + private readonly IList> _resouces = new List>(); + + /// + /// Creates new instance of object. + /// + /// + /// Assembly tables context - contains all tables used for building target assembly. + /// + public nanoResourceFileTable( + nanoTablesContext context) + { + _context = context; + } + + /// + /// Adds infromation about embedded resource file in Mono.Cecil format into list. + /// + /// Embedded resouce file information in Mono.Cecil format. + /// Number of recource items in this resouce file. + public void AddResourceFile( + EmbeddedResource item, + uint count) + { + var correctFileName = Path.ChangeExtension(item.Name, ".tinyresources"); + var nameStringId = _context.StringTable.GetOrCreateStringId(correctFileName); + + _resouces.Add(new Tuple(nameStringId, count)); + } + + /// + public void Write( + nanoBinaryWriter writer) + { + var offset = 0U; + foreach (var item in _resouces) + { + writer.WriteUInt32(0x02); // Version + writer.WriteUInt32(0x04); // Size of header + writer.WriteUInt32(0x08); // Size of resouce header + + writer.WriteUInt32(item.Item2); + + writer.WriteUInt16(item.Item1); + writer.WriteUInt16(0x0); // paddding + + writer.WriteUInt32(offset); + offset += 8; // Size of resource table record + } + + } + } +} \ No newline at end of file diff --git a/source/MetadataProcessor.Core/Tables/nanoResourcesTable.cs b/source/MetadataProcessor.Core/Tables/nanoResourcesTable.cs new file mode 100644 index 00000000..8b69e16f --- /dev/null +++ b/source/MetadataProcessor.Core/Tables/nanoResourcesTable.cs @@ -0,0 +1,208 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using Mono.Cecil; +using System; +using System.Collections; +using System.Collections.Generic; +using System.Drawing; +using System.IO; +using System.Linq; +using System.Resources; + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Encapsulates logic for storing embedded resources list and writing + /// this collected list into target assembly in .NET nanoFramework format. + /// + public sealed class nanoResourcesTable : InanoTable + { + private enum ResourceKind : byte + { + None = 0x00, + Bitmap = 0x01, + Font = 0x02, + String = 0x03, + Binary = 0x04 + } + + private const uint FONT_HEADER_MAGIC = 0xf995b0a8; + + /// + /// Original list of resouces in Mono.Cecil format. + /// + private readonly IEnumerable _resources; + + /// + /// Assembly tables context - contains all tables used for building target assembly. + /// + private readonly nanoTablesContext _context; + + /// + /// Creates new instance of object. + /// + /// Original list of resouces in Mono.Cecil format. + /// + /// Assembly tables context - contains all tables used for building target assembly. + /// + public nanoResourcesTable( + IEnumerable resources, + nanoTablesContext context) + { + _resources = resources.ToList(); + _context = context; + } + + /// + public void Write( + nanoBinaryWriter writer) + { + var orderedResources = new SortedDictionary>(); + foreach (var item in _resources.OfType()) + { + var count = 0U; + using (var reader = new ResourceReader(item.GetResourceStream())) + { + foreach (DictionaryEntry resource in reader) + { + string resourceType; + byte[] resourceData; + var resourceName = resource.Key.ToString(); + + reader.GetResourceData(resourceName, out resourceType, out resourceData); + + var kind = GetResourceKind(resourceType, resourceData); + + if (kind == ResourceKind.Bitmap) + { + using (var stream = new MemoryStream(resourceData.Length)) + { + var bitmapProcessor = new nanoBitmapProcessor((Bitmap)resource.Value); + bitmapProcessor.Process(writer.GetMemoryBasedClone(stream)); + resourceData = stream.ToArray(); + } + } + + orderedResources.Add(GenerateIdFromResourceName(resourceName), + new Tuple(kind, resourceData)); + + ++count; + } + } + + _context.ResourceFileTable.AddResourceFile(item, count); + } + + foreach (var item in orderedResources) + { + var kind = item.Value.Item1; + var bytes = item.Value.Item2; + + var padding = 0; + switch (kind) + { + case ResourceKind.String: + var stringLength = (int)bytes[0]; + if (stringLength < 0x7F) + { + bytes = bytes.Skip(1).Concat(Enumerable.Repeat((byte)0, 1)).ToArray(); + } + else + { + bytes = bytes.Skip(2).Concat(Enumerable.Repeat((byte)0, 1)).ToArray(); + } + break; + case ResourceKind.Bitmap: + padding = _context.ResourceDataTable.AlignToWord(); + break; + case ResourceKind.Binary: + bytes = bytes.Skip(4).ToArray(); + break; + case ResourceKind.Font: + padding = _context.ResourceDataTable.AlignToWord(); + bytes = bytes.Skip(32).ToArray(); // File size + resource header size + break; + } + + // Pre-process font data (swap endiannes if needed). + if (kind == ResourceKind.Font) + { + using (var stream = new MemoryStream(bytes.Length)) + { + var fontProcessor = new nanoFontProcessor(bytes); + fontProcessor.Process(writer.GetMemoryBasedClone(stream)); + bytes = stream.ToArray(); + } + } + + writer.WriteInt16(item.Key); + writer.WriteByte((byte)kind); + writer.WriteByte((byte)padding); + writer.WriteInt32(_context.ResourceDataTable.CurrentOffset); + + _context.ResourceDataTable.AddResourceData(bytes); + } + + if (orderedResources.Count != 0) + { + writer.WriteInt16(0x7FFF); + writer.WriteByte((byte)ResourceKind.None); + writer.WriteByte(0x00); + writer.WriteInt32(_context.ResourceDataTable.CurrentOffset); + } + } + + private static ResourceKind GetResourceKind( + string resourceType, + byte[] resourceData) + { + if (resourceType.EndsWith(".String")) + { + return ResourceKind.String; + } + + if (resourceType.StartsWith("System.Drawing.Bitmap")) + { + return ResourceKind.Bitmap; + } + + using(var stream = new MemoryStream(resourceData)) + using (var reader = new BinaryReader(stream)) + { + var size = reader.ReadUInt32(); + return (size > 4 && reader.ReadUInt32() == FONT_HEADER_MAGIC + ? ResourceKind.Font + : ResourceKind.Binary); + } + } + + private static short GenerateIdFromResourceName( + string value) + { + var hash1 = (5381 << 16) + 5381; + var hash2 = hash1; + + for (var i = 0; i < value.Length; ++i) + { + var c = value[i]; + if (i % 2 == 0) + { + hash1 = ((hash1 << 5) + hash1) ^ c; + } + else + { + hash2 = ((hash2 << 5) + hash2) ^ c; + } + } + + var hash = hash1 + (hash2 * 1566083941); + + return (short)((short)(hash >> 16) ^ (short)hash); + } + + } +} diff --git a/source/MetadataProcessor.Core/Tables/nanoSignaturesTable.cs b/source/MetadataProcessor.Core/Tables/nanoSignaturesTable.cs new file mode 100644 index 00000000..eced3911 --- /dev/null +++ b/source/MetadataProcessor.Core/Tables/nanoSignaturesTable.cs @@ -0,0 +1,591 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using Mono.Cecil; +using Mono.Cecil.Cil; +using Mono.Collections.Generic; +using System; +using System.Collections.Generic; +using System.Diagnostics; +using System.IO; +using System.Linq; + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Encapsulates logic for storing member (methods or fields) signatures list and writing + /// this collected list into target assembly in .NET nanoFramework format. + /// + public sealed class nanoSignaturesTable : InanoTable + { + /// + /// Helper class for comparing two instances of objects + /// using full array content for comparison (length of arrays also should be equal). + /// + private sealed class ByteArrayComparer : IEqualityComparer + { + /// + public bool Equals(byte[] lhs, byte[] rhs) + { + return (lhs.Length == rhs.Length && lhs.SequenceEqual(rhs)); + } + + /// + public int GetHashCode(byte[] that) + { + return that.Aggregate(37, (hash, item) => item ^ hash); + } + } + + private static readonly IDictionary _primitiveTypes = + new Dictionary(StringComparer.Ordinal); + + static nanoSignaturesTable() + { + _primitiveTypes.Add(typeof(void).FullName, nanoCLR_DataType.DATATYPE_VOID); + + _primitiveTypes.Add(typeof(sbyte).FullName, nanoCLR_DataType.DATATYPE_I1); + _primitiveTypes.Add(typeof(short).FullName, nanoCLR_DataType.DATATYPE_I2); + _primitiveTypes.Add(typeof(int).FullName, nanoCLR_DataType.DATATYPE_I4); + _primitiveTypes.Add(typeof(long).FullName, nanoCLR_DataType.DATATYPE_I8); + + _primitiveTypes.Add(typeof(byte).FullName, nanoCLR_DataType.DATATYPE_U1); + _primitiveTypes.Add(typeof(ushort).FullName, nanoCLR_DataType.DATATYPE_U2); + _primitiveTypes.Add(typeof(uint).FullName, nanoCLR_DataType.DATATYPE_U4); + _primitiveTypes.Add(typeof(ulong).FullName, nanoCLR_DataType.DATATYPE_U8); + + _primitiveTypes.Add(typeof(float).FullName, nanoCLR_DataType.DATATYPE_R4); + _primitiveTypes.Add(typeof(double).FullName, nanoCLR_DataType.DATATYPE_R8); + + _primitiveTypes.Add(typeof(char).FullName, nanoCLR_DataType.DATATYPE_CHAR); + _primitiveTypes.Add(typeof(string).FullName, nanoCLR_DataType.DATATYPE_STRING); + _primitiveTypes.Add(typeof(bool).FullName, nanoCLR_DataType.DATATYPE_BOOLEAN); + + _primitiveTypes.Add(typeof(object).FullName, nanoCLR_DataType.DATATYPE_OBJECT); + _primitiveTypes.Add(typeof(IntPtr).FullName, nanoCLR_DataType.DATATYPE_I4); + _primitiveTypes.Add(typeof(UIntPtr).FullName, nanoCLR_DataType.DATATYPE_U4); + } + + /// + /// Stores list of unique signatures and corresspoinding identifiers. + /// + private readonly IDictionary _idsBySignatures = + new Dictionary(new ByteArrayComparer()); + + /// + /// Assembly tables context - contains all tables used for building target assembly. + /// + private readonly nanoTablesContext _context; + + /// + /// Last available signature id (offset in resulting table). + /// + private ushort _lastAvailableId; + + /// + /// Creates new instance of object. + /// + /// + /// Assembly tables context - contains all tables used for building target assembly. + /// + public nanoSignaturesTable( + nanoTablesContext context) + { + _context = context; + } + + /// + /// Gets existing or creates new singature identifier for method definition. + /// + /// Method definition in Mono.Cecil format. + public ushort GetOrCreateSignatureId( + MethodDefinition methodDefinition) + { + return GetOrCreateSignatureIdImpl(GetSignature(methodDefinition)); + } + + /// + /// Gets existing or creates new singature identifier for field definition. + /// + /// Field definition in Mono.Cecil format. + public ushort GetOrCreateSignatureId( + FieldDefinition fieldDefinition) + { + return GetOrCreateSignatureIdImpl(GetSignature(fieldDefinition.FieldType, true)); + } + + /// + /// Gets existing or creates new singature identifier for field reference. + /// + /// Field reference in Mono.Cecil format. + public ushort GetOrCreateSignatureId( + FieldReference fieldReference) + { + return GetOrCreateSignatureIdImpl(GetSignature(fieldReference)); + } + + /// + /// Gets existing or creates new singature identifier for member reference. + /// + /// Method reference in Mono.Cecil format. + public ushort GetOrCreateSignatureId( + MethodReference methodReference) + { + return GetOrCreateSignatureIdImpl(GetSignature(methodReference)); + } + + /// + /// Gets existing or creates new singature identifier for list of local variables. + /// + /// List of variables information in Mono.Cecil format. + public ushort GetOrCreateSignatureId( + Collection variables) + { + if (variables == null || variables.Count == 0) + { + return 0xFFFF; // No local variables + } + + return GetOrCreateSignatureIdImpl(GetSignature(variables)); + } + + /// + /// Gets existing or creates new singature identifier for list of class interfaces. + /// + /// List of interfaes information in Mono.Cecil format. + public ushort GetOrCreateSignatureId( + Collection interfaces) + { + if (interfaces == null || interfaces.Count == 0) + { + return 0xFFFF; // No implemented interfaces + } + + return GetOrCreateSignatureIdImpl(GetSignature(interfaces)); + } + + /// + /// Gets existing or creates new field default value (just writes value as is with size). + /// + /// Default field value in binary format. + public ushort GetOrCreateSignatureId( + byte[] defaultValue) + { + if (defaultValue == null || defaultValue.Length == 0) + { + return 0xFFFF; // No default value + } + + return GetOrCreateSignatureIdImpl(GetSignature(defaultValue)); + } + + /// + /// Gets existing or creates new type reference signature (used for encoding type specification). + /// + /// Interface implementation in Mono.Cecil format. + public ushort GetOrCreateSignatureId( + InterfaceImplementation interfaceImplementation) + { + return GetOrCreateSignatureIdImpl(GetSignature(interfaceImplementation, false)); + } + + /// + /// Gets existing or creates new type reference signature (used for encoding type specification). + /// + /// Type reference in Mono.Cecil format. + public ushort GetOrCreateSignatureId( + TypeReference typeReference) + { + return GetOrCreateSignatureIdImpl(GetSignature(typeReference, false)); + } + + /// + /// Gets existing or creates new custom attribute signature. + /// + /// Custom attribute in Mono.Cecil format. + public ushort GetOrCreateSignatureId(CustomAttribute customAttribute) + { + return GetOrCreateSignatureIdImpl(GetSignature(customAttribute)); + } + + /// + /// Writes data tzpe signature into ouput stream. + /// + /// Tzpe reference or definition in Mono.Cecil format. + /// Target binary writer for writing signature information. + /// If set to true also sub-type will be written. + /// If set to true expand enum with base type. + public void WriteDataType( + TypeReference typeDefinition, + nanoBinaryWriter writer, + bool alsoWriteSubType, + bool expandEnumType) + { + nanoCLR_DataType dataType; + if (_primitiveTypes.TryGetValue(typeDefinition.FullName, out dataType)) + { + writer.WriteByte((byte)dataType); + return; + } + + if (typeDefinition is TypeSpecification) + { + //Debug.Fail("Gotcha!"); + } + + if (typeDefinition.MetadataType == MetadataType.Class) + { + writer.WriteByte((byte)nanoCLR_DataType.DATATYPE_CLASS); + if (alsoWriteSubType) + { + WriteSubTypeInfo(typeDefinition, writer); + } + return; + } + + if (typeDefinition.MetadataType == MetadataType.ValueType) + { + var resolvedType = typeDefinition.Resolve(); + if (resolvedType != null && resolvedType.IsEnum && expandEnumType) + { + var baseTypeValue = resolvedType.Fields.FirstOrDefault(item => item.IsSpecialName); + if (baseTypeValue != null) + { + WriteTypeInfo(baseTypeValue.FieldType, writer); + return; + } + } + + writer.WriteByte((byte)nanoCLR_DataType.DATATYPE_VALUETYPE); + if (alsoWriteSubType) + { + WriteSubTypeInfo(typeDefinition, writer); + } + return; + } + + if (typeDefinition.IsArray) + { + writer.WriteByte((byte)nanoCLR_DataType.DATATYPE_SZARRAY); + + if (alsoWriteSubType) + { + var array = (ArrayType)typeDefinition; + WriteDataType(array.ElementType, writer, true, expandEnumType); + } + return; + } + + writer.WriteByte(0x00); + } + + /// + public void Write( + nanoBinaryWriter writer) + { + foreach (var signature in _idsBySignatures + .OrderBy(item => item.Value) + .Select(item => item.Key)) + { + writer.WriteBytes(signature); + } + } + + private byte[] GetSignature( + FieldReference fieldReference) + { + using (var buffer = new MemoryStream()) + using (var writer = new BinaryWriter(buffer)) // Only Write(Byte) will be used + { + var binaryWriter = nanoBinaryWriter.CreateBigEndianBinaryWriter(writer); + + binaryWriter.WriteByte(0x06); // Field reference calling convention + WriteTypeInfo(fieldReference.FieldType, binaryWriter); + + return buffer.ToArray(); + } + } + + private byte[] GetSignature( + IMethodSignature methodReference) + { + using (var buffer = new MemoryStream()) + using (var writer = new BinaryWriter(buffer)) // Only Write(Byte) will be used + { + var binaryWriter = nanoBinaryWriter.CreateLittleEndianBinaryWriter(writer); + writer.Write((byte)(methodReference.HasThis ? 0x20 : 0x00)); + + writer.Write((byte)(methodReference.Parameters.Count)); + + WriteTypeInfo(methodReference.ReturnType, binaryWriter); + foreach (var parameter in methodReference.Parameters) + { + WriteTypeInfo(parameter.ParameterType, binaryWriter); + } + + return buffer.ToArray(); + } + } + + private byte[] GetSignature( + IEnumerable variables) + { + using (var buffer = new MemoryStream()) + using (var writer = new BinaryWriter(buffer)) // Only Write(Byte) will be used + { + var binaryWriter = nanoBinaryWriter.CreateBigEndianBinaryWriter(writer); + foreach (var variable in variables) + { + WriteTypeInfo(variable.VariableType, binaryWriter); + } + + return buffer.ToArray(); + } + } + + private byte[] GetSignature( + Collection interfaces) + { + using (var buffer = new MemoryStream()) + using (var writer = new BinaryWriter(buffer)) // Only Write(Byte) will be used + { + var binaryWriter = nanoBinaryWriter.CreateBigEndianBinaryWriter(writer); + + binaryWriter.WriteByte((byte)interfaces.Count); + foreach (var item in interfaces) + { + WriteSubTypeInfo(item.InterfaceType, binaryWriter); + } + + return buffer.ToArray(); + } + } + + private byte[] GetSignature( + TypeReference typeReference, + bool isFieldSignature) + { + using (var buffer = new MemoryStream()) + using (var writer = new BinaryWriter(buffer)) // Only Write(Byte) will be used + { + var binaryWriter = nanoBinaryWriter.CreateBigEndianBinaryWriter(writer); + + if (isFieldSignature) + { + writer.Write((byte)0x06); // Field signature prefix + } + WriteTypeInfo(typeReference, binaryWriter); + + return buffer.ToArray(); + } + } + + private byte[] GetSignature( + InterfaceImplementation typeReference, + bool isFieldSignature) + { + return GetSignature(typeReference.InterfaceType, isFieldSignature); + } + + private byte[] GetSignature( + byte[] defaultValue) + { + using (var buffer = new MemoryStream()) + using (var writer = new BinaryWriter(buffer)) + { + writer.Write((byte)defaultValue.Length); + writer.Write((byte)0x00); // TODO: investigate this temporary fix + writer.Write(defaultValue); + + return buffer.ToArray(); + } + } + + private byte[] GetSignature( + CustomAttribute customAttribute) + { + using (var buffer = new MemoryStream()) + using (var writer = new BinaryWriter(buffer)) + { + foreach (var argument in customAttribute.ConstructorArguments) + { + WriteAttributeArgumentValue(writer, argument); + } + + // TODO: use compressed format + writer.Write((ushort)(customAttribute.Properties.Count + customAttribute.Fields.Count)); + + foreach (var namedArgument in customAttribute.Fields.OrderBy(item => item.Name)) + { + writer.Write((byte)nanoSerializationType.SERIALIZATION_TYPE_FIELD); + writer.Write(_context.StringTable.GetOrCreateStringId(namedArgument.Name)); + WriteAttributeArgumentValue(writer, namedArgument.Argument); + } + + foreach (var namedArgument in customAttribute.Properties.OrderBy(item => item.Name)) + { + writer.Write((byte)nanoSerializationType.SERIALIZATION_TYPE_PROPERTY); + writer.Write(_context.StringTable.GetOrCreateStringId(namedArgument.Name)); + WriteAttributeArgumentValue(writer, namedArgument.Argument); + } + + return buffer.ToArray(); + } + } + + private void WriteAttributeArgumentValue( + BinaryWriter writer, + CustomAttributeArgument argument) + { + nanoCLR_DataType dataType; + if (_primitiveTypes.TryGetValue(argument.Type.FullName, out dataType)) + { + switch (dataType) + { + case nanoCLR_DataType.DATATYPE_BOOLEAN: + writer.Write((byte)nanoSerializationType.ELEMENT_TYPE_BOOLEAN); + writer.Write((byte)((bool)argument.Value ? 1 : 0)); + break; + case nanoCLR_DataType.DATATYPE_I1: + writer.Write((byte)nanoSerializationType.ELEMENT_TYPE_I1); + writer.Write((sbyte)argument.Value); + break; + case nanoCLR_DataType.DATATYPE_U1: + writer.Write((byte)nanoSerializationType.ELEMENT_TYPE_U1); + writer.Write((byte)argument.Value); + break; + case nanoCLR_DataType.DATATYPE_I2: + writer.Write((byte)nanoSerializationType.ELEMENT_TYPE_I2); + writer.Write((short)argument.Value); + break; + case nanoCLR_DataType.DATATYPE_U2: + writer.Write((byte)nanoSerializationType.ELEMENT_TYPE_U2); + writer.Write((ushort)argument.Value); + break; + case nanoCLR_DataType.DATATYPE_I4: + writer.Write((byte)nanoSerializationType.ELEMENT_TYPE_I4); + writer.Write((int)argument.Value); + break; + case nanoCLR_DataType.DATATYPE_U4: + writer.Write((byte)nanoSerializationType.ELEMENT_TYPE_U4); + writer.Write((uint)argument.Value); + break; + case nanoCLR_DataType.DATATYPE_I8: + writer.Write((byte)nanoSerializationType.ELEMENT_TYPE_I8); + writer.Write((long)argument.Value); + break; + case nanoCLR_DataType.DATATYPE_U8: + writer.Write((byte)nanoSerializationType.ELEMENT_TYPE_U8); + writer.Write((ulong)argument.Value); + break; + case nanoCLR_DataType.DATATYPE_R4: + writer.Write((byte)nanoSerializationType.ELEMENT_TYPE_R4); + writer.Write((float)argument.Value); + break; + case nanoCLR_DataType.DATATYPE_R8: + writer.Write((byte)nanoSerializationType.ELEMENT_TYPE_R8); + writer.Write((double)argument.Value); + break; + case nanoCLR_DataType.DATATYPE_CHAR: + writer.Write((byte)nanoSerializationType.ELEMENT_TYPE_CHAR); + writer.Write((char)argument.Value); + break; + case nanoCLR_DataType.DATATYPE_STRING: + writer.Write((byte)nanoSerializationType.ELEMENT_TYPE_STRING); + writer.Write(_context.StringTable.GetOrCreateStringId((string)argument.Value)); + break; + default: + Debug.Fail(dataType.ToString()); + break; + } + } + if (argument.Type.FullName == "System.Type") + { + writer.Write((byte)nanoSerializationType.ELEMENT_TYPE_STRING); + writer.Write(_context.StringTable.GetOrCreateStringId(((TypeReference)argument.Value).FullName)); + } + } + + private ushort GetOrCreateSignatureIdImpl( + byte[] signature) + { + ushort id; + if (_idsBySignatures.TryGetValue(signature, out id)) + { + return id; + } + + var fullSignatures = GetFullSignaturesArray(); + for (var i = 0; i < fullSignatures.Length - signature.Length; ++i) + { + if (signature.SequenceEqual(fullSignatures.Skip(i).Take(signature.Length))) + { + return (ushort)i; + } + } + + id = _lastAvailableId; + _idsBySignatures.Add(signature, id); + _lastAvailableId += (ushort)signature.Length; + + return id; + } + + private void WriteTypeInfo( + TypeReference typeReference, + nanoBinaryWriter writer) + { + if (typeReference.IsOptionalModifier) + { + writer.WriteByte(0); // OpTypeModifier ??? + } + + var byReference = typeReference as ByReferenceType; + if (byReference != null) + { + writer.WriteByte((byte)nanoCLR_DataType.DATATYPE_BYREF); + WriteDataType(byReference.ElementType, writer, true, false); + } + else + { + WriteDataType(typeReference, writer, true, false); + } + } + + private byte[] GetFullSignaturesArray() + { + return _idsBySignatures + .OrderBy(item => item.Value) + .Select(item => item.Key) + .Aggregate(new List(), + (current, item) => + { + current.AddRange(item); + return current; + }) + .ToArray(); + } + + private void WriteSubTypeInfo(TypeReference typeDefinition, nanoBinaryWriter writer) + { + ushort referenceId; + if (typeDefinition is TypeSpecification && + _context.TypeSpecificationsTable.TryGetTypeReferenceId(typeDefinition, out referenceId)) + { + writer.WriteMetadataToken(((uint)referenceId << 2) | 0x04); + } + else if (_context.TypeReferencesTable.TryGetTypeReferenceId(typeDefinition, out referenceId)) + { + writer.WriteMetadataToken(((uint)referenceId << 2) | 0x01); + } + else if (_context.TypeDefinitionTable.TryGetTypeReferenceId( + typeDefinition.Resolve(), out referenceId)) + { + writer.WriteMetadataToken((uint)referenceId << 2); + } + } + } +} diff --git a/source/MetadataProcessor.Core/Tables/nanoStringTable.cs b/source/MetadataProcessor.Core/Tables/nanoStringTable.cs new file mode 100644 index 00000000..118debc2 --- /dev/null +++ b/source/MetadataProcessor.Core/Tables/nanoStringTable.cs @@ -0,0 +1,116 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using System; +using System.Collections.Generic; +using System.Linq; +using System.Text; + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Encapsulates logic for storing strings list and writing this + /// list into target assembly in .NET nanoFramework format. + /// + public sealed class nanoStringTable : InanoTable + { + /// + /// Default implementation of interface. + /// Do nothing and just returns original sequence of string literals. + /// + private sealed class EmptyStringSorter : ICustomStringSorter + { + /// + public IEnumerable Sort( + ICollection strings) + { + return strings; + } + } + + /// + /// Maps for each unique string and related identifier (offset in strings table). + /// + private readonly Dictionary _idsByStrings = + new Dictionary(StringComparer.Ordinal); + + /// + /// Concrete implementation of string literals sorting algorithm (used by UTs). + /// + private readonly ICustomStringSorter _stringSorter; + + /// + /// Last available string identifier. + /// + private ushort _lastAvailableId; + + /// + /// Creates new instance of object. + /// + public nanoStringTable( + ICustomStringSorter stringSorter = null) + { + GetOrCreateStringId(string.Empty); // First item in string table always empty string + _stringSorter = stringSorter ?? new EmptyStringSorter(); + } + + /// + /// Gets existing or creates new string reference identifier related to passed string value. + /// + /// + /// Identifier is offset in strings table or just number from table of pre-defined constants. + /// + /// String value for obtaining identifier. + /// + /// If true hard-coded string constants table will be used (should be false + /// for byte code writer because onlyloader use this pre-defined string table optimization). + /// + /// Existing identifier if string already in table or new one. + public ushort GetOrCreateStringId( + string value, + bool useConstantsTable = true) + { + ushort id; + if (useConstantsTable && nanoStringsConstants.TryGetStringIndex(value, out id)) + { + return id; + } + if (!_idsByStrings.TryGetValue(value, out id)) + { + id = _lastAvailableId; + _idsByStrings.Add(value, id); + var length = Encoding.UTF8.GetBytes(value).Length + 1; + _lastAvailableId += (ushort)(length); + } + return id; + } + + /// + public void Write( + nanoBinaryWriter writer) + { + foreach (var item in _idsByStrings + .OrderBy(item => item.Value) + .Select(item => item.Key)) + { + writer.WriteString(item); + } + } + + /// + /// Adds all string constants from table into this one. + /// + /// Additional string table for merging with this one. + internal void MergeValues( + nanoStringTable fakeStringTable) + { + foreach (var item in _stringSorter.Sort(fakeStringTable._idsByStrings.Keys)) + { + GetOrCreateStringId(item, false); + } + } + } +} diff --git a/source/MetadataProcessor.Core/Tables/nanoTablesContext.cs b/source/MetadataProcessor.Core/Tables/nanoTablesContext.cs new file mode 100644 index 00000000..fc54915f --- /dev/null +++ b/source/MetadataProcessor.Core/Tables/nanoTablesContext.cs @@ -0,0 +1,400 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using Mono.Cecil; +using System; +using System.Collections.Generic; +using System.Linq; + +namespace nanoFramework.Tools.MetadataProcessor +{ + public sealed class nanoTablesContext + { + private readonly HashSet _ignoringAttributes = + new HashSet(StringComparer.Ordinal) + { + // Assembly-level attributes + "System.Reflection.AssemblyCultureAttribute", + "System.Reflection.AssemblyVersionAttribute", + "System.Reflection.AssemblyFileVersionAttribute", + "System.Reflection.AssemblyTrademarkAttribute", + "System.Reflection.AssemblyTitleAttribute", + "System.Reflection.AssemblyProductAttribute", + "System.Reflection.AssemblyKeyNameAttribute", + "System.Reflection.AssemblyKeyFileAttribute", + "System.Reflection.AssemblyInformationalVersionAttribute", + "System.Reflection.AssemblyFlagsAttribute", + "System.Reflection.AssemblyDescriptionAttribute", + "System.Reflection.AssemblyDelaySignAttribute", + "System.Reflection.AssemblyDefaultAliasAttribute", + "System.Reflection.AssemblyCopyrightAttribute", + "System.Reflection.AssemblyConfigurationAttribute", + "System.Reflection.AssemblyCompanyAttribute", + "System.Runtime.InteropServices.ComVisibleAttribute", + "System.Runtime.InteropServices.GuidAttribute", + + // Compiler-specific attributes + "System.ParamArrayAttribute", + "System.SerializableAttribute", + "System.NonSerializedAttribute", + "System.Runtime.InteropServices.StructLayoutAttribute", + "System.Runtime.InteropServices.LayoutKind", + "System.Runtime.InteropServices.OutAttribute", + "System.Runtime.CompilerServices.ExtensionAttribute", + "System.Runtime.CompilerServices.MethodImplAttribute", + "System.Runtime.CompilerServices.InternalsVisibleToAttribute", + "System.Runtime.CompilerServices.IndexerNameAttribute", + "System.Runtime.CompilerServices.MethodImplOptions", + "System.Reflection.FieldNoReflectionAttribute", + "System.Reflection.DefaultMemberAttribute", + + // Debugger-specific attributes + "System.Diagnostics.DebuggableAttribute", + "System.Diagnostics.DebuggerNonUserCodeAttribute", + "System.Diagnostics.DebuggerStepThroughAttribute", + "System.Diagnostics.DebuggerDisplayAttribute", + "System.Diagnostics.DebuggerBrowsableAttribute", + "System.Diagnostics.DebuggerBrowsableState", + "System.Diagnostics.DebuggerHiddenAttribute", + + // Compile-time attributes + "System.AttributeUsageAttribute", + "System.CLSCompliantAttribute", + "System.FlagsAttribute", + "System.ObsoleteAttribute", + "System.Diagnostics.ConditionalAttribute", + + // Intellisense filtering attributes + "System.ComponentModel.EditorBrowsableAttribute", + + // Not supported attributes + "System.MTAThreadAttribute", + "System.STAThreadAttribute", + "System.Reflection.DefaultMemberAttribute", + }; + + public nanoTablesContext( + AssemblyDefinition assemblyDefinition, + List explicitTypesOrder, + ICustomStringSorter stringSorter, + bool applyAttributesCompression) + { + AssemblyDefinition = assemblyDefinition; + + foreach (var item in assemblyDefinition.CustomAttributes) + { + _ignoringAttributes.Add(item.AttributeType.FullName); + } + + NativeMethodsCrc = new NativeMethodsCrc(assemblyDefinition); + + var mainModule = AssemblyDefinition.MainModule; + + // External references + + AssemblyReferenceTable = new nanoAssemblyReferenceTable( + mainModule.AssemblyReferences, this); + + var typeReferences = mainModule.GetTypeReferences() + .Where(item => !IsAttribute(item)) + .ToList(); + TypeReferencesTable = new nanoTypeReferenceTable( + typeReferences, this); + + var typeReferencesNames = new HashSet( + typeReferences.Select(item => item.FullName), + StringComparer.Ordinal); + var memberReferences = mainModule.GetMemberReferences() + .Where(item => typeReferencesNames.Contains(item.DeclaringType.FullName)) + .ToList(); + FieldReferencesTable = new nanoFieldReferenceTable( + memberReferences.OfType(), this); + MethodReferencesTable = new nanoMethodReferenceTable( + memberReferences.OfType(), this); + + // Internal types definitions + + var types = GetOrderedTypes(mainModule, explicitTypesOrder); + + TypeDefinitionTable = new nanoTypeDefinitionTable(types, this); + + var fields = types + .SelectMany(item => GetOrderedFields(item.Fields.Where(field => !field.HasConstant))) + .ToList(); + FieldsTable = new nanoFieldDefinitionTable(fields, this); + + var methods = types.SelectMany(item => GetOrderedMethods(item.Methods)).ToList(); + + MethodDefinitionTable = new nanoMethodDefinitionTable(methods, this); + + AttributesTable = new nanoAttributesTable( + GetAttributes(types, applyAttributesCompression), + GetAttributes(fields, applyAttributesCompression), + GetAttributes(methods, applyAttributesCompression), + this); + + TypeSpecificationsTable = new nanoTypeSpecificationsTable(this); + + // Resources information + + ResourcesTable = new nanoResourcesTable( + mainModule.Resources, this); + ResourceDataTable = new nanoResourceDataTable(); + + // Strings and signatures + + SignaturesTable = new nanoSignaturesTable(this); + StringTable = new nanoStringTable(stringSorter); + + // Byte code table + ByteCodeTable = new nanoByteCodeTable(this); + + // Additional information + + ResourceFileTable = new nanoResourceFileTable(this); + + // Pre-allocate strings from some tables + AssemblyReferenceTable.AllocateStrings(); + TypeReferencesTable.AllocateStrings(); + foreach (var item in memberReferences) + { + StringTable.GetOrCreateStringId(item.Name); + + var fieldReference = item as FieldReference; + if (fieldReference != null) + { + SignaturesTable.GetOrCreateSignatureId(fieldReference); + } + + var methodReference = item as MethodReference; + if (methodReference != null) + { + SignaturesTable.GetOrCreateSignatureId(methodReference); + } + } + } + + /// + /// Gets method reference identifier (external or internal) encoded with appropriate prefix. + /// + /// Method reference in Mono.Cecil format. + /// Reference identifier for passed value. + public ushort GetMethodReferenceId( + MethodReference methodReference) + { + ushort referenceId; + if (MethodReferencesTable.TryGetMethodReferenceId(methodReference, out referenceId)) + { + referenceId |= 0x8000; // External method reference + } + else + { + MethodDefinitionTable.TryGetMethodReferenceId(methodReference.Resolve(), out referenceId); + } + return referenceId; + } + + public AssemblyDefinition AssemblyDefinition { get; private set; } + + public NativeMethodsCrc NativeMethodsCrc { get; private set; } + + public nanoAssemblyReferenceTable AssemblyReferenceTable { get; private set; } + + public nanoTypeReferenceTable TypeReferencesTable { get; private set; } + + public nanoFieldReferenceTable FieldReferencesTable { get; private set; } + + public nanoMethodReferenceTable MethodReferencesTable { get; private set; } + + public nanoFieldDefinitionTable FieldsTable { get; private set; } + + public nanoMethodDefinitionTable MethodDefinitionTable { get; private set; } + + public nanoTypeDefinitionTable TypeDefinitionTable { get; private set; } + + public nanoAttributesTable AttributesTable { get; private set; } + + public nanoTypeSpecificationsTable TypeSpecificationsTable { get; private set; } + + public nanoResourcesTable ResourcesTable { get; private set; } + + public nanoResourceDataTable ResourceDataTable { get; private set; } + + public nanoSignaturesTable SignaturesTable { get; private set; } + + public nanoStringTable StringTable { get; private set; } + + public nanoByteCodeTable ByteCodeTable { get; private set; } + + public nanoResourceFileTable ResourceFileTable { get; private set; } + + private IEnumerable> GetAttributes( + IEnumerable types, + bool applyAttributesCompression) + { + if (applyAttributesCompression) + { + return types.SelectMany( + (item, index) => item.CustomAttributes + .Where(attr => !IsAttribute(attr.AttributeType)) + .OrderByDescending(attr => attr.AttributeType.FullName) + .Select(attr => new Tuple(attr, (ushort)index))); + + } + return types.SelectMany( + (item, index) => item.CustomAttributes + .Where(attr => !IsAttribute(attr.AttributeType)) + .Select(attr => new Tuple(attr, (ushort)index))); + } + + private bool IsAttribute( + MemberReference typeReference) + { + return + _ignoringAttributes.Contains(typeReference.FullName) || + (typeReference.DeclaringType != null && + _ignoringAttributes.Contains(typeReference.DeclaringType.FullName)); + } + + private static List GetOrderedTypes( + ModuleDefinition mainModule, + List explicitTypesOrder) + { + var unorderedTypes = mainModule.GetTypes() + .Where(item => item.FullName != "") + .ToList(); + + if (explicitTypesOrder == null || explicitTypesOrder.Count == 0) + { + return SortTypesAccordingUsages( + unorderedTypes, mainModule.FileName); + } + + return explicitTypesOrder + .Join(unorderedTypes, outer => outer, inner => inner.FullName, (inner, outer) => outer) + .ToList(); + } + + private static List SortTypesAccordingUsages( + IEnumerable types, + string mainModuleName) + { + var processedTypes = new HashSet(StringComparer.Ordinal); + return SortTypesAccordingUsagesImpl( + types.OrderBy(item => item.FullName), + mainModuleName, processedTypes) + .ToList(); + } + + private static IEnumerable SortTypesAccordingUsagesImpl( + IEnumerable types, + string mainModuleName, + ISet processedTypes) + { + foreach (var type in types) + { + if (processedTypes.Contains(type.FullName)) + { + continue; + } + + if (type.DeclaringType != null) + { + foreach (var declaredIn in SortTypesAccordingUsagesImpl( + Enumerable.Repeat(type.DeclaringType, 1), mainModuleName, processedTypes)) + { + yield return declaredIn; + } + } + + foreach (var implement in SortTypesAccordingUsagesImpl( + type.Interfaces.Select(itf => itf.InterfaceType.Resolve()) + .Where(item => item.Module.FileName == mainModuleName), + mainModuleName, processedTypes)) + { + yield return implement; + } + + if (processedTypes.Add(type.FullName)) + { + var operands = type.Methods + .Where(item => item.HasBody) + .SelectMany(item => item.Body.Instructions) + .Select(item => item.Operand) + .OfType() + .ToList(); + + foreach (var fieldType in SortTypesAccordingUsagesImpl( + operands.SelectMany(GetTypesList) + .Where(item => item.Module.FileName == mainModuleName), + mainModuleName, processedTypes)) + { + yield return fieldType; + } + + yield return type; + } + } + } + + private static IEnumerable GetTypesList( + MethodReference methodReference) + { + var returnType = methodReference.ReturnType.Resolve(); + if (returnType != null && returnType.FullName != "System.Void") + { + yield return returnType; + } + foreach (var parameter in methodReference.Parameters) + { + var parameterType = parameter.ParameterType.Resolve(); + if (parameterType != null) + { + yield return parameterType; + } + } + } + + private static IEnumerable GetOrderedMethods( + IEnumerable methods) + { + var ordered = methods + .ToList(); + + foreach (var method in ordered.Where(item => item.IsVirtual)) + { + yield return method; + } + + foreach (var method in ordered.Where(item => !(item.IsVirtual || item.IsStatic))) + { + yield return method; + } + + foreach (var method in ordered.Where(item => item.IsStatic)) + { + yield return method; + } + } + + private static IEnumerable GetOrderedFields( + IEnumerable fields) + { + var ordered = fields + .ToList(); + + foreach (var method in ordered.Where(item => item.IsStatic)) + { + yield return method; + } + + foreach (var method in ordered.Where(item => !item.IsStatic)) + { + yield return method; + } + } + } +} diff --git a/source/MetadataProcessor.Core/Tables/nanoTypeDefinitionTable.cs b/source/MetadataProcessor.Core/Tables/nanoTypeDefinitionTable.cs new file mode 100644 index 00000000..4ab64a5a --- /dev/null +++ b/source/MetadataProcessor.Core/Tables/nanoTypeDefinitionTable.cs @@ -0,0 +1,378 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using Mono.Cecil; +using Mono.Collections.Generic; +using System; +using System.Collections.Generic; +using System.IO; +using System.Linq; + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Encapsulates logic for storing type definitions (complete type metadata) list and writing + /// this collected list into target assembly in .NET nanoFramework format. + /// + public sealed class nanoTypeDefinitionTable : + nanoReferenceTableBase + { + /// + /// Helper class for comparing two instances of objects + /// using property as unique key for comparison. + /// + private sealed class TypeDefinitionEqualityComparer : IEqualityComparer + { + /// + public bool Equals(TypeDefinition lhs, TypeDefinition rhs) + { + return string.Equals(lhs.FullName, rhs.FullName, StringComparison.Ordinal); + } + + /// + public int GetHashCode(TypeDefinition item) + { + return item.FullName.GetHashCode(); + } + } + + private IDictionary>> _byteCodeOffsets = + new Dictionary>>(); + + /// + /// Creates new instance of object. + /// + /// List of types definitins in Mono.Cecil format. + /// + /// Assembly tables context - contains all tables used for building target assembly. + /// + public nanoTypeDefinitionTable( + IEnumerable items, + nanoTablesContext context) + : base(items, new TypeDefinitionEqualityComparer(), context) + { + } + + /// + /// Gets type reference identifier (if type is provided and this type is defined in target assembly). + /// + /// + /// For null value passed in returns 0xFFFF value. + /// + /// Type definition in Mono.Cecil format. + /// Type reference identifier for filling. + /// Returns true if item found, otherwise returns false. + public bool TryGetTypeReferenceId( + TypeDefinition typeDefinition, + out ushort referenceId) + { + if (typeDefinition == null) // This case is possible for encoding 'nested inside' case + { + referenceId = 0xFFFF; + return true; + } + + return TryGetIdByValue(typeDefinition, out referenceId); + } + + public IEnumerable> GetByteCodeOffsets( + uint clrMethodToken) + { + return _byteCodeOffsets[clrMethodToken]; + } + + /// + protected override void WriteSingleItem( + nanoBinaryWriter writer, + TypeDefinition item) + { + _context.StringTable.GetOrCreateStringId(item.Namespace); + + WriteStringReference(writer, item.Name); + WriteStringReference(writer, item.Namespace); + + writer.WriteUInt16(GetTypeReferenceOrDefinitionId(item.BaseType)); + writer.WriteUInt16(GetTypeReferenceOrDefinitionId(item.DeclaringType)); + + var fieldsList = item.Fields + .Where(field => !field.HasConstant) + .OrderByDescending(field => field.IsStatic) + .ToList(); + foreach (var field in fieldsList) + { + _context.SignaturesTable.GetOrCreateSignatureId(field); + _context.SignaturesTable.GetOrCreateSignatureId(field.InitialValue); + } + + using (var stream = new MemoryStream(6)) + { + WriteClassFields(fieldsList, writer.GetMemoryBasedClone(stream)); + + if (item.DeclaringType == null) + { + foreach (var method in item.Methods) + { + var offsets = CodeWriter + .PreProcessMethod(method, _context.ByteCodeTable.FakeStringTable) + .ToList(); + _byteCodeOffsets.Add(method.MetadataToken.ToUInt32(), offsets); + } + } + foreach (var nestedType in item.NestedTypes) + { + foreach (var method in nestedType.Methods) + { + var offsets = CodeWriter + .PreProcessMethod(method, _context.ByteCodeTable.FakeStringTable) + .ToList(); + _byteCodeOffsets.Add(method.MetadataToken.ToUInt32(), offsets); + } + } + + WriteMethodBodies(item.Methods, item.Interfaces, writer); + + _context.SignaturesTable.WriteDataType(item, writer, false, true); + + writer.WriteBytes(stream.ToArray()); + } + + writer.WriteUInt16(GetFlags(item)); // flags + } + + private void WriteClassFields( + IList fieldsList, + nanoBinaryWriter writer) + { + var firstStaticFieldId = _context.FieldsTable.MaxFieldId; + var staticFieldsNumber = 0; + foreach (var field in fieldsList.Where(item => item.IsStatic)) + { + ushort fieldReferenceId; + _context.FieldsTable.TryGetFieldReferenceId(field, true, out fieldReferenceId); + firstStaticFieldId = Math.Min(firstStaticFieldId, fieldReferenceId); + + _context.SignaturesTable.GetOrCreateSignatureId(field); + _context.StringTable.GetOrCreateStringId(field.Name); + + ++staticFieldsNumber; + } + + var firstInstanseFieldId = _context.FieldsTable.MaxFieldId; + var instanceFieldsNumber = 0; + foreach (var field in fieldsList.Where(item => !item.IsStatic)) + { + ushort fieldReferenceId; + _context.FieldsTable.TryGetFieldReferenceId(field, true, out fieldReferenceId); + firstInstanseFieldId = Math.Min(firstInstanseFieldId, fieldReferenceId); + + _context.SignaturesTable.GetOrCreateSignatureId(field); + _context.StringTable.GetOrCreateStringId(field.Name); + + ++instanceFieldsNumber; + } + + if (firstStaticFieldId > firstInstanseFieldId) + { + firstStaticFieldId = firstInstanseFieldId; + } + + writer.WriteUInt16(firstStaticFieldId); + writer.WriteUInt16(firstInstanseFieldId); + + writer.WriteByte((byte) staticFieldsNumber); + writer.WriteByte((byte) instanceFieldsNumber); + } + + private void WriteMethodBodies( + Collection methods, + Collection iInterfaces, + nanoBinaryWriter writer) + { + ushort firstMethodId = 0xFFFF; + var virtualMethodsNumber = 0; + foreach (var method in methods.Where(item => item.IsVirtual)) + { + firstMethodId = Math.Min(firstMethodId, _context.ByteCodeTable.GetMethodId(method)); + CreateMethodSignatures(method); + ++virtualMethodsNumber; + } + + var instanceMethodsNumber = 0; + foreach (var method in methods.Where(item => !(item.IsVirtual || item.IsStatic))) + { + firstMethodId = Math.Min(firstMethodId, _context.ByteCodeTable.GetMethodId(method)); + CreateMethodSignatures(method); + ++instanceMethodsNumber; + } + + var staticMethodsNumber = 0; + foreach (var method in methods.Where(item => item.IsStatic)) + { + firstMethodId = Math.Min(firstMethodId, _context.ByteCodeTable.GetMethodId(method)); + CreateMethodSignatures(method); + ++staticMethodsNumber; + } + + if (virtualMethodsNumber + instanceMethodsNumber + staticMethodsNumber == 0) + { + firstMethodId = _context.ByteCodeTable.NextMethodId; + } + + writer.WriteUInt16(_context.SignaturesTable.GetOrCreateSignatureId(iInterfaces)); + + writer.WriteUInt16(firstMethodId); + + writer.WriteByte((byte)virtualMethodsNumber); + writer.WriteByte((byte)instanceMethodsNumber); + writer.WriteByte((byte)staticMethodsNumber); + } + + private void CreateMethodSignatures( + MethodDefinition method) + { + _context.SignaturesTable.GetOrCreateSignatureId(method); + if (method.HasBody) + { + _context.SignaturesTable.GetOrCreateSignatureId(method.Body.Variables); + } + _context.StringTable.GetOrCreateStringId(method.Name); + } + + private ushort GetTypeReferenceOrDefinitionId( + TypeReference typeReference) + { + ushort referenceId; + if (_context.TypeReferencesTable.TryGetTypeReferenceId(typeReference, out referenceId)) + { + return (ushort)(0x8000 | referenceId); + } + + ushort typeId; + if (TryGetTypeReferenceId(typeReference.Resolve(), out typeId)) + { + return typeId; + } + + return 0xFFFF; + } + + private ushort GetFlags( + TypeDefinition definition) + { + const ushort TD_Scope_Public = 0x0001; // Class is public scope. + const ushort TD_Scope_NestedPublic = 0x0002; // Class is nested with public visibility. + const ushort TD_Scope_NestedPrivate = 0x0003; // Class is nested with private visibility. + const ushort TD_Scope_NestedFamily = 0x0004; // Class is nested with family visibility. + const ushort TD_Scope_NestedAssembly = 0x0005; // Class is nested with assembly visibility. + const ushort TD_Scope_NestedFamANDAssem = 0x0006; // Class is nested with family and assembly visibility. + const ushort TD_Scope_NestedFamORAssem = 0x0007; // Class is nested with family or assembly visibility. + + const ushort TD_Serializable = 0x0008; + + const ushort TD_Semantics_ValueType = 0x0010; + const ushort TD_Semantics_Interface = 0x0020; + const ushort TD_Semantics_Enum = 0x0030; + + const ushort TD_Abstract = 0x0040; + const ushort TD_Sealed = 0x0080; + + const ushort TD_SpecialName = 0x0100; + const ushort TD_Delegate = 0x0200; + const ushort TD_MulticastDelegate = 0x0400; + const ushort TD_Patched = 0x0800; + + const ushort TD_BeforeFieldInit = 0x1000; + const ushort TD_HasSecurity = 0x2000; + const ushort TD_HasFinalizer = 0x4000; + const ushort TD_HasAttributes = 0x8000; + + var flags = 0x0000; + + if (definition.IsPublic) + { + flags = TD_Scope_Public; + } + else if (definition.IsNestedPublic) + { + flags = TD_Scope_NestedPublic; + } + else if (definition.IsNestedPrivate) + { + flags = TD_Scope_NestedPrivate; + } + else if (definition.IsNestedFamily) + { + flags = TD_Scope_NestedFamily; + } + else if (definition.IsNestedAssembly) + { + flags = TD_Scope_NestedAssembly; + } + else if (definition.IsNestedFamilyAndAssembly) + { + flags = TD_Scope_NestedFamANDAssem; + } + else if (definition.IsNestedFamilyOrAssembly) + { + flags = TD_Scope_NestedFamORAssem; + } + + if (definition.IsSerializable) + { + flags |= TD_Serializable; + } + + if (definition.IsEnum) + { + flags |= TD_Semantics_Enum; + flags |= TD_Serializable; + } + else if (definition.IsValueType) + { + flags |= TD_Semantics_ValueType; + } + else if (definition.IsInterface) + { + flags |= TD_Semantics_Interface; + } + + if (definition.IsAbstract) + { + flags |= TD_Abstract; + } + if (definition.IsSealed) + { + flags |= TD_Sealed; + } + + if (definition.IsSpecialName) + { + flags |= TD_SpecialName; + } + + if (definition.IsBeforeFieldInit) + { + flags |= TD_BeforeFieldInit; + } + if (definition.HasSecurity) + { + flags |= TD_HasSecurity; + } + if (definition.HasCustomAttributes) + { + flags |= TD_HasAttributes; + } + + var baseType = definition.BaseType; + if (baseType != null && baseType.FullName == "System.MulticastDelegate") + { + flags |= TD_MulticastDelegate; + } + + return (ushort)flags; + } + } +} diff --git a/source/MetadataProcessor.Core/Tables/nanoTypeReferenceTable.cs b/source/MetadataProcessor.Core/Tables/nanoTypeReferenceTable.cs new file mode 100644 index 00000000..ad5b8c38 --- /dev/null +++ b/source/MetadataProcessor.Core/Tables/nanoTypeReferenceTable.cs @@ -0,0 +1,110 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using Mono.Cecil; +using System; +using System.Collections.Generic; + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Encapsulates logic for storing external type references list and writing + /// this collected list into target assembly in .NET nanoFramework format. + /// + public sealed class nanoTypeReferenceTable : + nanoReferenceTableBase + { + /// + /// Helper class for comparing two instances of objects + /// using property as unique key for comparison. + /// + private sealed class TypeReferenceEqualityComparer : IEqualityComparer + { + /// + public bool Equals(TypeReference lhs, TypeReference rhs) + { + return string.Equals(lhs.FullName, rhs.FullName, StringComparison.Ordinal); + } + + /// + public int GetHashCode(TypeReference item) + { + return item.FullName.GetHashCode(); + } + } + + /// + /// Creates new instance of object. + /// + /// Type references list in Mono.Cecil format. + /// + /// Assembly tables context - contains all tables used for building target assembly. + /// + public nanoTypeReferenceTable( + IEnumerable items, + nanoTablesContext context) + : base(items, new TypeReferenceEqualityComparer(), context) + { + } + + /// + /// Gets type reference identifier (if type is provided and this type is defined in target assembly). + /// + /// + /// For null value passed in returns 0xFFFF value. + /// + /// Type definition in Mono.Cecil format. + /// Type reference identifier for filling. + /// Returns true if item found, otherwise returns false. + public bool TryGetTypeReferenceId( + TypeReference typeReference, + out ushort referenceId) + { + if (typeReference == null) // This case is possible for encoding 'nested inside' case + { + referenceId = 0xFFFF; + return true; + } + + return TryGetIdByValue(typeReference, out referenceId); + } + + /// + protected override void WriteSingleItem( + nanoBinaryWriter writer, + TypeReference item) + { + WriteStringReference(writer, item.Name); + WriteStringReference(writer, item.Namespace); + + writer.WriteUInt16(GetScope(item)); // scope - TBL_AssemblyRef | TBL_TypeRef // 0x8000 + writer.WriteUInt16(0); // padding + } + + /// + protected override void AllocateSingleItemStrings( + TypeReference item) + { + GetOrCreateStringId(item.Namespace); + GetOrCreateStringId(item.Name); + } + + private ushort GetScope( + TypeReference typeReference) + { + if (typeReference.DeclaringType == null) + { + return _context.AssemblyReferenceTable.GetReferenceId(typeReference.Scope as AssemblyNameReference); + } + else + { + ushort referenceId; + _context.TypeReferencesTable.TryGetTypeReferenceId(typeReference.DeclaringType, out referenceId); + return (ushort)(0x8000 | referenceId); + } + } + } +} diff --git a/source/MetadataProcessor.Core/Tables/nanoTypeSpecificationsTable.cs b/source/MetadataProcessor.Core/Tables/nanoTypeSpecificationsTable.cs new file mode 100644 index 00000000..4afce906 --- /dev/null +++ b/source/MetadataProcessor.Core/Tables/nanoTypeSpecificationsTable.cs @@ -0,0 +1,113 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using Mono.Cecil; +using System; +using System.Collections.Generic; +using System.Linq; + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Encapsulates logic for storing type sprcifications list and writing this + /// list into target assembly in .NET nanoFramework format. + /// + public sealed class nanoTypeSpecificationsTable : InanoTable + { + /// + /// Helper class for comparing two instances of objects + /// using property as unique key for comparison. + /// + private sealed class TypeReferenceComparer : IEqualityComparer + { + /// + public bool Equals(TypeReference lhs, TypeReference rhs) + { + return string.Equals(lhs.FullName, rhs.FullName, StringComparison.Ordinal); + } + + /// + public int GetHashCode(TypeReference that) + { + return that.FullName.GetHashCode(); + } + } + + /// + /// Maps for each unique type specification and related identifier. + /// + private readonly IDictionary _idByTypeSpecifications = + new Dictionary(new TypeReferenceComparer()); + + /// + /// Assembly tables context - contains all tables used for building target assembly. + /// + private readonly nanoTablesContext _context; + + /// + /// Last available type specifier identificator. + /// + private ushort _lastAvailableId; + + /// + /// Creates new instance of object. + /// + /// + /// Assembly tables context - contains all tables used for building target assembly. + /// + public nanoTypeSpecificationsTable( + nanoTablesContext context) + { + _context = context; + } + + /// + /// Gets existing or creates new type specification reference identifier. + /// + /// Type reference value for obtaining identifier. + /// Existing identifier if specification already in table or new one. + public ushort GetOrCreateTypeSpecificationId( + TypeReference typeReference) + { + ushort referenceId; + if (!_idByTypeSpecifications.TryGetValue(typeReference, out referenceId)) + { + _idByTypeSpecifications.Add(typeReference, _lastAvailableId); + + referenceId = _lastAvailableId; + ++_lastAvailableId; + } + + return referenceId; + } + + /// + /// Gets type specification identifier (if it already added into type specifications list). + /// + /// Type reference in Mono.Cecil format. + /// Type reference identifier for filling. + /// Returns true if item found, otherwise returns false. + public bool TryGetTypeReferenceId( + TypeReference typeReference, + out ushort referenceId) + { + return _idByTypeSpecifications.TryGetValue(typeReference, out referenceId); + } + + /// + public void Write( + nanoBinaryWriter writer) + { + foreach (var item in _idByTypeSpecifications + .OrderBy(item => item.Value) + .Select(item => item.Key)) + { + writer.WriteUInt16(_context.SignaturesTable.GetOrCreateSignatureId(item)); + writer.WriteUInt16(0x0000); // padding + } + } + } +} diff --git a/source/MetadataProcessor.Core/Utility/Crc32.cs b/source/MetadataProcessor.Core/Utility/Crc32.cs new file mode 100644 index 00000000..32ad2eff --- /dev/null +++ b/source/MetadataProcessor.Core/Utility/Crc32.cs @@ -0,0 +1,66 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using System.Linq; + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Helper class for calculating CRC32 value according IEEE 802 standard (ZModem protocol). + /// + internal static class Crc32 + { + // + // CRC 32 table for use under ZModem protocol, IEEE 802 + // G(x) = x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 + // + private static readonly uint[] _crcTable = + { + 0x00000000, 0x04C11DB7, 0x09823B6E, 0x0D4326D9, 0x130476DC, 0x17C56B6B, 0x1A864DB2, 0x1E475005, + 0x2608EDB8, 0x22C9F00F, 0x2F8AD6D6, 0x2B4BCB61, 0x350C9B64, 0x31CD86D3, 0x3C8EA00A, 0x384FBDBD, + 0x4C11DB70, 0x48D0C6C7, 0x4593E01E, 0x4152FDA9, 0x5F15ADAC, 0x5BD4B01B, 0x569796C2, 0x52568B75, + 0x6A1936C8, 0x6ED82B7F, 0x639B0DA6, 0x675A1011, 0x791D4014, 0x7DDC5DA3, 0x709F7B7A, 0x745E66CD, + 0x9823B6E0, 0x9CE2AB57, 0x91A18D8E, 0x95609039, 0x8B27C03C, 0x8FE6DD8B, 0x82A5FB52, 0x8664E6E5, + 0xBE2B5B58, 0xBAEA46EF, 0xB7A96036, 0xB3687D81, 0xAD2F2D84, 0xA9EE3033, 0xA4AD16EA, 0xA06C0B5D, + 0xD4326D90, 0xD0F37027, 0xDDB056FE, 0xD9714B49, 0xC7361B4C, 0xC3F706FB, 0xCEB42022, 0xCA753D95, + 0xF23A8028, 0xF6FB9D9F, 0xFBB8BB46, 0xFF79A6F1, 0xE13EF6F4, 0xE5FFEB43, 0xE8BCCD9A, 0xEC7DD02D, + 0x34867077, 0x30476DC0, 0x3D044B19, 0x39C556AE, 0x278206AB, 0x23431B1C, 0x2E003DC5, 0x2AC12072, + 0x128E9DCF, 0x164F8078, 0x1B0CA6A1, 0x1FCDBB16, 0x018AEB13, 0x054BF6A4, 0x0808D07D, 0x0CC9CDCA, + 0x7897AB07, 0x7C56B6B0, 0x71159069, 0x75D48DDE, 0x6B93DDDB, 0x6F52C06C, 0x6211E6B5, 0x66D0FB02, + 0x5E9F46BF, 0x5A5E5B08, 0x571D7DD1, 0x53DC6066, 0x4D9B3063, 0x495A2DD4, 0x44190B0D, 0x40D816BA, + 0xACA5C697, 0xA864DB20, 0xA527FDF9, 0xA1E6E04E, 0xBFA1B04B, 0xBB60ADFC, 0xB6238B25, 0xB2E29692, + 0x8AAD2B2F, 0x8E6C3698, 0x832F1041, 0x87EE0DF6, 0x99A95DF3, 0x9D684044, 0x902B669D, 0x94EA7B2A, + 0xE0B41DE7, 0xE4750050, 0xE9362689, 0xEDF73B3E, 0xF3B06B3B, 0xF771768C, 0xFA325055, 0xFEF34DE2, + 0xC6BCF05F, 0xC27DEDE8, 0xCF3ECB31, 0xCBFFD686, 0xD5B88683, 0xD1799B34, 0xDC3ABDED, 0xD8FBA05A, + 0x690CE0EE, 0x6DCDFD59, 0x608EDB80, 0x644FC637, 0x7A089632, 0x7EC98B85, 0x738AAD5C, 0x774BB0EB, + 0x4F040D56, 0x4BC510E1, 0x46863638, 0x42472B8F, 0x5C007B8A, 0x58C1663D, 0x558240E4, 0x51435D53, + 0x251D3B9E, 0x21DC2629, 0x2C9F00F0, 0x285E1D47, 0x36194D42, 0x32D850F5, 0x3F9B762C, 0x3B5A6B9B, + 0x0315D626, 0x07D4CB91, 0x0A97ED48, 0x0E56F0FF, 0x1011A0FA, 0x14D0BD4D, 0x19939B94, 0x1D528623, + 0xF12F560E, 0xF5EE4BB9, 0xF8AD6D60, 0xFC6C70D7, 0xE22B20D2, 0xE6EA3D65, 0xEBA91BBC, 0xEF68060B, + 0xD727BBB6, 0xD3E6A601, 0xDEA580D8, 0xDA649D6F, 0xC423CD6A, 0xC0E2D0DD, 0xCDA1F604, 0xC960EBB3, + 0xBD3E8D7E, 0xB9FF90C9, 0xB4BCB610, 0xB07DABA7, 0xAE3AFBA2, 0xAAFBE615, 0xA7B8C0CC, 0xA379DD7B, + 0x9B3660C6, 0x9FF77D71, 0x92B45BA8, 0x9675461F, 0x8832161A, 0x8CF30BAD, 0x81B02D74, 0x857130C3, + 0x5D8A9099, 0x594B8D2E, 0x5408ABF7, 0x50C9B640, 0x4E8EE645, 0x4A4FFBF2, 0x470CDD2B, 0x43CDC09C, + 0x7B827D21, 0x7F436096, 0x7200464F, 0x76C15BF8, 0x68860BFD, 0x6C47164A, 0x61043093, 0x65C52D24, + 0x119B4BE9, 0x155A565E, 0x18197087, 0x1CD86D30, 0x029F3D35, 0x065E2082, 0x0B1D065B, 0x0FDC1BEC, + 0x3793A651, 0x3352BBE6, 0x3E119D3F, 0x3AD08088, 0x2497D08D, 0x2056CD3A, 0x2D15EBE3, 0x29D4F654, + 0xC5A92679, 0xC1683BCE, 0xCC2B1D17, 0xC8EA00A0, 0xD6AD50A5, 0xD26C4D12, 0xDF2F6BCB, 0xDBEE767C, + 0xE3A1CBC1, 0xE760D676, 0xEA23F0AF, 0xEEE2ED18, 0xF0A5BD1D, 0xF464A0AA, 0xF9278673, 0xFDE69BC4, + 0x89B8FD09, 0x8D79E0BE, 0x803AC667, 0x84FBDBD0, 0x9ABC8BD5, 0x9E7D9662, 0x933EB0BB, 0x97FFAD0C, + 0xAFB010B1, 0xAB710D06, 0xA6322BDF, 0xA2F33668, 0xBCB4666D, 0xB8757BDA, 0xB5365D03, 0xB1F740B4 + }; + + /// + /// Calculates CRC32 value for passsed byte array using + /// initial value of parameter as base for CRC calculation. + /// + public static uint Compute(byte[] buffer, uint crc = 0) + { + return buffer.Aggregate(crc, + (index, item) => _crcTable[((index >> 24) ^ item) & 0xFF] ^ (index << 8)); + } + } +} \ No newline at end of file diff --git a/source/MetadataProcessor.Core/Utility/LoadHintsAssemblyResolver.cs b/source/MetadataProcessor.Core/Utility/LoadHintsAssemblyResolver.cs new file mode 100644 index 00000000..929412f3 --- /dev/null +++ b/source/MetadataProcessor.Core/Utility/LoadHintsAssemblyResolver.cs @@ -0,0 +1,75 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using Mono.Cecil; +using System; +using System.Collections.Generic; +using System.Reflection; + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Implements special external .NET nanoFramework assemblies resolution logic. + /// MetadataTransformer gets maps with pair assembly name and assebly path in command line, + /// if we unable to load assemlby using default resolver we will try to use this map. + /// + public sealed class LoadHintsAssemblyResolver : BaseAssemblyResolver + { + /// + /// List of 'load hints' - map between assembly name and assembly path. + /// + private readonly IDictionary _loadHints; + + /// + /// Creates new instance of object. + /// + /// Metadata transformer load hints. + public LoadHintsAssemblyResolver( + IDictionary loadHints) + { + _loadHints = loadHints; + } + + /// + public override AssemblyDefinition Resolve(AssemblyNameReference name) + { + try + { + return base.Resolve(name); + } + catch (Exception) + { + string assemblyFileName; + if (_loadHints.TryGetValue(name.Name, out assemblyFileName)) + { + return AssemblyDefinition.ReadAssembly(assemblyFileName); + } + + throw; + } + } + + + /// + public override AssemblyDefinition Resolve(AssemblyNameReference name, ReaderParameters parameters) + { + try + { + return base.Resolve(name, parameters); + } + catch (Exception) + { + string assemblyFileName; + if (_loadHints.TryGetValue(new AssemblyName(name.FullName).Name, out assemblyFileName)) + { + return AssemblyDefinition.ReadAssembly(assemblyFileName); + } + + throw; + } + } + } +} \ No newline at end of file diff --git a/source/MetadataProcessor.Core/Utility/NativeMethodsCrc.cs b/source/MetadataProcessor.Core/Utility/NativeMethodsCrc.cs new file mode 100644 index 00000000..5fa45c43 --- /dev/null +++ b/source/MetadataProcessor.Core/Utility/NativeMethodsCrc.cs @@ -0,0 +1,100 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using Mono.Cecil; +using System; +using System.Collections.Generic; +using System.Globalization; +using System.Text; + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Helper class for calculating native methods CRC value. Really caclulates CRC32 value + /// for native method signatures (not methods itself) and signatures treated as string + /// values, formatted by weird rules incompartible with all rest codebase. + /// + public sealed class NativeMethodsCrc + { + private readonly HashSet _generatedNames = new HashSet(StringComparer.Ordinal); + + private readonly byte[] _null = Encoding.ASCII.GetBytes("NULL"); + + private readonly byte[] _name; + + public NativeMethodsCrc( + AssemblyDefinition assembly) + { + _name = Encoding.ASCII.GetBytes(assembly.Name.Name); + } + + public uint Current { get; private set; } + + public void UpdateCrc(MethodDefinition method) + { + var type = method.DeclaringType; + if ((type.IsClass || type.IsValueType) && + (method.RVA == 0xFFFFFFF && !method.IsAbstract)) + { + Current = Crc32.Compute(_name, Current); + Current = Crc32.Compute(Encoding.ASCII.GetBytes(GetClassName(type)), Current); + Current = Crc32.Compute(Encoding.ASCII.GetBytes(GetMethodName(method)), Current); + } + else + { + Current = Crc32.Compute(_null, Current); + } + } + + private string GetClassName( + TypeDefinition type) + { + return (type != null + ? string.Concat(GetClassName(type.DeclaringType), type.Namespace, type.Name) + .Replace(".", string.Empty) + : string.Empty); + } + + private string GetMethodName( + MethodDefinition method) + { + var name = string.Concat(method.Name, (method.IsStatic ? "___STATIC__" : "___"), + string.Join("__", GetAllParameters(method))); + + var originalName = name.Replace(".", string.Empty); + + var index = 1; + name = originalName; + while (_generatedNames.Add(name)) + { + name = string.Concat(originalName, index.ToString(CultureInfo.InvariantCulture)); + ++index; + } + + return name; + } + + private IEnumerable GetAllParameters( + MethodDefinition method) + { + yield return GetParameterType(method.ReturnType); + + if (method.HasParameters) + { + foreach (var item in method.Parameters) + { + yield return GetParameterType(item.ParameterType); + } + } + } + + private string GetParameterType( + TypeReference parameterType) + { + return parameterType.Name.ToUpper(); + } + } +} diff --git a/source/MetadataProcessor.Core/Utility/nanoBitmapProcessor.cs b/source/MetadataProcessor.Core/Utility/nanoBitmapProcessor.cs new file mode 100644 index 00000000..469309e9 --- /dev/null +++ b/source/MetadataProcessor.Core/Utility/nanoBitmapProcessor.cs @@ -0,0 +1,80 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using System.Drawing; +using System.Drawing.Imaging; + +namespace nanoFramework.Tools.MetadataProcessor +{ + internal sealed class nanoBitmapProcessor + { + private readonly Bitmap _bitmap; + + public nanoBitmapProcessor( + Bitmap bitmap) + { + _bitmap = bitmap; + } + + public void Process( + nanoBinaryWriter writer) + { + writer.WriteUInt32((uint)_bitmap.Width); + writer.WriteUInt32((uint)_bitmap.Height); + + writer.WriteUInt16(0x00); // flags + + var tinyImageFormat = GetTinytImageFormat(_bitmap.RawFormat); + + if (tinyImageFormat != 0) + { + writer.WriteByte(0x01); // bpp + writer.WriteByte(tinyImageFormat); + _bitmap.Save(writer.BaseStream, _bitmap.RawFormat); + } + else + { + writer.WriteByte(0x10); // bpp + writer.WriteByte(tinyImageFormat); + + var rect = new Rectangle(Point.Empty, _bitmap.Size); + using (var convertedBitmap = + _bitmap.Clone(new Rectangle(Point.Empty, _bitmap.Size), + PixelFormat.Format16bppRgb565)) + { + var bitmapData = convertedBitmap.LockBits( + rect, ImageLockMode.ReadOnly, convertedBitmap.PixelFormat); + + var buffer = new short[bitmapData.Stride * convertedBitmap.Height / sizeof(short)]; + System.Runtime.InteropServices.Marshal.Copy( + bitmapData.Scan0, buffer, 0, buffer.Length); + + convertedBitmap.UnlockBits(bitmapData); + foreach (var item in buffer) + { + writer.WriteInt16(item); + } + } + } + } + + private byte GetTinytImageFormat( + ImageFormat rawFormat) + { + if (rawFormat.Equals(ImageFormat.Gif)) + { + return 1; + } + + if (rawFormat.Equals(ImageFormat.Jpeg)) + { + return 2; + } + + return 0; + } + } +} \ No newline at end of file diff --git a/source/MetadataProcessor.Core/Utility/nanoCLR_DataType.cs b/source/MetadataProcessor.Core/Utility/nanoCLR_DataType.cs new file mode 100644 index 00000000..2b3436de --- /dev/null +++ b/source/MetadataProcessor.Core/Utility/nanoCLR_DataType.cs @@ -0,0 +1,40 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +namespace nanoFramework.Tools.MetadataProcessor +{ + internal enum nanoCLR_DataType : byte + { + // these where defined @ enum CLR_DataType + + DATATYPE_VOID, // 0 bytes + + DATATYPE_BOOLEAN, // 1 byte + DATATYPE_I1, // 1 byte + DATATYPE_U1, // 1 byte + + DATATYPE_CHAR, // 2 bytes + DATATYPE_I2, // 2 bytes + DATATYPE_U2, // 2 bytes + + DATATYPE_I4, // 4 bytes + DATATYPE_U4, // 4 bytes + DATATYPE_R4, // 4 bytes + + DATATYPE_I8, // 8 bytes + DATATYPE_U8, // 8 bytes + DATATYPE_R8, // 8 bytes + DATATYPE_DATETIME, // 8 bytes // Shortcut for System.DateTime + DATATYPE_TIMESPAN, // 8 bytes // Shortcut for System.TimeSpan + DATATYPE_STRING, + + DATATYPE_OBJECT, // Shortcut for System.Object + DATATYPE_CLASS, // CLASS + DATATYPE_VALUETYPE, // VALUETYPE + DATATYPE_SZARRAY, // Shortcut for single dimension zero lower bound array SZARRAY + DATATYPE_BYREF, // BYREF + } +} diff --git a/source/MetadataProcessor.Core/Utility/nanoFontProcessor.cs b/source/MetadataProcessor.Core/Utility/nanoFontProcessor.cs new file mode 100644 index 00000000..2d1b16b5 --- /dev/null +++ b/source/MetadataProcessor.Core/Utility/nanoFontProcessor.cs @@ -0,0 +1,130 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using System.IO; + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Encapsulates logic for processing .tinyfont resource data and swap endianness if neede. + /// + internal sealed class nanoFontProcessor + { + /// + /// Indicates additional font information in container (anti-aliasing). + /// + private const ushort FLAG_FONT_EX = 0x0008; + + /// + /// Original binary data for processing. + /// + private readonly byte[] _fontResouce; + + /// + /// Creates new instance of object. + /// + /// Original font binary data for processing. + public nanoFontProcessor( + byte[] fontResouce) + { + _fontResouce = fontResouce; + } + + /// + /// Processes original data and writes processed data into output writer. + /// + /// Endianness-aware binary writer. + public void Process( + nanoBinaryWriter writer) + { + using (var stream = new MemoryStream(_fontResouce, false)) + using (var reader = new BinaryReader(stream)) + { + // CLR_GFX_FontDescription + + { + // CLR_GFX_FontMetrics + + writer.WriteUInt16(reader.ReadUInt16()); // CLR_GFX_FontMetrics.m_height + writer.WriteInt16(reader.ReadInt16()); // CLR_GFX_FontMetrics.m_offset + + writer.WriteInt16(reader.ReadInt16()); // CLR_GFX_FontMetrics.m_ascent + writer.WriteInt16(reader.ReadInt16()); // CLR_GFX_FontMetrics.m_descent + + writer.WriteInt16(reader.ReadInt16()); // CLR_GFX_FontMetrics.m_internalLeading + writer.WriteInt16(reader.ReadInt16()); // CLR_GFX_FontMetrics.m_externalLeading + + writer.WriteInt16(reader.ReadInt16()); // CLR_GFX_FontMetrics.m_aveCharWidth + writer.WriteInt16(reader.ReadInt16()); // CLR_GFX_FontMetrics.m_aveCharWidth + } + + var rangesCount = reader.ReadInt16(); + writer.WriteInt16(rangesCount); // CLR_GFX_FontDescription.m_ranges + var charactersCount = reader.ReadInt16(); + writer.WriteInt16(charactersCount); // CLR_GFX_FontDescription.m_characters + + var flags = reader.ReadInt16(); + writer.WriteInt16(flags); // CLR_GFX_FontDescription.m_flags + writer.WriteInt16(reader.ReadInt16()); // CLR_GFX_FontDescription.m_pad + + // CLR_GFX_BitmapDescription + + var width = reader.ReadUInt32(); + writer.WriteUInt32(width); // CLR_GFX_BitmapDescription.m_width + var height = reader.ReadUInt32(); + writer.WriteUInt32(height); // CLR_GFX_BitmapDescription.m_height + + writer.WriteUInt16(reader.ReadUInt16()); // CLR_GFX_BitmapDescription.m_flags + + var bitsPerPixel = reader.ReadByte(); + writer.WriteByte(bitsPerPixel); // CLR_GFX_BitmapDescription.m_bitsPerPixel + writer.WriteByte(reader.ReadByte()); // CLR_GFX_BitmapDescription.m_type + + for (var i = 0; i <= rangesCount; ++i) // Including sentinel range + { + // CLR_GFX_FontCharacterRange + + writer.WriteUInt32(reader.ReadUInt32()); // CLR_GFX_FontCharacterRange.m_indexOfFirstFontCharacter + + writer.WriteUInt16(reader.ReadUInt16()); // CLR_GFX_FontCharacterRange.m_firstChar + writer.WriteUInt16(reader.ReadUInt16()); // CLR_GFX_FontCharacterRange.m_lastChar + + writer.WriteUInt32(reader.ReadUInt32()); // CLR_GFX_FontCharacterRange.m_rangeOffset + } + + for (var i = 0; i <= charactersCount; ++i) // Including sentinel character + { + // CLR_GFX_FontCharacter + + writer.WriteUInt16(reader.ReadUInt16()); // CLR_GFX_FontCharacter.m_offset + + writer.WriteByte(reader.ReadByte()); // CLR_GFX_FontCharacter.m_marginLeft + writer.WriteByte(reader.ReadByte()); // CLR_GFX_FontCharacter.m_marginRight + } + + if (bitsPerPixel == 0) + { + bitsPerPixel = 16; // Native value, rest calculations are same + } + var totalSizeInWords = ((width * bitsPerPixel + 31) / 32) * height; + for (var i = 0; i < totalSizeInWords; ++i) + { + writer.WriteUInt32(reader.ReadUInt32()); + } + + if ((flags & FLAG_FONT_EX) == FLAG_FONT_EX) + { + // TODO: implement it according original idea if needed + } + + while (stream.Position < stream.Length) + { + writer.WriteByte(reader.ReadByte()); + } + } + } + } +} diff --git a/source/MetadataProcessor.Core/Utility/nanoPdbxFileWriter.cs b/source/MetadataProcessor.Core/Utility/nanoPdbxFileWriter.cs new file mode 100644 index 00000000..03d0726c --- /dev/null +++ b/source/MetadataProcessor.Core/Utility/nanoPdbxFileWriter.cs @@ -0,0 +1,143 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using Mono.Cecil; +using System; +using System.Collections.Generic; +using System.Globalization; +using System.Linq; +using System.Xml; + +namespace nanoFramework.Tools.MetadataProcessor +{ + internal sealed class nanoPdbxFileWriter + { + private readonly nanoTablesContext _context; + + public nanoPdbxFileWriter( + nanoTablesContext context) + { + _context = context; + } + + public void Write( + XmlWriter writer) + { + writer.WriteStartElement("PdbxFile"); + writer.WriteStartElement("Assembly"); + + WriteTokensPair(writer, _context.AssemblyDefinition.MetadataToken.ToUInt32(), 0x00000000); + writer.WriteElementString("FileName", _context.AssemblyDefinition.MainModule.Name); + WriteVersionInfo(writer, _context.AssemblyDefinition.Name.Version); + + writer.WriteStartElement("Classes"); + _context.TypeDefinitionTable.ForEachItems((token, item) => WriteClassInfo(writer, token, item)); + + writer.WriteEndDocument(); + } + + private void WriteVersionInfo( + XmlWriter writer, + Version version) + { + writer.WriteStartElement("Version"); + + writer.WriteElementString("Major", version.Major.ToString("D", CultureInfo.InvariantCulture)); + writer.WriteElementString("Minor", version.Minor.ToString("D", CultureInfo.InvariantCulture)); + writer.WriteElementString("Build", version.Build.ToString("D", CultureInfo.InvariantCulture)); + writer.WriteElementString("Revision", version.Revision.ToString("D", CultureInfo.InvariantCulture)); + + writer.WriteEndElement(); + } + + private void WriteClassInfo( + XmlWriter writer, + uint tinyClrItemToken, + TypeDefinition item) + { + writer.WriteStartElement("Class"); + + WriteTokensPair(writer, item.MetadataToken.ToUInt32(), 0x04000000 | tinyClrItemToken); + + writer.WriteStartElement("Methods"); + foreach (var tuple in GetMethodsTokens(item.Methods)) + { + writer.WriteStartElement("Method"); + + WriteTokensPair(writer, tuple.Item1, tuple.Item2); + + if (!tuple.Item3.HasBody) + { + writer.WriteElementString("HasByteCode", "false"); + } + writer.WriteStartElement("ILMap"); + foreach (var offset in _context.TypeDefinitionTable.GetByteCodeOffsets(tuple.Item1)) + { + writer.WriteStartElement("IL"); + + writer.WriteElementString("CLR", "0x" + offset.Item1.ToString("X8", CultureInfo.InvariantCulture)); + writer.WriteElementString("TinyCLR", "0x" + offset.Item2.ToString("X8", CultureInfo.InvariantCulture)); + + writer.WriteEndElement(); + } + writer.WriteEndElement(); + + writer.WriteEndElement(); + } + writer.WriteEndElement(); + + writer.WriteStartElement("Fields"); + foreach (var pair in GetFieldsTokens(item.Fields)) + { + writer.WriteStartElement("Field"); + + WriteTokensPair(writer, pair.Item1, pair.Item2); + + writer.WriteEndElement(); + } + writer.WriteEndElement(); + + writer.WriteEndElement(); + } + + private IEnumerable> GetMethodsTokens( + IEnumerable methods) + { + foreach (var method in methods) + { + ushort fieldToken; + _context.MethodDefinitionTable.TryGetMethodReferenceId(method, out fieldToken); + yield return new Tuple( + method.MetadataToken.ToUInt32(), 0x06000000 | (uint)fieldToken, method); + } + } + + private IEnumerable> GetFieldsTokens( + IEnumerable fields) + { + foreach (var field in fields.Where(item => !item.HasConstant)) + { + ushort fieldToken; + _context.FieldsTable.TryGetFieldReferenceId(field, false, out fieldToken); + yield return new Tuple( + field.MetadataToken.ToUInt32(), 0x05000000 | (uint)fieldToken); + } + } + + private void WriteTokensPair( + XmlWriter writer, + uint clrToken, + uint tinyClrToken) + { + writer.WriteStartElement("Token"); + + writer.WriteElementString("CLR", "0x" + clrToken.ToString("X8", CultureInfo.InvariantCulture)); + writer.WriteElementString("TinyCLR", "0x" + tinyClrToken.ToString("X8", CultureInfo.InvariantCulture)); + + writer.WriteEndElement(); + } + } +} diff --git a/source/MetadataProcessor.Core/Utility/nanoSerializationType.cs b/source/MetadataProcessor.Core/Utility/nanoSerializationType.cs new file mode 100644 index 00000000..3dd86289 --- /dev/null +++ b/source/MetadataProcessor.Core/Utility/nanoSerializationType.cs @@ -0,0 +1,33 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// This list contains type codes used for serializing attributes signatures + /// + internal enum nanoSerializationType : byte + { + // these where defined @ typedef enum CorElementType + + ELEMENT_TYPE_BOOLEAN = 0x2, + ELEMENT_TYPE_CHAR = 0x3, + ELEMENT_TYPE_I1 = 0x4, + ELEMENT_TYPE_U1 = 0x5, + ELEMENT_TYPE_I2 = 0x6, + ELEMENT_TYPE_U2 = 0x7, + ELEMENT_TYPE_I4 = 0x8, + ELEMENT_TYPE_U4 = 0x9, + ELEMENT_TYPE_I8 = 0xa, + ELEMENT_TYPE_U8 = 0xb, + ELEMENT_TYPE_R4 = 0xc, + ELEMENT_TYPE_R8 = 0xd, + ELEMENT_TYPE_STRING = 0xe, + + SERIALIZATION_TYPE_FIELD = 0x53, + SERIALIZATION_TYPE_PROPERTY = 0x54, + } +} diff --git a/source/MetadataProcessor.Core/Utility/nanoStringsConstants.cs b/source/MetadataProcessor.Core/Utility/nanoStringsConstants.cs new file mode 100644 index 00000000..eb03ed55 --- /dev/null +++ b/source/MetadataProcessor.Core/Utility/nanoStringsConstants.cs @@ -0,0 +1,898 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using System; +using System.Collections.Generic; +using System.Linq; + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Helper class for storing list of 'predefined' string constants which encoded in + /// .NET nanoFramework assembly metadata using special notation (highest possible values). + /// + internal static class nanoStringsConstants + { + /// + /// Gets string reference identifier for passed string from constants table. + /// + /// String value for lookup. + /// String reference identifier. + /// Returns true if string found in constants table, false otherwise. + public static bool TryGetStringIndex( + string value, + out ushort index) + { + return _idsByStrings.TryGetValue(value, out index); + } + + private static readonly IDictionary _idsByStrings = new[] + { + /* 0000 */ ".cctor", + /* 0001 */ ".ctor", + /* 0002 */ "Abort", + /* 0003 */ "Abs", + /* 0004 */ "AccessedThroughPropertyAttribute", + /* 0005 */ "Acos", + /* 0006 */ "Add", + /* 0007 */ "AddDays", + /* 0008 */ "AddHours", + /* 0009 */ "AddMilliseconds", + /* 000A */ "AddMinutes", + /* 000B */ "AddSeconds", + /* 000C */ "AddTicks", + /* 000D */ "AnyPendingFinalizers", + /* 000E */ "AppDomain", + /* 000F */ "AppDomainUnloadedException", + /* 0010 */ "Append", + /* 0011 */ "AppendHelper", + /* 0012 */ "AppendLine", + /* 0013 */ "AppendTrailingZeros", + /* 0014 */ "ApplicationException", + /* 0015 */ "ArgumentException", + /* 0016 */ "ArgumentNullException", + /* 0017 */ "ArgumentOutOfRangeException", + /* 0018 */ "Arguments", + /* 0019 */ "Array", + /* 001A */ "ArrayList", + /* 001B */ "ArraySize", + /* 001C */ "Asin", + /* 001D */ "Assembly", + /* 001E */ "AssemblyInfo", + /* 001F */ "AssemblyMemoryInfo", + /* 0020 */ "AssemblyName", + /* 0021 */ "AssemblyNameFlags", + /* 0022 */ "AssemblyRef", + /* 0023 */ "AssemblyRefElements", + /* 0024 */ "Assert", + /* 0025 */ "AsyncCallback", + /* 0026 */ "Atan", + /* 0027 */ "Atan2", + /* 0028 */ "Attribute", + /* 0029 */ "Attributes", + /* 002A */ "AttributesElements", + /* 002B */ "AutoResetEvent", + /* 002C */ "Backlight", + /* 002D */ "BaseEvent", + /* 002E */ "BeginInvoke", + /* 002F */ "Bias", + /* 0030 */ "BinarySearch", + /* 0031 */ "Binder", + /* 0032 */ "BindingFlags", + /* 0033 */ "BitConverter", + /* 0034 */ "BitPacked", + /* 0035 */ "Boolean", + /* 0036 */ "Break", + /* 0037 */ "Byte", + /* 0038 */ "ByteCode", + /* 0039 */ "Ceiling", + /* 003A */ "Change", + /* 003B */ "Char", + /* 003C */ "Check", + /* 003D */ "Clear", + /* 003E */ "Clone", + /* 003F */ "Close", + /* 0040 */ "Combine", + /* 0041 */ "CombineArrays", + /* 0042 */ "Compare", + /* 0043 */ "CompareExchange", + /* 0044 */ "CompareTo", + /* 0045 */ "ComputeCRC", + /* 0046 */ "Concat", + /* 0047 */ "ConstraintException", + /* 0048 */ "ConstructorInfo", + /* 0049 */ "ContactHeight", + /* 004A */ "ContactWidth", + /* 004B */ "Contains", + /* 004C */ "Convert", + /* 004D */ "Copy", + /* 004E */ "CopyTo", + /* 004F */ "CopyToCollection", + /* 0050 */ "Cos", + /* 0051 */ "Cosh", + /* 0052 */ "CreateDomain", + /* 0053 */ "CreateInstance", + /* 0054 */ "CreateInstanceAndUnwrap", + /* 0055 */ "CultureInfo", + /* 0056 */ "CultureTypes", + /* 0057 */ "CurrentSystemTimeZone", + /* 0058 */ "DateTime", + /* 0059 */ "DateTimeFormat", + /* 005A */ "DateTimeFormatInfo", + /* 005B */ "DateTimeKind", + /* 005C */ "Day", + /* 005D */ "DayOfWeek", + /* 005E */ "DaylightBias", + /* 005F */ "DaylightDate", + /* 0060 */ "DaylightName", + /* 0061 */ "DaylightTime", + /* 0062 */ "DaysInMonth", + /* 0063 */ "Debug", + /* 0064 */ "DebuggableAttribute", + /* 0065 */ "Debugger", + /* 0066 */ "DebuggingModes", + /* 0067 */ "Decoder", + /* 0068 */ "Decrement", + /* 0069 */ "Delegate", + /* 006A */ "Dequeue", + /* 006B */ "Deserialize", + /* 006C */ "DictionaryEntry", + /* 006D */ "Dispose", + /* 006E */ "Double", + /* 006F */ "DoubleToInt64Bits", + /* 0070 */ "Duration", + /* 0071 */ "EditorBrowsableState", + /* 0072 */ "Empty", + /* 0073 */ "EnableGCMessages", + /* 0074 */ "Encoding", + /* 0075 */ "EndInvoke", + /* 0076 */ "EndPoint", + /* 0077 */ "Enqueue", + /* 0078 */ "EnsureCapacity", + /* 0079 */ "EnsureStringArrayResource", + /* 007A */ "EnsureStringResource", + /* 007B */ "Enter", + /* 007C */ "Entry", + /* 007D */ "EntryForKey", + /* 007E */ "Enum", + /* 007F */ "EnumeratorType", + /* 0080 */ "Equals", + /* 0081 */ "EventArgs", + /* 0082 */ "EventCategory", + /* 0083 */ "EventData", + /* 0084 */ "EventMessage", + /* 0085 */ "Exception", + /* 0086 */ "Exchange", + /* 0087 */ "ExecutionConstraint", + /* 0088 */ "Exit", + /* 0089 */ "Exp", + /* 008A */ "ExpandByABlock", + /* 008B */ "ExtendedTimer", + /* 008C */ "ExtendedWeakReference", + /* 008D */ "ExtensionAttribute", + /* 008E */ "ExtractRangeFromArray", + /* 008F */ "ExtractValueFromArray", + /* 0090 */ "FalseString", + /* 0091 */ "FieldDef", + /* 0092 */ "FieldDefElements", + /* 0093 */ "FieldInfo", + /* 0094 */ "FieldRef", + /* 0095 */ "FieldRefElements", + /* 0096 */ "Finalize", + /* 0097 */ "FindChunkForIndex", + /* 0098 */ "FindResource", + /* 0099 */ "Flags", + /* 009A */ "Floor", + /* 009B */ "Flush", + /* 009C */ "FlushAll", + /* 009D */ "Format", + /* 009E */ "FormatCustomized", + /* 009F */ "FormatDigits", + /* 00A0 */ "FormatNative", + /* 00A1 */ "FromBase64CharArray", + /* 00A2 */ "FromBase64String", + /* 00A3 */ "FromTicks", + /* 00A4 */ "GC", + /* 00A5 */ "GenericEvent", + /* 00A6 */ "Gesture", + /* 00A7 */ "GetAssemblies", + /* 00A8 */ "GetAssembly", + /* 00A9 */ "GetAssemblyFromHash", + /* 00AA */ "GetAssemblyHash", + /* 00AB */ "GetAssemblyInfo", + /* 00AC */ "GetAssemblyMemoryInfo", + /* 00AD */ "GetBase64EncodedLength", + /* 00AE */ "GetBytes", + /* 00AF */ "GetChars", + /* 00B0 */ "GetConstructor", + /* 00B1 */ "GetCultures", + /* 00B2 */ "GetDaylightChanges", + /* 00B3 */ "GetDecoder", + /* 00B4 */ "GetDelimitedStringResource", + /* 00B5 */ "GetDelimitedStringResources", + /* 00B6 */ "GetDomain", + /* 00B7 */ "GetDoubleNumber", + /* 00B8 */ "GetEffectiveDate", + /* 00B9 */ "GetElementType", + /* 00BA */ "GetEnumerator", + /* 00BB */ "GetExecutingAssembly", + /* 00BC */ "GetExpirationDate", + /* 00BD */ "GetField", + /* 00BE */ "GetFields", + /* 00BF */ "GetFormat", + /* 00C0 */ "GetHashCode", + /* 00C1 */ "GetInterfaces", + /* 00C2 */ "GetMachineTime", + /* 00C3 */ "GetManifestResourceNames", + /* 00C4 */ "GetMessage", + /* 00C5 */ "GetMethod", + /* 00C6 */ "GetMethods", + /* 00C7 */ "GetName", + /* 00C8 */ "GetObject", + /* 00C9 */ "GetObjectChunkFromId", + /* 00CA */ "GetObjectFromId", + /* 00CB */ "GetObjectInternal", + /* 00CC */ "GetObjectValue", + /* 00CD */ "GetParentCultureName", + /* 00CE */ "GetPosition", + /* 00CF */ "GetRawCertData", + /* 00D0 */ "GetRealFormat", + /* 00D1 */ "GetSatelliteAssembly", + /* 00D2 */ "GetString", + /* 00D3 */ "GetSystemVersion", + /* 00D4 */ "GetTimeZoneOffset", + /* 00D5 */ "GetType", + /* 00D6 */ "GetTypeFromHandle", + /* 00D7 */ "GetTypeFromHash", + /* 00D8 */ "GetTypeHash", + /* 00D9 */ "GetTypeInternal", + /* 00DA */ "GetTypes", + /* 00DB */ "GetTypesImplementingInterface", + /* 00DC */ "GetUtcOffset", + /* 00DD */ "GetValue", + /* 00DE */ "GetVersion", + /* 00DF */ "GloballySynchronizedAttribute", + /* 00E0 */ "Guid", + /* 00E1 */ "Hash", + /* 00E2 */ "Hashtable", + /* 00E3 */ "HashtableEnumerator", + /* 00E4 */ "HexToChar", + /* 00E5 */ "Hour", + /* 00E6 */ "IAsyncResult", + /* 00E7 */ "ICloneable", + /* 00E8 */ "ICollection", + /* 00E9 */ "IComparable", + /* 00EA */ "IComparer", + /* 00EB */ "ICustomFormatter", + /* 00EC */ "IDictionary", + /* 00ED */ "IDisposable", + /* 00EE */ "IEEERemainder", + /* 00EF */ "IEnumerable", + /* 00F0 */ "IEnumerator", + /* 00F1 */ "IEqualityComparer", + /* 00F2 */ "IEventListener", + /* 00F3 */ "IEventProcessor", + /* 00F4 */ "IFormatProvider", + /* 00F5 */ "IFormattable", + /* 00F6 */ "IList", + /* 00F7 */ "ILog", + /* 00F8 */ "IOException", + /* 00F9 */ "IOExceptionErrorCode", + /* 00FA */ "IReflect", + /* 00FB */ "Increment", + /* 00FC */ "IndexOf", + /* 00FD */ "IndexOfAny", + /* 00FE */ "IndexOutOfRangeException", + /* 00FF */ "Initialize", + /* 0100 */ "InitializeArray", + /* 0101 */ "InitializeForEventSource", + /* 0102 */ "InitializeHashTable", + /* 0103 */ "Insert", + /* 0104 */ "InsertGroupSeperators", + /* 0105 */ "InsertValueIntoArray", + /* 0106 */ "Install", + /* 0107 */ "Int16", + /* 0108 */ "Int32", + /* 0109 */ "Int64", + /* 010A */ "Int64BitsToDouble", + /* 010B */ "IntPtr", + /* 010C */ "Interlocked", + /* 010D */ "Intern", + /* 010E */ "InvalidCastException", + /* 010F */ "InvalidOperationException", + /* 0110 */ "Invoke", + /* 0111 */ "InvokeMember", + /* 0112 */ "IsDaylightSavingTime", + /* 0113 */ "IsEmulator", + /* 0114 */ "IsInfinity", + /* 0115 */ "IsInstanceOfType", + /* 0116 */ "IsInterned", + /* 0117 */ "IsNaN", + /* 0118 */ "IsNegativeInfinity", + /* 0119 */ "IsPositiveInfinity", + /* 011A */ "IsSubclassOf", + /* 011B */ "IsTransparentProxy", + /* 011C */ "IsTypeLoaded", + /* 011D */ "Join", + /* 011E */ "Key", + /* 011F */ "KeyCollection", + /* 0120 */ "LastIndexOf", + /* 0121 */ "LastIndexOfAny", + /* 0122 */ "Load", + /* 0123 */ "LoadInternal", + /* 0124 */ "Log", + /* 0125 */ "Log10", + /* 0126 */ "MakeRoom", + /* 0127 */ "ManualResetEvent", + /* 0128 */ "MarshalByRefObject", + /* 0129 */ "Math", + /* 012A */ "Max", + /* 012B */ "MaxValue", + /* 012C */ "MemberInfo", + /* 012D */ "MemberTypes", + /* 012E */ "MemberwiseClone", + /* 012F */ "Message", + /* 0130 */ "MetadataSize", + /* 0131 */ "MethodBase", + /* 0132 */ "MethodDef", + /* 0133 */ "MethodDefElements", + /* 0134 */ "MethodInfo", + /* 0135 */ "MethodRef", + /* 0136 */ "MethodRefElements", + /* 0137 */ "Microsoft.SPOT", + /* 0138 */ "Microsoft.SPOT.Hardware", + /* 0139 */ "Microsoft.SPOT.Messaging", + /* 013A */ "Microsoft.SPOT.Touch", + /* 013B */ "Milliseconds", + /* 013C */ "Min", + /* 013D */ "MinValue", + /* 013E */ "Minute", + /* 013F */ "Monitor", + /* 0140 */ "Month", + /* 0141 */ "MoveNext", + /* 0142 */ "MulticastDelegate", + /* 0143 */ "Native_Resources", + /* 0144 */ "Negate", + /* 0145 */ "NewGuid", + /* 0146 */ "Next", + /* 0147 */ "NextBytes", + /* 0148 */ "NextDouble", + /* 0149 */ "NotImplementedException", + /* 014A */ "NotSupportedException", + /* 014B */ "NullReferenceException", + /* 014C */ "Number", + /* 014D */ "NumberFormatInfo", + /* 014E */ "Object", + /* 014F */ "ObjectDisposedException", + /* 0150 */ "OnEvent", + /* 0151 */ "OutOfMemoryException", + /* 0152 */ "Parse", + /* 0153 */ "ParseAssemblyName", + /* 0154 */ "ParseCertificate", + /* 0155 */ "ParseNextChar", + /* 0156 */ "ParseQuoteString", + /* 0157 */ "ParseRepeatPattern", + /* 0158 */ "ParseTypeName", + /* 0159 */ "Peek", + /* 015A */ "Piezo", + /* 015B */ "Pop", + /* 015C */ "PostProcessFloat", + /* 015D */ "PostProcessInteger", + /* 015E */ "Pow", + /* 015F */ "Print", + /* 0160 */ "PriorityLevel", + /* 0161 */ "ProcessEvent", + /* 0162 */ "ProcessorArchitecture", + /* 0163 */ "PropertyInfo", + /* 0164 */ "Push", + /* 0165 */ "PushBackIntoRecoverList", + /* 0166 */ "Queue", + /* 0167 */ "Raise", + /* 0168 */ "RamSize", + /* 0169 */ "Random", + /* 016A */ "RangeBias", + /* 016B */ "ReRegisterForFinalize", + /* 016C */ "Read", + /* 016D */ "ReadByte", + /* 016E */ "Recover", + /* 016F */ "RecoverOrCreate", + /* 0170 */ "ReferenceEquals", + /* 0171 */ "Reflection", + /* 0172 */ "Rehash", + /* 0173 */ "RemotedException", + /* 0174 */ "RemotingServices", + /* 0175 */ "Remove", + /* 0176 */ "RemoveAt", + /* 0177 */ "Replace", + /* 0178 */ "ReplaceAllInChunk", + /* 0179 */ "ReplaceDecimalSeperator", + /* 017A */ "ReplaceInPlaceAtChunk", + /* 017B */ "ReplaceNegativeSign", + /* 017C */ "Reply", + /* 017D */ "ReplyRaw", + /* 017E */ "Reset", + /* 017F */ "ResourceManager", + /* 0180 */ "ResourceUtility", + /* 0181 */ "Resources", + /* 0182 */ "ResourcesData", + /* 0183 */ "ResourcesElements", + /* 0184 */ "ResourcesFiles", + /* 0185 */ "ResourcesFilesElements", + /* 0186 */ "Resume", + /* 0187 */ "RomSize", + /* 0188 */ "Round", + /* 0189 */ "RunClassConstructor", + /* 018A */ "RuntimeArgumentHandle", + /* 018B */ "RuntimeConstructorInfo", + /* 018C */ "RuntimeFieldHandle", + /* 018D */ "RuntimeFieldInfo", + /* 018E */ "RuntimeHelpers", + /* 018F */ "RuntimeMethodHandle", + /* 0190 */ "RuntimeMethodInfo", + /* 0191 */ "RuntimeType", + /* 0192 */ "RuntimeTypeHandle", + /* 0193 */ "SByte", + /* 0194 */ "SZArrayEnumerator", + /* 0195 */ "Scale", + /* 0196 */ "Second", + /* 0197 */ "Seek", + /* 0198 */ "SeekOrigin", + /* 0199 */ "SendMessage", + /* 019A */ "SendMessageRaw", + /* 019B */ "SerializationFlags", + /* 019C */ "SerializationHintsAttribute", + /* 019D */ "Serialize", + /* 019E */ "Set", + /* 019F */ "SetCapacity", + /* 01A0 */ "SetCurrentUICulture", + /* 01A1 */ "SetLength", + /* 01A2 */ "SetLocalTime", + /* 01A3 */ "SetValue", + /* 01A4 */ "Sign", + /* 01A5 */ "Signatures", + /* 01A6 */ "Sin", + /* 01A7 */ "Single", + /* 01A8 */ "Sinh", + /* 01A9 */ "Sleep", + /* 01AA */ "Source", + /* 01AB */ "SourceID", + /* 01AC */ "SpecifyKind", + /* 01AD */ "Split", + /* 01AE */ "Sqrt", + /* 01AF */ "Stack", + /* 01B0 */ "StandardBias", + /* 01B1 */ "StandardDate", + /* 01B2 */ "StandardName", + /* 01B3 */ "Start", + /* 01B4 */ "StartsWith", + /* 01B5 */ "StaticFields", + /* 01B6 */ "Stream", + /* 01B7 */ "String", + /* 01B8 */ "StringBuilder", + /* 01B9 */ "StringResources", + /* 01BA */ "Strings", + /* 01BB */ "Substring", + /* 01BC */ "Subtract", + /* 01BD */ "SuppressFinalize", + /* 01BE */ "Suspend", + /* 01BF */ "System", + /* 01C0 */ "System.Collections", + /* 01C1 */ "System.Collections.ICollection.get_Count", + /* 01C2 */ "System.Collections.IList.Add", + /* 01C3 */ "System.Collections.IList.Clear", + /* 01C4 */ "System.Collections.IList.Contains", + /* 01C5 */ "System.Collections.IList.IndexOf", + /* 01C6 */ "System.Collections.IList.Insert", + /* 01C7 */ "System.Collections.IList.Remove", + /* 01C8 */ "System.Collections.IList.RemoveAt", + /* 01C9 */ "System.Collections.IList.get_Item", + /* 01CA */ "System.Collections.IList.set_Item", + /* 01CB */ "System.ComponentModel", + /* 01CC */ "System.Diagnostics", + /* 01CD */ "System.Globalization", + /* 01CE */ "System.Globalization.Resources", + /* 01CF */ "System.IO", + /* 01D0 */ "System.Reflection", + /* 01D1 */ "System.Resources", + /* 01D2 */ "System.Runtime.CompilerServices", + /* 01D3 */ "System.Runtime.Remoting", + /* 01D4 */ "System.Runtime.Versioning", + /* 01D5 */ "System.Security.Cryptography.X509Certificates", + /* 01D6 */ "System.Text", + /* 01D7 */ "System.Threading", + /* 01D8 */ "SystemException", + /* 01D9 */ "SystemID", + /* 01DA */ "SystemInfo", + /* 01DB */ "SystemTime", + /* 01DC */ "Tan", + /* 01DD */ "Tanh", + /* 01DE */ "Target", + /* 01DF */ "TargetFrameworkAttribute", + /* 01E0 */ "Thread", + /* 01E1 */ "ThreadAbortException", + /* 01E2 */ "ThreadPriority", + /* 01E3 */ "ThreadStart", + /* 01E4 */ "ThreadState", + /* 01E5 */ "Time", + /* 01E6 */ "TimeEvents", + /* 01E7 */ "TimeSpan", + /* 01E8 */ "TimeStamp", + /* 01E9 */ "TimeZone", + /* 01EA */ "TimeZoneId", + /* 01EB */ "TimeZoneInformation", + /* 01EC */ "Timer", + /* 01ED */ "TimerCallback", + /* 01EE */ "Timestamp", + /* 01EF */ "ToArray", + /* 01F0 */ "ToBase64String", + /* 01F1 */ "ToBoolean", + /* 01F2 */ "ToByte", + /* 01F3 */ "ToByteArray", + /* 01F4 */ "ToChar", + /* 01F5 */ "ToCharArray", + /* 01F6 */ "ToDouble", + /* 01F7 */ "ToInt16", + /* 01F8 */ "ToInt32", + /* 01F9 */ "ToInt64", + /* 01FA */ "ToLocalTime", + /* 01FB */ "ToLower", + /* 01FC */ "ToSByte", + /* 01FD */ "ToSingle", + /* 01FE */ "ToString", + /* 01FF */ "ToUInt16", + /* 0200 */ "ToUInt32", + /* 0201 */ "ToUInt64", + /* 0202 */ "ToUniversalTime", + /* 0203 */ "ToUpper", + /* 0204 */ "TouchEvent", + /* 0205 */ "TouchGesture", + /* 0206 */ "TouchGestureEventArgs", + /* 0207 */ "TouchGestureEventHandler", + /* 0208 */ "TouchInput", + /* 0209 */ "TouchInputFlags", + /* 020A */ "TouchMessages", + /* 020B */ "TouchScreenEventArgs", + /* 020C */ "TouchScreenEventHandler", + /* 020D */ "Touches", + /* 020E */ "Trace", + /* 020F */ "Trim", + /* 0210 */ "TrimEnd", + /* 0211 */ "TrimStart", + /* 0212 */ "TrueString", + /* 0213 */ "Truncate", + /* 0214 */ "TryParse", + /* 0215 */ "TrySZIndexOf", + /* 0216 */ "Type", + /* 0217 */ "TypeCode", + /* 0218 */ "TypeDef", + /* 0219 */ "TypeDefElements", + /* 021A */ "TypeRef", + /* 021B */ "TypeRefElements", + /* 021C */ "TypeSpec", + /* 021D */ "TypeSpecElements", + /* 021E */ "UInt16", + /* 021F */ "UInt32", + /* 0220 */ "UInt64", + /* 0221 */ "UTF8Decoder", + /* 0222 */ "UTF8Encoding", + /* 0223 */ "UnknownTypeException", + /* 0224 */ "Unload", + /* 0225 */ "Utility", + /* 0226 */ "ValidateFormat", + /* 0227 */ "Value", + /* 0228 */ "ValueCollection", + /* 0229 */ "ValueType", + /* 022A */ "Version", + /* 022B */ "Void", + /* 022C */ "WaitAll", + /* 022D */ "WaitAny", + /* 022E */ "WaitForPendingFinalizers", + /* 022F */ "WaitHandle", + /* 0230 */ "WaitMultiple", + /* 0231 */ "WaitOne", + /* 0232 */ "WeakDelegate", + /* 0233 */ "WeakReference", + /* 0234 */ "Write", + /* 0235 */ "WriteByte", + /* 0236 */ "X", + /* 0237 */ "X509Certificate", + /* 0238 */ "Y", + /* 0239 */ "Year", + /* 023A */ "Zero", + /* 023B */ "_Build", + /* 023C */ "_Major", + /* 023D */ "_Minor", + /* 023E */ "_Revision", + /* 023F */ "_array", + /* 0240 */ "_arrayLength", + /* 0241 */ "_assembly", + /* 0242 */ "_buckets", + /* 0243 */ "_count", + /* 0244 */ "_endIndex", + /* 0245 */ "_frameworkDisplayName", + /* 0246 */ "_frameworkName", + /* 0247 */ "_growthFactor", + /* 0248 */ "_head", + /* 0249 */ "_index", + /* 024A */ "_items", + /* 024B */ "_loadFactor", + /* 024C */ "_maxLoadFactor", + /* 024D */ "_message", + /* 024E */ "_numberOfBuckets", + /* 024F */ "_random", + /* 0250 */ "_size", + /* 0251 */ "_startIndex", + /* 0252 */ "_tail", + /* 0253 */ "abbreviatedDayNames", + /* 0254 */ "abbreviatedMonthNames", + /* 0255 */ "amDesignator", + /* 0256 */ "dateSeparator", + /* 0257 */ "dateTimeInfo", + /* 0258 */ "dayNames", + /* 0259 */ "fullDateTimePattern", + /* 025A */ "generalLongTimePattern", + /* 025B */ "generalShortTimePattern", + /* 025C */ "get_AMDesignator", + /* 025D */ "get_AbbreviatedDayNames", + /* 025E */ "get_AbbreviatedMonthNames", + /* 025F */ "get_Angle", + /* 0260 */ "get_Assembly", + /* 0261 */ "get_AssemblyQualifiedName", + /* 0262 */ "get_BaseType", + /* 0263 */ "get_Build", + /* 0264 */ "get_CanRead", + /* 0265 */ "get_CanSeek", + /* 0266 */ "get_CanTimeout", + /* 0267 */ "get_CanWrite", + /* 0268 */ "get_Capacity", + /* 0269 */ "get_Chars", + /* 026A */ "get_Count", + /* 026B */ "get_Current", + /* 026C */ "get_CurrentDomain", + /* 026D */ "get_CurrentInfo", + /* 026E */ "get_CurrentThread", + /* 026F */ "get_CurrentTimeZone", + /* 0270 */ "get_CurrentUICulture", + /* 0271 */ "get_CurrentUICultureInternal", + /* 0272 */ "get_Date", + /* 0273 */ "get_DateSeparator", + /* 0274 */ "get_DateTimeFormat", + /* 0275 */ "get_Day", + /* 0276 */ "get_DayNames", + /* 0277 */ "get_DayOfWeek", + /* 0278 */ "get_DayOfYear", + /* 0279 */ "get_DaylightName", + /* 027A */ "get_Days", + /* 027B */ "get_DeclaringType", + /* 027C */ "get_Delta", + /* 027D */ "get_End", + /* 027E */ "get_ErrorCode", + /* 027F */ "get_FieldType", + /* 0280 */ "get_Flags", + /* 0281 */ "get_FrameworkDisplayName", + /* 0282 */ "get_FrameworkName", + /* 0283 */ "get_FriendlyName", + /* 0284 */ "get_FullDateTimePattern", + /* 0285 */ "get_FullName", + /* 0286 */ "get_GeneralLongTimePattern", + /* 0287 */ "get_GeneralShortTimePattern", + /* 0288 */ "get_GrowthFactor", + /* 0289 */ "get_Hour", + /* 028A */ "get_Hours", + /* 028B */ "get_Id", + /* 028C */ "get_InnerException", + /* 028D */ "get_IsAbstract", + /* 028E */ "get_IsAlive", + /* 028F */ "get_IsArray", + /* 0290 */ "get_IsAttached", + /* 0291 */ "get_IsBigEndian", + /* 0292 */ "get_IsClass", + /* 0293 */ "get_IsEnum", + /* 0294 */ "get_IsFinal", + /* 0295 */ "get_IsFixedSize", + /* 0296 */ "get_IsInterface", + /* 0297 */ "get_IsLittleEndian", + /* 0298 */ "get_IsNotPublic", + /* 0299 */ "get_IsPublic", + /* 029A */ "get_IsReadOnly", + /* 029B */ "get_IsSerializable", + /* 029C */ "get_IsStatic", + /* 029D */ "get_IsSynchronized", + /* 029E */ "get_IsValid", + /* 029F */ "get_IsValueType", + /* 02A0 */ "get_IsVirtual", + /* 02A1 */ "get_Issuer", + /* 02A2 */ "get_Item", + /* 02A3 */ "get_Keys", + /* 02A4 */ "get_Kind", + /* 02A5 */ "get_LastExpiration", + /* 02A6 */ "get_Length", + /* 02A7 */ "get_LongDatePattern", + /* 02A8 */ "get_LongTimePattern", + /* 02A9 */ "get_Major", + /* 02AA */ "get_ManagedThreadId", + /* 02AB */ "get_MaxCapacity", + /* 02AC */ "get_MaxLoadFactor", + /* 02AD */ "get_MemberType", + /* 02AE */ "get_Message", + /* 02AF */ "get_Method", + /* 02B0 */ "get_Millisecond", + /* 02B1 */ "get_Milliseconds", + /* 02B2 */ "get_Minor", + /* 02B3 */ "get_Minute", + /* 02B4 */ "get_Minutes", + /* 02B5 */ "get_Model", + /* 02B6 */ "get_Month", + /* 02B7 */ "get_MonthDayPattern", + /* 02B8 */ "get_MonthNames", + /* 02B9 */ "get_Name", + /* 02BA */ "get_NegativeSign", + /* 02BB */ "get_Now", + /* 02BC */ "get_NumberDecimalSeparator", + /* 02BD */ "get_NumberFormat", + /* 02BE */ "get_NumberGroupSeparator", + /* 02BF */ "get_NumberGroupSizes", + /* 02C0 */ "get_OEM", + /* 02C1 */ "get_OEMString", + /* 02C2 */ "get_OffsetToStringData", + /* 02C3 */ "get_PMDesignator", + /* 02C4 */ "get_ParamName", + /* 02C5 */ "get_Parent", + /* 02C6 */ "get_Payload", + /* 02C7 */ "get_PayloadRaw", + /* 02C8 */ "get_Position", + /* 02C9 */ "get_PositiveSign", + /* 02CA */ "get_Priority", + /* 02CB */ "get_PropertyName", + /* 02CC */ "get_PropertyType", + /* 02CD */ "get_RFC1123Pattern", + /* 02CE */ "get_ReadTimeout", + /* 02CF */ "get_ResourceManager", + /* 02D0 */ "get_ReturnType", + /* 02D1 */ "get_Revision", + /* 02D2 */ "get_SKU", + /* 02D3 */ "get_Second", + /* 02D4 */ "get_Seconds", + /* 02D5 */ "get_Selector", + /* 02D6 */ "get_ShortDatePattern", + /* 02D7 */ "get_ShortTimePattern", + /* 02D8 */ "get_SortableDateTimePattern", + /* 02D9 */ "get_StackTrace", + /* 02DA */ "get_StandardName", + /* 02DB */ "get_Start", + /* 02DC */ "get_Subject", + /* 02DD */ "get_SyncRoot", + /* 02DE */ "get_Target", + /* 02DF */ "get_ThreadState", + /* 02E0 */ "get_Ticks", + /* 02E1 */ "get_TimeOfDay", + /* 02E2 */ "get_TimeSeparator", + /* 02E3 */ "get_Today", + /* 02E4 */ "get_UTF8", + /* 02E5 */ "get_UniversalSortableDateTimePattern", + /* 02E6 */ "get_UseRFC4648Encoding", + /* 02E7 */ "get_UtcNow", + /* 02E8 */ "get_Values", + /* 02E9 */ "get_Version", + /* 02EA */ "get_WriteTimeout", + /* 02EB */ "get_Year", + /* 02EC */ "get_YearMonthPattern", + /* 02ED */ "ht", + /* 02EE */ "index", + /* 02EF */ "key", + /* 02F0 */ "longDatePattern", + /* 02F1 */ "longTimePattern", + /* 02F2 */ "m_AppDomain", + /* 02F3 */ "m_ChunkChars", + /* 02F4 */ "m_ChunkLength", + /* 02F5 */ "m_ChunkOffset", + /* 02F6 */ "m_ChunkPrevious", + /* 02F7 */ "m_Delegate", + /* 02F8 */ "m_HResult", + /* 02F9 */ "m_Id", + /* 02FA */ "m_MaxCapacity", + /* 02FB */ "m_Priority", + /* 02FC */ "m_Thread", + /* 02FD */ "m_appDomain", + /* 02FE */ "m_assembly", + /* 02FF */ "m_baseAssembly", + /* 0300 */ "m_baseName", + /* 0301 */ "m_callback", + /* 0302 */ "m_certificate", + /* 0303 */ "m_cultureInfo", + /* 0304 */ "m_cultureName", + /* 0305 */ "m_data", + /* 0306 */ "m_delta", + /* 0307 */ "m_effectiveDate", + /* 0308 */ "m_end", + /* 0309 */ "m_expirationDate", + /* 030A */ "m_flags", + /* 030B */ "m_friendlyName", + /* 030C */ "m_handle", + /* 030D */ "m_hash", + /* 030E */ "m_id", + /* 030F */ "m_innerException", + /* 0310 */ "m_issuer", + /* 0311 */ "m_message", + /* 0312 */ "m_name", + /* 0313 */ "m_paramName", + /* 0314 */ "m_parent", + /* 0315 */ "m_password", + /* 0316 */ "m_payload", + /* 0317 */ "m_rand", + /* 0318 */ "m_refs", + /* 0319 */ "m_resourceFileId", + /* 031A */ "m_rm", + /* 031B */ "m_rmFallback", + /* 031C */ "m_selector", + /* 031D */ "m_seq", + /* 031E */ "m_sessionHandle", + /* 031F */ "m_size", + /* 0320 */ "m_source", + /* 0321 */ "m_stackTrace", + /* 0322 */ "m_start", + /* 0323 */ "m_state", + /* 0324 */ "m_subject", + /* 0325 */ "m_ticks", + /* 0326 */ "m_ticksOffset", + /* 0327 */ "m_timer", + /* 0328 */ "m_type", + /* 0329 */ "m_value", + /* 032A */ "manager", + /* 032B */ "monthDayPattern", + /* 032C */ "monthNames", + /* 032D */ "mscorlib", + /* 032E */ "negativeSign", + /* 032F */ "next", + /* 0330 */ "numInfo", + /* 0331 */ "numberDecimalSeparator", + /* 0332 */ "numberGroupSeparator", + /* 0333 */ "numberGroupSizes", + /* 0334 */ "op_Addition", + /* 0335 */ "op_Equality", + /* 0336 */ "op_GreaterThan", + /* 0337 */ "op_GreaterThanOrEqual", + /* 0338 */ "op_Inequality", + /* 0339 */ "op_LessThan", + /* 033A */ "op_LessThanOrEqual", + /* 033B */ "op_Subtraction", + /* 033C */ "op_UnaryNegation", + /* 033D */ "op_UnaryPlus", + /* 033E */ "pmDesignator", + /* 033F */ "positiveSign", + /* 0340 */ "propertyName", + /* 0341 */ "returnType", + /* 0342 */ "s_ewr", + /* 0343 */ "s_rgbBase64Decode", + /* 0344 */ "s_rgchBase64Encoding", + /* 0345 */ "s_rgchBase64EncodingDefault", + /* 0346 */ "s_rgchBase64EncodingRFC4648", + /* 0347 */ "set_Capacity", + /* 0348 */ "set_CurrentUICultureInternal", + /* 0349 */ "set_FrameworkDisplayName", + /* 034A */ "set_GrowthFactor", + /* 034B */ "set_Item", + /* 034C */ "set_Length", + /* 034D */ "set_MaxLoadFactor", + /* 034E */ "set_Position", + /* 034F */ "set_Priority", + /* 0350 */ "set_ReadTimeout", + /* 0351 */ "set_Target", + /* 0352 */ "set_UseRFC4648Encoding", + /* 0353 */ "set_WriteTimeout", + /* 0354 */ "shortDatePattern", + /* 0355 */ "shortTimePattern", + /* 0356 */ "temp", + /* 0357 */ "ticksAtOrigin", + /* 0358 */ "timeSeparator", + /* 0359 */ "value", + /* 035A */ "value__", + /* 035B */ "yearMonthPattern", + } + .Select((value, index) => new {value, index = (ushort) (0xFFFF - index)}) + .ToDictionary(item => item.value, item => item.index, StringComparer.Ordinal); + } +} diff --git a/source/MetadataProcessor.Core/nanoAssemblyBuilder.cs b/source/MetadataProcessor.Core/nanoAssemblyBuilder.cs new file mode 100644 index 00000000..22be290e --- /dev/null +++ b/source/MetadataProcessor.Core/nanoAssemblyBuilder.cs @@ -0,0 +1,113 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using Mono.Cecil; +using System.Collections.Generic; +using System.IO; +using System.Xml; + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Main metadata transformation class - builds .NET nanoFramework assembly + /// from full .NET Framework assembly metadata represented in Mono.Cecil format. + /// + public sealed class nanoAssemblyBuilder + { + private readonly nanoTablesContext _tablesContext; + + /// + /// Creates new instance of object. + /// + /// Original assembly metadata in Mono.Cecil format. + /// List of full type names with explicit ordering. + /// Custom string literals sorter for UTs using only. + /// + /// If contains true each type/method/field should contains one attribute of each type. + /// + public nanoAssemblyBuilder( + AssemblyDefinition assemblyDefinition, + List explicitTypesOrder = null, + ICustomStringSorter stringSorter = null, + bool applyAttributesCompression = false) + { + _tablesContext = new nanoTablesContext( + assemblyDefinition, explicitTypesOrder, stringSorter, applyAttributesCompression); + } + + /// + /// Writes all .NET nanoFramework metadata into output stream. + /// + /// Binary writer with correct endianness. + public void Write( + nanoBinaryWriter binaryWriter) + { + var header = new nanoAssemblyDefinition(_tablesContext); + header.Write(binaryWriter, true); + + foreach (var table in GetTables(_tablesContext)) + { + var tableBegin = (binaryWriter.BaseStream.Position + 3) & 0xFFFFFFFC; + table.Write(binaryWriter); + + var padding = (4 - ((binaryWriter.BaseStream.Position - tableBegin) % 4)) % 4; + binaryWriter.WriteBytes(new byte[padding]); + + header.UpdateTableOffset(binaryWriter, tableBegin, padding); + } + + binaryWriter.BaseStream.Seek(0, SeekOrigin.Begin); + header.Write(binaryWriter, false); + } + + public void Write( + XmlWriter xmlWriter) + { + var pdbxWriter = new nanoPdbxFileWriter(_tablesContext); + pdbxWriter.Write(xmlWriter); + } + + private static IEnumerable GetTables( + nanoTablesContext context) + { + yield return context.AssemblyReferenceTable; + + yield return context.TypeReferencesTable; + + yield return context.FieldReferencesTable; + + yield return context.MethodReferencesTable; + + yield return context.TypeDefinitionTable; + + yield return context.FieldsTable; + + yield return context.MethodDefinitionTable; + + yield return context.AttributesTable; + + yield return context.TypeSpecificationsTable; + + yield return context.ResourcesTable; + + yield return context.ResourceDataTable; + + context.ByteCodeTable.UpdateStringTable(); + context.StringTable.GetOrCreateStringId( + context.AssemblyDefinition.Name.Name); + + yield return context.StringTable; + + yield return context.SignaturesTable; + + yield return context.ByteCodeTable; + + yield return context.ResourceFileTable; + + yield return nanoEmptyTable.Instance; + } + } +} diff --git a/source/MetadataProcessor.Core/nanoAssemblyDefinition.cs b/source/MetadataProcessor.Core/nanoAssemblyDefinition.cs new file mode 100644 index 00000000..0272f3ad --- /dev/null +++ b/source/MetadataProcessor.Core/nanoAssemblyDefinition.cs @@ -0,0 +1,186 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Original work from Oleg Rakhmatulin. +// See LICENSE file in the project root for full license information. +// + +using System.IO; + +namespace nanoFramework.Tools.MetadataProcessor +{ + /// + /// Encapsulates logic for assembly definition (header) writing. + /// + public sealed class nanoAssemblyDefinition + { + /// + /// nanoFramework assembly marker V1. + /// + private const string c_NFAssemblyMarker_v1 = "NFMRK1"; + + /// + /// Position of Assembly CRC32 in the PE file. + /// + private const int c_AssemblyCrc32Position = 0x0C; + + /// + /// Position of the header CRC32 in the PE file. + /// + private const int c_HeaderCrc32Position = 0x08; + + /// + /// Assembly tables context - contains all tables used for building target assembly. + /// + private readonly nanoTablesContext _context; + + /// + /// Offset for current table address writing. + /// + private long _tablesOffset; + + /// + /// Offset for current table padding writing. + /// + private long _paddingsOffset; + + /// + /// Creates new instance of object. + /// + /// + /// Assembly tables context - contains all tables used for building target assembly. + /// + public nanoAssemblyDefinition( + nanoTablesContext context) + { + _context = context; + } + + /// + /// Writes header information into output stream (w/o CRC and table offsets/paddings). + /// + /// Binary writer with correct endianness. + /// If true no assembly name will be written. + public void Write( + nanoBinaryWriter writer, + bool isPreAllocationCall) + { + // this replicates the original struct CLR_RECORD_ASSEMBLY + + writer.WriteString(c_NFAssemblyMarker_v1); + + // header CRC32 + writer.WriteUInt32(0); + + // assembly CRC32 + writer.WriteUInt32(0); + + // current builds are for little endian targets only + // keeping this here for now, just for compatibility + writer.WriteUInt32(0); + + // native methods CRC32 + writer.WriteUInt32(writer.IsBigEndian ? _context.NativeMethodsCrc.Current : 0x00); + + // the existing MDP seems to have a bug because it's adding an extra byte at this place in the struct + // right between the NativeMethodsChecksum and PatchEntryOffset fields. + //// need this here to pad the structure in order to have a PE exactly as the one being generated now + //writer.WriteByte(0); + + // Native methods offset + writer.WriteUInt32(0xFFFFFFFF); + + writer.WriteVersion(_context.AssemblyDefinition.Name.Version); + + writer.WriteUInt16(isPreAllocationCall + ? (ushort) 0x0000 + : _context.StringTable.GetOrCreateStringId(_context.AssemblyDefinition.Name.Name)); + writer.WriteUInt16(1); // String table version + + //For every table, a number of bytes that were padded to the end of the table + //to align to unsigned long. Each table starts at a unsigned long boundary, and ends + //at a unsigned long boundary. Some of these tables will, by construction, have + //no padding, and all will have values in the range [0-3]. This isn't the most + //compact form to hold this information, but it only costs 16 bytes/assembly. + //Trying to only align some of the tables is just much more hassle than it's worth. + //And, of course, this field also has to be unsigned long-aligned. + if (isPreAllocationCall) + { + _tablesOffset = writer.BaseStream.Position; + for (var i = 0; i < 16; ++i) + { + writer.WriteUInt32(0); + } + + writer.WriteUInt32(0); // Number of patched methods + + _paddingsOffset = writer.BaseStream.Position; + for (var i = 0; i < 16; ++i) + { + writer.WriteByte(0); + } + } + else + { + // order matters! + // need to compute Assembly CRC32 before header CRC32 + + // set writer position at Assembly CRC32 position + writer.BaseStream.Seek(c_AssemblyCrc32Position, SeekOrigin.Begin); + + var assemblyCrc32 = ComputeCrc32( + writer.BaseStream, + _paddingsOffset, + writer.BaseStream.Length - _paddingsOffset); + writer.WriteUInt32(assemblyCrc32); + + // set writer position at Header CRC32 position + writer.BaseStream.Seek(c_HeaderCrc32Position, SeekOrigin.Begin); + + var headerCrc32 = ComputeCrc32( + writer.BaseStream, + 0, + _paddingsOffset); + writer.WriteUInt32(headerCrc32); + } + } + + /// + /// Updates tables offset value and padding value for current table and + /// advance writing position for next method call (filling tables info). + /// + /// Binary writer. + /// Table beginning address (offset). + /// Table padding value. + public void UpdateTableOffset( + nanoBinaryWriter writer, + long tableBegin, + long padding) + { + writer.BaseStream.Seek(_tablesOffset, SeekOrigin.Begin); + writer.WriteUInt32((uint)tableBegin); + _tablesOffset += sizeof(int); + + writer.BaseStream.Seek(_paddingsOffset, SeekOrigin.Begin); + writer.WriteByte((byte)padding); + _paddingsOffset += sizeof(byte); + + writer.BaseStream.Seek(0, SeekOrigin.End); + } + + private static uint ComputeCrc32( + Stream outputStream, + long startOffset, + long size) + { + var currentPosition = outputStream.Position; + outputStream.Seek(startOffset, SeekOrigin.Begin); + + var buffer = new byte[size]; + outputStream.Read(buffer, 0, buffer.Length); + + outputStream.Seek(currentPosition, SeekOrigin.Begin); + + return Crc32.Compute(buffer); + } + } +} diff --git a/source/MetadataProcessor.Core/packages.config b/source/MetadataProcessor.Core/packages.config new file mode 100644 index 00000000..778a66e9 --- /dev/null +++ b/source/MetadataProcessor.Core/packages.config @@ -0,0 +1,5 @@ + + + + + \ No newline at end of file diff --git a/source/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/CL.command.1.tlog b/source/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/CL.command.1.tlog deleted file mode 100644 index 8d0a18a8..00000000 Binary files a/source/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/CL.command.1.tlog and /dev/null differ diff --git a/source/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/CL.write.1.tlog b/source/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/CL.write.1.tlog deleted file mode 100644 index 0df2e7ed..00000000 Binary files a/source/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/CL.write.1.tlog and /dev/null differ diff --git a/source/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/Lib-link.read.1.tlog b/source/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/Lib-link.read.1.tlog deleted file mode 100644 index 128723c0..00000000 Binary files a/source/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/Lib-link.read.1.tlog and /dev/null differ diff --git a/source/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/Lib-link.write.1.tlog b/source/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/Lib-link.write.1.tlog deleted file mode 100644 index 904771fd..00000000 Binary files a/source/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/Lib-link.write.1.tlog and /dev/null differ diff --git a/source/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/Lib.command.1.tlog b/source/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/Lib.command.1.tlog deleted file mode 100644 index bfb51b42..00000000 Binary files a/source/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/Lib.command.1.tlog and /dev/null differ diff --git a/source/Tools.CorHelper/Debug/Tools.Lib.CorHelper.idb b/source/Tools.CorHelper/Debug/Tools.Lib.CorHelper.idb deleted file mode 100644 index 5fb91df1..00000000 Binary files a/source/Tools.CorHelper/Debug/Tools.Lib.CorHelper.idb and /dev/null differ diff --git a/source/Tools.Parser/Debug/Tools.Lib.Parser.idb b/source/Tools.Parser/Debug/Tools.Lib.Parser.idb deleted file mode 100644 index dbbe31e4..00000000 Binary files a/source/Tools.Parser/Debug/Tools.Lib.Parser.idb and /dev/null differ diff --git a/source/Tools.Parser/Debug/Tools.Lib.Parser.tlog/CL.command.1.tlog b/source/Tools.Parser/Debug/Tools.Lib.Parser.tlog/CL.command.1.tlog deleted file mode 100644 index 79d1ac8f..00000000 Binary files a/source/Tools.Parser/Debug/Tools.Lib.Parser.tlog/CL.command.1.tlog and /dev/null differ diff --git a/source/Tools.Parser/Debug/Tools.Lib.Parser.tlog/CL.write.1.tlog b/source/Tools.Parser/Debug/Tools.Lib.Parser.tlog/CL.write.1.tlog deleted file mode 100644 index e2320f3c..00000000 Binary files a/source/Tools.Parser/Debug/Tools.Lib.Parser.tlog/CL.write.1.tlog and /dev/null differ diff --git a/source/Tools.Parser/Debug/Tools.Lib.Parser.tlog/Lib-link.read.1.tlog b/source/Tools.Parser/Debug/Tools.Lib.Parser.tlog/Lib-link.read.1.tlog deleted file mode 100644 index f871b6e7..00000000 Binary files a/source/Tools.Parser/Debug/Tools.Lib.Parser.tlog/Lib-link.read.1.tlog and /dev/null differ diff --git a/source/Tools.Parser/Debug/Tools.Lib.Parser.tlog/Lib-link.write.1.tlog b/source/Tools.Parser/Debug/Tools.Lib.Parser.tlog/Lib-link.write.1.tlog deleted file mode 100644 index 114a122a..00000000 Binary files a/source/Tools.Parser/Debug/Tools.Lib.Parser.tlog/Lib-link.write.1.tlog and /dev/null differ diff --git a/source/Tools.Parser/Debug/Tools.Lib.Parser.tlog/Lib.command.1.tlog b/source/Tools.Parser/Debug/Tools.Lib.Parser.tlog/Lib.command.1.tlog deleted file mode 100644 index ff69c4df..00000000 Binary files a/source/Tools.Parser/Debug/Tools.Lib.Parser.tlog/Lib.command.1.tlog and /dev/null differ diff --git a/source/nanoFramework.Tools.MetadataProcessor.sln b/source/nanoFramework.Tools.MetadataProcessor.sln index 6eecaffd..e8016217 100644 --- a/source/nanoFramework.Tools.MetadataProcessor.sln +++ b/source/nanoFramework.Tools.MetadataProcessor.sln @@ -1,207 +1,34 @@  Microsoft Visual Studio Solution File, Format Version 12.00 # Visual Studio 15 -VisualStudioVersion = 15.0.27130.2027 +VisualStudioVersion = 15.0.28307.902 MinimumVisualStudioVersion = 10.0.40219.1 -Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "MetaDataProcessor", "MetaDataProcessor", "{FCCC9596-0809-4BB4-ACC2-3615EEC264C7}" +Project("{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}") = "MetadataProcessor.Core", "MetadataProcessor.Core\MetadataProcessor.Core.csproj", "{E32F7D15-2499-440C-8026-4D5EE1C5EC3A}" EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Core", "..\nf-interpreter\src\CLR\Core\Core.vcxproj", "{89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}" -EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "CorLib", "..\nf-interpreter\src\CLR\CorLib\CorLib.vcxproj", "{58E950CC-2FF6-423C-B006-A70A19272F20}" -EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Diagnostics", "..\nf-interpreter\src\CLR\Diagnostics\Diagnostics.vcxproj", "{A5E9AE41-F4FA-40CE-AD82-A7861EBA007B}" -EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Tools.Lib.Parser", "Tools.Parser\Parser.vcxproj", "{AB1ED6AC-5C7F-49CD-A84B-4B7362D355BC}" -EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Serialization", "..\nf-interpreter\src\CLR\Core\Serialization\Serialization.vcxproj", "{16BF6131-A3B8-4B97-B867-E45669FB48BD}" -EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "RPC", "..\nf-interpreter\src\CLR\Core\RPC\RPC.vcxproj", "{ED4C887A-EC09-465B-B5D9-075450ADC52D}" -EndProject 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{ED4C887A-EC09-465B-B5D9-075450ADC52D} = {FCCC9596-0809-4BB4-ACC2-3615EEC264C7} - {131001E3-0201-451F-A87B-951D1C5C3EEE} = {FCCC9596-0809-4BB4-ACC2-3615EEC264C7} - {2337C4A4-3AB4-4014-9C29-9EBE32F4510E} = {FCCC9596-0809-4BB4-ACC2-3615EEC264C7} - {5D50772E-DAC8-407D-972F-37DEB4450B72} = {FCCC9596-0809-4BB4-ACC2-3615EEC264C7} - {079E1BC1-3B21-46E8-B1BA-AEDB68CCDC11} = {FCCC9596-0809-4BB4-ACC2-3615EEC264C7} - {D32EE397-7E49-452D-AC95-AFCB3C962E3D} = {FCCC9596-0809-4BB4-ACC2-3615EEC264C7} - {80209A7E-B9F0-4143-BCD1-B1891236A3CF} = {FCCC9596-0809-4BB4-ACC2-3615EEC264C7} - EndGlobalSection GlobalSection(ExtensibilityGlobals) = postSolution - SolutionGuid = {5DF99A8C-CA3C-451A-ABC1-4D862154708B} + SolutionGuid = {31412224-888D-40FC-AE73-2FF5468E59CD} + EndGlobalSection + GlobalSection(MonoDevelopProperties) = preSolution + StartupItem = MFMetaDataProcessor.Core\MFMetaDataProcessor.Core.csproj EndGlobalSection EndGlobal diff --git a/source/Tools.CorHelper/CorHelper-vs2019.vcproj b/source/native/Tools.CorHelper/CorHelper-vs2019.vcproj similarity index 100% rename from source/Tools.CorHelper/CorHelper-vs2019.vcproj rename to source/native/Tools.CorHelper/CorHelper-vs2019.vcproj diff --git a/source/Tools.CorHelper/CorHelper-vs2019.vcxproj b/source/native/Tools.CorHelper/CorHelper-vs2019.vcxproj similarity index 90% rename from source/Tools.CorHelper/CorHelper-vs2019.vcxproj rename to source/native/Tools.CorHelper/CorHelper-vs2019.vcxproj index c7b9081d..01842e23 100644 --- a/source/Tools.CorHelper/CorHelper-vs2019.vcxproj +++ b/source/native/Tools.CorHelper/CorHelper-vs2019.vcxproj @@ -62,7 +62,7 @@ Disabled - ..\Tools.MetaDataProcessor;..\Tools.Parser;..\..\nf-interpreter\src\CLR\CorLib;..\..\nf-interpreter\targets\os\win32\Include;..\..\nf-interpreter\src\PAL\Include;..\..\nf-interpreter\src\HAL\Include;..\..\nf-interpreter\src\CLR\Include;%(AdditionalIncludeDirectories) + ..\Tools.MetaDataProcessor;..\Tools.Parser;..\nf-interpreter\src\CLR\CorLib;..\nf-interpreter\targets\os\win32\Include;..\nf-interpreter\src\PAL\Include;..\nf-interpreter\src\HAL\Include;..\nf-interpreter\src\CLR\Include;%(AdditionalIncludeDirectories) WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) true EnableFastChecks @@ -80,7 +80,7 @@ MaxSpeed OnlyExplicitInline true - ..\Tools.MetaDataProcessor;..\Tools.Parser;..\..\nf-interpreter\src\CLR\CorLib;..\..\nf-interpreter\targets\os\win32\Include;..\..\nf-interpreter\src\PAL\Include;..\..\nf-interpreter\src\HAL\Include;..\..\nf-interpreter\src\CLR\Include;%(AdditionalIncludeDirectories) + ..\Tools.MetaDataProcessor;..\Tools.Parser;..\nf-interpreter\src\CLR\CorLib;..\nf-interpreter\targets\os\win32\Include;..\nf-interpreter\src\PAL\Include;..\nf-interpreter\src\HAL\Include;..\nf-interpreter\src\CLR\Include;%(AdditionalIncludeDirectories) WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) true MultiThreadedDLL diff --git a/source/Tools.CorHelper/CorHelper-vs2019.vcxproj.filters b/source/native/Tools.CorHelper/CorHelper-vs2019.vcxproj.filters similarity index 100% rename from source/Tools.CorHelper/CorHelper-vs2019.vcxproj.filters rename to source/native/Tools.CorHelper/CorHelper-vs2019.vcxproj.filters diff --git a/source/Tools.CorHelper/CorHelper.vcproj b/source/native/Tools.CorHelper/CorHelper.vcproj similarity index 100% rename from source/Tools.CorHelper/CorHelper.vcproj rename to source/native/Tools.CorHelper/CorHelper.vcproj diff --git a/source/Tools.CorHelper/CorHelper.vcxproj b/source/native/Tools.CorHelper/CorHelper.vcxproj similarity index 90% rename from source/Tools.CorHelper/CorHelper.vcxproj rename to source/native/Tools.CorHelper/CorHelper.vcxproj index 4c1e41f8..60676b47 100644 --- a/source/Tools.CorHelper/CorHelper.vcxproj +++ b/source/native/Tools.CorHelper/CorHelper.vcxproj @@ -62,7 +62,7 @@ Disabled - ..\Tools.MetaDataProcessor;..\Tools.Parser;..\..\nf-interpreter\src\CLR\CorLib;..\..\nf-interpreter\targets\os\win32\Include;..\..\nf-interpreter\src\PAL\Include;..\..\nf-interpreter\src\HAL\Include;..\..\nf-interpreter\src\CLR\Include;%(AdditionalIncludeDirectories) + ..\Tools.MetaDataProcessor;..\Tools.Parser;..\nf-interpreter\src\CLR\CorLib;..\nf-interpreter\targets\os\win32\Include;..\nf-interpreter\src\PAL\Include;..\nf-interpreter\src\HAL\Include;..\nf-interpreter\src\CLR\Include;%(AdditionalIncludeDirectories) WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) true EnableFastChecks @@ -80,7 +80,7 @@ MaxSpeed OnlyExplicitInline true - ..\Tools.MetaDataProcessor;..\Tools.Parser;..\..\nf-interpreter\src\CLR\CorLib;..\..\nf-interpreter\targets\os\win32\Include;..\..\nf-interpreter\src\PAL\Include;..\..\nf-interpreter\src\HAL\Include;..\..\nf-interpreter\src\CLR\Include;%(AdditionalIncludeDirectories) + ..\Tools.MetaDataProcessor;..\Tools.Parser;..\nf-interpreter\src\CLR\CorLib;..\nf-interpreter\targets\os\win32\Include;..\nf-interpreter\src\PAL\Include;..\nf-interpreter\src\HAL\Include;..\nf-interpreter\src\CLR\Include;%(AdditionalIncludeDirectories) WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) true MultiThreadedDLL diff --git a/source/Tools.CorHelper/CorHelper.vcxproj.filters b/source/native/Tools.CorHelper/CorHelper.vcxproj.filters similarity index 100% rename from source/Tools.CorHelper/CorHelper.vcxproj.filters rename to source/native/Tools.CorHelper/CorHelper.vcxproj.filters diff --git a/source/native/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/CL.command.1.tlog b/source/native/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/CL.command.1.tlog new file mode 100644 index 00000000..5e317af6 Binary files /dev/null and b/source/native/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/CL.command.1.tlog differ diff --git a/source/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/CL.read.1.tlog b/source/native/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/CL.read.1.tlog similarity index 96% rename from source/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/CL.read.1.tlog rename to source/native/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/CL.read.1.tlog index bfd3ebd5..994a84b8 100644 Binary files a/source/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/CL.read.1.tlog and b/source/native/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/CL.read.1.tlog differ diff --git a/source/native/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/CL.write.1.tlog b/source/native/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/CL.write.1.tlog new file mode 100644 index 00000000..b2fdf23f Binary files /dev/null and b/source/native/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/CL.write.1.tlog differ diff --git a/source/native/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/Lib-link.read.1.tlog b/source/native/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/Lib-link.read.1.tlog new file mode 100644 index 00000000..5f54e52d Binary files /dev/null and b/source/native/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/Lib-link.read.1.tlog differ diff --git a/source/native/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/Lib-link.write.1.tlog b/source/native/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/Lib-link.write.1.tlog new file mode 100644 index 00000000..60824f5b Binary files /dev/null and b/source/native/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/Lib-link.write.1.tlog differ diff --git a/source/native/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/Lib.command.1.tlog b/source/native/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/Lib.command.1.tlog new file mode 100644 index 00000000..b7dffefb Binary files /dev/null and b/source/native/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/Lib.command.1.tlog differ diff --git a/source/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/Tools.Lib.CorHelper.lastbuildstate b/source/native/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/Tools.Lib.CorHelper.lastbuildstate similarity index 70% rename from source/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/Tools.Lib.CorHelper.lastbuildstate rename to source/native/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/Tools.Lib.CorHelper.lastbuildstate index 34f2059c..d9067f79 100644 --- a/source/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/Tools.Lib.CorHelper.lastbuildstate +++ b/source/native/Tools.CorHelper/Debug/Tools.Li.079E1BC1.tlog/Tools.Lib.CorHelper.lastbuildstate @@ -1,2 +1,2 @@ #TargetFrameworkVersion=v4.0:PlatformToolSet=v141:EnableManagedIncrementalBuild=false:VCToolArchitecture=Native32Bit:WindowsTargetPlatformVersion=10.0.17763.0 -Debug|Win32|E:\GitHub\nf-tool-metadata-processor\source\| +Debug|Win32|E:\GitHub\nf-tool-metadata-processor\source\native\| diff --git a/source/native/Tools.CorHelper/Debug/Tools.Lib.CorHelper.idb b/source/native/Tools.CorHelper/Debug/Tools.Lib.CorHelper.idb new file mode 100644 index 00000000..f17fb8a1 Binary files /dev/null and b/source/native/Tools.CorHelper/Debug/Tools.Lib.CorHelper.idb differ diff --git a/source/Tools.CorHelper/corhlpr.cpp b/source/native/Tools.CorHelper/corhlpr.cpp similarity index 100% rename from source/Tools.CorHelper/corhlpr.cpp rename to source/native/Tools.CorHelper/corhlpr.cpp diff --git a/source/Tools.CorHelper/dotNetMF.proj b/source/native/Tools.CorHelper/dotNetMF.proj similarity index 100% rename from source/Tools.CorHelper/dotNetMF.proj rename to source/native/Tools.CorHelper/dotNetMF.proj diff --git a/source/Tools.CorHelper/stdafx.cpp b/source/native/Tools.CorHelper/stdafx.cpp similarity index 100% rename from source/Tools.CorHelper/stdafx.cpp rename to source/native/Tools.CorHelper/stdafx.cpp diff --git a/source/Tools.CorHelper/stdafx.h b/source/native/Tools.CorHelper/stdafx.h similarity index 100% rename from source/Tools.CorHelper/stdafx.h rename to source/native/Tools.CorHelper/stdafx.h diff --git a/source/Tools.MetaDataProcessor/AssemblyParser.h b/source/native/Tools.MetaDataProcessor/AssemblyParser.h similarity index 99% rename from source/Tools.MetaDataProcessor/AssemblyParser.h rename to source/native/Tools.MetaDataProcessor/AssemblyParser.h index 93620f9c..01f88596 100644 --- a/source/Tools.MetaDataProcessor/AssemblyParser.h +++ b/source/native/Tools.MetaDataProcessor/AssemblyParser.h @@ -418,6 +418,7 @@ namespace MetaData FieldDef(Parser* holder); bool SetValue(const void* ptr, int len); + bool SetEmptyString(const void* ptr); }; struct MethodDef diff --git a/source/Tools.MetaDataProcessor/AssemblyReparser.h b/source/native/Tools.MetaDataProcessor/AssemblyReparser.h similarity index 100% rename from source/Tools.MetaDataProcessor/AssemblyReparser.h rename to source/native/Tools.MetaDataProcessor/AssemblyReparser.h diff --git a/source/Tools.MetaDataProcessor/HAL_Windows.h b/source/native/Tools.MetaDataProcessor/HAL_Windows.h similarity index 100% rename from source/Tools.MetaDataProcessor/HAL_Windows.h rename to source/native/Tools.MetaDataProcessor/HAL_Windows.h diff --git a/source/Tools.MetaDataProcessor/Info_Win32.cpp b/source/native/Tools.MetaDataProcessor/Info_Win32.cpp similarity index 100% rename from source/Tools.MetaDataProcessor/Info_Win32.cpp rename to source/native/Tools.MetaDataProcessor/Info_Win32.cpp diff --git a/source/Tools.MetaDataProcessor/ManagedElementTypes_Win32.cpp b/source/native/Tools.MetaDataProcessor/ManagedElementTypes_Win32.cpp similarity index 100% rename from source/Tools.MetaDataProcessor/ManagedElementTypes_Win32.cpp rename to source/native/Tools.MetaDataProcessor/ManagedElementTypes_Win32.cpp diff --git a/source/Tools.MetaDataProcessor/ManagedElementTypes_Win32.h b/source/native/Tools.MetaDataProcessor/ManagedElementTypes_Win32.h similarity index 100% rename from source/Tools.MetaDataProcessor/ManagedElementTypes_Win32.h rename to source/native/Tools.MetaDataProcessor/ManagedElementTypes_Win32.h diff --git a/source/Tools.MetaDataProcessor/MetaDataProcessor-vs2019.vcxproj b/source/native/Tools.MetaDataProcessor/MetaDataProcessor-vs2019.vcxproj similarity index 77% rename from source/Tools.MetaDataProcessor/MetaDataProcessor-vs2019.vcxproj rename to source/native/Tools.MetaDataProcessor/MetaDataProcessor-vs2019.vcxproj index 61f3f668..4b2144ce 100644 --- a/source/Tools.MetaDataProcessor/MetaDataProcessor-vs2019.vcxproj +++ b/source/native/Tools.MetaDataProcessor/MetaDataProcessor-vs2019.vcxproj @@ -99,7 +99,7 @@ Level3 Disabled WIN32;METADATAPROCESSOR;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - ..\Tools.Parser;..\..\nf-interpreter\src\CLR\CorLib;..\..\nf-interpreter\targets\os\win32\Include;..\..\nf-interpreter\src\PAL\Include;..\..\nf-interpreter\src\HAL\Include;..\..\nf-interpreter\src\CLR\Include;..\..\nf-interpreter\src\CLR\Core;..\..\nf-interpreter\src\CLR\Helpers\Base64;%(AdditionalIncludeDirectories) + ..\Tools.Parser;..\nf-interpreter\src\CLR\CorLib;..\nf-interpreter\targets\os\win32\Include;..\nf-interpreter\src\PAL\Include;..\nf-interpreter\src\HAL\Include;..\nf-interpreter\src\CLR\Include;..\nf-interpreter\src\CLR\Core;..\nf-interpreter\src\CLR\Helpers\Base64;%(AdditionalIncludeDirectories) MultiThreadedDebugDLL @@ -113,7 +113,7 @@ Level3 Disabled _DEBUG;_CONSOLE;%(PreprocessorDefinitions) - ..\..\nf-interpreter\src\CLR\CorLib;..\..\nf-interpreter\targets\os\win32\Include;..\..\nf-interpreter\src\PAL\Include;..\..\nf-interpreter\src\HAL\Include;..\..\nf-interpreter\src\CLR\Include;..\..\nf-interpreter\src\CLR\Core;%(AdditionalIncludeDirectories) + ..\nf-interpreter\src\CLR\CorLib;..\nf-interpreter\targets\os\win32\Include;..\nf-interpreter\src\PAL\Include;..\nf-interpreter\src\HAL\Include;..\nf-interpreter\src\CLR\Include;..\nf-interpreter\src\CLR\Core;%(AdditionalIncludeDirectories) Console @@ -127,7 +127,7 @@ false true WIN32;METADATAPROCESSOR;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - ..\Tools.Parser;..\..\nf-interpreter\src\CLR\CorLib;..\..\nf-interpreter\targets\os\win32\Include;..\..\nf-interpreter\src\PAL\Include;..\..\nf-interpreter\src\HAL\Include;..\..\nf-interpreter\src\CLR\Include;..\..\nf-interpreter\src\CLR\Core;..\..\nf-interpreter\src\CLR\Helpers\Base64;%(AdditionalIncludeDirectories) + ..\Tools.Parser;..\nf-interpreter\src\CLR\CorLib;..\nf-interpreter\targets\os\win32\Include;..\nf-interpreter\src\PAL\Include;..\nf-interpreter\src\HAL\Include;..\nf-interpreter\src\CLR\Include;..\nf-interpreter\src\CLR\Core;..\nf-interpreter\src\CLR\Helpers\Base64;%(AdditionalIncludeDirectories) MultiThreadedDLL @@ -146,7 +146,7 @@ true true NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - ..\..\nf-interpreter\src\CLR\CorLib;..\..\nf-interpreter\targets\os\win32\Include;..\..\nf-interpreter\src\PAL\Include;..\..\nf-interpreter\src\HAL\Include;..\..\nf-interpreter\src\CLR\Include;..\..\nf-interpreter\src\CLR\Core;%(AdditionalIncludeDirectories) + ..\nf-interpreter\src\CLR\CorLib;..\nf-interpreter\targets\os\win32\Include;..\nf-interpreter\src\PAL\Include;..\nf-interpreter\src\HAL\Include;..\nf-interpreter\src\CLR\Include;..\nf-interpreter\src\CLR\Core;%(AdditionalIncludeDirectories) Console @@ -168,15 +168,15 @@ - - - - - - - - - + + + + + + + + + @@ -196,28 +196,28 @@ - + {89cf8bdb-9c8a-4d18-bc3e-4312c5bd34b1} - + {5d50772e-dac8-407d-972f-37deb4450b72} - + {d32ee397-7e49-452d-ac95-afcb3c962e3d} - + {ed4c887a-ec09-465b-b5d9-075450adc52d} - + {16bf6131-a3b8-4b97-b867-e45669fb48bd} - + {58e950cc-2ff6-423c-b006-a70a19272f20} - + {a5e9ae41-f4fa-40ce-ad82-a7861eba007b} - + {131001e3-0201-451f-a87b-951d1c5c3eee} diff --git a/source/Tools.MetaDataProcessor/MetaDataProcessor-vs2019.vcxproj.filters b/source/native/Tools.MetaDataProcessor/MetaDataProcessor-vs2019.vcxproj.filters similarity index 80% rename from source/Tools.MetaDataProcessor/MetaDataProcessor-vs2019.vcxproj.filters rename to source/native/Tools.MetaDataProcessor/MetaDataProcessor-vs2019.vcxproj.filters index 679f8d9e..cc8cdd93 100644 --- a/source/Tools.MetaDataProcessor/MetaDataProcessor-vs2019.vcxproj.filters +++ b/source/native/Tools.MetaDataProcessor/MetaDataProcessor-vs2019.vcxproj.filters @@ -56,7 +56,7 @@ Source Files - + Source Files @@ -65,16 +65,16 @@ Source Files - + Source Files Source Files - + Source Files - + Source Files @@ -89,16 +89,16 @@ Source Files - + Source Files - + Source Files - + Source Files - + Source Files @@ -107,7 +107,7 @@ Source Files - + Source Files diff --git a/source/Tools.MetaDataProcessor/MetaDataProcessor.cpp b/source/native/Tools.MetaDataProcessor/MetaDataProcessor.cpp similarity index 100% rename from source/Tools.MetaDataProcessor/MetaDataProcessor.cpp rename to source/native/Tools.MetaDataProcessor/MetaDataProcessor.cpp diff --git a/source/Tools.MetaDataProcessor/MetaDataProcessor.vcxproj b/source/native/Tools.MetaDataProcessor/MetaDataProcessor.vcxproj similarity index 79% rename from source/Tools.MetaDataProcessor/MetaDataProcessor.vcxproj rename to source/native/Tools.MetaDataProcessor/MetaDataProcessor.vcxproj index 7a508e8c..1f8037b6 100644 --- a/source/Tools.MetaDataProcessor/MetaDataProcessor.vcxproj +++ b/source/native/Tools.MetaDataProcessor/MetaDataProcessor.vcxproj @@ -95,7 +95,7 @@ Level3 Disabled WIN32;METADATAPROCESSOR;_DEBUG;_CONSOLE;%(PreprocessorDefinitions) - ..\Tools.Parser;..\..\nf-interpreter\src\CLR\CorLib;..\..\nf-interpreter\targets\os\win32\Include;..\..\nf-interpreter\src\PAL\Include;..\..\nf-interpreter\src\HAL\Include;..\..\nf-interpreter\src\CLR\Include;..\..\nf-interpreter\src\CLR\Core;%(AdditionalIncludeDirectories) + ..\Tools.Parser;..\nf-interpreter\src\CLR\CorLib;..\nf-interpreter\targets\os\win32\Include;..\nf-interpreter\src\PAL\Include;..\nf-interpreter\src\HAL\Include;..\nf-interpreter\src\CLR\Include;..\nf-interpreter\src\CLR\Core;%(AdditionalIncludeDirectories) MultiThreadedDebugDLL @@ -109,7 +109,7 @@ Level3 Disabled _DEBUG;_CONSOLE;%(PreprocessorDefinitions) - ..\..\nf-interpreter\src\CLR\CorLib;..\..\nf-interpreter\targets\os\win32\Include;..\..\nf-interpreter\src\PAL\Include;..\..\nf-interpreter\src\HAL\Include;..\..\nf-interpreter\src\CLR\Include;..\..\nf-interpreter\src\CLR\Core;%(AdditionalIncludeDirectories) + ..\nf-interpreter\src\CLR\CorLib;..\nf-interpreter\targets\os\win32\Include;..\nf-interpreter\src\PAL\Include;..\nf-interpreter\src\HAL\Include;..\nf-interpreter\src\CLR\Include;..\nf-interpreter\src\CLR\Core;%(AdditionalIncludeDirectories) Console @@ -123,7 +123,7 @@ false true WIN32;METADATAPROCESSOR;NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - ..\Tools.Parser;..\..\nf-interpreter\src\CLR\CorLib;..\..\nf-interpreter\targets\os\win32\Include;..\..\nf-interpreter\src\PAL\Include;..\..\nf-interpreter\src\HAL\Include;..\..\nf-interpreter\src\CLR\Include;..\..\nf-interpreter\src\CLR\Core;%(AdditionalIncludeDirectories) + ..\Tools.Parser;..\nf-interpreter\src\CLR\CorLib;..\nf-interpreter\targets\os\win32\Include;..\nf-interpreter\src\PAL\Include;..\nf-interpreter\src\HAL\Include;..\nf-interpreter\src\CLR\Include;..\nf-interpreter\src\CLR\Core;%(AdditionalIncludeDirectories) MultiThreadedDLL @@ -142,7 +142,7 @@ true true NDEBUG;_CONSOLE;%(PreprocessorDefinitions) - ..\..\nf-interpreter\src\CLR\CorLib;..\..\nf-interpreter\targets\os\win32\Include;..\..\nf-interpreter\src\PAL\Include;..\..\nf-interpreter\src\HAL\Include;..\..\nf-interpreter\src\CLR\Include;..\..\nf-interpreter\src\CLR\Core;%(AdditionalIncludeDirectories) + ..\nf-interpreter\src\CLR\CorLib;..\nf-interpreter\targets\os\win32\Include;..\nf-interpreter\src\PAL\Include;..\nf-interpreter\src\HAL\Include;..\nf-interpreter\src\CLR\Include;..\nf-interpreter\src\CLR\Core;%(AdditionalIncludeDirectories) Console @@ -164,15 +164,15 @@ - - - - - - - - - + + + + + + + + + @@ -192,28 +192,28 @@ - + {89cf8bdb-9c8a-4d18-bc3e-4312c5bd34b1} - + {5d50772e-dac8-407d-972f-37deb4450b72} - + {d32ee397-7e49-452d-ac95-afcb3c962e3d} - + {ed4c887a-ec09-465b-b5d9-075450adc52d} - + {16bf6131-a3b8-4b97-b867-e45669fb48bd} - + {58e950cc-2ff6-423c-b006-a70a19272f20} - + {a5e9ae41-f4fa-40ce-ad82-a7861eba007b} - + {131001e3-0201-451f-a87b-951d1c5c3eee} diff --git a/source/Tools.MetaDataProcessor/MetaDataProcessor.vcxproj.filters b/source/native/Tools.MetaDataProcessor/MetaDataProcessor.vcxproj.filters similarity index 80% rename from source/Tools.MetaDataProcessor/MetaDataProcessor.vcxproj.filters rename to source/native/Tools.MetaDataProcessor/MetaDataProcessor.vcxproj.filters index 6593fece..3ab4e416 100644 --- a/source/Tools.MetaDataProcessor/MetaDataProcessor.vcxproj.filters +++ b/source/native/Tools.MetaDataProcessor/MetaDataProcessor.vcxproj.filters @@ -56,7 +56,7 @@ Source Files - + Source Files @@ -65,16 +65,16 @@ Source Files - + Source Files Source Files - + Source Files - + Source Files @@ -89,16 +89,16 @@ Source Files - + Source Files - + Source Files - + Source Files - + Source Files @@ -107,7 +107,7 @@ Source Files - + Source Files diff --git a/source/Tools.MetaDataProcessor/ParseOptions_Win32.cpp b/source/native/Tools.MetaDataProcessor/ParseOptions_Win32.cpp similarity index 100% rename from source/Tools.MetaDataProcessor/ParseOptions_Win32.cpp rename to source/native/Tools.MetaDataProcessor/ParseOptions_Win32.cpp diff --git a/source/Tools.MetaDataProcessor/StubWinHal.cpp b/source/native/Tools.MetaDataProcessor/StubWinHal.cpp similarity index 100% rename from source/Tools.MetaDataProcessor/StubWinHal.cpp rename to source/native/Tools.MetaDataProcessor/StubWinHal.cpp diff --git a/source/Tools.MetaDataProcessor/Time_stubs.cpp b/source/native/Tools.MetaDataProcessor/Time_stubs.cpp similarity index 100% rename from source/Tools.MetaDataProcessor/Time_stubs.cpp rename to source/native/Tools.MetaDataProcessor/Time_stubs.cpp diff --git a/source/Tools.MetaDataProcessor/Various.cpp b/source/native/Tools.MetaDataProcessor/Various.cpp similarity index 100% rename from source/Tools.MetaDataProcessor/Various.cpp rename to source/native/Tools.MetaDataProcessor/Various.cpp diff --git a/source/Tools.MetaDataProcessor/WatchAssemblyBuilder.h b/source/native/Tools.MetaDataProcessor/WatchAssemblyBuilder.h similarity index 100% rename from source/Tools.MetaDataProcessor/WatchAssemblyBuilder.h rename to source/native/Tools.MetaDataProcessor/WatchAssemblyBuilder.h diff --git a/source/Tools.MetaDataProcessor/XmlUtil.cpp b/source/native/Tools.MetaDataProcessor/XmlUtil.cpp similarity index 100% rename from source/Tools.MetaDataProcessor/XmlUtil.cpp rename to source/native/Tools.MetaDataProcessor/XmlUtil.cpp diff --git a/source/Tools.MetaDataProcessor/cor.h b/source/native/Tools.MetaDataProcessor/cor.h similarity index 100% rename from source/Tools.MetaDataProcessor/cor.h rename to source/native/Tools.MetaDataProcessor/cor.h diff --git a/source/Tools.MetaDataProcessor/corerror.h b/source/native/Tools.MetaDataProcessor/corerror.h similarity index 100% rename from source/Tools.MetaDataProcessor/corerror.h rename to source/native/Tools.MetaDataProcessor/corerror.h diff --git a/source/Tools.MetaDataProcessor/corhdr.h b/source/native/Tools.MetaDataProcessor/corhdr.h similarity index 100% rename from source/Tools.MetaDataProcessor/corhdr.h rename to source/native/Tools.MetaDataProcessor/corhdr.h diff --git a/source/Tools.MetaDataProcessor/corhlpr.h b/source/native/Tools.MetaDataProcessor/corhlpr.h similarity index 100% rename from source/Tools.MetaDataProcessor/corhlpr.h rename to source/native/Tools.MetaDataProcessor/corhlpr.h diff --git a/source/Tools.MetaDataProcessor/corlib_native.cpp b/source/native/Tools.MetaDataProcessor/corlib_native.cpp similarity index 100% rename from source/Tools.MetaDataProcessor/corlib_native.cpp rename to source/native/Tools.MetaDataProcessor/corlib_native.cpp diff --git a/source/Tools.MetaDataProcessor/corsym.h b/source/native/Tools.MetaDataProcessor/corsym.h similarity index 100% rename from source/Tools.MetaDataProcessor/corsym.h rename to source/native/Tools.MetaDataProcessor/corsym.h diff --git a/source/Tools.MetaDataProcessor/minheap.cpp b/source/native/Tools.MetaDataProcessor/minheap.cpp similarity index 100% rename from source/Tools.MetaDataProcessor/minheap.cpp rename to source/native/Tools.MetaDataProcessor/minheap.cpp diff --git a/source/Tools.MetaDataProcessor/mintime.cpp b/source/native/Tools.MetaDataProcessor/mintime.cpp similarity index 100% rename from source/Tools.MetaDataProcessor/mintime.cpp rename to source/native/Tools.MetaDataProcessor/mintime.cpp diff --git a/source/Tools.MetaDataProcessor/nanoFramework.Tools.MetaDataProcessor.sln b/source/native/Tools.MetaDataProcessor/nanoFramework.Tools.MetaDataProcessor.sln similarity index 100% rename from source/Tools.MetaDataProcessor/nanoFramework.Tools.MetaDataProcessor.sln rename to source/native/Tools.MetaDataProcessor/nanoFramework.Tools.MetaDataProcessor.sln diff --git a/source/native/Tools.MetaDataProcessor/nanoFramework.Tools.MetaDataProcessor.targets b/source/native/Tools.MetaDataProcessor/nanoFramework.Tools.MetaDataProcessor.targets new file mode 100644 index 00000000..ebda3f9c --- /dev/null +++ b/source/native/Tools.MetaDataProcessor/nanoFramework.Tools.MetaDataProcessor.targets @@ -0,0 +1,10 @@ + + + + MSBuild + nanoFramework\v1.0\ + Always + true + + + diff --git a/source/Tools.MetaDataProcessor/nanoHAL_Watchdog_stubs.cpp b/source/native/Tools.MetaDataProcessor/nanoHAL_Watchdog_stubs.cpp similarity index 100% rename from source/Tools.MetaDataProcessor/nanoHAL_Watchdog_stubs.cpp rename to source/native/Tools.MetaDataProcessor/nanoHAL_Watchdog_stubs.cpp diff --git a/source/Tools.MetaDataProcessor/package.nuspec b/source/native/Tools.MetaDataProcessor/package.nuspec similarity index 100% rename from source/Tools.MetaDataProcessor/package.nuspec rename to source/native/Tools.MetaDataProcessor/package.nuspec diff --git a/source/Tools.MetaDataProcessor/packages.config b/source/native/Tools.MetaDataProcessor/packages.config similarity index 100% rename from source/Tools.MetaDataProcessor/packages.config rename to source/native/Tools.MetaDataProcessor/packages.config diff --git a/source/Tools.MetaDataProcessor/stdafx.cpp b/source/native/Tools.MetaDataProcessor/stdafx.cpp similarity index 100% rename from source/Tools.MetaDataProcessor/stdafx.cpp rename to source/native/Tools.MetaDataProcessor/stdafx.cpp diff --git a/source/Tools.MetaDataProcessor/stdafx.h b/source/native/Tools.MetaDataProcessor/stdafx.h similarity index 100% rename from source/Tools.MetaDataProcessor/stdafx.h rename to source/native/Tools.MetaDataProcessor/stdafx.h diff --git a/source/Tools.MetaDataProcessor/targetver.h b/source/native/Tools.MetaDataProcessor/targetver.h similarity index 100% rename from source/Tools.MetaDataProcessor/targetver.h rename to source/native/Tools.MetaDataProcessor/targetver.h diff --git a/source/Tools.Parser/AssemblyParser.cpp b/source/native/Tools.Parser/AssemblyParser.cpp similarity index 99% rename from source/Tools.Parser/AssemblyParser.cpp rename to source/native/Tools.Parser/AssemblyParser.cpp index 548f6bb5..2e38c873 100644 --- a/source/Tools.Parser/AssemblyParser.cpp +++ b/source/native/Tools.Parser/AssemblyParser.cpp @@ -825,6 +825,13 @@ bool MetaData::FieldDef::SetValue( const void* ptr, int len ) return true; } +bool MetaData::FieldDef::SetEmptyString(const void* ptr) +{ + m_value.resize(0); + + return true; +} + MetaData::MethodDef::MethodDef( Parser* holder ) : m_method(holder), m_vars(holder) { m_td = mdTypeDefNil; // mdTypeDef m_td; @@ -1630,9 +1637,24 @@ HRESULT MetaData::Parser::GetTypeField( mdFieldDef fd ) } if(pValue) - { - _ASSERTE(len > 0); - db.SetValue( pValue, len ); + { + // only ASSERT for non strings because it's acceptable to have strings with 0 length + if (db.m_attr == ELEMENT_TYPE_STRING) + { + if (len == 0) + { + db.SetEmptyString(pValue); + } + else + { + db.SetValue(pValue, len); + } + } + else + { + _ASSERTE(len > 0); + db.SetValue(pValue, len); + } } m_mapDef_Field.insert( FieldDefMap::value_type( fd, db ) ); diff --git a/source/Tools.Parser/AssemblyParserDump.cpp b/source/native/Tools.Parser/AssemblyParserDump.cpp similarity index 100% rename from source/Tools.Parser/AssemblyParserDump.cpp rename to source/native/Tools.Parser/AssemblyParserDump.cpp diff --git a/source/Tools.Parser/AssemblyReparser.cpp b/source/native/Tools.Parser/AssemblyReparser.cpp similarity index 100% rename from source/Tools.Parser/AssemblyReparser.cpp rename to source/native/Tools.Parser/AssemblyReparser.cpp diff --git a/source/Tools.Parser/ByteCodeParser.cpp b/source/native/Tools.Parser/ByteCodeParser.cpp similarity index 100% rename from source/Tools.Parser/ByteCodeParser.cpp rename to source/native/Tools.Parser/ByteCodeParser.cpp diff --git a/source/Tools.Parser/ByteCodeParser_Load.cpp b/source/native/Tools.Parser/ByteCodeParser_Load.cpp similarity index 100% rename from source/Tools.Parser/ByteCodeParser_Load.cpp rename to source/native/Tools.Parser/ByteCodeParser_Load.cpp diff --git a/source/Tools.Parser/ByteCodeParser_Save.cpp b/source/native/Tools.Parser/ByteCodeParser_Save.cpp similarity index 100% rename from source/Tools.Parser/ByteCodeParser_Save.cpp rename to source/native/Tools.Parser/ByteCodeParser_Save.cpp diff --git a/source/native/Tools.Parser/Debug/Tools.Lib.Parser.idb b/source/native/Tools.Parser/Debug/Tools.Lib.Parser.idb new file mode 100644 index 00000000..1218f0e3 Binary files /dev/null and b/source/native/Tools.Parser/Debug/Tools.Lib.Parser.idb differ diff --git a/source/native/Tools.Parser/Debug/Tools.Lib.Parser.tlog/CL.command.1.tlog b/source/native/Tools.Parser/Debug/Tools.Lib.Parser.tlog/CL.command.1.tlog new file mode 100644 index 00000000..bf0e7c27 Binary files /dev/null and b/source/native/Tools.Parser/Debug/Tools.Lib.Parser.tlog/CL.command.1.tlog differ diff --git a/source/Tools.Parser/Debug/Tools.Lib.Parser.tlog/CL.read.1.tlog b/source/native/Tools.Parser/Debug/Tools.Lib.Parser.tlog/CL.read.1.tlog similarity index 84% rename from source/Tools.Parser/Debug/Tools.Lib.Parser.tlog/CL.read.1.tlog rename to source/native/Tools.Parser/Debug/Tools.Lib.Parser.tlog/CL.read.1.tlog index bb6c169e..c95bb788 100644 Binary files a/source/Tools.Parser/Debug/Tools.Lib.Parser.tlog/CL.read.1.tlog and b/source/native/Tools.Parser/Debug/Tools.Lib.Parser.tlog/CL.read.1.tlog differ diff --git a/source/native/Tools.Parser/Debug/Tools.Lib.Parser.tlog/CL.write.1.tlog b/source/native/Tools.Parser/Debug/Tools.Lib.Parser.tlog/CL.write.1.tlog new file mode 100644 index 00000000..e220eaa6 Binary files /dev/null and b/source/native/Tools.Parser/Debug/Tools.Lib.Parser.tlog/CL.write.1.tlog differ diff --git a/source/native/Tools.Parser/Debug/Tools.Lib.Parser.tlog/Lib-link.read.1.tlog b/source/native/Tools.Parser/Debug/Tools.Lib.Parser.tlog/Lib-link.read.1.tlog new file mode 100644 index 00000000..63bac243 Binary files /dev/null and b/source/native/Tools.Parser/Debug/Tools.Lib.Parser.tlog/Lib-link.read.1.tlog differ diff --git a/source/native/Tools.Parser/Debug/Tools.Lib.Parser.tlog/Lib-link.write.1.tlog b/source/native/Tools.Parser/Debug/Tools.Lib.Parser.tlog/Lib-link.write.1.tlog new file mode 100644 index 00000000..28d0cf25 Binary files /dev/null and b/source/native/Tools.Parser/Debug/Tools.Lib.Parser.tlog/Lib-link.write.1.tlog differ diff --git a/source/native/Tools.Parser/Debug/Tools.Lib.Parser.tlog/Lib.command.1.tlog b/source/native/Tools.Parser/Debug/Tools.Lib.Parser.tlog/Lib.command.1.tlog new file mode 100644 index 00000000..0f724b67 Binary files /dev/null and b/source/native/Tools.Parser/Debug/Tools.Lib.Parser.tlog/Lib.command.1.tlog differ diff --git a/source/Tools.Parser/Debug/Tools.Lib.Parser.tlog/Tools.Lib.Parser.lastbuildstate b/source/native/Tools.Parser/Debug/Tools.Lib.Parser.tlog/Tools.Lib.Parser.lastbuildstate similarity index 70% rename from source/Tools.Parser/Debug/Tools.Lib.Parser.tlog/Tools.Lib.Parser.lastbuildstate rename to source/native/Tools.Parser/Debug/Tools.Lib.Parser.tlog/Tools.Lib.Parser.lastbuildstate index 34f2059c..d9067f79 100644 --- a/source/Tools.Parser/Debug/Tools.Lib.Parser.tlog/Tools.Lib.Parser.lastbuildstate +++ b/source/native/Tools.Parser/Debug/Tools.Lib.Parser.tlog/Tools.Lib.Parser.lastbuildstate @@ -1,2 +1,2 @@ #TargetFrameworkVersion=v4.0:PlatformToolSet=v141:EnableManagedIncrementalBuild=false:VCToolArchitecture=Native32Bit:WindowsTargetPlatformVersion=10.0.17763.0 -Debug|Win32|E:\GitHub\nf-tool-metadata-processor\source\| +Debug|Win32|E:\GitHub\nf-tool-metadata-processor\source\native\| diff --git a/source/Tools.Parser/FileStore_Win32.cpp b/source/native/Tools.Parser/FileStore_Win32.cpp similarity index 100% rename from source/Tools.Parser/FileStore_Win32.cpp rename to source/native/Tools.Parser/FileStore_Win32.cpp diff --git a/source/Tools.Parser/Linker.cpp b/source/native/Tools.Parser/Linker.cpp similarity index 100% rename from source/Tools.Parser/Linker.cpp rename to source/native/Tools.Parser/Linker.cpp diff --git a/source/Tools.Parser/Parser-vs2019.vcxproj b/source/native/Tools.Parser/Parser-vs2019.vcxproj similarity index 91% rename from source/Tools.Parser/Parser-vs2019.vcxproj rename to source/native/Tools.Parser/Parser-vs2019.vcxproj index c96e0a27..389c3213 100644 --- a/source/Tools.Parser/Parser-vs2019.vcxproj +++ b/source/native/Tools.Parser/Parser-vs2019.vcxproj @@ -58,7 +58,7 @@ Disabled - ..\Tools.MetaDataProcessor;..\Tools.Parser;..\..\nf-interpreter\src\CLR\CorLib;..\..\nf-interpreter\targets\os\win32\Include;..\..\nf-interpreter\src\PAL\Include;..\..\nf-interpreter\src\HAL\Include;..\..\nf-interpreter\src\CLR\Include;%(AdditionalIncludeDirectories) + ..\Tools.MetaDataProcessor;..\Tools.Parser;..\nf-interpreter\src\CLR\CorLib;..\nf-interpreter\targets\os\win32\Include;..\nf-interpreter\src\PAL\Include;..\nf-interpreter\src\HAL\Include;..\nf-interpreter\src\CLR\Include;%(AdditionalIncludeDirectories) WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) true EnableFastChecks @@ -76,7 +76,7 @@ MaxSpeed OnlyExplicitInline true - ..\Tools.MetaDataProcessor;..\Tools.Parser;..\..\nf-interpreter\src\CLR\CorLib;..\..\nf-interpreter\targets\os\win32\Include;..\..\nf-interpreter\src\PAL\Include;..\..\nf-interpreter\src\HAL\Include;..\..\nf-interpreter\src\CLR\Include;%(AdditionalIncludeDirectories) + ..\Tools.MetaDataProcessor;..\Tools.Parser;..\nf-interpreter\src\CLR\CorLib;..\nf-interpreter\targets\os\win32\Include;..\nf-interpreter\src\PAL\Include;..\nf-interpreter\src\HAL\Include;..\nf-interpreter\src\CLR\Include;%(AdditionalIncludeDirectories) WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) true MultiThreadedDLL diff --git a/source/Tools.Parser/Parser-vs2019.vcxproj.filters b/source/native/Tools.Parser/Parser-vs2019.vcxproj.filters similarity index 100% rename from source/Tools.Parser/Parser-vs2019.vcxproj.filters rename to source/native/Tools.Parser/Parser-vs2019.vcxproj.filters diff --git a/source/Tools.Parser/Parser.vcxproj b/source/native/Tools.Parser/Parser.vcxproj similarity index 91% rename from source/Tools.Parser/Parser.vcxproj rename to source/native/Tools.Parser/Parser.vcxproj index 66d6f637..2a1e56f5 100644 --- a/source/Tools.Parser/Parser.vcxproj +++ b/source/native/Tools.Parser/Parser.vcxproj @@ -58,7 +58,7 @@ Disabled - ..\Tools.MetaDataProcessor;..\Tools.Parser;..\..\nf-interpreter\src\CLR\CorLib;..\..\nf-interpreter\targets\os\win32\Include;..\..\nf-interpreter\src\PAL\Include;..\..\nf-interpreter\src\HAL\Include;..\..\nf-interpreter\src\CLR\Include;%(AdditionalIncludeDirectories) + ..\Tools.MetaDataProcessor;..\Tools.Parser;..\nf-interpreter\src\CLR\CorLib;..\nf-interpreter\targets\os\win32\Include;..\nf-interpreter\src\PAL\Include;..\nf-interpreter\src\HAL\Include;..\nf-interpreter\src\CLR\Include;%(AdditionalIncludeDirectories) WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) true EnableFastChecks @@ -76,7 +76,7 @@ MaxSpeed OnlyExplicitInline true - ..\Tools.MetaDataProcessor;..\Tools.Parser;..\..\nf-interpreter\src\CLR\CorLib;..\..\nf-interpreter\targets\os\win32\Include;..\..\nf-interpreter\src\PAL\Include;..\..\nf-interpreter\src\HAL\Include;..\..\nf-interpreter\src\CLR\Include;%(AdditionalIncludeDirectories) + ..\Tools.MetaDataProcessor;..\Tools.Parser;..\nf-interpreter\src\CLR\CorLib;..\nf-interpreter\targets\os\win32\Include;..\nf-interpreter\src\PAL\Include;..\nf-interpreter\src\HAL\Include;..\nf-interpreter\src\CLR\Include;%(AdditionalIncludeDirectories) WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) true MultiThreadedDLL diff --git a/source/Tools.Parser/Parser.vcxproj.filters b/source/native/Tools.Parser/Parser.vcxproj.filters similarity index 100% rename from source/Tools.Parser/Parser.vcxproj.filters rename to source/native/Tools.Parser/Parser.vcxproj.filters diff --git a/source/Tools.Parser/Support.cpp b/source/native/Tools.Parser/Support.cpp similarity index 100% rename from source/Tools.Parser/Support.cpp rename to source/native/Tools.Parser/Support.cpp diff --git a/source/Tools.Parser/dotNetMF.proj b/source/native/Tools.Parser/dotNetMF.proj similarity index 100% rename from source/Tools.Parser/dotNetMF.proj rename to source/native/Tools.Parser/dotNetMF.proj diff --git a/source/Tools.Parser/stdafx.cpp b/source/native/Tools.Parser/stdafx.cpp similarity index 100% rename from source/Tools.Parser/stdafx.cpp rename to source/native/Tools.Parser/stdafx.cpp diff --git a/source/Tools.Parser/stdafx.h b/source/native/Tools.Parser/stdafx.h similarity index 100% rename from source/Tools.Parser/stdafx.h rename to source/native/Tools.Parser/stdafx.h diff --git a/source/native/nanoFramework.Tools.MetadataProcessor.sln b/source/native/nanoFramework.Tools.MetadataProcessor.sln new file mode 100644 index 00000000..c4c770e9 --- /dev/null +++ b/source/native/nanoFramework.Tools.MetadataProcessor.sln @@ -0,0 +1,206 @@ +Microsoft Visual Studio Solution File, Format Version 12.00 +# Visual Studio 15 +VisualStudioVersion = 15.0.27130.2027 +MinimumVisualStudioVersion = 10.0.40219.1 +Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "MetaDataProcessor", "MetaDataProcessor", "{FCCC9596-0809-4BB4-ACC2-3615EEC264C7}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Core", "nf-interpreter\src\CLR\Core\Core.vcxproj", "{89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "CorLib", "nf-interpreter\src\CLR\CorLib\CorLib.vcxproj", "{58E950CC-2FF6-423C-B006-A70A19272F20}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Diagnostics", "nf-interpreter\src\CLR\Diagnostics\Diagnostics.vcxproj", "{A5E9AE41-F4FA-40CE-AD82-A7861EBA007B}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Tools.Lib.Parser", "Tools.Parser\Parser.vcxproj", "{AB1ED6AC-5C7F-49CD-A84B-4B7362D355BC}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Serialization", "nf-interpreter\src\CLR\Core\Serialization\Serialization.vcxproj", "{16BF6131-A3B8-4B97-B867-E45669FB48BD}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "RPC", "nf-interpreter\src\CLR\Core\RPC\RPC.vcxproj", "{ED4C887A-EC09-465B-B5D9-075450ADC52D}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Messaging", "nf-interpreter\src\CLR\Messaging\Messaging.vcxproj", "{131001E3-0201-451F-A87B-951D1C5C3EEE}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "WireProtocol", "nf-interpreter\src\CLR\WireProtocol\WireProtocol.vcxproj", "{2337C4A4-3AB4-4014-9C29-9EBE32F4510E}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Hardware", "nf-interpreter\src\CLR\Core\Hardware\Hardware.vcxproj", "{5D50772E-DAC8-407D-972F-37DEB4450B72}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Tools.Lib.CorHelper", "Tools.CorHelper\CorHelper.vcxproj", "{079E1BC1-3B21-46E8-B1BA-AEDB68CCDC11}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "InterruptHandler", "nf-interpreter\src\CLR\Core\InterruptHandler\InterruptHandler.vcxproj", "{D32EE397-7E49-452D-AC95-AFCB3C962E3D}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Tools.MetaDataProcessor", "Tools.MetaDataProcessor\MetaDataProcessor.vcxproj", "{80209A7E-B9F0-4143-BCD1-B1891236A3CF}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|Any CPU = Debug|Any CPU + Debug|x64 = Debug|x64 + Debug|x86 = Debug|x86 + Release|Any CPU = Release|Any CPU + Release|x64 = Release|x64 + Release|x86 = Release|x86 + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}.Debug|Any CPU.ActiveCfg = Debug|Win32 + {89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}.Debug|Any CPU.Build.0 = Debug|Win32 + {89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}.Debug|x64.ActiveCfg = Debug|x64 + {89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}.Debug|x64.Build.0 = Debug|x64 + {89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}.Debug|x86.ActiveCfg = Debug|Win32 + {89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}.Debug|x86.Build.0 = Debug|Win32 + {89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}.Release|Any CPU.ActiveCfg = Release|Win32 + {89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}.Release|Any CPU.Build.0 = Release|Win32 + {89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}.Release|x64.ActiveCfg = Release|x64 + {89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}.Release|x64.Build.0 = Release|x64 + {89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}.Release|x86.ActiveCfg = Release|Win32 + {89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}.Release|x86.Build.0 = Release|Win32 + {58E950CC-2FF6-423C-B006-A70A19272F20}.Debug|Any CPU.ActiveCfg = Debug|Win32 + {58E950CC-2FF6-423C-B006-A70A19272F20}.Debug|Any CPU.Build.0 = Debug|Win32 + {58E950CC-2FF6-423C-B006-A70A19272F20}.Debug|x64.ActiveCfg = Debug|x64 + {58E950CC-2FF6-423C-B006-A70A19272F20}.Debug|x64.Build.0 = Debug|x64 + {58E950CC-2FF6-423C-B006-A70A19272F20}.Debug|x86.ActiveCfg = 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EndGlobalSection + GlobalSection(ExtensibilityGlobals) = postSolution + SolutionGuid = {5DF99A8C-CA3C-451A-ABC1-4D862154708B} + EndGlobalSection +EndGlobal diff --git a/source/native/nf-interpreter/.github/FUNDING.yml b/source/native/nf-interpreter/.github/FUNDING.yml new file mode 100644 index 00000000..d2b838f9 --- /dev/null +++ b/source/native/nf-interpreter/.github/FUNDING.yml @@ -0,0 +1,2 @@ +#github: # Replace with up to 4 GitHub Sponsors-enabled usernames e.g., [user1, user2] +open_collective: nanoframework diff --git a/source/native/nf-interpreter/.github/ISSUE_TEMPLATE.md b/source/native/nf-interpreter/.github/ISSUE_TEMPLATE.md new file mode 100644 index 00000000..ce54f609 --- /dev/null +++ b/source/native/nf-interpreter/.github/ISSUE_TEMPLATE.md @@ -0,0 +1,4 @@ +# Please **DO NOT** open issues in this repository. + + +We are now using the Home repository for centralized issue management. diff --git a/source/native/nf-interpreter/.github/PULL_REQUEST_TEMPLATE.md b/source/native/nf-interpreter/.github/PULL_REQUEST_TEMPLATE.md new file mode 100644 index 00000000..0f768fce --- /dev/null +++ b/source/native/nf-interpreter/.github/PULL_REQUEST_TEMPLATE.md @@ -0,0 +1,36 @@ + + +## Description + + +## Motivation and Context + + +- Fixes/Closes/Resolves nanoFramework/Home#NNNN + +## How Has This Been Tested? + + + + +## Screenshots + +## Types of changes + +- [ ] Improvement (non-breaking change that improves a feature, code or algorithm) +- [ ] Bug fix (non-breaking change which fixes an issue) +- [ ] New feature (non-breaking change which adds functionality) +- [ ] Breaking change (fix or feature that would cause existing functionality to change) + +## Checklist: + + +- [ ] My code follows the code style of this project. +- [ ] My change requires a change to the documentation. +- [ ] I have updated the documentation accordingly. +- [ ] I have read the **CONTRIBUTING** document. +- [ ] I have added tests to cover my changes. +- [ ] All new and existing tests passed. + + +Signed-off-by: GITHUB_USER diff --git a/source/native/nf-interpreter/.github/stale.yml b/source/native/nf-interpreter/.github/stale.yml new file mode 100644 index 00000000..8cf7da36 --- /dev/null +++ b/source/native/nf-interpreter/.github/stale.yml @@ -0,0 +1,19 @@ +# Number of days of inactivity before an issue becomes stale +daysUntilStale: 60 + +# Number of days of inactivity before a stale issue is closed +daysUntilClose: 7 + +# Issues with these labels will never be considered stale +exemptLabels: + - :pushpin: pinned + - security + +# Label to use when marking an issue as stale +staleLabel: stale + +# Comment to post when marking an issue as stale. Set to `false` to disable +markComment: > + This issue has been automatically marked as stale because it has not had + recent activity. It will be closed if no further activity occurs. Thank you + for your contributions. diff --git a/source/native/nf-interpreter/.github_changelog_generator b/source/native/nf-interpreter/.github_changelog_generator new file mode 100644 index 00000000..f39e1766 --- /dev/null +++ b/source/native/nf-interpreter/.github_changelog_generator @@ -0,0 +1,14 @@ +user=nanoframework +project=nf-interpreter +issues=true +add_issues_wo_labels=false +add_pr_wo_labels=false +add_issues_wo_labels=false +filter_issues_by_milestone=false +exclude_labels=Area: Config-and-Build,Area: Infrastructure-and-Organization,reverted +enhancement_labels=Type: enhancement +bug_labels=Type: bug +merge_prefix=**Documentation and other chores:** +unreleased_label=**Changes available only in 'Preview' images:** +issue_line_labels=Area: ESP32,Area: STM32-ChibiOS,Area: WIN32,Area: Interpreter,Area: Common libs,Breaking-Change,documentation +author=false diff --git a/source/native/nf-interpreter/.gitignore b/source/native/nf-interpreter/.gitignore new file mode 100644 index 00000000..f279299b --- /dev/null +++ b/source/native/nf-interpreter/.gitignore @@ -0,0 +1,63 @@ +# ignore all ZIP files +*.zip +/zips/ + +# ignore build folder +/build/ +/build/.gitkeep + +# ignore cmake-variants file (will change frequently per user/board setup, use should derive content from cmake-variants.TEMPLATE.json) +cmake-variants.json + +# ignore any content inside the Interop assemblies folder +InteropAssemblies/* +!InteropAssemblies/CLR_RT_InteropAssembliesTable.cpp.in +!InteropAssemblies/README.md + +# Visual Studio Code +# ignore C/C++ launch file (will change frequently per user/board setup, use should derive content from launch.TEMPLATE.json) +.vscode/launch.json +.vscode/.cmaketools.json +.vscode/settings.json +.vscode/tasks.json +.vscode/extensions.json +.vscode/c_cpp_properties.json +.vscode/cmake-kits.json +.vscode/ipch + +# ignore CMake modules for Interop assemblies +CMake/Modules/FindINTEROP*.cmake + +# Visual Studio +## Ignore Visual Studio temporary files, build results, and +## files generated by popular Visual Studio add-ons. +## +## Get latest from https://github.com/github/gitignore/blob/master/VisualStudio.gitignore + +# User-specific files +*.suo +*.user + +# Build results +[Dd]ebug/ +[Rr]elease/ +[Rr]eleases/ +[Bb]in/ +[Oo]bj/ + +# Visual Studio cache/options directory contents but not the example launch.vs.json +!.vs/ +.vs/* +!.vs/launch.vs.SAMPLE.json +!.vs/tasks.vs.SAMPLE.json +**/ipch/* + +# Visual C++ cache files +*.VC.db + +# NuGet Packages +*.nupkg +# The packages folder can be ignored because of Package Restore +**/packages/* +# except build/, which is used as an MSBuild target. +!**/packages/build/ diff --git a/source/native/nf-interpreter/.gitmodules b/source/native/nf-interpreter/.gitmodules new file mode 100644 index 00000000..c8fe6c8e --- /dev/null +++ b/source/native/nf-interpreter/.gitmodules @@ -0,0 +1,3 @@ +[submodule "targets-community"] + path = targets-community + url = https://github.com/nanoframework/nf-Community-Targets diff --git a/source/native/nf-interpreter/.vs/launch.vs.SAMPLE.json b/source/native/nf-interpreter/.vs/launch.vs.SAMPLE.json new file mode 100644 index 00000000..c945015d --- /dev/null +++ b/source/native/nf-interpreter/.vs/launch.vs.SAMPLE.json @@ -0,0 +1,90 @@ +{ + "version": "0.2.1", + "defaults": {}, + "configurations": [ + { + "type": "cppdbg", + "name": "ESP32 nanoCLR - Segger JLink", + "project": "Build/ESP32/nanoCLR.elf", + "cwd": "${workspaceRoot}", + "program": "Build/ESP32/nanoCLR.elf", + "MIMode": "gdb", + "stopAtEntry": false, + "externalConsole": true, + "miDebuggerPath": "C:/Esp32_Tools/xtensa-esp32-elf/bin/xtensa-esp32-elf-gdb.exe", + "setupCommands": [ + { + "text": "set logging on" + }, + { + "text": "!${workspaceRoot}/startocd.bat ESP32_JLINK" + }, + { + "text": "target extended-remote localhost:3333" + }, + { + "text": "-file-exec-and-symbols C:/usr/src/NanoFramework/nf-interpreter/build/ESP32/nanoCLR.elf" + }, + { + "text": "set remote hardware-watchpoint-limit 2" + }, + { + "text": "monitor reset halt" + }, + { + "text": "flushregs" + }, + { + "text": "thb app_main" + } + ], + "launchCompleteCommand": "None", + "serverStarted": "Info : .*Tensilica.*0x1.", + "filterStderr": true, + "filterStdout": true + }, + { + "type": "cppdbg", + "name": "STM769IDiscovery nanobooter.elf", + "project": "Build\\STM769IDiscovery\\nanobooter.elf", + "cwd": "${workspaceRoot}", + "program": "${workspaceRoot}\\BUILD\\STM769IDiscovery\\nanobooter.elf", + "MIMode": "gdb", + "externalConsole": true, + "miDebuggerPath": "C:\\Program Files (x86)\\Microsoft Visual Studio\\2017\\Community\\Linux\\gcc_arm\\bin\\arm-none-eabi-gdb.exe", + "setupCommands": [ + { + "text": "-environment-cd ${workspaceRoot}\\Build" + }, + { + "text": "!${workspaceRoot}/startocd.bat STM32_STLINK" + }, + { + "text": "target extended-remote localhost:3333" + }, + { + "text": "-file-exec-and-symbols C:/usr/src/NanoFramework/nf-interpreter/build/STM769IDiscovery/nanobooter.elf" + }, + { + "text": "-enable-pretty-printing", + "ignoreFailures": true + }, + { + "text": "monitor reset_config none separate" + }, + { + "text": "monitor reset halt" + } + ], + "serverStarted": "Info\\ :\\ [\\w\\d\\.]*:\\ hardware", + "filterStderr": true, + "filterStdout": true + }, + { + "type": "default", + "project": "CMakeLists.txt", + "projectTarget": "nanoCLR.elf", + "name": "nanoCLR.elf" + } + ] +} \ No newline at end of file diff --git a/source/native/nf-interpreter/.vs/tasks.vs.SAMPLE.json b/source/native/nf-interpreter/.vs/tasks.vs.SAMPLE.json new file mode 100644 index 00000000..8f5031ca --- /dev/null +++ b/source/native/nf-interpreter/.vs/tasks.vs.SAMPLE.json @@ -0,0 +1,76 @@ +{ + "version": "0.2.1", + "outDir": "Build\\${cpp.activeConfiguration}", + "port": "\"COM3\"", + "esptool": "python ${env.ESP32_IDF_PATH}/components/esptool_py/esptool/esptool.py", + "comment": "This is a comment", + "tasks": [ + { + "taskLabel": "task-CMakeLists", + "appliesTo": "CMakeLists.txt", + "type": "launch" + }, + { + "taskLabel": "task-nf-interpreter", + "appliesTo": "/", + "type": "launch" + }, + { + "taskLabel": "Print Output Directory", + "appliesTo": "*", + "type": "default", + "command": "${env.COMSPEC}", + "args": [ + "echo Output Directory: ${outDir} " + ] + }, + { + "taskLabel": "Erase Flash ESP32 on port ${port}", + "appliesTo": "*", + "type": "default", + "command": "${env.COMSPEC}", + "args": [ + "start \"Erasing Flash ESP32 on ${port}\" /wait runcmd -5", + "${esptool} --chip esp32 --port ${port} --baud 115200 --before \"default_reset\" --after \"hard_reset\" erase_flash" + ] + }, + { + "taskLabel": "Flash nanoCLR ESP32 on port ${port}", + "appliesTo": "*", + "type": "default", + "command": "${env.COMSPEC}", + "args": [ + "start \"ESP32 - Flashing nanoCLR ESP32 on port ${port}\" /wait runcmd -5", + "${esptool} --chip esp32 --port ${port} --baud 921600 --before \"default_reset\" --after \"hard_reset\" write_flash -z --flash_mode \"dio\" --flash_freq \"40m\" --flash_size detect 0x1000 ${env.ESP32_LIBS_PATH}/bootloader.bin 0x10000 ${outDir}/nanoCLR.bin 0x8000 ${outDir}/partitions_4mb.bin" + ] + }, + { + "taskLabel": "Erase Flash ESP32 port ${port} (Working auto-program)", + "appliesTo": "*", + "type": "default", + "command": "${env.COMSPEC}", + "args": [ + "${esptool} --chip esp32 --port ${port} --baud 921600 --before \"default_reset\" --after \"hard_reset\" erase_flash" + ] + }, + { + "taskLabel": "task-GetShortPath", + "appliesTo": "GetShortPath.bat", + "type": "launch" + }, + { + "taskName": "task-README", + "appliesTo": "README.md", + "type": "launch" + }, + { + "taskName": "task-SetNFRoot", + "appliesTo": "SetNFRoot.bat", + "type": "default", + "command": "${env.COMSPEC}", + "args": [ + "SetNFRoot.bat" + ] + } + ] +} \ No newline at end of file diff --git a/source/native/nf-interpreter/.vscode/cmake-kits.TEMPLATE-ESP32.json b/source/native/nf-interpreter/.vscode/cmake-kits.TEMPLATE-ESP32.json new file mode 100644 index 00000000..cbcba892 --- /dev/null +++ b/source/native/nf-interpreter/.vscode/cmake-kits.TEMPLATE-ESP32.json @@ -0,0 +1,6 @@ +[ + { + "name": "ESP32 Tools", + "toolchainFile": "CMake/toolchain.FreeRtos.ESP32.GCC.cmake" + } +] \ No newline at end of file diff --git a/source/native/nf-interpreter/.vscode/launch.TEMPLATE-ESP32.json b/source/native/nf-interpreter/.vscode/launch.TEMPLATE-ESP32.json new file mode 100644 index 00000000..c5a8ed25 --- /dev/null +++ b/source/native/nf-interpreter/.vscode/launch.TEMPLATE-ESP32.json @@ -0,0 +1,76 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "ESP32 nanoCLR - OLimex OCD-H", + "type": "cppdbg", + "request": "launch", + "MIMode": "gdb", + "miDebuggerPath": "/xtensa-esp32-elf/bin/xtensa-esp32-elf-gdb.exe", + "stopAtEntry":true, + "program": "/nanoCLR.elf", + + "setupCommands": [ + {"description":"" , "text" : "set logging on"}, + {"description":"" , "text" : "target extended-remote localhost:3333"}, + {"description":"" , "text" : "file /nanoCLR.elf"}, + {"description":"" , "text" : "monitor reset halt"}, + {"description":"" , "text" : "thb app_main"}, + {"description":"" , "text" : "x $a1=0"} + ], + + "launchCompleteCommand": "exec-run", + "debugServerPath": "/bin/openocd.exe", + "debugServerArgs": "-s \"/share/openocd/scripts/\" -f interface/ftdi/olimex-arm-usb-ocd-h.cfg -f target/esp32.cfg -c \"adapter_khz 3000\" " , + "serverStarted": "Info : .*Tensilica.*0x1.", + "filterStderr": true, + "externalConsole": true, + "cwd": "${cwd}", + + "logging": { + "trace": true, + "traceResponse": true, + "engineLogging": true, + "programOutput": true, + "exceptions": true, + "moduleLoad": true + } + }, + { + "name": "ESP32 nanoCLR - Wrover", + "type": "cppdbg", + "request": "launch", + "MIMode": "gdb", + "miDebuggerPath": "/xtensa-esp32-elf/bin/xtensa-esp32-elf-gdb.exe", + "stopAtEntry":true, + "program": "/nanoCLR.elf", + + "setupCommands": [ + {"description":"" , "text" : "set logging on"}, + {"description":"" , "text" : "target extended-remote localhost:3333"}, + {"description":"" , "text" : "file /nanoCLR.elf"}, + {"description":"" , "text" : "monitor reset halt"}, + {"description":"" , "text" : "thb app_main"}, + {"description":"" , "text" : "x $a1=0"} + ], + + "launchCompleteCommand": "exec-run", + "debugServerPath": "/bin/openocd.exe", + "debugServerArgs": "-s \"/share/openocd/scripts/\" -f interface/ftdi/esp32_devkitj_v1.cfg -f target/esp32.cfg -c \"adapter_khz 2000\" " , + "serverStarted": "Info : .*Tensilica.*0x1.", + "filterStderr": true, + "externalConsole": true, + "cwd": "${cwd}", + + "logging": { + "trace": true, + "traceResponse": true, + "engineLogging": true, + "programOutput": true, + "exceptions": true, + "moduleLoad": true + } + } + + ] +} diff --git a/source/native/nf-interpreter/.vscode/launch.TEMPLATE.json b/source/native/nf-interpreter/.vscode/launch.TEMPLATE.json new file mode 100644 index 00000000..12bd0344 --- /dev/null +++ b/source/native/nf-interpreter/.vscode/launch.TEMPLATE.json @@ -0,0 +1,103 @@ +{ + "version": "0.2.0", + "configurations": [ + { + "name": "name the launch configuration 1 (booter) here", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "", + "targetArchitecture": "ARM", + "program": "/nanoBooter.elf", + + "setupCommands": [ + {"description":"" , "text" : "target extended-remote localhost:3333"}, + {"description":"" , "text" : "monitor reset_config none separate"}, + {"description":"" , "text" : "monitor reset halt"}, + {"description":"" , "text" : "monitor flash write_image erase \"/nanoBooter.hex\" "}, + {"description":"" , "text" : "file /nanoBooter.elf"}, + {"description":"" , "text" : "monitor reset halt"} + ], + + "customLaunchSetupCommands": [ + {"description":"" , "text" : "monitor reset_config none separate"}, + {"description":"" , "text" : "monitor reset halt"} + ], + + "launchCompleteCommand": "exec-continue", + "debugServerPath": "/bin/openocd.exe", + "debugServerArgs": "-s \"/share/openocd/scripts/\" -f interface/.cfg -f board/.cfg", + "serverStarted": "Info\\ :\\ [\\w\\d\\.]*:\\ hardware", + "filterStderr": true, + "externalConsole": true, + "cwd": "${cwd}", + // Enable the following to debug GDB + //"logging": { + // "engineLogging": true, + // "traceResponse": true + //}, + }, + + { + "name": "name the launch configuration 2 (CLR) here", + "type": "cppdbg", + "request": "launch", + "miDebuggerPath": "", + "targetArchitecture": "ARM", + "program": "/nanoCLR.elf", + + "setupCommands": [ + {"description":"" , "text" : "target extended-remote localhost:3333"}, + {"description":"" , "text" : "monitor reset_config none separate"}, + {"description":"" , "text" : "monitor reset halt"}, + {"description":"" , "text" : "monitor flash write_image erase \"/nanoCLR.hex\" "}, + {"description":"" , "text" : "file /nanoCLR.elf"}, + {"description":"" , "text" : "monitor reset halt"} + ], + + "customLaunchSetupCommands": [ + {"description":"" , "text" : "monitor reset_config none separate"}, + {"description":"" , "text" : "monitor reset halt"} + ], + + "launchCompleteCommand": "exec-continue", + "debugServerPath": "/bin/openocd.exe", + "debugServerArgs": "-s \"/share/openocd/scripts/\" -f interface/.cfg -f board/.cfg", + "serverStarted": "Info\\ :\\ [\\w\\d\\.]*:\\ hardware", + "filterStderr": true, + "externalConsole": true, + "cwd": "${cwd}" + // Enable the following to debug GDB + //"logging": { + // "engineLogging": true, + // "traceResponse": true + //}, + }, + + { + "MIMode": "gdb", + "name": "CC3200 Launchpad nanoCLR TEMPLATE", + "type": "cppdbg", + "request": "launch", + + "setupCommands": [ + {"description":"" , "text" : "target remote | e:/openocd-0.10.0/bin/openocd.exe -c \"gdb_port pipe; log_output openocd.log\" -f "}, + {"description":"" , "text" : "file /nanoCLR.elf>"}, + {"description":"" , "text" : "load"}, + {"description":"" , "text" : "set $sp = g_pfnVectors[0]"}, + {"description":"" , "text" : "set $pc = g_pfnVectors[1]"}, + {"description":"" , "text" : "break main"}, + {"description":"" , "text" : "continue", "ignoreFailures": true } + ], + + "miDebuggerPath": "", + "targetArchitecture": "ARM", + "program": "${workspaceRoot}/build/nanoCLR.elf", + + "launchCompleteCommand": "None", + "serverStarted": "Info\\ :\\ [\\w\\d\\.]*:\\ hardware", + "filterStderr": true, + "externalConsole": true, + "cwd": "${cwd}" + } + ] +} diff --git a/source/native/nf-interpreter/.vscode/settings.TEMPLATE.json b/source/native/nf-interpreter/.vscode/settings.TEMPLATE.json new file mode 100644 index 00000000..4a47defe --- /dev/null +++ b/source/native/nf-interpreter/.vscode/settings.TEMPLATE.json @@ -0,0 +1,13 @@ +{ + "cmake.preferredGenerators": [ + "ninja.exe" + ], + "cmake.generator": "ninja.exe", + "cmake.useCMakeServer" : true, + "cmake.autoRestartBuild" : true, + "cmake.configureSettings": { + "CMAKE_MAKE_PROGRAM":"/ninja/ninja.exe" + }, + "cmake.cmakePath": "/cmake/bin/cmake.exe", + "cmake.configureOnOpen": false +} diff --git a/source/native/nf-interpreter/.vscode/tasks.TEMPLATE-ESP32.json b/source/native/nf-interpreter/.vscode/tasks.TEMPLATE-ESP32.json new file mode 100644 index 00000000..58d72280 --- /dev/null +++ b/source/native/nf-interpreter/.vscode/tasks.TEMPLATE-ESP32.json @@ -0,0 +1,47 @@ +{ + // See https://go.microsoft.com/fwlink/?LinkId=733558 + // for the documentation about the tasks.json format + "version": "2.0.0", + "tasks": [ + { + "taskName": "Flash nanoCLR ", + "type": "shell", + "command": "python /components/esptool_py/esptool/esptool.py --chip esp32 --port \"\" --baud 921600 --before \"default_reset\" --after \"hard_reset\" write_flash -z --flash_mode \"dio\" --flash_freq \"40m\" --flash_size detect 0x1000 /bootloader.bin 0x10000 /nanoCLR.bin 0x8000 /partitions_4mb.bin", + "presentation": { + "reveal": "always", + "panel": "shared" + }, + "problemMatcher": [] + }, + { + "taskName": "Erase flash ", + "type": "shell", + "command": "python /components/esptool_py/esptool/esptool.py --chip esp32 --port \"\" --baud 115200 --before \"default_reset\" --after \"hard_reset\" erase_flash", + "presentation": { + "reveal": "always", + "panel": "shared" + }, + "problemMatcher": [] + }, + { + "taskName": "Flash nanoCLR Wrover ", + "type": "shell", + "command": "python /components/esptool_py/esptool/esptool.py --chip esp32 --port \"\" --baud 921600 --before \"default_reset\" --after \"hard_reset\" write_flash -z --flash_mode \"dio\" --flash_freq \"40m\" --flash_size detect 0x1000 /bootloader.bin 0x10000 /nanoCLR.bin 0x8000 /partitions_4mb.bin", + "presentation": { + "reveal": "always", + "panel": "shared" + }, + "problemMatcher": [] + }, + { + "taskName": "Flash nanoCLR ESP32-EVB ", + "type": "shell", + "command": "python /components/esptool_py/esptool/esptool.py --chip esp32 --port \"\" --baud 921600 --before \"default_reset\" --after \"hard_reset\" write_flash -z --flash_mode \"dio\" --flash_freq \"40m\" --flash_size detect 0x1000 /bootloader.bin 0x10000 /nanoCLR.bin 0x8000 /partitions_4mb.bin", + "presentation": { + "reveal": "always", + "panel": "shared" + }, + "problemMatcher": [] + } + ] +} \ No newline at end of file diff --git a/source/native/nf-interpreter/CHANGELOG.md b/source/native/nf-interpreter/CHANGELOG.md new file mode 100644 index 00000000..5bfc6717 --- /dev/null +++ b/source/native/nf-interpreter/CHANGELOG.md @@ -0,0 +1,517 @@ +# Change Log + +## [**Changes available only in 'Preview' images:**](https://github.com/nanoframework/nf-interpreter/tree/HEAD) + +[Full Changelog](https://github.com/nanoframework/nf-interpreter/compare/v1.0.1...HEAD) + +**Implemented enhancements:** + +- Socket changes and fixes for HTTP [\#955](https://github.com/nanoframework/nf-interpreter/pull/955) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Rework inclusion of UART declarations in STM32 [\#951](https://github.com/nanoframework/nf-interpreter/pull/951) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Add native support for Hardware.Stm32 class lib [\#935](https://github.com/nanoframework/nf-interpreter/pull/935) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Implemented Base64 encoding/decoding [\#934](https://github.com/nanoframework/nf-interpreter/pull/934) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] + +**Fixed bugs:** + +- Fix mscorlib native checksum for 1.0.6-preview-001 [\#969](https://github.com/nanoframework/nf-interpreter/pull/969) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Socket changes and fixes for HTTP [\#955](https://github.com/nanoframework/nf-interpreter/pull/955) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Fix UART4 setting for Windows.Device.SerialCommunication [\#950](https://github.com/nanoframework/nf-interpreter/pull/950) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fixes for issue \#416 [\#933](https://github.com/nanoframework/nf-interpreter/pull/933) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] + +**Documentation and other chores:** + +- Update nanoFramework.Hardware.Esp32 version to 1.0.2-preview-009 [\#980](https://github.com/nanoframework/nf-interpreter/pull/980) +- Update Windows.Devices.Gpio version to 1.0.2-preview-008 [\#979](https://github.com/nanoframework/nf-interpreter/pull/979) +- Update Windows.Devices.SerialCommunication version to 1.0.2-preview-009 [\#978](https://github.com/nanoframework/nf-interpreter/pull/978) +- Update Windows.Devices.Spi version to 1.0.2-preview-007 [\#977](https://github.com/nanoframework/nf-interpreter/pull/977) +- Update Windows.Devices.I2c version to 1.0.2-preview-007 [\#976](https://github.com/nanoframework/nf-interpreter/pull/976) +- Update declaration of Windows.Devices.Gpio [\#973](https://github.com/nanoframework/nf-interpreter/pull/973) +- Update declaration for Windows.Devices.Spi [\#972](https://github.com/nanoframework/nf-interpreter/pull/972) +- Update declaration for Windows.Devices.SerialCommunication [\#971](https://github.com/nanoframework/nf-interpreter/pull/971) +- Update Windows.Devices.I2c declaration [\#970](https://github.com/nanoframework/nf-interpreter/pull/970) +- Update nanoFramework.Hardware.Esp32 version to 1.0.2-preview-004 [\#968](https://github.com/nanoframework/nf-interpreter/pull/968) +- Update Windows.Devices.SerialCommunication version to 1.0.2-preview-004 [\#967](https://github.com/nanoframework/nf-interpreter/pull/967) +- Update Windows.Devices.WiFi version to 1.0.2-preview-004 [\#966](https://github.com/nanoframework/nf-interpreter/pull/966) +- Update nanoFramework.System.Net version to 1.0.2-preview-001 [\#965](https://github.com/nanoframework/nf-interpreter/pull/965) +- Update Windows.Devices.Spi version to 1.0.2-preview-004 [\#964](https://github.com/nanoframework/nf-interpreter/pull/964) +- Update Windows.Devices.Gpio version to 1.0.2-preview-004 [\#963](https://github.com/nanoframework/nf-interpreter/pull/963) +- Update nanoFramework.Hardware.Stm32 version to 1.0.2-preview-004 [\#962](https://github.com/nanoframework/nf-interpreter/pull/962) +- Update nanoFramework.Networking.Sntp version to 1.0.2-preview-005 [\#961](https://github.com/nanoframework/nf-interpreter/pull/961) +- Update Windows.Devices.I2c version to 1.0.2-preview-004 [\#960](https://github.com/nanoframework/nf-interpreter/pull/960) +- Update Windows.Devices.Adc version to 1.0.2-preview-004 [\#959](https://github.com/nanoframework/nf-interpreter/pull/959) +- Update nanoFramework.Runtime.Native version to 1.0.2-preview-004 [\#958](https://github.com/nanoframework/nf-interpreter/pull/958) +- Update nanoFramework.Runtime.Events version to 1.0.2-preview-004 [\#957](https://github.com/nanoframework/nf-interpreter/pull/957) +- Update nanoFramework.CorLib version to 1.0.6-preview-001 [\#956](https://github.com/nanoframework/nf-interpreter/pull/956) +- Update nanoFramework.Networking.Sntp version to 1.0.2-preview-002 [\#954](https://github.com/nanoframework/nf-interpreter/pull/954) +- Move System.Math to it's own class lib [\#948](https://github.com/nanoframework/nf-interpreter/pull/948) + +## [v1.0.1](https://github.com/nanoframework/nf-interpreter/tree/v1.0.1) (2018-10-18) +[Full Changelog](https://github.com/nanoframework/nf-interpreter/compare/v1.0.0...v1.0.1) + +## [v1.0.0](https://github.com/nanoframework/nf-interpreter/tree/v1.0.0) (2018-10-18) +[Full Changelog](https://github.com/nanoframework/nf-interpreter/compare/v0.0.0...v1.0.0) + +**Implemented enhancements:** + +- Work on config block [\#904](https://github.com/nanoframework/nf-interpreter/pull/904) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Add support for GetCustomAttributes [\#865](https://github.com/nanoframework/nf-interpreter/pull/865) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Fix for issue \#402: Type.GetInterfaces doesn't return the inherited interfaces [\#851](https://github.com/nanoframework/nf-interpreter/pull/851) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Fix: Unable to start debug session on ESP32 when using SerialCommunication [\#846](https://github.com/nanoframework/nf-interpreter/pull/846) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] +- Fix for string.LastIndexOf\(char, int\) and string.LastIndexOf\(string, int\) should search toward the beginning of the string \#400 [\#845](https://github.com/nanoframework/nf-interpreter/pull/845) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Add native implementation of resource utility [\#844](https://github.com/nanoframework/nf-interpreter/pull/844) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- SNTP fixes for ESP32 [\#838](https://github.com/nanoframework/nf-interpreter/pull/838) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] +- Fix WiFi version [\#834](https://github.com/nanoframework/nf-interpreter/pull/834) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Move CLR\_SETTINGS to targets [\#832](https://github.com/nanoframework/nf-interpreter/pull/832) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] [[Area: WIN32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20WIN32)] +- Implemented WatchChar in ESP32 [\#831](https://github.com/nanoframework/nf-interpreter/pull/831) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] +- Improve posting of managed events [\#830](https://github.com/nanoframework/nf-interpreter/pull/830) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Add back GenericPort\_Write to ESP32 [\#829](https://github.com/nanoframework/nf-interpreter/pull/829) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] +- Rework system math implementation [\#823](https://github.com/nanoframework/nf-interpreter/pull/823) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Merge watchdog branch [\#819](https://github.com/nanoframework/nf-interpreter/pull/819) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Independent watchdog skeleton definitions [\#808](https://github.com/nanoframework/nf-interpreter/pull/808) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Work on mbed TLS parse certificate [\#807](https://github.com/nanoframework/nf-interpreter/pull/807) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Add new Guid and random for Esp32 [\#804](https://github.com/nanoframework/nf-interpreter/pull/804) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] +- Clean-up messaging class [\#799](https://github.com/nanoframework/nf-interpreter/pull/799) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] [[Area: WIN32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20WIN32)] +- Correct comment about heap for STM32 targets [\#794](https://github.com/nanoframework/nf-interpreter/pull/794) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Update ChibiOS config files for STM32F091RC target [\#793](https://github.com/nanoframework/nf-interpreter/pull/793) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Move booter blinker thread code to main loop [\#790](https://github.com/nanoframework/nf-interpreter/pull/790) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Updates required by ChibiOS fixes [\#787](https://github.com/nanoframework/nf-interpreter/pull/787) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Add support for target reporting if it has nanoBooter [\#785](https://github.com/nanoframework/nf-interpreter/pull/785) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] [[Area: WIN32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20WIN32)] +- Add support for configurable Wire Protocol packet size [\#784](https://github.com/nanoframework/nf-interpreter/pull/784) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Fix required for build with RelWithDebInfo [\#774](https://github.com/nanoframework/nf-interpreter/pull/774) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Update native implementation of serial comm [\#767](https://github.com/nanoframework/nf-interpreter/pull/767) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Add managed event on serial communication [\#766](https://github.com/nanoframework/nf-interpreter/pull/766) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Add native support for runtime.native.power [\#762](https://github.com/nanoframework/nf-interpreter/pull/762) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Work native implementation of Runtime.Native.Rtc [\#761](https://github.com/nanoframework/nf-interpreter/pull/761) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Update native code for nanoFramework.Runtime.Native [\#760](https://github.com/nanoframework/nf-interpreter/pull/760) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Housekeeping on ESP32 code base [\#758](https://github.com/nanoframework/nf-interpreter/pull/758) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] +- Work string to value conversion implementation [\#756](https://github.com/nanoframework/nf-interpreter/pull/756) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Review ESP32 compiler options to enable warnings as errors [\#754](https://github.com/nanoframework/nf-interpreter/pull/754) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Update TimeSpan native declarations [\#747](https://github.com/nanoframework/nf-interpreter/pull/747) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Add support to String.Format [\#744](https://github.com/nanoframework/nf-interpreter/pull/744) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Rework several RAM assignment for STM32 targets [\#741](https://github.com/nanoframework/nf-interpreter/pull/741) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Work on compiler warnings 🚧 [\#739](https://github.com/nanoframework/nf-interpreter/pull/739) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix ADC declaration on all targets 🚧 [\#736](https://github.com/nanoframework/nf-interpreter/pull/736) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix Debugging\_Execution\_BreakpointDef [\#735](https://github.com/nanoframework/nf-interpreter/pull/735) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Fix ChibiOS usbcfg code on all STM32 targets 🚧 [\#732](https://github.com/nanoframework/nf-interpreter/pull/732) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Remove unused code from nanoBooter main 🚧 [\#730](https://github.com/nanoframework/nf-interpreter/pull/730) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Improvements on BlockStorage declarations 🚧 [\#728](https://github.com/nanoframework/nf-interpreter/pull/728) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Change OS Task priority for ReceiverThread [\#724](https://github.com/nanoframework/nf-interpreter/pull/724) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Remove unused exception [\#721](https://github.com/nanoframework/nf-interpreter/pull/721) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Removed all IRAM\_ATTR attributes [\#718](https://github.com/nanoframework/nf-interpreter/pull/718) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] +- GLOBAL\_LOCK / GLOBAL\_UNLOCK implemented [\#716](https://github.com/nanoframework/nf-interpreter/pull/716) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] +- Update corlib to support Timeout.InfiniteTimeSpan [\#715](https://github.com/nanoframework/nf-interpreter/pull/715) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Move command to list native interop assemblies to QueryCLRCapabilities [\#714](https://github.com/nanoframework/nf-interpreter/pull/714) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Add WP command to list interop native assemblies [\#710](https://github.com/nanoframework/nf-interpreter/pull/710) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Update board.h [\#708](https://github.com/nanoframework/nf-interpreter/pull/708) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Update win\_dev\_gpio\_native\_Windows\_Devices\_Gpio\_GpioPin.cpp [\#704](https://github.com/nanoframework/nf-interpreter/pull/704) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] +- Update GPIO to add support for toggle [\#699](https://github.com/nanoframework/nf-interpreter/pull/699) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Remove UpdateTime from Engine [\#698](https://github.com/nanoframework/nf-interpreter/pull/698) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Improvements GC [\#697](https://github.com/nanoframework/nf-interpreter/pull/697) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Improvements on Time\_Uninitialize [\#696](https://github.com/nanoframework/nf-interpreter/pull/696) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Work on scheduler, CLR events and sys time related code [\#695](https://github.com/nanoframework/nf-interpreter/pull/695) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Improvements with timers from ChibiOS API [\#694](https://github.com/nanoframework/nf-interpreter/pull/694) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Add performance counters stubs [\#692](https://github.com/nanoframework/nf-interpreter/pull/692) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Work on PAL events and PAL time [\#690](https://github.com/nanoframework/nf-interpreter/pull/690) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- General improvements in STM32 USB code [\#689](https://github.com/nanoframework/nf-interpreter/pull/689) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Improvements in STM32 I2C class lib code [\#685](https://github.com/nanoframework/nf-interpreter/pull/685) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Implement RTC SetSystemTime [\#684](https://github.com/nanoframework/nf-interpreter/pull/684) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] +- Improvements in ChibiOS SPI native [\#679](https://github.com/nanoframework/nf-interpreter/pull/679) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Work on STM32 SPI implementation [\#677](https://github.com/nanoframework/nf-interpreter/pull/677) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Improvements in STM32 I2C native implementation [\#671](https://github.com/nanoframework/nf-interpreter/pull/671) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Implement ADC feature for ST\_NUCLEO\_F746ZG board [\#667](https://github.com/nanoframework/nf-interpreter/pull/667) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- adc-feature-for-stm32f429i-discovery [\#666](https://github.com/nanoframework/nf-interpreter/pull/666) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Add ADC helper class for STM32F769I [\#665](https://github.com/nanoframework/nf-interpreter/pull/665) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Enable external SRAM for STM32F769I-DISCO [\#664](https://github.com/nanoframework/nf-interpreter/pull/664) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix to ADC last change to managed code [\#663](https://github.com/nanoframework/nf-interpreter/pull/663) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] +- Add FSMC driver for STM32 [\#661](https://github.com/nanoframework/nf-interpreter/pull/661) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Remove left overs from previous EXT GPIO stuff [\#660](https://github.com/nanoframework/nf-interpreter/pull/660) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Work on ADC [\#659](https://github.com/nanoframework/nf-interpreter/pull/659) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Add support for ADC in STM32F769I DISCO [\#658](https://github.com/nanoframework/nf-interpreter/pull/658) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Work on GPIO events [\#657](https://github.com/nanoframework/nf-interpreter/pull/657) +- Various board updates for Netduino 3 Wifi [\#656](https://github.com/nanoframework/nf-interpreter/pull/656) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Work on native ADC [\#655](https://github.com/nanoframework/nf-interpreter/pull/655) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Improvements in STM32 hard fault handler code [\#654](https://github.com/nanoframework/nf-interpreter/pull/654) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Implement Monitor\_FlashSectorMap for nanoBooter [\#647](https://github.com/nanoframework/nf-interpreter/pull/647) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix and update for STM32 flash driver [\#646](https://github.com/nanoframework/nf-interpreter/pull/646) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Various fixes for ESP32 [\#645](https://github.com/nanoframework/nf-interpreter/pull/645) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] +- Work on random number generator [\#643](https://github.com/nanoframework/nf-interpreter/pull/643) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- STM32 HRNG driver [\#642](https://github.com/nanoframework/nf-interpreter/pull/642) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Support for serial on F4 Discovery board [\#638](https://github.com/nanoframework/nf-interpreter/pull/638) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Develop target specific call [\#633](https://github.com/nanoframework/nf-interpreter/pull/633) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- CRC32 in Wire Protocol is now optional [\#629](https://github.com/nanoframework/nf-interpreter/pull/629) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Networking [\#623](https://github.com/nanoframework/nf-interpreter/pull/623) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Remove "local time" stuff [\#622](https://github.com/nanoframework/nf-interpreter/pull/622) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Work on UNDONE FIXME [\#621](https://github.com/nanoframework/nf-interpreter/pull/621) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Work on GC [\#613](https://github.com/nanoframework/nf-interpreter/pull/613) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Improve reboot command execution [\#612](https://github.com/nanoframework/nf-interpreter/pull/612) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Correct implementation of Debugging\_Deployment\_Status [\#610](https://github.com/nanoframework/nf-interpreter/pull/610) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Work on native events [\#608](https://github.com/nanoframework/nf-interpreter/pull/608) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Add noreturn attribute to thread function [\#606](https://github.com/nanoframework/nf-interpreter/pull/606) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Work on Gpio [\#603](https://github.com/nanoframework/nf-interpreter/pull/603) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix vars casing to follow code guidelines [\#602](https://github.com/nanoframework/nf-interpreter/pull/602) +- Allow events to be fired when no threads active [\#601](https://github.com/nanoframework/nf-interpreter/pull/601) +- Add check for series definition in ChibiOS targetPAL [\#600](https://github.com/nanoframework/nf-interpreter/pull/600) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Improvements on Gpio setting of alternate function [\#597](https://github.com/nanoframework/nf-interpreter/pull/597) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Work on serial [\#585](https://github.com/nanoframework/nf-interpreter/pull/585) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Add serial feature to Nucleo F746ZG [\#584](https://github.com/nanoframework/nf-interpreter/pull/584) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Add Serial support to ND3 [\#581](https://github.com/nanoframework/nf-interpreter/pull/581) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Add Serial feature to F429 Discovery [\#580](https://github.com/nanoframework/nf-interpreter/pull/580) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Improve serial operations [\#579](https://github.com/nanoframework/nf-interpreter/pull/579) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Work on CLR events [\#578](https://github.com/nanoframework/nf-interpreter/pull/578) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Implement read timeout on serial device [\#577](https://github.com/nanoframework/nf-interpreter/pull/577) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Update win\_dev\_serial\_native\_Windows\_Devices\_SerialCommunication\_Seri… [\#573](https://github.com/nanoframework/nf-interpreter/pull/573) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Work on native support for Serial.Communication [\#569](https://github.com/nanoframework/nf-interpreter/pull/569) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Improve STM32 v2 flash driver [\#565](https://github.com/nanoframework/nf-interpreter/pull/565) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Improve Wire Protocol trace output [\#564](https://github.com/nanoframework/nf-interpreter/pull/564) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Improvements in device information [\#563](https://github.com/nanoframework/nf-interpreter/pull/563) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Revert "Rework System.DateTime \(\#553\)" [\#560](https://github.com/nanoframework/nf-interpreter/pull/560) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Add pwm support for STM32F407 [\#559](https://github.com/nanoframework/nf-interpreter/pull/559) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Rework System.DateTime [\#553](https://github.com/nanoframework/nf-interpreter/pull/553) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Drivemode "Alternate" [\#552](https://github.com/nanoframework/nf-interpreter/pull/552) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- FatFS Integration [\#551](https://github.com/nanoframework/nf-interpreter/pull/551) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Clean-up type system [\#544](https://github.com/nanoframework/nf-interpreter/pull/544) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Remove ExtendedWeakReference [\#543](https://github.com/nanoframework/nf-interpreter/pull/543) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Update nanoCLR project [\#542](https://github.com/nanoframework/nf-interpreter/pull/542) +- Rework bool functions and args [\#539](https://github.com/nanoframework/nf-interpreter/pull/539) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Work on Debugger conditions in CLR\_RT\_ExecutionEngine [\#538](https://github.com/nanoframework/nf-interpreter/pull/538) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Improvements in Wire Protocol responsivness [\#536](https://github.com/nanoframework/nf-interpreter/pull/536) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] + +**Fixed bugs:** + +- Fix bug with infinite timeout handling [\#906](https://github.com/nanoframework/nf-interpreter/pull/906) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Work on config block [\#904](https://github.com/nanoframework/nf-interpreter/pull/904) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fixes to SPI for half duplex/TransferSequential [\#872](https://github.com/nanoframework/nf-interpreter/pull/872) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] +- Fix STM32 series defines throughout the code [\#862](https://github.com/nanoframework/nf-interpreter/pull/862) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix enumeration of config blocks when device has no config block [\#857](https://github.com/nanoframework/nf-interpreter/pull/857) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix Convert::NativeToInt64 for multiple base conversions [\#855](https://github.com/nanoframework/nf-interpreter/pull/855) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Fix for issue \#390: object.GetHashCode not working [\#852](https://github.com/nanoframework/nf-interpreter/pull/852) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Fix for issue \\#402: Type.GetInterfaces doesn't return the inherited interfaces [\#851](https://github.com/nanoframework/nf-interpreter/pull/851) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Fix for issue \#409: NativeToDouble doesn't support the "e"/"E" exponential char [\#850](https://github.com/nanoframework/nf-interpreter/pull/850) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Fix for issue 403: type.GetMethods returns also static methods of the base class [\#849](https://github.com/nanoframework/nf-interpreter/pull/849) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- The format for 64bit values is "ll" not "l" [\#848](https://github.com/nanoframework/nf-interpreter/pull/848) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Uncommented the CLR\_RT\_TypeSystem::FindTypeDef functionality [\#847](https://github.com/nanoframework/nf-interpreter/pull/847) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Fix for string.LastIndexOf\\(char, int\\) and string.LastIndexOf\\(string, int\\) should search toward the beginning of the string \\#400 [\#845](https://github.com/nanoframework/nf-interpreter/pull/845) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Fix for double.ToString\(\) and float.ToString\(\) [\#841](https://github.com/nanoframework/nf-interpreter/pull/841) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Fix Random.Next returns negative numbers \#405 [\#840](https://github.com/nanoframework/nf-interpreter/pull/840) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Fix Math.Round [\#839](https://github.com/nanoframework/nf-interpreter/pull/839) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Fix DateTime.DaysInMonth [\#837](https://github.com/nanoframework/nf-interpreter/pull/837) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Fix single precision Truncate\_\_\_STATIC\_\_R4\_\_R4 [\#836](https://github.com/nanoframework/nf-interpreter/pull/836) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Rework math calls [\#827](https://github.com/nanoframework/nf-interpreter/pull/827) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Rework system math implementation [\#823](https://github.com/nanoframework/nf-interpreter/pull/823) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Config changes [\#818](https://github.com/nanoframework/nf-interpreter/pull/818) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] +- Fix number conversion [\#816](https://github.com/nanoframework/nf-interpreter/pull/816) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Fix ToString for doubles and floats [\#815](https://github.com/nanoframework/nf-interpreter/pull/815) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Fix tiny printf implementation [\#813](https://github.com/nanoframework/nf-interpreter/pull/813) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix I2c issues [\#803](https://github.com/nanoframework/nf-interpreter/pull/803) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] +- Remove debug code on SSL Network timeouts [\#802](https://github.com/nanoframework/nf-interpreter/pull/802) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Flash erase fix [\#801](https://github.com/nanoframework/nf-interpreter/pull/801) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] +- Fix ChibiOS ADCv2 config struct [\#789](https://github.com/nanoframework/nf-interpreter/pull/789) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix typo in function name [\#786](https://github.com/nanoframework/nf-interpreter/pull/786) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Fix LaunchCLR to detect valid image [\#780](https://github.com/nanoframework/nf-interpreter/pull/780) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix declaration for build config RelWithDebInfo [\#779](https://github.com/nanoframework/nf-interpreter/pull/779) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fixes required for STM32F0 series [\#778](https://github.com/nanoframework/nf-interpreter/pull/778) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Improve code in CheckValidCLRImage [\#776](https://github.com/nanoframework/nf-interpreter/pull/776) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix time methods as per \#350 \#351 [\#770](https://github.com/nanoframework/nf-interpreter/pull/770) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fixes with declarations for SMT32L0 series [\#757](https://github.com/nanoframework/nf-interpreter/pull/757) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Improved code to remove compiler warning [\#749](https://github.com/nanoframework/nf-interpreter/pull/749) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix format specifier for double printf [\#743](https://github.com/nanoframework/nf-interpreter/pull/743) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Fix issue with CLR\_RT\_UnicodeHelper::ConvertFromUTF8 [\#742](https://github.com/nanoframework/nf-interpreter/pull/742) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Various fixes with Devices.Gpio [\#740](https://github.com/nanoframework/nf-interpreter/pull/740) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix System.Math.Truncate [\#734](https://github.com/nanoframework/nf-interpreter/pull/734) [[Area: Common libs](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Common%20libs)] +- Fix wrong field declaration in System\_String [\#727](https://github.com/nanoframework/nf-interpreter/pull/727) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Improvement on Serial NativeRead [\#722](https://github.com/nanoframework/nf-interpreter/pull/722) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Correct ConstraintException in type system lookup table [\#720](https://github.com/nanoframework/nf-interpreter/pull/720) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Corrected the device selector string for the ESP32 serial ports [\#717](https://github.com/nanoframework/nf-interpreter/pull/717) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] +- SPI: Use the max clock frequency if unset \(\#327\) [\#711](https://github.com/nanoframework/nf-interpreter/pull/711) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] +- Fix bug with unwanted read or write after I2C operation [\#709](https://github.com/nanoframework/nf-interpreter/pull/709) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix ESP32 Gpio toggle [\#703](https://github.com/nanoframework/nf-interpreter/pull/703) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] +- Fix issues with ESP32 time and event functions [\#700](https://github.com/nanoframework/nf-interpreter/pull/700) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] +- Work on STM32 SPI [\#686](https://github.com/nanoframework/nf-interpreter/pull/686) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Correct calls to cache helpers for STM32 targets [\#676](https://github.com/nanoframework/nf-interpreter/pull/676) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix error introduced in last ESP32 I2C change [\#674](https://github.com/nanoframework/nf-interpreter/pull/674) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] +- Improve debug session start [\#669](https://github.com/nanoframework/nf-interpreter/pull/669) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Work on GPIO events [\#657](https://github.com/nanoframework/nf-interpreter/pull/657) +- Added header for ESP32 to define uint8\_t etc [\#649](https://github.com/nanoframework/nf-interpreter/pull/649) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] +- Fix and update for STM32 flash driver [\#646](https://github.com/nanoframework/nf-interpreter/pull/646) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Various fixes for ESP32 [\#645](https://github.com/nanoframework/nf-interpreter/pull/645) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] +- Correct code writing single bytes to flash [\#644](https://github.com/nanoframework/nf-interpreter/pull/644) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix var name for config block [\#641](https://github.com/nanoframework/nf-interpreter/pull/641) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix STM32F7 loader files [\#640](https://github.com/nanoframework/nf-interpreter/pull/640) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix wrong button check in booter \(STM32F4 disco\) [\#636](https://github.com/nanoframework/nf-interpreter/pull/636) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Correct code reading Gpio value [\#635](https://github.com/nanoframework/nf-interpreter/pull/635) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Rework code for Serial ouput stream Store [\#607](https://github.com/nanoframework/nf-interpreter/pull/607) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix serial com Store\(\) delay [\#605](https://github.com/nanoframework/nf-interpreter/pull/605) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix Wire Protocol comm issues [\#596](https://github.com/nanoframework/nf-interpreter/pull/596) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Fix inclusion of target source file for serial API [\#587](https://github.com/nanoframework/nf-interpreter/pull/587) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Work on serial [\#585](https://github.com/nanoframework/nf-interpreter/pull/585) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Update win\_dev\_serial\_native\_Windows\_Devices\_SerialCommunication\_Seri… [\#574](https://github.com/nanoframework/nf-interpreter/pull/574) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix UART definition requried for serial support [\#572](https://github.com/nanoframework/nf-interpreter/pull/572) +- Correct UART\_INIT macro for F4 and F0 targets [\#570](https://github.com/nanoframework/nf-interpreter/pull/570) +- Correct CRT heap size for nanoBooter [\#556](https://github.com/nanoframework/nf-interpreter/pull/556) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Change Spi Full-duplex buffer size [\#546](https://github.com/nanoframework/nf-interpreter/pull/546) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Amend comparison size of assembly marker [\#541](https://github.com/nanoframework/nf-interpreter/pull/541) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Correct missing call to wait debugger commands [\#537](https://github.com/nanoframework/nf-interpreter/pull/537) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix managed heap initialization [\#534](https://github.com/nanoframework/nf-interpreter/pull/534) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] + +**Documentation and other chores:** + +- Merge back changes from Release 1.0.0 [\#928](https://github.com/nanoframework/nf-interpreter/pull/928) +- Merge 'develop' for Release 1.0.0 [\#927](https://github.com/nanoframework/nf-interpreter/pull/927) +- Update nanoFramework.CorLib version to 1.0.4 [\#918](https://github.com/nanoframework/nf-interpreter/pull/918) +- normalize line endings [\#900](https://github.com/nanoframework/nf-interpreter/pull/900) +- Update nanoFramework.CorLib version to 1.0.1-preview118 [\#898](https://github.com/nanoframework/nf-interpreter/pull/898) +- High Res Timer added to Nanoframework.Hardware.Esp32 [\#866](https://github.com/nanoframework/nf-interpreter/pull/866) +- remove obsolete parameter BOARD\_NAME [\#861](https://github.com/nanoframework/nf-interpreter/pull/861) +- Getting the MinSizeRel build working for the ESP32 [\#796](https://github.com/nanoframework/nf-interpreter/pull/796) +- Changed build back to Debug [\#783](https://github.com/nanoframework/nf-interpreter/pull/783) +- Updated the ESP32 build documentation [\#755](https://github.com/nanoframework/nf-interpreter/pull/755) +- Add FP information about STM32 targets to readme [\#753](https://github.com/nanoframework/nf-interpreter/pull/753) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix for timeout errors on I2C introduced with 3.0 release. [\#746](https://github.com/nanoframework/nf-interpreter/pull/746) +- Initial ESP32 native hardware support [\#712](https://github.com/nanoframework/nf-interpreter/pull/712) +- Improvements in ESP32 related docs [\#691](https://github.com/nanoframework/nf-interpreter/pull/691) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] +- Updated the setup procedure for the ESP32 development [\#682](https://github.com/nanoframework/nf-interpreter/pull/682) [[Area: ESP32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20ESP32)] +- Fix issues that stopped ESP32 build after change to events [\#611](https://github.com/nanoframework/nf-interpreter/pull/611) +- ESP32 Gpio update to support SetAlternateFunction [\#598](https://github.com/nanoframework/nf-interpreter/pull/598) +- Update sub module community targets @1d0bc8b0 [\#575](https://github.com/nanoframework/nf-interpreter/pull/575) +- Update target\_windows\_devices\_serialcommunication\_config.cpp [\#571](https://github.com/nanoframework/nf-interpreter/pull/571) +- Include community board in select clause for I2C [\#567](https://github.com/nanoframework/nf-interpreter/pull/567) +- PWM - Add more MCUs [\#558](https://github.com/nanoframework/nf-interpreter/pull/558) +- PWM support initial commit [\#557](https://github.com/nanoframework/nf-interpreter/pull/557) +- Update corlib\_native\_System\_Number.cpp [\#550](https://github.com/nanoframework/nf-interpreter/pull/550) +- Update corlib\_native\_System\_Number.cpp [\#549](https://github.com/nanoframework/nf-interpreter/pull/549) +- Update targetHAL\_Time.cpp [\#548](https://github.com/nanoframework/nf-interpreter/pull/548) + +## [v0.0.0](https://github.com/nanoframework/nf-interpreter/tree/v0.0.0) (2017-09-26) +**Implemented enhancements:** + +- Add exception handlers for debug [\#488](https://github.com/nanoframework/nf-interpreter/pull/488) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Update Devces.Gpio native code for 1.0.0.22 [\#470](https://github.com/nanoframework/nf-interpreter/pull/470) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Add CR+LF to improve output [\#463](https://github.com/nanoframework/nf-interpreter/pull/463) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Add more SetResult\_\* methods [\#460](https://github.com/nanoframework/nf-interpreter/pull/460) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Work on System.Convert [\#459](https://github.com/nanoframework/nf-interpreter/pull/459) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Enhanced 16bit support [\#457](https://github.com/nanoframework/nf-interpreter/pull/457) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Enable SPI5 \(this is used in the board mems sensor\) [\#453](https://github.com/nanoframework/nf-interpreter/pull/453) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Update test app for nanoCLR [\#450](https://github.com/nanoframework/nf-interpreter/pull/450) [[Area: WIN32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20WIN32)] +- Update native code for System.Globalization [\#446](https://github.com/nanoframework/nf-interpreter/pull/446) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Work on events [\#441](https://github.com/nanoframework/nf-interpreter/pull/441) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Work on Events [\#440](https://github.com/nanoframework/nf-interpreter/pull/440) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Improve assembly loading [\#439](https://github.com/nanoframework/nf-interpreter/pull/439) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Correct types in declarations of Async Process calls [\#437](https://github.com/nanoframework/nf-interpreter/pull/437) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Add native code for System.Console [\#431](https://github.com/nanoframework/nf-interpreter/pull/431) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- SPI native code [\#429](https://github.com/nanoframework/nf-interpreter/pull/429) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Work on Devices.Spi [\#428](https://github.com/nanoframework/nf-interpreter/pull/428) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Move CLRStartup to its own OS thread [\#425](https://github.com/nanoframework/nf-interpreter/pull/425) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Work on Devices.Spi native [\#424](https://github.com/nanoframework/nf-interpreter/pull/424) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Work on Devices.Gpio [\#418](https://github.com/nanoframework/nf-interpreter/pull/418) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Rename NativeEvents native code [\#409](https://github.com/nanoframework/nf-interpreter/pull/409) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Update nanoCLR test solution [\#406](https://github.com/nanoframework/nf-interpreter/pull/406) [[Area: WIN32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20WIN32)] +- Minor fixes [\#401](https://github.com/nanoframework/nf-interpreter/pull/401) +- Fix flash driver for use in SMT32F7 series [\#400](https://github.com/nanoframework/nf-interpreter/pull/400) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Various fixes for MBN\_QUAIL [\#395](https://github.com/nanoframework/nf-interpreter/pull/395) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Work on Execution [\#375](https://github.com/nanoframework/nf-interpreter/pull/375) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] [[Area: WIN32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20WIN32)] +- Update test app in nanoCLR [\#374](https://github.com/nanoframework/nf-interpreter/pull/374) [[Area: WIN32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20WIN32)] +- Initial work on Events [\#373](https://github.com/nanoframework/nf-interpreter/pull/373) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Improve ContiguousBlockAssemblies [\#371](https://github.com/nanoframework/nf-interpreter/pull/371) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Remove endianess checking of assemblies [\#368](https://github.com/nanoframework/nf-interpreter/pull/368) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Aligned CorLib declarations with managed stubs [\#367](https://github.com/nanoframework/nf-interpreter/pull/367) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Fix issues with assemblies loading at startup [\#365](https://github.com/nanoframework/nf-interpreter/pull/365) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Remove addresses from Debugging\_Deployment\_Status [\#362](https://github.com/nanoframework/nf-interpreter/pull/362) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Add error code to reply of access memory commands [\#361](https://github.com/nanoframework/nf-interpreter/pull/361) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Enable IncrementalDeployment in capabilites [\#360](https://github.com/nanoframework/nf-interpreter/pull/360) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Work on Debugging\_Deployment\_Status [\#359](https://github.com/nanoframework/nf-interpreter/pull/359) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Improvements in flash driver [\#358](https://github.com/nanoframework/nf-interpreter/pull/358) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Work on DeviceBlockInfo\_FindRegionFromAddress [\#357](https://github.com/nanoframework/nf-interpreter/pull/357) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Work on Debugging\_Deployment\_Status [\#356](https://github.com/nanoframework/nf-interpreter/pull/356) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Sync flags with debugger library code [\#350](https://github.com/nanoframework/nf-interpreter/pull/350) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Remove unsupported c\_Monitor\_SignatureKeyUpdate [\#349](https://github.com/nanoframework/nf-interpreter/pull/349) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Work on ChibiOS v17 USB code [\#344](https://github.com/nanoframework/nf-interpreter/pull/344) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Second try on Windows.Devices.Gpio [\#329](https://github.com/nanoframework/nf-interpreter/pull/329) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Update Nuget packages [\#318](https://github.com/nanoframework/nf-interpreter/pull/318) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: WIN32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20WIN32)] +- Update documentation to include API option [\#317](https://github.com/nanoframework/nf-interpreter/pull/317) +- Add native code for base class library \(mscolib\) [\#310](https://github.com/nanoframework/nf-interpreter/pull/310) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Include support for ChibiOS syscalls to use newlib stuff [\#309](https://github.com/nanoframework/nf-interpreter/pull/309) +- Add declaration for MDP [\#301](https://github.com/nanoframework/nf-interpreter/pull/301) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Add Interop feature to CLR [\#299](https://github.com/nanoframework/nf-interpreter/pull/299) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- removed unused include for nanoHAL.h [\#298](https://github.com/nanoframework/nf-interpreter/pull/298) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Remove legacy functions [\#293](https://github.com/nanoframework/nf-interpreter/pull/293) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Update Nuget for MSBuild System [\#291](https://github.com/nanoframework/nf-interpreter/pull/291) [[Area: WIN32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20WIN32)] +- Add code to output to VS console [\#290](https://github.com/nanoframework/nf-interpreter/pull/290) [[Area: WIN32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20WIN32)] +- Update Nuget packages [\#289](https://github.com/nanoframework/nf-interpreter/pull/289) [[Area: WIN32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20WIN32)] +- Replace path for mscorlib.pe [\#288](https://github.com/nanoframework/nf-interpreter/pull/288) [[Area: WIN32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20WIN32)] +- Improve error reporting detail [\#286](https://github.com/nanoframework/nf-interpreter/pull/286) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Fix ComputeAssemblyHash [\#279](https://github.com/nanoframework/nf-interpreter/pull/279) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Moved nanoCLR\_ParseOptions file to src folder [\#277](https://github.com/nanoframework/nf-interpreter/pull/277) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Enable Target\_GetReleaseInfo [\#267](https://github.com/nanoframework/nf-interpreter/pull/267) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Enable GetClrReleaseInfo in Debugger [\#266](https://github.com/nanoframework/nf-interpreter/pull/266) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Revert types to well known defined types [\#251](https://github.com/nanoframework/nf-interpreter/pull/251) +- Replace types with standard C [\#250](https://github.com/nanoframework/nf-interpreter/pull/250) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Correct declaration to use standard types [\#249](https://github.com/nanoframework/nf-interpreter/pull/249) +- Replace attributes with define [\#248](https://github.com/nanoframework/nf-interpreter/pull/248) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Complete work on \#195 [\#240](https://github.com/nanoframework/nf-interpreter/pull/240) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Rework code base to have a single debugger and messaging port [\#238](https://github.com/nanoframework/nf-interpreter/pull/238) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Rename ReplyCommand in WireProtocol C implementation [\#236](https://github.com/nanoframework/nf-interpreter/pull/236) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Further work on BlockStorage [\#235](https://github.com/nanoframework/nf-interpreter/pull/235) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Update build-instructions.md [\#229](https://github.com/nanoframework/nf-interpreter/pull/229) +- Moved linker symbols to targetHAL [\#218](https://github.com/nanoframework/nf-interpreter/pull/218) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Update documentation on contributions [\#217](https://github.com/nanoframework/nf-interpreter/pull/217) +- Add GetSector in STM32 flash driver [\#214](https://github.com/nanoframework/nf-interpreter/pull/214) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- First implement of Monitor\_CheckMemory logic. [\#211](https://github.com/nanoframework/nf-interpreter/pull/211) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Implement Monitor\_MemoryMap command [\#207](https://github.com/nanoframework/nf-interpreter/pull/207) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Add flash driver for STM32F7 series [\#200](https://github.com/nanoframework/nf-interpreter/pull/200) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Rework HAL time functions [\#160](https://github.com/nanoframework/nf-interpreter/pull/160) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Cleaned up unused,obsolete and unsupported platforms and toolchains [\#99](https://github.com/nanoframework/nf-interpreter/pull/99) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- WP test app over USB CDC [\#65](https://github.com/nanoframework/nf-interpreter/pull/65) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Implement Wire Protocol in plain C [\#56](https://github.com/nanoframework/nf-interpreter/pull/56) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Moved CLR folder up one level [\#50](https://github.com/nanoframework/nf-interpreter/pull/50) +- Add test app for mBed RTOS [\#16](https://github.com/nanoframework/nf-interpreter/pull/16) +- Add demo app for FreeRTOS [\#15](https://github.com/nanoframework/nf-interpreter/pull/15) +- Add support for specifing RTOS for build [\#14](https://github.com/nanoframework/nf-interpreter/pull/14) + +**Fixed bugs:** + +- Add missing defines in mcuconf header of ST\_STM32F769I\_DISCOVERY [\#487](https://github.com/nanoframework/nf-interpreter/pull/487) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix linker file for ST\_STM32F769I\_DISCOVERY [\#486](https://github.com/nanoframework/nf-interpreter/pull/486) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Remove references to removed source files [\#447](https://github.com/nanoframework/nf-interpreter/pull/447) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Correct wrong declation of argument in Interop code [\#417](https://github.com/nanoframework/nf-interpreter/pull/417) +- Correct issue with flash driver for STM32F4XX devices [\#415](https://github.com/nanoframework/nf-interpreter/pull/415) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix flash driver for use in SMT32F7 series [\#400](https://github.com/nanoframework/nf-interpreter/pull/400) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Various fixes for MBN\\_QUAIL [\#395](https://github.com/nanoframework/nf-interpreter/pull/395) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Various fixes in ST\_STM32F429I\_DISCOVERY [\#394](https://github.com/nanoframework/nf-interpreter/pull/394) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix debugger wait loop [\#383](https://github.com/nanoframework/nf-interpreter/pull/383) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Fix ContiguousBlockAssemblies [\#372](https://github.com/nanoframework/nf-interpreter/pull/372) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Correct submodule naming [\#256](https://github.com/nanoframework/nf-interpreter/pull/256) +- Fixed ram0 start address on linker file [\#206](https://github.com/nanoframework/nf-interpreter/pull/206) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Add missing \#ifdef for Win32 nanoCLR solution [\#175](https://github.com/nanoframework/nf-interpreter/pull/175) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] + +**Documentation and other chores:** + +- Fix linker files for SMT32F7 series [\#516](https://github.com/nanoframework/nf-interpreter/pull/516) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix issue \#70 [\#515](https://github.com/nanoframework/nf-interpreter/pull/515) +- Fix compilation error for F091 with SPI [\#508](https://github.com/nanoframework/nf-interpreter/pull/508) +- Changed I2C transmit timeout [\#507](https://github.com/nanoframework/nf-interpreter/pull/507) +- Replace duplicate implementations of SafeSprint\* [\#506](https://github.com/nanoframework/nf-interpreter/pull/506) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Add implementation for TimeSpan.ToString\(\) [\#505](https://github.com/nanoframework/nf-interpreter/pull/505) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Remove unused vars and related code file [\#504](https://github.com/nanoframework/nf-interpreter/pull/504) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix I2C for F769I reference board [\#500](https://github.com/nanoframework/nf-interpreter/pull/500) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Increase memory for image of firmware [\#499](https://github.com/nanoframework/nf-interpreter/pull/499) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Activate channels for SPI, I2C [\#498](https://github.com/nanoframework/nf-interpreter/pull/498) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Correct include version for I2C [\#497](https://github.com/nanoframework/nf-interpreter/pull/497) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Definitive fix for I2C and SPI on F7 MCU [\#495](https://github.com/nanoframework/nf-interpreter/pull/495) +- Work on I2C for STM32F7xx [\#492](https://github.com/nanoframework/nf-interpreter/pull/492) +- Improve HAL EXT initialization [\#491](https://github.com/nanoframework/nf-interpreter/pull/491) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fixes exception in ToString\(\) [\#490](https://github.com/nanoframework/nf-interpreter/pull/490) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Fix ChibiOS rules [\#489](https://github.com/nanoframework/nf-interpreter/pull/489) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Dereference Unsigned shorts in SPI [\#484](https://github.com/nanoframework/nf-interpreter/pull/484) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Remove setting of PB3 for SWO [\#482](https://github.com/nanoframework/nf-interpreter/pull/482) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Improve SWO config [\#481](https://github.com/nanoframework/nf-interpreter/pull/481) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Spi f7 [\#480](https://github.com/nanoframework/nf-interpreter/pull/480) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Remove ST\_NUCLEO144\_F746ZG from nF overlay [\#476](https://github.com/nanoframework/nf-interpreter/pull/476) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Update program with SPI test code [\#474](https://github.com/nanoframework/nf-interpreter/pull/474) [[Area: WIN32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20WIN32)] +- Correct assembly name [\#473](https://github.com/nanoframework/nf-interpreter/pull/473) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Update nanoCLR test app to latest Nugets [\#472](https://github.com/nanoframework/nf-interpreter/pull/472) [[Area: WIN32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20WIN32)] +- Disable Gpio on F091 board [\#471](https://github.com/nanoframework/nf-interpreter/pull/471) +- SetResult - Fix bytes return values [\#469](https://github.com/nanoframework/nf-interpreter/pull/469) +- Update docs [\#467](https://github.com/nanoframework/nf-interpreter/pull/467) +- I2c [\#445](https://github.com/nanoframework/nf-interpreter/pull/445) +- Add missing file to nanoCLR [\#438](https://github.com/nanoframework/nf-interpreter/pull/438) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: WIN32](https://github.com/nanoframework/nf-interpreter/labels/Area:%20WIN32)] +- Add documentation on using Ninja build [\#436](https://github.com/nanoframework/nf-interpreter/pull/436) +- Improve documentation [\#426](https://github.com/nanoframework/nf-interpreter/pull/426) +- Improve communication responsiveness [\#423](https://github.com/nanoframework/nf-interpreter/pull/423) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- refactored template to make it slightly simpler [\#410](https://github.com/nanoframework/nf-interpreter/pull/410) +- Improvements in documentation for class libraries [\#405](https://github.com/nanoframework/nf-interpreter/pull/405) +- Corrections for F69I \(deployment still fails\) [\#396](https://github.com/nanoframework/nf-interpreter/pull/396) +- Fix regions on F746ZG \(\#391\) [\#392](https://github.com/nanoframework/nf-interpreter/pull/392) +- updates to documentation \(\#386\) [\#389](https://github.com/nanoframework/nf-interpreter/pull/389) +- fix for USB connection issues with F769I [\#388](https://github.com/nanoframework/nf-interpreter/pull/388) +- Devices.Gpio fixes [\#387](https://github.com/nanoframework/nf-interpreter/pull/387) +- F746 device id \(\#380\) [\#384](https://github.com/nanoframework/nf-interpreter/pull/384) +- update travis arm toolchain [\#381](https://github.com/nanoframework/nf-interpreter/pull/381) +- update travis arm toolchain \#196 and cmake to 3.8.2 [\#379](https://github.com/nanoframework/nf-interpreter/pull/379) +- updated documents [\#378](https://github.com/nanoframework/nf-interpreter/pull/378) +- Add documenation about thread execution and context switching [\#376](https://github.com/nanoframework/nf-interpreter/pull/376) +- F7 improvements and attempts at CLR RAM optimisations for some boards [\#370](https://github.com/nanoframework/nf-interpreter/pull/370) +- clr managed heap document improvements [\#369](https://github.com/nanoframework/nf-interpreter/pull/369) +- Add doc with explanation about deployment [\#363](https://github.com/nanoframework/nf-interpreter/pull/363) +- Fix \#353 [\#354](https://github.com/nanoframework/nf-interpreter/pull/354) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Fix issue \#337 [\#338](https://github.com/nanoframework/nf-interpreter/pull/338) +- Work on new DateTime native side [\#336](https://github.com/nanoframework/nf-interpreter/pull/336) +- Fixes \#314 [\#315](https://github.com/nanoframework/nf-interpreter/pull/315) +- Fix declaration of Interop\_Marshal\_GetField for bool type [\#295](https://github.com/nanoframework/nf-interpreter/pull/295) +- Add stdafx.h include [\#282](https://github.com/nanoframework/nf-interpreter/pull/282) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Update Community Targets submodule [\#280](https://github.com/nanoframework/nf-interpreter/pull/280) +- Moved nanoCLR\_ParseOptions file to src folder \(\#277\) [\#278](https://github.com/nanoframework/nf-interpreter/pull/278) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Add documentation about cmake-variants.TEMPLATE.json [\#276](https://github.com/nanoframework/nf-interpreter/pull/276) +- Correct GNU ARM Eclipse OpenOCD link [\#273](https://github.com/nanoframework/nf-interpreter/pull/273) +- Correct issue when checking for user button pressed [\#271](https://github.com/nanoframework/nf-interpreter/pull/271) +- Add missing CLRStartup thread to reference boards [\#262](https://github.com/nanoframework/nf-interpreter/pull/262) +- Fix \#259 [\#261](https://github.com/nanoframework/nf-interpreter/pull/261) +- Correct linker scripts to aling deployment [\#260](https://github.com/nanoframework/nf-interpreter/pull/260) +- Correct button check [\#258](https://github.com/nanoframework/nf-interpreter/pull/258) +- Correction for support of community boards [\#253](https://github.com/nanoframework/nf-interpreter/pull/253) +- Update gitignore for VS Code [\#246](https://github.com/nanoframework/nf-interpreter/pull/246) +- Fixes issue \#118 [\#245](https://github.com/nanoframework/nf-interpreter/pull/245) +- Fix Quail nanoBooter main code [\#244](https://github.com/nanoframework/nf-interpreter/pull/244) +- Update README.md [\#243](https://github.com/nanoframework/nf-interpreter/pull/243) +- Fix \#241 [\#242](https://github.com/nanoframework/nf-interpreter/pull/242) +- update build instructions related to launch.json [\#234](https://github.com/nanoframework/nf-interpreter/pull/234) +- Initial implementation of Monitor\_FlashSectorMap \(\#215\) [\#223](https://github.com/nanoframework/nf-interpreter/pull/223) +- Moved some declarations to nanoHAL\_v2 [\#204](https://github.com/nanoframework/nf-interpreter/pull/204) +- Add dummy flash sector 11 definition [\#203](https://github.com/nanoframework/nf-interpreter/pull/203) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Implement AccessMemory function [\#198](https://github.com/nanoframework/nf-interpreter/pull/198) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Implement Monitor\_EraseMemory command [\#197](https://github.com/nanoframework/nf-interpreter/pull/197) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- HAL config was missing the USE\_SERIAL definition [\#194](https://github.com/nanoframework/nf-interpreter/pull/194) +- Add Travis CI badge to readme [\#193](https://github.com/nanoframework/nf-interpreter/pull/193) +- Correct filename case [\#190](https://github.com/nanoframework/nf-interpreter/pull/190) +- Correct file name case [\#189](https://github.com/nanoframework/nf-interpreter/pull/189) +- Change filename case [\#187](https://github.com/nanoframework/nf-interpreter/pull/187) +- update Travis file [\#183](https://github.com/nanoframework/nf-interpreter/pull/183) +- Add Travis file [\#180](https://github.com/nanoframework/nf-interpreter/pull/180) +- Aligned CMakes for reference boards [\#179](https://github.com/nanoframework/nf-interpreter/pull/179) +- Enable WireProtocol in nanoBooter [\#177](https://github.com/nanoframework/nf-interpreter/pull/177) +- Quail board support again [\#168](https://github.com/nanoframework/nf-interpreter/pull/168) +- Fix mcu configs for NUCLEO901 in nanoCLR [\#167](https://github.com/nanoframework/nf-interpreter/pull/167) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Uncomment line that was causing issues with nanoCLR image detection [\#163](https://github.com/nanoframework/nf-interpreter/pull/163) +- Lineup the sys tick configurations on all reference boards [\#156](https://github.com/nanoframework/nf-interpreter/pull/156) +- Add code to check for valid CLR image and launch it [\#155](https://github.com/nanoframework/nf-interpreter/pull/155) +- Revert ChibiOS setting for using classic periodic timer [\#153](https://github.com/nanoframework/nf-interpreter/pull/153) +- Add STM32F429I\_DISCOVERY board [\#147](https://github.com/nanoframework/nf-interpreter/pull/147) [[Area: STM32-ChibiOS](https://github.com/nanoframework/nf-interpreter/labels/Area:%20STM32-ChibiOS)] +- Implement HAL\_Time\_TicksToTimeMilliSec [\#145](https://github.com/nanoframework/nf-interpreter/pull/145) +- Moved include of target\_board header to targetHAL [\#144](https://github.com/nanoframework/nf-interpreter/pull/144) +- Deleted nanoCLR.VC.db [\#138](https://github.com/nanoframework/nf-interpreter/pull/138) +- Fixes \#81 [\#137](https://github.com/nanoframework/nf-interpreter/pull/137) +- Resolves \#133 [\#135](https://github.com/nanoframework/nf-interpreter/pull/135) +- Rename FLASH in HAL\_SYSTEM\_CONFIG struct [\#129](https://github.com/nanoframework/nf-interpreter/pull/129) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Add logo in common size \(32x32\) [\#117](https://github.com/nanoframework/nf-interpreter/pull/117) +- Correct "source" directory references in \/CMakeLists.txt \#96 [\#111](https://github.com/nanoframework/nf-interpreter/pull/111) +- Rename nanoCLR [\#105](https://github.com/nanoframework/nf-interpreter/pull/105) +- Added empty line to make GitHub diff happy [\#103](https://github.com/nanoframework/nf-interpreter/pull/103) +- Correct buffer size for ST\_NUCLEO\_F091RC [\#102](https://github.com/nanoframework/nf-interpreter/pull/102) +- Add Monitor\_Reboot command [\#100](https://github.com/nanoframework/nf-interpreter/pull/100) +- \[WIP\] nanoCLR [\#95](https://github.com/nanoframework/nf-interpreter/pull/95) +- Fixed copyright notice in CMakeLists [\#94](https://github.com/nanoframework/nf-interpreter/pull/94) +- Fixed project name [\#88](https://github.com/nanoframework/nf-interpreter/pull/88) +- Import cmake build [\#84](https://github.com/nanoframework/nf-interpreter/pull/84) +- Renamed keepers to maintainers, fixed links [\#75](https://github.com/nanoframework/nf-interpreter/pull/75) +- Updated organization name nanoFramework [\#74](https://github.com/nanoframework/nf-interpreter/pull/74) +- Updated copyright notice header format to handle partial content [\#66](https://github.com/nanoframework/nf-interpreter/pull/66) +- Fix 58 [\#63](https://github.com/nanoframework/nf-interpreter/pull/63) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Fix variable names in WireProtocol\_Receiver [\#60](https://github.com/nanoframework/nf-interpreter/pull/60) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- Added Developer Certificate of Origin documentation [\#52](https://github.com/nanoframework/nf-interpreter/pull/52) +- Updated copyright notice header format [\#49](https://github.com/nanoframework/nf-interpreter/pull/49) +- Add official logo files [\#36](https://github.com/nanoframework/nf-interpreter/pull/36) +- Updated README-s [\#34](https://github.com/nanoframework/nf-interpreter/pull/34) +- \[WIP\] nanoBooter mbed-os sample implementation [\#32](https://github.com/nanoframework/nf-interpreter/pull/32) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- \[WIP\] Wire protocol proof-of-concept [\#31](https://github.com/nanoframework/nf-interpreter/pull/31) [[Area: Interpreter](https://github.com/nanoframework/nf-interpreter/labels/Area:%20Interpreter)] +- cosmetic changes in doc [\#29](https://github.com/nanoframework/nf-interpreter/pull/29) +- add preliminary versions of documentation [\#25](https://github.com/nanoframework/nf-interpreter/pull/25) +- update information about build deliverables [\#24](https://github.com/nanoframework/nf-interpreter/pull/24) +- Small correction on typos [\#17](https://github.com/nanoframework/nf-interpreter/pull/17) +- Add support for STM32F0 series [\#13](https://github.com/nanoframework/nf-interpreter/pull/13) +- Add readme file to perform as documentation index [\#12](https://github.com/nanoframework/nf-interpreter/pull/12) +- Add preliminary version of documentation with build and VS Code debug instructions [\#11](https://github.com/nanoframework/nf-interpreter/pull/11) +- Initial works on CMake build and debug for VS Code [\#10](https://github.com/nanoframework/nf-interpreter/pull/10) +- Added README-s, LICENSE and CONTRIBUTORS [\#1](https://github.com/nanoframework/nf-interpreter/pull/1) + + + +\* *This Change Log was automatically generated by [github_changelog_generator](https://github.com/skywinder/Github-Changelog-Generator)* \ No newline at end of file diff --git a/source/native/nf-interpreter/CMake/ChibiOS-Contrib.CMakeLists.cmake.in b/source/native/nf-interpreter/CMake/ChibiOS-Contrib.CMakeLists.cmake.in new file mode 100644 index 00000000..e0e66965 --- /dev/null +++ b/source/native/nf-interpreter/CMake/ChibiOS-Contrib.CMakeLists.cmake.in @@ -0,0 +1,22 @@ +cmake_minimum_required(VERSION 2.8.2) + +project(ChibiOS-Contrib-download NONE) + +include(ExternalProject) + +# download ChibiOS Community contributions source from GitHub repo +# need to specify nanoframework as the active branch +ExternalProject_Add( + ChibiOS-Contrib + PREFIX ChibiOS-Contrib + SOURCE_DIR ${CMAKE_BINARY_DIR}/ChibiOS-Contrib_Source + GIT_REPOSITORY https://github.com/nanoframework/ChibiOS-Contrib + GIT_TAG nanoframework # target specified branch + GIT_SHALLOW 1 # download only the tip of the branch, not the complete history + TIMEOUT 10 + LOG_DOWNLOAD 1 + # Disable all other steps + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND "" +) diff --git a/source/native/nf-interpreter/CMake/ChibiOS.CMakeLists.cmake.in b/source/native/nf-interpreter/CMake/ChibiOS.CMakeLists.cmake.in new file mode 100644 index 00000000..eaf0b167 --- /dev/null +++ b/source/native/nf-interpreter/CMake/ChibiOS.CMakeLists.cmake.in @@ -0,0 +1,21 @@ +cmake_minimum_required(VERSION 2.8.2) + +project(ChibiOS-download NONE) + +include(ExternalProject) + +# download ChibiOS source from official SVN repo +ExternalProject_Add( + ChibiOS + PREFIX ChibiOS + SOURCE_DIR ${CMAKE_BINARY_DIR}/ChibiOS_Source + GIT_REPOSITORY https://github.com/nanoframework/chibios + GIT_TAG ${CHIBIOS_GIT_TAG} # target specified branch + GIT_SHALLOW 1 # download only the tip of the branch, not the complete history + TIMEOUT 10 + LOG_DOWNLOAD 1 + # Disable all other steps + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND "" +) diff --git a/source/native/nf-interpreter/CMake/ChibiOS_target_os.h.in b/source/native/nf-interpreter/CMake/ChibiOS_target_os.h.in new file mode 100644 index 00000000..1621ff73 --- /dev/null +++ b/source/native/nf-interpreter/CMake/ChibiOS_target_os.h.in @@ -0,0 +1,33 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_OS_H_ +#define _TARGET_OS_H_ + +#define STR_HELPER(x) #x +#define STR(x) STR_HELPER(x) + +#define VERSION_MAJOR @nanoFramework_VERSION_MAJOR@U +#define VERSION_MINOR @nanoFramework_VERSION_MINOR@U +#define VERSION_BUILD @nanoFramework_VERSION_PATCH@U +#define VERSION_REVISION @nanoFramework_VERSION_TWEAK@U + +#define NANOCLR_LIGHT_MATH @TARGET_LIGHT_MATH@ +#define DP_FLOATINGPOINT @TARGET_DP_FLOATINGPOINT@ + +#define SUPPORT_ANY_BASE_CONVERSION @TARGET_SUPPORT_ANY_BASE_CONVERSION@ + +#define HAS_CONFIG_BLOCK @TARGET_HAS_CONFIG_BLOCK@ + +#define NANOCLR_REFLECTION @TARGET_NANOCLR_REFLECTION@ + +#define NANOCLR_SYSTEM_COLLECTIONS @TARGET_SYSTEM_COLLECTIONS@ + +#endif /* _TARGET_OS_H_ */ diff --git a/source/native/nf-interpreter/CMake/ESP32_target_os.h.in b/source/native/nf-interpreter/CMake/ESP32_target_os.h.in new file mode 100644 index 00000000..1ae5bc75 --- /dev/null +++ b/source/native/nf-interpreter/CMake/ESP32_target_os.h.in @@ -0,0 +1,30 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_OS_H_ +#define _TARGET_OS_H_ + +#define VERSION_MAJOR @nanoFramework_VERSION_MAJOR@U +#define VERSION_MINOR @nanoFramework_VERSION_MINOR@U +#define VERSION_BUILD @nanoFramework_VERSION_PATCH@U +#define VERSION_REVISION @nanoFramework_VERSION_TWEAK@U + +#define NANOCLR_LIGHT_MATH @TARGET_LIGHT_MATH@ +#define DP_FLOATINGPOINT @TARGET_DP_FLOATINGPOINT@ + +#define SUPPORT_ANY_BASE_CONVERSION @TARGET_SUPPORT_ANY_BASE_CONVERSION@ + +#define HAS_CONFIG_BLOCK @TARGET_HAS_CONFIG_BLOCK@ + +#define NANOCLR_REFLECTION @TARGET_NANOCLR_REFLECTION@ + +#define NANOCLR_SYSTEM_COLLECTIONS @TARGET_SYSTEM_COLLECTIONS@ + +#endif /* _TARGET_OS_H_ */ diff --git a/source/native/nf-interpreter/CMake/FreeRTOS.CMakeLists.cmake.in b/source/native/nf-interpreter/CMake/FreeRTOS.CMakeLists.cmake.in new file mode 100644 index 00000000..ac289de6 --- /dev/null +++ b/source/native/nf-interpreter/CMake/FreeRTOS.CMakeLists.cmake.in @@ -0,0 +1,21 @@ +cmake_minimum_required(VERSION 2.8.2) + +project(FreeRTOS-download NONE) + +include(ExternalProject) + +# download FreeRTOS source from official Amazon GitHub repo +ExternalProject_Add( + FreeRTOS + PREFIX FreeRTOS + SOURCE_DIR ${CMAKE_BINARY_DIR}/FreeRTOS_Source + GIT_REPOSITORY https://github.com/aws/amazon-freertos.git + GIT_TAG ${FREERTOS_VERSION_TAG} # target specified branch + GIT_SHALLOW 1 # download only the tip of the branch, not the complete history + TIMEOUT 10 + LOG_DOWNLOAD 1 + # Disable all other steps + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND "" +) diff --git a/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32F0xx_GCC_options.cmake b/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32F0xx_GCC_options.cmake new file mode 100644 index 00000000..7b89de2b --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32F0xx_GCC_options.cmake @@ -0,0 +1,47 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +################################################################# +# WHEN ADDING A NEW SERIES add the appropriate GCC options below +################################################################# + +# need to specify this for assembler +set(CMAKE_ASM_FLAGS " -mthumb -mcpu=cortex-m0 -mfloat-abi=soft -mabi=aapcs -x assembler-with-cpp" CACHE INTERNAL "asm compiler flags") + +# need to specify linker flags here +set(CMAKE_EXE_LINKER_FLAGS " -Wl,--gc-sections -Wl,--no-wchar-size-warning -Wl,--print-memory-usage -mthumb -mcpu=cortex-m0 -mfloat-abi=soft -mabi=aapcs -nostartfiles " CACHE INTERNAL "executable linker flags") + + +function(NF_SET_COMPILER_OPTIONS TARGET) + + # include any extra options coming from any extra args? + target_compile_options(${TARGET} PUBLIC ${ARGN} -mthumb -mcpu=cortex-m0 -mabi=aapcs -nostdlib -Wall -Wextra -Werror -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) + + # this series doesn't have FPU + target_compile_definitions(${TARGET} PUBLIC -DCORTEX_USE_FPU=FALSE) + +endfunction() + + +function(NF_SET_LINKER_OPTIONS TARGET) + + # request specs from newlib nano + set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " --specs=nano.specs ") + + # set extra linker flags + set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " ${ARGN}") + + # set optimization linker flags for RELEASE and MinSizeRel + if(CMAKE_BUILD_TYPE STREQUAL "Release" OR CMAKE_BUILD_TYPE STREQUAL "MinSizeRel") + set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " -flto -fuse-linker-plugin -Os") + endif() + + # set optimization flags + nf_set_optimization_options(${TARGET}) + + # set link map + nf_set_link_map(${TARGET}) + +endfunction() diff --git a/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake b/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake new file mode 100644 index 00000000..86a435fc --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32F0xx_sources.cmake @@ -0,0 +1,138 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# from startup_stm32f0xx.mk +# List of the ChibiOS generic STM32F0xx startup and CMSIS files. + +################################################################################ +# WHEN ADDING A NEW BOARD add the source code file for the STM32F0xx\platform.mk +################################################################################ + +set(CHIBIOS_PORT_SRCS + # startup code + crt1.c + vectors.S + crt0_v6m.S + + nvic.c + stm32_isr.c + hal_lld.c + + hal_adc_lld.c + hal_can_lld.c + hal_dac_lld.c + stm32_dma.c + stm32_exti.c + hal_pal_lld.c + hal_i2c_lld.c + hal_rtc_lld.c + + hal_i2s_lld.c + hal_spi_lld.c + + hal_st_lld.c + hal_gpt_lld.c + hal_icu_lld.c + hal_pwm_lld.c + + hal_serial_lld.c + hal_uart_lld.c + + hal_usb_lld.c + + hal_wdg_lld.c + + # RT + chcore.c + chcore_v6m.c + chcoreasm_v6m.S +) + +foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) + set(CHIBIOS_F0_SRC_FILE SRC_FILE-NOTFOUND) + find_file(CHIBIOS_F0_SRC_FILE ${SRC_FILE} + PATHS + + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx/compilers/GCC + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/startup/ARMCMx/compilers/GCC + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/common/ARMCMx + + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/STM32F0xx + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/ADCv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DACv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DMAv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/EXTIv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/GPIOv2 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/I2Cv2 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/RTCv2 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/SPIv2 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/TIMv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/USARTv2 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/USBv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/xWDGv1 + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${CHIBIOS_F0_SRC_FILE}") # debug helper + list(APPEND CHIBIOS_SOURCES ${CHIBIOS_F0_SRC_FILE}) +endforeach() + +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/portability/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/startup/ARMCMx/compilers/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/startup/ARMCMx/devices/STM32F0xx) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ext/ARM/CMSIS/Core/Include) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ext/ST/STM32F0xx) + +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/ADCv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DACv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DMAv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/EXTIv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/GPIOv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/I2Cv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/RTCv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/SPIv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/TIMv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/USARTv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/USBv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/xWDGv1) + + +#################################################################################### +# WHEN ADDING A NEW CHIBIOS OVERLAY component add the include directory(ies) below +#################################################################################### +# component STM32_FLASH +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv1) +# component STM32_CRC +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/CRCv1) +# component STM32_ONEWIRE +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/ONEWIREv1) + +############################################################################################################################### +# Add above the required include directory(ies) for a new nanoFramework overlay component that you are adding +# following the template below. +# +# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/) +############################################################################################################################### + + +#################################################################################################### +# WHEN ADDING A NEW CHIBIOS OVERLAY component add the source file(s) specific to this series below +#################################################################################################### +# component STM32_FLASH +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv1/flash_lld.c) +# component STM32_CRC +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/CRCv1/crc_lld.c) +# component STM32_ONEWIRE +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/ONEWIREv1/onewire_lld.c) + +########################################################################################################################## +# Add above ALL the source code file(s) low level driver specif for a series required for a new nanoFramework +# overlay component that you are adding following the template below. +# +# list(APPEND CHIBIOS_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/) +########################################################################################################################## diff --git a/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32F4xx_GCC_options.cmake b/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32F4xx_GCC_options.cmake new file mode 100644 index 00000000..a7d444ba --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32F4xx_GCC_options.cmake @@ -0,0 +1,47 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +################################################################# +# WHEN ADDING A NEW SERIES add the appropriate GCC options below +################################################################# + +# need to specify this for assembler +set(CMAKE_ASM_FLAGS " -mthumb -mcpu=cortex-m4 -x assembler-with-cpp" CACHE INTERNAL "asm compiler flags") + +# need to specify linker flags here +set(CMAKE_EXE_LINKER_FLAGS " -Wl,--gc-sections -Wl,--no-wchar-size-warning -Wl,--print-memory-usage -mthumb -mcpu=cortex-m4 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mabi=aapcs -nostartfiles " CACHE INTERNAL "executable linker flags") + + +function(NF_SET_COMPILER_OPTIONS TARGET) + + # include any extra options coming from any extra args? + target_compile_options(${TARGET} PUBLIC ${ARGN} -mthumb -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mabi=aapcs -nostdlib -Wall -Wextra -Werror -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) + + # this series has FPU + target_compile_definitions(${TARGET} PUBLIC -DCORTEX_USE_FPU=TRUE) + +endfunction() + + +function(NF_SET_LINKER_OPTIONS TARGET) + + # request specs from newlib nano + set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " --specs=nano.specs ") + + # set extra linker flags + set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " ${ARGN}") + + # set optimization linker flags for RELEASE and MinSizeRel + if(CMAKE_BUILD_TYPE STREQUAL "Release" OR CMAKE_BUILD_TYPE STREQUAL "MinSizeRel") + set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " -flto -fuse-linker-plugin -Os") + endif() + + # set optimization flags + nf_set_optimization_options(${TARGET}) + + # set link map + nf_set_link_map(${TARGET}) + +endfunction() diff --git a/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake b/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake new file mode 100644 index 00000000..8a25d5ea --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32F4xx_sources.cmake @@ -0,0 +1,166 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# from startup_stm32f4xx.mk +# List of the ChibiOS generic STM32F4xx startup and CMSIS files. + +################################################################################################ +# WHEN ADDING A NEW BOARD add the source code file for the hal/ports/STM32/STM32F4xx/platform.mk +################################################################################################ + +set(CHIBIOS_PORT_SRCS + # startup code + crt1.c + vectors.S + crt0_v7m.S + + nvic.c + stm32_isr.c + hal_lld.c + + hal_adc_lld.c + hal_can_lld.c + hal_crypto_lld.c + hal_dac_lld.c + stm32_dma.c + stm32_exti.c + hal_pal_lld.c + hal_i2c_lld.c + hal_mac_lld.c + hal_usb_lld.c + hal_wspi_lld.c + hal_trng_lld.c + hal_rtc_lld.c + hal_sdc_lld.c + + hal_i2s_lld.c + hal_spi_lld.c + + hal_st_lld.c + hal_gpt_lld.c + hal_icu_lld.c + hal_pwm_lld.c + + hal_serial_lld.c + hal_uart_lld.c + + hal_wdg_lld.c + + # RT + chcore.c + chcore_v7m.c + chcoreasm_v7m.S +) + +foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) + set(CHIBIOS_F4_SRC_FILE SRC_FILE-NOTFOUND) + find_file(CHIBIOS_F4_SRC_FILE ${SRC_FILE} + PATHS + + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx/compilers/GCC + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/startup/ARMCMx/compilers/GCC + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/common/ARMCMx + + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/STM32F4xx + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/ADCv2 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CRYPv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DACv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DMAv2 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/EXTIv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/GPIOv2 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/I2Cv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/MACv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/OTGv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/QUADSPIv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/RNGv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/RTCv2 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/SDIOv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/SPIv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/TIMv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/USARTv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/xWDGv1 + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${CHIBIOS_F4_SRC_FILE}") # debug helper + list(APPEND CHIBIOS_SOURCES ${CHIBIOS_F4_SRC_FILE}) +endforeach() + +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/portability/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/startup/ARMCMx/compilers/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/startup/ARMCMx/devices/STM32F4xx) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ext/ARM/CMSIS/Core/Include) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ext/ST/STM32F4xx) + +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/ADCv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CRYPv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DACv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DMAv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/EXTIv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/GPIOv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/I2Cv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/MACv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/OTGv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/QUADSPIv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/RNGv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/RTCv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/SDIOv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/SPIv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/TIMv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/USARTv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/xWDGv1) + + +#################################################################################### +# WHEN ADDING A NEW CHIBIOS OVERLAY component add the include directory(ies) below +#################################################################################### +# component STM32_FLASH +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv2) +# component STM32_CRC +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/CRCv1) +# component STM32_RNG +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/RNGv1) +# component STM32_FSMC (Flexible Memory Controller) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1) +# component STM32_ONEWIRE (One Wire driver) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/ONEWIREv1) +# component STM32_QSPI (Quad-SPI) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/QSPIv1) + +############################################################################################################################### +# Add above the required include directory(ies) for a new nanoFramework overlay component that you are adding +# following the template below. +# +# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/) +############################################################################################################################### + + +#################################################################################################### +# WHEN ADDING A NEW CHIBIOS OVERLAY component add the source file(s) specific to this series below +#################################################################################################### +# component STM32_FLASH +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv2/flash_lld.c) +# component STM32_CRC +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/CRCv1/crc_lld.c) +# component STM32_RNG +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/RNGv1/rng_lld.c) +# component STM32_FSMC (Flexible Memory Controller) +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_nand_lld.c) +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram_lld.c) +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram_lld.c) +# component STM32_ONEWIRE +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/ONEWIREv1/onewire_lld.c) +# component STM32_QSPI (Quad-SPI) +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/QSPIv1/qspi_lld.c) + +########################################################################################################################## +# Add above ALL the source code file(s) low level driver specif for a series required for a new nanoFramework +# overlay component that you are adding following the template below. +# +# list(APPEND CHIBIOS_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/) +########################################################################################################################## diff --git a/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32F7xx_GCC_options.cmake b/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32F7xx_GCC_options.cmake new file mode 100644 index 00000000..5c901ec9 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32F7xx_GCC_options.cmake @@ -0,0 +1,48 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +################################################################# +# WHEN ADDING A NEW SERIES add the appropriate GCC options below +################################################################# + +# need to specify this for assembler +set(CMAKE_ASM_FLAGS " -mthumb -mcpu=cortex-m7 -x assembler-with-cpp" CACHE INTERNAL "asm compiler flags") + +# need to specify linker flags here +set(CMAKE_EXE_LINKER_FLAGS " -Wl,--gc-sections -Wl,--no-wchar-size-warning -Wl,--print-memory-usage -mthumb -mcpu=cortex-m7 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mabi=aapcs -nostartfiles " CACHE INTERNAL "executable linker flags") + + +function(NF_SET_COMPILER_OPTIONS TARGET) + + # include any extra options coming from any extra args? + # STMF7 cores have SP and DP, the default is SP. DP can be set if developer realy needs that. + target_compile_options(${TARGET} PUBLIC ${ARGN} -mthumb -mcpu=cortex-m7 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mabi=aapcs -nostdlib -Wall -Wextra -Werror -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) + + # this series has FPU + target_compile_definitions(${TARGET} PUBLIC -DCORTEX_USE_FPU=TRUE) + +endfunction() + + +function(NF_SET_LINKER_OPTIONS TARGET) + + # request specs from newlib nano + set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " --specs=nano.specs ") + + # set extra linker flags + set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " ${ARGN}") + + # set optimization linker flags for RELEASE and MinSizeRel + if(CMAKE_BUILD_TYPE STREQUAL "Release" OR CMAKE_BUILD_TYPE STREQUAL "MinSizeRel") + set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " -flto -fuse-linker-plugin -Os") + endif() + + # set optimization flags + nf_set_optimization_options(${TARGET}) + + # set link map + nf_set_link_map(${TARGET}) + +endfunction() diff --git a/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake b/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake new file mode 100644 index 00000000..f3b2ff2c --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32F7xx_sources.cmake @@ -0,0 +1,168 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# from startup_stm32f7xx.mk +# List of the ChibiOS generic STM32F7xx startup and CMSIS files. + +################################################################################################ +# WHEN ADDING A NEW BOARD add the source code file for the hal/ports/STM32/STM32F7xx/platform.mk +################################################################################################ + +set(CHIBIOS_PORT_SRCS + # startup code + crt1.c + vectors.S + crt0_v7m.S + + nvic.c + stm32_isr.c + hal_lld.c + + hal_adc_lld.c + hal_can_lld.c + hal_crypto_lld.c + hal_dac_lld.c + stm32_dma.c + stm32_exti.c + hal_pal_lld.c + hal_i2c_lld.c + hal_mac_lld.c + hal_usb_lld.c + hal_wspi_lld.c + hal_trng_lld.c + hal_rtc_lld.c + hal_sdc_lld.c + + hal_i2s_lld.c + hal_spi_lld.c + + hal_st_lld.c + hal_gpt_lld.c + hal_icu_lld.c + hal_pwm_lld.c + + hal_serial_lld.c + hal_uart_lld.c + + hal_wdg_lld.c + + # RT + chcore.c + chcore_v7m.c + chcoreasm_v7m.S +) + +foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) + set(CHIBIOS_F7_SRC_FILE SRC_FILE-NOTFOUND) + find_file(CHIBIOS_F7_SRC_FILE ${SRC_FILE} + PATHS + + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx/compilers/GCC + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/startup/ARMCMx/compilers/GCC + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/common/ARMCMx + + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/STM32F7xx + + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/ADCv2 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CRYPv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DACv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DMAv2 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/EXTIv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/GPIOv2 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/I2Cv2 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/MACv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/OTGv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/QUADSPIv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/RNGv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/RTCv2 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/SDMMCv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/SPIv2 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/TIMv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/USARTv2 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/xWDGv1 + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${CHIBIOS_F7_SRC_FILE}") # debug helper + list(APPEND CHIBIOS_SOURCES ${CHIBIOS_F7_SRC_FILE}) +endforeach() + +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/portability/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/startup/ARMCMx/compilers/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/startup/ARMCMx/devices/STM32F7xx) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ext/ARM/CMSIS/Core/Include) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ext/ST/STM32F7xx) + +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/ADCv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CRYPv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DACv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DMAv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/EXTIv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/GPIOv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/I2Cv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/MACv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/OTGv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/QUADSPIv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/RNGv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/RTCv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/SDMMCv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/SPIv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/TIMv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/USARTv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/xWDGv1) + + +#################################################################################### +# WHEN ADDING A NEW CHIBIOS OVERLAY component add the include directory(ies) below +#################################################################################### +# component STM32_FLASH +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv2) +# component STM32_CRC +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/CRCv1) +# component STM32_RNG +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/RNGv1) +# component STM32_FSMC (Flexible Memory Controller) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1) +# component STM32_ONEWIRE +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/ONEWIREv1) +# component STM32_QSPI (Quad-SPI) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/QSPIv1) +list(APPEND CHIBIOS_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/STM32_CubePackage_Source/Drivers/STM32F7xx_HAL_Driver/Inc") + +############################################################################################################################### +# Add above the required include directory(ies) for a new nanoFramework overlay component that you are adding +# following the template below. +# +# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/) +############################################################################################################################### + + +#################################################################################################### +# WHEN ADDING A NEW CHIBIOS OVERLAY component add the source file(s) specific to this series below +#################################################################################################### +# component STM32_FLASH +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv2/flash_lld.c) +# component STM32_CRC +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/CRCv1/crc_lld.c) +# component STM32_RNG +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/RNGv1/rng_lld.c) +# component STM32_FSMC (Flexible Memory Controller) +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_nand_lld.c) +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram_lld.c) +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram_lld.c) +# component STM32_ONEWIRE +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/ONEWIREv1/onewire_lld.c) +# component STM32_QSPI (Quad-SPI) +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/QSPIv1/qspi_lld.c) + +########################################################################################################################## +# Add above ALL the source code file(s) low level driver specif for a series required for a new nanoFramework +# overlay component that you are adding following the template below. +# +# list(APPEND CHIBIOS_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/) +########################################################################################################################## diff --git a/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32H7xx_GCC_options.cmake b/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32H7xx_GCC_options.cmake new file mode 100644 index 00000000..5c901ec9 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32H7xx_GCC_options.cmake @@ -0,0 +1,48 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +################################################################# +# WHEN ADDING A NEW SERIES add the appropriate GCC options below +################################################################# + +# need to specify this for assembler +set(CMAKE_ASM_FLAGS " -mthumb -mcpu=cortex-m7 -x assembler-with-cpp" CACHE INTERNAL "asm compiler flags") + +# need to specify linker flags here +set(CMAKE_EXE_LINKER_FLAGS " -Wl,--gc-sections -Wl,--no-wchar-size-warning -Wl,--print-memory-usage -mthumb -mcpu=cortex-m7 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mabi=aapcs -nostartfiles " CACHE INTERNAL "executable linker flags") + + +function(NF_SET_COMPILER_OPTIONS TARGET) + + # include any extra options coming from any extra args? + # STMF7 cores have SP and DP, the default is SP. DP can be set if developer realy needs that. + target_compile_options(${TARGET} PUBLIC ${ARGN} -mthumb -mcpu=cortex-m7 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -mabi=aapcs -nostdlib -Wall -Wextra -Werror -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) + + # this series has FPU + target_compile_definitions(${TARGET} PUBLIC -DCORTEX_USE_FPU=TRUE) + +endfunction() + + +function(NF_SET_LINKER_OPTIONS TARGET) + + # request specs from newlib nano + set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " --specs=nano.specs ") + + # set extra linker flags + set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " ${ARGN}") + + # set optimization linker flags for RELEASE and MinSizeRel + if(CMAKE_BUILD_TYPE STREQUAL "Release" OR CMAKE_BUILD_TYPE STREQUAL "MinSizeRel") + set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " -flto -fuse-linker-plugin -Os") + endif() + + # set optimization flags + nf_set_optimization_options(${TARGET}) + + # set link map + nf_set_link_map(${TARGET}) + +endfunction() diff --git a/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake b/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake new file mode 100644 index 00000000..d31fd89e --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32H7xx_sources.cmake @@ -0,0 +1,165 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# from os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32h7xx.mk +# List of the ChibiOS generic STM32H7xx startup and CMSIS files. + +################################################################################################ +# WHEN ADDING A NEW BOARD add the source code file for the hal/ports/STM32/STM32H7xx/platform.mk +################################################################################################ + +set(CHIBIOS_PORT_SRCS + # startup code + crt1.c + vectors.S + crt0_v7m.S + + nvic.c + stm32_isr.c + hal_lld.c + + hal_adc_lld.c + hal_can_lld.c + hal_crypto_lld.c + hal_dac_lld.c + stm32_dma.c + stm32_exti.c + hal_pal_lld.c + hal_i2c_lld.c + hal_mac_lld.c + hal_usb_lld.c + hal_wspi_lld.c + hal_trng_lld.c + hal_rtc_lld.c + hal_sdc_lld.c + + hal_i2s_lld.c + hal_spi_lld.c + + hal_st_lld.c + hal_gpt_lld.c + hal_icu_lld.c + hal_pwm_lld.c + + hal_serial_lld.c + hal_uart_lld.c + + hal_wdg_lld.c + + # RT + chcore.c + chcore_v7m.c + chcoreasm_v7m.S +) + +foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) + set(CHIBIOS_H7_SRC_FILE SRC_FILE-NOTFOUND) + find_file(CHIBIOS_H7_SRC_FILE ${SRC_FILE} + PATHS + + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx/compilers/GCC + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/startup/ARMCMx/compilers/GCC + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/common/ARMCMx + + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/STM32H7xx + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/ADCv4 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CRYPv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DACv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DMAv3 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/EXTIv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/GPIOv3 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/I2Cv3 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/MACv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/OTGv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/QUADSPIv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/RNGv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/RTCv2 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/RTCv2 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/SDMMCv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/SPIv3 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/TIMv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/USARTv2 + # ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/USBv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/xWDGv1 + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${CHIBIOS_H7_SRC_FILE}") # debug helper + list(APPEND CHIBIOS_SOURCES ${CHIBIOS_H7_SRC_FILE}) +endforeach() + +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/portability/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/startup/ARMCMx/compilers/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/startup/ARMCMx/devices/STM32H7xx) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ext/ARM/CMSIS/Core/Include) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ext/ST/STM32H7xx) + +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/ADCv4) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CRYPv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DACv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DMAv3) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/EXTIv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/GPIOv3) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/I2Cv3) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/MACv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/OTGv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/QUADSPIv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/RNGv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/RTCv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/SDMMCv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/SPIv3) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/TIMv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/USARTv2) +# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/USBv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/xWDGv1) + + +#################################################################################### +# WHEN ADDING A NEW CHIBIOS OVERLAY component add the include directory(ies) below +#################################################################################### +# component STM32_FLASH +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv2) +# component STM32_CRC +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/CRCv1) +# component STM32_RNG +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/RNGv1) +# component STM32_FSMC (Flexible Memory Controller) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1) +# component STM32_ONEWIRE +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/ONEWIREv1) + +############################################################################################################################### +# Add above the required include directory(ies) for a new nanoFramework overlay component that you are adding +# following the template below. +# +# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/) +############################################################################################################################### + + +#################################################################################################### +# WHEN ADDING A NEW CHIBIOS OVERLAY component add the source file(s) specific to this series below +#################################################################################################### +# component STM32_FLASH +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv2/flash_lld.c) +# component STM32_CRC +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/CRCv1/crc_lld.c) +# component STM32_RNG +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/RNGv1/rng_lld.c) +# component STM32_FSMC (Flexible Memory Controller) +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_nand_lld.c) +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram_lld.c) +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram_lld.c) +# component STM32_ONEWIRE +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/ONEWIREv1/onewire_lld.c) + +########################################################################################################################## +# Add above ALL the source code file(s) low level driver specif for a series required for a new nanoFramework +# overlay component that you are adding following the template below. +# +# list(APPEND CHIBIOS_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/) +########################################################################################################################## diff --git a/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32L0xx_GCC_options.cmake b/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32L0xx_GCC_options.cmake new file mode 100644 index 00000000..a2bd1ea3 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32L0xx_GCC_options.cmake @@ -0,0 +1,51 @@ +# +# Copyright (c) 2018 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +################################################################# +# WHEN ADDING A NEW SERIES add the appropriate GCC options below +################################################################# + +# need to specify this for assembler +##################################################################### +# because nanoCLR is loaded the VTOR has to be init in ChibiOS CRT0 +# this define has to be placed here because it's on an assembly file +##################################################################### +set(CMAKE_ASM_FLAGS " -mthumb -mcpu=cortex-m0plus -mfloat-abi=soft -mabi=aapcs -mtune=cortex-m0plus -x assembler-with-cpp -DCRT0_VTOR_INIT=TRUE" CACHE INTERNAL "asm compiler flags") + +# need to specify linker flags here +set(CMAKE_EXE_LINKER_FLAGS " -Wl,--gc-sections -Wl,--no-wchar-size-warning -Wl,--print-memory-usage -mthumb -mcpu=cortex-m0plus -mfloat-abi=soft -mabi=aapcs -mtune=cortex-m0plus -nostartfiles " CACHE INTERNAL "executable linker flags") + + +function(NF_SET_COMPILER_OPTIONS TARGET) + + # include any extra options coming from any extra args? + target_compile_options(${TARGET} PUBLIC ${ARGN} -mthumb -mcpu=cortex-m0plus -mfloat-abi=soft -mabi=aapcs -mtune=cortex-m0plus -nostdlib -Wall -Wextra -Werror -ffunction-sections -fshort-wchar -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -frounding-math -fsignaling-nans -ffloat-store -fno-math-errno -ftree-vectorize -fcheck-new ) + + # this series doesn't have FPU + target_compile_definitions(${TARGET} PUBLIC -DCORTEX_USE_FPU=FALSE) + +endfunction() + + +function(NF_SET_LINKER_OPTIONS TARGET) + + # request specs from newlib nano + set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " --specs=nano.specs ") + + # set extra linker flags + set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " ${ARGN}") + + # set optimization linker flags for RELEASE and MinSizeRel + if(CMAKE_BUILD_TYPE STREQUAL "Release" OR CMAKE_BUILD_TYPE STREQUAL "MinSizeRel") + set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " -flto -fuse-linker-plugin -Os") + endif() + + # set optimization flags + nf_set_optimization_options(${TARGET}) + + # set link map + nf_set_link_map(${TARGET}) + +endfunction() diff --git a/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake b/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake new file mode 100644 index 00000000..fe07cfc4 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/CHIBIOS_STM32L0xx_sources.cmake @@ -0,0 +1,142 @@ +# +# Copyright (c) 2018 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# from startup_stm32l0xx.mk +# List of the ChibiOS generic STM32L0xx startup and CMSIS files. + +################################################################################ +# WHEN ADDING A NEW BOARD add the source code file for the STM32L0xx\platform.mk +################################################################################ + +set(CHIBIOS_PORT_SRCS + # startup code + crt1.c + vectors.S + crt0_v6m.S + + nvic.c + stm32_isr.c + hal_lld.c + + hal_adc_lld.c + hal_can_lld.c + hal_dac_lld.c + stm32_dma.c + stm32_exti.c + hal_pal_lld.c + hal_i2c_lld.c + hal_rtc_lld.c + + hal_i2s_lld.c + hal_spi_lld.c + + hal_st_lld.c + hal_gpt_lld.c + hal_icu_lld.c + hal_pwm_lld.c + + hal_serial_lld.c + hal_uart_lld.c + + hal_usb_lld.c + + hal_wdg_lld.c + + # RT + chcore.c + chcore_v6m.c + chcoreasm_v6m.S +) + +foreach(SRC_FILE ${CHIBIOS_PORT_SRCS}) + set(CHIBIOS_L0_SRC_FILE SRC_FILE-NOTFOUND) + find_file(CHIBIOS_L0_SRC_FILE ${SRC_FILE} + PATHS + + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx/compilers/GCC + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/startup/ARMCMx/compilers/GCC + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/common/ARMCMx + + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/STM32L0xx + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/ADCv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DACv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DMAv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/EXTIv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/GPIOv2 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/I2Cv2 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/RTCv2 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/SPIv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/TIMv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/USARTv2 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/USBv1 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/xWDGv1 + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${CHIBIOS_L0_SRC_FILE}") # debug helper + list(APPEND CHIBIOS_SOURCES ${CHIBIOS_L0_SRC_FILE}) +endforeach() + +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/portability/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/startup/ARMCMx/compilers/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/startup/ARMCMx/devices/STM32L0xx) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ext/ARM/CMSIS/Core/Include) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ext/ST/STM32L0xx) + +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/ADCv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/CANv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DACv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/DMAv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/EXTIv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/GPIOv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/I2Cv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/RTCv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/SPIv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/TIMv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/USARTv2) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/USBv1) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/LLD/xWDGv1) + + +#################################################################################### +# WHEN ADDING A NEW CHIBIOS OVERLAY component add the include directory(ies) below +#################################################################################### +# component STM32_FLASH +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv3) +# component STM32_CRC +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/CRCv1) +# component STM32_RNG +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/RNGv1) +# component STM32_ONEWIRE +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/ONEWIREv1) + +############################################################################################################################### +# Add above the required include directory(ies) for a new nanoFramework overlay component that you are adding +# following the template below. +# +# list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/) +############################################################################################################################### + + +#################################################################################################### +# WHEN ADDING A NEW CHIBIOS OVERLAY component add the source file(s) specific to this series below +#################################################################################################### +# component STM32_FLASH +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv3/flash_lld.c) +# component STM32_CRC +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/CRCv1/crc_lld.c) +# component STM32_RNG +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/RNGv1/rng_lld.c) +# component STM32_ONEWIRE +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/ONEWIREv1/onewire_lld.c) + +########################################################################################################################## +# Add above ALL the source code file(s) low level driver specif for a series required for a new nanoFramework +# overlay component that you are adding following the template below. +# +# list(APPEND CHIBIOS_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/) +########################################################################################################################## diff --git a/source/native/nf-interpreter/CMake/Modules/FindBuildUtils.cmake b/source/native/nf-interpreter/CMake/Modules/FindBuildUtils.cmake new file mode 100644 index 00000000..6373e03c --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindBuildUtils.cmake @@ -0,0 +1,91 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +function(NF_GENERATE_DFU_PACKAGE FILE1 ADDRESS1 FILE2 ADDRESS2 OUTPUTFILENAME) + + add_custom_command( + + TARGET ${NANOCLR_PROJECT_NAME}.elf POST_BUILD + + COMMAND ${TOOL_HEX2DFU_PREFIX}/hex2dfu + + -b="${FILE1}" -a="${ADDRESS1}" + -b="${FILE2}" -a="${ADDRESS2}" + -o="${OUTPUTFILENAME}" + + WORKING_DIRECTORY ${TOOL_HEX2DFU_PREFIX} + + COMMENT "exporting bin files to DFU image" + ) + + # need to add a dependency of NANOCLR to NANOBOOTER because DFU util needs bin outputs of both targets + add_dependencies(${NANOCLR_PROJECT_NAME}.elf ${NANOBOOTER_PROJECT_NAME}.elf) + +endfunction() + +function(NF_GENERATE_BUILD_OUTPUT_FILES TARGET) + + # need to remove the .elf suffix from target name + string(FIND ${TARGET} "." TARGET_EXTENSION_DOT_INDEX) + string(SUBSTRING ${TARGET} 0 ${TARGET_EXTENSION_DOT_INDEX} TARGET_SHORT) + + set(TARGET_HEX_FILE ${PROJECT_BINARY_DIR}/${TARGET_SHORT}.hex) + set(TARGET_S19_FILE ${PROJECT_BINARY_DIR}/${TARGET_SHORT}.s19) + set(TARGET_BIN_FILE ${PROJECT_BINARY_DIR}/${TARGET_SHORT}.bin) + set(TARGET_DUMP_FILE ${PROJECT_BINARY_DIR}/${TARGET_SHORT}.lst) + + if(CMAKE_BUILD_TYPE EQUAL "Release" OR CMAKE_BUILD_TYPE EQUAL "MinSizeRel") + + add_custom_command(TARGET ${TARGET_SHORT}.elf POST_BUILD + # copy target image to other formats + COMMAND ${CMAKE_OBJCOPY} -Oihex $ ${TARGET_HEX_FILE} + COMMAND ${CMAKE_OBJCOPY} -Osrec $ ${TARGET_S19_FILE} + COMMAND ${CMAKE_OBJCOPY} -Obinary $ ${TARGET_BIN_FILE} + + # copy target file to build folder (this is only usefull for debugging in VS Code because of path in launch.json) + COMMAND ${CMAKE_OBJCOPY} $ ${PROJECT_SOURCE_DIR}/build/${TARGET_SHORT}.elf + + COMMENT "Generate nanoBooter HEX and BIN files for deployment") + + else() + + add_custom_command(TARGET ${TARGET_SHORT}.elf POST_BUILD + # copy target image to other formats + COMMAND ${CMAKE_OBJCOPY} -Oihex $ ${TARGET_HEX_FILE} + COMMAND ${CMAKE_OBJCOPY} -Osrec $ ${TARGET_S19_FILE} + COMMAND ${CMAKE_OBJCOPY} -Obinary $ ${TARGET_BIN_FILE} + + # copy target file to build folder (this is only usefull for debugging in VS Code because of path in launch.json) + COMMAND ${CMAKE_OBJCOPY} $ ${PROJECT_SOURCE_DIR}/build/${TARGET_SHORT}.elf + + # dump target image as source code listing + # ONLY when DEBUG info is available, this is on 'Debug' and 'RelWithDebInfo' + COMMAND ${CMAKE_OBJDUMP} -d -EL -S $ > ${TARGET_DUMP_FILE} + + COMMENT "Generate nanoBooter HEX and BIN files for deployment, LST file for debug") + + endif() + + nf_add_hex_bin_dump_targets(${TARGET}) + + # add this to print the size of the output targets + nf_print_size_of_targets(${TARGET}) + +endfunction() + + +####################################################################################################################################### +# this function sets the linker options AND a specific linker file (full path and name, including extension) +function(NF_SET_LINKER_OPTIONS_AND_FILE TARGET LINKER_FILE_NAME) + + get_target_property(TARGET_LD_FLAGS ${TARGET} LINK_FLAGS) + if(TARGET_LD_FLAGS) + set(TARGET_LD_FLAGS "-T${LINKER_FILE_NAME} ${TARGET_LD_FLAGS}") + else() + set(TARGET_LD_FLAGS "-T${LINKER_FILE_NAME}") + endif() + set_target_properties(${TARGET} PROPERTIES LINK_FLAGS ${TARGET_LD_FLAGS}) + +endfunction() diff --git a/source/native/nf-interpreter/CMake/Modules/FindCHIBIOS.cmake b/source/native/nf-interpreter/CMake/Modules/FindCHIBIOS.cmake new file mode 100644 index 00000000..41fca7de --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindCHIBIOS.cmake @@ -0,0 +1,181 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +################################################################################################################################### +# WHEN ADDING A NEW SERIES, add the respective name to the list below along with the CMake files with GCC options and source files +################################################################################################################################### + +# check if the series name is supported + +set(CHIBIOS_STM_SUPPORTED_SERIES "STM32F0xx" "STM32F4xx" "STM32F7xx" "STM32H7xx" "TICC3200" CACHE INTERNAL "supported STM series names for ChibiOS") +set(CHIBIOS_TI_SUPPORTED_SERIES "TICC3200" CACHE INTERNAL "supported TI series names for ChibiOS") + +list(FIND CHIBIOS_STM_SUPPORTED_SERIES ${TARGET_SERIES} TARGET_SERIES_NAME_INDEX) +if(TARGET_SERIES_NAME_INDEX EQUAL -1) + # series is NOT supported by STM + # try TI + list(FIND CHIBIOS_TI_SUPPORTED_SERIES ${TARGET_SERIES} TARGET_SERIES_NAME_INDEX) + if(TARGET_SERIES_NAME_INDEX EQUAL -1) + message(FATAL_ERROR "\n\nSorry but the ${TARGET_SERIES} is not supported at this time...\nYou can wait for it to be added, or you might want to contribute by working on a PR for it.\n\n") + else() + # series is supported by TI + set(TARGET_VENDOR "TI" CACHE INTERNAL "target vendor is TI") + endif() +else() + # series is supported by STM + set(TARGET_VENDOR "STM" CACHE INTERNAL "target vendor is STM") +endif() + +# including here the CMake files for the source files specific to the target series +include(CHIBIOS_${TARGET_SERIES}_sources) +# and here the GCC options tuned for the target series +include(CHIBIOS_${TARGET_SERIES}_GCC_options) + +# message("ChibiOS board series is ${TARGET_SERIES}") # debug helper + +# set include directories for ChibiOS +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/license) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/common/ARMCMx) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/include) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/boards/${CHIBIOS_BOARD}) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/osal/rt) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/oslib/include) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/rt/include) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/ports/STM32/${TARGET_SERIES}) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ports/ARMCMx/compilers/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/abstractions/cmsis_os) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/startup/ARMCMx/compilers/GCC) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ext/CMSIS/include) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/ext/CMSIS/ST/${TARGET_SERIES}) + +# append dummy include directory when not using ChibiOS-Contrib +if(NOT CHIBIOS_CONTRIB_REQUIRED) + list(APPEND CHIBIOS_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/dummy_includes") +endif() + +# append include directory for boards in the nanoFramework ChibiOS 'overlay' +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/boards/${CHIBIOS_BOARD}) + +# append include directory for boards in the nanoFramework ChibiOS 'overlay' provideded by the community +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets-community/CMSIS-OS/ChibiOS/nf-overlay/os/hal/boards/${CHIBIOS_BOARD}) + +# +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CMSIS/TI/${TARGET_SERIES}) +list(APPEND CHIBIOS_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/startup/ARMCMx/devices/${TARGET_SERIES}) + + +# source files and GCC options according to target vendor and series + +# source files for ChibiOS +set(CHIBIOS_SRCS + # HAL-OSAL files + hal.c + hal_st.c + + hal_buffers.c + hal_queues.c + hal_mmcsd.c + + hal_adc.c + hal_can.c + hal_crypto.c + hal_dac.c + hal_gpt.c + hal_i2c.c + hal_i2s.c + hal_icu.c + hal_mac.c + hal_mmc_spi.c + hal_pal.c + hal_pwm.c + hal_rtc.c + hal_sdc.c + hal_serial.c + hal_serial_usb.c + hal_sio.c + hal_spi.c + hal_trng.c + hal_uart.c + hal_usb.c + hal_wdg.c + hal_wspi.c + + # OSAL RT + osal.c + + # RT + chsys.c + chdebug.c + chtrace.c + chvt.c + chschd.c + chthreads.c + chtm.c + chstats.c + chregistry.c + chsem.c + chmtx.c + chcond.c + chevents.c + chmsg.c + chdynamic.c + + chmboxes.c + chmemcore.c + chmemheaps.c + chmempools.c + chpipes.c + chfactory.c + + # required to use malloc and other newlib stuff + syscalls.c + + # CMSIS + cmsis_os.c + + # board file(s) + board.c + +) + +foreach(SRC_FILE ${CHIBIOS_SRCS}) + set(CHIBIOS_SRC_FILE SRC_FILE -NOTFOUND) + find_file(CHIBIOS_SRC_FILE ${SRC_FILE} + PATHS + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/src + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/osal/rt + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/rt/src + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/oslib/src + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/common/abstractions/cmsis_os + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/various + + # the following hint order is for the board.c file, it has to match the search order of the main CMake otherwise we'll pick one that is the pair + # this path hint is for OEM boards for which the board file(s) are probably located directly in the "target" folder along with remaining files + ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/${CHIBIOS_BOARD} + + # this path hint is for the alternative boards folder in the nanoFramework ChibiOS 'overlay' + ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/boards/${CHIBIOS_BOARD} + + # this path hint is for the usual location of the board.c file + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/boards/${CHIBIOS_BOARD} + + # this path hint is for the alternative boards folder in the nanoFramework ChibiOS 'overlay' provideded by the community + ${PROJECT_SOURCE_DIR}/targets-community/CMSIS-OS/ChibiOS/nf-overlay/os/hal/boards/${CHIBIOS_BOARD} + + # this path hint is for Community provided boards that are located directly in the "targets-community" folder + ${PROJECT_SOURCE_DIR}/targets-community/CMSIS-OS/ChibiOS/${CHIBIOS_BOARD} + + CMAKE_FIND_ROOT_PATH_BOTH + ) + #message("${SRC_FILE} >> ${CHIBIOS_SRC_FILE}") # debug helper + list(APPEND CHIBIOS_SOURCES ${CHIBIOS_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(CHIBIOS DEFAULT_MSG CHIBIOS_INCLUDE_DIRS CHIBIOS_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindCHIBIOS_FATFS.cmake b/source/native/nf-interpreter/CMake/Modules/FindCHIBIOS_FATFS.cmake new file mode 100644 index 00000000..1b2ae5e4 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindCHIBIOS_FATFS.cmake @@ -0,0 +1,64 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +execute_process( + COMMAND ${CMAKE_COMMAND} -E tar xvf ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/fatfs-0.13_patched.7z + WORKING_DIRECTORY ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/ +) + + +# List of the required FatFs include files. +list(APPEND CHIBIOS_FATFS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/fatfs/src) + + +set(FATFS_SRCS + # bindings + fatfs_syscall.c + + # fatfs + ff.c + ffunicode.c +) + +foreach(SRC_FILE ${FATFS_SRCS}) + set(FATFS_SRC_FILE SRC_FILE -NOTFOUND) + find_file(FATFS_SRC_FILE ${SRC_FILE} + PATHS + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/various/fatfs_bindings + ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/fatfs/src + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${FATFS_SRC_FILE}") # debug helper + list(APPEND CHIBIOS_FATFS_SOURCES ${FATFS_SRC_FILE}) +endforeach() + +# fatfs_diskio is hacked because of USB Host, so we need to use the source from the appropriate location +if(NF_FEATURE_HAS_USB_MSD) + # get it from ChibiOS contribution + list(APPEND CHIBIOS_FATFS_SOURCES ${PROJECT_BINARY_DIR}/ChibiOS-Contrib_Source/os/various/fatfs_bindings/fatfs_diskio.c) +else() + # get it from standard ChibiOS + list(APPEND CHIBIOS_FATFS_SOURCES ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/various/fatfs_bindings/fatfs_diskio.c) +endif() + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(CHIBIOS_FATFS DEFAULT_MSG CHIBIOS_FATFS_INCLUDE_DIRS CHIBIOS_FATFS_SOURCES) + +# setup target to unzip ChibiOS external filesystem components +add_custom_target( CHIBIOS_FILESYSTEM_COMPONENTS ALL ) + +add_custom_command(TARGET CHIBIOS_FILESYSTEM_COMPONENTS +PRE_BUILD + COMMAND ${CMAKE_COMMAND} -E tar xvf ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/fatfs-0.13_patched.7z + WORKING_DIRECTORY ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/ + DEPENDS ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/fatfs-0.13_patched.7z + + VERBATIM +) + +# this depends on ChibiOS target being already downloaded +add_dependencies(CHIBIOS_FILESYSTEM_COMPONENTS ChibiOS) diff --git a/source/native/nf-interpreter/CMake/Modules/FindCHIBIOS_LWIP.cmake b/source/native/nf-interpreter/CMake/Modules/FindCHIBIOS_LWIP.cmake new file mode 100644 index 00000000..18c34782 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindCHIBIOS_LWIP.cmake @@ -0,0 +1,233 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# extract LwIP source files +execute_process( + COMMAND ${CMAKE_COMMAND} -E tar xvf ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/lwip-2.0.3-patched.7z + WORKING_DIRECTORY ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/ +) + +# List of the required lwIp include files. +list(APPEND CHIBIOS_LWIP_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/Lwip) +list(APPEND CHIBIOS_LWIP_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/various) +list(APPEND CHIBIOS_LWIP_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/various/lwip_bindings) +list(APPEND CHIBIOS_LWIP_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/lwip/src/include) +list(APPEND CHIBIOS_LWIP_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/lwip/src/include/lwip) +list(APPEND CHIBIOS_LWIP_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/lwip/src/include/netif) +list(APPEND CHIBIOS_LWIP_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/lwip/src/include/posix) +list(APPEND CHIBIOS_LWIP_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/DeviceInterfaces/Networking.Sntp) + +set(LWIP_SRCS + + # sys_arch.c + + # core + init.c + def.c + dns.c + inet_chksum.c + ip.c + mem.c + memp.c + netif.c + pbuf.c + raw.c + stats.c + sys.c + tcp.c + tcp_in.c + tcp_out.c + timeouts.c + udp.c + + # ipv4 + autoip.c + dhcp.c + etharp.c + icmp.c + igmp.c + ip4_frag.c + ip4.c + ip4_addr.c + + # ip6 + dhcp6.c + ethip6.c + icmp6.c + inet6.c + ip6.c + ip6_addr.c + ip6_frag.c + mld6.c + nd6.c + + # api + api_lib.c + # api_msg.c + err.c + netbuf.c + netdb.c + netifapi.c + # sockets.c + tcpip.c + + # api patched files for nanoframework + nf_api_msg.c + nf_sockets.c + nf_sys_arch.c + + # bindings + nf_lwipthread.c + + # platform implementations + platform_sys_arch.c + + #extras + evtimer.c + + # netif + ethernet.c + slipif.c + + # 6LoWPAN + # lowpan6.c + + # PPP + auth.c + ccp.c + chap-md5.c + chap_ms.c + chap-new.c + demand.c + eap.c + ecp.c + eui64.c + fsm.c + ipcp.c + ipv6cp.c + lcp.c + magic.c + mppe.c + multilink.c + ppp.c + pppapi.c + pppcrypt.c + pppoe.c + pppol2tp.c + pppos.c + upap.c + utils.c + vj.c + + # PPP SSL + arc4.c + des.c + md4.c + md5.c + sha1.c + + # APPS! + + # SNMPv2c agent + # snmp_asn1.c + # snmp_core.c + # snmp_mib2.c + # snmp_mib2_icmp.c + # snmp_mib2_interfaces.c + # snmp_mib2_ip.c + # snmp_mib2_snmp.c + # snmp_mib2_system.c + # snmp_mib2_tcp.c + # snmp_mib2_udp.c + # snmp_msg.c + # snmpv3.c + # snmp_netconn.c + # snmp_pbuf_stream.c + # snmp_raw.c + # snmp_scalar.c + # snmp_table.c + # snmp_threadsync.c + # snmp_traps.c + # snmpv3_mbedtls.c + # snmpv3_dummy.c + + # http server + # fs.c + # httpd.c + + # iperf server + # lwiperf.c + + # SNTP client + # this one is added below if NF_NETWORKING_SNTP option is ON + # sntp.c + + # MDNS responder + mdns.c + + # NetBIOS server + # netbiosns.c + + # TFTP server + # tftp_server.c + + # MQTT client + # mqtt.c +) + +if(NF_NETWORKING_SNTP) + list(APPEND LWIP_SRCS sntp.c) +endif() + +foreach(SRC_FILE ${LWIP_SRCS}) + set(LWIP_SRC_FILE SRC_FILE -NOTFOUND) + find_file(LWIP_SRC_FILE ${SRC_FILE} + PATHS + ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/various + ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/lwip/src/core + ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/lwip/src/core/ipv4 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/lwip/src/core/ipv6 + ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/lwip/src/api + ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/lwip/src/netif + ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/lwip/src/netif/ppp + ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/lwip/src/netif/ppp/polarssl + + ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/Lwip + ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/Lwip + + # APPS: + ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/lwip/src/apps/snmp + ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/lwip/src/apps/httpd + ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/lwip/src/apps/lwiperf + ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/lwip/src/apps/sntp + ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/lwip/src/apps/mdns + ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/lwip/src/apps/netbiosns + ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/lwip/src/apps/tftp + ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/lwip/src/apps/mqtt + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${LWIP_SRC_FILE}") # debug helper + list(APPEND CHIBIOS_LWIP_SOURCES ${LWIP_SRC_FILE}) +endforeach() + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(CHIBIOS_LWIP DEFAULT_MSG CHIBIOS_LWIP_INCLUDE_DIRS CHIBIOS_LWIP_SOURCES) + +# setup target to unzip ChibiOS external network components +add_custom_target( CHIBIOS_NETWORK_COMPONENTS ALL ) + +add_custom_command(TARGET CHIBIOS_NETWORK_COMPONENTS +PRE_BUILD + COMMAND ${CMAKE_COMMAND} -E tar xvf ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/lwip-2.0.3-patched.7z + WORKING_DIRECTORY ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/ + DEPENDS ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/lwip-2.0.3-patched.7z + + VERBATIM +) + +# this depends on ChibiOS target being already downloaded +add_dependencies(CHIBIOS_NETWORK_COMPONENTS ChibiOS) diff --git a/source/native/nf-interpreter/CMake/Modules/FindChibiOS-Contrib.cmake b/source/native/nf-interpreter/CMake/Modules/FindChibiOS-Contrib.cmake new file mode 100644 index 00000000..69c5d9ac --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindChibiOS-Contrib.cmake @@ -0,0 +1,46 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# set include directories for ChibiOS-Contrib + +# the path is one folder UP from the includes directory to allow a selective inclusion of our own hal_community.h +list(APPEND CHIBIOS_CONTRIB_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS-Contrib_Source/os/hal/include) + +#################################################################################### +# WHEN ADDING A NEW ChibiOS-Contrib component add the include directory(ies) below +#################################################################################### +# component IMACOMPONENT +#list(APPEND CHIBIOS_CONTRIB_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS-Contrib_Source/os/hal/include/IMACOMPONENT) + +# USB Host v1 +list(APPEND CHIBIOS_CONTRIB_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS-Contrib_Source/os/hal/ports/STM32/LLD/USBHv1) + + +#################################################################################################################################### +# Because we've "hacked" ChibiOS overlay mechanism used by the community contributions we can't add the "official" hal_community.c # +# Instead we have to add the required and equivalent calls that exist in the official source file # +# in our hal_community.c @ targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/hal_community.c # +# the include paths are to be added to our hal_community.h @ targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/hal_community.h # +#################################################################################################################################### + + +#################################################################################################### +# WHEN ADDING A NEW ChibiOS-Contrib component add the source file(s) specific to it below +#################################################################################################### +# component IMACOMPONENT +# list(APPEND CHIBIOS_CONTRIB_SOURCES ${PROJECT_BINARY_DIR}/ChibiOS-Contrib_Source/os/hal/src/IMACOMPONENT/source-file-1.c) +# list(APPEND CHIBIOS_CONTRIB_SOURCES ${PROJECT_BINARY_DIR}/ChibiOS-Contrib_Source/os/hal/src/IMACOMPONENT/source-file-2.c) +# list(APPEND CHIBIOS_CONTRIB_SOURCES ${PROJECT_BINARY_DIR}/ChibiOS-Contrib_Source/os/hal/src/IMACOMPONENT/source-file-3.c) + +# USB Host v1 +list(APPEND CHIBIOS_CONTRIB_SOURCES ${PROJECT_BINARY_DIR}/ChibiOS-Contrib_Source/os/hal/src/hal_usbh.c) +list(APPEND CHIBIOS_CONTRIB_SOURCES ${PROJECT_BINARY_DIR}/ChibiOS-Contrib_Source/os/hal/src/usbh/hal_usbh_msd.c) +list(APPEND CHIBIOS_CONTRIB_SOURCES ${PROJECT_BINARY_DIR}/ChibiOS-Contrib_Source/os/hal/src/usbh/hal_usbh_desciter.c) +list(APPEND CHIBIOS_CONTRIB_SOURCES ${PROJECT_BINARY_DIR}/ChibiOS-Contrib_Source/os/hal/src/usbh/hal_usbh_hub.c) +list(APPEND CHIBIOS_CONTRIB_SOURCES ${PROJECT_BINARY_DIR}/ChibiOS-Contrib_Source/os/hal/src/hal_usb_msd.c) +list(APPEND CHIBIOS_CONTRIB_SOURCES ${PROJECT_BINARY_DIR}/ChibiOS-Contrib_Source/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c) + +include(FindPackageHandleStandardArgs) +FIND_PACKAGE_HANDLE_STANDARD_ARGS(CHIBIOS_CONTRIB DEFAULT_MSG CHIBIOS_CONTRIB_INCLUDE_DIRS CHIBIOS_CONTRIB_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindChibiOSnfOverlay.cmake b/source/native/nf-interpreter/CMake/Modules/FindChibiOSnfOverlay.cmake new file mode 100644 index 00000000..82aabec2 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindChibiOSnfOverlay.cmake @@ -0,0 +1,69 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# set include directories for ChibiOS nanoFramework Overlay +list(APPEND ChibiOSnfOverlay_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include) + +#################################################################################### +# WHEN ADDING A NEW CHIBIOS OVERLAY component add the include directory(ies) below +#################################################################################### +# component STM32_FLASH +list(APPEND ChibiOSnfOverlay_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_flash) +# component STM32_CRC +list(APPEND ChibiOSnfOverlay_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_crc) +# component STM32_RNG +list(APPEND ChibiOSnfOverlay_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_rng) +# component STM32_FSMC (Flexible Memory Controller) +list(APPEND ChibiOSnfOverlay_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_fsmc) +# component STM32_ONEWIRE (One Wire driver) +list(APPEND ChibiOSnfOverlay_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_onewire) +# component STM32_QSPI (QSPI driver) +list(APPEND ChibiOSnfOverlay_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_qspi) + +################################################################################################################################## +# Add above the required include directory(ies) for a new nanoFramework overlay component that you are adding +# following the template below. +# +# If the component includes a low level driver specific to a series, make sure you add the include dirs +# in the CHIBIOS_NNNNNN_sources.cmake +# +# list(APPEND ChibiOSnfOverlay_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/) +################################################################################################################################## + + +################################################## +# source files for ChibiOS nanoFramework Overlay +################################################## +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/hal_community.c) + +#################################################################################################### +# WHEN ADDING A NEW CHIBIOS OVERLAY component add the source file(s) specific to this series below +#################################################################################################### +# component STM32_FLASH +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_flash/hal_stm32_flash.c) +# component STM32_CRC +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_crc/hal_stm32_crc.c) +# component STM32_RNG +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_rng/hal_stm32_rng.c) +# component STM32_FSMC (Flexible Memory Controller) +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_fsmc/hal_stm32_fsmc.c) +# component STM32_ONEWIRE (One Wire driver) +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_onewire/hal_stm32_onewire.c) +# component STM32_QSPI (QSPI driver) +list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_qspi/hal_stm32_qspi.c) + +######################################################################################################################### +# Add above ALL the source code file(s) required for a new nanoFramework overlay component that you are adding +# following the template below. +# +# If the component includes a low level driver specific to a series, make sure you add the source files +# in the CHIBIOS_NNNNNN_sources.cmake +# +# list(APPEND ChibiOSnfOverlay_SOURCES ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/) +######################################################################################################################### + + +include(FindPackageHandleStandardArgs) +FIND_PACKAGE_HANDLE_STANDARD_ARGS(ChibiOSnfOverlay DEFAULT_MSG ChibiOSnfOverlay_INCLUDE_DIRS ChibiOSnfOverlay_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindMBEDOS.cmake b/source/native/nf-interpreter/CMake/Modules/FindMBEDOS.cmake new file mode 100644 index 00000000..65518a6b --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindMBEDOS.cmake @@ -0,0 +1,389 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +include(JSONParser) + +# read mBed targets file +file(READ "${PROJECT_BINARY_DIR}/mBedOS_Source/targets/targets.json" TARGETS_JSON) + +# try to find target +string(FIND ${TARGETS_JSON} ${MBED_TARGET} FOUND_TARGET) + +# message(STATUS "${MBED_TARGET} @ ${FOUND_TARGET}") + +if(${FOUND_TARGET} GREATER -1) + # target found + + message(STATUS "mBed target '${MBED_TARGET}' found") + # get substring with data + math(EXPR FOUND_TARGET "${FOUND_TARGET} - 1") + + # because there is not an elegant way of finding the end of the json section of this target we are setting this to 1000 chars + # the downside is that for most target this overuns to the next target + string(SUBSTRING "${TARGETS_JSON}" ${FOUND_TARGET} 2000 TARGET_TENTATIVE_JSON) +else() + message(FATAL_ERROR "\n\nSorry but ${MBED_TARGET} seems to be missing in the list of the mBed supported targets...\n\n") +endif() + +# parse target data +sbeParseJson(MBED_TARGET_DATA TARGET_TENTATIVE_JSON) + +# try to extract relevant data +foreach(var ${MBED_TARGET_DATA}) + + # sanity check when json parse has overun to the next target + string(FIND ${var} "MBED_TARGET_DATA.${MBED_TARGET}" MBED_TARGET_NAME_FOUND) + if(MBED_TARGET_NAME_FOUND GREATER -1) + + # seems to belong to target, extract data + #message("${var} : ${${var}}") # debug helper + + # core + string(FIND ${var} "core" MBED_TARGET_CORE_INDEX) + if(${MBED_TARGET_CORE_INDEX} GREATER -1) + set(MBED_TARGET_CORE ${${var}}) + endif() + + # extra labels 0 is: target vendor + string(FIND ${var} "MBED_TARGET_DATA.${MBED_TARGET}.extra_labels_0" MBED_TARGET_VENDOR_INDEX) + if(${MBED_TARGET_VENDOR_INDEX} GREATER -1) + set(MBED_TARGET_VENDOR ${${var}}) + endif() + + # extra labels 1 is: target series/variant + string(FIND ${var} "MBED_TARGET_DATA.${MBED_TARGET}.extra_labels_1" MBED_TARGET_SERIES_INDEX) + if(${MBED_TARGET_SERIES_INDEX} GREATER -1) + set(MBED_TARGET_SERIES ${${var}}) + endif() + + # extra labels 2 is used for compiler defs + string(FIND ${var} "MBED_TARGET_DATA.${MBED_TARGET}.extra_labels_2" MBED_TARGET_EXTRA_LABEL2_INDEX) + if(${MBED_TARGET_EXTRA_LABEL2_INDEX} GREATER -1) + set(MBED_TARGET_EXTRA_LABEL2 ${${var}}) + endif() + + # 'macros' lists target aditional macros + string(FIND ${var} "MBED_TARGET_DATA.${MBED_TARGET}.macros_" MBED_TARGET_MACROS_INDEX) + if(${MBED_TARGET_MACROS_INDEX} GREATER -1) + list(APPEND MBED_TARGET_MACROS ${${var}}) + endif() + + # 'device has' lists target features + string(FIND ${var} "MBED_TARGET_DATA.${MBED_TARGET}.device_has_" MBED_TARGET_DEVICE_HAS_INDEX) + if(${MBED_TARGET_DEVICE_HAS_INDEX} GREATER -1) + list(APPEND MBED_TARGET_FEATURES ${${var}}) + endif() + + # 'supported form factors' lists supported form factors for board + string(FIND ${var} "MBED_TARGET_DATA.${MBED_TARGET}.supported_form_factors_" MBED_TARGET_DEVICE_FORM_FACTORS_INDEX) + if(${MBED_TARGET_DEVICE_FORM_FACTORS_INDEX} GREATER -1) + list(APPEND MBED_TARGET_DEVICE_FORM_FACTORS ${${var}}) + endif() + + endif() + +endforeach() + +message("mBed target has ${MBED_TARGET_CORE}") +message("mBed target vendor is ${MBED_TARGET_VENDOR}") +message("mBed target series is ${MBED_TARGET_SERIES}") +#message("mBed target features: ${MBED_TARGET_FEATURES}") + +# get target core short name +string(REPLACE "Cortex-" "" MBED_TARGET_CORE_SHORT ${MBED_TARGET_CORE} ) + +# set compiler options (general) +string(APPEND MBEDOS_COMPILE_OPTIONS "-D__CORTEX_${MBED_TARGET_CORE_SHORT} -D__MBED__=1 -DTARGET_LIKE_MBED -D__MBED_CMSIS_RTOS_CM -DTOOLCHAIN_object -D__CMSIS_RTOS -DTOOLCHAIN_GCC -DTARGET_CORTEX_M -DARM_MATH_C${MBED_TARGET_CORE_SHORT} -DTARGET_${MBED_TARGET_CORE_SHORT} -DTOOLCHAIN_GCC_ARM -DTARGET_RELEASE -DTARGET_LIKE_CORTEX_${MBED_TARGET_CORE_SHORT} -D__CORTEX_${MBED_TARGET_CORE_SHORT} -DTARGET_${MBED_TARGET_VENDOR} -DTARGET_${MBED_TARGET_SERIES} -DTARGET_UVISOR_UNSUPPORTED -DTARGET_${MBED_TARGET}") + +# extra compiler def from extra label 2 +if(MBED_TARGET_EXTRA_LABEL2) + string(APPEND MBEDOS_COMPILE_OPTIONS " -DTARGET_${MBED_TARGET_EXTRA_LABEL2}") +endif() + +# set compiler options (target specific features) +foreach(feature ${MBED_TARGET_FEATURES}) + string(APPEND MBEDOS_COMPILE_OPTIONS " -DDEVICE_${feature}=1") +endforeach() + +# set compiler options (form factors) +foreach(ff ${MBED_TARGET_DEVICE_FORM_FACTORS}) + string(APPEND MBEDOS_COMPILE_OPTIONS " -DTARGET_FF_${ff}") +endforeach() + +# set compiler options (macros) +foreach(macro ${MBED_TARGET_MACROS}) + string(APPEND MBEDOS_COMPILE_OPTIONS " -D${macro}") +endforeach() + +#message(">>MBEDOS_COMPILE_OPTIONS: ${MBEDOS_COMPILE_OPTIONS}<<") # debug helper + +# set include directories for mBed RTOS +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/cmsis) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/cmsis/TOOLCHAIN_GCC) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/docs) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/drivers) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/events) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/events/equeue) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/features) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/features/frameworks) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/features/frameworks/greentea-client) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/features/frameworks/greentea-client/greentea-client) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/features/frameworks/greentea-client/source) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/features/frameworks/unity) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/features/frameworks/unity/source) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/features/frameworks/unity/unity) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/features/frameworks/utest) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/features/frameworks/utest/source) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/features/frameworks/utest/utest) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/features/mbedtls) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/features/mbedtls/importer) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/features/mbedtls/inc) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/features/mbedtls/inc/mbedtls) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/features/mbedtls/platform) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/features/mbedtls/platform/inc) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/features/mbedtls/platform/src) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/features/mbedtls/src) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/features/nanostack) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/features/netsocket) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/features/storage) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/hal) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/hal/storage_abstraction) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/platform) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/rtos) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/rtos/rtx) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/rtos/rtx/TARGET_CORTEX_M) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/rtos/rtx/TARGET_CORTEX_M/TARGET_${MBED_TARGET_CORE_SHORT}) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/rtos/rtx/TARGET_CORTEX_M/TARGET_${MBED_TARGET_CORE_SHORT}/TOOLCHAIN_GCC) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/targets) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/targets/TARGET_${MBED_TARGET_VENDOR}) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/targets/TARGET_${MBED_TARGET_VENDOR}/TARGET_${MBED_TARGET_SERIES}) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/targets/TARGET_${MBED_TARGET_VENDOR}/TARGET_${MBED_TARGET_SERIES}/device) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/targets/TARGET_${MBED_TARGET_VENDOR}/TARGET_${MBED_TARGET_SERIES}/TARGET_${MBED_TARGET}) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/targets/TARGET_${MBED_TARGET_VENDOR}/TARGET_${MBED_TARGET_SERIES}/TARGET_${MBED_TARGET}/device) +list(APPEND MBEDOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mBedOS_Source/targets/TARGET_${MBED_TARGET_VENDOR}/TARGET_${MBED_TARGET_SERIES}/TARGET_${MBED_TARGET}/device/TOOLCHAIN_GCC_ARM) + +# source files and GCC options according to target vendor and series +if("${MBED_TARGET_VENDOR}" STREQUAL "STM") + include(MBED_${MBED_TARGET_SERIES}_sources) + include(MBED_${MBED_TARGET_SERIES}_GCC_options) +endif() + +# source files for RTOS +set(MBEDRTOS_SRCS + # drivers + AnalogIn.cpp + BusIn.cpp + BusInOut.cpp + BusOut.cpp + CAN.cpp + Ethernet.cpp + FileBase.cpp + FileLike.cpp + FilePath.cpp + FileSystemLike.cpp + I2C.cpp + I2CSlave.cpp + InterruptIn.cpp + InterruptManager.cpp + LocalFileSystem.cpp + RawSerial.cpp + SPI.cpp + SPISlave.cpp + Serial.cpp + SerialBase.cpp + Stream.cpp + Ticker.cpp + Timeout.cpp + Timer.cpp + TimerEvent.cpp + + # events + EventQueue.cpp + equeue.c + equeue_mbed.cpp + equeue_posix.c + + # features + greentea_metrics.cpp + greentea_serial.cpp + test_env.cpp + unity.c + mbed-utest-shim.cpp + unity_handler.cpp + utest_case.cpp + utest_default_handlers.cpp + utest_greentea_handlers.cpp + utest_harness.cpp + utest_shim.cpp + utest_stack_trace.cpp + utest_types.cpp + + # mbed tls + mbed_trng.c + aes.c + aesni.c + arc4.c + asn1parse.c + asn1write.c + base64.c + bignum.c + blowfish.c + camellia.c + ccm.c + certs.c + cipher.c + cipher_wrap.c + cmac.c + ctr_drbg.c + debug.c + des.c + dhm.c + ecdh.c + ecdsa.c + ecjpake.c + ecp.c + ecp_curves.c + entropy.c + entropy_poll.c + error.c + gcm.c + havege.c + hmac_drbg.c + md.c + md2.c + md4.c + md5.c + md_wrap.c + memory_buffer_alloc.c + net_sockets.c + oid.c + padlock.c + pem.c + pk.c + pk_wrap.c + pkcs11.c + pkcs12.c + pkcs5.c + pkparse.c + pkwrite.c + platform.c + ripemd160.c + rsa.c + sha1.c + sha256.c + sha512.c + ssl_cache.c + ssl_ciphersuites.c + ssl_cli.c + ssl_cookie.c + ssl_srv.c + ssl_ticket.c + ssl_tls.c + threading.c + timing.c + version.c + version_features.c + x509.c + x509_create.c + x509_crl.c + x509_crt.c + x509_csr.c + x509write_crt.c + x509write_csr.c + xtea.c + + # net socket + NetworkInterface.cpp + NetworkStack.cpp + Socket.cpp + SocketAddress.cpp + TCPServer.cpp + TCPSocket.cpp + UDPSocket.cpp + WiFiAccessPoint.cpp + nsapi_dns.cpp + + # mBed HAL + mbed_gpio.c + mbed_lp_ticker_api.c + mbed_pinmap_common.c + mbed_ticker_api.c + mbed_us_ticker_api.c + + # mBed platfom + CallChain.cpp + mbed_alloc_wrappers.cpp + mbed_assert.c + mbed_board.c + mbed_critical.c + mbed_error.c + mbed_interface.c + mbed_mem_trace.c + mbed_rtc_time.cpp + mbed_semihost_api.c + mbed_stats.c + mbed_wait_api_no_rtos.c + mbed_wait_api_rtos.cpp + retarget.cpp + + # RTOS + Mutex.cpp + RtosTimer.cpp + Semaphore.cpp + Thread.cpp + rtos_idle.c + HAL_CM.c + RTX_Conf_CM.c + rt_CMSIS.c + rt_Event.c + rt_List.c + rt_Mailbox.c + rt_MemBox.c + rt_Memory.c + rt_Mutex.c + rt_OsEventObserver.c + rt_Robin.c + rt_Semaphore.c + rt_System.c + rt_Task.c + rt_Time.c + rt_Timer.c +) + +foreach(SRC_FILE ${MBEDRTOS_SRCS}) + set(MBEDOS_SRC_FILE SRC_FILE-NOTFOUND) + find_file(MBEDOS_SRC_FILE ${SRC_FILE} + PATHS + ${PROJECT_BINARY_DIR}/mBedOS_Source/drivers + ${PROJECT_BINARY_DIR}/mBedOS_Source/events + ${PROJECT_BINARY_DIR}/mBedOS_Source/events/equeue + ${PROJECT_BINARY_DIR}/mBedOS_Source/features/frameworks/greentea-client/source + ${PROJECT_BINARY_DIR}/mBedOS_Source/features/frameworks/unity/source + ${PROJECT_BINARY_DIR}/mBedOS_Source/features/frameworks/utest + ${PROJECT_BINARY_DIR}/mBedOS_Source/features/frameworks/utest/source + + ${PROJECT_BINARY_DIR}/mBedOS_Source/features/mbedtls/platform/src + ${PROJECT_BINARY_DIR}/mBedOS_Source/features/mbedtls/src + ${PROJECT_BINARY_DIR}/mBedOS_Source/features/netsocket + + ${PROJECT_BINARY_DIR}/mBedOS_Source/hal + + ${PROJECT_BINARY_DIR}/mBedOS_Source/platform + + ${PROJECT_BINARY_DIR}/mBedOS_Source/rtos + ${PROJECT_BINARY_DIR}/mBedOS_Source/rtos/rtx + ${PROJECT_BINARY_DIR}/mBedOS_Source/rtos/rtx/TARGET_CORTEX_M + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${MBEDOS_SRC_FILE}") # debug helper + list(APPEND MBEDOS_SOURCES ${MBEDOS_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(MBEDOS DEFAULT_MSG MBEDOS_INCLUDE_DIRS MBEDOS_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindNF_CoreCLR.cmake b/source/native/nf-interpreter/CMake/Modules/FindNF_CoreCLR.cmake new file mode 100644 index 00000000..76cae905 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindNF_CoreCLR.cmake @@ -0,0 +1,256 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# set include directories for nanoFramework Core, CoreLib and CLR startup + +# include directories for Core +list(APPEND NF_CoreCLR_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Core) +list(APPEND NF_CoreCLR_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Include) +list(APPEND NF_CoreCLR_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/HAL/Include) +list(APPEND NF_CoreCLR_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/PAL/Include) + +# include directories for CoreLib +list(APPEND NF_CoreCLR_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/CorLib) + +# CLR startup +list(APPEND NF_CoreCLR_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Startup) + +# others +list(APPEND NF_CoreCLR_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Diagnostics) +list(APPEND NF_CoreCLR_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Debugger) +list(APPEND NF_CoreCLR_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Helpers/TinyPrintf) +list(APPEND NF_CoreCLR_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Helpers/Base64) +list(APPEND NF_CoreCLR_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/nanoFramework.Runtime.Native) + +# source files for nanoFramework Core, CoreLib and CLR startup +set(NF_CoreCLR_SRCS + + # Core + Cache.cpp + Checks.cpp + CLR_RT_DblLinkedList.cpp + CLR_RT_HeapBlock.cpp + CLR_RT_HeapBlock_Array.cpp + CLR_RT_HeapBlock_ArrayList.cpp + CLR_RT_HeapBlock_BinaryBlob.cpp + CLR_RT_HeapBlock_Delegate.cpp + CLR_RT_HeapBlock_Delegate_List.cpp + CLR_RT_HeapBlock_Finalizer.cpp + CLR_RT_HeapBlock_Lock.cpp + CLR_RT_HeapBlock_LockRequest.cpp + CLR_RT_HeapBlock_Node.cpp + CLR_RT_HeapBlock_String.cpp + CLR_RT_HeapBlock_Timer.cpp + CLR_RT_HeapBlock_WaitForObject.cpp + CLR_RT_HeapCluster.cpp + CLR_RT_Interop.cpp + CLR_RT_Memory.cpp + CLR_RT_ObjectToEvent_Destination.cpp + CLR_RT_ObjectToEvent_Source.cpp + CLR_RT_RuntimeMemory.cpp + CLR_RT_StackFrame.cpp + CLR_RT_SystemAssembliesTable.cpp + CLR_RT_UnicodeHelper.cpp + Core.cpp + Execution.cpp + GarbageCollector.cpp + GarbageCollector_Compaction.cpp + GarbageCollector_ComputeReachabilityGraph.cpp + GarbageCollector_Info.cpp + Interpreter.cpp + Random.cpp + Streams.cpp + StringTable.cpp + Thread.cpp + TypeSystemLookup.cpp + StringTableData.cpp + TypeSystem.cpp + nanoSupport_CRC32.c + nanoHAL_SystemInformation.cpp + # Various.cpp + + # CoreLib + corlib_native_System_AppDomain.cpp + corlib_native_System_Array.cpp + corlib_native_System_Attribute.cpp + corlib_native_System_BitConverter.cpp + corlib_native_System_Collections_ArrayList.cpp + corlib_native_System_Console.cpp + corlib_native_System_Convert.cpp + corlib_native_System_DateTime.cpp + corlib_native_System_Delegate.cpp + corlib_native_System_Diagnostics_Debugger.cpp + corlib_native_System_Double.cpp + corlib_native_System_Enum.cpp + corlib_native_System_Exception.cpp + corlib_native_System_GC.cpp + corlib_native_System_Globalization_CultureInfo.cpp + corlib_native_System_Globalization_DateTimeFormat.cpp + corlib_native_System_Guid.cpp + corlib_native_System_MarshalByRefObject.cpp + corlib_native_System_MathInternal.cpp + corlib_native_System_MulticastDelegate.cpp + corlib_native_System_Number.cpp + corlib_native_System_Object.cpp + corlib_native_System_Random.cpp + corlib_native_System_Reflection_Binder.cpp + corlib_native_System_Reflection_MemberInfo.cpp + corlib_native_System_Runtime_CompilerServices_RuntimeHelpers.cpp + corlib_native_System_Runtime_Remoting_RemotingServices.cpp + corlib_native_System_String.cpp + corlib_native_System_Text_UTF8Decoder.cpp + corlib_native_System_Text_UTF8Encoding.cpp + corlib_native_System_Threading_AutoResetEvent.cpp + corlib_native_System_Threading_Interlocked.cpp + corlib_native_System_Threading_ManualResetEvent.cpp + corlib_native_System_Threading_Monitor.cpp + corlib_native_System_Threading_Thread.cpp + corlib_native_System_Threading_Timer.cpp + corlib_native_System_Threading_WaitHandle.cpp + corlib_native_System_TimeSpan.cpp + corlib_native_System_ValueType.cpp + corlib_native_System_WeakReference.cpp + corlib_native.cpp + + # CLR startup + CLRStartup.cpp + + # Messaging + Messaging.cpp + + # Runtime.Native + nf_rt_native.cpp + nf_rt_native_nanoFramework_Runtime_Hardware_SystemInfo.cpp + nf_rt_native_nanoFramework_Runtime_Native_Debug.cpp + nf_rt_native_nanoFramework_Runtime_Native_ExecutionConstraint.cpp + nf_rt_native_nanoFramework_Runtime_Native_Power.cpp + nf_rt_native_nanoFramework_Runtime_Native_Rtc_stubs.cpp + + # Core stubs + Hardware_stub.cpp + InterruptHandler_stub.cpp + NativeEventDispatcher_stub.cpp + RPC_stub.cpp + BinaryFormatter_stub.cpp + + # CLR stubs + Debugger_stub.cpp + Diagnostics_stub.cpp + Messaging_stub.cpp + + # Helpers + printf.c + + # HAL + nanoHAL_Time.cpp + nanoHAL_Watchdog.c + + # PAL + nanoPAL_BlockStorage.c + nanoPAL_NativeDouble.cpp + nanoPAL_Network_stubs.cpp + nanoPAL_PerformanceCounters_stubs.cpp + + # PAL stubs + Async_stubs.cpp + COM_stubs.c + GenericPort_stubs.c + + # target specifics + target_BlockStorage.c +) + +# include System.Reflection API files depending on build option +if(NF_FEATURE_SUPPORT_REFLECTION) + list(APPEND NF_CoreCLR_SRCS corlib_native_System_Reflection_Assembly.cpp) + list(APPEND NF_CoreCLR_SRCS corlib_native_System_Reflection_ConstructorInfo.cpp) + list(APPEND NF_CoreCLR_SRCS corlib_native_System_Reflection_FieldInfo.cpp) + list(APPEND NF_CoreCLR_SRCS corlib_native_System_Reflection_MethodBase.cpp) + list(APPEND NF_CoreCLR_SRCS corlib_native_System_Reflection_PropertyInfo.cpp) + list(APPEND NF_CoreCLR_SRCS corlib_native_System_Reflection_RuntimeFieldInfo.cpp) + list(APPEND NF_CoreCLR_SRCS corlib_native_System_Reflection_RuntimeMethodInfo.cpp) + list(APPEND NF_CoreCLR_SRCS corlib_native_System_RuntimeType.cpp) + list(APPEND NF_CoreCLR_SRCS corlib_native_System_Type.cpp) +endif() + +# include Collection support files depending on build option +if(API_nanoFramework.System.Collections) + list(APPEND NF_CoreCLR_SRCS CLR_RT_HeapBlock_Queue.cpp) + list(APPEND NF_CoreCLR_SRCS CLR_RT_HeapBlock_Stack.cpp) +endif() + +# need a conditional include because of ESP32 building network as a library +if(NOT USE_SECURITY_MBEDTLS_OPTION) + list(APPEND NF_CoreCLR_SRCS base64.c) +endif() + +# include configuration manager file +if(NF_FEATURE_HAS_CONFIG_BLOCK) + # feature enabled, full support + list(APPEND NF_CoreCLR_SRCS nanoHAL_ConfigurationManager.c) +else() + # feature disabled, stubs only + list(APPEND NF_CoreCLR_SRCS nanoHAL_ConfigurationManager_stubs.c) +endif() + +foreach(SRC_FILE ${NF_CoreCLR_SRCS}) + set(NF_CoreCLR_SRC_FILE SRC_FILE-NOTFOUND) + find_file(NF_CoreCLR_SRC_FILE ${SRC_FILE} + PATHS + + # Core + ${PROJECT_SOURCE_DIR}/src/CLR/Core + + # CoreLib + ${PROJECT_SOURCE_DIR}/src/CLR/CorLib + + # CLR startup + ${PROJECT_SOURCE_DIR}/src/CLR/Startup + + # Runtime.Native + ${PROJECT_SOURCE_DIR}/src/nanoFramework.Runtime.Native + + # Core stubs + ${PROJECT_SOURCE_DIR}/src/CLR/Core/Hardware + ${PROJECT_SOURCE_DIR}/src/CLR/Core/InterruptHandler + ${PROJECT_SOURCE_DIR}/src/CLR/Core/NativeEventDispatcher + ${PROJECT_SOURCE_DIR}/src/CLR/Core/RPC + ${PROJECT_SOURCE_DIR}/src/CLR/Core/Serialization + + # CLR stubs + ${PROJECT_SOURCE_DIR}/src/CLR/Debugger + ${PROJECT_SOURCE_DIR}/src/CLR/Diagnostics + ${PROJECT_SOURCE_DIR}/src/CLR/Messaging + + # Helpers + ${PROJECT_SOURCE_DIR}/src/CLR/Helpers/TinyPrintf + ${PROJECT_SOURCE_DIR}/src/CLR/Helpers/Base64 + + # HAL + ${PROJECT_SOURCE_DIR}/src/HAL + + # PAL + ${PROJECT_SOURCE_DIR}/src/PAL + ${PROJECT_SOURCE_DIR}/src/PAL/BlockStorage + ${PROJECT_SOURCE_DIR}/src/PAL/Double + + # PAL stubs + ${PROJECT_SOURCE_DIR}/src/PAL/AsyncProcCall + ${PROJECT_SOURCE_DIR}/src/PAL/COM + ${PROJECT_SOURCE_DIR}/src/PAL/Profiler + + # target + "${TARGET_BASE_LOCATION}" + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${NF_CoreCLR_SRC_FILE}") # debug helper + list(APPEND NF_CoreCLR_SOURCES ${NF_CoreCLR_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(NF_CoreCLR DEFAULT_MSG NF_CoreCLR_INCLUDE_DIRS NF_CoreCLR_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindNF_Debugger.cmake b/source/native/nf-interpreter/CMake/Modules/FindNF_Debugger.cmake new file mode 100644 index 00000000..84655de4 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindNF_Debugger.cmake @@ -0,0 +1,53 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# set include directories for nanoFramework Debugger +list(APPEND NF_Debugger_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Debugger) +list(APPEND NF_Debugger_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Messaging) +list(APPEND NF_Debugger_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/WireProtocol) +list(APPEND NF_Debugger_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Include) + +# source files for nanoFramework Debugger +set(NF_Debugger_SRCS + + Debugger.cpp + + Messaging.cpp + + WireProtocol_Message.c + WireProtocol_MonitorCommands.c + WireProtocol_HAL_Interface.c + WireProtocol_App_Interface.c + + nanoSupport_CRC32.c +) + +# add the debugger source file according to the build flavor +if(NF_BUILD_RTM) + set(NF_Debugger_SRCS ${NF_Debugger_SRCS} Debugger_minimal.cpp) +else() + set(NF_Debugger_SRCS ${NF_Debugger_SRCS} Debugger_full.cpp) +endif() + + +foreach(SRC_FILE ${NF_Debugger_SRCS}) + set(NF_Debugger_SRC_FILE SRC_FILE-NOTFOUND) + find_file(NF_Debugger_SRC_FILE ${SRC_FILE} + PATHS + ${PROJECT_SOURCE_DIR}/src/CLR/Debugger + ${PROJECT_SOURCE_DIR}/src/CLR/Messaging + ${PROJECT_SOURCE_DIR}/src/CLR/WireProtocol + ${PROJECT_SOURCE_DIR}/src/CLR/Core + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${NF_Debugger_SRC_FILE}") # debug helper + list(APPEND NF_Debugger_SOURCES ${NF_Debugger_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(NF_Debugger DEFAULT_MSG NF_Debugger_INCLUDE_DIRS NF_Debugger_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindNF_Diagnostics.cmake b/source/native/nf-interpreter/CMake/Modules/FindNF_Diagnostics.cmake new file mode 100644 index 00000000..a5b68c76 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindNF_Diagnostics.cmake @@ -0,0 +1,33 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# set include directories +list(APPEND NF_Diagnostics_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Diagnostics) +list(APPEND NF_Diagnostics_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Include) + +# source files +set(NF_Diagnostics_SRCS + + Info.cpp + Profile.cpp + Profiler.cpp +) + +foreach(SRC_FILE ${NF_Diagnostics_SRCS}) + set(NF_Diagnostics_SRC_FILE SRC_FILE-NOTFOUND) + find_file(NF_Diagnostics_SRC_FILE ${SRC_FILE} + PATHS + ${PROJECT_SOURCE_DIR}/src/CLR/Diagnostics + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${NF_Diagnostics_SRC_FILE}") # debug helper + list(APPEND NF_Diagnostics_SOURCES ${NF_Diagnostics_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(NF_Diagnostics DEFAULT_MSG NF_Diagnostics_INCLUDE_DIRS NF_Diagnostics_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindNF_Networking.cmake b/source/native/nf-interpreter/CMake/Modules/FindNF_Networking.cmake new file mode 100644 index 00000000..281b6aa8 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindNF_Networking.cmake @@ -0,0 +1,107 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# set include directories for nanoFramework network +list(APPEND NF_Networking_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/PAL/Com/sockets) +list(APPEND NF_Networking_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/PAL/Com/sockets/ssl) +list(APPEND NF_Networking_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/PAL/Lwip) +list(APPEND NF_Networking_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/DeviceInterfaces/Networking.Sntp) + +if(USE_SECURITY_MBEDTLS_OPTION) + list(APPEND NF_Networking_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/PAL/Com/sockets/ssl/mbedTLS) +endif() + +# source files for nanoFramework Networking +set(NF_Networking_SRCS + + #pal Socket + sockets_lwip.cpp + + #Lwip + LwIP_Sockets.cpp + LwIP_Sockets_functions.cpp + +) + +# need a conditional include because of ESP32 building network as a library +if(NOT USE_SECURITY_MBEDTLS_OPTION) + list(APPEND NF_Networking_SRCS ssl_stubs.cpp) +endif() + +# source files for security layer +set(NF_Networking_Security_SRCS + + ssl.cpp + ssl_accept_internal.cpp + ssl_add_cert_auth_internal.cpp + ssl_close_socket_internal.cpp + ssl_connect_internal.cpp + ssl_decode_private_key_internal.cpp + ssl_exit_context_internal.cpp + ssl_generic.cpp + ssl_generic_init_internal.cpp + ssl_initialize_internal.cpp + ssl_parse_certificate_internal.cpp + ssl_pending_internal.cpp + ssl_read_internal.cpp + ssl_uninitialize_internal.cpp + ssl_write_internal.cpp + +) + + +if(NF_FEATURE_DEBUGGER) + list(APPEND NF_Networking_SRCS sockets_debugger.cpp) +endif() + +# add source files in two steps +# 1st pass: common source files +foreach(SRC_FILE ${NF_Networking_SRCS}) + set(NF_Networking_SRC_FILE SRC_FILE-NOTFOUND) + find_file(NF_Networking_SRC_FILE ${SRC_FILE} + PATHS + + ${PROJECT_SOURCE_DIR}/src/PAL/COM/sockets + ${PROJECT_SOURCE_DIR}/src/PAL/COM/sockets/ssl + + ${PROJECT_SOURCE_DIR}/src/PAL/COM/sockets/ssl/mbedTLS + + ${PROJECT_SOURCE_DIR}/src/PAL/Lwip + ${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES} + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${NF_Networking_SRC_FILE}") # debug helper + list(APPEND NF_Networking_SOURCES ${NF_Networking_SRC_FILE}) +endforeach() + +if(USE_SECURITY_MBEDTLS_OPTION) + set(NF_Security_Search_Path "${PROJECT_SOURCE_DIR}/src/PAL/COM/sockets/ssl/mbedTLS") +endif() + +if(USE_SECURITY_MBEDTLS_OPTION) + + # 2nd pass: security files if option is selected + foreach(SRC_FILE ${NF_Networking_Security_SRCS}) + set(NF_Networking_SRC_FILE SRC_FILE-NOTFOUND) + find_file(NF_Networking_SRC_FILE ${SRC_FILE} + PATHS + + ${PROJECT_SOURCE_DIR}/src/PAL/COM/sockets/ssl + ${NF_Security_Search_Path} + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${NF_Networking_SRC_FILE}") # debug helper + list(APPEND NF_Networking_SOURCES ${NF_Networking_SRC_FILE}) + endforeach() + +endif() + + +include(FindPackageHandleStandardArgs) + + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(NF_Networking DEFAULT_MSG NF_Networking_INCLUDE_DIRS NF_Networking_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindRTXRTOS.cmake b/source/native/nf-interpreter/CMake/Modules/FindRTXRTOS.cmake new file mode 100644 index 00000000..c36076bb --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindRTXRTOS.cmake @@ -0,0 +1,99 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +if(NOT STM32_CHIP_TYPE) + STM32_GET_CHIP_TYPE(${TARGET_CHIP} STM32_CHIP_TYPE) + if(NOT STM32_CHIP_TYPE) + message(FATAL_ERROR "Unknown chip: ${TARGET_CHIP}.") + endif() + message(STATUS "${TARGET_CHIP} is ${STM32_CHIP_TYPE} device") +endif() +string(TOLOWER ${STM32_CHIP_TYPE} STM32_CHIP_TYPE_LOWER) + + +# build path hints according to device series +if(STM32_SERIES STREQUAL "F0") + set(RTXRTOS_HAL_NAME HAL_CM0.S) + set(RTXRTOS_COMPILE_OPTIONS -D__CORTEX_M0) +elseif(STM32_SERIES STREQUAL "F1") + set(RTXRTOS_HAL_NAME HAL_CM0.S) + set(RTXRTOS_COMPILE_OPTIONS -D__CORTEX_M0) +elseif(STM32_SERIES STREQUAL "F2") + set(RTXRTOS_HAL_NAME HAL_CM0.S) + set(RTXRTOS_COMPILE_OPTIONS -D__CORTEX_M0) +elseif(STM32_SERIES STREQUAL "F3") + set(RTXRTOS_HAL_NAME HAL_CM3.S) + set(RTXRTOS_COMPILE_OPTIONS -D__CORTEX_M3) +elseif(STM32_SERIES STREQUAL "F4") + set(RTXRTOS_HAL_NAME HAL_CM4.S) + set(RTXRTOS_COMPILE_OPTIONS -D__CORTEX_M4) +elseif(STM32_SERIES STREQUAL "F7") + set(RTXRTOS_HAL_NAME HAL_CM4.S) + set(RTXRTOS_COMPILE_OPTIONS -D__CORTEX_M7) +elseif(STM32_SERIES STREQUAL "L0") + set(RTXRTOS_HAL_NAME HAL_CM0.S) + set(RTXRTOS_COMPILE_OPTIONS -D__CORTEX_M0) +elseif(STM32_SERIES STREQUAL "L1") + set(RTXRTOS_HAL_NAME HAL_CM0.S) + set(RTXRTOS_COMPILE_OPTIONS -D__CORTEX_M0) +elseif(STM32_SERIES STREQUAL "L4") + set(RTXRTOS_HAL_NAME HAL_CM4.S) + set(RTXRTOS_COMPILE_OPTIONS -D__CORTEX_M4) +endif() + +# set include directories for RXT RTOS +list(APPEND RTXRTOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/RTXRTOS_Source/CMSIS/RTOS/RTX/INC) +list(APPEND RTXRTOS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/RTXRTOS_Source/CMSIS/RTOS/RTX/SRC) + +set(RTXRTOS_SRCS + Mutex.cpp + RtosTimer.cpp + Semaphore.cpp + Thread.cpp + + HAL_CM.c + rt_CMSIS.c + rt_Event.c + rt_List.c + rt_Mailbox.c + rt_MemBox.c + rt_Memory.c + rt_Mutex.c + rt_Robin.c + rt_Semaphore.c + rt_System.c + rt_Task.c + rt_Time.c + rt_Timer.c +) + +foreach(SRC_FILE ${RTXRTOS_SRCS}) + set(RTXRTOS_SRC_FILE SRC_FILE-NOTFOUND) + find_file(RTXRTOS_SRC_FILE ${SRC_FILE} + PATHS ${PROJECT_BINARY_DIR}/RTXRTOS_Source/CMSIS/RTOS/RTX/SRC ${PROJECT_BINARY_DIR}/RTXRTOS_Source/CMSIS/RTOS/Template/CPP + CMAKE_FIND_ROOT_PATH_BOTH + ) + list(APPEND RTXRTOS_SOURCES ${RTXRTOS_SRC_FILE}) +endforeach() + +# find path for HAL_CMx file +set(RTXRTOS_SRC_FILE SRC_FILE-NOTFOUND) +find_file(RTXRTOS_SRC_FILE ${RTXRTOS_HAL_NAME} + PATHS PATHS ${PROJECT_BINARY_DIR}/RTXRTOS_Source/CMSIS/RTOS/RTX/SRC/GCC + CMAKE_FIND_ROOT_PATH_BOTH +) +list(APPEND RTXRTOS_SOURCES ${RTXRTOS_SRC_FILE}) + +# find path for SVC_Table file +set(RTXRTOS_SRC_FILE SRC_FILE-NOTFOUND) +find_file(RTXRTOS_SRC_FILE SVC_Table.S + PATHS PATHS ${PROJECT_BINARY_DIR}/RTXRTOS_Source/CMSIS/RTOS/RTX/SRC/GCC + CMAKE_FIND_ROOT_PATH_BOTH +) +list(APPEND RTXRTOS_SOURCES ${RTXRTOS_SRC_FILE}) + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(RTXRTOS DEFAULT_MSG RTXRTOS_INCLUDE_DIRS RTXRTOS_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindRTXRTOS2.cmake b/source/native/nf-interpreter/CMake/Modules/FindRTXRTOS2.cmake new file mode 100644 index 00000000..cc3342ae --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindRTXRTOS2.cmake @@ -0,0 +1,112 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +if(NOT STM32_CHIP_TYPE) + STM32_GET_CHIP_TYPE(${TARGET_CHIP} STM32_CHIP_TYPE) + if(NOT STM32_CHIP_TYPE) + message(FATAL_ERROR "Unknown chip: ${TARGET_CHIP}.") + endif() + message(STATUS "${TARGET_CHIP} is ${STM32_CHIP_TYPE} device") +endif() +string(TOLOWER ${STM32_CHIP_TYPE} STM32_CHIP_TYPE_LOWER) + + +# build path hints according to device series +if(STM32_SERIES STREQUAL "F0") + set(RTXRTOS2_HAL_NAME irq_cm0.S) + set(RTXRTOS2_COMPILE_OPTIONS -D__CORTEX_M0 -DCMSIS_device_header=ARMCM0.h) + list(APPEND RTXRTOS2_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/RTXRTOS_Source/Device/ARM/ARMCM0/Include) +elseif(STM32_SERIES STREQUAL "F1") + set(RTXRTOS2_HAL_NAME irq_cm0.S) + set(RTXRTOS2_COMPILE_OPTIONS -D__CORTEX_M0 -DCMSIS_device_header=ARMCM0.h) + list(APPEND RTXRTOS2_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/RTXRTOS_Source/Device/ARM/ARMCM0/Include) +elseif(STM32_SERIES STREQUAL "F2") + set(RTXRTOS2_HAL_NAME irq_cm0.S) + set(RTXRTOS2_COMPILE_OPTIONS -D__CORTEX_M0 -DCMSIS_device_header=ARMCM0.h) + list(APPEND RTXRTOS2_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/RTXRTOS_Source/Device/ARM/ARMCM0/Include) +elseif(STM32_SERIES STREQUAL "F3") + set(RTXRTOS2_HAL_NAME irq_cm3.S) + set(RTXRTOS2_COMPILE_OPTIONS -D__CORTEX_M3 -DCMSIS_device_header=ARMCM3.h) + list(APPEND RTXRTOS2_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/RTXRTOS_Source/Device/ARM/ARMCM3/Include) +elseif(STM32_SERIES STREQUAL "F4") + set(RTXRTOS2_HAL_NAME irq_cm4f.S) + set(RTXRTOS2_COMPILE_OPTIONS -D__CORTEX_M4 -DCMSIS_device_header=ARMCM4.h) + list(APPEND RTXRTOS2_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/RTXRTOS_Source/Device/ARM/ARMCM4/Include) +elseif(STM32_SERIES STREQUAL "F7") + set(RTXRTOS2_HAL_NAME irq_cm4f.S) + set(RTXRTOS2_COMPILE_OPTIONS -D__CORTEX_M7 -DCMSIS_device_header=ARMCM7.h) + list(APPEND RTXRTOS2_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/RTXRTOS_Source/Device/ARM/ARMCM7/Include) +elseif(STM32_SERIES STREQUAL "L0") + set(RTXRTOS2_HAL_NAME irq_cm0.S) + set(RTXRTOS2_COMPILE_OPTIONS -D__CORTEX_M0 -DCMSIS_device_header=ARMCM0.h) + list(APPEND RTXRTOS2_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/RTXRTOS_Source/Device/ARM/ARMCM0/Include) +elseif(STM32_SERIES STREQUAL "L1") + set(RTXRTOS2_HAL_NAME irq_cm0.S) + set(RTXRTOS2_COMPILE_OPTIONS -D__CORTEX_M0 -DCMSIS_device_header=ARMCM0.h) + list(APPEND RTXRTOS2_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/RTXRTOS_Source/Device/ARM/ARMCM0/Include) +elseif(STM32_SERIES STREQUAL "L4") + set(RTXRTOS2_HAL_NAME irq_cm4f.S) + set(RTXRTOS2_COMPILE_OPTIONS -D__CORTEX_M4 -DCMSIS_device_header=ARMCM4.h) + list(APPEND RTXRTOS2_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/RTXRTOS_Source/Device/ARM/ARMCM0/Include) +endif() + +# set include directories for RXT RTOS +list(APPEND RTXRTOS2_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/RTXRTOS_Source/CMSIS/Core/Include) +list(APPEND RTXRTOS2_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/RTXRTOS_Source/CMSIS/RTOS2/Include) +list(APPEND RTXRTOS2_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/RTXRTOS_Source/CMSIS/RTOS2/RTX/Include) +list(APPEND RTXRTOS2_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/RTXRTOS_Source/CMSIS/RTOS2/RTX/Include1) +list(APPEND RTXRTOS2_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/RTXRTOS_Source/CMSIS/RTOS2/RTX/Source) + +set(RTXRTOS2_SRCS + Events.c + MemPool.c + MsgQueue.c + Mutex.c + Semaphore.c + Thread.c + Timer.c + + rtx_delay.c + rtx_evflags.c + rtx_kernel.c + rtx_memory.c + rtx_mempool.c + rtx_msgqueue.c + rtx_mutex.c + rtx_semaphore.c + rtx_system.c + rtx_thread.c + rtx_timer.c + user_svc.c +) + +foreach(SRC_FILE ${RTXRTOS2_SRCS}) + set(RTXRTOS2_SRC_FILE SRC_FILE-NOTFOUND) + find_file(RTXRTOS2_SRC_FILE ${SRC_FILE} + PATHS ${PROJECT_BINARY_DIR}/RTXRTOS_Source/CMSIS/RTOS2/RTX/Source ${PROJECT_BINARY_DIR}/RTXRTOS_Source/CMSIS/RTOS2/RTX/Template + CMAKE_FIND_ROOT_PATH_BOTH + ) + list(APPEND RTXRTOS2_SOURCES ${RTXRTOS2_SRC_FILE}) +endforeach() + +# find path for HAL_CMx file +set(RTXRTOS2_SRC_FILE SRC_FILE-NOTFOUND) +find_file(RTXRTOS2_SRC_FILE ${RTXRTOS2_HAL_NAME} + PATHS PATHS ${PROJECT_BINARY_DIR}/RTXRTOS_Source/CMSIS/RTOS2/RTX/Source/GCC + CMAKE_FIND_ROOT_PATH_BOTH +) +list(APPEND RTXRTOS2_SOURCES ${RTXRTOS2_SRC_FILE}) + +# # find path for SVC_Table file +# set(RTXRTOS2_SRC_FILE SRC_FILE-NOTFOUND) +# find_file(RTXRTOS2_SRC_FILE SVC_Table.S +# PATHS PATHS ${PROJECT_BINARY_DIR}/RTXRTOS_Source/CMSIS/RTOS/RTX/SRC/GCC +# CMAKE_FIND_ROOT_PATH_BOTH +# ) +# list(APPEND RTXRTOS2_SOURCES ${RTXRTOS2_SRC_FILE}) + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(RTXRTOS2 DEFAULT_MSG RTXRTOS2_INCLUDE_DIRS RTXRTOS2_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindSPIFFS.cmake b/source/native/nf-interpreter/CMake/Modules/FindSPIFFS.cmake new file mode 100644 index 00000000..d3a13b9e --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindSPIFFS.cmake @@ -0,0 +1,40 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# List of the required include paths +list(APPEND SPIFFS_INCLUDE_DIRS ${CMAKE_BINARY_DIR}/SPIFFS_Source/src) + +set(src_spiffs + + spiffs_nucleus.c + spiffs_gc.c + spiffs_hydrogen.c + spiffs_cache.c + spiffs_check.c + + # HAL implementation specific to a platform + # has to be included at platform level + # hal_spiffs.c + + target_spiffs.c +) + +foreach(SRC_FILE ${src_spiffs}) + set(SPIFFS_SRC_FILE SRC_FILE -NOTFOUND) + find_file(SPIFFS_SRC_FILE ${SRC_FILE} + PATHS + + "${PROJECT_BINARY_DIR}/SPIFFS_Source/src" + "${TARGET_BASE_LOCATION}" + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${SPIFFS_SRC_FILE}") # debug helper + list(APPEND SPIFFS_SOURCES ${SPIFFS_SRC_FILE}) +endforeach() + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(SPIFFS DEFAULT_MSG SPIFFS_INCLUDE_DIRS SPIFFS_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindSTM32F0_CubePackage.cmake b/source/native/nf-interpreter/CMake/Modules/FindSTM32F0_CubePackage.cmake new file mode 100644 index 00000000..75939aa2 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindSTM32F0_CubePackage.cmake @@ -0,0 +1,31 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# set include directories +list(APPEND STM32F0_CubePackage_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/STM32F0_CubePackage_Source/Drivers/STM32F0xx_HAL_Driver/Inc") + +# source files +set(STM32F0_CubePackage_SRCS + + # add HAL files here as required +) + +foreach(SRC_FILE ${STM32F0_CubePackage_SRCS}) + set(STM32F0_CubePackage_SRC_FILE SRC_FILE-NOTFOUND) + find_file(STM32F0_CubePackage_SRC_FILE ${SRC_FILE} + PATHS + + "${PROJECT_BINARY_DIR}/STM32F0_CubePackage_Source/Drivers/STM32F0xx_HAL_Driver/Src" + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${STM32F0_CubePackage_SRC_FILE}") # debug helper + list(APPEND STM32F0_CubePackage_SOURCES ${STM32F0_CubePackage_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(STM32F0_CubePackage DEFAULT_MSG STM32F0_CubePackage_INCLUDE_DIRS STM32F0_CubePackage_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindSTM32F4_CubePackage.cmake b/source/native/nf-interpreter/CMake/Modules/FindSTM32F4_CubePackage.cmake new file mode 100644 index 00000000..557c94f4 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindSTM32F4_CubePackage.cmake @@ -0,0 +1,35 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# set include directories +list(APPEND STM32F4_CubePackage_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/STM32F4_CubePackage_Source/Drivers/STM32F4xx_HAL_Driver/Inc") + +# source files +set(STM32F4_CubePackage_SRCS + + # add HAL files here as required + + # SPIFFS + stm32f4xx_hal_dma.c + stm32f4xx_hal_qspi.c +) + +foreach(SRC_FILE ${STM32F4_CubePackage_SRCS}) + set(STM32F4_CubePackage_SRC_FILE SRC_FILE-NOTFOUND) + find_file(STM32F4_CubePackage_SRC_FILE ${SRC_FILE} + PATHS + + "${PROJECT_BINARY_DIR}/STM32F4_CubePackage_Source/Drivers/STM32F4xx_HAL_Driver/Src" + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${STM32F4_CubePackage_SRC_FILE}") # debug helper + list(APPEND STM32F4_CubePackage_SOURCES ${STM32F4_CubePackage_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(STM32F4_CubePackage DEFAULT_MSG STM32F4_CubePackage_INCLUDE_DIRS STM32F4_CubePackage_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindSTM32F7_CubePackage.cmake b/source/native/nf-interpreter/CMake/Modules/FindSTM32F7_CubePackage.cmake new file mode 100644 index 00000000..c5fb281c --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindSTM32F7_CubePackage.cmake @@ -0,0 +1,34 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# set include directories +list(APPEND STM32F7_CubePackage_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/STM32F7_CubePackage_Source/Drivers/STM32F7xx_HAL_Driver/Inc") + +# source files +set(STM32F7_CubePackage_SRCS + + # add HAL files here as required + + # SPIFFS + stm32f7xx_hal_dma.c + stm32f7xx_hal_qspi.c +) + +foreach(SRC_FILE ${STM32F7_CubePackage_SRCS}) + set(STM32F7_CubePackage_SRC_FILE SRC_FILE-NOTFOUND) + find_file(STM32F7_CubePackage_SRC_FILE ${SRC_FILE} + PATHS + + "${PROJECT_BINARY_DIR}/STM32F7_CubePackage_Source/Drivers/STM32F7xx_HAL_Driver/Src/" + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${STM32F7_CubePackage_SRC_FILE}") # debug helper + list(APPEND STM32F7_CubePackage_SOURCES ${STM32F7_CubePackage_SRC_FILE}) +endforeach() + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(STM32F7_CubePackage DEFAULT_MSG STM32F7_CubePackage_INCLUDE_DIRS STM32F7_CubePackage_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindSTM32FREERTOS.cmake b/source/native/nf-interpreter/CMake/Modules/FindSTM32FREERTOS.cmake new file mode 100644 index 00000000..8b557481 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindSTM32FREERTOS.cmake @@ -0,0 +1,115 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +if(NOT STM32_CHIP_TYPE) + STM32_GET_CHIP_TYPE(${TARGET_CHIP} STM32_CHIP_TYPE) + if(NOT STM32_CHIP_TYPE) + message(FATAL_ERROR "Unknown chip: ${TARGET_CHIP}.") + endif() + message(STATUS "${TARGET_CHIP} is ${STM32_CHIP_TYPE} device") +endif() +string(TOLOWER ${STM32_CHIP_TYPE} STM32_CHIP_TYPE_LOWER) + +# find path of STM32 CMSIS FreeRTOS port for include files +find_path(STM32CMSISFREERTOS_INCLUDE_DIR cmsis_os.h + PATH_SUFFIXES CMSIS_RTOS + HINTS ${STM32Cube_DIR}/Middlewares/Third_Party/FreeRTOS/Source + CMAKE_FIND_ROOT_PATH_BOTH +) + +# set path search for FreeRTOS distribution +set(FREERTOS_HEADERS + croutine.h + deprecated_definitions.h + event_groups.h + FreeRTOS.h + list.h + mpu_prototypes.h + mpu_wrappers.h + portable.h + projdefs.h + queue.h + semphr.h + StackMacros.h + task.h + timers.h +) + +# build path hints according to device series +if(STM32_SERIES STREQUAL "F0") + set(FREERTOS_PATH_SUFFIXES ARM_CM0) +elseif(STM32_SERIES STREQUAL "F1") + set(FREERTOS_PATH_SUFFIXES ARM_CM0) +elseif(STM32_SERIES STREQUAL "F2") + set(FREERTOS_PATH_SUFFIXES ARM_CM0) +elseif(STM32_SERIES STREQUAL "F3") + set(FREERTOS_PATH_SUFFIXES ARM_CM3) +elseif(STM32_SERIES STREQUAL "F4") + set(FREERTOS_PATH_SUFFIXES ARM_CM4F) +elseif(STM32_SERIES STREQUAL "F7") + set(FREERTOS_PATH_SUFFIXES ARM_CM7) +elseif(STM32_SERIES STREQUAL "L0") + set(FREERTOS_PATH_SUFFIXES ARM_CM0) +elseif(STM32_SERIES STREQUAL "L1") + set(FREERTOS_PATH_SUFFIXES ARM_CM0) +elseif(STM32_SERIES STREQUAL "L4") + set(FREERTOS_PATH_SUFFIXES ARM_CM4F) +endif() + +find_path(FREERTOS_INCLUDE_DIR ${FREERTOS_HEADERS} + PATH_SUFFIXES FreeRTOS_Source Include + PATHS ${PROJECT_BINARY_DIR}/FreeRTOS_Source + CMAKE_FIND_ROOT_PATH_BOTH +) + +find_path(FREERTOS_PORTABLE_INCLUDE_DIR portmacro.h + PATHS ${PROJECT_BINARY_DIR}/FreeRTOS_Source/portable/GCC/${FREERTOS_PATH_SUFFIXES} + CMAKE_FIND_ROOT_PATH_BOTH +) + +set(STM32FREERTOS_INCLUDE_DIR + ${STM32CMSISFREERTOS_INCLUDE_DIR} + ${FREERTOS_INCLUDE_DIR} + ${FREERTOS_PORTABLE_INCLUDE_DIR} +) + +set(SRC_FILE_FOUND SRC_FILE-NOTFOUND) +find_file(SRC_FILE_FOUND cmsis_os.c + #PATH_SUFFIXES CMSIS_RTOS + PATHS ${STM32Cube_DIR}/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS + CMAKE_FIND_ROOT_PATH_BOTH +) +list(APPEND STM32FREERTOS_SOURCES ${SRC_FILE_FOUND}) + +set(FREERTOS_SOURCES + croutine.c + event_groups.c + list.c + queue.c + tasks.c + timers.c + port.c + + # choose here the appropriate memory management for FreeRTOS (see http://www.freertos.org/a00111.html) + # heap_1.c + # heap_2.c + # heap_3.c + heap_4.c + #heap_5.c +) + +foreach(SRC_FILE ${FREERTOS_SOURCES}) + set(FREERTOS_SRC_FILE SRC_FILE-NOTFOUND) + find_file(FREERTOS_SRC_FILE ${SRC_FILE} + PATH_SUFFIXES FreeRTOS_Source Include ${FREERTOS_PATH_SUFFIXES} + PATHS ${PROJECT_BINARY_DIR} ${PROJECT_BINARY_DIR}/FreeRTOS_Source/portable/MemMang ${PROJECT_BINARY_DIR}/FreeRTOS_Source/portable/GCC + CMAKE_FIND_ROOT_PATH_BOTH + ) + list(APPEND STM32FREERTOS_SOURCES ${FREERTOS_SRC_FILE}) +endforeach() + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(STM32FREERTOS DEFAULT_MSG STM32FREERTOS_INCLUDE_DIR STM32FREERTOS_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindSTM32H7_CubePackage.cmake b/source/native/nf-interpreter/CMake/Modules/FindSTM32H7_CubePackage.cmake new file mode 100644 index 00000000..1f0cb07d --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindSTM32H7_CubePackage.cmake @@ -0,0 +1,34 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# set include directories +list(APPEND STM32H7_CubePackage_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/STM32H7_CubePackage_Source/Drivers/STM32H7xx_HAL_Driver/Inc") + +# source files +set(STM32H7_CubePackage_SRCS + + # add HAL files here as required + + # SPIFFS + stm32h7xx_hal_qspi.c +) + +foreach(SRC_FILE ${STM32H7_CubePackage_SRCS}) + set(STM32H7_CubePackage_SRC_FILE SRC_FILE-NOTFOUND) + find_file(STM32H7_CubePackage_SRC_FILE ${SRC_FILE} + PATHS + + "${PROJECT_BINARY_DIR}/STM32H7_CubePackage_Source/Drivers/STM32H7xx_HAL_Driver/Src" + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${STM32H7_CubePackage_SRC_FILE}") # debug helper + list(APPEND STM32H7_CubePackage_SOURCES ${STM32H7_CubePackage_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(STM32H7_CubePackage DEFAULT_MSG STM32H7_CubePackage_INCLUDE_DIRS STM32H7_CubePackage_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindSTM32L0_CubePackage.cmake b/source/native/nf-interpreter/CMake/Modules/FindSTM32L0_CubePackage.cmake new file mode 100644 index 00000000..e126f65f --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindSTM32L0_CubePackage.cmake @@ -0,0 +1,31 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# set include directories +list(APPEND STM32L0_CubePackage_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/STM32L0_CubePackage_Source/Drivers/STM32L0xx_HAL_Driver/Inc") + +# source files +set(STM32_CubePackage_SRCS + + # add HAL files here as required +) + +foreach(SRC_FILE ${STM32L0_CubePackage_SRCS}) + set(STM32L0_CubePackage_SRC_FILE SRC_FILE-NOTFOUND) + find_file(STM32L0_CubePackage_SRC_FILE ${SRC_FILE} + PATHS + + "${PROJECT_BINARY_DIR}/STM32L0_CubePackage_Source/Drivers/STM32L0xx_HAL_Driver/Src" + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${STM32L0_CubePackage_SRC_FILE}") # debug helper + list(APPEND STM32L0_CubePackage_SOURCES ${STM32L0_CubePackage_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(STM32L0_CubePackage DEFAULT_MSG STM32L0_CubePackage_INCLUDE_DIRS STM32L0_CubePackage_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindSystem.Devices.Dac.cmake b/source/native/nf-interpreter/CMake/Modules/FindSystem.Devices.Dac.cmake new file mode 100644 index 00000000..94b36889 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindSystem.Devices.Dac.cmake @@ -0,0 +1,46 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# native code directory +set(BASE_PATH_FOR_THIS_MODULE "${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/System.Devices.Dac") + + +# set include directories +list(APPEND System.Devices.Dac_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Core) +list(APPEND System.Devices.Dac_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Include) +list(APPEND System.Devices.Dac_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/HAL/Include) +list(APPEND System.Devices.Dac_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/PAL/Include) +list(APPEND System.Devices.Dac_INCLUDE_DIRS ${BASE_PATH_FOR_THIS_MODULE}) +list(APPEND System.Devices.Dac_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/System.Devices.Dac) + + +# source files +set(System.Devices.Dac_SRCS + + sys_dev_dac_native.cpp + sys_dev_dac_native_System_Devices_Dac_DacController.cpp + sys_dev_dac_native_System_Devices_Dac_DacChannel.cpp + + target_system_devices_dac_config.cpp +) + +foreach(SRC_FILE ${System.Devices.Dac_SRCS}) + set(System.Devices.Dac_SRC_FILE SRC_FILE-NOTFOUND) + find_file(System.Devices.Dac_SRC_FILE ${SRC_FILE} + PATHS + ${BASE_PATH_FOR_THIS_MODULE} + ${TARGET_BASE_LOCATION} + ${PROJECT_SOURCE_DIR}/src/System.Devices.Dac + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${System.Devices.Dac_SRC_FILE}") # debug helper + list(APPEND System.Devices.Dac_SOURCES ${System.Devices.Dac_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(System.Devices.Dac DEFAULT_MSG System.Devices.Dac_INCLUDE_DIRS System.Devices.Dac_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindSystem.Math.cmake b/source/native/nf-interpreter/CMake/Modules/FindSystem.Math.cmake new file mode 100644 index 00000000..e211bf2b --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindSystem.Math.cmake @@ -0,0 +1,38 @@ +# +# Copyright (c) 2018 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + + +# native code directory +set(BASE_PATH_FOR_THIS_MODULE "${PROJECT_SOURCE_DIR}/src/CLR/System.Math") + + +# set include directories +list(APPEND System.Math_INCLUDE_DIRS "${BASE_PATH_FOR_THIS_MODULE}") + + +# source files +set(System.Math_SRCS + + nf_native_system_math.cpp + nf_native_system_math_System_Math.cpp + +) + +foreach(SRC_FILE ${System.Math_SRCS}) + set(System.Math_SRC_FILE SRC_FILE-NOTFOUND) + find_file(System.Math_SRC_FILE ${SRC_FILE} + PATHS + "${BASE_PATH_FOR_THIS_MODULE}" + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${System.Math_SRC_FILE}") # debug helper + list(APPEND System.Math_SOURCES ${System.Math_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(System.Math DEFAULT_MSG System.Math_INCLUDE_DIRS System.Math_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindSystem.Net.cmake b/source/native/nf-interpreter/CMake/Modules/FindSystem.Net.cmake new file mode 100644 index 00000000..3f8f444f --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindSystem.Net.cmake @@ -0,0 +1,47 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# set include directories +list(APPEND System.Net_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/HAL/Include") +list(APPEND System.Net_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/DeviceInterfaces/System.Net") + +# source files +set(System.Net_SRCS + + # System.Net + sys_net_native.cpp + sys_net_native_System_Net_Sockets_NativeSocket.cpp + + # System.Net.NetworkInformation + sys_net_native_System_Net_NetworkInformation_NetworkInterface.cpp + sys_net_native_System_Net_NetworkInformation_Wireless80211Configuration.cpp + sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration.cpp + + # System.Security.Cryptography.X509Certificates + sys_net_native_System_Security_Cryptography_X509Certificates_X509Certificate.cpp + sys_net_native_System_Security_Cryptography_X509Certificates_X509Certificate2.cpp + + # System.Net.Security + sys_net_native_System_Net_Security_SslNative.cpp + sys_net_native_System_Net_Security_CertificateManager.cpp + +) + +foreach(SRC_FILE ${System.Net_SRCS}) + set(System.Net_SRC_FILE SRC_FILE-NOTFOUND) + find_file(System.Net_SRC_FILE ${SRC_FILE} + PATHS + + "${PROJECT_SOURCE_DIR}/src/DeviceInterfaces/System.Net" + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${System.Net_SRC_FILE}") # debug helper + list(APPEND System.Net_SOURCES ${System.Net_SRC_FILE}) +endforeach() + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(System.Net DEFAULT_MSG System.Net_INCLUDE_DIRS System.Net_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindTI_SimpleLink.cmake b/source/native/nf-interpreter/CMake/Modules/FindTI_SimpleLink.cmake new file mode 100644 index 00000000..9c76d4ee --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindTI_SimpleLink.cmake @@ -0,0 +1,95 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +################################################################################################################################### +# WHEN ADDING A NEW series add the respective name to the list below along with the CMake files with GCC options and source files +################################################################################################################################### + +# check if the series name is supported + +set(TI_SIMPLELINK_SUPPORTED_SERIES "CC32xx" CACHE INTERNAL "supported TI series names") + +list(FIND TI_SIMPLELINK_SUPPORTED_SERIES ${TARGET_SERIES} TARGET_SERIES_NAME_INDEX) +if(TI_SIMPLELINK_SUPPORTED_SERIES EQUAL -1) + if(TARGET_SERIES_NAME_INDEX EQUAL -1) + message(FATAL_ERROR "\n\nSorry but the ${TARGET_SERIES} is not supported at this time...\nYou can wait for it to be added, or you might want to contribute by working on a PR for it.\n\n") + else() + # series is supported by TI + set(TARGET_VENDOR "TI" CACHE INTERNAL "target vendor is TI") + endif() +endif() + +# including here the CMake files for the source files specific to the target series +include(TI_SimpleLink_${TARGET_SERIES}_sources) + +# and here the GCC options tuned for the target series +include(TI_SimpleLink_${TARGET_SERIES}_GCC_options) + +# includes for FreeRTOS +list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/FreeRTOS_Source/lib/include") +list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/FreeRTOS_Source/lib/include/private") +list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/FreeRTOS_Source/lib/FreeRTOS/portable/GCC/ARM_CM3") +list(APPEND TI_SimpleLink_INCLUDE_DIRS "${TARGET_BASE_LOCATION}") + +# source files for FreeRTOS +set(FreeRTOS_SRCS + + # FreeRTOS + event_groups.c + list.c + queue.c + stream_buffer.c + tasks.c + timers.c + port.c + heap_4.c + clock.c + memory.c + mqueue.c + pthread_barrier.c + pthread_cond.c + pthread.c + pthread_mutex.c + pthread_rwlock.c + sched.c + semaphore.c + sleep.c + timer.c + PTLS.c + aeabi_portable.c + ClockP_freertos.c + DebugP_freertos.c + MutexP_freertos.c + SemaphoreP_freertos.c + SystemP_freertos.c + HwiPCC32XX_freertos.c + PowerCC32XX_freertos.c + startup_cc32xx_gcc.c + +) + +foreach(SRC_FILE ${FreeRTOS_SRCS}) + set(FreeRTOS_SCR_FILE SRC_FILE -NOTFOUND) + find_file(FreeRTOS_SCR_FILE ${SRC_FILE} + PATHS + + # FreeRTOS + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/posix/freertos" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/source" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/kernel/freertos/dpl" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/kernel/freertos/startup" + "${PROJECT_BINARY_DIR}/FreeRTOS_Source/lib/FreeRTOS/portable/MemMang" + "${PROJECT_BINARY_DIR}/FreeRTOS_Source/lib/FreeRTOS/portable/GCC/ARM_CM3" + "${PROJECT_BINARY_DIR}/FreeRTOS_Source/lib/FreeRTOS" + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${FreeRTOS_SCR_FILE}") # debug helper + list(APPEND TI_SimpleLink_SOURCES ${FreeRTOS_SCR_FILE}) +endforeach() + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(TI_SimpleLink DEFAULT_MSG TI_SimpleLink_INCLUDE_DIRS TI_SimpleLink_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindWindows.Devices.Adc.cmake b/source/native/nf-interpreter/CMake/Modules/FindWindows.Devices.Adc.cmake new file mode 100644 index 00000000..70d6479a --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindWindows.Devices.Adc.cmake @@ -0,0 +1,46 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# native code directory +set(BASE_PATH_FOR_THIS_MODULE "${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/Windows.Devices.Adc") + + +# set include directories +list(APPEND Windows.Devices.Adc_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Core) +list(APPEND Windows.Devices.Adc_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Include) +list(APPEND Windows.Devices.Adc_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/HAL/Include) +list(APPEND Windows.Devices.Adc_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/PAL/Include) +list(APPEND Windows.Devices.Adc_INCLUDE_DIRS ${BASE_PATH_FOR_THIS_MODULE}) +list(APPEND Windows.Devices.Adc_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/Windows.Devices.Adc) + + +# source files +set(Windows.Devices.Adc_SRCS + + win_dev_adc_native.cpp + win_dev_adc_native_Windows_Devices_Adc_AdcController.cpp + win_dev_adc_native_Windows_Devices_Adc_AdcChannel.cpp + + target_windows_devices_adc_config.cpp +) + +foreach(SRC_FILE ${Windows.Devices.Adc_SRCS}) + set(Windows.Devices.Adc_SRC_FILE SRC_FILE-NOTFOUND) + find_file(Windows.Devices.Adc_SRC_FILE ${SRC_FILE} + PATHS + ${BASE_PATH_FOR_THIS_MODULE} + ${TARGET_BASE_LOCATION} + ${PROJECT_SOURCE_DIR}/src/Windows.Devices.Adc + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${Windows.Devices.Adc_SRC_FILE}") # debug helper + list(APPEND Windows.Devices.Adc_SOURCES ${Windows.Devices.Adc_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(Windows.Devices.Adc DEFAULT_MSG Windows.Devices.Adc_INCLUDE_DIRS Windows.Devices.Adc_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindWindows.Devices.Gpio.cmake b/source/native/nf-interpreter/CMake/Modules/FindWindows.Devices.Gpio.cmake new file mode 100644 index 00000000..7cda082a --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindWindows.Devices.Gpio.cmake @@ -0,0 +1,60 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# native code directory +set(BASE_PATH_FOR_THIS_MODULE "${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/Windows.Devices.Gpio") + + +# set include directories +list(APPEND Windows.Devices.Gpio_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Core) +list(APPEND Windows.Devices.Gpio_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Include) +list(APPEND Windows.Devices.Gpio_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/HAL/Include) +list(APPEND Windows.Devices.Gpio_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/PAL/Include) +list(APPEND Windows.Devices.Gpio_INCLUDE_DIRS ${BASE_PATH_FOR_THIS_MODULE}) +list(APPEND Windows.Devices.Gpio_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/Windows.Devices.Gpio) + + +# source files +set(Windows.Devices.Gpio_SRCS + + # class library source files + win_dev_gpio_native_Windows_Devices_Gpio_GpioController.cpp + win_dev_gpio_native_Windows_Devices_Gpio_GpioPin.cpp + win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter.cpp + win_dev_gpio_native.cpp + + # core source files + AsyncCompletions.cpp + AsyncContinuations.cpp + NativeEventDispatcher.cpp + InterruptHandler.cpp + Hardware.cpp +) + +foreach(SRC_FILE ${Windows.Devices.Gpio_SRCS}) + set(Windows.Devices.Gpio_SRC_FILE SRC_FILE-NOTFOUND) + find_file(Windows.Devices.Gpio_SRC_FILE ${SRC_FILE} + PATHS + + # class library source files + ${BASE_PATH_FOR_THIS_MODULE} + + # core source files + ${PROJECT_SOURCE_DIR}/src/PAL/AsyncProcCall + ${PROJECT_SOURCE_DIR}/src/CLR/Core/NativeEventDispatcher + ${PROJECT_SOURCE_DIR}/src/CLR/Core/InterruptHandler + ${PROJECT_SOURCE_DIR}/src/CLR/Core/Hardware + ${PROJECT_SOURCE_DIR}/src/Windows.Devices.Gpio + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${Windows.Devices.Gpio_SRC_FILE}") # debug helper + list(APPEND Windows.Devices.Gpio_SOURCES ${Windows.Devices.Gpio_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(Windows.Devices.Gpio DEFAULT_MSG Windows.Devices.Gpio_INCLUDE_DIRS Windows.Devices.Gpio_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindWindows.Devices.I2c.cmake b/source/native/nf-interpreter/CMake/Modules/FindWindows.Devices.I2c.cmake new file mode 100644 index 00000000..ea9f242c --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindWindows.Devices.I2c.cmake @@ -0,0 +1,46 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# native code directory +set(BASE_PATH_FOR_THIS_MODULE "${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/Windows.Devices.I2c") + + +# set include directories +list(APPEND Windows.Devices.I2c_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Core) +list(APPEND Windows.Devices.I2c_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Include) +list(APPEND Windows.Devices.I2c_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/HAL/Include) +list(APPEND Windows.Devices.I2c_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/PAL/Include) +list(APPEND Windows.Devices.I2c_INCLUDE_DIRS ${BASE_PATH_FOR_THIS_MODULE}) +list(APPEND Windows.Devices.I2c_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/Windows.Devices.I2c) + + +# source files +set(Windows.Devices.I2c_SRCS + + win_dev_i2c_native.cpp + win_dev_i2c_native_Windows_Devices_I2C_I2cDevice.cpp + win_dev_i2c_native_Windows_Devices_I2c_I2cController.cpp + + target_windows_devices_i2c_config.cpp +) + +foreach(SRC_FILE ${Windows.Devices.I2c_SRCS}) + set(Windows.Devices.I2c_SRC_FILE SRC_FILE-NOTFOUND) + find_file(Windows.Devices.I2c_SRC_FILE ${SRC_FILE} + PATHS + ${BASE_PATH_FOR_THIS_MODULE} + ${TARGET_BASE_LOCATION} + ${PROJECT_SOURCE_DIR}/src/Windows.Devices.I2c + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${Windows.Devices.I2c_SRC_FILE}") # debug helper + list(APPEND Windows.Devices.I2c_SOURCES ${Windows.Devices.I2c_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(Windows.Devices.I2c DEFAULT_MSG Windows.Devices.I2c_INCLUDE_DIRS Windows.Devices.I2c_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindWindows.Devices.Pwm.cmake b/source/native/nf-interpreter/CMake/Modules/FindWindows.Devices.Pwm.cmake new file mode 100644 index 00000000..3dbc6351 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindWindows.Devices.Pwm.cmake @@ -0,0 +1,43 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# native code directory +set(BASE_PATH_FOR_THIS_MODULE "${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/Windows.Devices.Pwm") + + +# set include directories +list(APPEND Windows.Devices.Pwm_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Core) +list(APPEND Windows.Devices.Pwm_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Include) +list(APPEND Windows.Devices.Pwm_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/HAL/Include) +list(APPEND Windows.Devices.Pwm_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/PAL/Include) +list(APPEND Windows.Devices.Pwm_INCLUDE_DIRS ${BASE_PATH_FOR_THIS_MODULE}) +list(APPEND Windows.Devices.Pwm_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/Windows.Devices.Pwm) + + +# source files +set(Windows.Devices.Pwm_SRCS + + win_dev_pwm_native.cpp + win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp + win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp +) + +foreach(SRC_FILE ${Windows.Devices.Pwm_SRCS}) + set(Windows.Devices.Pwm_SRC_FILE SRC_FILE-NOTFOUND) + find_file(Windows.Devices.Pwm_SRC_FILE ${SRC_FILE} + PATHS + ${BASE_PATH_FOR_THIS_MODULE} + ${PROJECT_SOURCE_DIR}/src/Windows.Devices.Pwm + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${Windows.Devices.Pwm_SRC_FILE}") # debug helper + list(APPEND Windows.Devices.Pwm_SOURCES ${Windows.Devices.Pwm_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(Windows.Devices.Pwm DEFAULT_MSG Windows.Devices.Pwm_INCLUDE_DIRS Windows.Devices.Pwm_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindWindows.Devices.SerialCommunication.cmake b/source/native/nf-interpreter/CMake/Modules/FindWindows.Devices.SerialCommunication.cmake new file mode 100644 index 00000000..5c3baf41 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindWindows.Devices.SerialCommunication.cmake @@ -0,0 +1,42 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# native code directory +set(BASE_PATH_FOR_THIS_MODULE "${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/Windows.Devices.SerialCommunication") + + +# set include directories +list(APPEND Windows.Devices.SerialCommunication_INCLUDE_DIRS ${BASE_PATH_FOR_THIS_MODULE}) +list(APPEND Windows.Devices.SerialCommunication_INCLUDE_DIRS ${TARGET_BASE_LOCATION}) +list(APPEND Windows.Devices.SerialCommunication_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/Windows.Devices.SerialCommunication) + + +# source files +set(Windows.Devices.SerialCommunication_SRCS + + win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice.cpp + win_dev_serial_native.cpp + + target_windows_devices_serialcommunication_config.cpp +) + +foreach(SRC_FILE ${Windows.Devices.SerialCommunication_SRCS}) + set(Windows.Devices.SerialCommunication_SRC_FILE SRC_FILE-NOTFOUND) + find_file(Windows.Devices.SerialCommunication_SRC_FILE ${SRC_FILE} + PATHS + ${BASE_PATH_FOR_THIS_MODULE} + ${TARGET_BASE_LOCATION} + ${PROJECT_SOURCE_DIR}/src/Windows.Devices.SerialCommunication + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${Windows.Devices.SerialCommunication_SRC_FILE}") # debug helper + list(APPEND Windows.Devices.SerialCommunication_SOURCES ${Windows.Devices.SerialCommunication_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(Windows.Devices.SerialCommunication DEFAULT_MSG Windows.Devices.SerialCommunication_INCLUDE_DIRS Windows.Devices.SerialCommunication_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindWindows.Devices.Spi.cmake b/source/native/nf-interpreter/CMake/Modules/FindWindows.Devices.Spi.cmake new file mode 100644 index 00000000..ec3f708f --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindWindows.Devices.Spi.cmake @@ -0,0 +1,47 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# native code directory +set(BASE_PATH_FOR_THIS_MODULE "${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/Windows.Devices.Spi") + + +# set include directories +list(APPEND Windows.Devices.Spi_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Core) +list(APPEND Windows.Devices.Spi_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Include) +list(APPEND Windows.Devices.Spi_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/HAL/Include) +list(APPEND Windows.Devices.Spi_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/PAL/Include) +list(APPEND Windows.Devices.Spi_INCLUDE_DIRS ${BASE_PATH_FOR_THIS_MODULE}) +list(APPEND Windows.Devices.Spi_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/Windows.Devices.Spi) + + +# source files +set(Windows.Devices.Spi_SRCS + + win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo.cpp + win_dev_spi_native_Windows_Devices_Spi_SpiController.cpp + win_dev_spi_native_Windows_Devices_Spi_SpiDevice.cpp + win_dev_spi_native.cpp + + target_windows_devices_spi_config.cpp +) + +foreach(SRC_FILE ${Windows.Devices.Spi_SRCS}) + set(Windows.Devices.Spi_SRC_FILE SRC_FILE-NOTFOUND) + find_file(Windows.Devices.Spi_SRC_FILE ${SRC_FILE} + PATHS + ${BASE_PATH_FOR_THIS_MODULE} + ${TARGET_BASE_LOCATION} + ${PROJECT_SOURCE_DIR}/src/Windows.Devices.Spi + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${Windows.Devices.Spi_SRC_FILE}") # debug helper + list(APPEND Windows.Devices.Spi_SOURCES ${Windows.Devices.Spi_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(Windows.Devices.Spi DEFAULT_MSG Windows.Devices.Spi_INCLUDE_DIRS Windows.Devices.Spi_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindWindows.Devices.WiFi.cmake b/source/native/nf-interpreter/CMake/Modules/FindWindows.Devices.WiFi.cmake new file mode 100644 index 00000000..e1221581 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindWindows.Devices.WiFi.cmake @@ -0,0 +1,42 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# native code directory +set(BASE_PATH_FOR_THIS_MODULE "${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/Windows.Devices.Wifi") + + +# set include directories +list(APPEND Windows.Devices.Wifi_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Core) +list(APPEND Windows.Devices.Wifi_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Include) +list(APPEND Windows.Devices.Wifi_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/HAL/Include) +list(APPEND Windows.Devices.Wifi_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/PAL/Include) +list(APPEND Windows.Devices.Wifi_INCLUDE_DIRS ${BASE_PATH_FOR_THIS_MODULE}) +list(APPEND Windows.Devices.Wifi_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/Windows.Devices.Wifi) + + +# source files +set(Windows.Devices.Wifi_SRCS + + win_dev_wifi_native.cpp + win_dev_wifi_native_Windows_Devices_WIFI_WifiAdapter.cpp +) + +foreach(SRC_FILE ${Windows.Devices.Wifi_SRCS}) + set(Windows.Devices.Wifi_SRC_FILE SRC_FILE-NOTFOUND) + find_file(Windows.Devices.Wifi_SRC_FILE ${SRC_FILE} + PATHS + ${BASE_PATH_FOR_THIS_MODULE} + ${PROJECT_SOURCE_DIR}/src/Windows.Devices.Wifi + + CMAKE_FIND_ROOT_PATH_BOTH + ) + #message("${SRC_FILE} >> ${Windows.Devices.Wifi_SRC_FILE}") # debug helper + list(APPEND Windows.Devices.Wifi_SOURCES ${Windows.Devices.Wifi_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(Windows.Devices.Wifi DEFAULT_MSG Windows.Devices.Wifi_INCLUDE_DIRS Windows.Devices.Wifi_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindWindows.Networking.Sockets.cmake b/source/native/nf-interpreter/CMake/Modules/FindWindows.Networking.Sockets.cmake new file mode 100644 index 00000000..a54b830f --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindWindows.Networking.Sockets.cmake @@ -0,0 +1,45 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# native code directory +#set(BASE_PATH_FOR_THIS_MODULE "${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/Windows.Networking.Sockets") +set(BASE_PATH_FOR_THIS_MODULE "${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/System.Net") + + +# set include directories +list(APPEND Windows.Networking.Sockets_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Core) +list(APPEND Windows.Networking.Sockets_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Include) +list(APPEND Windows.Networking.Sockets_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/HAL/Include) +list(APPEND Windows.Networking.Sockets_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/PAL/Include) +list(APPEND Windows.Networking.Sockets_INCLUDE_DIRS ${BASE_PATH_FOR_THIS_MODULE}) +list(APPEND Windows.Networking.Sockets_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/Windows.Networking.Sockets) + + +# source files +set(Windows.Networking.Sockets_SRCS + +# win_net_sockets_native.cpp +# win_net_sockets_native_Windows_Networking_Sockets_SocketNative.cpp + sys_net_native.cpp + sys_net_native_System_Net_Sockets_NativeSocket.cpp +) + +foreach(SRC_FILE ${Windows.Networking.Sockets_SRCS}) + set(Windows.Networking.Sockets_SRC_FILE SRC_FILE-NOTFOUND) + find_file(Windows.Networking.Sockets_SRC_FILE ${SRC_FILE} + PATHS + ${BASE_PATH_FOR_THIS_MODULE} + ${PROJECT_SOURCE_DIR}/src/Windows.Networking.Sockets + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${Windows.Networking.Sockets_SRC_FILE}") # debug helper + list(APPEND Windows.Networking.Sockets_SOURCES ${Windows.Networking.Sockets_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(Windows.Networking.Sockets DEFAULT_MSG Windows.Networking.Sockets_INCLUDE_DIRS Windows.Networking.Sockets_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindWindows.Storage.cmake b/source/native/nf-interpreter/CMake/Modules/FindWindows.Storage.cmake new file mode 100644 index 00000000..2577f5e7 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindWindows.Storage.cmake @@ -0,0 +1,52 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# native code directory +set(BASE_PATH_FOR_THIS_MODULE "${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/Windows.Storage") + + +# set include directories +if(RTOS_CHIBIOS_CHECK) + list(APPEND Windows.Storage_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/fatfs/src) + set( PROJECT_COMMON_PATH ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/common) +endif() + +list(APPEND Windows.Storage_INCLUDE_DIRS ${TARGET_BASE_LOCATION}/Include) +list(APPEND Windows.Storage_INCLUDE_DIRS ${BASE_PATH_FOR_THIS_MODULE}) +list(APPEND Windows.Storage_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/Windows.Storage) + + +# source files +set(Windows.Storage_SRCS + + win_storage_native_Windows_Storage_FileIO.cpp + win_storage_native_Windows_Storage_StorageFile.cpp + win_storage_native_Windows_Storage_StorageFolder.cpp + win_storage_native_Windows_Storage_Devices_SDCard.cpp + win_storage_native.cpp + + Target_Windows_Storage.c +) + +foreach(SRC_FILE ${Windows.Storage_SRCS}) + set(Windows.Storage_SRC_FILE SRC_FILE-NOTFOUND) + find_file(Windows.Storage_SRC_FILE ${SRC_FILE} + PATHS + + ${BASE_PATH_FOR_THIS_MODULE} + ${TARGET_BASE_LOCATION} + ${PROJECT_COMMON_PATH} + ${PROJECT_SOURCE_DIR}/src/Windows.Storage + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${Windows.Storage_SRC_FILE}") # debug helper + list(APPEND Windows.Storage_SOURCES ${Windows.Storage_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(Windows.Storage DEFAULT_MSG Windows.Storage_INCLUDE_DIRS Windows.Storage_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindWireProtocol.cmake b/source/native/nf-interpreter/CMake/Modules/FindWireProtocol.cmake new file mode 100644 index 00000000..4ab68c8c --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindWireProtocol.cmake @@ -0,0 +1,71 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# handle Wire Protocol _TRACE_ preferences, if any +option(NF_WP_TRACE_ERRORS "option to Trace errors with Wire Protocol") +option(NF_WP_TRACE_HEADERS "option to Trace headers with Wire Protocol") +option(NF_WP_TRACE_STATE "option to Trace state with Wire Protocol") +option(NF_WP_TRACE_NODATA "option to Trace empty packets with Wire Protocol") +option(NF_WP_TRACE_ALL "option to Trace with Wire Protocol") +option(NF_WP_IMPLEMENTS_CRC32 "option to report if target implements CRC32 in Wire Protocol") + +# this one has to follow the declaration on src\CLR\Include\WireProtocol_Message.h +# #define TRACE_ERRORS 1 +# #define TRACE_HEADERS 2 +# #define TRACE_STATE 4 +# #define TRACE_NODATA 8 + +# default to 0 (no Wire Protocol trace) +set(WP_TRACE_MASK 0 CACHE INTERNAL "WP trace mask") + +if(NF_WP_TRACE_ERRORS) + math(EXPR WP_TRACE_MASK "${WP_TRACE_MASK} + 1") +endif() +if(NF_WP_TRACE_HEADERS) + math(EXPR WP_TRACE_MASK "${WP_TRACE_MASK} + 2") +endif() +if(NF_WP_TRACE_STATE) + math(EXPR WP_TRACE_MASK "${WP_TRACE_MASK} + 4") +endif() +if(NF_WP_TRACE_NODATA) + math(EXPR WP_TRACE_MASK "${WP_TRACE_MASK} + 8") +endif() +if(NF_WP_TRACE_ALL) + math(EXPR WP_TRACE_MASK "8 + 4 + 2 + 1") +endif() + +message(STATUS "Wire Protocol TRACE_MASK is '${WP_TRACE_MASK}'") # debug helper + +# set include directories for Wire Protocol +list(APPEND WireProtocol_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Include) + +# source files for Wire Protocol +set(WireProtocol_SRCS + + WireProtocol_Message.c + WireProtocol_MonitorCommands.c + WireProtocol_HAL_Interface.c + WireProtocol_App_Interface.c + + nanoSupport_CRC32.c +) + +foreach(SRC_FILE ${WireProtocol_SRCS}) + set(WireProtocol_SRC_FILE SRC_FILE-NOTFOUND) + find_file(WireProtocol_SRC_FILE ${SRC_FILE} + PATHS + ${PROJECT_SOURCE_DIR}/src/CLR/WireProtocol + ${PROJECT_SOURCE_DIR}/src/CLR/Core + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${WireProtocol_SRC_FILE}") # debug helper + list(APPEND WireProtocol_SOURCES ${WireProtocol_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(WireProtocol DEFAULT_MSG WireProtocol_INCLUDE_DIRS WireProtocol_SOURCES) \ No newline at end of file diff --git a/source/native/nf-interpreter/CMake/Modules/FindmbedTLS.cmake b/source/native/nf-interpreter/CMake/Modules/FindmbedTLS.cmake new file mode 100644 index 00000000..52149f83 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindmbedTLS.cmake @@ -0,0 +1,157 @@ +# +# Copyright (c) 2018 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# because of issues when passing the config file as a string when using ExternalProject_Add with mbedTLS +# we are replicating their CMakeList here. Actually this is more a simplified version... + +# List of the required include paths +list(APPEND mbedTLS_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/mbedTLS_Source/include/) + +option(USE_PKCS11_HELPER_LIBRARY "Build mbed TLS with the pkcs11-helper library." OFF) +option(ENABLE_ZLIB_SUPPORT "Build mbed TLS with zlib library." OFF) + +if(ENABLE_ZLIB_SUPPORT) + find_package(ZLIB) + + if(ZLIB_FOUND) + include_directories(${ZLIB_INCLUDE_DIR}) + endif(ZLIB_FOUND) +endif(ENABLE_ZLIB_SUPPORT) + +# add_subdirectory(library) +# add_subdirectory(include) + +set(src_crypto + aes.c + aesni.c + arc4.c + aria.c + asn1parse.c + asn1write.c + base64.c + bignum.c + blowfish.c + camellia.c + ccm.c + cipher.c + cipher_wrap.c + cmac.c + ctr_drbg.c + des.c + dhm.c + ecdh.c + ecdsa.c + ecjpake.c + ecp.c + ecp_curves.c + entropy.c + entropy_poll.c + error.c + gcm.c + havege.c + hkdf.c + hmac_drbg.c + md.c + md2.c + md4.c + md5.c + md_wrap.c + memory_buffer_alloc.c + oid.c + padlock.c + pem.c + pk.c + pk_wrap.c + pkcs12.c + pkcs5.c + pkparse.c + pkwrite.c + platform.c + platform_util.c + ripemd160.c + rsa.c + rsa_internal.c + sha1.c + sha256.c + sha512.c + threading.c + timing.c + version.c + version_features.c + xtea.c + + # platform implementation of hardware random provider + mbedtls_entropy_hardware_pool.c +) + +set(src_x509 + certs.c + pkcs11.c + x509.c + x509_create.c + x509_crl.c + x509_crt.c + x509_csr.c + x509write_crt.c + x509write_csr.c +) + +set(src_tls + debug.c + net_sockets.c + ssl_cache.c + ssl_ciphersuites.c + ssl_cli.c + ssl_cookie.c + ssl_srv.c + ssl_ticket.c + ssl_tls.c +) + +foreach(SRC_FILE ${src_crypto}) + set(MBEDTLS_SRC_FILE SRC_FILE -NOTFOUND) + find_file(MBEDTLS_SRC_FILE ${SRC_FILE} + PATHS + ${PROJECT_BINARY_DIR}/mbedTLS_Source/library + + ${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/ + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${MBEDTLS_SRC_FILE}") # debug helper + list(APPEND mbedTLS_SOURCES ${MBEDTLS_SRC_FILE}) +endforeach() + +# unset this warning as error required for this source file +SET_SOURCE_FILES_PROPERTIES( ${PROJECT_BINARY_DIR}/mbedTLS_Source/library/hmac_drbg.c PROPERTIES COMPILE_FLAGS -Wno-maybe-uninitialized) +SET_SOURCE_FILES_PROPERTIES( ${PROJECT_BINARY_DIR}/mbedTLS_Source/library/x509_crt.c PROPERTIES COMPILE_FLAGS -Wno-maybe-uninitialized) + +foreach(SRC_FILE ${src_x509}) + set(MBEDTLS_SRC_FILE SRC_FILE -NOTFOUND) + find_file(MBEDTLS_SRC_FILE ${SRC_FILE} + PATHS + ${PROJECT_BINARY_DIR}/mbedTLS_Source/library + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${MBEDTLS_SRC_FILE}") # debug helper + list(APPEND mbedTLS_SOURCES ${MBEDTLS_SRC_FILE}) +endforeach() + +foreach(SRC_FILE ${src_tls}) + set(MBEDTLS_SRC_FILE SRC_FILE -NOTFOUND) + find_file(MBEDTLS_SRC_FILE ${SRC_FILE} + PATHS + ${PROJECT_BINARY_DIR}/mbedTLS_Source/library + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${MBEDTLS_SRC_FILE}") # debug helper + list(APPEND mbedTLS_SOURCES ${MBEDTLS_SRC_FILE}) +endforeach() + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(mbedTLS DEFAULT_MSG mbedTLS_INCLUDE_DIRS mbedTLS_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindnanoFramework.Devices.Can.cmake b/source/native/nf-interpreter/CMake/Modules/FindnanoFramework.Devices.Can.cmake new file mode 100644 index 00000000..384152a8 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindnanoFramework.Devices.Can.cmake @@ -0,0 +1,42 @@ +# +# Copyright (c) 2018 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + + +# native code directory +set(BASE_PATH_FOR_THIS_MODULE "${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/nanoFramework.Devices.Can") + + +# set include directories +list(APPEND nanoFramework.Devices.Can_INCLUDE_DIRS ${BASE_PATH_FOR_THIS_MODULE}) +list(APPEND nanoFramework.Devices.Can_INCLUDE_DIRS ${TARGET_BASE_LOCATION}) +list(APPEND nanoFramework.Devices.Can_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/nanoFramework.Devices.Can) + +# source files +set(nanoFramework.Devices.Can_SRCS + + nf_devices_can_native_nanoFramework_Devices_Can_CanController.cpp + nf_devices_can_native.cpp + + target_nf_devices_can_config.cpp +) + +foreach(SRC_FILE ${nanoFramework.Devices.Can_SRCS}) + set(nanoFramework.Devices.Can_SRC_FILE SRC_FILE-NOTFOUND) + find_file(nanoFramework.Devices.Can_SRC_FILE ${SRC_FILE} + PATHS + ${BASE_PATH_FOR_THIS_MODULE} + ${TARGET_BASE_LOCATION} + ${PROJECT_SOURCE_DIR}/src/nanoFramework.Devices.Can + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${nanoFramework.Devices.Can_SRC_FILE}") # debug helper + list(APPEND nanoFramework.Devices.Can_SOURCES ${nanoFramework.Devices.Can_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(nanoFramework.Devices.Can DEFAULT_MSG nanoFramework.Devices.Can_INCLUDE_DIRS nanoFramework.Devices.Can_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindnanoFramework.Devices.OneWire.cmake b/source/native/nf-interpreter/CMake/Modules/FindnanoFramework.Devices.OneWire.cmake new file mode 100644 index 00000000..c3d9e3a4 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindnanoFramework.Devices.OneWire.cmake @@ -0,0 +1,42 @@ +# +# Copyright (c) 2018 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + + +# native code directory +set(BASE_PATH_FOR_THIS_MODULE "${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/nanoFramework.Devices.OneWire") + + +# set include directories +list(APPEND nanoFramework.Devices.OneWire_INCLUDE_DIRS ${BASE_PATH_FOR_THIS_MODULE}) +list(APPEND nanoFramework.Devices.OneWire_INCLUDE_DIRS ${TARGET_BASE_LOCATION}) +list(APPEND nanoFramework.Devices.OneWire_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/nanoFramework.Devices.OneWire) + +# source files +set(nanoFramework.Devices.OneWire_SRCS + + nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController.cpp + nf_devices_onewire_native.cpp + + target_nf_devices_onewire_config.cpp +) + +foreach(SRC_FILE ${nanoFramework.Devices.OneWire_SRCS}) + set(nanoFramework.Devices.OneWire_SRC_FILE SRC_FILE-NOTFOUND) + find_file(nanoFramework.Devices.OneWire_SRC_FILE ${SRC_FILE} + PATHS + ${BASE_PATH_FOR_THIS_MODULE} + ${TARGET_BASE_LOCATION} + ${PROJECT_SOURCE_DIR}/src/nanoFramework.Devices.OneWire + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${nanoFramework.Devices.OneWire_SRC_FILE}") # debug helper + list(APPEND nanoFramework.Devices.OneWire_SOURCES ${nanoFramework.Devices.OneWire_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(nanoFramework.Devices.OneWire DEFAULT_MSG nanoFramework.Devices.OneWire_INCLUDE_DIRS nanoFramework.Devices.OneWire_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindnanoFramework.Hardware.Esp32.cmake b/source/native/nf-interpreter/CMake/Modules/FindnanoFramework.Hardware.Esp32.cmake new file mode 100644 index 00000000..9255d68c --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindnanoFramework.Hardware.Esp32.cmake @@ -0,0 +1,42 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# native code directory +set(BASE_PATH_FOR_THIS_MODULE "${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/nanoFramework.Hardware.Esp32") + + +# set include directories +list(APPEND nanoFramework.Hardware.Esp32_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/CLR/Core") +list(APPEND nanoFramework.Hardware.Esp32_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/CLR/Include") +list(APPEND nanoFramework.Hardware.Esp32_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/HAL/Include") +list(APPEND nanoFramework.Hardware.Esp32_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/PAL/Include") +list(APPEND nanoFramework.Hardware.Esp32_INCLUDE_DIRS "${BASE_PATH_FOR_THIS_MODULE}") + +# source files +set(nanoFramework.Hardware.Esp32_SRCS + + nanoFramework_hardware_esp32_native.cpp + nanoFramework_hardware_esp32_native_Hardware_Esp32_sleep.cpp + nanoFramework_hardware_esp32_native_Hardware_Esp32_Logging.cpp + nanoFramework_hardware_esp32_native_Hardware_Esp32_HighResTimer.cpp + nanoFramework_hardware_esp32_native_Hardware_Esp32_Configuration.cpp +) + +foreach(SRC_FILE ${nanoFramework.Hardware.Esp32_SRCS}) + set(nanoFramework.Hardware.Esp32_SRC_FILE SRC_FILE-NOTFOUND) + find_file(nanoFramework.Hardware.Esp32_SRC_FILE ${SRC_FILE} + PATHS + ${BASE_PATH_FOR_THIS_MODULE} + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${nanoFramework.Hardware.Esp32_SRC_FILE}") # debug helper + list(APPEND nanoFramework.Hardware.Esp32_SOURCES ${nanoFramework.Hardware.Esp32_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(nanoFramework.Hardware.Esp32 DEFAULT_MSG nanoFramework.Hardware.Esp32_INCLUDE_DIRS nanoFramework.Hardware.Esp32_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindnanoFramework.Hardware.Stm32.cmake b/source/native/nf-interpreter/CMake/Modules/FindnanoFramework.Hardware.Stm32.cmake new file mode 100644 index 00000000..87dfaeb5 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindnanoFramework.Hardware.Stm32.cmake @@ -0,0 +1,44 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + + +# native code directory +set(BASE_PATH_FOR_THIS_MODULE "${BASE_PATH_FOR_CLASS_LIBRARIES_MODULES}/nanoFramework.Hardware.Stm32") + + +# set include directories +# list(APPEND nanoFramework.Hardware.Stm32_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/CLR/Core") +# list(APPEND nanoFramework.Hardware.Stm32_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/CLR/Include") +# list(APPEND nanoFramework.Hardware.Stm32_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/HAL/Include") +# list(APPEND nanoFramework.Hardware.Stm32_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/PAL/Include") +list(APPEND nanoFramework.Hardware.Stm32_INCLUDE_DIRS "${BASE_PATH_FOR_THIS_MODULE}") + + +# source files +set(nanoFramework.Hardware.Stm32_SRCS + + nf_hardware_stm32_native.cpp + nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_BackupMemory.cpp + nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_Power.cpp + nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_RTC.cpp + nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_Utilities.cpp +) + +foreach(SRC_FILE ${nanoFramework.Hardware.Stm32_SRCS}) + set(nanoFramework.Hardware.Stm32_SRC_FILE SRC_FILE-NOTFOUND) + find_file(nanoFramework.Hardware.Stm32_SRC_FILE ${SRC_FILE} + PATHS + ${BASE_PATH_FOR_THIS_MODULE} + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${nanoFramework.Hardware.Stm32_SRC_FILE}") # debug helper + list(APPEND nanoFramework.Hardware.Stm32_SOURCES ${nanoFramework.Hardware.Stm32_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(nanoFramework.Hardware.Stm32 DEFAULT_MSG nanoFramework.Hardware.Stm32_INCLUDE_DIRS nanoFramework.Hardware.Stm32_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindnanoFramework.Networking.Sntp.cmake b/source/native/nf-interpreter/CMake/Modules/FindnanoFramework.Networking.Sntp.cmake new file mode 100644 index 00000000..75604406 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindnanoFramework.Networking.Sntp.cmake @@ -0,0 +1,38 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + + +# set include directories +list(APPEND CHIBIOS_LWIP_INCLUDE_DIRS ${PROJECT_BINARY_DIR}/ChibiOS_Source/ext/lwip/src/include/lwip) +list(APPEND nanoFramework.Networking.Sntp_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/HAL/Include") +list(APPEND nanoFramework.Networking.Sntp_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/DeviceInterfaces/Networking.Sntp") + + +# source files +set(nanoFramework.Networking.Sntp_SRCS + + # source files of the assembly + nf_networking_sntp_nanoFramework_Networking_Sntp.cpp + nf_networking_sntp.cpp +) + +foreach(SRC_FILE ${nanoFramework.Networking.Sntp_SRCS}) + set(nanoFramework.Networking.Sntp_SRC_FILE SRC_FILE-NOTFOUND) + find_file(nanoFramework.Networking.Sntp_SRC_FILE ${SRC_FILE} + PATHS + + # path for source files of this module + ${PROJECT_SOURCE_DIR}/src/DeviceInterfaces/Networking.Sntp + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${nanoFramework.Networking.Sntp_SRC_FILE}") # debug helper + list(APPEND nanoFramework.Networking.Sntp_SOURCES ${nanoFramework.Networking.Sntp_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(nanoFramework.Networking.Sntp DEFAULT_MSG nanoFramework.Networking.Sntp_INCLUDE_DIRS nanoFramework.Networking.Sntp_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindnanoFramework.ResourceManager.cmake b/source/native/nf-interpreter/CMake/Modules/FindnanoFramework.ResourceManager.cmake new file mode 100644 index 00000000..bb2dbb00 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindnanoFramework.ResourceManager.cmake @@ -0,0 +1,38 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + + +# set include directories +list(APPEND nanoFramework.ResourceManager_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/HAL/Include") +list(APPEND nanoFramework.ResourceManager_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/nanoFramework.ResourceManager") + + +# source files +set(nanoFramework.ResourceManager_SRCS + + # source files of the assembly + nf_system_resourcemanager_nanoFramework_Runtime_Native_ResourceUtility.cpp + nf_system_resourcemanager_System_Resources_ResourceManager.cpp + nf_system_resourcemanager.cpp +) + +foreach(SRC_FILE ${nanoFramework.ResourceManager_SRCS}) + set(nanoFramework.ResourceManager_SRC_FILE SRC_FILE-NOTFOUND) + find_file(nanoFramework.ResourceManager_SRC_FILE ${SRC_FILE} + PATHS + + # path for source files of this module + ${PROJECT_SOURCE_DIR}/src/nanoFramework.ResourceManager + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${nanoFramework.ResourceManager_SRC_FILE}") # debug helper + list(APPEND nanoFramework.ResourceManager_SOURCES ${nanoFramework.ResourceManager_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(nanoFramework.ResourceManager DEFAULT_MSG nanoFramework.ResourceManager_INCLUDE_DIRS nanoFramework.ResourceManager_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindnanoFramework.Runtime.Events.cmake b/source/native/nf-interpreter/CMake/Modules/FindnanoFramework.Runtime.Events.cmake new file mode 100644 index 00000000..d7e9be4f --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindnanoFramework.Runtime.Events.cmake @@ -0,0 +1,55 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# native code directory +set(BASE_PATH_FOR_THIS_MODULE "${PROJECT_SOURCE_DIR}/src/nanoFramework.Runtime.Events") + + +# set include directories +list(APPEND nanoFramework.Runtime.Events_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/CLR/Core") +list(APPEND nanoFramework.Runtime.Events_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/CLR/Include") +list(APPEND nanoFramework.Runtime.Events_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/HAL/Include") +list(APPEND nanoFramework.Runtime.Events_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/PAL/Include") +list(APPEND nanoFramework.Runtime.Events_INCLUDE_DIRS "${BASE_PATH_FOR_THIS_MODULE}") + + +# source files +set(nanoFramework.Runtime.Events_SRCS + + # source files of the assembly + nf_rt_events_native_nanoFramework_Runtime_Events_EventSink.cpp + nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher.cpp + nf_rt_events_native_nanoFramework_Runtime_Events_WeakDelegate.cpp + nf_rt_events_native.cpp + + # source files + AsyncCompletions.cpp + AsyncContinuations.cpp + nanoPAL_Events_functions.cpp + +) + +foreach(SRC_FILE ${nanoFramework.Runtime.Events_SRCS}) + set(nanoFramework.Runtime.Events_SRC_FILE SRC_FILE-NOTFOUND) + find_file(nanoFramework.Runtime.Events_SRC_FILE ${SRC_FILE} + PATHS + + # path for source files of this module + ${BASE_PATH_FOR_THIS_MODULE} + + # path for AsyncProcCall and related code + ${PROJECT_SOURCE_DIR}/src/PAL/AsyncProcCall + ${PROJECT_SOURCE_DIR}/src/PAL/Events + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${nanoFramework.Runtime.Events_SRC_FILE}") # debug helper + list(APPEND nanoFramework.Runtime.Events_SOURCES ${nanoFramework.Runtime.Events_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(nanoFramework.Runtime.Events DEFAULT_MSG nanoFramework.Runtime.Events_INCLUDE_DIRS nanoFramework.Runtime.Events_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/FindnanoFramework.System.Collections.cmake b/source/native/nf-interpreter/CMake/Modules/FindnanoFramework.System.Collections.cmake new file mode 100644 index 00000000..afa84191 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/FindnanoFramework.System.Collections.cmake @@ -0,0 +1,42 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + + +# set include directories +list(APPEND nanoFramework.System.Collections_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/HAL/Include") +list(APPEND nanoFramework.System.Collections_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/nanoFramework.System.Collections") + + +# the following CLR support files are required and added to the build by FindNF_CoreCLR.cmake +# CLR_RT_HeapBlock_Queue.cpp +# CLR_RT_HeapBlock_Stack.cpp + +# source files +set(nanoFramework.System.Collections_SRCS + + # source files of the assembly + nf_system_collections_System_Collections_Queue.cpp + nf_system_collections_System_Collections_Stack.cpp + nf_system_collections.cpp +) + +foreach(SRC_FILE ${nanoFramework.System.Collections_SRCS}) + set(nanoFramework.System.Collections_SRC_FILE SRC_FILE-NOTFOUND) + find_file(nanoFramework.System.Collections_SRC_FILE ${SRC_FILE} + PATHS + + # path for source files of this module + ${PROJECT_SOURCE_DIR}/src/nanoFramework.System.Collections + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${nanoFramework.System.Collections_SRC_FILE}") # debug helper + list(APPEND nanoFramework.System.Collections_SOURCES ${nanoFramework.System.Collections_SRC_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(nanoFramework.System.Collections DEFAULT_MSG nanoFramework.System.Collections_INCLUDE_DIRS nanoFramework.System.Collections_SOURCES) diff --git a/source/native/nf-interpreter/CMake/Modules/JSONParser.cmake b/source/native/nf-interpreter/CMake/Modules/JSONParser.cmake new file mode 100644 index 00000000..b9230e4e --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/JSONParser.cmake @@ -0,0 +1,289 @@ +# source from https://github.com/sbellus/json-cmake + +cmake_minimum_required(VERSION 3.1) + +if (DEFINED JSonParserGuard) + return() +endif() + +set(JSonParserGuard yes) + +macro(sbeParseJson prefix jsonString) + cmake_policy(PUSH) + + set(json_string "${${jsonString}}") + string(LENGTH "${json_string}" json_jsonLen) + set(json_index 0) + set(json_AllVariables ${prefix}) + set(json_ArrayNestingLevel 0) + set(json_MaxArrayNestingLevel 0) + + _sbeParse(${prefix}) + + unset(json_index) + unset(json_AllVariables) + unset(json_jsonLen) + unset(json_string) + unset(json_value) + unset(json_inValue) + unset(json_name) + unset(json_inName) + unset(json_newPrefix) + unset(json_reservedWord) + unset(json_arrayIndex) + unset(json_char) + unset(json_end) + unset(json_ArrayNestingLevel) + foreach(json_nestingLevel RANGE ${json_MaxArrayNestingLevel}) + unset(json_${json_nestingLevel}_arrayIndex) + endforeach() + unset(json_nestingLevel) + unset(json_MaxArrayNestingLevel) + + cmake_policy(POP) +endmacro() + +macro(sbeClearJson prefix) + foreach(json_var ${${prefix}}) + unset(${json_var}) + endforeach() + + unset(${prefix}) + unset(json_var) +endmacro() + +macro(sbePrintJson prefix) + foreach(json_var ${${prefix}}) + message("${json_var} = ${${json_var}}") + endforeach() +endmacro() + +macro(_sbeParse prefix) + + while(${json_index} LESS ${json_jsonLen}) + string(SUBSTRING "${json_string}" ${json_index} 1 json_char) + + if("\"" STREQUAL "${json_char}") + _sbeParseNameValue(${prefix}) + elseif("{" STREQUAL "${json_char}") + _sbeMoveToNextNonEmptyCharacter() + _sbeParseObject(${prefix}) + elseif("[" STREQUAL "${json_char}") + _sbeMoveToNextNonEmptyCharacter() + _sbeParseArray(${prefix}) + endif() + + if(${json_index} LESS ${json_jsonLen}) + string(SUBSTRING "${json_string}" ${json_index} 1 json_char) + else() + break() + endif() + + if ("}" STREQUAL "${json_char}" OR "]" STREQUAL "${json_char}") + break() + endif() + + _sbeMoveToNextNonEmptyCharacter() + endwhile() +endmacro() + +macro(_sbeParseNameValue prefix) + set(json_name "") + set(json_inName no) + + while(${json_index} LESS ${json_jsonLen}) + string(SUBSTRING "${json_string}" ${json_index} 1 json_char) + + # check if name ends + if("\"" STREQUAL "${json_char}" AND json_inName) + set(json_inName no) + _sbeMoveToNextNonEmptyCharacter() + if(NOT ${json_index} LESS ${json_jsonLen}) + break() + endif() + string(SUBSTRING "${json_string}" ${json_index} 1 json_char) + set(json_newPrefix ${prefix}.${json_name}) + set(json_name "") + + if(":" STREQUAL "${json_char}") + _sbeMoveToNextNonEmptyCharacter() + if(NOT ${json_index} LESS ${json_jsonLen}) + break() + endif() + string(SUBSTRING "${json_string}" ${json_index} 1 json_char) + + if("\"" STREQUAL "${json_char}") + _sbeParseValue(${json_newPrefix}) + break() + elseif("{" STREQUAL "${json_char}") + _sbeMoveToNextNonEmptyCharacter() + _sbeParseObject(${json_newPrefix}) + break() + elseif("[" STREQUAL "${json_char}") + _sbeMoveToNextNonEmptyCharacter() + _sbeParseArray(${json_newPrefix}) + break() + else() + # reserved word starts + _sbeParseReservedWord(${json_newPrefix}) + break() + endif() + else() + # name without value + list(APPEND ${json_AllVariables} ${json_newPrefix}) + set(${json_newPrefix} "") + break() + endif() + endif() + + if(json_inName) + # remove escapes + if("\\" STREQUAL "${json_char}") + math(EXPR json_index "${json_index} + 1") + if(NOT ${json_index} LESS ${json_jsonLen}) + break() + endif() + string(SUBSTRING "${json_string}" ${json_index} 1 json_char) + endif() + + set(json_name "${json_name}${json_char}") + endif() + + # check if name starts + if("\"" STREQUAL "${json_char}" AND NOT json_inName) + set(json_inName yes) + endif() + + _sbeMoveToNextNonEmptyCharacter() + endwhile() +endmacro() + +macro(_sbeParseReservedWord prefix) + set(json_reservedWord "") + set(json_end no) + while(${json_index} LESS ${json_jsonLen} AND NOT json_end) + string(SUBSTRING "${json_string}" ${json_index} 1 json_char) + + if("," STREQUAL "${json_char}" OR "}" STREQUAL "${json_char}" OR "]" STREQUAL "${json_char}") + set(json_end yes) + else() + set(json_reservedWord "${json_reservedWord}${json_char}") + math(EXPR json_index "${json_index} + 1") + endif() + endwhile() + + list(APPEND ${json_AllVariables} ${prefix}) + string(STRIP "${json_reservedWord}" json_reservedWord) + set(${prefix} ${json_reservedWord}) +endmacro() + +macro(_sbeParseValue prefix) + cmake_policy(SET CMP0054 NEW) # turn off implicit expansions in if statement + + set(json_value "") + set(json_inValue no) + + while(${json_index} LESS ${json_jsonLen}) + string(SUBSTRING "${json_string}" ${json_index} 1 json_char) + + # check if json_value ends, it is ended by " + if("\"" STREQUAL "${json_char}" AND json_inValue) + set(json_inValue no) + + set(${prefix} ${json_value}) + list(APPEND ${json_AllVariables} ${prefix}) + _sbeMoveToNextNonEmptyCharacter() + break() + endif() + + if(json_inValue) + # if " is escaped consume + if("\\" STREQUAL "${json_char}") + math(EXPR json_index "${json_index} + 1") + if(NOT ${json_index} LESS ${json_jsonLen}) + break() + endif() + string(SUBSTRING "${json_string}" ${json_index} 1 json_char) + if(NOT "\"" STREQUAL "${json_char}") + # if it is not " then copy also escape character + set(json_char "\\${json_char}") + endif() + endif() + + _sbeAddEscapedCharacter("${json_char}") + endif() + + # check if value starts + if("\"" STREQUAL "${json_char}" AND NOT json_inValue) + set(json_inValue yes) + endif() + + math(EXPR json_index "${json_index} + 1") + endwhile() +endmacro() + +macro(_sbeAddEscapedCharacter char) + string(CONCAT json_value "${json_value}" "${char}") +endmacro() + +macro(_sbeParseObject prefix) + _sbeParse(${prefix}) + _sbeMoveToNextNonEmptyCharacter() +endmacro() + +macro(_sbeParseArray prefix) + math(EXPR json_ArrayNestingLevel "${json_ArrayNestingLevel} + 1") + set(json_${json_ArrayNestingLevel}_arrayIndex 0) + + set(${prefix} "") + list(APPEND ${json_AllVariables} ${prefix}) + + while(${json_index} LESS ${json_jsonLen}) + string(SUBSTRING "${json_string}" ${json_index} 1 json_char) + + if("\"" STREQUAL "${json_char}") + # simple value + list(APPEND ${prefix} ${json_${json_ArrayNestingLevel}_arrayIndex}) + _sbeParseValue(${prefix}_${json_${json_ArrayNestingLevel}_arrayIndex}) + elseif("{" STREQUAL "${json_char}") + # object + _sbeMoveToNextNonEmptyCharacter() + list(APPEND ${prefix} ${json_${json_ArrayNestingLevel}_arrayIndex}) + _sbeParseObject(${prefix}_${json_${json_ArrayNestingLevel}_arrayIndex}) + else() + list(APPEND ${prefix} ${json_${json_ArrayNestingLevel}_arrayIndex}) + _sbeParseReservedWord(${prefix}_${json_${json_ArrayNestingLevel}_arrayIndex}) + endif() + + if(NOT ${json_index} LESS ${json_jsonLen}) + break() + endif() + + string(SUBSTRING "${json_string}" ${json_index} 1 json_char) + + if("]" STREQUAL "${json_char}") + _sbeMoveToNextNonEmptyCharacter() + break() + elseif("," STREQUAL "${json_char}") + math(EXPR json_${json_ArrayNestingLevel}_arrayIndex "${json_${json_ArrayNestingLevel}_arrayIndex} + 1") + endif() + + _sbeMoveToNextNonEmptyCharacter() + endwhile() + + if(${json_MaxArrayNestingLevel} LESS ${json_ArrayNestingLevel}) + set(json_MaxArrayNestingLevel ${json_ArrayNestingLevel}) + endif() + math(EXPR json_ArrayNestingLevel "${json_ArrayNestingLevel} - 1") +endmacro() + +macro(_sbeMoveToNextNonEmptyCharacter) + math(EXPR json_index "${json_index} + 1") + if(${json_index} LESS ${json_jsonLen}) + string(SUBSTRING "${json_string}" ${json_index} 1 json_char) + while(${json_char} MATCHES "[ \t\n\r]" AND ${json_index} LESS ${json_jsonLen}) + math(EXPR json_index "${json_index} + 1") + string(SUBSTRING "${json_string}" ${json_index} 1 json_char) + endwhile() + endif() +endmacro() diff --git a/source/native/nf-interpreter/CMake/Modules/MBED_STM32F0_GCC_options.cmake b/source/native/nf-interpreter/CMake/Modules/MBED_STM32F0_GCC_options.cmake new file mode 100644 index 00000000..b7c46de5 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/MBED_STM32F0_GCC_options.cmake @@ -0,0 +1,16 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +################################################################# +# WHEN ADDING A NEW TARGET add the appropriate GCC options below +################################################################# + +set(CMAKE_C_FLAGS "-mthumb -mcpu=cortex-m0 -fno-builtin -std=c11 -g -Wall -ffunction-sections -fdata-sections -fomit-frame-pointer -mlong-calls -mabi=aapcs -fno-exceptions -fno-unroll-loops -ftree-vectorize -specs=nano.specs" CACHE INTERNAL "c compiler flags") +set(CMAKE_CXX_FLAGS "-mthumb -mcpu=cortex-m0 -std=c++11 -ffunction-sections -fdata-sections -fomit-frame-pointer -mlong-calls -mabi=aapcs -fno-exceptions -fno-unroll-loops -ftree-vectorize -specs=nano.specs" CACHE INTERNAL "cxx compiler flags") +set(CMAKE_ASM_FLAGS "-c -mthumb -mcpu=cortex-m0 -g -Wa,--no-warn -x assembler-with-cpp " CACHE INTERNAL "asm compiler flags") + +set(CMAKE_EXE_LINKER_FLAGS "-mthumb -mcpu=cortex-m0 -static -mabi=aapcs -Wl,-gc-sections" CACHE INTERNAL "executable linker flags") +set(CMAKE_MODULE_LINKER_FLAGS "-mthumb -mcpu=cortex-m0 -specs=nano.specs " CACHE INTERNAL "module linker flags") +set(CMAKE_SHARED_LINKER_FLAGS "-mthumb -mcpu=cortex-m0 -specs=nano.specs " CACHE INTERNAL "shared linker flags") diff --git a/source/native/nf-interpreter/CMake/Modules/MBED_STM32F0_sources.cmake b/source/native/nf-interpreter/CMake/Modules/MBED_STM32F0_sources.cmake new file mode 100644 index 00000000..4eb322d8 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/MBED_STM32F0_sources.cmake @@ -0,0 +1,134 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +########################################################################### +# WHEN ADDING A NEW SERIES add the include to the vendor source code below +########################################################################### +include(MBED_STM_sources) + +####################################################################################### +# WHEN ADDING A NEW TARGET add the source code file for the series\device folder below +####################################################################################### + +# sources in series\device folder +set(MBED_VENDOR_SERIES_DEVICE_SRCS + stm32f0xx_hal.c + stm32f0xx_hal_adc.c + stm32f0xx_hal_adc_ex.c + stm32f0xx_hal_can.c + stm32f0xx_hal_cec.c + stm32f0xx_hal_comp.c + stm32f0xx_hal_cortex.c + stm32f0xx_hal_crc.c + stm32f0xx_hal_crc_ex.c + stm32f0xx_hal_dac.c + stm32f0xx_hal_dac_ex.c + stm32f0xx_hal_dma.c + stm32f0xx_hal_flash.c + stm32f0xx_hal_flash_ex.c + stm32f0xx_hal_gpio.c + stm32f0xx_hal_i2c.c + stm32f0xx_hal_i2c_ex.c + stm32f0xx_hal_i2s.c + stm32f0xx_hal_irda.c + stm32f0xx_hal_iwdg.c + stm32f0xx_hal_pcd.c + stm32f0xx_hal_pcd_ex.c + stm32f0xx_hal_pwr.c + stm32f0xx_hal_pwr_ex.c + stm32f0xx_hal_rcc.c + stm32f0xx_hal_rcc_ex.c + stm32f0xx_hal_rtc.c + stm32f0xx_hal_rtc_ex.c + stm32f0xx_hal_smartcard.c + stm32f0xx_hal_smartcard_ex.c + stm32f0xx_hal_smbus.c + stm32f0xx_hal_spi.c + stm32f0xx_hal_spi_ex.c + stm32f0xx_hal_tim.c + stm32f0xx_hal_tim_ex.c + stm32f0xx_hal_tsc.c + stm32f0xx_hal_uart.c + stm32f0xx_hal_uart_ex.c + stm32f0xx_hal_usart.c + stm32f0xx_hal_wwdg.c +) +foreach(SRC_FILE ${MBED_VENDOR_SERIES_DEVICE_SRCS}) + set(MBEDOS_SRC_FILE SRC_FILE-NOTFOUND) + find_file(MBEDOS_SRC_FILE ${SRC_FILE} + PATHS + ${PROJECT_BINARY_DIR}/mBedOS_Source/targets/TARGET_${MBED_TARGET_VENDOR}/TARGET_${MBED_TARGET_SERIES}/device + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${MBEDOS_SRC_FILE}") # debug helper + list(APPEND MBEDOS_SOURCES ${MBEDOS_SRC_FILE}) +endforeach() + +########################################################################## +# WHEN ADDING A NEW TARGET add the source code file for the series below +########################################################################## + +set(MBED_VENDOR_SERIES_AND_TARGET_SRCS + analogin_api.c + analogout_api.c + can_api.c + gpio_api.c + gpio_irq_api.c + lp_ticker.c + mbed_overrides.c + pinmap.c + port_api.c + pwmout_api.c + rtc_api.c + serial_api.c + sleep.c + spi_api.c + + PeripheralPins.c + cmsis_nvic.c + system_stm32f0xx.c +) +foreach(SRC_FILE ${MBED_VENDOR_SERIES_AND_TARGET_SRCS}) + set(MBEDOS_SRC_FILE SRC_FILE-NOTFOUND) + find_file(MBEDOS_SRC_FILE ${SRC_FILE} + PATHS + ${PROJECT_BINARY_DIR}/mBedOS_Source/targets/TARGET_${MBED_TARGET_VENDOR}/TARGET_${MBED_TARGET_SERIES} + ${PROJECT_BINARY_DIR}/mBedOS_Source/targets/TARGET_${MBED_TARGET_VENDOR}/TARGET_${MBED_TARGET_SERIES}/TARGET_${MBED_TARGET} + ${PROJECT_BINARY_DIR}/mBedOS_Source/targets/TARGET_${MBED_TARGET_VENDOR}/TARGET_${MBED_TARGET_SERIES}/TARGET_${MBED_TARGET}/device + ${PROJECT_BINARY_DIR}/mBedOS_Source/targets/TARGET_${MBED_TARGET_VENDOR}/TARGET_${MBED_TARGET_SERIES}/TARGET_${MBED_TARGET}/device/TOOLCHAIN_GCC_ARM + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${MBEDOS_SRC_FILE}") # debug helper + list(APPEND MBEDOS_SOURCES ${MBEDOS_SRC_FILE}) +endforeach() + +####################################################################################################################################### +# WHEN ADDING A NEW TARGET add the respective if clause below along with the startup file and the linker file name (without extension) +####################################################################################################################################### + +# startup file +if(${MBED_TARGET} STREQUAL "NUCLEO_F091RC") + list(APPEND MBEDOS_SOURCES ${PROJECT_BINARY_DIR}/mBedOS_Source/targets/TARGET_${MBED_TARGET_VENDOR}/TARGET_${MBED_TARGET_SERIES}/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_GCC_ARM/startup_stm32f091xc.S) + set(LINKER_FILE "STM32F091XC") +endif() + +####################################################################################################################################### + + +################################################################ +# WHEN ADDING A NEW TARGET check if the linker file below works +################################################################ + +function(MBED_SET_LINKER_OPTIONS TARGET) + + get_target_property(TARGET_LD_FLAGS ${TARGET} LINK_FLAGS) + if(TARGET_LD_FLAGS) + set(TARGET_LD_FLAGS "-T${PROJECT_BINARY_DIR}/mBedOS_Source/targets/TARGET_${MBED_TARGET_VENDOR}/TARGET_${MBED_TARGET_SERIES}/TARGET_${MBED_TARGET}/device/TOOLCHAIN_GCC_ARM/${LINKER_FILE}.LD ${TARGET_LD_FLAGS}") + else() + set(TARGET_LD_FLAGS "-T${PROJECT_BINARY_DIR}/mBedOS_Source/targets/TARGET_${MBED_TARGET_VENDOR}/TARGET_${MBED_TARGET_SERIES}/TARGET_${MBED_TARGET}/device/TOOLCHAIN_GCC_ARM/${LINKER_FILE}.LD") + endif() + set_target_properties(${TARGET} PROPERTIES LINK_FLAGS ${TARGET_LD_FLAGS}) + +endfunction() diff --git a/source/native/nf-interpreter/CMake/Modules/MBED_STM_sources.cmake b/source/native/nf-interpreter/CMake/Modules/MBED_STM_sources.cmake new file mode 100644 index 00000000..5116e037 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/MBED_STM_sources.cmake @@ -0,0 +1,35 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +############################################################################ +# WHEN ADDING A NEW VENDOR add the source code from the vendor folder below +############################################################################ + +# source files common for all STM targets +set(MBED_VENDOR_SRCS + hal_tick_16b.c + hal_tick_32b.c + i2c_api.c + stm_spi_api.c + trng_api.c + us_ticker_16b.c + us_ticker_32b.c +) +foreach(SRC_FILE ${MBED_VENDOR_SRCS}) + set(MBEDOS_SRC_FILE SRC_FILE-NOTFOUND) + find_file(MBEDOS_SRC_FILE ${SRC_FILE} + PATHS + ${PROJECT_BINARY_DIR}/mBedOS_Source/targets/TARGET_${MBED_TARGET_VENDOR} + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${MBEDOS_SRC_FILE}") # debug helper + list(APPEND MBEDOS_SOURCES ${MBEDOS_SRC_FILE}) +endforeach() + +# HAL_CMx file +list(APPEND MBEDOS_SOURCES ${PROJECT_BINARY_DIR}/mBedOS_Source/rtos/rtx/TARGET_CORTEX_M/TARGET_${MBED_TARGET_CORE_SHORT}/TOOLCHAIN_GCC/HAL_C${MBED_TARGET_CORE_SHORT}.S) + +# SVC_Table file +list(APPEND MBEDOS_SOURCES ${PROJECT_BINARY_DIR}/mBedOS_Source/rtos/rtx/TARGET_CORTEX_M/TARGET_${MBED_TARGET_CORE_SHORT}/TOOLCHAIN_GCC/SVC_Table.S) diff --git a/source/native/nf-interpreter/CMake/Modules/NF_NativeAssemblies.cmake b/source/native/nf-interpreter/CMake/Modules/NF_NativeAssemblies.cmake new file mode 100644 index 00000000..35387d73 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/NF_NativeAssemblies.cmake @@ -0,0 +1,326 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +############################################################################################ +# WHEN ADDING A NEW API add the name that corresponds to the CMake option here +# e.g.: for namespace Windows.Devices.Gpio, the CMake option is 'API_Windows.Devices.Gpio' +# and the namespace designation is 'Windows.Devices.Gpio' +########################################################################################### + +option(API_nanoFramework.Devices.Can "option for nanoFramework.Devices.Can") +option(API_nanoFramework.Devices.OneWire "option for nanoFramework.Devices.OneWire") +option(API_nanoFramework.Networking.Sntp "option for nanoFramework.Networking.Sntp") +option(API_nanoFramework.Runtime.Events "option for nanoFramework.Runtime.Events API") +option(API_nanoFramework.ResourceManager "option for nanoFramework.ResourceManager") +option(API_nanoFramework.System.Collections "option for nanoFramework.System.Collections") +option(API_System.Math "option for System.Math") +option(API_System.Net "option for System.Net") +option(API_Windows.Devices.Adc "option for Windows.Devices.Adc API") +option(API_System.Devices.Dac "option for System.Devices.Dac API") +option(API_Windows.Devices.Gpio "option for Windows.Devices.Gpio API") +option(API_Windows.Devices.I2c "option for Windows.Devices.I2c API") +option(API_Windows.Devices.Pwm "option for Windows.Devices.Pwm API") +option(API_Windows.Devices.SerialCommunication "option for Windows.Devices.SerialCommunication API") +option(API_Windows.Devices.Spi "option for Windows.Devices.Spi API") +option(API_Windows.Networking.Sockets "option for Windows.Networking.Sockets") +option(API_Windows.Storage "option for Windows.Storage") + + +# Esp32 only +option(API_Hardware.Esp32 "option for Hardware.Esp32") + + +# Stm32 only +option(API_Hardware.Stm32 "option for Hardware.Stm32") + + +################################################################# +# macro to perform individual settings to add an API to the build +macro(PerformSettingsForApiEntry apiNamespace) + + # namespace with '_' replacing '.' + string(REPLACE "." "_" apiNamespaceWithoutDots "${apiNamespace}") + + # list this option + list(APPEND apiListing "${apiNamespace}") + + # append to list of declaration for Interop Assemblies table + list(APPEND CLR_RT_NativeAssemblyDataList "extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_${apiNamespaceWithoutDots};") + + # append to list of entries for Interop Assemblies table + list(APPEND CLR_RT_NativeAssemblyDataTableEntriesList "&g_CLR_AssemblyNative_${apiNamespaceWithoutDots},") + + # find the module + find_package(${apiNamespace} REQUIRED) + + # append include directories to list with includes for all the APIs + list(APPEND TARGET_NANO_APIS_INCLUDES "${${apiNamespace}_INCLUDE_DIRS}") + list(REMOVE_DUPLICATES TARGET_NANO_APIS_INCLUDES) + + # append source files to list wiht source files for all the APIs + list(APPEND TARGET_NANO_APIS_SOURCES "${${apiNamespace}_SOURCES}") + list(REMOVE_DUPLICATES TARGET_NANO_APIS_SOURCES) + +endmacro() +################################################################# + + +############################################################################################ +# WHEN ADDING A NEW API add the corresponding block below +# required changes: +# 1. change the 'IF' to match the CMake option +# 2. change the call to PerformSettingsForApiEntry() macro with the API name (doted naming) +############################################################################################ + +macro(ParseNativeAssemblies) + + # Hardware.Esp32 + if(API_Hardware.Esp32) + ##### API name here (doted name) + PerformSettingsForApiEntry("nanoFramework.Hardware.Esp32") + endif() + + # Hardware.Stm32 + if(API_Hardware.Stm32) + ##### API name here (doted name) + PerformSettingsForApiEntry("nanoFramework.Hardware.Stm32") + endif() + + # nanoFramework.Devices.Can + if(API_nanoFramework.Devices.Can) + ##### API name here (doted name) + PerformSettingsForApiEntry("nanoFramework.Devices.Can") + endif() + + # nanoFramework.Devices.OneWire + if(API_nanoFramework.Devices.OneWire) + ##### API name here (doted name) + PerformSettingsForApiEntry("nanoFramework.Devices.OneWire") + endif() + + # nanoFramework.Networking.Sntp + if(API_nanoFramework.Networking.Sntp) + ##### API name here (doted name) + PerformSettingsForApiEntry("nanoFramework.Networking.Sntp") + endif() + + # nanoFramework.ResourceManager + if(API_nanoFramework.ResourceManager) + ##### API name here (doted name) + PerformSettingsForApiEntry("nanoFramework.ResourceManager") + endif() + + # nanoFramework.System.Collections + if(API_nanoFramework.System.Collections) + ##### API name here (doted name) + PerformSettingsForApiEntry("nanoFramework.System.Collections") + endif() + + # nanoFramework.Runtime.Events + if(API_nanoFramework.Runtime.Events) + ##### API name here (doted name) + PerformSettingsForApiEntry("nanoFramework.Runtime.Events") + + # this one is special because it requires also another assembly for events that is internal (doens't have a managed end) + + # append to list of declaration for Interop Assemblies table + list(APPEND CLR_RT_NativeAssemblyDataList "extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Runtime_Events_EventSink_DriverProcs;") + # append to list of entries for Interop Assemblies table + list(APPEND CLR_RT_NativeAssemblyDataTableEntriesList "&g_CLR_AssemblyNative_nanoFramework_Runtime_Events_EventSink_DriverProcs,") + + endif() + + # System.Math + if(API_System.Math) + ##### API name here (doted name) + PerformSettingsForApiEntry("System.Math") + endif() + + # System.Net + if(API_System.Net) + ##### API name here (doted name) + PerformSettingsForApiEntry("System.Net") + endif() + + # Windows.Devices.Adc + if(API_Windows.Devices.Adc) + ##### API name here (doted name) + PerformSettingsForApiEntry("Windows.Devices.Adc") + endif() + + # System.Devices.Dac + if(API_System.Devices.Dac) + ##### API name here (doted name) + PerformSettingsForApiEntry("System.Devices.Dac") + endif() + + # Windows.Devices.Gpio + if(API_Windows.Devices.Gpio) + ##### API name here (doted name) + PerformSettingsForApiEntry("Windows.Devices.Gpio") + endif() + + # Windows.Devices.I2c + if(API_Windows.Devices.I2c) + ##### API name here (doted name) + PerformSettingsForApiEntry("Windows.Devices.I2c") + endif() + + # Windows.Devices.Pwm + if(API_Windows.Devices.Pwm) + ##### API name here (doted name) + PerformSettingsForApiEntry("Windows.Devices.Pwm") + endif() + + # Windows.Devices.SerialCommunication + if(API_Windows.Devices.SerialCommunication) + ##### API name here (doted name) + PerformSettingsForApiEntry("Windows.Devices.SerialCommunication") + endif() + + # Windows.Devices.Spi + if(API_Windows.Devices.Spi) + ##### API name here (doted name) + PerformSettingsForApiEntry("Windows.Devices.Spi") + endif() + + # Windows.Networking.Sockets + if(API_Windows.Networking.Sockets) + ##### API name here (doted name) + PerformSettingsForApiEntry("Windows.Networking.Sockets") + endif() + + # Windows.Devices.Wifi + if(API_Windows.Devices.Wifi) + ##### API name here (doted name) + PerformSettingsForApiEntry("Windows.Devices.Wifi") + endif() + + # Windows.Storage + if(API_Windows.Storage) + ##### API name here (doted name) + PerformSettingsForApiEntry("Windows.Storage") + endif() + + # Interop assemblies + ParseInteropAssemblies() + + + # parse the declarations to have new lines and ';' + string(REPLACE ";;" ";\n" CLR_RT_NativeAssemblyDataDeclarations "${CLR_RT_NativeAssemblyDataList}") + # parse the list to have new lines, ',' and identation + string(REPLACE ";" "\n " CLR_RT_NativeAssemblyDataTableEntries "${CLR_RT_NativeAssemblyDataTableEntriesList}") + + + # configure code file with Interop Assemblies table and... + configure_file("${PROJECT_SOURCE_DIR}/InteropAssemblies/CLR_RT_InteropAssembliesTable.cpp.in" + "${CMAKE_CURRENT_BINARY_DIR}/CLR_RT_InteropAssembliesTable.cpp" @ONLY) + # ... now add Interop Assemblies table to ChibiOS nanoCLR sources list + list(APPEND TARGET_NANO_APIS_SOURCES "${CMAKE_CURRENT_BINARY_DIR}/CLR_RT_InteropAssembliesTable.cpp") + + # make the vars global + set(TARGET_NANO_APIS_INCLUDES ${TARGET_NANO_APIS_INCLUDES} CACHE INTERNAL "make global") + set(TARGET_NANO_APIS_SOURCES ${TARGET_NANO_APIS_SOURCES} CACHE INTERNAL "make global") + + + # output the list of APIs included + list(LENGTH apiListing apiListingLenght) + + if(apiListingLenght GREATER 0) + + # APIs included + message(STATUS "") + message(STATUS " *** APIs included ***") + message(STATUS "") + + foreach(entry ${apiListing}) + message(STATUS " ${entry}") + endforeach(entry ${}) + + message(STATUS "") + message(STATUS " *** end of APIs ***") + message(STATUS "") + + else() + # no APIs were included + message(STATUS " *** NO APIs included ***") + endif() + +endmacro() + +############################################################################## +# macro to perform individual settings to add an Interop assembly to the build +macro(PerformSettingsForInteropEntry interopAssemblyName) + + # namespace with '_' replacing '.' + string(REPLACE "." "_" interopAssemblyNameWithoutDots "${interopAssemblyName}") + + # list this option + list(APPEND interopAssemblyList "${interopAssemblyName}") + + # append to list of declaration for Interop Assemblies table + list(APPEND CLR_RT_NativeAssemblyDataList "extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_${interopAssemblyNameWithoutDots};") + + # append to list of entries for Interop Assemblies table + list(APPEND CLR_RT_NativeAssemblyDataTableEntriesList "&g_CLR_AssemblyNative_${interopAssemblyNameWithoutDots},") + + # find the module + find_package("INTEROP-${interopAssemblyName}" REQUIRED) + + ######### + # because Interop assemblies are considered and treated as like any CLR assembly we add them to the same lists + ######### + + # append include directories to list with includes for all the APIs + list(APPEND TARGET_NANO_APIS_INCLUDES "${${interopAssemblyName}_INCLUDE_DIRS}") + list(REMOVE_DUPLICATES TARGET_NANO_APIS_INCLUDES) + + # append source files to list wiht source files for all the APIs + list(APPEND TARGET_NANO_APIS_SOURCES "${${interopAssemblyName}_SOURCES}") + list(REMOVE_DUPLICATES TARGET_NANO_APIS_SOURCES) + +endmacro() + +################################################################# +# macro that adds the requested Interop assemblies to the build +# requiremens to add an Interop assemble: +# 1) add it's namespace to the NF_INTEROP_ASSEMBLIES CMake options +# 2) have the corresponding CMake module in the Modules folder (mind the correct naming) +macro(ParseInteropAssemblies) + + # check if there are any Interop assemblies to be added + if(NF_INTEROP_ASSEMBLIES) + + # loop through each Interop assembly and add it to the build + foreach(assembly ${NF_INTEROP_ASSEMBLIES}) + PerformSettingsForInteropEntry(${assembly}) + endforeach() + + endif() + + # output the list of Interop assemblies included + list(LENGTH interopAssemblyList interopAssemblyListLenght) + + if(interopAssemblyListLenght GREATER 0) + + # APIs included + message(STATUS "") + message(STATUS " *** Interop assemblies included ***") + message(STATUS "") + + foreach(entry ${interopAssemblyList}) + message(STATUS " ${entry}") + endforeach(entry ${}) + + message(STATUS "") + message(STATUS " *** end of Interop assemblies ***") + message(STATUS "") + + else() + # no Interop assemblies were included + message(STATUS " *** NO Interop assemblies included ***") + endif() + +endmacro() diff --git a/source/native/nf-interpreter/CMake/Modules/STM32_CubePackage.cmake b/source/native/nf-interpreter/CMake/Modules/STM32_CubePackage.cmake new file mode 100644 index 00000000..8285b9e7 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/STM32_CubePackage.cmake @@ -0,0 +1,103 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# include the STM32 Cube package for the appropriate series, if requested + +# check if cube package source was specified or if it's empty (default is empty) +macro(ProcessSTM32CubePackage) + + # process target series, which is in the format "STM32F4xx" + string(REPLACE "STM32" "" TARGET_SERIES_SHORT_1 "${TARGET_SERIES}") + string(REPLACE "xx" "" TARGET_SERIES_SHORT "${TARGET_SERIES_SHORT_1}") + + set(NO_STM32_CUBE_PACKAGE_SOURCE TRUE) + if(NO_STM32_CUBE_PACKAGE_SOURCE) + if(NOT "${STM32_CUBE_PACKAGE_SOURCE}" STREQUAL "") + set(NO_STM32_CUBE_PACKAGE_SOURCE FALSE) + endif() + endif() + + if(NO_STM32_CUBE_PACKAGE_SOURCE) + # no STM Cube package source specified, download it from nanoFramework fork + + # check for Git (needed here for advanced warning to user if it's not installed) + find_package(Git) + + # check if Git was found, if not report to user and abort + if(NOT GIT_EXECUTABLE) + message(FATAL_ERROR "error: could not find Git, make sure you have it installed.") + endif() + + message(STATUS "STM32 ${TARGET_SERIES_SHORT} Cube package from GitHub repo") + + # need to setup a separate CMake project to download the code from the GitHub repository + # otherwise it won't be available before the actual build step + configure_file("${PROJECT_SOURCE_DIR}/CMake/STM32.CubePackage.CMakeLists.cmake.in" + "${CMAKE_BINARY_DIR}/STM32${TARGET_SERIES_SHORT}-CubePackage_Download/CMakeLists.txt") + + # setup CMake project for STM32_CubePackage download + execute_process(COMMAND ${CMAKE_COMMAND} -G "${CMAKE_GENERATOR}" . + RESULT_VARIABLE result + WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/STM32${TARGET_SERIES_SHORT}-CubePackage_Download") + + # run build on STM32_CubePackage download CMake project to perform the download + execute_process(COMMAND ${CMAKE_COMMAND} --build . + RESULT_VARIABLE result + WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/STM32${TARGET_SERIES_SHORT}-CubePackage_Download") + + # add STM32_CubePackage as external project + # need to specify nanoframework as the active branch + ExternalProject_Add( + STM32${TARGET_SERIES_SHORT}_CubePackage + PREFIX STM32${TARGET_SERIES_SHORT}_CubePackage + SOURCE_DIR ${CMAKE_BINARY_DIR}/STM32${TARGET_SERIES_SHORT}_CubePackage_Source + GIT_REPOSITORY https://github.com/nanoframework/STM32Cube${TARGET_SERIES_SHORT} + GIT_TAG "nf-build" # target specific branch + GIT_SHALLOW 1 # download only the tip of the branch, not the complete history + TIMEOUT 10 + LOG_DOWNLOAD 1 + # Disable all other steps + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND "" + ) + + # get source dir for STM32_CubePackage CMake project + ExternalProject_Get_Property(STM32${TARGET_SERIES_SHORT}_CubePackage SOURCE_DIR) + + else() + # STM32 Cube package source was specified + + # sanity check is source path exists + if(EXISTS "${STM32_CUBE_PACKAGE_SOURCE}/") + message(STATUS "STM32 Cube package source from: ${STM32_CUBE_PACKAGE_SOURCE}") + + # check if we already have the sources, no need to copy again + if(NOT EXISTS "${CMAKE_BINARY_DIR}/STM32${TARGET_SERIES_SHORT}_CubePackage_Source") + file(COPY "${STM32_CUBE_PACKAGE_SOURCE}/" DESTINATION "${CMAKE_BINARY_DIR}/STM32${TARGET_SERIES_SHORT}_CubePackage_Source") + else() + message(STATUS "Using local cache of STM32 Cube package source from ${STM32_CUBE_PACKAGE_SOURCE}") + endif() + else() + message(FATAL_ERROR "Couldn't find STM32 Cube package source at ${STM32_CUBE_PACKAGE_SOURCE}/") + endif() + + # add STM32_CubePackage as external project + ExternalProject_Add( + STM32${TARGET_SERIES_SHORT}_CubePackage + PREFIX STM32${TARGET_SERIES_SHORT}_CubePackage + SOURCE_DIR ${CMAKE_BINARY_DIR}/STM32${TARGET_SERIES_SHORT}_CubePackage_Source + # Disable all other steps + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND "" + ) + + # get source dir for STM32_CubePackage CMake project + ExternalProject_Get_Property(STM32${TARGET_SERIES_SHORT}_CubePackage SOURCE_DIR) + + endif() + +endmacro() diff --git a/source/native/nf-interpreter/CMake/Modules/TI_SimpleLink_CC32xx_GCC_options.cmake b/source/native/nf-interpreter/CMake/Modules/TI_SimpleLink_CC32xx_GCC_options.cmake new file mode 100644 index 00000000..72b2250a --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/TI_SimpleLink_CC32xx_GCC_options.cmake @@ -0,0 +1,48 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +################################################################# +# WHEN ADDING A NEW SERIES add the appropriate GCC options below +################################################################# + +# need to specify this for assembler +set(CMAKE_ASM_FLAGS " -mthumb -mcpu=cortex-m4 -x assembler-with-cpp" CACHE INTERNAL "asm compiler flags") + +# need to specify linker flags here +# -mfpu=fpv5-sp-d16 +set(CMAKE_EXE_LINKER_FLAGS " -Wl,--gc-sections -Wl,--no-wchar-size-warning -Wl,--print-memory-usage -mcpu=cortex-m4 -march=armv7e-m -mthumb -nostartfiles -std=c99 -mfloat-abi=soft -ffunction-sections -fdata-sections -g -gstrict-dwarf -Wall " CACHE INTERNAL "executable linker flags") + + +function(NF_SET_COMPILER_OPTIONS TARGET) + + # include any extra options coming from any extra args? + target_compile_options(${TARGET} PUBLIC ${ARGN} -march=armv7e-m -mthumb -mcpu=cortex-m4 -mfloat-abi=soft -mabi=aapcs -gstrict-dwarf -nostdlib -Wall -w -static -ffunction-sections -falign-functions=16 -fdata-sections -fno-builtin -fno-common -fsingle-precision-constant -fomit-frame-pointer -mlong-calls -fdollars-in-identifiers -fno-exceptions -fno-unroll-loops -ffast-math -ftree-vectorize -fcheck-new -fno-rtti -fno-use-cxa-atexit -fno-threadsafe-statics) + + # this series has FPU + target_compile_definitions(${TARGET} PUBLIC -DCORTEX_USE_FPU=TRUE) + +endfunction() + + +function(NF_SET_LINKER_OPTIONS TARGET) + + # request specs from newlib nano + set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " --specs=nano.specs ") + + # set extra linker flags + set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " ${ARGN}") + + # set optimization linker flags for RELEASE and MinSizeRel + if(CMAKE_BUILD_TYPE STREQUAL "Release" OR CMAKE_BUILD_TYPE STREQUAL "MinSizeRel") + set_property(TARGET ${TARGET} APPEND_STRING PROPERTY LINK_FLAGS " -flto -fuse-linker-plugin -Os") + endif() + + # set optimization flags + nf_set_optimization_options(${TARGET}) + + # set link map + nf_set_link_map(${TARGET}) + +endfunction() diff --git a/source/native/nf-interpreter/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake b/source/native/nf-interpreter/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake new file mode 100644 index 00000000..12c3df28 --- /dev/null +++ b/source/native/nf-interpreter/CMake/Modules/TI_SimpleLink_CC32xx_sources.cmake @@ -0,0 +1,245 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# includes for SimpleLink CC32xx SDK +list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source") +list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers") +list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/posix/gcc") +list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/boards/CC3220SF_LAUNCHXL") +list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/devices/cc32xx") +list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/devices/cc32xx/driverlib") +list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/net") +list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/bsd") + +# includes for nanoFramework SSL driver +list(APPEND TI_SimpleLink_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/PAL/Com/sockets/ssl") + + +# source files for board drivers +set(BoardDrivers_SRCS + + # board drivers + # NVS.c + # NVSRAM.c + # NVSSPI25X.c + # SD.c + # SDSPI.c + # SDFatFS.c + List.c + RingBuf.c + ADC.c + ADCCC32XX.c + # Camera.c + # CameraCC32XXDMA.c + Capture.c + CaptureCC32XX.c + CryptoCC32XX.c + UDMACC32XX.c + GPIOCC32XX.c + I2C.c + I2CCC32XX.c + I2S.c + PowerCC32XX.c + PowerCC32XX_asm.sm4g + PWM.c + PWMTimerCC32XX.c + SDHostCC32XX.c + SPI.c + SPICC32XXDMA.c + SPICC32XXDMA.c + Timer.c + TimerCC32XX.c + UART.c + UARTCC32XX.c + UARTCC32XXDMA.c + Watchdog.c + WatchdogCC32XX.c +) + +foreach(SRC_FILE ${BoardDrivers_SRCS}) + set(BoardDrivers_SCR_FILE SRC_FILE -NOTFOUND) + find_file(BoardDrivers_SCR_FILE ${SRC_FILE} + PATHS + + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/nvs" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/sd" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/adc" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/camera" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/capture" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/crypto" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/dma" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/gpio" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/i2c" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/i2s" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/power" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/pwm" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/sd" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/spi" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/timer" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/uart" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/watchdog" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/utils" + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${BoardDrivers_SCR_FILE}") # debug helper + list(APPEND TI_SimpleLink_SOURCES ${BoardDrivers_SCR_FILE}) +endforeach() + +# need to specify a language for this assembler source file because its not using a standard extension +set_source_files_properties("${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/power/PowerCC32XX_asm.sm4g" PROPERTIES LANGUAGE ASM) + +# source files for drivers library +set(DriversLibrary_SRCS + + #drivers library + adc.c + aes.c + camera.c + cpu.c + crc.c + des.c + flash.c + gpio.c + hwspinlock.c + i2c.c + interrupt.c + i2s.c + pin.c + prcm.c + sdhost.c + shamd5.c + spi.c + systick.c + timer.c + uart.c + udma.c + utils.c + wdt.c + + # display specific + DisplayUart.c +) + +foreach(SRC_FILE ${DriversLibrary_SRCS}) + set(DriversLibrary_SCR_FILE SRC_FILE -NOTFOUND) + find_file(DriversLibrary_SCR_FILE ${SRC_FILE} + PATHS + + #drivers library + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/devices/cc32xx/driverlib" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/display" + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${DriversLibrary_SCR_FILE}") # debug helper + list(APPEND TI_SimpleLink_SOURCES ${DriversLibrary_SCR_FILE}) +endforeach() + +# source files for SimpleLink +set(SimpleLink_SRCS + + device.c + driver.c + flowcont.c + fs.c + netapp.c + netcfg.c + netutil.c + nonos.c + sl_socket.c + spawn.c + wlan.c + cc_pal.c + eventreg.c + wlanconfig.c + + # eventreg.c + +) + +foreach(SRC_FILE ${SimpleLink_SRCS}) + set(SimpleLink_SCR_FILE SRC_FILE -NOTFOUND) + find_file(SimpleLink_SCR_FILE ${SRC_FILE} + PATHS + + #drivers library + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/net/wifi" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/net/wifi/porting" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/net/wifi/source" + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${SimpleLink_SCR_FILE}") # debug helper + list(APPEND TI_SimpleLink_SOURCES ${SimpleLink_SCR_FILE}) +endforeach() + + +# source files for SimpleLink net Wi-Fi +set(SLNetWiFi_SRCS + + slnetsock.c + slnetutils.c + slnetif.c + + # bsd + netdb.c + socket.c + errnoutil.c + + # drivers + eventreg.c + slnetifwifi.c + + # utils + clock_sync.c +) + +foreach(SRC_FILE ${SLNetWiFi_SRCS}) + set(SLNetWiFi_SCR_FILE SRC_FILE -NOTFOUND) + find_file(SLNetWiFi_SCR_FILE ${SRC_FILE} + PATHS + + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/net" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/net/bsd" + + # drivers + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/net/wifi" + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/drivers/net/wifi/slnetif" + + # utils + "${PROJECT_BINARY_DIR}/SimpleLinkCC32xxSDK_Source/ti/net/utils" + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${SLNetWiFi_SCR_FILE}") # debug helper + list(APPEND TI_SimpleLink_SOURCES ${SLNetWiFi_SCR_FILE}) +endforeach() + + +# source files for nanoFramework SSL driver +set(nanoSsl_SRCS + + ssl.cpp +) + +foreach(SRC_FILE ${nanoSsl_SRCS}) + set(nanoSsl_SCR_FILE SRC_FILE -NOTFOUND) + find_file(nanoSsl_SCR_FILE ${SRC_FILE} + PATHS + + "${PROJECT_SOURCE_DIR}/src/PAL/COM/sockets/ssl" + + CMAKE_FIND_ROOT_PATH_BOTH + ) + # message("${SRC_FILE} >> ${nanoSsl_SCR_FILE}") # debug helper + list(APPEND TI_SimpleLink_SOURCES ${nanoSsl_SCR_FILE}) +endforeach() + + +include(FindPackageHandleStandardArgs) + +FIND_PACKAGE_HANDLE_STANDARD_ARGS(SimpleLinkCC32xxSDK DEFAULT_MSG TI_SimpleLink_INCLUDE_DIRS TI_SimpleLink_SOURCES) diff --git a/source/native/nf-interpreter/CMake/RTXRTOS.CMakeLists.cmake.in b/source/native/nf-interpreter/CMake/RTXRTOS.CMakeLists.cmake.in new file mode 100644 index 00000000..c203606d --- /dev/null +++ b/source/native/nf-interpreter/CMake/RTXRTOS.CMakeLists.cmake.in @@ -0,0 +1,22 @@ +cmake_minimum_required(VERSION 2.8.2) + +project(RTXRTOS-download NONE) + +include(ExternalProject) + +# download RTX RTOS source from official ARM GitHub repo + ExternalProject_Add( + RTXRTOS + PREFIX RTXRTOS + SOURCE_DIR ${CMAKE_BINARY_DIR}/RTXRTOS_Source + GIT_REPOSITORY https://github.com/ARM-software/CMSIS_5 + GIT_TAG master # target master branch + GIT_SHALLOW 1 # download only the tip of the branch, not the complete history + TIMEOUT 10 + LOG_DOWNLOAD 1 + + # Disable all other steps + CONFIGURE_COMMAND "" + BUILD_COMMAND "" + INSTALL_COMMAND "" + ) diff --git a/source/native/nf-interpreter/CMake/SPIFFS.CMakeLists.cmake.in b/source/native/nf-interpreter/CMake/SPIFFS.CMakeLists.cmake.in new file mode 100644 index 00000000..d7f3e5ad --- /dev/null +++ b/source/native/nf-interpreter/CMake/SPIFFS.CMakeLists.cmake.in @@ -0,0 +1,24 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +project(SPIFFS-download NONE) + +include(ExternalProject) + +# download SPIFFS source from nanoFramework GitHub fork +ExternalProject_Add( + SPIFFS + PREFIX SPIFFS + SOURCE_DIR ${CMAKE_BINARY_DIR}/SPIFFS_Source + GIT_REPOSITORY https://github.com/nanoframework/spiffs + GIT_TAG "nf-build" # target nanoFramework modified branch + GIT_SHALLOW 1 # download only the tip of the branch, not the complete history + TIMEOUT 10 + LOG_DOWNLOAD 1 + # Disable all other steps + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND "" +) diff --git a/source/native/nf-interpreter/CMake/STM32.CubePackage.CMakeLists.cmake.in b/source/native/nf-interpreter/CMake/STM32.CubePackage.CMakeLists.cmake.in new file mode 100644 index 00000000..3c99cca9 --- /dev/null +++ b/source/native/nf-interpreter/CMake/STM32.CubePackage.CMakeLists.cmake.in @@ -0,0 +1,24 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +project(STM32-CubePackage-download NONE) + +include(ExternalProject) + +# download STM32 Cube Package source from nanoFramework GitHub fork +ExternalProject_Add( + STM32${TARGET_SERIES_SHORT}_CubePackage + PREFIX STM32${TARGET_SERIES_SHORT}_CubePackage + SOURCE_DIR ${CMAKE_BINARY_DIR}/STM32${TARGET_SERIES_SHORT}_CubePackage_Source + GIT_REPOSITORY https://github.com/nanoframework/STM32Cube${TARGET_SERIES_SHORT} + GIT_TAG "nf-build" # target specific branch + GIT_SHALLOW 1 # download only the tip of the branch, not the complete history + TIMEOUT 10 + LOG_DOWNLOAD 1 + # Disable all other steps + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND "" +) diff --git a/source/native/nf-interpreter/CMake/SimpleLinkCC32xxSdk.CMakeLists.cmake.in b/source/native/nf-interpreter/CMake/SimpleLinkCC32xxSdk.CMakeLists.cmake.in new file mode 100644 index 00000000..8892b9db --- /dev/null +++ b/source/native/nf-interpreter/CMake/SimpleLinkCC32xxSdk.CMakeLists.cmake.in @@ -0,0 +1,25 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +project(SimpleLinkCC32xxSDK-download NONE) + +include(ExternalProject) + +# download SimpleLinkCC32xx SDK from nanoFramework repo +ExternalProject_Add( + SimpleLinkCC32xxSDK + PREFIX SimpleLinkCC32xxSdk + SOURCE_DIR ${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Source + GIT_REPOSITORY https://github.com/nanoframework/SimpleLink_CC32xx_SDK + GIT_TAG ${TI_SL_CC32xx_SDK_TAG} # target specified branch + GIT_SHALLOW 1 # download only the tip of the branch, not the complete history + TIMEOUT 10 + LOG_DOWNLOAD 1 + + # Disable all other steps + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND "" +) diff --git a/source/native/nf-interpreter/CMake/TI_SimpleLink_target_os.h.in b/source/native/nf-interpreter/CMake/TI_SimpleLink_target_os.h.in new file mode 100644 index 00000000..73ec8d87 --- /dev/null +++ b/source/native/nf-interpreter/CMake/TI_SimpleLink_target_os.h.in @@ -0,0 +1,30 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_OS_H_ +#define _TARGET_OS_H_ + +#define VERSION_MAJOR @nanoFramework_VERSION_MAJOR@U +#define VERSION_MINOR @nanoFramework_VERSION_MINOR@U +#define VERSION_BUILD @nanoFramework_VERSION_PATCH@U +#define VERSION_REVISION @nanoFramework_VERSION_TWEAK@U + +#define NANOCLR_LIGHT_MATH @TARGET_LIGHT_MATH@ +#define DP_FLOATINGPOINT @TARGET_DP_FLOATINGPOINT@ + +#define SUPPORT_ANY_BASE_CONVERSION @TARGET_SUPPORT_ANY_BASE_CONVERSION@ + +#define HAS_CONFIG_BLOCK @TARGET_HAS_CONFIG_BLOCK@ + +#define NANOCLR_REFLECTION @TARGET_NANOCLR_REFLECTION@ + +#define NANOCLR_SYSTEM_COLLECTIONS @TARGET_SYSTEM_COLLECTIONS@ + +#endif /* _TARGET_OS_H_ */ diff --git a/source/native/nf-interpreter/CMake/mBedOS.CMakeLists.cmake.in b/source/native/nf-interpreter/CMake/mBedOS.CMakeLists.cmake.in new file mode 100644 index 00000000..2ce4be90 --- /dev/null +++ b/source/native/nf-interpreter/CMake/mBedOS.CMakeLists.cmake.in @@ -0,0 +1,22 @@ +cmake_minimum_required(VERSION 2.8.2) + +project(mBedOS-download NONE) + +include(ExternalProject) + +# download mBed RTOS source from official mBed GitHub repo + ExternalProject_Add( + mBedOS + PREFIX mBedOS + SOURCE_DIR ${CMAKE_BINARY_DIR}/mBedOS_Source + GIT_REPOSITORY https://github.com/ARMmbed/mbed-os/ + GIT_TAG master # target master branch + GIT_SHALLOW 1 # download only the tip of the branch, not the complete history + TIMEOUT 10 + LOG_DOWNLOAD 1 + + # Disable all other steps + CONFIGURE_COMMAND "" + BUILD_COMMAND "" + INSTALL_COMMAND "" + ) diff --git a/source/native/nf-interpreter/CMake/mbedTLS.CMakeLists.cmake.in b/source/native/nf-interpreter/CMake/mbedTLS.CMakeLists.cmake.in new file mode 100644 index 00000000..1be3e498 --- /dev/null +++ b/source/native/nf-interpreter/CMake/mbedTLS.CMakeLists.cmake.in @@ -0,0 +1,24 @@ +# +# Copyright (c) 2018 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +project(mbedTLS-download NONE) + +include(ExternalProject) + +# download mbedTLS source from official GitHub repo +ExternalProject_Add( + mbedTLS + PREFIX mbedTLS + SOURCE_DIR ${CMAKE_BINARY_DIR}/mbedTLS_Source + GIT_REPOSITORY https://github.com/nanoframework/mbedtls + GIT_TAG ${MBEDTLS_GIT_TAG} # target specified branch + GIT_SHALLOW 1 # download only the tip of the branch, not the complete history + TIMEOUT 10 + LOG_DOWNLOAD 1 + # Disable all other steps + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND "" +) diff --git a/source/native/nf-interpreter/CMake/toolchain.ChibiOS.GCC.cmake b/source/native/nf-interpreter/CMake/toolchain.ChibiOS.GCC.cmake new file mode 100644 index 00000000..bee8b68e --- /dev/null +++ b/source/native/nf-interpreter/CMake/toolchain.ChibiOS.GCC.cmake @@ -0,0 +1,180 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +INCLUDE(CMakeForceCompiler) +# if( DEFINED CMAKE_CROSSCOMPILING ) +# # subsequent toolchain loading is not really needed +# return() +# endif() + + +################################################### +# set C and C++ flags for compiler detection tests +################################################### +# IMPORTANT: these flags need to be removed after +# the compiler detection otherwise they'll get +# added to all compiler build calls and +# will colide with the use of nano.specs +################################################### +set(CMAKE_C_FLAGS_INIT "-specs=nosys.specs") +set(CMAKE_CXX_FLAGS_INIT "-specs=nosys.specs") +################################################### + + +# set toolchain directories +set(TOOLCHAIN_BIN_DIR ${TOOLCHAIN_PREFIX}/bin) +set(TOOLCHAIN_INC_DIR ${TOOLCHAIN_PREFIX}/arm-none-eabi/include) +set(TOOLCHAIN_LIB_DIR ${TOOLCHAIN_PREFIX}/arm-none-eabi/lib) + +# the name of the operating system for which CMake is to build +set(CMAKE_SYSTEM_NAME Generic) + +# name of the CPU CMake is building for +set(CMAKE_SYSTEM_PROCESSOR arm) + +# macro to setup compilers +macro(SET_COMPILER_VAR var name) + find_program(CMAKE_${var} arm-none-eabi-${name} HINTS ${TOOLCHAIN_BIN_DIR} DOC "${name} tool") +endmacro() + +# setup C compiler +if(NOT CMAKE_C_COMPILER) + SET_COMPILER_VAR(C_COMPILER gcc) +endif() + +# setup C++ compiler +if(NOT CMAKE_CXX_COMPILER) + SET_COMPILER_VAR(CXX_COMPILER g++) +endif() + +# setup Assembler compiler +SET_COMPILER_VAR(ASM-ATT_COMPILER as) + +# other toolchain configurations +set(CMAKE_OBJCOPY ${TOOLCHAIN_BIN_DIR}/arm-none-eabi-objcopy CACHE INTERNAL "objcopy tool") +set(CMAKE_OBJDUMP ${TOOLCHAIN_BIN_DIR}/arm-none-eabi-objdump CACHE INTERNAL "objdump tool") +set(CMAKE_SIZE ${TOOLCHAIN_BIN_DIR}/arm-none-eabi-size CACHE INTERNAL "size tool") +set(CMAKE_DEBUGER ${TOOLCHAIN_BIN_DIR}/arm-none-eabi-gdb CACHE INTERNAL "debuger") + +# root paths to search on the filesystem for cross-compiling +set(CMAKE_FIND_ROOT_PATH ${TOOLCHAIN_PREFIX}/arm-none-eabi ${EXTRA_FIND_PATH}) +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) + +# set required C and C++ standard for ALL targets +set(CMAKE_C_STANDARD 11 CACHE INTERNAL "C standard for all targets") +set(CMAKE_CXX_STANDARD 11 CACHE INTERNAL "C++ standard for all targets") + +# set all C and C++ extensions to be OFF on ALL targets +# this forces the use of -std=c11 and -std=c++11 instead of -std=gnu11 and -std=gnu++11 +set(CMAKE_C_EXTENSIONS OFF CACHE INTERNAL "C compiler extensions OFF") +set(CMAKE_CXX_EXTENSIONS OFF CACHE INTERNAL "C++ compiler extensions OFF") + + +function(NF_ADD_HEX_BIN_DUMP_TARGETS TARGET) + if(EXECUTABLE_OUTPUT_PATH) + set(FILENAME "${EXECUTABLE_OUTPUT_PATH}/${TARGET}") + else() + set(FILENAME "${TARGET}") + endif() + + #get_filename_component(FNSHORT ${FILENAME} NAME_WE) + string(REGEX REPLACE "\\.[^.]*$" "" FNSHORT ${FILENAME}) + + # add targets for HEX, BIN and S19 formats with no output so they will always be built + add_custom_target(${TARGET}.hex DEPENDS ${TARGET} COMMAND ${CMAKE_OBJCOPY} -Oihex ${FILENAME} ${FNSHORT}.hex) + add_custom_target(${TARGET}.s19 DEPENDS ${TARGET} COMMAND ${CMAKE_OBJCOPY} -Osrec ${FILENAME} ${FNSHORT}.s19) + add_custom_target(${TARGET}.bin DEPENDS ${TARGET} COMMAND ${CMAKE_OBJCOPY} -Obinary ${FILENAME} ${FNSHORT}.bin) + add_custom_target(${TARGET}.dump DEPENDS ${TARGET} COMMAND ${CMAKE_OBJDUMP} -d -EL -S ${FILENAME} ${FNSHORT}.dump) +endfunction() + + +function(NF_PRINT_SIZE_OF_TARGETS TARGET) + if(EXECUTABLE_OUTPUT_PATH) + set(FILENAME "${EXECUTABLE_OUTPUT_PATH}/${TARGET}") + else() + set(FILENAME "${TARGET}") + endif() + add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_SIZE} -A -x ${FILENAME}) +endfunction() + + +function(NF_SET_OPTIMIZATION_OPTIONS TARGET) + + target_compile_options(${TARGET} PRIVATE + $<$:-Og -femit-class-debug-always -g3 -ggdb> + $<$:-O3 -flto -fuse-linker-plugin -fno-fat-lto-objects> + $<$:-Os -flto -fuse-linker-plugin -fno-fat-lto-objects> + $<$:-Os -femit-class-debug-always -g3 -ggdb> + ) + +endfunction() + + +function(NF_SET_LINK_MAP TARGET) + + # need to remove the .elf suffix from target name + string(FIND ${TARGET} "." TARGET_EXTENSION_DOT_INDEX) + string(SUBSTRING ${TARGET} 0 ${TARGET_EXTENSION_DOT_INDEX} TARGET_SHORT) + + # add linker flags to generate map file + set_property(TARGET ${TARGET_SHORT}.elf APPEND_STRING PROPERTY LINK_FLAGS " -Wl,-Map=${PROJECT_BINARY_DIR}/${TARGET_SHORT}.map,--library-path=${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/common") + +endfunction() + + +function(NF_SET_COMPILER_DEFINITIONS TARGET) + + # definition for platform + # (always ARM here) + # ChibiOS HAL community always include (nanoFramework overlay and official community contributions optionally) + target_compile_definitions(${TARGET} PUBLIC "-DPLATFORM_ARM -DHAL_USE_COMMUNITY") + + # build types that have debugging capabilities AND are NOT RTM have to have the define 'NANOCLR_ENABLE_SOURCELEVELDEBUGGING' + if((NOT NF_BUILD_RTM) OR NF_FEATURE_DEBUGGER) + target_compile_definitions(${TARGET} PUBLIC "-DNANOCLR_ENABLE_SOURCELEVELDEBUGGING ") + endif() + + # set compiler definition for RTM build option + if(NF_BUILD_RTM) + target_compile_definitions(${TARGET} PUBLIC -DBUILD_RTM) + endif() + + # set compiler definition for using Application Domains feature + if(NF_FEATURE_USE_APPDOMAINS) + target_compile_definitions(${TARGET} PUBLIC -DNANOCLR_USE_APPDOMAINS) + endif() + + # set compiler definition for implementing (or not) CRC32 in Wire Protocol + if(NF_WP_IMPLEMENTS_CRC32) + target_compile_definitions(${TARGET} PUBLIC -DWP_IMPLEMENTS_CRC32) + endif() + + # set definition for Wire Protocol trace mask + target_compile_definitions(${TARGET} PUBLIC -DTRACE_MASK=${WP_TRACE_MASK}) + + # set compiler definition regarding inclusion of trace messages and checks on CLR + if(NF_PLATFORM_NO_CLR_TRACE) + target_compile_definitions(${TARGET} PUBLIC -DPLATFORM_NO_CLR_TRACE=1) + endif() + + # set compiler definition regarding CLR IL inlining + if(NF_CLR_NO_IL_INLINE) + target_compile_definitions(${TARGET} PUBLIC -DNANOCLR_NO_IL_INLINE=1) + endif() + + # include any extra compiler definitions coming from extra args + target_compile_definitions(${TARGET} PUBLIC ${ARGN}) + +endfunction() + + +function(NF_SET_LINKER_FILE TARGET LINKER_FILE_NAME) + + # set linker file name + set_target_properties(${TARGET} PROPERTIES LINK_FLAGS "-T${LINKER_FILE_NAME}") + +endfunction() diff --git a/source/native/nf-interpreter/CMake/toolchain.FreeRtos.ESP32.GCC.cmake b/source/native/nf-interpreter/CMake/toolchain.FreeRtos.ESP32.GCC.cmake new file mode 100644 index 00000000..67970bca --- /dev/null +++ b/source/native/nf-interpreter/CMake/toolchain.FreeRtos.ESP32.GCC.cmake @@ -0,0 +1,95 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +INCLUDE(CMakeForceCompiler) +# if( DEFINED CMAKE_CROSSCOMPILING ) +# # subsequent toolchain loading is not really needed +# return() +# endif() + +# check for toolchain path +# if(NOT TOOLCHAIN_PREFIX) +# message( "tcp ${TOOLCHAIN_PREFIX}" ) +# message(STATUS "\n-- ########################################\nNo TOOLCHAIN_PREFIX specified, need one!\nCall CMake with -DTOOLCHAIN_PREFIX=\"\"\n specifing the path to your GCC toolchain") +# message(STATUS "\nNOTE: mind the forward slash in the path, without trailing slash.)") +# message(STATUS "########################################\n\n") +# message(FATAL_ERROR "No TOOLCHAIN_PREFIX specified") +# endif() + +# Stop cmake trying to check if compiler works +set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY ) + +# set toolchain directories +set(TOOLCHAIN_BIN_DIR ${TOOLCHAIN_PREFIX}/xtensa-esp32-elf/bin) +set(TOOLCHAIN_INC_DIR ${ESP32_IDF_PATH}/components/newlib/include) +set(TOOLCHAIN_LIB_DIR ${TOOLCHAIN_PREFIX}/xtensa-esp32-elf/xtensa-esp32-elf/lib) + +# the name of the operating system for which CMake is to build +set(CMAKE_SYSTEM_NAME Generic) + +# name of the CPU CMake is building for +set(CMAKE_SYSTEM_PROCESSOR xtensa-esp32) + +# macro to setup compilers +macro(SET_COMPILER_VAR var name) + find_program(CMAKE_${var} xtensa-esp32-elf-${name} HINTS ${TOOLCHAIN_BIN_DIR} DOC "${name} tool") +endmacro() + +# setup C compiler +if(NOT CMAKE_C_COMPILER) + SET_COMPILER_VAR(C_COMPILER gcc) +endif() +SET_COMPILER_VAR(C_COMPILER gcc) + +# setup C++ compiler +if(NOT CMAKE_CXX_COMPILER) + SET_COMPILER_VAR(CXX_COMPILER g++) +endif() + +# setup Assembler compiler +SET_COMPILER_VAR(ASM-ATT_COMPILER as) + +# other toolchain configurations +set(CMAKE_OBJCOPY ${TOOLCHAIN_BIN_DIR}/xtensa-esp32-elf-objcopy CACHE INTERNAL "objcopy tool") +set(CMAKE_OBJDUMP ${TOOLCHAIN_BIN_DIR}/xtensa-esp32-elf-objdump CACHE INTERNAL "objdump tool") +set(CMAKE_SIZE ${TOOLCHAIN_BIN_DIR}/xtensa-esp32-elf-size CACHE INTERNAL "size tool") +set(CMAKE_DEBUGER ${TOOLCHAIN_BIN_DIR}/xtensa-esp32-elf-gdb CACHE INTERNAL "debuger") + +set(GCC_ESP32_LINKER_FLAGS, " -nostdlib -u call_user_start_cpu0 -Wl,--gc-sections -Wl,-static -Wl,--start-group -Wl,--print-memory-usage " CACHE INTERNAL "Gcc esp32 liker flags" ) +set(GCC_ESP32_LINKER_LIBS, " ${ESP32_IDF_PATH}/components/newlib/lib/libc.a ${ESP32_IDF_PATH}/components/newlib/lib/libm.a ${ESP32_IDF_PATH}/components/esp32/libhal.a -L${ESP32_IDF_PATH}/components/esp32/lib -lcore -lrtc -lnet80211 -lmesh -lpp -lwpa -lsmartconfig -lcoexist -lwps -lwpa2 -lphy -lgcc -lstdc++ " CACHE INTERNAL "Gcc esp32 liker libs") +set(GCC_ESP32_LINKER_LD, " -L ${ESP32_IDF_PATH}/components/esp32/ld -T esp32_out.ld -u ld_include_panic_highint_hdl -T esp32.common.ld -T esp32.rom.ld -T esp32.peripherals.ld " CACHE INTERNAL "Gcc esp32 liker LD") + +# set debug flags +#set(CMAKE_C_FLAGS "-DTEST_WITH_C_FLAGS " CACHE INTERNAL "c compiler flags ") + + +set(CMAKE_CXX_FLAGS "" CACHE INTERNAL "") + +set(CMAKE_C_FLAGS_DEBUG "-std=gnu99 -Og -ggdb -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -mlongcalls -nostdlib -Wall -Wextra -Werror -mfix-esp32-psram-cache-issue -DWITH_POSIX -DHAVE_CONFIG_H -DESP_PLATFORM -D IDF_VER=\"v3.3\" -MMD -MP " CACHE INTERNAL "c compiler flags debug") +set(CMAKE_CXX_FLAGS_DEBUG " -Og -ggdb -std=gnu++11 -fno-exceptions -fno-rtti -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -mlongcalls -nostdlib -Wall -Wextra -Werror -mfix-esp32-psram-cache-issue -DESP_PLATFORM " CACHE INTERNAL "cxx compiler flags debug") + +set(CMAKE_ASM_FLAGS_DEBUG " -g3 -ggdb" CACHE INTERNAL "asm compiler flags debug") + +#set(CMAKE_EXE_LINKER_FLAGS_DEBUG " ${GCC_ESP32_LINKER_FLAGS} ${GCC_ESP32_LINKER_LIBS} ${GCC_ESP32_LINKER_LD} " CACHE INTERNAL "linker flags debug") +set(CMAKE_EXE_LINKER_FLAGS_DEBUG " -nostdlib -u call_user_start_cpu0 -Wl,--gc-sections -Wl,-static " CACHE INTERNAL "linker flags debug") + +# set release flags +set(CMAKE_C_FLAGS_RELEASE " -std=gnu99 -Os -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -mlongcalls -nostdlib -MMD -MP -Wall -Wextra -Werror -mfix-esp32-psram-cache-issue -D IDF_VER=\"v3.3\" " CACHE INTERNAL "c compiler flags release") +set(CMAKE_C_FLAGS_MINSIZEREL " -std=gnu99 -Os -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -mlongcalls -nostdlib -MMD -MP -Wall -Wextra -Werror -mfix-esp32-psram-cache-issue -D IDF_VER=\"v3.3\" " CACHE INTERNAL "c compiler flags minsizerel") +set(CMAKE_CXX_FLAGS_RELEASE " -Os -std=gnu++11 -g3 -fno-exceptions -fno-rtti -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -mlongcalls -nostdlib -Wall -Wextra -Werror -mfix-esp32-psram-cache-issue -DESP_PLATFORM " CACHE INTERNAL "cxx compiler flags release") +set(CMAKE_CXX_FLAGS_MINSIZEREL " -Os -std=gnu++11 -g3 -fno-exceptions -fno-rtti -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -mlongcalls -nostdlib -Wall -Wextra -Werror -mfix-esp32-psram-cache-issue -DESP_PLATFORM " CACHE INTERNAL "cxx compiler flags minsizerel") + +set(CMAKE_ASM_FLAGS_RELEASE "" CACHE INTERNAL "asm compiler flags release") +set(CMAKE_EXE_LINKER_FLAGS_RELEASE " -nostdlib -u call_user_start_cpu0 -Wl,--gc-sections -Wl,-static " CACHE INTERNAL "linker flags release") +set(CMAKE_EXE_LINKER_FLAGS_MINSIZEREL " -nostdlib -u call_user_start_cpu0 -Wl,--gc-sections -Wl,-static " CACHE INTERNAL "linker flags minsizerel") + +set( CMAKE_C_LINK_EXECUTABLE " -o ") +set( CMAKE_CXX_LINK_EXECUTABLE " -o ") + +# root paths to search on the filesystem for cross-compiling +set(CMAKE_FIND_ROOT_PATH ${TOOLCHAIN_PREFIX}/xtensa-esp32-elf ${EXTRA_FIND_PATH}) +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) diff --git a/source/native/nf-interpreter/CMake/toolchain.TI_SimpleLink.GCC.cmake b/source/native/nf-interpreter/CMake/toolchain.TI_SimpleLink.GCC.cmake new file mode 100644 index 00000000..37b908a6 --- /dev/null +++ b/source/native/nf-interpreter/CMake/toolchain.TI_SimpleLink.GCC.cmake @@ -0,0 +1,174 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +INCLUDE(CMakeForceCompiler) + +################################################### +# set C and C++ flags for compiler detection tests +################################################### +# IMPORTANT: these flags need to be removed after +# the compiler detection otherwise they'll get +# added to all compiler build calls and +# will colide with the use of nano.specs +################################################### +set(CMAKE_C_FLAGS_INIT "-specs=nosys.specs") +set(CMAKE_CXX_FLAGS_INIT "-specs=nosys.specs") +################################################### + + +# set toolchain directories +set(TOOLCHAIN_BIN_DIR ${TOOLCHAIN_PREFIX}/bin) +set(TOOLCHAIN_INC_DIR ${TOOLCHAIN_PREFIX}/arm-none-eabi/include) +set(TOOLCHAIN_LIB_DIR ${TOOLCHAIN_PREFIX}/arm-none-eabi/lib) + +# the name of the operating system for which CMake is to build +set(CMAKE_SYSTEM_NAME Generic) + +# name of the CPU CMake is building for +set(CMAKE_SYSTEM_PROCESSOR arm) + +# macro to setup compilers +macro(SET_COMPILER_VAR var name) + find_program(CMAKE_${var} arm-none-eabi-${name} HINTS ${TOOLCHAIN_BIN_DIR} DOC "${name} tool") +endmacro() + +# setup C compiler +if(NOT CMAKE_C_COMPILER) + SET_COMPILER_VAR(C_COMPILER gcc) +endif() + +# setup C++ compiler +if(NOT CMAKE_CXX_COMPILER) + SET_COMPILER_VAR(CXX_COMPILER g++) +endif() + +# setup Assembler compiler +SET_COMPILER_VAR(ASM-ATT_COMPILER as) + +# other toolchain configurations +set(CMAKE_OBJCOPY ${TOOLCHAIN_BIN_DIR}/arm-none-eabi-objcopy CACHE INTERNAL "objcopy tool") +set(CMAKE_OBJDUMP ${TOOLCHAIN_BIN_DIR}/arm-none-eabi-objdump CACHE INTERNAL "objdump tool") +set(CMAKE_SIZE ${TOOLCHAIN_BIN_DIR}/arm-none-eabi-size CACHE INTERNAL "size tool") +set(CMAKE_DEBUGER ${TOOLCHAIN_BIN_DIR}/arm-none-eabi-gdb CACHE INTERNAL "debuger") + +# root paths to search on the filesystem for cross-compiling +set(CMAKE_FIND_ROOT_PATH ${TOOLCHAIN_PREFIX}/arm-none-eabi ${EXTRA_FIND_PATH}) +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) + +# set required C and C++ standard for ALL targets +set(CMAKE_C_STANDARD 11 CACHE INTERNAL "C standard for all targets") +set(CMAKE_CXX_STANDARD 11 CACHE INTERNAL "C++ standard for all targets") + +# set all C and C++ extensions to be OFF on ALL targets +# this forces the use of -std=c11 and -std=c++11 instead of -std=gnu11 and -std=gnu++11 +set(CMAKE_C_EXTENSIONS OFF CACHE INTERNAL "C compiler extensions OFF") +set(CMAKE_CXX_EXTENSIONS OFF CACHE INTERNAL "C++ compiler extensions OFF") + + +function(NF_ADD_HEX_BIN_DUMP_TARGETS TARGET) + if(EXECUTABLE_OUTPUT_PATH) + set(FILENAME "${EXECUTABLE_OUTPUT_PATH}/${TARGET}") + else() + set(FILENAME "${TARGET}") + endif() + + # add targets for HEX, BIN and S19 formats with no output so they will always be built + add_custom_target(${TARGET}.hex DEPENDS ${TARGET} COMMAND ${CMAKE_OBJCOPY} -Oihex ${FILENAME} ${FILENAME}.hex) + add_custom_target(${TARGET}.s19 DEPENDS ${TARGET} COMMAND ${CMAKE_OBJCOPY} -Osrec ${FILENAME} ${FILENAME}.s19) + add_custom_target(${TARGET}.bin DEPENDS ${TARGET} COMMAND ${CMAKE_OBJCOPY} -Obinary ${FILENAME} ${FILENAME}.bin) + add_custom_target(${TARGET}.dump DEPENDS ${TARGET} COMMAND ${CMAKE_OBJDUMP} -d -EL -S ${FILENAME} ${FILENAME}.dump) +endfunction() + + +function(NF_PRINT_SIZE_OF_TARGETS TARGET) + if(EXECUTABLE_OUTPUT_PATH) + set(FILENAME "${EXECUTABLE_OUTPUT_PATH}/${TARGET}") + else() + set(FILENAME "${TARGET}") + endif() + add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_SIZE} -A -x ${FILENAME}) +endfunction() + + +function(NF_SET_OPTIMIZATION_OPTIONS TARGET) + + target_compile_options(${TARGET} PRIVATE + $<$:-Og -femit-class-debug-always -g3 -ggdb> + $<$:-O3 -flto -fuse-linker-plugin -fno-fat-lto-objects> + $<$:-Os -flto -fuse-linker-plugin -fno-fat-lto-objects> + $<$:-Os -femit-class-debug-always -g3 -ggdb> + ) + +endfunction() + + +function(NF_SET_LINK_MAP TARGET) + + # need to remove the .elf suffix from target name + string(FIND ${TARGET} "." TARGET_EXTENSION_DOT_INDEX) + string(SUBSTRING ${TARGET} 0 ${TARGET_EXTENSION_DOT_INDEX} TARGET_SHORT) + + # add linker flags to generate map file + set_property(TARGET ${TARGET_SHORT}.elf APPEND_STRING PROPERTY LINK_FLAGS " -Wl,-Map=${PROJECT_SOURCE_DIR}/build/${TARGET_SHORT}.map,--library-path=${PROJECT_SOURCE_DIR}/targets/TI-SimpleLink/common") + +endfunction() + + +function(NF_SET_COMPILER_DEFINITIONS TARGET) + + # definition for platform + # (always ARM here) + target_compile_definitions(${TARGET} PUBLIC "-DPLATFORM_ARM ") + + # definitions required for SimpleLink CC32xx SDK + target_compile_definitions(${TARGET} PUBLIC -Dgcc -DPTLS_TLS_INDEX=0 -DCC32XX -DBOARD_DISPLAY_USE_UART_ANSI=0 -DBOARD_DISPLAY_USE_LCD=0 -DconfigNUM_THREAD_LOCAL_STORAGE_POINTERS=1 -DSL_PLATFORM_MULTI_THREADED) + + # build types that have debugging capabilities AND are NOT RTM have to have the define 'NANOCLR_ENABLE_SOURCELEVELDEBUGGING' + if((NOT NF_BUILD_RTM) OR NF_FEATURE_DEBUGGER) + target_compile_definitions(${TARGET} PUBLIC "-DNANOCLR_ENABLE_SOURCELEVELDEBUGGING ") + endif() + + # set compiler definition for RTM build option + if(NF_BUILD_RTM) + target_compile_definitions(${TARGET} PUBLIC -DBUILD_RTM) + endif() + + # set compiler definition for using Application Domains feature + if(NF_FEATURE_USE_APPDOMAINS) + target_compile_definitions(${TARGET} PUBLIC -DNANOCLR_USE_APPDOMAINS) + endif() + + # set compiler definition for implementing (or not) CRC32 in Wire Protocol + if(NF_WP_IMPLEMENTS_CRC32) + target_compile_definitions(${TARGET} PUBLIC -DWP_IMPLEMENTS_CRC32) + endif() + + # set definition for Wire Protocol trace mask + target_compile_definitions(${TARGET} PUBLIC -DTRACE_MASK=${WP_TRACE_MASK}) + + # set compiler definition regarding inclusion of trace messages and checks on CLR + if(NF_PLATFORM_NO_CLR_TRACE) + target_compile_definitions(${TARGET} PUBLIC -DPLATFORM_NO_CLR_TRACE=1) + endif() + + # set compiler definition regarding CLR IL inlining + if(NF_CLR_NO_IL_INLINE) + target_compile_definitions(${TARGET} PUBLIC -DNANOCLR_NO_IL_INLINE=1) + endif() + + # include any extra compiler definitions coming from extra args + target_compile_definitions(${TARGET} PUBLIC ${ARGN}) + +endfunction() + + +function(NF_SET_LINKER_FILE TARGET LINKER_FILE_NAME) + + # set linker file name + set_target_properties(${TARGET} PROPERTIES LINK_FLAGS "-T${LINKER_FILE_NAME}") + +endfunction() diff --git a/source/native/nf-interpreter/CMake/toolchain.mBed.GCC.cmake b/source/native/nf-interpreter/CMake/toolchain.mBed.GCC.cmake new file mode 100644 index 00000000..b2917483 --- /dev/null +++ b/source/native/nf-interpreter/CMake/toolchain.mBed.GCC.cmake @@ -0,0 +1,101 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +INCLUDE(CMakeForceCompiler) +# if( DEFINED CMAKE_CROSSCOMPILING ) +# # subsequent toolchain loading is not really needed +# return() +# endif() + +# check for toolchain path +if(NOT TOOLCHAIN_PREFIX) + message(STATUS "\n-- ########################################\nNo TOOLCHAIN_PREFIX specified, need one!\nCall CMake with -DTOOLCHAIN_PREFIX=\"\"\n specifing the path to your GCC toolchain (ex: E:/GNU_Tools_ARM_Embedded/5_4_2016q3)") + message(STATUS "\nNOTE: mind the forward slash in the path, without trailing slash.)") + message(STATUS "########################################\n\n") + message(FATAL_ERROR "No TOOLCHAIN_PREFIX specified") +endif() + +# set toolchain directories +set(TOOLCHAIN_BIN_DIR ${TOOLCHAIN_PREFIX}/bin) +set(TOOLCHAIN_INC_DIR ${TOOLCHAIN_PREFIX}/arm-none-eabi/include) +set(TOOLCHAIN_LIB_DIR ${TOOLCHAIN_PREFIX}/arm-none-eabi/lib) + +# the name of the operating system for which CMake is to build +set(CMAKE_SYSTEM_NAME Generic) + +# name of the CPU CMake is building for +set(CMAKE_SYSTEM_PROCESSOR arm) + +# macro to setup compilers +macro(SET_COMPILER_VAR var name) + find_program(CMAKE_${var} arm-none-eabi-${name} HINTS ${TOOLCHAIN_BIN_DIR} DOC "${name} tool") +endmacro() + +# setup C compiler +if(NOT CMAKE_C_COMPILER) + SET_COMPILER_VAR(C_COMPILER gcc) + if(CMAKE_C_COMPILER) + CMAKE_FORCE_C_COMPILER(${CMAKE_C_COMPILER} GNU) + endif() +endif() +SET_COMPILER_VAR(C_COMPILER gcc) + +# setup C++ compiler +if(NOT CMAKE_CXX_COMPILER) + SET_COMPILER_VAR(CXX_COMPILER g++) + if(CMAKE_CXX_COMPILER) + CMAKE_FORCE_CXX_COMPILER(${CMAKE_CXX_COMPILER} GNU) + endif() +endif() + +# setup Assembler compiler +SET_COMPILER_VAR(ASM-ATT_COMPILER as) + +# other toolchain configurations +set(CMAKE_OBJCOPY ${TOOLCHAIN_BIN_DIR}/arm-none-eabi-objcopy CACHE INTERNAL "objcopy tool") +set(CMAKE_OBJDUMP ${TOOLCHAIN_BIN_DIR}/arm-none-eabi-objdump CACHE INTERNAL "objdump tool") +set(CMAKE_SIZE ${TOOLCHAIN_BIN_DIR}/arm-none-eabi-size CACHE INTERNAL "size tool") +set(CMAKE_DEBUGER ${TOOLCHAIN_BIN_DIR}/arm-none-eabi-gdb CACHE INTERNAL "debuger") + +# set debug flags +set(CMAKE_C_FLAGS_DEBUG "-Og -femit-class-debug-always -g3 -ggdb" CACHE INTERNAL "c compiler flags debug") +set(CMAKE_CXX_FLAGS_DEBUG "-Og -femit-class-debug-always -g3 -ggdb" CACHE INTERNAL "cxx compiler flags debug") +set(CMAKE_ASM_FLAGS_DEBUG "-g3 -ggdb" CACHE INTERNAL "asm compiler flags debug") +set(CMAKE_EXE_LINKER_FLAGS_DEBUG "" CACHE INTERNAL "linker flags debug") + +# set release flags +set(CMAKE_C_FLAGS_RELEASE "-Os -flto" CACHE INTERNAL "c compiler flags release") +set(CMAKE_CXX_FLAGS_RELEASE "-Os -flto" CACHE INTERNAL "cxx compiler flags release") +set(CMAKE_ASM_FLAGS_RELEASE "" CACHE INTERNAL "asm compiler flags release") +set(CMAKE_EXE_LINKER_FLAGS_RELEASE "-flto" CACHE INTERNAL "linker flags release") + +# root paths to search on the filesystem for cross-compiling +set(CMAKE_FIND_ROOT_PATH ${TOOLCHAIN_PREFIX}/arm-none-eabi ${EXTRA_FIND_PATH}) +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) + +function(MBED_ADD_HEX_BIN_DUMP_TARGETS TARGET) + if(EXECUTABLE_OUTPUT_PATH) + set(FILENAME "${EXECUTABLE_OUTPUT_PATH}/${TARGET}") + else() + set(FILENAME "${TARGET}") + endif() + + # add targets for HEX, BIN and S19 formats with no output so they will always be built + add_custom_target(${TARGET}.hex DEPENDS ${TARGET} COMMAND ${CMAKE_OBJCOPY} -Oihex ${FILENAME} ${FILENAME}.hex) + add_custom_target(${TARGET}.s19 DEPENDS ${TARGET} COMMAND ${CMAKE_OBJCOPY} -Osrec ${FILENAME} ${FILENAME}.s19) + add_custom_target(${TARGET}.bin DEPENDS ${TARGET} COMMAND ${CMAKE_OBJCOPY} -Obinary ${FILENAME} ${FILENAME}.bin) + add_custom_target(${TARGET}.dump DEPENDS ${TARGET} COMMAND ${CMAKE_OBJDUMP} -d -EL -S ${FILENAME} ${FILENAME}.dump) +endfunction() + +function(MBED_PRINT_SIZE_OF_TARGETS TARGET) + if(EXECUTABLE_OUTPUT_PATH) + set(FILENAME "${EXECUTABLE_OUTPUT_PATH}/${TARGET}") + else() + set(FILENAME "${TARGET}") + endif() + add_custom_command(TARGET ${TARGET} POST_BUILD COMMAND ${CMAKE_SIZE} ${FILENAME}) +endfunction() diff --git a/source/native/nf-interpreter/CMakeLists.txt b/source/native/nf-interpreter/CMakeLists.txt new file mode 100644 index 00000000..8f9039d9 --- /dev/null +++ b/source/native/nf-interpreter/CMakeLists.txt @@ -0,0 +1,730 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +cmake_minimum_required(VERSION 3.11) +include(CMakeToolsHelpers OPTIONAL) +include(ExternalProject) + +# set(CMAKE_VERBOSE_MAKEFILE 1) # debug helper + +# the following prevents launchin a build in the source tree +set(CMAKE_DISABLE_SOURCE_CHANGES ON) +set(CMAKE_DISABLE_IN_SOURCE_BUILD ON) + +# fatal error and message explaining this +if (CMAKE_SOURCE_DIR STREQUAL CMAKE_BINARY_DIR) + message(STATUS "\n-- ###############################################\n") + message(STATUS "Please run the build outside of the source tree.\n\n") + message(STATUS "Hint: create a 'build' folder and run CMake from there..") + message(STATUS "###############################################\n\n") + message(FATAL_ERROR "Build launched in the source tree.") +endif() +######################################### + + +######################################################## +# path to local CMake modules +set(CMAKE_MODULE_PATH ${CMAKE_SOURCE_DIR}/CMake/Modules) +######################################################## + + +###################################################### +# set build type to release if not specified otherwise +if(NOT CMAKE_BUILD_TYPE) + set(CMAKE_BUILD_TYPE "Debug") +endif() +###################################################### + +# add compiler define for DEBUG +add_compile_options("$<$:-DDEBUG>") + +###################################################### +# set time stamp of build +string(TIMESTAMP BUILD_TIMESTAMP UTC) +###################################################### + +####################### +# handle RTOSes choice + +if("${RTOS}" STREQUAL "") + # no RTOS selected, defaulting to ChibiOS + set(RTOS "CHIBIOS") +endif() + +# list of supported RTOSes +# when adding a new RTOS add the corresponding string below AND... +# ... also on the compare block below +set(RTOS_SUPPORTED "CHIBIOS" "FREERTOS_ESP32" "TI_SIMPLELINK" CACHE INTERNAL "supported RTOS options") + +list(FIND RTOS_SUPPORTED ${RTOS} RTOS_INDEX) +if(RTOS_INDEX EQUAL -1) + message(FATAL_ERROR "\n\n'${RTOS}' is an invalid option for RTOS. Please choose a valid RTOS.\n\n") +else() + message(STATUS "\nSetting RTOS to ${RTOS}\n") +endif() + +string(COMPARE EQUAL "CHIBIOS" "${RTOS}" RTOS_CHIBIOS_CHECK) +string(COMPARE EQUAL "FREERTOS_ESP32" "${RTOS}" RTOS_FREERTOS_ESP32_CHECK) +string(COMPARE EQUAL "TI_SIMPLELINK" "${RTOS}" RTOS_TI_SIMPLELINK_CHECK) + +########################################################################## + +if(RTOS_FREERTOS_ESP32_CHECK) + set(RTOS_FREERTOS_ESP32_CHECK TRUE) + set(RTOS_TI_SIMPLELINK_CHECK FALSE) + set(RTOS_CHIBIOS_CHECK FALSE) +endif() + +if(RTOS_CHIBIOS_CHECK) + set(RTOS_CHIBIOS_CHECK TRUE) + set(RTOS_FREERTOS_ESP32_CHECK FALSE) + set(RTOS_TI_SIMPLELINK_CHECK FALSE) +endif() + +if(RTOS_TI_SIMPLELINK_CHECK) + set(RTOS_TI_SIMPLELINK_CHECK TRUE) + set(RTOS_FREERTOS_ESP32_CHECK FALSE) + set(RTOS_CHIBIOS_CHECK FALSE) +endif() + +####################### + + +########################################## +# set default toolchain to GCC +set(TOOLCHAIN GCC) +# have it lower case too for file names +string(TOLOWER TOOLCHAIN_LOWER ${TOOLCHAIN}) +########################################## + +if(RTOS_CHIBIOS_CHECK) + + # check for toolchain path + if(NOT TOOLCHAIN_PREFIX) + message(STATUS "\n-- ########################################\nNo TOOLCHAIN_PREFIX specified, need one!\nCall CMake with -DTOOLCHAIN_PREFIX=\"\"\n specifing the path to your GCC toolchain (ex: E:/GNU_Tools_ARM_Embedded/5_4_2016q3)") + message(STATUS "\nNOTE: mind the forward slash in the path, without trailing slash.)") + message(STATUS "########################################\n\n") + message(FATAL_ERROR "No TOOLCHAIN_PREFIX specified") + endif() + + message(STATUS "\nSetting Toolchain file for ChibiOS \n") + # set toolchain file + set(CMAKE_TOOLCHAIN_FILE CMake/toolchain.ChibiOS.${TOOLCHAIN}.cmake) + + # Set up short path substitution on Windows + if(WIN32) + if(EXISTS ${CMAKE_SOURCE_DIR}/SetNFRoot.bat) + execute_process(COMMAND ${CMAKE_SOURCE_DIR}/SetNFRoot.bat OUTPUT_VARIABLE NFROOT OUTPUT_STRIP_TRAILING_WHITESPACE) + set(ENV{nfRoot} ${NFROOT}) + endif() + endif() + +elseif(RTOS_FREERTOS_ESP32_CHECK) + message(STATUS "\nSetting Toolchain file for FreeRTOS ESP32 \n") + set(CMAKE_TOOLCHAIN_FILE CMake/toolchain.FreeRtos.ESP32.${TOOLCHAIN}.cmake) + +elseif(RTOS_TI_SIMPLELINK_CHECK) + message(STATUS "\nSetting Toolchain file for FreeRTOS CC32XX \n") + set(CMAKE_TOOLCHAIN_FILE CMake/toolchain.TI_SimpleLink.${TOOLCHAIN}.cmake) + +endif() + +######################################### + +# set default version +if(NOT BUILD_VERSION) + set(BUILD_VERSION 0.0.0.0) +endif() +project(nanoFramework VERSION ${BUILD_VERSION}) + +####################### +message(STATUS "") +message(STATUS "Building nanoFramework version ${PROJECT_VERSION} using build type '${CMAKE_BUILD_TYPE}'.") +message(STATUS "Source directory is '${PROJECT_SOURCE_DIR}'.") +message(STATUS "Build directory is '${PROJECT_BINARY_DIR}'.") +message(STATUS "Toolchain is '${TOOLCHAIN}'.") +message(STATUS "") +####################### + + +################################################################# +# ouput RTM build option +# Build RTM version of firmware (default is OFF so the build is not RTM and the CLR outputs some debug informations) +option(NF_BUILD_RTM "option to build with RTM definition") + +if(NF_BUILD_RTM) + message(STATUS "***************************") + message(STATUS "** Building RTM firmware **") + message(STATUS "***************************") + message(STATUS "") +endif() +################################################################# + +if(RTOS_CHIBIOS_CHECK) + + ################################################################# + # clear CMAKE_C_FLAGS_INIT and CMAKE_CXX_FLAGS_INIT + # (this needs to be here and not before because by now + # the compiler detection has already occurred) + set(CMAKE_C_FLAGS "" CACHE INTERNAL "clear c compiler flags") + set(CMAKE_CXX_FLAGS "" CACHE INTERNAL "clear cxx compiler flags") + ################################################################# + + + ################################################################# + # clear some CMake flavor flags that are being set as default + # in the GNU compiler init + # we want to control and fine tune these + set(CMAKE_C_FLAGS_DEBUG "" CACHE INTERNAL "clear c compiler flags") + set(CMAKE_C_FLAGS_MINSIZEREL "" CACHE INTERNAL "clear c compiler flags") + set(CMAKE_C_FLAGS_RELEASE "" CACHE INTERNAL "clear c compiler flags") + set(CMAKE_C_FLAGS_RELWITHDEBINFO "" CACHE INTERNAL "clear c compiler flags") + set(CMAKE_CXX_FLAGS_DEBUG "" CACHE INTERNAL "clear c++ compiler flags") + set(CMAKE_CXX_FLAGS_MINSIZEREL "" CACHE INTERNAL "clear c++ compiler flags") + set(CMAKE_CXX_FLAGS_RELEASE "" CACHE INTERNAL "clear c++ compiler flags") + set(CMAKE_CXX_FLAGS_RELWITHDEBINFO "" CACHE INTERNAL "clear c++ compiler flags") + ################################################################# + + + ################################################################# + # clear default libraries that are set by CMake + # we want to control + set(CMAKE_C_IMPLICIT_LINK_LIBRARIES "" CACHE INTERNAL "clear c linker default libs") + set(CMAKE_CXX_IMPLICIT_LINK_LIBRARIES "" CACHE INTERNAL "clear c++ linker default libs") + ################################################################# + +endif() + +################################################################################# +# chooses if double-point float point support is provided by the platform +# (default is OFF which means that single-precision floating point is effective) +option(DP_FLOATINGPOINT "option to enable support for double-precision floating point") + +if(DP_FLOATINGPOINT) + set(TARGET_DP_FLOATINGPOINT TRUE CACHE INTERNAL "DP FP support") + message(STATUS "Double-precision floating point is effective") +else() + set(TARGET_DP_FLOATINGPOINT FALSE CACHE INTERNAL "DP FP support") + message(STATUS "Single-precision floating point is effective") +endif() + +################################################################################# +# chooses if build without complex math functions +# (default is OFF which means that all floating point math functions are available) +option(NF_FEATURE_LIGHT_MATH "option to build without complex math functions") + +if(NF_FEATURE_LIGHT_MATH) + set(TARGET_LIGHT_MATH TRUE CACHE INTERNAL "Complex Math functions disabled") + message(STATUS "Complex math functions not available") +else() + set(TARGET_LIGHT_MATH FALSE CACHE INTERNAL "Complex Math functions enabled") + message(STATUS "Complex math functions available") +endif() + +################################################################################### +# chooses if platform provides support for converting string to values on any base +# (default is OFF which means that conversion to value from base 10 and 16 (partial) is effective) +option(SUPPORT_ANY_BASE_CONVERSION "option to enable support for converting strings to value on any base") + +if(SUPPORT_ANY_BASE_CONVERSION) + set(TARGET_SUPPORT_ANY_BASE_CONVERSION TRUE CACHE INTERNAL "Option for string conversion to value from any base") + message(STATUS "String conversion to value on any base is effective") +else() + set(TARGET_SUPPORT_ANY_BASE_CONVERSION FALSE CACHE INTERNAL "Option for string conversion to value from base 10 and partial for 16") + message(STATUS "String conversion to value from base 10 and 16 (partial) is effective") +endif() + +################################################################# +# true random number generation option supported by hardware +option(USE_RNG "option to enable use of true random generator hardware block" ON) + +if(USE_RNG) + message(STATUS "Random Number Generation by target MCU is activated") +else() + message(STATUS "Random Number Generation by target MCU is NOT activated") +endif() + +################################################################# +# nanoFramework features +################################################################# + +################################################################### +# debugger (default is OFF so no support for debugging is included +option(NF_FEATURE_DEBUGGER "option to enable support for debugging") + +if(NF_FEATURE_DEBUGGER) + message(STATUS "Support for debugging managed applications is included.") +else() + message(STATUS "Support for debugging managed applications IS NOT included.") +endif() + +################################################################# +# enables Application Domains support in nanoCLR +# (default is OFF so Application Domains is NOT supported) +option(NF_FEATURE_USE_APPDOMAINS "option to enable Application Domains") + +if(NF_FEATURE_USE_APPDOMAINS) + message(STATUS "Application Domains support is included") +else() + message(STATUS "Application Domains support IS NOT included") +endif() + +################################################################# +# disable all trace messages and checks on CLR +# (default is OFF so all traces and checks are enabled) +option(NF_PLATFORM_NO_CLR_TRACE "option to disable all trace stuff in CLR") + +if(NF_PLATFORM_NO_CLR_TRACE) + message(STATUS "CLR has all trace messages and checks DISABLED") +else() + message(STATUS "CLR has all trace messages and checks enabled") +endif() + +################################################################# +# disable CLR IL inlining +# (default is OFF so CLR IL inline is enabled) +option(NF_CLR_NO_IL_INLINE "option to disable CLR IL inlining") + +if(NF_CLR_NO_IL_INLINE) + message(STATUS "CLR IL inlining is DISABLED") +else() + message(STATUS "CLR IL inlining is enabled") +endif() + +################################################################# +# enables configuration block storage support +# (default is OFF so Configuration block storage is NOT supported) +option(NF_FEATURE_HAS_CONFIG_BLOCK "option to enable configuration block storage") + +if(NF_FEATURE_HAS_CONFIG_BLOCK) + set(TARGET_HAS_CONFIG_BLOCK TRUE CACHE INTERNAL "Option for config block") + message(STATUS "Configuration block storage is included") +else() + set(TARGET_HAS_CONFIG_BLOCK FALSE CACHE INTERNAL "Option for config block") + message(STATUS "Configuration block storage IS NOT included") +endif() + +################################################################# +# enables support for SD Card +# (default is OFF so SD Card is NOT supported) +option(NF_FEATURE_HAS_SDCARD "option to enable support for SD Card") + +if(NF_FEATURE_HAS_SDCARD) + + # this feature currently is supported only on ChibiOS and ESP32 FreeRTOS + if(NOT RTOS_CHIBIOS_CHECK AND NOT RTOS_FREERTOS_ESP32_CHECK) + message(FATAL_ERROR "Support for SD Card is only available for ChibiOS Cortex-M and ESP32 targets.") + endif() + + # force inclusion of Windows.Storage API + set(API_Windows.Storage ON CACHE INTERNAL "Forcing Windows.Storage API option to ON") + + message(STATUS "Support for SD Card is included") +else() + message(STATUS "Support for SD Card IS NOT included") +endif() + +################################################################# + +################################################################# +# enables USB Mass Storage support +# (default is OFF so USB Mass Storage is NOT supported) +option(NF_FEATURE_HAS_USB_MSD "option to enable USB Mass Storage") + +if(NF_FEATURE_HAS_USB_MSD) + + # this feature currently is supported only on ChibiOS + if(NOT RTOS_CHIBIOS_CHECK) + message(FATAL_ERROR "Support for USB Mass Storage is only available for ChibiOS Cortex-M targets.") + endif() + + # this feature requires inclusion of ChibiOS contribution repository + set(CHIBIOS_CONTRIB_REQUIRED ON CACHE INTERNAL "Forcing ChibiOS contribution repo option to ON") + + # force inclusion of Windows.Storage API + set(API_Windows.Storage ON CACHE INTERNAL "Forcing Windows.Storage API option to ON") + + message(STATUS "Support for USB Mass Storage is included") +else() + message(STATUS "Support for USB Mass Storage IS NOT included") +endif() + +################################################################# + +################################################################# +# enables support for SPI file system +# (default is OFF so SPIFFS is NOT supported) +option(NF_FEATURE_USE_SPIFFS "option to enable support for SPI file system") + +if(NF_FEATURE_USE_SPIFFS) + + # this feature currently is supported only on ChibiOS and ESP32 + if(NOT RTOS_CHIBIOS_CHECK) + message(FATAL_ERROR "Support for SPIFFS is only available for ChibiOS Cortex-M and ESP32 targets.") + endif() + + # force inclusion of Windows.Storage API + set(API_Windows.Storage ON CACHE INTERNAL "Forcing Windows.Storage API option to ON") + + set(NF_FEATURE_USE_SPIFFS_OPTION TRUE CACHE INTERNAL "Set nF SPIFFS feature TRUE") + + message(STATUS "Support for SPIFFS is included") +else() + set(NF_FEATURE_USE_SPIFFS_OPTION FALSE CACHE INTERNAL "Set nF SPIFFS feature FALSE") + message(STATUS "Support for SPIFFS IS NOT included") +endif() + +################################################################# + +if(RTOS_CHIBIOS_CHECK) + + ################################################################# + # ARM Cortex-M Single Wire Output (SWO) + # (default is OFF so no SWO output) + + option(SWO_OUTPUT "option to enable SWO") + + if(SWO_OUTPUT) + set(SWO_OUTPUT_OPTION TRUE CACHE INTERNAL "Single Wire Output Option") + message(STATUS "Single Wire Output (SWO) enabled") + else() + set(SWO_OUTPUT_OPTION FALSE CACHE INTERNAL "Single Wire Output Option") + endif() + + ################################################################# + + ################################################################# + # enables use of ChibiOS Community contribution + # (default is OFF so ChibiOS Community is NOT included) + option(CHIBIOS_CONTRIB_REQUIRED "option to include ChibiOS Community contributions repository") + ################################################################# + +endif() + +################################################################# +# reports Wire Protocol CRC32 implementation +if(NF_WP_IMPLEMENTS_CRC32) + message(STATUS "Wire Protocol implements CRC32") +else() + message(STATUS "Wire Protocol does NOT implement CRC32") +endif() + +################################################################# +# enables Networking support in nanoCLR +# declares Networking option +# needs to show before the API namespaces processing because it's used there +# (default is OFF so Networking is NOT supported) +option(USE_NETWORKING_OPTION "option to use networking") + +# (default is OFF so mbed TLS is NOT used) +option(NF_SECURITY_MBEDTLS "option to use mbed TLS as the network security provider") + +# set default option for SNTP to ON +option(NF_NETWORKING_SNTP "option to use add SNTP support, requires networking otherwise has no effect" ON) + +################################################################# + +############################################# +# handles inclusion of System.Reflection API +############################################# + +# set default option for SNTP to ON +option(NF_FEATURE_SUPPORT_REFLECTION "option to add support for System.Reflection API" ON) + +if(NF_FEATURE_SUPPORT_REFLECTION) + set(TARGET_NANOCLR_REFLECTION TRUE CACHE INTERNAL "enable support for System.Reflection API") + message(STATUS "Support for System.Reflection API enabled") +else() + set(TARGET_NANOCLR_REFLECTION FALSE CACHE INTERNAL "DISABLE support for System.Reflection API") + message(STATUS "Support for System.Reflection API **IS NOT** enabled") +endif() + +################################################################# + +################################################################# + +############################################# +# handles inclusion of System.Collections API +############################################# + +if(API_nanoFramework.System.Collections) + set(TARGET_SYSTEM_COLLECTIONS TRUE CACHE INTERNAL "enable support for System.Collections API") + message(STATUS "Support for System.Collections API enabled") +else() + set(TARGET_SYSTEM_COLLECTIONS FALSE CACHE INTERNAL "DISABLE support for System.Collections API") + message(STATUS "Support for System.Collections API **IS NOT** enabled") +endif() + +################################################################# + +################################################################# +# manage HAL/PAL required for API namespaces +################################################################# +# for some APIs we need to enable the device in the HAL config +# and/or manage other APIs that are required + +if( API_nanoFramework.Devices.OneWire OR + API_Windows.Devices.SerialCommunication) + + set(HAL_USE_UART_OPTION TRUE CACHE INTERNAL "HAL OneWire for nanoFramework.Devices.OneWire") + +else() + set(HAL_USE_UART_OPTION FALSE CACHE INTERNAL "HAL OneWire for nanoFramework.Devices.OneWire") +endif() + +if( API_System.Net OR + API_Windows.Networking.Sockets) + + # set NETWORKING option to true + set(USE_NETWORKING_OPTION TRUE CACHE INTERNAL "NF feature NETWORKING") + + # set Security module to use + if(NF_SECURITY_MBEDTLS ) + set(USE_SECURITY_MBEDTLS_OPTION TRUE CACHE INTERNAL "NF security MBEDTLS") + endif() + + if(API_Windows.Devices.Wifi) + set(USE_WIFI_OPTION TRUE CACHE INTERNAL "Wifi for Windows.Devices.WiFi") + else() + set(USE_WIFI_OPTION FALSE CACHE INTERNAL "Wifi for Windows.Devices.WiFi") + endif() + +endif() + + +if(API_Windows.Devices.Adc) + set(HAL_USE_ADC_OPTION TRUE CACHE INTERNAL "HAL ADC for Windows.Devices.Adc") +else() + set(HAL_USE_ADC_OPTION FALSE CACHE INTERNAL "HAL ADC for Windows.Devices.Adc") +endif() + + +if(API_System.Devices.Dac) + set(HAL_USE_DAC_OPTION TRUE CACHE INTERNAL "HAL DAC for System.Devices.Dac") +else() + set(HAL_USE_DAC_OPTION FALSE CACHE INTERNAL "HAL DAC for System.Devices.Dac") +endif() + + +if(API_Windows.Devices.Gpio) + set(HAL_USE_GPIO_OPTION TRUE CACHE INTERNAL "HAL GPIO for Windows.Devices.Gpio") +else() + set(HAL_USE_GPIO_OPTION FALSE CACHE INTERNAL "HAL GPIO for Windows.Devices.Gpio") +endif() + + +if(API_Windows.Devices.I2c) + set(HAL_USE_I2C_OPTION TRUE CACHE INTERNAL "HAL I2C for Windows.Devices.I2c") +else() + set(HAL_USE_I2C_OPTION FALSE CACHE INTERNAL "HAL I2C for Windows.Devices.I2c") +endif() + + +if(API_Windows.Devices.Pwm) + set(HAL_USE_PWM_OPTION TRUE CACHE INTERNAL "HAL PWM for Windows.Devices.Pwm") +else() + set(HAL_USE_PWM_OPTION FALSE CACHE INTERNAL "HAL PWM for Windows.Devices.Pwm") +endif() + + +if(API_Windows.Devices.Spi) + set(HAL_USE_SPI_OPTION TRUE CACHE INTERNAL "HAL SPI for Windows.Devices.Spi") +else() + set(HAL_USE_SPI_OPTION FALSE CACHE INTERNAL "HAL SPI for Windows.Devices.Spi") +endif() + + +if(API_nanoFramework.Devices.Can) + set(HAL_USE_CAN_OPTION TRUE CACHE INTERNAL "HAL CAN for nanoFramework.Devices.Can") +else() + set(HAL_USE_CAN_OPTION FALSE CACHE INTERNAL "HAL CAN for nanoFramework.Devices.Can") +endif() + + +if(API_nanoFramework.Devices.OneWire) + set(HAL_USE_STM32_ONEWIRE_OPTION TRUE CACHE INTERNAL "HAL STM32_ONEWIRE for nanoFramework.Devices.OneWire") +else() + set(HAL_USE_STM32_ONEWIRE_OPTION FALSE CACHE INTERNAL "HAL STM32_ONEWIRE for nanoFramework.Devices.OneWire") +endif() + +if(NF_FEATURE_HAS_SDCARD) + set(HAL_USE_SDC_OPTION TRUE CACHE INTERNAL "HAL SDC for NF_FEATURE_HAS_SDCARD") +else() + set(HAL_USE_SDC_OPTION FALSE CACHE INTERNAL "HAL SDC for NF_FEATURE_HAS_SDCARD") +endif() + +if(NF_FEATURE_HAS_USB_MSD) + set(HAL_USBH_USE_MSDC_OPTION TRUE CACHE INTERNAL "HAL USBH_USE_MSD for NF_FEATURE_HAS_USB_MSD") +else() + set(HAL_USBH_USE_MSDC_OPTION FALSE CACHE INTERNAL "HAL USBH_USE_MSD for NF_FEATURE_HAS_USB_MSD") +endif() + +################################################################# +# manage dependent APIs required for some API namespaces +################################################################# + +# include nanoFramework.Runtime.Events API +if( API_nanoFramework.Devices.OneWire OR + API_System.Net OR + API_Windows.Devices.Gpio OR + API_Windows.Devices.SerialCommunication OR + API_Windows.Networking.Sockets OR + API_nanoFramework.Devices.Can OR + API_Windows.Storage) + + # these APIs requires nanoFramework.Runtime.Events + set(API_nanoFramework.Runtime.Events ON CACHE INTERNAL "enable of API_nanoFramework.Runtime.Events") + +endif() + +if(API_System.Net) + # manage inclusion of SNTP + if(NF_NETWORKING_SNTP) + set(API_nanoFramework.Networking.Sntp ON CACHE INTERNAL "enable API_nanoFramework.Networking.Sntp") + else() + set(API_nanoFramework.Networking.Sntp OFF CACHE INTERNAL "disable API_nanoFramework.Networking.Sntp") + endif() +endif() + + +################################################################# +# handles Networking support at HAL level + +if(USE_NETWORKING_OPTION) + set(HAL_USE_MAC_OPTION TRUE CACHE INTERNAL "HAL MAC for USE_NETWORKING_OPTION") + + if(NF_SECURITY_MBEDTLS) + message(STATUS "Support for networking enabled with security from mbedTLS") + elseif(RTOS_TI_SIMPLELINK_CHECK) + message(STATUS "Support for networking enabled with security") + else() + message(STATUS "Support for networking enabled WITHOUT security") + endif() + + # sanity check for missing configuration block option + # which is required for network + + if(NOT NF_FEATURE_HAS_CONFIG_BLOCK) + message(FATAL_ERROR "\n\nERROR: network build requires NF_FEATURE_HAS_CONFIG_BLOCK build option to be 'ON'. Make sure you have that on your cmake-variants or in the build command line.") + endif() + +else() + set(HAL_USE_MAC_OPTION FALSE CACHE INTERNAL "HAL MAC for USE_NETWORKING_OPTION") + message(STATUS "Support for networking IS NOT enabled") +endif() + +################################################################# + + +################################################################# +# enables filesysytem support in nanoCLR + +if(NF_FEATURE_HAS_SDCARD OR NF_FEATURE_HAS_USB_MSD) + set(USE_FILESYSTEM_OPTION TRUE CACHE INTERNAL "NF feature FILESYSTEM") +else() + set(USE_FILESYSTEM_OPTION FALSE CACHE INTERNAL "NF feature FILESYSTEM") +endif() + +################################################################# + + +################################################################# +# RTC (real time clock) (default is OFF so RTC is NOT included) +option(NF_FEATURE_RTC "option to use hardware RTC") + +if(NF_FEATURE_RTC) + set(HAL_USE_RTC_OPTION TRUE CACHE INTERNAL "NF feature RTC") +else() + set(HAL_USE_RTC_OPTION FALSE CACHE INTERNAL "NF feature RTC") +endif() + +################################################################# + +################################################################# +# CPU watchdog (default is ON so watchdog is included) +option(NF_FEATURE_WATCHDOG "option to use hardware watchdog" ON) + +if(NF_FEATURE_WATCHDOG) + set(HAL_USE_WDG_OPTION TRUE CACHE INTERNAL "NF feature watchdog") +else() + set(HAL_USE_WDG_OPTION FALSE CACHE INTERNAL "NF feature watchdog") +endif() + +################################################################# + +####################### +# ChibiOS +if(RTOS_CHIBIOS_CHECK) + + # Define base path for the class libraries + set(BASE_PATH_FOR_CLASS_LIBRARIES_MODULES "${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nanoCLR") + + add_subdirectory(targets/CMSIS-OS/ChibiOS) + add_subdirectory(targets/CMSIS-OS/common) + add_subdirectory(targets/CMSIS-OS/common/Include) + add_subdirectory(targets/CMSIS-OS/nanoBooter) + add_subdirectory(targets/CMSIS-OS/nanoCLR) + + # now add the subdirectory for the board + # try to find board in the targets folder + if(EXISTS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/${CHIBIOS_BOARD}) + + # board found + message(STATUS "Support for target board '${CHIBIOS_BOARD}' found") + message(STATUS "${CHIBIOS_BOARD_DEFINITIONS_LOCATION}") + + # add TARGET board directory + add_subdirectory("${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/${CHIBIOS_BOARD}") + + else() + + # try to find board in the Community targets folder + if(EXISTS ${PROJECT_SOURCE_DIR}/targets-community/CMSIS-OS/ChibiOS/${CHIBIOS_BOARD}) + # board found + message(STATUS "Support for target board '${CHIBIOS_BOARD}' found in Community targets") + message(STATUS "${CHIBIOS_BOARD_DEFINITIONS_LOCATION}") + + # add TARGET board directory from Community + add_subdirectory("targets-community/CMSIS-OS/ChibiOS/${CHIBIOS_BOARD}") + else() + # board NOT found in targets folder + # board NOT found in targets folder + message(FATAL_ERROR "\n\nSorry but support for ${CHIBIOS_BOARD} target is not available...\n\You can wait for that to be added or you might want to contribute and start working on a PR for that.\n\n") + endif() + + endif() + +####################### +# FreeRTOS_ESP32 +elseif(RTOS_FREERTOS_ESP32_CHECK) + + if("${TARGET_SERIES}" STREQUAL "ESP32") + message(STATUS "Platform ESP32 target board: ${ESP32_BOARD}") + + # check watchdog feature + # EPS32 build has watchdog enabled by default, so setting it to OFF doens't make sense + # becuase the build system can't honour that preference + if(NOT NF_FEATURE_WATCHDOG) + message(FATAL_ERROR "\n\nESP32 watchdog is enabled by default in so you can't have the NF_FEATURE_WATCHDOG option set to OFF.\n\n") + endif() + + # Define base path for the class libraries + set(BASE_PATH_FOR_CLASS_LIBRARIES_MODULES "${PROJECT_SOURCE_DIR}/targets/FreeRTOS_ESP32/${ESP32_BOARD}/nanoCLR") + + add_subdirectory(targets/FreeRTOS_ESP32) + + # set target base location + set(TARGET_BASE_LOCATION "${PROJECT_SOURCE_DIR}/targets/FreeRTOS_ESP32/${ESP32_BOARD}") + add_subdirectory(targets/FreeRTOS_ESP32/${ESP32_BOARD}) + + endif() + +####################### +# TI_SIMPLELINK +elseif(RTOS_TI_SIMPLELINK_CHECK) + + add_subdirectory(targets/TI-SimpleLink) + +endif() diff --git a/source/native/nf-interpreter/CMakeSettings.SAMPLE.json b/source/native/nf-interpreter/CMakeSettings.SAMPLE.json new file mode 100644 index 00000000..a18ff205 --- /dev/null +++ b/source/native/nf-interpreter/CMakeSettings.SAMPLE.json @@ -0,0 +1,519 @@ +{ + "configurations": [ + { + "name": "ESP32", + "generator": "Ninja", + "configurationType": "Debug", + "inheritEnvironments": [ "gcc-arm" ], + "environments": [ { "PATH": "C:\\Windows\\system32;${env.PATH}" } ], + "buildRoot": "${workspaceRoot}/Build\\${name}", + "installRoot": "${workspaceRoot}/Build/install/${name}", + "cmakeCommandArgs": "", + "buildCommandArgs": "-v", + "ctestCommandArgs": "", + "intelliSenseMode": "linux-gcc-arm", + "variables": [ + { + "name": "EXECUTABLE_OUTPUT_PATH", + "value": "${workspaceRoot}/Build/${name}", + "type": "PATH" + }, + { + "name": "ESP32_TOOLCHAIN_PATH", + "value": "C:/ESP32_TOOLS", + "type": "PATH" + }, + { + "name": "TOOLCHAIN_PREFIX", + "value": "C:/ESP32_TOOLS", + "type": "PATH" + }, + { + "name": "ESP32_IDF_PATH", + "value": "C:/ESP32_TOOLS/esp-idf-v3.3", + "type": "PATH" + }, + { + "name": "ESP32_LIBS_PATH", + "value": "C:/ESP32_TOOLS/libs-v3.3", + "type": "PATH" + }, + { + "name": "CMAKE_SYSTEM_NAME", + "value": "Generic", + "type": "STRING" + }, + { + "name": "GIT_EXECUTABLE", + "value": "${env.VSINSTALLDIR}/Common7/IDE/CommonExtensions/Microsoft/TeamFoundation/Team Explorer/Git/cmd/git.exe", + "type": "FILEPATH" + }, + { + "name": "GIT_VERSION_STRING", + "value": "2.19.0", + "type": "STRING" + }, + { + "name": "TARGET_SERIES", + "value": "ESP32", + "type": "STRING" + }, + { + "name": "ESP32_BOARD", + "value": "ESP32_WROOM_32", + "type": "STRING" + }, + { + "name": "USE_RNG", + "value": "True", + "type": "BOOL" + }, + { + "name": "TARGET_LIGHT_MATH", + "value": "FALSE", + "type": "BOOL" + }, + { + "name": "TARGET_DP_FLOATINGPOINT", + "value": "FALSE", + "type": "BOOL" + }, + { + "name": "TARGET_SUPPORT_ANY_BASE_CONVERSION", + "value": "FALSE", + "type": "BOOL" + }, + { + "name": "RTOS", + "value": "FREERTOS_ESP32", + "type": "STRING" + }, + { + "name": "NF_BUILD_RTM", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "NF_WP_TRACE_ERRORS", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "NF_WP_TRACE_HEADERS", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "NF_WP_TRACE_STATE", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "NF_WP_TRACE_NODATA", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "NF_WP_TRACE_ALL", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "NF_WP_IMPLEMENTS_CRC32", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "NF_FEATURE_DEBUGGER", + "value": "True", + "type": "BOOL" + }, + { + "name": "NF_FEATURE_RTC", + "value": "True", + "type": "BOOL" + }, + { + "name": "NF_FEATURE_USE_APPDOMAINS", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "NF_FEATURE_WATCHDOG", + "value": "True", + "type": "BOOL" + }, + { + "name": "NF_FEATURE_HAS_CONFIG_BLOCK", + "value": "True", + "type": "BOOL" + }, + { + "name": "NF_PLATFORM_NO_CLR_TRACE", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "NF_CLR_NO_IL_INLINE", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "NF_INTEROP_ASSEMBLIES", + "value": "False", + "type": "BOOL" + }, + { + "name": "NF_NETWORKING_SNTP", + "value": "True", + "type": "BOOL" + }, + { + "name": "NF_SECURITY_MBEDTLS", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "API_nanoFramework.Devices.OneWire", + "value": "True", + "type": "BOOL" + }, + { + "name": "API_System.Math", + "value": "True", + "type": "BOOL" + }, + { + "name": "API_nanoFramework.ResourceManager", + "value": "True", + "type": "BOOL" + }, + { + "name": "API_System.Net", + "value": "True", + "type": "BOOL" + }, + { + "name": "API_Windows.Devices.Adc", + "value": "True", + "type": "BOOL" + }, + { + "name": "API_System.Devices.Dac", + "value": "False", + "type": "BOOL" + }, + { + "name": "API_Windows.Devices.Gpio", + "value": "True", + "type": "BOOL" + }, + { + "name": "API_Windows.Devices.I2c", + "value": "True", + "type": "BOOL" + }, + { + "name": "API_Windows.Devices.Pwm", + "value": "True", + "type": "BOOL" + }, + { + "name": "API_Windows.Devices.SerialCommunication", + "value": "True", + "type": "BOOL" + }, + { + "name": "API_Windows.Devices.Spi", + "value": "True", + "type": "BOOL" + }, + { + "name": "API_Windows.Devices.Wifi", + "value": "True", + "type": "BOOL" + }, + { + "name": "API_Windows.Networking.Sockets", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "API_Windows.Storage", + "value": "True", + "type": "BOOL" + }, + { + "name": "API_Hardware.Esp32", + "value": "True", + "type": "BOOL" + }, + { + "name": "NF_FEATURE_USE_SPIFFS", + "value": "False", + "type": "BOOL" + }, + { + "name": "NF_FEATURE_HAS_SDCARD", + "value": "True", + "type": "BOOL" + } + ] + }, + { + "name": "STM769IDiscovery", + "generator": "Ninja", + "configurationType": "Debug", + "inheritEnvironments": [ "gcc-arm" ], + "environments": [ { "PATH": "C:\\Windows\\system32;${env.PATH}" } ], + "buildRoot": "${env.nfRoot}Build/${name}", + "installRoot": "${workspaceRoot}/Build/install/${name}", + "cmakeCommandArgs": "", + "buildCommandArgs": "-v", + "ctestCommandArgs": "", + "intelliSenseMode": "linux-gcc-arm", + "variables": [ + { + "name": "EXECUTABLE_OUTPUT_PATH", + "value": "${workspaceRoot}/Build/${name}", + "type": "STRING" + }, + { + "name": "TOOLCHAIN_PREFIX", + "value": "${env.GNU_GCC_TOOLCHAIN_PATH}", + "type": "PATH" + }, + { + "name": "CMAKE_SYSTEM_NAME", + "value": "Generic", + "type": "STRING" + }, + { + "name": "TARGET_SERIES", + "value": "STM32F7xx", + "type": "STRING" + }, + { + "name": "CHIBIOS_BOARD", + "value": "ST_STM32F769I_DISCOVERY", + "type": "STRING" + }, + { + "name": "CHIBIOS_SOURCE", + "value": "C:/usr/src/NanoFramework/ChibiOS", + "type": "PATH" + }, + { + "name": "CHIBIOS_VERSION", + "value": "", + "type": "STRING" + }, + { + "name": "USE_RNG", + "value": "ON", + "type": "BOOL" + }, + { + "name": "TARGET_LIGHT_MATH", + "value": "FALSE", + "type": "BOOL" + }, + { + "name": "TARGET_DP_FLOATINGPOINT", + "value": "FALSE", + "type": "BOOL" + }, + { + "name": "TARGET_SUPPORT_ANY_BASE_CONVERSION", + "value": "ON", + "type": "BOOL" + }, + { + "name": "TOOL_HEX2DFU_PREFIX", + "value": "${env.HEX2DFU_PATH}", + "type": "PATH" + }, + { + "name": "RTOS", + "value": "CHIBIOS", + "type": "STRING" + }, + { + "name": "SWO_OUTPUT_OPTION", + "value": "TRUE", + "type": "BOOL" + }, + { + "name": "NF_BUILD_RTM", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "NF_WP_TRACE_ERRORS", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "NF_WP_TRACE_HEADERS", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "NF_WP_TRACE_STATE", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "NF_WP_TRACE_NODATA", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "NF_WP_TRACE_ALL", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "NF_WP_IMPLEMENTS_CRC32", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "NF_FEATURE_DEBUGGER", + "value": "ON", + "type": "BOOL" + }, + { + "name": "NF_FEATURE_RTC", + "value": "ON", + "type": "BOOL" + }, + { + "name": "NF_FEATURE_USE_APPDOMAINS", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "NF_FEATURE_WATCHDOG", + "value": "ON", + "type": "BOOL" + }, + { + "name": "NF_FEATURE_HAS_CONFIG_BLOCK", + "value": "ON", + "type": "BOOL" + }, + { + "name": "NF_FEATURE_HAS_SDCARD", + "value": "ON", + "type": "BOOL" + }, + { + "name": "NF_PLATFORM_NO_CLR_TRACE", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "NF_CLR_NO_IL_INLINE", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "NF_INTEROP_ASSEMBLIES", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "NF_NETWORKING_SNTP", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "NF_SECURITY_MBEDTLS", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "MBEDTLS_SOURCE", + "value": "", + "type": "PATH" + }, + { + "name": "API_nanoFramework.Devices.OneWire", + "value": "True", + "type": "BOOL" + }, + { + "name": "API_System.Math", + "value": "ON", + "type": "BOOL" + }, + { + "name": "API_System.Net", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "API_Windows.Devices.Adc", + "value": "True", + "type": "BOOL" + }, + { + "name": "API_System.Devices.Dac", + "value": "False", + "type": "BOOL" + }, + { + "name": "API_Windows.Devices.Gpio", + "value": "True", + "type": "BOOL" + }, + { + "name": "API_Windows.Devices.I2c", + "value": "True", + "type": "BOOL" + }, + { + "name": "API_Windows.Devices.Pwm", + "value": "True", + "type": "BOOL" + }, + { + "name": "API_Windows.Devices.SerialCommunication", + "value": "True", + "type": "BOOL" + }, + { + "name": "API_Windows.Devices.Spi", + "value": "True", + "type": "BOOL" + }, + { + "name": "API_Windows.Networking.Sockets", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "API_Windows.Storage", + "value": "True", + "type": "BOOL" + }, + { + "name": "API_nanoFramework.Devices.Can", + "value": "True", + "type": "BOOL" + }, + { + "name": "API_Hardware.Esp32", + "value": "OFF", + "type": "BOOL" + }, + { + "name": "API_Hardware.Stm32", + "value": "True", + "type": "BOOL" + } + ] + } + ] +} \ No newline at end of file diff --git a/source/native/nf-interpreter/CMakeSettings.json b/source/native/nf-interpreter/CMakeSettings.json new file mode 100644 index 00000000..4f1b76b0 --- /dev/null +++ b/source/native/nf-interpreter/CMakeSettings.json @@ -0,0 +1,460 @@ +{ + "configurations": [ + { + "name": "STM769IDiscovery", + "generator": "Ninja", + "configurationType": "Debug", + "inheritEnvironments": [ + "gcc-arm" + ], + "environments": [ + { + "PATH": "C:\\Windows\\system32;${env.PATH}" // Work around for Ninja not finding Cmd.exe with add_custom_command + } + ], + "buildRoot": "${env.nfRoot}Build/${name}", + "installRoot": "${workspaceRoot}/Build/install/${name}", + "cmakeCommandArgs": "", + "buildCommandArgs": "-v", + "ctestCommandArgs": "", + "intelliSenseMode": "linux-gcc-arm", + "variables": [ + { + "name": "EXECUTABLE_OUTPUT_PATH", + "value": "${workspaceRoot}/Build/${name}" + }, + { + "name": "TOOLCHAIN_PREFIX:PATH", + "value": "${env.GNU_GCC_TOOLCHAIN_PATH}" + }, + { + "name": "CMAKE_SYSTEM_NAME", + "value": "Generic" + }, + { + "name": "GIT_EXECUTABLE", + "value": "${env.VSINSTALLDIR}/Common7/IDE/CommonExtensions/Microsoft/TeamFoundation/Team Explorer/Git/cmd/git.exe" + }, + { + "name": "GIT_VERSION_STRING", + "value": "2.19.0" + }, + { + "name": "TARGET_SERIES:STRING", + "value": "STM32F7xx" + }, + { + "name": "CHIBIOS_BOARD:STRING", + "value": "ST_STM32F769I_DISCOVERY" + }, + { + "name": "CHIBIOS_SOURCE:PATH", // manually download, problems at the moment with value="" which forces a auto copy; causes failure with access denied at build? ( on .git directory) + "value": "C:/usr/src/NanoFramework/ChibiOS" + }, + { + "name": "CHIBIOS_VERSION", // default blank, set to specific version ( Not working with Visual Studio, clone and checkout specific manually) + "value": "" + }, + { + "name": "USE_RNG:BOOL", //option to enable use of true random generator hardware block + "value": "ON" + }, + { + "name": "TARGET_LIGHT_MATH:BOOL", //option to build without complex math function + "value": "FALSE" + }, + { + "name": "TARGET_DP_FLOATINGPOINT:BOOL", + "value": "FALSE" + }, + { + "name": "TARGET_SUPPORT_ANY_BASE_CONVERSION:BOOL", //"Option for string conversion to value from base 10 and partial for 16" + "value": "ON" + }, + { + "name": "TOOL_HEX2DFU_PREFIX:PATH", //"PATH for HEX TOOL" + "value": "${env.HEX2DFU_PATH}" + }, + { + "name": "RTOS:STRING", //"Selected Operating system + "value": "CHIBIOS" + }, + { + "name": "SWO_OUTPUT_OPTION:BOOL", // Single Wire Output Option + "value": "TRUE" + }, + { + "name": "NF_BUILD_RTM:BOOL", // OFF-default-ON-to-enable-RTM-build + "value": "OFF" + }, + { + "name": "NF_WP_TRACE_ERRORS:BOOL", //OFF-default-ON-to-enable-trace-error-messages-wire-protocol + "value": "OFF" + }, + { + "name": "NF_WP_TRACE_HEADERS:BOOL", //OFF-default-ON-to-enable-trace-header-messages-wire-protocol + "value": "OFF" + }, + { + "name": "NF_WP_TRACE_STATE:BOOL", //OFF-default-ON-to-enable-trace-state-messages-wire-protocol + "value": "OFF" + }, + { + "name": "NF_WP_TRACE_NODATA:BOOL", //OFF-default-ON-to-enable-trace-no-data-messages-wire-protocol + "value": "OFF" + }, + { + "name": "NF_WP_TRACE_ALL:BOOL", //OFF-default-ON-to-enable-trace-all-messages-wire-protocol + "value": "OFF" + }, + { + "name": "NF_WP_IMPLEMENTS_CRC32:BOOL", //OFF-default-ON-to-enable-CRC32-wire-protocol + "value": "OFF" + }, + { + "name": "NF_FEATURE_DEBUGGER:BOOL", //OFF-default-ON-to-include-managed-app-debugging-capability + "value": "OFF" + }, + { + "name": "NF_FEATURE_RTC:BOOL", //OFF-default-ON-to-enable-hardware-RTC + "value": "ON" + }, + { + "name": "NF_FEATURE_USE_APPDOMAINS:BOOL", //OFF-default-ON-to-enable-support-for-Application-Domains + "value": "OFF" + }, + { + "name": "NF_FEATURE_WATCHDOG:BOOL", //ON-to-enable-hardware-watchdog-ON-is-default + "value": "ON" + }, + { + "name": "NF_FEATURE_HAS_CONFIG_BLOCK:BOOL", //OFF-default-ON-to-enable-configuration-block-storage + "value": "ON" + }, + { + "name": "NF_FEATURE_HAS_SDCARD:BOOL", //OFF-default-ON-to-enable-sd-card + "value": "ON" + }, + { + "name": "NF_PLATFORM_NO_CLR_TRACE:BOOL", //OFF-default-ON-to-disable-all-trace-on-CLR + "value": "OFF" + }, + { + "name": "NF_CLR_NO_IL_INLINE:BOOL", //OFF-default-ON-to-disable-CLR-IL-inlining + "value": "OFF" + }, + { + "name": "NF_INTEROP_ASSEMBLIES:BOOL", //OFF-default-ON-to-disable-CLR-IL-inlining + "value": "OFF" + }, + { + "name": "NF_NETWORKING_SNTP:BOOL", //ON-default-to-add-SNTP-client-requires-networking + "value": "ON" + }, + { + "name": "NF_SECURITY_MBEDTLS:BOOL", //OFF-default-ON-to-add-network-security-from-mbedTLS + "value": "ON" + }, + { + "name": "MBEDTLS_SOURCE:PATH", //path-to-mbedtls-source-mind-the-forward-slashes + "value": "" + }, + // LIBRARIES + { + "name": "API_nanoFramework.Devices.OneWire:BOOL", //OFF-default-ON-to-add-this-API + "value": "ON" + }, + { + "name": "API_System.Math:BOOL", //OFF-default-ON-to-add-this-API + "value": "ON" + }, + { + "name": "API_System.Net:BOOL", //OFF-default-ON-to-add-this-API + "value": "ON" + }, + { + "name": "API_Windows.Devices.Adc:BOOL", //OFF-default-ON-to-add-this-API + "value": "ON" + }, + { + "name": "API_System.Devices.Dac:BOOL", //OFF-default-ON-to-add-this-API + "value": "ON" + }, + { + "name": "API_Windows.Devices.Gpio:BOOL", //OFF-default-ON-to-add-this-API + "value": "ON" + }, + { + "name": "API_Windows.Devices.I2c:BOOL", //OFF-default-ON-to-add-this-API + "value": "ON" + }, + { + "name": "API_Windows.Devices.Pwm:BOOL", //OFF-default-ON-to-add-this-API + "value": "ON" + }, + { + "name": "API_Windows.Devices.SerialCommunication:BOOL", //OFF-default-ON-to-add-this-API + "value": "ON" + }, + { + "name": "API_Windows.Devices.Spi:BOOL", //OFF-default-ON-to-add-this-API + "value": "ON" + }, + { + "name": "API_Windows.Networking.Sockets:BOOL", //OFF-default-ON-to-add-this-API + "value": "OFF" + }, + { + "name": "API_Windows.Storage:BOOL", //OFF-default-ON-to-add-this-API + "value": "ON" + }, + { + "name": "API_nanoFramework.Devices.Can:BOOL", //OFF-default-ON-to-add-this-API + "value": "ON" + }, + { + "name": "API_Hardware.Esp32:BOOL", //OFF-default-ON-to-add-this-API + "value": "OFF" + }, + { + "name": "API_Hardware.Stm32:BOOL", //OFF-default-ON-to-add-this-API + "value": "ON" + } + ] + }, + { + "name": "ESP32", + "generator": "Ninja", + "configurationType": "Debug", + "inheritEnvironments": [ + "gcc-arm" + ], + "environments": [ + { + // Work around for Ninja not finding Cmd.exe with add_custom_command + "PATH": "C:\\Windows\\system32;C:\\Program Files\\Espressif\\ESP-IDF Tools\\mconf-idf;c:\\python27;${env.PATH}", + + // ESP32 paths set up in environment so we can use in variables + "ESP32_IDF_VERSION": "v3.3", + "ESP32_TOOLS": "C:\\ESP32_TOOLS", + "ESP32_IDF": "${env.ESP32_TOOLS}\\esp-idf-${env.ESP32_IDF_VERSION}", + "ESP32_LIB": "${env.ESP32_TOOLS}\\libs-${env.ESP32_IDF_VERSION}", + "ESP32_MBEDTLS_SOURCE": "${env.ESP32_IDF}/Components/mbedtls/mbedtls", + + "IDF_PATH": "${env.ESP32_IDF}" + } + ], + "buildRoot": "${workspaceRoot}/Build\\${name}", + "installRoot": "${workspaceRoot}/Build/install/${name}", + "cmakeCommandArgs": "", + "buildCommandArgs": "-v", + "ctestCommandArgs": "", + "intelliSenseMode": "linux-gcc-arm", + "variables": [ + { + "name": "EXECUTABLE_OUTPUT_PATH", + "value": "${workspaceRoot}/Build/${name}" + }, + { + "name": "ESP32_TOOLCHAIN_PATH:PATH", + "value": "${env.ESP32_TOOLS}" + }, + { + "name": "TOOLCHAIN_PREFIX:PATH", + "value": "${env.ESP32_TOOLS}" + }, + { + "name": "ESP32_IDF_PATH:PATH", + "value": "${env.ESP32_IDF}" + }, + { + "name": "ESP32_LIBS_PATH:PATH", + "value": "${env.ESP32_LIB}" + }, + { + "name": "CMAKE_SYSTEM_NAME:STRING", + "value": "Generic" + }, + { + "name": "GIT_EXECUTABLE:FILEPATH", + "value": "${env.VSINSTALLDIR}/Common7/IDE/CommonExtensions/Microsoft/TeamFoundation/Team Explorer/Git/cmd/git.exe" + }, + { + "name": "GIT_VERSION_STRING:STRING", + "value": "2.19.0" + }, + { + "name": "TARGET_SERIES:STRING", + "value": "ESP32" + }, + { + "name": "ESP32_BOARD:STRING", + "value": "ESP32_WROOM_32" + }, + { + "name": "USE_RNG:BOOL", //option to enable use of true random generator hardware block + "value": "ON" + }, + { + "name": "TARGET_LIGHT_MATH:BOOL", //option to build without complex math function + "value": "FALSE" + }, + { + "name": "TARGET_DP_FLOATINGPOINT:BOOL", + "value": "TRUE" + }, + { + "name": "TARGET_SUPPORT_ANY_BASE_CONVERSION:BOOL", //"Option for string conversion to value from base 10 and partial for 16" + "value": "FALSE" + }, + { + "name": "RTOS:STRING", //"Selected Operating system + "value": "FREERTOS_ESP32" + }, + { + "name": "NF_BUILD_RTM:BOOL", // OFF-default-ON-to-enable-RTM-build + "value": "OFF" + }, + { + "name": "NF_WP_TRACE_ERRORS:BOOL", //OFF-default-ON-to-enable-trace-error-messages-wire-protocol + "value": "OFF" + }, + { + "name": "NF_WP_TRACE_HEADERS:BOOL", //OFF-default-ON-to-enable-trace-header-messages-wire-protocol + "value": "OFF" + }, + { + "name": "NF_WP_TRACE_STATE:BOOL", //OFF-default-ON-to-enable-trace-state-messages-wire-protocol + "value": "OFF" + }, + { + "name": "NF_WP_TRACE_NODATA:BOOL", //OFF-default-ON-to-enable-trace-no-data-messages-wire-protocol + "value": "OFF" + }, + { + "name": "NF_WP_TRACE_ALL:BOOL", //OFF-default-ON-to-enable-trace-all-messages-wire-protocol + "value": "OFF" + }, + { + "name": "NF_WP_IMPLEMENTS_CRC32:BOOL", //OFF-default-ON-to-enable-CRC32-wire-protocol + "value": "OFF" + }, + { + "name": "NF_FEATURE_DEBUGGER:BOOL", //OFF-default-ON-to-include-managed-app-debugging-capability + "value": "ON" + }, + { + "name": "NF_FEATURE_RTC:BOOL", //OFF-default-ON-to-enable-hardware-RTC + "value": "ON" + }, + { + "name": "NF_FEATURE_USE_APPDOMAINS:BOOL", //OFF-default-ON-to-enable-support-for-Application-Domains + "value": "OFF" + }, + { + "name": "NF_FEATURE_WATCHDOG:BOOL", //ON-to-enable-hardware-watchdog-ON-is-default + "value": "ON" + }, + { + "name": "NF_FEATURE_HAS_CONFIG_BLOCK:BOOL", //OFF-default-ON-to-enable-configuration-block-storage + "value": "ON" + }, + { + "name": "NF_PLATFORM_NO_CLR_TRACE:BOOL", //OFF-default-ON-to-disable-all-trace-on-CLR + "value": "OFF" + }, + { + "name": "NF_CLR_NO_IL_INLINE:BOOL", //OFF-default-ON-to-disable-CLR-IL-inlining + "value": "OFF" + }, + { + "name": "NF_INTEROP_ASSEMBLIES:BOOL", //OFF-default-ON-to-disable-CLR-IL-inlining + "value": "OFF" + }, + { + "name": "NF_NETWORKING_SNTP:BOOL", //ON-default-to-add-SNTP-client-requires-networking + "value": "ON" + }, + { + "name": "NF_SECURITY_MBEDTLS:BOOL", + "value": "ON" + }, + { + "name": "MBEDTLS_SOURCE:PATH", //path-to-mbedtls-source-mind-the-forward-slashes + "value": "${env.ESP32_MBEDTLS_SOURCE}" + }, + // LIBRARIES + { + "name": "API_nanoFramework.Devices.OneWire:BOOL", //OFF-default-ON-to-add-this-API + "value": "ON" + }, + { + "name": "API_System.Math:BOOL", //OFF-default-ON-to-add-this-API + "value": "ON" + }, + { + "name": "API_System.Net:BOOL", //OFF-default-ON-to-add-this-API + "value": "ON" + }, + { + "name": "API_nanoFramework.ResourceManager:BOOL", + "value": "ON" + }, + { + "name": "API_Windows.Devices.Adc:BOOL", //OFF-default-ON-to-add-this-API + "value": "ON" + }, + { + "name": "API_System.Devices.Dac:BOOL", //OFF-default-ON-to-add-this-API + "value": "ON" + }, + { + "name": "API_Windows.Devices.Gpio:BOOL", //OFF-default-ON-to-add-this-API + "value": "ON" + }, + { + "name": "API_Windows.Devices.I2c:BOOL", //OFF-default-ON-to-add-this-API + "value": "ON" + }, + { + "name": "API_Windows.Devices.Pwm:BOOL", //OFF-default-ON-to-add-this-API + "value": "ON" + }, + { + "name": "API_Windows.Devices.SerialCommunication:BOOL", //OFF-default-ON-to-add-this-API + "value": "ON" + }, + { + "name": "API_Windows.Devices.Spi:BOOL", //OFF-default-ON-to-add-this-API + "value": "ON" + }, + { + "name": "API_Windows.Devices.Wifi:BOOL", + "value": "True" + }, + { + "name": "API_Windows.Networking.Sockets:BOOL", //OFF-default-ON-to-add-this-API + "value": "OFF" + }, + { + "name": "API_Windows.Storage:BOOL", //OFF-default-ON-to-add-this-API + "value": "ON" + }, + { + "name": "API_Hardware.Esp32:BOOL", //OFF-default-ON-to-add-this-API + "value": "ON" + }, + { + "name": "NF_FEATURE_USE_SPIFFS", + "value": "False", + "type": "BOOL" + }, + { + "name": "NF_FEATURE_HAS_SDCARD", + "value": "True", + "type": "BOOL" + } + ] + } + ] +} diff --git a/source/native/nf-interpreter/InteropAssemblies/CLR_RT_InteropAssembliesTable.cpp.in b/source/native/nf-interpreter/InteropAssemblies/CLR_RT_InteropAssembliesTable.cpp.in new file mode 100644 index 00000000..78ae4af5 --- /dev/null +++ b/source/native/nf-interpreter/InteropAssemblies/CLR_RT_InteropAssembliesTable.cpp.in @@ -0,0 +1,23 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#include + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_mscorlib; +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Runtime_Native; +@CLR_RT_NativeAssemblyDataDeclarations@ + +const CLR_RT_NativeAssemblyData *g_CLR_InteropAssembliesNativeData[] = +{ + &g_CLR_AssemblyNative_mscorlib, + &g_CLR_AssemblyNative_nanoFramework_Runtime_Native, + @CLR_RT_NativeAssemblyDataTableEntries@ + NULL +}; diff --git a/source/native/nf-interpreter/InteropAssemblies/README.md b/source/native/nf-interpreter/InteropAssemblies/README.md new file mode 100644 index 00000000..ff8e08be --- /dev/null +++ b/source/native/nf-interpreter/InteropAssemblies/README.md @@ -0,0 +1,6 @@ + +This folder contains the configuration file for the Assemblies Table collection. + +It's a placeholder for the Interop assemblies source files. +The source files for each Interop assembly should be placed in it's own folder. +Anything inside this folder is ignored by an exception pattern in .gitignore file. diff --git a/source/native/nf-interpreter/LICENSE.md b/source/native/nf-interpreter/LICENSE.md new file mode 100644 index 00000000..44a0d2d8 --- /dev/null +++ b/source/native/nf-interpreter/LICENSE.md @@ -0,0 +1,192 @@ + + Apache License + Version 2.0, January 2004 + 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In no event and under no legal theory, + whether in tort (including negligence), contract, or otherwise, + unless required by applicable law (such as deliberate and grossly + negligent acts) or agreed to in writing, shall any Contributor be + liable to You for damages, including any direct, indirect, special, + incidental, or consequential damages of any character arising as a + result of this License or out of the use or inability to use the + Work (including but not limited to damages for loss of goodwill, + work stoppage, computer failure or malfunction, or any and all + other commercial damages or losses), even if such Contributor + has been advised of the possibility of such damages. + + 9. Accepting Warranty or Additional Liability. While redistributing + the Work or Derivative Works thereof, You may choose to offer, + and charge a fee for, acceptance of support, warranty, indemnity, + or other liability obligations and/or rights consistent with this + License. However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS + + + Copyright 2017 The nanoFramework project contributors + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. \ No newline at end of file diff --git a/source/native/nf-interpreter/README.md b/source/native/nf-interpreter/README.md new file mode 100644 index 00000000..a7ee1155 --- /dev/null +++ b/source/native/nf-interpreter/README.md @@ -0,0 +1,103 @@ +[![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0) [![#yourfirstpr](https://img.shields.io/badge/first--timers--only-friendly-blue.svg)](https://github.com/nanoframework/Home/blob/master/CONTRIBUTING.md) + [![Discord](https://img.shields.io/discord/478725473862549535.svg)](https://discord.gg/gCyBu8T) + + +![nanoFramework logo](https://github.com/nanoframework/Home/blob/master/resources/logo/nanoFramework-repo-logo.png) + +----- +Document Language: [English](README.md) | [中文简体](README.zh-cn.md) + +### Welcome to the **nanoFramework** Interpreter repository! + +This repo contains: + +* **nanoFramework** agnostic blocks + * [CLR](src/CLR) + * [HAL](src/HAL) + * [PAL](src/PAL) +* Target reference for CMSIS OS + * [ChibiOS](targets/CMSIS-OS/ChibiOS) + * Reference target boards + * [Mikrobus QUAIL](targets/CMSIS-OS/ChibiOS/MBN_QUAIL) + * [ST NUCLEO64 F091RC](targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC) + * [ST STM32F429I DISCOVERY](targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY) + * [ST STM32F769I DISCOVERY](targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY) + * [Wilderness Labs Netduino3 WiFi](targets/CMSIS-OS/ChibiOS/NETDIUNO3_WIFI) + * ChibiOS overlay for **nanoFramework** + * [STM32 1.Wire driver](targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_onewire) + * [STM32 CRC32 driver](targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_crc) + * [STM32 Flash driver](targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_flash) + * [STM32 Flexible Memory Controller driver](targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_fsmc) + * [STM32 Random number generator driver](targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_rng) +* Target reference for FreeRTOS + * [ESP32_WROOM_32](targets/FreeRTOS_ESP32/ESP32_WROOM_32) +* Target references for TI SimpleLink + * [TI CC3220SF_LAUNCHXL](targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL) +* Target reference for other OSes + * [Win32 OS (test project only at this time)](targets/os/win32) +* [CMake files for the build system](CMake) + + +## Build status + +| Component | Build Status | Build Status (develop) | +|:-|---|---| +| nanoBooter + nanoCLR | [![Build Status](https://dev.azure.com/nanoframework/nf-interpreter/_apis/build/status/nanoframework.nf-interpreter?branchName=master)](https://dev.azure.com/nanoframework/nf-interpreter/_build/latest?definitionId=34?branchName=master) | [![Build Status](https://dev.azure.com/nanoframework/nf-interpreter/_apis/build/status/nanoframework.nf-interpreter?branchName=develop)](https://dev.azure.com/nanoframework/nf-interpreter/_build/latest?definitionId=34?branchName=develop) | +| Win32 test project | [![Build Status](https://dev.azure.com/nanoframework/nf-interpreter/_apis/build/status/nanoframework.nf-interpreter?branchName=master)](https://dev.azure.com/nanoframework/nf-interpreter/_build/latest?definitionId=34?branchName=master) | [![Build Status](https://dev.azure.com/nanoframework/nf-interpreter/_apis/build/status/nanoframework.nf-interpreter?branchName=develop)](https://dev.azure.com/nanoframework/nf-interpreter/_build/latest?definitionId=34?branchName=develop) | + + +## Firmware for reference boards + + +Each of the following ZIP files contains the image files for nanoBooter and nanoCLR in various formats (HEX, BIN and DFU). They should be flashed in the target boards using an appropriate software utility. + +The **stable** versions are RTM builds with the smallest possible size. They include the latest stable version. The debugging feature is disabled and only minimal (or none) error messages. + +The **preview** versions are continuous builds of the reference targets. They include the latest version of all features and bug corrections. They also have the debugging feature enabled along with detailed error messages. + + +| Target | Stable | Preview | +|:-|---|---| +| ST_STM32F429I_DISCOVERY | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images/ST_STM32F429I_DISCOVERY/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images/ST_STM32F429I_DISCOVERY/_latestVersion) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-dev/ST_STM32F429I_DISCOVERY/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-dev/ST_STM32F429I_DISCOVERY/_latestVersion) | +| ST_NUCLEO64_F091RC | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images/ST_NUCLEO64_F091RC/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images/ST_NUCLEO64_F091RC/_latestVersion) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-dev/ST_NUCLEO64_F091RC/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-dev/ST_NUCLEO64_F091RC/_latestVersion) | +| ST_STM32F769I_DISCOVERY | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images/ST_STM32F769I_DISCOVERY/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images/ST_STM32F769I_DISCOVERY/_latestVersion) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-dev/ST_STM32F769I_DISCOVERY/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-dev/ST_STM32F769I_DISCOVERY/_latestVersion) | +| MBN_QUAIL | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images/MBN_QUAIL/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images/MBN_QUAIL/_latestVersion) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-dev/MBN_QUAIL/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-dev/MBN_QUAIL/_latestVersion) | +| NETDUINO3_WIFI | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images/NETDUINO3_WIFI/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images/NETDUINO3_WIFI/_latestVersion) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-dev/NETDUINO3_WIFI/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-dev/NETDUINO3_WIFI/_latestVersion) | +| ESP32_WROOM_32 | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images/ESP32_WROOM_32/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images/ESP32_WROOM_32/_latestVersion) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-dev/ESP32_WROOM_32/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-dev/ESP32_WROOM_32/_latestVersion) | +| TI_CC3220SF_LAUNCHXL | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images/TI_CC3220SF_LAUNCHXL/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images/TI_CC3220SF_LAUNCHXL/_latestVersion) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-dev/TI_CC3220SF_LAUNCHXL/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-dev/TI_CC3220SF_LAUNCHXL/_latestVersion) | + + +The above firmware builds include support for the class libraries and features marked below. + + +| Target | Gpio | Spi | I2c | Pwm | Adc | Dac | Serial | OneWire | Events | SWO | Networking | Large Heap | +|:-: |:-: |:-: |:-: |:-: |:-: |:-: |:-: |:-: |:-: |:-: |:-: |:-: | +| ST_STM32F429I_DISCOVERY | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | +| ST_NUCLEO64_F091RC | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | +| ST_STM32F769I_DISCOVERY | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| MBN_QUAIL | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | | +| NETDUINO3_WIFI | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | | +| ESP32_WROOM_32 | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | | +| TI_CC3220SF_LAUNCHXL | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | | :heavy_check_mark: | | :heavy_check_mark: | | + + +## Feedback and documentation + +For documentation, providing feedback, issues and finding out how to contribute please refer to the [Home repo](https://github.com/nanoframework/Home). + +Join our Discord community [here](https://discord.gg/gCyBu8T). + + +## Credits + +The list of contributors to this project can be found at [CONTRIBUTORS](https://github.com/nanoframework/Home/blob/master/CONTRIBUTORS.md). + + +## License + +The nanoFramework Interpreter is licensed under the [Apache 2.0 license](http://www.apache.org/licenses/LICENSE-2.0). + + +## Code of Conduct +This project has adopted the code of conduct defined by the [Contributor Covenant](CODE_OF_CONDUCT.md) +to clarify expected behavior in our community. diff --git a/source/native/nf-interpreter/README.zh-cn.md b/source/native/nf-interpreter/README.zh-cn.md new file mode 100644 index 00000000..7cdd04f7 --- /dev/null +++ b/source/native/nf-interpreter/README.zh-cn.md @@ -0,0 +1,101 @@ +[![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0) [![#yourfirstpr](https://img.shields.io/badge/first--timers--only-friendly-blue.svg)](https://github.com/nanoframework/Home/blob/master/CONTRIBUTING.md) + [![Discord](https://img.shields.io/discord/478725473862549535.svg)](https://discord.gg/gCyBu8T) + + +![nanoFramework logo](https://github.com/nanoframework/Home/blob/master/resources/logo/nanoFramework-repo-logo.png) + +----- +文档语言: [English](README.md) | [中文简体](README.zh-cn.md) + +### 欢迎使用 **nanoFramework** 解析器！ + +本库包括： + +* **nanoFramework** 核心板块 + * [CLR](src/CLR) + * [HAL](src/HAL) + * [PAL](src/PAL) +* CMSIS OS 移植 + * [ChibiOS](targets/CMSIS-OS/ChibiOS) + * 板卡移植 + * [Mikrobus QUAIL](targets/CMSIS-OS/ChibiOS/MBN_QUAIL) + * [ST NUCLEO64 F091RC](targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC) + * [ST STM32F429I DISCOVERY](targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY) + * [ST STM32F769I DISCOVERY](targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY) + * [Wilderness Labs Netduino3 WiFi](targets/CMSIS-OS/ChibiOS/NETDIUNO3_WIFI) + * ChibiOS 增强 **nanoFramework** + * [STM32 1.Wire driver](targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_onewire) + * [STM32 CRC32 driver](targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_crc) + * [STM32 Flash driver](targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_flash) + * [STM32 Flexible Memory Controller driver](targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_fsmc) + * [STM32 Random number generator driver](targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_rng) +* FreeRTOS 移植 + * [ESP32_WROOM_32](targets/FreeRTOS_ESP32/ESP32_WROOM_32) +* TI SimpleLink 移植 + * [TI CC3220SF_LAUNCHXL](targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL) +* 其它系统移植 + * [Win32 OS (test project only at this time)](targets/os/win32) +* [CMake 编译文件](CMake) + + +## 编译状态 + +| 组件 | 编译状态 | 编译状态（开发） | +|:-|---|---| +| nanoBooter + nanoCLR | [![Build Status](https://dev.azure.com/nanoframework/nf-interpreter/_apis/build/status/nanoframework.nf-interpreter?branchName=master)](https://dev.azure.com/nanoframework/nf-interpreter/_build/latest?definitionId=34?branchName=master) | [![Build Status](https://dev.azure.com/nanoframework/nf-interpreter/_apis/build/status/nanoframework.nf-interpreter?branchName=develop)](https://dev.azure.com/nanoframework/nf-interpreter/_build/latest?definitionId=34?branchName=develop) | +| Win32 test project | [![Build Status](https://dev.azure.com/nanoframework/nf-interpreter/_apis/build/status/nanoframework.nf-interpreter?branchName=master)](https://dev.azure.com/nanoframework/nf-interpreter/_build/latest?definitionId=34?branchName=master) | [![Build Status](https://dev.azure.com/nanoframework/nf-interpreter/_apis/build/status/nanoframework.nf-interpreter?branchName=develop)](https://dev.azure.com/nanoframework/nf-interpreter/_build/latest?definitionId=34?branchName=develop) | + + +## 评估板固件 + + +以下每个ZIP文件包括了nanoBooter和nanoCLR镜像（HEX，BIN，DFU）。可以使用相应烧写工具把它们写入目标板卡中。 + +**稳定** 版是RTM最小大小编译。它包含了最后稳定版本，关闭调试功能，仅有最少或没有错误信息。 +**预览** 版是目标板持续编译。它包含所有功能和错误修正的最后版本，也包括调试信息和详细错误信息。 + + +| 目标 | 稳定 | 预览 | +|:-|---|---| +| ST_STM32F429I_DISCOVERY | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images/ST_STM32F429I_DISCOVERY/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images/ST_STM32F429I_DISCOVERY/_latestVersion) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-dev/ST_STM32F429I_DISCOVERY/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-dev/ST_STM32F429I_DISCOVERY/_latestVersion) | +| ST_NUCLEO64_F091RC | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images/ST_NUCLEO64_F091RC/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images/ST_NUCLEO64_F091RC/_latestVersion) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-dev/ST_NUCLEO64_F091RC/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-dev/ST_NUCLEO64_F091RC/_latestVersion) | +| ST_STM32F769I_DISCOVERY | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images/ST_STM32F769I_DISCOVERY/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images/ST_STM32F769I_DISCOVERY/_latestVersion) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-dev/ST_STM32F769I_DISCOVERY/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-dev/ST_STM32F769I_DISCOVERY/_latestVersion) | +| MBN_QUAIL | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images/MBN_QUAIL/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images/MBN_QUAIL/_latestVersion) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-dev/MBN_QUAIL/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-dev/MBN_QUAIL/_latestVersion) | +| NETDUINO3_WIFI | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images/NETDUINO3_WIFI/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images/NETDUINO3_WIFI/_latestVersion) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-dev/NETDUINO3_WIFI/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-dev/NETDUINO3_WIFI/_latestVersion) | +| ESP32_WROOM_32 | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images/ESP32_WROOM_32/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images/ESP32_WROOM_32/_latestVersion) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-dev/ESP32_WROOM_32/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-dev/ESP32_WROOM_32/_latestVersion) | +| TI_CC3220SF_LAUNCHXL | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images/TI_CC3220SF_LAUNCHXL/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images/TI_CC3220SF_LAUNCHXL/_latestVersion) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-dev/TI_CC3220SF_LAUNCHXL/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-dev/TI_CC3220SF_LAUNCHXL/_latestVersion) | + + +以上固件支持以下类库和功能。 + + +| Target | Gpio | Spi | I2c | Pwm | Adc | Dac | Serial | OneWire | Events | SWO | Networking | Large Heap | +|:-: |:-: |:-: |:-: |:-: |:-: |:-: |:-: |:-: |:-: |:-: |:-: |:-: | +| ST_STM32F429I_DISCOVERY | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | +| ST_NUCLEO64_F091RC | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | +| ST_STM32F769I_DISCOVERY | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | +| MBN_QUAIL | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | | +| NETDUINO3_WIFI | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | | +| ESP32_WROOM_32 | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | | +| TI_CC3220SF_LAUNCHXL | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | | :heavy_check_mark: | | :heavy_check_mark: | | + + +## 文档反馈 + +有关文档、提供反馈、问题以及如何做出贡献的信息，请参阅 [Home repo](https://github.com/nanoframework/Home). + +加入我们的讨论社区 [here](https://discord.gg/gCyBu8T). + + +## Credits + +本项目贡献者可在 [CONTRIBUTORS](https://github.com/nanoframework/Home/blob/master/CONTRIBUTORS.md) 中找到。 + + +## 授权 + +nanoFramework 解析器基于 [Apache 2.0 license](http://www.apache.org/licenses/LICENSE-2.0) 授权。 + + +## 行为准则 +本项目采用了 [Contributor Covenant](CODE_OF_CONDUCT.md) 规范来阐明社区预期行为。 diff --git a/source/native/nf-interpreter/RunCmd.bat b/source/native/nf-interpreter/RunCmd.bat new file mode 100644 index 00000000..d998f942 --- /dev/null +++ b/source/native/nf-interpreter/RunCmd.bat @@ -0,0 +1,26 @@ + @echo off + REM Call with first parameter as timeout, number of seconds to delay after command finishes + REM Rest of parameters are the command to run and arguments to be passed to it + REM If timeout = 0, always wait for user input. timeout < 0, wait for user only if error + setlocal + set errwait=0 + set dly=%1 + if %1 lss 0 set errwait=1 & set /A dly=0-%1 + set _tail=%* + call set _tail=%%_tail:*%1=%% + %_tail% + if %ERRORLEVEL% neq 0 goto :cmderror + if %dly% equ 0 goto :waitforuser + +:tick + timeout %dly% + exit 0 + +:cmderror + Echo "Error %ERRORLEVEL% processing command" + if %errwait% equ 0 goto :tick +:waitforuser + pause + exit 0 + + diff --git a/source/native/nf-interpreter/SetNFRoot.bat b/source/native/nf-interpreter/SetNFRoot.bat new file mode 100644 index 00000000..91118ad5 --- /dev/null +++ b/source/native/nf-interpreter/SetNFRoot.bat @@ -0,0 +1,132 @@ +@echo off +REM SetNFRoot - Find/Create and return short path for current directory +REM DAV 01APR19 +setlocal + +if %1.==. goto :set_path + +:check_opts +if /I %1==-h goto :help +if /I %1==-d set rmsubst=-d + +:set_path +set _mypath=%~dp0 +call :setshortpath %_mypath% +rem pushd %shortpath% +if [%rmsubst%]==[-d] goto :remsubst +goto :end + +:remsubst +set v=%shortpath:~0,2% +echo Remove subst of %mypath% on %v% +if [%rmsubst%]==[-d] subst /D %v% +endlocal & set "nfRoot=%_mypath%" +setx nfRoot %nfRoot% >nul +echo %nfRoot% +goto :eof + +:end +:: Clear %errorlevel% +call set _a=a > nul +endlocal & set "nfRoot=%shortpath%" +setx nfRoot %nfRoot% >nul +echo %nfRoot% +rem popd +::exit +goto :eof + +:: ============ Utility commands ===== + +:: === Help +:help +echo: +echo Usage: %0 [opt] +echo: +echo opt = -d Delete subst if exists +echo opt = -h Display this help message +echo: +echo Command line tool to find or create a short directory path +echo for the current directory using the subst command +echo: +goto :eof + +REM ========================================================== +REM Utility Functions +REM +REM Call to set a short path to try avoid overflowing 250 char file path limit +:setshortpath +set "mypath=%~1" +set shortpath=%mypath% +rem echo mypath = %_mypath% + +REM Are we already on short path? +set t=%mypath:~0,3% +if /I %t%==%mypath% goto :haveshortpath + +REM Not on short path - is there already a subst for it? +FOR /F "tokens=1,3" %%G IN ('subst') DO ( + if /I "%%H\"=="%mypath%" ( + set sdg=%%G + goto :foundsubst + ) +) +REM No subst short path found - create one +call :freedrive driveletter && goto :cont +echo ERROR: No free drive letter found, staying on original path +goto :haveshortpath + +:cont +echo Found free drive letter: %driveletter% 1>&2 +pushd %mypath% +subst %driveletter% . +popd +set shortpath=%driveletter%\ +echo Created new subst for %mypath% on %driveletter% 1>&2 +echo You can remove it with subst %driveletter% /D 1>&2 +goto :haveshortpath + +:foundsubst +set shortpath=%sdg:~0,3% +echo Using existing subst for %mypath% on %shortpath% 1>&2 +goto :haveshortpath + +:haveshortpath +echo Using short path %shortpath% for %mypath% 1>&2 +REM So now we have a short path if it was possible +goto :eof + +rem Finds a free drive letter. +rem +rem Parameters: +rem %1 = Output variable name. +rem +rem Example: +rem call :freedrive mydriveletter && goto :cont +rem echo ERROR: No free drive letter found. +rem goto :EOF +rem :cont +rem echo Found drive letter: %mydriveletter% +:freedrive +setlocal EnableDelayedExpansion +set exitcode=0 +set "output_var=%~1" +for %%i in (B,D,E,F,G,H,I,J,K,L,M,N,O,P,Q,R,S,T,U,V,W,X,Y,Z) do ( + set "drive=%%i:" + rem If 'subst' fails, the drive letter is already in use. + rem This way we can even detect optical drives that have a drive + rem letter but no media in them, a case that goes undetected when + rem using 'if exist'. + subst !drive! %SystemDrive%\ >nul + if !errorlevel! == 0 ( + subst !drive! /d >nul + goto :freedrive0 + ) +) +set exitcode=1 +set drive= +:freedrive0 +endlocal & set "%output_var%=%drive%" & exit /b %exitcode% + +:exit + +:eof diff --git a/source/native/nf-interpreter/VisualStudioDevelopment/CopyBuildOutput.cmd b/source/native/nf-interpreter/VisualStudioDevelopment/CopyBuildOutput.cmd new file mode 100644 index 00000000..4579ec18 --- /dev/null +++ b/source/native/nf-interpreter/VisualStudioDevelopment/CopyBuildOutput.cmd @@ -0,0 +1,19 @@ +Rem -------------------------------------------------------------------------------- +Rem -- Open a command prompt at your build target root to run the following commands +Rem -- For example +Rem -- Open a command prompt at "Build\" +Rem -------------------------------------------------------------------------------- + +copy nanobooter.elf ..\nanobooter.elf +"C:/Program Files (x86)/Microsoft Visual Studio/2017/Community/Linux/gcc_arm/bin/arm-none-eabi-objcopy.exe" -Oihex nanobooter.elf ..\nanobooter.hex +"C:/Program Files (x86)/Microsoft Visual Studio/2017/Community/Linux/gcc_arm/bin/arm-none-eabi-objcopy.exe" -Osrec nanobooter.elf ..\nanobooter.s19 +"C:/Program Files (x86)/Microsoft Visual Studio/2017/Community/Linux/gcc_arm/bin/arm-none-eabi-objcopy.exe" -Obinary nanobooter.elf ..\nanobooter.bin +"C:/Program Files (x86)/Microsoft Visual Studio/2017/Community/Linux/gcc_arm/bin/arm-none-eabi-objdump.exe" -d -EL -S nanobooter.elf > ..\nanobooter.lst +"C:/Program Files (x86)/Microsoft Visual Studio/2017/Community/Linux/gcc_arm/bin/arm-none-eabi-size.exe" nanobooter.elf > ..\nanobooter.size.txt + +copy nanoCLR.elf ..\nanoCLR.elf +"C:/Program Files (x86)/Microsoft Visual Studio/2017/Community/Linux/gcc_arm/bin/arm-none-eabi-objcopy.exe" -Oihex nanoCLR.elf ..\nanoCLR.hex +"C:/Program Files (x86)/Microsoft Visual Studio/2017/Community/Linux/gcc_arm/bin/arm-none-eabi-objcopy.exe" -Osrec nanoCLR.elf ..\nanoCLR.s19 +"C:/Program Files (x86)/Microsoft Visual Studio/2017/Community/Linux/gcc_arm/bin/arm-none-eabi-objcopy.exe" -Obinary nanoCLR.elf ..\nanoCLR.bin +"C:/Program Files (x86)/Microsoft Visual Studio/2017/Community/Linux/gcc_arm/bin/arm-none-eabi-objdump.exe" -d -EL -S nanoCLR.elf > ..\nanoCLR.lst +"C:/Program Files (x86)/Microsoft Visual Studio/2017/Community/Linux/gcc_arm/bin/arm-none-eabi-size.exe" nanoCLR.elf > ..\nanoCLR.size.txt diff --git a/source/native/nf-interpreter/VisualStudioDevelopment/README.md b/source/native/nf-interpreter/VisualStudioDevelopment/README.md new file mode 100644 index 00000000..b391c601 --- /dev/null +++ b/source/native/nf-interpreter/VisualStudioDevelopment/README.md @@ -0,0 +1,138 @@ +### Developing firmware for the nanoframework using Visual Studio 2017 community edition + +##### 🚧 IMPORTANT : The firmware build for Visual Studio is under construction. 🚧 +Some compromises were required to get this to a working stage. +I made a decision to put the code at the top level to reduce path length of files which caused warnings of the potential to overflow the command line. +>Hard coded paths are used to ensure it works with the current CMake coding and the Microsoft usage of CMake +>There are some issues with the CMakeSettings.json file with path separators. + +
+ + +### Directory structure for the project +Two top level directories have been created to support the development with Visual Studio. +* `c:\nanoFramework\nf-interpreter` +* `c:\nanoFramework_Tools` + +#### c:\nanoFramework\nf-interpreter +- The nf-interpreter repository is cloned to this directory. +###### c:\nanoFramework\nf-interpreter\Build +- This directory contains the build output, the files in here are transient. When the CMake cache is deleted, files in this directory are deleted. +The files in this directory are only visible when selecting "Show All Files". These files are not part of the GIT repository. +At the end of a successful build the build outputs are copied to the *\Build* directory. + +> - Note: It is sometimes necessary to delete the contents of these folders if Visual Studio misbehaves. +Using Visual Studio with CMake results in what appears to be inconsistencies at times. +Sometime the CMake server goes away, shutting down Visual Studio and restarting usually fixes the problem. +
+> - Note: After clearing the Cmake cache, on occassions the build/chibios_source directory is left empty or only containing the .git file +>due to some conflict. The current CMakeLists.txt file finds the directory and does not re-copy the code. +>It is necessary to manually delete the directory from file explorer and generate the cache for the copy to run. +>_ + +#### c:\nanoFramework_Tools\ + Manually create this directory to contain the following folders. +###### c:\nanoFramework_Tools\ChibiOS ++ Copy of the ChibiOS repository cloned from https://github.com/nanoframework/chibios.git + +###### C:\nanoFramework_Tools\Tools\openocd ++ Copy of the openocd installation http://www.freddiechopin.info/en/download/category/4-openocd ++ > Currently version 0.10.0 + +###### C:\nanoFramework_Tools\Tools\ ++ Place a copy of the hex2dfu.exe tool here + + + +### Example of the directory structure + +![](VSDevDirectoryStructure.png) + + +### Major configuration files + +##### CMakeSettings.json +> Configuration file used by Visual Studio. This is the standard configuration file for CMake development. +> This file can contain more than one configuration. In addition to setting the compiler +> toolchain, additional variables are defined to select the target hardware and operating system to build. +>###### Note: Work in progress +
+ +##### CMakeLists.txt +> This is the standard CMakeLists.txt file for the nf-intepreter + +
+ + +##### launch.vs.json +> Sets up the debugging environment using the gdbserver debugging via configurations. +> The example references the openocd application. + +
+ +#### Setup and Installation + +| Software Component | Notes | Link | +|:-|---|---| +| Visual Studio 2017 community edition |Linux development with C++| +|option|Visual C++ tools for Cmake and Linux +|option|Embedded and IoT Development|GCC version 6.3.1. December/2018 +|GCC Tool Chain - Version 8-2019-q3-update|GNU Arm Embedded Toolchain|https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads# + + +#### GCC Toolchain NOTES +> Version 6.3.1 installed by Visual Studio has a problem with fallthrough, Version 8, has a problem with structures ( an issue has been raised to fix this) + +The following GCC version has been download, installed and tested. +> GNU Arm Embedded Toolchain - Version 7-2018-q2-update + https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads# + +In CMakeSettings.json the following variables determine the build tool. + + { + "name": "TOOLCHAIN_PREFIX", + "value": "C:/Program Files (x86)/GNU Tools Arm Embedded/8 2019-q3-update" + // "value": "${env.GCCPATH}" // Standard Visual Studio Install of GCC 6.3.1 + }, + +
+#### Debugging + +The launch.vs.json file contains an example configuration for setup to debug the STM32769IDiscovery board. +Additonal configurations can be added, although the implementation of the options does not seem consistent with +the VSCODE version and some options do not appear to work properly. +Also, the whole system is a bit flakey. The openocd program is run as sub process of Visual Studio,and if it runs into problems the +system fails, and you must run up task manager to end the openocd.exe task listed as a process of Visual Studio. + + +#### Diagnosing problems with the debug and launch.vs.json + +You can get a better understanding of problems that may be occuring with the gdb/openocd debug setup. +In Visual Studio select the Command Window Ctrl+Alt+A, and turn on debug logging with the following command. + +`debug.midebuglog /On:c:\Temp\debug.log` + +Run a debugging session to collect data and turn it off with the following command. + +`debug.midebuglog /Off` + +This will give you a log of the operation and communications occuring. ( Good luck!) + + +__*An example snippet displays error for "Monitor reset halt ( not quite sure why?)*__ + + 8: (1976730) ->^done + 8: (1976730) <-1005-interpreter-exec console "monitor reset halt" + 8: (1976730) ->(gdb)` + 8: (1976741) ->&"\"monitor\" command not supported by this target.\n" + 8: (1976742) ->1005^error,msg="\"monitor\" command not supported by this target." + 8: (1976742) ->(gdb) + 8: (1976742) 1005: elapsed time 11 + 8: (1976742) <-1006-interpreter-exec console "monitor reset init" + 8: (1976742) ->&"\n" + 8: (1976742) ->^done + 8: (1976742) ->(gdb) + +#### Feedback + +If you are using this your feedback is greatly appreciated. Please join our [Discord community](https://discord.gg/gCyBu8T) and start chatting about this. diff --git a/source/native/nf-interpreter/VisualStudioDevelopment/VSDevDirectoryStructure.png b/source/native/nf-interpreter/VisualStudioDevelopment/VSDevDirectoryStructure.png new file mode 100644 index 00000000..10583bdd Binary files /dev/null and b/source/native/nf-interpreter/VisualStudioDevelopment/VSDevDirectoryStructure.png differ diff --git a/source/native/nf-interpreter/azure-pipelines-templates/build-chibios-stm32.yml b/source/native/nf-interpreter/azure-pipelines-templates/build-chibios-stm32.yml new file mode 100644 index 00000000..ce0cb6f2 --- /dev/null +++ b/source/native/nf-interpreter/azure-pipelines-templates/build-chibios-stm32.yml @@ -0,0 +1,27 @@ +# Copyright (c) 2018 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. + +parameters: + buildDirectory: '$(Build.SourcesDirectory)\build' + +steps: + + - task: CMake@1 + inputs: + cmakeArgs: '-G Ninja -DTOOLCHAIN_PREFIX=$(GNU_GCC_TOOLCHAIN_PATH) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_AssemblyVersion) -DCHIBIOS_BOARD=$(BoardName) $(BuildOptions) -DTOOL_HEX2DFU_PREFIX=$(HEX2DFU_PATH) ..' + workingDirectory: ${{ parameters.buildDirectory }} + displayName: Setup build with CMake and DFU + condition: eq(variables['NeedsDFU'], true) + + - task: CMake@1 + inputs: + cmakeArgs: '-G Ninja -DTOOLCHAIN_PREFIX=$(GNU_GCC_TOOLCHAIN_PATH) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_AssemblyVersion) -DCHIBIOS_BOARD=$(BoardName) $(BuildOptions) ..' + workingDirectory: ${{ parameters.buildDirectory }} + displayName: Setup build with CMake without DFU + condition: eq(variables['NeedsDFU'], false) + + - task: CMake@1 + inputs: + cmakeArgs: '--build ${{ parameters.buildDirectory }} --target all --config MinSizeRel' + workingDirectory: ${{ parameters.buildDirectory }} + displayName: Build with CMake diff --git a/source/native/nf-interpreter/azure-pipelines-templates/build-esp32.yml b/source/native/nf-interpreter/azure-pipelines-templates/build-esp32.yml new file mode 100644 index 00000000..52eb06cb --- /dev/null +++ b/source/native/nf-interpreter/azure-pipelines-templates/build-esp32.yml @@ -0,0 +1,68 @@ +# Copyright (c) 2018 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. + +parameters: + buildDirectory: '$(Build.SourcesDirectory)\build' + +steps: + - task: CMake@1 + inputs: + cmakeArgs: '-G Ninja -DTOOLCHAIN_PREFIX=$(ESP32_TOOLCHAIN_PATH) -DESP32_IDF_PATH=$(ESP32_IDF_PATH) -DESP32_LIBS_PATH=$(ESP32_LIBS_PATH) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_AssemblyVersion) -DESP32_BOARD=$(BoardName) $(BuildOptions) ..' + workingDirectory: ${{ parameters.buildDirectory }} + displayName: Setup build with CMake + + - task: CMake@1 + inputs: + cmakeArgs: '--build ${{ parameters.buildDirectory }} --target all --config MinSizeRel' + workingDirectory: ${{ parameters.buildDirectory }} + displayName: Build with CMake + + - task: PythonScript@0 + inputs: + scriptSource: 'filePath' + scriptPath: '$(Agent.TempDirectory)\ESP32_Tools\esp-idf-v3.3\components\esptool_py\esptool\esptool.py' + arguments: '--chip esp32 elf2image --flash_mode dio --flash_freq 40m --flash_size 4MB -o ${{ parameters.buildDirectory }}\nanoCLR.bin ${{ parameters.buildDirectory }}\targets\FreeRTOS_ESP32\$(BoardName)\nanoCLR.elf' + condition: succeeded() + displayName: Generate nanoCLR bin file for deployment + + # because of permission issues (the python script isn't allowed to write on the output folder) + # we need to perform these steps by calling directly the python scripts + - task: PythonScript@0 + inputs: + scriptSource: 'filePath' + scriptPath: '$(Agent.TempDirectory)\ESP32_Tools\esp-idf-v3.3\components\partition_table\gen_esp32part.py' + arguments: '--verify $(Build.SourcesDirectory)\targets\FreeRTOS_ESP32\$(BoardName)\IDF\partitions_nanoclr_16mb.csv ${{ parameters.buildDirectory }}\partitions_16mb.bin' + condition: succeeded() + displayName: Generate Esp32 Partition tables for 16MB flash + + - task: PythonScript@0 + inputs: + scriptSource: 'filePath' + scriptPath: '$(Agent.TempDirectory)\ESP32_Tools\esp-idf-v3.3\components\partition_table\gen_esp32part.py' + arguments: '--verify $(Build.SourcesDirectory)\targets\FreeRTOS_ESP32\$(BoardName)\IDF\partitions_nanoclr_8mb.csv ${{ parameters.buildDirectory }}\partitions_8mb.bin' + condition: succeeded() + displayName: Generate Esp32 Partition tables for 8MB flash + + - task: PythonScript@0 + inputs: + scriptSource: 'filePath' + scriptPath: '$(Agent.TempDirectory)\ESP32_Tools\esp-idf-v3.3\components\partition_table\gen_esp32part.py' + arguments: '--verify $(Build.SourcesDirectory)\targets\FreeRTOS_ESP32\$(BoardName)\IDF\partitions_nanoclr_4mb.csv ${{ parameters.buildDirectory }}\partitions_4mb.bin' + condition: succeeded() + displayName: Generate Esp32 Partition tables for 4MB flash + + - task: PythonScript@0 + inputs: + scriptSource: 'filePath' + scriptPath: '$(Agent.TempDirectory)\ESP32_Tools\esp-idf-v3.3\components\partition_table\gen_esp32part.py' + arguments: '--verify $(Build.SourcesDirectory)\targets\FreeRTOS_ESP32\$(BoardName)\IDF\partitions_nanoclr_2mb.csv ${{ parameters.buildDirectory }}\partitions_2mb.bin' + condition: succeeded() + displayName: Generate Esp32 Partition tables for 2MB flash + + - task: PythonScript@0 + inputs: + scriptSource: 'filePath' + scriptPath: '$(Agent.TempDirectory)\ESP32_Tools\esp-idf-v3.3\components\partition_table\gen_esp32part.py' + arguments: '${{ parameters.buildDirectory }}\partitions_4mb.bin' + condition: succeeded() + displayName: List flash 4Mb Esp32 Partition tables diff --git a/source/native/nf-interpreter/azure-pipelines-templates/build-ti-simplelink.yml b/source/native/nf-interpreter/azure-pipelines-templates/build-ti-simplelink.yml new file mode 100644 index 00000000..683e59c1 --- /dev/null +++ b/source/native/nf-interpreter/azure-pipelines-templates/build-ti-simplelink.yml @@ -0,0 +1,19 @@ +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. + +parameters: + buildDirectory: '$(Build.SourcesDirectory)\build' + +steps: + + - task: CMake@1 + inputs: + cmakeArgs: '-G Ninja -DTOOLCHAIN_PREFIX=$(GNU_GCC_TOOLCHAIN_PATH) -DCMAKE_BUILD_TYPE=MinSizeRel -DBUILD_VERSION=$(NBGV_AssemblyVersion) -DTI_BOARD=$(BoardName) $(BuildOptions) ..' + workingDirectory: ${{ parameters.buildDirectory }} + displayName: Setup build with CMake + + - task: CMake@1 + inputs: + cmakeArgs: '--build ${{ parameters.buildDirectory }} --target all --config MinSizeRel' + workingDirectory: ${{ parameters.buildDirectory }} + displayName: Build with CMake diff --git a/source/native/nf-interpreter/azure-pipelines-templates/download-hexdfu.yml b/source/native/nf-interpreter/azure-pipelines-templates/download-hexdfu.yml new file mode 100644 index 00000000..da8fd09b --- /dev/null +++ b/source/native/nf-interpreter/azure-pipelines-templates/download-hexdfu.yml @@ -0,0 +1,27 @@ +# Copyright (c) 2018 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. + +steps: + - task: PowerShell@2 + inputs: + targetType: 'inline' + script: | + Write-Host "Downloading hex2dfu..." + $url = "https://github.com/nanoframework/hex2dfu/releases/latest/download/hex2dfu.exe" + $output = "$env:Agent_TempDirectory\hex2dfu.exe" + (New-Object Net.WebClient).DownloadFile($url, $output) + errorActionPreference: 'stop' + failOnStderr: 'true' + condition: eq(variables['NeedsDFU'], true) + displayName: Install HEX2DFU + + - task: PowerShell@2 + inputs: + targetType: 'inline' + script: | + $newPath = "$env:Agent_TempDirectory".Replace('\','/') + Write-Host "$("##vso[task.setvariable variable=HEX2DFU_PATH]")$newPath" + errorActionPreference: 'stop' + failOnStderr: 'true' + condition: eq(variables['NeedsDFU'], true) + displayName: Adjust HexDFU path diff --git a/source/native/nf-interpreter/azure-pipelines-templates/download-install-arm-gcc-toolchain.yml b/source/native/nf-interpreter/azure-pipelines-templates/download-install-arm-gcc-toolchain.yml new file mode 100644 index 00000000..3ebc67ee --- /dev/null +++ b/source/native/nf-interpreter/azure-pipelines-templates/download-install-arm-gcc-toolchain.yml @@ -0,0 +1,45 @@ +# Copyright (c) 2018 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. + +steps: + - task: PowerShell@2 + inputs: + targetType: 'inline' + script: | + + if("$(GccArm_Version)" -ne "") + { + if("$(GccArm_Version)" -eq "5-2016-q3-update") + { + $url = "https://bintray.com/nfbot/internal-build-tools/download_file?file_path=gcc-arm-none-eabi-5-2016-q3-update-win32.7z" + } + else + { + # no valid version specified, use the default one + # current default is , this is is "8-2019-q3-update" + $url = "https://bintray.com/nfbot/internal-build-tools/download_file?file_path=gcc-arm-none-eabi-8-2019-q3-update-win32.7z" + } + } + else + { + # no version specified, use the default one + # current default is , this is is "8-2019-q3-update" + $url = "https://bintray.com/nfbot/internal-build-tools/download_file?file_path=gcc-arm-none-eabi-8-2019-q3-update-win32.7z" + } + + Write-Host "Downloading ARM GNU GCC toolchain $(GccArm_Version)..." + + $output = "$PSScriptRoot\gcc-arm.7z" + (New-Object Net.WebClient).DownloadFile($url, $output) + errorActionPreference: 'stop' + failOnStderr: 'true' + displayName: Downloading ARM GCC toolchain + + - task: ExtractFiles@1 + inputs: + archiveFilePatterns: '$(Agent.TempDirectory)\gcc-arm.7z' + destinationFolder: '$(Agent.TempDirectory)\GNU_Tools_ARM_Embedded' + displayName: Extracting ARM GCC toolchain + + - script: echo "##vso[task.prependpath]C:\Windows\System32" + displayName: Tweak PATH to reach cmd diff --git a/source/native/nf-interpreter/azure-pipelines-templates/download-install-esp32-build-components.yml b/source/native/nf-interpreter/azure-pipelines-templates/download-install-esp32-build-components.yml new file mode 100644 index 00000000..f22ea4d4 --- /dev/null +++ b/source/native/nf-interpreter/azure-pipelines-templates/download-install-esp32-build-components.yml @@ -0,0 +1,93 @@ +# Copyright (c) 2018 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. + +steps: + - task: PowerShell@2 + inputs: + targetType: 'inline' + script: | + Write-Host "Downloading Xtensa ESP32 toolchain..." + $url = "https://dl.espressif.com/dl/xtensa-esp32-elf-win32-1.22.0-80-g6c4433a-5.2.0.zip" + $output = "$PSScriptRoot\xtensa-esp32-elf-win32.zip" + (New-Object Net.WebClient).DownloadFile($url, $output) + errorActionPreference: 'stop' + failOnStderr: 'true' + displayName: Download xtensa ESP32 toolchain + + - task: ExtractFiles@1 + inputs: + archiveFilePatterns: '$(Agent.TempDirectory)\xtensa-esp32-elf-win32.zip' + destinationFolder: '$(Agent.TempDirectory)\ESP32_Tools' + cleanDestinationFolder: false + displayName: Extracting xtensa ESP32 toolchain + + - task: PowerShell@2 + inputs: + targetType: 'inline' + script: | + Write-Host "Downloading ESP32 pre-compiled libs..." + $url = "https://bintray.com/nfbot/internal-build-tools/download_file?file_path=IDF_libs-v3.3.zip" + $output = "$PSScriptRoot\IDF_libs-v3.3.zip" + (New-Object Net.WebClient).DownloadFile($url, $output) + errorActionPreference: 'stop' + failOnStderr: 'true' + displayName: Downloading ESP32 pre-compiled libs + + - task: ExtractFiles@1 + inputs: + archiveFilePatterns: '$(Agent.TempDirectory)\IDF_libs-v3.3.zip' + destinationFolder: '$(Agent.TempDirectory)\ESP32_Tools\libs-v3.3' + cleanDestinationFolder: false + displayName: Installing ESP32 pre-compiled libs + + - task: PowerShell@2 + inputs: + targetType: 'inline' + script: | + Write-Host "Downloading ESP32 IDF..." + $url = "https://github.com/espressif/esp-idf/releases/download/v3.3/esp-idf-v3.3.zip" + $output = "$PSScriptRoot\esp-idf-v3.3.zip" + (New-Object Net.WebClient).DownloadFile($url, $output) + errorActionPreference: 'stop' + failOnStderr: 'true' + displayName: Downloading ESP32 IDF + + - task: ExtractFiles@1 + inputs: + archiveFilePatterns: '$(Agent.TempDirectory)\esp-idf-v3.3.zip' + destinationFolder: '$(Agent.TempDirectory)\ESP32_Tools' + cleanDestinationFolder: false + displayName: Installing Espressif IDF + + # Use Python Version 3.7 and add it to path + - task: UsePythonVersion@0 + inputs: + versionSpec: '3.7' + addToPath: true + displayName: Set Python to v3.7 + + # in this one have to call Python with full path otherwise it can fail + - task: PowerShell@2 + inputs: + targetType: 'inline' + script: python -m pip install pyserial + # the below settings are required as the script is installing an outdated version of pyserial + errorActionPreference: 'silentlyContinue' + failOnStderr: false + ignoreLASTEXITCODE: false + displayName: Installing python pyserial + + - task: PowerShell@2 + inputs: + targetType: 'inline' + script: | + # need to replace forward slash for paths to work with GCC and CMake + $tempDirPath = "$env:Agent_TempDirectory".Replace('\','/') + Write-Host "$("##vso[task.setvariable variable=ESP32_LIBS_PATH]")$tempDirPath/ESP32_Tools/libs-v3.3" + Write-Host "$("##vso[task.setvariable variable=ESP32_IDF_PATH]")$tempDirPath/ESP32_Tools/esp-idf-v3.3" + errorActionPreference: 'stop' + failOnStderr: 'true' + displayName: Adjust paths + + - script: echo "##vso[task.prependpath]C:\Windows\System32" + displayName: Tweak PATH to reach cmd diff --git a/source/native/nf-interpreter/azure-pipelines-templates/download-install-ninja.yml b/source/native/nf-interpreter/azure-pipelines-templates/download-install-ninja.yml new file mode 100644 index 00000000..78d3a1c8 --- /dev/null +++ b/source/native/nf-interpreter/azure-pipelines-templates/download-install-ninja.yml @@ -0,0 +1,24 @@ +# Copyright (c) 2018 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. + +steps: + - task: PowerShell@2 + inputs: + targetType: 'inline' + script: | + Write-Host "Downloading Ninja..." + $url = "https://github.com/ninja-build/ninja/releases/download/v1.8.2/ninja-win.zip" + $output = "$PSScriptRoot\ninja.zip" + (New-Object Net.WebClient).DownloadFile($url, $output) + errorActionPreference: 'stop' + failOnStderr: 'true' + displayName: Download Ninja + + - task: ExtractFiles@1 + inputs: + archiveFilePatterns: '$(Agent.TempDirectory)\ninja.zip' + destinationFolder: '$(Agent.TempDirectory)\ninja' + displayName: Extract Ninja + + - script: echo "##vso[task.prependpath]$(Agent.TempDirectory)\ninja" + displayName: Tweak PATH with Ninja diff --git a/source/native/nf-interpreter/azure-pipelines-templates/nb-gitversioning.yml b/source/native/nf-interpreter/azure-pipelines-templates/nb-gitversioning.yml new file mode 100644 index 00000000..43fb32b8 --- /dev/null +++ b/source/native/nf-interpreter/azure-pipelines-templates/nb-gitversioning.yml @@ -0,0 +1,24 @@ +# Copyright (c) 2018 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. + +steps: + - task: DotNetCoreCLI@2 + inputs: + command: custom + custom: tool + arguments: install --tool-path . nbgv + condition: ne(variables['system.pullrequest.isfork'], true) + displayName: Install NBGV tool + + - script: nbgv cloud -a -c + condition: ne(variables['system.pullrequest.isfork'], true) + displayName: Set build number + + # Currently Azure pipelines won't let PRs from forks setting the build ID + # so we need to come up with a versiom number to use for the build + - task: PowerShell@2 + inputs: + targetType: 'inline' + script: Write-Host "$("##vso[task.setvariable variable=NBGV_AssemblyVersion]")0.0.0.$env:System_PullRequest_PullRequestNumber" + condition: eq(variables['system.pullrequest.isfork'], true) + displayName: Set temporary build number diff --git a/source/native/nf-interpreter/azure-pipelines-templates/pack-publish-artifacts.yml b/source/native/nf-interpreter/azure-pipelines-templates/pack-publish-artifacts.yml new file mode 100644 index 00000000..065b2149 --- /dev/null +++ b/source/native/nf-interpreter/azure-pipelines-templates/pack-publish-artifacts.yml @@ -0,0 +1,27 @@ +# Copyright (c) 2018 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. + +parameters: + buildDirectory: '$(Build.SourcesDirectory)\build' + +steps: + - task: CopyFiles@1 + inputs: + sourceFolder: ${{ parameters.buildDirectory }} + Contents: | + *.bin + *.hex + *.s19 + *.dfu + TargetFolder: '$(Build.ArtifactStagingDirectory)\$(BoardName)' + flattenFolders: true + condition: and( succeeded(), ne(variables['Build.Reason'], 'PullRequest') ) + displayName: Collecting deployable artifacts + + - task: PublishBuildArtifacts@1 + inputs: + PathtoPublish: '$(Build.ArtifactStagingDirectory)\$(BoardName)' + ArtifactName: $(BoardName) + ArtifactType: Container + condition: and( succeeded(), ne(variables['Build.Reason'], 'PullRequest') ) + displayName: Publish deployables artifacts diff --git a/source/native/nf-interpreter/azure-pipelines-templates/pack-publish-managed-helpers.yml b/source/native/nf-interpreter/azure-pipelines-templates/pack-publish-managed-helpers.yml new file mode 100644 index 00000000..77cbe9e7 --- /dev/null +++ b/source/native/nf-interpreter/azure-pipelines-templates/pack-publish-managed-helpers.yml @@ -0,0 +1,62 @@ +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. + +steps: + + # check if managed helper files where changed + - powershell: | + git config --global user.email "nanoframework@outlook.com" + git config --global user.name "nfbot" + + $auth = "basic $([System.Convert]::ToBase64String([System.Text.Encoding]::UTF8.GetBytes(":$(GitHubToken)"))))" + + $commit = Invoke-RestMethod -Uri "https://api.github.com/repos/nanoframework/nf-interpreter/commits/$(Build.SourceVersion)" -Header @{"Authorization"="$auth"} -ContentType "application/json" -Method GET + Write-host "Files changed:" + $commit.files | % {$_.filename} + + if ( $commit.files.filename -like "*$(BoardName)/managed_helpers*" ) + { + echo "##vso[task.setvariable variable=BUILD_NUGET_PACKAGE]true" + + $counter = $env:HelperPackageVersion + $version = [int]$counter + $packageVersion = "1.0." + $version.ToString() + + echo "##vso[task.setvariable variable=PACKAGE_NUGET_VERSION]$packageVersion" + + Write-host "Package version is: $packageVersion" + } + else + { + echo "##vso[task.setvariable variable=BUILD_NUGET_PACKAGE]False" + } + + condition: succeeded() + displayName: Check if managed helpers files were changed + + - task: NuGetCommand@2 + inputs: + command: 'custom' + arguments: 'pack targets\CMSIS-OS\ChibiOS\$(BoardName)\managed_helpers\package.nuspec -Version $(PACKAGE_NUGET_VERSION)' + condition: and( succeeded(), eq(variables['BUILD_NUGET_PACKAGE'], true) ) + displayName: Pack managed helpers NuGet + + - task: CopyFiles@1 + inputs: + sourceFolder: $(Build.SourcesDirectory) + Contents: | + **\nanoFramework.Targets*.nupkg + TargetFolder: '$(Build.ArtifactStagingDirectory)' + flattenFolders: true + condition: and( succeeded(), eq(variables['BUILD_NUGET_PACKAGE'], true) ) + displayName: Collecting managed helpers deployable artifacts + + # push NuGet packages to NuGet (happens except on PR builds) + - task: NuGetCommand@2 + inputs: + command: push + nuGetFeedType: external + packagesToPush: '$(Build.ArtifactStagingDirectory)/*.nupkg' + publishFeedCredentials: 'NuGet' + condition: and( succeeded(), eq(variables['BUILD_NUGET_PACKAGE'], true), not( startsWith(variables['Build.SourceBranch'], 'refs/pull') ) ) + displayName: Push managed helpers NuGet packages to NuGet diff --git a/source/native/nf-interpreter/azure-pipelines-templates/pack-publish-ti-sl-managed-helpers.yml b/source/native/nf-interpreter/azure-pipelines-templates/pack-publish-ti-sl-managed-helpers.yml new file mode 100644 index 00000000..acbf53a4 --- /dev/null +++ b/source/native/nf-interpreter/azure-pipelines-templates/pack-publish-ti-sl-managed-helpers.yml @@ -0,0 +1,62 @@ +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. + +steps: + + # check if managed helper files where changed + - powershell: | + git config --global user.email "nanoframework@outlook.com" + git config --global user.name "nfbot" + + $auth = "basic $([System.Convert]::ToBase64String([System.Text.Encoding]::UTF8.GetBytes(":$(GitHubToken)"))))" + + $commit = Invoke-RestMethod -Uri "https://api.github.com/repos/nanoframework/nf-interpreter/commits/$(Build.SourceVersion)" -Header @{"Authorization"="$auth"} -ContentType "application/json" -Method GET + Write-host "Files changed:" + $commit.files | % {$_.filename} + + if ( $commit.files.filename -like "*$(BoardName)/managed_helpers*" ) + { + echo "##vso[task.setvariable variable=BUILD_NUGET_PACKAGE]true" + + $counter = $env:HelperPackageVersion + $version = [int]$counter + $packageVersion = "1.0." + $version.ToString() + + echo "##vso[task.setvariable variable=PACKAGE_NUGET_VERSION]$packageVersion" + + Write-host "Package version is: $packageVersion" + } + else + { + echo "##vso[task.setvariable variable=BUILD_NUGET_PACKAGE]False" + } + + condition: succeeded() + displayName: Check if managed helpers files were changed + + - task: NuGetCommand@2 + inputs: + command: 'custom' + arguments: 'pack targets\TI-SimpleLink\$(BoardName)\managed_helpers\package.nuspec -Version $(PACKAGE_NUGET_VERSION)' + condition: and( succeeded(), eq(variables['BUILD_NUGET_PACKAGE'], true) ) + displayName: Pack managed helpers NuGet + + - task: CopyFiles@1 + inputs: + sourceFolder: $(Build.SourcesDirectory) + Contents: | + **\nanoFramework.Targets*.nupkg + TargetFolder: '$(Build.ArtifactStagingDirectory)' + flattenFolders: true + condition: and( succeeded(), eq(variables['BUILD_NUGET_PACKAGE'], true) ) + displayName: Collecting managed helpers deployable artifacts + + # push NuGet packages to NuGet (happens except on PR builds) + - task: NuGetCommand@2 + inputs: + command: push + nuGetFeedType: external + packagesToPush: '$(Build.ArtifactStagingDirectory)/*.nupkg' + publishFeedCredentials: 'NuGet' + condition: and( succeeded(), eq(variables['BUILD_NUGET_PACKAGE'], true), not( startsWith(variables['Build.SourceBranch'], 'refs/pull') ) ) + displayName: Push managed helpers NuGet packages to NuGet diff --git a/source/native/nf-interpreter/azure-pipelines-templates/publish-bintray.yml b/source/native/nf-interpreter/azure-pipelines-templates/publish-bintray.yml new file mode 100644 index 00000000..9b32110c --- /dev/null +++ b/source/native/nf-interpreter/azure-pipelines-templates/publish-bintray.yml @@ -0,0 +1,62 @@ +# Copyright (c) 2018 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. + +steps: + - task: ArchiveFiles@2 + inputs: + rootFolderOrFile: '$(Build.ArtifactStagingDirectory)\$(BoardName)' + includeRootFolder: false + archiveType: 'zip' + archiveFile: '$(Agent.TempDirectory)\$(BoardName)-$(NBGV_SimpleVersion)$(NBGV_PrereleaseVersion).zip' + replaceExistingArchive: true + # skip task on PR build and when on branch other than develop, master or release + condition: and( succeeded(), ne(variables['Build.Reason'], 'PullRequest'), or( eq(variables['Build.SourceBranchName'], 'develop'), eq(variables['Build.SourceBranchName'], 'master'), contains(variables['Build.SourceBranchName'], 'release') ) ) + displayName: Zip binary files + + - task: PowerShell@2 + inputs: + targetType: 'inline' + script: | + + $repoName = $env:Build_Repository_Name + $branchName = $env:Build_SourceBranchName + + Write-Host "repo name is: $repoName" + Write-Host "branch name is: $branchName" + + if( $env:Build_Repository_Name -like "*nf-Community-Targets" ) + { + # this is a build for a community target + Write-Host "$("##vso[task.setvariable variable=BINTRAY_REPO]")nanoframework-images-community-targets" + } + else + { + if( $env:Build_SourceBranchName -eq "develop" -or + $env:Build_SourceBranchName -match "^release*" ) + { + # this a dev or release branch, publish to Bintray dev repo + Write-Host "$("##vso[task.setvariable variable=BINTRAY_REPO]")nanoframework-images-dev" + } + else + { + # this master branch, publish to Bintray stable repo + Write-Host "$("##vso[task.setvariable variable=BINTRAY_REPO]")nanoframework-images" + } + } + errorActionPreference: 'stop' + failOnStderr: 'true' + # skip task on PR build and when on branch other than develop, master or release + condition: and( succeeded(), ne(variables['Build.Reason'], 'PullRequest'), or( eq(variables['Build.SourceBranchName'], 'develop'), eq(variables['Build.SourceBranchName'], 'master'), contains(variables['Build.SourceBranchName'], 'release') ) ) + displayName: Set Bintray repo path + + - task: cURLUploader@2 + inputs: + files: '$(Agent.TempDirectory)\$(BoardName)-$(NBGV_SimpleVersion)$(NBGV_PrereleaseVersion).zip' + authType: 'userAndPass' + username: 'nfbot' + password: '$(BinTrayKey)' + url: 'https://api.bintray.com/' + remotePath: 'content/nfbot/$(BINTRAY_REPO)/$(BoardName)/$(NBGV_SimpleVersion)$(NBGV_PrereleaseVersion)/$(BoardName)-$(NBGV_SimpleVersion)$(NBGV_PrereleaseVersion).zip;publish=1' + # skip task on PR build and when on branch other than develop, master or release + condition: and( succeeded(), ne(variables['Build.Reason'], 'PullRequest'), or( eq(variables['Build.SourceBranchName'], 'develop'), eq(variables['Build.SourceBranchName'], 'master'), contains(variables['Build.SourceBranchName'], 'release') ) ) + displayName: Upload artifact to Bintray diff --git a/source/native/nf-interpreter/azure-pipelines.yml b/source/native/nf-interpreter/azure-pipelines.yml new file mode 100644 index 00000000..d40bee0d --- /dev/null +++ b/source/native/nf-interpreter/azure-pipelines.yml @@ -0,0 +1,416 @@ +trigger: + branches: + include: + - master + - develop/* + - release/* + - refs/tags/* + paths: + exclude: + - CHANGELOG.md + - /*.md + - .gitignore + +# no pr config, we want to trigger builds for all PRs on all branches + +# add nf-tools repo to resources (for Azure Pipelines templates) +resources: + repositories: + - repository: templates + type: github + name: nanoframework/nf-tools + endpoint: nanoframework + +jobs: + +############################## +- job: Check_Build_Options + pool: + vmImage: 'VS2017-Win2016' + + steps: + - checkout: self + fetchDepth: 1 + + # get commint message + - powershell: | + + if($env:StartReleaseCandidate -like "true") + { + # this is a release prep so NO build + echo "##vso[task.setvariable variable=SKIP_BUILD;isOutput=true]true" + + Write-Host "Release preparation, skipping build." + } + else + { + # get commit details, if this is a PR + if($env:Build_SourceBranch -like "refs/pull*") + { + $commit = Invoke-RestMethod -Uri "https://api.github.com/repos/nanoframework/nf-interpreter/commits/$(Build.SourceVersion)" -ContentType "application/json" -Method GET + + if( ($commit.commit.author.name -eq "nfbot") -and (($commit.commit.message -like "*[version update]*") -or ($commit.commit.message -like "***NO_CI***")) ) + { + echo "##vso[task.setvariable variable=SKIP_BUILD;isOutput=true]true" + } + else + { + echo "##vso[task.setvariable variable=SKIP_BUILD;isOutput=true]false" + } + } + else + { + if($commit.commit.message -like "***NO_CI***") + { + echo "##vso[task.setvariable variable=SKIP_BUILD;isOutput=true]true" + } + else + { + echo "##vso[task.setvariable variable=SKIP_BUILD;isOutput=true]false" + } + } + } + + name: BuildOptions + displayName: Evaluate build options + + - task: DotNetCoreCLI@2 + inputs: + command: custom + custom: tool + arguments: install -g nbgv + condition: eq( variables['StartReleaseCandidate'], true ) + displayName: Install NBGV tool + + - powershell: | + + # compute authorization header in format "AUTHORIZATION: basic 'encoded token'" + # 'encoded token' is the Base64 of the string "nfbot:personal-token" + $auth = "basic $([System.Convert]::ToBase64String([System.Text.Encoding]::UTF8.GetBytes("nfbot:$(GitHubToken)"))))" + + cd "$env:Agent_TempDirectory" > $null + + git init "$env:Agent_TempDirectory\repo" + cd repo > $null + git remote add origin "$env:Build_Repository_Uri" + git config --global gc.auto 0 + git config --global user.name nfbot + git config --global user.email nanoframework@outlook.com + git config --global core.autocrlf true + git -c http.extraheader="AUTHORIZATION: $auth" fetch --progress origin + + git checkout develop + + cd source + + # prepare release and capture output + $release = nbgv prepare-release + + # get commit message for the merge + $commitMessage = git log -1 --pretty=%B + + # amend commit message to skip build + git commit --amend -m "$commitMessage" -m "***NO_CI***" > $null + + # push all changes to github + git -c http.extraheader="AUTHORIZATION: $auth" push --all origin + + # get release branch name + $branch = $release.Split(' ')[0] + + # start PR for release + $prRequestBody = @{title="Release $branch";body="";head="$branch";base="master"} | ConvertTo-Json + $githubApiEndpoint = "https://api.github.com/repos/$env:Build_Repository_Name/pulls" + [Net.ServicePointManager]::SecurityProtocol = [Net.SecurityProtocolType]::Tls12 + + $headers = @{} + $headers.Add("Authorization","$auth") + $headers.Add("Accept","application/vnd.github.symmetra-preview+json") + + try + { + $result = Invoke-RestMethod -Method Post -UserAgent [Microsoft.PowerShell.Commands.PSUserAgent]::InternetExplorer -Uri $githubApiEndpoint -Header $headers -ContentType "application/json" -Body $prRequestBody + 'Started PR for new release...' | Write-Host -NoNewline + 'OK' | Write-Host -ForegroundColor Green + } + catch + { + $result = $_.Exception.Response.GetResponseStream() + $reader = New-Object System.IO.StreamReader($result) + $reader.BaseStream.Position = 0 + $reader.DiscardBufferedData() + $responseBody = $reader.ReadToEnd(); + + "Error starting PR: $responseBody" | Write-Host -ForegroundColor Red + } + + condition: eq( variables['StartReleaseCandidate'], true ) + displayName: NBGV prepare release + +################# +# STM32 +- job: Build_STM32_targets + condition: not( eq( dependencies.Check_Build_Options.outputs['BuildOptions.SKIP_BUILD'], true ) ) + + dependsOn: + - Check_Build_Options + + pool: + vmImage: 'VS2017-Win2016' + + strategy: + matrix: + MBN_QUAIL: + BoardName: MBN_QUAIL + BuildOptions: -DTARGET_SERIES=STM32F4xx -DRTOS=CHIBIOS -DSUPPORT_ANY_BASE_CONVERSION=ON -DNF_FEATURE_DEBUGGER=ON -DNF_FEATURE_RTC=ON -DAPI_System.Math=ON -DAPI_Hardware.Stm32=ON -DAPI_Windows.Devices.Gpio=ON -DAPI_Windows.Devices.Spi=ON -DAPI_Windows.Devices.I2c=ON -DAPI_Windows.Devices.Pwm=ON -DAPI_Windows.Devices.SerialCommunication=ON -DAPI_nanoFramework.Devices.OneWire=ON -DAPI_nanoFramework.ResourceManager=ON -DAPI_nanoFramework.System.Collections=ON + GccArm_Version: + NeedsDFU: true + NETDUINO3_WIFI: + BoardName: NETDUINO3_WIFI + BuildOptions: -DTARGET_SERIES=STM32F4xx -DRTOS=CHIBIOS -DSUPPORT_ANY_BASE_CONVERSION=ON -DNF_FEATURE_DEBUGGER=ON -DNF_FEATURE_RTC=ON -DNF_FEATURE_HAS_SDCARD=ON -DAPI_System.Math=ON -DAPI_Hardware.Stm32=ON -DAPI_Windows.Devices.Gpio=ON -DAPI_Windows.Devices.Spi=ON -DAPI_Windows.Devices.I2c=ON -DAPI_Windows.Devices.Pwm=ON -DAPI_Windows.Devices.SerialCommunication=ON -DAPI_Windows.Devices.Adc=ON -DAPI_System.Devices.Dac=OFF -DAPI_nanoFramework.Devices.OneWire=ON -DAPI_Windows.Storage=ON -DAPI_nanoFramework.ResourceManager=ON -DAPI_nanoFramework.System.Collections=ON + GccArm_Version: + NeedsDFU: true + ST_STM32F429I_DISCOVERY: + BoardName: ST_STM32F429I_DISCOVERY + BuildOptions: -DTARGET_SERIES=STM32F4xx -DRTOS=CHIBIOS -DSUPPORT_ANY_BASE_CONVERSION=ON -DNF_FEATURE_DEBUGGER=ON -DSWO_OUTPUT=ON -DNF_FEATURE_RTC=ON -DAPI_System.Math=ON -DAPI_Hardware.Stm32=ON -DAPI_Windows.Devices.Gpio=ON -DAPI_Windows.Devices.Spi=ON -DAPI_Windows.Devices.I2c=ON -DAPI_Windows.Devices.Pwm=ON -DAPI_Windows.Devices.SerialCommunication=ON -DAPI_Windows.Devices.Adc=ON -DAPI_nanoFramework.Devices.OneWire=ON -DAPI_nanoFramework.Devices.Can=ON -DAPI_nanoFramework.ResourceManager=ON -DAPI_nanoFramework.System.Collections=ON + GccArm_Version: + NeedsDFU: false + ST_NUCLEO64_F091RC: + BoardName: ST_NUCLEO64_F091RC + BuildOptions: -DTARGET_SERIES=STM32F0xx -DRTOS=CHIBIOS -DNF_FEATURE_DEBUGGER=ON -DNF_FEATURE_RTC=ON -DUSE_RNG=OFF -DNF_PLATFORM_NO_CLR_TRACE=ON -DNF_CLR_NO_IL_INLINE=ON -DAPI_Hardware.Stm32=ON -DAPI_Windows.Devices.Gpio=ON -DAPI_Windows.Devices.Spi=ON -DAPI_Windows.Devices.I2c=ON -DAPI_Windows.Devices.Pwm=ON -DAPI_Windows.Devices.SerialCommunication=ON + GccArm_Version: 5-2016-q3-update + NeedsDFU: false + ST_STM32F769I_DISCOVERY: + BoardName: ST_STM32F769I_DISCOVERY + BuildOptions: -DTARGET_SERIES=STM32F7xx -DRTOS=CHIBIOS -DSUPPORT_ANY_BASE_CONVERSION=ON -DNF_FEATURE_DEBUGGER=ON -DSWO_OUTPUT=ON -DNF_FEATURE_RTC=ON -DNF_FEATURE_HAS_SDCARD=ON -DAPI_System.Math=ON -DAPI_Hardware.Stm32=ON -DNF_FEATURE_HAS_CONFIG_BLOCK=ON -DAPI_Windows.Devices.Gpio=ON -DAPI_Windows.Devices.Spi=ON -DAPI_Windows.Devices.I2c=ON -DAPI_Windows.Devices.Pwm=ON -DAPI_Windows.Devices.SerialCommunication=ON -DAPI_Windows.Devices.Adc=ON -DAPI_System.Devices.Dac=ON -DAPI_System.Net=ON -DNF_SECURITY_MBEDTLS=ON -DAPI_nanoFramework.Devices.OneWire=ON -DAPI_nanoFramework.Devices.Can=ON -DAPI_Windows.Storage=ON -DAPI_nanoFramework.ResourceManager=ON -DAPI_nanoFramework.System.Collections=ON + GccArm_Version: + NeedsDFU: false + + variables: + GNU_GCC_TOOLCHAIN_PATH: $(Agent.TempDirectory)\GNU_Tools_ARM_Embedded + HelperPackageVersion: $[counter('HelperPackageVersioncounter', 0)] + + steps: + - template: azure-pipelines-templates/nb-gitversioning.yml + + - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml + + - template: azure-pipelines-templates/download-install-ninja.yml + + - template: azure-pipelines-templates/download-hexdfu.yml + + - template: azure-pipelines-templates/build-chibios-stm32.yml + + - template: azure-pipelines-templates/pack-publish-artifacts.yml + + - template: azure-pipelines-templates/publish-bintray.yml + + - template: azure-pipelines-templates/pack-publish-managed-helpers.yml + +################# +# ESP32 targets +- job: Build_ESP32_targets + condition: not( eq( dependencies.Check_Build_Options.outputs['BuildOptions.SKIP_BUILD'], true ) ) + + dependsOn: + - Check_Build_Options + + pool: + vmImage: 'VS2017-Win2016' + + # there is only a single ESP32 target, but this is already config as a matrix to make it easy to add new ones + strategy: + matrix: + ESP32_WROOM_32: + BoardName: ESP32_WROOM_32 + BuildOptions: -DTARGET_SERIES=ESP32 -DRTOS=FREERTOS_ESP32 -DNF_WP_IMPLEMENTS_CRC32=OFF -DNF_FEATURE_DEBUGGER=ON -DNF_FEATURE_RTC=ON -DNF_FEATURE_HAS_CONFIG_BLOCK=ON -DNF_FEATURE_HAS_SDCARD=ON -DAPI_System.Math=ON -DAPI_Windows.Devices.Gpio=ON -DAPI_Windows.Devices.Spi=ON -DAPI_Windows.Devices.I2c=ON -DAPI_Windows.Devices.Pwm=ON -DAPI_Windows.Devices.SerialCommunication=ON -DAPI_Windows.Devices.Adc=ON -DAPI_System.Net=ON -DAPI_Windows.Devices.Wifi=ON -DAPI_Windows.Storage=ON -DNF_SECURITY_MBEDTLS=ON -DAPI_Hardware.Esp32=ON -DSUPPORT_ANY_BASE_CONVERSION=ON -DAPI_nanoFramework.Devices.OneWire=ON -DAPI_nanoFramework.ResourceManager=ON -DAPI_nanoFramework.System.Collections=ON + + variables: + ESP32_TOOLCHAIN_PATH: $(Agent.TempDirectory)\ESP32_Tools + + steps: + - template: azure-pipelines-templates/nb-gitversioning.yml + + - template: azure-pipelines-templates/download-install-esp32-build-components.yml + + - template: azure-pipelines-templates/download-install-ninja.yml + + - template: azure-pipelines-templates/build-esp32.yml + + - task: CopyFiles@1 + inputs: + sourceFolder: $(ESP32_LIBS_PATH) + Contents: | + bootloader.bin + TargetFolder: '$(Build.ArtifactStagingDirectory)\$(BoardName)' + flattenFolders: true + condition: and( succeeded(), ne(variables['Build.Reason'], 'PullRequest') ) + displayName: Copying bootloader from ESP32 libs + + - template: azure-pipelines-templates/pack-publish-artifacts.yml + + - template: azure-pipelines-templates/publish-bintray.yml + +################# +# TI SimpleLink +- job: Build_TI_SimpleLink_targets + condition: not( eq( dependencies.Check_Build_Options.outputs['BuildOptions.SKIP_BUILD'], true ) ) + + dependsOn: + - Check_Build_Options + + pool: + vmImage: 'VS2017-Win2016' + + strategy: + matrix: + TI_CC3220SF_LAUNCHXL: + BoardName: TI_CC3220SF_LAUNCHXL + BuildOptions: -DTARGET_SERIES=CC32xx -DRTOS=TI_SIMPLELINK -DSUPPORT_ANY_BASE_CONVERSION=OFF -DNF_FEATURE_DEBUGGER=ON -DNF_FEATURE_RTC=ON -DNF_FEATURE_WATCHDOG=OFF -DNF_FEATURE_HAS_CONFIG_BLOCK=ON -DAPI_Windows.Devices.Gpio=ON -DAPI_Windows.Devices.Spi=ON -DAPI_Windows.Devices.I2c=ON -DAPI_Windows.Devices.Pwm=ON -DAPI_Windows.Devices.SerialCommunication=OFF -DAPI_Windows.Devices.Adc=ON -DAPI_System.Net=ON -DAPI_nanoFramework.System.Collections=ON + GccArm_Version: + + variables: + GNU_GCC_TOOLCHAIN_PATH: $(Agent.TempDirectory)\GNU_Tools_ARM_Embedded + HelperPackageVersion: $[counter('HelperPackageVersioncounter', 0)] + + steps: + - template: azure-pipelines-templates/nb-gitversioning.yml + + - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml + + - template: azure-pipelines-templates/download-install-ninja.yml + + - template: azure-pipelines-templates/build-ti-simplelink.yml + + - template: azure-pipelines-templates/pack-publish-artifacts.yml + + - template: azure-pipelines-templates/publish-bintray.yml + + - template: azure-pipelines-templates/pack-publish-ti-sl-managed-helpers.yml + +################# +# WIN32 +- job: Build_WIN32_nanoCLR + condition: not( eq( dependencies.Check_Build_Options.outputs['BuildOptions.SKIP_BUILD'], true ) ) + + dependsOn: + - Check_Build_Options + + pool: + vmImage: 'VS2017-Win2016' + + steps: + - task: NuGetToolInstaller@0 + + - task: VSBuild@1 + inputs: + solution: 'targets\os\win32\nanoCLR.sln' + platform: 'x86' + configuration: 'Release' + +####################### +# generate change log +- job: Generate_change_log + dependsOn: + - Build_STM32_targets + - Build_ESP32_targets + - Build_TI_SimpleLink_targets + # skip build if this is a PR, submitted by nfbot and the commit message contains [version update] + condition: and( succeeded('Build_STM32_targets'), succeeded('Build_ESP32_targets'), succeeded('Build_TI_SimpleLink_targets'), not( eq(variables['Build.Reason'], 'PullRequest') ), not( and( eq(variables['Build.RequestedForId'], 'nfbot'), contains(variables['Build.SourceVersionMessage'], '[version update]') ) ) ) + + pool: + vmImage: 'VS2017-Win2016' + + steps: + - task: DotNetCoreCLI@2 + inputs: + command: custom + custom: tool + arguments: install --tool-path . nbgv + displayName: Install NBGV tool + + - task: PowerShell@2 + inputs: + targetType: 'inline' + script: nbgv cloud -a -c + errorActionPreference: 'silentlyContinue' + failOnStderr: 'false' + displayName: Set build number + # condition: ne(variables['system.pullrequest.isfork'], true) + + - task: UseRubyVersion@0 + inputs: + versionSpec: '>= 2.4' + addToPath: true + + # generate change log including future version + - script: | + gem install bundler + bundle install --retry=3 --jobs=4 + gem install github_changelog_generator + bundle exec github_changelog_generator --token $(GitHubToken) --future-release "v$(NBGV_Version)" + condition: or( eq(variables['Build.SourceBranchName'], 'master'), contains(variables['Build.SourceBranchName'], 'release') ) + displayName: Generate change log + + # generate change log including future version + - script: | + gem install github_changelog_generator + bundle exec github_changelog_generator --token $(GitHubToken) + condition: not( or( eq(variables['Build.SourceBranchName'], 'master'), contains(variables['Build.SourceBranchName'], 'release') ) ) + displayName: Generate change log + +####################### +# create or update GitHub release ON tags from release or master branches +- job: Publish_Release + dependsOn: + - Build_STM32_targets + - Build_ESP32_targets + - Build_TI_SimpleLink_targets + - Build_WIN32_nanoCLR + - Generate_change_log + + pool: + vmImage: 'VS2017-Win2016' + + steps: + - task: GitHubReleasePublish@1 + inputs: + githubEndpoint: 'nanoframework' + githubOwner: 'nanoframework' + githubRepositoryName: nf-interpreter + githubTag: v$(NBGV_Version) + githubReleaseTitle: 'nf Interpreter v$(NBGV_Version)' + githubTargetCommitsh: $(Build.SourceVersion) + githubReleaseDraft: false + githubReleasePrerelease: false + githubReuseDraftOnly: false + githubReuseRelease: true + githubEditRelease: false + githubDeleteEmptyTag: true + githubReleaseAsset: + condition: and( succeeded(), startsWith(variables['Build.SourceBranch'], 'refs/tags/v'), not(contains(variables['Build.SourceBranch'], 'preview') ), ne( variables['StartReleaseCandidate'], true ) ) + displayName: Create/Update GitHub stable release + +################################## +# report build failure to Discord +- job: Report_Build_Failure + dependsOn: + - Build_STM32_targets + - Build_ESP32_targets + - Build_TI_SimpleLink_targets + - Build_WIN32_nanoCLR + condition: or( failed('Build_STM32_targets'), failed('Build_ESP32_targets'), failed('Build_TI_SimpleLink_targets'), failed('Build_WIN32_nanoCLR')) + + pool: + vmImage: 'VS2017-Win2016' + + steps: + + - checkout: self + + # step from template @ nf-tools repo + - template: azure-pipelines-templates/discord-webhook.yml@templates + parameters: + status: 'failure' + webhookUrl: '$(DiscordWebhook)' + message: '' diff --git a/source/native/nf-interpreter/cmake-variants.TEMPLATE-ESP32.json b/source/native/nf-interpreter/cmake-variants.TEMPLATE-ESP32.json new file mode 100644 index 00000000..6ffef054 --- /dev/null +++ b/source/native/nf-interpreter/cmake-variants.TEMPLATE-ESP32.json @@ -0,0 +1,77 @@ +{ + "buildType": { + "default": "debug", + "choices": { + "debug": { + "short": "Debug", + "long": "Emit debug information without performing optimizations", + "buildType": "Debug" + }, + "release": { + "short": "Release", + "long": "Enable optimizations, omit debug info", + "buildType": "Release" + }, + "minsize": { + "short": "MinSizeRel", + "long": "Optimize for smallest binary size", + "buildType": "MinSizeRel" + }, + "reldeb": { + "short": "RelWithDebInfo", + "long": "Perform optimizations AND include debugging information", + "buildType": "RelWithDebInfo" + } + } + }, + + "linkage": { + "default": "", + "choices": { + + "Esp32_nanoCLR": { + "short": "NanoCLR", + "settings": { + "BUILD_VERSION": "0.9.99.999", + "TOOLCHAIN_PREFIX": "", + "ESP32_IDF_PATH": "", + "ESP32_LIBS_PATH": "", + "EXECUTABLE_OUTPUT_PATH": "${workspaceRoot}/build", + "TARGET_SERIES": "ESP32", + "ESP32_BOARD": "ESP32_WROOM_32", + "USE_FPU": "TRUE", + "RTOS": "FREERTOS_ESP32", + "SWO_OUTPUT": "OFF", + "NF_BUILD_RTM": "OFF", + "NF_WP_TRACE_ERRORS": "OFF", + "NF_WP_TRACE_HEADERS": "OFF", + "NF_WP_TRACE_STATE": "OFF", + "NF_WP_TRACE_NODATA": "OFF", + "NF_WP_TRACE_ALL": "OFF", + "NF_WP_IMPLEMENTS_CRC32": "OFF", + "NF_FEATURE_DEBUGGER": "ON", + "NF_FEATURE_RTC": "ON", + "NF_FEATURE_USE_APPDOMAINS": "OFF", + "NF_FEATURE_SUPPORT_REFLECTION" : "ON", + "NF_FEATURE_HAS_CONFIG_BLOCK": "ON", + "NF_FEATURE_HAS_SDCARD": "ON", + "API_System.Net": "ON", + "NF_SECURITY_MBEDTLS": "ON", + "API_nanoFramework.ResourceManager" : "ON", + "API_nanoFramework.System.Collections" : "ON", + "API_Windows.Devices.Wifi": "ON", + "API_Windows.Devices.Adc": "ON", + "API_System.Devices.Dac" : "OFF", + "API_Windows.Devices.Gpio": "ON", + "API_Windows.Devices.I2c": "ON", + "API_Windows.Devices.Pwm": "ON", + "API_Windows.Devices.SerialCommunication": "ON", + "API_Windows.Devices.Spi": "ON", + "API_Windows.Networking.Sockets": "OFF", + "API_Windows.Storage": "ON", + "API_Hardware.Esp32": "ON" + } + } + } + } +} diff --git a/source/native/nf-interpreter/cmake-variants.TEMPLATE.json b/source/native/nf-interpreter/cmake-variants.TEMPLATE.json new file mode 100644 index 00000000..a9883682 --- /dev/null +++ b/source/native/nf-interpreter/cmake-variants.TEMPLATE.json @@ -0,0 +1,91 @@ +{ + "buildType": { + "default": "debug", + "choices": { + "debug": { + "short": "Debug", + "long": "Emit debug information without performing optimizations", + "buildType": "Debug" + }, + "minsize": { + "short": "MinSizeRel", + "long": "Optimize for smallest binary size", + "buildType": "MinSizeRel" + }, + "reldeb": { + "short": "RelWithDebInfo", + "long": "Perform optimizations AND include debugging information", + "buildType": "RelWithDebInfo" + } + } + }, + + "linkage": { + "default": "", + "choices": { + "OPTION_NAME_HERE": { + "short": "", + "settings": { + "BUILD_VERSION" : "0.9.99.999", + "TOOLCHAIN_PREFIX" : "", + "TOOL_HEX2DFU_PREFIX" : "", + "ESP32_IDF_PATH" : "/esp-idf", + "ESP32_LIBS_PATH" : "/libs", + "TARGET_SERIES" : "", + "USE_RNG" : "", + "DP_FLOATINGPOINT" : "", + "SUPPORT_ANY_BASE_CONVERSION" : "", + "RTOS" : "", + "CHIBIOS_SOURCE" : "", + "CHIBIOS_CONTRIB_REQUIRED" : "OFF-default-ON-to-include_ChibiOS-Contrib-repository-in-the-build", + "CHIBIOS_CONTRIB_SOURCE" : "", + "CHIBIOS_BOARD" : "", + "STM32_CUBE_PACKAGE_REQUIRED" : "", + "STM32_CUBE_PACKAGE_SOURCE" : "", + "TI_BOARD" : "", + "TI_SL_CC32xx_SDK_SOURCE" : "", + "SPIFFS_SOURCE" : "", + "SWO_OUTPUT" : "OFF-default-ON-to-enable-ARM-CortexM-Single-Wire-Output", + "NF_BUILD_RTM" : "OFF-default-ON-to-enable-RTM-build", + "NF_WP_TRACE_ERRORS" : "OFF-default-ON-to-enable-trace-error-messages-wire-protocol", + "NF_WP_TRACE_HEADERS" : "OFF-default-ON-to-enable-trace-header-messages-wire-protocol", + "NF_WP_TRACE_STATE" : "OFF-default-ON-to-enable-trace-state-messages-wire-protocol", + "NF_WP_TRACE_NODATA" : "OFF-default-ON-to-enable-trace-no-data-messages-wire-protocol", + "NF_WP_TRACE_ALL" : "OFF-default-ON-to-enable-trace-all-messages-wire-protocol", + "NF_WP_IMPLEMENTS_CRC32" : "OFF-default-ON-to-enable-CRC32-wire-protocol", + "NF_FEATURE_DEBUGGER" : "OFF-default-ON-to-include-managed-app-debugging-capability", + "NF_FEATURE_RTC" : "OFF-default-ON-to-enable-hardware-RTC", + "NF_FEATURE_USE_APPDOMAINS" : "OFF-default-ON-to-enable-support-for-Application-Domains", + "NF_FEATURE_SUPPORT_REFLECTION" : "ON-default-OFF-to-disable-support-for-System.Reflection-API", + "NF_FEATURE_WATCHDOG" : "ON-to-enable-hardware-watchdog-ON-is-default", + "NF_FEATURE_HAS_CONFIG_BLOCK" : "OFF-default-ON-to-enable-configuration-block-storage", + "NF_FEATURE_HAS_SDCARD" : "OFF-default-ON-to-enable-support-for-SDCard-storage-device", + "NF_FEATURE_HAS_USB_MSD" : "OFF-default-ON-to-enable-support-for-USB-Mass-storage-device", + "NF_FEATURE_USE_SPIFFS" : "OFF-default-ON-to-enable-support-for-SPI-flash-file-system", + "NF_PLATFORM_NO_CLR_TRACE" : "OFF-default-ON-to-disable-all-trace-on-CLR", + "NF_CLR_NO_IL_INLINE" : "OFF-default-ON-to-disable-CLR-IL-inlining", + "NF_INTEROP_ASSEMBLIES" : [ "Assembly1-Namespace", "Assembly2-Namespace" ], + "NF_NETWORKING_SNTP" : "ON-default-to-add-SNTP-client-requires-networking", + "NF_SECURITY_MBEDTLS" : "OFF-default-ON-to-add-network-security-from-mbedTLS", + "MBEDTLS_SOURCE" : "", + "API_nanoFramework.Devices.Can" : "OFF-default-ON-to-add-this-API", + "API_nanoFramework.Devices.OneWire" : "OFF-default-ON-to-add-this-API", + "API_nanoFramework.ResourceManager" : "OFF-default-ON-to-add-this-API", + "API_nanoFramework.System.Collections" : "OFF-default-ON-to-add-this-API", + "API_System.Math" : "OFF-default-ON-to-add-this-API", + "API_System.Net" : "OFF-default-ON-to-add-this-API", + "API_Windows.Devices.Adc" : "OFF-default-ON-to-add-this-API", + "API_System.Devices.Dac" : "OFF-default-ON-to-add-this-API", + "API_Windows.Devices.Gpio" : "OFF-default-ON-to-add-this-API", + "API_Windows.Devices.I2c" : "OFF-default-ON-to-add-this-API", + "API_Windows.Devices.Pwm" : "OFF-default-ON-to-add-this-API", + "API_Windows.Devices.SerialCommunication" : "OFF-default-ON-to-add-this-API", + "API_Windows.Devices.Spi" : "OFF-default-ON-to-add-this-API", + "API_Windows.Networking.Sockets" : "OFF-default-ON-to-add-this-API", + "API_Hardware.Esp32" : "OFF-default-ON-to-add-this-API", + "API_Hardware.Stm32" : "OFF-default-ON-to-add-this-API" + } + } + } + } +} diff --git a/source/native/nf-interpreter/install-scripts/Set-PathVariable.ps1 b/source/native/nf-interpreter/install-scripts/Set-PathVariable.ps1 new file mode 100644 index 00000000..cc7b6505 --- /dev/null +++ b/source/native/nf-interpreter/install-scripts/Set-PathVariable.ps1 @@ -0,0 +1,82 @@ + ## Based on Hahndorf's awesome collection of PowerShell scripts. + ## https://github.com/hahndorf/hacops + [CmdletBinding(SupportsShouldProcess = $true)] +Param( + [parameter(Mandatory=$true)] + [string]$NewLocation) + +Begin +{ + +# requires –runasadministrator + + $regPath = "SYSTEM\CurrentControlSet\Control\Session Manager\Environment" + $hklm = [Microsoft.Win32.Registry]::LocalMachine + + Function GetOldPath() + { + $regKey = $hklm.OpenSubKey($regPath, $FALSE) + $envpath = $regKey.GetValue("Path", "", [Microsoft.Win32.RegistryValueOptions]::DoNotExpandEnvironmentNames) + return $envPath + } +} + +Process +{ + # Win32API error codes + $ERROR_SUCCESS = 0 + $ERROR_DUP_NAME = 34 + $ERROR_INVALID_DATA = 13 + + $NewLocation = $NewLocation.Trim(); + + If ($NewLocation -eq "" -or $NewLocation -eq $null) + { + Exit $ERROR_INVALID_DATA + } + + [string]$oldPath = GetOldPath + Write-Verbose "Old Path: $oldPath" + + # check whether the new location is already in the path + $parts = $oldPath.split(";") + If ($parts -contains $NewLocation) + { + Write-Warning ("The new location is already in the path ('"+$NewLocation+"')") + Exit $ERROR_DUP_NAME + } + + # build the new path, make sure we don't have double semicolons + $newPath = $oldPath + ";" + $NewLocation + $newPath = $newPath -replace ";;",";" + + if ($pscmdlet.ShouldProcess("%Path%", "Set $newPath")){ + # add to the current session + $env:path += ";$NewLocation" + # save into registry + $regKey = $hklm.OpenSubKey($regPath, $True) + $regKey.SetValue("Path", $newPath, [Microsoft.Win32.RegistryValueKind]::ExpandString) + Write-Output "The operation completed successfully." + } + + Exit $ERROR_SUCCESS +} + +<# +.SYNOPSIS + Adds a new item to the machine path environment variable +.DESCRIPTION + Most more popular methods to change the %path% actually break it. +.PARAMETER NewLocation + The new directory location to add at the end of the path. Can be an variable itself. +.EXAMPLE + Set-PathVariable.ps1 -NewLocation "%bin%" + Adds the string "%bin%" to the path, when using it it is expanded. +.NOTES + Tested on Windows 10 and Server 2016 + Author: Peter Hahndorf + Created: October 7th, 2016 +.LINK + https://github.com/hahndorf/hacops + https://peter.hahndorf.eu/blog/AddingToPathVariable +#> diff --git a/source/native/nf-interpreter/install-scripts/install-arm-gcc-toolchain.ps1 b/source/native/nf-interpreter/install-scripts/install-arm-gcc-toolchain.ps1 new file mode 100644 index 00000000..c365fec1 --- /dev/null +++ b/source/native/nf-interpreter/install-scripts/install-arm-gcc-toolchain.ps1 @@ -0,0 +1,35 @@ +# This PS installs the ARM GNU GCC toolchain from our Bintray repository if it's not already available + +if($psISE) { $PSScriptRoot = Split-Path -Path $psISE.CurrentFile.FullPath} #In case running in psISE +if(!$PSScriptRoot){ $PSScriptRoot = Split-Path $MyInvocation.MyCommand.Path -Parent } # or older PS +#Set location of nf-interpreter top-level +$nfRoot = "$PSScriptRoot\.." +$zipRoot = "$nfRoot\zips\" + +# check if path already exists +$GnuGccPathExists = Test-Path $env:GNU_GCC_TOOLCHAIN_PATH -ErrorAction SilentlyContinue + +If($GnuGccPathExists -eq $False) +{ + Write-Host "Downloading ARM GNU GCC toolchain..." + + $url = "https://bintray.com/nfbot/internal-build-tools/download_file?file_path=gcc-arm-none-eabi-8-2019-q3-update-win32.7z" + $output = "$zipRoot\gcc-arm.7z" + + # Stop security tripping us up + [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" + + # Create directory for zip files if necessary + md -Force $zipRoot | Out-Null + + # download 7zip with toolchain + (New-Object Net.WebClient).DownloadFile($url, $output) + + # Install 7Zip4PowerShell module from PSGallery if not already installed + Install-Module -Name 7Zip4Powershell -RequiredVersion 1.8.0 -Scope CurrentUser + + Write-Host "Installing ARM GNU GCC toolchain..." + + # unzip toolchain + Expand-7Zip -ArchiveFileName $output -TargetPath $env:GNU_GCC_TOOLCHAIN_PATH +} diff --git a/source/native/nf-interpreter/install-scripts/install-esp32-idf.ps1 b/source/native/nf-interpreter/install-scripts/install-esp32-idf.ps1 new file mode 100644 index 00000000..5dda86c7 --- /dev/null +++ b/source/native/nf-interpreter/install-scripts/install-esp32-idf.ps1 @@ -0,0 +1,41 @@ +# This PS installs IDF esp32 sdk + +if($psISE) { $PSScriptRoot = Split-Path -Path $psISE.CurrentFile.FullPath} #In case running in psISE +if(!$PSScriptRoot){ $PSScriptRoot = Split-Path $MyInvocation.MyCommand.Path -Parent } # or older PS +#Set location of nf-interpreter top-level +$nfRoot = "$PSScriptRoot\.." +$zipRoot = "$nfRoot\zips\" + +# check if path already exists +$Esp32IdfPathExists = Test-Path $env:ESP32_IDF_PATH -ErrorAction SilentlyContinue + +If($Esp32IdfPathExists -eq $False) +{ + $url = "https://github.com/espressif/esp-idf/releases/download/v3.3/esp-idf-v3.3.zip" + $output = "$zipRoot\esp-idf-v3.3.zip" + + # Don't download again if already exists. User can remove from zips to force... + if(![System.IO.File]::Exists($output)){ + + Write-Host "Downloading ESP32 IDF..." + + # Stop security tripping us up + [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" + + # Create directory for zip files if necessary + md -Force $zipRoot | Out-Null + + # download zip with Espressif IDF + (New-Object Net.WebClient).DownloadFile($url, $output) + } + + Write-Host "Installing Espressif IDF..." + + # unzip + Expand-Archive $output -DestinationPath $env:ESP32_TOOLS_PATH +} + +Write-Host "Installing python pyserial..." +# Make sure serial package is installed in python otherwise +# the esptool.py tool won't run +python -m pip install pyserial diff --git a/source/native/nf-interpreter/install-scripts/install-esp32-libs.ps1 b/source/native/nf-interpreter/install-scripts/install-esp32-libs.ps1 new file mode 100644 index 00000000..96ab1cec --- /dev/null +++ b/source/native/nf-interpreter/install-scripts/install-esp32-libs.ps1 @@ -0,0 +1,38 @@ +# This PS installs the pre-compiled EPS32 libraries from our Bintray repository + +if($psISE) { $PSScriptRoot = Split-Path -Path $psISE.CurrentFile.FullPath} #In case running in psISE +if(!$PSScriptRoot){ $PSScriptRoot = Split-Path $MyInvocation.MyCommand.Path -Parent } # or older PS +#Set location of nf-interpreter top-level +$nfRoot = "$PSScriptRoot\.." +$zipRoot = "$nfRoot\zips\" + +# check if path already exists +$ESP32LibPathExists = Test-Path $env:ESP32_LIBS_PATH -ErrorAction SilentlyContinue + +If($ESP32LibPathExists -eq $False) +{ + $url = "https://bintray.com/nfbot/internal-build-tools/download_file?file_path=IDF_libs-v3.3.zip" + $output = "$zipRoot\IDF_libs-v3.3.zip" + + # Don't download again if already exists. User can remove from zips to force... + if(![System.IO.File]::Exists($output)){ + + Write-Host "Downloading ESP32 pre-compiled libs..." + + # Stop security tripping us up + [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" + + # Create directory for zip files if necessary + md -Force $zipRoot | Out-Null + + # download zip IDF + (New-Object Net.WebClient).DownloadFile($url, $output) + } + + Write-Host "Installing ESP32 pre-compiled libs..." + + # unzip libs + #Expand-7Zip -ArchiveFileName $output -TargetPath $env:ESP32_LIBS_PATH + #unzip using PowerShell 5+ inbuilt command + Expand-Archive -Path $output -DestinationPath $env:ESP32_LIBS_PATH +} diff --git a/source/native/nf-interpreter/install-scripts/install-esp32-openocd.ps1 b/source/native/nf-interpreter/install-scripts/install-esp32-openocd.ps1 new file mode 100644 index 00000000..98c50e82 --- /dev/null +++ b/source/native/nf-interpreter/install-scripts/install-esp32-openocd.ps1 @@ -0,0 +1,38 @@ +# This PS installs the OpenOCD ESP32 toolchain from Espressif downloads repository +# if it's not already available at ESP32_TOOLS_PATH\openocd-esp32 + +if($psISE) { $PSScriptRoot = Split-Path -Path $psISE.CurrentFile.FullPath} #In case running in psISE +if(!$PSScriptRoot){ $PSScriptRoot = Split-Path $MyInvocation.MyCommand.Path -Parent } # or older PS +#Set location of nf-interpreter top-level +$nfRoot = "$PSScriptRoot\.." +$zipRoot = "$nfRoot\zips\" + +$env:ESP32_OPENOCD_PATH=($env:ESP32_TOOLS_PATH+'\openocd-esp32') +# check if path already exists +$OpenOCDPathExists = Test-Path $env:ESP32_OPENOCD_PATH -ErrorAction SilentlyContinue + +If($OpenOCDPathExists -eq $False) +{ + Write-Host "Downloading OpenOCD for ESP32 ..." + + $url = "https://github.com/espressif/openocd-esp32/releases/download/v0.10.0-esp32-20190212/openocd-esp32-win32-0.10.0-esp32-20190212.zip" + $output = "$zipRoot\openocd-esp32.zip" + + # Stop security tripping us up + [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" + + # Create directory for zip files if necessary + md -Force $zipRoot | Out-Null + + # download zip with OpenOcd tool + (New-Object Net.WebClient).DownloadFile($url, $output) + + Write-Host "Installing OpenOCD..." + + # unzip + #Expand-Archive $output -DestinationPath $env:ESP32_OPENOCD_PATH + + Expand-Archive $output -DestinationPath "$PSScriptRoot\openocd-esp32" + Move-Item -Path ("$PSScriptRoot\openocd-esp32\openocd-esp32\") -Destination $env:ESP32_OPENOCD_PATH + Remove-Item "$PSScriptRoot\openocd-esp32" -Force +} diff --git a/source/native/nf-interpreter/install-scripts/install-esp32-toolchain.ps1 b/source/native/nf-interpreter/install-scripts/install-esp32-toolchain.ps1 new file mode 100644 index 00000000..ed1c7ac7 --- /dev/null +++ b/source/native/nf-interpreter/install-scripts/install-esp32-toolchain.ps1 @@ -0,0 +1,41 @@ +# This PS installs the xtensa ESP32 toolchain from Espressif downloads repository +# if it's not already available at ESP32_TOOLCHAIN_PATH + +if($psISE) { $PSScriptRoot = Split-Path -Path $psISE.CurrentFile.FullPath} #In case running in psISE +if(!$PSScriptRoot){ $PSScriptRoot = Split-Path $MyInvocation.MyCommand.Path -Parent } # or older PS +#Set location of nf-interpreter top-level +$nfRoot = "$PSScriptRoot\.." +$zipRoot = "$nfRoot\zips\" + +# check if path already exists +$XtensaPathExists = Test-Path $env:ESP32_TOOLCHAIN_PATH -ErrorAction SilentlyContinue + +If($XtensaPathExists -eq $False) +{ + # Download xtensa ESP32 toolchain and install + + $url = "https://dl.espressif.com/dl/xtensa-esp32-elf-win32-1.22.0-80-g6c4433a-5.2.0.zip" + $output = "$zipRoot\xtensa-esp32-elf-win32.zip" + + # Don't download again if already exists. User can remove from zips to force... + if(![System.IO.File]::Exists($output)){ + Write-Host "Downloading Xtensa ESP32 toolchain..." + + # Stop security tripping us up + [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" + + # Create directory for zip files if necessary + md -Force $zipRoot | Out-Null + + # download zip with toolchain + (New-Object Net.WebClient).DownloadFile($url, $output) + } + + Write-Host "Installing Xtensa ESP32 toolchain..." + + # unzip toolchain (This used the older of the two Expand-7Zip addons) + #Expand-7Zip -ArchiveFileName $output -TargetPath $env:ESP32_TOOLCHAIN_PATH + + #unzip using PowerShell 5+ inbuilt command + Expand-Archive -Path $output -DestinationPath $env:ESP32_TOOLCHAIN_PATH +} diff --git a/source/native/nf-interpreter/install-scripts/install-esp32-tools.ps1 b/source/native/nf-interpreter/install-scripts/install-esp32-tools.ps1 new file mode 100644 index 00000000..2743b6d4 --- /dev/null +++ b/source/native/nf-interpreter/install-scripts/install-esp32-tools.ps1 @@ -0,0 +1,149 @@ +[CmdletBinding(SupportsShouldProcess = $true)] +param ( +[Parameter(HelpMessage="Please enter the COM port for ESP32 flash utility [e.g. COM1 or /dev/ttyUSB0].",Position=2)][string]$COMPORT, +[switch]$force = $false +) + + +[Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" +Write-Host "Install Tools to build nanoCLR into default folders and configure json files ..." +$env:BOARD_NAME = "ESP32_WROOM_32" + +If([string]::IsNullOrEmpty($COMPORT)) +{ + Write-Warning ("Please use parameter -C to set COM port for ESP32 flash utility [e.g. -C COM1], or edit tasks.json") +} + +$env:NANOCLR_COMPORT = $COMPORT + +if($psISE) { $PSScriptRoot = Split-Path -Path $psISE.CurrentFile.FullPath} #In case running in psISE +if(!$PSScriptRoot){ $PSScriptRoot = Split-Path $MyInvocation.MyCommand.Path -Parent } # or older PS + +#Set location of nf-interpreter top-level +$nfRoot = "$PSScriptRoot\.." + +# create build folder if necessary +md -Force "$nfRoot\build" | Out-Null + +#Write-Host $PSScriptRoot +#Write-Host $nfRoot +Write-Host "BOARD_NAME=" $env:BOARD_NAME + +Write-Host "Set User Environment Variables ... (can be slow if many Applications running.)" +If([string]::IsNullOrEmpty($env:ESP32_TOOLS_PATH) -or $force) +{ + $env:ESP32_TOOLS_PATH= 'C:\ESP32_TOOLS' + Write-Host ("Set User Environment ESP32_TOOLS_PATH='"+$env:ESP32_TOOLS_PATH+"'") + [System.Environment]::SetEnvironmentVariable("ESP32_TOOLS_PATH", $env:ESP32_TOOLS_PATH, "User") +} +If([string]::IsNullOrEmpty($env:ESP32_TOOLCHAIN_PREFIX) -or $force) +{ + $env:ESP32_TOOLCHAIN_PREFIX= ($env:ESP32_TOOLS_PATH) + Write-Host ("Set User Environment ESP32_TOOLCHAIN_PREFIX='"+$env:ESP32_TOOLCHAIN_PREFIX+"'") + [System.Environment]::SetEnvironmentVariable("ESP32_TOOLCHAIN_PREFIX", $env:ESP32_TOOLCHAIN_PREFIX, "User") +} +If([string]::IsNullOrEmpty($env:ESP32_TOOLCHAIN_PATH) -or $force) +{ + $env:ESP32_TOOLCHAIN_PATH= ($env:ESP32_TOOLS_PATH) + Write-Host ("Set User Environment ESP32_TOOLCHAIN_PATH='"+$env:ESP32_TOOLCHAIN_PATH+"'") + [System.Environment]::SetEnvironmentVariable("ESP32_TOOLCHAIN_PATH", $env:ESP32_TOOLCHAIN_PATH, "User") +} +If([string]::IsNullOrEmpty($env:ESP32_LIBS_PATH) -or $force) +{ + $env:ESP32_LIBS_PATH=($env:ESP32_TOOLS_PATH+'\libs-v3.3') + Write-Host ("Set User Environment ESP32_LIBS_PATH='"+$env:ESP32_LIBS_PATH+"'") + [System.Environment]::SetEnvironmentVariable("ESP32_LIBS_PATH", $env:ESP32_LIBS_PATH, "User") +} +If([string]::IsNullOrEmpty($env:ESP32_IDF_PATH) -or [string]::IsNullOrEmpty($env:IDF_PATH) -or $force) +{ + $env:IDF_PATH=$env:ESP32_IDF_PATH=($env:ESP32_TOOLS_PATH+'\esp-idf-v3.3') + Write-Host ("Set User Environment ESP32_IDF_PATH='"+$env:ESP32_IDF_PATH+"'") + Write-Host ("Set User Environment IDF_PATH='"+$env:IDF_PATH+"'") + [System.Environment]::SetEnvironmentVariable("ESP32_IDF_PATH", $env:ESP32_IDF_PATH, "User") + [System.Environment]::SetEnvironmentVariable("IDF_PATH", $env:IDF_PATH, "User") +} +If([string]::IsNullOrEmpty($env:NINJA_PATH) -or $force) +{ + $env:NINJA_PATH= ($env:ESP32_TOOLS_PATH+'\ninja') + Write-Host ("Set User Environment NINJA_PATH='"+$env:NINJA_PATH+"'") + [System.Environment]::SetEnvironmentVariable("NINJA_PATH", $env:NINJA_PATH, "User") +} + +Invoke-Expression -Command $PSScriptRoot\install-esp32-toolchain.ps1 +Invoke-Expression -Command $PSScriptRoot\install-esp32-libs.ps1 +Invoke-Expression -Command $PSScriptRoot\install-esp32-idf.ps1 +Invoke-Expression -Command $PSScriptRoot\install-ninja.ps1 +Invoke-Expression -Command $PSScriptRoot\install-esp32-openocd.ps1 + +Write-Host ("Adding Ninja to the path "+$env:NINJA_PATH) +Invoke-Expression -Command "$PSScriptRoot\Set-PathVariable.ps1 -NewLocation $env:NINJA_PATH" + +$filePathExists = Test-Path "$nfRoot\cmake-variants.json" -ErrorAction SilentlyContinue +If($filePathExists -eq $False -or $force) +{ + Write-Host ("Create .\cmake-variants.json with install paths from .\cmake-variants.TEMPLATE-ESP32.json") + Copy-Item "$nfRoot\cmake-variants.TEMPLATE-ESP32.json" -Destination "$nfRoot\cmake-variants.json" -Force + $variants = (Get-Content "$nfRoot\cmake-variants.json") + $variants = $variants.Replace('', $env:ESP32_IDF_PATH.ToString().Replace("\", "/")) + $variants = $variants.Replace('', $env:ESP32_LIBS_PATH.ToString().Replace("\", "/")) + $variants = $variants.Replace('', $env:ESP32_TOOLCHAIN_PREFIX.ToString().Replace("\", "/")) + Set-Content -Path "$nfRoot\cmake-variants.json" -Value $variants +} + +$filePathExists = Test-Path "$nfRoot\.vscode\cmake-kits.json" -ErrorAction SilentlyContinue +If($filePathExists -eq $False -or $force) +{ + Copy-Item "$nfRoot\.vscode\cmake-kits.TEMPLATE-ESP32.json" -Destination "$nfRoot\.vscode\cmake-kits.json" -Force +} + +$buildFolderPath = Resolve-Path $nfRoot\build + +$filePathExists = Test-Path "$nfRoot\.vscode\tasks.json" -ErrorAction SilentlyContinue +$filePathExists=$False +If($filePathExists -eq $False -or $force) +{ + Write-Host ("Create .\.vscode\tasks.json with install paths from .\vscode\tasks.TEMPLATE-ESP32.json") + Copy-Item "$nfRoot\.vscode\tasks.TEMPLATE-ESP32.json" -Destination "$nfRoot\.vscode\tasks.json" -Force + $tasks = (Get-Content "$nfRoot\.vscode\tasks.json") + $tasks = $tasks.Replace('', $env:ESP32_IDF_PATH.ToString().Replace("\", "/")) + $tasks = $tasks.Replace('', $env:ESP32_LIBS_PATH.ToString().Replace("\", "/")) + $tasks = $tasks.Replace('', $buildFolderPath.ToString().Replace("\", "/")) + $tasks = $tasks.Replace('', $env:ESP32_TOOLCHAIN_PREFIX.ToString().Replace("\", "/")) + + # Update the COMPORT placeholder if the paramter is supplied. + If(![string]::IsNullOrEmpty($COMPORT)) + { + $tasks = $tasks.Replace('', $env:NANOCLR_COMPORT.ToString()) + } + Set-Content -Path "$nfRoot\.vscode\tasks.json" -Value $tasks +} +$filePathExists = Test-Path "$nfRoot\.vscode\launch.json" -ErrorAction SilentlyContinue +$filePathExists=$False +If($filePathExists -eq $False -or $force) +{ + Write-Host "Create .\.vscode\launch.json with install paths from .\vscode\launch.TEMPLATE-ESP32.json" + Copy-Item "$nfRoot\.vscode\launch.TEMPLATE-ESP32.json" -Destination "$nfRoot\.vscode\launch.json" -Force + + $launch = (Get-Content "$nfRoot\.vscode\launch.json") + $launch = $launch.Replace('', $buildFolderPath.ToString().Replace("\", "/")) + $launch = $launch.Replace('', $env:ESP32_OPENOCD_PATH.Replace("\", "/")) + $launch = $launch.Replace('', $env:ESP32_TOOLCHAIN_PATH.Replace("\", "/")) + Set-Content -Path "$nfRoot\.vscode\launch.json" -Value $launch +} +<# +.SYNOPSIS + Install the default ESP32 tools and libraries neede to build nanoFramework, and setup the build environemnt. +.DESCRIPTION + Power Shell Script to install the default tools to build nanoFramework, including setting the machine path and other environment variables needed for ESP32 DevKitC. Use the -Force paramter to over-write existing Environment variables. +.PARAMETER COMPORT + The COM port for NANOCLR [e.g. COM1]. +.EXAMPLE + .\install-esp32-tools.ps1 -COMPORT COM19 + Installs the tools for Espressive ESP32 to default path, define required envisonment variables and update VSCode files with paths and set COM19 in tasks.json +.NOTES + Tested on Windows 10 + Author: nanoFramework Contributors + Created: September 9th, 2018 +.LINK + https://https://github.com/nanoframework/Home +#> diff --git a/source/native/nf-interpreter/install-scripts/install-nf-hex2dfu.ps1 b/source/native/nf-interpreter/install-scripts/install-nf-hex2dfu.ps1 new file mode 100644 index 00000000..72cfdf8f --- /dev/null +++ b/source/native/nf-interpreter/install-scripts/install-nf-hex2dfu.ps1 @@ -0,0 +1,21 @@ +# This PS installs nanoFramework hex2dfu command line utility + +# check if path already exists +$hex2dfuPathExists = Test-Path $env:HEX2DFU_PATH -ErrorAction SilentlyContinue + +If($hex2dfuPathExists -eq $False) +{ + & md $($env:HEX2DFU_PATH) > $null + + Write-Host "Downloading hex2dfu..." + + $url = "https://github.com/nanoframework/hex2dfu/releases/latest/download/hex2dfu.exe" + + $output = "$env:HEX2DFU_PATH\hex2dfu.exe" + + # Stop security tripping us up + [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" + + # download executable with utility + (New-Object Net.WebClient).DownloadFile($url, $output) +} diff --git a/source/native/nf-interpreter/install-scripts/install-ninja.ps1 b/source/native/nf-interpreter/install-scripts/install-ninja.ps1 new file mode 100644 index 00000000..e4ea2213 --- /dev/null +++ b/source/native/nf-interpreter/install-scripts/install-ninja.ps1 @@ -0,0 +1,31 @@ +# This PS installs Ninja build tool + +if($psISE) { $PSScriptRoot = Split-Path -Path $psISE.CurrentFile.FullPath} #In case running in psISE +if(!$PSScriptRoot){ $PSScriptRoot = Split-Path $MyInvocation.MyCommand.Path -Parent } # or older PS +#Set location of nf-interpreter top-level +$nfRoot = "$PSScriptRoot\.." +$zipRoot = "$nfRoot\zips\" + +# check if path already exists +$NinjaPathExists = Test-Path $env:NINJA_PATH -ErrorAction SilentlyContinue + +If($NinjaPathExists -eq $False) +{ + Write-Host "Downloading Ninja..." + + $url = "https://github.com/ninja-build/ninja/releases/download/v1.8.2/ninja-win.zip" + $output = "$zipRoot\ninja.zip" + # Stop security tripping us up + [Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" + + # Create directory for zip files if necessary + md -Force $zipRoot | Out-Null + + # download zip with Ninja tool + (New-Object Net.WebClient).DownloadFile($url, $output) + + Write-Host "Installing Ninja..." + + # unzip + Expand-Archive $output -DestinationPath $env:NINJA_PATH +} diff --git a/source/native/nf-interpreter/install-scripts/install-stm32-tools.ps1 b/source/native/nf-interpreter/install-scripts/install-stm32-tools.ps1 new file mode 100644 index 00000000..85878f9b --- /dev/null +++ b/source/native/nf-interpreter/install-scripts/install-stm32-tools.ps1 @@ -0,0 +1,66 @@ +$BOARD_NAME = "STM32" + +[Net.ServicePointManager]::SecurityProtocol = "tls12, tls11, tls" + +Write-Host "Install Tools to build nanoCLR into default folders and configure json files ..." +$env:BOARD_NAME = $BOARD_NAME +$env:NANOCLR_COMPORT = $COMPORT + +if($psISE) { $PSScriptRoot = Split-Path -Path $psISE.CurrentFile.FullPath} #In case running in psISE +if(!$PSScriptRoot){ $PSScriptRoot = Split-Path $MyInvocation.MyCommand.Path -Parent } # or older PS + +#Set location of nf-interpreter +$nfRoot = "$PSScriptRoot\.." + +# create build folder if necessary +md -Force "$nfRoot\build" | Out-Null + +Write-Host "BOARD_NAME=" $env:BOARD_NAME +If([string]::IsNullOrEmpty($env:GNU_GCC_TOOLCHAIN_PATH) -or $force) +{ + $env:GNU_GCC_TOOLCHAIN_PATH='C:\GNU_Tools_ARM_Embedded\8-2019-q3-update' + Write-Host ("Set User Environment GNU_GCC_TOOLCHAIN_PATH='"+$env:GNU_GCC_TOOLCHAIN_PATH+"'") + [System.Environment]::SetEnvironmentVariable("GNU_GCC_TOOLCHAIN_PATH", $env:GNU_GCC_TOOLCHAIN_PATH, "User") +} +If([string]::IsNullOrEmpty($env:HEX2DFU_PATH) -or $force) +{ + $env:HEX2DFU_PATH= 'C:\mytools\hex2dfu' + Write-Host ("Set User Environment HEX2DFU_PATH='"+$env:HEX2DFU_PATH+"'") + [System.Environment]::SetEnvironmentVariable("HEX2DFU_PATH", $env:HEX2DFU_PATH, "User") +} +If([string]::IsNullOrEmpty($env:NINJA_PATH) -or $force) +{ + $env:NINJA_PATH= 'C:\mytools\ninja' + Write-Host ("Set User Environment NINJA_PATH='"+$env:NINJA_PATH+"'") + [System.Environment]::SetEnvironmentVariable("NINJA_PATH", $env:NINJA_PATH, "User") +} + +# get build matrix (Not used anymore) +#Invoke-Expression -Command $PSScriptRoot\get-stm32-targets-to-build.ps1 + +# install tools and utilities +Invoke-Expression -Command $PSScriptRoot\install-arm-gcc-toolchain.ps1 +Invoke-Expression -Command $PSScriptRoot\install-ninja.ps1 +Invoke-Expression -Command $PSScriptRoot\install-nf-hex2dfu.ps1 + +$test = [System.Environment]::GetEnvironmentVariable("NINJA_PATH", "User") +If($test -eq "") +{ + [System.Environment]::SetEnvironmentVariable("NINJA_PATH", $env:NINJA_PATH, "User") +} + +<# +.SYNOPSIS + Install the default tools to build nanoFramework for STM32 and setup build environemnt. +.DESCRIPTION + Power Shell Script to install the default tools to build nano Framework, including setting the machine path and other environment variables needed for STM32 +.EXAMPLE + .\install-stm32-tools.ps1 + Install the tools for STM32 to default path, define required environment variables and update VSCode files with paths and set COM19 in tasks.json +.NOTES + Tested on Windows 10 + Author: nanoFramework Contributors + Created: September 9th, 2018 +.LINK + https://https://github.com/nanoframework/Home +#> diff --git a/source/native/nf-interpreter/nf.props b/source/native/nf-interpreter/nf.props new file mode 100644 index 00000000..585f1a7c --- /dev/null +++ b/source/native/nf-interpreter/nf.props @@ -0,0 +1,19 @@ + + + + + + + $(__BuildDir)\ + $(MSBuildThisFileDirectory)build\ + + $(__BinDir) + $(BuildDir)bin\$(Configuration)\ + + $(__IntDir) + $(BuildDir)obj\$(Configuration)\$(ProjectName)\ + + + + + diff --git a/source/native/nf-interpreter/nfcore.vssettings b/source/native/nf-interpreter/nfcore.vssettings new file mode 100644 index 00000000..04850706 --- /dev/null +++ b/source/native/nf-interpreter/nfcore.vssettings @@ -0,0 +1,74 @@ + + + + + + + 4 + false + 4 + true + + + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 2 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + + + + diff --git a/source/native/nf-interpreter/sd1.bat b/source/native/nf-interpreter/sd1.bat new file mode 100644 index 00000000..ccadfa1d --- /dev/null +++ b/source/native/nf-interpreter/sd1.bat @@ -0,0 +1,6 @@ + @echo off + REM Run command in short-path version of this directory + setlocal + pushd B:\ + %1 + popd diff --git a/source/native/nf-interpreter/sdkconfig b/source/native/nf-interpreter/sdkconfig new file mode 100644 index 00000000..cfaea8f1 --- /dev/null +++ b/source/native/nf-interpreter/sdkconfig @@ -0,0 +1,490 @@ +# +# Automatically generated file. DO NOT EDIT. +# Espressif IoT Development Framework (ESP-IDF) Project Configuration +# +CONFIG_IDF_TARGET="esp32" + +# +# SDK tool configuration +# +CONFIG_TOOLPREFIX="xtensa-esp32-elf-" +CONFIG_MAKE_WARN_UNDEFINED_VARIABLES=y +CONFIG_APP_COMPILE_TIME_DATE=y +# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set +# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set +CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y +# CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE is not set +CONFIG_LOG_BOOTLOADER_LEVEL=3 +# CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_8V is not set +CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y +# CONFIG_BOOTLOADER_FACTORY_RESET is not set +# CONFIG_BOOTLOADER_APP_TEST is not set +CONFIG_BOOTLOADER_WDT_ENABLE=y +# CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set +CONFIG_BOOTLOADER_WDT_TIME_MS=9000 +# CONFIG_APP_ROLLBACK_ENABLE is not set +# CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set +# CONFIG_SECURE_BOOT_ENABLED is not set +# CONFIG_FLASH_ENCRYPTION_ENABLED is not set +CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200 +# CONFIG_FLASHMODE_QIO is not set +# CONFIG_FLASHMODE_QOUT is not set +CONFIG_FLASHMODE_DIO=y +# CONFIG_FLASHMODE_DOUT is not set +CONFIG_ESPTOOLPY_FLASHMODE="dio" +# CONFIG_ESPTOOLPY_FLASHFREQ_80M is not set +CONFIG_ESPTOOLPY_FLASHFREQ_40M=y +# CONFIG_ESPTOOLPY_FLASHFREQ_26M is not set +# CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set +CONFIG_ESPTOOLPY_FLASHFREQ="40m" +# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE_2MB=y +# CONFIG_ESPTOOLPY_FLASHSIZE_4MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE="2MB" +CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y +CONFIG_ESPTOOLPY_BEFORE_RESET=y +# CONFIG_ESPTOOLPY_BEFORE_NORESET is not set +CONFIG_ESPTOOLPY_BEFORE="default_reset" +CONFIG_ESPTOOLPY_AFTER_RESET=y +# CONFIG_ESPTOOLPY_AFTER_NORESET is not set +CONFIG_ESPTOOLPY_AFTER="hard_reset" +# CONFIG_MONITOR_BAUD_9600B is not set +# CONFIG_MONITOR_BAUD_57600B is not set +CONFIG_MONITOR_BAUD_115200B=y +# CONFIG_MONITOR_BAUD_230400B is not set +# CONFIG_MONITOR_BAUD_921600B is not set +# CONFIG_MONITOR_BAUD_2MB is not set +# CONFIG_MONITOR_BAUD_OTHER is not set +CONFIG_MONITOR_BAUD_OTHER_VAL=115200 +CONFIG_MONITOR_BAUD=115200 +CONFIG_PARTITION_TABLE_SINGLE_APP=y +# CONFIG_PARTITION_TABLE_TWO_OTA is not set +# CONFIG_PARTITION_TABLE_CUSTOM is not set +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions_singleapp.csv" +CONFIG_PARTITION_TABLE_OFFSET=0x8000 +CONFIG_PARTITION_TABLE_MD5=y +CONFIG_OPTIMIZATION_LEVEL_DEBUG=y +# CONFIG_OPTIMIZATION_LEVEL_RELEASE is not set +CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y +# CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set +# CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED is not set +# CONFIG_CXX_EXCEPTIONS is not set +CONFIG_STACK_CHECK_NONE=y +# CONFIG_STACK_CHECK_NORM is not set +# CONFIG_STACK_CHECK_STRONG is not set +# CONFIG_STACK_CHECK_ALL is not set +# CONFIG_STACK_CHECK is not set +# CONFIG_WARN_WRITE_STRINGS is not set +# CONFIG_DISABLE_GCC8_WARNINGS is not set +# CONFIG_ESP32_APPTRACE_DEST_TRAX is not set +CONFIG_ESP32_APPTRACE_DEST_NONE=y +# CONFIG_ESP32_APPTRACE_ENABLE is not set +CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y +# CONFIG_AWS_IOT_SDK is not set +# CONFIG_BT_ENABLED is not set +CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE=0 +CONFIG_BT_RESERVE_DRAM=0 +# CONFIG_ADC_FORCE_XPD_FSM is not set +CONFIG_ADC2_DISABLE_DAC=y +# CONFIG_SPI_MASTER_IN_IRAM is not set +CONFIG_SPI_MASTER_ISR_IN_IRAM=y +# CONFIG_SPI_SLAVE_IN_IRAM is not set +CONFIG_SPI_SLAVE_ISR_IN_IRAM=y +# CONFIG_EFUSE_CUSTOM_TABLE is not set +# CONFIG_EFUSE_VIRTUAL is not set +# CONFIG_EFUSE_CODE_SCHEME_COMPAT_NONE is not set +CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4=y +# CONFIG_EFUSE_CODE_SCHEME_COMPAT_REPEAT is not set +CONFIG_EFUSE_MAX_BLK_LEN=192 +CONFIG_IDF_TARGET_ESP32=y +CONFIG_ESP32_REV_MIN_0=y +# CONFIG_ESP32_REV_MIN_1 is not set +# CONFIG_ESP32_REV_MIN_2 is not set +# CONFIG_ESP32_REV_MIN_3 is not set +CONFIG_ESP32_REV_MIN=0 +CONFIG_ESP32_DPORT_WORKAROUND=y +# CONFIG_ESP32_DEFAULT_CPU_FREQ_80 is not set +CONFIG_ESP32_DEFAULT_CPU_FREQ_160=y +# CONFIG_ESP32_DEFAULT_CPU_FREQ_240 is not set +CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=160 +# CONFIG_SPIRAM_SUPPORT is not set +# CONFIG_MEMMAP_TRACEMEM is not set +# CONFIG_MEMMAP_TRACEMEM_TWOBANKS is not set +# CONFIG_ESP32_TRAX is not set +CONFIG_TRACEMEM_RESERVE_DRAM=0x0 +# CONFIG_TWO_UNIVERSAL_MAC_ADDRESS is not set +CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS=y +CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS=4 +CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_MAIN_TASK_STACK_SIZE=3584 +CONFIG_IPC_TASK_STACK_SIZE=1024 +CONFIG_TIMER_TASK_STACK_SIZE=3584 +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set +CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y +# CONFIG_NEWLIB_NANO_FORMAT is not set +CONFIG_CONSOLE_UART_DEFAULT=y +# CONFIG_CONSOLE_UART_CUSTOM is not set +# CONFIG_CONSOLE_UART_NONE is not set +CONFIG_CONSOLE_UART_NUM=0 +CONFIG_CONSOLE_UART_BAUDRATE=115200 +# CONFIG_ULP_COPROC_ENABLED is not set +CONFIG_ULP_COPROC_RESERVE_MEM=0 +# CONFIG_ESP32_PANIC_PRINT_HALT is not set +CONFIG_ESP32_PANIC_PRINT_REBOOT=y +# CONFIG_ESP32_PANIC_SILENT_REBOOT is not set +# CONFIG_ESP32_PANIC_GDBSTUB is not set +CONFIG_ESP32_DEBUG_OCDAWARE=y +CONFIG_ESP32_DEBUG_STUBS_ENABLE=y +CONFIG_INT_WDT=y +CONFIG_INT_WDT_TIMEOUT_MS=300 +CONFIG_INT_WDT_CHECK_CPU1=y +CONFIG_TASK_WDT=y +# CONFIG_TASK_WDT_PANIC is not set +CONFIG_TASK_WDT_TIMEOUT_S=5 +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y +CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y +CONFIG_BROWNOUT_DET=y +CONFIG_BROWNOUT_DET_LVL_SEL_0=y +# CONFIG_BROWNOUT_DET_LVL_SEL_1 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_7 is not set +CONFIG_BROWNOUT_DET_LVL=0 +CONFIG_REDUCE_PHY_TX_POWER=y +CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1=y +# CONFIG_ESP32_TIME_SYSCALL_USE_RTC is not set +# CONFIG_ESP32_TIME_SYSCALL_USE_FRC1 is not set +# CONFIG_ESP32_TIME_SYSCALL_USE_NONE is not set +CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y +# CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL is not set +# CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC is not set +# CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256 is not set +CONFIG_ESP32_RTC_CLK_CAL_CYCLES=1024 +CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000 +CONFIG_ESP32_XTAL_FREQ_40=y +# CONFIG_ESP32_XTAL_FREQ_26 is not set +# CONFIG_ESP32_XTAL_FREQ_AUTO is not set +CONFIG_ESP32_XTAL_FREQ=40 +# CONFIG_DISABLE_BASIC_ROM_CONSOLE is not set +# CONFIG_NO_BLOBS is not set +# CONFIG_ESP_TIMER_PROFILING is not set +# CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set +CONFIG_ESP_ERR_TO_NAME_LOOKUP=y +CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +# CONFIG_ESP32_WIFI_STATIC_TX_BUFFER is not set +CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER=y +CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=1 +CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM=32 +# CONFIG_ESP32_WIFI_CSI_ENABLED is not set +CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP32_WIFI_TX_BA_WIN=6 +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +CONFIG_ESP32_WIFI_NVS_ENABLED=y +CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y +# CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1 is not set +CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32 +# CONFIG_ESP32_WIFI_DEBUG_LOG_ENABLE is not set +CONFIG_ESP32_WIFI_IRAM_OPT=y +CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y +# CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set +CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP32_PHY_MAX_TX_POWER=20 +# CONFIG_PM_ENABLE is not set +CONFIG_ADC_CAL_EFUSE_TP_ENABLE=y +CONFIG_ADC_CAL_EFUSE_VREF_ENABLE=y +CONFIG_ADC_CAL_LUT_ENABLE=y +# CONFIG_EVENT_LOOP_PROFILING is not set +CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y +CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 +CONFIG_HTTPD_MAX_URI_LEN=512 +CONFIG_HTTPD_ERR_RESP_NO_DELAY=y +CONFIG_HTTPD_PURGE_BUF_LEN=32 +# CONFIG_HTTPD_LOG_PURGE_DATA is not set +# CONFIG_OTA_ALLOW_HTTP is not set +# CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set +# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set +CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y +# CONFIG_ESP32_ENABLE_COREDUMP is not set +CONFIG_DMA_RX_BUF_NUM=10 +CONFIG_DMA_TX_BUF_NUM=10 +CONFIG_EMAC_L2_TO_L3_RX_BUF_MODE=y +CONFIG_EMAC_CHECK_LINK_PERIOD_MS=2000 +CONFIG_EMAC_TASK_PRIORITY=20 +CONFIG_EMAC_TASK_STACK_SIZE=3072 +# CONFIG_FATFS_CODEPAGE_DYNAMIC is not set +CONFIG_FATFS_CODEPAGE_437=y +# CONFIG_FATFS_CODEPAGE_720 is not set +# CONFIG_FATFS_CODEPAGE_737 is not set +# CONFIG_FATFS_CODEPAGE_771 is not set +# CONFIG_FATFS_CODEPAGE_775 is not set +# CONFIG_FATFS_CODEPAGE_850 is not set +# CONFIG_FATFS_CODEPAGE_852 is not set +# CONFIG_FATFS_CODEPAGE_855 is not set +# CONFIG_FATFS_CODEPAGE_857 is not set +# CONFIG_FATFS_CODEPAGE_860 is not set +# CONFIG_FATFS_CODEPAGE_861 is not set +# CONFIG_FATFS_CODEPAGE_862 is not set +# CONFIG_FATFS_CODEPAGE_863 is not set +# CONFIG_FATFS_CODEPAGE_864 is not set +# CONFIG_FATFS_CODEPAGE_865 is not set +# CONFIG_FATFS_CODEPAGE_866 is not set +# CONFIG_FATFS_CODEPAGE_869 is not set +# CONFIG_FATFS_CODEPAGE_932 is not set +# CONFIG_FATFS_CODEPAGE_936 is not set +# CONFIG_FATFS_CODEPAGE_949 is not set +# CONFIG_FATFS_CODEPAGE_950 is not set +CONFIG_FATFS_CODEPAGE=437 +CONFIG_FATFS_LFN_NONE=y +# CONFIG_FATFS_LFN_HEAP is not set +# CONFIG_FATFS_LFN_STACK is not set +CONFIG_FATFS_FS_LOCK=0 +CONFIG_FATFS_TIMEOUT_MS=10000 +CONFIG_FATFS_PER_FILE_CACHE=y +CONFIG_MB_QUEUE_LENGTH=20 +CONFIG_MB_SERIAL_TASK_STACK_SIZE=2048 +CONFIG_MB_SERIAL_BUF_SIZE=256 +CONFIG_MB_SERIAL_TASK_PRIO=10 +# CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT is not set +CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20 +CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20 +CONFIG_MB_CONTROLLER_STACK_SIZE=4096 +CONFIG_MB_EVENT_QUEUE_TIMEOUT=20 +CONFIG_MB_TIMER_PORT_ENABLED=y +CONFIG_MB_TIMER_GROUP=0 +CONFIG_MB_TIMER_INDEX=0 +# CONFIG_FREERTOS_UNICORE is not set +CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF +CONFIG_FREERTOS_CORETIMER_0=y +# CONFIG_FREERTOS_CORETIMER_1 is not set +CONFIG_FREERTOS_HZ=100 +CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y +# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set +CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y +CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 +CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y +# CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE is not set +# CONFIG_FREERTOS_ASSERT_DISABLE is not set +CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536 +CONFIG_FREERTOS_ISR_STACKSIZE=1536 +# CONFIG_FREERTOS_LEGACY_HOOKS is not set +CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 +# CONFIG_SUPPORT_STATIC_ALLOCATION is not set +CONFIG_TIMER_TASK_PRIORITY=1 +CONFIG_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_TIMER_QUEUE_LENGTH=10 +CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 +# CONFIG_FREERTOS_USE_TRACE_FACILITY is not set +# CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS is not set +# CONFIG_FREERTOS_DEBUG_INTERNALS is not set +CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y +CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y +# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set +CONFIG_HEAP_POISONING_DISABLED=y +# CONFIG_HEAP_POISONING_LIGHT is not set +# CONFIG_HEAP_POISONING_COMPREHENSIVE is not set +# CONFIG_HEAP_TRACING is not set +CONFIG_LIBSODIUM_USE_MBEDTLS_SHA=y +# CONFIG_LOG_DEFAULT_LEVEL_NONE is not set +# CONFIG_LOG_DEFAULT_LEVEL_ERROR is not set +# CONFIG_LOG_DEFAULT_LEVEL_WARN is not set +CONFIG_LOG_DEFAULT_LEVEL_INFO=y +# CONFIG_LOG_DEFAULT_LEVEL_DEBUG is not set +# CONFIG_LOG_DEFAULT_LEVEL_VERBOSE is not set +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_LOG_COLORS=y +# CONFIG_L2_TO_L3_COPY is not set +# CONFIG_LWIP_IRAM_OPTIMIZATION is not set +CONFIG_LWIP_MAX_SOCKETS=10 +# CONFIG_USE_ONLY_LWIP_SELECT is not set +CONFIG_LWIP_SO_REUSE=y +CONFIG_LWIP_SO_REUSE_RXTOALL=y +# CONFIG_LWIP_SO_RCVBUF is not set +CONFIG_LWIP_DHCP_MAX_NTP_SERVERS=1 +# CONFIG_LWIP_IP_FRAG is not set +# CONFIG_LWIP_IP_REASSEMBLY is not set +# CONFIG_LWIP_STATS is not set +# CONFIG_LWIP_ETHARP_TRUST_IP_MAC is not set +CONFIG_ESP_GRATUITOUS_ARP=y +CONFIG_GARP_TMR_INTERVAL=60 +CONFIG_TCPIP_RECVMBOX_SIZE=32 +CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y +# CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set +CONFIG_LWIP_DHCPS_LEASE_UNIT=60 +CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 +# CONFIG_LWIP_AUTOIP is not set +CONFIG_LWIP_NETIF_LOOPBACK=y +CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 +CONFIG_LWIP_MAX_ACTIVE_TCP=16 +CONFIG_LWIP_MAX_LISTENING_TCP=16 +CONFIG_TCP_MAXRTX=12 +CONFIG_TCP_SYNMAXRTX=6 +CONFIG_TCP_MSS=1436 +CONFIG_TCP_MSL=60000 +CONFIG_TCP_SND_BUF_DEFAULT=5744 +CONFIG_TCP_WND_DEFAULT=5744 +CONFIG_TCP_RECVMBOX_SIZE=6 +CONFIG_TCP_QUEUE_OOSEQ=y +# CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set +CONFIG_TCP_OVERSIZE_MSS=y +# CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_TCP_OVERSIZE_DISABLE is not set +CONFIG_LWIP_MAX_UDP_PCBS=16 +CONFIG_UDP_RECVMBOX_SIZE=6 +CONFIG_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +# CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set +# CONFIG_TCPIP_TASK_AFFINITY_CPU1 is not set +CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF +# CONFIG_PPP_SUPPORT is not set +# CONFIG_LWIP_MULTICAST_PING is not set +# CONFIG_LWIP_BROADCAST_PING is not set +CONFIG_LWIP_MAX_RAW_PCBS=16 +CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y +# CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC is not set +# CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC is not set +CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN=16384 +# CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN is not set +# CONFIG_MBEDTLS_DEBUG is not set +CONFIG_MBEDTLS_HARDWARE_AES=y +# CONFIG_MBEDTLS_HARDWARE_MPI is not set +# CONFIG_MBEDTLS_HARDWARE_SHA is not set +CONFIG_MBEDTLS_HAVE_TIME=y +# CONFIG_MBEDTLS_HAVE_TIME_DATE is not set +CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y +# CONFIG_MBEDTLS_TLS_SERVER_ONLY is not set +# CONFIG_MBEDTLS_TLS_CLIENT_ONLY is not set +# CONFIG_MBEDTLS_TLS_DISABLED is not set +CONFIG_MBEDTLS_TLS_SERVER=y +CONFIG_MBEDTLS_TLS_CLIENT=y +CONFIG_MBEDTLS_TLS_ENABLED=y +# CONFIG_MBEDTLS_PSK_MODES is not set +CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y +CONFIG_MBEDTLS_SSL_RENEGOTIATION=y +# CONFIG_MBEDTLS_SSL_PROTO_SSL3 is not set +CONFIG_MBEDTLS_SSL_PROTO_TLS1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y +# CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set +CONFIG_MBEDTLS_SSL_ALPN=y +CONFIG_MBEDTLS_SSL_SESSION_TICKETS=y +CONFIG_MBEDTLS_AES_C=y +# CONFIG_MBEDTLS_CAMELLIA_C is not set +# CONFIG_MBEDTLS_DES_C is not set +CONFIG_MBEDTLS_RC4_DISABLED=y +# CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT is not set +# CONFIG_MBEDTLS_RC4_ENABLED is not set +# CONFIG_MBEDTLS_BLOWFISH_C is not set +# CONFIG_MBEDTLS_XTEA_C is not set +CONFIG_MBEDTLS_CCM_C=y +CONFIG_MBEDTLS_GCM_C=y +# CONFIG_MBEDTLS_RIPEMD160_C is not set +CONFIG_MBEDTLS_PEM_PARSE_C=y +CONFIG_MBEDTLS_PEM_WRITE_C=y +CONFIG_MBEDTLS_X509_CRL_PARSE_C=y +CONFIG_MBEDTLS_X509_CSR_PARSE_C=y +CONFIG_MBEDTLS_ECP_C=y +CONFIG_MBEDTLS_ECDH_C=y +CONFIG_MBEDTLS_ECDSA_C=y +CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y +CONFIG_MBEDTLS_ECP_NIST_OPTIM=y +CONFIG_MDNS_MAX_SERVICES=10 +CONFIG_MQTT_PROTOCOL_311=y +CONFIG_MQTT_TRANSPORT_SSL=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y +# CONFIG_MQTT_USE_CUSTOM_CONFIG is not set +# CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED is not set +# CONFIG_MQTT_CUSTOM_OUTBOX is not set +# CONFIG_OPENSSL_DEBUG is not set +CONFIG_OPENSSL_ASSERT_DO_NOTHING=y +# CONFIG_OPENSSL_ASSERT_EXIT is not set +CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_PTHREAD_STACK_MIN=768 +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY=y +# CONFIG_ESP32_DEFAULT_PTHREAD_CORE_0 is not set +# CONFIG_ESP32_DEFAULT_PTHREAD_CORE_1 is not set +CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread" +# CONFIG_SPI_FLASH_VERIFY_WRITE is not set +# CONFIG_SPI_FLASH_ENABLE_COUNTERS is not set +CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y +CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y +# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set +# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set +CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y +CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20 +CONFIG_SPI_FLASH_ERASE_YIELD_TICKS=1 +CONFIG_SPIFFS_MAX_PARTITIONS=3 +CONFIG_SPIFFS_CACHE=y +CONFIG_SPIFFS_CACHE_WR=y +# CONFIG_SPIFFS_CACHE_STATS is not set +CONFIG_SPIFFS_PAGE_CHECK=y +CONFIG_SPIFFS_GC_MAX_RUNS=10 +# CONFIG_SPIFFS_GC_STATS is not set +CONFIG_SPIFFS_PAGE_SIZE=256 +CONFIG_SPIFFS_OBJ_NAME_LEN=32 +CONFIG_SPIFFS_USE_MAGIC=y +CONFIG_SPIFFS_USE_MAGIC_LENGTH=y +CONFIG_SPIFFS_META_LENGTH=4 +CONFIG_SPIFFS_USE_MTIME=y +# CONFIG_SPIFFS_DBG is not set +# CONFIG_SPIFFS_API_DBG is not set +# CONFIG_SPIFFS_GC_DBG is not set +# CONFIG_SPIFFS_CACHE_DBG is not set +# CONFIG_SPIFFS_CHECK_DBG is not set +# CONFIG_SPIFFS_TEST_VISUALISATION is not set +CONFIG_IP_LOST_TIMER_INTERVAL=120 +CONFIG_TCPIP_LWIP=y +CONFIG_UNITY_ENABLE_FLOAT=y +CONFIG_UNITY_ENABLE_DOUBLE=y +# CONFIG_UNITY_ENABLE_COLOR is not set +CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y +# CONFIG_UNITY_ENABLE_FIXTURE is not set +CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_SUPPORT_TERMIOS=y +# CONFIG_WL_SECTOR_SIZE_512 is not set +CONFIG_WL_SECTOR_SIZE_4096=y +CONFIG_WL_SECTOR_SIZE=4096 +CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16 diff --git a/source/native/nf-interpreter/src/CLR/CorLib/CorLib-vs2019.vcxproj b/source/native/nf-interpreter/src/CLR/CorLib/CorLib-vs2019.vcxproj new file mode 100644 index 00000000..1f9a8abd --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/CorLib-vs2019.vcxproj @@ -0,0 +1,212 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + {58E950CC-2FF6-423C-B006-A70A19272F20} + Win32Proj + CorLib + 10.0.17763.0 + CorLib + + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + false + v142 + true + Unicode + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + false + v142 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(SolutionDir)$(Configuration)\ + $(IntDir) + + + $(SolutionDir)$(Configuration)\ + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + NANOCLR_REFLECTION=TRUE;WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\..\HAL\Include;..\..\PAL\Include;..\..\CLR\Helpers\Base64 + + + Windows + + + + + + + Level3 + Disabled + NANOCLR_REFLECTION=TRUE;_DEBUG;_LIB;%(PreprocessorDefinitions) + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + NANOCLR_REFLECTION=TRUE;WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\..\HAL\Include;..\..\PAL\Include;..\..\CLR\Helpers\Base64 + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NANOCLR_REFLECTION=TRUE;NDEBUG;_LIB;%(PreprocessorDefinitions) + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/CorLib/CorLib-vs2019.vcxproj.filters b/source/native/nf-interpreter/src/CLR/CorLib/CorLib-vs2019.vcxproj.filters new file mode 100644 index 00000000..adc9315e --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/CorLib-vs2019.vcxproj.filters @@ -0,0 +1,189 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Header Files + + + Header Files + + + Header Files + + + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/CorLib/CorLib.h b/source/native/nf-interpreter/src/CLR/CorLib/CorLib.h new file mode 100644 index 00000000..10739403 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/CorLib.h @@ -0,0 +1,23 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _NANOCLR_CORLIB_NATIVE_H_ +#define _NANOCLR_CORLIB_NATIVE_H_ + +#include +#include +//#include +//#include +//#include + +#include "corlib_native.h" +#include "nanoCRT.h" + +#if !defined(_WIN32) +#include +#endif // !defined(_WIN32) + +#endif + diff --git a/source/native/nf-interpreter/src/CLR/CorLib/CorLib.vcxproj b/source/native/nf-interpreter/src/CLR/CorLib/CorLib.vcxproj new file mode 100644 index 00000000..206d6e66 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/CorLib.vcxproj @@ -0,0 +1,210 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + {58E950CC-2FF6-423C-B006-A70A19272F20} + Win32Proj + CorLib + 10.0.17763.0 + + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\ + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\ + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + NANOCLR_REFLECTION=TRUE;WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\..\HAL\Include;..\..\PAL\Include;..\..\CLR\Helpers\Base64 + + + Windows + + + + + + + Level3 + Disabled + NANOCLR_REFLECTION=TRUE;_DEBUG;_LIB;%(PreprocessorDefinitions) + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + NANOCLR_REFLECTION=TRUE;WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\..\HAL\Include;..\..\PAL\Include;..\..\CLR\Helpers\Base64 + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NANOCLR_REFLECTION=TRUE;NDEBUG;_LIB;%(PreprocessorDefinitions) + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/CorLib/CorLib.vcxproj.filters b/source/native/nf-interpreter/src/CLR/CorLib/CorLib.vcxproj.filters new file mode 100644 index 00000000..3619d5c5 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/CorLib.vcxproj.filters @@ -0,0 +1,186 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Header Files + + + Header Files + + + Header Files + + + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native.cpp new file mode 100644 index 00000000..7d9549dc --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native.cpp @@ -0,0 +1,1517 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + +#if (NANOCLR_REFLECTION == TRUE) + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + Library_corlib_native_System_Object::Equals___BOOLEAN__OBJECT, + Library_corlib_native_System_Object::GetHashCode___I4, + NULL, + Library_corlib_native_System_Object::GetType___SystemType, + Library_corlib_native_System_Object::MemberwiseClone___OBJECT, + NULL, + Library_corlib_native_System_Object::ReferenceEquals___STATIC__BOOLEAN__OBJECT__OBJECT, + NULL, + Library_corlib_native_System_ValueType::Equals___BOOLEAN__OBJECT, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Exception::get_StackTrace___STRING, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Array::System_Collections_IList_get_Item___OBJECT__I4, + Library_corlib_native_System_Array::System_Collections_IList_set_Item___VOID__I4__OBJECT, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Array::get_Length___I4, + NULL, + NULL, + Library_corlib_native_System_Array::CreateInstance___STATIC__SystemArray__SystemType__I4, + NULL, + Library_corlib_native_System_Array::Copy___STATIC__VOID__SystemArray__I4__SystemArray__I4__I4, + Library_corlib_native_System_Array::Clear___STATIC__VOID__SystemArray__I4__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Array::TrySzIndexOf___STATIC__BOOLEAN__SystemArray__I4__I4__OBJECT__BYREF_I4, + Library_corlib_native_System_Delegate::Equals___BOOLEAN__OBJECT, + Library_corlib_native_System_Delegate::GetInvocationList___SZARRAY_SystemDelegate, + Library_corlib_native_System_Delegate::get_Method___SystemReflectionMethodInfo, + Library_corlib_native_System_Delegate::get_Target___OBJECT, + NULL, + Library_corlib_native_System_Delegate::Combine___STATIC__SystemDelegate__SystemDelegate__SystemDelegate, + Library_corlib_native_System_Delegate::Remove___STATIC__SystemDelegate__SystemDelegate__SystemDelegate, + Library_corlib_native_System_Delegate::op_Equality___STATIC__BOOLEAN__SystemDelegate__SystemDelegate, + Library_corlib_native_System_Delegate::op_Inequality___STATIC__BOOLEAN__SystemDelegate__SystemDelegate, + NULL, + NULL, + Library_corlib_native_System_MulticastDelegate::op_Equality___STATIC__BOOLEAN__SystemMulticastDelegate__SystemMulticastDelegate, + Library_corlib_native_System_MulticastDelegate::op_Inequality___STATIC__BOOLEAN__SystemMulticastDelegate__SystemMulticastDelegate, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_BitConverter::get_IsLittleEndian___STATIC__BOOLEAN, + Library_corlib_native_System_BitConverter::DoubleToInt64Bits___STATIC__I8__R8, + Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__BOOLEAN, + Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__CHAR, + Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__R8, + Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__R4, + Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__I4, + Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__I8, + Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__I2, + Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__U4, + Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__U8, + Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__U2, + Library_corlib_native_System_BitConverter::Int64BitsToDouble___STATIC__R8__I8, + Library_corlib_native_System_BitConverter::ToBoolean___STATIC__BOOLEAN__SZARRAY_U1__I4, + Library_corlib_native_System_BitConverter::ToChar___STATIC__CHAR__SZARRAY_U1__I4, + Library_corlib_native_System_BitConverter::ToDouble___STATIC__R8__SZARRAY_U1__I4, + Library_corlib_native_System_BitConverter::ToInt16___STATIC__I2__SZARRAY_U1__I4, + Library_corlib_native_System_BitConverter::ToInt32___STATIC__I4__SZARRAY_U1__I4, + Library_corlib_native_System_BitConverter::ToInt64___STATIC__I8__SZARRAY_U1__I4, + Library_corlib_native_System_BitConverter::ToSingle___STATIC__R4__SZARRAY_U1__I4, + Library_corlib_native_System_BitConverter::ToString___STATIC__STRING__SZARRAY_U1, + Library_corlib_native_System_BitConverter::ToString___STATIC__STRING__SZARRAY_U1__I4, + Library_corlib_native_System_BitConverter::ToString___STATIC__STRING__SZARRAY_U1__I4__I4, + Library_corlib_native_System_BitConverter::ToUInt16___STATIC__U2__SZARRAY_U1__I4, + Library_corlib_native_System_BitConverter::ToUInt32___STATIC__U4__SZARRAY_U1__I4, + Library_corlib_native_System_BitConverter::ToUInt64___STATIC__U8__SZARRAY_U1__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Collections_ArrayList::get_Item___OBJECT__I4, + Library_corlib_native_System_Collections_ArrayList::set_Item___VOID__I4__OBJECT, + Library_corlib_native_System_Collections_ArrayList::Add___I4__OBJECT, + NULL, + Library_corlib_native_System_Collections_ArrayList::Clear___VOID, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Collections_ArrayList::Insert___VOID__I4__OBJECT, + NULL, + Library_corlib_native_System_Collections_ArrayList::RemoveAt___VOID__I4, + NULL, + NULL, + NULL, + Library_corlib_native_System_Collections_ArrayList::SetCapacity___VOID__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Console::OutNative___STATIC__VOID__STRING__BOOLEAN, + NULL, + NULL, + Library_corlib_native_System_Convert::NativeToInt64___STATIC__I8__STRING__BOOLEAN__I8__I8__I4, + Library_corlib_native_System_Convert::NativeToDouble___STATIC__R8__STRING, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Convert::ToBase64String___STATIC__STRING__SZARRAY_U1__I4__I4__BOOLEAN, + NULL, + NULL, + Library_corlib_native_System_Convert::FromBase64CharArray___STATIC__SZARRAY_U1__SZARRAY_CHAR__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_DateTime::_ctor___VOID__I4__I4__I4__I4__I4__I4__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_DateTime::get_Day___I4, + Library_corlib_native_System_DateTime::get_DayOfWeek___SystemDayOfWeek, + Library_corlib_native_System_DateTime::get_DayOfYear___I4, + Library_corlib_native_System_DateTime::get_Hour___I4, + NULL, + Library_corlib_native_System_DateTime::get_Millisecond___I4, + Library_corlib_native_System_DateTime::get_Minute___I4, + Library_corlib_native_System_DateTime::get_Month___I4, + Library_corlib_native_System_DateTime::get_Second___I4, + NULL, + NULL, + Library_corlib_native_System_DateTime::get_Year___I4, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_DateTime::DaysInMonth___STATIC__I4__I4__I4, + NULL, + Library_corlib_native_System_DateTime::get_UtcNow___STATIC__SystemDateTime, + Library_corlib_native_System_DateTime::get_Today___STATIC__SystemDateTime, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Diagnostics_Debugger::get_IsAttached___STATIC__BOOLEAN, + Library_corlib_native_System_Diagnostics_Debugger::Break___STATIC__VOID, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Double::CompareTo___STATIC__I4__R8__R8, + Library_corlib_native_System_Double::IsInfinity___STATIC__BOOLEAN__R8, + Library_corlib_native_System_Double::IsNaN___STATIC__BOOLEAN__R8, + Library_corlib_native_System_Double::IsNegativeInfinity___STATIC__BOOLEAN__R8, + Library_corlib_native_System_Double::IsPositiveInfinity___STATIC__BOOLEAN__R8, + NULL, + NULL, + Library_corlib_native_System_GC::AnyPendingFinalizers___STATIC__BOOLEAN, + NULL, + Library_corlib_native_System_GC::SuppressFinalize___STATIC__VOID__OBJECT, + Library_corlib_native_System_GC::ReRegisterForFinalize___STATIC__VOID__OBJECT, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Globalization_CultureInfo::get_CurrentUICultureInternal___STATIC__SystemGlobalizationCultureInfo, + Library_corlib_native_System_Globalization_CultureInfo::set_CurrentUICultureInternal___STATIC__VOID__SystemGlobalizationCultureInfo, + Library_corlib_native_System_Globalization_DateTimeFormat::FormatDigits___STATIC__STRING__I4__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Guid::GenerateNewGuid___STATIC__SZARRAY_U1, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_MathInternal::Abs___STATIC__I4__I4, + Library_corlib_native_System_MathInternal::Min___STATIC__I4__I4__I4, + Library_corlib_native_System_MathInternal::Max___STATIC__I4__I4__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Number::FormatNative___STATIC__STRING__OBJECT__CHAR__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Random::Next___I4, + Library_corlib_native_System_Random::Next___I4__I4, + Library_corlib_native_System_Random::NextDouble___R8, + Library_corlib_native_System_Random::NextBytes___VOID__SZARRAY_U1, + Library_corlib_native_System_Random::_ctor___VOID, + Library_corlib_native_System_Random::_ctor___VOID__I4, + Library_corlib_native_System_Reflection_Assembly::get_FullName___STRING, + Library_corlib_native_System_Reflection_Assembly::GetType___SystemType__STRING, + NULL, + Library_corlib_native_System_Reflection_Assembly::GetTypes___SZARRAY_SystemType, + Library_corlib_native_System_Reflection_Assembly::GetVersion___VOID__BYREF_I4__BYREF_I4__BYREF_I4__BYREF_I4, + NULL, + NULL, + Library_corlib_native_System_Reflection_Assembly::GetManifestResourceNames___SZARRAY_STRING, + NULL, + Library_corlib_native_System_Reflection_Assembly::GetExecutingAssembly___STATIC__SystemReflectionAssembly, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Reflection_Assembly::LoadInternal___STATIC__SystemReflectionAssembly__STRING__BOOLEAN__I4__I4__I4__I4, + Library_corlib_native_System_Reflection_Assembly::Load___STATIC__SystemReflectionAssembly__SZARRAY_U1, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Reflection_MethodBase::get_Name___STRING, + Library_corlib_native_System_Reflection_MethodBase::get_DeclaringType___SystemType, + Library_corlib_native_System_Reflection_MethodBase::get_IsPublic___BOOLEAN, + Library_corlib_native_System_Reflection_MethodBase::get_IsStatic___BOOLEAN, + Library_corlib_native_System_Reflection_MethodBase::get_IsFinal___BOOLEAN, + Library_corlib_native_System_Reflection_MethodBase::get_IsVirtual___BOOLEAN, + Library_corlib_native_System_Reflection_MethodBase::get_IsAbstract___BOOLEAN, + Library_corlib_native_System_Reflection_MethodBase::Invoke___OBJECT__OBJECT__SZARRAY_OBJECT, + NULL, + NULL, + Library_corlib_native_System_Reflection_ConstructorInfo::GetCustomAttributes___SZARRAY_OBJECT__BOOLEAN, + Library_corlib_native_System_Reflection_ConstructorInfo::Invoke___OBJECT__SZARRAY_OBJECT, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Reflection_FieldInfo::SetValue___VOID__OBJECT__OBJECT, + Library_corlib_native_System_Reflection_FieldInfo::GetCustomAttributes___SZARRAY_OBJECT__BOOLEAN, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Reflection_PropertyInfo::GetValue___OBJECT__OBJECT__SZARRAY_OBJECT, + Library_corlib_native_System_Reflection_PropertyInfo::SetValue___VOID__OBJECT__OBJECT__SZARRAY_OBJECT, + NULL, + NULL, + Library_corlib_native_System_Reflection_RuntimeFieldInfo::get_Name___STRING, + Library_corlib_native_System_Reflection_RuntimeFieldInfo::get_DeclaringType___SystemType, + Library_corlib_native_System_Reflection_RuntimeFieldInfo::get_FieldType___SystemType, + Library_corlib_native_System_Reflection_RuntimeFieldInfo::GetValue___OBJECT__OBJECT, + NULL, + Library_corlib_native_System_Reflection_RuntimeMethodInfo::get_ReturnType___SystemType, + Library_corlib_native_System_Reflection_RuntimeMethodInfo::GetCustomAttributes___SZARRAY_OBJECT__BOOLEAN, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Runtime_CompilerServices_RuntimeHelpers::InitializeArray___STATIC__VOID__SystemArray__SystemRuntimeFieldHandle, + Library_corlib_native_System_Runtime_CompilerServices_RuntimeHelpers::GetObjectValue___STATIC__OBJECT__OBJECT, + Library_corlib_native_System_Runtime_CompilerServices_RuntimeHelpers::RunClassConstructor___STATIC__VOID__SystemRuntimeTypeHandle, + Library_corlib_native_System_Runtime_CompilerServices_RuntimeHelpers::get_OffsetToStringData___STATIC__I4, + Library_corlib_native_System_Runtime_Remoting_RemotingServices::IsTransparentProxy___STATIC__BOOLEAN__OBJECT, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Type::get_DeclaringType___SystemType, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Type::GetMethod___SystemReflectionMethodInfo__STRING__SystemReflectionBindingFlags, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Type::IsInstanceOfType___BOOLEAN__OBJECT, + NULL, + Library_corlib_native_System_Type::InvokeMember___OBJECT__STRING__SystemReflectionBindingFlags__SystemReflectionBinder__OBJECT__SZARRAY_OBJECT, + Library_corlib_native_System_Type::GetConstructor___SystemReflectionConstructorInfo__SZARRAY_SystemType, + Library_corlib_native_System_Type::GetMethod___SystemReflectionMethodInfo__STRING__SZARRAY_SystemType, + Library_corlib_native_System_Type::GetMethod___SystemReflectionMethodInfo__STRING, + NULL, + NULL, + NULL, + Library_corlib_native_System_Type::get_IsNotPublic___BOOLEAN, + Library_corlib_native_System_Type::get_IsPublic___BOOLEAN, + Library_corlib_native_System_Type::get_IsClass___BOOLEAN, + Library_corlib_native_System_Type::get_IsInterface___BOOLEAN, + Library_corlib_native_System_Type::get_IsValueType___BOOLEAN, + Library_corlib_native_System_Type::get_IsAbstract___BOOLEAN, + Library_corlib_native_System_Type::get_IsEnum___BOOLEAN, + Library_corlib_native_System_Type::get_IsSerializable___BOOLEAN, + Library_corlib_native_System_Type::get_IsArray___BOOLEAN, + NULL, + NULL, + Library_corlib_native_System_Type::GetTypeInternal___STATIC__SystemType__STRING__STRING__BOOLEAN__SZARRAY_I4, + Library_corlib_native_System_Type::GetTypeFromHandle___STATIC__SystemType__SystemRuntimeTypeHandle, + NULL, + NULL, + Library_corlib_native_System_RuntimeType::get_Assembly___SystemReflectionAssembly, + Library_corlib_native_System_RuntimeType::get_Name___STRING, + Library_corlib_native_System_RuntimeType::get_FullName___STRING, + NULL, + Library_corlib_native_System_RuntimeType::get_BaseType___SystemType, + Library_corlib_native_System_RuntimeType::GetMethods___SZARRAY_SystemReflectionMethodInfo__SystemReflectionBindingFlags, + Library_corlib_native_System_RuntimeType::GetField___SystemReflectionFieldInfo__STRING__SystemReflectionBindingFlags, + Library_corlib_native_System_RuntimeType::GetFields___SZARRAY_SystemReflectionFieldInfo__SystemReflectionBindingFlags, + Library_corlib_native_System_RuntimeType::GetInterfaces___SZARRAY_SystemType, + Library_corlib_native_System_RuntimeType::GetElementType___SystemType, + Library_corlib_native_System_RuntimeType::GetCustomAttributes___SZARRAY_OBJECT__BOOLEAN, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_String::CompareTo___I4__OBJECT, + NULL, + Library_corlib_native_System_String::get_Chars___CHAR__I4, + Library_corlib_native_System_String::ToCharArray___SZARRAY_CHAR, + Library_corlib_native_System_String::ToCharArray___SZARRAY_CHAR__I4__I4, + Library_corlib_native_System_String::get_Length___I4, + Library_corlib_native_System_String::Split___SZARRAY_STRING__SZARRAY_CHAR, + Library_corlib_native_System_String::Split___SZARRAY_STRING__SZARRAY_CHAR__I4, + Library_corlib_native_System_String::Substring___STRING__I4, + Library_corlib_native_System_String::Substring___STRING__I4__I4, + Library_corlib_native_System_String::Trim___STRING__SZARRAY_CHAR, + Library_corlib_native_System_String::TrimStart___STRING__SZARRAY_CHAR, + Library_corlib_native_System_String::TrimEnd___STRING__SZARRAY_CHAR, + Library_corlib_native_System_String::_ctor___VOID__SZARRAY_CHAR__I4__I4, + Library_corlib_native_System_String::_ctor___VOID__SZARRAY_CHAR, + Library_corlib_native_System_String::_ctor___VOID__CHAR__I4, + Library_corlib_native_System_String::CompareTo___I4__STRING, + Library_corlib_native_System_String::IndexOf___I4__CHAR, + Library_corlib_native_System_String::IndexOf___I4__CHAR__I4, + Library_corlib_native_System_String::IndexOf___I4__CHAR__I4__I4, + Library_corlib_native_System_String::IndexOfAny___I4__SZARRAY_CHAR, + Library_corlib_native_System_String::IndexOfAny___I4__SZARRAY_CHAR__I4, + Library_corlib_native_System_String::IndexOfAny___I4__SZARRAY_CHAR__I4__I4, + Library_corlib_native_System_String::IndexOf___I4__STRING, + Library_corlib_native_System_String::IndexOf___I4__STRING__I4, + Library_corlib_native_System_String::IndexOf___I4__STRING__I4__I4, + Library_corlib_native_System_String::LastIndexOf___I4__CHAR, + Library_corlib_native_System_String::LastIndexOf___I4__CHAR__I4, + Library_corlib_native_System_String::LastIndexOf___I4__CHAR__I4__I4, + Library_corlib_native_System_String::LastIndexOfAny___I4__SZARRAY_CHAR, + Library_corlib_native_System_String::LastIndexOfAny___I4__SZARRAY_CHAR__I4, + Library_corlib_native_System_String::LastIndexOfAny___I4__SZARRAY_CHAR__I4__I4, + Library_corlib_native_System_String::LastIndexOf___I4__STRING, + Library_corlib_native_System_String::LastIndexOf___I4__STRING__I4, + Library_corlib_native_System_String::LastIndexOf___I4__STRING__I4__I4, + Library_corlib_native_System_String::ToLower___STRING, + Library_corlib_native_System_String::ToUpper___STRING, + Library_corlib_native_System_String::Trim___STRING, + NULL, + NULL, + Library_corlib_native_System_String::Equals___STATIC__BOOLEAN__STRING__STRING, + Library_corlib_native_System_String::op_Equality___STATIC__BOOLEAN__STRING__STRING, + Library_corlib_native_System_String::op_Inequality___STATIC__BOOLEAN__STRING__STRING, + Library_corlib_native_System_String::Compare___STATIC__I4__STRING__STRING, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_String::Concat___STATIC__STRING__STRING__STRING, + Library_corlib_native_System_String::Concat___STATIC__STRING__STRING__STRING__STRING, + Library_corlib_native_System_String::Concat___STATIC__STRING__STRING__STRING__STRING__STRING, + Library_corlib_native_System_String::Concat___STATIC__STRING__SZARRAY_STRING, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Text_UTF8Decoder::Convert___VOID__SZARRAY_U1__I4__I4__SZARRAY_CHAR__I4__I4__BOOLEAN__BYREF_I4__BYREF_I4__BYREF_BOOLEAN, + NULL, + Library_corlib_native_System_Text_UTF8Encoding::GetBytes___SZARRAY_U1__STRING, + Library_corlib_native_System_Text_UTF8Encoding::GetBytes___I4__STRING__I4__I4__SZARRAY_U1__I4, + Library_corlib_native_System_Text_UTF8Encoding::GetChars___SZARRAY_CHAR__SZARRAY_U1, + Library_corlib_native_System_Text_UTF8Encoding::GetChars___SZARRAY_CHAR__SZARRAY_U1__I4__I4, + NULL, + NULL, + Library_corlib_native_System_Threading_WaitHandle::WaitOne___BOOLEAN__I4__BOOLEAN, + NULL, + NULL, + Library_corlib_native_System_Threading_WaitHandle::WaitMultiple___STATIC__I4__SZARRAY_SystemThreadingWaitHandle__I4__BOOLEAN__BOOLEAN, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Threading_AutoResetEvent::_ctor___VOID__BOOLEAN, + Library_corlib_native_System_Threading_AutoResetEvent::Reset___BOOLEAN, + Library_corlib_native_System_Threading_AutoResetEvent::Set___BOOLEAN, + Library_corlib_native_System_Threading_Interlocked::Increment___STATIC__I4__BYREF_I4, + Library_corlib_native_System_Threading_Interlocked::Decrement___STATIC__I4__BYREF_I4, + Library_corlib_native_System_Threading_Interlocked::Exchange___STATIC__I4__BYREF_I4__I4, + Library_corlib_native_System_Threading_Interlocked::CompareExchange___STATIC__I4__BYREF_I4__I4__I4, + Library_corlib_native_System_Threading_ManualResetEvent::_ctor___VOID__BOOLEAN, + Library_corlib_native_System_Threading_ManualResetEvent::Reset___BOOLEAN, + Library_corlib_native_System_Threading_ManualResetEvent::Set___BOOLEAN, + Library_corlib_native_System_Threading_Monitor::Enter___STATIC__VOID__OBJECT, + Library_corlib_native_System_Threading_Monitor::Exit___STATIC__VOID__OBJECT, + Library_corlib_native_System_Threading_Thread::_ctor___VOID__SystemThreadingThreadStart, + Library_corlib_native_System_Threading_Thread::Start___VOID, + Library_corlib_native_System_Threading_Thread::Abort___VOID, + Library_corlib_native_System_Threading_Thread::Suspend___VOID, + Library_corlib_native_System_Threading_Thread::Resume___VOID, + Library_corlib_native_System_Threading_Thread::get_Priority___SystemThreadingThreadPriority, + Library_corlib_native_System_Threading_Thread::set_Priority___VOID__SystemThreadingThreadPriority, + Library_corlib_native_System_Threading_Thread::get_ManagedThreadId___I4, + Library_corlib_native_System_Threading_Thread::get_IsAlive___BOOLEAN, + Library_corlib_native_System_Threading_Thread::Join___VOID, + Library_corlib_native_System_Threading_Thread::Join___BOOLEAN__I4, + Library_corlib_native_System_Threading_Thread::Join___BOOLEAN__SystemTimeSpan, + Library_corlib_native_System_Threading_Thread::get_ThreadState___SystemThreadingThreadState, + Library_corlib_native_System_Threading_Thread::Sleep___STATIC__VOID__I4, + NULL, + Library_corlib_native_System_Threading_Thread::get_CurrentThread___STATIC__SystemThreadingThread, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Threading_Timer::Dispose___VOID, + Library_corlib_native_System_Threading_Timer::_ctor___VOID__SystemThreadingTimerCallback__OBJECT__I4__I4, + Library_corlib_native_System_Threading_Timer::_ctor___VOID__SystemThreadingTimerCallback__OBJECT__SystemTimeSpan__SystemTimeSpan, + Library_corlib_native_System_Threading_Timer::Change___BOOLEAN__I4__I4, + Library_corlib_native_System_Threading_Timer::Change___BOOLEAN__SystemTimeSpan__SystemTimeSpan, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_TimeSpan::Equals___BOOLEAN__OBJECT, + Library_corlib_native_System_TimeSpan::ToString___STRING, + NULL, + NULL, + Library_corlib_native_System_TimeSpan::_ctor___VOID__I4__I4__I4, + Library_corlib_native_System_TimeSpan::_ctor___VOID__I4__I4__I4__I4, + Library_corlib_native_System_TimeSpan::_ctor___VOID__I4__I4__I4__I4__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_TimeSpan::CompareTo___I4__OBJECT, + NULL, + NULL, + NULL, + Library_corlib_native_System_TimeSpan::Compare___STATIC__I4__SystemTimeSpan__SystemTimeSpan, + Library_corlib_native_System_TimeSpan::Equals___STATIC__BOOLEAN__SystemTimeSpan__SystemTimeSpan, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_WeakReference::get_IsAlive___BOOLEAN, + Library_corlib_native_System_WeakReference::get_Target___OBJECT, + Library_corlib_native_System_WeakReference::set_Target___VOID__OBJECT, + Library_corlib_native_System_WeakReference::_ctor___VOID__OBJECT, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +#elif (NANOCLR_REFLECTION == FALSE) + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + Library_corlib_native_System_Object::Equals___BOOLEAN__OBJECT, + Library_corlib_native_System_Object::GetHashCode___I4, + NULL, + Library_corlib_native_System_Object::MemberwiseClone___OBJECT, + NULL, + Library_corlib_native_System_Object::ReferenceEquals___STATIC__BOOLEAN__OBJECT__OBJECT, + NULL, + Library_corlib_native_System_ValueType::Equals___BOOLEAN__OBJECT, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Exception::get_StackTrace___STRING, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Array::System_Collections_IList_get_Item___OBJECT__I4, + Library_corlib_native_System_Array::System_Collections_IList_set_Item___VOID__I4__OBJECT, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Array::get_Length___I4, + NULL, + NULL, + NULL, + Library_corlib_native_System_Array::Copy___STATIC__VOID__SystemArray__I4__SystemArray__I4__I4, + Library_corlib_native_System_Array::Clear___STATIC__VOID__SystemArray__I4__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Array::TrySzIndexOf___STATIC__BOOLEAN__SystemArray__I4__I4__OBJECT__BYREF_I4, + Library_corlib_native_System_Delegate::Equals___BOOLEAN__OBJECT, + NULL, + Library_corlib_native_System_Delegate::Combine___STATIC__SystemDelegate__SystemDelegate__SystemDelegate, + Library_corlib_native_System_Delegate::Remove___STATIC__SystemDelegate__SystemDelegate__SystemDelegate, + Library_corlib_native_System_Delegate::op_Equality___STATIC__BOOLEAN__SystemDelegate__SystemDelegate, + Library_corlib_native_System_Delegate::op_Inequality___STATIC__BOOLEAN__SystemDelegate__SystemDelegate, + NULL, + NULL, + Library_corlib_native_System_MulticastDelegate::op_Equality___STATIC__BOOLEAN__SystemMulticastDelegate__SystemMulticastDelegate, + Library_corlib_native_System_MulticastDelegate::op_Inequality___STATIC__BOOLEAN__SystemMulticastDelegate__SystemMulticastDelegate, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_BitConverter::get_IsLittleEndian___STATIC__BOOLEAN, + Library_corlib_native_System_BitConverter::DoubleToInt64Bits___STATIC__I8__R8, + Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__BOOLEAN, + Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__CHAR, + Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__R8, + Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__R4, + Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__I4, + Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__I8, + Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__I2, + Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__U4, + Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__U8, + Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__U2, + Library_corlib_native_System_BitConverter::Int64BitsToDouble___STATIC__R8__I8, + Library_corlib_native_System_BitConverter::ToBoolean___STATIC__BOOLEAN__SZARRAY_U1__I4, + Library_corlib_native_System_BitConverter::ToChar___STATIC__CHAR__SZARRAY_U1__I4, + Library_corlib_native_System_BitConverter::ToDouble___STATIC__R8__SZARRAY_U1__I4, + Library_corlib_native_System_BitConverter::ToInt16___STATIC__I2__SZARRAY_U1__I4, + Library_corlib_native_System_BitConverter::ToInt32___STATIC__I4__SZARRAY_U1__I4, + Library_corlib_native_System_BitConverter::ToInt64___STATIC__I8__SZARRAY_U1__I4, + Library_corlib_native_System_BitConverter::ToSingle___STATIC__R4__SZARRAY_U1__I4, + Library_corlib_native_System_BitConverter::ToString___STATIC__STRING__SZARRAY_U1, + Library_corlib_native_System_BitConverter::ToString___STATIC__STRING__SZARRAY_U1__I4, + Library_corlib_native_System_BitConverter::ToString___STATIC__STRING__SZARRAY_U1__I4__I4, + Library_corlib_native_System_BitConverter::ToUInt16___STATIC__U2__SZARRAY_U1__I4, + Library_corlib_native_System_BitConverter::ToUInt32___STATIC__U4__SZARRAY_U1__I4, + Library_corlib_native_System_BitConverter::ToUInt64___STATIC__U8__SZARRAY_U1__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Collections_ArrayList::get_Item___OBJECT__I4, + Library_corlib_native_System_Collections_ArrayList::set_Item___VOID__I4__OBJECT, + Library_corlib_native_System_Collections_ArrayList::Add___I4__OBJECT, + NULL, + Library_corlib_native_System_Collections_ArrayList::Clear___VOID, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Collections_ArrayList::Insert___VOID__I4__OBJECT, + NULL, + Library_corlib_native_System_Collections_ArrayList::RemoveAt___VOID__I4, + NULL, + Library_corlib_native_System_Collections_ArrayList::SetCapacity___VOID__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Console::OutNative___STATIC__VOID__STRING__BOOLEAN, + NULL, + NULL, + Library_corlib_native_System_Convert::NativeToInt64___STATIC__I8__STRING__BOOLEAN__I8__I8__I4, + Library_corlib_native_System_Convert::NativeToDouble___STATIC__R8__STRING, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Convert::ToBase64String___STATIC__STRING__SZARRAY_U1__I4__I4__BOOLEAN, + NULL, + NULL, + Library_corlib_native_System_Convert::FromBase64CharArray___STATIC__SZARRAY_U1__SZARRAY_CHAR__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_DateTime::_ctor___VOID__I4__I4__I4__I4__I4__I4__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_DateTime::get_Day___I4, + Library_corlib_native_System_DateTime::get_DayOfWeek___SystemDayOfWeek, + Library_corlib_native_System_DateTime::get_DayOfYear___I4, + Library_corlib_native_System_DateTime::get_Hour___I4, + NULL, + Library_corlib_native_System_DateTime::get_Millisecond___I4, + Library_corlib_native_System_DateTime::get_Minute___I4, + Library_corlib_native_System_DateTime::get_Month___I4, + Library_corlib_native_System_DateTime::get_Second___I4, + NULL, + NULL, + Library_corlib_native_System_DateTime::get_Year___I4, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_DateTime::DaysInMonth___STATIC__I4__I4__I4, + NULL, + Library_corlib_native_System_DateTime::get_UtcNow___STATIC__SystemDateTime, + Library_corlib_native_System_DateTime::get_Today___STATIC__SystemDateTime, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Diagnostics_Debugger::get_IsAttached___STATIC__BOOLEAN, + Library_corlib_native_System_Diagnostics_Debugger::Break___STATIC__VOID, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Double::CompareTo___STATIC__I4__R8__R8, + Library_corlib_native_System_Double::IsInfinity___STATIC__BOOLEAN__R8, + Library_corlib_native_System_Double::IsNaN___STATIC__BOOLEAN__R8, + Library_corlib_native_System_Double::IsNegativeInfinity___STATIC__BOOLEAN__R8, + Library_corlib_native_System_Double::IsPositiveInfinity___STATIC__BOOLEAN__R8, + NULL, + NULL, + Library_corlib_native_System_GC::AnyPendingFinalizers___STATIC__BOOLEAN, + NULL, + Library_corlib_native_System_GC::SuppressFinalize___STATIC__VOID__OBJECT, + Library_corlib_native_System_GC::ReRegisterForFinalize___STATIC__VOID__OBJECT, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Globalization_CultureInfo::get_CurrentUICultureInternal___STATIC__SystemGlobalizationCultureInfo, + Library_corlib_native_System_Globalization_CultureInfo::set_CurrentUICultureInternal___STATIC__VOID__SystemGlobalizationCultureInfo, + Library_corlib_native_System_Globalization_DateTimeFormat::FormatDigits___STATIC__STRING__I4__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Guid::GenerateNewGuid___STATIC__SZARRAY_U1, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_MathInternal::Abs___STATIC__I4__I4, + Library_corlib_native_System_MathInternal::Min___STATIC__I4__I4__I4, + Library_corlib_native_System_MathInternal::Max___STATIC__I4__I4__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Number::FormatNative___STATIC__STRING__OBJECT__CHAR__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Random::Next___I4, + Library_corlib_native_System_Random::Next___I4__I4, + Library_corlib_native_System_Random::NextDouble___R8, + Library_corlib_native_System_Random::NextBytes___VOID__SZARRAY_U1, + Library_corlib_native_System_Random::_ctor___VOID, + Library_corlib_native_System_Random::_ctor___VOID__I4, + NULL, + NULL, + NULL, + Library_corlib_native_System_Runtime_CompilerServices_RuntimeHelpers::InitializeArray___STATIC__VOID__SystemArray__SystemRuntimeFieldHandle, + Library_corlib_native_System_Runtime_CompilerServices_RuntimeHelpers::GetObjectValue___STATIC__OBJECT__OBJECT, + Library_corlib_native_System_Runtime_CompilerServices_RuntimeHelpers::RunClassConstructor___STATIC__VOID__SystemRuntimeTypeHandle, + Library_corlib_native_System_Runtime_CompilerServices_RuntimeHelpers::get_OffsetToStringData___STATIC__I4, + Library_corlib_native_System_Runtime_Remoting_RemotingServices::IsTransparentProxy___STATIC__BOOLEAN__OBJECT, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_String::CompareTo___I4__OBJECT, + NULL, + Library_corlib_native_System_String::get_Chars___CHAR__I4, + Library_corlib_native_System_String::ToCharArray___SZARRAY_CHAR, + Library_corlib_native_System_String::ToCharArray___SZARRAY_CHAR__I4__I4, + Library_corlib_native_System_String::get_Length___I4, + Library_corlib_native_System_String::Split___SZARRAY_STRING__SZARRAY_CHAR, + Library_corlib_native_System_String::Split___SZARRAY_STRING__SZARRAY_CHAR__I4, + Library_corlib_native_System_String::Substring___STRING__I4, + Library_corlib_native_System_String::Substring___STRING__I4__I4, + Library_corlib_native_System_String::Trim___STRING__SZARRAY_CHAR, + Library_corlib_native_System_String::TrimStart___STRING__SZARRAY_CHAR, + Library_corlib_native_System_String::TrimEnd___STRING__SZARRAY_CHAR, + Library_corlib_native_System_String::_ctor___VOID__SZARRAY_CHAR__I4__I4, + Library_corlib_native_System_String::_ctor___VOID__SZARRAY_CHAR, + Library_corlib_native_System_String::_ctor___VOID__CHAR__I4, + Library_corlib_native_System_String::CompareTo___I4__STRING, + Library_corlib_native_System_String::IndexOf___I4__CHAR, + Library_corlib_native_System_String::IndexOf___I4__CHAR__I4, + Library_corlib_native_System_String::IndexOf___I4__CHAR__I4__I4, + Library_corlib_native_System_String::IndexOfAny___I4__SZARRAY_CHAR, + Library_corlib_native_System_String::IndexOfAny___I4__SZARRAY_CHAR__I4, + Library_corlib_native_System_String::IndexOfAny___I4__SZARRAY_CHAR__I4__I4, + Library_corlib_native_System_String::IndexOf___I4__STRING, + Library_corlib_native_System_String::IndexOf___I4__STRING__I4, + Library_corlib_native_System_String::IndexOf___I4__STRING__I4__I4, + Library_corlib_native_System_String::LastIndexOf___I4__CHAR, + Library_corlib_native_System_String::LastIndexOf___I4__CHAR__I4, + Library_corlib_native_System_String::LastIndexOf___I4__CHAR__I4__I4, + Library_corlib_native_System_String::LastIndexOfAny___I4__SZARRAY_CHAR, + Library_corlib_native_System_String::LastIndexOfAny___I4__SZARRAY_CHAR__I4, + Library_corlib_native_System_String::LastIndexOfAny___I4__SZARRAY_CHAR__I4__I4, + Library_corlib_native_System_String::LastIndexOf___I4__STRING, + Library_corlib_native_System_String::LastIndexOf___I4__STRING__I4, + Library_corlib_native_System_String::LastIndexOf___I4__STRING__I4__I4, + Library_corlib_native_System_String::ToLower___STRING, + Library_corlib_native_System_String::ToUpper___STRING, + Library_corlib_native_System_String::Trim___STRING, + NULL, + NULL, + Library_corlib_native_System_String::Equals___STATIC__BOOLEAN__STRING__STRING, + Library_corlib_native_System_String::op_Equality___STATIC__BOOLEAN__STRING__STRING, + Library_corlib_native_System_String::op_Inequality___STATIC__BOOLEAN__STRING__STRING, + Library_corlib_native_System_String::Compare___STATIC__I4__STRING__STRING, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_String::Concat___STATIC__STRING__STRING__STRING, + Library_corlib_native_System_String::Concat___STATIC__STRING__STRING__STRING__STRING, + Library_corlib_native_System_String::Concat___STATIC__STRING__STRING__STRING__STRING__STRING, + Library_corlib_native_System_String::Concat___STATIC__STRING__SZARRAY_STRING, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Text_UTF8Decoder::Convert___VOID__SZARRAY_U1__I4__I4__SZARRAY_CHAR__I4__I4__BOOLEAN__BYREF_I4__BYREF_I4__BYREF_BOOLEAN, + NULL, + Library_corlib_native_System_Text_UTF8Encoding::GetBytes___SZARRAY_U1__STRING, + Library_corlib_native_System_Text_UTF8Encoding::GetBytes___I4__STRING__I4__I4__SZARRAY_U1__I4, + Library_corlib_native_System_Text_UTF8Encoding::GetChars___SZARRAY_CHAR__SZARRAY_U1, + Library_corlib_native_System_Text_UTF8Encoding::GetChars___SZARRAY_CHAR__SZARRAY_U1__I4__I4, + NULL, + NULL, + Library_corlib_native_System_Threading_WaitHandle::WaitOne___BOOLEAN__I4__BOOLEAN, + NULL, + NULL, + Library_corlib_native_System_Threading_WaitHandle::WaitMultiple___STATIC__I4__SZARRAY_SystemThreadingWaitHandle__I4__BOOLEAN__BOOLEAN, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Threading_AutoResetEvent::_ctor___VOID__BOOLEAN, + Library_corlib_native_System_Threading_AutoResetEvent::Reset___BOOLEAN, + Library_corlib_native_System_Threading_AutoResetEvent::Set___BOOLEAN, + Library_corlib_native_System_Threading_Interlocked::Increment___STATIC__I4__BYREF_I4, + Library_corlib_native_System_Threading_Interlocked::Decrement___STATIC__I4__BYREF_I4, + Library_corlib_native_System_Threading_Interlocked::Exchange___STATIC__I4__BYREF_I4__I4, + Library_corlib_native_System_Threading_Interlocked::CompareExchange___STATIC__I4__BYREF_I4__I4__I4, + Library_corlib_native_System_Threading_ManualResetEvent::_ctor___VOID__BOOLEAN, + Library_corlib_native_System_Threading_ManualResetEvent::Reset___BOOLEAN, + Library_corlib_native_System_Threading_ManualResetEvent::Set___BOOLEAN, + Library_corlib_native_System_Threading_Monitor::Enter___STATIC__VOID__OBJECT, + Library_corlib_native_System_Threading_Monitor::Exit___STATIC__VOID__OBJECT, + Library_corlib_native_System_Threading_Thread::_ctor___VOID__SystemThreadingThreadStart, + Library_corlib_native_System_Threading_Thread::Start___VOID, + Library_corlib_native_System_Threading_Thread::Abort___VOID, + Library_corlib_native_System_Threading_Thread::Suspend___VOID, + Library_corlib_native_System_Threading_Thread::Resume___VOID, + Library_corlib_native_System_Threading_Thread::get_Priority___SystemThreadingThreadPriority, + Library_corlib_native_System_Threading_Thread::set_Priority___VOID__SystemThreadingThreadPriority, + Library_corlib_native_System_Threading_Thread::get_ManagedThreadId___I4, + Library_corlib_native_System_Threading_Thread::get_IsAlive___BOOLEAN, + Library_corlib_native_System_Threading_Thread::Join___VOID, + Library_corlib_native_System_Threading_Thread::Join___BOOLEAN__I4, + Library_corlib_native_System_Threading_Thread::Join___BOOLEAN__SystemTimeSpan, + Library_corlib_native_System_Threading_Thread::get_ThreadState___SystemThreadingThreadState, + Library_corlib_native_System_Threading_Thread::Sleep___STATIC__VOID__I4, + NULL, + Library_corlib_native_System_Threading_Thread::get_CurrentThread___STATIC__SystemThreadingThread, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_Threading_Timer::Dispose___VOID, + Library_corlib_native_System_Threading_Timer::_ctor___VOID__SystemThreadingTimerCallback__OBJECT__I4__I4, + Library_corlib_native_System_Threading_Timer::_ctor___VOID__SystemThreadingTimerCallback__OBJECT__SystemTimeSpan__SystemTimeSpan, + Library_corlib_native_System_Threading_Timer::Change___BOOLEAN__I4__I4, + Library_corlib_native_System_Threading_Timer::Change___BOOLEAN__SystemTimeSpan__SystemTimeSpan, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_TimeSpan::Equals___BOOLEAN__OBJECT, + Library_corlib_native_System_TimeSpan::ToString___STRING, + NULL, + NULL, + Library_corlib_native_System_TimeSpan::_ctor___VOID__I4__I4__I4, + Library_corlib_native_System_TimeSpan::_ctor___VOID__I4__I4__I4__I4, + Library_corlib_native_System_TimeSpan::_ctor___VOID__I4__I4__I4__I4__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_TimeSpan::CompareTo___I4__OBJECT, + NULL, + NULL, + NULL, + Library_corlib_native_System_TimeSpan::Compare___STATIC__I4__SystemTimeSpan__SystemTimeSpan, + Library_corlib_native_System_TimeSpan::Equals___STATIC__BOOLEAN__SystemTimeSpan__SystemTimeSpan, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_corlib_native_System_WeakReference::get_IsAlive___BOOLEAN, + Library_corlib_native_System_WeakReference::get_Target___OBJECT, + Library_corlib_native_System_WeakReference::set_Target___VOID__OBJECT, + Library_corlib_native_System_WeakReference::_ctor___VOID__OBJECT, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +#else +#error "NANOCLR_REFLECTION has to be define either TRUE or FALSE. Check the build options." +#endif + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_mscorlib = +{ + "mscorlib", + +#if (NANOCLR_REFLECTION == TRUE) + + 0xDCB6AEBA, + +#elif (NANOCLR_REFLECTION == FALSE) + + 0x7E26EC5E, + +#else +#error "NANOCLR_REFLECTION has to be define either TRUE or FALSE. Check the build options." +#endif + + method_lookup, + { 100, 4, 5, 0 } +}; diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native.h b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native.h new file mode 100644 index 00000000..45c1ce83 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native.h @@ -0,0 +1,1064 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#ifndef _CORLIB_NATIVE_H_ +#define _CORLIB_NATIVE_H_ + +#include +#include +#include + +struct Library_corlib_native_System_Object +{ + NANOCLR_NATIVE_DECLARE(Equals___BOOLEAN__OBJECT); + NANOCLR_NATIVE_DECLARE(GetHashCode___I4); + NANOCLR_NATIVE_DECLARE(GetType___SystemType); + NANOCLR_NATIVE_DECLARE(MemberwiseClone___OBJECT); + NANOCLR_NATIVE_DECLARE(ReferenceEquals___STATIC__BOOLEAN__OBJECT__OBJECT); + + //--// + +}; + +struct Library_corlib_native_System_ValueType +{ + NANOCLR_NATIVE_DECLARE(Equals___BOOLEAN__OBJECT); + + //--// + +}; + +struct Library_corlib_native_System_Collections_Hashtable +{ + static const int FIELD___buckets = 1; + static const int FIELD___numberOfBuckets = 2; + static const int FIELD___count = 3; + static const int FIELD___loadFactor = 4; + static const int FIELD___maxLoadFactor = 5; + static const int FIELD___growthFactor = 6; + + + //--// + +}; + +struct Library_corlib_native_System_Collections_Hashtable__Entry +{ + static const int FIELD__key = 1; + static const int FIELD__value = 2; + static const int FIELD__next = 3; + + + //--// + +}; + +struct Library_corlib_native_System_Collections_Hashtable__HashtableEnumerator +{ + static const int FIELD__ht = 1; + static const int FIELD__temp = 2; + static const int FIELD__index = 3; + static const int FIELD__returnType = 4; + + + //--// + +}; + +struct Library_corlib_native_System_Exception +{ + static const int FIELD___message = 1; + static const int FIELD___innerException = 2; + static const int FIELD___stackTrace = 3; + static const int FIELD__HResult = 4; + + NANOCLR_NATIVE_DECLARE(get_StackTrace___STRING); + + //--// + + struct StackTrace + { + CLR_RT_MethodDef_Index m_md; + CLR_UINT32 m_IP; + }; + + static HRESULT CreateInstance( CLR_RT_HeapBlock& ref, HRESULT hr, CLR_RT_StackFrame* stack ); + static HRESULT CreateInstance( CLR_RT_HeapBlock& ref, const CLR_RT_TypeDef_Index& cls , HRESULT hr, CLR_RT_StackFrame* stack ); + static HRESULT SetStackTrace ( CLR_RT_HeapBlock& ref, CLR_RT_StackFrame* stack ); + + static CLR_RT_HeapBlock* GetTarget ( CLR_RT_HeapBlock& ref ); + static StackTrace* GetStackTrace( CLR_RT_HeapBlock* obj, CLR_UINT32& depth ); + + //--// + + static const char* GetMessage( CLR_RT_HeapBlock* obj ) { return obj[ Library_corlib_native_System_Exception::FIELD___message ].RecoverString() ; } + static CLR_UINT32 GetHResult( CLR_RT_HeapBlock* obj ) { return obj[ Library_corlib_native_System_Exception::FIELD__HResult ].NumericByRef().u4; } +}; + +struct Library_corlib_native_System_Collections_Hashtable__KeyCollection +{ + static const int FIELD__ht = 1; + + + //--// + +}; + +#if (NANOCLR_REFLECTION == TRUE) + +struct Library_corlib_native_System_AppDomain +{ + static const int FIELD___appDomain = 1; + static const int FIELD___friendlyName = 2; + + NANOCLR_NATIVE_DECLARE(GetAssemblies___SZARRAY_SystemReflectionAssembly); + NANOCLR_NATIVE_DECLARE(LoadInternal___SystemReflectionAssembly__STRING__BOOLEAN__I4__I4__I4__I4); + NANOCLR_NATIVE_DECLARE(CreateDomain___STATIC__SystemAppDomain__STRING); + NANOCLR_NATIVE_DECLARE(Unload___STATIC__VOID__SystemAppDomain); + + //--// +#if defined(NANOCLR_APPDOMAINS) + static HRESULT GetAppDomain( CLR_RT_HeapBlock& ref, CLR_RT_AppDomain*& appDomain, CLR_RT_AppDomain*& appDomainSav, bool fCheckForUnloadingAppDomain ); +#endif +}; + +#endif // NANOCLR_REFLECTION + +struct Library_corlib_native_System_ArgumentException +{ + static const int FIELD___paramName = 5; + + + //--// + +}; + +struct Library_corlib_native_System_Array +{ + NANOCLR_NATIVE_DECLARE(System_Collections_IList_get_Item___OBJECT__I4); + NANOCLR_NATIVE_DECLARE(System_Collections_IList_set_Item___VOID__I4__OBJECT); + NANOCLR_NATIVE_DECLARE(get_Length___I4); +#if (NANOCLR_REFLECTION == TRUE) + NANOCLR_NATIVE_DECLARE(CreateInstance___STATIC__SystemArray__SystemType__I4); +#endif // NANOCLR_REFLECTION + NANOCLR_NATIVE_DECLARE(Copy___STATIC__VOID__SystemArray__I4__SystemArray__I4__I4); + NANOCLR_NATIVE_DECLARE(Clear___STATIC__VOID__SystemArray__I4__I4); + NANOCLR_NATIVE_DECLARE(TrySzIndexOf___STATIC__BOOLEAN__SystemArray__I4__I4__OBJECT__BYREF_I4); + + //--// + + static HRESULT Clear ( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock& arg , int index , int length ); + static HRESULT Copy ( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock& argSrc, int indexSrc, CLR_RT_HeapBlock& argDst, int indexDst, int length ); + static HRESULT TrySzIndexOf( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock& argSrc, CLR_RT_HeapBlock& match , int start , int stop , bool fForward, CLR_RT_HeapBlock& retValue ); +}; + +struct Library_corlib_native_System_Delegate +{ + NANOCLR_NATIVE_DECLARE(Equals___BOOLEAN__OBJECT); + NANOCLR_NATIVE_DECLARE(Combine___STATIC__SystemDelegate__SystemDelegate__SystemDelegate); + NANOCLR_NATIVE_DECLARE(Remove___STATIC__SystemDelegate__SystemDelegate__SystemDelegate); + NANOCLR_NATIVE_DECLARE(op_Equality___STATIC__BOOLEAN__SystemDelegate__SystemDelegate); + NANOCLR_NATIVE_DECLARE(op_Inequality___STATIC__BOOLEAN__SystemDelegate__SystemDelegate); + +#if (NANOCLR_REFLECTION == TRUE) + NANOCLR_NATIVE_DECLARE(GetInvocationList___SZARRAY_SystemDelegate); + NANOCLR_NATIVE_DECLARE(get_Method___SystemReflectionMethodInfo); + NANOCLR_NATIVE_DECLARE(get_Target___OBJECT); +#endif // NANOCLR_REFLECTION + + //--// + + static CLR_RT_HeapBlock_Delegate* GetLastDelegate( CLR_RT_HeapBlock_Delegate* dlg ); +}; + +struct Library_corlib_native_System_MulticastDelegate +{ + NANOCLR_NATIVE_DECLARE(op_Equality___STATIC__BOOLEAN__SystemMulticastDelegate__SystemMulticastDelegate); + NANOCLR_NATIVE_DECLARE(op_Inequality___STATIC__BOOLEAN__SystemMulticastDelegate__SystemMulticastDelegate); + + //--// + +}; + +struct Library_corlib_native_System_BitConverter +{ + NANOCLR_NATIVE_DECLARE(get_IsLittleEndian___STATIC__BOOLEAN); + NANOCLR_NATIVE_DECLARE(DoubleToInt64Bits___STATIC__I8__R8); + NANOCLR_NATIVE_DECLARE(GetBytes___STATIC__SZARRAY_U1__BOOLEAN); + NANOCLR_NATIVE_DECLARE(GetBytes___STATIC__SZARRAY_U1__CHAR); + NANOCLR_NATIVE_DECLARE(GetBytes___STATIC__SZARRAY_U1__R8); + NANOCLR_NATIVE_DECLARE(GetBytes___STATIC__SZARRAY_U1__R4); + NANOCLR_NATIVE_DECLARE(GetBytes___STATIC__SZARRAY_U1__I4); + NANOCLR_NATIVE_DECLARE(GetBytes___STATIC__SZARRAY_U1__I8); + NANOCLR_NATIVE_DECLARE(GetBytes___STATIC__SZARRAY_U1__I2); + NANOCLR_NATIVE_DECLARE(GetBytes___STATIC__SZARRAY_U1__U4); + NANOCLR_NATIVE_DECLARE(GetBytes___STATIC__SZARRAY_U1__U8); + NANOCLR_NATIVE_DECLARE(GetBytes___STATIC__SZARRAY_U1__U2); + NANOCLR_NATIVE_DECLARE(Int64BitsToDouble___STATIC__R8__I8); + NANOCLR_NATIVE_DECLARE(ToBoolean___STATIC__BOOLEAN__SZARRAY_U1__I4); + NANOCLR_NATIVE_DECLARE(ToChar___STATIC__CHAR__SZARRAY_U1__I4); + NANOCLR_NATIVE_DECLARE(ToDouble___STATIC__R8__SZARRAY_U1__I4); + NANOCLR_NATIVE_DECLARE(ToInt16___STATIC__I2__SZARRAY_U1__I4); + NANOCLR_NATIVE_DECLARE(ToInt32___STATIC__I4__SZARRAY_U1__I4); + NANOCLR_NATIVE_DECLARE(ToInt64___STATIC__I8__SZARRAY_U1__I4); + NANOCLR_NATIVE_DECLARE(ToSingle___STATIC__R4__SZARRAY_U1__I4); + NANOCLR_NATIVE_DECLARE(ToString___STATIC__STRING__SZARRAY_U1); + NANOCLR_NATIVE_DECLARE(ToString___STATIC__STRING__SZARRAY_U1__I4); + NANOCLR_NATIVE_DECLARE(ToString___STATIC__STRING__SZARRAY_U1__I4__I4); + NANOCLR_NATIVE_DECLARE(ToUInt16___STATIC__U2__SZARRAY_U1__I4); + NANOCLR_NATIVE_DECLARE(ToUInt32___STATIC__U4__SZARRAY_U1__I4); + NANOCLR_NATIVE_DECLARE(ToUInt64___STATIC__U8__SZARRAY_U1__I4); + + //--// + +}; + +struct Library_corlib_native_System_Boolean +{ + static const int FIELD_STATIC__FalseString = 0; + static const int FIELD_STATIC__TrueString = 1; + + static const int FIELD___value = 1; + + + //--// + +}; + +struct Library_corlib_native_System_Byte +{ + static const int FIELD___value = 1; + + + //--// + +}; + +struct Library_corlib_native_System_Char +{ + static const int FIELD___value = 1; + + + //--// + +}; + +struct Library_corlib_native_System_Collections_ArrayList +{ + static const int FIELD___items = 1; + static const int FIELD___size = 2; + + NANOCLR_NATIVE_DECLARE(get_Item___OBJECT__I4); + NANOCLR_NATIVE_DECLARE(set_Item___VOID__I4__OBJECT); + NANOCLR_NATIVE_DECLARE(Add___I4__OBJECT); + NANOCLR_NATIVE_DECLARE(Clear___VOID); + NANOCLR_NATIVE_DECLARE(Insert___VOID__I4__OBJECT); + NANOCLR_NATIVE_DECLARE(RemoveAt___VOID__I4); + NANOCLR_NATIVE_DECLARE(SetCapacity___VOID__I4); + + //--// + +}; + +struct Library_corlib_native_System_Console +{ + NANOCLR_NATIVE_DECLARE(OutNative___STATIC__VOID__STRING__BOOLEAN); + + //--// + +}; + +struct Library_corlib_native_System_Convert +{ + NANOCLR_NATIVE_DECLARE(NativeToInt64___STATIC__I8__STRING__BOOLEAN__I8__I8__I4); + NANOCLR_NATIVE_DECLARE(NativeToDouble___STATIC__R8__STRING); + NANOCLR_NATIVE_DECLARE(ToBase64String___STATIC__STRING__SZARRAY_U1__I4__I4__BOOLEAN); + NANOCLR_NATIVE_DECLARE(FromBase64CharArray___STATIC__SZARRAY_U1__SZARRAY_CHAR__I4); + + //--// + + static double GetDoubleFractionalPart(char* str, int length); + static int64_t GetIntegerPart(char* str, int length); + static int64_t GetIntegerFromHexString(char* str); +}; + +struct Library_corlib_native_System_DateTime +{ + static const int FIELD_STATIC__MinValue = 2; + static const int FIELD_STATIC__MaxValue = 3; + static const int FIELD_STATIC__UnixEpoch = 4; + + static const int FIELD___ticks = 1; + + NANOCLR_NATIVE_DECLARE(_ctor___VOID__I4__I4__I4__I4__I4__I4__I4); + NANOCLR_NATIVE_DECLARE(get_Day___I4); + NANOCLR_NATIVE_DECLARE(get_DayOfWeek___SystemDayOfWeek); + NANOCLR_NATIVE_DECLARE(get_DayOfYear___I4); + NANOCLR_NATIVE_DECLARE(get_Hour___I4); + NANOCLR_NATIVE_DECLARE(get_Millisecond___I4); + NANOCLR_NATIVE_DECLARE(get_Minute___I4); + NANOCLR_NATIVE_DECLARE(get_Month___I4); + NANOCLR_NATIVE_DECLARE(get_Second___I4); + NANOCLR_NATIVE_DECLARE(get_Year___I4); + NANOCLR_NATIVE_DECLARE(DaysInMonth___STATIC__I4__I4__I4); + NANOCLR_NATIVE_DECLARE(get_UtcNow___STATIC__SystemDateTime); + NANOCLR_NATIVE_DECLARE(get_Today___STATIC__SystemDateTime); + + //--// + + static CLR_INT64* NewObject ( CLR_RT_StackFrame& stack ); + static CLR_INT64* GetValuePtr( CLR_RT_StackFrame& stack ); + static CLR_INT64* GetValuePtr( CLR_RT_HeapBlock& ref ); + + static void Expand ( CLR_RT_StackFrame& stack, SYSTEMTIME& st ); + static void Compress( CLR_RT_StackFrame& stack, const SYSTEMTIME& st ); +}; + +struct Library_corlib_native_System_Diagnostics_Debugger +{ + NANOCLR_NATIVE_DECLARE(get_IsAttached___STATIC__BOOLEAN); + NANOCLR_NATIVE_DECLARE(Break___STATIC__VOID); + + //--// + +}; + +struct Library_corlib_native_System_Diagnostics_DebuggerBrowsableAttribute +{ + static const int FIELD___state = 1; + + + //--// + +}; + +struct Library_corlib_native_System_Double +{ + static const int FIELD___value = 1; + + NANOCLR_NATIVE_DECLARE(CompareTo___STATIC__I4__R8__R8); + NANOCLR_NATIVE_DECLARE(IsInfinity___STATIC__BOOLEAN__R8); + NANOCLR_NATIVE_DECLARE(IsNaN___STATIC__BOOLEAN__R8); + NANOCLR_NATIVE_DECLARE(IsNegativeInfinity___STATIC__BOOLEAN__R8); + NANOCLR_NATIVE_DECLARE(IsPositiveInfinity___STATIC__BOOLEAN__R8); + + //--// + +}; + +struct Library_corlib_native_System_GC +{ + NANOCLR_NATIVE_DECLARE(AnyPendingFinalizers___STATIC__BOOLEAN); + NANOCLR_NATIVE_DECLARE(SuppressFinalize___STATIC__VOID__OBJECT); + NANOCLR_NATIVE_DECLARE(ReRegisterForFinalize___STATIC__VOID__OBJECT); + + //--// + +}; + +struct Library_corlib_native_System_Globalization_CultureInfo +{ + static const int FIELD___numInfo = 1; + static const int FIELD___dateTimeInfo = 2; + static const int FIELD___cultureInfoName = 3; + static const int FIELD___name = 4; + static const int FIELD___parent = 5; + + NANOCLR_NATIVE_DECLARE(get_CurrentUICultureInternal___STATIC__SystemGlobalizationCultureInfo); + NANOCLR_NATIVE_DECLARE(set_CurrentUICultureInternal___STATIC__VOID__SystemGlobalizationCultureInfo); + + //--// + +}; + +struct Library_corlib_native_System_Globalization_DateTimeFormat +{ + NANOCLR_NATIVE_DECLARE(FormatDigits___STATIC__STRING__I4__I4); + + //--// + +}; + +struct Library_corlib_native_System_Globalization_DateTimeFormatInfo +{ + static const int FIELD___generalShortTimePattern = 1; + static const int FIELD___generalLongTimePattern = 2; + static const int FIELD___fullDateTimePattern = 3; + + + //--// + +}; + +struct Library_corlib_native_System_Globalization_NumberFormatInfo +{ + static const int FIELD___numberGroupSizes = 1; + static const int FIELD___positiveSign = 2; + static const int FIELD___negativeSign = 3; + static const int FIELD___numberDecimalSeparator = 4; + static const int FIELD___numberGroupSeparator = 5; + static const int FIELD___cultureInfo = 6; + + + //--// + +}; + +struct Library_corlib_native_System_Guid +{ + static const int FIELD_STATIC__Empty = 5; + + static const int FIELD___a = 1; + static const int FIELD___b = 2; + static const int FIELD___c = 3; + static const int FIELD___d = 4; + static const int FIELD___e = 5; + static const int FIELD___f = 6; + static const int FIELD___g = 7; + static const int FIELD___h = 8; + static const int FIELD___i = 9; + static const int FIELD___j = 10; + static const int FIELD___k = 11; + + NANOCLR_NATIVE_DECLARE(GenerateNewGuid___STATIC__SZARRAY_U1); + + //--// + +}; + +struct Library_corlib_native_System_Int16 +{ + static const int FIELD___value = 1; + + + //--// + +}; + +struct Library_corlib_native_System_Int32 +{ + static const int FIELD___value = 1; + + + //--// + +}; + +struct Library_corlib_native_System_Int64 +{ + static const int FIELD___value = 1; + + + //--// + +}; + +struct Library_corlib_native_System_MathInternal +{ + NANOCLR_NATIVE_DECLARE(Abs___STATIC__I4__I4); + NANOCLR_NATIVE_DECLARE(Min___STATIC__I4__I4__I4); + NANOCLR_NATIVE_DECLARE(Max___STATIC__I4__I4__I4); + + //--// + +}; + +struct Library_corlib_native_System_Number +{ + NANOCLR_NATIVE_DECLARE(FormatNative___STATIC__STRING__OBJECT__CHAR__I4); + + //--// + +}; + +struct Library_corlib_native_System_Random +{ + static const int FIELD___random = 1; + + NANOCLR_NATIVE_DECLARE(Next___I4); + NANOCLR_NATIVE_DECLARE(Next___I4__I4); + NANOCLR_NATIVE_DECLARE(NextDouble___R8); + NANOCLR_NATIVE_DECLARE(NextBytes___VOID__SZARRAY_U1); + NANOCLR_NATIVE_DECLARE(_ctor___VOID); + NANOCLR_NATIVE_DECLARE(_ctor___VOID__I4); + + //--// + + static HRESULT GetRandom( CLR_RT_StackFrame& stack, CLR_RT_Random*& rand, bool create = false ); +}; + +struct Library_corlib_native_System_Reflection_Assembly +{ + NANOCLR_NATIVE_DECLARE(get_FullName___STRING); + NANOCLR_NATIVE_DECLARE(GetType___SystemType__STRING); + NANOCLR_NATIVE_DECLARE(GetTypes___SZARRAY_SystemType); + NANOCLR_NATIVE_DECLARE(GetVersion___VOID__BYREF_I4__BYREF_I4__BYREF_I4__BYREF_I4); + NANOCLR_NATIVE_DECLARE(GetManifestResourceNames___SZARRAY_STRING); + NANOCLR_NATIVE_DECLARE(GetExecutingAssembly___STATIC__SystemReflectionAssembly); + NANOCLR_NATIVE_DECLARE(LoadInternal___STATIC__SystemReflectionAssembly__STRING__BOOLEAN__I4__I4__I4__I4); + NANOCLR_NATIVE_DECLARE(Load___STATIC__SystemReflectionAssembly__SZARRAY_U1); + + //--// + +#if (NANOCLR_REFLECTION == TRUE) + static HRESULT GetTypeDescriptor( CLR_RT_HeapBlock& arg, CLR_RT_Assembly_Instance& inst ); +#endif // NANOCLR_REFLECTION +}; + +struct Library_corlib_native_System_Reflection_AssemblyName +{ + static const int FIELD___assembly = 1; + + + //--// + +}; + +struct Library_corlib_native_System_Reflection_MethodBase +{ + NANOCLR_NATIVE_DECLARE(get_Name___STRING); + NANOCLR_NATIVE_DECLARE(get_DeclaringType___SystemType); + NANOCLR_NATIVE_DECLARE(get_IsPublic___BOOLEAN); + NANOCLR_NATIVE_DECLARE(get_IsStatic___BOOLEAN); + NANOCLR_NATIVE_DECLARE(get_IsFinal___BOOLEAN); + NANOCLR_NATIVE_DECLARE(get_IsVirtual___BOOLEAN); + NANOCLR_NATIVE_DECLARE(get_IsAbstract___BOOLEAN); + NANOCLR_NATIVE_DECLARE(Invoke___OBJECT__OBJECT__SZARRAY_OBJECT); + + //--// + +#if (NANOCLR_REFLECTION == TRUE) + static HRESULT GetMethodDescriptor( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock& arg, CLR_RT_MethodDef_Instance& inst ); + static HRESULT CheckFlags( CLR_RT_StackFrame& stack, CLR_UINT32 mask, CLR_UINT32 flag ); +#endif // NANOCLR_REFLECTION +}; + +struct Library_corlib_native_System_Reflection_ConstructorInfo +{ + NANOCLR_NATIVE_DECLARE(GetCustomAttributes___SZARRAY_OBJECT__BOOLEAN); + NANOCLR_NATIVE_DECLARE(Invoke___OBJECT__SZARRAY_OBJECT); + + //--// + +}; + +struct Library_corlib_native_System_Reflection_FieldInfo +{ + NANOCLR_NATIVE_DECLARE(SetValue___VOID__OBJECT__OBJECT); + NANOCLR_NATIVE_DECLARE(GetCustomAttributes___SZARRAY_OBJECT__BOOLEAN); + + //--// + +#if (NANOCLR_REFLECTION == TRUE) + static HRESULT Initialize( CLR_RT_StackFrame& stack, CLR_RT_FieldDef_Instance& instFD, CLR_RT_TypeDef_Instance& instTD, CLR_RT_HeapBlock*& obj ); +#endif // NANOCLR_REFLECTION +}; + +struct Library_corlib_native_System_Reflection_PropertyInfo +{ + NANOCLR_NATIVE_DECLARE(GetValue___OBJECT__OBJECT__SZARRAY_OBJECT); + NANOCLR_NATIVE_DECLARE(SetValue___VOID__OBJECT__OBJECT__SZARRAY_OBJECT); + + //--// + +}; + +struct Library_corlib_native_System_Reflection_RuntimeFieldInfo +{ + NANOCLR_NATIVE_DECLARE(get_Name___STRING); + NANOCLR_NATIVE_DECLARE(get_DeclaringType___SystemType); + NANOCLR_NATIVE_DECLARE(get_FieldType___SystemType); + NANOCLR_NATIVE_DECLARE(GetValue___OBJECT__OBJECT); + + //--// + +#if (NANOCLR_REFLECTION == TRUE) + static bool GetFieldDescriptor( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock& arg, CLR_RT_FieldDef_Instance& inst ); +#endif // NANOCLR_REFLECTION +}; + +struct Library_corlib_native_System_Reflection_RuntimeMethodInfo +{ + NANOCLR_NATIVE_DECLARE(get_ReturnType___SystemType); + NANOCLR_NATIVE_DECLARE(GetCustomAttributes___SZARRAY_OBJECT__BOOLEAN); + + //--// + +}; + +struct Library_corlib_native_System_Runtime_CompilerServices_AccessedThroughPropertyAttribute +{ + static const int FIELD___propertyName = 1; + + + //--// + +}; + +struct Library_corlib_native_System_Runtime_CompilerServices_RuntimeHelpers +{ + NANOCLR_NATIVE_DECLARE(InitializeArray___STATIC__VOID__SystemArray__SystemRuntimeFieldHandle); + NANOCLR_NATIVE_DECLARE(GetObjectValue___STATIC__OBJECT__OBJECT); + NANOCLR_NATIVE_DECLARE(RunClassConstructor___STATIC__VOID__SystemRuntimeTypeHandle); + NANOCLR_NATIVE_DECLARE(get_OffsetToStringData___STATIC__I4); + + //--// + +}; + +struct Library_corlib_native_System_Runtime_Remoting_RemotingServices +{ + NANOCLR_NATIVE_DECLARE(IsTransparentProxy___STATIC__BOOLEAN__OBJECT); + + //--// + +}; + +struct Library_corlib_native_System_Runtime_Versioning_TargetFrameworkAttribute +{ + static const int FIELD___frameworkName = 1; + static const int FIELD___frameworkDisplayName = 2; + + + //--// + +}; + +#if (NANOCLR_REFLECTION == TRUE) + +struct Library_corlib_native_System_Type +{ + NANOCLR_NATIVE_DECLARE(get_DeclaringType___SystemType); + NANOCLR_NATIVE_DECLARE(GetMethod___SystemReflectionMethodInfo__STRING__SystemReflectionBindingFlags); + NANOCLR_NATIVE_DECLARE(IsInstanceOfType___BOOLEAN__OBJECT); + NANOCLR_NATIVE_DECLARE(InvokeMember___OBJECT__STRING__SystemReflectionBindingFlags__SystemReflectionBinder__OBJECT__SZARRAY_OBJECT); + NANOCLR_NATIVE_DECLARE(GetConstructor___SystemReflectionConstructorInfo__SZARRAY_SystemType); + NANOCLR_NATIVE_DECLARE(GetMethod___SystemReflectionMethodInfo__STRING__SZARRAY_SystemType); + NANOCLR_NATIVE_DECLARE(GetMethod___SystemReflectionMethodInfo__STRING); + NANOCLR_NATIVE_DECLARE(get_IsNotPublic___BOOLEAN); + NANOCLR_NATIVE_DECLARE(get_IsPublic___BOOLEAN); + NANOCLR_NATIVE_DECLARE(get_IsClass___BOOLEAN); + NANOCLR_NATIVE_DECLARE(get_IsInterface___BOOLEAN); + NANOCLR_NATIVE_DECLARE(get_IsValueType___BOOLEAN); + NANOCLR_NATIVE_DECLARE(get_IsAbstract___BOOLEAN); + NANOCLR_NATIVE_DECLARE(get_IsEnum___BOOLEAN); + NANOCLR_NATIVE_DECLARE(get_IsSerializable___BOOLEAN); + NANOCLR_NATIVE_DECLARE(get_IsArray___BOOLEAN); + NANOCLR_NATIVE_DECLARE(GetTypeInternal___STATIC__SystemType__STRING__STRING__BOOLEAN__SZARRAY_I4); + NANOCLR_NATIVE_DECLARE(GetTypeFromHandle___STATIC__SystemType__SystemRuntimeTypeHandle); + + //--// + + static const int c_BindingFlags_Default = 0x00000000; // a place holder for no flag specifed + + static const int c_BindingFlags_IgnoreCase = 0x00000001; // Ignore the case of Names while searching + static const int c_BindingFlags_DeclaredOnly = 0x00000002; // Only look at the members declared on the Type + static const int c_BindingFlags_Instance = 0x00000004; // Include Instance members in search + static const int c_BindingFlags_Static = 0x00000008; // Include Static members in search + static const int c_BindingFlags_Public = 0x00000010; // Include Public members in search + static const int c_BindingFlags_NonPublic = 0x00000020; // Include Non-Public members in search + static const int c_BindingFlags_FlattenHierarchy = 0x00000040; // Rollup the statics into the class. + + static const int c_BindingFlags_InvokeMethod = 0x00000100; + static const int c_BindingFlags_CreateInstance = 0x00000200; + static const int c_BindingFlags_GetField = 0x00000400; + static const int c_BindingFlags_SetField = 0x00000800; + static const int c_BindingFlags_GetProperty = 0x00001000; + static const int c_BindingFlags_SetProperty = 0x00002000; + + static const int c_BindingFlags_PutDispProperty = 0x00004000; + static const int c_BindingFlags_PutRefDispProperty = 0x00008000; + + static const int c_BindingFlags_ExactBinding = 0x00010000; // Bind with Exact Type matching, No Change type + static const int c_BindingFlags_SuppressChangeType = 0x00020000; + + static const int c_BindingFlags_OptionalParamBinding = 0x00040000; + static const int c_BindingFlags_IgnoreReturn = 0x01000000; // This is used in COM Interop + + //--// + + static const int c_BindingFlags_DefaultLookup = c_BindingFlags_Instance | c_BindingFlags_Static | c_BindingFlags_Public; + + //--// + + static HRESULT CheckFlags( CLR_RT_StackFrame& stack, CLR_UINT32 mask, CLR_UINT32 flag ); + + static HRESULT GetFields ( CLR_RT_StackFrame& stack, const char* szText, CLR_UINT32 attr , bool fAllMatches ); + static HRESULT GetMethods( CLR_RT_StackFrame& stack, const char* szText, CLR_UINT32 attr, CLR_RT_HeapBlock* pParams, int iParams, bool fAllMatches ); +}; +#endif // NANOCLR_REFLECTION + +#if (NANOCLR_REFLECTION == TRUE) +struct Library_corlib_native_System_RuntimeType +{ + NANOCLR_NATIVE_DECLARE(get_Assembly___SystemReflectionAssembly); + NANOCLR_NATIVE_DECLARE(get_Name___STRING); + NANOCLR_NATIVE_DECLARE(get_FullName___STRING); + NANOCLR_NATIVE_DECLARE(get_BaseType___SystemType); + NANOCLR_NATIVE_DECLARE(GetMethods___SZARRAY_SystemReflectionMethodInfo__SystemReflectionBindingFlags); + NANOCLR_NATIVE_DECLARE(GetField___SystemReflectionFieldInfo__STRING__SystemReflectionBindingFlags); + NANOCLR_NATIVE_DECLARE(GetFields___SZARRAY_SystemReflectionFieldInfo__SystemReflectionBindingFlags); + NANOCLR_NATIVE_DECLARE(GetInterfaces___SZARRAY_SystemType); + NANOCLR_NATIVE_DECLARE(GetElementType___SystemType); + NANOCLR_NATIVE_DECLARE(GetCustomAttributes___SZARRAY_OBJECT__BOOLEAN); + + //--// + + static HRESULT GetTypeDescriptor( CLR_RT_HeapBlock& arg, CLR_RT_TypeDef_Instance& inst, CLR_UINT32* levels ); + static HRESULT GetTypeDescriptor( CLR_RT_HeapBlock& arg, CLR_RT_TypeDef_Instance& inst ); + static HRESULT GetName( CLR_RT_HeapBlock& arg, bool fFullName, CLR_RT_HeapBlock& res ); +}; +#endif // NANOCLR_REFLECTION + +struct Library_corlib_native_System_SByte +{ + static const int FIELD___value = 1; + + + //--// + +}; + +struct Library_corlib_native_System_Single +{ + static const int FIELD___value = 1; + + + //--// + +}; + +struct Library_corlib_native_System_String +{ + static const int FIELD_STATIC__Empty = 6; + + NANOCLR_NATIVE_DECLARE(CompareTo___I4__OBJECT); + NANOCLR_NATIVE_DECLARE(get_Chars___CHAR__I4); + NANOCLR_NATIVE_DECLARE(ToCharArray___SZARRAY_CHAR); + NANOCLR_NATIVE_DECLARE(ToCharArray___SZARRAY_CHAR__I4__I4); + NANOCLR_NATIVE_DECLARE(get_Length___I4); + NANOCLR_NATIVE_DECLARE(Split___SZARRAY_STRING__SZARRAY_CHAR); + NANOCLR_NATIVE_DECLARE(Split___SZARRAY_STRING__SZARRAY_CHAR__I4); + NANOCLR_NATIVE_DECLARE(Substring___STRING__I4); + NANOCLR_NATIVE_DECLARE(Substring___STRING__I4__I4); + NANOCLR_NATIVE_DECLARE(Trim___STRING__SZARRAY_CHAR); + NANOCLR_NATIVE_DECLARE(TrimStart___STRING__SZARRAY_CHAR); + NANOCLR_NATIVE_DECLARE(TrimEnd___STRING__SZARRAY_CHAR); + NANOCLR_NATIVE_DECLARE(_ctor___VOID__SZARRAY_CHAR__I4__I4); + NANOCLR_NATIVE_DECLARE(_ctor___VOID__SZARRAY_CHAR); + NANOCLR_NATIVE_DECLARE(_ctor___VOID__CHAR__I4); + NANOCLR_NATIVE_DECLARE(CompareTo___I4__STRING); + NANOCLR_NATIVE_DECLARE(IndexOf___I4__CHAR); + NANOCLR_NATIVE_DECLARE(IndexOf___I4__CHAR__I4); + NANOCLR_NATIVE_DECLARE(IndexOf___I4__CHAR__I4__I4); + NANOCLR_NATIVE_DECLARE(IndexOfAny___I4__SZARRAY_CHAR); + NANOCLR_NATIVE_DECLARE(IndexOfAny___I4__SZARRAY_CHAR__I4); + NANOCLR_NATIVE_DECLARE(IndexOfAny___I4__SZARRAY_CHAR__I4__I4); + NANOCLR_NATIVE_DECLARE(IndexOf___I4__STRING); + NANOCLR_NATIVE_DECLARE(IndexOf___I4__STRING__I4); + NANOCLR_NATIVE_DECLARE(IndexOf___I4__STRING__I4__I4); + NANOCLR_NATIVE_DECLARE(LastIndexOf___I4__CHAR); + NANOCLR_NATIVE_DECLARE(LastIndexOf___I4__CHAR__I4); + NANOCLR_NATIVE_DECLARE(LastIndexOf___I4__CHAR__I4__I4); + NANOCLR_NATIVE_DECLARE(LastIndexOfAny___I4__SZARRAY_CHAR); + NANOCLR_NATIVE_DECLARE(LastIndexOfAny___I4__SZARRAY_CHAR__I4); + NANOCLR_NATIVE_DECLARE(LastIndexOfAny___I4__SZARRAY_CHAR__I4__I4); + NANOCLR_NATIVE_DECLARE(LastIndexOf___I4__STRING); + NANOCLR_NATIVE_DECLARE(LastIndexOf___I4__STRING__I4); + NANOCLR_NATIVE_DECLARE(LastIndexOf___I4__STRING__I4__I4); + NANOCLR_NATIVE_DECLARE(ToLower___STRING); + NANOCLR_NATIVE_DECLARE(ToUpper___STRING); + NANOCLR_NATIVE_DECLARE(Trim___STRING); + NANOCLR_NATIVE_DECLARE(Equals___STATIC__BOOLEAN__STRING__STRING); + NANOCLR_NATIVE_DECLARE(op_Equality___STATIC__BOOLEAN__STRING__STRING); + NANOCLR_NATIVE_DECLARE(op_Inequality___STATIC__BOOLEAN__STRING__STRING); + NANOCLR_NATIVE_DECLARE(Compare___STATIC__I4__STRING__STRING); + NANOCLR_NATIVE_DECLARE(Concat___STATIC__STRING__STRING__STRING); + NANOCLR_NATIVE_DECLARE(Concat___STATIC__STRING__STRING__STRING__STRING); + NANOCLR_NATIVE_DECLARE(Concat___STATIC__STRING__STRING__STRING__STRING__STRING); + NANOCLR_NATIVE_DECLARE(Concat___STATIC__STRING__SZARRAY_STRING); + + //--// + + static const int c_IndexOf__SingleChar = 0x00000001; + static const int c_IndexOf__MultipleChars = 0x00000002; + static const int c_IndexOf__String = 0x00000004; + static const int c_IndexOf__StartIndex = 0x00000010; + static const int c_IndexOf__Count = 0x00000020; + static const int c_IndexOf__Last = 0x00000040; + static const int c_IndexOf__String_Last = 0x00000044; + + static HRESULT FromCharArray( CLR_RT_StackFrame& stack, int startIndex, int count ); + static HRESULT ToCharArray ( CLR_RT_StackFrame& stack, int startIndex, int count ); + static HRESULT IndexOf ( CLR_RT_StackFrame& stack, int mode ); + static HRESULT ChangeCase ( CLR_RT_StackFrame& stack, bool fToUpper ); + static HRESULT Substring ( CLR_RT_StackFrame& stack, int startIndex, int count ); + + + static HRESULT Trim( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock_Array* arrayTrimChars, bool fStart, bool fEnd ); + + static HRESULT Split( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock& chars, int maxStrings ); + + //--// + + static HRESULT Concat( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock* array, int num ); + + static HRESULT ConvertToCharArray( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock& ref, CLR_RT_HeapBlock_Array*& array, int startIndex, int length ); + static HRESULT ConvertToCharArray( const char* szText , CLR_RT_HeapBlock& ref, CLR_RT_HeapBlock_Array*& array, int startIndex, int length ); +}; + +struct Library_corlib_native_System_Text_StringBuilder +{ + static const int FIELD___maxCapacity = 1; + static const int FIELD___chunkChars = 2; + static const int FIELD___chunkLength = 3; + static const int FIELD___chunkPrevious = 4; + static const int FIELD___chunkOffset = 5; + + + //--// + +}; + +struct Library_corlib_native_System_Text_UTF8Decoder +{ + NANOCLR_NATIVE_DECLARE(Convert___VOID__SZARRAY_U1__I4__I4__SZARRAY_CHAR__I4__I4__BOOLEAN__BYREF_I4__BYREF_I4__BYREF_BOOLEAN); + + //--// + +}; + +struct Library_corlib_native_System_Text_UTF8Encoding +{ + NANOCLR_NATIVE_DECLARE(GetBytes___SZARRAY_U1__STRING); + NANOCLR_NATIVE_DECLARE(GetBytes___I4__STRING__I4__I4__SZARRAY_U1__I4); + NANOCLR_NATIVE_DECLARE(GetChars___SZARRAY_CHAR__SZARRAY_U1); + NANOCLR_NATIVE_DECLARE(GetChars___SZARRAY_CHAR__SZARRAY_U1__I4__I4); + + //--// + + static HRESULT Helper__GetChars(CLR_RT_StackFrame& stack, bool fIndexed); +}; + +struct Library_corlib_native_System_Threading_WaitHandle +{ + NANOCLR_NATIVE_DECLARE(WaitOne___BOOLEAN__I4__BOOLEAN); + NANOCLR_NATIVE_DECLARE(WaitMultiple___STATIC__I4__SZARRAY_SystemThreadingWaitHandle__I4__BOOLEAN__BOOLEAN); + + //--// + + static void Set ( CLR_RT_StackFrame& stack ); + static void Reset( CLR_RT_StackFrame& stack ); + + static HRESULT Wait( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock& blkTimeout, CLR_RT_HeapBlock& blkExitContext, CLR_RT_HeapBlock* objects, int cObjects, bool fWaitAll ); +}; + +struct Library_corlib_native_System_Threading_AutoResetEvent +{ + NANOCLR_NATIVE_DECLARE(_ctor___VOID__BOOLEAN); + NANOCLR_NATIVE_DECLARE(Reset___BOOLEAN); + NANOCLR_NATIVE_DECLARE(Set___BOOLEAN); + + //--// + +}; + +struct Library_corlib_native_System_Threading_Interlocked +{ + NANOCLR_NATIVE_DECLARE(Increment___STATIC__I4__BYREF_I4); + NANOCLR_NATIVE_DECLARE(Decrement___STATIC__I4__BYREF_I4); + NANOCLR_NATIVE_DECLARE(Exchange___STATIC__I4__BYREF_I4__I4); + NANOCLR_NATIVE_DECLARE(CompareExchange___STATIC__I4__BYREF_I4__I4__I4); + + //--// + +}; + +struct Library_corlib_native_System_Threading_ManualResetEvent +{ + NANOCLR_NATIVE_DECLARE(_ctor___VOID__BOOLEAN); + NANOCLR_NATIVE_DECLARE(Reset___BOOLEAN); + NANOCLR_NATIVE_DECLARE(Set___BOOLEAN); + + //--// + +}; + +struct Library_corlib_native_System_Threading_Monitor +{ + NANOCLR_NATIVE_DECLARE(Enter___STATIC__VOID__OBJECT); + NANOCLR_NATIVE_DECLARE(Exit___STATIC__VOID__OBJECT); + + //--// + +}; + +struct Library_corlib_native_System_Threading_Thread +{ + static const int FIELD___delegate = 1; + static const int FIELD___priority = 2; + static const int FIELD___thread = 3; + static const int FIELD___appDomain = 4; + static const int FIELD___id = 5; + + NANOCLR_NATIVE_DECLARE(_ctor___VOID__SystemThreadingThreadStart); + NANOCLR_NATIVE_DECLARE(Start___VOID); + NANOCLR_NATIVE_DECLARE(Abort___VOID); + NANOCLR_NATIVE_DECLARE(Suspend___VOID); + NANOCLR_NATIVE_DECLARE(Resume___VOID); + NANOCLR_NATIVE_DECLARE(get_Priority___SystemThreadingThreadPriority); + NANOCLR_NATIVE_DECLARE(set_Priority___VOID__SystemThreadingThreadPriority); + NANOCLR_NATIVE_DECLARE(get_ManagedThreadId___I4); + NANOCLR_NATIVE_DECLARE(get_IsAlive___BOOLEAN); + NANOCLR_NATIVE_DECLARE(Join___VOID); + NANOCLR_NATIVE_DECLARE(Join___BOOLEAN__I4); + NANOCLR_NATIVE_DECLARE(Join___BOOLEAN__SystemTimeSpan); + NANOCLR_NATIVE_DECLARE(get_ThreadState___SystemThreadingThreadState); + NANOCLR_NATIVE_DECLARE(Sleep___STATIC__VOID__I4); + NANOCLR_NATIVE_DECLARE(get_CurrentThread___STATIC__SystemThreadingThread); +#if (NANOCLR_REFLECTION == TRUE) + NANOCLR_NATIVE_DECLARE(GetDomain___STATIC__SystemAppDomain); +#endif // NANOCLR_REFLECTION + + //--// + + static CLR_RT_ObjectToEvent_Source* GetThreadReference ( CLR_RT_StackFrame& stack ); + static void ResetThreadReference( CLR_RT_StackFrame& stack ); + static HRESULT SetThread ( CLR_RT_StackFrame& stack, CLR_RT_Thread* th ); + static HRESULT GetThread ( CLR_RT_StackFrame& stack, CLR_RT_Thread*& th, bool mustBeStarted, bool noSystemThreads ); + + static HRESULT Join( CLR_RT_StackFrame& stack, const CLR_INT64& timeExpire ); +}; + +struct Library_corlib_native_System_Threading_Timeout +{ + static const int FIELD_STATIC__InfiniteTimeSpan = 7; + + + //--// + +}; + +struct Library_corlib_native_System_Threading_Timer +{ + static const int FIELD___timer = 1; + static const int FIELD___state = 2; + static const int FIELD___callback = 3; + + NANOCLR_NATIVE_DECLARE(Dispose___VOID); + NANOCLR_NATIVE_DECLARE(_ctor___VOID__SystemThreadingTimerCallback__OBJECT__I4__I4); + NANOCLR_NATIVE_DECLARE(_ctor___VOID__SystemThreadingTimerCallback__OBJECT__SystemTimeSpan__SystemTimeSpan); + NANOCLR_NATIVE_DECLARE(Change___BOOLEAN__I4__I4); + NANOCLR_NATIVE_DECLARE(Change___BOOLEAN__SystemTimeSpan__SystemTimeSpan); + + //--// + + static HRESULT SetValues ( CLR_RT_StackFrame& stack, CLR_UINT32 flags ); + static bool CheckDisposed( CLR_RT_StackFrame& stack ); +}; + +struct Library_corlib_native_System_TimeSpan +{ + static const int FIELD_STATIC__Zero = 8; + static const int FIELD_STATIC__MaxValue = 9; + static const int FIELD_STATIC__MinValue = 10; + + static const int FIELD___ticks = 1; + + NANOCLR_NATIVE_DECLARE(Equals___BOOLEAN__OBJECT); + NANOCLR_NATIVE_DECLARE(ToString___STRING); + NANOCLR_NATIVE_DECLARE(_ctor___VOID__I4__I4__I4); + NANOCLR_NATIVE_DECLARE(_ctor___VOID__I4__I4__I4__I4); + NANOCLR_NATIVE_DECLARE(_ctor___VOID__I4__I4__I4__I4__I4); + NANOCLR_NATIVE_DECLARE(CompareTo___I4__OBJECT); + NANOCLR_NATIVE_DECLARE(Compare___STATIC__I4__SystemTimeSpan__SystemTimeSpan); + NANOCLR_NATIVE_DECLARE(Equals___STATIC__BOOLEAN__SystemTimeSpan__SystemTimeSpan); + + //--// + + static CLR_INT64* NewObject ( CLR_RT_StackFrame& stack ); + static CLR_INT64* GetValuePtr( CLR_RT_StackFrame& stack ); + static CLR_INT64* GetValuePtr( CLR_RT_HeapBlock& ref ); + + static void ConstructTimeSpan( CLR_INT64* val, CLR_INT32 days, CLR_INT32 hours, CLR_INT32 minutes, CLR_INT32 seconds, CLR_INT32 ms ); +}; + +struct Library_corlib_native_System_UInt16 +{ + static const int FIELD___value = 1; + + + //--// + +}; + +struct Library_corlib_native_System_UInt32 +{ + static const int FIELD___value = 1; + + + //--// + +}; + +struct Library_corlib_native_System_UInt64 +{ + static const int FIELD___value = 1; + + + //--// + +}; + +struct Library_corlib_native_System_Version +{ + static const int FIELD___Major = 1; + static const int FIELD___Minor = 2; + static const int FIELD___Build = 3; + static const int FIELD___Revision = 4; + + + //--// + +}; + +struct Library_corlib_native_System_WeakReference +{ + NANOCLR_NATIVE_DECLARE(get_IsAlive___BOOLEAN); + NANOCLR_NATIVE_DECLARE(get_Target___OBJECT); + NANOCLR_NATIVE_DECLARE(set_Target___VOID__OBJECT); + NANOCLR_NATIVE_DECLARE(_ctor___VOID__OBJECT); + + //--// + +}; + +struct Library_corlib_native_System_Array__SzArrayEnumerator +{ + static const int FIELD___array = 1; + static const int FIELD___index = 2; + static const int FIELD___endIndex = 3; + static const int FIELD___startIndex = 4; + static const int FIELD___arrayLength = 5; + + + //--// + +}; + +struct Library_corlib_native_System_Collections_Hashtable__ValueCollection +{ + static const int FIELD__ht = 1; + + + //--// + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_mscorlib; + +#endif //_CORLIB_NATIVE_H_ diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_AppDomain.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_AppDomain.cpp new file mode 100644 index 00000000..ea354bd0 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_AppDomain.cpp @@ -0,0 +1,313 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + +#if defined(NANOCLR_APPDOMAINS) + + + +HRESULT Library_corlib_native_System_AppDomain::GetAssemblies___SZARRAY_SystemReflectionAssembly( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_AppDomain* appDomainSav = NULL; + CLR_RT_AppDomain* appDomain; + + NANOCLR_CHECK_HRESULT(GetAppDomain( stack.ThisRef(), appDomain, appDomainSav, true )); + + NANOCLR_CHECK_HRESULT(appDomain->GetAssemblies( stack.PushValueAndClear() )); + + NANOCLR_CLEANUP(); + + g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( appDomainSav ); + + NANOCLR_CLEANUP_END(); +} + +HRESULT Library_corlib_native_System_AppDomain::LoadInternal___SystemReflectionAssembly__STRING__BOOLEAN__I4__I4__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* pArgs = &(stack.Arg1()); + CLR_RT_AppDomain* appDomainSav; + CLR_RT_AppDomain* appDomain; + CLR_RT_Assembly* assembly; + CLR_RT_Assembly_Index idx; + bool fVersion; + CLR_INT16 maj, min, build, rev; + const char* szAssembly; + + NANOCLR_CHECK_HRESULT(GetAppDomain( stack.ThisRef(), appDomain, appDomainSav, true )); + + szAssembly = pArgs[ 0 ].RecoverString(); FAULT_ON_NULL(szAssembly); + fVersion = pArgs[ 1 ].NumericByRef().u8 != 0; + maj = pArgs[ 2 ].NumericByRef().s4; + min = pArgs[ 3 ].NumericByRef().s4; + build = pArgs[ 4 ].NumericByRef().s4; + rev = pArgs[ 5 ].NumericByRef().s4; + + if(fVersion && (maj == -1 || min == -1 || build == -1 || rev == -1)) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + if(fVersion) + { + CLR_RECORD_VERSION ver; + + ver.iMajorVersion = (CLR_UINT16) maj; + ver.iMinorVersion = (CLR_UINT16) min; + ver.iBuildNumber = (CLR_UINT16) build; + ver.iRevisionNumber = (CLR_UINT16) rev; + + assembly = g_CLR_RT_TypeSystem.FindAssembly( szAssembly, &ver, true ); FAULT_ON_NULL_HR(assembly, CLR_E_INVALID_PARAMETER); + } + else + { + assembly = g_CLR_RT_TypeSystem.FindAssembly( szAssembly, NULL, false ); FAULT_ON_NULL_HR(assembly, CLR_E_INVALID_PARAMETER); + } + + NANOCLR_CHECK_HRESULT(appDomain->LoadAssembly( assembly )); + + { + CLR_RT_HeapBlock& top = stack.PushValue(); + CLR_RT_HeapBlock* hbObj; + + idx.Set( assembly->m_idx ); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_Assembly)); + + hbObj = top.Dereference(); + hbObj->SetReflection( idx ); + } + + NANOCLR_CLEANUP(); + + g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( appDomainSav ); + + NANOCLR_CLEANUP_END(); +} + +HRESULT Library_corlib_native_System_AppDomain::CreateDomain___STATIC__SystemAppDomain__STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_AppDomain* appDomain = NULL; + CLR_RT_HeapBlock& pArgs = stack.Arg0(); + CLR_RT_HeapBlock res; res.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc( res ); + const char* szName; + + szName = pArgs.RecoverString(); FAULT_ON_NULL(szName); + + NANOCLR_CHECK_HRESULT(CLR_RT_AppDomain::CreateInstance( szName, appDomain )); + + //load mscorlib + NANOCLR_CHECK_HRESULT(appDomain->LoadAssembly( g_CLR_RT_TypeSystem.m_assemblyMscorlib )); + + //load Runtime.Native + if(g_CLR_RT_TypeSystem.m_assemblyNative != NULL) + { + NANOCLR_CHECK_HRESULT(appDomain->LoadAssembly( g_CLR_RT_TypeSystem.m_assemblyNative )); + } + + NANOCLR_CHECK_HRESULT(appDomain->GetManagedObject( res )); + + //Marshal the new AD to the calling AD. + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.GetCurrentAppDomain()->MarshalObject( res, res, appDomain )); + + stack.PushValueAndAssign( res ); + + NANOCLR_CLEANUP(); + + if(FAILED(hr)) + { + if(appDomain) + { + appDomain->DestroyInstance(); + } + } + + NANOCLR_CLEANUP_END(); +} + +HRESULT Library_corlib_native_System_AppDomain::Unload___STATIC__VOID__SystemAppDomain( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_AppDomain* appDomainSav; + CLR_RT_AppDomain* appDomain; + CLR_RT_HeapBlock hbTimeout; + CLR_INT64* timeout; + bool fRes; + + NANOCLR_CHECK_HRESULT(GetAppDomain( stack.ThisRef(), appDomain, appDomainSav, false )); + + hbTimeout.SetInteger( 5 * 1000 * TIME_CONVERSION__TO_MILLISECONDS); + + if(stack.m_customState == 0) + { + //Attempt to unload the AppDomain only once + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.UnloadAppDomain( appDomain, stack.m_owningThread )); + } + + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks( hbTimeout, timeout )); + + fRes = true; + while(fRes) + { + //Check to make sure this AppDomain is the one that caused the event to fire + if(appDomain->m_state == CLR_RT_AppDomain::AppDomainState_Unloaded) break; + + _ASSERTE(CLR_EE_IS(UnloadingAppDomain)); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_AppDomain, fRes )); + } + + if(!fRes) NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); + + appDomain->DestroyInstance(); + + stack.PopValue(); + + NANOCLR_CLEANUP(); + + g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( appDomainSav ); + + NANOCLR_CLEANUP_END(); +} + +//--// + +HRESULT Library_corlib_native_System_AppDomain::GetAppDomain( CLR_RT_HeapBlock& ref, CLR_RT_AppDomain*& appDomain, CLR_RT_AppDomain*& appDomainSav, bool fCheckForUnloadingAppDomain ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* obj; + CLR_RT_ObjectToEvent_Source* src; + + //Setting up appDomainSav is guaranteed to be initialized correctly by this function + appDomainSav = g_CLR_RT_ExecutionEngine.GetCurrentAppDomain(); + + _ASSERTE(ref.DataType() == DATATYPE_OBJECT); + + obj = ref.Dereference(); FAULT_ON_NULL(obj); + + if(obj->DataType() == DATATYPE_TRANSPARENT_PROXY) + { + appDomain = obj->TransparentProxyAppDomain(); + + if(!appDomain) NANOCLR_SET_AND_LEAVE(CLR_E_APPDOMAIN_EXITED); + + obj = obj->TransparentProxyDereference(); FAULT_ON_NULL(obj); + } + + _ASSERTE(obj->DataType() == DATATYPE_CLASS ); + _ASSERTE(obj->ObjectCls().m_data == g_CLR_RT_WellKnownTypes.m_AppDomain.m_data); + + src = CLR_RT_ObjectToEvent_Source::ExtractInstance( obj[ FIELD___appDomain ] ); FAULT_ON_NULL(src); + appDomain = (CLR_RT_AppDomain*)src->m_eventPtr ; FAULT_ON_NULL(appDomain); + + _ASSERTE(appDomain->DataType() == DATATYPE_APPDOMAIN_HEAD); + + if(fCheckForUnloadingAppDomain) + { + if(!appDomain->IsLoaded()) NANOCLR_SET_AND_LEAVE(CLR_E_APPDOMAIN_EXITED); + } + + (void)g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( appDomain ); + + NANOCLR_NOCLEANUP(); +} + +#else //#if defined(NANOCLR_APPDOMAINS) + +#if (NANOCLR_REFLECTION == TRUE) + +HRESULT Library_corlib_native_System_AppDomain::GetAssemblies___SZARRAY_SystemReflectionAssembly( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + + int count = 0; + CLR_RT_HeapBlock* pArray = NULL; + + for(int pass=0; pass<2; pass++) + { + NANOCLR_FOREACH_ASSEMBLY(g_CLR_RT_TypeSystem) + { + if(pASSM->m_header->flags & CLR_RECORD_ASSEMBLY::c_Flags_Patch) continue; + + if(pass == 0) + { + count++; + } + else + { + CLR_RT_HeapBlock* hbObj; + CLR_RT_Assembly_Index idx; idx.Set( pASSM->m_idx ); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*pArray, g_CLR_RT_WellKnownTypes.m_Assembly)); + hbObj = pArray->Dereference(); + + hbObj->SetReflection( idx ); + + pArray++; + } + } + NANOCLR_FOREACH_ASSEMBLY_END(); + + if(pass == 0) + { + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( top, count, g_CLR_RT_WellKnownTypes.m_Assembly )); + + pArray = (CLR_RT_HeapBlock*)top.DereferenceArray()->GetFirstElement(); + } + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_AppDomain::LoadInternal___SystemReflectionAssembly__STRING__BOOLEAN__I4__I4__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_AppDomain::CreateDomain___STATIC__SystemAppDomain__STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_AppDomain::Unload___STATIC__VOID__SystemAppDomain( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +#endif // NANOCLR_REFLECTION + +#endif //#if defined(NANOCLR_APPDOMAINS) diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Array.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Array.cpp new file mode 100644 index 00000000..03eb5be5 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Array.cpp @@ -0,0 +1,190 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_Array::System_Collections_IList_get_Item___OBJECT__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock& thisRef = stack.ThisRef(); + int index = stack.Arg1().NumericByRef().s4; + + CLR_RT_HeapBlock ref; NANOCLR_CHECK_HRESULT(ref.InitializeArrayReference( thisRef, index )); + + { + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + + NANOCLR_CHECK_HRESULT(top.LoadFromReference ( ref )); + NANOCLR_CHECK_HRESULT(top.PerformBoxingIfNeeded( )); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Array::System_Collections_IList_set_Item___VOID__I4__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock& thisRef = stack.ThisRef(); + int index = stack.Arg1().NumericByRef().s4; + + CLR_RT_HeapBlock ref; NANOCLR_CHECK_HRESULT(ref.InitializeArrayReference( thisRef, index )); + + NANOCLR_SET_AND_LEAVE(stack.Arg2().StoreToReference( ref, 0 )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Array::get_Length___I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_CHECK_HRESULT(CLR_Checks::VerifyArrayReference( stack.Arg0() )); + + stack.SetResult_I4( stack.Arg0().DereferenceArray()->m_numOfElements ); + + NANOCLR_NOCLEANUP(); +} + +#if (NANOCLR_REFLECTION == TRUE) + +HRESULT Library_corlib_native_System_Array::CreateInstance___STATIC__SystemArray__SystemType__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Instance td; + CLR_RT_HeapBlock* hbType = stack.Arg0().Dereference(); + + NANOCLR_CHECK_HRESULT(Library_corlib_native_System_RuntimeType::GetTypeDescriptor( *hbType, td )); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( stack.PushValue(), stack.Arg1().NumericByRefConst().s4, td )); + + NANOCLR_NOCLEANUP(); +} + +#endif // NANOCLR_REFLECTION + +HRESULT Library_corlib_native_System_Array::Copy___STATIC__VOID__SystemArray__I4__SystemArray__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(Copy( stack, stack.Arg0(), stack.Arg1().NumericByRef().s4, stack.Arg2(), stack.Arg3().NumericByRef().s4, stack.Arg4().NumericByRef().s4 )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Array::Clear___STATIC__VOID__SystemArray__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(Clear( stack, stack.Arg0(), stack.Arg1().NumericByRef().s4, stack.Arg2().NumericByRef().s4 )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Array::TrySzIndexOf___STATIC__BOOLEAN__SystemArray__I4__I4__OBJECT__BYREF_I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_INT32 start = stack.Arg1().NumericByRefConst().s4; + CLR_INT32 count = stack.Arg2().NumericByRefConst().s4; + CLR_INT32 stop = start + count; + + NANOCLR_SET_AND_LEAVE(TrySzIndexOf( stack, stack.Arg0(), stack.Arg3(), start, stop, true, stack.Arg4() )); + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT Library_corlib_native_System_Array::Clear( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock& arg, int index, int length ) +{ + (void)stack; + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* array; + int numElem; + + NANOCLR_CHECK_HRESULT(CLR_Checks::VerifyArrayReference( arg )); + + array = arg.DereferenceArray(); + numElem = array->m_numOfElements; + + if(length == -1) length = numElem; + + if(length < 0 || + index < 0 || + length + index > numElem ) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + } + + NANOCLR_SET_AND_LEAVE(array->ClearElements( index, length )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Array::Copy( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock& argSrc, int indexSrc, CLR_RT_HeapBlock& argDst, int indexDst, int length ) +{ + (void)stack; + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(length) + { + NANOCLR_CHECK_HRESULT(CLR_Checks::VerifyArrayReference( argSrc )); + NANOCLR_CHECK_HRESULT(CLR_Checks::VerifyArrayReference( argDst )); + + NANOCLR_SET_AND_LEAVE(CLR_RT_HeapBlock_Array::Copy( argSrc.DereferenceArray(), indexSrc, argDst.DereferenceArray(), indexDst, length )); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Array::TrySzIndexOf( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock& argSrc, CLR_RT_HeapBlock& match, int start, int stop, bool fForward, CLR_RT_HeapBlock& retValue ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + int index; + bool fRet; + CLR_RT_HeapBlock_Array* array = argSrc.DereferenceArray(); + + NANOCLR_CHECK_HRESULT(CLR_Checks::VerifyArrayReference( argSrc )); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::IndexOf( array, match, start, stop, fForward, index )); + + _ASSERTE(retValue.DataType() == DATATYPE_BYREF); + + retValue.Dereference()->SetInteger( index ); + + fRet = (index >= 0); + + if(array->m_typeOfElement <= DATATYPE_LAST_PRIMITIVE) + { + //Primitives do not override Equals, so this check is good enough. + //If match is not found, index == -1, so the managed Array.IndexOf will + //skip the more expensive Object.Equals call. + + _ASSERTE(FIMPLIES(!fRet, index == -1)); + fRet = true; + } + + stack.SetResult_Boolean( fRet ); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Attribute.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Attribute.cpp new file mode 100644 index 00000000..488a22e7 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Attribute.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + +// no code generated for this class diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_BitConverter.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_BitConverter.cpp new file mode 100644 index 00000000..d257eed2 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_BitConverter.cpp @@ -0,0 +1,600 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + +char DigitalToHex(unsigned char x) +{ + return x < 10 ? x + '0' : x - 10 + 'A'; +} + +char* ByteArrayToHex(unsigned char* pInput, int index, int length) +{ + char* pOutput = (char*) malloc(length * 3); + char* p = pOutput; + + pInput += index; + for(int i = 0; i < length; i++, pInput++) + { + *p++ = DigitalToHex(*pInput / 16); + *p++ = DigitalToHex(*pInput % 16); + *p++ = '-'; + } + *(--p) = 0; + + return pOutput; +} + + +HRESULT Library_corlib_native_System_BitConverter::get_IsLittleEndian___STATIC__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + unsigned long x = 0x12345678; + unsigned char* p = reinterpret_cast(&x); + stack.SetResult_Boolean(*p == 0x78); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_BitConverter::DoubleToInt64Bits___STATIC__I8__R8( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + double input = stack.Arg0().NumericByRefConst().r8; +#else + CLR_INT64 input = stack.Arg0().NumericByRefConst().r8; +#endif + __int64* p = reinterpret_cast<__int64*>(&input); + stack.SetResult_I8(*p); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + bool input = stack.Arg0().NumericByRefConst().u1 != 0; + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance(stack.PushValueAndClear(), 1, g_CLR_RT_WellKnownTypes.m_UInt8)); + { + unsigned char* p = stack.TopValue().DereferenceArray()->GetFirstElement(); + *reinterpret_cast(p) = input; + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__CHAR( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + wchar_t input = stack.Arg0().NumericByRefConst().u2; + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance(stack.PushValueAndClear(), 2, g_CLR_RT_WellKnownTypes.m_UInt8)); + { + unsigned char* p = stack.TopValue().DereferenceArray()->GetFirstElement(); + *reinterpret_cast(p) = input; + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__R8( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + double input = stack.Arg0().NumericByRefConst().r8; +#else + CLR_INT64 input = stack.Arg0().NumericByRefConst().r8; +#endif + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance(stack.PushValueAndClear(), 8, g_CLR_RT_WellKnownTypes.m_UInt8)); + { + unsigned char* p = stack.TopValue().DereferenceArray()->GetFirstElement(); +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + *reinterpret_cast(p) = input; +#else + *reinterpret_cast(p) = input; +#endif + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__R4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + float input = stack.Arg0().NumericByRefConst().r4; +#else + CLR_INT32 input = stack.Arg0().NumericByRefConst().r4; +#endif + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance(stack.PushValueAndClear(), 4, g_CLR_RT_WellKnownTypes.m_UInt8)); + { + unsigned char* p = stack.TopValue().DereferenceArray()->GetFirstElement(); +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + *reinterpret_cast(p) = input; +#else + *reinterpret_cast(p) = input; +#endif + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + int input = stack.Arg0().NumericByRefConst().s4; + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance(stack.PushValueAndClear(), 4, g_CLR_RT_WellKnownTypes.m_UInt8)); + { + unsigned char* p = stack.TopValue().DereferenceArray()->GetFirstElement(); + *reinterpret_cast(p) = input; + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__I8( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + __int64 input = stack.Arg0().NumericByRefConst().s8; + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance(stack.PushValueAndClear(), 8, g_CLR_RT_WellKnownTypes.m_UInt8)); + { + unsigned char* p = stack.TopValue().DereferenceArray()->GetFirstElement(); + *reinterpret_cast<__int64*>(p) = input; + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__I2( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + short input = stack.Arg0().NumericByRefConst().s2; + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance(stack.PushValueAndClear(), 2, g_CLR_RT_WellKnownTypes.m_UInt8)); + { + unsigned char* p = stack.TopValue().DereferenceArray()->GetFirstElement(); + *reinterpret_cast(p) = input; + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__U4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + unsigned int input = stack.Arg0().NumericByRefConst().u4; + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance(stack.PushValueAndClear(), 4, g_CLR_RT_WellKnownTypes.m_UInt8)); + { + unsigned char* p = stack.TopValue().DereferenceArray()->GetFirstElement(); + *reinterpret_cast(p) = input; + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__U8( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + unsigned __int64 input = stack.Arg0().NumericByRefConst().u8; + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance(stack.PushValueAndClear(), 8, g_CLR_RT_WellKnownTypes.m_UInt8)); + { + unsigned char* p = stack.TopValue().DereferenceArray()->GetFirstElement(); + *reinterpret_cast(p) = input; + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_BitConverter::GetBytes___STATIC__SZARRAY_U1__U2( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + unsigned short input = stack.Arg0().NumericByRefConst().u2; + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance(stack.PushValueAndClear(), 2, g_CLR_RT_WellKnownTypes.m_UInt8)); + { + unsigned char* p = stack.TopValue().DereferenceArray()->GetFirstElement(); + *reinterpret_cast(p) = input; + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_BitConverter::Int64BitsToDouble___STATIC__R8__I8( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + __int64 input = stack.Arg0().NumericByRefConst().s8; +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + double* p = reinterpret_cast(&input); +#else + CLR_INT64* p = reinterpret_cast(&input); +#endif + stack.SetResult_R8(*p); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_BitConverter::ToBoolean___STATIC__BOOLEAN__SZARRAY_U1__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + unsigned char *p = NULL; + unsigned char b=0; + int index = 0; + bool res = false; + + CLR_RT_HeapBlock_Array* pArray = stack.Arg0().DereferenceArray(); + FAULT_ON_NULL_ARG(pArray); + + index = stack.Arg1().NumericByRefConst().s4; + if (index < 0 || (unsigned int)index >= pArray->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + + p = pArray->GetFirstElement(); + b = *(p + index); + res = (b != 0); // assume any value not zero is true. Zero is false. + stack.SetResult_Boolean(res); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_BitConverter::ToChar___STATIC__CHAR__SZARRAY_U1__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + unsigned char *p = NULL; + int index = 0; + wchar_t value=0; + unsigned char *pValue = (unsigned char*)(&value); + + CLR_RT_HeapBlock_Array* pArray = stack.Arg0().DereferenceArray(); + FAULT_ON_NULL_ARG(pArray); + + index = stack.Arg1().NumericByRefConst().s4; + if (index < 0 || (unsigned int)index >= pArray->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + if ((unsigned int)index + 2 > pArray->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + p = pArray->GetFirstElement(); + for (int i=0; i<2; ++i) + { + pValue[i] = p[index+i]; + } + + stack.SetResult(value, DATATYPE_CHAR); + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_BitConverter::ToDouble___STATIC__R8__SZARRAY_U1__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + unsigned char *p = NULL; + int index = 0; + + double value=0; + unsigned char *pValue = (unsigned char*)(&value); + + CLR_RT_HeapBlock_Array* pArray = stack.Arg0().DereferenceArray(); + FAULT_ON_NULL_ARG(pArray); + + index = stack.Arg1().NumericByRefConst().s4; + if (index < 0 || (unsigned int)index >= pArray->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + if ((unsigned int)index + 8 > pArray->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + // fetch unsigned char aligned values, and store in object that is correctly aligned for this system. + p = pArray->GetFirstElement(); + for (int i=0; i<8; ++i) + { + pValue[i] = p[index+i]; + } + stack.SetResult_R8(value); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_BitConverter::ToSingle___STATIC__R4__SZARRAY_U1__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + unsigned char *p = NULL; + int index = 0; + float value=0; + unsigned char *pValue = (unsigned char*)(&value); + + CLR_RT_HeapBlock_Array* pArray = stack.Arg0().DereferenceArray(); + FAULT_ON_NULL_ARG(pArray); + + index = stack.Arg1().NumericByRefConst().s4; + if (index < 0 || (unsigned int)index >= pArray->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + if ((unsigned int)index + 4 > pArray->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + // fetch unsigned char aligned values, and store in object that is correctly aligned for this system. + p = pArray->GetFirstElement(); + + for (int i=0; i<4; ++i) + { + pValue[i] = p[index+i]; + } + stack.SetResult_R4(value); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_BitConverter::ToInt16___STATIC__I2__SZARRAY_U1__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + unsigned char *p = NULL; + int index = 0; + signed short value=0; + unsigned char *pValue = (unsigned char*)(&value); + + CLR_RT_HeapBlock_Array* pArray = stack.Arg0().DereferenceArray(); + FAULT_ON_NULL_ARG(pArray); + + index = stack.Arg1().NumericByRefConst().s4; + if (index < 0 || (unsigned int)index >= pArray->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + if ((unsigned int)index + 2 > pArray->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + p = pArray->GetFirstElement(); + // big vs little endian? + for (int i=0; i<2; ++i) + { + pValue[i] = p[index+i]; + } + stack.SetResult_I4(value); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_BitConverter::ToInt32___STATIC__I4__SZARRAY_U1__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + unsigned char *p = NULL; + int index = 0; + + signed int value=0; + unsigned char *pValue = (unsigned char*)(&value); + + CLR_RT_HeapBlock_Array* pArray = stack.Arg0().DereferenceArray(); + FAULT_ON_NULL_ARG(pArray); + + index = stack.Arg1().NumericByRefConst().s4; + if (index < 0 || (unsigned int)index >= pArray->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + if ((unsigned int)index + 4 > pArray->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + p = pArray->GetFirstElement(); + // big vs little endian? + for (int i=0; i<4; ++i) + { + pValue[i] = p[index+i]; + } + stack.SetResult_I4(value); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_BitConverter::ToInt64___STATIC__I8__SZARRAY_U1__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + unsigned char *p = NULL; + int index = 0; + + CLR_INT64 value=0; + unsigned char *pValue = (unsigned char*)(&value); + + CLR_RT_HeapBlock_Array* pArray = stack.Arg0().DereferenceArray(); + FAULT_ON_NULL_ARG(pArray); + + index = stack.Arg1().NumericByRefConst().s4; + if (index < 0 || (unsigned int)index >= pArray->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + if ((unsigned int)index + 8 > pArray->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + p = pArray->GetFirstElement(); + + for (int i=0; i<8; ++i) + { + pValue[i] = p[index+i]; + } + stack.SetResult_I8(value) ; + + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_BitConverter::ToUInt16___STATIC__U2__SZARRAY_U1__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + unsigned char *p = NULL; + int index = 0; + CLR_UINT16 value=0; + unsigned char *pValue = (unsigned char*)(&value); + + CLR_RT_HeapBlock_Array* pArray = stack.Arg0().DereferenceArray(); + FAULT_ON_NULL_ARG(pArray); + + index = stack.Arg1().NumericByRefConst().s4; + if (index < 0 || (unsigned int)index >= pArray->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + if ((unsigned int)index + 2 > pArray->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + p = pArray->GetFirstElement(); + for (int i=0; i<2; ++i) + { + pValue[i] = p[index+i]; + } + stack.SetResult_I4(value); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_BitConverter::ToUInt32___STATIC__U4__SZARRAY_U1__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + unsigned char *p = NULL; + int index = 0; + CLR_UINT32 value=0; + unsigned char *pValue = (unsigned char*)(&value); + + CLR_RT_HeapBlock_Array* pArray = stack.Arg0().DereferenceArray(); + FAULT_ON_NULL_ARG(pArray); + + index = stack.Arg1().NumericByRefConst().s4; + if (index < 0 || (unsigned int)index >= pArray->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + if ((unsigned int)index + 4 > pArray->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + p = pArray->GetFirstElement(); + for (int i=0; i<4; ++i) + { + pValue[i] = p[index+i]; + } + stack.SetResult_U4(value) ; + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_BitConverter::ToUInt64___STATIC__U8__SZARRAY_U1__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + unsigned char *p = NULL; + int index = 0; + CLR_UINT64 value=0; + unsigned char *pValue = (unsigned char*)(&value); + + CLR_RT_HeapBlock_Array* pArray = stack.Arg0().DereferenceArray(); + FAULT_ON_NULL_ARG(pArray); + + index = stack.Arg1().NumericByRefConst().s4; + if (index < 0 || (unsigned int)index >= pArray->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + if ((unsigned int)index + 8 > pArray->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + p = pArray->GetFirstElement(); + + for (int i=0; i<8; ++i) + { + pValue[i] = p[index+i]; + } + stack.SetResult_U8(value) ; + + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_BitConverter::ToString___STATIC__STRING__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* pArray = stack.Arg0().DereferenceArray(); + FAULT_ON_NULL_ARG(pArray); + + if (pArray->m_numOfElements == 0) + { + NANOCLR_CHECK_HRESULT(stack.SetResult_String("")); + } + else + { + unsigned char* p = pArray->GetFirstElement(); + char* pOutput = ByteArrayToHex(p, 0, pArray->m_numOfElements); + NANOCLR_CHECK_HRESULT(stack.SetResult_String(pOutput)); + free(pOutput); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_BitConverter::ToString___STATIC__STRING__SZARRAY_U1__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + int index = 0; + + CLR_RT_HeapBlock_Array* pArray = stack.Arg0().DereferenceArray(); + FAULT_ON_NULL_ARG(pArray); + + index = stack.Arg1().NumericByRefConst().s4; + if (pArray->m_numOfElements == 0 && index == 0) + { + NANOCLR_CHECK_HRESULT(stack.SetResult_String("")); + } + else + { + if (index < 0 || (unsigned int)index >= pArray->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + + unsigned char* p = pArray->GetFirstElement(); + char* pOutput = ByteArrayToHex(p, index, pArray->m_numOfElements - index); + NANOCLR_CHECK_HRESULT(stack.SetResult_String(pOutput)); + free(pOutput); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_BitConverter::ToString___STATIC__STRING__SZARRAY_U1__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + int index = 0; + int length = 0; + + CLR_RT_HeapBlock_Array* pArray = stack.Arg0().DereferenceArray(); + FAULT_ON_NULL_ARG(pArray); + + index = stack.Arg1().NumericByRefConst().s4; + length = stack.Arg2().NumericByRefConst().s4; + if (pArray->m_numOfElements == 0 && index == 0 && length == 0) + { + NANOCLR_CHECK_HRESULT(stack.SetResult_String("")); + } + else + { + if (index < 0 || length < 0 || (unsigned int)index >= pArray->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + if ((unsigned int)index + length > pArray->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + unsigned char* p = pArray->GetFirstElement(); + char* pOutput = ByteArrayToHex(p, index, length); + NANOCLR_CHECK_HRESULT(stack.SetResult_String(pOutput)); + free(pOutput); + } + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Collections_ArrayList.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Collections_ArrayList.cpp new file mode 100644 index 00000000..440a584e --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Collections_ArrayList.cpp @@ -0,0 +1,97 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_Collections_ArrayList::get_Item___OBJECT__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_ArrayList* pThis = (CLR_RT_HeapBlock_ArrayList*)stack.This(); FAULT_ON_NULL(pThis); + CLR_RT_HeapBlock* value; + + NANOCLR_CHECK_HRESULT(pThis->GetItem( stack.Arg1().NumericByRef().s4, value )); + + stack.SetResult_Object( value ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Collections_ArrayList::set_Item___VOID__I4__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_ArrayList* pThis = (CLR_RT_HeapBlock_ArrayList*)stack.This(); FAULT_ON_NULL(pThis); + + NANOCLR_SET_AND_LEAVE(pThis->SetItem( stack.Arg1().NumericByRef().s4, stack.Arg2().Dereference() )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Collections_ArrayList::Add___I4__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_ArrayList* pThis = (CLR_RT_HeapBlock_ArrayList*)stack.This(); FAULT_ON_NULL(pThis); + CLR_INT32 index; + + NANOCLR_CHECK_HRESULT(pThis->Add( stack.Arg1().Dereference(), index )); + + stack.SetResult_I4( index ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Collections_ArrayList::Clear___VOID( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_ArrayList* pThis = (CLR_RT_HeapBlock_ArrayList*)stack.This(); FAULT_ON_NULL(pThis); + + NANOCLR_SET_AND_LEAVE(pThis->Clear()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Collections_ArrayList::Insert___VOID__I4__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_ArrayList* pThis = (CLR_RT_HeapBlock_ArrayList*)stack.This(); FAULT_ON_NULL(pThis); + + NANOCLR_SET_AND_LEAVE(pThis->Insert( stack.Arg1().NumericByRef().s4, stack.Arg2().Dereference() )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Collections_ArrayList::RemoveAt___VOID__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_ArrayList* pThis = (CLR_RT_HeapBlock_ArrayList*)stack.This(); FAULT_ON_NULL(pThis); + + NANOCLR_SET_AND_LEAVE(pThis->RemoveAt( stack.Arg1().NumericByRef().s4 )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Collections_ArrayList::SetCapacity___VOID__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_ArrayList* pThis = (CLR_RT_HeapBlock_ArrayList*)stack.This(); FAULT_ON_NULL(pThis); + + NANOCLR_SET_AND_LEAVE(pThis->SetCapacity( stack.Arg1().NumericByRef().s4 )); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Console.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Console.cpp new file mode 100644 index 00000000..ff30e02d --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Console.cpp @@ -0,0 +1,26 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_Console::OutNative___STATIC__VOID__STRING__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + const char * szText0 = stack.Arg0().RecoverString(); + bool addLineFeed = (bool)stack.Arg1().NumericByRef().u1; + + if(!szText0) szText0 = ""; + + CLR_Debug::Emit( szText0, -1 ); + + if(addLineFeed) + { + CLR_Debug::Emit( "\r\n" , -1 ); + } + + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Convert.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Convert.cpp new file mode 100644 index 00000000..ae34fa14 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Convert.cpp @@ -0,0 +1,593 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "corlib_native.h" +#include +#include + +HRESULT Library_corlib_native_System_Convert::NativeToInt64___STATIC__I8__STRING__BOOLEAN__I8__I8__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + int64_t result = 0; + + char* str = (char*)stack.Arg0().RecoverString(); + signed int radix = stack.Arg4().NumericByRef().s4; + +#if (SUPPORT_ANY_BASE_CONVERSION == TRUE) + // suport for conversion from any base + char* endptr = NULL; + + bool isUInt64 = false; + + bool isSigned = (bool)stack.Arg1().NumericByRef().u1; + long long minValue = stack.Arg2().NumericByRef().s8; + long long maxValue = stack.Arg3().NumericByRef().s8; + + // UInt64? => use also strtoull the result will be casted to Int64 + if (minValue == 0 && maxValue == 0) { + isUInt64 = true; + isSigned = false; + + //allow spaces before digits + while (*str == ' ') { + str++; + } + + //UInt64 can't begin with minus + if (*str == '-' ) { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + } + } + + // convert via strtoll / strtoull + result = isSigned ? strtoll(str, &endptr, radix) : (long long) strtoull(str, &endptr, radix); + + // TODO: + // If the value in input string is out of the range of representable values + // by a long long int / unsigned long int, the function returns + // LLONG_MAX or LLONG_MIN for signed conversion + // and ULONG_MAX for unsigned conversion + // It is necessary to add a check + + // if no valid conversion endptr is equal str + if (str == endptr) { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // allow spaces after digits + while (*endptr == ' ') { + endptr++; + } + + // should reach end of string no aditional chars + if (*endptr != 0) { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // the signed values for SByte, Int16 and Int32 are always positive for base 2, 8 or 16 conversions + // because the 64-bit function strtoll is used; need the post process the value + // if the result is greater max and smaller (max + 1) * 2 this value should be subtracted + if (radix == 2 || radix == 8 || radix == 16) { + if (isSigned && result > maxValue && result < (maxValue + 1) * 2) result -= (maxValue + 1) * 2; + } + + if (!isUInt64 && !isSigned && (uint64_t)result > (uint64_t)maxValue) { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + } else if (!isUInt64 && (result > maxValue || result < minValue)) { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + } else { + stack.SetResult_I8(result); + } + } + NANOCLR_NOCLEANUP(); +#else + // support for conversion from base 10 and 16 (partial) + + if(radix == 10) + { + // conversion from base 10 + + // check for minus sign + if(*str == '-') + { + // call GetIntegerPart() in 'guess' mode by throwing a crazy number for the length + result = GetIntegerPart((str + 1), 99); + + // is negative + result *= -1; + } + // check for plus sign + else if(*str == '+') + { + // call GetIntegerPart() in 'guess' mode by throwing a crazy number for the length + result = GetIntegerPart((str + 1), 99); + } + else + { + // call GetIntegerPart() in 'guess' mode by throwing a crazy number for the length + result = GetIntegerPart(str, 99); + } + + } + else if(radix == 16) + { + // conversion from base 16 + result = GetIntegerFromHexString(str); + } + else + { + // all other bases are not supported + return stack.NotImplementedStub(); + } + + stack.SetResult_I8(result); + } + NANOCLR_NOCLEANUP_NOLABEL(); +#endif // defined(SUPPORT_ANY_BASE_CONVERSION) + +} + +HRESULT Library_corlib_native_System_Convert::NativeToDouble___STATIC__R8__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + char* str = (char*)stack.Arg0().RecoverString(); + + #if (SUPPORT_ANY_BASE_CONVERSION == TRUE) + // suport for conversion from any base + + stack.SetResult_R8 (strtod(str, nullptr)); + } + NANOCLR_NOCLEANUP_NOLABEL(); + + #else + // support for conversion from base 10 and 16 (partial) + // in this particular function the base isn't relevant + + int length = 0; + bool hasMinusSign = false; + bool hasPlusSign = false; + int decimalPoint = -1; + int exponentialSign = -1; + bool hasMinusExponentialSign = false; + bool hasPlusExponentialSign = false; + double returnValue = 0.0; + + // first pass, get count of decimal places, integer part and check for valid chars + char* temp = str; + while (*temp != '\0') + { + switch (*temp) + { + case '-': + if (exponentialSign == -1) + { + if (length == 0) + { + hasMinusSign = true; + } + else + { + // found a minus signal NOT at the start of the string + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + } + else + { + if (length == exponentialSign + 1) + { + hasMinusExponentialSign = true; + } + else + { + // found a minus signal NOT at the start of the exponent + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + } + break; + + case '+': + if (exponentialSign == -1) + { + if (length == 0) + { + hasPlusSign = true; + } + else + { + // found a plus signal NOT at the start of the string + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + } + else + { + if (length == exponentialSign + 1) + { + hasPlusExponentialSign = true; + } + else + { + // found a plus signal NOT at the start of the exponent + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + } + break; + + case '.': + if (decimalPoint == -1) + { + decimalPoint = length; + } + else + { + // already found a decimal point, can't have another + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + break; + + case 'e': + case 'E': + if (exponentialSign == -1) + { + exponentialSign = length; + } + else + { + // already found a exponential sign, can't have another + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + break; + + default: + if (*temp < '0' && *temp > '9') + { + // there is an invalid char in the string + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + } + length++; + temp++; + } + + // now parse the string according to it's format + int endOrExponentialPart = exponentialSign == -1 ? length : exponentialSign; + if (decimalPoint == -1) + { + // string doesn't have fractional part, treat as integer + returnValue = GetIntegerPart(str, endOrExponentialPart); + } + else if (decimalPoint == 0) + { + // string starts with the decimal point, only has fractional part + returnValue = GetDoubleFractionalPart((str+decimalPoint+1), (endOrExponentialPart-decimalPoint-1)); + } + else if (hasMinusSign || hasPlusSign) + { + // string starts with sign and... + + if(decimalPoint == 1) + { + // ... is followed by a decimal point, only has fractional part + returnValue = GetDoubleFractionalPart((str+decimalPoint+1), (endOrExponentialPart-decimalPoint-1)); + } + else + { + // ... has integer and fractional parts + returnValue = GetIntegerPart(str+1, decimalPoint-1); + returnValue = (returnValue + GetDoubleFractionalPart((str+decimalPoint+1), (endOrExponentialPart-decimalPoint-1))); + } + + if (hasMinusSign) + { + returnValue *= -1; + } + } + else + { + // string has integer and fractional parts + returnValue = GetIntegerPart(str, decimalPoint); + returnValue = returnValue + GetDoubleFractionalPart((str+decimalPoint+1), (endOrExponentialPart-decimalPoint-1)); + } + + // exponential part found? + if (exponentialSign != -1) + { + // advance by one if a sign (+ or -) is after the exponential sign + if (hasMinusExponentialSign || hasPlusExponentialSign) exponentialSign++; + // get the exponential part + int exponent = GetIntegerPart((str+exponentialSign+1), (length-exponentialSign-1)); + // each time multiply or divide by 10 + for (int i = 0; i < exponent; i++) + { + if (hasMinusExponentialSign) + { + returnValue /= 10; + } + else + { + returnValue *= 10; + } + } + } + + stack.SetResult_R8(returnValue); + } + NANOCLR_NOCLEANUP(); + + #endif // defined(SUPPORT_ANY_BASE_CONVERSION) + +} + +HRESULT Library_corlib_native_System_Convert::ToBase64String___STATIC__STRING__SZARRAY_U1__I4__I4__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + size_t outputLength; + char* outArray = NULL; + char* outArrayWitLineBreak = NULL; + uint8_t* inArrayPointer = NULL; + uint8_t lineBreakCount; + uint16_t offsetIndex = 0; + uint8_t count = 0; + uint16_t result; + + CLR_RT_HeapBlock_Array* inArray = stack.Arg0().DereferenceArray(); + size_t offset = (size_t)stack.Arg1().NumericByRef().s4; + size_t length = (size_t)stack.Arg2().NumericByRef().s4; + bool insertLineBreaks = (bool)stack.Arg3().NumericByRefConst().u1; + + if(inArray == NULL) NANOCLR_SET_AND_LEAVE(CLR_E_ARGUMENT_NULL); + + inArrayPointer = (uint8_t*)inArray->GetFirstElement(); + inArrayPointer += (offset * sizeof(uint8_t)); + + // compute base64 string length + outputLength = 4 * ((length + 2) / 3); + + // need malloc with base64 string length plus string terminator (+1) + outArray = (char*)platform_malloc(outputLength + 1); + + // check if have allocation + if (outArray == NULL) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + + // perform the operation + // need to tweak the parameter with the output length because it includes room for the terminator + result = mbedtls_base64_encode( + (unsigned char*)outArray, + (outputLength + 1), + &outputLength, + inArrayPointer, + length ); + + if(result != 0) + { + // internal error occurred + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + + if(insertLineBreaks) + { + // get line break count (line break every 76 chars) + lineBreakCount = outputLength / 76; + + // need malloc with base64 string length plus line breaks (line break is 2 char long: CR + LF) plus final line break + outArrayWitLineBreak = (char*)platform_malloc(outputLength + (lineBreakCount * 2) + 2); + + for(int i = 0; i <= lineBreakCount; i++) + { + // how many chars to copy + if(outputLength > 76) + { + // first/next 76 chars + count = 76; + } + else + { + // last outputLength chars + count = outputLength; + } + + // copy first/next count chars + // because we are using same offset for both arrays, we need to discount line break for tmp array + memcpy(outArrayWitLineBreak + offsetIndex, outArray + (offsetIndex - (i * 2)), count); + + // remove copied chars from original output length if more than 76 chars still to be copied + if(outputLength >= 76) + { + // more chars + + // adjust output length + outputLength -= 76; + + // add line break + outArrayWitLineBreak[count + offsetIndex] = '\r'; + outArrayWitLineBreak[count + offsetIndex + 1] = '\n'; + + // move offset for next copy (including line break +2) + offsetIndex += count + 2; + } + else + { + // move offset for last position + offsetIndex += count; + // reached end of array, add terminator + outArrayWitLineBreak[offsetIndex] = 0; + } + } + // set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + NANOCLR_CHECK_HRESULT(stack.SetResult_String(outArrayWitLineBreak)); + } + else + { + // set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + NANOCLR_CHECK_HRESULT(stack.SetResult_String(outArray)); + } + + // need to free memory from arrays + platform_free((void*)outArray); + + if(outArrayWitLineBreak != NULL) + { + platform_free((void*)outArrayWitLineBreak); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Convert::FromBase64CharArray___STATIC__SZARRAY_U1__SZARRAY_CHAR__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + size_t outputLength; + char* outArray = NULL; + uint16_t* inArrayPointerTmp = NULL; + uint8_t* inArrayPointer = NULL; + uint8_t charValue; + CLR_UINT8* returnArray; + int16_t i = 0; + uint16_t result; + + CLR_RT_HeapBlock_Array* inArray = stack.Arg0().DereferenceArray(); + size_t length = (size_t)stack.Arg1().NumericByRef().s4; + + if(inArray == NULL) NANOCLR_SET_AND_LEAVE(CLR_E_ARGUMENT_NULL); + + outputLength = length / 4 * 3; + + // transform the 16 bits inArray to a 8 bits array so mbed knows how to convert it + inArrayPointerTmp = (uint16_t*)inArray->GetFirstElementUInt16(); + inArrayPointer = (uint8_t*)inArray->GetFirstElement(); + for(i = 0; i < (int16_t)length; i++) + { + *inArrayPointer = *inArrayPointerTmp; + inArrayPointer++; + inArrayPointerTmp++; + } + + // pointer is pointing to the end + // point to last char in array and get it + inArrayPointer--; + charValue = *inArrayPointer; + // adjust output length + if (charValue == '=') + { + outputLength--; + } + + // point to before last char and get it + inArrayPointer--; + charValue = *inArrayPointer; + // adjust output length + if (charValue == '=') + { + outputLength--; + } + + // reset pointer position (-2 because above we already went back two positions) + inArrayPointer -= length - 2; + + outArray = (char*)platform_malloc(outputLength + 1); + // check malloc success + if (outArray == NULL) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + + // perform the operation + // need to tweak the parameter with the output length because it includes room for the terminator + result = mbedtls_base64_decode( + (unsigned char*)outArray, + (outputLength + 1), + &outputLength, + inArrayPointer, + length ); + + if(result != 0) + { + // internal error occurred + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + + // create heap block array instance with appropriate size (the length of the output array) and type (byte which is uint8_t) + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( stack.PushValueAndClear() , outputLength, g_CLR_RT_WellKnownTypes.m_UInt8 )); + + // get a pointer to the array in the heap block array just created + returnArray = stack.TopValue().DereferenceArray()->GetFirstElement(); + + // copy outArray to the returnArray + memcpy(returnArray, outArray, outputLength); + + // need to free memory from outArray + platform_free(outArray); + + NANOCLR_NOCLEANUP(); +} + +double Library_corlib_native_System_Convert::GetDoubleFractionalPart(char* str, int length) +{ + double place = 1; + double returnValue = 0.0; + + for (int i = 0; i < length; i++) + { + // move decimal place to the right + place /= 10.0; + + returnValue += ((int)(*str++) - '0') * place; + } + + return returnValue; +} + +int64_t Library_corlib_native_System_Convert::GetIntegerPart(char* str, int length) +{ + int64_t returnValue = 0; + + for (int i = 0; i < length; i++) + { + returnValue = returnValue * 10 + (*str - '0'); + str++; + + // check for terminator, in case this is being called in 'guess' mode + if(*str == '\0') + { + break; + } + } + + return returnValue; +} + +int64_t Library_corlib_native_System_Convert::GetIntegerFromHexString(char* str) +{ + int64_t returnValue = 0; + + if ((*str == '0') && (*(str+1) == 'x')) + { + // there a 0x at the begining of the string, so move pointer forward 2 notches + str += 2; + } + + while (*str != '\0') + { + char c = toupper(*str++); + + if ((c < '0') || (c > 'F') || ((c > '9') && (c < 'A'))) + { + // there is an invalid char in the string + break; + } + + c -= '0'; + + if (c > 9) + { + c -= 7; + } + + returnValue = (returnValue << 4) + c; + } + + return returnValue; +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_DateTime.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_DateTime.cpp new file mode 100644 index 00000000..60b26107 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_DateTime.cpp @@ -0,0 +1,270 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "CorLib.h" + +HRESULT Library_corlib_native_System_DateTime::_ctor___VOID__I4__I4__I4__I4__I4__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* pArg = &(stack.Arg1()); + SYSTEMTIME st; + + NANOCLR_CLEAR(st); + st.wYear = pArg[ 0 ].NumericByRef().s4; + st.wMonth = pArg[ 1 ].NumericByRef().s4; + st.wDay = pArg[ 2 ].NumericByRef().s4; + st.wHour = pArg[ 3 ].NumericByRef().s4; + st.wMinute = pArg[ 4 ].NumericByRef().s4; + st.wSecond = pArg[ 5 ].NumericByRef().s4; + st.wMilliseconds = pArg[ 6 ].NumericByRef().s4; + + /// Our current supported range is between 1601 and 3000. Years before 1582 requires different calculation (see explanation + /// in time_decl.h), same way years after 3000 will not hold the simple arithmetic which we are using. More complex calculations + /// outside these range are not worth the CPU cycle and codesize. + if ((st.wYear < 1601) || (st.wYear > 3000) || + (st.wMonth < 1) || (st.wMonth > 12) || + (st.wDay < 1) || (st.wDay > 31)) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + } + + + Compress( stack, st ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_DateTime::get_Day___I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + SYSTEMTIME st; Expand( stack, st ); + + stack.SetResult_I4( st.wDay ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_DateTime::get_DayOfWeek___SystemDayOfWeek( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + SYSTEMTIME st; Expand( stack, st ); + + stack.SetResult_I4( st.wDayOfWeek ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_DateTime::get_DayOfYear___I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + SYSTEMTIME st ; + signed int days; + Expand( stack, st ); + + NANOCLR_CHECK_HRESULT(HAL_Time_AccDaysInMonth( st.wYear, st.wMonth, &days )); + days += st.wDay; + + stack.SetResult_I4( days ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_DateTime::get_Hour___I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + SYSTEMTIME st; Expand( stack, st ); + + stack.SetResult_I4( st.wHour ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_DateTime::get_Millisecond___I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + SYSTEMTIME st; Expand( stack, st ); + + stack.SetResult_I4( st.wMilliseconds ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_DateTime::get_Minute___I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + SYSTEMTIME st; Expand( stack, st ); + + stack.SetResult_I4( st.wMinute ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_DateTime::get_Month___I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + SYSTEMTIME st; Expand( stack, st ); + + stack.SetResult_I4( st.wMonth ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_DateTime::get_Second___I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + SYSTEMTIME st; Expand( stack, st ); + + stack.SetResult_I4( st.wSecond ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_DateTime::get_Year___I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + SYSTEMTIME st; Expand( stack, st ); + + stack.SetResult_I4( st.wYear ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_DateTime::DaysInMonth___STATIC__I4__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_INT32 year = stack.Arg0().NumericByRef().s4; + CLR_INT32 month = stack.Arg1().NumericByRef().s4; + CLR_INT32 days = 0; + + HAL_Time_DaysInMonth( year, month, &days ); + + stack.SetResult_I4( days ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_DateTime::get_UtcNow___STATIC__SystemDateTime( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_INT64* pRes = NewObject( stack ); + + // request full date&time + *pRes = HAL_Time_CurrentDateTime(false); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_DateTime::get_Today___STATIC__SystemDateTime( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_INT64* pRes = NewObject( stack ); + + // request date part only + *pRes = HAL_Time_CurrentDateTime(true); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +//--// + +CLR_INT64* Library_corlib_native_System_DateTime::NewObject( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock& ref = stack.PushValue(); + + ref.SetDataId( CLR_RT_HEAPBLOCK_RAW_ID(DATATYPE_DATETIME, 0, 1) ); + ref.ClearData(); + + //return (CLR_INT64*)&ref.NumericByRef().s8; + // NOTE: reinterpret_cast is a test. It can be safely removed ;) + return reinterpret_cast(&ref.NumericByRef().s8); +} + +CLR_INT64* Library_corlib_native_System_DateTime::GetValuePtr( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + return GetValuePtr( stack.Arg0() ); +} + +CLR_INT64* Library_corlib_native_System_DateTime::GetValuePtr( CLR_RT_HeapBlock& ref ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock* obj = &ref; + CLR_DataType dt = obj->DataType(); + + if(dt == DATATYPE_OBJECT || dt == DATATYPE_BYREF) + { + obj = obj->Dereference(); if(!obj) return NULL; + dt = obj->DataType(); + } + + if(dt == DATATYPE_DATETIME) + { + return (CLR_INT64*)&obj->NumericByRef().s8; + } + + if(dt == DATATYPE_I8) + { + return (CLR_INT64*)&obj->NumericByRef().s8; + } + + if(dt == DATATYPE_VALUETYPE && obj->ObjectCls().m_data == g_CLR_RT_WellKnownTypes.m_DateTime.m_data) + { + return (CLR_INT64*)&obj[ FIELD___ticks ].NumericByRef().s8; + } + + return NULL; +} + +void Library_corlib_native_System_DateTime::Expand( CLR_RT_StackFrame& stack, SYSTEMTIME& st ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_INT64* val = GetValuePtr( stack ); + + if(val) + { + CLR_INT64 ticks = *val; + HAL_Time_ToSystemTime( ticks, &st ); + } +} + +// Compress function always creates local time. +void Library_corlib_native_System_DateTime::Compress( CLR_RT_StackFrame& stack, const SYSTEMTIME& st ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_INT64* val = GetValuePtr( stack ); + + if(val) + { + *val = HAL_Time_ConvertFromSystemTime( &st ); + } +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Delegate.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Delegate.cpp new file mode 100644 index 00000000..fc08e48e --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Delegate.cpp @@ -0,0 +1,184 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_Delegate::Equals___BOOLEAN__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + stack.SetResult_Boolean( CLR_RT_HeapBlock::Compare_Unsigned_Values( stack.Arg0(), stack.Arg1() ) == 0 ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +#if (NANOCLR_REFLECTION == TRUE) + +HRESULT Library_corlib_native_System_Delegate::GetInvocationList___SZARRAY_SystemDelegate( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Delegate *dlg = stack.Arg0().DereferenceDelegate(); + CLR_RT_HeapBlock_Delegate_List *lst = (CLR_RT_HeapBlock_Delegate_List *)dlg; + + int delegatesCount = 0; + CLR_RT_HeapBlock *returnArray = NULL; + + // put the return array on the stack + CLR_RT_HeapBlock &top = stack.PushValueAndClear(); + + if (dlg) { + if (dlg->DataType() == DATATYPE_DELEGATELIST_HEAD) { + delegatesCount = lst->m_length; + } else { + delegatesCount = 1; + } + } + + // create the result array + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance(top, delegatesCount, g_CLR_RT_WellKnownTypes.m_Delegate)); + + if (delegatesCount > 0) { + + // get the pointer to the first element + returnArray = (CLR_RT_HeapBlock *)top.DereferenceArray()->GetFirstElement(); + + if (delegatesCount > 1) { + CLR_RT_HeapBlock *ptr = lst->GetDelegates(); + // fill the array with the delegates + for (int i = 0; i < delegatesCount; i++) { + + // create an instance of delegate + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*returnArray, g_CLR_RT_WellKnownTypes.m_Delegate)); + + //fetch delegate from list + dlg = ptr[i].DereferenceDelegate(); + //set delegate reference to return element + returnArray->SetObjectReference(dlg); + + returnArray++; + } + } else { + // create an instance of delegate + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*returnArray, g_CLR_RT_WellKnownTypes.m_Delegate)); + //set delegate reference to return element + returnArray->SetObjectReference(dlg); + } + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Delegate::get_Method___SystemReflectionMethodInfo( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Delegate* dlg = stack.Arg0().DereferenceDelegate(); + + dlg = GetLastDelegate( dlg ); if(!dlg) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + { + CLR_RT_HeapBlock& top = stack.PushValue(); + CLR_RT_HeapBlock* hbObj; + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_MethodInfo)); + hbObj = top.Dereference(); + + hbObj->SetReflection( dlg->DelegateFtn() ); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Delegate::get_Target___OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Delegate* dlg = stack.Arg0().DereferenceDelegate(); + + dlg = GetLastDelegate( dlg ); if(!dlg) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + { + stack.PushValueAndAssign( dlg->m_object ); + } + + NANOCLR_NOCLEANUP(); +} + +#endif // NANOCLR_REFLECTION + +HRESULT Library_corlib_native_System_Delegate::Combine___STATIC__SystemDelegate__SystemDelegate__SystemDelegate( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(CLR_RT_HeapBlock_Delegate_List::Combine( stack.PushValue(), stack.Arg0(), stack.Arg1(), false )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Delegate::Remove___STATIC__SystemDelegate__SystemDelegate__SystemDelegate( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(CLR_RT_HeapBlock_Delegate_List::Remove( stack.PushValue(), stack.Arg0(), stack.Arg1() )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Delegate::op_Equality___STATIC__BOOLEAN__SystemDelegate__SystemDelegate( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(Library_corlib_native_System_Delegate::Equals___BOOLEAN__OBJECT( stack )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Delegate::op_Inequality___STATIC__BOOLEAN__SystemDelegate__SystemDelegate( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_CHECK_HRESULT(Library_corlib_native_System_Delegate::op_Equality___STATIC__BOOLEAN__SystemDelegate__SystemDelegate( stack )); + + stack.NegateResult(); + + NANOCLR_NOCLEANUP(); +} + +//--// + +CLR_RT_HeapBlock_Delegate* Library_corlib_native_System_Delegate::GetLastDelegate( CLR_RT_HeapBlock_Delegate* dlg ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(dlg) + { + if(dlg->DataType() == DATATYPE_DELEGATELIST_HEAD) + { + CLR_RT_HeapBlock_Delegate_List* lst = (CLR_RT_HeapBlock_Delegate_List*)dlg; + + if(lst->m_length == 0) + { + dlg = NULL; + } + else + { + CLR_RT_HeapBlock* ptr = lst->GetDelegates(); + + dlg = ptr[ lst->m_length-1 ].DereferenceDelegate(); + } + } + } + + return dlg; +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Diagnostics_Debugger.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Diagnostics_Debugger.cpp new file mode 100644 index 00000000..3a2e394f --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Diagnostics_Debugger.cpp @@ -0,0 +1,50 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_Diagnostics_Debugger::get_IsAttached___STATIC__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + stack.SetResult_Boolean( CLR_EE_DBG_IS( SourceLevelDebugging )); + +#else + + stack.SetResult_Boolean( false ); + +#endif + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_Diagnostics_Debugger::Break___STATIC__VOID( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + if(stack.m_customState == 0) + { + stack.m_customState++; + g_CLR_RT_ExecutionEngine.Breakpoint_StackFrame_Break( &stack ); + + hr = CLR_E_RESCHEDULE; NANOCLR_LEAVE(); + } + + NANOCLR_NOCLEANUP(); + +#else + (void)stack; + NANOCLR_NOCLEANUP_NOLABEL(); + +#endif + +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Double.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Double.cpp new file mode 100644 index 00000000..2c3ddcd3 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Double.cpp @@ -0,0 +1,112 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" +#include "nanoPAL_NativeDouble.h" + +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + +HRESULT Library_corlib_native_System_Double::CompareTo___STATIC__I4__R8__R8( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double d = stack.Arg0().NumericByRefConst().r8; + double val = stack.Arg1().NumericByRefConst().r8; + CLR_INT32 res = System::Double::CompareTo( d, val ); + + stack.PushValue().SetInteger( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_Double::IsInfinity___STATIC__BOOLEAN__R8( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double d = stack.Arg0().NumericByRefConst().r8; + bool res = System::Double::IsInfinity( d ); + + stack.SetResult_Boolean( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_Double::IsNaN___STATIC__BOOLEAN__R8( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double d = stack.Arg0().NumericByRefConst().r8; + bool res = System::Double::IsNaN( d ); + + stack.SetResult_Boolean( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_Double::IsNegativeInfinity___STATIC__BOOLEAN__R8( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double d = stack.Arg0().NumericByRefConst().r8; + bool res = System::Double::IsNegativeInfinity( d ); + + stack.SetResult_Boolean( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_Double::IsPositiveInfinity___STATIC__BOOLEAN__R8( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double d = stack.Arg0().NumericByRefConst().r8; + bool res = System::Double::IsPositiveInfinity( d ); + + stack.SetResult_Boolean( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +#else + +HRESULT Library_corlib_native_System_Double::CompareTo___STATIC__I4__R8__R8( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_INT64 left = stack.Arg0().NumericByRef().s8; + CLR_INT64 right = stack.Arg1().NumericByRef().s8; + + stack.SetResult_I4((left < right) ? -1 : (left > right) ? 1 : 0); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_Double::IsInfinity___STATIC__BOOLEAN__R8( CLR_RT_StackFrame& stack ) +{ + stack.NotImplementedStub(); +} + +HRESULT Library_corlib_native_System_Double::IsNaN___STATIC__BOOLEAN__R8( CLR_RT_StackFrame& stack ) +{ + stack.NotImplementedStub(); +} + +HRESULT Library_corlib_native_System_Double::IsNegativeInfinity___STATIC__BOOLEAN__R8( CLR_RT_StackFrame& stack ) +{ + stack.NotImplementedStub(); +} + +HRESULT Library_corlib_native_System_Double::IsPositiveInfinity___STATIC__BOOLEAN__R8( CLR_RT_StackFrame& stack ) +{ + stack.NotImplementedStub(); +} + +#endif diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Enum.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Enum.cpp new file mode 100644 index 00000000..488a22e7 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Enum.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + +// no code generated for this class diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Exception.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Exception.cpp new file mode 100644 index 00000000..0205f404 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Exception.cpp @@ -0,0 +1,236 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + +struct ExceptionLookup +{ + HRESULT hr; + CLR_RT_TypeDef_Index* ptr; +}; + +static const ExceptionLookup c_ExceptionLookup[] = +{ +#define EL(hr,fld) { hr, &g_CLR_RT_WellKnownTypes.fld } + EL(CLR_E_APPDOMAIN_EXITED , m_AppDomainUnloadedException ), + EL(CLR_E_INVALID_PARAMETER , m_ArgumentException ), + EL(CLR_E_ARGUMENT_NULL , m_ArgumentNullException ), + EL(CLR_E_OUT_OF_RANGE , m_ArgumentOutOfRangeException), + EL(CLR_E_INDEX_OUT_OF_RANGE , m_IndexOutOfRangeException ), + EL(CLR_E_INVALID_CAST , m_InvalidCastException ), + EL(CLR_E_INVALID_OPERATION , m_InvalidOperationException ), + EL(CLR_E_NOT_SUPPORTED , m_NotSupportedException ), + EL(CLR_E_NOTIMPL , m_NotImplementedException ), + EL(CLR_E_NULL_REFERENCE , m_NullReferenceException ), + EL(CLR_E_OUT_OF_MEMORY , m_OutOfMemoryException ), + EL(CLR_E_OBJECT_DISPOSED , m_ObjectDisposedException ), + EL(CLR_E_WATCHDOG_TIMEOUT , m_WatchdogException ), + +#undef EL +}; + +//--// + +HRESULT Library_corlib_native_System_Exception::get_StackTrace___STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* pArray; + StackTrace* pStackTrace; + CLR_RT_HeapBlock* pBlkString; + char buf[ 512 ]; + char* strName; + size_t iName; + CLR_RT_HeapBlock tmpArray; tmpArray.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc(tmpArray); + int depth = 0; + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + pArray = pThis[ FIELD___stackTrace ].DereferenceArray(); + + if(pArray) + { + _ASSERTE(pArray->m_typeOfElement == DATATYPE_U1); + + depth = pArray->m_numOfElements / sizeof(StackTrace); + } + + if(depth == 0) NANOCLR_SET_AND_LEAVE(stack.SetResult_String(NULL)); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( tmpArray, depth, g_CLR_RT_WellKnownTypes.m_String )); + + pStackTrace = (StackTrace*)pArray->GetFirstElement(); + pBlkString = (CLR_RT_HeapBlock*)tmpArray.DereferenceArray()->GetFirstElement(); + + for(int i = 0; i < depth; i++) + { + strName = &buf[ 0 ]; + iName = MAXSTRLEN(buf) - 2 ; + + NANOCLR_CHECK_HRESULT(g_CLR_RT_TypeSystem.BuildMethodName( pStackTrace->m_md, strName, iName )); + + memcpy(strName, "\r\n\0", 3); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( *pBlkString, buf )); + + pStackTrace++; + pBlkString++; + } + + NANOCLR_SET_AND_LEAVE(Library_corlib_native_System_String::Concat( stack, (CLR_RT_HeapBlock*)tmpArray.DereferenceArray()->GetFirstElement(), depth )); + + NANOCLR_NOCLEANUP(); +} + +//--// + +/* + This function will always succeed. + Return values + - S_OK. + - S_FALSE. ref points to the pre-allocated OutOfMemory exception +*/ +HRESULT Library_corlib_native_System_Exception::CreateInstance( CLR_RT_HeapBlock& ref, const CLR_RT_TypeDef_Index& cls, HRESULT hrIn, CLR_RT_StackFrame* stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + +#if defined(NANOCLR_APPDOMAINS) + CLR_RT_AppDomain* appDomainSav = g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( stack->m_appDomain ); +#endif + + CLR_RT_HeapBlock* obj; + + _ASSERTE(CLR_RT_ExecutionEngine::IsInstanceOf( cls, g_CLR_RT_WellKnownTypes.m_Exception )); + + if(FAILED(hr = g_CLR_RT_ExecutionEngine.NewObjectFromIndex( ref, cls ))) + { +#if defined(NANOCLR_APPDOMAINS) + ref.SetObjectReference( g_CLR_RT_ExecutionEngine.GetCurrentAppDomain()->m_outOfMemoryException ); +#else + ref.SetObjectReference( g_CLR_RT_ExecutionEngine.m_outOfMemoryException ); +#endif + + hrIn = CLR_E_OUT_OF_MEMORY; + hr = S_FALSE; + } + + obj = ref.Dereference(); + + obj[ FIELD__HResult ].SetInteger( (CLR_UINT32)hrIn ); + + if(hr == S_OK) + { + (void)SetStackTrace( ref, stack ); + } + +#if defined(NANOCLR_APPDOMAINS) + (void)g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( appDomainSav ); +#endif + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_Exception::CreateInstance( CLR_RT_HeapBlock& ref, HRESULT hrIn, CLR_RT_StackFrame* stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_TypeDef_Index* cls = &g_CLR_RT_WellKnownTypes.m_Exception; + + _ASSERTE(FAILED(hrIn)); + + for(uint32_t i = 0; i < ARRAYSIZE(c_ExceptionLookup); i++) + { + if(c_ExceptionLookup[ i ].hr == hrIn) + { + cls = c_ExceptionLookup[ i ].ptr; + break; + } + } + + return CreateInstance( ref, *cls, hrIn, stack ); +} + +HRESULT Library_corlib_native_System_Exception::SetStackTrace( CLR_RT_HeapBlock& ref, CLR_RT_StackFrame* stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(stack) + { + CLR_RT_HeapBlock* obj; + CLR_RT_HeapBlock_Array* array; + StackTrace* dst; + CLR_UINT32 depth; + + if(CLR_RT_ExecutionEngine::IsInstanceOf( ref, g_CLR_RT_WellKnownTypes.m_Exception ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + //--// + + obj = ref.Dereference(); + depth = 0; + + NANOCLR_FOREACH_NODE_BACKWARD__DIRECT(CLR_RT_StackFrame,stackSub,stack) + { + depth++; + } + NANOCLR_FOREACH_NODE_BACKWARD_END(); + + //--// + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( obj[ FIELD___stackTrace ], depth * sizeof(StackTrace), g_CLR_RT_WellKnownTypes.m_UInt8 )); + + //--// + + array = obj[ FIELD___stackTrace ].DereferenceArray(); + dst = (StackTrace*)array->GetFirstElement(); + + NANOCLR_FOREACH_NODE_BACKWARD__DIRECT(CLR_RT_StackFrame,stackSub,stack) + { + dst->m_md = stackSub->m_call; + dst->m_IP = (CLR_UINT32)(stackSub->m_IP - stackSub->m_IPstart); + + dst++; + } + NANOCLR_FOREACH_NODE_BACKWARD_END(); + +#if !defined(BUILD_RTM) + //shutting down the EE happens by Thread->Abort. These exceptions are by design, and + //don't need to be logged, or written to the console.... + if(!g_CLR_RT_ExecutionEngine.m_fShuttingDown) +#endif + { + CLR_RT_DUMP::EXCEPTION( *stack, ref ); + } + } + + NANOCLR_NOCLEANUP(); +} + +CLR_RT_HeapBlock* Library_corlib_native_System_Exception::GetTarget( CLR_RT_HeapBlock& ref ) +{ + NATIVE_PROFILE_CLR_CORE(); + return CLR_RT_ExecutionEngine::IsInstanceOf( ref, g_CLR_RT_WellKnownTypes.m_Exception ) ? ref.Dereference() : NULL; +} + +Library_corlib_native_System_Exception::StackTrace* Library_corlib_native_System_Exception::GetStackTrace( CLR_RT_HeapBlock* obj, CLR_UINT32& depth ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(obj) + { + CLR_RT_HeapBlock_Array* array = obj[ FIELD___stackTrace ].DereferenceArray(); + + if(array) + { + depth = array->m_numOfElements / sizeof(StackTrace); + + return (StackTrace*)array->GetFirstElement(); + } + } + + depth = 0; + + return NULL; +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_GC.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_GC.cpp new file mode 100644 index 00000000..2f94e266 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_GC.cpp @@ -0,0 +1,50 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_GC::AnyPendingFinalizers___STATIC__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + stack.SetResult_Boolean( g_CLR_RT_ExecutionEngine.m_finalizersPending.IsEmpty() == false + || (g_CLR_RT_ExecutionEngine.m_finalizerThread != NULL && !g_CLR_RT_ExecutionEngine.m_finalizerThread->CanThreadBeReused())); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_GC::SuppressFinalize___STATIC__VOID__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* pObj = stack.Arg0().Dereference(); FAULT_ON_NULL(pObj); + + CLR_RT_HeapBlock_Finalizer::SuppressFinalize( pObj ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_GC::ReRegisterForFinalize___STATIC__VOID__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_TypeDescriptor desc; + CLR_RT_HeapBlock* pObj = stack.Arg0().Dereference(); FAULT_ON_NULL(pObj); + + CLR_RT_HeapBlock_Finalizer::SuppressFinalize( pObj ); + + NANOCLR_CHECK_HRESULT(desc.InitializeFromObject( stack.Arg0() )); + + if(desc.m_handlerCls.HasFinalizer()) + { + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Finalizer::CreateInstance( stack.Arg0().Dereference(), desc.m_handlerCls )); + } + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Globalization_CultureInfo.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Globalization_CultureInfo.cpp new file mode 100644 index 00000000..274c3db7 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Globalization_CultureInfo.cpp @@ -0,0 +1,27 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_Globalization_CultureInfo::get_CurrentUICultureInternal___STATIC__SystemGlobalizationCultureInfo( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + stack.PushValue().SetObjectReference( g_CLR_RT_ExecutionEngine.m_currentUICulture ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_Globalization_CultureInfo::set_CurrentUICultureInternal___STATIC__VOID__SystemGlobalizationCultureInfo( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + g_CLR_RT_ExecutionEngine.m_currentUICulture = stack.Arg0().Dereference(); + + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Globalization_DateTimeFormat.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Globalization_DateTimeFormat.cpp new file mode 100644 index 00000000..a667560a --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Globalization_DateTimeFormat.cpp @@ -0,0 +1,39 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_Globalization_DateTimeFormat::FormatDigits___STATIC__STRING__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* pArgs = &(stack.Arg0()); + + int value = pArgs[ 0 ].NumericByRef().s4; + int len = pArgs[ 1 ].NumericByRef().s4; + + char buffer[ 12 ]; // Enough to accommodate max int + + char fmt [10]; + + if(len >= 2) + { + sprintf( fmt, "%%0%dd", len ); + } + else + { + fmt[0] = '%'; + fmt[1] = 'd'; + fmt[2] = '\0'; + } + + sprintf( buffer, fmt, value ); + + NANOCLR_SET_AND_LEAVE(stack.SetResult_String( buffer )); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Guid.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Guid.cpp new file mode 100644 index 00000000..ccadaf36 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Guid.cpp @@ -0,0 +1,34 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + +// +// Generate a new GUID +// +// Based on the version 4 GUID (random) +// http://guid.one/guid/make + + +HRESULT Library_corlib_native_System_Guid::GenerateNewGuid___STATIC__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_Random rand; + CLR_UINT8* buf; + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + + // Create a array of 16 bytes on top of stack to return + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( top, 16, g_CLR_RT_WellKnownTypes.m_UInt8 )); + buf = top.DereferenceArray()->GetFirstElement(); + + rand.Initialize(); + rand.NextBytes(buf, 16); // fill with random numbers + + buf[7] = (buf[7] & 0x0f) | 0x40; // Set verion + buf[9] = (buf[7] & 0x3f) | 0x80; // Set variant + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_MarshalByRefObject.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_MarshalByRefObject.cpp new file mode 100644 index 00000000..488a22e7 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_MarshalByRefObject.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + +// no code generated for this class diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_MathInternal.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_MathInternal.cpp new file mode 100644 index 00000000..335f396c --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_MathInternal.cpp @@ -0,0 +1,48 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + +HRESULT Library_corlib_native_System_MathInternal::Abs___STATIC__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_INT32 d = stack.Arg0().NumericByRefConst().s4; + CLR_INT32 res = abs( d ); + + stack.SetResult_I4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_MathInternal::Max___STATIC__I4__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_INT32 x = stack.Arg0().NumericByRefConst().s4; + CLR_INT32 y = stack.Arg1().NumericByRefConst().s4; + CLR_INT32 res = x >= y ? x : y; + + stack.SetResult_I4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_MathInternal::Min___STATIC__I4__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_INT32 x = stack.Arg0().NumericByRefConst().s4; + CLR_INT32 y = stack.Arg1().NumericByRefConst().s4; + CLR_INT32 res = x <= y ? x : y; + + stack.SetResult_I4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_MulticastDelegate.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_MulticastDelegate.cpp new file mode 100644 index 00000000..7ee1daf5 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_MulticastDelegate.cpp @@ -0,0 +1,27 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_MulticastDelegate::op_Equality___STATIC__BOOLEAN__SystemMulticastDelegate__SystemMulticastDelegate( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(Library_corlib_native_System_Delegate::op_Equality___STATIC__BOOLEAN__SystemDelegate__SystemDelegate( stack )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_MulticastDelegate::op_Inequality___STATIC__BOOLEAN__SystemMulticastDelegate__SystemMulticastDelegate( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(Library_corlib_native_System_Delegate::op_Inequality___STATIC__BOOLEAN__SystemDelegate__SystemDelegate( stack )); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Number.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Number.cpp new file mode 100644 index 00000000..e67e1793 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Number.cpp @@ -0,0 +1,266 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + +// compose sprintf format string according to requested parameters +void nf_GetFormatString(char* formatStr, char formatCh, int precision, bool isLong, bool isFloat, bool isSigned) +{ + if(formatCh == 'X' || formatCh=='x') + sprintf(formatStr, "%%0%d%sX", precision, isLong ? "ll" : ""); + else + sprintf(formatStr, "%%%s%d%s%s", isFloat ? "." : isSigned ? "-0" : "0", precision, isLong ? "ll" : isFloat ? "f" : "", isFloat ? "" : isSigned ? "d" : "u"); +} + +// remove the prepended zeros and (if possible) the decimal point in a float that's formated as string. e.g. "47.1100815000000" => "47.1100815" or "8.0000E-12" => "8E-12" +void nf_RemovePrependedZeros(char* floatStr) +{ + int length = hal_strlen_s(floatStr); + // flag for finding the decimal point + bool pointFound = false; + // if not -1 we found the first zero after the decimal point + int firstZero = -1; + // if not -1 we found an "e" or "E" after the last zero of this is the string length + int nextNonZero = length; + + // iterate thru all chars + for (int i = 0; i < length; i++) + { + // no decimal point found until now? + if (!pointFound) + { + // is it the decimal point? + if (floatStr[i] == '.') + { + pointFound = true; + } + + // next char + continue; + } + + // at this point we found the decimal point + // no zero found until now? + if (firstZero == -1) + { + // is it a zero? + if (floatStr[i] == '0') + { + // store the position of the first zero after the decimal point + firstZero = i; + } + + // next char + continue; + } + + // at this point we found the decimal point and the first zero + // an "e" or "E" char stops the sequence of zeros + if (floatStr[i] == 'e' || floatStr[i] == 'E') + { + // store the position of the e/E char + nextNonZero = i; + // done! we found the positions for the prepended zeros + break; + } + + // at this point we found the decimal point and the first zero and the current char is not the e/E char + // is this not a zero? + if (floatStr[i] != '0') + { + // reset! we need to find another zero + firstZero = -1; + } + } + + // something to remove? + if (pointFound && firstZero != -1 && nextNonZero != -1) + { + // is the char before the first zero the decimal point? => Remove the decimal point + int startIndex = floatStr[firstZero - 1] == '.' ? firstZero - 1 : firstZero; + // no e/E char after the last trailing zero? + if (nextNonZero == length) + { + // we can cut away the prepended zeros by terminating the string at first zero + floatStr[startIndex] = 0; + } + else + { + // otherwise we copy the last part over the prepended zeros and terminate the string + int lengthToCopy = length - nextNonZero; + memcpy(&floatStr[startIndex], &floatStr[nextNonZero], lengthToCopy); + floatStr[startIndex + lengthToCopy] = 0; + } + } +} + +HRESULT Library_corlib_native_System_Number::FormatNative___STATIC__STRING__OBJECT__CHAR__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* pArgs = &(stack.Arg0()); + CLR_RT_HeapBlock* value = pArgs; + CLR_DataType dt; + CLR_RT_TypeDescriptor desc; + char result[ 24 ]; + // This is temporary buffer to create proper format string. + char formatStr[ 8 ]; + char formatCh = (char)pArgs[ 1 ].NumericByRef().u1; + int precision = pArgs[ 2 ].NumericByRef().s4; + bool shouldRemovePrependedZeros = false; + + NANOCLR_CHECK_HRESULT(desc.InitializeFromObject( *value )); + NANOCLR_CHECK_HRESULT(value->PerformUnboxing( desc.m_handlerCls )); + + dt = value->DataType(); + + if(formatCh == 'G' && precision == 0) + { + precision = 1; + shouldRemovePrependedZeros = true; + } + + switch(dt) + { + case DATATYPE_I1: + // get format string + nf_GetFormatString(formatStr, formatCh, precision, false, false, true); + sprintf(result, formatStr, value->NumericByRef().s1 ); + break; + + case DATATYPE_U1: + // get format string + nf_GetFormatString(formatStr, formatCh, precision, false, false, false); + sprintf(result, formatStr, value->NumericByRef().u1 ); + break; + + case DATATYPE_I2: + // get format string + nf_GetFormatString(formatStr, formatCh, precision, false, false, true); + sprintf(result, formatStr, value->NumericByRef().s2 ); + break; + + case DATATYPE_U2: + // get format string + nf_GetFormatString(formatStr, formatCh, precision, false, false, false); + sprintf(result, formatStr, value->NumericByRef().u2 ); + break; + + case DATATYPE_I4: + // get format string + nf_GetFormatString(formatStr, formatCh, precision, false, false, true); + sprintf(result, formatStr, value->NumericByRef().s4); + break; + + case DATATYPE_U4: + // get format string + nf_GetFormatString(formatStr, formatCh, precision, false, false, false); + sprintf(result, formatStr, value->NumericByRef().u4); + break; + + case DATATYPE_I8: + { + #if defined(_WIN32) + hal_snprintf( result, ARRAYSIZE(result), "%I64d",(CLR_INT64_TEMP_CAST)value->NumericByRef().s8 ); + #else + // get format string + nf_GetFormatString(formatStr, formatCh, precision, true, false, true); + sprintf(result, formatStr, (CLR_INT64_TEMP_CAST)value->NumericByRef().s8); + #endif // defined(_WIN32) + } + break; + + case DATATYPE_U8: + { + #if defined(_WIN32) + hal_snprintf( result, ARRAYSIZE(result), "%I64u",(CLR_UINT64_TEMP_CAST)value->NumericByRef().u8 ); + #else + // get format string + nf_GetFormatString(formatStr, formatCh, precision, true, false, false); + sprintf(result, formatStr, (CLR_UINT64_TEMP_CAST)value->NumericByRef().u8 ); + #endif // defined(_WIN32) + } + break; + + case DATATYPE_R4: + { + // All the formatCh have been converted to upper case in the managed layer + _ASSERTE(formatCh == 'G' || formatCh == 'N' || formatCh == 'F' || formatCh == 'D'); + + if (precision < 0 || precision > 99) + { + NANOCLR_SET_AND_LEAVE( CLR_E_INVALID_PARAMETER ); + } + + // DATATYPE_R4 is float and uses a precision of 9, standard sprintf format is "%.9g" + + #if defined(_WIN32) || defined(WIN32) || defined(_WIN32_WCE) + hal_snprintf( result, ARRAYSIZE(result), "%.9g", value->NumericByRef().r4 ); + #else + + #if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + // use default precision is none is specfied AND if format in not generic + precision = (formatCh == 'G' && precision == 1) ? 9 : precision; + + // get format string + nf_GetFormatString(formatStr, formatCh, precision, false, true, false); + + sprintf(result, formatStr, value->NumericByRef().r4); + if (shouldRemovePrependedZeros) + { + nf_RemovePrependedZeros(result); + } + #else + CLR_INT32 f = value->NumericByRef().r4; + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + #endif // !defined(NANOCLR_EMULATED_FLOATINGPOINT) + #endif // defined(_WIN32) + } + break; + + case DATATYPE_R8: + { + // All the formatCh have been converted to upper case in the managed layer + _ASSERTE(formatCh == 'G' || formatCh == 'N' || formatCh == 'F' || formatCh == 'D'); + + if (precision < 0 || precision > 99) + { + NANOCLR_SET_AND_LEAVE( CLR_E_INVALID_PARAMETER ); + } + + // DATATYPE_R8 is double and uses a precision of 15, standard sprintf format is "%.15g" + + #if defined(_WIN32) || defined(WIN32) || defined(_WIN32_WCE) + hal_snprintf( result, ARRAYSIZE(result), "%.15g", (CLR_DOUBLE_TEMP_CAST)value->NumericByRef().r8 ); + #else + #if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + // use default precision is none is specfied AND format is not generic + precision = (formatCh == 'G' && precision == 1) ? 15 : precision; + + // get format string + nf_GetFormatString(formatStr, formatCh, precision, false, true, false); + + sprintf(result, formatStr, (CLR_DOUBLE_TEMP_CAST)value->NumericByRef().r8); + if (shouldRemovePrependedZeros) + { + nf_RemovePrependedZeros(result); + } + #else + CLR_INT64 d = (CLR_DOUBLE_TEMP_CAST)value->NumericByRef().r8; + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + #endif // !defined(NANOCLR_EMULATED_FLOATINGPOINT) + #endif // defined(_WIN32) + } + break; + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + + NANOCLR_SET_AND_LEAVE(stack.SetResult_String( result )); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Object.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Object.cpp new file mode 100644 index 00000000..6f7dde24 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Object.cpp @@ -0,0 +1,91 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +//--// + +HRESULT Library_corlib_native_System_Object::Equals___BOOLEAN__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + stack.SetResult_Boolean( CLR_RT_HeapBlock::ObjectsEqual( stack.Arg0(), stack.Arg1(), true ) ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_Object::GetHashCode___I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + stack.SetResult_I4( CLR_RT_HeapBlock::GetHashCode( stack.This(), true, 0 ) ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +#if (NANOCLR_REFLECTION == TRUE) + +HRESULT Library_corlib_native_System_Object::GetType___SystemType( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_TypeDescriptor desc; + CLR_RT_ReflectionDef_Index idx; + CLR_RT_HeapBlock& arg0 = stack.Arg0(); + CLR_RT_HeapBlock* pObj; + + NANOCLR_CHECK_HRESULT(desc.InitializeFromObject( arg0 )); + + pObj = arg0.Dereference(); + + if(pObj && pObj->DataType() == DATATYPE_REFLECTION) + { + idx.m_kind = REFLECTION_TYPE; + idx.m_levels = 0; + idx.m_data.m_type.m_data = desc.m_handlerCls.m_data; + } + else + { + idx = desc.m_reflex; + } + + { + CLR_RT_HeapBlock& top = stack.PushValue(); + CLR_RT_HeapBlock* hbObj; + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_TypeStatic)); + + hbObj = top.Dereference(); + hbObj->SetReflection( idx ); + } + + NANOCLR_NOCLEANUP(); +} + +#endif // NANOCLR_REFLECTION + +HRESULT Library_corlib_native_System_Object::MemberwiseClone___OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(g_CLR_RT_ExecutionEngine.CloneObject( stack.PushValueAndClear(), stack.Arg0() )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Object::ReferenceEquals___STATIC__BOOLEAN__OBJECT__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + stack.SetResult_Boolean( CLR_RT_HeapBlock::ObjectsEqual( stack.Arg0(), stack.Arg1(), true ) ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Random.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Random.cpp new file mode 100644 index 00000000..233dd569 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Random.cpp @@ -0,0 +1,125 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_Random::Next___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_Random* rand; + + NANOCLR_CHECK_HRESULT(GetRandom( stack, rand )); + + stack.SetResult_I4( rand->Next() & 0x7FFFFFFF ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Random::Next___I4__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_Random* rand; + CLR_INT32 maxValue; + + NANOCLR_CHECK_HRESULT(GetRandom( stack, rand )); + + maxValue = stack.Arg1().NumericByRef().s4; + + if(maxValue <= 0) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + + stack.SetResult_I4( rand->Next() % maxValue ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Random::NextDouble___R8( CLR_RT_StackFrame& stack ) +{ + + + NANOCLR_HEADER(); + + CLR_RT_Random* rand; + +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + + double nextDouble; +#else + CLR_INT64 nextDouble; + +#endif + + NANOCLR_CHECK_HRESULT(GetRandom( stack, rand )); + + nextDouble = rand->NextDouble(); + + stack.SetResult_R8( nextDouble ); + + NANOCLR_NOCLEANUP(); + + +} + +HRESULT Library_corlib_native_System_Random::NextBytes___VOID__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_Random* rand; + CLR_RT_HeapBlock_Array* buffer; + + NANOCLR_CHECK_HRESULT(GetRandom( stack, rand )); + + buffer = stack.Arg1().DereferenceArray(); FAULT_ON_NULL(buffer); + + rand->NextBytes( buffer->GetFirstElement(), buffer->m_numOfElements ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Random::_ctor___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_Random* rand; + + NANOCLR_CHECK_HRESULT(GetRandom( stack, rand, true )); + + rand->Initialize(); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Random::_ctor___VOID__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_Random* rand; + + NANOCLR_CHECK_HRESULT(GetRandom( stack, rand, true )); + + rand->Initialize( stack.Arg1().NumericByRef().s4 ); + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT Library_corlib_native_System_Random::GetRandom( CLR_RT_StackFrame& stack, CLR_RT_Random*& rand, bool create ) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + if(create) + { + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_BinaryBlob::CreateInstance( pThis[ FIELD___random ], sizeof(CLR_RT_Random), NULL, NULL, 0 )); + } + + rand = (CLR_RT_Random*)pThis[ FIELD___random ].DereferenceBinaryBlob()->GetData(); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_Assembly.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_Assembly.cpp new file mode 100644 index 00000000..d1165947 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_Assembly.cpp @@ -0,0 +1,324 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_Reflection_Assembly::get_FullName___STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + //The defines for maxFULLNAME and parameters for snprintf are currently not validated. + CLR_RT_Assembly_Instance instance; + CLR_RT_Assembly* assm; + char buffer[ NANOCLR_MAX_ASSEMBLY_NAME * 2 ]; + const CLR_RECORD_ASSEMBLY* header ; + CLR_RT_HeapBlock* hbAsm = stack.Arg0().Dereference(); + + NANOCLR_CHECK_HRESULT(GetTypeDescriptor( *hbAsm, instance )); + + assm = instance.m_assm; + header = assm->m_header; + + if(hal_strlen_s(assm->m_szName) > NANOCLR_MAX_ASSEMBLY_NAME) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + sprintf( buffer, + "%s, Version=%d.%d.%d.%d", + assm->m_szName, + header->version.iMajorVersion, + header->version.iMinorVersion, + header->version.iBuildNumber, + header->version.iRevisionNumber ); + + stack.SetResult_String( buffer ); + + NANOCLR_NOCLEANUP(); +#undef MAXFULLNAME +} + +HRESULT Library_corlib_native_System_Reflection_Assembly::GetType___SystemType__STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_Assembly_Instance assm; + CLR_RT_TypeDef_Index td; + CLR_RT_HeapBlock* hbRef; + CLR_RT_HeapBlock* hbObj; + const char* szClass = stack.Arg1().RecoverString(); + CLR_RT_HeapBlock* hbAsm = stack.Arg0().Dereference(); + + FAULT_ON_NULL(szClass); + FAULT_ON_NULL(hbAsm); + + NANOCLR_CHECK_HRESULT(GetTypeDescriptor( *hbAsm, assm )); + + hbRef = &stack.PushValueAndClear(); + + if(g_CLR_RT_TypeSystem.FindTypeDef( szClass, assm.m_assm, td )) + { + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*hbRef, g_CLR_RT_WellKnownTypes.m_TypeStatic)); + + hbObj = hbRef->Dereference(); + hbObj->SetReflection( td ); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Reflection_Assembly::GetTypes___SZARRAY_SystemType( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_Assembly_Instance assm; + CLR_RT_HeapBlock* hbAsm = stack.Arg0().Dereference(); + + NANOCLR_CHECK_HRESULT(GetTypeDescriptor( *hbAsm, assm )); + + { + CLR_RT_Assembly* pASSM = assm.m_assm; + CLR_UINT32 num = pASSM->m_pTablesSize[ TBL_TypeDef ]; + CLR_RT_HeapBlock& top = stack.PushValue(); + CLR_RT_HeapBlock* hbObj; + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( top, num, g_CLR_RT_WellKnownTypes.m_TypeStatic )); + + if(num) + { + CLR_RT_HeapBlock* pArray = (CLR_RT_HeapBlock*)top.DereferenceArray()->GetFirstElement(); + + for(CLR_UINT32 i=0; im_idx, i ); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*pArray, g_CLR_RT_WellKnownTypes.m_TypeStatic)); + + hbObj = pArray->Dereference(); + hbObj->SetReflection( idx ); + } + } + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Reflection_Assembly::GetVersion___VOID__BYREF_I4__BYREF_I4__BYREF_I4__BYREF_I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_StackFrame* caller = stack.Caller(); + if(caller == NULL) + { + NANOCLR_SET_AND_LEAVE(S_OK); + } + else + { + CLR_RT_Assembly_Instance assm; + CLR_RT_HeapBlock* hbAsm = stack.Arg0().Dereference(); + + NANOCLR_CHECK_HRESULT(GetTypeDescriptor( *hbAsm, assm )); + + const CLR_RECORD_VERSION& version = assm.m_assm->m_header->version; + + // we do not check for the reference not to be NULL because this is an internal method + stack.Arg1().Dereference()->NumericByRef().s4 = version.iMajorVersion; + stack.Arg2().Dereference()->NumericByRef().s4 = version.iMinorVersion; + stack.Arg3().Dereference()->NumericByRef().s4 = version.iBuildNumber; + stack.Arg4().Dereference()->NumericByRef().s4 = version.iRevisionNumber; + } + NANOCLR_NOCLEANUP(); +} + + +HRESULT Library_corlib_native_System_Reflection_Assembly::GetManifestResourceNames___SZARRAY_STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_Assembly_Instance assm; + CLR_RT_HeapBlock* hbAsm = stack.Arg0().Dereference(); + + NANOCLR_CHECK_HRESULT(GetTypeDescriptor( *hbAsm, assm )); + + { + CLR_RT_Assembly* pAssm = assm.m_assm; + CLR_RT_HeapBlock& result = stack.PushValue(); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( result, pAssm->m_pTablesSize[ TBL_ResourcesFiles ], g_CLR_RT_WellKnownTypes.m_String )); + + { + CLR_RT_HeapBlock* pArray = (CLR_RT_HeapBlock*)result.Array()->GetFirstElement(); + + for(int idxResourceFile = 0; idxResourceFile < pAssm->m_pTablesSize[ TBL_ResourcesFiles ]; idxResourceFile++) + { + const CLR_RECORD_RESOURCE_FILE* resourceFile = pAssm->GetResourceFile( idxResourceFile ); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( *pArray, pAssm->GetString( resourceFile->name ) )); + + pArray++; + } + } + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Reflection_Assembly::GetExecutingAssembly___STATIC__SystemReflectionAssembly( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + CLR_RT_HeapBlock* hbObj; + + CLR_RT_StackFrame* caller = stack.Caller(); if(caller == NULL) NANOCLR_SET_AND_LEAVE(S_OK); + + { + CLR_RT_Assembly_Index idx; idx.Set( caller->MethodCall().m_assm->m_idx ); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_Assembly)); + + hbObj = top.Dereference(); + hbObj->SetReflection( idx ); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Reflection_Assembly::LoadInternal___STATIC__SystemReflectionAssembly__STRING__BOOLEAN__I4__I4__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + +#if defined(NANOCLR_APPDOMAINS) + CLR_RT_AppDomain* appDomain = g_CLR_RT_ExecutionEngine.GetCurrentAppDomain(); +#endif + CLR_RT_HeapBlock* pArgs = &stack.Arg0(); + CLR_RT_HeapBlock* hbObj; + CLR_RT_Assembly* assembly; + const char* szAssembly; + CLR_RT_Assembly_Index idx; + bool fVersion; + CLR_INT16 maj, min, build, rev; + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + + szAssembly = pArgs[ 0 ].RecoverString(); FAULT_ON_NULL(szAssembly ); + fVersion = pArgs[ 1 ].NumericByRef().u1 != 0; + maj = pArgs[ 2 ].NumericByRef().s4; + min = pArgs[ 3 ].NumericByRef().s4; + build = pArgs[ 4 ].NumericByRef().s4; + rev = pArgs[ 5 ].NumericByRef().s4; + + if(fVersion && (maj == -1 || min == -1 || build == -1 || rev == -1)) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + if(fVersion) + { + CLR_RECORD_VERSION ver; + + ver.iMajorVersion = (CLR_UINT16)maj; + ver.iMinorVersion = (CLR_UINT16)min; + ver.iBuildNumber = (CLR_UINT16)build; + ver.iRevisionNumber = (CLR_UINT16)rev; + + assembly = g_CLR_RT_TypeSystem.FindAssembly( szAssembly, &ver, true ); FAULT_ON_NULL_HR(assembly, CLR_E_INVALID_PARAMETER); + } + else + { + assembly = g_CLR_RT_TypeSystem.FindAssembly( szAssembly, NULL, false ); FAULT_ON_NULL_HR(assembly, CLR_E_INVALID_PARAMETER); + } + +#if defined(NANOCLR_APPDOMAINS) + NANOCLR_CHECK_HRESULT(appDomain->LoadAssembly( assembly )); +#endif + idx.Set( assembly->m_idx ); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_Assembly)); + + hbObj = top.Dereference(); + hbObj->SetReflection( idx ); + + NANOCLR_CLEANUP(); + + //Avoid exception handling in common case. Just return NULL on failure. + //Managed code decides to throw the exception or not. + hr = S_OK; + + NANOCLR_CLEANUP_END(); +} + +HRESULT Library_corlib_native_System_Reflection_Assembly::Load___STATIC__SystemReflectionAssembly__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* array = NULL; + CLR_RT_Assembly* assm = NULL; + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + CLR_RT_HeapBlock* hbObj; + CLR_RECORD_ASSEMBLY* header; + + array = stack.Arg0().DereferenceArray(); FAULT_ON_NULL(array); + + header = (CLR_RECORD_ASSEMBLY*)array->GetFirstElement(); + + if(header->GoodAssembly()) + { + // + // Sorry, you'll have to reboot to load this assembly. + // + if(header->flags & CLR_RECORD_ASSEMBLY::c_Flags_NeedReboot) + { + NANOCLR_SET_AND_LEAVE(CLR_E_BUSY); + } + + NANOCLR_CHECK_HRESULT(CLR_RT_Assembly::CreateInstance( header, assm )); + + assm->m_pFile = array; + + g_CLR_RT_TypeSystem.Link( assm ); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_TypeSystem.ResolveAll ()); + NANOCLR_CHECK_HRESULT(g_CLR_RT_TypeSystem.PrepareForExecution()); + } + + if(assm) + { + CLR_RT_Assembly_Index idx; idx.Set( assm->m_idx ); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_Assembly)); + + hbObj = top.Dereference(); + hbObj->SetReflection( idx ); + } + + NANOCLR_CLEANUP(); + + if(FAILED(hr)) + { + if(assm) + { + assm->DestroyInstance(); + } + } + + NANOCLR_CLEANUP_END(); +} + +//--// + +HRESULT Library_corlib_native_System_Reflection_Assembly::GetTypeDescriptor( CLR_RT_HeapBlock& arg, CLR_RT_Assembly_Instance& inst ) +{ + NATIVE_PROFILE_CLR_CORE(); + return CLR_RT_ReflectionDef_Index::Convert( arg, inst ) ? S_OK : CLR_E_NULL_REFERENCE; +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_Binder.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_Binder.cpp new file mode 100644 index 00000000..488a22e7 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_Binder.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + +// no code generated for this class diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_ConstructorInfo.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_ConstructorInfo.cpp new file mode 100644 index 00000000..3c05abc9 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_ConstructorInfo.cpp @@ -0,0 +1,45 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_Reflection_ConstructorInfo::GetCustomAttributes___SZARRAY_OBJECT__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Reflection_ConstructorInfo::Invoke___OBJECT__SZARRAY_OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* thisRef = stack.ThisRef().Dereference(); + CLR_RT_MethodDef_Instance md; + CLR_RT_HeapBlock_Array* pArray = stack.Arg1().DereferenceArray(); + CLR_RT_HeapBlock* args = NULL; + int numArgs = 0; + + if(md.InitializeFromIndex( thisRef->ReflectionDataConst().m_data.m_method ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_NULL_REFERENCE); + + if(stack.m_customState == 0) + { + stack.m_customState = 1; + + if(pArray) + { + args = (CLR_RT_HeapBlock*)pArray->GetFirstElement(); + numArgs = pArray->m_numOfElements; + } + + NANOCLR_CHECK_HRESULT(stack.MakeCall( md, NULL, args, numArgs )); + } + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_FieldInfo.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_FieldInfo.cpp new file mode 100644 index 00000000..c6a2a0d2 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_FieldInfo.cpp @@ -0,0 +1,206 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_Reflection_FieldInfo::SetValue___VOID__OBJECT__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_FieldDef_Instance instFD; + CLR_RT_TypeDef_Instance instTD; + CLR_RT_TypeDescriptor instTDescObj; + CLR_RT_TypeDef_Instance instTDField; + const CLR_RECORD_FIELDDEF* fd; + CLR_RT_HeapBlock* obj; + bool fValueType; + CLR_RT_HeapBlock& srcVal = stack.Arg2(); + CLR_RT_HeapBlock val; val.Assign( srcVal ); + CLR_RT_ProtectFromGC gc( val ); + + + NANOCLR_CHECK_HRESULT(Library_corlib_native_System_Reflection_FieldInfo::Initialize( stack, instFD, instTD, obj )); + + fd = instFD.m_target; + + if(fd->flags & CLR_RECORD_FIELDDEF::FD_NoReflection) // don't allow reflection for fields with NoReflection attribute + { + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + } + + NANOCLR_CHECK_HRESULT(instTDescObj.InitializeFromFieldDefinition(instFD)); + + // make sure the right side object is of the same type as the left side + if(NULL != val.Dereference() && !CLR_RT_ExecutionEngine::IsInstanceOf(val, instTDescObj.m_handlerCls)) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + fValueType = obj->IsAValueType(); + if(fValueType || (c_CLR_RT_DataTypeLookup[ obj->DataType() ].m_flags & CLR_RT_DataTypeLookup::c_OptimizedValueType)) + { + if(val.Dereference() == NULL || !val.Dereference()->IsBoxed()) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + if(fValueType) + { + _ASSERTE(NULL != obj->Dereference()); + if(NULL == obj->Dereference()) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + instTDField.InitializeFromIndex( obj->Dereference()->ObjectCls() ); + } + else + { + instTDField.InitializeFromIndex( *c_CLR_RT_DataTypeLookup[ obj->DataType() ].m_cls ); + } + + NANOCLR_CHECK_HRESULT(val.PerformUnboxing( instTDField )); + } + else + { +#if defined(NANOCLR_APPDOMAINS) + CLR_RT_HeapBlock& srcObj = stack.Arg1(); + + if(srcObj.IsTransparentProxy()) + { + _ASSERTE(srcObj.DataType() == DATATYPE_OBJECT); + _ASSERTE(srcObj.Dereference() != NULL && srcObj.Dereference()->DataType() == DATATYPE_TRANSPARENT_PROXY); + + NANOCLR_CHECK_HRESULT(srcObj.Dereference()->TransparentProxyValidate()); + NANOCLR_CHECK_HRESULT(srcObj.Dereference()->TransparentProxyAppDomain()->MarshalObject( val, val )); + } +#endif + } + + switch(obj->DataType()) + { + case DATATYPE_DATETIME: // Special case. + case DATATYPE_TIMESPAN: // Special case. + obj->NumericByRef().s8 = val.NumericByRefConst().s8; + break; + + default: + obj->Assign( val ); + break; + } + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT Library_corlib_native_System_Reflection_FieldInfo::Initialize( CLR_RT_StackFrame& stack, CLR_RT_FieldDef_Instance& instFD, CLR_RT_TypeDef_Instance& instTD, CLR_RT_HeapBlock*& obj ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + CLR_RT_HeapBlock* hbField = stack.Arg0().Dereference(); + + if(CLR_RT_ReflectionDef_Index::Convert( *hbField, instFD ) == false || + instTD.InitializeFromField ( instFD ) == false ) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + if(instFD.m_target->flags & CLR_RECORD_FIELDDEF::FD_Static) + { + obj = CLR_RT_ExecutionEngine::AccessStaticField( instFD ); + + if(obj == NULL) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + else + { + NANOCLR_CHECK_HRESULT(stack.Arg1().EnsureObjectReference( obj )); + + if(CLR_RT_ExecutionEngine::IsInstanceOf( *obj, instTD ) == false) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + obj = &obj[ instFD.CrossReference().m_offset ]; + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Reflection_FieldInfo::GetCustomAttributes___SZARRAY_OBJECT__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* callerField; + CLR_RT_HeapBlock* returnArray = NULL; + CLR_RT_FieldDef_Instance fieldDefinition; + int count = 0; + + // put the return array on the stack + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + + // get the caller field + callerField = stack.Arg0().Dereference(); + + NANOCLR_CHECK_HRESULT(Library_corlib_native_System_Reflection_RuntimeFieldInfo::GetFieldDescriptor( stack, *callerField, fieldDefinition )); + + // setup attribute enumerator + CLR_RT_AttributeEnumerator attributeEnumerator; + attributeEnumerator.Initialize( fieldDefinition ); + + // 1st pass: count attributes + do + { + // move to the next attribute in the collection, if any + if(attributeEnumerator.Advance()) + { + count++; + } + else + { + // done sweeping attributes + + // create the result array + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( top, count, g_CLR_RT_WellKnownTypes.m_TypeStatic )); + + // use this to skip the 2nd pass if no attribute was found + if (count == 0) break; + + // get the pointer to the first element + returnArray = (CLR_RT_HeapBlock*)top.DereferenceArray()->GetFirstElement(); + + // reset attribute enumerator + attributeEnumerator.Initialize( fieldDefinition ); + + break; + } + } + while(true); + + // 2nd pass: fill the array with the attributes types, if any + while(count > 0) + { + // move to the next attribute in the collection, if any + if(attributeEnumerator.Advance()) + { + CLR_RT_TypeDef_Instance instanceTypeDef; + CLR_RT_HeapBlock* hbObj; + + // get the type def for the current attribute + attributeEnumerator.GetCurrent(&instanceTypeDef); + + CLR_RT_TypeDef_Index attributeType; + attributeType.Set(instanceTypeDef.Assembly(), instanceTypeDef.Type()); + + // create a new object for the attribute type and put it on the return array + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*returnArray, g_CLR_RT_WellKnownTypes.m_TypeStatic)); + hbObj = returnArray->Dereference(); + // make sure the reflection is pointing to the attribute type + hbObj->SetReflection( attributeType ); + + returnArray++; + count--; + } + else + { + // no more attributes + break; + } + } + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_MemberInfo.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_MemberInfo.cpp new file mode 100644 index 00000000..488a22e7 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_MemberInfo.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + +// no code generated for this class diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_MethodBase.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_MethodBase.cpp new file mode 100644 index 00000000..a77af234 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_MethodBase.cpp @@ -0,0 +1,184 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + + + +HRESULT Library_corlib_native_System_Reflection_MethodBase::get_Name___STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_MethodDef_Instance md; + CLR_RT_HeapBlock* hbMeth = stack.Arg0().Dereference(); + + NANOCLR_CHECK_HRESULT(GetMethodDescriptor( stack, *hbMeth, md )); + + NANOCLR_SET_AND_LEAVE(CLR_RT_HeapBlock_String::CreateInstance( stack.PushValue(), md.m_target->name, md.m_assm )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Reflection_MethodBase::get_DeclaringType___SystemType( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_MethodDef_Instance md; + CLR_RT_TypeDef_Instance cls; + CLR_RT_HeapBlock* hbMeth = stack.Arg0().Dereference(); + + NANOCLR_CHECK_HRESULT(GetMethodDescriptor( stack, *hbMeth, md )); + + if(cls.InitializeFromMethod( md ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + { + CLR_RT_HeapBlock& top = stack.PushValue(); + CLR_RT_HeapBlock* hbObj; + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_TypeStatic)); + + hbObj = top.Dereference(); + hbObj->SetReflection( cls ); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Reflection_MethodBase::get_IsPublic___BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(CheckFlags( stack, CLR_RECORD_METHODDEF::MD_Scope_Mask, CLR_RECORD_METHODDEF::MD_Scope_Public )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Reflection_MethodBase::get_IsStatic___BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(CheckFlags( stack, CLR_RECORD_METHODDEF::MD_Static, CLR_RECORD_METHODDEF::MD_Static )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Reflection_MethodBase::get_IsFinal___BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(CheckFlags( stack, CLR_RECORD_METHODDEF::MD_Final, CLR_RECORD_METHODDEF::MD_Final )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Reflection_MethodBase::get_IsVirtual___BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(CheckFlags( stack, CLR_RECORD_METHODDEF::MD_Virtual, CLR_RECORD_METHODDEF::MD_Virtual )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Reflection_MethodBase::get_IsAbstract___BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(CheckFlags( stack, CLR_RECORD_METHODDEF::MD_Abstract, CLR_RECORD_METHODDEF::MD_Abstract )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Reflection_MethodBase::Invoke___OBJECT__OBJECT__SZARRAY_OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock& obj = stack.Arg1(); + CLR_RT_MethodDef_Instance md; + const CLR_RECORD_METHODDEF* mdR; + CLR_RT_HeapBlock_Array* pArray = stack.Arg2().DereferenceArray(); + CLR_RT_HeapBlock* args = NULL; + int numArgs = 0; + CLR_RT_HeapBlock* hbMeth = stack.Arg0().Dereference(); + + NANOCLR_CHECK_HRESULT(GetMethodDescriptor( stack, *hbMeth, md )); + + mdR = md.m_target; + + if(stack.m_customState == 0) + { + stack.m_customState = 1; + + if(pArray) + { + args = (CLR_RT_HeapBlock*)pArray->GetFirstElement(); + numArgs = pArray->m_numOfElements; + } + + NANOCLR_CHECK_HRESULT(stack.MakeCall( md, &obj, args, numArgs )); + } + else + { + if(mdR->retVal != DATATYPE_VOID) + { + if(mdR->retVal < DATATYPE_I4) + { + stack.TopValue().ChangeDataType( mdR->retVal ); + } + + NANOCLR_CHECK_HRESULT(stack.TopValue().PerformBoxingIfNeeded()); + } + else + { + stack.SetResult_Object( NULL ); + } + } + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT Library_corlib_native_System_Reflection_MethodBase::GetMethodDescriptor( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock& arg, CLR_RT_MethodDef_Instance& inst ) +{ + (void)stack; + + NATIVE_PROFILE_CLR_CORE(); + return CLR_RT_ReflectionDef_Index::Convert( arg, inst ) ? S_OK : CLR_E_NULL_REFERENCE; +} + +HRESULT Library_corlib_native_System_Reflection_MethodBase::CheckFlags( CLR_RT_StackFrame& stack, CLR_UINT32 mask, CLR_UINT32 flag ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_MethodDef_Instance md; + bool fRes; + CLR_RT_HeapBlock* hbMeth = stack.Arg0().Dereference(); + + NANOCLR_CHECK_HRESULT(GetMethodDescriptor( stack, *hbMeth, md )); + + if((md.m_target->flags & mask) == flag) + { + fRes = true; + } + else + { + fRes = false; + } + + stack.SetResult_Boolean( fRes ); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_PropertyInfo.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_PropertyInfo.cpp new file mode 100644 index 00000000..8c58f62a --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_PropertyInfo.cpp @@ -0,0 +1,27 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_Reflection_PropertyInfo::GetValue___OBJECT__OBJECT__SZARRAY_OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Reflection_PropertyInfo::SetValue___VOID__OBJECT__OBJECT__SZARRAY_OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_RuntimeFieldInfo.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_RuntimeFieldInfo.cpp new file mode 100644 index 00000000..a47a8cf1 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_RuntimeFieldInfo.cpp @@ -0,0 +1,129 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_Reflection_RuntimeFieldInfo::get_Name___STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + CLR_RT_HeapBlock* hbField = stack.Arg0().Dereference(); + + CLR_RT_FieldDef_Instance fd; if(GetFieldDescriptor( stack, *hbField, fd ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_NULL_REFERENCE); + + NANOCLR_SET_AND_LEAVE(CLR_RT_HeapBlock_String::CreateInstance( stack.PushValue(), fd.m_target->name, fd.m_assm )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Reflection_RuntimeFieldInfo::get_DeclaringType___SystemType( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_FieldDef_Instance fd; + CLR_RT_TypeDef_Instance cls; + CLR_RT_HeapBlock* hbField = stack.Arg0().Dereference(); + + if(GetFieldDescriptor( stack, *hbField, fd ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_NULL_REFERENCE); + + if(cls.InitializeFromField( fd ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + { + CLR_RT_HeapBlock& top = stack.PushValue(); + CLR_RT_HeapBlock* hbObj; + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_TypeStatic)); + + hbObj = top.Dereference(); + hbObj->SetReflection( cls ); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Reflection_RuntimeFieldInfo::get_FieldType___SystemType( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_TypeDescriptor desc; + CLR_RT_FieldDef_Instance fd; + CLR_RT_HeapBlock* hbField = stack.Arg0().Dereference(); + + if(GetFieldDescriptor( stack, *hbField, fd ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_NULL_REFERENCE); + + NANOCLR_CHECK_HRESULT(desc.InitializeFromFieldDefinition( fd )); + + { + CLR_RT_HeapBlock& top = stack.PushValue(); + CLR_RT_HeapBlock* hbObj; + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_TypeStatic)); + hbObj = top.Dereference(); + hbObj->SetReflection( desc.m_handlerCls ); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Reflection_RuntimeFieldInfo::GetValue___OBJECT__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_FieldDef_Instance instFD; + CLR_RT_TypeDef_Instance instTD; + const CLR_RECORD_FIELDDEF* fd; + CLR_RT_HeapBlock* obj; + CLR_RT_HeapBlock dst; + + NANOCLR_CHECK_HRESULT(Library_corlib_native_System_Reflection_FieldInfo::Initialize( stack, instFD, instTD, obj )); + + fd = instFD.m_target; + if(fd->flags & CLR_RECORD_FIELDDEF::FD_NoReflection) // don't allow reflection for fields with NoReflection attribute + { + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + } + + { + dst.Assign( *obj ); + +#if defined(NANOCLR_APPDOMAINS) + CLR_RT_HeapBlock* argObj = &stack.Arg1(); + + //Marshal if necessary. + if(argObj->IsTransparentProxy()) + { + _ASSERTE(argObj->DataType() == DATATYPE_OBJECT); + + argObj = argObj->Dereference(); + + _ASSERTE(argObj != NULL && argObj->DataType() == DATATYPE_TRANSPARENT_PROXY); + + NANOCLR_CHECK_HRESULT(argObj->TransparentProxyValidate()); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.GetCurrentAppDomain()->MarshalObject( *obj, dst, argObj->TransparentProxyAppDomain() )); + } +#endif + + CLR_RT_HeapBlock& res = stack.PushValueAndAssign( dst ); + + NANOCLR_CHECK_HRESULT(res.PerformBoxingIfNeeded()); + } + + NANOCLR_NOCLEANUP(); +} + +//--// + +bool Library_corlib_native_System_Reflection_RuntimeFieldInfo::GetFieldDescriptor( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock& arg, CLR_RT_FieldDef_Instance& inst ) +{ + (void)stack; + + NATIVE_PROFILE_CLR_CORE(); + return CLR_RT_ReflectionDef_Index::Convert( arg, inst ); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_RuntimeMethodInfo.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_RuntimeMethodInfo.cpp new file mode 100644 index 00000000..1a0e6176 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Reflection_RuntimeMethodInfo.cpp @@ -0,0 +1,126 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_Reflection_RuntimeMethodInfo::get_ReturnType___SystemType( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_MethodDef_Instance md; + CLR_RT_SignatureParser parser; + CLR_RT_TypeDescriptor desc; + CLR_RT_HeapBlock* hbMeth = stack.Arg0().Dereference(); + + NANOCLR_CHECK_HRESULT(Library_corlib_native_System_Reflection_MethodBase::GetMethodDescriptor( stack, *hbMeth, md )); + + parser.Initialize_MethodSignature( md.m_assm, md.m_target ); + + NANOCLR_CHECK_HRESULT(desc.InitializeFromSignatureParser( parser )); + + { + CLR_RT_HeapBlock& top = stack.PushValue(); + CLR_RT_HeapBlock* hbObj; + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_TypeStatic)); + hbObj = top.Dereference(); + hbObj->SetReflection( desc.m_reflex ); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Reflection_RuntimeMethodInfo::GetCustomAttributes___SZARRAY_OBJECT__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* returnArray = NULL; + CLR_RT_MethodDef_Instance methodDefinition; + CLR_RT_SignatureParser signatureParser; + CLR_RT_TypeDescriptor desc; + CLR_RT_HeapBlock* callerMethod; + int count = 0; + + // put the return array on the stack + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + + // get the caller method + callerMethod = stack.Arg0().Dereference(); + + NANOCLR_CHECK_HRESULT(Library_corlib_native_System_Reflection_MethodBase::GetMethodDescriptor( stack, *callerMethod, methodDefinition )); + + signatureParser.Initialize_MethodSignature( methodDefinition.m_assm, methodDefinition.m_target ); + + NANOCLR_CHECK_HRESULT(desc.InitializeFromSignatureParser( signatureParser )); + + // setup attribute enumerator + CLR_RT_AttributeEnumerator attributeEnumerator; + attributeEnumerator.Initialize( methodDefinition ); + + // 1st pass: count attributes + do + { + // move to the next attribute in the collection, if any + if(attributeEnumerator.Advance()) + { + count++; + } + else + { + // done sweeping attributes + + // create the result array + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( top, count, g_CLR_RT_WellKnownTypes.m_TypeStatic )); + + // use this to skip the 2nd pass if no attribute was found + if (count == 0) break; + + // get the pointer to the first element + returnArray = (CLR_RT_HeapBlock*)top.DereferenceArray()->GetFirstElement(); + + // reset attribute enumerator + attributeEnumerator.Initialize( methodDefinition ); + + break; + } + } + while(true); + + // 2nd pass: fill the array with the attributes types, if any + while(count > 0) + { + // move to the next attribute in the collection, if any + if(attributeEnumerator.Advance()) + { + CLR_RT_TypeDef_Instance instanceTypeDef; + CLR_RT_HeapBlock* hbObj; + + // get the type def for the current attribute + attributeEnumerator.GetCurrent(&instanceTypeDef); + + CLR_RT_TypeDef_Index attributeType; + attributeType.Set(instanceTypeDef.Assembly(), instanceTypeDef.Type()); + + // create a new object for the attribute type and put it on the return array + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*returnArray, g_CLR_RT_WellKnownTypes.m_TypeStatic)); + hbObj = returnArray->Dereference(); + // make sure the reflection is pointing to the attribute type + hbObj->SetReflection( attributeType ); + + returnArray++; + count--; + } + else + { + // no more attributes + break; + } + } + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_RuntimeType.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_RuntimeType.cpp new file mode 100644 index 00000000..02fa4bad --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_RuntimeType.cpp @@ -0,0 +1,325 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_RuntimeType::get_Assembly___SystemReflectionAssembly( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Instance td; + CLR_RT_HeapBlock* hbType = stack.Arg0().Dereference(); + + NANOCLR_CHECK_HRESULT(GetTypeDescriptor( *hbType, td, NULL )); + + { + CLR_RT_Assembly_Index idx; idx.Set( td.Assembly() ); + CLR_RT_HeapBlock& top = stack.PushValue(); + CLR_RT_HeapBlock* hbObj; + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_Assembly)); + hbObj = top.Dereference(); + hbObj->SetReflection( idx ); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_RuntimeType::get_Name___STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + CLR_RT_HeapBlock* hbType = stack.Arg0().Dereference(); + + NANOCLR_CHECK_HRESULT(GetName( *hbType, false, stack.PushValueAndClear() )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_RuntimeType::get_FullName___STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + CLR_RT_HeapBlock* hbType = stack.Arg0().Dereference(); + + NANOCLR_CHECK_HRESULT(GetName( *hbType, true, stack.PushValueAndClear() )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_RuntimeType::get_BaseType___SystemType( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Instance td; + CLR_UINT32 levels; + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + CLR_RT_HeapBlock* hbType = stack.Arg0().Dereference(); + + NANOCLR_CHECK_HRESULT(GetTypeDescriptor( *hbType, td, &levels )); + + if(levels > 0) + { + CLR_RT_HeapBlock* hbObj; + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_TypeStatic)); + hbObj = top.Dereference(); + hbObj->SetReflection( g_CLR_RT_WellKnownTypes.m_Array ); + } + else if(td.SwitchToParent()) + { + CLR_RT_HeapBlock* hbObj; + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_TypeStatic)); + hbObj = top.Dereference(); + hbObj->SetReflection( td ); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_RuntimeType::GetMethods___SZARRAY_SystemReflectionMethodInfo__SystemReflectionBindingFlags( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + return Library_corlib_native_System_Type::GetMethods( stack, NULL, stack.Arg1().NumericByRef().s4, NULL, 0, true ); +} + +HRESULT Library_corlib_native_System_RuntimeType::GetField___SystemReflectionFieldInfo__STRING__SystemReflectionBindingFlags( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + return Library_corlib_native_System_Type::GetFields( stack, stack.Arg1().RecoverString(), stack.Arg2().NumericByRef().s4, false ); +} + +HRESULT Library_corlib_native_System_RuntimeType::GetFields___SZARRAY_SystemReflectionFieldInfo__SystemReflectionBindingFlags( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + return Library_corlib_native_System_Type::GetFields( stack, NULL, stack.Arg1().NumericByRef().s4, true ); +} + +HRESULT Library_corlib_native_System_RuntimeType::GetInterfaces___SZARRAY_SystemType( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Instance td; + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + CLR_RT_HeapBlock* ptr = NULL; + CLR_RT_HeapBlock* hbType = stack.Arg0().Dereference(); + int count = 0; + + // 2-pass algorithm. 1. count the interfaces; 2. store the interfaces in an array + for (int pass = 1; pass <= 2; pass++) + { + NANOCLR_CHECK_HRESULT(GetTypeDescriptor( *hbType, td )); + + do + { + // Scan the list of interfaces. + CLR_RT_SignatureParser parser; parser.Initialize_Interfaces( td.m_assm, td.m_target ); + CLR_RT_SignatureParser::Element res; + + // 1. pass count + if (pass == 1) + { + count += parser.Available(); + } + else + { + // 2. pass fill the data into the array + while(parser.Available() > 0) + { + CLR_RT_HeapBlock* hbObj; + + NANOCLR_CHECK_HRESULT(parser.Advance( res )); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*ptr, g_CLR_RT_WellKnownTypes.m_TypeStatic)); + hbObj = ptr->Dereference(); + hbObj->SetReflection( res.m_cls ); + + ptr++; + count--; + } + + // array full? => Done + if (count == 0) + { + break; + } + } + } + while(td.SwitchToParent()); + + if (pass == 1) + { + // create the result array + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( top, count, g_CLR_RT_WellKnownTypes.m_TypeStatic )); + // don't need the second pass if nothing found + if (count == 0) break; + // get the pointer to the first element + ptr = (CLR_RT_HeapBlock*)top.DereferenceArray()->GetFirstElement(); + } + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_RuntimeType::GetElementType___SystemType( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_TypeDescriptor desc; + CLR_RT_TypeDescriptor descSub; + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + CLR_RT_HeapBlock* hbType = stack.Arg0().Dereference(); + + NANOCLR_CHECK_HRESULT(desc.InitializeFromReflection( hbType->ReflectionDataConst() )); + + if(desc.GetElementType( descSub )) + { + CLR_RT_HeapBlock* hbObj; + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_TypeStatic)); + hbObj = top.Dereference(); + hbObj->SetReflection( descSub.m_reflex ); + } + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT Library_corlib_native_System_RuntimeType::GetTypeDescriptor( CLR_RT_HeapBlock& arg, CLR_RT_TypeDef_Instance& inst, CLR_UINT32* levels ) +{ + NATIVE_PROFILE_CLR_CORE(); + return CLR_RT_ReflectionDef_Index::Convert( arg, inst, levels ) ? S_OK : CLR_E_NULL_REFERENCE; +} + +HRESULT Library_corlib_native_System_RuntimeType::GetTypeDescriptor( CLR_RT_HeapBlock& arg, CLR_RT_TypeDef_Instance& inst ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_UINT32 levels; + + NANOCLR_CHECK_HRESULT(GetTypeDescriptor( arg, inst, &levels )); + + if(levels > 0) + { + inst.InitializeFromIndex( g_CLR_RT_WellKnownTypes.m_Array ); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_RuntimeType::GetName( CLR_RT_HeapBlock& arg, bool fFullName, CLR_RT_HeapBlock& res ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Instance td; + CLR_UINT32 levels; + char rgBuffer[ 256 ]; + char* szBuffer; + size_t iBuffer; + + NANOCLR_CHECK_HRESULT(GetTypeDescriptor( arg, td, &levels )); + + szBuffer = rgBuffer; + iBuffer = MAXSTRLEN(rgBuffer); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_TypeSystem.BuildTypeName( td, szBuffer, iBuffer, fFullName ? CLR_RT_TypeSystem::TYPENAME_FLAGS_FULL : 0, levels )); + + NANOCLR_SET_AND_LEAVE(CLR_RT_HeapBlock_String::CreateInstance( res, rgBuffer )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_RuntimeType::GetCustomAttributes___SZARRAY_OBJECT__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* returnArray = NULL; + CLR_RT_HeapBlock* callerType = NULL; + CLR_RT_TypeDef_Instance instanceTypeDef; + CLR_RT_TypeDef_Instance typeDefinition; + CLR_RT_HeapBlock* hbObj; + int count = 0; + + // put the return array on the stack + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + + // get the caller type + callerType = stack.Arg0().Dereference(); + + NANOCLR_CHECK_HRESULT(GetTypeDescriptor( *callerType, typeDefinition )); + + // setup attribute enumerator + CLR_RT_AttributeEnumerator attributeEnumerator; + attributeEnumerator.Initialize( typeDefinition ); + + // 1st pass: count attributes + do + { + // move to the next attribute in the collection, if any + if(attributeEnumerator.Advance()) + { + count++; + } + else + { + // done sweeping attributes + + // create the result array + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( top, count, g_CLR_RT_WellKnownTypes.m_TypeStatic )); + + // use this to skip the 2nd pass if no attribute was found + if (count == 0) break; + + // get the pointer to the first element + returnArray = (CLR_RT_HeapBlock*)top.DereferenceArray()->GetFirstElement(); + + // reset attribute enumerator + attributeEnumerator.Initialize( typeDefinition ); + + break; + } + } + while(true); + + // 2nd pass: fill the array with the attributes types, if any + while(count > 0) + { + // move to the next attribute in the collection, if any + if(attributeEnumerator.Advance()) + { + // get the type def for the current attribute + attributeEnumerator.GetCurrent(&instanceTypeDef); + + CLR_RT_TypeDef_Index attributeType; + attributeType.Set(instanceTypeDef.Assembly(), instanceTypeDef.Type()); + + // create a new object for the attribute type and put it on the return array + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*returnArray, g_CLR_RT_WellKnownTypes.m_TypeStatic)); + hbObj = returnArray->Dereference(); + // make sure the reflection is pointing to the attribute type + hbObj->SetReflection( attributeType ); + + returnArray++; + count--; + } + else + { + // no more attributes + break; + } + } + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Runtime_CompilerServices_RuntimeHelpers.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Runtime_CompilerServices_RuntimeHelpers.cpp new file mode 100644 index 00000000..69f9ac19 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Runtime_CompilerServices_RuntimeHelpers.cpp @@ -0,0 +1,217 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_Runtime_CompilerServices_RuntimeHelpers::InitializeArray___STATIC__VOID__SystemArray__SystemRuntimeFieldHandle( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_FieldDef_Instance inst; + CLR_RT_HeapBlock_Array* array = stack.Arg0().DereferenceArray(); FAULT_ON_NULL(array); + + if(array->m_fReference) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + if(CLR_RT_ReflectionDef_Index::Convert( stack.Arg1(), inst ) == false) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + if((inst.m_target->flags & CLR_RECORD_FIELDDEF::FD_HasFieldRVA) == 0 || inst.m_target->defaultValue == CLR_EmptyIndex) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + { + CLR_PMETADATA ptrSrc = inst.m_assm->GetSignature( inst.m_target->defaultValue ); + CLR_UINT32 lenSrc; NANOCLR_READ_UNALIGNED_UINT16( lenSrc, ptrSrc ); + + CLR_UINT8* ptrDst = array->GetFirstElement(); + CLR_UINT32 lenDst = array->m_numOfElements; + CLR_UINT32 sizeDst = array->m_sizeOfElement; + + lenSrc /= sizeDst; if(lenSrc > lenDst) lenSrc = lenDst; +#if !defined(NETMF_TARGET_BIG_ENDIAN) + memcpy( ptrDst, ptrSrc, lenSrc * sizeDst ); + +#if defined(NANOCLR_EMULATED_FLOATINGPOINT) + switch(array->m_typeOfElement) + { + case DATATYPE_R4: + { + CLR_RT_HeapBlock tmp; + CLR_UINT32* ptr = (CLR_UINT32*)ptrDst; + + for(;lenSrc; lenSrc--, ptr++) + { + NANOCLR_CHECK_HRESULT(tmp.SetFloatIEEE754( *ptr )); + + *ptr = tmp.NumericByRef().u4; + } + } + break; + + case DATATYPE_R8: + { + CLR_RT_HeapBlock tmp; + CLR_UINT64* ptr = (CLR_UINT64*)ptrDst; + + for(;lenSrc; lenSrc--, ptr++) + { + NANOCLR_CHECK_HRESULT(tmp.SetDoubleIEEE754( *ptr )); + + *ptr = tmp.NumericByRef().u8; + } + } + break; + } +#endif + +#else + // FIXME GJS - WOuld it be possible to move the endian swap to pe compile time to get rid of this? + // If this is a numeric dataype of datatype size other than a byte then byteswap the entries + // Unaligned reads handle endianess, just use them. FIXME GJS - this could be the subject of much optimization + switch(array->m_typeOfElement) + { + case DATATYPE_CHAR: + case DATATYPE_I2: + case DATATYPE_U2: + { + CLR_UINT32 count=0; + CLR_UINT16 d; + CLR_UINT16 *p16 = (CLR_UINT16*)ptrDst; + while( count < lenDst ) + { + NANOCLR_READ_UNALIGNED_UINT16( d, ptrSrc ); + *p16++ = SwapEndian(d); + count++; + } + } + break; + + case DATATYPE_I4: + case DATATYPE_U4: + case DATATYPE_R4: + { + CLR_UINT32 count=0; + CLR_UINT32 d; + CLR_UINT32 *p32 = (CLR_UINT32*)ptrDst; + while( count < lenDst ) + { + NANOCLR_READ_UNALIGNED_UINT32( d, ptrSrc ); + *p32++ = SwapEndian(d); + count++; + } + } + break; + case DATATYPE_I8: + case DATATYPE_U8: + case DATATYPE_R8: + { + CLR_UINT32 count=0; + CLR_UINT64 d; + CLR_UINT64 *p64 = (CLR_UINT64*)ptrDst; + + while( count < lenDst ) + { + NANOCLR_READ_UNALIGNED_UINT64( d, ptrSrc ); + *p64++ = SwapEndian( d ); + count++; + } + } + break; + default: + memcpy( ptrDst, ptrSrc, lenSrc * sizeDst ); + break; + } + + + +#if defined(NANOCLR_EMULATED_FLOATINGPOINT) + switch(array->m_typeOfElement) + { + case DATATYPE_R4: + { + CLR_RT_HeapBlock tmp; + CLR_UINT32* ptr = (CLR_UINT32*)ptrDst; + + for(;lenSrc; lenSrc--, ptr++) + { + NANOCLR_CHECK_HRESULT(tmp.SetFloatIEEE754( *ptr )); + + *ptr = tmp.NumericByRef().u4; + } + } + break; + + case DATATYPE_R8: + { + CLR_RT_HeapBlock tmp; + CLR_UINT64* ptr = (CLR_UINT64*)ptrDst; + + for(;lenSrc; lenSrc--, ptr++) + { + NANOCLR_CHECK_HRESULT(tmp.SetDoubleIEEE754( *ptr )); + + *ptr = tmp.NumericByRef().u8; + } + } + break; + } +#endif +#endif //NETMF_TARGET_BIG_ENDIAN + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Runtime_CompilerServices_RuntimeHelpers::GetObjectValue___STATIC__OBJECT__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + CLR_RT_HeapBlock* src = stack.Arg0().Dereference(); + + if(src && src->DataType() == DATATYPE_VALUETYPE && src->IsBoxed()) + { + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.CloneObject( top, *src )); + } + else + { + top.SetObjectReference( src ); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Runtime_CompilerServices_RuntimeHelpers::RunClassConstructor___STATIC__VOID__SystemRuntimeTypeHandle( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Runtime_CompilerServices_RuntimeHelpers::get_OffsetToStringData___STATIC__I4( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Runtime_Remoting_RemotingServices.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Runtime_Remoting_RemotingServices.cpp new file mode 100644 index 00000000..be4d82a6 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Runtime_Remoting_RemotingServices.cpp @@ -0,0 +1,24 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_Runtime_Remoting_RemotingServices::IsTransparentProxy___STATIC__BOOLEAN__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + bool fProxy = false; + + #if defined(NANOCLR_APPDOMAINS) + CLR_RT_HeapBlock& obj = stack.Arg0(); + fProxy = obj.IsTransparentProxy(); + #endif + + stack.SetResult_Boolean( fProxy ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_String.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_String.cpp new file mode 100644 index 00000000..2a9d4e27 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_String.cpp @@ -0,0 +1,1182 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +static const CLR_UINT16 c_WhiteSpaces[] = +{ + 0x0009, + 0x000A, + 0x000B, + 0x000C, + 0x000D, + 0x0020, + 0x00A0, + 0x2000, + 0x2001, + 0x2002, + 0x2003, + 0x2004, + 0x2005, + 0x2006, + 0x2007, + 0x2008, + 0x2009, + 0x200A, + 0x200B, + 0x3000, + 0xFEFF, +}; + +//--// + +HRESULT Library_corlib_native_System_String::CompareTo___I4__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(Library_corlib_native_System_String::CompareTo___I4__STRING( stack )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::get_Chars___CHAR__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + const char* szText; + CLR_RT_UnicodeHelper uh; + CLR_UINT16 buf[ 3 ]; + int len; + int index; + + szText = stack.Arg0().RecoverString(); FAULT_ON_NULL(szText); + + uh.SetInputUTF8( szText ); + + len = uh.CountNumberOfCharacters() ; if(len < 0 ) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + index = stack.Arg1().NumericByRef().s4; if(index < 0 || index >= len) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + + uh.m_outputUTF16 = buf; + uh.m_outputUTF16_size = MAXSTRLEN(buf); + + // + // First move to the character, then read it. + // + uh.ConvertFromUTF8( index, true ); + uh.ConvertFromUTF8( 1 , false ); + + stack.SetResult( buf[ 0 ], DATATYPE_CHAR ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::ToCharArray___SZARRAY_CHAR( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(ToCharArray( stack, 0, -1 )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::ToCharArray___SZARRAY_CHAR__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(ToCharArray( stack, stack.Arg1().NumericByRef().s4, stack.Arg2().NumericByRef().s4 )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::get_Length___I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + const char* szText = stack.Arg0().RecoverString(); FAULT_ON_NULL(szText); + + CLR_RT_UnicodeHelper uh; uh.SetInputUTF8( szText ); + + stack.SetResult_I4( uh.CountNumberOfCharacters() ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::Split___SZARRAY_STRING__SZARRAY_CHAR( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(Split( stack, stack.Arg1(), 0x7FFFFFFF )); /// Sending INT_MAX instead of -1. + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::Split___SZARRAY_STRING__SZARRAY_CHAR__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(Split( stack, stack.Arg1(), stack.Arg2().NumericByRef().s4 )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::Substring___STRING__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(Substring( stack, stack.Arg1().NumericByRef().s4, -1 )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::Substring___STRING__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_INT32 length = stack.Arg2().NumericByRef().s4; + + if(length < 0) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + + NANOCLR_SET_AND_LEAVE(Substring( stack, stack.Arg1().NumericByRef().s4, length )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::Trim___STRING__SZARRAY_CHAR( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(Trim( stack, stack.Arg1().DereferenceArray(), true, true )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::TrimStart___STRING__SZARRAY_CHAR( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(Trim( stack, stack.Arg1().DereferenceArray(), true, false )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::TrimEnd___STRING__SZARRAY_CHAR( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(Trim( stack, stack.Arg1().DereferenceArray(), false, true )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::_ctor___VOID__SZARRAY_CHAR__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(FromCharArray( stack, stack.Arg2().NumericByRef().s4, stack.Arg3().NumericByRef().s4 )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::_ctor___VOID__SZARRAY_CHAR( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(FromCharArray( stack, 0, -1 )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::_ctor___VOID__CHAR__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_UINT16 ch = stack.Arg1().NumericByRef().u2; + int len = stack.Arg2().NumericByRef().s4; if(len < 0) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + + { + CLR_RT_HeapBlock tmp; tmp.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc( tmp ); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( tmp, len, g_CLR_RT_WellKnownTypes.m_Char )); + + { + CLR_RT_HeapBlock_Array* tmpArray = tmp.DereferenceArray(); + CLR_UINT16* pTmp = (CLR_UINT16*)tmpArray->GetFirstElement(); + CLR_UINT16* p; + + p = pTmp; while(len--) *p++ = ch; + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( stack.Arg0(), pTmp, tmpArray->m_numOfElements )); + } + } + + NANOCLR_NOCLEANUP(); +} + + +HRESULT Library_corlib_native_System_String::CompareTo___I4__STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock& pThis = stack.Arg0(); // String references are special, they don't point to an object, they are the object. So use stack.Arg0() instead of stack.This() + CLR_RT_HeapBlock& pArg = stack.Arg1(); + + stack.SetResult_I4( CLR_RT_HeapBlock::Compare_Unsigned_Values( pThis, pArg ) ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_String::IndexOf___I4__CHAR( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(IndexOf( stack, c_IndexOf__SingleChar )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::IndexOf___I4__CHAR__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(IndexOf( stack, c_IndexOf__SingleChar | c_IndexOf__StartIndex )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::IndexOf___I4__CHAR__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(IndexOf( stack, c_IndexOf__SingleChar | c_IndexOf__StartIndex | c_IndexOf__Count )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::IndexOfAny___I4__SZARRAY_CHAR( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(IndexOf( stack, c_IndexOf__MultipleChars )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::IndexOfAny___I4__SZARRAY_CHAR__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(IndexOf( stack, c_IndexOf__MultipleChars | c_IndexOf__StartIndex )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::IndexOfAny___I4__SZARRAY_CHAR__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(IndexOf( stack, c_IndexOf__MultipleChars | c_IndexOf__StartIndex | c_IndexOf__Count )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::IndexOf___I4__STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(IndexOf( stack, c_IndexOf__String )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::IndexOf___I4__STRING__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(IndexOf( stack, c_IndexOf__String | c_IndexOf__StartIndex )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::IndexOf___I4__STRING__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(IndexOf( stack, c_IndexOf__String | c_IndexOf__StartIndex | c_IndexOf__Count )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::LastIndexOf___I4__CHAR( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(IndexOf( stack, c_IndexOf__SingleChar | c_IndexOf__Last )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::LastIndexOf___I4__CHAR__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(IndexOf( stack, c_IndexOf__SingleChar | c_IndexOf__Last | c_IndexOf__StartIndex )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::LastIndexOf___I4__CHAR__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(IndexOf( stack, c_IndexOf__SingleChar | c_IndexOf__Last | c_IndexOf__StartIndex | c_IndexOf__Count )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::LastIndexOfAny___I4__SZARRAY_CHAR( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(IndexOf( stack, c_IndexOf__MultipleChars | c_IndexOf__Last )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::LastIndexOfAny___I4__SZARRAY_CHAR__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(IndexOf( stack, c_IndexOf__MultipleChars | c_IndexOf__Last | c_IndexOf__StartIndex )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::LastIndexOfAny___I4__SZARRAY_CHAR__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(IndexOf( stack, c_IndexOf__MultipleChars | c_IndexOf__Last | c_IndexOf__StartIndex | c_IndexOf__Count )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::LastIndexOf___I4__STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(IndexOf( stack, c_IndexOf__String | c_IndexOf__Last )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::LastIndexOf___I4__STRING__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(IndexOf( stack, c_IndexOf__String | c_IndexOf__Last | c_IndexOf__StartIndex )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::LastIndexOf___I4__STRING__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(IndexOf( stack, c_IndexOf__String | c_IndexOf__Last | c_IndexOf__StartIndex | c_IndexOf__Count )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::ToLower___STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(ChangeCase( stack, false )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::ToUpper___STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(ChangeCase( stack, true )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::Trim___STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(Trim( stack, NULL, true, true )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::Equals___STATIC__BOOLEAN__STRING__STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + stack.SetResult_Boolean( CLR_RT_HeapBlock::Compare_Unsigned_Values( stack.Arg0(), stack.Arg1() ) == 0 ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_String::op_Equality___STATIC__BOOLEAN__STRING__STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(Library_corlib_native_System_String::Equals___STATIC__BOOLEAN__STRING__STRING( stack )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::op_Inequality___STATIC__BOOLEAN__STRING__STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_CHECK_HRESULT(Library_corlib_native_System_String::Equals___STATIC__BOOLEAN__STRING__STRING( stack )); + + stack.NegateResult(); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::Compare___STATIC__I4__STRING__STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + stack.SetResult_I4( CLR_RT_HeapBlock::Compare_Unsigned_Values( stack.Arg0(), stack.Arg1() ) ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_String::Concat___STATIC__STRING__STRING__STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(Concat( stack, &stack.Arg0(), 2 )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::Concat___STATIC__STRING__STRING__STRING__STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(Concat( stack, &stack.Arg0(), 3 )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::Concat___STATIC__STRING__STRING__STRING__STRING__STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(Concat( stack, &stack.Arg0(), 4 )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::Concat___STATIC__STRING__SZARRAY_STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* pArray = stack.Arg0().DereferenceArray(); FAULT_ON_NULL(pArray); + + NANOCLR_SET_AND_LEAVE(Concat( stack, (CLR_RT_HeapBlock*)pArray->GetFirstElement(), pArray->m_numOfElements )); + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT Library_corlib_native_System_String::FromCharArray( CLR_RT_StackFrame& stack, int startIndex, int length ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* array; + CLR_UINT32 len; + + array = stack.Arg1().DereferenceArray(); + if (!array || array->m_numOfElements == 0) + { + NANOCLR_SET_AND_LEAVE(CLR_RT_HeapBlock_String::CreateInstance(stack.Arg0(), "")); + } + else + { + len = array->m_numOfElements; + + if (length == -1) + length = len - startIndex; + + if (CLR_RT_HeapBlock_Array::CheckRange(startIndex, length, len) == false) + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + + NANOCLR_SET_AND_LEAVE(CLR_RT_HeapBlock_String::CreateInstance(stack.Arg0(), (CLR_UINT16*)array->GetElement(startIndex), length)); + } + + NANOCLR_NOCLEANUP(); +} + + +HRESULT Library_corlib_native_System_String::ToCharArray( CLR_RT_StackFrame& stack, int startIndex, int length ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* array; + + NANOCLR_SET_AND_LEAVE(ConvertToCharArray( stack, stack.PushValueAndClear(), array, startIndex, length )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::IndexOf( CLR_RT_StackFrame& stack, int mode ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + const char* szText; + int startIndex; + int count; + int pos; + const char* pString; + const CLR_UINT16* pChars; + int iChars = 0; + CLR_RT_UnicodeHelper inputIterator; + int inputLen; + int searchLen = 1; + + szText = stack.Arg0().RecoverString(); if(!szText) szText = ""; + pos = -1; + pString = NULL; + pChars = NULL; + + if(mode & c_IndexOf__SingleChar) + { + pChars = (CLR_UINT16*)&stack.Arg1().NumericByRefConst().u2; + iChars = 1; + } + else if(mode & c_IndexOf__MultipleChars) + { + CLR_RT_HeapBlock_Array* array = stack.Arg1().DereferenceArray(); FAULT_ON_NULL(array); + + pChars = (const CLR_UINT16*)array->GetFirstElement(); + iChars = array->m_numOfElements; + } + else if(mode & c_IndexOf__String) + { + pString = stack.Arg1().RecoverString(); FAULT_ON_NULL(pString); + // how long is the search string? + inputIterator.SetInputUTF8( pString ); + searchLen = inputIterator.CountNumberOfCharacters(); + } + + // calculate input string length + inputIterator.SetInputUTF8( szText ); + inputLen = inputIterator.CountNumberOfCharacters(); + + // calculate start index + if(mode & c_IndexOf__StartIndex) + { + startIndex = stack.Arg2().NumericByRefConst().s4; + } + else + { + // for mode LastIndex... we are searching backwards toward the start of the string + if(mode & c_IndexOf__Last) + { + startIndex = inputLen - 1; + } + else + { + startIndex = 0; + } + } + + // check the start index + if(startIndex < 0 || startIndex > inputLen) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + + // for mode LastIndex... with string we move the start index back by the search string length -1 + if((mode & c_IndexOf__String_Last) == c_IndexOf__String_Last) + { + startIndex -= searchLen - 1; + // check the start index; if not in range skip the search + if(startIndex < 0 || startIndex > inputLen) goto Exit; + } + + // calculate the iteration count + if(mode & c_IndexOf__Count) + { + // count form parameter + count = stack.Arg3().NumericByRefConst().s4; + } + else + { + // for mode LastIndex... we are searching from start index backwards toward the start of the string + if(mode & c_IndexOf__Last) + { + // backward until the start of string + // one more time than the startIndex because we should iterate until zero + count = startIndex + 1; + } + else + { + // forward until the end of string + count = inputLen - startIndex; + } + } + + // for mode with string we reduce the count by the search string length -1 + // if we search foreward + if((mode & c_IndexOf__String_Last) == c_IndexOf__String) + { + count -= searchLen - 1; + } + + // check the count + if(mode & c_IndexOf__Last) + { + // check for backward mode; no exception; just exit + if(count > startIndex + 1) goto Exit; + } + else + { + // check for forward mode + if(startIndex + count > inputLen) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + } + + // First move to the character, then read it. + if(inputIterator.ConvertFromUTF8( startIndex, true )) + { + // string mode? + if(pString) + { + // iterate thru all positions + while(count-- > 0) + { + CLR_RT_UnicodeHelper inputString; inputString.SetInputUTF8( (const char*)inputIterator.m_inputUTF8 ); + CLR_RT_UnicodeHelper searchString; searchString.SetInputUTF8( pString ); + bool finished = false; + + while(true) + { + CLR_UINT16 bufInput[ 3 ]; + CLR_UINT16 bufSearch[ 3 ]; + + inputString.m_outputUTF16 = bufInput; + inputString.m_outputUTF16_size = MAXSTRLEN(bufInput); + + searchString.m_outputUTF16 = bufSearch; + searchString.m_outputUTF16_size = MAXSTRLEN(bufSearch); + + // read next char from search string; if no more chars to read (false) + // then we are done and found the search string in the input string + if(searchString.ConvertFromUTF8( 1, false ) == false) + { + pos = startIndex; + finished = true; + break; + } + + // read the next char from the input string; if no more chars to read (false) + // we didn't found the search string in the input string; we abort the search now + if(inputString.ConvertFromUTF8( 1, false ) == false) + { + finished = true; + break; + } + + // does the char from input not match the char from the search string + if(bufInput[ 0 ] != bufSearch[ 0 ]) + { + // next iteration round but not finished + break; + } + } + + // finished (with or without a found) then break + if (finished) + { + break; + } + + // reading forward or backward + if(mode & c_IndexOf__Last) + { + startIndex--; + // move one chars backward + if(inputIterator.MoveBackwardInUTF8( szText, 1 ) == false) + { + break; + } + } + else + { + startIndex++; + // move to the next char + if(inputIterator.ConvertFromUTF8( 1, true ) == false) + { + break; + } + } + } + } + + // char mode? + if(pChars) + { + // iterate thru all positions + while(count-- > 0) + { + CLR_UINT16 buf[ 3 ]; + + inputIterator.m_outputUTF16 = buf; + inputIterator.m_outputUTF16_size = MAXSTRLEN(buf); + + // read the next char from the input string; if no more chars to read (false) + // we didn't found the search chars in the input string + if(inputIterator.ConvertFromUTF8( 1, false ) == false) + { + break; + } + + // test each search char if it's a match + for(int i=0; i break + if (pos != -1) + { + break; + } + + // for mode LastIndex... we are searching from start index backwards toward the start of the string + if(mode & c_IndexOf__Last) + { + // in backward mode + startIndex--; + // move two chars backward, because the current char is already read + if(inputIterator.MoveBackwardInUTF8( szText, 2 ) == false) + { + break; + } + } + else + { + // forward mode; simple advance the start index + startIndex++; + } + } + } + } + +Exit: + stack.SetResult_I4( pos ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::ChangeCase( CLR_RT_StackFrame& stack, bool fToUpper ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock refTmp; refTmp.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc( refTmp ); + CLR_RT_HeapBlock_Array* arrayTmp; + CLR_UINT16* ptr; + + NANOCLR_CHECK_HRESULT(ConvertToCharArray( stack, refTmp, arrayTmp, 0, -1 )); + + ptr = (CLR_UINT16*)arrayTmp->GetFirstElement(); + + for(CLR_UINT32 i=0; im_numOfElements; i++) + { + CLR_UINT16 c = *ptr; + + if(fToUpper) + { + if(c >= 'a' && c <= 'z') c += 'A' - 'a'; + } + else + { + if(c >= 'A' && c <= 'Z') c -= 'A' - 'a'; + } + + *ptr++ = c; + } + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( stack.PushValue(), (CLR_UINT16*)arrayTmp->GetFirstElement(), arrayTmp->m_numOfElements )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::Substring( CLR_RT_StackFrame& stack, int startIndex, int length ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock refTmp; refTmp.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc( refTmp ); + CLR_RT_HeapBlock_Array* arrayTmp; + + NANOCLR_CHECK_HRESULT(ConvertToCharArray( stack, refTmp, arrayTmp, 0, -1 )); + + if(startIndex < 0 || startIndex > (int)arrayTmp->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + + if(length == -1) + { + length = arrayTmp->m_numOfElements - startIndex; + } + else + { + if(length < 0 || (startIndex + length) > (int)arrayTmp->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + } + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( stack.PushValue(), (CLR_UINT16*)arrayTmp->GetElement( startIndex ), length )); + + NANOCLR_NOCLEANUP(); +} + + +HRESULT Library_corlib_native_System_String::Trim( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock_Array* arrayTrimChars, bool fStart, bool fEnd ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock refTmp; refTmp.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc( refTmp ); + CLR_RT_HeapBlock_Array* arrayTmp; + CLR_UINT16* pSrcStart; + CLR_UINT16* pSrcEnd; + + NANOCLR_CHECK_HRESULT(ConvertToCharArray( stack, refTmp, arrayTmp, 0, -1 )); + + pSrcStart = (CLR_UINT16*)arrayTmp->GetFirstElement(); + pSrcEnd = &pSrcStart[ arrayTmp->m_numOfElements ]; + + const CLR_UINT16* pTrim; + CLR_UINT32 iTrim; + + if(arrayTrimChars && arrayTrimChars->m_numOfElements) + { + pTrim = (const CLR_UINT16*)arrayTrimChars->GetFirstElement(); + iTrim = arrayTrimChars->m_numOfElements; + } + else + { + pTrim = c_WhiteSpaces; + iTrim = ARRAYSIZE(c_WhiteSpaces); + } + + //--// + + if(fStart) + { + while(pSrcStart < pSrcEnd) + { + const CLR_UINT16* p = pTrim; + CLR_UINT32 i; + + for(i=0; im_numOfElements > 0) + { + pChars = (CLR_UINT16*)arrayChars->GetFirstElement(); + cChars = arrayChars->m_numOfElements; + } + else + { + pChars = &c_WhiteSpaces[ 0 ]; + cChars = ARRAYSIZE(c_WhiteSpaces); + } + + arrayDst = NULL; + + { + CLR_RT_HeapBlock refSrc; refSrc.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc( refSrc ); + + NANOCLR_CHECK_HRESULT(ConvertToCharArray( stack, refSrc, arraySrc, 0, -1 )); + + for(int pass=0; pass<2; pass++) + { + CLR_UINT16* pSrcStart = (CLR_UINT16*)arraySrc->GetFirstElement(); + CLR_UINT16* pSrc = pSrcStart; + int count = 0; + bool fFound = false; + bool fContinueSearching = true; + + for(CLR_UINT32 iSrc=0; iSrc <= arraySrc->m_numOfElements; iSrc++, pSrc++) + { + if(iSrc == arraySrc->m_numOfElements) + { + fFound = true; + } + else if ((count + 1) >= maxStrings) + { + fContinueSearching = false; + } + else if (fContinueSearching) + { + const CLR_UINT16* pCharsT = pChars; + + for(CLR_UINT32 iChars=0; iCharsGetElement( count ); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( *str, pSrcStart, (CLR_UINT32)(pSrc - pSrcStart) )); + + pSrcStart = pSrc + 1; + } + + count++; + fFound = false; + } + } + + if(pass == 0) + { + CLR_RT_HeapBlock& refTarget = stack.PushValue(); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( refTarget, count, g_CLR_RT_WellKnownTypes.m_String )); + + arrayDst = refTarget.DereferenceArray(); + } + } + } + } + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT Library_corlib_native_System_String::Concat( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock* array, int num ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* ptrSrc; + const char* szTextSrc; + char* szTextDst = NULL; + CLR_UINT32 totLen; + CLR_UINT32 len; + + totLen = 0; + + for(int i=0; i<2; i++) + { + ptrSrc = array; + + for(int iStr=0; iStrDataType() == DATATYPE_OBJECT); + _ASSERTE(FIMPLIES(ptrSrc->Dereference(), ptrSrc->Dereference()->DataType() == DATATYPE_STRING)); + + szTextSrc = ptrSrc->RecoverString(); + if(szTextSrc) + { + len = (CLR_UINT32)hal_strlen_s( szTextSrc ); + + if(i==0) + { + totLen += len; + } + else + { + memcpy( szTextDst, szTextSrc, len ); + + szTextDst += len; + } + } + + ptrSrc++; + } + + if(i==0) + { + //push return value + CLR_RT_HeapBlock& blkResult = stack.PushValue(); + CLR_RT_HeapBlock_String* str = CLR_RT_HeapBlock_String::CreateInstance( blkResult, totLen ); CHECK_ALLOCATION(str); + + szTextDst = (char*)str->StringText(); + szTextDst[ totLen ] = 0; + } + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::ConvertToCharArray( const char* szText, CLR_RT_HeapBlock& ref, CLR_RT_HeapBlock_Array*& array, int startIndex, int length ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_UnicodeHelper uh; + int totLength; + + FAULT_ON_NULL(szText); + + uh.SetInputUTF8( szText ); + + totLength = uh.CountNumberOfCharacters(); if(totLength < 0) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + if(length == -1) length = totLength; + + if(CLR_RT_HeapBlock_Array::CheckRange( startIndex, length, totLength ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( ref, length, g_CLR_RT_WellKnownTypes.m_Char )); + + array = ref.DereferenceArray(); + + uh.m_outputUTF16 = (CLR_UINT16*)array->GetFirstElement(); + uh.m_outputUTF16_size = array->m_numOfElements; + + // + // First move to the character, then read it. + // + uh.ConvertFromUTF8( startIndex , true ); + uh.ConvertFromUTF8( array->m_numOfElements, false ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_String::ConvertToCharArray( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock& ref, CLR_RT_HeapBlock_Array*& array, int startIndex, int length ) +{ + NATIVE_PROFILE_CLR_CORE(); + return ConvertToCharArray( stack.Arg0().RecoverString(), ref, array, startIndex, length ); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Text_UTF8Decoder.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Text_UTF8Decoder.cpp new file mode 100644 index 00000000..ddbf11fb --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Text_UTF8Decoder.cpp @@ -0,0 +1,74 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_Text_UTF8Decoder::Convert___VOID__SZARRAY_U1__I4__I4__SZARRAY_CHAR__I4__I4__BOOLEAN__BYREF_I4__BYREF_I4__BYREF_BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_UTF8_DECODER(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* pArrayBytes; + CLR_INT32 byteIndex; + CLR_INT32 byteCount; + CLR_RT_HeapBlock_Array* pArrayChars; + CLR_INT32 charIndex; + CLR_INT32 charCount; + CLR_INT32 byteUsed; + CLR_INT32 charUsed; + bool completed; + + CLR_RT_UnicodeHelper uh; + CLR_UINT8* byteStart; + + // Get all the parameters + pArrayBytes = stack.Arg1().DereferenceArray(); FAULT_ON_NULL(pArrayBytes); + byteIndex = stack.Arg2().NumericByRef().s4; + byteCount = stack.Arg3().NumericByRef().s4; + + pArrayChars = stack.Arg4( ).DereferenceArray(); FAULT_ON_NULL(pArrayChars); + charIndex = stack.ArgN( 5 ).NumericByRef().s4; + charCount = stack.ArgN( 6 ).NumericByRef().s4; + + // Parameters error checking + if (byteIndex < 0 || + byteCount < 0 || + charIndex < 0 || + charCount < 0 || + (CLR_INT32)pArrayBytes->m_numOfElements - byteIndex < byteCount || + (CLR_INT32)pArrayChars->m_numOfElements - charIndex < charCount ) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + _ASSERTE(pArrayBytes->m_typeOfElement == DATATYPE_U1); + _ASSERTE(pArrayChars->m_typeOfElement == DATATYPE_CHAR); + + _ASSERTE(stack.ArgN( 8 ).DataType() == DATATYPE_BYREF); + _ASSERTE(stack.ArgN( 9 ).DataType() == DATATYPE_BYREF); + _ASSERTE(stack.ArgN( 10 ).DataType() == DATATYPE_BYREF); + + + // Setup the UnicodeHelper + byteStart = pArrayBytes->GetElement( byteIndex ); + uh.SetInputUTF8( (const char*)byteStart ); + + uh.m_outputUTF16 = (CLR_UINT16*)pArrayChars->GetElement( charIndex ); + uh.m_outputUTF16_size = charCount; + + uh.ConvertFromUTF8( charCount, false, byteCount ); + + // Calculate return values + byteUsed = (CLR_INT32)(uh.m_inputUTF8 - byteStart); + charUsed = charCount - uh.m_outputUTF16_size; + completed = (byteUsed == byteCount); + + stack.ArgN(8).Dereference()->SetInteger( byteUsed ); + stack.ArgN(9).Dereference()->SetInteger( charUsed ); + stack.ArgN(10).Dereference()->SetBoolean( completed ); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Text_UTF8Encoding.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Text_UTF8Encoding.cpp new file mode 100644 index 00000000..a1f14888 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Text_UTF8Encoding.cpp @@ -0,0 +1,127 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_Text_UTF8Encoding::GetBytes___SZARRAY_U1__STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + size_t cBytes; + CLR_RT_HeapBlock_Array* arr; + const char* str; + CLR_RT_HeapBlock& ret = stack.PushValueAndClear(); + + str = stack.Arg1().RecoverString(); FAULT_ON_NULL(str); + cBytes = hal_strlen_s(str); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( ret, (CLR_UINT32)cBytes, g_CLR_RT_WellKnownTypes.m_UInt8 )); + + arr = ret.DereferenceArray(); + + memcpy( arr->GetFirstElement(), str, cBytes ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Text_UTF8Encoding::GetBytes___I4__STRING__I4__I4__SZARRAY_U1__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + const char* str = stack.Arg1().RecoverString(); + CLR_INT32 strIdx = stack.Arg2().NumericByRef().s4; + CLR_INT32 strCnt = stack.Arg3().NumericByRef().s4; + CLR_RT_HeapBlock_Array* pArrayBytes = stack.Arg4().DereferenceArray(); + CLR_INT32 byteIdx = stack.Arg5().NumericByRef().s4; + + const CLR_UINT8* i; + const CLR_UINT8* j; + CLR_RT_UnicodeHelper uh; + int strLength; + + FAULT_ON_NULL(str); + FAULT_ON_NULL(pArrayBytes); + + uh.SetInputUTF8(str); + strLength = uh.CountNumberOfCharacters(); + if (strLength < 0) + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + if ((strIdx + strCnt) > (CLR_INT32)strLength) + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + + uh.ConvertFromUTF8(strIdx, true); + i = uh.m_inputUTF8; + uh.ConvertFromUTF8(strCnt, true); + j = uh.m_inputUTF8; + + if ((byteIdx + j - i) > (CLR_INT32)pArrayBytes->m_numOfElements) + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + + memcpy(pArrayBytes->GetElement(byteIdx), i, j - i); + + stack.SetResult_I4(j - i); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Text_UTF8Encoding::GetChars___SZARRAY_CHAR__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_CHECK_HRESULT(Helper__GetChars( stack, false )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Text_UTF8Encoding::GetChars___SZARRAY_CHAR__SZARRAY_U1__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_CHECK_HRESULT(Helper__GetChars( stack, true )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Text_UTF8Encoding::Helper__GetChars(CLR_RT_StackFrame& stack, bool fIndexed) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + const char* szText; + CLR_RT_HeapBlock ref; ref.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc( ref ); + CLR_RT_HeapBlock_Array* pArrayBytes = stack.Arg1().DereferenceArray(); + CLR_INT32 byteIdx = fIndexed ? stack.Arg2().NumericByRef().s4 : 0; + CLR_INT32 byteCnt = fIndexed ? stack.Arg3().NumericByRef().s4 : pArrayBytes->m_numOfElements; + CLR_RT_HeapBlock_Array* pArrayBytesCopy; + CLR_RT_HeapBlock_Array* arrTmp; + int cBytesCopy; + + FAULT_ON_NULL(pArrayBytes); + + _ASSERTE(pArrayBytes->m_typeOfElement == DATATYPE_U1); + + if((byteIdx + byteCnt) > (CLR_INT32)pArrayBytes->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + + cBytesCopy = byteCnt+1; + + /* Copy the array to a temporary buffer to create a zero-terminated string */ + NANOCLR_CHECK_HRESULT( CLR_RT_HeapBlock_Array::CreateInstance( ref, cBytesCopy, g_CLR_RT_WellKnownTypes.m_UInt8 )); + + pArrayBytesCopy = ref.DereferenceArray(); + szText = (const char*)pArrayBytesCopy->GetFirstElement(); + + hal_strncpy_s( (char*) szText, cBytesCopy, (const char*)pArrayBytes->GetElement(byteIdx), byteCnt ); + + NANOCLR_CHECK_HRESULT(Library_corlib_native_System_String::ConvertToCharArray( szText, stack.PushValueAndClear(), arrTmp, 0, -1 )); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Threading_AutoResetEvent.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Threading_AutoResetEvent.cpp new file mode 100644 index 00000000..1037e1d3 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Threading_AutoResetEvent.cpp @@ -0,0 +1,44 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_Threading_AutoResetEvent::_ctor___VOID__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* pThis = stack.This(); + + pThis->SetFlags( CLR_RT_HeapBlock::HB_SignalAutoReset ); + + if(stack.Arg1().NumericByRef().s4) + { + pThis->SetFlags( CLR_RT_HeapBlock::HB_Signaled ); + } + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_Threading_AutoResetEvent::Reset___BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + Library_corlib_native_System_Threading_WaitHandle::Reset( stack ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_Threading_AutoResetEvent::Set___BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + Library_corlib_native_System_Threading_WaitHandle::Set( stack ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Threading_Interlocked.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Threading_Interlocked.cpp new file mode 100644 index 00000000..54bb9322 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Threading_Interlocked.cpp @@ -0,0 +1,92 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_Threading_Interlocked::Increment___STATIC__I4__BYREF_I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock heapLocation; + NANOCLR_CHECK_HRESULT(heapLocation.LoadFromReference( stack.Arg0() )); + signed int &location = heapLocation.NumericByRef().s4; + + // Increment the value passed by reference + location++; + + SetResult_INT32( stack, location ); + + NANOCLR_CHECK_HRESULT(heapLocation.StoreToReference( stack.Arg0(), 0 )); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Threading_Interlocked::Decrement___STATIC__I4__BYREF_I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock heapLocation; + NANOCLR_CHECK_HRESULT(heapLocation.LoadFromReference( stack.Arg0() )); + signed int &location = heapLocation.NumericByRef().s4; + + // Decrement the value passed by reference + location--; + + SetResult_INT32( stack, location ); + + NANOCLR_CHECK_HRESULT(heapLocation.StoreToReference( stack.Arg0(), 0 )); + } + NANOCLR_NOCLEANUP(); +} + + +HRESULT Library_corlib_native_System_Threading_Interlocked::Exchange___STATIC__I4__BYREF_I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock heapLocation; + NANOCLR_CHECK_HRESULT(heapLocation.LoadFromReference( stack.Arg0() )); + signed int &location = heapLocation.NumericByRef().s4; + + // Always return value of first parameter + signed int retVal = location; + // Move second parameter into the first. + location = stack.Arg1().NumericByRef().s4; + + SetResult_INT32( stack, retVal ); + + NANOCLR_CHECK_HRESULT(heapLocation.StoreToReference( stack.Arg0(), 0 )); + } + NANOCLR_NOCLEANUP(); +} + + +HRESULT Library_corlib_native_System_Threading_Interlocked::CompareExchange___STATIC__I4__BYREF_I4__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock heapLocation; + NANOCLR_CHECK_HRESULT(heapLocation.LoadFromReference( stack.Arg0() )); + signed int &location = heapLocation.NumericByRef().s4; + + // Always return value of first parameter + signed int retVal = location; + // Exchange value if first and third parameters has equal value. + if (stack.Arg2().NumericByRef().s4 == location) + { + location = stack.Arg1().NumericByRef().s4; + } + + SetResult_INT32( stack, retVal ); + + NANOCLR_CHECK_HRESULT(heapLocation.StoreToReference( stack.Arg0(), 0 )); + } + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Threading_ManualResetEvent.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Threading_ManualResetEvent.cpp new file mode 100644 index 00000000..8482a43d --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Threading_ManualResetEvent.cpp @@ -0,0 +1,42 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_Threading_ManualResetEvent::_ctor___VOID__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* pThis = stack.This(); + + if(stack.Arg1().NumericByRef().s4) + { + pThis->SetFlags( CLR_RT_HeapBlock::HB_Signaled ); + } + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_Threading_ManualResetEvent::Reset___BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + Library_corlib_native_System_Threading_WaitHandle::Reset( stack ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_Threading_ManualResetEvent::Set___BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + Library_corlib_native_System_Threading_WaitHandle::Set( stack ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Threading_Monitor.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Threading_Monitor.cpp new file mode 100644 index 00000000..0a1c43fb --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Threading_Monitor.cpp @@ -0,0 +1,65 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_Threading_Monitor::Enter___STATIC__VOID__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_StackFrame* caller = NULL; + + if(stack.Arg0().Dereference() == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_ARGUMENT_NULL); + } + + switch(stack.m_customState) + { + case 0: + { + caller = stack.Caller(); FAULT_ON_NULL(caller); // We need to set the constraint on the caller, not on us... + + hr = g_CLR_RT_ExecutionEngine.LockObject( stack.Arg0(), caller->m_owningSubThread, TIMEOUT_INFINITE, false ); + if(hr == CLR_E_THREAD_WAITING) + { + stack.m_customState = 1; + } + + NANOCLR_LEAVE(); + } + break; + + case 1: + NANOCLR_SET_AND_LEAVE(S_OK); + break; + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Threading_Monitor::Exit___STATIC__VOID__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_StackFrame* caller = NULL; + + if(stack.Arg0().Dereference() == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_ARGUMENT_NULL); + } + + caller = stack.Caller(); FAULT_ON_NULL(caller); // We need to set the constraint on the caller, not on us... + + NANOCLR_SET_AND_LEAVE(g_CLR_RT_ExecutionEngine.UnlockObject( stack.Arg0(), caller->m_owningSubThread )); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Threading_Thread.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Threading_Thread.cpp new file mode 100644 index 00000000..add106ca --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Threading_Thread.cpp @@ -0,0 +1,575 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + +//--// + +HRESULT Library_corlib_native_System_Threading_Thread::_ctor___VOID__SystemThreadingThreadStart( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* pThis = stack.This(); + + pThis[ FIELD___delegate ].Assign ( stack.Arg1() ); + + // Thread is always constructed with normal priority. + pThis[ FIELD___priority ].NumericByRef().s4 = ThreadPriority::Normal; + + // Book a Thread ID + pThis[ FIELD___id ].NumericByRef().s4 = g_CLR_RT_ExecutionEngine.GetNextThreadId(); + + +#if defined(NANOCLR_APPDOMAINS) + NANOCLR_CHECK_HRESULT(CLR_RT_ObjectToEvent_Source::CreateInstance( g_CLR_RT_ExecutionEngine.GetCurrentAppDomain(), *pThis, pThis[ FIELD___appDomain ] )); + NANOCLR_NOCLEANUP(); +#else + NANOCLR_NOCLEANUP_NOLABEL(); +#endif + +} + +HRESULT Library_corlib_native_System_Threading_Thread::Start___VOID( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_Thread* th; + CLR_RT_HeapBlock* pThis; + CLR_RT_HeapBlock_Delegate* dlg; + int pri; + + // + // Don't start twice... + // + NANOCLR_CHECK_HRESULT(GetThread( stack, th, false, false )); + if(th != NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + pThis = stack.This(); FAULT_ON_NULL(pThis); + dlg = pThis[ FIELD___delegate ].DereferenceDelegate(); FAULT_ON_NULL(dlg ); + + // Set priority of new sub-thread to the priority stored in the thread C# object. + // The new sub-thread becames the current one, it should always match priority stored in Thread C# object + + pri = pThis[ FIELD___priority ].NumericByRef().s4; + + pThis->ResetFlags( CLR_RT_HeapBlock::HB_Signaled ); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewThread( th, dlg, pri, pThis[ FIELD___id ].NumericByRef().s4 )); + + NANOCLR_SET_AND_LEAVE(SetThread( stack, th )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Threading_Thread::Abort___VOID( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_Thread* th; + + NANOCLR_CHECK_HRESULT(GetThread( stack, th, true, true )); + + if(th == stack.m_owningThread) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + th->Abort(); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Threading_Thread::Suspend___VOID( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + // Test if this the call from managed Thread.Suspend() or second call on resume. + switch( stack.m_customState ) + { + // This is the normal call from managed code. + case 0: + { + CLR_RT_Thread* th; + + NANOCLR_CHECK_HRESULT(GetThread( stack, th, true, true )); + + NANOCLR_CHECK_HRESULT(th->Suspend()); + + // If the thread suspends itself, then we need to re-schedule. + if ( stack.m_owningThread == th ) + { // Set flag in thread stack that thread is re-scheduled. + stack.m_customState = 1; + + // Call to th->Suspend() was successful and moved thread to suspended list. + // Now the threads should be re-scheduled to make suspension effective immidiately. + // In order to do it we return CLR_E_RESCHEDULE from this function - Suspend___VOID + NANOCLR_SET_AND_LEAVE( CLR_E_RESCHEDULE ); + } + } + break; + + // This is the case when thread is resumed, brought back from suspended state. + case 1: + { + stack.m_customState = 0; + NANOCLR_SET_AND_LEAVE(S_OK); + } + break; + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + break; + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Threading_Thread::Resume___VOID( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_Thread* th; + + NANOCLR_CHECK_HRESULT(GetThread( stack, th, true, true )); + + NANOCLR_SET_AND_LEAVE(th->Resume()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Threading_Thread::get_Priority___SystemThreadingThreadPriority( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_Thread* th; + int pri; + + // Get C# thread object + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Reads priority stored in C# object. + pri = pThis[ FIELD___priority ].NumericByRef().s4; + + // Here we check consistency of values stored in C# and internal thread objects. + // Get thread associated with C# thread object. It might be NULL if thread was not started. + NANOCLR_CHECK_HRESULT(GetThread( stack, th, false, false )); + + // If thread was started, then we use priority from the CLR_RT_Thread. + // There are 2 reasons it might be different from priority from C# object: + // 1. The manager C# object was garbage collected and then re-created. + // 2. Sub-thread with different priority may have been created in Library_spot_native_Microsoft_SPOT_ExecutionConstraint::Install___STATIC__VOID__I4__I4 + + if ( th != NULL ) + { + pri = th->GetThreadPriority(); + + // We store it back to managed object to keep values consistent. + pThis[ FIELD___priority ].NumericByRef().s4 = pri; + } + + // Zero priority correspond is equal to managed. ThreadPriority.Lowest. + // The highest value should be 4 ( ThreadPriority.highest ), but we allow higher values. + // Users cannot create threads with values outside the Lowest-Highest range; we exceed that + // range internally, but we can't expose those values to managed code. + if (pri < ThreadPriority::Lowest ) pri = ThreadPriority::Lowest; + else if (pri > ThreadPriority::Highest) pri = ThreadPriority::Highest; + + // Return value back to C# code. + stack.SetResult_I4( pri ); + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Threading_Thread::set_Priority___VOID__SystemThreadingThreadPriority( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if ( stack.m_customState == 0 ) + { + CLR_RT_Thread* th; + + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Get argument for priority. Check the range - should be between ThreadPriority::Highest and ThreadPriority::Lowest ( 0 - 4 ) + int pri = stack.Arg1().NumericByRef().s4; + if ( pri < ThreadPriority::Lowest || pri > ThreadPriority::Highest ) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // Get CLR thread. The object exists if thread was started. + NANOCLR_CHECK_HRESULT(GetThread( stack, th, false, true )); + + // Save priority to managed C# object + pThis[ FIELD___priority ].NumericByRef().s4 = pri; + + if ( th ) + { + // Priority of current sub-thread is set the thread priority. + th->SetThreadPriority( pri ); + + stack.m_customState = 1; + + // If we set high priority to another thread, then we need to swtich to another thread. + if ( pri > stack.m_owningThread->GetThreadPriority() ) + { + NANOCLR_SET_AND_LEAVE(CLR_E_RESCHEDULE); + } + } + } + + NANOCLR_NOCLEANUP(); + +} + +HRESULT Library_corlib_native_System_Threading_Thread::get_ManagedThreadId___I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + int id; + + // Get C# thread object + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Reads priority stored in C# object. + id = pThis[ FIELD___id ].NumericByRef().s4; + + // Return value back to C# code. + stack.SetResult_I4( id ); + NANOCLR_NOCLEANUP(); +} + + +HRESULT Library_corlib_native_System_Threading_Thread::get_IsAlive___BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_Thread* th; + + GetThread( stack, th, false, false ); + + stack.SetResult_Boolean( th != NULL && th->m_status != CLR_RT_Thread::TH_S_Terminated ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_Threading_Thread::Join___VOID( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(Join( stack, TIMEOUT_INFINITE )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Threading_Thread::Join___BOOLEAN__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_INT64 timeExpire; + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.InitTimeout( timeExpire, stack.Arg1().NumericByRef().s4 )); + + NANOCLR_SET_AND_LEAVE(Join( stack, timeExpire )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Threading_Thread::Join___BOOLEAN__SystemTimeSpan( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_INT64* timeExpireIn; + CLR_INT64 timeExpireOut; + + timeExpireIn = Library_corlib_native_System_TimeSpan::GetValuePtr( stack.Arg1() ); FAULT_ON_NULL(timeExpireIn); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.InitTimeout( timeExpireOut, *timeExpireIn )); + + NANOCLR_SET_AND_LEAVE(Join( stack, timeExpireOut )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Threading_Thread::get_ThreadState___SystemThreadingThreadState( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + + NANOCLR_HEADER(); + + CLR_RT_Thread* th; + int val = 0; + + NANOCLR_CHECK_HRESULT(GetThread( stack, th, false, false )); + + if(th == NULL) + { + val = 8; //Unstarted + } + else + { + switch(th->m_status) + { + case CLR_RT_Thread::TH_S_Ready : val = 0; break; // Running + case CLR_RT_Thread::TH_S_Waiting : val = 32; break; // WaitSleepJoin + case CLR_RT_Thread::TH_S_Terminated: val = 16; break; // Stopped + default : _ASSERTE(false); break; + } + + // Suspended thread. Add ThreadState.Suspended to the return value + if(th->m_flags & CLR_RT_Thread::TH_F_Suspended) + { + val |= 64; // ThreadState.Suspended = 64 + } + // Aborted thread. Add ThreadState.Aborted to the return value + if(th->m_flags & CLR_RT_Thread::TH_F_Aborted) + { + val |= 256; // ThreadState.Aborted = 256 + } + + } + + stack.SetResult_I4( val ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Threading_Thread::Sleep___STATIC__VOID__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_INT64 timeExpire; + CLR_INT32 timeSleep; + + switch(stack.m_customState) + { + case 0: + + timeSleep = stack.m_arguments[ 0 ].NumericByRef().s4; + if ( timeSleep != 0 ) + { + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.InitTimeout( timeExpire, stack.m_arguments[ 0 ].NumericByRef().s4 )); + + hr = g_CLR_RT_ExecutionEngine.Sleep( stack.m_owningThread, timeExpire ); + if(hr == CLR_E_THREAD_WAITING) + { + stack.m_customState = 1; + } + } + else + { + // In case of Sleep(0) call the threads should be re-scheduled . + // This function updates execution counter in pThread and makes it last to execute. + // Used to Thread.Sleep(0) imlementation. The thread is still ready, but is last to execute. + g_CLR_RT_ExecutionEngine.UpdateToLowestExecutionCounter( stack.m_owningThread ); + // In order to do it we return CLR_E_RESCHEDULE from this function. + stack.m_customState = 1; + NANOCLR_SET_AND_LEAVE( CLR_E_RESCHEDULE ); + } + + + NANOCLR_LEAVE(); + + case 1: + NANOCLR_SET_AND_LEAVE(S_OK); + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Threading_Thread::get_CurrentThread___STATIC__SystemThreadingThread( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_Thread* thread = stack.m_owningThread; + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + CLR_RT_HeapBlock* pRes; + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + //If we are a thread spawned by the debugger to perform evaluations, + //return the thread object that correspond to thread that has focus in debugger. + thread = thread->m_realThread; +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + //Find an existing managed thread, if it exists + //making sure to only return the managed object association with the current appdomain + //to prevent leaking of managed Thread objects across AD boundaries. + NANOCLR_FOREACH_NODE(CLR_RT_ObjectToEvent_Source,src,thread->m_references) + { + CLR_RT_HeapBlock* pManagedThread = src->m_objectPtr; + bool fFound = false; + _ASSERTE(pManagedThread != NULL); + +#if defined(NANOCLR_APPDOMAINS) + { + CLR_RT_ObjectToEvent_Source* appDomainSrc = CLR_RT_ObjectToEvent_Source::ExtractInstance( pManagedThread[ FIELD___appDomain ] ); + + FAULT_ON_NULL_HR(appDomainSrc, CLR_E_FAIL); + + fFound = (appDomainSrc->m_eventPtr == g_CLR_RT_ExecutionEngine.GetCurrentAppDomain()); + } +#else + fFound = true; +#endif + + if(fFound) + { + top.SetObjectReference( pManagedThread ); + + NANOCLR_SET_AND_LEAVE(S_OK); + } + } + NANOCLR_FOREACH_NODE_END(); + + + //Create the managed thread. + //This implies that there is no state in the managed object. This is not exactly true, as the managed thread + //contains the priority as well as the delegate to start. However, that state is really just used as a placeholder for + //the data before the thread is started. Once the thread is started, they are copied over to the unmanaged thread object + //and no longer used. The managed object is then used simply as a wrapper for the unmanaged thread. Therefore, it is safe + //to simply make another managed thread here. + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex( top, g_CLR_RT_WellKnownTypes.m_Thread )); + + pRes = top.Dereference(); + + NANOCLR_CHECK_HRESULT(CLR_RT_ObjectToEvent_Source::CreateInstance( thread, *pRes, pRes[ FIELD___thread ] )); + +#if defined(NANOCLR_APPDOMAINS) + NANOCLR_CHECK_HRESULT(CLR_RT_ObjectToEvent_Source::CreateInstance( g_CLR_RT_ExecutionEngine.GetCurrentAppDomain(), *pRes, pRes[ FIELD___appDomain ] )); +#endif + + NANOCLR_NOCLEANUP(); +} + +#if (NANOCLR_REFLECTION == TRUE) + +HRESULT Library_corlib_native_System_Threading_Thread::GetDomain___STATIC__SystemAppDomain( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + +#if !defined(NANOCLR_APPDOMAINS) + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); +#else + CLR_RT_AppDomain* appDomain = g_CLR_RT_ExecutionEngine.GetCurrentAppDomain(); + + NANOCLR_CHECK_HRESULT(appDomain->GetManagedObject( stack.PushValue() )); +#endif + + NANOCLR_NOCLEANUP(); +} +#endif // NANOCLR_REFLECTION + +//--// + +CLR_RT_ObjectToEvent_Source* Library_corlib_native_System_Threading_Thread::GetThreadReference( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock* pThis = stack.This(); + + return CLR_RT_ObjectToEvent_Source::ExtractInstance( pThis[ FIELD___thread ] ); +} + +void Library_corlib_native_System_Threading_Thread::ResetThreadReference( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_ObjectToEvent_Source* src = GetThreadReference( stack ); + if(src) + { + src->Detach(); + } +} + +HRESULT Library_corlib_native_System_Threading_Thread::SetThread( CLR_RT_StackFrame& stack, CLR_RT_Thread* th ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* pThis = stack.This(); + + ResetThreadReference( stack ); + + NANOCLR_SET_AND_LEAVE(CLR_RT_ObjectToEvent_Source::CreateInstance( th, *pThis, pThis[ FIELD___thread ] )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Threading_Thread::GetThread( CLR_RT_StackFrame& stack, CLR_RT_Thread*& th, bool mustBeStarted, bool noSystemThreads ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + CLR_RT_ObjectToEvent_Source* src = GetThreadReference( stack ); + + th = (src == NULL) ? NULL : (CLR_RT_Thread*)src->m_eventPtr; + if(th == NULL) + { + if (mustBeStarted) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + } + else if (noSystemThreads && th->m_flags & CLR_RT_Thread::TH_F_System) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Threading_Thread::Join( CLR_RT_StackFrame& stack, const CLR_INT64& timeExpire ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_Thread* th; + bool fRes = true; + + NANOCLR_CHECK_HRESULT(GetThread( stack, th, true, false )); + + //Don't let programs join from system threads like interrupts or finalizers + if ( stack.m_owningThread->m_flags & CLR_RT_Thread::TH_F_System ) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + } + + // + // You cannot join yourself. + // + if(th == stack.m_owningThread) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + if(th->m_status != CLR_RT_Thread::TH_S_Terminated) + { + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_WaitForObject::WaitForSignal( stack, timeExpire, stack.ThisRef() )); + + fRes = (stack.m_owningThread->m_waitForObject_Result != CLR_RT_Thread::TH_WAIT_RESULT_TIMEOUT); + } + + stack.SetResult_Boolean( fRes ); + + NANOCLR_NOCLEANUP(); +} + diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Threading_Timer.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Threading_Timer.cpp new file mode 100644 index 00000000..6f5aa716 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Threading_Timer.cpp @@ -0,0 +1,91 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_Threading_Timer::Dispose___VOID( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + (void)SetValues( stack, CLR_RT_HeapBlock_Timer::c_ACTION_Destroy ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_corlib_native_System_Threading_Timer::_ctor___VOID__SystemThreadingTimerCallback__OBJECT__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(SetValues( stack, CLR_RT_HeapBlock_Timer::c_ACTION_Create | CLR_RT_HeapBlock_Timer::c_INPUT_Int32 )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Threading_Timer::_ctor___VOID__SystemThreadingTimerCallback__OBJECT__SystemTimeSpan__SystemTimeSpan( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(SetValues( stack, CLR_RT_HeapBlock_Timer::c_ACTION_Create | CLR_RT_HeapBlock_Timer::c_INPUT_TimeSpan )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Threading_Timer::Change___BOOLEAN__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(CheckDisposed( stack )) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + stack.SetResult_Boolean( true ); + + NANOCLR_SET_AND_LEAVE(SetValues( stack, CLR_RT_HeapBlock_Timer::c_ACTION_Change | CLR_RT_HeapBlock_Timer::c_INPUT_Int32 )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Threading_Timer::Change___BOOLEAN__SystemTimeSpan__SystemTimeSpan( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(CheckDisposed( stack )) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + stack.SetResult_Boolean( true ); + + NANOCLR_SET_AND_LEAVE(SetValues( stack, CLR_RT_HeapBlock_Timer::c_ACTION_Change | CLR_RT_HeapBlock_Timer::c_INPUT_TimeSpan )); + + NANOCLR_NOCLEANUP(); +} + +//--// + +bool Library_corlib_native_System_Threading_Timer::CheckDisposed( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + + return CLR_RT_HeapBlock_Timer::CheckDisposed( stack ); +} + + +HRESULT Library_corlib_native_System_Threading_Timer::SetValues( CLR_RT_StackFrame& stack, CLR_UINT32 flags ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(CLR_RT_HeapBlock_Timer::ConfigureObject( stack, flags )); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Threading_WaitHandle.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Threading_WaitHandle.cpp new file mode 100644 index 00000000..abf735d6 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Threading_WaitHandle.cpp @@ -0,0 +1,71 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_Threading_WaitHandle::WaitOne___BOOLEAN__I4__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_CHECK_HRESULT(Wait( stack, stack.Arg1(), stack.Arg2(), &stack.ThisRef(), 1, false )); + + stack.SetResult_Boolean( stack.m_owningThread->m_waitForObject_Result != CLR_RT_Thread::TH_WAIT_RESULT_TIMEOUT ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Threading_WaitHandle::WaitMultiple___STATIC__I4__SZARRAY_SystemThreadingWaitHandle__I4__BOOLEAN__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* arr = stack.Arg0().DereferenceArray(); FAULT_ON_NULL(arr); + + NANOCLR_CHECK_HRESULT(Wait( stack, stack.Arg1(), stack.Arg2(), (CLR_RT_HeapBlock*)arr->GetFirstElement(), arr->m_numOfElements, stack.Arg3().NumericByRef().s1 == 1 )); + + stack.SetResult_I4( stack.m_owningThread->m_waitForObject_Result ); + + NANOCLR_NOCLEANUP(); +} + +//--// + +void Library_corlib_native_System_Threading_WaitHandle::Set( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock* pThis = stack.This(); + + CLR_RT_HeapBlock_WaitForObject::SignalObject( *pThis ); + + stack.SetResult_Boolean( true ); +} + +void Library_corlib_native_System_Threading_WaitHandle::Reset( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock* pThis = stack.This(); + + pThis->ResetFlags( CLR_RT_HeapBlock::HB_Signaled ); + + stack.SetResult_Boolean( true ); +} + +HRESULT Library_corlib_native_System_Threading_WaitHandle::Wait( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock& blkTimeout, CLR_RT_HeapBlock& blkExitContext, CLR_RT_HeapBlock* objects, int cObjects, bool fWaitAll ) +{ + (void)blkExitContext; + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_INT64 timeExpire; + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.InitTimeout( timeExpire, blkTimeout.NumericByRef().s4 )); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_WaitForObject::WaitForSignal( stack, timeExpire, objects, cObjects, fWaitAll )); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_TimeSpan.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_TimeSpan.cpp new file mode 100644 index 00000000..71c1a076 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_TimeSpan.cpp @@ -0,0 +1,193 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_TimeSpan::Equals___BOOLEAN__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_CHECK_HRESULT(CompareTo___I4__OBJECT( stack )); + + { + CLR_RT_HeapBlock& res = stack.TopValue(); + + res.SetBoolean( res.NumericByRef().s4 == 0 ); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_TimeSpan::ToString___STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + char rgBuffer[ 128 ]; + char* szBuffer = rgBuffer; + size_t iBuffer = ARRAYSIZE(rgBuffer); + CLR_INT64* val = GetValuePtr( stack ); FAULT_ON_NULL(val); + + HAL_Time_TimeSpanToStringEx( *val, szBuffer, iBuffer ); + + NANOCLR_SET_AND_LEAVE(stack.SetResult_String( rgBuffer )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_TimeSpan::_ctor___VOID__I4__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* pArgs = &(stack.Arg1()); + CLR_INT64* val = GetValuePtr( stack ); FAULT_ON_NULL(val); + + ConstructTimeSpan( val, 0, pArgs[ 0 ].NumericByRef().s4, pArgs[ 1 ].NumericByRef().s4, pArgs[ 2 ].NumericByRef().s4, 0 ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_TimeSpan::_ctor___VOID__I4__I4__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* pArgs = &(stack.Arg1()); + CLR_INT64* val = GetValuePtr( stack ); FAULT_ON_NULL(val); + + ConstructTimeSpan( val, pArgs[ 0 ].NumericByRef().s4, pArgs[ 1 ].NumericByRef().s4, pArgs[ 2 ].NumericByRef().s4, pArgs[ 3 ].NumericByRef().s4, 0 ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_TimeSpan::_ctor___VOID__I4__I4__I4__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* pArgs = &(stack.Arg1()); + CLR_INT64* val = GetValuePtr( stack ); FAULT_ON_NULL(val); + + ConstructTimeSpan( val, pArgs[ 0 ].NumericByRef().s4, pArgs[ 1 ].NumericByRef().s4, pArgs[ 2 ].NumericByRef().s4, pArgs[ 3 ].NumericByRef().s4, pArgs[ 4 ].NumericByRef().s4 ); + + NANOCLR_NOCLEANUP(); +} + +void Library_corlib_native_System_TimeSpan::ConstructTimeSpan( CLR_INT64* val, CLR_INT32 days, CLR_INT32 hours, CLR_INT32 minutes, CLR_INT32 seconds, CLR_INT32 msec ) + +{ + *val = ((CLR_INT64)days) * TIME_CONVERSION__ONEDAY + + hours * TIME_CONVERSION__ONEHOUR + + minutes * TIME_CONVERSION__ONEMINUTE + + seconds * TIME_CONVERSION__ONESECOND; + + *val *= 1000; + *val += msec; + *val *= TIME_CONVERSION__TICKUNITS; +} + +HRESULT Library_corlib_native_System_TimeSpan::CompareTo___I4__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* pRight = stack.Arg1().Dereference(); + + if(pRight) + { + NANOCLR_SET_AND_LEAVE(Compare___STATIC__I4__SystemTimeSpan__SystemTimeSpan( stack )); + } + + stack.SetResult_I4( 1 ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_TimeSpan::Compare___STATIC__I4__SystemTimeSpan__SystemTimeSpan( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_INT64* pLeft; + CLR_INT64* pRight; + CLR_RT_HeapBlock resLeft; + CLR_RT_HeapBlock resRight; + + pLeft = Library_corlib_native_System_TimeSpan::GetValuePtr( stack ); FAULT_ON_NULL(pLeft); + pRight = Library_corlib_native_System_TimeSpan::GetValuePtr( stack.Arg1() ); FAULT_ON_NULL(pRight); + + resLeft .SetInteger( *pLeft ); + resRight.SetInteger( *pRight ); + + stack.SetResult_I4( CLR_RT_HeapBlock::Compare_Signed_Values( resLeft, resRight ) ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_TimeSpan::Equals___STATIC__BOOLEAN__SystemTimeSpan__SystemTimeSpan( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_CHECK_HRESULT(Compare___STATIC__I4__SystemTimeSpan__SystemTimeSpan( stack )); + + stack.ConvertResultToBoolean(); + + NANOCLR_NOCLEANUP(); +} + +//--// + +CLR_INT64* Library_corlib_native_System_TimeSpan::NewObject( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock& ref = stack.PushValue(); + + ref.SetDataId( CLR_RT_HEAPBLOCK_RAW_ID( DATATYPE_TIMESPAN, 0, 1 ) ); + ref.ClearData( ); + + return (CLR_INT64*)&ref.NumericByRef().s8; +} + +CLR_INT64* Library_corlib_native_System_TimeSpan::GetValuePtr( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + return GetValuePtr( stack.Arg0() ); +} + +CLR_INT64* Library_corlib_native_System_TimeSpan::GetValuePtr( CLR_RT_HeapBlock& ref ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock* obj = &ref; + CLR_DataType dt = obj->DataType(); + + if(dt == DATATYPE_OBJECT || dt == DATATYPE_BYREF) + { + obj = obj->Dereference(); if(!obj) return NULL; + + dt = obj->DataType(); + } + + if(dt == DATATYPE_TIMESPAN) + { + return (CLR_INT64*)&obj->NumericByRef().s8; + } + + if(dt == DATATYPE_I8) + { + return (CLR_INT64*)&obj->NumericByRef().s8; + } + + if(dt == DATATYPE_VALUETYPE && obj->ObjectCls().m_data == g_CLR_RT_WellKnownTypes.m_TimeSpan.m_data) + { + return (CLR_INT64*)&obj[ FIELD___ticks ].NumericByRef().s8; + } + + return NULL; +} + diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Type.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Type.cpp new file mode 100644 index 00000000..0e47acd7 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_Type.cpp @@ -0,0 +1,660 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_Type::get_DeclaringType___SystemType( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Instance td; + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + CLR_RT_HeapBlock* hbType = stack.Arg0().Dereference(); + + NANOCLR_CHECK_HRESULT(Library_corlib_native_System_RuntimeType::GetTypeDescriptor( *hbType, td )); + + if(td.m_target->enclosingType != CLR_EmptyIndex) + { + CLR_RT_HeapBlock* hbObj; + td.Set( td.Assembly(), td.m_target->enclosingType ); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_TypeStatic)); + hbObj = top.Dereference(); + hbObj->SetReflection( td ); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Type::GetMethod___SystemReflectionMethodInfo__STRING__SystemReflectionBindingFlags( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + const char* szText = stack.Arg1().RecoverString(); FAULT_ON_NULL(szText); + + NANOCLR_SET_AND_LEAVE(GetMethods( stack, szText, stack.Arg2().NumericByRef().s4, NULL, 0, false )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Type::IsInstanceOfType___BOOLEAN__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_TypeDescriptor descTarget; + CLR_RT_TypeDescriptor desc; + CLR_RT_HeapBlock* hbType = stack.Arg0().Dereference(); + + if(hbType->DataType() != DATATYPE_REFLECTION) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + NANOCLR_CHECK_HRESULT(descTarget.InitializeFromReflection( hbType->ReflectionDataConst() )); + NANOCLR_CHECK_HRESULT(desc .InitializeFromObject ( stack.Arg1() )); + + stack.SetResult_Boolean( CLR_RT_ExecutionEngine::IsInstanceOf( desc, descTarget ) ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Type::InvokeMember___OBJECT__STRING__SystemReflectionBindingFlags__SystemReflectionBinder__OBJECT__SZARRAY_OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Type::GetConstructor___SystemReflectionConstructorInfo__SZARRAY_SystemType( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* array = stack.Arg1().DereferenceArray(); FAULT_ON_NULL(array); + CLR_RT_HeapBlock* pParams; + int iParams; + + pParams = (CLR_RT_HeapBlock*)array->GetFirstElement(); + iParams = array->m_numOfElements; + + NANOCLR_SET_AND_LEAVE(GetMethods( stack, NULL, c_BindingFlags_CreateInstance | c_BindingFlags_Instance | c_BindingFlags_Public | c_BindingFlags_NonPublic, pParams, iParams, false )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Type::GetMethod___SystemReflectionMethodInfo__STRING__SZARRAY_SystemType( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* array = stack.Arg2().DereferenceArray(); + CLR_RT_HeapBlock* pParams; + int iParams; + + if(array) + { + pParams = (CLR_RT_HeapBlock*)array->GetFirstElement(); + iParams = array->m_numOfElements; + } + else + { + pParams = NULL; + iParams = 0; + } + + const char* szText = stack.Arg1().RecoverString(); FAULT_ON_NULL(szText); + + NANOCLR_SET_AND_LEAVE(GetMethods( stack, szText, c_BindingFlags_DefaultLookup, pParams, iParams, false )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Type::GetMethod___SystemReflectionMethodInfo__STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + const char* szText = stack.Arg1().RecoverString(); FAULT_ON_NULL(szText); + + NANOCLR_SET_AND_LEAVE(GetMethods( stack, szText, c_BindingFlags_DefaultLookup, NULL, 0, false )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Type::get_IsNotPublic___BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(CheckFlags( stack, CLR_RECORD_TYPEDEF::TD_Scope_Mask, CLR_RECORD_TYPEDEF::TD_Scope_NotPublic )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Type::get_IsPublic___BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(CheckFlags( stack, CLR_RECORD_TYPEDEF::TD_Scope_Mask, CLR_RECORD_TYPEDEF::TD_Scope_Public )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Type::get_IsClass___BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(CheckFlags( stack, CLR_RECORD_TYPEDEF::TD_Semantics_Mask, CLR_RECORD_TYPEDEF::TD_Semantics_Class )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Type::get_IsInterface___BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(CheckFlags( stack, CLR_RECORD_TYPEDEF::TD_Semantics_Mask, CLR_RECORD_TYPEDEF::TD_Semantics_Interface )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Type::get_IsValueType___BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(CheckFlags( stack, CLR_RECORD_TYPEDEF::TD_Semantics_Mask, CLR_RECORD_TYPEDEF::TD_Semantics_ValueType )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Type::get_IsAbstract___BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(CheckFlags( stack, CLR_RECORD_TYPEDEF::TD_Abstract, CLR_RECORD_TYPEDEF::TD_Abstract )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Type::get_IsEnum___BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(CheckFlags( stack, CLR_RECORD_TYPEDEF::TD_Semantics_Mask, CLR_RECORD_TYPEDEF::TD_Semantics_Enum )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Type::get_IsSerializable___BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(CheckFlags( stack, CLR_RECORD_TYPEDEF::TD_Serializable, CLR_RECORD_TYPEDEF::TD_Serializable )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Type::get_IsArray___BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Instance td; + CLR_RT_HeapBlock* hbType = stack.Arg0().Dereference(); + + NANOCLR_CHECK_HRESULT(Library_corlib_native_System_RuntimeType::GetTypeDescriptor( *hbType, td )); + + stack.SetResult_Boolean(td.m_data == g_CLR_RT_WellKnownTypes.m_Array.m_data); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Type::GetTypeInternal___STATIC__SystemType__STRING__STRING__BOOLEAN__SZARRAY_I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + const char* szClass; + const char* szAssembly; + CLR_RT_HeapBlock_Array* verArray; + CLR_RT_Assembly* assm; + CLR_RT_TypeDef_Index td; + CLR_INT32* ver; + bool fVersion; + + CLR_RECORD_VERSION version; + + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + CLR_RT_HeapBlock* hbObj; + szClass = stack.Arg0().RecoverString(); FAULT_ON_NULL(szClass); + szAssembly = stack.Arg1().RecoverString(); + + fVersion = stack.Arg2().NumericByRef().u1 != 0; + + if(fVersion) + { + verArray = stack.Arg3().DereferenceArray(); FAULT_ON_NULL(verArray); + ver = (CLR_INT32*)verArray->GetFirstElement(); + + version.iMajorVersion = ver[0]; + version.iMinorVersion = ver[1]; + version.iBuildNumber = ver[2]; + version.iRevisionNumber = ver[3]; + } + else + { + memset( &version, 0, sizeof(CLR_RECORD_VERSION)); + } + + if(szAssembly) + { + assm = g_CLR_RT_TypeSystem.FindAssembly( szAssembly, fVersion ? &version : NULL, fVersion ); + } + else + { + assm = NULL; + } + + if(g_CLR_RT_TypeSystem.FindTypeDef( szClass, assm, td )) + { +#if defined(NANOCLR_APPDOMAINS) + CLR_RT_TypeDef_Instance inst; + + inst.InitializeFromIndex( td ); + if(!g_CLR_RT_ExecutionEngine.GetCurrentAppDomain()->FindAppDomainAssembly( inst.m_assm )) NANOCLR_SET_AND_LEAVE(S_OK); +#endif + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_TypeStatic)); + hbObj = top.Dereference(); + hbObj->SetReflection( td ); + } + else + { + CLR_RT_ReflectionDef_Index reflex; + if(g_CLR_RT_TypeSystem.FindTypeDef( szClass, assm, reflex )) + { +#if defined(NANOCLR_APPDOMAINS) + CLR_RT_TypeDef_Instance inst; + + inst.InitializeFromIndex( reflex.m_data.m_type ); + if(!g_CLR_RT_ExecutionEngine.GetCurrentAppDomain()->FindAppDomainAssembly( inst.m_assm )) NANOCLR_SET_AND_LEAVE(S_OK); +#endif + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_TypeStatic)); + hbObj = top.Dereference(); + hbObj->SetReflection( reflex ); + } + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Type::GetTypeFromHandle___STATIC__SystemType__SystemRuntimeTypeHandle( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock& pThis = stack.Arg0(); + CLR_RT_HeapBlock& top = stack.PushValue(); + CLR_RT_HeapBlock* hbObj; + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_TypeStatic)); + hbObj = top.Dereference(); + hbObj->Assign(pThis); // RuntimeTypeHandle and Type have the same representation. + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT Library_corlib_native_System_Type::CheckFlags( CLR_RT_StackFrame& stack, CLR_UINT32 mask, CLR_UINT32 flag ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Instance td; + bool fRes; + CLR_RT_HeapBlock* hbType = stack.Arg0().Dereference(); + + NANOCLR_CHECK_HRESULT(Library_corlib_native_System_RuntimeType::GetTypeDescriptor( *hbType, td )); + + if((td.m_target->flags & mask) == flag) + { + fRes = true; + } + // + // Special case, an enum is a valuetype, so let's check for that one. + // + else if(mask == CLR_RECORD_TYPEDEF::TD_Semantics_Mask && flag == CLR_RECORD_TYPEDEF::TD_Semantics_ValueType) + { + NANOCLR_SET_AND_LEAVE(CheckFlags( stack, CLR_RECORD_TYPEDEF::TD_Semantics_Mask, CLR_RECORD_TYPEDEF::TD_Semantics_Enum )); + } + else + { + fRes = false; + } + + stack.SetResult_Boolean( fRes ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Type::GetFields( CLR_RT_StackFrame& stack, const char* szText, CLR_UINT32 bindingFlags, bool fAllMatches ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Instance td; + CLR_RT_TypeDef_Instance tdArg; + int iField; + CLR_RT_HeapBlock* hbType = stack.Arg0().Dereference(); + + if(bindingFlags == c_BindingFlags_Default) bindingFlags = c_BindingFlags_DefaultLookup; + + NANOCLR_CHECK_HRESULT(Library_corlib_native_System_RuntimeType::GetTypeDescriptor( *hbType, tdArg )); + + { + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + + for(int pass=0; pass < 2; pass++) + { + td = tdArg; + iField = 0; + + do + { + CLR_RT_Assembly* assm = td.m_assm; + const CLR_RECORD_TYPEDEF* tdR = td.m_target; + const CLR_RECORD_FIELDDEF* fd = td.m_assm->GetFieldDef( tdR->sFields_First ); + int iTot = tdR->iFields_Num + tdR->sFields_Num; + int i; + CLR_RT_FieldDef_Index idx; + + for(i=0; iGetString( fd->name ); + + if(fd->flags & CLR_RECORD_FIELDDEF::FD_NoReflection) + { + continue; + } + + if(fd->flags & CLR_RECORD_FIELDDEF::FD_Static) + { + if((bindingFlags & c_BindingFlags_Static) == 0) continue; + } + else + { + if((bindingFlags & c_BindingFlags_Instance) == 0) continue; + } + + if((fd->flags & CLR_RECORD_FIELDDEF::FD_Scope_Mask) == CLR_RECORD_FIELDDEF::FD_Scope_Public) + { + if((bindingFlags & c_BindingFlags_Public) == 0) continue; + } + else + { + if((bindingFlags & c_BindingFlags_NonPublic) == 0) continue; + } + + // In this block we check if requested name szText is the same as examined field name. + // We check if compare is case insensitive. + if (bindingFlags & c_BindingFlags_IgnoreCase) + { + // If strings are not eqaul - continue + if(szText != NULL && hal_stricmp( fieldName, szText )) continue; + } + else // Case sensitive compare + { + // If strings are not eqaul - continue + if(szText != NULL && strcmp( fieldName, szText )) continue; + } + + idx.Set( td.Assembly(), i + tdR->sFields_First ); + + if(!fAllMatches) + { + CLR_RT_HeapBlock* hbObj; + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_FieldInfo)); + hbObj = top.Dereference(); + hbObj->SetReflection( idx ); + + NANOCLR_SET_AND_LEAVE(S_OK); + } + else if(pass == 1) + { + CLR_RT_HeapBlock* elem = (CLR_RT_HeapBlock*)top.DereferenceArray()->GetElement(iField); + CLR_RT_HeapBlock* hbObj; + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*elem, g_CLR_RT_WellKnownTypes.m_FieldInfo)); + hbObj = elem->Dereference(); + NANOCLR_CHECK_HRESULT(hbObj->SetReflection( idx )); + } + + iField++; + } + + if(bindingFlags & c_BindingFlags_DeclaredOnly) break; + } + while(td.SwitchToParent()); + + if(pass == 0) + { + if(!fAllMatches) NANOCLR_SET_AND_LEAVE(S_OK); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( top, iField, g_CLR_RT_WellKnownTypes.m_FieldInfo )); + } + } + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_Type::GetMethods( CLR_RT_StackFrame& stack, const char* szText, CLR_UINT32 bindingFlags, CLR_RT_HeapBlock* pParams, int iParams, bool fAllMatches ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_MethodDef_Instance inst; inst.Clear(); + CLR_RT_TypeDef_Instance td; + CLR_RT_TypeDef_Instance tdArg; + int iMethod; + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + CLR_RT_HeapBlock* hbType = stack.Arg0().Dereference(); + bool staticInstanceOnly = false; + + if(bindingFlags == c_BindingFlags_Default) bindingFlags = c_BindingFlags_DefaultLookup; + // in default lookup mode we want the static methods only from the instance not from the base classes + if(bindingFlags == c_BindingFlags_DefaultLookup) staticInstanceOnly = true; + + NANOCLR_CHECK_HRESULT(Library_corlib_native_System_RuntimeType::GetTypeDescriptor( *hbType, tdArg )); + + for(int pass = 0; pass < 2; pass++) + { + td = tdArg; + iMethod = 0; + bool isInstance = true; + + do + { + CLR_RT_Assembly* assm = td.m_assm; + const CLR_RECORD_TYPEDEF* tdR = td.m_target; + const CLR_RECORD_METHODDEF* md = assm->GetMethodDef( tdR->methods_First ); + int iTot = tdR->sMethods_Num + tdR->iMethods_Num + tdR->vMethods_Num; + int i; + + if (staticInstanceOnly) + { + if (isInstance) + { + // for the instance we use DefaultLookup + bindingFlags = c_BindingFlags_DefaultLookup; + // goto the else block in the next round + isInstance = false; + } + else + { + // otherwise (for the base classes) we use Instance+Public + bindingFlags = c_BindingFlags_Instance | c_BindingFlags_Public; + } + } + + for(i=0; iflags & CLR_RECORD_METHODDEF::MD_Static) + { + if((bindingFlags & c_BindingFlags_Static) == 0) continue; + } + else + { + if((bindingFlags & c_BindingFlags_Instance) == 0) continue; + } + + if((md->flags & CLR_RECORD_METHODDEF::MD_Scope_Mask) == CLR_RECORD_METHODDEF::MD_Scope_Public) + { + if((bindingFlags & c_BindingFlags_Public) == 0) continue; + } + else + { + if((bindingFlags & c_BindingFlags_NonPublic) == 0) continue; + } + + //--// + + if(md->flags & CLR_RECORD_METHODDEF::MD_Constructor) + { + if((bindingFlags & c_BindingFlags_CreateInstance) == 0) continue; + } + else + { + if((bindingFlags & c_BindingFlags_CreateInstance) != 0) continue; + + if(szText != NULL && !strcmp( assm->GetString( md->name ), szText ) == false) continue; + } + + if(pParams) + { + CLR_RT_SignatureParser parserLeft ; parserLeft .Initialize_MethodSignature( assm, md ); + CLR_RT_SignatureParser parserRight; parserRight.Initialize_Objects ( pParams, iParams, true ); + CLR_RT_SignatureParser::Element res; + + // + // Skip return value. + // + NANOCLR_CHECK_HRESULT(parserLeft.Advance( res )); + + if(CLR_RT_TypeSystem::MatchSignatureDirect( parserLeft, parserRight, true ) == false) continue; + } + + CLR_RT_MethodDef_Index idx; idx.Set( td.Assembly(), i + tdR->methods_First ); + CLR_RT_MethodDef_Instance inst2; inst2.InitializeFromIndex( idx ); + + if(fAllMatches) + { + if(pass==1) + { + CLR_RT_HeapBlock* elem = (CLR_RT_HeapBlock*)top.DereferenceArray()->GetElement(iMethod); + CLR_RT_HeapBlock* hbObj; + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*elem, g_CLR_RT_WellKnownTypes.m_MethodInfo)); + hbObj = elem->Dereference(); + NANOCLR_CHECK_HRESULT(hbObj->SetReflection( idx )); + } + + iMethod++; + } + else + { + CLR_RT_HeapBlock* hbObj; + + if(NANOCLR_INDEX_IS_VALID(inst)) + { + CLR_RT_SignatureParser parserLeft ; parserLeft .Initialize_MethodSignature( inst .m_assm, inst .m_target ); + CLR_RT_SignatureParser parserRight; parserRight.Initialize_MethodSignature( inst2.m_assm, inst2.m_target ); + + CLR_RT_SignatureParser::Element resLeft; + CLR_RT_SignatureParser::Element resRight; + + // + // Skip return value. + // + NANOCLR_CHECK_HRESULT(parserLeft.Advance ( resLeft )); + NANOCLR_CHECK_HRESULT(parserRight.Advance( resRight )); + + if(!pParams) + { + if(CLR_RT_TypeSystem::MatchSignatureDirect( parserLeft, parserRight, false ) == false) + { + //Two methods with different signatures, we cannot distinguish between the two. + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + //If they are identical signatures, the first one wins (subclass takes precendence) + continue; + } + else + { + bool fLeftBetterMatch = false; + bool fRightBetterMatch = false; + + while(parserLeft.Available() > 0) + { + NANOCLR_CHECK_HRESULT(parserLeft.Advance ( resLeft )); + NANOCLR_CHECK_HRESULT(parserRight.Advance( resRight )); + + bool fRightBetterMatchT = CLR_RT_TypeSystem::MatchSignatureElement( resLeft , resRight, true ); + bool fLeftBetterMatchT = CLR_RT_TypeSystem::MatchSignatureElement( resRight, resLeft , true ); + + //If fLeftBetterMatchT && fRightBetterMatchT, one is assignable from the other, they must be the same + // !fLeftBetterMatchT && !fRightBetterMatchT cannot happen, since this signature matches pParams + + if(fLeftBetterMatchT && !fRightBetterMatchT) fLeftBetterMatch = true; + if(!fLeftBetterMatchT && fRightBetterMatchT) fRightBetterMatch = true; + } + + if(fLeftBetterMatch && fRightBetterMatch) + { + //If the params match both Foo(Super, Sub) and Foo(Sub, Super) + //we cannot choose between the two + NANOCLR_SET_AND_LEAVE( CLR_E_INVALID_PARAMETER ); + } + + //If they are identical signatures, the first one wins (subclass takes precendence) + //Only if Right is better do we have a strictly better match + if(!fRightBetterMatch) continue; + + //Found a better match + } + } + + inst.InitializeFromIndex( idx ); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_MethodInfo)); + hbObj = top.Dereference(); + hbObj->SetReflection( inst ); + } + } + + if(bindingFlags & (c_BindingFlags_DeclaredOnly | c_BindingFlags_CreateInstance)) break; + } + while(td.SwitchToParent()); + + if(pass == 0) + { + if(!fAllMatches) NANOCLR_SET_AND_LEAVE(S_OK); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( top, iMethod, g_CLR_RT_WellKnownTypes.m_MethodInfo )); + } + } + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_ValueType.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_ValueType.cpp new file mode 100644 index 00000000..fe06deaf --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_ValueType.cpp @@ -0,0 +1,17 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +HRESULT Library_corlib_native_System_ValueType::Equals___BOOLEAN__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + stack.SetResult_Boolean( CLR_RT_HeapBlock::ObjectsEqual( stack.Arg0(), stack.Arg1(), false ) ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_WeakReference.cpp b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_WeakReference.cpp new file mode 100644 index 00000000..edc390bb --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/CorLib/corlib_native_System_WeakReference.cpp @@ -0,0 +1,181 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "CorLib.h" + + +void CLR_RT_HeapBlock_WeakReference::InsertInPriorityOrder() +{ + NATIVE_PROFILE_CLR_HEAP_PERSISTENCE(); + + this->Unlink(); // Remove from the list before looking for a spot, to avoid comparing against ourselves. + + g_CLR_RT_ExecutionEngine.m_weakReferences.LinkAtBack( this ); +} + +void CLR_RT_HeapBlock_WeakReference::Relocate() +{ + NATIVE_PROFILE_CLR_HEAP_PERSISTENCE(); + CLR_RT_HeapBlock_Node::Relocate(); + + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_targetDirect ); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_targetSerialized ); +} + +CLR_UINT32 CLR_RT_HeapBlock_WeakReference_Identity::ComputeCRC( const CLR_UINT8* ptr, CLR_UINT32 len ) const +{ + NATIVE_PROFILE_CLR_HEAP_PERSISTENCE(); + CLR_UINT32 hash; + + hash = SUPPORT_ComputeCRC( ptr , len , g_buildCRC ); + hash = SUPPORT_ComputeCRC( &m_selectorHash, sizeof(m_selectorHash), hash ); + hash = SUPPORT_ComputeCRC( &m_id , sizeof(m_id ), hash ); + + return hash; +} + +void CLR_RT_HeapBlock_WeakReference::RecoverObjects( CLR_RT_DblLinkedList& lstHeap ) +{ + NATIVE_PROFILE_CLR_HEAP_PERSISTENCE(); + NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster,hc,lstHeap) + { + CLR_RT_HeapBlock_Node* ptr = hc->m_payloadStart; + CLR_RT_HeapBlock_Node* end = hc->m_payloadEnd; + + while(ptr < end) + { + if(ptr->DataType() == DATATYPE_WEAKCLASS) + { + CLR_RT_HeapBlock_WeakReference* weak = (CLR_RT_HeapBlock_WeakReference*)ptr; + CLR_RT_HeapBlock* target = weak->m_targetSerialized; + + NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster,hc2,lstHeap) + { + CLR_RT_HeapBlock_Node* ptr2 = hc2->m_payloadStart; + CLR_RT_HeapBlock_Node* end2 = hc2->m_payloadEnd; + + if(ptr2 <= target && target < end2) + { + while(ptr2 < end2) + { + if(ptr2 == target) + { + CLR_RT_HeapBlock_Array* array = (CLR_RT_HeapBlock_Array*)ptr2; + + if(array->m_numOfElements == weak->m_identity.m_length) + { + if(weak->m_identity.m_crc == weak->m_identity.ComputeCRC( array->GetFirstElement(), weak->m_identity.m_length )) + { + weak->m_identity.m_flags |= CLR_RT_HeapBlock_WeakReference::WR_Restored; + + weak->InsertInPriorityOrder(); + + weak = NULL; + } + } + + break; + } + + ptr2 += ptr2->DataSize(); + } + + if(ptr2 < end2) break; + } + } + NANOCLR_FOREACH_NODE_END(); + + if(weak) + { + weak->ChangeDataType( DATATYPE_FREEBLOCK ); + } + } + + ptr += ptr->DataSize(); + } + } + NANOCLR_FOREACH_NODE_END(); +} + +HRESULT CLR_RT_HeapBlock_WeakReference::GetTarget( CLR_RT_HeapBlock& targetReference ) +{ + NATIVE_PROFILE_CLR_HEAP_PERSISTENCE(); + NANOCLR_HEADER(); + + targetReference.SetObjectReference( m_targetDirect ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT CLR_RT_HeapBlock_WeakReference::SetTarget( CLR_RT_HeapBlock& targetReference ) +{ + NATIVE_PROFILE_CLR_HEAP_PERSISTENCE(); + NANOCLR_HEADER(); + + // + // Only classes and value types can be associated with a weak reference! + // + if(targetReference.DataType() != DATATYPE_OBJECT) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + m_targetDirect = targetReference.Dereference(); + + InsertInPriorityOrder(); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_WeakReference::get_IsAlive___BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_WeakReference* weak; + + weak = (CLR_RT_HeapBlock_WeakReference*)stack.This(); FAULT_ON_NULL(weak); + + stack.SetResult_Boolean( weak->m_targetDirect != NULL ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_WeakReference::get_Target___OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_WeakReference* weak; + + weak = (CLR_RT_HeapBlock_WeakReference*)stack.This(); FAULT_ON_NULL(weak); + + NANOCLR_SET_AND_LEAVE(weak->GetTarget( stack.PushValue() )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_WeakReference::set_Target___VOID__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_WeakReference* weak; + + weak = (CLR_RT_HeapBlock_WeakReference*)stack.This(); FAULT_ON_NULL(weak); + + NANOCLR_SET_AND_LEAVE(weak->SetTarget( stack.Arg1() )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_corlib_native_System_WeakReference::_ctor___VOID__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_WeakReference* weak = (CLR_RT_HeapBlock_WeakReference*)stack.This(); FAULT_ON_NULL(weak); + + NANOCLR_SET_AND_LEAVE(weak->SetTarget( stack.Arg1() )); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/Core/CLR_RT_DblLinkedList.cpp b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_DblLinkedList.cpp new file mode 100644 index 00000000..c5ab184c --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_DblLinkedList.cpp @@ -0,0 +1,88 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +void CLR_RT_DblLinkedList::DblLinkedList_Initialize() +{ + NATIVE_PROFILE_CLR_CORE(); + m_first = Tail(); + m_null = NULL; + m_last = Head(); +} + +void CLR_RT_DblLinkedList::DblLinkedList_PushToCache() +{ + NATIVE_PROFILE_CLR_CORE(); + ValidateList(); + + while(true) + { + CLR_RT_HeapBlock_Node* node = ExtractFirstNode(); if(!node) break; + + g_CLR_RT_EventCache.Append_Node( node ); + } +} + +void CLR_RT_DblLinkedList::DblLinkedList_Release() +{ + NATIVE_PROFILE_CLR_CORE(); + ValidateList(); + + while(true) + { + CLR_RT_HeapBlock_Node* node = ExtractFirstNode(); if(!node) break; + + CLR_RT_Memory::Release( node ); + } +} + +int CLR_RT_DblLinkedList::NumOfNodes() +{ + NATIVE_PROFILE_CLR_CORE(); + ValidateList(); + + int num = 0; + + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Node,node,(*this)) + { + num++; + } + NANOCLR_FOREACH_NODE_END(); + + return num; +} + +void CLR_RT_DblLinkedList::Relocate() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_first ); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_last ); +} + +#if NANOCLR_VALIDATE_HEAP >= NANOCLR_VALIDATE_HEAP_2_DblLinkedList + +void CLR_RT_DblLinkedList::ValidateList() +{ + NATIVE_PROFILE_CLR_CORE(); + + if(m_null != NULL) NANOCLR_DEBUG_STOP(); + + CLR_RT_HeapBlock_Node* prev = Head(); + CLR_RT_HeapBlock_Node* node = prev->Next(); + + while(node) + { + if(node->Prev() != prev) NANOCLR_DEBUG_STOP(); + + prev = node; + node = prev->Next(); + } +} + +#endif + diff --git a/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock.cpp b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock.cpp new file mode 100644 index 00000000..94000db1 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock.cpp @@ -0,0 +1,2003 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" +#include + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +void CLR_RT_HeapBlock::InitializeToZero() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_Memory::ZeroFill( &m_data, this->DataSize() * sizeof(*this) - offsetof(CLR_RT_HeapBlock,m_data) ); +} + +//--//--//--//--//--// + +#if defined(NANOCLR_EMULATED_FLOATINGPOINT) + +HRESULT CLR_RT_HeapBlock::SetFloatIEEE754( const CLR_UINT32 arg ) +{ + + CLR_INT32 res; + CLR_UINT32 mantissa = ( arg & 0x007FFFFF) | 0x00800000; + int exponent = (int)((arg >> 23) & 0x000000FF) - 127; + + exponent -= (23 - CLR_RT_HeapBlock::HB_FloatShift); + + if(arg == 0) + { + res = 0; + } + else if(exponent <= -31) + { + res = 0; + + // + // Uncomment to produce an overflow exception for emulated floating points + // + // return CLR_E_OUT_OF_RANGE; + } + else if(exponent >= 31) + { + res = 0x7FFFFFFF; + + // + // Uncomment to produce an overflow exception for emulated floating points + // + // return CLR_E_OUT_OF_RANGE; + } + else + { + if(exponent > 0) + { + CLR_UINT64 tmpRes; + + tmpRes = ((CLR_UINT64)mantissa) << exponent; + + if(0 != (tmpRes >> 31)) + { + res = 0x7FFFFFFF; + + // + // Uncomment to produce an overflow exception for emulated floating points + // + // return CLR_E_OUT_OF_RANGE; + } + else + { + res = (CLR_UINT32)tmpRes; + } + } + else if(exponent < 0) res = mantissa >> (-exponent); + else res = mantissa; + } + + if(arg & 0x80000000) res = -res; + + SetFloat( res ); + + return S_OK; +} + +HRESULT CLR_RT_HeapBlock::SetDoubleIEEE754( const CLR_UINT64& arg ) +{ + + CLR_INT64 res; + CLR_UINT64 mantissa = ( arg & ULONGLONGCONSTANT(0x000FFFFFFFFFFFFF)) | ULONGLONGCONSTANT(0x0010000000000000); + int exponent = (int)((arg >> 52) & ULONGLONGCONSTANT(0x00000000000007FF)) - 1023; + + CLR_UINT64 mask = ULONGLONGCONSTANT(0xFFFFFFFFFFFFFFFF); + + exponent -= (52 - CLR_RT_HeapBlock::HB_DoubleShift); + + if(arg == 0) + { + res = 0; + } + else if(exponent <= -63) + { + res = 0; + + // + // Uncomment to produce an overflow exception for emulated floating points + // + // return CLR_E_OUT_OF_RANGE; + } + else if(exponent >= 63) + { + res = ULONGLONGCONSTANT(0x7FFFFFFFFFFFFFFF); + + // + // Uncomment to produce an overflow exception for emulated floating points + // + // return CLR_E_OUT_OF_RANGE; + } + else + { + if(exponent > 0) + { + mask <<= (63 - exponent); + + if(0 != (mask & mantissa)) + { + res = ULONGLONGCONSTANT(0x7FFFFFFFFFFFFFFF); + + // + // Uncomment to produce an overflow exception for emulated floating points + // + // return CLR_E_OUT_OF_RANGE; + } + else + { + res = mantissa << exponent; + } + } + else if(exponent < 0) res = mantissa >> (-exponent); + else res = mantissa; + } + + if(arg & ULONGLONGCONSTANT(0x8000000000000000)) res = -res; + + SetDouble( res ); + + return S_OK; +} + +#endif + + + +HRESULT CLR_RT_HeapBlock::EnsureObjectReference( CLR_RT_HeapBlock*& obj ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + switch(this->DataType()) + { + case DATATYPE_OBJECT: + case DATATYPE_BYREF: + { + obj = Dereference(); FAULT_ON_NULL(obj); + + #if defined(NANOCLR_APPDOMAINS) + if(obj->DataType() == DATATYPE_TRANSPARENT_PROXY) + { + NANOCLR_CHECK_HRESULT(obj->TransparentProxyValidate()); + obj = obj->TransparentProxyDereference(); FAULT_ON_NULL(obj); + } + #endif + switch(obj->DataType()) + { + case DATATYPE_CLASS : + case DATATYPE_VALUETYPE: + case DATATYPE_DATETIME: // Special case. + case DATATYPE_TIMESPAN: // Special case. + NANOCLR_SET_AND_LEAVE(S_OK); + + default: + // the remaining data types aren't to be handled + break; + } + } + break; + + case DATATYPE_DATETIME: // Special case. + case DATATYPE_TIMESPAN: // Special case. + obj = this; + NANOCLR_SET_AND_LEAVE(S_OK); + + default: + // the remaining data types aren't to be handled + break; + } + + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT CLR_RT_HeapBlock::SetReflection( const CLR_RT_ReflectionDef_Index& reflex ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + m_id.raw = CLR_RT_HEAPBLOCK_RAW_ID(DATATYPE_REFLECTION,0,1); + m_data.reflection = reflex; + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT CLR_RT_HeapBlock::SetReflection( const CLR_RT_Assembly_Index& assm ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + m_id.raw = CLR_RT_HEAPBLOCK_RAW_ID(DATATYPE_REFLECTION,0,1); + m_data.reflection.m_kind = REFLECTION_ASSEMBLY; + m_data.reflection.m_levels = 0; + m_data.reflection.m_data.m_assm = assm; + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT CLR_RT_HeapBlock::SetReflection( const CLR_RT_TypeSpec_Index& sig ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_TypeDescriptor desc; + + NANOCLR_CHECK_HRESULT(desc.InitializeFromTypeSpec( sig )); + + m_id.raw = CLR_RT_HEAPBLOCK_RAW_ID(DATATYPE_REFLECTION,0,1); + m_data.reflection = desc.m_reflex; + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock::SetReflection( const CLR_RT_TypeDef_Index& cls ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + m_id.raw = CLR_RT_HEAPBLOCK_RAW_ID(DATATYPE_REFLECTION,0,1); + m_data.reflection.m_kind = REFLECTION_TYPE; + m_data.reflection.m_levels = 0; + m_data.reflection.m_data.m_type = cls; + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT CLR_RT_HeapBlock::SetReflection( const CLR_RT_FieldDef_Index& fd ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + m_id.raw = CLR_RT_HEAPBLOCK_RAW_ID(DATATYPE_REFLECTION,0,1); + m_data.reflection.m_kind = REFLECTION_FIELD; + m_data.reflection.m_levels = 0; + m_data.reflection.m_data.m_field = fd; + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT CLR_RT_HeapBlock::SetReflection( const CLR_RT_MethodDef_Index& md ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_MethodDef_Instance inst; + + if(inst.InitializeFromIndex( md ) == false) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + m_id.raw = CLR_RT_HEAPBLOCK_RAW_ID(DATATYPE_REFLECTION,0,1); + m_data.reflection.m_kind = (inst.m_target->flags & CLR_RECORD_METHODDEF::MD_Constructor) ? REFLECTION_CONSTRUCTOR : REFLECTION_METHOD; + m_data.reflection.m_levels = 0; + m_data.reflection.m_data.m_method = md; + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock::SetObjectCls( const CLR_RT_TypeDef_Index& cls ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Instance inst; + + if(inst.InitializeFromIndex( cls ) == false) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + + m_data.objectHeader.cls = cls; + m_data.objectHeader.lock = NULL; + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT CLR_RT_HeapBlock::InitializeArrayReference( CLR_RT_HeapBlock& ref, int index ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* array; + + if(ref.DataType() != DATATYPE_OBJECT) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + array = ref.DereferenceArray(); FAULT_ON_NULL(array); + + if(array->DataType() != DATATYPE_SZARRAY) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + if(index < 0 || index >= (CLR_INT32)array->m_numOfElements) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INDEX_OUT_OF_RANGE); + } + + InitializeArrayReferenceDirect( *array, index ); + + NANOCLR_NOCLEANUP(); +} + +void CLR_RT_HeapBlock::InitializeArrayReferenceDirect( CLR_RT_HeapBlock_Array& array, int index ) +{ + NATIVE_PROFILE_CLR_CORE(); + m_id.raw = CLR_RT_HEAPBLOCK_RAW_ID(DATATYPE_ARRAY_BYREF,0,1); + m_data.arrayReference.array = &array; + m_data.arrayReference.index = index; +} + +void CLR_RT_HeapBlock::FixArrayReferenceForValueTypes() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock_Array* array = m_data.arrayReference.array; + + // + // ValueTypes are implemented as pointers to objects, + // so getting an array reference to a ValueType has to be treated like assigning a pointer! + // + // DateTime and TimeSpan are optimized as primitive types, + // so getting an array reference to them is like getting a reference to them. + // + switch(array->m_typeOfElement) + { + case DATATYPE_VALUETYPE: + this->SetReference( *(CLR_RT_HeapBlock*)array->GetElement( m_data.arrayReference.index ) ); + break; + + case DATATYPE_DATETIME: + case DATATYPE_TIMESPAN: + m_id.raw = CLR_RT_HEAPBLOCK_RAW_ID(DATATYPE_BYREF,0,1); + m_data.objectReference.ptr = (CLR_RT_HeapBlock*)array->GetElement( m_data.arrayReference.index ); + break; + } +} + +HRESULT CLR_RT_HeapBlock::LoadFromReference( CLR_RT_HeapBlock& ref ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock tmp; + CLR_RT_HeapBlock* obj; + CLR_DataType dt = ref.DataType(); + + if(dt == DATATYPE_ARRAY_BYREF) + { + CLR_RT_HeapBlock_Array* array = ref.m_data.arrayReference.array; FAULT_ON_NULL(array); + CLR_UINT8* src = array->GetElement( ref.m_data.arrayReference.index ); + CLR_UINT32 size = array->m_sizeOfElement; + + if(!array->m_fReference) + { + CLR_UINT32 second = 0; + CLR_UINT32 first; + + SetDataId( CLR_RT_HEAPBLOCK_RAW_ID(array->m_typeOfElement,0,1) ); + + if (size == 4) { first = ((CLR_UINT32*)src)[ 0 ]; } + else if(size == 8) { first = ((CLR_UINT32*)src)[ 0 ]; second = ((CLR_UINT32*)src)[ 1 ]; } + else if(size == 1) { first = ((CLR_UINT8 *)src)[ 0 ]; } + else { first = ((CLR_UINT16*)src)[ 0 ]; } + + ((CLR_UINT32*)&NumericByRef())[ 0 ] = first; + ((CLR_UINT32*)&NumericByRef())[ 1 ] = second; + + NANOCLR_SET_AND_LEAVE(S_OK); + } + + // + // It's a pointer to a full CLR_RT_HeapBlock. + // + obj = (CLR_RT_HeapBlock*)src; + } + else if(dt == DATATYPE_BYREF) + { + obj = ref.Dereference(); FAULT_ON_NULL(obj); + + if(obj->DataType() == DATATYPE_VALUETYPE) + { + tmp.SetObjectReference( obj ); + + obj = &tmp; + } + } + else if(c_CLR_RT_DataTypeLookup[ dt ].m_flags & CLR_RT_DataTypeLookup::c_Direct) + { + obj = &ref; + + if(dt == DATATYPE_OBJECT) + { + CLR_RT_HeapBlock* objT = ref.Dereference(); + + if(objT && objT->IsBoxed()) + { + CLR_RT_TypeDef_Instance inst; + if (objT->DataType() != DATATYPE_VALUETYPE) { NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); } + + if(!inst.InitializeFromIndex( objT->ObjectCls() )) { NANOCLR_SET_AND_LEAVE(CLR_E_TYPE_UNAVAILABLE); } + + if(inst.m_target->dataType != DATATYPE_VALUETYPE) // It's a boxed primitive/enum type. + { + obj = &objT[ 1 ]; + } + } + } + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + if(obj->IsAValueType()) + { + NANOCLR_SET_AND_LEAVE(g_CLR_RT_ExecutionEngine.CloneObject( *this, *obj )); + } + + this->Assign( *obj ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock::StoreToReference( CLR_RT_HeapBlock& ref, int size ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* obj; + CLR_DataType dt = ref.DataType(); + + if(dt == DATATYPE_ARRAY_BYREF) + { + CLR_RT_HeapBlock_Array* array = ref.m_data.arrayReference.array; FAULT_ON_NULL(array); + CLR_UINT8* dst = array->GetElement( ref.m_data.arrayReference.index ); + + if(!array->m_fReference) + { + CLR_INT32 sizeArray = array->m_sizeOfElement; + + // + // Cannot copy NULL reference to a primitive type array. + // + obj = FixBoxingReference(); FAULT_ON_NULL(obj); + + if(size == -1) + { + //size == -1 tells StoreToReference to allow the value 'this' to have more precision than the dest + //array. This fixes the following bug. + // : conv.u1 + // : stobj [mscorlib]System.Byte + // The conv.u1 will convert the top of the eval stack to a u1. But since the eval stack is required + // to contain at least 4 byte values, this heap block will be promoted to an I4. + // stobj ignores the type token (System.Byte) and calls Reassign, which calls StoreToReference. + + if(c_CLR_RT_DataTypeLookup[ this->DataType() ].m_sizeInBytes < sizeArray) + { + //Not enough precision here. + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + +#if defined(_DEBUG) + { + CLR_DataType dtElem = (CLR_DataType)array->m_typeOfElement; + CLR_RT_HeapBlock blk; blk.Assign( *this ); + + NANOCLR_CHECK_HRESULT(blk.Convert( dtElem, false, (c_CLR_RT_DataTypeLookup[ dtElem ].m_flags & CLR_RT_DataTypeLookup::c_Signed) == 0)); + + switch(sizeArray) + { + case 1: _ASSERTE(blk.NumericByRefConst().u1 == this->NumericByRefConst().u1); break; + case 2: _ASSERTE(blk.NumericByRefConst().u2 == this->NumericByRefConst().u2); break; + case 4: _ASSERTE(blk.NumericByRefConst().u4 == this->NumericByRefConst().u4); break; + case 8: _ASSERTE(blk.NumericByRefConst().u8 == this->NumericByRefConst().u8); break; + } + } +#endif + } + else if(size == 0) + { + if(obj->DataType() != array->m_typeOfElement) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + } + else + { + if(size != sizeArray) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + } + + CLR_UINT32 first = ((CLR_UINT32*)&obj->NumericByRef())[ 0 ]; + CLR_UINT32 second = ((CLR_UINT32*)&obj->NumericByRef())[ 1 ]; + + if (sizeArray == 4) { ((CLR_UINT32*)dst)[ 0 ] = (CLR_UINT32)first; } + else if(sizeArray == 8) { ((CLR_UINT32*)dst)[ 0 ] = (CLR_UINT32)first; ((CLR_UINT32*)dst)[ 1 ] = (CLR_UINT32)second; } + else if(sizeArray == 1) { ((CLR_UINT8 *)dst)[ 0 ] = (CLR_UINT8 )first; } + else { ((CLR_UINT16*)dst)[ 0 ] = (CLR_UINT16)first; } + + NANOCLR_SET_AND_LEAVE(S_OK); + } + else + { + // + // If the source is not null, make sure the types are compatible. + // + if(this->DataType() == DATATYPE_OBJECT && this->Dereference()) + { + CLR_RT_TypeDescriptor descSrc; + CLR_RT_TypeDescriptor descDst; + CLR_RT_TypeDescriptor descDstSub; + + NANOCLR_CHECK_HRESULT(descSrc.InitializeFromObject( *this )); + NANOCLR_CHECK_HRESULT(descDst.InitializeFromObject( *array )); descDst.GetElementType( descDstSub ); + + if(CLR_RT_ExecutionEngine::IsInstanceOf( descSrc, descDstSub ) == false) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + } + + obj = (CLR_RT_HeapBlock*)dst; + + NANOCLR_SET_AND_LEAVE(obj->Reassign( *this )); + } + } + else if(dt == DATATYPE_BYREF) + { + obj = ref.Dereference(); FAULT_ON_NULL(obj); + + if(obj->DataType() == DATATYPE_VALUETYPE) + { + NANOCLR_SET_AND_LEAVE(ref.Reassign( *this )); + } + } + else if(c_CLR_RT_DataTypeLookup[ dt ].m_flags & CLR_RT_DataTypeLookup::c_Direct) + { + obj = &ref; + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + obj->Assign( *this ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock::Reassign( const CLR_RT_HeapBlock& value ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* obj; + CLR_RT_HeapBlock ref; + + if(this->DataType() == DATATYPE_BYREF) + { + obj = this->Dereference(); FAULT_ON_NULL(obj); + + // + // Real value types can be passed as references. + // + if(obj->DataType() == DATATYPE_VALUETYPE) + { + ref.SetObjectReference( obj ); + + obj = &ref; + } + + NANOCLR_SET_AND_LEAVE(obj->Reassign( value )); + } + else if(value.DataType() == DATATYPE_BYREF) + { + obj = value.Dereference(); FAULT_ON_NULL(obj); + + // + // Real value types can be passed as references. + // + if(obj->DataType() == DATATYPE_VALUETYPE) + { + ref.SetObjectReference( obj ); + + obj = &ref; + } + + NANOCLR_SET_AND_LEAVE(this->Reassign( *obj )); + } + else if(this->DataType() == DATATYPE_ARRAY_BYREF) + { + NANOCLR_CHECK_HRESULT(ref.LoadFromReference( *this )); + NANOCLR_CHECK_HRESULT(ref.Reassign ( value )); + NANOCLR_SET_AND_LEAVE(ref.StoreToReference ( *this, -1 )); + } + else if(value.DataType() == DATATYPE_ARRAY_BYREF) + { + _ASSERTE( false ); //not tested + + CLR_RT_HeapBlock valueT; valueT.Assign( value ); + + NANOCLR_CHECK_HRESULT(ref.LoadFromReference( valueT )); + NANOCLR_SET_AND_LEAVE(this->Reassign ( ref )); + } + else + { + bool fDestination = this->IsAValueType(); + bool fSource = value.IsAValueType(); + + if(fSource != fDestination) + { + // For value type objects we don't care if the source item is boxed because + // CopyValueType will take care of the boxing/unboxing + if(fDestination != value.IsAReferenceOfThisType(DATATYPE_VALUETYPE)) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + } + + if(fDestination) + { + NANOCLR_SET_AND_LEAVE(g_CLR_RT_ExecutionEngine.CopyValueType( this->Dereference(), value.Dereference() )); + } + + this->Assign( value ); + } + + NANOCLR_NOCLEANUP(); +} + +void CLR_RT_HeapBlock::AssignAndPinReferencedObject( const CLR_RT_HeapBlock& value ) +{ + // This is very special case that we have local variable with pinned attribute in metadata. + // This code is called only if "fixed" keyword is present in the managed code. Executed on assignment to "fixed" pointer. + // First check if there is object referenced by the local var. We unpin it, since the reference is replaced. + if ((m_data.objectReference.ptr != NULL && m_id.type.dataType == DATATYPE_ARRAY_BYREF) || m_id.type.dataType == DATATYPE_BYREF) + { + // Unpin the object that has been pointed by local variable. + m_data.objectReference.ptr->Unpin(); + } + + // Move the data. + m_data = value.m_data; + + // Leave the same logic as in AssignAndPreserveType + if(DataType() > DATATYPE_LAST_PRIMITIVE_TO_PRESERVE) + { + m_id.type.dataType = value.m_id.type.dataType; + m_id.type.size = value.m_id.type.size; + // We take new flags, but preserve "pinned" attribute + m_id.type.flags = m_id.type.flags | HB_Pinned; + } + + // Pin the object referenced by local variable. + if ((m_data.objectReference.ptr != NULL && m_id.type.dataType == DATATYPE_ARRAY_BYREF) || m_id.type.dataType == DATATYPE_BYREF) + { + m_data.objectReference.ptr->Pin(); + } +} + + +HRESULT CLR_RT_HeapBlock::PerformBoxingIfNeeded() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + + // we need to box the optimized value types... + bool fBox = (c_CLR_RT_DataTypeLookup[ this->DataType() ].m_flags & CLR_RT_DataTypeLookup::c_OptimizedValueType) != 0; + + // ... but also the value types under object types + if(!fBox && this->DataType() == DATATYPE_OBJECT) + { + CLR_RT_HeapBlock* src = this->Dereference(); + + if(src && src->DataType() == DATATYPE_VALUETYPE && !src->IsBoxed()) + { + fBox = true; + } + } + + if(fBox) + { + CLR_RT_TypeDescriptor desc; + + NANOCLR_CHECK_HRESULT(desc.InitializeFromObject( *this )); + + NANOCLR_CHECK_HRESULT(PerformBoxing( desc.m_handlerCls )); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock::PerformBoxing( const CLR_RT_TypeDef_Instance& cls ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock tmp; + CLR_RT_HeapBlock* obj = this; + CLR_DataType dt = obj->DataType(); + + // + // System.DateTime and System.TimeSpan are real value types, so sometimes they are passed by reference. + // + if(dt == DATATYPE_BYREF) + { + obj = obj->Dereference(); FAULT_ON_NULL(obj); + dt = obj->DataType(); + + // + // Real value types can be passed as references. + // + if(dt == DATATYPE_VALUETYPE) + { + tmp.SetObjectReference( obj ); obj = &tmp; + + dt = DATATYPE_OBJECT; + } + } + + { + CLR_DataType dataType = (CLR_DataType)cls.m_target->dataType; + const CLR_RT_DataTypeLookup& dtl = c_CLR_RT_DataTypeLookup[ dataType ]; + + if(dtl.m_flags & CLR_RT_DataTypeLookup::c_OptimizedValueType) + { + CLR_RT_HeapBlock* ptr = g_CLR_RT_ExecutionEngine.ExtractHeapBlocksForClassOrValueTypes( DATATYPE_VALUETYPE, HB_Boxed, cls, 2 ); FAULT_ON_NULL(ptr); + + switch(dataType) + { + case DATATYPE_DATETIME: // Special case. + case DATATYPE_TIMESPAN: // Special case. + dataType = DATATYPE_I8; + break; + + default: + // the remaining data types aren't to be handled + break; + } + + ptr[ 1 ].SetDataId ( CLR_RT_HEAPBLOCK_RAW_ID(dataType,0,1) ); + ptr[ 1 ].AssignData( *this ); + + this->SetObjectReference( ptr ); + } + else if(dt == DATATYPE_OBJECT) + { + CLR_RT_HeapBlock* ptr = this->Dereference(); + + if(ptr->IsBoxed() || ptr->DataType() != DATATYPE_VALUETYPE) + { + NANOCLR_SET_AND_LEAVE(S_FALSE); // Don't box twice... + } + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.CloneObject( *this, *ptr )); + + this->Dereference()->Box(); + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + } + + NANOCLR_NOCLEANUP(); +} + +/******************************************************************************************* +* Thefunction CLR_RT_HeapBlock::PerformUnboxing is used during processing of unbox.any IL instruction. +* Example +* unbox.any [mscorlib]System.Int32 +* unbox.any takes the value at the top of evaluation stack and performs unboxing into the type +* specified after the instruction. In this case the type is [mscorlib]System.Int32. +* Function parameters: +* 1. this - Heap block at the top of evaluation stack. +* 2. cls - Runtime Type Definition of the type specified after instruction. +* The functoin takes the object pointed by top of ev. stack. Then it does 3 operatioins: +* 1. Dereferences the object +* 2. Validates the type of data kept by object corresponds to type in cls. +* 3. Moves de-referenced date to top of evaluation stack. +*******************************************************************************************/ + +HRESULT CLR_RT_HeapBlock::PerformUnboxing( const CLR_RT_TypeDef_Instance& cls ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* src; + + if(this->DataType() != DATATYPE_OBJECT) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + // Finds the object that keeps the boxed type. + src = this->Dereference(); FAULT_ON_NULL(src); + + // Validates that src keeps something boxed and the boxed value is VALUE type. + if(src->IsBoxed() == false || src->DataType() != DATATYPE_VALUETYPE) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + // Validates the type of data kept by object corresponds to type in cls. + // If typedef indexes are the same, then skip and go to assigment of objects. + if(src->ObjectCls().m_data != cls.m_data) + { + // The typedef indexes are different, but src and cls may have identical basic data type. + // Need to check it. If identical - the unboxing is allowed. + // This "if" compares underlying type in object and cls. Should be equal in order to continue. + if ( !( src->DataSize() > 1 && ( src[ 1 ].DataType() == cls.m_target->dataType ) ) ) + { + // No luck. The types in src object and specified by cls are different. Need to throw exceptioin. + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_CAST); + } + } + + if(cls.m_target->dataType == DATATYPE_VALUETYPE) + { + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.CloneObject( *this, *this )); + + this->Dereference()->Unbox(); + } + else // It's a boxed primitive/enum type. + { + this->Assign( src[ 1 ] ); + + this->ChangeDataType( cls.m_target->dataType ); + } + + NANOCLR_NOCLEANUP(); +} + +CLR_RT_HeapBlock* CLR_RT_HeapBlock::FixBoxingReference() +{ + NATIVE_PROFILE_CLR_CORE(); + // + // Not boxed, nothing to do. + // + if(this->DataType() == DATATYPE_OBJECT) + { + CLR_RT_HeapBlock* src = this->Dereference(); if(!src) return src; + + if(src->DataType() == DATATYPE_VALUETYPE && src->IsBoxed()) + { + CLR_RT_TypeDef_Instance inst; + + if(!inst.InitializeFromIndex( src->ObjectCls() )) return NULL; + + if(inst.m_target->dataType != DATATYPE_VALUETYPE) // It's a boxed primitive/enum type. + { + return &src[ 1 ]; + } + } + } + + return this; +} + +//--// + +bool CLR_RT_HeapBlock::IsZero() const +{ + NATIVE_PROFILE_CLR_CORE(); + switch(DataType()) + { + case DATATYPE_OBJECT: return (m_data.objectReference.ptr == NULL); + + case DATATYPE_I8 : + case DATATYPE_U8 : return (m_data.numeric.u8 == 0); + + + case DATATYPE_R4 : return (m_data.numeric.r4 == 0); + case DATATYPE_R8 : return (m_data.numeric.r8 == 0); + + + default : return (m_data.numeric.u4 == 0); + } +} + +//--// + +void CLR_RT_HeapBlock::Promote() +{ + NATIVE_PROFILE_CLR_CORE(); + + switch(DataType()) + { + case DATATYPE_I1 : m_id.type.dataType = DATATYPE_I4; m_data.numeric.s4 = (CLR_INT32 )m_data.numeric.s1; break; + + case DATATYPE_I2 : m_id.type.dataType = DATATYPE_I4; m_data.numeric.s4 = (CLR_INT32 )m_data.numeric.s2; break; + + case DATATYPE_BOOLEAN: + case DATATYPE_U1 : m_id.type.dataType = DATATYPE_I4; m_data.numeric.u4 = (CLR_UINT32)m_data.numeric.u1; break; + + case DATATYPE_CHAR : + case DATATYPE_U2 : m_id.type.dataType = DATATYPE_I4; m_data.numeric.u4 = (CLR_UINT32)m_data.numeric.u2; break; + + default: + // this data type is not to be promoted + break; + } +} + +//--// + +CLR_UINT32 CLR_RT_HeapBlock::GetHashCode( CLR_RT_HeapBlock* ptr, bool fRecurse, CLR_UINT32 crc = 0 ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(!ptr) return 0; + + switch(ptr->DataType()) + { + case DATATYPE_OBJECT: + crc = GetHashCode( ptr->Dereference(), fRecurse, crc ); + break; + + case DATATYPE_STRING: + { + const char* szText = ptr->StringText(); + + crc = SUPPORT_ComputeCRC( szText, (int)hal_strlen_s( szText ), crc ); + } + break; + + case DATATYPE_CLASS: + case DATATYPE_VALUETYPE: + if(fRecurse) + { + CLR_RT_TypeDef_Instance cls; cls.InitializeFromIndex( ptr->ObjectCls() ); + int totFields = cls.CrossReference().m_totalFields; + + if (totFields > 0) + { + while(totFields-- > 0) + { + crc = GetHashCode( ++ptr, false, crc ); + } + } + else + { + crc = SUPPORT_ComputeCRC( &ptr, sizeof(ptr), crc ); + } + } + break; + + case DATATYPE_DELEGATE_HEAD: + { + CLR_RT_HeapBlock_Delegate* dlg = (CLR_RT_HeapBlock_Delegate*)ptr; + const CLR_RT_MethodDef_Index& ftn = dlg->DelegateFtn(); + + crc = GetHashCode( &dlg->m_object, false, crc ); + + crc = SUPPORT_ComputeCRC( &ftn, sizeof(ftn), crc ); + } + break; + + case DATATYPE_OBJECT_TO_EVENT: + { + CLR_RT_ObjectToEvent_Source* evtSrc = (CLR_RT_ObjectToEvent_Source*)ptr; + + crc = GetHashCode(evtSrc->m_eventPtr, false, crc); + crc = GetHashCode(evtSrc->m_objectPtr, false, crc); + } + break; + + default: + crc = SUPPORT_ComputeCRC( &ptr->DataByRefConst(), ptr->GetAtomicDataUsedBytes(), crc ); + break; + } + + return crc; +} + +CLR_UINT32 CLR_RT_HeapBlock::GetAtomicDataUsedBytes() const + +{ + switch( DataType() ) + { + case DATATYPE_BOOLEAN : // Fall through, hashDataSize = 1 + case DATATYPE_U1 : // Fall through, hashDataSize = 1 + case DATATYPE_CHAR : return 1; + + case DATATYPE_I2 : // Fall through, hashDataSize = 2 + case DATATYPE_U2 : return 2; break; + + case DATATYPE_I4 : + case DATATYPE_U4 : + case DATATYPE_R4 : return 4; break; + + case DATATYPE_I8 : // Fall through, hashDataSize = 8 + case DATATYPE_U8 : // Fall through, hashDataSize = 8 + case DATATYPE_R8 : // Fall through, hashDataSize = 8 + case DATATYPE_DATETIME: // Fall through, hashDataSize = 8 + case DATATYPE_TIMESPAN: return 8; break; + + // Default full size of CLR_RT_HeapBlock_AtomicData + default : return sizeof(CLR_RT_HeapBlock_AtomicData); + } + // The same as default. This is never reached, but I put it to avoid potential compiler warning. + return sizeof(CLR_RT_HeapBlock_AtomicData); +} + +bool CLR_RT_HeapBlock::ObjectsEqual( const CLR_RT_HeapBlock& pArgLeft, const CLR_RT_HeapBlock& pArgRight, bool fSameReference ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(&pArgLeft == &pArgRight) return true; + + if(pArgLeft.DataType() == pArgRight.DataType()) + { + switch(pArgLeft.DataType()) + { + case DATATYPE_VALUETYPE: + if(pArgLeft.ObjectCls().m_data == pArgRight.ObjectCls().m_data) + { + const CLR_RT_HeapBlock* objLeft = &pArgLeft ; + const CLR_RT_HeapBlock* objRight = &pArgRight; + CLR_UINT32 num = pArgLeft.DataSize(); + + while(--num) + { + if(ObjectsEqual( *++objLeft, *++objRight, false ) == false) return false; + } + + return true; + } + break; + +#if defined(NANOCLR_APPDOMAINS) + case DATATYPE_TRANSPARENT_PROXY: +#endif + case DATATYPE_OBJECT: + { + CLR_RT_HeapBlock* objLeft = pArgLeft .Dereference(); + CLR_RT_HeapBlock* objRight = pArgRight.Dereference(); + if(objLeft == objRight) return true; + + if(objLeft && objRight) + { + if(!fSameReference || (objLeft->DataType() == DATATYPE_REFLECTION)) return ObjectsEqual( *objLeft, *objRight, false ); + } + } + break; + + case DATATYPE_SZARRAY: + if(fSameReference == false) + { + _ASSERTE(false); //can this code path ever be executed? + + CLR_RT_HeapBlock_Array* objLeft = (CLR_RT_HeapBlock_Array*)&pArgLeft; + CLR_RT_HeapBlock_Array* objRight = (CLR_RT_HeapBlock_Array*)&pArgRight; + + if(objLeft->m_numOfElements == objRight->m_numOfElements && + objLeft->m_sizeOfElement == objRight->m_sizeOfElement && + objLeft->m_typeOfElement == objRight->m_typeOfElement ) + { + if(!objLeft->m_fReference) + { + if(memcmp( objLeft->GetFirstElement(), objRight->GetFirstElement(), objLeft->m_numOfElements * objLeft->m_sizeOfElement ) == 0) + { + return true; + } + } + } + } + break; + case DATATYPE_REFLECTION: + if(pArgLeft.SameHeader( pArgRight )) return true; + break; + default: + if(fSameReference == false) + { + const CLR_RT_DataTypeLookup& dtl = c_CLR_RT_DataTypeLookup[ pArgLeft.DataType() ]; + + if((dtl.m_flags & CLR_RT_DataTypeLookup::c_Reference) == 0) + { + CLR_UINT32 size = (dtl.m_sizeInBits + 7) / 8; + + if(memcmp( &pArgLeft.DataByRefConst(), &pArgRight.DataByRefConst(), size ) == 0) + { + return true; + } + } + } + break; + } + } + + return false; +} + +//--// + +static const CLR_RT_HeapBlock* FixReflectionForType( const CLR_RT_HeapBlock& src, CLR_RT_HeapBlock& tmp ) +{ + NATIVE_PROFILE_CLR_CORE(); + const CLR_RT_ReflectionDef_Index& rd = src.ReflectionDataConst(); + + if(rd.m_kind == REFLECTION_TYPE) + { + CLR_RT_TypeDef_Instance inst; + CLR_UINT32 levels; + + if(inst.InitializeFromReflection( rd, &levels ) && levels == 0) + { + tmp.Assign( src ); + + CLR_RT_ReflectionDef_Index& rd2 = tmp.ReflectionData(); + + rd2.InitializeFromHash( inst.CrossReference().m_hash ); + + return &tmp; + } + } + + return &src; +} + +//--// + +static inline int CompareValues_Numeric( CLR_INT32 left, CLR_INT32 right ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(left > right) return 1; + if(left < right) return -1; + /**************/ return 0; +} + +static inline int CompareValues_Numeric( CLR_UINT32 left, CLR_UINT32 right ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(left > right) return 1; + if(left < right) return -1; + /**************/ return 0; +} + +static int CompareValues_Numeric( const CLR_INT64 left, const CLR_INT64 right ) +{ + NATIVE_PROFILE_CLR_CORE(); + + if(left > right) return 1; + if(left < right) return -1; + /**************/ return 0; +} + +static int CompareValues_Numeric( const CLR_UINT64 left, const CLR_UINT64 right ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(left > right) return 1; + if(left < right) return -1; + /**************/ return 0; +} + +static int CompareValues_Numeric( const CLR_RT_HeapBlock& left, const CLR_RT_HeapBlock& right, bool fSigned, int bytes ) +{ + NATIVE_PROFILE_CLR_CORE(); + + switch(bytes) + { + case 4: + if(fSigned) return CompareValues_Numeric( (CLR_INT32 )left.NumericByRefConst().s4, (CLR_INT32 )right.NumericByRefConst().s4 ); + else return CompareValues_Numeric( (CLR_UINT32)left.NumericByRefConst().u4, (CLR_UINT32)right.NumericByRefConst().u4 ); + + case 8: + if(fSigned) return CompareValues_Numeric( (CLR_INT64 )left.NumericByRefConst().s8, (CLR_INT64 )right.NumericByRefConst().s8 ); + else return CompareValues_Numeric( (CLR_UINT64)left.NumericByRefConst().u8, (CLR_UINT64)right.NumericByRefConst().u8 ); + + case 2: + if(fSigned) return CompareValues_Numeric( (CLR_INT32 )left.NumericByRefConst().s2, (CLR_INT32 )right.NumericByRefConst().s2 ); + else return CompareValues_Numeric( (CLR_UINT32)left.NumericByRefConst().u2, (CLR_UINT32)right.NumericByRefConst().u2 ); + + case 1: + if(fSigned) return CompareValues_Numeric( (CLR_INT32 )left.NumericByRefConst().s1, (CLR_INT32 )right.NumericByRefConst().s1 ); + else return CompareValues_Numeric( (CLR_UINT32)left.NumericByRefConst().u1, (CLR_UINT32)right.NumericByRefConst().u1 ); + + default: + return -1; + } +} + + + +static inline int CompareValues_Pointers( const CLR_RT_HeapBlock* left, const CLR_RT_HeapBlock* right ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(left > right) return 1; + if(left < right) return -1; + /**************/ return 0; +} + + +CLR_INT32 CLR_RT_HeapBlock::Compare_Values( const CLR_RT_HeapBlock& left, const CLR_RT_HeapBlock& right, bool fSigned ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_DataType leftDataType = left .DataType(); + CLR_DataType rightDataType = right.DataType(); + + if(leftDataType == rightDataType) + { + switch(leftDataType) + { + #if defined(NANOCLR_APPDOMAINS) + case DATATYPE_TRANSPARENT_PROXY: + #endif + case DATATYPE_OBJECT: + case DATATYPE_BYREF: + { + CLR_RT_HeapBlock* leftObj = left .Dereference(); + CLR_RT_HeapBlock* rightObj = right.Dereference(); + + if(!leftObj) + { + return !rightObj ? 0 : -1; // NULL references always compare smaller than non-NULL ones. + } + else if(!rightObj) + { + return 1; // NULL references always compare smaller than non-NULL ones. + } + + return Compare_Values( *leftObj, *rightObj, fSigned ); + } + + case DATATYPE_STRING: + { + CLR_RT_HeapBlock_String* leftStr = (CLR_RT_HeapBlock_String*)&left ; + CLR_RT_HeapBlock_String* rightStr = (CLR_RT_HeapBlock_String*)&right; + + return strcmp( leftStr->StringText(), rightStr->StringText() ); + } + + case DATATYPE_DELEGATELIST_HEAD: + { + CLR_RT_HeapBlock_Delegate_List* leftDlg = (CLR_RT_HeapBlock_Delegate_List*)&left ; + CLR_RT_HeapBlock_Delegate_List* rightDlg = (CLR_RT_HeapBlock_Delegate_List*)&right; + CLR_RT_HeapBlock* leftPtr = leftDlg ->GetDelegates(); + CLR_RT_HeapBlock* rightPtr = rightDlg->GetDelegates(); + CLR_UINT32 leftLen = leftDlg ->m_length; + CLR_UINT32 rightLen = rightDlg->m_length; + + while(leftLen > 0 && rightLen > 0) + { + int res = CLR_RT_HeapBlock::Compare_Values( *leftPtr++, *rightPtr++, fSigned ); if(res) return res; + + leftLen--; + rightLen--; + } + + if(!leftLen) + { + return !rightLen ? 0 : -1; // NULL references always compare smaller than non-NULL ones. + } + else // rightLen != 0 for sure. + { + return 1; // NULL references always compare smaller than non-NULL ones. + } + } + + case DATATYPE_DELEGATE_HEAD: + { + CLR_RT_HeapBlock_Delegate* leftDlg = (CLR_RT_HeapBlock_Delegate*)&left ; + CLR_RT_HeapBlock_Delegate* rightDlg = (CLR_RT_HeapBlock_Delegate*)&right; + CLR_UINT32 leftData = leftDlg ->DelegateFtn().m_data; + CLR_UINT32 rightData = rightDlg->DelegateFtn().m_data; + + if(leftData > rightData) return 1; + if(leftData < rightData) return -1; + + return Compare_Values( leftDlg->m_object, rightDlg->m_object, fSigned ); + } + + case DATATYPE_CLASS: + case DATATYPE_VALUETYPE: + case DATATYPE_SZARRAY: + case DATATYPE_WEAKCLASS: + return CompareValues_Pointers( &left, &right ); + + case DATATYPE_REFLECTION: + { + const CLR_RT_HeapBlock* ptrLeft; + const CLR_RT_HeapBlock* ptrRight; + CLR_RT_HeapBlock hbLeft; + CLR_RT_HeapBlock hbRight; + + if(left.ReflectionDataConst().m_kind != right.ReflectionDataConst().m_kind) + { + ptrLeft = FixReflectionForType( left , hbLeft ); + ptrRight = FixReflectionForType( right, hbRight ); + } + else + { + ptrLeft = &left; + ptrRight = &right; + } + + return CompareValues_Numeric( *ptrLeft, *ptrRight, false, 8 ); + } + + //--// + #if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + + case DATATYPE_R4: + if(left.NumericByRefConst().r4 > right.NumericByRefConst().r4) return 1; + if(left.NumericByRefConst().r4 < right.NumericByRefConst().r4) return -1; + /************************************************************/ return 0; + + case DATATYPE_R8: + + if(left.NumericByRefConst().r8 > right.NumericByRefConst().r8) return 1; + if(left.NumericByRefConst().r8 < right.NumericByRefConst().r8) return -1; + /************************************************************/ return 0; + + #else + case DATATYPE_R4 : + case DATATYPE_R8 : + fSigned = true; + #endif + + case DATATYPE_BOOLEAN : + case DATATYPE_I1 : + case DATATYPE_U1 : + + case DATATYPE_CHAR : + case DATATYPE_I2 : + case DATATYPE_U2 : + + case DATATYPE_I4 : + case DATATYPE_U4 : + + case DATATYPE_I8 : + case DATATYPE_U8 : + case DATATYPE_DATETIME: + case DATATYPE_TIMESPAN: + return CompareValues_Numeric( left, right, fSigned, c_CLR_RT_DataTypeLookup[ leftDataType ].m_sizeInBytes ); + + default: + // the remaining data types aren't to be handled + break; + } + } + else + { + if(leftDataType == DATATYPE_STRING && rightDataType == DATATYPE_OBJECT) + { + CLR_RT_HeapBlock* rightObj = right.Dereference(); + + if(!rightObj) + { + return 1; // NULL references always compare smaller than non-NULL ones. + } + + return Compare_Values( left, *rightObj, fSigned ); + } + + if(leftDataType == DATATYPE_OBJECT && rightDataType == DATATYPE_STRING) + { + CLR_RT_HeapBlock* leftObj = left.Dereference(); + + if(!leftObj) + { + return -1; // NULL references always compare smaller than non-NULL ones. + } + + return Compare_Values( *leftObj, right, fSigned ); + } + + //--// + + const CLR_RT_DataTypeLookup& leftDtl = c_CLR_RT_DataTypeLookup[ leftDataType ]; + const CLR_RT_DataTypeLookup& rightDtl = c_CLR_RT_DataTypeLookup[ rightDataType ]; + + if((leftDtl .m_flags & CLR_RT_DataTypeLookup::c_Numeric) && + (rightDtl.m_flags & CLR_RT_DataTypeLookup::c_Numeric) ) + { + if(leftDtl.m_sizeInBytes == rightDtl.m_sizeInBytes) + { + return CompareValues_Numeric( left, right, fSigned, leftDtl.m_sizeInBytes ); + } + else + { + CLR_Debug::Printf( "\r\n\r\nRUNTIME ERROR: comparing two values of different size: %d vs. %d!!!\r\n\r\n\r\n", leftDataType, rightDataType ); +#if defined(NANOCLR_PROFILE_NEW) + g_CLR_PRF_Profiler.DumpHeap(); +#endif + } + } + } + + return -1; // Not comparable... +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +HRESULT CLR_RT_HeapBlock::NumericAdd( const CLR_RT_HeapBlock& right ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + switch(DataType()) + { + case DATATYPE_I4: m_data.numeric.s4 += right.m_data.numeric.s4; break; + + case DATATYPE_U4: m_data.numeric.u4 += right.m_data.numeric.u4; break; + + case DATATYPE_I8: m_data.numeric.s8 += right.m_data.numeric.s8; break; + + case DATATYPE_U8: m_data.numeric.u8 += right.m_data.numeric.u8; break; + + case DATATYPE_R4: +#if defined(NANOCLR_EMULATED_FLOATINGPOINT) + { + CLR_INT32 orig = (CLR_INT32)m_data.numeric.r4; + CLR_INT32 rhs = (CLR_INT32)right.m_data.numeric.r4; +#endif + m_data.numeric.r4 += right.m_data.numeric.r4; + +#if defined(NANOCLR_EMULATED_FLOATINGPOINT) + if(rhs > 0 && orig > 0 && orig > (CLR_INT32)m_data.numeric.r4) { m_data.numeric.r4 = 0x7FFFFFFF; /*return CLR_E_OUT_OF_RANGE*/ } + else if(rhs < 0 && orig < 0 && orig < (CLR_INT32)m_data.numeric.r4) { m_data.numeric.r4 = (CLR_INT32)(CLR_UINT32)0x80000000; /*return CLR_E_OUT_OF_RANGE*/ } + } +#endif + break; + + case DATATYPE_R8: +#if defined(NANOCLR_EMULATED_FLOATINGPOINT) + { + CLR_INT64 orig = (CLR_INT64)m_data.numeric.r8; + CLR_INT64 rhs = (CLR_INT64)right.m_data.numeric.r8; +#endif + m_data.numeric.r8 += right.m_data.numeric.r8; + +#if defined(NANOCLR_EMULATED_FLOATINGPOINT) + if(rhs > 0 && orig > 0 && orig > (CLR_INT64)m_data.numeric.r8) { m_data.numeric.r8 = (CLR_INT64)ULONGLONGCONSTANT(0x7FFFFFFFFFFFFFFF); /*return CLR_E_OUT_OF_RANGE*/ } + else if(rhs < 0 && orig < 0 && orig < (CLR_INT64)m_data.numeric.r8) { m_data.numeric.r8 = (CLR_INT64)ULONGLONGCONSTANT(0x8000000000000000); /*return CLR_E_OUT_OF_RANGE*/ } + } +#endif + break; + + + // Adding of value to array reference is like advancing the index in array. + case DATATYPE_ARRAY_BYREF: + { + // Retrieve refernced array. Test if it is not NULL + CLR_RT_HeapBlock_Array* array = m_data.arrayReference.array; FAULT_ON_NULL(array); + // Advance current index. C# on pointer operations multiplies the offset by object size. We need to reverse it. + m_data.arrayReference.index += right.m_data.numeric.s4 / array->m_sizeOfElement; + } + break; + + default : NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock::NumericSub( const CLR_RT_HeapBlock& right ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + switch(DataType()) + { + case DATATYPE_U4: m_data.numeric.u4 -= right.m_data.numeric.u4; break; + + case DATATYPE_I4: m_data.numeric.s4 -= right.m_data.numeric.s4; break; + + case DATATYPE_U8: m_data.numeric.u8 -= right.m_data.numeric.u8; break; + + case DATATYPE_I8: m_data.numeric.s8 -= right.m_data.numeric.s8; break; + + case DATATYPE_R4: +#if defined(NANOCLR_EMULATED_FLOATINGPOINT) + { + CLR_INT32 orig = (CLR_INT32)m_data.numeric.r8; + CLR_INT32 rhs = (CLR_INT32)right.m_data.numeric.r4; +#endif + m_data.numeric.r4 -= right.m_data.numeric.r4; + +#if defined(NANOCLR_EMULATED_FLOATINGPOINT) + if(rhs < 0 && orig > 0 && orig > (CLR_INT32)m_data.numeric.r4) { m_data.numeric.r4 = 0x7FFFFFFF; /*return CLR_E_OUT_OF_RANGE*/ } + else if(rhs > 0 && orig < 0 && orig < (CLR_INT32)m_data.numeric.r4) { m_data.numeric.r4 = (CLR_INT32)(CLR_UINT32)0x80000000; /*return CLR_E_OUT_OF_RANGE*/ } + } +#endif + + break; + + case DATATYPE_R8: +#if defined(NANOCLR_EMULATED_FLOATINGPOINT) + { + CLR_INT64 orig = (CLR_INT64)m_data.numeric.r8; + CLR_INT64 rhs = (CLR_INT64)right.m_data.numeric.r8; +#endif + + m_data.numeric.r8 -= right.m_data.numeric.r8; + +#if defined(NANOCLR_EMULATED_FLOATINGPOINT) + if(rhs < 0 && orig > 0 && orig > (CLR_INT64)m_data.numeric.r8) { m_data.numeric.r8 = (CLR_INT64)ULONGLONGCONSTANT(0x7FFFFFFFFFFFFFFF); /*return CLR_E_OUT_OF_RANGE*/ } + else if(rhs > 0 && orig < 0 && orig < (CLR_INT64)m_data.numeric.r8) { m_data.numeric.r8 = (CLR_INT64)ULONGLONGCONSTANT(0x8000000000000000); /*return CLR_E_OUT_OF_RANGE*/ } + } +#endif + + break; + + + // Substructing of value to array reference is like decreasing the index in array. + case DATATYPE_ARRAY_BYREF: + { + // Retrieve refernced array. Test if it is not NULL + CLR_RT_HeapBlock_Array* array = m_data.arrayReference.array; FAULT_ON_NULL(array); + // Advance current index. C# on pointer operations multiplies the offset by object size. We need to reverse it. + m_data.arrayReference.index -= right.m_data.numeric.s4 / array->m_sizeOfElement; + } + break; + default : NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock::NumericMul( const CLR_RT_HeapBlock& right ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + switch(DataType()) + { + case DATATYPE_U4: m_data.numeric.u4 = m_data.numeric.u4 * right.m_data.numeric.u4; break; + + case DATATYPE_I4: m_data.numeric.s4 = m_data.numeric.s4 * right.m_data.numeric.s4; break; + + case DATATYPE_U8: m_data.numeric.u8 = m_data.numeric.u8 * right.m_data.numeric.u8; break; + + case DATATYPE_I8: m_data.numeric.s8 = m_data.numeric.s8 * right.m_data.numeric.s8; break; + + case DATATYPE_R4: +#if defined(NANOCLR_EMULATED_FLOATINGPOINT) + { + CLR_INT32 orig = (CLR_INT32)m_data.numeric.r4; + CLR_INT32 rhs; +#endif + m_data.numeric.r4 = m_data.numeric.r4 * right.m_data.numeric.r4; + +#if defined(NANOCLR_EMULATED_FLOATINGPOINT) + rhs = (CLR_INT32)right.m_data.numeric.r4; + + if(orig != 0 && rhs != 0) + { + CLR_INT32 ret_value = (CLR_INT32)m_data.numeric.r4; + bool isNeg = orig < 0; + + if(rhs < 0) isNeg = !isNeg; + + if(!isNeg && (ret_value < 0 || ret_value < orig || ret_value < rhs)) { m_data.numeric.r4 = 0x7FFFFFFF; /* return CLR_E_OUT_OF_RANGE; */ } + else if( isNeg && (ret_value > 0 || ret_value > orig || ret_value > rhs)) { m_data.numeric.r4 = (CLR_INT32)(CLR_UINT32)0x80000000; /* return CLR_E_OUT_OF_RANGE; */ } + } + } +#endif + break; + + case DATATYPE_R8: +#if defined(NANOCLR_EMULATED_FLOATINGPOINT) + { + CLR_INT64 orig = (CLR_INT64)m_data.numeric.r8; + CLR_INT64 rhs; +#endif + m_data.numeric.r8 = m_data.numeric.r8 * right.m_data.numeric.r8; + +#if defined(NANOCLR_EMULATED_FLOATINGPOINT) + rhs = (CLR_INT64)right.m_data.numeric.r8; + + if(orig != 0 && rhs != 0) + { + CLR_INT64 ret_value = (CLR_INT64)m_data.numeric.r8; + bool isNeg = orig < 0; + + if(rhs < 0) isNeg = !isNeg; + + if(!isNeg && (ret_value < 0 || ret_value < orig || ret_value < rhs)) { m_data.numeric.r8 = (CLR_INT64)ULONGLONGCONSTANT(0x7FFFFFFFFFFFFFFF); /* return CLR_E_OUT_OF_RANGE; */ } + else if( isNeg && (ret_value > 0 || ret_value > orig || ret_value > rhs)) { m_data.numeric.r8 = (CLR_INT64)ULONGLONGCONSTANT(0x8000000000000000); /* return CLR_E_OUT_OF_RANGE; */ } + } + } +#endif + break; + + default : NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock::NumericDiv( const CLR_RT_HeapBlock& right ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(right.IsZero()) NANOCLR_SET_AND_LEAVE(CLR_E_DIVIDE_BY_ZERO); + + switch(DataType()) + { + case DATATYPE_U4: + case DATATYPE_I4: m_data.numeric.s4 = m_data.numeric.s4 / right.m_data.numeric.s4; break; + + case DATATYPE_U8: + case DATATYPE_I8: m_data.numeric.s8 = m_data.numeric.s8 / right.m_data.numeric.s8; break; + + case DATATYPE_R4: m_data.numeric.r4 = m_data.numeric.r4 / right.m_data.numeric.r4; break; + + case DATATYPE_R8: m_data.numeric.r8 = m_data.numeric.r8 / right.m_data.numeric.r8; break; + + default : NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock::NumericDivUn( const CLR_RT_HeapBlock& right ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(right.IsZero()) NANOCLR_SET_AND_LEAVE(CLR_E_DIVIDE_BY_ZERO); + + switch(DataType()) + { + case DATATYPE_I4: + case DATATYPE_U4: m_data.numeric.u4 = m_data.numeric.u4 / right.m_data.numeric.u4; break; + + case DATATYPE_I8: + case DATATYPE_U8:m_data.numeric.u8 = m_data.numeric.u8 / right.m_data.numeric.u8; break; + + default : NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock::NumericRem( const CLR_RT_HeapBlock& right ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(right.IsZero()) NANOCLR_SET_AND_LEAVE(CLR_E_DIVIDE_BY_ZERO); + + switch(DataType()) + { + case DATATYPE_U4: m_data.numeric.u4 %= right.m_data.numeric.u4 ; break; + + case DATATYPE_I4: m_data.numeric.s4 %= right.m_data.numeric.s4 ; break; + + case DATATYPE_U8: m_data.numeric.u8 %= right.m_data.numeric.u8 ; break; + + case DATATYPE_I8: m_data.numeric.s8 %= right.m_data.numeric.s8 ; break; + +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + + case DATATYPE_R4: m_data.numeric.r4 = fmod( m_data.numeric.r4, right.m_data.numeric.r4 ); break; + + case DATATYPE_R8: m_data.numeric.r8 = fmod( (CLR_DOUBLE_TEMP_CAST)m_data.numeric.r8,(CLR_DOUBLE_TEMP_CAST) right.m_data.numeric.r8 ); break; + +#else + + case DATATYPE_R4: m_data.numeric.r4 %= right.m_data.numeric.r4; break; + + case DATATYPE_R8: m_data.numeric.r8 %= right.m_data.numeric.r8; break; + +#endif + + + default : NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock::NumericRemUn( const CLR_RT_HeapBlock& right ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(right.IsZero()) NANOCLR_SET_AND_LEAVE(CLR_E_DIVIDE_BY_ZERO); + + switch(DataType()) + { + case DATATYPE_I4: + case DATATYPE_U4: m_data.numeric.u4 %= right.m_data.numeric.u4; break; + + case DATATYPE_I8: + case DATATYPE_U8: m_data.numeric.u8 %= right.m_data.numeric.u8; break; + + default : NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock::NumericShl( const CLR_RT_HeapBlock& right ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + switch(DataType()) + { + case DATATYPE_I4: + case DATATYPE_U4: m_data.numeric.u4 <<= right.m_data.numeric.u4; break; + + case DATATYPE_I8: + case DATATYPE_U8: m_data.numeric.u8 <<= right.m_data.numeric.u4; break; + + default : NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock::NumericShr( const CLR_RT_HeapBlock& right ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + switch(DataType()) + { + case DATATYPE_U4: m_data.numeric.u4 >>= right.m_data.numeric.u4; break; + + case DATATYPE_I4: m_data.numeric.s4 >>= right.m_data.numeric.u4; break; + + case DATATYPE_U8: m_data.numeric.u8 >>= right.m_data.numeric.u4; break; + + case DATATYPE_I8: m_data.numeric.s8 >>= right.m_data.numeric.u4; break; + + default : NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock::NumericShrUn( const CLR_RT_HeapBlock& right ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + switch(DataType()) + { + case DATATYPE_I4: + case DATATYPE_U4: m_data.numeric.u4 >>= right.m_data.numeric.u4; break; + + case DATATYPE_I8: + case DATATYPE_U8: m_data.numeric.u8 >>= right.m_data.numeric.u4; break; + + default : NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock::NumericNeg() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + switch(DataType()) + { + case DATATYPE_U4: + case DATATYPE_I4: m_data.numeric.s4 = -m_data.numeric.s4; break; + + case DATATYPE_U8: + case DATATYPE_I8: m_data.numeric.s8 = -m_data.numeric.s8; break; + + case DATATYPE_R4: m_data.numeric.r4 = -m_data.numeric.r4; break; + + case DATATYPE_R8: m_data.numeric.r8 = -m_data.numeric.r8; break; + + + + default : NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + NANOCLR_NOCLEANUP(); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +CLR_RT_HeapBlock* CLR_RT_HeapBlock::ExtractValueBlock( int offset ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock* ptr = Dereference(); + + if(ptr) + { + ptr = &ptr[ offset ]; + } + + return ptr; +} + +void CLR_RT_HeapBlock::ReadValue( CLR_INT64& val, int offset ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock* ptr = ExtractValueBlock( offset ); + + if(ptr) + { + val = ptr->NumericByRefConst().s8; + } + else + { + CLR_INT32 val2 = 0; + + val = val2; + } +} + +void CLR_RT_HeapBlock::WriteValue( const CLR_INT64& val, int offset ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock* ptr = ExtractValueBlock( offset ); + + if(ptr) ptr->NumericByRef().s8 = val; +} + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +#if defined(NANOCLR_APPDOMAINS) + +void CLR_RT_HeapBlock::SetTransparentProxyReference( CLR_RT_AppDomain* appDomain, CLR_RT_HeapBlock* ptr) + { +#if defined(_DEBUG) + if(ptr) + { + //Make sure the data points to a MBRO. + CLR_RT_TypeDef_Instance inst; + + _ASSERTE(ptr->DataType() == DATATYPE_CLASS); + + inst.InitializeFromIndex( ptr->ObjectCls() ); + _ASSERTE((inst.CrossReference().m_flags & CLR_RT_TypeDef_CrossReference::TD_CR_IsMarshalByRefObject) != 0); + } +#endif + + m_data.transparentProxy.appDomain = appDomain; + m_data.transparentProxy.ptr = ptr; + } + +HRESULT CLR_RT_HeapBlock::TransparentProxyValidate() const +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_AppDomain* appDomain = TransparentProxyAppDomain (); + CLR_RT_HeapBlock* obj = TransparentProxyDereference(); + + if(appDomain == NULL || !appDomain->IsLoaded()) NANOCLR_SET_AND_LEAVE(CLR_E_APPDOMAIN_EXITED); + + FAULT_ON_NULL(obj); + + NANOCLR_NOCLEANUP(); +} + +#endif //NANOCLR_APPDOMAINS +//////////////////////////////////////////////////////////////////////////////////////////////////// + +void CLR_RT_HeapBlock::Relocate__HeapBlock() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HEAPBLOCK_RELOCATE(this); +} + + +void CLR_RT_HeapBlock::Relocate_String() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_data.string.m_text ); +#if !defined(NANOCLR_NO_ASSEMBLY_STRINGS) + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_data.string.m_assm ); +#endif +} + +void CLR_RT_HeapBlock::Relocate_Obj() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_data.objectReference.ptr ); +} + +void CLR_RT_HeapBlock::Relocate_Cls() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_data.objectHeader.lock ); + + CLR_RT_GarbageCollector::Heap_Relocate( this + 1, DataSize() - 1 ); +} + +void CLR_RT_HeapBlock::Relocate_Ref() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_data.objectReference.ptr ); +} + +void CLR_RT_HeapBlock::Relocate_ArrayRef() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_data.arrayReference.array ); +} + +#if defined(NANOCLR_APPDOMAINS) +void CLR_RT_HeapBlock::Relocate_TransparentProxy() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_data.transparentProxy.ptr ); +} +#endif + +//--// + +#if defined(NANOCLR_FILL_MEMORY_WITH_DIRTY_PATTERN) + +void CLR_RT_HeapBlock::Debug_CheckPointer() const +{ + NATIVE_PROFILE_CLR_CORE(); + if(m_id.type.dataType == DATATYPE_OBJECT) + { + Debug_CheckPointer( Dereference() ); + } +} + +void CLR_RT_HeapBlock::Debug_CheckPointer( void* ptr ) +{ + NATIVE_PROFILE_CLR_CORE(); + switch((size_t)ptr) + { + case 0xCFCFCFCF: + case 0xCBCBCBCB: + case 0xABABABAB: + case 0xADADADAD: + case 0xDFDFDFDF: + NANOCLR_STOP(); + break; + } +} + +void CLR_RT_HeapBlock::Debug_ClearBlock( int data ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_UINT32 size = DataSize(); + + if(size > 1) + { + CLR_RT_HeapBlock_Raw* ptr = (CLR_RT_HeapBlock_Raw*)this; + CLR_UINT32 raw1 = CLR_RT_HEAPBLOCK_RAW_ID(DATATYPE_OBJECT,0,1); + CLR_UINT32 raw2; + + raw2 = data & 0xFF; + raw2 = raw2 | (raw2 << 8); + raw2 = raw2 | (raw2 << 16); + + while(--size) + { + ptr++; + + ptr->data[ 0 ] = raw1; + ptr->data[ 1 ] = raw2; + ptr->data[ 2 ] = raw2; + } + } +} + +#endif + diff --git a/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Array.cpp b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Array.cpp new file mode 100644 index 00000000..4f2c8dde --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Array.cpp @@ -0,0 +1,375 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +HRESULT CLR_RT_HeapBlock_Array::CreateInstance( CLR_RT_HeapBlock& reference, CLR_UINT32 length, const CLR_RT_ReflectionDef_Index& reflex ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* pArray; + CLR_RT_TypeDef_Index cls; + CLR_RT_TypeDef_Instance inst; + + reference.SetObjectReference( NULL ); + + if((CLR_INT32)length < 0) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + + if(reflex.m_kind != REFLECTION_TYPE) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + if(reflex.m_levels == 1) + { + cls = reflex.m_data.m_type; + } + else + { + cls = g_CLR_RT_WellKnownTypes.m_Array; + } + + if(inst.InitializeFromIndex( cls ) == false) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + else + { + CLR_DataType dt = (CLR_DataType)inst.m_target->dataType; + const CLR_RT_DataTypeLookup& dtl = c_CLR_RT_DataTypeLookup[ dt ]; + + if(dtl.m_sizeInBytes == CLR_RT_DataTypeLookup::c_NA) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + pArray = (CLR_RT_HeapBlock_Array*)g_CLR_RT_ExecutionEngine.ExtractHeapBlocksForArray( inst, length, reflex ); CHECK_ALLOCATION(pArray); + + reference.SetObjectReference( pArray ); + + NANOCLR_SET_AND_LEAVE(pArray->ClearElements( 0, length )); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock_Array::CreateInstance( CLR_RT_HeapBlock& reference, CLR_UINT32 length, const CLR_RT_TypeDef_Index& cls ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_ReflectionDef_Index reflex; + + reflex.m_kind = REFLECTION_TYPE; + reflex.m_levels = 1; + reflex.m_data.m_type = cls; + + NANOCLR_SET_AND_LEAVE(CreateInstance( reference, length, reflex )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock_Array::CreateInstance( CLR_RT_HeapBlock& reference, CLR_UINT32 length, CLR_RT_Assembly* assm, CLR_UINT32 tk ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock ref; + CLR_RT_TypeDef_Instance cls; + CLR_RT_TypeSpec_Instance def; + + if(cls.ResolveToken( tk, assm )) + { + ref.SetReflection( cls ); + } + else if(def.ResolveToken( tk, assm )) + { + NANOCLR_CHECK_HRESULT(ref.SetReflection( def )); + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + ref.ReflectionData().m_levels++; + + NANOCLR_SET_AND_LEAVE(CreateInstance( reference, length, ref.ReflectionData() )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock_Array::ClearElements( int index, int length ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + const CLR_RT_ReflectionDef_Index& reflex = ReflectionDataConst(); + CLR_UINT8* data = GetElement( index ); + + CLR_RT_Memory::ZeroFill( data, length * m_sizeOfElement ); + + if(m_fReference) + { + CLR_DataType dt = (CLR_DataType)m_typeOfElement; + bool fAllocate = (reflex.m_levels == 1 && dt == DATATYPE_VALUETYPE); + CLR_RT_HeapBlock* ptr = (CLR_RT_HeapBlock*)data; + + switch(dt) + { + case DATATYPE_VALUETYPE: + case DATATYPE_CLASS: + case DATATYPE_WEAKCLASS: + dt = DATATYPE_OBJECT; + break; + + default: + // the remaining data types aren't to be handled + break; + } + + while(length > 0) + { + ptr->SetDataId( CLR_RT_HEAPBLOCK_RAW_ID(dt,0,1) ); + + if(fAllocate) + { + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex( *ptr, reflex.m_data.m_type )); + } + + ptr++; length--; + } + } + + NANOCLR_NOCLEANUP(); +} + +void CLR_RT_HeapBlock_Array::Relocate() +{ + NATIVE_PROFILE_CLR_CORE(); + // + // If the array is full of reference types, relocate each of them. + // + if(m_fReference) + { + CLR_RT_GarbageCollector::Heap_Relocate( (CLR_RT_HeapBlock*)GetFirstElement(), m_numOfElements ); + } +} + +bool CLR_RT_HeapBlock_Array::CheckRange( int index, int length, int numOfElements ) +{ + NATIVE_PROFILE_CLR_CORE(); + if( length < 0 ) return false; + if( index < 0 || index > numOfElements) return false; + if((index + length) < 0 || (index + length) > numOfElements) return false; + + return true; +} + +/* + This is not the same functionality as System.Array.IndexOf. CLR_RT_HeapBlock_Array::IndexOf does the search analogous + to calling Object.ReferenceEquals, not Object.Equals, as System.Array.IndexOf demands. This function is used by + TrySzIndexOf +*/ +HRESULT CLR_RT_HeapBlock_Array::IndexOf( CLR_RT_HeapBlock_Array* array, CLR_RT_HeapBlock& match, int start, int stop, bool fForward, int& index ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + int numElem = array->m_numOfElements; + int count; + + if(stop == -1) stop = numElem; + + count = stop - start; + + if(CheckRange( start, count, numElem ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + + if(count > 0) + { + CLR_UINT8* data = array->GetFirstElement(); + CLR_UINT8 sizeElem = array->m_sizeOfElement; + int pos; + int incr; + + if(fForward) { pos = start ; incr = 1; } + else { pos = stop-1; incr = -1; } + + data += pos * sizeElem; + + if(!array->m_fReference) + { + CLR_RT_HeapBlock* matchPtr = match.FixBoxingReference(); FAULT_ON_NULL(matchPtr); + + if(matchPtr->DataType() <= DATATYPE_LAST_PRIMITIVE) + { + int incrElem = incr * sizeElem; + + while(true) + { + if(memcmp( data, &matchPtr->NumericByRef(), sizeElem ) == 0) + { + index = pos; + NANOCLR_SET_AND_LEAVE(S_OK); + } + + if(--count == 0) break; + + pos += incr; + data += incrElem; + } + } + } + else + { + CLR_RT_HeapBlock* dataPtr = (CLR_RT_HeapBlock*)data; + + while(true) + { + if(CLR_RT_HeapBlock::Compare_Unsigned_Values( *dataPtr, match ) == 0) + { + index = pos; + NANOCLR_SET_AND_LEAVE(S_OK); + } + + if(--count == 0) break; + + pos += incr; + dataPtr += incr; + } + } + } + + index = -1; + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock_Array::Copy( CLR_RT_HeapBlock_Array* arraySrc, int indexSrc, CLR_RT_HeapBlock_Array* arrayDst, int indexDst, int length ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(length) + { + int numElemSrc = arraySrc->m_numOfElements; + int numElemDst = arrayDst->m_numOfElements; + + if(length < 0 || + indexSrc < 0 || + indexDst < 0 || + length + indexSrc > numElemSrc || + length + indexDst > numElemDst ) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + } + + // + // Copy of an array on itself. + // + if(arraySrc == arrayDst && indexSrc == indexDst) NANOCLR_SET_AND_LEAVE(S_OK); + + if(arraySrc->SameHeader( *arrayDst )) + { + CLR_UINT8* dataSrc = arraySrc->GetFirstElement(); + CLR_UINT8* dataDst = arrayDst->GetFirstElement(); + CLR_UINT8 sizeElem = arraySrc->m_sizeOfElement; + + dataSrc += indexSrc * sizeElem; + dataDst += indexDst * sizeElem; + + if(!arraySrc->m_fReference) + { + memmove( dataDst, dataSrc, length * sizeElem ); + } + else + { + CLR_RT_HeapBlock* ptrSrc = (CLR_RT_HeapBlock*)dataSrc; + CLR_RT_HeapBlock* ptrDst = (CLR_RT_HeapBlock*)dataDst; + int incr; + + if(arraySrc == arrayDst && ptrSrc < ptrDst) + { + incr = -1; + ptrSrc += length-1; + ptrDst += length-1; + } + else + { + incr = 1; + } + + for(int i=0; iReassign( *ptrSrc )); + } + } + } + else if(arraySrc->m_fReference && arrayDst->m_fReference) + { + CLR_RT_TypeDescriptor descSrc; + CLR_RT_TypeDescriptor descDst; + CLR_RT_HeapBlock* ptrSrc = (CLR_RT_HeapBlock*)arraySrc->GetElement( indexSrc ); + CLR_RT_HeapBlock* ptrDst = (CLR_RT_HeapBlock*)arrayDst->GetElement( indexDst ); + + NANOCLR_CHECK_HRESULT(descDst.InitializeFromObject( *arrayDst )); descDst.GetElementType( descDst ); + + for(int i=0; iDataType() == DATATYPE_OBJECT && ptrSrc->Dereference() == NULL) + { + ; + } + else + { + NANOCLR_CHECK_HRESULT(descSrc.InitializeFromObject( *ptrSrc )); + + if(CLR_RT_ExecutionEngine::IsInstanceOf( descSrc, descDst ) == false) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_CAST); + } + } + + NANOCLR_CHECK_HRESULT(ptrDst->Reassign( *ptrSrc )); + } + } + else + { + CLR_RT_TypeDescriptor descSrc; + CLR_RT_TypeDescriptor descDst; + CLR_RT_HeapBlock ref; + CLR_RT_HeapBlock elem; elem.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc( elem ); + + NANOCLR_CHECK_HRESULT(descDst.InitializeFromObject( *arrayDst )); descDst.GetElementType( descDst ); + + for(int i=0; i= GetSize()) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + + value = ((CLR_RT_HeapBlock*)GetItems()->GetElement( index ))->Dereference(); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock_ArrayList::SetItem( CLR_INT32 index, CLR_RT_HeapBlock* value ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(index < 0 || index >= GetSize()) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + + ((CLR_RT_HeapBlock*)GetItems()->GetElement( index ))->SetObjectReference( value ); + + NANOCLR_NOCLEANUP(); +} + +// May Trigger GC, but parameter value will be protected +HRESULT CLR_RT_HeapBlock_ArrayList::Add( CLR_RT_HeapBlock* value, CLR_INT32& index ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* items = GetItems(); + CLR_INT32 size = GetSize(); + CLR_INT32 capacity = items->m_numOfElements; + + if(size == capacity) + { + // Protect value from GC, in case EnsureCapacity triggers one + CLR_RT_HeapBlock valueHB; valueHB.SetObjectReference( value ); + CLR_RT_ProtectFromGC gc( valueHB ); + + NANOCLR_CHECK_HRESULT(EnsureCapacity( size + 1, capacity )); + + // needs to update the reference to the new array + items = GetItems(); + } + + SetSize( size + 1 ); + + ((CLR_RT_HeapBlock*)items->GetElement( size ))->SetObjectReference( value ); + + index = size; + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock_ArrayList::Clear() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_CHECK_HRESULT(GetItems()->ClearElements( 0, GetSize() )); + + SetSize( 0 ); + + NANOCLR_NOCLEANUP(); +} + +// May Trigger GC, but parameter value will be protected +HRESULT CLR_RT_HeapBlock_ArrayList::Insert( CLR_INT32 index, CLR_RT_HeapBlock* value ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* items = GetItems(); + CLR_INT32 size = GetSize(); + CLR_INT32 capacity = items->m_numOfElements; + + if(index < 0 || index > size) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + + if(size == capacity) + { + // Protect value from GC, in case EnsureCapacity triggers one + CLR_RT_HeapBlock valueHB; valueHB.SetObjectReference( value ); + CLR_RT_ProtectFromGC gc( valueHB ); + + NANOCLR_CHECK_HRESULT(EnsureCapacity( size + 1, capacity )); + + // needs to update the reference to the new array + items = GetItems(); + } + + if(index < size) + { + // Move everything up one slot. + CLR_RT_HeapBlock* current = (CLR_RT_HeapBlock*)items->GetElement( size ); + CLR_RT_HeapBlock* end = (CLR_RT_HeapBlock*)items->GetElement( index ); + + do + { + current->Assign( *(current - 1) ); + } + while(--current != end); + } + + ((CLR_RT_HeapBlock*)items->GetElement( index ))->SetObjectReference( value ); + + SetSize( size + 1 ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock_ArrayList::RemoveAt( CLR_INT32 index ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* items = GetItems(); + CLR_INT32 size = GetSize(); + + if(index < 0 || index >= size) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + + // Need to shift everything, if it's not the last item + if(index < size - 1) + { + // Move everything down one slot. + CLR_RT_HeapBlock* current = (CLR_RT_HeapBlock*)items->GetElement( index ); + CLR_RT_HeapBlock* end = (CLR_RT_HeapBlock*)items->GetElement( size - 1 ); + + do + { + current->Assign( *(current + 1) ); + } + while(++current != end); + } + + size--; + + ((CLR_RT_HeapBlock*)items->GetElement( size ))->SetObjectReference( NULL ); + + SetSize( size ); + + NANOCLR_NOCLEANUP(); +} + +// May Trigger GC +HRESULT CLR_RT_HeapBlock_ArrayList::SetCapacity( CLR_UINT32 newCapacity ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* items = GetItems(); + CLR_UINT32 size = GetSize(); + + if(newCapacity != items->m_numOfElements) // if capacity is changing + { + CLR_RT_HeapBlock newItemsHB; + CLR_RT_HeapBlock_Array* newItems; + + if(newCapacity < size) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + + if(newCapacity < c_DefaultCapacity) + { + newCapacity = c_DefaultCapacity; + } + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( newItemsHB, newCapacity, g_CLR_RT_WellKnownTypes.m_Object )); + + newItems = newItemsHB.DereferenceArray(); + + if(size > 0) + { + memcpy( newItems->GetFirstElement(), items->GetFirstElement(), size * sizeof(CLR_RT_HeapBlock) ); + } + + SetItems( newItems ); + } + + NANOCLR_NOCLEANUP(); +} + +// May Trigger GC +HRESULT CLR_RT_HeapBlock_ArrayList::EnsureCapacity( CLR_INT32 min, CLR_INT32 currentCapacity ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(currentCapacity < min) + { + CLR_INT32 newCapacity = currentCapacity * 3 / 2; + + if(newCapacity < min) newCapacity = min; + + NANOCLR_SET_AND_LEAVE(SetCapacity( newCapacity )); + } + + NANOCLR_NOCLEANUP(); +} + +//--// + +CT_ASSERT(Library_corlib_native_System_Collections_ArrayList__FIELD___items == Library_corlib_native_System_Collections_ArrayList::FIELD___items); +CT_ASSERT(Library_corlib_native_System_Collections_ArrayList__FIELD___size == Library_corlib_native_System_Collections_ArrayList::FIELD___size ); diff --git a/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_BinaryBlob.cpp b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_BinaryBlob.cpp new file mode 100644 index 00000000..e871bc86 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_BinaryBlob.cpp @@ -0,0 +1,67 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +HRESULT CLR_RT_HeapBlock_BinaryBlob::CreateInstance( CLR_RT_HeapBlock& reference, CLR_UINT32 length, CLR_RT_MarkingHandler mark, CLR_RT_RelocationHandler relocate, CLR_UINT32 flags ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_BinaryBlob* obj = Allocate( length, flags ); CHECK_ALLOCATION(obj); + + reference.SetObjectReference( obj ); + + obj->SetBinaryBlobHandlers( mark, relocate ); + obj->m_assembly = NULL; + + NANOCLR_NOCLEANUP(); +} + +CLR_RT_HeapBlock_BinaryBlob* CLR_RT_HeapBlock_BinaryBlob::Allocate( CLR_UINT32 length, CLR_UINT32 flags ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_UINT32 totLength = (CLR_UINT32)( sizeof(CLR_RT_HeapBlock_BinaryBlob) + length ); + + CLR_RT_HeapBlock_BinaryBlob* obj; + + if(flags & CLR_RT_HeapBlock::HB_Event) + { + obj = EVENTCACHE_EXTRACT_NODE_AS_BYTES(g_CLR_RT_EventCache,CLR_RT_HeapBlock_BinaryBlob,DATATYPE_BINARY_BLOB_HEAD,flags,totLength); + } + else + { + obj = (CLR_RT_HeapBlock_BinaryBlob*)g_CLR_RT_ExecutionEngine.ExtractHeapBytesForObjects( DATATYPE_BINARY_BLOB_HEAD, flags, totLength ); + } + + if(obj) + { + obj->SetBinaryBlobHandlers( NULL, NULL ); + } + + return obj; +} + +void CLR_RT_HeapBlock_BinaryBlob::Release( bool fEvent ) +{ + NATIVE_PROFILE_CLR_CORE(); + SetBinaryBlobHandlers( NULL, NULL ); + + if(fEvent) g_CLR_RT_EventCache.Append_Node( this ); +} + +void CLR_RT_HeapBlock_BinaryBlob::Relocate() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_RelocationHandler relocate = BinaryBlobRelocationHandler(); + + if(relocate) + { + relocate( this ); + } +} + diff --git a/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Delegate.cpp b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Delegate.cpp new file mode 100644 index 00000000..5af4e0b5 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Delegate.cpp @@ -0,0 +1,79 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +HRESULT CLR_RT_HeapBlock_Delegate::CreateInstance( CLR_RT_HeapBlock& reference, const CLR_RT_MethodDef_Index& ftn, CLR_RT_StackFrame* call ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + reference.SetObjectReference( NULL ); + + CLR_UINT32 length = 0; + + #if defined(NANOCLR_DELEGATE_PRESERVE_STACK) + if(call) + { + NANOCLR_FOREACH_NODE_BACKWARD__DIRECT(CLR_RT_StackFrame,ptr,call) + { + length++; + } + NANOCLR_FOREACH_NODE_BACKWARD_END(); + } + + // + // Limit depth to three callers. + // + if(length > 3) length = 3; + #else + (void)call; + #endif + + CLR_UINT32 totLength = (CLR_UINT32)(sizeof(CLR_RT_HeapBlock_Delegate) + length * sizeof(CLR_RT_MethodDef_Index)); + + CLR_RT_HeapBlock_Delegate* dlg = (CLR_RT_HeapBlock_Delegate*)g_CLR_RT_ExecutionEngine.ExtractHeapBytesForObjects( DATATYPE_DELEGATE_HEAD, 0, totLength ); CHECK_ALLOCATION(dlg); + + reference.SetObjectReference( dlg ); + + dlg->ClearData(); + dlg->m_cls.Clear(); + dlg->m_ftn = ftn; +#if defined(NANOCLR_DELEGATE_PRESERVE_STACK) + dlg->m_numOfStackFrames = length; +#endif + + dlg->m_object.SetObjectReference( NULL ); + +#if defined(NANOCLR_APPDOMAINS) + dlg->m_appDomain = g_CLR_RT_ExecutionEngine.GetCurrentAppDomain(); +#endif + +#if defined(NANOCLR_DELEGATE_PRESERVE_STACK) + if(call) + { + CLR_RT_MethodDef_Index* callStack = dlg->GetStackFrames(); + + NANOCLR_FOREACH_NODE_BACKWARD__DIRECT(CLR_RT_StackFrame,ptr,call) + { + if(length-- == 0) break; + + *callStack++ = ptr->m_call; + } + NANOCLR_FOREACH_NODE_BACKWARD_END(); + } +#endif + + NANOCLR_NOCLEANUP(); +} + +void CLR_RT_HeapBlock_Delegate::Relocate() +{ + NATIVE_PROFILE_CLR_CORE(); + m_object.Relocate__HeapBlock(); +} + diff --git a/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Delegate_List.cpp b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Delegate_List.cpp new file mode 100644 index 00000000..e9a199b5 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Delegate_List.cpp @@ -0,0 +1,232 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +HRESULT CLR_RT_HeapBlock_Delegate_List::CreateInstance( CLR_RT_HeapBlock_Delegate_List*& list, CLR_UINT32 length ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_UINT32 totLength = (CLR_UINT32)(sizeof(CLR_RT_HeapBlock_Delegate_List) + length * sizeof(CLR_RT_HeapBlock)); + + list = (CLR_RT_HeapBlock_Delegate_List*)g_CLR_RT_ExecutionEngine.ExtractHeapBytesForObjects( DATATYPE_DELEGATELIST_HEAD, 0, totLength ); CHECK_ALLOCATION(list); + + list->ClearData(); + list->m_cls.Clear(); + list->m_length = length; + list->m_flags = 0; + + NANOCLR_NOCLEANUP(); +} + +CLR_RT_HeapBlock* CLR_RT_HeapBlock_Delegate_List::CopyAndCompress( CLR_RT_HeapBlock* src, CLR_RT_HeapBlock* dst, CLR_UINT32 num ) +{ + NATIVE_PROFILE_CLR_CORE(); + while(num--) + { + CLR_RT_HeapBlock_Delegate* dlg = src->DereferenceDelegate(); + if(dlg) + { + dst->SetObjectReference( dlg ); + + dst++; + } + else + { + m_length--; + } + + src++; + } + + return dst; +} + +HRESULT CLR_RT_HeapBlock_Delegate_List::Change( CLR_RT_HeapBlock& reference, CLR_RT_HeapBlock& delegateSrc, CLR_RT_HeapBlock& delegateTarget, bool fCombine, bool fWeak ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Delegate_List* dlgListSrc; + CLR_RT_HeapBlock_Delegate_List* dlgListDst; + CLR_RT_HeapBlock_Delegate* dlg; + CLR_RT_HeapBlock* newDlgs; + CLR_RT_HeapBlock* oldDlgs; + CLR_UINT32 oldNum; + CLR_UINT32 newNum; + + CLR_UINT32 num = 0; + + reference.SetObjectReference( NULL ); + + if(delegateSrc .DataType() != DATATYPE_OBJECT || + delegateTarget.DataType() != DATATYPE_OBJECT ) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + dlg = delegateTarget.DereferenceDelegate(); + + if(dlg == NULL) + { + reference.SetObjectReference( delegateSrc.DereferenceDelegate() ); + NANOCLR_SET_AND_LEAVE(S_OK); + } + + if(dlg->DataType() == DATATYPE_DELEGATELIST_HEAD) + { + CLR_RT_HeapBlock intermediate; intermediate.Assign( delegateSrc ); + CLR_RT_ProtectFromGC gc( intermediate ); + + dlgListDst = (CLR_RT_HeapBlock_Delegate_List*)dlg; + newDlgs = dlgListDst->GetDelegates(); + + for(num=0; numm_length; num++, newDlgs++) + { + if(newDlgs->DataType() == DATATYPE_OBJECT && newDlgs->DereferenceDelegate() != NULL) // The delegate could have been GC'ed. + { + NANOCLR_CHECK_HRESULT(Change( reference, intermediate, *newDlgs, fCombine, fWeak )); + + intermediate.Assign( reference ); + } + } + } + else + { + dlgListSrc = delegateSrc.DereferenceDelegateList(); + if(dlgListSrc == NULL) + { + oldDlgs = NULL; + oldNum = 0; + } + else + { + switch(dlgListSrc->DataType()) + { + case DATATYPE_DELEGATE_HEAD: + oldDlgs = &delegateSrc; + oldNum = 1; + break; + + case DATATYPE_DELEGATELIST_HEAD: + oldDlgs = dlgListSrc->GetDelegates(); + oldNum = dlgListSrc->m_length; + break; + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + } + + if(fCombine) + { + if(oldNum == 0 && fWeak == false) + { + // + // Empty input list, copy the delegate. + // + reference.Assign( delegateTarget ); + NANOCLR_SET_AND_LEAVE(S_OK); + } + + //--// + + newNum = oldNum + 1; + } + else + { + for(num=0, newDlgs=oldDlgs; numDereferenceDelegate(); + if(ptr) + { + if( ptr->DelegateFtn().m_data == dlg->DelegateFtn().m_data && + ptr->m_object.Dereference() == dlg->m_object.Dereference() ) + { + break; + } + } + } + + if(num == oldNum) + { + reference.Assign( delegateSrc ); // Nothing to remove. + NANOCLR_SET_AND_LEAVE(S_OK); + } + + if(oldNum == 2 && (dlgListSrc->m_flags & CLR_RT_HeapBlock_Delegate_List::c_Weak) == 0) + { + reference.Assign( oldDlgs[ 1-num ] ); // Convert from a list to delegate. + NANOCLR_SET_AND_LEAVE(S_OK); + } + + if(oldNum == 1) + { + reference.SetObjectReference( NULL ); // Oops, empty delegate... + NANOCLR_SET_AND_LEAVE(S_OK); + } + + //--// + + newNum = oldNum - 1; + } + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Delegate_List::CreateInstance( dlgListDst, newNum )); + + dlgListDst->m_cls = dlg->m_cls; + + newDlgs = dlgListDst->GetDelegates(); + + if(fCombine) + { + newDlgs = dlgListDst->CopyAndCompress( oldDlgs, newDlgs, oldNum ); + + newDlgs->Assign( delegateTarget ); + } + else + { + newDlgs = dlgListDst->CopyAndCompress( oldDlgs , newDlgs, num++ ); + newDlgs = dlgListDst->CopyAndCompress( oldDlgs + num, newDlgs, oldNum - num ); + } + + dlgListDst->m_flags = (dlgListSrc && oldNum > 1) ? dlgListSrc->m_flags : 0; + + if(fWeak) dlgListDst->m_flags |= CLR_RT_HeapBlock_Delegate_List::c_Weak; + + reference.SetObjectReference( dlgListDst ); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock_Delegate_List::Combine( CLR_RT_HeapBlock& reference, CLR_RT_HeapBlock& delegateSrc, CLR_RT_HeapBlock& delegateNew, bool fWeak ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(Change( reference, delegateSrc, delegateNew, true, fWeak )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock_Delegate_List::Remove( CLR_RT_HeapBlock& reference, CLR_RT_HeapBlock& delegateSrc, CLR_RT_HeapBlock& delegateOld ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(Change( reference, delegateSrc, delegateOld, false, false )); + + NANOCLR_NOCLEANUP(); +} + +void CLR_RT_HeapBlock_Delegate_List::Relocate() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_GarbageCollector::Heap_Relocate( GetDelegates(), m_length ); +} + diff --git a/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Finalizer.cpp b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Finalizer.cpp new file mode 100644 index 00000000..c06cee13 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Finalizer.cpp @@ -0,0 +1,80 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +HRESULT CLR_RT_HeapBlock_Finalizer::CreateInstance( CLR_RT_HeapBlock* object, const CLR_RT_TypeDef_Instance& inst ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Instance inst2 = inst; + + do + { + if(inst2.m_target->flags & CLR_RECORD_TYPEDEF::TD_HasFinalizer) + { + int pos = inst2.m_target->methods_First; + int end = pos + inst2.m_target->vMethods_Num + inst2.m_target->iMethods_Num; + const CLR_RECORD_METHODDEF* md = inst2.m_assm->GetMethodDef( pos ); + + for(; posflags & CLR_RECORD_METHODDEF::MD_Finalizer) break; + } + + if(pos < end) + { + CLR_RT_HeapBlock_Finalizer* fin = EVENTCACHE_EXTRACT_NODE_NOALLOC(g_CLR_RT_EventCache,CLR_RT_HeapBlock_Finalizer,DATATYPE_FINALIZER_HEAD); CHECK_ALLOCATION(fin); + + fin->m_object = object; + + fin->m_md.Set( inst2.Assembly(), pos ); + +#if defined(NANOCLR_APPDOMAINS) + fin->m_appDomain = g_CLR_RT_ExecutionEngine.GetCurrentAppDomain(); +#endif + + g_CLR_RT_ExecutionEngine.m_finalizersAlive.LinkAtBack( fin ); + + break; + } + } + } + while(inst2.SwitchToParent()); + + NANOCLR_NOCLEANUP(); +} + +void CLR_RT_HeapBlock_Finalizer::Relocate() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_object ); +} + +void CLR_RT_HeapBlock_Finalizer::SuppressFinalize( CLR_RT_HeapBlock* object ) +{ + NATIVE_PROFILE_CLR_CORE(); + RemoveInstance( object, g_CLR_RT_ExecutionEngine.m_finalizersAlive ); + RemoveInstance( object, g_CLR_RT_ExecutionEngine.m_finalizersPending ); +} + +void CLR_RT_HeapBlock_Finalizer::RemoveInstance( CLR_RT_HeapBlock* object, CLR_RT_DblLinkedList& lst ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Finalizer,fin,lst) + { + if(fin->m_object == object) + { + g_CLR_RT_EventCache.Append_Node( fin ); + + break; + } + } + NANOCLR_FOREACH_NODE_END(); +} + diff --git a/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Lock.cpp b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Lock.cpp new file mode 100644 index 00000000..99a040c7 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Lock.cpp @@ -0,0 +1,228 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +HRESULT CLR_RT_HeapBlock_Lock::CreateInstance( CLR_RT_HeapBlock_Lock*& lock, CLR_RT_Thread* th, CLR_RT_HeapBlock& resource ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + lock = EVENTCACHE_EXTRACT_NODE(g_CLR_RT_EventCache,CLR_RT_HeapBlock_Lock,DATATYPE_LOCK_HEAD); CHECK_ALLOCATION(lock); + + lock->m_owningThread = th; // CLR_RT_Thread* m_owningThread; + // + lock->m_resource.Assign( resource ); // CLR_RT_HeapBlock m_resource; + // + lock->m_owners .DblLinkedList_Initialize(); // CLR_RT_DblLinkedList m_owners; + lock->m_requests.DblLinkedList_Initialize(); // CLR_RT_DblLinkedList m_requests; + +#if defined(NANOCLR_APPDOMAINS) + lock->m_appDomain = g_CLR_RT_ExecutionEngine.GetCurrentAppDomain(); +#endif + + //--// + + if(resource.DataType() == DATATYPE_OBJECT) + { + CLR_RT_HeapBlock* ptr = resource.Dereference(); + + if(ptr) + { + switch(ptr->DataType()) + { + case DATATYPE_VALUETYPE: + case DATATYPE_CLASS : + ptr->SetObjectLock( lock ); + break; + + default: + // the remaining data types aren't to be handled + break; + } + } + } + + th->m_locks.LinkAtBack( lock ); + + NANOCLR_NOCLEANUP(); +} + +void CLR_RT_HeapBlock_Lock::DestroyOwner( CLR_RT_SubThread* sth ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Lock::Owner,owner,m_owners) + { + if(owner->m_owningSubThread == sth) + { + g_CLR_RT_EventCache.Append_Node( owner ); + } + } + NANOCLR_FOREACH_NODE_END(); + + if(m_owners.IsEmpty()) + { + ChangeOwner(); + } +} + +void CLR_RT_HeapBlock_Lock::ChangeOwner() +{ + NATIVE_PROFILE_CLR_CORE(); + m_owners.DblLinkedList_PushToCache(); + + while(true) + { + CLR_RT_HeapBlock_LockRequest* req = (CLR_RT_HeapBlock_LockRequest*)m_requests.ExtractFirstNode(); if(!req) break; + + CLR_RT_SubThread* sth = req->m_subthreadWaiting; + CLR_RT_Thread* th = sth->m_owningThread; + + g_CLR_RT_EventCache.Append_Node( req ); + + sth->ChangeLockRequestCount( -1 ); + + th->m_locks.LinkAtBack( this ); + + m_owningThread = th; + + CLR_RT_HeapBlock_Lock::IncrementOwnership( this, sth, TIMEOUT_INFINITE, false ); + + // + // If the new owner was waiting on something, update the flags. + // + { + CLR_RT_StackFrame* stack = th->CurrentFrame(); + + if(stack->m_flags & CLR_RT_StackFrame::c_PendingSynchronizeGlobally) + { + stack->m_flags &= ~CLR_RT_StackFrame::c_PendingSynchronizeGlobally; + stack->m_flags |= CLR_RT_StackFrame::c_SynchronizedGlobally; + } + + if(stack->m_flags & CLR_RT_StackFrame::c_PendingSynchronize) + { + stack->m_flags &= ~CLR_RT_StackFrame::c_PendingSynchronize; + stack->m_flags |= CLR_RT_StackFrame::c_Synchronized; + } + } + + return; + } + + // + // None is listening for this object, unlock it. + // + if(m_resource.DataType() == DATATYPE_OBJECT) + { + CLR_RT_HeapBlock* ptr = m_resource.Dereference(); + + if(ptr) + { + switch(ptr->DataType()) + { + case DATATYPE_VALUETYPE: + case DATATYPE_CLASS : + ptr->SetObjectLock( NULL ); + break; + + default: + // the remaining data types aren't to be handled + break; + } + } + } + + g_CLR_RT_EventCache.Append_Node( this ); +} + +HRESULT CLR_RT_HeapBlock_Lock::IncrementOwnership( CLR_RT_HeapBlock_Lock* lock, CLR_RT_SubThread* sth, const CLR_INT64& timeExpire, bool fForce ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_Thread* th = sth ->m_owningThread; + CLR_RT_Thread* thOwner = lock->m_owningThread; + + if(thOwner == th) + { + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Lock::Owner,owner,lock->m_owners) + { + if(owner->m_owningSubThread == sth) + { + owner->m_recursion++; + NANOCLR_SET_AND_LEAVE(S_OK); + } + } + NANOCLR_FOREACH_NODE_END(); + + { + CLR_RT_HeapBlock_Lock::Owner* owner = EVENTCACHE_EXTRACT_NODE(g_CLR_RT_EventCache,Owner,DATATYPE_LOCK_OWNER_HEAD); CHECK_ALLOCATION(owner); + + owner->m_owningSubThread = sth; + owner->m_recursion = 1; + + lock->m_owners.LinkAtFront( owner ); + NANOCLR_SET_AND_LEAVE(S_OK); + } + } + + // + // Create a request and stop the calling thread. + // + NANOCLR_SET_AND_LEAVE(CLR_RT_HeapBlock_LockRequest::CreateInstance( lock, sth, timeExpire, fForce )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock_Lock::DecrementOwnership( CLR_RT_HeapBlock_Lock* lock, CLR_RT_SubThread* sth ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_Thread* th = sth->m_owningThread; + + if(lock && lock->m_owningThread == th) + { + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Lock::Owner,owner,lock->m_owners) + { + if(owner->m_owningSubThread == sth) + { + if(--owner->m_recursion == 0) + { + g_CLR_RT_EventCache.Append_Node( owner ); + } + + //--// + + if(lock->m_owners.IsEmpty()) + { + lock->ChangeOwner(); + } + + NANOCLR_SET_AND_LEAVE(S_OK); + } + } + NANOCLR_FOREACH_NODE_END(); + } + + NANOCLR_SET_AND_LEAVE(CLR_E_LOCK_SYNCHRONIZATION_EXCEPTION); + + NANOCLR_NOCLEANUP(); +} + +void CLR_RT_HeapBlock_Lock::Relocate() +{ + NATIVE_PROFILE_CLR_CORE(); + m_resource.Relocate__HeapBlock(); +} + +void CLR_RT_HeapBlock_Lock::Relocate_Owner() +{ + NATIVE_PROFILE_CLR_CORE(); +} + diff --git a/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_LockRequest.cpp b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_LockRequest.cpp new file mode 100644 index 00000000..807f4fcb --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_LockRequest.cpp @@ -0,0 +1,29 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +HRESULT CLR_RT_HeapBlock_LockRequest::CreateInstance( CLR_RT_HeapBlock_Lock* lock, CLR_RT_SubThread* sth, const CLR_INT64& timeExpire, bool fForce ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_LockRequest* req = EVENTCACHE_EXTRACT_NODE(g_CLR_RT_EventCache,CLR_RT_HeapBlock_LockRequest,DATATYPE_LOCK_REQUEST_HEAD); CHECK_ALLOCATION(req); + + req->m_subthreadWaiting = sth; + req->m_timeExpire = timeExpire; CLR_RT_ExecutionEngine::InvalidateTimerCache(); + req->m_fForce = fForce; + + lock->m_requests.LinkAtBack( req ); + + sth->ChangeLockRequestCount( +1 ); + + NANOCLR_SET_AND_LEAVE(CLR_E_THREAD_WAITING); + + NANOCLR_NOCLEANUP(); +} + diff --git a/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Node.cpp b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Node.cpp new file mode 100644 index 00000000..1ece5611 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Node.cpp @@ -0,0 +1,16 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +void CLR_RT_HeapBlock_Node::Relocate() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_data.nodeLink.prevBlock ); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_data.nodeLink.nextBlock ); +} + diff --git a/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Queue.cpp b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Queue.cpp new file mode 100644 index 00000000..85b6c176 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Queue.cpp @@ -0,0 +1,173 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +#if (NANOCLR_SYSTEM_COLLECTIONS == TRUE) +#include + +HRESULT CLR_RT_HeapBlock_Queue::Dequeue( CLR_RT_HeapBlock*& value ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* array = GetArray(); + CLR_INT32 size = GetSize(); + CLR_INT32 head = Head(); + CLR_RT_HeapBlock* removed; + + if(size == 0) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + + removed = (CLR_RT_HeapBlock*)array->GetElement( head ); + + value = removed->Dereference(); + + removed->SetObjectReference( NULL ); + + SetHead( (head + 1) % array->m_numOfElements ); + + SetSize( size - 1 ); + + NANOCLR_NOCLEANUP(); +} + +// May Trigger GC, but parameter value will be protected +HRESULT CLR_RT_HeapBlock_Queue::Enqueue( CLR_RT_HeapBlock* value ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* array = GetArray(); + CLR_INT32 size = GetSize(); + CLR_INT32 tail = GetTail(); + CLR_INT32 capacity = array->m_numOfElements; + + if(size == capacity) + { + // Set new capacity + CLR_RT_HeapBlock newArrayHB; + + // Protect value from GC, in case CreateInstance triggers one + CLR_RT_HeapBlock valueHB; valueHB.SetObjectReference( value ); + CLR_RT_ProtectFromGC gc( valueHB ); + + capacity *= 2; + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( newArrayHB, capacity, g_CLR_RT_WellKnownTypes.m_Object )); + + array = newArrayHB.DereferenceArray(); + + CopyTo( array, 0 ); + + tail = size; + + SetArray( array ); + SetHead ( 0 ); + SetTail ( tail ); + } + + ((CLR_RT_HeapBlock*)array->GetElement( tail ))->SetObjectReference( value ); + + SetTail( (tail + 1) % capacity ); + + SetSize( size + 1 ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock_Queue::Peek( CLR_RT_HeapBlock*& value ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(GetSize() == 0) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + + value = ((CLR_RT_HeapBlock*)GetArray()->GetElement( Head() ))->Dereference(); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock_Queue::Clear() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* array = GetArray(); + CLR_INT32 size = GetSize(); + CLR_INT32 head = Head(); + CLR_INT32 tail = GetTail(); + + if(size > 0) + { + if(head < tail) + { + NANOCLR_CHECK_HRESULT(array->ClearElements( head, size )); + } + else + { + NANOCLR_CHECK_HRESULT(array->ClearElements( head, array->m_numOfElements - head )); + NANOCLR_CHECK_HRESULT(array->ClearElements( 0 , tail )); + } + + SetSize( 0 ); + } + + SetHead( 0 ); + SetTail( 0 ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock_Queue::ObjArrayMemcpy( CLR_RT_HeapBlock_Array* arraySrc, int indexSrc, CLR_RT_HeapBlock_Array* arrayDst, int indexDst, int length ) +{ + NANOCLR_HEADER(); + + memcpy( arraySrc->GetElement( indexSrc ), arrayDst->GetElement( indexDst ), length * sizeof(CLR_RT_HeapBlock) ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT CLR_RT_HeapBlock_Queue::CopyTo( CLR_RT_HeapBlock_Array* toArray, CLR_INT32 index ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* array = GetArray(); + CLR_INT32 size = GetSize(); + CLR_INT32 head = Head(); + CLR_INT32 tail = GetTail(); + + // if the target array is of type Object, we don't need to call the complex Array::Copy() since there will be no casting involved + HRESULT (*arrayCopy)( CLR_RT_HeapBlock_Array*, int, CLR_RT_HeapBlock_Array*, int, int ) = + (toArray->m_typeOfElement == DATATYPE_OBJECT) ? ObjArrayMemcpy : CLR_RT_HeapBlock_Array::Copy; + + if(((CLR_INT32)toArray->m_numOfElements) - index < size) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + if(size > 0) + { + if(head < tail) + { + NANOCLR_SET_AND_LEAVE(arrayCopy( array, head, toArray, index, size )); + } + else + { + CLR_INT32 firstPart = array->m_numOfElements - head; + + NANOCLR_CHECK_HRESULT(arrayCopy( array, head, toArray, index , firstPart )); + NANOCLR_SET_AND_LEAVE(arrayCopy( array, 0 , toArray, index + firstPart, tail )); + } + } + + NANOCLR_NOCLEANUP(); +} + +//--// + +CT_ASSERT(Library_nf_system_collections_System_Collections_Queue__FIELD___array == Library_nf_system_collections_System_Collections_Queue::FIELD___array); +CT_ASSERT(Library_nf_system_collections_System_Collections_Queue__FIELD___head == Library_nf_system_collections_System_Collections_Queue::FIELD___head ); +CT_ASSERT(Library_nf_system_collections_System_Collections_Queue__FIELD___tail == Library_nf_system_collections_System_Collections_Queue::FIELD___tail ); +CT_ASSERT(Library_nf_system_collections_System_Collections_Queue__FIELD___size == Library_nf_system_collections_System_Collections_Queue::FIELD___size ); + +#endif diff --git a/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Stack.cpp b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Stack.cpp new file mode 100644 index 00000000..0b64745a --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Stack.cpp @@ -0,0 +1,111 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "Core.h" + +#if (NANOCLR_SYSTEM_COLLECTIONS == TRUE) +#include + +//////////////////////////////////////////////////////////////////////////////////////////////////// +HRESULT CLR_RT_HeapBlock_Stack::Pop( CLR_RT_HeapBlock*& value ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* array = GetArray(); + CLR_INT32 size = GetSize(); + CLR_RT_HeapBlock* removed; + + if(size == 0) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + + removed = (CLR_RT_HeapBlock*)array->GetElement( array->m_numOfElements - size ); + + value = removed->Dereference(); + + removed->SetObjectReference( NULL ); + + SetSize( size - 1 ); + + NANOCLR_NOCLEANUP(); +} + +// May Trigger GC, but parameter value will be protected +HRESULT CLR_RT_HeapBlock_Stack::Push( CLR_RT_HeapBlock* value ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* array = GetArray(); + CLR_INT32 size = GetSize(); + CLR_INT32 capacity = array->m_numOfElements; + + if(size == capacity) + { + // Set new capacity + CLR_RT_HeapBlock newArrayHB; + CLR_RT_HeapBlock_Array* newArray; + + // Protect value from GC, in case CreateInstance triggers one + CLR_RT_HeapBlock valueHB; valueHB.SetObjectReference( value ); + CLR_RT_ProtectFromGC gc( valueHB ); + + capacity *= 2; + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( newArrayHB, capacity, g_CLR_RT_WellKnownTypes.m_Object )); + + newArray = newArrayHB.DereferenceArray(); + + memcpy( newArray->GetElement( size ), array->GetFirstElement(), size * sizeof(CLR_RT_HeapBlock) ); + + SetArray( newArray ); + array = newArray; + } + + size++; + + ((CLR_RT_HeapBlock*)array->GetElement( capacity - size ))->SetObjectReference( value ); + + SetSize( size ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock_Stack::Peek( CLR_RT_HeapBlock*& value ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* array = GetArray(); + CLR_INT32 size = GetSize(); + + if(size == 0) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + + value = ((CLR_RT_HeapBlock*)array->GetElement( array->m_numOfElements - size ))->Dereference(); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock_Stack::Clear() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* array = GetArray(); + CLR_INT32 size = GetSize(); + + NANOCLR_CHECK_HRESULT(array->ClearElements( array->m_numOfElements - size, size )); + + SetSize( 0 ); + + NANOCLR_NOCLEANUP(); +} + +//--// + +CT_ASSERT(Library_nf_system_collections_System_Collections_Stack__FIELD___array == Library_nf_system_collections_System_Collections_Stack::FIELD___array); +CT_ASSERT(Library_nf_system_collections_System_Collections_Stack__FIELD___size == Library_nf_system_collections_System_Collections_Stack::FIELD___size ); + +#endif diff --git a/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_String.cpp b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_String.cpp new file mode 100644 index 00000000..69b849df --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_String.cpp @@ -0,0 +1,116 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +CLR_RT_HeapBlock_String* CLR_RT_HeapBlock_String::CreateInstance( CLR_RT_HeapBlock& reference, CLR_UINT32 length ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_UINT32 totLength = sizeof(CLR_RT_HeapBlock_String) + length + 1; + CLR_RT_HeapBlock_String* str; + + reference.SetObjectReference( NULL ); + + str = (CLR_RT_HeapBlock_String*)g_CLR_RT_ExecutionEngine.ExtractHeapBytesForObjects( DATATYPE_STRING, 0, totLength ); + if(str) + { + char* szText = (char*)&str[ 1 ]; szText[ 0 ] = 0; + +#if defined(NANOCLR_NO_ASSEMBLY_STRINGS) + str->SetStringText( szText ); +#else + str->SetStringText( szText, NULL ); +#endif + + reference.SetObjectReference( str ); + } + + return str; +} + +HRESULT CLR_RT_HeapBlock_String::CreateInstance( CLR_RT_HeapBlock& reference, const char* szText ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(!szText) szText = ""; + + NANOCLR_SET_AND_LEAVE(CLR_RT_HeapBlock_String::CreateInstance( reference, szText, (CLR_UINT32)hal_strlen_s( szText ) )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock_String::CreateInstance( CLR_RT_HeapBlock& reference, const char* szText, CLR_UINT32 length ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_String* str; + char* szTextDst; + + str = CreateInstance( reference, length ); CHECK_ALLOCATION(str); + + szTextDst = (char*)str->StringText(); + + memcpy( szTextDst, szText, length ); szTextDst[ length ] = 0; + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock_String::CreateInstance( CLR_RT_HeapBlock& reference, const char* szText, CLR_RT_Assembly* assm ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_String* str; + + reference.SetObjectReference( NULL ); + + str = (CLR_RT_HeapBlock_String*)g_CLR_RT_ExecutionEngine.ExtractHeapBytesForObjects( DATATYPE_STRING, 0, sizeof(CLR_RT_HeapBlock_String) ); CHECK_ALLOCATION(str); + + reference.SetObjectReference( str ); + +#if defined(NANOCLR_NO_ASSEMBLY_STRINGS) + (void)szText; + (void)assm; + + NANOCLR_CHECK_HRESULT( CLR_RT_HeapBlock_String::CreateInstance( reference, szText ) ); +#else + str->SetStringText( szText, assm ); +#endif + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock_String::CreateInstance( CLR_RT_HeapBlock& reference, CLR_UINT32 token, CLR_RT_Assembly* assm ) +{ + NATIVE_PROFILE_CLR_CORE(); + return CreateInstance( reference, assm->GetString( CLR_DataFromTk( token ) ), assm ); +} + +HRESULT CLR_RT_HeapBlock_String::CreateInstance( CLR_RT_HeapBlock& reference, CLR_UINT16* szText, CLR_UINT32 length ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_UnicodeHelper uh; uh.SetInputUTF16 ( szText ); + CLR_UINT32 lengthInBytes = uh.CountNumberOfBytes( length ); + CLR_RT_HeapBlock_String* str = CreateInstance( reference, lengthInBytes ); CHECK_ALLOCATION(str); + + uh.m_outputUTF8 = (CLR_UINT8*)str->StringText(); + uh.m_outputUTF8_size = lengthInBytes + 1; + + uh.ConvertToUTF8( length, false ); + + NANOCLR_NOCLEANUP(); +} + +CLR_RT_HeapBlock_String* CLR_RT_HeapBlock_String::GetStringEmpty() +{ + return g_CLR_RT_TypeSystem.m_assemblyMscorlib->GetStaticField( Library_corlib_native_System_String::FIELD_STATIC__Empty )->DereferenceString(); +} + diff --git a/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Timer.cpp b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Timer.cpp new file mode 100644 index 00000000..f04bccb0 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_Timer.cpp @@ -0,0 +1,327 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + + HRESULT CLR_RT_HeapBlock_Timer::CreateInstance( CLR_UINT32 flags, CLR_RT_HeapBlock& owner, CLR_RT_HeapBlock& tmRef ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Timer* timer = NULL; + + // + // Create a request and stop the calling thread. + // + timer = EVENTCACHE_EXTRACT_NODE(g_CLR_RT_EventCache,CLR_RT_HeapBlock_Timer,DATATYPE_TIMER_HEAD); CHECK_ALLOCATION(timer); + + { + CLR_RT_ProtectFromGC gc( *timer ); + + timer->Initialize(); + + timer->m_flags = flags; + timer->m_timeExpire = TIMEOUT_INFINITE; + timer->m_timeFrequency = TIMEOUT_INFINITE; + timer->m_timeLastExpiration = 0; + timer->m_ticksLastExpiration = 0; + + g_CLR_RT_ExecutionEngine.m_timers.LinkAtBack( timer ); + + NANOCLR_SET_AND_LEAVE(CLR_RT_ObjectToEvent_Source::CreateInstance( timer, owner, tmRef )); + } + + NANOCLR_CLEANUP(); + + if(FAILED(hr)) + { + if(timer) timer->ReleaseWhenDead(); + } + + NANOCLR_CLEANUP_END(); +} + +HRESULT CLR_RT_HeapBlock_Timer::ExtractInstance( CLR_RT_HeapBlock& ref, CLR_RT_HeapBlock_Timer*& timer ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_ObjectToEvent_Source* src = CLR_RT_ObjectToEvent_Source::ExtractInstance( ref ); FAULT_ON_NULL(src); + + timer = (CLR_RT_HeapBlock_Timer*)src->m_eventPtr; + + NANOCLR_NOCLEANUP(); +} + +//--// + +void CLR_RT_HeapBlock_Timer::RecoverFromGC() +{ + NATIVE_PROFILE_CLR_CORE(); + CheckAll(); + + ReleaseWhenDead(); +} + +//--// + +void CLR_RT_HeapBlock_Timer::Trigger() +{ + NATIVE_PROFILE_CLR_CORE(); + if(m_references.IsEmpty()) return; + + if(m_flags & CLR_RT_HeapBlock_Timer::c_Executing) + { + return; + } + + m_flags |= CLR_RT_HeapBlock_Timer::c_Triggered; +} + +void CLR_RT_HeapBlock_Timer::SpawnTimer( CLR_RT_Thread* th ) +{ + NATIVE_PROFILE_CLR_CORE(); + //Only one managed timer max + _ASSERTE(m_references.NumOfNodes() == 1); + + CLR_RT_ObjectToEvent_Source* ref = (CLR_RT_ObjectToEvent_Source*)m_references.FirstValidNode(); + CLR_RT_HeapBlock* managedTimer = ref->m_objectPtr; + CLR_RT_HeapBlock* callback = &managedTimer[ Library_corlib_native_System_Threading_Timer::FIELD___callback ]; + CLR_RT_HeapBlock* state = &managedTimer[ Library_corlib_native_System_Threading_Timer::FIELD___state ]; + CLR_RT_HeapBlock_Delegate* delegate = callback->DereferenceDelegate(); + CLR_RT_ProtectFromGC gc( *managedTimer ); + + _ASSERTE(delegate != NULL); if(delegate == NULL) return; + _ASSERTE(delegate->DataType() == DATATYPE_DELEGATE_HEAD); + + m_ticksLastExpiration = HAL_Time_CurrentTime(); + m_timeLastExpiration = m_timeExpire; + m_timeExpire = TIMEOUT_INFINITE; + + if(SUCCEEDED(th->PushThreadProcDelegate( delegate ))) + { + CLR_RT_StackFrame* stack = th->FirstFrame(); + if(stack->Next() != NULL) + { + int numArgs = stack->m_call.m_target->numArgs; + if(numArgs > 0) + { + stack->m_arguments[ numArgs-1 ].Assign( *state ); + } + } + + // + // Associate the timer with the thread. + // + m_flags |= CLR_RT_HeapBlock_Timer::c_Executing; + m_flags &= ~CLR_RT_HeapBlock_Timer::c_Triggered; + + th->m_terminationCallback = CLR_RT_HeapBlock_Timer::ThreadTerminationCallback; + th->m_terminationParameter = this; + } +} + +void CLR_RT_HeapBlock_Timer::ThreadTerminationCallback( void* param ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock_Timer* pThis = (CLR_RT_HeapBlock_Timer*)param; + + pThis->m_flags &= ~CLR_RT_HeapBlock_Timer::c_Executing; + + pThis->Reschedule(); + + g_CLR_RT_ExecutionEngine.SpawnTimer(); +} + +void CLR_RT_HeapBlock_Timer::Reschedule() +{ + NATIVE_PROFILE_CLR_CORE(); + if((m_flags & CLR_RT_HeapBlock_Timer::c_Recurring ) && + (m_flags & CLR_RT_HeapBlock_Timer::c_EnabledTimer) ) + { + CLR_UINT64 expire = m_timeLastExpiration + m_timeFrequency; + + // + // Normally, adding the 'timeFrequency' will put the expiration in the future. + // + // If we fall back too much, we need to compute the next expiration in the future, to avoid an avalanche effect. + // + if(expire < HAL_Time_CurrentTime()) + { + expire = HAL_Time_CurrentTime() - ((HAL_Time_CurrentTime() - expire) % m_timeFrequency) + m_timeFrequency; + } + + m_timeExpire = expire; CLR_RT_ExecutionEngine::InvalidateTimerCache(); + } +} + +//--// + +void CLR_RT_HeapBlock_Timer::AdjustNextFixedExpire( const SYSTEMTIME& systemTime, bool fNext ) +{ + NATIVE_PROFILE_CLR_CORE(); + SYSTEMTIME st = systemTime; + CLR_INT64 baseTime; + CLR_INT64 add; + + CLR_RT_ExecutionEngine::InvalidateTimerCache(); + + switch(m_flags & CLR_RT_HeapBlock_Timer::c_AnyChange) + { + case CLR_RT_HeapBlock_Timer::c_SecondChange: add = TIME_CONVERSION__ONESECOND * (CLR_INT64)TIME_CONVERSION__TO_SECONDS; break; + case CLR_RT_HeapBlock_Timer::c_MinuteChange: add = TIME_CONVERSION__ONEMINUTE * (CLR_INT64)TIME_CONVERSION__TO_SECONDS; st.wSecond = 0; break; + case CLR_RT_HeapBlock_Timer::c_HourChange : add = TIME_CONVERSION__ONEHOUR * (CLR_INT64)TIME_CONVERSION__TO_SECONDS; st.wSecond = 0; st.wMinute = 0; break; + case CLR_RT_HeapBlock_Timer::c_DayChange : add = TIME_CONVERSION__ONEDAY * (CLR_INT64)TIME_CONVERSION__TO_SECONDS; st.wSecond = 0; st.wMinute = 0; st.wHour = 0; break; + + default : return; + } + + st.wMilliseconds = 0; + baseTime = HAL_Time_ConvertFromSystemTime( &st ); + + m_timeExpire = fNext ? baseTime + add : baseTime; + m_timeFrequency = add; + m_flags |= CLR_RT_HeapBlock_Timer::c_Recurring; +} + +bool CLR_RT_HeapBlock_Timer::CheckDisposed( CLR_RT_StackFrame& stack ) +{ + CLR_RT_HeapBlock* pThis = stack.This(); + CLR_RT_HeapBlock_Timer* timer; + + if(!FAILED(CLR_RT_HeapBlock_Timer::ExtractInstance( pThis[ Library_corlib_native_System_Threading_Timer::FIELD___timer ], timer ))) + { + if((timer->m_flags & CLR_RT_HeapBlock_Timer::c_ACTION_Destroy) == 0) + { + return false; + } + } + + return true; +} + +HRESULT CLR_RT_HeapBlock_Timer::ConfigureObject( CLR_RT_StackFrame& stack, CLR_UINT32 flags ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* pThis = stack.This(); + CLR_RT_HeapBlock* args = &(stack.Arg1()); + CLR_RT_HeapBlock_Timer* timer; + + const CLR_INT64 maxTime = (CLR_INT64)0x7FFFFFFF * (CLR_INT64)TIME_CONVERSION__TO_MILLISECONDS; + const CLR_INT64 minTime = 0; + + if(flags & CLR_RT_HeapBlock_Timer::c_ACTION_Create) + { + FAULT_ON_NULL(args[ 0 ].DereferenceDelegate()); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Timer::CreateInstance( 0, *pThis, pThis[ Library_corlib_native_System_Threading_Timer::FIELD___timer ] )); + + pThis[ Library_corlib_native_System_Threading_Timer::FIELD___callback ].Assign( args[ 0 ] ); + pThis[ Library_corlib_native_System_Threading_Timer::FIELD___state ].Assign( args[ 1 ] ); + + args += 2; + } + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Timer::ExtractInstance( pThis[ Library_corlib_native_System_Threading_Timer::FIELD___timer ], timer )); + + if(flags & CLR_RT_HeapBlock_Timer::c_ACTION_Create) + { + CLR_UINT32 anyChange = (flags & CLR_RT_HeapBlock_Timer::c_AnyChange); + + if(anyChange) + { + SYSTEMTIME systemTime; HAL_Time_ToSystemTime( HAL_Time_CurrentTime(), &systemTime ); + + timer->m_flags |= anyChange | CLR_RT_HeapBlock_Timer::c_EnabledTimer; + + timer->AdjustNextFixedExpire( systemTime, true ); + } + else + { + flags |= CLR_RT_HeapBlock_Timer::c_ACTION_Change; + } + } + + if(flags & CLR_RT_HeapBlock_Timer::c_ACTION_Destroy) + { + timer->m_flags &= ~CLR_RT_HeapBlock_Timer::c_EnabledTimer; + } + + if(flags & CLR_RT_HeapBlock_Timer::c_ACTION_Change) + { + // + // You cannot change a fixed timer after creation. + // + if(timer->m_flags & CLR_RT_HeapBlock_Timer::c_AnyChange) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + if(flags & CLR_RT_HeapBlock_Timer::c_INPUT_Int32) + { + timer->m_timeExpire = args[ 0 ].NumericByRef().s4; + timer->m_timeFrequency = args[ 1 ].NumericByRef().s4; + + if (timer->m_timeExpire == -1) timer->m_timeExpire = TIMEOUT_INFINITE; + if (timer->m_timeFrequency == -1) timer->m_timeFrequency = TIMEOUT_INFINITE; + } + else if(flags & CLR_RT_HeapBlock_Timer::c_INPUT_TimeSpan) + { + CLR_INT64* pVal; + + pVal = Library_corlib_native_System_TimeSpan::GetValuePtr( args[ 0 ] ); FAULT_ON_NULL(pVal); + if (*pVal == -c_TickPerMillisecond) timer->m_timeExpire = TIMEOUT_INFINITE; + else timer->m_timeExpire = *pVal; + + pVal = Library_corlib_native_System_TimeSpan::GetValuePtr( args[ 1 ] ); FAULT_ON_NULL(pVal); + if (*pVal == -c_TickPerMillisecond) timer->m_timeFrequency = TIMEOUT_INFINITE; + else timer->m_timeFrequency = *pVal; + } + + if(timer->m_timeExpire == TIMEOUT_INFINITE) + { + timer->m_flags &= ~CLR_RT_HeapBlock_Timer::c_EnabledTimer; + } + else + { + if(flags & CLR_RT_HeapBlock_Timer::c_INPUT_Int32) timer->m_timeExpire *= TIME_CONVERSION__TO_MILLISECONDS; + + if (minTime <= timer->m_timeExpire && timer->m_timeExpire <= maxTime) + { + timer->m_timeExpire += HAL_Time_CurrentTime(); + + timer->m_flags |= CLR_RT_HeapBlock_Timer::c_EnabledTimer; + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + } + } + + if(timer->m_timeFrequency == 0 || timer->m_timeFrequency == TIMEOUT_INFINITE) + { + timer->m_flags &= ~CLR_RT_HeapBlock_Timer::c_Recurring; + } + else + { + if(flags & CLR_RT_HeapBlock_Timer::c_INPUT_Int32) timer->m_timeFrequency *= TIME_CONVERSION__TO_MILLISECONDS; + + if(minTime <= timer->m_timeFrequency && timer->m_timeFrequency <= maxTime ) + { + timer->m_flags |= CLR_RT_HeapBlock_Timer::c_Recurring; + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + } + } + } + + CLR_RT_ExecutionEngine::InvalidateTimerCache(); + + NANOCLR_NOCLEANUP(); +} + diff --git a/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_WaitForObject.cpp b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_WaitForObject.cpp new file mode 100644 index 00000000..aa42285f --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapBlock_WaitForObject.cpp @@ -0,0 +1,189 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// CreateInstance - Creates a wait object +// +// Result - returns S_OK - if the target object is in the signaled state - indicating no wait is needed +// - returns CLR_E_THREAD_WAITING - if the target object is not signaled - indicating that the caller thread is waiting +// for the object to be signaled +// +HRESULT CLR_RT_HeapBlock_WaitForObject::CreateInstance( CLR_RT_Thread* caller, const CLR_INT64& timeExpire, CLR_RT_HeapBlock* objects, CLR_UINT32 cObjects, bool fWaitAll ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + // + // Create a request and stop the calling thread. + // + + _ASSERTE( sizeof(CLR_RT_HeapBlock_WaitForObject) % 4 == 0 ); + + CLR_UINT32 totLength = (CLR_UINT32)(sizeof(CLR_RT_HeapBlock_WaitForObject) + cObjects * sizeof(CLR_RT_HeapBlock)); + + CLR_RT_HeapBlock_WaitForObject* wait = EVENTCACHE_EXTRACT_NODE_AS_BYTES(g_CLR_RT_EventCache,CLR_RT_HeapBlock_WaitForObject,DATATYPE_WAIT_FOR_OBJECT_HEAD,0,totLength); CHECK_ALLOCATION(wait); + + wait->m_timeExpire = timeExpire; CLR_RT_ExecutionEngine::InvalidateTimerCache(); + wait->m_cObjects = cObjects; + wait->m_fWaitAll = fWaitAll; + + memcpy( wait->GetWaitForObjects(), objects, sizeof(CLR_RT_HeapBlock) * cObjects ); + + caller->m_waitForObject = wait; + caller->m_status = CLR_RT_Thread::TH_S_Waiting; + caller->m_waitForObject_Result = CLR_RT_Thread::TH_WAIT_RESULT_INIT; + + NANOCLR_SET_AND_LEAVE(CLR_E_THREAD_WAITING); + + NANOCLR_NOCLEANUP(); +} + +void CLR_RT_HeapBlock_WaitForObject::TryWaitForSignal( CLR_RT_Thread* th ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock_WaitForObject* wait = th->m_waitForObject; + + if(wait) + { + if (CLR_RT_HeapBlock_WaitForObject::TryWaitForSignal( th, wait->GetWaitForObjects(), wait->m_cObjects, wait->m_fWaitAll )) + { + th->Restart( true ); + } + } +} + +bool CLR_RT_HeapBlock_WaitForObject::TryWaitForSignal(CLR_RT_Thread* caller, CLR_RT_HeapBlock* objects, CLR_UINT32 cObjects, bool fWaitAll) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock* blk; + CLR_RT_HeapBlock* obj; + + if(fWaitAll) + { + //first time through, find out whether or not the requested objects are signaled + //second time through, reset the signalled objects + for(int phase = 0; phase < 2; phase++) + { + blk = objects; + for(CLR_UINT32 i = 0; i < cObjects; i++) + { + obj = blk->Dereference(); + _ASSERTE(obj != NULL); + + if(phase == 0) + { + if(!obj->IsFlagSet( CLR_RT_HeapBlock::HB_Signaled )) + { + return false; + } + } + else + { + if(obj->IsFlagSet( CLR_RT_HeapBlock::HB_SignalAutoReset )) + { + obj->ResetFlags( CLR_RT_HeapBlock::HB_Signaled ); + } + } + + blk++; + } + } + + caller->m_waitForObject_Result = CLR_RT_Thread::TH_WAIT_RESULT_HANDLE_ALL; + return true; + } + else + { + blk = objects; + for(CLR_UINT32 i = 0; i < cObjects; i++) + { + obj = blk->Dereference(); + _ASSERTE(obj != NULL); + + if(obj->IsFlagSet( CLR_RT_HeapBlock::HB_Signaled )) + { + if(obj->IsFlagSet( CLR_RT_HeapBlock::HB_SignalAutoReset )) + { + obj->ResetFlags( CLR_RT_HeapBlock::HB_Signaled ); + } + + caller->m_waitForObject_Result = CLR_RT_Thread::TH_WAIT_RESULT_HANDLE_0 + i; + return true; + } + + blk++; + } + } + + return false; +} + +void CLR_RT_HeapBlock_WaitForObject::SignalObject( CLR_RT_HeapBlock& object ) +{ + NATIVE_PROFILE_CLR_CORE(); + object.SetFlags( CLR_RT_HeapBlock::HB_Signaled ); + + NANOCLR_FOREACH_NODE(CLR_RT_Thread,th,g_CLR_RT_ExecutionEngine.m_threadsWaiting) + { + CLR_RT_HeapBlock_WaitForObject::TryWaitForSignal( th ); + + if(!object.IsFlagSet( CLR_RT_HeapBlock::HB_Signaled )) + { + _ASSERTE(object.IsFlagSet( CLR_RT_HeapBlock::HB_SignalAutoReset )); + //This is an AutoResetEvent. Since the event got unsignaled, we can break out of + //the loop early, as this object can only free one thread. + break; + } + } + NANOCLR_FOREACH_NODE_END(); +} + +HRESULT CLR_RT_HeapBlock_WaitForObject::WaitForSignal( CLR_RT_StackFrame& stack, const CLR_INT64& timeExpire, CLR_RT_HeapBlock* objects, CLR_UINT32 cObjects, bool fWaitAll ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(stack.m_customState == 0) + { + CLR_RT_HeapBlock* objectsT = objects; + + stack.m_customState = 1; + + if(cObjects > 64) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + for(CLR_UINT32 i = 0; i < cObjects; i++) + { + _ASSERTE(objects->DataType() == DATATYPE_OBJECT); + + FAULT_ON_NULL(objectsT->Dereference()); + + objectsT++; + } + + if(!TryWaitForSignal( stack.m_owningThread, objects, cObjects, fWaitAll )) + { + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_WaitForObject::CreateInstance( stack.m_owningThread, timeExpire, objects, cObjects, fWaitAll )); + } + } + + NANOCLR_NOCLEANUP(); +} + + +HRESULT CLR_RT_HeapBlock_WaitForObject::WaitForSignal ( CLR_RT_StackFrame& stack, const CLR_INT64& timeExpire, CLR_RT_HeapBlock& object ) +{ + NATIVE_PROFILE_CLR_CORE(); + return WaitForSignal( stack, timeExpire, &object, 1, false ); +} + +void CLR_RT_HeapBlock_WaitForObject::Relocate() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_GarbageCollector::Heap_Relocate( GetWaitForObjects(), m_cObjects ); +} + diff --git a/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapCluster.cpp b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapCluster.cpp new file mode 100644 index 00000000..bacf114f --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_HeapCluster.cpp @@ -0,0 +1,340 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +void CLR_RT_HeapCluster::HeapCluster_Initialize( CLR_UINT32 size, CLR_UINT32 blockSize ) +{ + NATIVE_PROFILE_CLR_CORE(); + GenericNode_Initialize(); + + size = (size - sizeof(*this)) / sizeof(CLR_RT_HeapBlock); + + m_freeList.DblLinkedList_Initialize(); // CLR_RT_DblLinkedList m_freeList; + m_payloadStart = (CLR_RT_HeapBlock_Node*)&this[ 1 ]; // CLR_RT_HeapBlock_Node* m_payloadStart; + m_payloadEnd = &m_payloadStart[ size ]; // CLR_RT_HeapBlock_Node* m_payloadEnd; + + // + // Scan memory looking for possible objects to salvage. This method returns false if HeapPersistence is stubbed + // which requires us to set up the free list. + // + // used to be CLR_RT_HeapBlock_WeakReference::PrepareForRecovery( CLR_RT_HeapBlock_Node* ptr, CLR_RT_HeapBlock_Node* end, CLR_UINT32 blockSize ) + + CLR_RT_HeapBlock_Node* ptr = m_payloadStart; + CLR_RT_HeapBlock_Node* end = m_payloadEnd; + + while(ptr < end) + { + if(ptr->DataType() == DATATYPE_WEAKCLASS) + { + CLR_RT_HeapBlock_WeakReference* weak = (CLR_RT_HeapBlock_WeakReference*)ptr; + + if(weak->DataSize() == CONVERTFROMSIZETOHEAPBLOCKS(sizeof(*weak)) && weak->m_targetSerialized != NULL && (weak->m_identity.m_flags & CLR_RT_HeapBlock_WeakReference::WR_SurviveBoot)) + { + weak->SetNext( NULL ); + weak->SetPrev( NULL ); + + weak->m_identity.m_flags &= ~CLR_RT_HeapBlock_WeakReference::WR_Persisted; + + weak->m_targetDirect = NULL; + + weak->MarkAlive(); + + ptr += ptr->DataSize(); + continue; + } + } + else if(ptr->DataType() == DATATYPE_SZARRAY) + { + CLR_RT_HeapBlock_Array* array = (CLR_RT_HeapBlock_Array*)ptr; + + if(array->m_typeOfElement == DATATYPE_U1 && array->m_fReference == 0) + { + CLR_UINT32 tot = sizeof(*array) + array->m_sizeOfElement * array->m_numOfElements; + + if(array->DataSize() == CONVERTFROMSIZETOHEAPBLOCKS(tot) && (ptr + ptr->DataSize()) <= end) + { + array->MarkAlive(); + + ptr += ptr->DataSize(); + continue; + } + } + } + + if((unsigned int)(ptr + blockSize) > (unsigned int)end) + { + blockSize = (CLR_UINT32)(end - ptr); + } + + ptr->SetDataId( CLR_RT_HEAPBLOCK_RAW_ID(DATATYPE_FREEBLOCK,0,blockSize) ); + ptr += blockSize; + } + + while(ptr < m_payloadEnd) + { + if((unsigned int)(ptr + blockSize) > (unsigned int)m_payloadEnd) + { + blockSize = (CLR_UINT32)(m_payloadEnd - ptr); + } + + ptr->SetDataId( CLR_RT_HEAPBLOCK_RAW_ID(DATATYPE_FREEBLOCK,0,blockSize) ); + ptr += blockSize; + } + + RecoverFromGC(); + + m_freeList.ValidateList(); +} + +CLR_RT_HeapBlock* CLR_RT_HeapCluster::ExtractBlocks( CLR_UINT32 dataType, CLR_UINT32 flags, CLR_UINT32 length ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock_Node* res = NULL; + CLR_UINT32 available = 0; + + m_freeList.ValidateList(); + + if(flags & CLR_RT_HeapBlock::HB_Event) + { + NANOCLR_FOREACH_NODE_BACKWARD(CLR_RT_HeapBlock_Node,ptr,m_freeList) + { + available = ptr->DataSize(); + + if(available >= length) + { + res = ptr; + break; + } + } + NANOCLR_FOREACH_NODE_BACKWARD_END(); + } + else + { + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Node,ptr,m_freeList) + { + available = ptr->DataSize(); + + if(available >= length) + { + res = ptr; + break; + } + } + NANOCLR_FOREACH_NODE_END(); + } + + if(res) + { + CLR_RT_HeapBlock_Node* next = res->Next(); + CLR_RT_HeapBlock_Node* prev = res->Prev(); + + available -= length; + + if(available != 0) + { + if(flags & CLR_RT_HeapBlock::HB_Event) + { + res->SetDataId( CLR_RT_HEAPBLOCK_RAW_ID(DATATYPE_FREEBLOCK,CLR_RT_HeapBlock::HB_Pinned,available) ); + + res += available; + } + else + { + CLR_RT_HeapBlock_Node* ptr = &res[ length ]; + + // + // Relink to the new free block. + // + ptr->SetDataId( CLR_RT_HEAPBLOCK_RAW_ID(DATATYPE_FREEBLOCK,CLR_RT_HeapBlock::HB_Pinned,available) ); + + ptr->SetNext( next ); + ptr->SetPrev( prev ); + + prev->SetNext( ptr ); + next->SetPrev( ptr ); + } + } + else + { + // + // Unlink the whole block. + // + prev->SetNext( next ); + next->SetPrev( prev ); + } + + res->SetDataId( CLR_RT_HEAPBLOCK_RAW_ID(dataType,flags,length) ); + + if(flags & CLR_RT_HeapBlock::HB_InitializeToZero) + { + res->InitializeToZero(); + } + else + { + res->Debug_ClearBlock( 0xCB ); + } + } + + m_freeList.ValidateList(); + + return res; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +void CLR_RT_HeapCluster::RecoverFromGC() +{ + NATIVE_PROFILE_CLR_CORE(); + + CLR_RT_HeapBlock_Node* ptr = m_payloadStart; + CLR_RT_HeapBlock_Node* end = m_payloadEnd; + + // + // Open the free list. + // + CLR_RT_HeapBlock_Node* last = m_freeList.Head(); last->SetPrev( NULL ); + + while(ptr < end) + { + + ValidateBlock( ptr ); + + if(ptr->IsAlive() == false) + { + CLR_RT_HeapBlock_Node* next = ptr; + CLR_UINT32 lenTot = 0; + + do + { + ValidateBlock( next ); + +#if defined(NANOCLR_PROFILE_NEW_ALLOCATIONS) + g_CLR_PRF_Profiler.TrackObjectDeletion( next ); +#endif + + NANOCLR_CHECK_EARLY_COLLECTION(next); + + int len = next->DataSize(); + + next += len; + lenTot += len; + + } while(next < end && next->IsAlive() == false); + + ptr->SetDataId( CLR_RT_HEAPBLOCK_RAW_ID(DATATYPE_FREEBLOCK,CLR_RT_HeapBlock::HB_Pinned,lenTot) ); + + // + // Link to the free list. + // + last->SetNext( ptr ); + ptr ->SetPrev( last ); + last = ptr; + + ptr->Debug_ClearBlock( 0xDF ); + + ptr = next; + } + else + { + if(ptr->IsEvent() == false) ptr->MarkDead(); + + ptr += ptr->DataSize(); + } + } + + // + // Close the free list. + // + last ->SetNext( m_freeList.Tail() ); + m_freeList.Tail()->SetPrev( last ); + m_freeList.Tail()->SetNext( NULL ); +} + +CLR_RT_HeapBlock_Node* CLR_RT_HeapCluster::InsertInOrder( CLR_RT_HeapBlock_Node* node, CLR_UINT32 size ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock_Node* ptr; + + NANOCLR_FOREACH_NODE__NODECL(CLR_RT_HeapBlock_Node,ptr,m_freeList) + { + if(ptr > node) break; + } + NANOCLR_FOREACH_NODE_END(); + + node->ClearData(); m_freeList.InsertBeforeNode( ptr, node ); + + // + // Try to coalesce with the following free block. + // + ptr = node->Next(); + if(ptr->Next() && (node + size) == ptr) + { + size += ptr->DataSize(); ptr->Unlink(); + } + + // + // Try to coalesce with the preceding free block. + // + ptr = node->Prev(); + if(ptr->Prev() && (ptr + ptr->DataSize()) == node) + { + size += ptr->DataSize(); node->Unlink(); node = ptr; + } + + node->SetDataId( CLR_RT_HEAPBLOCK_RAW_ID(DATATYPE_FREEBLOCK,CLR_RT_HeapBlock::HB_Pinned,size ) ); + node->Debug_ClearBlock( 0xCF ); + + return node; +} + +//--// + +#if NANOCLR_VALIDATE_HEAP >= NANOCLR_VALIDATE_HEAP_1_HeapBlocksAndUnlink + +void CLR_RT_HeapCluster::ValidateBlock( CLR_RT_HeapBlock* ptr ) +{ + NATIVE_PROFILE_CLR_CORE(); + + while(true) + { + if(ptr < m_payloadStart || ptr >= m_payloadEnd) + { + CLR_Debug::Printf( "Block beyond cluster limits: %08x [%08x : %08x-%08x]\r\n", (size_t)ptr, (size_t)this, (size_t)m_payloadStart, (size_t)m_payloadEnd ); + + break; + } + + if(ptr->DataType() >= DATATYPE_FIRST_INVALID) + { + CLR_Debug::Printf( "Bad Block Type: %08x %02x [%08x : %08x-%08x]\r\n", (size_t)ptr, ptr->DataType(), (size_t)this, (size_t)m_payloadStart, (size_t)m_payloadEnd ); + + break; + } + + if(ptr->DataSize() == 0) + { + CLR_Debug::Printf( "Bad Block null-size: %08x [%08x : %08x-%08x]\r\n", (size_t)ptr, (size_t)this, (size_t)m_payloadStart, (size_t)m_payloadEnd ); + + break; + } + + if(ptr + ptr->DataSize() > m_payloadEnd) + { + CLR_Debug::Printf( "Bad Block size: %d %08x [%08x : %08x-%08x]\r\n", ptr->DataSize(), (size_t)ptr, (size_t)this, (size_t)m_payloadStart, (size_t)m_payloadEnd ); + + break; + } + + return; + } + + NANOCLR_DEBUG_STOP(); +} + +#endif + diff --git a/source/native/nf-interpreter/src/CLR/Core/CLR_RT_Interop.cpp b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_Interop.cpp new file mode 100644 index 00000000..b49ac2e5 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_Interop.cpp @@ -0,0 +1,813 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "Core.h" + + +/********************************************************************** +** Macro: NANOCLR_INTEROP_CHECK_ARG_TYPE +** This macro is specific for Interop_Marshal_ functions. +** It checks that data type corresponds to the data type stored in heapblock +** in parameter paramIndex. +** In release mode macro does nothing. +**********************************************************************/ + + +// For the final product we disable checking of the argument types +// NANOCLR_INTEROP_CHECK_ARG_TYPE is reduced to nothing. +#define NANOCLR_INTEROP_CHECK_ARG_TYPE( arg_type ) +#define NANOCLR_INTEROP_NOCLEANUP() return S_OK; + + +HRESULT Interop_Marshal_bool( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, bool ¶m ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_INTEROP_CHECK_ARG_TYPE(DATATYPE_I4); +// The comparison with 0 converts numeric type "u1" to boolean type. + param = stackFrame.ArgN( paramIndex ).NumericByRef().u1 != 0; + NANOCLR_INTEROP_NOCLEANUP(); +} + +HRESULT Interop_Marshal_UINT8( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, unsigned char ¶m ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_INTEROP_CHECK_ARG_TYPE(DATATYPE_I4); + param = stackFrame.ArgN( paramIndex ).NumericByRef().u1; + NANOCLR_INTEROP_NOCLEANUP(); +} + +HRESULT Interop_Marshal_UINT16( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, signed short ¶m ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_INTEROP_CHECK_ARG_TYPE(DATATYPE_I4) + param = stackFrame.ArgN( paramIndex ).NumericByRef().u2; + NANOCLR_INTEROP_NOCLEANUP(); +} + +HRESULT Interop_Marshal_UINT32( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, signed int ¶m ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_INTEROP_CHECK_ARG_TYPE(DATATYPE_I4) + param = stackFrame.ArgN( paramIndex ).NumericByRef().u4; + NANOCLR_INTEROP_NOCLEANUP(); +} + +HRESULT Interop_Marshal_UINT64( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, unsigned __int64 ¶m ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_INTEROP_CHECK_ARG_TYPE(DATATYPE_I8); + param = stackFrame.ArgN( paramIndex ).NumericByRef().u8; + NANOCLR_INTEROP_NOCLEANUP(); +} + +HRESULT Interop_Marshal_CHAR( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, char ¶m ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_INTEROP_CHECK_ARG_TYPE(DATATYPE_I4) + param = stackFrame.ArgN( paramIndex ).NumericByRef().s1; + NANOCLR_INTEROP_NOCLEANUP(); +} + +HRESULT Interop_Marshal_INT8( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, signed char ¶m ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_INTEROP_CHECK_ARG_TYPE(DATATYPE_I4) + param = stackFrame.ArgN( paramIndex ).NumericByRef().s1; + NANOCLR_INTEROP_NOCLEANUP(); +} + +HRESULT Interop_Marshal_INT16( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, signed short ¶m ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_INTEROP_CHECK_ARG_TYPE(DATATYPE_I4); + param = stackFrame.ArgN( paramIndex ).NumericByRef().s2; + NANOCLR_INTEROP_NOCLEANUP(); +} + +HRESULT Interop_Marshal_INT32( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, signed int ¶m ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_INTEROP_CHECK_ARG_TYPE(DATATYPE_I4); + param = stackFrame.ArgN( paramIndex ).NumericByRef().s4; + NANOCLR_INTEROP_NOCLEANUP(); +} + +HRESULT Interop_Marshal_INT64( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, signed __int64 ¶m ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_INTEROP_CHECK_ARG_TYPE(DATATYPE_I8); + param = stackFrame.ArgN( paramIndex ).NumericByRef().s8; + NANOCLR_INTEROP_NOCLEANUP(); +} + +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + +HRESULT Interop_Marshal_float( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, float ¶m ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_INTEROP_CHECK_ARG_TYPE(DATATYPE_R4); + param = stackFrame.ArgN( paramIndex ).NumericByRef().r4; + NANOCLR_INTEROP_NOCLEANUP(); +} + +HRESULT Interop_Marshal_double( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, double ¶m ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_INTEROP_CHECK_ARG_TYPE(DATATYPE_R8); + param = stackFrame.ArgN( paramIndex ).NumericByRef().r8; + NANOCLR_INTEROP_NOCLEANUP(); +} +#else +HRESULT Interop_Marshal_float( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, signed int ¶m ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_INTEROP_CHECK_ARG_TYPE(DATATYPE_R4); + param = stackFrame.ArgN( paramIndex ).NumericByRef().r4; + NANOCLR_INTEROP_NOCLEANUP(); +} + +HRESULT Interop_Marshal_double( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, signed __int64 ¶m ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_INTEROP_CHECK_ARG_TYPE(DATATYPE_R8); + param = stackFrame.ArgN( paramIndex ).NumericByRef().r8; + NANOCLR_INTEROP_NOCLEANUP(); +} + +#endif + +HRESULT Interop_Marshal_LPCSTR( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, const char* ¶m ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + // Check the type of passed varialble - should be object for strings. + if ( stackFrame.ArgN( paramIndex ).DataType() != DATATYPE_OBJECT ) + { NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + // Checks that the string was actually present in managed code, not a NULL reference to sting. + param = stackFrame.ArgN( paramIndex ).RecoverString(); FAULT_ON_NULL(param); + + NANOCLR_NOCLEANUP(); +} + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +// For unsupported types we set param to zero and always return S_OK. +HRESULT Interop_Marshal_UNSUPPORTED_TYPE( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, UNSUPPORTED_TYPE ¶m ) +{ + NATIVE_PROFILE_CLR_CORE(); + param = NULL; + return S_OK; +} + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#undef NANOCLR_INTEROP_CHECK_ARG_TYPE +/********************************************************************** +** +** Function: Interop_Marshal_NUMERIC_ARRAY +** +** Synopsis: This function is used marshal arrays of basic types created by managed code. +** The native code can access and update array data. +** Thus the data can be exchanged between managed and native code in both directions. +** The native code cannot change size of array. +** +** Arguments: [stackFrame] - Reference to the managed stack frame. +** [paramIndex] - Index of parameter passed from managed code. This parameter will be updated now. +** [pByteParam] - Reference of pointer to buffer with array data. Filled by the function +** [arraySize] - Count of elements in array. Filled by the function +** [elementSize] - Size of array element in bytes. +** +** Returns: S_OK on success or error from StoreToReference. Error return would cause exception thrown in managed code. +**********************************************************************/ +template +static HRESULT Interop_Marshal_NUMERIC_ARRAY +( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, T *&pByteParam, unsigned int &arraySize, unsigned int elementSize ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array *pHeapBlockArray = NULL; + + if ( stackFrame.ArgN( paramIndex ).DataType() != DATATYPE_OBJECT ) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + pHeapBlockArray = stackFrame.ArgN( paramIndex ).DereferenceArray(); FAULT_ON_NULL(pHeapBlockArray); + + if ( pHeapBlockArray->m_sizeOfElement != elementSize ) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + arraySize = pHeapBlockArray->m_numOfElements; + pByteParam = (T *)pHeapBlockArray->GetFirstElement(); + + NANOCLR_NOCLEANUP(); +} + +/********************************************************************** +** Group of function that retrive array of values from managed stack frame. +** All these functions are wrappers around Interop_Marshal_NUMERIC_ARRAY, +** they create type safe interface for users of Interop library. +**********************************************************************/ +HRESULT Interop_Marshal_bool_ARRAY( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_UINT8 &typedArray ) +{ + NATIVE_PROFILE_CLR_CORE(); + return Interop_Marshal_NUMERIC_ARRAY( stackFrame, paramIndex, typedArray.m_pData, typedArray.m_ElemCount, sizeof( unsigned char ) ); +} + +HRESULT Interop_Marshal_UINT8_ARRAY( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_UINT8 &typedArray ) +{ + NATIVE_PROFILE_CLR_CORE(); + return Interop_Marshal_NUMERIC_ARRAY( stackFrame, paramIndex, typedArray.m_pData, typedArray.m_ElemCount, sizeof( unsigned char ) ); +} + +HRESULT Interop_Marshal_UINT16_ARRAY( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_UINT16 &typedArray ) +{ + NATIVE_PROFILE_CLR_CORE(); + return Interop_Marshal_NUMERIC_ARRAY( stackFrame, paramIndex, typedArray.m_pData, typedArray.m_ElemCount, sizeof( unsigned short ) ); +} + +HRESULT Interop_Marshal_UINT32_ARRAY( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_UINT32 &typedArray ) +{ + NATIVE_PROFILE_CLR_CORE(); + return Interop_Marshal_NUMERIC_ARRAY( stackFrame, paramIndex, typedArray.m_pData, typedArray.m_ElemCount, sizeof( unsigned int ) ); +} + +HRESULT Interop_Marshal_UINT64_ARRAY( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_UINT64 &typedArray ) +{ + NATIVE_PROFILE_CLR_CORE(); + return Interop_Marshal_NUMERIC_ARRAY( stackFrame, paramIndex, typedArray.m_pData, typedArray.m_ElemCount, sizeof( unsigned __int64 ) ); +} + +HRESULT Interop_Marshal_CHAR_ARRAY( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_CHAR &typedArray ) +{ + NATIVE_PROFILE_CLR_CORE(); + return Interop_Marshal_NUMERIC_ARRAY( stackFrame, paramIndex, typedArray.m_pData, typedArray.m_ElemCount, sizeof( char ) ); +} + +HRESULT Interop_Marshal_INT8_ARRAY( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_INT8 &typedArray ) +{ + NATIVE_PROFILE_CLR_CORE(); + return Interop_Marshal_NUMERIC_ARRAY( stackFrame, paramIndex, typedArray.m_pData, typedArray.m_ElemCount, sizeof( signed char ) ); +} + +HRESULT Interop_Marshal_INT16_ARRAY( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_INT16 &typedArray ) +{ + NATIVE_PROFILE_CLR_CORE(); + return Interop_Marshal_NUMERIC_ARRAY( stackFrame, paramIndex, typedArray.m_pData, typedArray.m_ElemCount, sizeof( signed short ) ); +} + +HRESULT Interop_Marshal_INT32_ARRAY( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_INT32 &typedArray ) +{ + NATIVE_PROFILE_CLR_CORE(); + return Interop_Marshal_NUMERIC_ARRAY( stackFrame, paramIndex, typedArray.m_pData, typedArray.m_ElemCount, sizeof( signed int ) ); +} + +HRESULT Interop_Marshal_INT64_ARRAY( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_INT64 &typedArray ) +{ + NATIVE_PROFILE_CLR_CORE(); + return Interop_Marshal_NUMERIC_ARRAY( stackFrame, paramIndex, typedArray.m_pData, typedArray.m_ElemCount, sizeof( signed __int64 ) ); +} + +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) +HRESULT Interop_Marshal_float_ARRAY( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_float &typedArray ) +{ + NATIVE_PROFILE_CLR_CORE(); + return Interop_Marshal_NUMERIC_ARRAY( stackFrame, paramIndex, typedArray.m_pData, typedArray.m_ElemCount, sizeof( float ) ); +} + +HRESULT Interop_Marshal_double_ARRAY( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_double &typedArray ) +{ + NATIVE_PROFILE_CLR_CORE(); + return Interop_Marshal_NUMERIC_ARRAY( stackFrame, paramIndex, typedArray.m_pData, typedArray.m_ElemCount, sizeof( double ) ); +} +#else + +HRESULT Interop_Marshal_float_ARRAY( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_float &typedArray ) +{ + NATIVE_PROFILE_CLR_CORE(); + return Interop_Marshal_NUMERIC_ARRAY( stackFrame, paramIndex, typedArray.m_pData, typedArray.m_ElemCount, sizeof( signed int ) ); +} + +HRESULT Interop_Marshal_double_ARRAY( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_double &typedArray ) +{ + NATIVE_PROFILE_CLR_CORE(); + return Interop_Marshal_NUMERIC_ARRAY( stackFrame, paramIndex, typedArray.m_pData, typedArray.m_ElemCount, sizeof( signed __int64 ) ); +} + +#endif + + +/********************************************************************** +** +** Functions: SetResult_* +** +** Synopsis: This group of functions set result returned by native function to managed stack frame. +** It stores data from heap block pointed by pVoidHeapBlock back to the managed stack frame. +** +** Arguments: [stackFrame] - Reference to the managed stack frame. +** [pVoidHeapBlock] - Pointer to heap block that keeps updated basic type value +** [paramIndex] - Index of parameter passed from managed code. This parameter will be updated now. +** +** Returns: S_OK on success or error from StoreToReference. Error return would cause exception thrown in managed code. +**********************************************************************/ + +void SetResult_bool( CLR_RT_StackFrame &stackFrame, bool value ) +{ + NATIVE_PROFILE_CLR_CORE(); + stackFrame.SetResult_Boolean( value ); +} + +void SetResult_CHAR( CLR_RT_StackFrame &stackFrame, char value ) +{ + NATIVE_PROFILE_CLR_CORE(); + stackFrame.SetResult( value, DATATYPE_I1 ); +} + +void SetResult_INT8( CLR_RT_StackFrame &stackFrame, signed char value ) +{ + NATIVE_PROFILE_CLR_CORE(); + stackFrame.SetResult( value, DATATYPE_I1 ); +} + +void SetResult_INT16( CLR_RT_StackFrame &stackFrame, signed short value ) +{ + NATIVE_PROFILE_CLR_CORE(); + stackFrame.SetResult( value, DATATYPE_I2 ); +} + +void SetResult_INT32( CLR_RT_StackFrame &stackFrame, signed int value ) +{ + NATIVE_PROFILE_CLR_CORE(); + stackFrame.SetResult( value, DATATYPE_I4 ); +} + +void SetResult_INT64( CLR_RT_StackFrame &stackFrame, signed __int64 value ) +{ + NATIVE_PROFILE_CLR_CORE(); + stackFrame.SetResult_I8( value ); +} + +void SetResult_UINT8( CLR_RT_StackFrame &stackFrame, unsigned char value ) +{ + NATIVE_PROFILE_CLR_CORE(); + stackFrame.SetResult( value, DATATYPE_U1 ); +} + +void SetResult_UINT16( CLR_RT_StackFrame &stackFrame, signed short value ) +{ + NATIVE_PROFILE_CLR_CORE(); + stackFrame.SetResult( value, DATATYPE_U2 ); +} + +void SetResult_UINT32( CLR_RT_StackFrame &stackFrame, signed int value ) +{ + NATIVE_PROFILE_CLR_CORE(); + stackFrame.SetResult( value, DATATYPE_U4 ); +} + +void SetResult_UINT64( CLR_RT_StackFrame &stackFrame, unsigned __int64 value ) +{ + NATIVE_PROFILE_CLR_CORE(); + stackFrame.SetResult_U8( value ); +} +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) +void SetResult_float( CLR_RT_StackFrame &stackFrame, float value ) +{ + NATIVE_PROFILE_CLR_CORE(); + stackFrame.SetResult_R4( value ); +} + +void SetResult_double( CLR_RT_StackFrame &stackFrame, double value ) +{ + NATIVE_PROFILE_CLR_CORE(); + stackFrame.SetResult_R8( value ); +} +#else +void SetResult_float( CLR_RT_StackFrame &stackFrame, CLR_INT32 value ) +{ + NATIVE_PROFILE_CLR_CORE(); + stackFrame.SetResult_R4( value ); +} + +void SetResult_double( CLR_RT_StackFrame &stackFrame, CLR_INT64& value ) +{ + NATIVE_PROFILE_CLR_CORE(); + stackFrame.SetResult_R8( value ); +} +#endif + +void SetResult_LPCSTR( CLR_RT_StackFrame &stackFrame, const char* lpszString ) +{ + NATIVE_PROFILE_CLR_CORE(); + stackFrame.SetResult_String( lpszString ); +} + +/********************************************************************** +** +** Group of function that retrive reference to particular type from managed stack frame. +** This function hides CLR_RT_HeapBlock structure. +** +** Functions: Interop_Marshal_*_ByRef +** +** Synopsis: For paramenters passed by reference gets the +** reference to basic type parameter. +** After the call the pParam points to variable passed by reference from managed code. +** +** Arguments: [stackFrame] - Reference to the managed stack frame. +** [pHeapBlock] - Pointer to heap block that keeps reference type extracted from managed stack frame +** [paramIndex] - Index of parameter passed from managed code. +** [pParam] - Pointer to variable passed by reference from managed code. Filled by function. +** +** Returns: S_OK on success or error from LoadFromReference of CLR_E_WRONG_TYPE if type invalid. Error return would cause exception thrown in managed code. +**********************************************************************/ + +/********************************************************************** +** Macro: NANOCLR_INTEROP_CHECK_REF_TYPE +** This macro is specific for Interop_Marshal_*_ByRef functions. +** It checks that retrived type corresponds to the data type stored in heapblock +** in parameter paramIndex. +** In release mode macro does nothing. +**********************************************************************/ + +#if defined(_DEBUG) + +// In debug mode check reference type. +#define NANOCLR_INTEROP_CHECK_REF_TYPE( ref_type ) \ +if ( ((CLR_RT_HeapBlock *)pHeapBlock)->DataType() != ref_type ) \ +{ \ + NANOCLR_SET_AND_LEAVE( CLR_E_WRONG_TYPE ); \ +} + +#else // Not defined _DEBUG, means we are in release mode - do nothing. + +#define NANOCLR_INTEROP_CHECK_REF_TYPE( ref_type ) + +#endif + +//------------------ Unsigned Integral types ---------------------------------------------------------------------------- +HRESULT Interop_Marshal_bool_ByRef( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, unsigned char *&pParam ) +{ + NATIVE_PROFILE_CLR_CORE(); + // Declare hRes ( #define NANOCLR_HEADER() HRESULT hr ) + NANOCLR_HEADER(); + + // Loads heapblock data from heapblock in managed stack frame + NANOCLR_CHECK_HRESULT(((CLR_RT_HeapBlock *)pHeapBlock)->LoadFromReference( stackFrame.ArgN(paramIndex) )); + + // Validates that data in heapblock correspond to requested parameter. + NANOCLR_INTEROP_CHECK_REF_TYPE(DATATYPE_U1) + + // Now we have initialized pHeapBlock with reference paramenter. + // Need to cast the pointer because &s1 is "CLR_INT8 *", while we need "bool *" + pParam = &((CLR_RT_HeapBlock *)pHeapBlock)->NumericByRef().u1; + + // Return S_OK or error if there is "go to" from NANOCLR_CHECK_HRESULT or NANOCLR_SET_AND_LEAVE + NANOCLR_NOCLEANUP(); +} + +HRESULT Interop_Marshal_UINT8_ByRef( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, unsigned char *&pParam ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + NANOCLR_CHECK_HRESULT(((CLR_RT_HeapBlock *)pHeapBlock)->LoadFromReference( stackFrame.ArgN(paramIndex) )); + NANOCLR_INTEROP_CHECK_REF_TYPE(DATATYPE_U1) + pParam = &((CLR_RT_HeapBlock *)pHeapBlock)->NumericByRef().u1; + NANOCLR_NOCLEANUP(); +} + +HRESULT Interop_Marshal_UINT16_ByRef( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, unsigned short *&pParam ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + NANOCLR_CHECK_HRESULT(((CLR_RT_HeapBlock *)pHeapBlock)->LoadFromReference( stackFrame.ArgN(paramIndex) )); + NANOCLR_INTEROP_CHECK_REF_TYPE(DATATYPE_U2) + pParam = &((CLR_RT_HeapBlock *)pHeapBlock)->NumericByRef().u2; + NANOCLR_NOCLEANUP(); +} + +HRESULT Interop_Marshal_UINT32_ByRef( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, unsigned int *&pParam ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + NANOCLR_CHECK_HRESULT(((CLR_RT_HeapBlock *)pHeapBlock)->LoadFromReference( stackFrame.ArgN(paramIndex) )); + NANOCLR_INTEROP_CHECK_REF_TYPE(DATATYPE_U4) + pParam = &((CLR_RT_HeapBlock *)pHeapBlock)->NumericByRef().u4; + NANOCLR_NOCLEANUP(); +} + +HRESULT Interop_Marshal_UINT64_ByRef( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, unsigned __int64 *&pParam ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + NANOCLR_CHECK_HRESULT(((CLR_RT_HeapBlock *)pHeapBlock)->LoadFromReference( stackFrame.ArgN(paramIndex) )); + NANOCLR_INTEROP_CHECK_REF_TYPE(DATATYPE_U8) + pParam = (unsigned __int64 *)&((CLR_RT_HeapBlock *)pHeapBlock)->NumericByRef().u8; + NANOCLR_NOCLEANUP(); +} + +//------------------ Signed Integral types ---------------------------------------------------------------------------- +HRESULT Interop_Marshal_CHAR_ByRef( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, char *&pParam ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + NANOCLR_CHECK_HRESULT(((CLR_RT_HeapBlock *)pHeapBlock)->LoadFromReference( stackFrame.ArgN(paramIndex) )); + NANOCLR_INTEROP_CHECK_REF_TYPE(DATATYPE_CHAR) + pParam = (char *)&((CLR_RT_HeapBlock *)pHeapBlock)->NumericByRef().s1; + NANOCLR_NOCLEANUP(); +} + +HRESULT Interop_Marshal_INT8_ByRef( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, signed char *&pParam ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + NANOCLR_CHECK_HRESULT(((CLR_RT_HeapBlock *)pHeapBlock)->LoadFromReference( stackFrame.ArgN(paramIndex) )); + // signed char servers for both boolean and sbyte types. So we check for either of them. +#if defined(_DEBUG) + if ( !( ((CLR_RT_HeapBlock *)pHeapBlock)->DataType() == DATATYPE_I1 || + ((CLR_RT_HeapBlock *)pHeapBlock)->DataType() == DATATYPE_BOOLEAN ) + ) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } +#endif + pParam = &((CLR_RT_HeapBlock *)pHeapBlock)->NumericByRef().s1; + NANOCLR_NOCLEANUP(); +} + +HRESULT Interop_Marshal_INT16_ByRef( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, signed short *&pParam ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + NANOCLR_CHECK_HRESULT(((CLR_RT_HeapBlock *)pHeapBlock)->LoadFromReference( stackFrame.ArgN(paramIndex) )); + NANOCLR_INTEROP_CHECK_REF_TYPE(DATATYPE_I2) + pParam = &((CLR_RT_HeapBlock *)pHeapBlock)->NumericByRef().s2; + NANOCLR_NOCLEANUP(); +} + +HRESULT Interop_Marshal_INT32_ByRef( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, signed int *&pParam ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + NANOCLR_CHECK_HRESULT(((CLR_RT_HeapBlock *)pHeapBlock)->LoadFromReference( stackFrame.ArgN(paramIndex) )); + NANOCLR_INTEROP_CHECK_REF_TYPE(DATATYPE_I4) + pParam = &((CLR_RT_HeapBlock *)pHeapBlock)->NumericByRef().s4; + NANOCLR_NOCLEANUP(); +} + +HRESULT Interop_Marshal_INT64_ByRef( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, signed __int64 *&pParam ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + NANOCLR_CHECK_HRESULT(((CLR_RT_HeapBlock *)pHeapBlock)->LoadFromReference( stackFrame.ArgN(paramIndex) )); + NANOCLR_INTEROP_CHECK_REF_TYPE(DATATYPE_I8) + pParam = (signed __int64 *)&((CLR_RT_HeapBlock *)pHeapBlock)->NumericByRef().s8; + NANOCLR_NOCLEANUP(); +} + +//----------------- Float point types - float and double +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + +HRESULT Interop_Marshal_float_ByRef( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, float *&pParam ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + NANOCLR_CHECK_HRESULT(((CLR_RT_HeapBlock *)pHeapBlock)->LoadFromReference( stackFrame.ArgN(paramIndex) )); + NANOCLR_INTEROP_CHECK_REF_TYPE(DATATYPE_R4) + pParam = &((CLR_RT_HeapBlock *)pHeapBlock)->NumericByRef().r4; + NANOCLR_NOCLEANUP(); +} + +HRESULT Interop_Marshal_double_ByRef( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, double *&pParam ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + NANOCLR_CHECK_HRESULT(((CLR_RT_HeapBlock *)pHeapBlock)->LoadFromReference( stackFrame.ArgN(paramIndex) )); + NANOCLR_INTEROP_CHECK_REF_TYPE(DATATYPE_R8) + pParam = (double *)&((CLR_RT_HeapBlock *)pHeapBlock)->NumericByRef().r8; + NANOCLR_NOCLEANUP(); +} + + +//----------------- Non Float point types - float and double +#else +HRESULT Interop_Marshal_float_ByRef( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, signed int *&pParam ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + NANOCLR_CHECK_HRESULT(((CLR_RT_HeapBlock *)pHeapBlock)->LoadFromReference( stackFrame.ArgN(paramIndex) )); + NANOCLR_INTEROP_CHECK_REF_TYPE(DATATYPE_R4) + pParam = (signed int *)&((CLR_RT_HeapBlock *)pHeapBlock)->NumericByRef().r4; + NANOCLR_NOCLEANUP(); +} + +HRESULT Interop_Marshal_double_ByRef( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, signed __int64* &pParam ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + NANOCLR_CHECK_HRESULT(((CLR_RT_HeapBlock *)pHeapBlock)->LoadFromReference( stackFrame.ArgN(paramIndex) )); + NANOCLR_INTEROP_CHECK_REF_TYPE(DATATYPE_R8) + pParam = (signed __int64 *)&((CLR_RT_HeapBlock *)pHeapBlock)->NumericByRef().r8; + NANOCLR_NOCLEANUP(); +} + +#endif +HRESULT Interop_Marshal_UNSUPPORTED_TYPE_ByRef( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, UNSUPPORTED_TYPE *&pParam ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + NANOCLR_CHECK_HRESULT(((CLR_RT_HeapBlock *)pHeapBlock)->LoadFromReference( stackFrame.ArgN(paramIndex) )); + pParam = NULL; + NANOCLR_NOCLEANUP(); +} + + +#undef NANOCLR_INTEROP_CHECK_REF_TYPE + + +/********************************************************************** +** +** Function: Interop_Marshal_StoreRef +** +** Synopsis: Stores data from the heap block passed in pVoidHeapBlock back to managed stack frame. +** Thus the managed stack frame and application may receive modified value of variable passed by reference.. +** +** Arguments: [stackFrame] - Reference to the managed stack frame. +** [pVoidHeapBlock] - Pointer to heap block that keeps updated value of variable passed by reference. +** [paramIndex] - Index of parameter passed from managed code. +** +** Returns: S_OK on success or error from StoreToReference. Error return would cause exception thrown in managed code. +**********************************************************************/ + +HRESULT Interop_Marshal_StoreRef( CLR_RT_StackFrame &stackFrame, void *pVoidHeapBlock, unsigned int paramIndex ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + CLR_RT_HeapBlock *pHeapBlock = (CLR_RT_HeapBlock *)pVoidHeapBlock; + NANOCLR_CHECK_HRESULT(pHeapBlock->StoreToReference( stackFrame.ArgN(paramIndex), 0 )); + NANOCLR_NOCLEANUP(); +} + +CLR_RT_HeapBlock* Interop_Marshal_RetrieveManagedObject( CLR_RT_StackFrame &stackFrame ) + +{ + return stackFrame.This(); +} + +/********************************************************************** +** +** Functions: Interop_Marshal_GetField_ +** +** Synopsis: Retrieves C++ reference ( pointer ) to the field in managed object. +** +** Arguments: [pThis] - Pointer to the managed object retrieved by Interop_Marshal_RetrieveManagedObject. +** [fieldIndex] - Field index. +** +** Returns: Reference to the field. +**********************************************************************/ + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstrict-aliasing" +#endif + +bool &Interop_Marshal_GetField_bool( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ) +{ + return (bool&)pThis[ fieldIndex ].NumericByRef().u1; +} + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +unsigned char &Interop_Marshal_GetField_UINT8( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ) +{ + return pThis[ fieldIndex ].NumericByRef().u1; +} + +unsigned short &Interop_Marshal_GetField_UINT16( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ) +{ + return pThis[ fieldIndex ].NumericByRef().u2; +} + +unsigned int &Interop_Marshal_GetField_UINT32( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ) +{ + return pThis[ fieldIndex ].NumericByRef().u4; +} + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstrict-aliasing" +#endif + +unsigned __int64 &Interop_Marshal_GetField_UINT64( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ) +{ + return (unsigned __int64 &)pThis[ fieldIndex ].NumericByRef().u8; +} + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +char &Interop_Marshal_GetField_CHAR( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ) +{ + return (char &)pThis[ fieldIndex ].NumericByRef().s1; +} + +signed char &Interop_Marshal_GetField_INT8( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ) +{ + return pThis[ fieldIndex ].NumericByRef().s1; +} + +signed short &Interop_Marshal_GetField_INT16( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ) +{ + return pThis[ fieldIndex ].NumericByRef().s2; +} + +signed int &Interop_Marshal_GetField_INT32( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ) +{ + return pThis[ fieldIndex ].NumericByRef().s4; +} + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstrict-aliasing" +#endif + +signed __int64 &Interop_Marshal_GetField_INT64( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ) +{ + return (signed __int64 &)pThis[ fieldIndex ].NumericByRef().s8; +} + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +//----------------- Float point types - float and double +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + +float &Interop_Marshal_GetField_float( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ) +{ + return pThis[ fieldIndex ].NumericByRef().r4; +} + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstrict-aliasing" +#endif + +double &Interop_Marshal_GetField_double( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ) +{ + return (double &)pThis[ fieldIndex ].NumericByRef().r8; +} + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#else + +signed int &Interop_Marshal_GetField_float( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ) +{ + return (signed int &) pThis[ fieldIndex ].NumericByRef().r4; +} + +signed __int64 &Interop_Marshal_GetField_double( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ) +{ + return (signed __int64 &)pThis[ fieldIndex ].NumericByRef().r8; +} + + +#endif + +#if defined(__arm) +#pragma push +#pragma diag_suppress 284 +#endif +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif +UNSUPPORTED_TYPE &Interop_Marshal_GetField_UNSUPPORTED_TYPE( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ) +{ + return (UNSUPPORTED_TYPE &)(*((UNSUPPORTED_TYPE *)NULL)); +} +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif +#if defined(__arm) +#pragma pop +#endif + diff --git a/source/native/nf-interpreter/src/CLR/Core/CLR_RT_Memory.cpp b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_Memory.cpp new file mode 100644 index 00000000..493bf048 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_Memory.cpp @@ -0,0 +1,208 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#if defined(NANOCLR_TRACE_MALLOC) +static CLR_UINT32 s_TotalAllocated; +#endif + +CLR_RT_MemoryRange s_CLR_RT_Heap = { 0, 0 }; + +static int s_PreHeapInitIndex = 0; + +//////////////////////////////////////////////////////////// + + + +//--// + +void CLR_RT_Memory::Reset() +{ + NATIVE_PROFILE_CLR_CORE(); + ::HeapLocation( s_CLR_RT_Heap.m_location, s_CLR_RT_Heap.m_size ); + +#if defined(NANOCLR_TRACE_MALLOC) + s_TotalAllocated = 0; +#endif +} + +void* CLR_RT_Memory::SubtractFromSystem( size_t len ) +{ + NATIVE_PROFILE_CLR_CORE(); + len = ROUNDTOMULTIPLE(len,CLR_UINT32); + + if(len <= s_CLR_RT_Heap.m_size) + { + s_CLR_RT_Heap.m_size -= (CLR_UINT32)len; + + return &s_CLR_RT_Heap.m_location[ s_CLR_RT_Heap.m_size ]; + } + + return NULL; +} + +//--// + +#if defined(NANOCLR_FILL_MEMORY_WITH_DIRTY_PATTERN) + +#define DEBUG_POINTER_INCREMENT(ptr,size) ptr = (void*)((char*)ptr + (size)) +#define DEBUG_POINTER_DECREMENT(ptr,size) ptr = (void*)((char*)ptr - (size)) + +const CLR_UINT32 c_extra = sizeof(CLR_RT_HeapBlock) * 2; + +#endif + + +void CLR_RT_Memory::Release( void* ptr ) +{ + NATIVE_PROFILE_CLR_CORE(); + + // CLR heap not initialized yet, return (this is not an error condition because we allow pre + if(s_CLR_RT_Heap.m_size == 0) + { + return; + } + + if(ptr) + { +#if defined(NANOCLR_FILL_MEMORY_WITH_DIRTY_PATTERN) + DEBUG_POINTER_DECREMENT(ptr,c_extra+sizeof(CLR_UINT32)); +#endif + + CLR_RT_HeapBlock_BinaryBlob* pThis = CLR_RT_HeapBlock_BinaryBlob::GetBlob( ptr ); + + if(pThis->DataType() != DATATYPE_BINARY_BLOB_HEAD) + { + NANOCLR_STOP(); + } + else + { +#if defined(NANOCLR_FILL_MEMORY_WITH_DIRTY_PATTERN) + CLR_UINT32 len = *(CLR_UINT32*)ptr; + CLR_UINT8* blk; + CLR_UINT32 pos; + + for(pos=0, blk=(CLR_UINT8*)ptr + sizeof(len); posDataSize(); + CLR_Debug::Printf( "CLR_RT_Memory::Release : %08x = %3d blocks (tot %4d)\r\n", ptr, pThis->DataSize(), s_TotalAllocated ); +#endif + + pThis->Release( true ); + } + } +} + +void* CLR_RT_Memory::Allocate( size_t len, CLR_UINT32 flags ) +{ + NATIVE_PROFILE_CLR_CORE(); + + if(s_CLR_RT_Heap.m_size == 0) + { + unsigned char* heapStart = NULL; + unsigned int heapSize = 0; + + ::HeapLocation( heapStart, heapSize ); + + if(len > heapSize) + { + ASSERT(false); + return NULL; + + } + + // use the current index to prevent heap thrashing before initialization + heapStart = &heapStart[ s_PreHeapInitIndex ]; + + s_PreHeapInitIndex += len; + + return heapStart; + } + + flags |= CLR_RT_HeapBlock::HB_Event; + +#if defined(NANOCLR_FILL_MEMORY_WITH_DIRTY_PATTERN) + len += c_extra * 2 + sizeof(CLR_UINT32); +#endif + + CLR_RT_HeapBlock_BinaryBlob* obj = CLR_RT_HeapBlock_BinaryBlob::Allocate( (CLR_UINT32)len, flags ); + if(obj) + { + void* res = obj->GetData(); + +#if defined(NANOCLR_TRACE_MALLOC) + s_TotalAllocated += obj->DataSize(); + CLR_Debug::Printf( "CLR_RT_Memory::Allocate: %08x = %3d blocks (tot %4d), %d bytes\r\n", res, obj->DataSize(), s_TotalAllocated, len ); +#endif + +#if defined(NANOCLR_FILL_MEMORY_WITH_DIRTY_PATTERN) + memset( res, 0xDD, len ); + + *(CLR_UINT32*)res = (CLR_UINT32)len; + + DEBUG_POINTER_INCREMENT(res,c_extra+sizeof(CLR_UINT32)); +#endif + + return res; + } + + return NULL; +} + +void* CLR_RT_Memory::Allocate_And_Erase( size_t len, CLR_UINT32 flags ) +{ + NATIVE_PROFILE_CLR_CORE(); + void* ptr = CLR_RT_Memory::Allocate( len, flags ); + + if(ptr) ZeroFill( ptr, len ); + + return ptr; +} + + +void* CLR_RT_Memory::ReAllocate( void* ptr, size_t len ) +{ + NATIVE_PROFILE_CLR_CORE(); + + // allocate always as an event but do not run GC on failure + void* p = CLR_RT_Memory::Allocate( len, CLR_RT_HeapBlock::HB_Event | CLR_RT_HeapBlock::HB_NoGcOnFailedAllocation); if(!p) return NULL; + + if(ptr) + { + CLR_RT_HeapBlock_BinaryBlob* pThis = CLR_RT_HeapBlock_BinaryBlob::GetBlob( ptr ); + + size_t prevLen = pThis->DataSize() * sizeof(CLR_RT_HeapBlock); + + memcpy( p, ptr, len > prevLen ? prevLen : len ); + + CLR_RT_Memory::Release( ptr ); + + ptr = p; + } + + return p; +} + diff --git a/source/native/nf-interpreter/src/CLR/Core/CLR_RT_ObjectToEvent_Destination.cpp b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_ObjectToEvent_Destination.cpp new file mode 100644 index 00000000..6f11dad9 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_ObjectToEvent_Destination.cpp @@ -0,0 +1,73 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +void CLR_RT_ObjectToEvent_Destination::Initialize() +{ + NATIVE_PROFILE_CLR_CORE(); + m_references.DblLinkedList_Initialize(); +} + +void CLR_RT_ObjectToEvent_Destination::CheckAll() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_NODE(CLR_RT_ObjectToEvent_Source,ref,m_references) + { + ref->EnsureObjectIsAlive(); + } + NANOCLR_FOREACH_NODE_END(); +} + +void CLR_RT_ObjectToEvent_Destination::SignalAll() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_NODE(CLR_RT_ObjectToEvent_Source,ref,m_references) + { + if(ref->m_objectPtr) + { + CLR_RT_HeapBlock_WaitForObject::SignalObject( *ref->m_objectPtr ); + } + } + NANOCLR_FOREACH_NODE_END(); +} + +void CLR_RT_ObjectToEvent_Destination::DetachAll() +{ + NATIVE_PROFILE_CLR_CORE(); + while(true) + { + CLR_RT_ObjectToEvent_Source* ref = (CLR_RT_ObjectToEvent_Source*)m_references.ExtractFirstNode(); if(!ref) break; + + ref->Detach(); + } +} + +bool CLR_RT_ObjectToEvent_Destination::IsReadyForRelease() +{ + NATIVE_PROFILE_CLR_CORE(); + if(m_references.IsEmpty()) + { + if(IsForcedAlive() == false) + { + return true; + } + } + + return false; +} + +bool CLR_RT_ObjectToEvent_Destination::ReleaseWhenDead() +{ + NATIVE_PROFILE_CLR_CORE(); + bool res = IsReadyForRelease(); + + if(res) g_CLR_RT_EventCache.Append_Node( this ); + + return res; +} + diff --git a/source/native/nf-interpreter/src/CLR/Core/CLR_RT_ObjectToEvent_Source.cpp b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_ObjectToEvent_Source.cpp new file mode 100644 index 00000000..57dbe957 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_ObjectToEvent_Source.cpp @@ -0,0 +1,63 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +HRESULT CLR_RT_ObjectToEvent_Source::CreateInstance( CLR_RT_ObjectToEvent_Destination* event, CLR_RT_HeapBlock& object, CLR_RT_HeapBlock& reference ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_ObjectToEvent_Source* oe = EVENTCACHE_EXTRACT_NODE(g_CLR_RT_EventCache,CLR_RT_ObjectToEvent_Source,DATATYPE_OBJECT_TO_EVENT); CHECK_ALLOCATION(oe); + + oe->m_eventPtr = event; // Pointer to the event referenced. + + oe->m_objectPtr = &object; // Pointer to the object to keep alive. + oe->m_referencePtr = &reference; // Pointer to the HeapBlock referencing this structure. + + reference.SetObjectReference( oe ); + + event->m_references.LinkAtBack( oe ); + + NANOCLR_NOCLEANUP(); +} + +CLR_RT_ObjectToEvent_Source* CLR_RT_ObjectToEvent_Source::ExtractInstance( CLR_RT_HeapBlock& reference ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(reference.IsAReferenceOfThisType( DATATYPE_OBJECT_TO_EVENT ) == false) return NULL; + + return (CLR_RT_ObjectToEvent_Source*)reference.Dereference(); +} + + +void CLR_RT_ObjectToEvent_Source::EnsureObjectIsAlive() +{ + NATIVE_PROFILE_CLR_CORE(); + if(m_objectPtr && m_objectPtr->IsAlive()) return; + + Detach(); +} + +void CLR_RT_ObjectToEvent_Source::Detach() +{ + NATIVE_PROFILE_CLR_CORE(); + if(m_referencePtr) + { + m_referencePtr->SetObjectReference( NULL ); + } + + g_CLR_RT_EventCache.Append_Node( this ); +} + +void CLR_RT_ObjectToEvent_Source::Relocate() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_objectPtr ); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_referencePtr ); +} + diff --git a/source/native/nf-interpreter/src/CLR/Core/CLR_RT_RuntimeMemory.cpp b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_RuntimeMemory.cpp new file mode 100644 index 00000000..0a5902e2 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_RuntimeMemory.cpp @@ -0,0 +1,136 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "nanoCLR_Interop.h" + +//////////////////////////////////////// +// !!! DO NOT EDIT THIS FILE !!! + +#define LINK_SIZE_BYTES 4 +#define PAYLOAD_SIZE_BYTES 12 +#define INTERRUPT_RECORD_SIZE_BYTES 24 +#define INLINE_SIZE_BYTES (8 * sizeof(int*) + sizeof(int)) + +#define ENTRY_SIZE__extrasmall 32 +#define HASH_TABLE_ENTRY__extrasmall 9 +#define INTERRUPT_RECORDS__extrasmall 16 +#define INLINE_BUFFER__extrasmall 16 + +#define ENTRY_SIZE__small 128 +#define HASH_TABLE_ENTRY__small 33 +#define INTERRUPT_RECORDS__small 64 +#define INLINE_BUFFER__small 32 + +#define ENTRY_SIZE__medium 512 +#define HASH_TABLE_ENTRY__medium 129 +#define INTERRUPT_RECORDS__medium 128 +#define INLINE_BUFFER__medium 64 + +#define ENTRY_SIZE__large 2048 +#define HASH_TABLE_ENTRY__large 521 +#define INTERRUPT_RECORDS__large 512 +#define INLINE_BUFFER__large 128 + +///////////////////////////////////////////// +// undefine everything and define defaults +#ifdef PLATFORM_DEPENDENT_ENTRY_SIZE +#undef PLATFORM_DEPENDENT_ENTRY_SIZE +#endif +#define PLATFORM_DEPENDENT_ENTRY_SIZE ENTRY_SIZE__medium + +#ifdef PLATFORM_DEPENDENT_HASH_TABLE_SIZE +#undef PLATFORM_DEPENDENT_HASH_TABLE_SIZE +#endif +#define PLATFORM_DEPENDENT_HASH_TABLE_SIZE HASH_TABLE_ENTRY__medium + +#ifdef PLATFORM_DEPENDENT_INTERRUPT_RECORDS +#undef PLATFORM_DEPENDENT_INTERRUPT_RECORDS +#endif +#define PLATFORM_DEPENDENT_INTERRUPT_RECORDS INTERRUPT_RECORDS__medium + +#ifdef PLATFORM_DEPENDENT_INLINE_BUFFER_SIZE +#undef PLATFORM_DEPENDENT_INLINE_BUFFER_SIZE +#endif +#define PLATFORM_DEPENDENT_INLINE_BUFFER_SIZE INLINE_BUFFER__medium + +// undefine everything and define defaults +///////////////////////////////////////////// + +//////////////////////////////////////////////////////// +// apply user selection from platform_selector.h file +#ifdef RUNTIME_MEMORY_PROFILE__extrasmall +#undef PLATFORM_DEPENDENT_ENTRY_SIZE +#define PLATFORM_DEPENDENT_ENTRY_SIZE ENTRY_SIZE__extrasmall +#undef PLATFORM_DEPENDENT_HASH_TABLE_SIZE +#define PLATFORM_DEPENDENT_HASH_TABLE_SIZE HASH_TABLE_ENTRY__extrasmall +#undef PLATFORM_DEPENDENT_INTERRUPT_RECORDS +#define PLATFORM_DEPENDENT_INTERRUPT_RECORDS INTERRUPT_RECORDS__extrasmall +#undef PLATFORM_DEPENDENT_INLINE_BUFFER_SIZE +#define PLATFORM_DEPENDENT_INLINE_BUFFER_SIZE INLINE_BUFFER__extrasmall +#endif + +#ifdef RUNTIME_MEMORY_PROFILE__small +#undef PLATFORM_DEPENDENT_ENTRY_SIZE +#define PLATFORM_DEPENDENT_ENTRY_SIZE ENTRY_SIZE__small +#undef PLATFORM_DEPENDENT_HASH_TABLE_SIZE +#define PLATFORM_DEPENDENT_HASH_TABLE_SIZE HASH_TABLE_ENTRY__small +#undef PLATFORM_DEPENDENT_INTERRUPT_RECORDS +#define PLATFORM_DEPENDENT_INTERRUPT_RECORDS INTERRUPT_RECORDS__small +#undef PLATFORM_DEPENDENT_INLINE_BUFFER_SIZE +#define PLATFORM_DEPENDENT_INLINE_BUFFER_SIZE INLINE_BUFFER__small +#endif + +#ifdef RUNTIME_MEMORY_PROFILE__medium +#undef PLATFORM_DEPENDENT_ENTRY_SIZE +#define PLATFORM_DEPENDENT_ENTRY_SIZE ENTRY_SIZE__medium +#undef PLATFORM_DEPENDENT_HASH_TABLE_SIZE +#define PLATFORM_DEPENDENT_HASH_TABLE_SIZE HASH_TABLE_ENTRY__medium +#undef PLATFORM_DEPENDENT_INTERRUPT_RECORDS +#define PLATFORM_DEPENDENT_INTERRUPT_RECORDS INTERRUPT_RECORDS__medium +#undef PLATFORM_DEPENDENT_INLINE_BUFFER_SIZE +#define PLATFORM_DEPENDENT_INLINE_BUFFER_SIZE INLINE_BUFFER__medium +#endif + +#ifdef RUNTIME_MEMORY_PROFILE__large +#undef PLATFORM_DEPENDENT_ENTRY_SIZE +#define PLATFORM_DEPENDENT_ENTRY_SIZE ENTRY_SIZE__large +#undef PLATFORM_DEPENDENT_HASH_TABLE_SIZE +#define PLATFORM_DEPENDENT_HASH_TABLE_SIZE HASH_TABLE_ENTRY__large +#undef PLATFORM_DEPENDENT_INTERRUPT_RECORDS +#define PLATFORM_DEPENDENT_INTERRUPT_RECORDS INTERRUPT_RECORDS__large +#undef PLATFORM_DEPENDENT_INLINE_BUFFER_SIZE +#define PLATFORM_DEPENDENT_INLINE_BUFFER_SIZE INLINE_BUFFER__large +#endif +// apply user selection from platform_selector.h file +//////////////////////////////////////////////////////// + +//--// + +size_t LinkArraySize () { return (PLATFORM_DEPENDENT_ENTRY_SIZE + PLATFORM_DEPENDENT_HASH_TABLE_SIZE); } +size_t LinkMRUArraySize() { return (PLATFORM_DEPENDENT_ENTRY_SIZE + 1 ); } +size_t PayloadArraySize() { return PLATFORM_DEPENDENT_ENTRY_SIZE; } +#ifndef CLR_NO_IL_INLINE +size_t InlineBufferCount() { return PLATFORM_DEPENDENT_INLINE_BUFFER_SIZE; } +#endif + +unsigned int g_scratchVirtualMethodTableLink [ LINK_SIZE_BYTES * (PLATFORM_DEPENDENT_ENTRY_SIZE + PLATFORM_DEPENDENT_HASH_TABLE_SIZE) / sizeof(unsigned int) + 1 ]; +unsigned int g_scratchVirtualMethodTableLinkMRU[ LINK_SIZE_BYTES * (PLATFORM_DEPENDENT_ENTRY_SIZE + 1 ) / sizeof(unsigned int) + 1 ]; +unsigned int g_scratchVirtualMethodPayload [ PAYLOAD_SIZE_BYTES * PLATFORM_DEPENDENT_ENTRY_SIZE / sizeof(unsigned int) + 1 ]; + +#ifndef CLR_NO_IL_INLINE +unsigned int g_scratchInlineBuffer[ INLINE_SIZE_BYTES * PLATFORM_DEPENDENT_INLINE_BUFFER_SIZE / sizeof(unsigned int) + 1 ]; +#endif + +//--// + +size_t InterruptRecords() { return PLATFORM_DEPENDENT_INTERRUPT_RECORDS; } + +unsigned int g_scratchInterruptDispatchingStorage[ (PLATFORM_DEPENDENT_INTERRUPT_RECORDS * INTERRUPT_RECORD_SIZE_BYTES) / sizeof(unsigned int) + 1 ]; + +//--// + +// !!! DO NOT EDIT THIS FILE !!! +//////////////////////////////////////// + diff --git a/source/native/nf-interpreter/src/CLR/Core/CLR_RT_StackFrame.cpp b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_StackFrame.cpp new file mode 100644 index 00000000..d52684a3 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_StackFrame.cpp @@ -0,0 +1,1208 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +HRESULT CLR_RT_StackFrame::Push( CLR_RT_Thread* th, const CLR_RT_MethodDef_Instance& callInst, CLR_INT32 extraBlocks ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_StackFrame* stack; + CLR_RT_StackFrame* caller; + CLR_RT_Assembly* assm; + const CLR_RECORD_METHODDEF* md; + const CLR_RT_MethodDef_Instance* callInstPtr = &callInst; + CLR_UINT32 sizeLocals; + CLR_UINT32 sizeEvalStack; + +#if defined(PLATFORM_WINDOWS_EMULATOR) + if(s_CLR_RT_fTrace_SimulateSpeed > c_CLR_RT_Trace_None) + { + CLR_PROF_Handler::SuspendTime(); + + HAL_Windows_FastSleep( g_HAL_Configuration_Windows.TicksPerMethodCall ); + + CLR_PROF_Handler::ResumeTime(); + } +#endif + + assm = callInstPtr->m_assm; + md = callInstPtr->m_target; + + sizeLocals = md->numLocals; +#ifndef CLR_NO_IL_INLINE + sizeEvalStack = md->lengthEvalStack + CLR_RT_StackFrame::c_OverheadForNewObjOrInteropMethod + 1; +#else + sizeEvalStack = md->lengthEvalStack + CLR_RT_StackFrame::c_OverheadForNewObjOrInteropMethod; +#endif + + //--// + + caller = th->CurrentFrame(); + + //--// + + // + // Allocate memory for the runtime state. + // + { + CLR_UINT32 memorySize = sizeLocals + sizeEvalStack; + + if(extraBlocks > 0 ) memorySize += extraBlocks; +#ifndef CLR_NO_IL_INLINE + if(memorySize < c_MinimumStack) + { + sizeEvalStack += c_MinimumStack - memorySize; + memorySize = c_MinimumStack; + } +#else + if(memorySize < c_MinimumStack) memorySize = c_MinimumStack; +#endif + + #ifdef __GNUC__ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Winvalid-offsetof" + #endif + + memorySize += CONVERTFROMSIZETOHEAPBLOCKS(offsetof(CLR_RT_StackFrame,m_extension)); + + #ifdef __GNUC__ + #pragma GCC diagnostic pop + #endif + + stack = EVENTCACHE_EXTRACT_NODE_AS_BLOCKS(g_CLR_RT_EventCache,CLR_RT_StackFrame,DATATYPE_STACK_FRAME,0,memorySize); CHECK_ALLOCATION(stack); + } + + //--// + + { // + stack->m_owningSubThread = th->CurrentSubThread(); // CLR_RT_SubThread* m_owningSubThread; // EVENT HEAP - NO RELOCATION - + stack->m_owningThread = th; // CLR_RT_Thread* m_owningThread; // EVENT HEAP - NO RELOCATION - + // CLR_UINT32 m_flags; + // + stack->m_call = *callInstPtr; // CLR_RT_MethodDef_Instance m_call; + // + // CLR_RT_MethodHandler m_nativeMethod; + // CLR_PMETADATA m_IPstart; // ANY HEAP - DO RELOCATION - + // CLR_PMETADATA m_IP; // ANY HEAP - DO RELOCATION - + // + stack->m_locals = stack->m_extension; // CLR_RT_HeapBlock* m_locals; // EVENT HEAP - NO RELOCATION - + stack->m_evalStack = stack->m_extension + sizeLocals; // CLR_RT_HeapBlock* m_evalStack; // EVENT HEAP - NO RELOCATION - + stack->m_evalStackPos = stack->m_evalStack; // CLR_RT_HeapBlock* m_evalStackPos; // EVENT HEAP - NO RELOCATION - + stack->m_evalStackEnd = stack->m_evalStack + sizeEvalStack; // CLR_RT_HeapBlock* m_evalStackEnd; // EVENT HEAP - NO RELOCATION - + stack->m_arguments = NULL; // CLR_RT_HeapBlock* m_arguments; // EVENT HEAP - NO RELOCATION - + // + // union + // { + stack->m_customState = 0; // CLR_UINT32 m_customState; + // void* m_customPointer; + // }; + // +#ifndef CLR_NO_IL_INLINE + stack->m_inlineFrame = NULL; +#endif +#if defined(NANOCLR_PROFILE_NEW_CALLS) + stack->m_callchain.Enter( stack ); // CLR_PROF_CounterCallChain m_callchain; +#endif + // + // CLR_RT_HeapBlock m_extension[1]; + // +#if defined(ENABLE_NATIVE_PROFILER) + stack->m_fNativeProfiled = stack->m_owningThread->m_fNativeProfiled; +#endif + CLR_RT_MethodHandler impl; + +#if defined(NANOCLR_APPDOMAINS) + stack->m_appDomain = g_CLR_RT_ExecutionEngine.GetCurrentAppDomain(); +#endif + + if(md->flags & CLR_RECORD_METHODDEF::MD_DelegateInvoke) // Special case for delegate calls. + { + stack->m_nativeMethod = (CLR_RT_MethodHandler)CLR_RT_Thread::Execute_DelegateInvoke; + + stack->m_flags = CLR_RT_StackFrame::c_MethodKind_Native; + stack->m_IPstart = NULL; + } + else if(assm->m_nativeCode && (impl = assm->m_nativeCode[ stack->m_call.Method() ]) != NULL) + { + stack->m_nativeMethod = impl; + + stack->m_flags = CLR_RT_StackFrame::c_MethodKind_Native; + stack->m_IPstart = NULL; + stack->m_IP = NULL; + } + else + { + stack->m_nativeMethod = (CLR_RT_MethodHandler)CLR_RT_Thread::Execute_IL; + + if(md->RVA == CLR_EmptyIndex) NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + stack->m_flags = CLR_RT_StackFrame::c_MethodKind_Interpreted; + stack->m_IPstart = assm->GetByteCode( md->RVA ); + stack->m_IP = stack->m_IPstart; + } + + #if defined(ENABLE_NATIVE_PROFILER) + if(stack->m_owningThread->m_fNativeProfiled == false && md->flags & CLR_RECORD_METHODDEF::MD_NativeProfiled) + { + stack->m_flags |= CLR_RT_StackFrame::c_NativeProfiled; + stack->m_owningThread->m_fNativeProfiled = true; + } + #endif + + //--// + + th->m_stackFrames.LinkAtBack( stack ); + +#if defined(NANOCLR_PROFILE_NEW_CALLS) + g_CLR_PRF_Profiler.RecordFunctionCall( th, callInst ); +#endif + } + + if(md->numLocals) + { + g_CLR_RT_ExecutionEngine.InitializeLocals( stack->m_locals, assm, md ); + } + + { + CLR_UINT32 flags = md->flags & (md->MD_Synchronized | md->MD_GloballySynchronized); + + if(flags) + { + if(flags & md->MD_Synchronized ) stack->m_flags |= c_NeedToSynchronize; + if(flags & md->MD_GloballySynchronized) stack->m_flags |= c_NeedToSynchronizeGlobally; + } + } + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + stack->m_depth = stack->Caller()->Prev() ? stack->Caller()->m_depth + 1 : 0; + + if(g_CLR_RT_ExecutionEngine.m_breakpointsNum) + { + if(stack->m_call.DebuggingInfo().HasBreakpoint()) + { + stack->m_flags |= CLR_RT_StackFrame::c_HasBreakpoint; + } + + if(stack->m_owningThread->m_fHasJMCStepper || (stack->m_flags & c_HasBreakpoint) || (caller->Prev() != NULL && (caller->m_flags & c_HasBreakpoint))) + { + g_CLR_RT_ExecutionEngine.Breakpoint_StackFrame_Push( stack, CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_DEPTH_STEP_CALL ); + } + } +#endif + + //--// + + if(caller->Prev() != NULL && caller->m_nativeMethod == stack->m_nativeMethod) + { + if(stack->m_flags & CLR_RT_StackFrame::c_ProcessSynchronize) + { + stack->m_flags |= CLR_RT_StackFrame::c_CallerIsCompatibleForRet; + } + else + { + stack->m_flags |= CLR_RT_StackFrame::c_CallerIsCompatibleForCall | CLR_RT_StackFrame::c_CallerIsCompatibleForRet; + } + } + + // + // If the arguments are in the caller's stack frame (var == 0), let's link the two. + // + if(extraBlocks < 0) + { +#if defined(_WIN32) + if(caller->m_evalStackPos > caller->m_evalStackEnd) + { + NANOCLR_SET_AND_LEAVE(CLR_E_STACK_OVERFLOW); + } +#endif + + // + // Everything is set up correctly, pop the operands. + // + stack->m_arguments = &caller->m_evalStackPos[ -md->numArgs ]; + + caller->m_evalStackPos = stack->m_arguments; + +#if defined(_WIN32) + if(stack->m_arguments < caller->m_evalStack) + { + NANOCLR_SET_AND_LEAVE(CLR_E_STACK_UNDERFLOW); + } +#endif + } + else + { + stack->m_arguments = stack->m_evalStackEnd; + } + + NANOCLR_CLEANUP(); + + + NANOCLR_CLEANUP_END(); +} + +#ifndef CLR_NO_IL_INLINE +bool CLR_RT_StackFrame::PushInline( CLR_PMETADATA& ip, CLR_RT_Assembly*& assm, CLR_RT_HeapBlock*& evalPos, CLR_RT_MethodDef_Instance& calleeInst, CLR_RT_HeapBlock* pThis) +{ + const CLR_RECORD_METHODDEF* md = calleeInst.m_target; + + if( (m_inlineFrame != NULL) || // We can only support one inline at a time per stack call + (m_evalStackEnd - evalPos) <= (md->numArgs + md->numLocals + md->lengthEvalStack + 2) || // We must have enough space on the current stack for the inline method + (m_nativeMethod != (CLR_RT_MethodHandler)CLR_RT_Thread::Execute_IL) || // We only support IL inlining + (md->flags & ~CLR_RECORD_METHODDEF::MD_HasExceptionHandlers) >= CLR_RECORD_METHODDEF::MD_Constructor || // Do not try to inline constructors, etc because they require special processing + (0 != (md->flags & CLR_RECORD_METHODDEF::MD_Static)) || // Static methods also requires special processing + (calleeInst.m_assm->m_nativeCode != NULL && (calleeInst.m_assm->m_nativeCode[ calleeInst.Method() ] != NULL)) || // Make sure the callee is not an internal method + (md->RVA == CLR_EmptyIndex) || // Make sure we have a valid IP address for the method + !g_CLR_RT_EventCache.GetInlineFrameBuffer(&m_inlineFrame)) // Make sure we have an extra slot in the inline cache + { + return false; + } + + CLR_PMETADATA ipTmp = calleeInst.m_assm->GetByteCode( md->RVA ); + +#if defined(PLATFORM_WINDOWS_EMULATOR) + if(s_CLR_RT_fTrace_SimulateSpeed > c_CLR_RT_Trace_None) + { + CLR_PROF_Handler::SuspendTime(); + + HAL_Windows_FastSleep( g_HAL_Configuration_Windows.TicksPerMethodCall ); + + CLR_PROF_Handler::ResumeTime(); + } +#endif + + // make backup + m_inlineFrame->m_frame.m_IP = ip; + m_inlineFrame->m_frame.m_IPStart = m_IPstart; + m_inlineFrame->m_frame.m_locals = m_locals; + m_inlineFrame->m_frame.m_args = m_arguments; + m_inlineFrame->m_frame.m_call = m_call; + m_inlineFrame->m_frame.m_evalStack = m_evalStack; + m_inlineFrame->m_frame.m_evalPos = pThis; + + // increment the evalPos pointer so that we don't corrupt the real stack + evalPos++; + assm = calleeInst.m_assm; + ip = ipTmp; + + m_arguments = pThis; + m_locals = &m_evalStackEnd[-md->numLocals]; + m_call = calleeInst; + m_evalStackEnd = m_locals; + m_evalStack = evalPos; + m_evalStackPos = evalPos + 1; + m_IPstart = ip; + m_IP = ip; + + if(md->numLocals) + { + g_CLR_RT_ExecutionEngine.InitializeLocals( m_locals, calleeInst.m_assm, md ); + } + + m_flags |= CLR_RT_StackFrame::c_MethodKind_Inlined; + + if(md->retVal != DATATYPE_VOID) + { + m_flags |= CLR_RT_StackFrame::c_InlineMethodHasReturnValue; + } + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + m_depth++; + + if(g_CLR_RT_ExecutionEngine.m_breakpointsNum) + { + if(m_call.DebuggingInfo().HasBreakpoint()) + { + m_flags |= CLR_RT_StackFrame::c_HasBreakpoint; + } + + if(m_owningThread->m_fHasJMCStepper || (m_flags & CLR_RT_StackFrame::c_HasBreakpoint)) + { + g_CLR_RT_ExecutionEngine.Breakpoint_StackFrame_Push( this, CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_DEPTH_STEP_CALL ); + } + } +#endif + + return true; +} + +void CLR_RT_StackFrame::PopInline() +{ + + CLR_RT_HeapBlock& src = m_evalStackPos[0]; + + RestoreFromInlineStack(); + + if(m_flags & CLR_RT_StackFrame::c_InlineMethodHasReturnValue) + { + if(m_owningThread->m_currentException.Dereference() == NULL) + { + CLR_RT_HeapBlock& dst = PushValueAndAssign( src ); + + dst.Promote(); + } + } + + g_CLR_RT_EventCache.FreeInlineBuffer(m_inlineFrame); + m_inlineFrame = NULL; + m_flags &= ~(CLR_RT_StackFrame::c_MethodKind_Inlined | CLR_RT_StackFrame::c_InlineMethodHasReturnValue); + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(m_owningThread->m_fHasJMCStepper || (m_flags & CLR_RT_StackFrame::c_HasBreakpoint)) + { + g_CLR_RT_ExecutionEngine.Breakpoint_StackFrame_Pop( this, false ); + } + m_depth--; +#endif +} + +void CLR_RT_StackFrame::RestoreFromInlineStack() +{ + m_arguments = m_inlineFrame->m_frame.m_args; + m_locals = m_inlineFrame->m_frame.m_locals; + m_evalStackEnd += m_call.m_target->numLocals; + m_call = m_inlineFrame->m_frame.m_call; + m_IP = m_inlineFrame->m_frame.m_IP; + m_IPstart = m_inlineFrame->m_frame.m_IPStart; + m_evalStack = m_inlineFrame->m_frame.m_evalStack; + m_evalStackPos = m_inlineFrame->m_frame.m_evalPos; +} + +void CLR_RT_StackFrame::RestoreStack(CLR_RT_InlineFrame& frame) +{ + m_arguments = frame.m_args; + m_locals = frame.m_locals; + m_call = frame.m_call; + m_IP = frame.m_IP; + m_IPstart = frame.m_IPStart; + m_evalStack = frame.m_evalStack; + m_evalStackPos = frame.m_evalPos; + m_evalStackEnd -= m_call.m_target->numLocals; +} + +void CLR_RT_StackFrame::SaveStack(CLR_RT_InlineFrame& frame) +{ + frame.m_args = m_arguments; + frame.m_locals = m_locals; + frame.m_call = m_call; + frame.m_IP = m_IP; + frame.m_IPStart = m_IPstart; + frame.m_evalPos = m_evalStackPos; + frame.m_evalStack = m_evalStack; +} +#endif + +#if defined(NANOCLR_APPDOMAINS) +HRESULT CLR_RT_StackFrame::PopAppDomainTransition() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + bool fException = false; + CLR_RT_HeapBlock exception; + CLR_RT_StackFrame* caller = this->Caller(); + + exception.SetObjectReference( NULL ); + + if(m_flags & CLR_RT_StackFrame::c_AppDomainInjectException) + { + //this is the last frame on the thread in a doomed AppDomain + //Convert the current ThreadAbortException into an AppDomainUnloaded exception + + _ASSERTE(m_owningThread->m_flags & CLR_RT_Thread::TH_F_Aborted); + _ASSERTE(m_owningThread->m_flags & CLR_RT_Thread::TH_F_ContainsDoomedAppDomain); + _ASSERTE(m_owningThread->m_currentException.Dereference() != NULL); + _ASSERTE(m_owningThread->m_currentException.Dereference()->ObjectCls().m_data == g_CLR_RT_WellKnownTypes.m_ThreadAbortException.m_data); + _ASSERTE(!m_appDomain->IsLoaded()); + + m_owningThread->m_flags &= ~(CLR_RT_Thread::TH_F_Aborted | CLR_RT_Thread::TH_F_ContainsDoomedAppDomain); + + hr = CLR_E_APPDOMAIN_EXITED; + } + else if(m_owningThread->m_currentException.Dereference() == NULL) + { + _ASSERTE((m_flags & CLR_RT_StackFrame::c_AppDomainInjectException) == 0); + + //Normal return. No exception is in flight + + if(m_flags & CLR_RT_StackFrame::c_AppDomainMethodInvoke) + { + // For dynamic invoke, + // we do not marshal byRef parameters back to the calling AppDomain + // The caller is a native method (MethodBase::Invoke), and does not have the args on it's eval stack. + } + else + { + int cArgs = m_call.m_target->numArgs; + + //First marshal the ref parameters + NANOCLR_CHECK_HRESULT(caller->m_appDomain->MarshalParameters( &caller->m_evalStackPos[ -cArgs ], m_arguments, cArgs, true )); + + //Now, pop the caller's arguments off the eval stack + caller->m_evalStackPos -= cArgs; + } + + // Now, push the return, if any. + if(m_call.m_target->retVal != DATATYPE_VOID) + { + CLR_RT_HeapBlock& dst = caller->PushValueAndClear(); + CLR_RT_HeapBlock& src = this ->TopValue (); + + NANOCLR_CHECK_HRESULT(caller->m_appDomain->MarshalObject( src, dst )); + + dst.Promote(); + } + } + else //Exception + { + //Normal exceptions must be marshaled to the caller's AppDomain + NANOCLR_CHECK_HRESULT(caller->m_appDomain->MarshalObject( m_owningThread->m_currentException, exception )); + fException = true; + } + + NANOCLR_CLEANUP(); + + if(FAILED(hr) || fException) + { + if(FAILED(hr)) + { + (void)Library_corlib_native_System_Exception::CreateInstance( exception, hr, caller ); + } + + m_owningThread->m_currentException.Assign( exception ); + } + + (void)g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( caller->m_appDomain ); + + NANOCLR_CLEANUP_END(); +} + +HRESULT CLR_RT_StackFrame::PushAppDomainTransition( CLR_RT_Thread* th, const CLR_RT_MethodDef_Instance& callInst, CLR_RT_HeapBlock* pThis, CLR_RT_HeapBlock* pArgs ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_StackFrame* frame = NULL; + int cArgs = callInst.m_target->numArgs; + CLR_RT_HeapBlock* proxy; + + _ASSERTE(pThis->IsTransparentProxy()); + + proxy = pThis->Dereference(); + + NANOCLR_CHECK_HRESULT(proxy->TransparentProxyValidate()); + + NANOCLR_CHECK_HRESULT(Push( th, callInst, cArgs )); + + frame = th->CurrentFrame(); + + frame->m_appDomain = proxy->TransparentProxyAppDomain(); + frame->m_flags |= CLR_RT_StackFrame::c_AppDomainTransition; + frame->m_flags &= ~CLR_RT_StackFrame::c_CallerIsCompatibleForRet; + + //Marshal the arguments from the caller (on the eval stack) to the callee, unitialized heapblocks that + //are set up by the extra blocks in CLR_RT_StackFrame::Push + NANOCLR_CHECK_HRESULT(frame->m_appDomain->MarshalObject ( *pThis, frame->m_arguments[ 0 ] )); + NANOCLR_CHECK_HRESULT(frame->m_appDomain->MarshalParameters( pArgs, &frame->m_arguments[ 1 ], cArgs-1, false )); + + (void)g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( frame->m_appDomain ); + + NANOCLR_NOCLEANUP(); +} + +#endif //NANOCLR_APPDOMAINS + +HRESULT CLR_RT_StackFrame::MakeCall( CLR_RT_MethodDef_Instance md, CLR_RT_HeapBlock* obj, CLR_RT_HeapBlock* args, int nArgs ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + const CLR_RECORD_METHODDEF* mdR = md.m_target; + bool fStatic =(mdR->flags & CLR_RECORD_METHODDEF::MD_Static) != 0; + int numArgs = mdR->numArgs; + int argsOffset = 0; + CLR_RT_StackFrame* stackSub; + CLR_RT_HeapBlock tmp; tmp.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc(tmp); + + if(mdR->flags & CLR_RECORD_METHODDEF::MD_Constructor) + { + CLR_RT_TypeDef_Instance owner; owner.InitializeFromMethod( md ); + + _ASSERTE(obj == NULL); + + _SIDE_ASSERTE(owner.InitializeFromMethod( md )); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObject( tmp, owner )); + + obj = &tmp; + + // + // Make a copy of the object pointer. + // + PushValueAndAssign( tmp ); + } + + if(!fStatic) + { + FAULT_ON_NULL(obj); + numArgs--; + argsOffset = 1; + } + + if(numArgs != nArgs) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + // + // In case the invoked method is abstract or virtual, resolve it to the correct method implementation. + // + if(mdR->flags & (CLR_RECORD_METHODDEF::MD_Abstract | CLR_RECORD_METHODDEF::MD_Virtual)) + { + CLR_RT_TypeDef_Index cls; + CLR_RT_MethodDef_Index mdReal; + + _ASSERTE(obj); + _ASSERTE(!fStatic); + + NANOCLR_CHECK_HRESULT(CLR_RT_TypeDescriptor::ExtractTypeIndexFromObject( *obj, cls )); + + if(g_CLR_RT_EventCache.FindVirtualMethod( cls, md, mdReal ) == false) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + md.InitializeFromIndex( mdReal ); + + mdR = md.m_target; + } + +#if defined(NANOCLR_APPDOMAINS) + + if(!fStatic && obj->IsTransparentProxy()) + { + NANOCLR_CHECK_HRESULT(CLR_RT_StackFrame::PushAppDomainTransition( m_owningThread, md, obj, args )); + + stackSub = m_owningThread->CurrentFrame(); + + stackSub->m_flags |= CLR_RT_StackFrame::c_AppDomainMethodInvoke; + } + else +#endif + { + NANOCLR_CHECK_HRESULT(CLR_RT_StackFrame::Push( m_owningThread, md, md.m_target->numArgs )); + + stackSub = m_owningThread->CurrentFrame(); + + if(!fStatic) + { + stackSub->m_arguments[ 0 ].Assign( *obj ); + } + + if(numArgs) + { + memcpy( &stackSub->m_arguments[ argsOffset ], args, sizeof(CLR_RT_HeapBlock) * numArgs ); + } + } + + NANOCLR_CHECK_HRESULT(stackSub->FixCall()); + + NANOCLR_SET_AND_LEAVE(CLR_E_RESTART_EXECUTION); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_StackFrame::FixCall() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + const CLR_RECORD_METHODDEF* target = m_call.m_target; + CLR_UINT8 numArgs = target->numArgs; + + // + // The copy of ValueTypes is delayed as much as possible. + // + // If an argument is a ValueType, now it's a good time to clone it. + // + if(numArgs) + { + CLR_RT_SignatureParser parser; parser.Initialize_MethodSignature( m_call.m_assm, target ); + CLR_RT_SignatureParser::Element res; + CLR_RT_HeapBlock* args = m_arguments; + + if(parser.m_flags & PIMAGE_CEE_CS_CALLCONV_HASTHIS) + { + args++; + } + + // + // Skip return value. + // + NANOCLR_CHECK_HRESULT(parser.Advance( res )); + + for(;parser.Available() > 0;args++) + { + NANOCLR_CHECK_HRESULT(parser.Advance( res )); + + if(res.m_levels > 0) continue; // Array, no need to fix. + + if(args->DataType() == DATATYPE_OBJECT) + { + CLR_RT_TypeDef_Instance inst; inst.InitializeFromIndex( res.m_cls ); + CLR_DataType dtT = (CLR_DataType)inst.m_target->dataType; + const CLR_RT_DataTypeLookup& dtl = c_CLR_RT_DataTypeLookup[ dtT ]; + + if(dtl.m_flags & (CLR_RT_DataTypeLookup::c_OptimizedValueType | CLR_RT_DataTypeLookup::c_ValueType)) + { + CLR_RT_HeapBlock* value = args->FixBoxingReference(); FAULT_ON_NULL(value); + + if(value->DataType() == dtT) + { + // It's a boxed primitive/enum type. + args->Assign( *value ); + } + else if(args->Dereference()->ObjectCls().m_data == res.m_cls.m_data) + { + NANOCLR_CHECK_HRESULT(args->PerformUnboxing( inst )); + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + } + } + + if(res.m_dt == DATATYPE_VALUETYPE && res.m_fByRef == false) + { + if(args->IsAReferenceOfThisType( DATATYPE_VALUETYPE )) + { + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.CloneObject( *args, *args )); + } + } + } + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_StackFrame::HandleSynchronized( bool fAcquire, bool fGlobal ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock refType; + CLR_RT_HeapBlock* obj; + CLR_RT_HeapBlock ref; + CLR_RT_HeapBlock** ppGlobalLock; + CLR_RT_HeapBlock* pGlobalLock; + + if(fGlobal) + { + obj = &ref; + +#if defined(NANOCLR_APPDOMAINS) + //With AppDomains enabled, the global lock is no longer global. It is only global wrt the AppDomain/ + //Do we need a GlobalGlobalLock? (an attribute on GloballySynchronized (GlobalAcrossAppDomain?) + ppGlobalLock = &g_CLR_RT_ExecutionEngine.GetCurrentAppDomain()->m_globalLock; +#else + ppGlobalLock = &g_CLR_RT_ExecutionEngine.m_globalLock; +#endif + + pGlobalLock = *ppGlobalLock; + + if(pGlobalLock) + { + obj->SetObjectReference( pGlobalLock ); + } + else + { + // + // Create an private object to implement global locks. + // + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex( *obj, g_CLR_RT_WellKnownTypes.m_Object )); + + *ppGlobalLock = obj->Dereference(); + } + } + else if(m_call.m_target->flags & CLR_RECORD_METHODDEF::MD_Static) + { + CLR_RT_TypeDef_Index idx; + + idx.Set( m_call.Assembly(), m_call.CrossReference().GetOwner() ); + + refType.SetReflection( idx ); + + obj = &refType; + } + else + { + obj = &Arg0(); + } + + if(fAcquire) + { + NANOCLR_SET_AND_LEAVE(g_CLR_RT_ExecutionEngine.LockObject( *obj, m_owningSubThread, TIMEOUT_INFINITE, false )); + } + else + { + NANOCLR_SET_AND_LEAVE(g_CLR_RT_ExecutionEngine.UnlockObject( *obj, m_owningSubThread )); + } + + NANOCLR_NOCLEANUP(); +} + +void CLR_RT_StackFrame::Pop() +{ + NATIVE_PROFILE_CLR_CORE(); + +#if defined(NANOCLR_PROFILE_NEW_CALLS) + { + // + // This passivates any outstanding handler. + // + CLR_PROF_HANDLER_CALLCHAIN(pm2,m_callchain); + + m_callchain.Leave(); + } +#endif + +#if defined(NANOCLR_PROFILE_NEW_CALLS) + g_CLR_PRF_Profiler.RecordFunctionReturn( m_owningThread, m_callchain ); +#endif + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(m_owningThread->m_fHasJMCStepper || (m_flags & c_HasBreakpoint)) + { + g_CLR_RT_ExecutionEngine.Breakpoint_StackFrame_Pop( this, false ); + } +#endif + + const CLR_UINT32 c_flagsToCheck = CLR_RT_StackFrame::c_CallOnPop | CLR_RT_StackFrame::c_Synchronized | CLR_RT_StackFrame::c_SynchronizedGlobally | CLR_RT_StackFrame::c_NativeProfiled; + + if(m_flags & c_flagsToCheck) + { + if(m_flags & CLR_RT_StackFrame::c_CallOnPop) + { + m_flags |= CLR_RT_StackFrame::c_CalledOnPop; + + if(m_nativeMethod) + { + (void)m_nativeMethod( *this ); + } + } + + if(m_flags & CLR_RT_StackFrame::c_Synchronized) + { + m_flags &= ~CLR_RT_StackFrame::c_Synchronized; + + (void)HandleSynchronized( false, false ); + } + + if(m_flags & CLR_RT_StackFrame::c_SynchronizedGlobally) + { + m_flags &= ~CLR_RT_StackFrame::c_SynchronizedGlobally; + + (void)HandleSynchronized( false, true ); + } + + #if defined(ENABLE_NATIVE_PROFILER) + if(m_flags & CLR_RT_StackFrame::c_NativeProfiled) + { + m_owningThread->m_fNativeProfiled = false; + m_flags &= ~CLR_RT_StackFrame::c_NativeProfiled; + Native_Profiler_Stop(); + } + #endif + } + + CLR_RT_StackFrame* caller = Caller(); + + if(caller->Prev() != NULL) + { +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(caller->m_flags & CLR_RT_StackFrame::c_HasBreakpoint) + { + g_CLR_RT_ExecutionEngine.Breakpoint_StackFrame_Step( caller, caller->m_IP ); + } +#endif + + // + // Constructors are slightly different, they push the 'this' pointer back into the caller stack. + // + // This is to enable the special case for strings, where the object can be recreated by the constructor... + // + if(caller->m_flags & CLR_RT_StackFrame::c_ExecutingConstructor) + { + CLR_RT_HeapBlock& src = this ->Arg0 ( ); + CLR_RT_HeapBlock& dst = caller->PushValueAndAssign( src ); + + dst.Promote(); + + // + // Undo the special "object -> reference" hack done by CEE_NEWOBJ. + // + if(dst.DataType() == DATATYPE_BYREF) + { + dst.ChangeDataType( DATATYPE_OBJECT ); + } + + caller->m_flags &= ~CLR_RT_StackFrame::c_ExecutingConstructor; + + _ASSERTE((m_flags & CLR_RT_StackFrame::c_AppDomainTransition) == 0); + } + else + { //Note that ExecutingConstructor is checked on 'caller', whereas the other two flags are checked on 'this' + const CLR_UINT32 c_moreFlagsToCheck = CLR_RT_StackFrame::c_PseudoStackFrameForFilter | CLR_RT_StackFrame::c_AppDomainTransition; + + if(m_flags & c_moreFlagsToCheck) + { + if(m_flags & CLR_RT_StackFrame::c_PseudoStackFrameForFilter) + { + //Do nothing here. Pushing return values onto stack frames that don't expect them are a bad idea. + } +#if defined(NANOCLR_APPDOMAINS) + else if((m_flags & CLR_RT_StackFrame::c_AppDomainTransition) != 0) + { + (void)PopAppDomainTransition(); + } +#endif + } + else //!c_moreFlagsToCheck + { + // + // Push the return, if any. + // + if(m_call.m_target->retVal != DATATYPE_VOID) + { + if(m_owningThread->m_currentException.Dereference() == NULL) + { + CLR_RT_HeapBlock& src = this ->TopValue ( ); + CLR_RT_HeapBlock& dst = caller->PushValueAndAssign( src ); + + dst.Promote(); + } + } + } + } + } +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + else + { + int idx = m_owningThread->m_scratchPad; + + if(idx >= 0) + { + CLR_RT_HeapBlock_Array* array = g_CLR_RT_ExecutionEngine.m_scratchPadArray; + + if(array && array->m_numOfElements > (CLR_UINT32)idx) + { + CLR_RT_HeapBlock* dst = (CLR_RT_HeapBlock*)array->GetElement( (CLR_UINT32)idx ); + CLR_RT_HeapBlock* exception = m_owningThread->m_currentException.Dereference(); + + dst->SetObjectReference( NULL ); + + if(exception != NULL) + { + dst->SetObjectReference( exception ); + } + else if(m_call.m_target->retVal != DATATYPE_VOID) + { + CLR_RT_SignatureParser sig; sig.Initialize_MethodSignature( this->m_call.m_assm, this->m_call.m_target ); + CLR_RT_SignatureParser::Element res; + CLR_RT_TypeDescriptor desc; + + dst->Assign( this->TopValue() ); + + //Perform boxing, if needed. + + //Box to the return value type + _SIDE_ASSERTE(SUCCEEDED(sig.Advance( res ))); + _SIDE_ASSERTE(SUCCEEDED(desc.InitializeFromType( res.m_cls ))); + + + if(c_CLR_RT_DataTypeLookup[ this->DataType() ].m_flags & CLR_RT_DataTypeLookup::c_OptimizedValueType + || desc.m_handlerCls.m_target->IsEnum() + ) + { + if(FAILED(dst->PerformBoxing( desc.m_handlerCls ))) + { + dst->SetObjectReference( NULL ); + } + } + } + } + } + } +#endif + + // + // We could be jumping outside of a nested exception handler. + // + + m_owningThread->PopEH( this, NULL ); + + + // + // If this StackFrame owns a SubThread, kill it. + // + { + CLR_RT_SubThread* sth = (CLR_RT_SubThread*)m_owningSubThread->Next(); + + if(sth->Next() && sth->m_owningStackFrame == this) + { + CLR_RT_SubThread::DestroyInstance( sth->m_owningThread, sth, CLR_RT_SubThread::MODE_IncludeSelf ); + } + } + + g_CLR_RT_EventCache.Append_Node( this ); +} + +//--// + +void CLR_RT_StackFrame::SetResult( CLR_INT32 val, CLR_DataType dataType ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock& top = PushValue(); + + top.SetInteger( val, dataType ); +} + +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + +void CLR_RT_StackFrame::SetResult_R4( float val ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock& top = PushValue(); + + top.SetFloat( val ); +} + +void CLR_RT_StackFrame::SetResult_R8( double val ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock& top = PushValue(); + + top.SetDouble( val ); +} + +#else + +void CLR_RT_StackFrame::SetResult_R4( CLR_INT32 val ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock& top = PushValue(); + + top.SetFloat( val ); +} + +void CLR_RT_StackFrame::SetResult_R8( CLR_INT64 val ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock& top = PushValue(); + + top.SetDouble( val ); +} + +#endif + +void CLR_RT_StackFrame::SetResult_I1( CLR_UINT8 val ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock& top = PushValue(); + + top.SetInteger( val ); +} + +void CLR_RT_StackFrame::SetResult_I2( CLR_INT16 val ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock& top = PushValue(); + + top.SetInteger( val ); +} + +void CLR_RT_StackFrame::SetResult_I4( CLR_INT32 val ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock& top = PushValue(); + + top.SetInteger( val ); +} + +void CLR_RT_StackFrame::SetResult_I8( CLR_INT64& val ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock& top = PushValue(); + + top.SetInteger( val ); +} + +void CLR_RT_StackFrame::SetResult_U1( CLR_INT8 val ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock& top = PushValue(); + + top.SetInteger( val ); +} + +void CLR_RT_StackFrame::SetResult_U2( CLR_UINT16 val ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock& top = PushValue(); + + top.SetInteger( val ); +} + +void CLR_RT_StackFrame::SetResult_U4( CLR_UINT32 val ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock& top = PushValue(); + + top.SetInteger( val ); +} + +void CLR_RT_StackFrame::SetResult_U8( CLR_UINT64& val ) + +{ + CLR_RT_HeapBlock& top = PushValue(); + + top.SetInteger( val ); +} + +void CLR_RT_StackFrame::SetResult_Boolean( bool val ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock& top = PushValue(); + + top.SetBoolean( val ); +} + +void CLR_RT_StackFrame::SetResult_Object( CLR_RT_HeapBlock* val ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock& top = PushValue(); + + top.SetObjectReference( val ); +} + +HRESULT CLR_RT_StackFrame::SetResult_String( const char* val ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock& top = PushValue(); + + NANOCLR_SET_AND_LEAVE(CLR_RT_HeapBlock_String::CreateInstance( top, val )); + + NANOCLR_NOCLEANUP(); +} + + +void CLR_RT_StackFrame::ConvertResultToBoolean() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock& top = TopValue(); + + top.SetBoolean( top.NumericByRef().s4 == 0 ); +} + +void CLR_RT_StackFrame::NegateResult() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock& top = TopValue(); + + top.NumericByRef().s4 = top.NumericByRef().s4 ? 0 : 1; +} + +//--// + +// input HeapBlock has timeout value **IN TICKS** +// sometimes you have to force a cast to (CLR_INT64) otherwise the set operations will fail because of the var size mismatch +HRESULT CLR_RT_StackFrame::SetupTimeoutFromTicks( CLR_RT_HeapBlock& input, CLR_INT64*& output ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(m_customState == 0) + { + CLR_RT_HeapBlock& ref = PushValueAndClear(); + CLR_INT64 timeExpire; + + // + // Initialize timeout and save it on the stack. + // + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.InitTimeout( timeExpire, input.NumericByRef().s8 )); + + ref.SetInteger( timeExpire ); + + m_customState = 1; + } + + output = (CLR_INT64*)&m_evalStack[ 0 ].NumericByRef().s8; + + NANOCLR_NOCLEANUP(); +} + +//--// + +void CLR_RT_StackFrame::Relocate() +{ + NATIVE_PROFILE_CLR_CORE(); + +#ifndef CLR_NO_IL_INLINE + if(m_inlineFrame) + { + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_inlineFrame->m_frame.m_call.m_assm ); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_inlineFrame->m_frame.m_call.m_target ); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_inlineFrame->m_frame.m_IPStart ); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_inlineFrame->m_frame.m_IP ); + + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_call.m_assm ); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_call.m_target ); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_nativeMethod ); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_IPstart ); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_IP ); + + CLR_RT_GarbageCollector::Heap_Relocate( m_inlineFrame->m_frame.m_args , m_inlineFrame->m_frame.m_call.m_target->numArgs ); + CLR_RT_GarbageCollector::Heap_Relocate( m_inlineFrame->m_frame.m_locals , m_inlineFrame->m_frame.m_call.m_target->numLocals ); + CLR_RT_GarbageCollector::Heap_Relocate( m_inlineFrame->m_frame.m_evalStack, (int)(m_evalStackPos - m_inlineFrame->m_frame.m_evalStack) ); + CLR_RT_GarbageCollector::Heap_Relocate( m_locals, m_call.m_target->numLocals ); + } + else +#endif + { + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_call.m_assm ); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_call.m_target ); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_nativeMethod ); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_IPstart ); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_IP ); + + CLR_RT_GarbageCollector::Heap_Relocate( m_arguments, m_call.m_target->numArgs ); + CLR_RT_GarbageCollector::Heap_Relocate( m_locals , m_call.m_target->numLocals ); + CLR_RT_GarbageCollector::Heap_Relocate( m_evalStack, TopValuePosition() ); + } +} + +//--// + +HRESULT CLR_RT_StackFrame::NotImplementedStub() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(m_call.m_target->retVal != DATATYPE_VOID) + { + SetResult_I4( 0 ); + } + + NANOCLR_SET_AND_LEAVE(CLR_E_NOTIMPL); + + NANOCLR_NOCLEANUP(); +} + + diff --git a/source/native/nf-interpreter/src/CLR/Core/CLR_RT_SystemAssembliesTable.cpp b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_SystemAssembliesTable.cpp new file mode 100644 index 00000000..e078c67e --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_SystemAssembliesTable.cpp @@ -0,0 +1,45 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include +//#include +//#include +//#include "nanoCLR_Interop.h" + +static const CLR_RT_NativeAssemblyData *LookUpAssemblyNativeDataByName +( + const CLR_RT_NativeAssemblyData **pAssembliesNativeData, + const char *lpszAssemblyName +) +{ + // Just sanity check to avoid crash in strcmp if name is NULL. + if ( lpszAssemblyName == NULL ) + { + return NULL; + } + + // Loops in all entries and looks for the CLR_RT_NativeAssemblyData with name same as lpszAssemblyName + for ( int i = 0; pAssembliesNativeData[ i ]; i++ ) + { + if ( pAssembliesNativeData[ i ] != NULL && 0 == strcmp( lpszAssemblyName, pAssembliesNativeData[ i ]->m_szAssemblyName ) ) + { + return pAssembliesNativeData[ i ]; + } + } + return NULL; +} + + +const CLR_RT_NativeAssemblyData *GetAssemblyNativeData( const char *lpszAssemblyName ) +{ + extern const CLR_RT_NativeAssemblyData *g_CLR_InteropAssembliesNativeData[]; + + // This will return NULL if there is no registered interop assembly of that name + return LookUpAssemblyNativeDataByName( + g_CLR_InteropAssembliesNativeData, + lpszAssemblyName + ); +} + diff --git a/source/native/nf-interpreter/src/CLR/Core/CLR_RT_UnicodeHelper.cpp b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_UnicodeHelper.cpp new file mode 100644 index 00000000..86ca3a81 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/CLR_RT_UnicodeHelper.cpp @@ -0,0 +1,586 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#define UTF8_BAD_LOWPART(ch) (ch < 0x80 || ch > 0xBF) + +#define UTF8_CHECK_LOWPART(ch,src) ch = (CLR_UINT32)*src++; if(UTF8_BAD_LOWPART(ch)) return -1 + +#define UTF8_LOAD_LOWPART(ch,ch2,src) ch = (CLR_UINT32)*src++; ch2 <<= 6; ch2 |= (ch & 0x3F) + +//--// + +int CLR_RT_UnicodeHelper::CountNumberOfCharacters( int max ) +{ + NATIVE_PROFILE_CLR_CORE(); + const CLR_UINT8* pSrc = m_inputUTF8; + int num = 0; + + while(true) + { + CLR_UINT32 ch = (CLR_UINT32)*pSrc++; if(!ch) break; + + if(max-- == 0) break; // This works even if you pass -1 as argument (it will walk through the whole string). + + switch(ch & 0xF0) + { + case 0x00: + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + num += 1; + break; + + case 0x80: + case 0x90: + case 0xA0: + case 0xB0: + return -1; // Illegal characters. + + case 0xC0: + case 0xD0: + UTF8_CHECK_LOWPART(ch,pSrc); + + num += 1; + break; + + case 0xE0: + UTF8_CHECK_LOWPART(ch,pSrc); + UTF8_CHECK_LOWPART(ch,pSrc); + + num += 1; + break; + + case 0xF0: + UTF8_CHECK_LOWPART(ch,pSrc); + UTF8_CHECK_LOWPART(ch,pSrc); + UTF8_CHECK_LOWPART(ch,pSrc); + + num += 2; + break; + } + } + + return num; +} + +int CLR_RT_UnicodeHelper::CountNumberOfBytes( int max ) +{ + NATIVE_PROFILE_CLR_CORE(); + const CLR_UINT16* pSrc = m_inputUTF16; + int num = 0; + + while(true) + { + CLR_UINT16 ch = *pSrc++; if(!ch) break; + + if(max-- == 0) break; // This works even if you pass -1 as argument (it will walk through the whole string). + + if(ch < 0x0080) + { + num += 1; + } + else if(ch < 0x0800) + { + num += 2; + } + else if(ch >= LOW_SURROGATE_START && ch <= LOW_SURROGATE_END) + { + return -1; // Invalid string: Low surrogate should only follow a high surrogate. + } + else if(ch >= HIGH_SURROGATE_START && ch <= HIGH_SURROGATE_END) + { + ch = *pSrc++; + + if(ch >= LOW_SURROGATE_START && ch <= LOW_SURROGATE_END) + { + num += 4; + max--; + } + else + { + return -1; // Invalid string: Low surrogate should follow a high surrogate. + } + } + else + { + num += 3; + } + } + + return num; +} + +//--// + +// dev note: need the pragma below because there are a couple of 'smart' hacks in +// the switch cases to improve the algorithm +#ifdef __GNUC__ +#pragma GCC diagnostic push +// -Wimplicit-fallthrough option was added in GCC 7 +#if (__GNUC__ >= 7) +#pragma GCC diagnostic ignored "-Wimplicit-fallthrough" +#endif +#endif + +bool CLR_RT_UnicodeHelper::ConvertFromUTF8( int iMaxChars, bool fJustMove, int iMaxBytes ) +{ + NATIVE_PROFILE_CLR_CORE(); + const CLR_UINT8* inputUTF8 = m_inputUTF8; + CLR_UINT16* outputUTF16 = m_outputUTF16; + int outputUTF16_size = m_outputUTF16_size; + CLR_UINT32 ch; + CLR_UINT32 ch2; + bool res; + + if (iMaxBytes == -1) + { + iMaxBytes = iMaxChars * 3; // the max number of bytes it can have based on iMaxChars -- if all characters are of 3 bytes. + } + + while(iMaxChars > 0 && iMaxBytes > 0) + { + ch = (CLR_UINT32)*inputUTF8++; + + switch(ch & 0xF0) + { + case 0x00: if(ch == 0) { inputUTF8--; goto ExitFalse; } + case 0x10: + case 0x20: + case 0x30: + case 0x40: + case 0x50: + case 0x60: + case 0x70: + if(fJustMove == false) + { + if(outputUTF16_size < 1) + { + // un-read the byte before exiting + inputUTF8--; + goto ExitFalse; + } + + outputUTF16[ 0 ] = ch; + + outputUTF16 += 1; + outputUTF16_size -= 1; + } + + iMaxChars -= 1; + iMaxBytes -= 1; + break; + + case 0x80: + case 0x90: + case 0xA0: + case 0xB0: + goto ExitFalse; // Illegal characters. + + case 0xC0: + case 0xD0: + if((ch & 0xFF) < 0xC2) { inputUTF8--; goto ExitFalse; } // illegal - overlong encoding + + if(iMaxBytes >= 2) + { + if(fJustMove) + { + inputUTF8++; + } + else + { + if(outputUTF16_size < 1) + { + // un-read the byte before exiting + inputUTF8--; + goto ExitFalse; + } + ch2 = (ch & 0x1F); + UTF8_LOAD_LOWPART(ch,ch2,inputUTF8); + + outputUTF16[ 0 ] = ch2; + + outputUTF16 += 1; + outputUTF16_size -= 1; + } + + iMaxChars -= 1; + iMaxBytes -= 2; + } + else + { + // un-read the byte before exiting + inputUTF8--; + goto ExitFalse; + } + break; + + case 0xE0: + if(iMaxBytes >= 3) + { + if(fJustMove) + { + inputUTF8 += 2; + } + else + { + if(outputUTF16_size < 1) + { + // un-read the byte before exiting + inputUTF8--; + goto ExitFalse; + } + ch2 = (ch & 0x0F); + UTF8_LOAD_LOWPART(ch,ch2,inputUTF8); + UTF8_LOAD_LOWPART(ch,ch2,inputUTF8); + + outputUTF16[ 0 ] = ch2; + + outputUTF16 += 1; + outputUTF16_size -= 1; + } + + iMaxChars -= 1; + iMaxBytes -= 3; + } + else + { + // un-read the byte before exiting + inputUTF8--; + goto ExitFalse; + } + break; + + case 0xF0: + if((ch & 0xFF) >= 0xF5) { inputUTF8--; goto ExitFalse; } // restricted by RFC 3629 + + if(iMaxBytes >= 4) + { + if(fJustMove) + { + inputUTF8 += 3; + } + else + { + if(outputUTF16_size < 2) + { + // un-read the byte before exiting + inputUTF8--; + goto ExitFalse; + } + + ch2 = (ch & 0x07); + UTF8_LOAD_LOWPART(ch,ch2,inputUTF8); + UTF8_LOAD_LOWPART(ch,ch2,inputUTF8); + UTF8_LOAD_LOWPART(ch,ch2,inputUTF8); + + outputUTF16[ 0 ] = (ch2 >> SURROGATE_HALFSHIFT) + HIGH_SURROGATE_START; + outputUTF16[ 1 ] = (ch2 & SURROGATE_HALFMASK ) + LOW_SURROGATE_START ; + + outputUTF16 += 2; + outputUTF16_size -= 2; + } + + iMaxChars -= 2; + iMaxBytes -= 4; + } + else + { + // un-read the byte before exiting + inputUTF8--; + goto ExitFalse; + } + break; + } + } + + if(fJustMove == false) + { + if(outputUTF16_size < 1) goto ExitFalse; + + outputUTF16[ 0 ] = 0; + } + + res = true; + goto Exit; + + ExitFalse: + res = false; + + Exit: + m_inputUTF8 = inputUTF8; + m_outputUTF16 = outputUTF16; + m_outputUTF16_size = outputUTF16_size; + + return res; +} + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +// move backward in the UTF8 input +bool CLR_RT_UnicodeHelper::MoveBackwardInUTF8( const char* utf8StringStart, int iMaxChars ) +{ + // already at the beginning or iMaxChars < 1? + if (m_inputUTF8 <= (const CLR_UINT8*)utf8StringStart || iMaxChars < 1) + { + return false; + } + + while (true) + { + // move back one byte and test if it's 0xxxxxxx or 11xxxxxx, because that are start bytes + m_inputUTF8--; + char current = m_inputUTF8[0]; + if ((current & 0x10000000) == 0x00000000 || (current & 0x11000000) == 0x11000000) + { + iMaxChars--; + } + + // moved back enough? + if (iMaxChars == 0) + { + return true; + } + + // reached the beginning? + if (m_inputUTF8 == (const CLR_UINT8*)utf8StringStart) + { + return false; + } + } +} + +bool CLR_RT_UnicodeHelper::ConvertToUTF8( int iMaxChars, bool fJustMove ) +{ + NATIVE_PROFILE_CLR_CORE(); + const CLR_UINT16* inputUTF16 = m_inputUTF16; + CLR_UINT8* outputUTF8 = m_outputUTF8; + int outputUTF8_size = m_outputUTF8_size; + CLR_UINT32 ch; + bool res; + + while(iMaxChars > 0) + { + ch = (CLR_UINT32)*inputUTF16++; + + if(ch < 0x0080) + { + if(ch == 0) + { + break; + } + + if(fJustMove == false) + { + if(outputUTF8_size < 1) goto ExitFalse; + + outputUTF8[ 0 ] = ch; + + outputUTF8 += 1; + outputUTF8_size -= 1; + } + + iMaxChars -= 1; + } + else if(ch < 0x0800) + { + if(fJustMove == false) + { + if(outputUTF8_size < 2) goto ExitFalse; + + outputUTF8[ 1 ] = 0x80 | (ch & 0x3F); ch >>= 6; + outputUTF8[ 0 ] = 0xC0 | (ch & 0x1F); + + outputUTF8 += 2; + outputUTF8_size -= 2; + } + + iMaxChars -= 1; + } + else if(ch >= HIGH_SURROGATE_START && ch <= HIGH_SURROGATE_END) + { + ch = SURROGATE_HALFBASE + ((ch - HIGH_SURROGATE_START) << SURROGATE_HALFSHIFT) + (*inputUTF16++ - LOW_SURROGATE_START); + + if(fJustMove == false) + { + if(outputUTF8_size < 4) goto ExitFalse; + + outputUTF8[ 3 ] = 0x80 | (ch & 0x3F); ch >>= 6; + outputUTF8[ 2 ] = 0x80 | (ch & 0x3F); ch >>= 6; + outputUTF8[ 1 ] = 0x80 | (ch & 0x3F); ch >>= 6; + outputUTF8[ 0 ] = 0xF0 | (ch & 0x07); + + outputUTF8 += 4; + outputUTF8_size -= 4; + } + + iMaxChars -= 2; + } + else + { + if(fJustMove == false) + { + if(outputUTF8_size < 3) goto ExitFalse; + + outputUTF8[ 2 ] = 0x80 | (ch & 0x3F); ch >>= 6; + outputUTF8[ 1 ] = 0x80 | (ch & 0x3F); ch >>= 6; + outputUTF8[ 0 ] = 0xE0 | (ch & 0x0F); + + outputUTF8 += 3; + outputUTF8_size -= 3; + } + + iMaxChars -= 1; + } + } + + if(fJustMove == false) + { + if(outputUTF8_size < 1) goto ExitFalse; + + outputUTF8[ 0 ] = 0; + } + + res = true; + goto Exit; + +ExitFalse: + res = false; + +Exit: + m_inputUTF16 = inputUTF16; + m_outputUTF8 = outputUTF8; + m_outputUTF8_size = outputUTF8_size; + + return res; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#if defined(_WIN32) + +void CLR_RT_UnicodeHelper::ConvertToUTF8( const std::wstring& src , + std::string& dst ) +{ + if(src.size()) + { + char* szBuf; + int iSize; + + iSize = ::WideCharToMultiByte( CP_UTF8, 0, src.c_str(), -1, NULL, 0, NULL, NULL ); + + if(iSize > 0) + { + szBuf = new char[ iSize ]; + + iSize = ::WideCharToMultiByte( CP_UTF8, 0, src.c_str(), -1, szBuf, iSize, NULL, NULL ); + if(iSize > 0) + { + dst = szBuf; + } + + delete [] szBuf; + } + } + else + { + dst.erase(); + } +} + +void CLR_RT_UnicodeHelper::ConvertFromUTF8( const std::string& src , + std::wstring& dst ) +{ + if(src.size()) + { + wchar_t* szBuf; + int iSize; + + iSize = ::MultiByteToWideChar( CP_UTF8, 0, src.c_str(), -1, NULL, 0 ); + + if(iSize > 0) + { + szBuf = new wchar_t[ iSize ]; + + iSize = ::MultiByteToWideChar( CP_UTF8, 0, src.c_str(), -1, szBuf, iSize ); + if(iSize > 0) + { + dst = szBuf; + } + + delete [] szBuf; + } + } + else + { + dst.erase(); + } +} + + +#endif + +UnicodeString::UnicodeString() +{ + m_wCharArray = NULL; + m_length = 0; +} + +UnicodeString::~UnicodeString() +{ + Release(); +} + +HRESULT UnicodeString::Assign( const char* string ) +{ + NATIVE_PROFILE_CLR_IO(); + NANOCLR_HEADER(); + + int byteLength = 0; + + /// Before we start assigning remove existing stuff. + Release(); + + m_unicodeHelper.SetInputUTF8( string ); + + m_length = m_unicodeHelper.CountNumberOfCharacters(); + + if(m_length < 0) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + /// We have m_length >=0 now. + + byteLength = (m_length + 1) * sizeof (CLR_UINT16); + + m_wCharArray = (CLR_UINT16 *)CLR_RT_Memory::Allocate( byteLength ); CHECK_ALLOCATION(m_wCharArray); + + m_unicodeHelper.m_outputUTF16 = m_wCharArray; + m_unicodeHelper.m_outputUTF16_size = m_length + 1; + + m_unicodeHelper.ConvertFromUTF8( m_length , false ); + + /// Note m_length > 0 already (see above), hence m_length >= 0 or a valid index. + m_wCharArray[ m_length ] = 0; + + NANOCLR_NOCLEANUP(); +} + +void UnicodeString::Release() +{ + if (m_wCharArray != NULL) + { + CLR_RT_Memory::Release( m_wCharArray ); + } + + m_wCharArray = NULL; +} + diff --git a/source/native/nf-interpreter/src/CLR/Core/Cache.cpp b/source/native/nf-interpreter/src/CLR/Core/Cache.cpp new file mode 100644 index 00000000..05524044 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Cache.cpp @@ -0,0 +1,591 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#if defined(NANOCLR_USE_AVLTREE_FOR_METHODLOOKUP) + +int CLR_RT_EventCache::LookupEntry::Callback_Compare( void* state, CLR_RT_AVLTree::Entry* left, CLR_RT_AVLTree::Entry* right ) +{ + NATIVE_PROFILE_CLR_CORE(); + + LookupEntry* leftDirect = (LookupEntry*)left; + LookupEntry* rightDirect = (LookupEntry*)right; + + return leftDirect->m_payload.Compare( rightDirect->m_payload ); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +void CLR_RT_EventCache::VirtualMethodTable::Initialize() +{ + NATIVE_PROFILE_CLR_CORE(); + + m_entries = (Payload*)&g_scratchVirtualMethodPayload[ 0 ]; + + LookupEntry* node; + size_t i; + + m_tree.Initialize(); + + + m_list_freeItems.DblLinkedList_Initialize(); + m_list_inUse .DblLinkedList_Initialize(); + + m_tree.m_owner.m_ftn_compare = LookupEntry ::Callback_Compare; + m_tree.m_owner.m_ftn_newNode = VirtualMethodTable::Callback_NewNode; + m_tree.m_owner.m_ftn_freeNode = VirtualMethodTable::Callback_FreeNode; + m_tree.m_owner.m_ftn_reassignNode = VirtualMethodTable::Callback_Reassign; + m_tree.m_owner.m_state = this; + + + for(i=0, node=m_entries; iGenericNode_Initialize(); + + m_list_freeItems.LinkAtBack( node ); + } +} + +bool CLR_RT_EventCache::VirtualMethodTable::FindVirtualMethod( const CLR_RT_TypeDef_Index& cls, const CLR_RT_MethodDef_Index& mdVirtual, CLR_RT_MethodDef_Index& md ) +{ + NATIVE_PROFILE_CLR_CORE(); + LookupEntry* en; + LookupEntry key; + CLR_RT_MethodDef_Instance instMD; + CLR_RT_TypeDef_Instance instCLS; + + instMD .InitializeFromIndex ( mdVirtual ); + instCLS.InitializeFromMethod( instMD ); + + // + // Shortcut for terminal virtual methods. + // + if(cls.m_data == instCLS.m_data) + { + if((instMD.m_target->flags & CLR_RECORD_METHODDEF::MD_Abstract) == 0) + { + md = mdVirtual; + + return true; + } + } + + key.m_payload.m_mdVirtual = mdVirtual; + key.m_payload.m_cls = cls; + key.m_payload.m_md.Clear(); + + en = (LookupEntry*)m_tree.Find( &key ); + if(en) + { + md = en->m_payload.m_md; + + // + // Move the node to the top of the MRU list. + // + m_list_inUse.LinkAtFront( en ); + + return true; + } + + { + if(g_CLR_RT_TypeSystem.FindVirtualMethodDef( cls, mdVirtual, md ) == false) + { + return false; + } + } + + { + if(m_list_freeItems.IsEmpty()) + { + en = (LookupEntry*)m_list_inUse.LastNode(); + if(en->Prev() == NULL) + { + // + // No node to steal, return. + // + return true; + } + + m_tree.Remove( en ); + + CLR_PROF_Handler::SuspendTime(); + if(!ConsistencyCheck()) + { + DumpTree(); + } + CLR_PROF_Handler::ResumeTime(); + } + + key.m_payload.m_md = md; + m_tree.Insert( &key ); + + CLR_PROF_Handler::SuspendTime(); + if(!ConsistencyCheck()) + { + DumpTree(); + } + CLR_PROF_Handler::ResumeTime(); + } + + return true; +} + +//--// + +CLR_RT_AVLTree::Entry* CLR_RT_EventCache::VirtualMethodTable::Callback_NewNode( void* state, CLR_RT_AVLTree::Entry* payload ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_EventCache::VirtualMethodTable* pThis = (CLR_RT_EventCache::VirtualMethodTable*)state; + LookupEntry* payloadDirect = (LookupEntry*)payload; + LookupEntry* en; + + en = (LookupEntry*)pThis->m_list_freeItems.ExtractFirstNode(); + if(en) + { + en->m_payload = payloadDirect->m_payload; + + pThis->m_list_inUse.LinkAtFront( en ); + } + + return en; +} + +void CLR_RT_EventCache::VirtualMethodTable::Callback_FreeNode( void* state, CLR_RT_AVLTree::Entry* node ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_EventCache::VirtualMethodTable* pThis = (CLR_RT_EventCache::VirtualMethodTable*)state; + LookupEntry* nodeDirect = (LookupEntry*)node; + + pThis->m_list_freeItems.LinkAtBack( nodeDirect ); +} + +void CLR_RT_EventCache::VirtualMethodTable::Callback_Reassign( void* state, CLR_RT_AVLTree::Entry* from, CLR_RT_AVLTree::Entry* to ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_EventCache::VirtualMethodTable* pThis = (CLR_RT_EventCache::VirtualMethodTable*)state; + LookupEntry* fromDirect = (LookupEntry*)from; + LookupEntry* toDirect = (LookupEntry*)to; + + pThis->m_list_inUse.InsertAfterNode( fromDirect, toDirect ); + + toDirect->m_payload = fromDirect->m_payload; +} + +#else + +void CLR_RT_EventCache::VirtualMethodTable::Initialize() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_UINT32 idx; + + m_entries = (Link*) &g_scratchVirtualMethodTableLink [ 0 ]; + m_entriesMRU = (Link*) &g_scratchVirtualMethodTableLinkMRU[ 0 ]; + m_payloads = (Payload*)&g_scratchVirtualMethodPayload [ 0 ]; + + // + // Link all the entries to themselves => no elements in the lists. + // + for(idx = 0; idx < LinkArraySize(); idx++) + { + Link& lnk = m_entries[ idx ]; + + lnk.m_next = idx; + lnk.m_prev = idx; + } + + // + // Link all the entries to the following one => all the elements are in the MRU list. + // + _ASSERTE(LinkMRUArraySize() < 0xFFFF); + for(idx = 0; idx < LinkMRUArraySize(); idx++) + { + Link& lnk = m_entriesMRU[ idx ]; + + lnk.m_next = idx == LinkMRUArraySize() - 1 ? 0 : idx + 1; + lnk.m_prev = idx == 0 ? (CLR_UINT16)LinkMRUArraySize() - 1 : idx - 1; + } +} + +bool CLR_RT_EventCache::VirtualMethodTable::FindVirtualMethod( const CLR_RT_TypeDef_Index& cls, const CLR_RT_MethodDef_Index& mdVirtual, CLR_RT_MethodDef_Index& md ) +{ + NATIVE_PROFILE_CLR_CORE(); + Payload::Key key; + CLR_UINT32 idx; + CLR_UINT32 idxHead; + CLR_UINT32 clsData = cls .m_data; + CLR_UINT32 mdVirtualData = mdVirtual.m_data; + +#if defined(_WIN32) + bool fVerify = false; + + { + CLR_RT_MethodDef_Instance instMD; + CLR_RT_TypeDef_Instance instCLS; + + instMD .InitializeFromIndex ( mdVirtual ); + instCLS.InitializeFromMethod( instMD ); + + // + // Shortcut for terminal virtual methods. + // + if(clsData == instCLS.m_data) + { + if((instMD.m_target->flags & CLR_RECORD_METHODDEF::MD_Abstract) == 0) + { + md = mdVirtual; + + fVerify = true; + } + } + } +#endif + + if(cls.Assembly() == mdVirtual.Assembly()) + { + CLR_RT_Assembly* assm = g_CLR_RT_TypeSystem.m_assemblies [ mdVirtual.Assembly()-1 ]; + CLR_IDX owner = assm->m_pCrossReference_MethodDef[ mdVirtual.Method() ].GetOwner(); + + if(cls.Type() == owner) + { +#if defined(_WIN32) + if(fVerify != true) + { + CLR_Debug::Printf( "INTERNAL ERROR: Shortcut for terminal virtual methods failed: CLS:%08x:%08x => %08x\r\n", cls.m_data, mdVirtual.m_data, md.m_data ); + ::DebugBreak(); + } +#endif + + md = mdVirtual; + + return true; + } + } + +#if defined(_WIN32) + if(fVerify != false) + { + CLR_Debug::Printf( "INTERNAL ERROR: Shortcut for terminal virtual methods failed: CLS:%08x:%08x\r\n", cls.m_data, mdVirtual.m_data ); + ::DebugBreak(); + } +#endif + + + key.m_mdVirtual.m_data = mdVirtualData; + key.m_cls .m_data = clsData; + + idxHead = (SUPPORT_ComputeCRC( &key, sizeof(key), 0 ) % (LinkArraySize() - PayloadArraySize())) + PayloadArraySize(); + + for(idx = m_entries[ idxHead ].m_next; ; idx = m_entries[ idx ].m_next) + { + if(idx != idxHead) + { + Payload& res = m_payloads[ idx ]; + + if(res.m_key.m_mdVirtual.m_data != mdVirtualData) continue; + if(res.m_key.m_cls .m_data != clsData ) continue; + + md = res.m_md; + + break; + } + else + { + if(g_CLR_RT_TypeSystem.FindVirtualMethodDef( cls, mdVirtual, md ) == false) return false; + + idx = GetNewEntry(); + + Payload& res = m_payloads[ idx ]; + + res.m_md = md; + res.m_key = key; + + break; + } + } + + MoveEntryToTop( m_entries , idxHead , idx ); + MoveEntryToTop( m_entriesMRU, LinkMRUArraySize() - 1, idx ); + + return true; +} + +void CLR_RT_EventCache::VirtualMethodTable::MoveEntryToTop( Link* entries, CLR_UINT32 slot, CLR_UINT32 idx ) +{ + NATIVE_PROFILE_CLR_CORE(); + Link& list = entries[ slot ]; + + if(list.m_next != idx) + { + Link& node = entries[ idx ]; + CLR_UINT32 next; + CLR_UINT32 prev; + + // + // Unlink. + // + next = node.m_next; + prev = node.m_prev; + + entries[ next ].m_prev = prev; + entries[ prev ].m_next = next; + + // + // Insert. + // + next = list.m_next; + + node.m_next = next; + node.m_prev = slot; + + list .m_next = idx; + entries[ next ].m_prev = idx; + } +} + +#endif // #if defined(NANOCLR_USE_AVLTREE_FOR_METHODLOOKUP) + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +void CLR_RT_EventCache::EventCache_Initialize() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_CLEAR(*this); + + m_events = (BoundedList*)&m_scratch[ 0 ]; + + BoundedList* lst = m_events; + size_t num = c_maxFastLists; + + while(num--) + { + lst->m_blocks.DblLinkedList_Initialize(); + + lst++; + } + + m_lookup_VirtualMethod.Initialize(); + +#ifndef CLR_NO_IL_INLINE + m_inlineBufferStart = (CLR_RT_InlineBuffer*)g_scratchInlineBuffer; + + num = InlineBufferCount()-1; + + for(int i=0; i<(int)num; i++) + { + m_inlineBufferStart[i].m_pNext = &m_inlineBufferStart[i+1]; + } + m_inlineBufferStart[num].m_pNext = NULL; +#endif +} + +CLR_UINT32 CLR_RT_EventCache::EventCache_Cleanup() +{ + NATIVE_PROFILE_CLR_CORE(); + BoundedList* lst = m_events; + size_t num = c_maxFastLists; + CLR_UINT32 tot = 0; + + while(num--) + { + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Node,ptr,lst->m_blocks) + { + ptr->SetDataId( CLR_RT_HEAPBLOCK_RAW_ID(DATATYPE_FREEBLOCK, CLR_RT_HeapBlock::HB_Pinned, ptr->DataSize()) ); + ptr->ClearData(); + + tot += ptr->DataSize(); + } + NANOCLR_FOREACH_NODE_END(); + + lst->m_blocks.DblLinkedList_Initialize(); + + lst++; + } + + return tot; +} + +//--// + +void CLR_RT_EventCache::Append_Node( CLR_RT_HeapBlock* node ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock_Node* ptr = (CLR_RT_HeapBlock_Node*)node; + CLR_UINT32 blocks = ptr->DataSize(); + BoundedList& lst = m_events[blocks < c_maxFastLists ? blocks : 0]; + + ptr->ChangeDataType ( DATATYPE_CACHEDBLOCK ); + ptr->ChangeDataFlags( CLR_RT_HeapBlock::HB_Alive | CLR_RT_HeapBlock::HB_Event ); + + NANOCLR_CHECK_EARLY_COLLECTION(ptr); + + ptr->Debug_ClearBlock( 0xAB ); + + lst.m_blocks.LinkAtBack( ptr ); + +#if defined(NANOCLR_PROFILE_NEW_ALLOCATIONS) + g_CLR_PRF_Profiler.TrackObjectDeletion(node); +#endif +} + +CLR_RT_HeapBlock* CLR_RT_EventCache::Extract_Node_Slow( CLR_UINT32 dataType, CLR_UINT32 flags, CLR_UINT32 blocks ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock_Node* ptr; + CLR_RT_HeapBlock_Node* best = NULL; + CLR_UINT32 bestSize = 0; + + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Node,ptr,m_events[ 0 ].m_blocks) + { + CLR_UINT32 size = ptr->DataSize(); + + if(size == blocks) + { + best = ptr; + bestSize = blocks; + break; + } + + if(size >= blocks) + { + if(( best && (size < bestSize )) || + (!best && (size <= (blocks * 20) / 16)) ) // Accept a maximum overhead of 25%. + { + best = ptr; + bestSize = size; + } + } + } + NANOCLR_FOREACH_NODE_END(); + + ptr = best; + + if(ptr) + { + // + // Did we select a block bigger than requested? Requeue the tail. + // + if(bestSize > blocks) + { + CLR_RT_HeapBlock_Node* next = &ptr[ blocks ]; + + ptr->SetDataId ( CLR_RT_HEAPBLOCK_RAW_ID(DATATYPE_CACHEDBLOCK, (CLR_RT_HeapBlock::HB_Alive | CLR_RT_HeapBlock::HB_Event), blocks) ); + next->SetDataId( CLR_RT_HEAPBLOCK_RAW_ID(DATATYPE_CACHEDBLOCK, (CLR_RT_HeapBlock::HB_Alive | CLR_RT_HeapBlock::HB_Event), (bestSize - blocks)) ); + next->ClearData(); + + Append_Node( next ); + } + + ptr->Unlink(); + + ptr->ChangeDataType ( dataType ); + ptr->ChangeDataFlags( CLR_RT_HeapBlock::HB_Alive | CLR_RT_HeapBlock::HB_Event ); + + if(flags & CLR_RT_HeapBlock::HB_InitializeToZero) + { + ptr->InitializeToZero(); + } + else + { + ptr->Debug_ClearBlock( 0xAD ); + } + +#if defined(NANOCLR_PROFILE_NEW_ALLOCATIONS) + g_CLR_PRF_Profiler.TrackObjectCreation( ptr ); +#endif + + return ptr; + } + + return g_CLR_RT_ExecutionEngine.ExtractHeapBlocksForEvents( dataType, flags, blocks ); +} + +CLR_RT_HeapBlock* CLR_RT_EventCache::Extract_Node_Fast( CLR_UINT32 dataType, CLR_UINT32 flags, CLR_UINT32 blocks ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock_Node* ptr = m_events[ blocks ].m_blocks.FirstNode(); + + if(ptr->Next()) + { + ptr->Unlink(); + + ptr->ChangeDataType ( dataType ); + ptr->ChangeDataFlags( CLR_RT_HeapBlock::HB_Alive | CLR_RT_HeapBlock::HB_Event ); + + if(flags & CLR_RT_HeapBlock::HB_InitializeToZero) + { + ptr->InitializeToZero(); + } + else + { + ptr->Debug_ClearBlock( 0xAD ); + } + +#if defined(NANOCLR_PROFILE_NEW_ALLOCATIONS) + g_CLR_PRF_Profiler.TrackObjectCreation( ptr ); +#endif + + return ptr; + } + + return g_CLR_RT_ExecutionEngine.ExtractHeapBlocksForEvents( dataType, flags, blocks ); +} + +CLR_RT_HeapBlock* CLR_RT_EventCache::Extract_Node_Bytes( CLR_UINT32 dataType, CLR_UINT32 flags, CLR_UINT32 bytes ) +{ + NATIVE_PROFILE_CLR_CORE(); + return Extract_Node( dataType, flags, CONVERTFROMSIZETOHEAPBLOCKS(bytes) ); +} + +CLR_RT_HeapBlock* CLR_RT_EventCache::Extract_Node( CLR_UINT32 dataType, CLR_UINT32 flags, CLR_UINT32 blocks ) +{ + NATIVE_PROFILE_CLR_CORE(); +#if defined(NANOCLR_FORCE_GC_BEFORE_EVERY_ALLOCATION) + return g_CLR_RT_ExecutionEngine.ExtractHeapBlocksForEvents( dataType, flags, blocks ); +#else + if(blocks > 0 && blocks < c_maxFastLists) return Extract_Node_Fast( dataType, flags, blocks ); + else return Extract_Node_Slow( dataType, flags, blocks ); +#endif +} + +//--// + +bool CLR_RT_EventCache::FindVirtualMethod( const CLR_RT_TypeDef_Index& cls, const CLR_RT_MethodDef_Index& mdVirtual, CLR_RT_MethodDef_Index& md ) +{ + NATIVE_PROFILE_CLR_CORE(); + return m_lookup_VirtualMethod.FindVirtualMethod( cls, mdVirtual, md ); +} + +// -- // + +#ifndef CLR_NO_IL_INLINE +bool CLR_RT_EventCache::GetInlineFrameBuffer(CLR_RT_InlineBuffer** ppBuffer) +{ + if(m_inlineBufferStart != NULL) + { + *ppBuffer = m_inlineBufferStart; + + m_inlineBufferStart = m_inlineBufferStart->m_pNext; + + return true; + } + + *ppBuffer = NULL; + + return false; +} + +bool CLR_RT_EventCache::FreeInlineBuffer(CLR_RT_InlineBuffer* pBuffer) +{ + pBuffer->m_pNext = m_inlineBufferStart; + m_inlineBufferStart = pBuffer; + return true; +} +#endif + +//////////////////////////////////////////////////////////////////////////////// + diff --git a/source/native/nf-interpreter/src/CLR/Core/Checks.cpp b/source/native/nf-interpreter/src/CLR/Core/Checks.cpp new file mode 100644 index 00000000..cc4984b6 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Checks.cpp @@ -0,0 +1,83 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +HRESULT CLR_Checks::VerifyObject( CLR_RT_HeapBlock& top ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + switch(top.DataType()) + { + case DATATYPE_OBJECT: + case DATATYPE_BYREF: + if(top.Dereference() != NULL) NANOCLR_SET_AND_LEAVE(S_OK); + break; + + case DATATYPE_ARRAY_BYREF: + if(top.DereferenceArray() != NULL) NANOCLR_SET_AND_LEAVE(S_OK); + break; + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + NANOCLR_SET_AND_LEAVE(CLR_E_NULL_REFERENCE); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_Checks::VerifyArrayReference( CLR_RT_HeapBlock& ref ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* array; + + if(ref.DataType() != DATATYPE_OBJECT) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + array = ref.DereferenceArray(); + if(array == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_NULL_REFERENCE); + } + + if(array->DataType() != DATATYPE_SZARRAY) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_Checks::VerifyUnknownInstruction( CLR_OPCODE op ) +{ + (void)op; + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(CLR_E_UNKNOWN_INSTRUCTION); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_Checks::VerifyUnsupportedInstruction( CLR_OPCODE op ) +{ + (void)op; + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(CLR_E_UNSUPPORTED_INSTRUCTION); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/Core/Core-vs2019.vcxproj b/source/native/nf-interpreter/src/CLR/Core/Core-vs2019.vcxproj new file mode 100644 index 00000000..0baacbd4 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Core-vs2019.vcxproj @@ -0,0 +1,218 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + {89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1} + Win32Proj + Core + 10.0.17763.0 + Core + + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + false + v142 + true + Unicode + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + false + v142 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(IntDir) + $(SolutionDir)$(Configuration)\ + + + $(SolutionDir)$(Configuration)\ + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + NotUsing + Level3 + Disabled + WIN32;_DEBUG;_LIB;VERSION_MAJOR=0;VERSION_MINOR=0;VERSION_BUILD=0;VERSION_REVISION=0;OEMSYSTEMINFOSTRING="WIN_32";TARGETNAMESTRING="CLR_WIN32";PLATFORMNAMESTRING="WIN32";%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\CorLib;..\..\HAL\Include;..\..\PAL\Include + + + Windows + + + + + Use + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + + + Windows + + + + + Level3 + NotUsing + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;VERSION_MAJOR=0;VERSION_MINOR=0;VERSION_BUILD=0;VERSION_REVISION=0;OEMSYSTEMINFOSTRING="WIN_32";TARGETNAMESTRING="CLR_WIN32";PLATFORMNAMESTRING="WIN32";%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\CorLib;..\..\HAL\Include;..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + Use + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/Core-vs2019.vcxproj.filters b/source/native/nf-interpreter/src/CLR/Core/Core-vs2019.vcxproj.filters new file mode 100644 index 00000000..106dbc69 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Core-vs2019.vcxproj.filters @@ -0,0 +1,215 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + + + Source Files + + + Header Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/Core.cpp b/source/native/nf-interpreter/src/CLR/Core/Core.cpp new file mode 100644 index 00000000..6ad28697 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Core.cpp @@ -0,0 +1,87 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +CLR_UINT32 g_buildCRC; + +CLR_RT_ExecutionEngine g_CLR_RT_ExecutionEngine; +CLR_RT_WellKnownTypes g_CLR_RT_WellKnownTypes; +CLR_RT_WellKnownMethods g_CLR_RT_WellKnownMethods; +CLR_RT_TypeSystem g_CLR_RT_TypeSystem; +CLR_RT_EventCache g_CLR_RT_EventCache; +CLR_RT_GarbageCollector g_CLR_RT_GarbageCollector; +CLR_HW_Hardware g_CLR_HW_Hardware; + +//const CLR_RADIAN c_CLR_radians[] = +//{ +// { 1000, -0 }, +// { 995, 105 }, +// { 978, 208 }, +// { 951, 309 }, +// { 914, 407 }, +// { 866, 500 }, +// { 809, 588 }, +// { 743, 669 }, +// { 669, 743 }, +// { 588, 809 }, +// { 500, 866 }, +// { 407, 914 }, +// { 309, 951 }, +// { 208, 978 }, +// { 105, 995 }, +// { 0, 1000 }, +// { -105, 995 }, +// { -208, 978 }, +// { -309, 951 }, +// { -407, 914 }, +// { -500, 866 }, +// { -588, 809 }, +// { -669, 743 }, +// { -743, 669 }, +// { -809, 588 }, +// { -866, 500 }, +// { -914, 407 }, +// { -951, 309 }, +// { -978, 208 }, +// { -995, 105 }, +// { -1000, 0 }, +// { -995, -105 }, +// { -978, -208 }, +// { -951, -309 }, +// { -914, -407 }, +// { -866, -500 }, +// { -809, -588 }, +// { -743, -669 }, +// { -669, -743 }, +// { -588, -809 }, +// { -500, -866 }, +// { -407, -914 }, +// { -309, -951 }, +// { -208, -978 }, +// { -105, -995 }, +// { 0, -1000 }, +// { 105, -995 }, +// { 208, -978 }, +// { 309, -951 }, +// { 407, -914 }, +// { 500, -866 }, +// { 588, -809 }, +// { 669, -743 }, +// { 743, -669 }, +// { 809, -588 }, +// { 866, -500 }, +// { 914, -407 }, +// { 951, -309 }, +// { 978, -208 }, +// { 995, -105 }, +//}; + +// UNDONE: FIXME: the Arm 3.0 compiler drags in a bunch of ABI methods (for initialization) if struct arrays are not initialized +CLR_UINT32 g_scratchDebugger [ sizeof(CLR_DBG_Debugger) ]; +CLR_UINT32 g_scratchDebuggerMessaging[ sizeof(CLR_Messaging) ]; +CLR_DBG_Debugger *g_CLR_DBG_Debugger; + +//--// diff --git a/source/native/nf-interpreter/src/CLR/Core/Core.h b/source/native/nf-interpreter/src/CLR/Core/Core.h new file mode 100644 index 00000000..1a5f4e57 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Core.h @@ -0,0 +1,26 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _NANOCLR_CORE_H_ +#define _NANOCLR_CORE_H_ + +#include +#include +//#include +//#include +#include +//#include +//#include +//#include +// +//#include +// +#include +//#include +//#include +#include + +#endif // _NANOCLR_CORE_H_ + diff --git a/source/native/nf-interpreter/src/CLR/Core/Core.vcxproj b/source/native/nf-interpreter/src/CLR/Core/Core.vcxproj new file mode 100644 index 00000000..803701fd --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Core.vcxproj @@ -0,0 +1,217 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + {89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1} + Win32Proj + Core + 10.0.17763.0 + + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(Configuration)\ + $(SolutionDir)$(Configuration)\ + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\ + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + NotUsing + Level3 + Disabled + WIN32;_DEBUG;_LIB;VERSION_MAJOR=0;VERSION_MINOR=0;VERSION_BUILD=0;VERSION_REVISION=0;OEMSYSTEMINFOSTRING="WIN_32";TARGETNAMESTRING="CLR_WIN32";PLATFORMNAMESTRING="WIN32";%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\CorLib;..\..\HAL\Include;..\..\PAL\Include + + + Windows + + + + + Use + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + + + Windows + + + + + Level3 + NotUsing + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;VERSION_MAJOR=0;VERSION_MINOR=0;VERSION_BUILD=0;VERSION_REVISION=0;OEMSYSTEMINFOSTRING="WIN_32";TARGETNAMESTRING="CLR_WIN32";PLATFORMNAMESTRING="WIN32";%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\CorLib;..\..\HAL\Include;..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + Use + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/Core.vcxproj.filters b/source/native/nf-interpreter/src/CLR/Core/Core.vcxproj.filters new file mode 100644 index 00000000..106dbc69 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Core.vcxproj.filters @@ -0,0 +1,215 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + + + Source Files + + + Header Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/Execution.cpp b/source/native/nf-interpreter/src/CLR/Core/Execution.cpp new file mode 100644 index 00000000..7f92b6f7 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Execution.cpp @@ -0,0 +1,3573 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" +#include +#include + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +static const CLR_INT64 c_MaximumTimeToActive = (TIME_CONVERSION__ONEMINUTE * TIME_CONVERSION__TO_SECONDS); + + +//--// + +CLR_RT_ExecutionEngine::ExecutionConstraintCompensation CLR_RT_ExecutionEngine::s_compensation = { 0, 0, 0 }; + +//--// + +HRESULT CLR_RT_ExecutionEngine::CreateInstance() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_CLEAR(g_CLR_RT_ExecutionEngine); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.ExecutionEngine_Initialize()); + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT CLR_RT_ExecutionEngine::ExecutionEngine_Initialize() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + m_maximumTimeToActive = c_MaximumTimeToActive; // CLR_INT64 m_maximumTimeToActive + // int m_iDebugger_Conditions; + // + + // CLR_INT64 m_currentNextActivityTime; + m_timerCache = false; // bool m_timerCache; + // CLR_INT64 m_timerCacheNextTimeout; + // + m_heap .DblLinkedList_Initialize(); // CLR_RT_DblLinkedList m_heap; + // CLR_RT_HeapCluster* m_lastHcUsed; + m_heapState = c_HeapState_Normal; // int m_heapState; + // + m_weakReferences.DblLinkedList_Initialize(); // CLR_RT_DblLinkedList m_weakReferences; + // + m_timers .DblLinkedList_Initialize(); // CLR_RT_DblLinkedList m_timers; + m_raisedEvents = 0; // CLR_UINT32 m_raisedEvents; + // + m_threadsReady .DblLinkedList_Initialize(); // CLR_RT_DblLinkedList m_threadsReady; + m_threadsWaiting.DblLinkedList_Initialize(); // CLR_RT_DblLinkedList m_threadsWaiting; + m_threadsZombie .DblLinkedList_Initialize(); // CLR_RT_DblLinkedList m_threadsZombie; + // int m_lastPid; + // + m_finalizersAlive .DblLinkedList_Initialize(); // CLR_RT_DblLinkedList m_finalizersAlive; + m_finalizersPending.DblLinkedList_Initialize(); // CLR_RT_DblLinkedList m_finalizersPending; + // CLR_RT_Thread* m_finalizerThread; + // CLR_RT_Thread* m_cctorThread; + // +#if !defined(NANOCLR_APPDOMAINS) + m_globalLock = NULL; // CLR_RT_HeapBlock* m_globalLock; + m_outOfMemoryException = NULL; // CLR_RT_HeapBlock* m_outOfMemoryException; +#endif // + + m_currentUICulture = NULL; // CLR_RT_HeapBlock* m_currentUICulture; + + CLR_RT_HeapBlock_EndPoint::HandlerMethod_Initialize(); + CLR_RT_HeapBlock_NativeEventDispatcher::HandlerMethod_Initialize(); + + m_interruptThread = NULL; // CLR_RT_Thread m_interruptThread; + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + m_scratchPadArray = NULL; // CLR_RT_HeapBlock_Array* m_scratchPadArray; +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + +#if defined(NANOCLR_APPDOMAINS) + m_appDomains.DblLinkedList_Initialize(); // CLR_RT_DblLinkedList m_appDomains; + + m_appDomainCurrent = NULL; // CLR_AppDomainCurrent* m_appDomainCurrent; + m_appDomainIdNext = c_AppDomainId_Invalid + 1; // int m_appDomainIdNext; +#endif + + m_currentThread = NULL; + + m_GlobalExecutionCounter = 0; + +#if !defined(BUILD_RTM) + m_fShuttingDown = false; //bool m_fShuttingDown; +#endif + + //--// + + NANOCLR_CHECK_HRESULT(AllocateHeaps()); + + g_CLR_RT_TypeSystem.TypeSystem_Initialize(); + g_CLR_RT_EventCache.EventCache_Initialize(); + + //--// + + NANOCLR_CHECK_HRESULT(CLR_HW_Hardware::CreateInstance()); + + //--// + + NANOCLR_CHECK_HRESULT(CLR_Messaging::CreateInstance()); + + NANOCLR_CHECK_HRESULT(CLR_DBG_Debugger::CreateInstance()); + +#if defined(NANOCLR_PROFILE_NEW) + NANOCLR_CHECK_HRESULT(CLR_PRF_Profiler::CreateInstance()); +#endif + +#if defined(NANOCLR_APPDOMAINS) + NANOCLR_CHECK_HRESULT(CLR_RT_AppDomain::CreateInstance( "default", m_appDomainCurrent )); +#endif + + m_startTime = HAL_Time_CurrentTime(); + + CLR_RT_HeapBlock_WeakReference::RecoverObjects( m_heap ); + + //--// + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_ExecutionEngine::AllocateHeaps() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + const CLR_UINT32 c_HeapClusterSize = sizeof(CLR_RT_HeapBlock) * CLR_RT_HeapBlock::HB_MaxSize; + + CLR_UINT8* heapFirstFree = s_CLR_RT_Heap.m_location; + CLR_UINT32 heapFree = s_CLR_RT_Heap.m_size; + CLR_INT32 i = 0; + CLR_UINT32 blockSize = 1; + + if(heapFree <= sizeof(CLR_RT_HeapCluster)) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + while(heapFree > sizeof(CLR_RT_HeapCluster)) + { + CLR_RT_HeapCluster* hc = (CLR_RT_HeapCluster*) heapFirstFree; + CLR_UINT32 size = (heapFree < c_HeapClusterSize) ? heapFree : c_HeapClusterSize; + +#if NANOCLR_VALIDATE_HEAP >= NANOCLR_VALIDATE_HEAP_1_HeapBlocksAndUnlink + + CLR_Debug::Printf( "Heap Cluster information\r\n"); + CLR_Debug::Printf( "Start: %08x\r\n", (size_t)heapFirstFree); + CLR_Debug::Printf( "Free: %08x\r\n", (size_t)heapFree); + CLR_Debug::Printf( "Block size: %d\r\n", sizeof(CLR_RT_HeapBlock)); + +#endif + /// + /// Speed up heap initialization for devices with very large heaps > 1MB + /// Exponentially increase the size of a default heap block + /// + if(i > 100*1024*1024) + { + blockSize = CLR_RT_HeapBlock::HB_MaxSize; + } + else if( i > 10*1024*1024) + { + blockSize = 10*1024; + } + else if(i > 1024*1024) + { + blockSize = 1*1024; + } + + hc->HeapCluster_Initialize( size, blockSize ); + + m_heap.LinkAtBack( hc ); + + heapFirstFree += size; + heapFree -= size; + i += size; + } + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT CLR_RT_ExecutionEngine::DeleteInstance() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + g_CLR_RT_ExecutionEngine.ExecutionEngine_Cleanup(); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +void CLR_RT_ExecutionEngine::ExecutionEngine_Cleanup() +{ + ///////////////////////////////////////////////////////////////////////////////////////////////// + // developer notes: + // Most of the following calls are just for pure ceremony and gracefully terminating stuff, + // cleaning collections and such. + // In particular the previous existing calls to Abort threads and ReleaseAllThreads is completely irrelevant + // because the execution engine wasn't running anymore. Whatever code that is on those threads + // there to be executed wouldn't never be executed anyways. + ///////////////////////////////////////////////////////////////////////////////////////////////// + + NATIVE_PROFILE_CLR_CORE(); + m_fShuttingDown = true; + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + m_scratchPadArray = NULL; + m_breakpointsNum = 0; + + CLR_DBG_Debugger::DeleteInstance(); +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + +#if defined(NANOCLR_PROFILE_NEW) + CLR_PRF_Profiler::DeleteInstance(); +#endif + + CLR_Messaging::DeleteInstance(); + + CLR_HW_Hardware::DeleteInstance(); + + m_finalizersAlive .DblLinkedList_PushToCache(); + m_finalizersPending.DblLinkedList_PushToCache(); + m_finalizerThread = NULL; + m_cctorThread = NULL; + m_timerThread = NULL; + + g_CLR_RT_TypeSystem.TypeSystem_Cleanup(); + g_CLR_RT_EventCache.EventCache_Cleanup(); + +#if !defined(NANOCLR_APPDOMAINS) + m_globalLock = NULL; +#endif + + CLR_RT_HeapBlock_EndPoint::HandlerMethod_CleanUp(); + CLR_RT_HeapBlock_NativeEventDispatcher::HandlerMethod_CleanUp(); + + m_interruptThread = NULL; + + m_heap.DblLinkedList_Initialize(); +} + +//--// + +HRESULT CLR_RT_ExecutionEngine::StartHardware() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(g_CLR_HW_Hardware.Hardware_Initialize()); + + NANOCLR_NOCLEANUP(); +} + +void CLR_RT_ExecutionEngine::Reboot( bool fHard ) +{ + NATIVE_PROFILE_CLR_CORE(); + + if(fHard) + { + ::CPU_Reset(); + } + else + { + CLR_EE_REBOOT_CLR; + CLR_EE_DBG_SET(RebootPending); + } +} + +CLR_INT64 CLR_RT_ExecutionEngine::GetUptime() +{ + return HAL_Time_CurrentTime() - g_CLR_RT_ExecutionEngine.m_startTime; +} + +void CLR_RT_ExecutionEngine::JoinAllThreadsAndExecuteFinalizer() +{ +} + +void CLR_RT_ExecutionEngine::LoadDownloadedAssemblies() +{ + NATIVE_PROFILE_CLR_CORE (); + PerformGarbageCollection(); + PerformHeapCompaction (); + + // + // Load any patch or similar! + // + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_WeakReference,weak,m_weakReferences) + { + if((weak->m_identity.m_flags & CLR_RT_HeapBlock_WeakReference::WR_ArrayOfBytes) != 0 && weak->m_targetSerialized) + { + CLR_RECORD_ASSEMBLY* header; + + header = (CLR_RECORD_ASSEMBLY*)weak->m_targetSerialized->GetFirstElement(); + + if(header->GoodAssembly()) + { + CLR_RT_Assembly* assm = NULL; + + if(SUCCEEDED(CLR_RT_Assembly::CreateInstance( header, assm ))) + { + assm->m_pFile = weak->m_targetSerialized; + + g_CLR_RT_TypeSystem.Link( assm ); + } + } + } + } + NANOCLR_FOREACH_NODE_END(); + + (void)g_CLR_RT_TypeSystem.ResolveAll(); + + NANOCLR_FOREACH_ASSEMBLY(g_CLR_RT_TypeSystem) + { + if(pASSM->m_pFile) + { + // + // For those assemblies that failed to load (missing dependency?), clean up. + // + if((pASSM->m_flags & CLR_RT_Assembly::ResolutionCompleted) == 0) + { + pASSM->m_pFile = NULL; + + pASSM->DestroyInstance(); + } + } + } + NANOCLR_FOREACH_ASSEMBLY_END(); + + g_CLR_RT_TypeSystem.PrepareForExecution(); +} + +//--// + +void CLR_RT_ExecutionEngine::ExecutionConstraint_Suspend() +{ + NATIVE_PROFILE_CLR_CORE(); + s_compensation.Suspend(); +} + +void CLR_RT_ExecutionEngine::ExecutionConstraint_Resume() +{ + NATIVE_PROFILE_CLR_CORE(); + s_compensation.Resume(); +} + +//--// + +CLR_UINT32 CLR_RT_ExecutionEngine::PerformGarbageCollection() +{ + NATIVE_PROFILE_CLR_CORE(); + m_heapState = c_HeapState_UnderGC; + + CLR_UINT32 freeMem = g_CLR_RT_GarbageCollector.ExecuteGarbageCollection(); + + m_heapState = c_HeapState_Normal; + + m_lastHcUsed = NULL; + +#if !defined(BUILD_RTM) || defined(_WIN32) + if(m_fPerformHeapCompaction) CLR_EE_SET( Compaction_Pending ); +#endif + + g_CLR_RT_ExecutionEngine.SpawnFinalizer(); + + return freeMem; +} + +void CLR_RT_ExecutionEngine::PerformHeapCompaction() +{ + NATIVE_PROFILE_CLR_CORE(); + if(CLR_EE_DBG_IS( NoCompaction )) return; + + g_CLR_RT_GarbageCollector.ExecuteCompaction(); + + CLR_EE_CLR( Compaction_Pending ); + + m_lastHcUsed = NULL; +} + +void CLR_RT_ExecutionEngine::Relocate() +{ + NATIVE_PROFILE_CLR_CORE(); +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_scratchPadArray ); +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + +#if !defined(NANOCLR_APPDOMAINS) + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_globalLock ); + //CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_outOfMemoryException ); +#endif + + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_currentUICulture ); + + m_weakReferences.Relocate(); +} + +//--// + +#if defined(NANOCLR_APPDOMAINS) + +void CLR_RT_ExecutionEngine::TryToUnloadAppDomains_Helper_Threads( CLR_RT_DblLinkedList& threads ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_NODE(CLR_RT_Thread,th,threads) + { + if(th->m_flags & CLR_RT_Thread::TH_F_ContainsDoomedAppDomain) + { + NANOCLR_FOREACH_NODE(CLR_RT_StackFrame, stack, th->m_stackFrames) + { + stack->m_appDomain->m_fCanBeUnloaded = false; + } + NANOCLR_FOREACH_NODE_END(); + } + } + NANOCLR_FOREACH_NODE_END(); +} + +void CLR_RT_ExecutionEngine::TryToUnloadAppDomains_Helper_Finalizers( CLR_RT_DblLinkedList& finalizers, bool fAlive ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Finalizer,fin,finalizers) + { + if(!fin->m_appDomain->IsLoaded()) + { + if(fAlive) + { + //When an AppDomain is being unloaded, all live finalizers are run, regardless + //of whether or not they are still reachable. + m_finalizersPending.LinkAtBack( fin ); + } + + fin->m_appDomain->m_fCanBeUnloaded = false; + } + } + NANOCLR_FOREACH_NODE_END(); +} + +bool CLR_RT_ExecutionEngine::TryToUnloadAppDomains() +{ + NATIVE_PROFILE_CLR_CORE(); + bool fAnyAppDomainsUnloaded = false; + + NANOCLR_FOREACH_NODE(CLR_RT_AppDomain,appDomain,m_appDomains) + { + appDomain->m_fCanBeUnloaded = true; + } + NANOCLR_FOREACH_NODE_END(); + + TryToUnloadAppDomains_Helper_Finalizers( m_finalizersAlive , true ); + TryToUnloadAppDomains_Helper_Finalizers( m_finalizersPending, false ); + + TryToUnloadAppDomains_Helper_Threads( m_threadsReady ); + TryToUnloadAppDomains_Helper_Threads( m_threadsWaiting ); + + CLR_EE_CLR( UnloadingAppDomain ); + + NANOCLR_FOREACH_NODE(CLR_RT_AppDomain,appDomain,m_appDomains) + { + if(appDomain->m_state == CLR_RT_AppDomain::AppDomainState_Unloading) + { + if(appDomain->m_fCanBeUnloaded) + { + appDomain->m_state = CLR_RT_AppDomain::AppDomainState_Unloaded; + appDomain->AppDomain_Uninitialize(); + fAnyAppDomainsUnloaded = true; + } + else + { + CLR_EE_SET(UnloadingAppDomain); + } + } + } + NANOCLR_FOREACH_NODE_END(); + + if(fAnyAppDomainsUnloaded) + { + SignalEvents( CLR_RT_ExecutionEngine::c_Event_AppDomain ); +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + Breakpoint_Assemblies_Loaded(); +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + } + + return fAnyAppDomainsUnloaded; +} + +#endif + +HRESULT CLR_RT_ExecutionEngine::WaitForDebugger() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + while(CLR_EE_DBG_IS(Stopped) && !CLR_EE_DBG_IS(RebootPending) && !CLR_EE_DBG_IS(ExitPending)) + { + // TODO: Generalize this as a standard HAL API +#if defined(WIN32) + if(HAL_Windows_IsShutdownPending()) + { + NANOCLR_SET_AND_LEAVE(CLR_E_SHUTTING_DOWN); + } +#endif + + DebuggerLoop(); + } + +#if defined(WIN32) + NANOCLR_NOCLEANUP(); +#else + NANOCLR_NOCLEANUP_NOLABEL(); +#endif +} + +#if defined(WIN32) +HRESULT CLR_RT_ExecutionEngine::CreateEntryPointArgs( CLR_RT_HeapBlock& argsBlk, wchar_t* szCommandLineArgs ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + std::list args; + + wchar_t* szArgNext = NULL; + wchar_t* szArg = szCommandLineArgs; + wchar_t* sep = L" "; + wchar_t* context = NULL; + + szArg = wcstok_s( szArg, sep, &context ); + + while(szArg != NULL) + { + std::wstring arg = szArg; + args.insert( args.end(), arg ); + + szArg = wcstok_s( NULL, sep, &context ); + } + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( argsBlk, (CLR_UINT32)args.size(), g_CLR_RT_WellKnownTypes.m_String )); + + CLR_RT_HeapBlock_Array* array = argsBlk.Array(); + CLR_UINT32 iArg = 0; + + for(std::list::iterator it = args.begin(); it != args.end(); it++, iArg++) + { + std::string arg; + + CLR_RT_HeapBlock* blk = (CLR_RT_HeapBlock*)array->GetElement( iArg ); + CLR_RT_UnicodeHelper::ConvertToUTF8( (*it).c_str(), arg ); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( *blk, arg.c_str() )); + } + + NANOCLR_NOCLEANUP(); +} + +#endif + +HRESULT CLR_RT_ExecutionEngine::Execute( wchar_t* entryPointArgs, int maxContextSwitch ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock ref; + CLR_RT_Thread* thMain = NULL; + + + if(NANOCLR_INDEX_IS_INVALID(g_CLR_RT_TypeSystem.m_entryPoint)) + { +#if !defined(BUILD_RTM) || defined(_WIN32) + CLR_Debug::Printf( "Cannot find any entrypoint!\r\n" ); +#endif + NANOCLR_SET_AND_LEAVE(CLR_E_ENTRYPOINT_NOT_FOUND); + } + + NANOCLR_CHECK_HRESULT(WaitForDebugger()); + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + CLR_EE_DBG_SET_MASK(StateProgramRunning,StateMask); +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Delegate::CreateInstance( ref, g_CLR_RT_TypeSystem.m_entryPoint, NULL )); + + { + CLR_RT_ProtectFromGC gc( ref ); + + NANOCLR_CHECK_HRESULT(NewThread( thMain, ref.DereferenceDelegate(), ThreadPriority::Normal, -1 )); + } + + { + CLR_RT_StackFrame* stack = thMain->CurrentFrame(); + + if(stack->m_call.m_target->numArgs > 0) + { + //Main entrypoint takes an optional String[] parameter. + //Set the arg to NULL, if that's the case. + + #if defined(WIN32) + if(entryPointArgs != NULL) + { + NANOCLR_CHECK_HRESULT(CreateEntryPointArgs( stack->m_arguments[ 0 ], entryPointArgs )); + } + else + #else + (void)entryPointArgs; + #endif + { + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( stack->m_arguments[ 0 ], 0, g_CLR_RT_WellKnownTypes.m_String )); + } + } + } + + //To debug static constructors, the thread should be created after the entrypoint thread. + NANOCLR_CHECK_HRESULT(WaitForDebugger()); + + // m_cctorThread is NULL before call and inialized by the SpawnStaticConstructor + SpawnStaticConstructor( m_cctorThread ); + + + while(true) + { + HRESULT hr2 = ScheduleThreads( maxContextSwitch ); NANOCLR_CHECK_HRESULT(hr2); + + if(CLR_EE_DBG_IS( RebootPending ) || CLR_EE_DBG_IS( ExitPending ) || CLR_EE_REBOOT_IS(ClrOnly)) + { + NANOCLR_SET_AND_LEAVE(S_FALSE); + } + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(CLR_EE_DBG_IS( Stopped )) + { + CLR_RT_ExecutionEngine::ExecutionConstraint_Suspend(); + + NANOCLR_CHECK_HRESULT(WaitForDebugger()); + + CLR_RT_ExecutionEngine::ExecutionConstraint_Resume(); + } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + if(CLR_EE_IS(Compaction_Pending)) + { + PerformHeapCompaction(); + _ASSERTE(FIMPLIES(CLR_EE_DBG_IS_NOT(NoCompaction), CLR_EE_IS_NOT(Compaction_Pending))); + } + + if(hr2 == CLR_S_NO_READY_THREADS) + { + WaitForActivity(); + } + else if(hr2 == CLR_S_QUANTUM_EXPIRED) + { +#if !defined(BUILD_RTM) || defined(_WIN32) + if(m_fPerformGarbageCollection) + { +#if defined(NANOCLR_GC_VERBOSE) + if(s_CLR_RT_fTrace_GC >= c_CLR_RT_Trace_Info) + { + CLR_Debug::Printf( " Memory: Forcing GC.\r\n" ); + } +#endif + PerformGarbageCollection(); + +#if defined(NANOCLR_GC_VERBOSE) + if(s_CLR_RT_fTrace_Memory > c_CLR_RT_Trace_Info) + { + CLR_UINT32 inUse = g_CLR_RT_GarbageCollector.m_totalBytes - g_CLR_RT_GarbageCollector.m_freeBytes; + + CLR_Debug::Printf( " Memory: INUSE: %d\r\n", (int)inUse ); + } +#endif + } +#endif + } + else + { + break; + } + } + + NANOCLR_CLEANUP(); + +#if defined(NANOCLR_PROFILE_NEW) + /* g_CLR_RT_ExecutionEngine.Cleanup() gets called too late to flush things out on the emulator since it + * only gets called when the finalizer dealing with the managed half of the emulator runs. + */ + g_CLR_PRF_Profiler.Stream_Flush(); +#endif + +#if defined(WIN32) +#if defined(NANOCLR_PROFILE_NEW) + if(CLR_EE_PRF_IS( Enabled )) + { + //Clients do not get all the messages they want if a program happens to end and the emulator terminates before + //the pipe can be read; furthermore the emulator must be able to persist until all required data is requested. + CLR_EE_DBG_SET(Stopped); + } +#endif + + //By skipping the whole CLRStartup routine, the Monitor_Program_Exit message never gets sent to clients. + CLR_EE_DBG_EVENT_BROADCAST(CLR_DBG_Commands::c_Monitor_ProgramExit,0,NULL,WP_Flags_c_NonCritical); + WaitForDebugger(); +#endif + + NANOCLR_CLEANUP_END(); +} + +bool CLR_RT_ExecutionEngine::EnsureSystemThread( CLR_RT_Thread*& thread, int priority ) +{ + NATIVE_PROFILE_CLR_CORE(); + + if(thread == NULL) + { + return SUCCEEDED(NewThread( thread, NULL, priority, -1, CLR_RT_Thread::TH_F_System )); + } + else + { + return thread->CanThreadBeReused(); + } +} + +void CLR_RT_ExecutionEngine::SpawnTimer() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Timer,timer,m_timers) + { + if(timer->m_flags & CLR_RT_HeapBlock_Timer::c_Triggered) + { + if(EnsureSystemThread( m_timerThread, ThreadPriority::Normal )) + { + //only fire one timer at a time + + timer->SpawnTimer( m_timerThread ); + + //put at the back of the queue to allow for fairness of the timers. + m_timers.LinkAtBack( timer ); + } + break; + } + } + NANOCLR_FOREACH_NODE_END(); +} + +void CLR_RT_ExecutionEngine::StaticConstructorTerminationCallback( void* arg ) +{ + (void)arg; + + NATIVE_PROFILE_CLR_CORE(); + g_CLR_RT_ExecutionEngine.SpawnStaticConstructor( g_CLR_RT_ExecutionEngine.m_cctorThread ); +} + +#if defined(NANOCLR_APPDOMAINS) +bool CLR_RT_ExecutionEngine::SpawnStaticConstructorHelper( CLR_RT_AppDomain* appDomain, CLR_RT_AppDomainAssembly* appDomainAssembly, const CLR_RT_MethodDef_Index& idx ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_MethodDef_Index idxNext; + + _ASSERTE(m_cctorThread != NULL); + //_ASSERTE(m_cctorThread->CanThreadBeReused()); + + idxNext.m_data = idx.m_data; + + _ASSERTE(appDomainAssembly != NULL); + + //find next method with static constructor + if(appDomainAssembly->m_assembly->FindNextStaticConstructor( idxNext )) + { + CLR_RT_HeapBlock_Delegate* dlg; + CLR_RT_HeapBlock refDlg; refDlg.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc( refDlg ); + + if(SUCCEEDED(CLR_RT_HeapBlock_Delegate::CreateInstance( refDlg, idxNext, NULL ))) + { + dlg = refDlg.DereferenceDelegate(); + dlg->m_appDomain = appDomain; + + if(SUCCEEDED(m_cctorThread->PushThreadProcDelegate( dlg ))) + { + m_cctorThread->m_terminationCallback = CLR_RT_ExecutionEngine::StaticConstructorTerminationCallback; + + return true; + } + } + } + + appDomainAssembly->m_flags |= CLR_RT_AppDomainAssembly::StaticConstructorsExecuted; + return false; +} + +void CLR_RT_ExecutionEngine::SpawnStaticConstructor( CLR_RT_Thread *&pCctorThread ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock_Delegate* dlg = NULL; + + if(!EnsureSystemThread(pCctorThread, ThreadPriority::System_Highest )) + return; + + dlg = pCctorThread->m_dlg; + + if(dlg != NULL) + { + CLR_RT_AppDomainAssembly* appDomainAssembly; + CLR_RT_MethodDef_Index idx = dlg->DelegateFtn(); + CLR_RT_MethodDef_Instance inst; + + //Find next static constructor for given idx + _ASSERTE(NANOCLR_INDEX_IS_VALID(idx)); + _SIDE_ASSERTE(inst.InitializeFromIndex( idx )); + + appDomainAssembly = dlg->m_appDomain->FindAppDomainAssembly( inst.m_assm ); + + _ASSERTE(appDomainAssembly != NULL); + _ASSERTE(appDomainAssembly->m_assembly == inst.m_assm ); + + //This is ok if idx is no longer valid. SpawnStaticConstructorHelper will call FindNextStaticConstructor + //which will fail + idx.m_data++; + + //This is not the first static constructor run in this appDomain + if(SpawnStaticConstructorHelper( dlg->m_appDomain, appDomainAssembly, idx )) + return; + } + + //first, find the AppDomainAssembly to run. (what about appdomains!!!) + NANOCLR_FOREACH_NODE(CLR_RT_AppDomain,appDomain,g_CLR_RT_ExecutionEngine.m_appDomains) + { + NANOCLR_FOREACH_NODE(CLR_RT_AppDomainAssembly,appDomainAssembly,appDomain->m_appDomainAssemblies) + { + CLR_RT_Assembly* assembly = appDomainAssembly->m_assembly; + + //Find an AppDomainAssembly that does not have it's static constructor bit set... + if((appDomainAssembly->m_flags & CLR_RT_AppDomainAssembly::StaticConstructorsExecuted) == 0) + { + CLR_RT_MethodDef_Index idx; idx.Set( assembly->m_idx, 0 ); + +#ifdef DEBUG + + //Check that all dependent assemblies have had static constructors run. + CLR_RT_AssemblyRef_CrossReference* ar = assembly->m_pCrossReference_AssemblyRef; + for(int i=0; im_pTablesSize[ TBL_AssemblyRef ]; i++, ar++) + { + CLR_RT_AppDomainAssembly* appDomainAssemblyRef = appDomain->FindAppDomainAssembly(ar->m_target); + + _ASSERTE(appDomainAssemblyRef != NULL); + _ASSERTE(appDomainAssemblyRef->m_flags & CLR_RT_AppDomainAssembly::StaticConstructorsExecuted); + } +#endif + + + if(SpawnStaticConstructorHelper( appDomain, appDomainAssembly, idx )) + return; + } + } + NANOCLR_FOREACH_NODE_END(); + } + NANOCLR_FOREACH_NODE_END(); + + + // No more static constructors needed... + // Perform 1 action: + // 1. Destroy constructor thread. + pCctorThread->DestroyInstance(); +} +#else //NANOCLR_APPDOMAINS + +bool CLR_RT_ExecutionEngine::SpawnStaticConstructorHelper( CLR_RT_Assembly* assembly, const CLR_RT_MethodDef_Index& idx ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_MethodDef_Index idxNext; + + _ASSERTE(m_cctorThread != NULL); + _ASSERTE(m_cctorThread->CanThreadBeReused()); + + idxNext.m_data = idx.m_data; + + _ASSERTE(assembly != NULL); + + //find next method with static constructor + if(assembly->FindNextStaticConstructor( idxNext )) + { + CLR_RT_HeapBlock_Delegate* dlg; + CLR_RT_HeapBlock refDlg; refDlg.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc( refDlg ); + + if(SUCCEEDED(CLR_RT_HeapBlock_Delegate::CreateInstance( refDlg, idxNext, NULL ))) + { + dlg = refDlg.DereferenceDelegate(); + + if(SUCCEEDED(m_cctorThread->PushThreadProcDelegate( dlg ))) + { + m_cctorThread->m_terminationCallback = CLR_RT_ExecutionEngine::StaticConstructorTerminationCallback; + + return true; + } + } + } + + assembly->m_flags |= CLR_RT_Assembly::StaticConstructorsExecuted; + return false; +} + +void CLR_RT_ExecutionEngine::SpawnStaticConstructor( CLR_RT_Thread *&pCctorThread ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock_Delegate* dlg = NULL; + + if(!EnsureSystemThread(pCctorThread, ThreadPriority::System_Highest)) + return; + + dlg = pCctorThread->m_dlg; + + if(dlg != NULL) + { + CLR_RT_MethodDef_Index idx = dlg->DelegateFtn(); + CLR_RT_MethodDef_Instance inst; + + //Find next static constructor for given idx + _ASSERTE(NANOCLR_INDEX_IS_VALID(idx)); + _SIDE_ASSERTE(inst.InitializeFromIndex( idx )); + + //This is ok if idx is no longer valid. SpawnStaticConstructorHelper will call FindNextStaticConstructor + //which will fail + idx.m_data++; + + if(SpawnStaticConstructorHelper( inst.m_assm, idx )) + return; + } + + //first, find the AppDomainAssembly to run. (what about appdomains!!!) + NANOCLR_FOREACH_ASSEMBLY(g_CLR_RT_TypeSystem) + { + //Find an AppDomainAssembly that does not have it's static constructor bit set... + if((pASSM->m_flags & CLR_RT_Assembly::StaticConstructorsExecuted) == 0) + { + CLR_RT_MethodDef_Index idx; idx.Set( pASSM->m_idx, 0 ); + bool fDepedenciesRun = true; + + //Check that all dependent assemblies have had static constructors run. + CLR_RT_AssemblyRef_CrossReference* ar = pASSM->m_pCrossReference_AssemblyRef; + for(int i=0; im_pTablesSize[ TBL_AssemblyRef ]; i++, ar++) + { + if((ar->m_target->m_flags & CLR_RT_Assembly::StaticConstructorsExecuted) == 0) + { + fDepedenciesRun = true; + break; + } + } + + if(fDepedenciesRun && SpawnStaticConstructorHelper( pASSM, idx )) + return; + } + } + NANOCLR_FOREACH_ASSEMBLY_END(); + + //no more static constructors needed... + pCctorThread->DestroyInstance(); +} +#endif //NANOCLR_APPDOMAINS + +void CLR_RT_ExecutionEngine::FinalizerTerminationCallback(void* arg) +{ + (void)arg; + + NATIVE_PROFILE_CLR_CORE(); + g_CLR_RT_ExecutionEngine.SpawnFinalizer(); +} + +void CLR_RT_ExecutionEngine::SpawnFinalizer() +{ + NATIVE_PROFILE_CLR_CORE(); + + CLR_RT_HeapBlock_Finalizer* fin = (CLR_RT_HeapBlock_Finalizer*)m_finalizersPending.FirstNode(); + if(fin->Next() != NULL) + { + CLR_RT_HeapBlock delegate; delegate.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc( delegate ); + +#if defined(NANOCLR_APPDOMAINS) + (void)SetCurrentAppDomain( fin->m_appDomain ); +#endif + + if(EnsureSystemThread(m_finalizerThread, ThreadPriority::BelowNormal)) + { + if(SUCCEEDED(CLR_RT_HeapBlock_Delegate::CreateInstance( delegate, fin->m_md, NULL ))) + { + CLR_RT_HeapBlock_Delegate* dlg = delegate.DereferenceDelegate(); + + dlg->m_object.SetObjectReference( fin->m_object ); + + if(SUCCEEDED(m_finalizerThread->PushThreadProcDelegate( dlg ))) + { + g_CLR_RT_EventCache.Append_Node( fin ); + m_finalizerThread->m_terminationCallback = CLR_RT_ExecutionEngine::FinalizerTerminationCallback; + } + } + } + } +} + +void CLR_RT_ExecutionEngine::AdjustExecutionCounter( CLR_RT_DblLinkedList &threadList, int iUpdateValue ) + +{ // Iterate over threads in increase executioin counter by iUpdateValue + NANOCLR_FOREACH_NODE(CLR_RT_Thread,pThread,threadList) + { + pThread->m_executionCounter += iUpdateValue; + // Update m_executionCounter if thread is too behind of m_GlobalExecutionCounter + pThread->BringExecCounterToDate( m_GlobalExecutionCounter, pThread->GetQuantumDebit() ); + } + NANOCLR_FOREACH_NODE_END() +} + +void CLR_RT_ExecutionEngine::UpdateToLowestExecutionCounter( CLR_RT_Thread *pThread ) const +{ + // Set the m_executionCounter in thread to lowest value among ready threads. + // Thus it will be executed last. + pThread->m_executionCounter = m_GlobalExecutionCounter - 1; +} + +void CLR_RT_ExecutionEngine::RetrieveCurrentMethod( CLR_UINT32& assmIdx, CLR_UINT32& methodIdx ) +{ + assmIdx = 0; + methodIdx = 0; + + if(m_currentThread != NULL) + { + CLR_RT_StackFrame* stack = m_currentThread->CurrentFrame(); + + if(stack) + { + assmIdx = stack->m_call.Assembly(); + methodIdx = stack->m_call.Method (); + } + } +} + +void CLR_RetrieveCurrentMethod( CLR_UINT32 & assmIdx, CLR_UINT32 & methodIdx ) +{ + g_CLR_RT_ExecutionEngine.RetrieveCurrentMethod( assmIdx, methodIdx ); +} + +void CLR_SoftReboot() +{ + CLR_EE_DBG_SET( RebootPending ); +} + +void CLR_DebuggerBreak() +{ + if(g_CLR_RT_ExecutionEngine.m_currentThread != NULL) + { + CLR_RT_HeapBlock *obj = g_CLR_RT_ExecutionEngine.m_currentThread->m_currentException.Dereference(); + + /// + /// Only inject the exception once -- if the dereference is not null then the exception is already set on the current thread + /// + if(obj == NULL) + { + Library_corlib_native_System_Exception::CreateInstance( g_CLR_RT_ExecutionEngine.m_currentThread->m_currentException, g_CLR_RT_WellKnownTypes.m_WatchdogException, CLR_E_WATCHDOG_TIMEOUT, g_CLR_RT_ExecutionEngine.m_currentThread->CurrentFrame() ); + } + } +} + +HRESULT CLR_RT_ExecutionEngine::ScheduleThreads( int maxContextSwitch ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + +#if defined(NANOCLR_APPDOMAINS) + CLR_RT_AppDomain* appDomainSav = g_CLR_RT_ExecutionEngine.GetCurrentAppDomain(); +#endif + + // We run threads based on the m_executionCounter. + // The thread with highest m_executionCounter is chosen for execution. + // The highest value of m_executionCounter of any thread is stored in m_GlobalExecutionCounter + // We need to check that m_GlobalExecutionCounter does not underflow ( runs below - -2147483647 ) This would be very rare condition, but it may happen. + // We put threshold at - 0x40000000 + if ( m_GlobalExecutionCounter < -EXECUTION_COUNTER_MAXIMUM ) + { // Iterate over threads in all queues and bump the execution counter by MAX_EXECUTION_COUNTER_ADJUSTMENT + + m_GlobalExecutionCounter += EXECUTION_COUNTER_ADJUSTMENT; + + // For each list of threads runs over it and updates execution counter. + // AdjustExecutionCounter gets const & to list of threads. + // List of threads is not modified, but m_executionCounter is bumped up in each thread. + + AdjustExecutionCounter( m_threadsReady, EXECUTION_COUNTER_ADJUSTMENT ); + AdjustExecutionCounter( m_threadsWaiting, EXECUTION_COUNTER_ADJUSTMENT ); + AdjustExecutionCounter( m_threadsZombie, EXECUTION_COUNTER_ADJUSTMENT ); + } + + while(maxContextSwitch-- > 0) + { + +#if defined(WIN32) + if(HAL_Windows_IsShutdownPending()) + { + NANOCLR_SET_AND_LEAVE(CLR_S_NO_THREADS); + } +#endif + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(CLR_EE_DBG_IS( Stopped )) + { + NANOCLR_SET_AND_LEAVE(CLR_S_NO_READY_THREADS); + } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + CLR_RT_Thread* th = NULL; + + // If a static constructor thread exists, we should be running it. + // What about func-eval? + if (m_cctorThread == NULL) + { + // This is normal case execution. Looks for first ready thread. + th = (CLR_RT_Thread*)m_threadsReady.FirstNode(); + } + else //If a static constructor thread exists, we should be running it. + { + // This is special case executed during initialization of static constructors. + if (m_cctorThread->m_status == CLR_RT_Thread::TH_S_Ready && !(m_cctorThread->m_flags & CLR_RT_Thread::TH_F_Suspended)) + { + th = m_cctorThread; + } + else + { + // The m_cctorThread is exists, but not ready - means entered blocking call. + // We do not want to preempt constructor thread, so stay idle. + NANOCLR_SET_AND_LEAVE(CLR_S_NO_READY_THREADS); + } + } + + + + + // If th->Next() is NULL, then there are no Ready to run threads in the system. + // In this case we spawn finalizer and make finalizer thread as ready one. + if(th->Next() == NULL) + { + g_CLR_RT_ExecutionEngine.SpawnFinalizer(); + + // Now finalizer thread might be in ready state if there are object that need call to finalizer. + // th might point to finilizer thread. + th = (CLR_RT_Thread*)m_threadsReady.FirstNode(); + + //Thread create can cause stopping debugging event +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(CLR_EE_DBG_IS(Stopped)) + { + NANOCLR_SET_AND_LEAVE(CLR_S_NO_READY_THREADS); + } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + } + + // If there is ready thread - decrease m_executionCounter for this (th) thread. + if( th->Next() != NULL ) + { + // The value to update m_executionCounter for each run. See comment for GetQuantumDebit for possible values + int debitForEachRun = th->GetQuantumDebit(); + + // If thread is way too much behind on its execution, we cutt off extra credit. + // We garantee the thread will not be scheduled more than 4 consequitive times. + th->BringExecCounterToDate( m_GlobalExecutionCounter, debitForEachRun ); + + // Substruct the execution counter by debit value ( for executing thread ) + th->m_executionCounter -= debitForEachRun; + + // Keep the track of lowest execution counter. + if ( th->m_executionCounter < m_GlobalExecutionCounter ) + { + m_GlobalExecutionCounter = th->m_executionCounter; + } + } + else + { + if(m_threadsWaiting.IsEmpty()) + { + NANOCLR_SET_AND_LEAVE(CLR_S_NO_THREADS); + } + + NANOCLR_SET_AND_LEAVE(CLR_S_NO_READY_THREADS); + } + + Watchdog_Reset(); + + { + // Runs the tread until expiration of its quantum or until thread is blocked. + hr = th->Execute(); + } + + if(FAILED(hr)) + { + switch(hr) + { + case CLR_E_RESCHEDULE: + break; + + case CLR_E_THREAD_WAITING: + th->m_status = CLR_RT_Thread::TH_S_Waiting; + break; + + default: + th->m_status = CLR_RT_Thread::TH_S_Terminated; + break; + } + } + + Watchdog_Reset(); + + PutInProperList( th ); + + (void)ProcessTimer(); + } + + NANOCLR_SET_AND_LEAVE(CLR_S_QUANTUM_EXPIRED); + + NANOCLR_CLEANUP(); + +#if defined(NANOCLR_APPDOMAINS) + + if(CLR_EE_IS( UnloadingAppDomain )) + { + if(TryToUnloadAppDomains()) + { + //If we are successful in unloading an AppDomain, return CLR_S_QUANTUM_EXPIRED + //to cause ScheduleThreads to be called again. This allows the somewhat expensive operation + //of trying to unload an AppDomain once every ScheduleThread call, rather than once every context switch + + hr = CLR_S_QUANTUM_EXPIRED; + } + } + + g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( appDomainSav ); +#endif + + NANOCLR_CLEANUP_END(); +} + +CLR_UINT32 CLR_RT_ExecutionEngine::WaitForActivity() +{ + NATIVE_PROFILE_CLR_CORE(); + + CLR_INT64 timeoutMin = ProcessTimer(); + + if(m_threadsReady.IsEmpty() == false) return 0; // Someone woke up... + + if(timeoutMin > 0LL) + { + NANOCLR_FOREACH_NODE(CLR_RT_Thread,th,m_threadsWaiting) + { + if((th->m_waitForEvents & c_Event_IdleCPU) != 0 && th->m_waitForEvents_IdleTimeWorkItem < timeoutMin) + { + th->m_waitForEvents_IdleTimeWorkItem = TIMEOUT_ZERO; + + th->Restart( true ); + + return SYSTEM_EVENT_FLAG_ALL; // Someone woke up... + } + } + NANOCLR_FOREACH_NODE_END(); + + return WaitForActivity( SLEEP_LEVEL__SLEEP, g_CLR_HW_Hardware.m_wakeupEvents, timeoutMin ); + } + + return 0; +} + +CLR_UINT32 CLR_RT_ExecutionEngine::WaitForActivity( CLR_UINT32 powerLevel, CLR_UINT32 events, CLR_INT64 timeout_ms ) +{ + NATIVE_PROFILE_CLR_CORE(); + + if(powerLevel != PowerLevel__Active) + { + return WaitSystemEvents( powerLevel, events, timeout_ms ); + } + + return 0; +} + +//--// + +void CLR_RT_ExecutionEngine::PutInProperList( CLR_RT_Thread* th ) +{ + NATIVE_PROFILE_CLR_CORE(); + switch(th->m_status) + { + case CLR_RT_Thread::TH_S_Ready: + if((th->m_flags & CLR_RT_Thread::TH_F_Suspended) == 0) + { + InsertThreadRoundRobin( m_threadsReady, th ); + break; + } + // + // Fall-through... + // + case CLR_RT_Thread::TH_S_Waiting: + m_threadsWaiting.LinkAtBack( th ); + break; + + case CLR_RT_Thread::TH_S_Terminated: + th->Passivate(); + break; + + case CLR_RT_Thread::TH_S_Unstarted: + m_threadsZombie.LinkAtFront( th ); + break; + } +} + +void CLR_RT_ExecutionEngine::AbortAllThreads( CLR_RT_DblLinkedList& threads ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_NODE(CLR_RT_Thread,th,threads) + { + if((th->m_flags & CLR_RT_Thread::TH_F_Aborted) == 0) + { + th->Abort(); + + NANOCLR_FOREACH_NODE_RESTART(CLR_RT_Thread,th,threads); + } + } + NANOCLR_FOREACH_NODE_END(); +} + +void CLR_RT_ExecutionEngine::ReleaseAllThreads( CLR_RT_DblLinkedList& threads ) +{ + NATIVE_PROFILE_CLR_CORE(); + while(true) + { + CLR_RT_Thread* th = (CLR_RT_Thread*)threads.ExtractFirstNode(); if(!th) break; + + th->DestroyInstance(); + } +} + +void CLR_RT_ExecutionEngine::InsertThreadRoundRobin( CLR_RT_DblLinkedList& threads, CLR_RT_Thread* thTarget ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_Thread* th; + + thTarget->Unlink(); + + if(threads.IsEmpty()) + { + th = (CLR_RT_Thread*)threads.Tail(); + } + else + { + int priTarget = thTarget->GetExecutionCounter(); + + NANOCLR_FOREACH_NODE__NODECL(CLR_RT_Thread,th,threads) + { + if(th->GetExecutionCounter() < priTarget) break; + } + NANOCLR_FOREACH_NODE_END(); + } + + thTarget->m_waitForEvents = 0; + thTarget->m_waitForEvents_Timeout = TIMEOUT_INFINITE; + + if(thTarget->m_waitForObject != NULL) + { + g_CLR_RT_EventCache.Append_Node( thTarget->m_waitForObject ); + + thTarget->m_waitForObject = NULL; + } + + threads.InsertBeforeNode( th, thTarget ); +} + +//--// + +HRESULT CLR_RT_ExecutionEngine::NewThread( CLR_RT_Thread*& thRes, CLR_RT_HeapBlock_Delegate* pDelegate, int priority, CLR_INT32 id, CLR_UINT32 flags ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_CHECK_HRESULT(CLR_RT_Thread::CreateInstance( id != -1 ? id : ++m_lastPid, pDelegate, priority, thRes, flags )); + + PutInProperList( thRes ); + + NANOCLR_CLEANUP(); + + if(FAILED(hr)) + { + if(thRes) + { + thRes->DestroyInstance(); + + thRes = NULL; + } + } + + NANOCLR_CLEANUP_END(); +} + +CLR_INT32 CLR_RT_ExecutionEngine::GetNextThreadId() +{ + return ++m_lastPid; +} + +//--// + +CLR_RT_HeapBlock* CLR_RT_ExecutionEngine::ExtractHeapBlocksForArray( CLR_RT_TypeDef_Instance& inst, CLR_UINT32 length, const CLR_RT_ReflectionDef_Index& reflex ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_DataType dt = (CLR_DataType)inst.m_target->dataType; + const CLR_RT_DataTypeLookup& dtl = c_CLR_RT_DataTypeLookup[ dt ]; + + CLR_UINT32 totLength = (CLR_UINT32)(sizeof(CLR_RT_HeapBlock_Array) + length * dtl.m_sizeInBytes); + CLR_UINT32 lengthHB = CONVERTFROMSIZETOHEAPBLOCKS(totLength); + + if(lengthHB > CLR_RT_HeapBlock::HB_MaxSize) return NULL; + + CLR_RT_HeapBlock_Array* pArray = (CLR_RT_HeapBlock_Array*)ExtractHeapBlocks( m_heap, DATATYPE_SZARRAY, 0, lengthHB ); + + if(pArray) + { + pArray->ReflectionData() = reflex; + pArray->m_numOfElements = length; + + pArray->m_typeOfElement = dt; + pArray->m_sizeOfElement = dtl.m_sizeInBytes; + pArray->m_fReference = (dtl.m_flags & CLR_RT_DataTypeLookup::c_Numeric) == 0; + +#if defined(NANOCLR_PROFILE_NEW_ALLOCATIONS) + g_CLR_PRF_Profiler.TrackObjectCreation( pArray ); +#endif + } + + return pArray; +} + +CLR_RT_HeapBlock* CLR_RT_ExecutionEngine::ExtractHeapBlocksForClassOrValueTypes( CLR_UINT32 dataType, CLR_UINT32 flags, const CLR_RT_TypeDef_Index& cls, CLR_UINT32 length ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(length > CLR_RT_HeapBlock::HB_MaxSize) return NULL; + + _ASSERTE(dataType == DATATYPE_CLASS || dataType == DATATYPE_VALUETYPE); + + flags = flags | CLR_RT_HeapBlock::HB_InitializeToZero; + CLR_RT_HeapBlock* hb = ExtractHeapBlocks( m_heap, dataType, flags, length ); + + if(hb) + { + hb->SetObjectCls(cls); + +#if defined(NANOCLR_PROFILE_NEW_ALLOCATIONS) + g_CLR_PRF_Profiler.TrackObjectCreation( hb ); +#endif + } + + return hb; +} + +CLR_RT_HeapBlock* CLR_RT_ExecutionEngine::ExtractHeapBytesForObjects( CLR_UINT32 dataType, CLR_UINT32 flags, CLR_UINT32 length ) +{ + NATIVE_PROFILE_CLR_CORE(); + return ExtractHeapBlocksForObjects( dataType, flags, CONVERTFROMSIZETOHEAPBLOCKS(length) ); +} + +CLR_RT_HeapBlock* CLR_RT_ExecutionEngine::ExtractHeapBlocksForObjects( CLR_UINT32 dataType, CLR_UINT32 flags, CLR_UINT32 length ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(length > CLR_RT_HeapBlock::HB_MaxSize) return NULL; + + _ASSERTE(dataType != DATATYPE_CLASS && dataType != DATATYPE_VALUETYPE && dataType != DATATYPE_SZARRAY); + + flags &= ~CLR_RT_HeapBlock::HB_Alive; + + CLR_RT_HeapBlock* hb = ExtractHeapBlocks( m_heap, dataType, flags, length ); + +#if defined(NANOCLR_PROFILE_NEW_ALLOCATIONS) + if(hb) + { + g_CLR_PRF_Profiler.TrackObjectCreation( hb ); + } +#endif + + return hb; +} + +//--// + +CLR_RT_HeapBlock_Node* CLR_RT_ExecutionEngine::ExtractHeapBlocksForEvents( CLR_UINT32 dataType, CLR_UINT32 flags, CLR_UINT32 length ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(length > CLR_RT_HeapBlock::HB_MaxSize) return NULL; + + flags |= CLR_RT_HeapBlock::HB_Alive | CLR_RT_HeapBlock::HB_Event; + + CLR_RT_HeapBlock_Node* hb = (CLR_RT_HeapBlock_Node*)ExtractHeapBlocks( m_heap, dataType, flags, length ); + + if(hb) + { + hb->GenericNode_Initialize(); + +#if defined(NANOCLR_PROFILE_NEW_ALLOCATIONS) + g_CLR_PRF_Profiler.TrackObjectCreation( hb ); +#endif + } + + return hb; +} + +CLR_RT_HeapBlock* CLR_RT_ExecutionEngine::ExtractHeapBlocks( CLR_RT_DblLinkedList& heap, CLR_UINT32 dataType, CLR_UINT32 flags, CLR_UINT32 length ) +{ + NATIVE_PROFILE_CLR_CORE(); +#if !defined(BUILD_RTM) + if(m_heapState == c_HeapState_UnderGC && ((flags & CLR_RT_HeapBlock::HB_SpecialGCAllocation) == 0)) + { + CLR_Debug::Printf( "Internal error: call to memory allocation during garbage collection!!!\r\n" ); + + // Getting here during a GC is possible, since the watchdog ISR may now require + // dynamic memory allocation for logging. Returning NULL means the watchdog log will + // be lost, but without major restructuring there is not much we can do. + return NULL; + } +#endif + +#if defined(NANOCLR_FORCE_GC_BEFORE_EVERY_ALLOCATION) + if(m_heapState != c_HeapState_UnderGC) + { + g_CLR_RT_EventCache.EventCache_Cleanup(); + PerformGarbageCollection(); + } +#endif + + for(int phase=0; ; phase++) + { + { + CLR_RT_HeapBlock* hb; + + if(flags & CLR_RT_HeapBlock::HB_Event) + { + NANOCLR_FOREACH_NODE_BACKWARD(CLR_RT_HeapCluster,hc,heap) + { + hb = hc->ExtractBlocks( dataType, flags, length ); + if(hb) + { + return hb; + } + } + NANOCLR_FOREACH_NODE_BACKWARD_END(); + } + else + { + if(m_lastHcUsed != NULL) + { + hb = m_lastHcUsed->ExtractBlocks( dataType, flags, length ); + if(hb) + { + return hb; + } + } + + NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster,hc,heap) + { + hb = hc->ExtractBlocks( dataType, flags, length ); + if(hb) + { +#if defined(NANOCLR_GC_VERBOSE) + if(s_CLR_RT_fTrace_Memory >= c_CLR_RT_Trace_Info) + { + if(phase != 0) + { + CLR_Debug::Printf( "ExtractHeapBlocks succeeded at phase %d\r\n", phase ); + } + } +#endif + m_lastHcUsed = hc; + return hb; + } + } + NANOCLR_FOREACH_NODE_END(); + } + + m_lastHcUsed = NULL; + } + + if(flags & CLR_RT_HeapBlock::HB_NoGcOnFailedAllocation) + { + return NULL; + } + + switch(phase) + { + case 0: +#if defined(NANOCLR_GC_VERBOSE) + if(s_CLR_RT_fTrace_Memory >= c_CLR_RT_Trace_Info) + { + CLR_Debug::Printf( " Memory: ExtractHeapBlocks: %d bytes needed.\r\n", length * sizeof(CLR_RT_HeapBlock) ); + } +#endif + + PerformGarbageCollection(); + + break; + + default: // Total failure... +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Failed allocation for %d blocks, %d bytes\r\n\r\n", length, length * sizeof(CLR_RT_HeapBlock) ); +#endif + if(g_CLR_RT_GarbageCollector.m_freeBytes >= (length * sizeof(CLR_RT_HeapBlock))) + { + + //A compaction probably would have saved this OOM + //Compaction will occur for Bitmaps, Arrays, etc. if this function returns NULL, so lets not + //through an assert here + + //Throw the OOM, and schedule a compaction at a safe point + CLR_EE_SET( Compaction_Pending ); + } + + return NULL; + } + } +} + + +CLR_RT_HeapBlock* CLR_RT_ExecutionEngine::AccessStaticField( const CLR_RT_FieldDef_Index& fd ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_FieldDef_Instance inst; + + if(inst.InitializeFromIndex( fd ) && inst.m_target->flags & CLR_RECORD_FIELDDEF::FD_Static) + { +#if defined(NANOCLR_APPDOMAINS) + { + CLR_RT_AppDomainAssembly* appDomainAssembly = g_CLR_RT_ExecutionEngine.GetCurrentAppDomain()->FindAppDomainAssembly( inst.m_assm ); + + if(appDomainAssembly) + { + return &appDomainAssembly->m_pStaticFields[ inst.CrossReference().m_offset ]; + } + } +#else + return &inst.m_assm->m_pStaticFields[ inst.CrossReference().m_offset ]; +#endif + } + + return NULL; +} + +HRESULT CLR_RT_ExecutionEngine::InitializeReference( CLR_RT_HeapBlock& ref, CLR_RT_SignatureParser& parser ) +{ + NATIVE_PROFILE_CLR_CORE(); + // + // WARNING!!! + // + // If you change this method, change "CLR_RT_ExecutionEngine::InitializeLocals" too. + // + + NANOCLR_HEADER(); + + CLR_RT_SignatureParser::Element res; + CLR_DataType dt; + + NANOCLR_CHECK_HRESULT(parser.Advance( res )); + + dt = res.m_dt; + + if(res.m_levels > 0) // Array + { + dt = DATATYPE_OBJECT; + } + else + { + if(dt == DATATYPE_VALUETYPE) + { + CLR_RT_TypeDef_Instance inst; inst.InitializeFromIndex( res.m_cls ); + + if((inst.m_target->flags & CLR_RECORD_TYPEDEF::TD_Semantics_Mask) == CLR_RECORD_TYPEDEF::TD_Semantics_Enum) + { + dt = (CLR_DataType)inst.m_target->dataType; + } + else + { + NANOCLR_SET_AND_LEAVE(NewObject( ref, inst )); + } + } + else + { + if(c_CLR_RT_DataTypeLookup[ dt ].m_flags & CLR_RT_DataTypeLookup::c_Reference) + { + dt = DATATYPE_OBJECT; + } + } + } + + ref.SetDataId( CLR_RT_HEAPBLOCK_RAW_ID( dt, CLR_RT_HeapBlock::HB_Alive, 1 ) ); + ref.ClearData(); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_ExecutionEngine::InitializeReference( CLR_RT_HeapBlock& ref, const CLR_RECORD_FIELDDEF* target, CLR_RT_Assembly* assm ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_SignatureParser parser; parser.Initialize_FieldDef( assm, target ); + + NANOCLR_SET_AND_LEAVE(InitializeReference( ref, parser )); + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT CLR_RT_ExecutionEngine::InitializeLocals( CLR_RT_HeapBlock* locals, CLR_RT_Assembly* assm, const CLR_RECORD_METHODDEF* md ) +{ + NATIVE_PROFILE_CLR_CORE(); + // + // WARNING!!! + // + // This method is a shortcut for the following code: + // + + NANOCLR_HEADER(); + + CLR_PMETADATA sig = assm->GetSignature( md->locals ); + CLR_UINT32 count = md->numLocals; + bool fZeroed = false; + + while(count) + { + CLR_DataType dt = DATATYPE_VOID; + CLR_RT_TypeDef_Index cls; + CLR_UINT32 levels = 0; + CLR_DataType dtModifier = DATATYPE_VOID; + + while(true) + { + dt = CLR_UncompressElementType( sig ); + + switch(dt) + { + case DATATYPE_TYPE_PINNED : + dtModifier = DATATYPE_TYPE_PINNED; + break; + + // Array declared on stack .locals init [0] int16[] foo, + case DATATYPE_SZARRAY: + // Reference declared on stack - .locals init [1] int16& pinned pShort, + case DATATYPE_BYREF: + levels++; + break; + + case DATATYPE_CLASS: + case DATATYPE_VALUETYPE: + { + CLR_UINT32 tk = CLR_TkFromStream( sig ); + CLR_UINT32 idx = CLR_DataFromTk( tk ); + + switch(CLR_TypeFromTk( tk )) + { + case TBL_TypeSpec: + { + CLR_RT_SignatureParser sub; sub.Initialize_TypeSpec( assm, assm->GetTypeSpec( idx ) ); + CLR_RT_SignatureParser::Element res; + + NANOCLR_CHECK_HRESULT(sub.Advance( res )); + + cls = res.m_cls; + levels += res.m_levels; + } + break; + + case TBL_TypeRef: + cls = assm->m_pCrossReference_TypeRef[ idx ].m_target; + break; + + case TBL_TypeDef: + cls.Set( assm->m_idx, idx ); + break; + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + } + goto done; + + default: + { + const CLR_RT_TypeDef_Index* cls2 = c_CLR_RT_DataTypeLookup[ dt ].m_cls; + + if(cls2 == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + cls = *cls2; + } + goto done; + } + } + +done: + if(levels > 0) // Array or reference + { + locals->SetObjectReference( NULL ); + + // If local varialb has DATATYPE_TYPE_PINNED, we mark heap block as + if ( dtModifier == DATATYPE_TYPE_PINNED ) + { + locals->Pin(); + } + } + else + { + if(dt == DATATYPE_VALUETYPE) + { + CLR_RT_TypeDef_Instance inst; inst.InitializeFromIndex( cls ); + + if(inst.m_target->dataType != DATATYPE_VALUETYPE) + { + locals->SetDataId( CLR_RT_HEAPBLOCK_RAW_ID( inst.m_target->dataType, CLR_RT_HeapBlock::HB_Alive, 1 ) ); + locals->ClearData(); + } + else + { + // + // Before we allocate anything, we need to make sure the rest of the local variables are in a consistent state. + // + if(fZeroed == false) + { + fZeroed = true; + + CLR_RT_HeapBlock* ptr = locals; + CLR_RT_HeapBlock* ptrEnd = &locals[ count ]; + + do + { + ptr->SetDataId( CLR_RT_HEAPBLOCK_RAW_ID(DATATYPE_I4,0,1) ); + + } while(++ptr < ptrEnd); + } + + NANOCLR_CHECK_HRESULT(NewObject( *locals, inst )); + } + } + else + { + if(c_CLR_RT_DataTypeLookup[ dt ].m_flags & CLR_RT_DataTypeLookup::c_Reference) + { + dt = DATATYPE_OBJECT; + } + + locals->SetDataId( CLR_RT_HEAPBLOCK_RAW_ID(dt,CLR_RT_HeapBlock::HB_Alive,1) ); + locals->ClearData(); + } + } + + locals++; + count--; + } + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT CLR_RT_ExecutionEngine::NewObjectFromIndex( CLR_RT_HeapBlock& reference, const CLR_RT_TypeDef_Index& cls ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Instance inst; + + if(inst.InitializeFromIndex( cls ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + NANOCLR_SET_AND_LEAVE(NewObject( reference, inst )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_ExecutionEngine::NewObject( CLR_RT_HeapBlock& reference, const CLR_RT_TypeDef_Instance& inst ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + reference.SetObjectReference( NULL ); + + CLR_DataType dt = (CLR_DataType)inst.m_target->dataType; + + // + // You cannot create an array this way. + // + if(inst.m_data == g_CLR_RT_WellKnownTypes.m_Array.m_data) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + if((c_CLR_RT_DataTypeLookup[ dt ].m_flags & CLR_RT_DataTypeLookup::c_Reference) == 0) + { + reference.SetDataId( CLR_RT_HEAPBLOCK_RAW_ID(dt,0,1) ); + } + else + { + switch(dt) + { + case DATATYPE_STRING: + // + // Special case for strings. + // + break; + + case DATATYPE_WEAKCLASS: + { + CLR_RT_HeapBlock_WeakReference* weakref; + + // this used to be a call to CLR_RT_HeapBlock_WeakReference::CreateInstance + weakref = (CLR_RT_HeapBlock_WeakReference*)g_CLR_RT_ExecutionEngine.ExtractHeapBytesForObjects( DATATYPE_WEAKCLASS, CLR_RT_HeapBlock::HB_InitializeToZero, sizeof(*weakref) ); + CHECK_ALLOCATION(weakref); + + reference.SetObjectReference( weakref ); + } + break; + + case DATATYPE_CLASS: + case DATATYPE_VALUETYPE: + { + int clsFields = inst.m_target->iFields_Num; + int totFields = inst.CrossReference().m_totalFields + CLR_RT_HeapBlock::HB_Object_Fields_Offset; + CLR_RT_HeapBlock* obj = ExtractHeapBlocksForClassOrValueTypes( dt, 0, inst, totFields ); CHECK_ALLOCATION(obj); + + reference.SetObjectReference( obj ); + + { + const CLR_RECORD_FIELDDEF* target = NULL; + CLR_RT_Assembly* assm = NULL; + CLR_RT_TypeDef_Instance instSub = inst; + + + NANOCLR_CHECK_HRESULT(obj->SetObjectCls( inst )); + + // + // Initialize field types, from last to first. + // + // We do the decrement BEFORE the comparison because we want to stop short of the first field, the object descriptor (already initialized). + // + obj += totFields; + while(--totFields > 0) + { + while(clsFields == 0) + { + if(instSub.SwitchToParent() == false) NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + + clsFields = instSub.m_target->iFields_Num; + target = NULL; + } + + if(target == NULL) + { + assm = instSub.m_assm; + target = assm->GetFieldDef( instSub.m_target->iFields_First + clsFields ); + } + + obj--; target--; clsFields--; + + NANOCLR_CHECK_HRESULT(InitializeReference( *obj, target, assm )); + } + } + + if(inst.HasFinalizer()) + { + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Finalizer::CreateInstance( reference.Dereference(), inst )); + } + } + break; + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_ExecutionEngine::NewObject( CLR_RT_HeapBlock& reference, CLR_UINT32 tk, CLR_RT_Assembly* assm ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Instance res; + + if(res.ResolveToken( tk, assm ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + NANOCLR_CHECK_HRESULT(NewObjectFromIndex( reference, res )); + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT CLR_RT_ExecutionEngine::CloneObject( CLR_RT_HeapBlock& reference, const CLR_RT_HeapBlock& source ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + const CLR_RT_HeapBlock* obj = &source; + CLR_DataType dt; + + while(true) + { + dt = (CLR_DataType)obj->DataType(); + + if(dt == DATATYPE_BYREF || + dt == DATATYPE_OBJECT ) + { + obj = obj->Dereference(); FAULT_ON_NULL(obj); + } + else + { + break; + } + } + + switch(dt) + { + + case DATATYPE_VALUETYPE: + case DATATYPE_CLASS: + { + // + // Save the pointer to the object to clone, in case 'reference' and 'source' point to the same block. + // + CLR_RT_HeapBlock safeSource; safeSource.SetObjectReference( obj ); + CLR_RT_ProtectFromGC gc( safeSource ); + + NANOCLR_CHECK_HRESULT(NewObjectFromIndex( reference , obj->ObjectCls() )); + NANOCLR_CHECK_HRESULT(CopyValueType ( reference.Dereference(), obj )); + } + break; + + default: + if((c_CLR_RT_DataTypeLookup[ dt ].m_flags & CLR_RT_DataTypeLookup::c_OptimizedValueType) == 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + } + + // + // Non-reference type, straight copy. + // + reference.Assign( source ); + break; + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_ExecutionEngine::CopyValueType( CLR_RT_HeapBlock* destination, const CLR_RT_HeapBlock* source ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(destination != source) + { + const CLR_RT_TypeDef_Index& cls = source->ObjectCls(); + if(cls.m_data == destination->ObjectCls().m_data) + { + CLR_RT_TypeDef_Instance inst; inst.InitializeFromIndex( cls ); + CLR_UINT32 totFields = inst.CrossReference().m_totalFields; + + if(source->IsBoxed()) destination->Box(); + + while(true) + { + if(totFields-- == 0) break; + + // + // We increment the two pointers to skip the header of the objects. + // + source ++; + destination++; + + NANOCLR_CHECK_HRESULT(destination->Reassign( *source )); + } + + NANOCLR_SET_AND_LEAVE(S_OK); + } + + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT CLR_RT_ExecutionEngine::NewArrayList( CLR_RT_HeapBlock& ref, int size, CLR_RT_HeapBlock_Array*& array ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + const int minCapacity = CLR_RT_ArrayListHelper::c_defaultCapacity; + int count = size; + int capacity = size < minCapacity ? minCapacity : size; + + NANOCLR_CHECK_HRESULT(NewObjectFromIndex( ref, g_CLR_RT_WellKnownTypes.m_ArrayList )); + + NANOCLR_CHECK_HRESULT(CLR_RT_ArrayListHelper::PrepareArrayList ( ref, count, capacity )); + NANOCLR_CHECK_HRESULT(CLR_RT_ArrayListHelper::ExtractArrayFromArrayList( ref, array, count, capacity )); + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT CLR_RT_ExecutionEngine::FindFieldDef( CLR_RT_TypeDef_Instance& inst, const char* szText, CLR_RT_FieldDef_Index& res ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Instance local = inst; + + do + { + if(local.m_assm->FindFieldDef( local.m_target, szText, NULL, 0, res )) NANOCLR_SET_AND_LEAVE(S_OK); + } + while(local.SwitchToParent()); + + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_ExecutionEngine::FindFieldDef( CLR_RT_HeapBlock& reference, const char* szText, CLR_RT_FieldDef_Index& res ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* obj; + CLR_RT_TypeDef_Instance inst; + + if(reference.DataType() != DATATYPE_OBJECT) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + obj = reference.Dereference(); FAULT_ON_NULL(obj); + + if(inst.InitializeFromIndex( obj->ObjectCls() ) == false) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + NANOCLR_SET_AND_LEAVE(FindFieldDef( inst, szText, res )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_ExecutionEngine::FindField( CLR_RT_HeapBlock& reference, const char* szText, CLR_RT_HeapBlock*& field ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_FieldDef_Instance inst; + CLR_RT_FieldDef_Index idx; + CLR_RT_HeapBlock* res; + + field = NULL; + + NANOCLR_CHECK_HRESULT(FindFieldDef( reference, szText, idx )); + + inst.InitializeFromIndex( idx ); + + if(inst.m_target->flags & CLR_RECORD_FIELDDEF::FD_Static) + { + res = CLR_RT_ExecutionEngine::AccessStaticField( idx ); if(res == NULL) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + else + { + res = reference.Dereference(); FAULT_ON_NULL(res); + + res += inst.CrossReference().m_offset; + } + + field = res; + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_ExecutionEngine::SetField( CLR_RT_HeapBlock& reference, const char* szText, CLR_RT_HeapBlock& value ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* field; + + NANOCLR_CHECK_HRESULT(FindField( reference, szText, field )); + + field->Assign( value ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_ExecutionEngine::GetField( CLR_RT_HeapBlock& reference, const char* szText, CLR_RT_HeapBlock& value ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* field; + + NANOCLR_CHECK_HRESULT(FindField( reference, szText, field )); + + value.Assign( *field ); + + NANOCLR_NOCLEANUP(); +} + +//--// + +CLR_RT_HeapBlock_Lock* CLR_RT_ExecutionEngine::FindLockObject( CLR_RT_DblLinkedList& threads, CLR_RT_HeapBlock& object ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_NODE(CLR_RT_Thread,th,threads) + { + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Lock,lock,th->m_locks) + { + CLR_RT_HeapBlock& res = lock->m_resource; + +#if defined(NANOCLR_APPDOMAINS) + if(lock->m_appDomain != GetCurrentAppDomain()) continue; +#endif + + if(CLR_RT_HeapBlock::ObjectsEqual(res, object, true)) + { + return lock; + } + } + NANOCLR_FOREACH_NODE_END(); + } + NANOCLR_FOREACH_NODE_END(); + + return NULL; +} + +CLR_RT_HeapBlock_Lock* CLR_RT_ExecutionEngine::FindLockObject( CLR_RT_HeapBlock& object ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock_Lock* lock; + + if(object.DataType() == DATATYPE_OBJECT) + { + CLR_RT_HeapBlock* ptr = object.Dereference(); + + if(ptr) + { + switch(ptr->DataType()) + { + case DATATYPE_VALUETYPE: + case DATATYPE_CLASS : + return ptr->ObjectLock(); + + default: + // the remaining data types aren't to be handled + break; + } + } + } + + lock = FindLockObject( m_threadsReady , object ); if(lock) return lock; + lock = FindLockObject( m_threadsWaiting, object ); return lock; +} + +//--// + +void CLR_RT_ExecutionEngine::DeleteLockRequests( CLR_RT_Thread* thTarget, CLR_RT_SubThread* sthTarget ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(( thTarget && thTarget->m_lockRequestsCount) || + (sthTarget && sthTarget->m_lockRequestsCount) ) + { + DeleteLockRequests( thTarget, sthTarget, m_threadsReady ); + DeleteLockRequests( thTarget, sthTarget, m_threadsWaiting ); + } +} + +void CLR_RT_ExecutionEngine::DeleteLockRequests( CLR_RT_Thread* thTarget, CLR_RT_SubThread* sthTarget, CLR_RT_DblLinkedList& threads ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_NODE(CLR_RT_Thread,th,threads) + { + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Lock,lock,th->m_locks) + { + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_LockRequest,req,lock->m_requests) + { + CLR_RT_SubThread* sth = req->m_subthreadWaiting; + + if(sth == sthTarget || sth->m_owningThread == thTarget) + { + g_CLR_RT_EventCache.Append_Node( req ); + + if(sth->ChangeLockRequestCount( -1 )) return; + } + } + NANOCLR_FOREACH_NODE_END(); + } + NANOCLR_FOREACH_NODE_END(); + } + NANOCLR_FOREACH_NODE_END(); +} + +//--// + +void CLR_RT_ExecutionEngine::ProcessHardware() +{ + NATIVE_PROFILE_CLR_CORE(); + Watchdog_Reset(); + + g_CLR_HW_Hardware.ProcessActivity(); +} + +CLR_INT64 CLR_RT_ExecutionEngine::ProcessTimer() +{ + NATIVE_PROFILE_CLR_CORE(); + + CLR_INT64 timeoutMin; + + ProcessHardware(); + + timeoutMin = m_maximumTimeToActive; // max sleep. + + //////////////////////////////////////////////// + // WARNING + // + // The check on the 'Stopped' condition, and the 'else' + // condition below cause a race condition when the application is running under debugger + // and there are no ready threads in the app. teh desktop side debugger in facts is prodigal + // of Stopped commands and so is the runtime itself. Since the commands come asynchronously + // though and there is no co-ordination it is possible that + // a) a 'Stopped' condition reset get lost or + // b) waiting threads whose timers are expired are never moved to the ready queue + // + + if(CLR_EE_DBG_IS( Stopped ) && m_threadsWaiting.IsEmpty()) + { + // Don't process events while the debugger is stopped and no thread was waiting. + // if some thread was waiting we might need to transfer it to the ready queue + } + else + { + if(m_timerCache && m_timerCacheNextTimeout > HAL_Time_CurrentTime()) + { + timeoutMin = m_timerCacheNextTimeout - HAL_Time_CurrentTime(); + } + //else + { + CheckTimers( timeoutMin ); + + CheckThreads( timeoutMin, m_threadsReady ); + CheckThreads( timeoutMin, m_threadsWaiting ); + + m_timerCacheNextTimeout = timeoutMin + HAL_Time_CurrentTime(); + m_timerCache = (m_timerCacheNextTimeout > HAL_Time_CurrentTime()); + + } + } + + // if the system timer is not set as one of the wakeup events then just return the max time to active + if(0 == (g_CLR_HW_Hardware.m_wakeupEvents & SYSTEM_EVENT_FLAG_SYSTEM_TIMER)) + { + timeoutMin = m_maximumTimeToActive; + } + + return timeoutMin; +} + +void CLR_RT_ExecutionEngine::ProcessTimeEvent( CLR_UINT32 event ) +{ + NATIVE_PROFILE_CLR_CORE(); + SYSTEMTIME systemTime; + + HAL_Time_ToSystemTime( HAL_Time_CurrentTime(), &systemTime ); + + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Timer,timer,m_timers) + { + if(timer->m_flags & CLR_RT_HeapBlock_Timer::c_EnabledTimer) + { + CLR_UINT32 val = timer->m_flags & CLR_RT_HeapBlock_Timer::c_AnyChange; + + if(val) + { + timer->AdjustNextFixedExpire( systemTime, true ); + + if(val == event && (timer->m_flags & CLR_RT_HeapBlock_Timer::c_Recurring) == 0) + { + timer->Trigger(); + } + } + } + } + NANOCLR_FOREACH_NODE_END(); + + SpawnTimer(); +} + +void CLR_RT_ExecutionEngine::InvalidateTimerCache() +{ + NATIVE_PROFILE_CLR_CORE(); + g_CLR_RT_ExecutionEngine.m_timerCache = false; +} + +//--//--// + +bool CLR_RT_ExecutionEngine::IsTimeExpired( const CLR_INT64& timeExpire, CLR_INT64& timeoutMin ) +{ + NATIVE_PROFILE_CLR_CORE(); + + if(timeExpire <= (CLR_INT64)HAL_Time_CurrentTime()) return true; + + CLR_INT64 diff = timeExpire - HAL_Time_CurrentTime(); + + if(diff < timeoutMin) + { + timeoutMin = diff; + } + + return false; +} + +bool CLR_RT_ExecutionEngine::IsThereEnoughIdleTime( CLR_UINT32 expectedMsec ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(::Events_MaskedRead( g_CLR_HW_Hardware.m_wakeupEvents )) return false; + + CLR_INT64 now = HAL_Time_CurrentTime(); + + if(now + expectedMsec * TIME_CONVERSION__TO_MILLISECONDS >= m_currentNextActivityTime) return false; + + return true; +} + +//--// + +void CLR_RT_ExecutionEngine::CheckTimers( CLR_INT64& timeoutMin ) +{ + NATIVE_PROFILE_CLR_CORE(); + bool fAnyTimersExpired = false; + + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Timer,timer,m_timers) + { + if(timer->m_flags & CLR_RT_HeapBlock_Timer::c_EnabledTimer) + { + CLR_INT64 expire = timer->m_timeExpire; + if(IsTimeExpired( expire, timeoutMin )) + { + + #if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(CLR_EE_DBG_IS_NOT( PauseTimers )) + #endif + { + timer->Trigger(); + fAnyTimersExpired = true; + } + } + } + } + NANOCLR_FOREACH_NODE_END(); + + if(fAnyTimersExpired) + { + SpawnTimer(); + } + +} + +void CLR_RT_ExecutionEngine::CheckThreads( CLR_INT64& timeoutMin, CLR_RT_DblLinkedList& threads ) +{ + NATIVE_PROFILE_CLR_CORE(); + + NANOCLR_FOREACH_NODE(CLR_RT_Thread,th,threads) + { + CLR_INT64 expire; + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(th->m_flags & CLR_RT_Thread::TH_F_Suspended) + { + continue; + } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + // + // Check events. + // + expire = th->m_waitForEvents_Timeout; + if(IsTimeExpired( expire, timeoutMin )) + { + th->m_waitForEvents_Timeout = TIMEOUT_INFINITE; + + th->Restart( false ); + } + + // + // Check wait for object. + // + + { + CLR_RT_HeapBlock_WaitForObject* wait = th->m_waitForObject; + + if(wait) + { + if(IsTimeExpired( wait->m_timeExpire, timeoutMin )) + { + th->m_waitForObject_Result = CLR_RT_Thread::TH_WAIT_RESULT_TIMEOUT; + + th->Restart( true ); + } + } + } + + // + // Check lock requests. + // + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Lock,lock,th->m_locks) + { + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_LockRequest,req,lock->m_requests) + { + if(IsTimeExpired( req->m_timeExpire, timeoutMin )) + { + CLR_RT_SubThread* sth = req->m_subthreadWaiting; + + sth->ChangeLockRequestCount( -1 ); + + g_CLR_RT_EventCache.Append_Node( req ); + } + } + NANOCLR_FOREACH_NODE_END(); + } + NANOCLR_FOREACH_NODE_END(); + + // + // Check constraints. + // + NANOCLR_FOREACH_NODE_BACKWARD(CLR_RT_SubThread,sth,th->m_subThreads) + { + if(sth->m_timeConstraint != TIMEOUT_INFINITE) + { + if(IsTimeExpired( s_compensation.Adjust( sth->m_timeConstraint ), timeoutMin )) + { + (void)Library_corlib_native_System_Exception::CreateInstance( th->m_currentException, g_CLR_RT_WellKnownTypes.m_ConstraintException, S_OK, th->CurrentFrame() ); + + if((sth->m_status & CLR_RT_SubThread::STATUS_Triggered) == 0) + { + sth->m_status |= CLR_RT_SubThread::STATUS_Triggered; + + // + // This is the first time, give it 500msec to clean before killing it. + // + sth->m_timeConstraint += TIME_CONVERSION__TO_MILLISECONDS * 500; CLR_RT_ExecutionEngine::InvalidateTimerCache(); + } + else + { + CLR_RT_SubThread::DestroyInstance( th, sth, CLR_RT_SubThread::MODE_CheckLocks ); + + // + // So it doesn't fire again... + // + sth->m_timeConstraint = TIMEOUT_INFINITE; + } + + th->Restart( true ); + } + } + } + NANOCLR_FOREACH_NODE_END(); + } + NANOCLR_FOREACH_NODE_END(); +} + +//--// + +HRESULT CLR_RT_ExecutionEngine::LockObject( CLR_RT_HeapBlock& reference, CLR_RT_SubThread* sth, const CLR_INT64& timeExpire, bool fForce ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Lock* lock; + + lock = FindLockObject( reference ); + + if(lock == NULL) + { + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Lock::CreateInstance( lock, sth->m_owningThread, reference )); + } + + NANOCLR_SET_AND_LEAVE(CLR_RT_HeapBlock_Lock::IncrementOwnership( lock, sth, timeExpire, fForce )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_ExecutionEngine::UnlockObject( CLR_RT_HeapBlock& reference, CLR_RT_SubThread* sth ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Lock* lock; + + lock = FindLockObject( reference ); + + NANOCLR_SET_AND_LEAVE(CLR_RT_HeapBlock_Lock::DecrementOwnership( lock, sth )); + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT CLR_RT_ExecutionEngine::Sleep( CLR_RT_Thread* caller, const CLR_INT64& timeExpire ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + caller->m_waitForEvents_Timeout = timeExpire; CLR_RT_ExecutionEngine::InvalidateTimerCache(); + caller->m_status = CLR_RT_Thread::TH_S_Waiting; + + NANOCLR_SET_AND_LEAVE(CLR_E_THREAD_WAITING); + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT CLR_RT_ExecutionEngine::WaitEvents( CLR_RT_Thread* caller, const CLR_INT64& timeExpire, CLR_UINT32 events, bool& fSuccess ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(m_raisedEvents & events) + { + m_raisedEvents &= ~events; + + fSuccess = true; + } + else + { + fSuccess = false; + + if((CLR_INT64)HAL_Time_CurrentTime() < timeExpire) + { + caller->m_waitForEvents = events; + caller->m_waitForEvents_Timeout = timeExpire; CLR_RT_ExecutionEngine::InvalidateTimerCache(); + caller->m_status = CLR_RT_Thread::TH_S_Waiting; + + NANOCLR_SET_AND_LEAVE(CLR_E_THREAD_WAITING); + } + } + + NANOCLR_NOCLEANUP(); +} + +void CLR_RT_ExecutionEngine::SignalEvents( CLR_RT_DblLinkedList& threads, CLR_UINT32 events ) +{ + NATIVE_PROFILE_CLR_CORE(); + m_raisedEvents |= events; + + NANOCLR_FOREACH_NODE(CLR_RT_Thread,th,threads) + { + if((th->m_waitForEvents & events) != 0) + { + _ASSERTE(&threads == &m_threadsWaiting); + _ASSERTE(th->m_status == CLR_RT_Thread::TH_S_Waiting); + + th->Restart( true ); + } + } + NANOCLR_FOREACH_NODE_END(); +} + +void CLR_RT_ExecutionEngine::SignalEvents( CLR_UINT32 events ) +{ + NATIVE_PROFILE_CLR_CORE(); + //Why does the ready queue need to be checked. + SignalEvents( m_threadsReady , events ); + SignalEvents( m_threadsWaiting, events ); +} + +//--// + +bool CLR_RT_ExecutionEngine::IsInstanceOf( CLR_RT_TypeDescriptor& desc, CLR_RT_TypeDescriptor& descTarget ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_TypeDef_Instance& inst = desc .m_handlerCls; + CLR_RT_TypeDef_Instance& instTarget = descTarget.m_handlerCls; + bool fArray = false; + + while(desc .m_reflex.m_levels > 0 && + descTarget.m_reflex.m_levels > 0 ) + { + desc .GetElementType( desc ); + descTarget.GetElementType( descTarget ); + + fArray = true; + } + + if(desc.m_reflex.m_levels < descTarget.m_reflex.m_levels) return false; + + if(desc.m_reflex.m_levels > descTarget.m_reflex.m_levels) + { + if(descTarget.m_reflex.m_levels == 0) + { + // + // Casting from [] to System.Array or System.Object is always allowed. + // + if(inst.m_data == g_CLR_RT_WellKnownTypes.m_Array .m_data || + inst.m_data == g_CLR_RT_WellKnownTypes.m_Object .m_data || + inst.m_data == g_CLR_RT_WellKnownTypes.m_IList .m_data || + inst.m_data == g_CLR_RT_WellKnownTypes.m_ICloneable.m_data ) + { + return true; + } + } + + if(inst.m_target->dataType != instTarget.m_target->dataType) + { + return false; + } + } + + CLR_UINT32 semantic = (inst .m_target->flags & CLR_RECORD_TYPEDEF::TD_Semantics_Mask); + CLR_UINT32 semanticTarget = (instTarget.m_target->flags & CLR_RECORD_TYPEDEF::TD_Semantics_Mask); + + if(fArray) + { + if(semantic != semanticTarget) + { + return false; + } + } + + do + { + if(inst.m_data == instTarget.m_data) + { + return true; + } + + // + // Scan the list of interfaces. + // + if(semanticTarget == CLR_RECORD_TYPEDEF::TD_Semantics_Interface && inst.m_target->interfaces != CLR_EmptyIndex) + { + CLR_RT_SignatureParser parser; parser.Initialize_Interfaces( inst.m_assm, inst.m_target ); + CLR_RT_SignatureParser::Element res; + + while(parser.Available() > 0) + { + if(FAILED(parser.Advance( res ))) break; + + if(res.m_cls.m_data == instTarget.m_data) + { + return true; + } + } + } + } + while(inst.SwitchToParent()); + + return false; +} + +bool CLR_RT_ExecutionEngine::IsInstanceOf( const CLR_RT_TypeDef_Index& cls, const CLR_RT_TypeDef_Index& clsTarget ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_TypeDescriptor desc; + CLR_RT_TypeDescriptor descTarget; + + if(FAILED(desc .InitializeFromType( cls ))) return false; + if(FAILED(descTarget.InitializeFromType( clsTarget ))) return false; + + return IsInstanceOf( desc, descTarget ); +} + +bool CLR_RT_ExecutionEngine::IsInstanceOf( CLR_RT_HeapBlock& ref, const CLR_RT_TypeDef_Index& clsTarget ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_TypeDescriptor desc; + CLR_RT_TypeDescriptor descTarget; + + if(FAILED(desc .InitializeFromObject( ref ))) return false; + if(FAILED(descTarget.InitializeFromType ( clsTarget ))) return false; + + return IsInstanceOf( desc, descTarget ); +} + +bool CLR_RT_ExecutionEngine::IsInstanceOf( CLR_RT_HeapBlock& obj, CLR_RT_Assembly* assm, CLR_UINT32 token ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_TypeDescriptor desc; + CLR_RT_TypeDescriptor descTarget; + CLR_RT_TypeDef_Instance clsTarget; + CLR_RT_TypeSpec_Instance defTarget; + + if(FAILED(desc.InitializeFromObject( obj ))) return false; + + if(clsTarget.ResolveToken( token, assm )) + { + // + // Shortcut for identity. + // + if(desc.m_handlerCls.m_data == clsTarget.m_data) return true; + + if(FAILED(descTarget.InitializeFromType( clsTarget ))) return false; + } + else if(defTarget.ResolveToken( token, assm )) + { + if(FAILED(descTarget.InitializeFromTypeSpec( defTarget ))) return false; + } + else + { + return false; + } + + return IsInstanceOf( desc, descTarget ); +} + +HRESULT CLR_RT_ExecutionEngine::CastToType( CLR_RT_HeapBlock& ref, CLR_UINT32 tk, CLR_RT_Assembly* assm, bool fUpdate ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(ref.DataType() == DATATYPE_OBJECT && ref.Dereference() == NULL) + { + ; + } + else if(g_CLR_RT_ExecutionEngine.IsInstanceOf( ref, assm, tk ) == true) + { + ; + } + else + { + if(fUpdate == false) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_CAST); + } + + ref.SetObjectReference( NULL ); + } + + NANOCLR_NOCLEANUP(); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +HRESULT CLR_RT_ExecutionEngine::InitTimeout( CLR_INT64& timeExpire, const CLR_INT64& timeout ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(timeout < 0) + { + // because we are expecting the timeout value to be in ticks + // need to check for two possible infinite timeouts: + // 1. when coding in native it's supposed to use -1L as a timeout infinite + // 2. in managed code the constant System.Threading.Timeout.Infinite is -1 milliseconds, therefore needs to be converted to ticks + if( (timeout != -1L) && + (timeout != -1L * TIME_CONVERSION__TO_MILLISECONDS)) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + } + + timeExpire = TIMEOUT_INFINITE; + } + else + { + timeExpire = timeout + HAL_Time_CurrentTime(); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_ExecutionEngine::InitTimeout( CLR_INT64& timeExpire, CLR_INT32 timeout ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(timeout < 0) + { + if(timeout != -1) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + } + + timeExpire = TIMEOUT_INFINITE; + } + else + { + timeExpire = timeout; + timeExpire *= TIME_CONVERSION__TO_MILLISECONDS; + timeExpire += HAL_Time_CurrentTime(); + } + + NANOCLR_NOCLEANUP(); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +void CLR_RT_ExecutionEngine::DebuggerLoop() +{ + NATIVE_PROFILE_CLR_CORE(); + ProcessHardware(); + + WaitSystemEvents(SLEEP_LEVEL__SLEEP, g_CLR_HW_Hardware.m_wakeupEvents, TIME_CONVERSION__TO_MILLISECONDS * 100 ); +} + + +//--// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + +void CLR_RT_ExecutionEngine::SetDebuggingInfoBreakpoints( bool fSet ) +{ + NATIVE_PROFILE_CLR_CORE(); + for(size_t pos=0; posm_pid; + th->m_timeQuantumExpired = true; + } + + if(m_breakpointsActiveNum == 1) + { + CLR_EE_DBG_EVENT_SEND(CLR_DBG_Commands::c_Debugging_Execution_BreakpointHit, sizeof(CLR_DBG_Commands::Debugging_Execution_BreakpointDef), &m_breakpointsActive[0],WP_Flags_c_NonCritical); + } + } + else + { + _ASSERTE(false); + } + } +} + +void CLR_RT_ExecutionEngine::StopOnBreakpoint( CLR_DBG_Commands::Debugging_Execution_BreakpointDef& def, CLR_RT_StackFrame* stack, CLR_PMETADATA ip ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(ip == NULL) ip = stack->m_IP; + + def.m_depth = stack->m_depth; + def.m_md = stack->m_call; + def.m_IP = (CLR_UINT32)(ip - stack->m_IPstart); + + //Don't fail for special cases regarding messages dealing with exception handling. + _ASSERTE(def.m_IP == 0xffffffff || ip >= stack->m_IPstart); + //we don't actually know the end of the method. + + StopOnBreakpoint( def, stack->m_owningThread ); +} + +bool CLR_RT_ExecutionEngine::DequeueActiveBreakpoint( CLR_DBG_Commands::Debugging_Execution_BreakpointDef& def ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(m_breakpointsActiveNum) + { + def = m_breakpointsActive[ 0 ]; + + if(--m_breakpointsActiveNum == 0) + { + def.m_flags |= CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_LAST_BREAKPOINT; + } + + memmove( &m_breakpointsActive[ 0 ], &m_breakpointsActive[ 1 ], sizeof(m_breakpointsActive[ 0 ]) * m_breakpointsActiveNum ); + + return true; + } + + return false; +} + +//--// + +void CLR_RT_ExecutionEngine::Breakpoint_System_Event( CLR_DBG_Commands::Debugging_Execution_BreakpointDef& hit, CLR_UINT16 event, CLR_RT_Thread* th, CLR_RT_StackFrame* stack, CLR_PMETADATA ip ) +{ + NATIVE_PROFILE_CLR_CORE(); + for(size_t pos=0; posm_owningThread)); + + th = stack->m_owningThread; + } + + if(th == NULL || (def.m_pid == th->m_pid) || def.m_pid == CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_PID_ANY) + { + if(def.m_flags & event) + { + hit.m_id = def.m_id; + hit.m_flags = event; + + if(stack != NULL) + { + StopOnBreakpoint( hit, stack, ip ); + } + else + { + StopOnBreakpoint( hit, th ); + } + } + } + } +} + +void CLR_RT_ExecutionEngine::Breakpoint_Assemblies_Loaded() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_DBG_Commands::Debugging_Execution_BreakpointDef hit; NANOCLR_CLEAR(hit); + + for(size_t i = 0; i < this->m_breakpointsActiveNum; i++) + { + CLR_DBG_Commands::Debugging_Execution_BreakpointDef& def = this->m_breakpointsActive[ i ]; + + if(def.m_flags & CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_ASSEMBLIES_LOADED) + { + //There is already one queued AssembliesLoaded breakpoint. No need to send another one. + return; + } + } + + Breakpoint_System_Event( hit, CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_ASSEMBLIES_LOADED, m_currentThread, NULL, NULL ); +} + +void CLR_RT_ExecutionEngine::Breakpoint_Threads_Prepare( CLR_RT_DblLinkedList& threads ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_NODE(CLR_RT_Thread,th,threads) + { + th->m_fHasJMCStepper = false; + + for(size_t pos=0; posm_pid) + { + th->m_fHasJMCStepper = true; + break; + } + } + } + + NANOCLR_FOREACH_NODE(CLR_RT_StackFrame,call,th->m_stackFrames) + { + call->m_flags &= ~CLR_RT_StackFrame::c_HasBreakpoint; + + if(call->m_call.DebuggingInfo().HasBreakpoint()) + { + call->m_flags |= CLR_RT_StackFrame::c_HasBreakpoint; + } + else + { + for(size_t pos=0; posm_pid && def.m_depth == call->m_depth) + { + call->m_flags |= CLR_RT_StackFrame::c_HasBreakpoint; + break; + } + } + } + } +#ifndef CLR_NO_IL_INLINE + if(call->m_inlineFrame) + { + if(call->m_inlineFrame->m_frame.m_call.DebuggingInfo().HasBreakpoint()) + { + call->m_flags |= CLR_RT_StackFrame::c_HasBreakpoint; + } + else + { + for(size_t pos=0; posm_pid && def.m_depth == (call->m_depth-1)) + { + call->m_flags |= CLR_RT_StackFrame::c_HasBreakpoint; + break; + } + } + } + } + } +#endif + } + NANOCLR_FOREACH_NODE_END(); + } + NANOCLR_FOREACH_NODE_END(); +} + +void CLR_RT_ExecutionEngine::Breakpoint_Thread_Terminated( CLR_RT_Thread* th ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_DBG_Commands::Debugging_Execution_BreakpointDef hit; NANOCLR_CLEAR(hit); + CLR_UINT16 evt = CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_THREAD_TERMINATED; + + hit.m_depth = 0xFFFFFFFF; + + if(th->m_scratchPad >= 0) + { + evt |= CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_EVAL_COMPLETE; + } + + Breakpoint_System_Event( hit, evt, th, NULL, NULL ); +} + +void CLR_RT_ExecutionEngine::Breakpoint_Thread_Created( CLR_RT_Thread* th ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_DBG_Commands::Debugging_Execution_BreakpointDef hit; NANOCLR_CLEAR(hit); + + Breakpoint_System_Event( hit, CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_THREAD_CREATED, th, NULL, NULL ); +} + +//--// + +void CLR_RT_ExecutionEngine::Breakpoint_StackFrame_Push( CLR_RT_StackFrame* stack, CLR_UINT32 reason ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_Thread* th = stack->m_owningThread; + int pid = th->m_pid; + CLR_UINT32 depthMax = stack->m_depth - 1; + CLR_UINT16 flags = CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_STEP_IN; + CLR_UINT32 depthMin = depthMax; + + if(stack->m_flags & CLR_RT_StackFrame::c_PseudoStackFrameForFilter) + { + //If a filter frame is being pushed on (assuming the InterceptMask for filters is set), we want to intercept the frame + //in certain special cases. + _ASSERTE(th->m_nestedExceptionsPos); + CLR_RT_Thread::UnwindStack& us = th->m_nestedExceptions[ th->m_nestedExceptionsPos-1 ]; + _ASSERTE(us.m_stack == stack); + depthMin = us.m_handlerStack->m_depth; + //If we popped off frames from AppDomain transitions that had steppers, we want to break there as well. + depthMax = 0xffffffff; + flags |= CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_STEP_OVER | CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_STEP_OUT; + } + + for(size_t pos=0; posm_call.DebuggingInfo().IsJMC(); + } + else + { + fStop = (def.m_depth >= depthMin && def.m_depth <= depthMax); + } + + if(def.m_depth == depthMin && (def.m_flags & CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_STEP) == CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_STEP_OUT) + { + //In the case a user did a step out in a frame, we don't want to break if a filter gets pushed from that frame. However, if there is a step in or over on that frame, + //we should break. + fStop = false; + } + + if(fStop) + { + CLR_DBG_Commands::Debugging_Execution_BreakpointDef hit = def; + + hit.m_flags = CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_STEP_IN; + hit.m_depthExceptionHandler = reason; + + StopOnBreakpoint( hit, stack, NULL ); + } + } + } + } + + Breakpoint_StackFrame_Hard( stack, stack->m_IP ); +} + +void CLR_RT_ExecutionEngine::Breakpoint_StackFrame_Pop( CLR_RT_StackFrame* stack, bool stepEH ) +{ + NATIVE_PROFILE_CLR_CORE(); + int pid = stack->m_owningThread->m_pid; + CLR_UINT32 depth = stack->m_depth; + CLR_RT_StackFrame* caller = stack->Caller(); + + if(caller->Prev() || stepEH) + { + for(size_t pos=0; posm_call.DebuggingInfo().IsJMC(); + } + else + { + fStop = (depth <= def.m_depth); + } + + if(fStop) + { + CLR_DBG_Commands::Debugging_Execution_BreakpointDef hit = def; + + hit.m_flags = CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_STEP_OUT; + + if(stepEH) + { + hit.m_depthExceptionHandler = CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_DEPTH_STEP_EXCEPTION_HANDLER; + } + else + { + hit.m_depthExceptionHandler = CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_DEPTH_STEP_RETURN; + } + + StopOnBreakpoint( hit, (stepEH)? stack : caller, NULL ); + } + } + } + } + } +} + +void CLR_RT_ExecutionEngine::Breakpoint_StackFrame_Step( CLR_RT_StackFrame* stack, CLR_PMETADATA ip ) +{ + NATIVE_PROFILE_CLR_CORE(); + int pid = stack->m_owningThread->m_pid; + CLR_UINT32 depth = stack->m_depth; + CLR_UINT32 IPoffset = (CLR_UINT32)(ip - stack->m_IPstart); + + for(size_t pos=0; pos= def.m_IPEnd)) + { + if(def.m_flags & CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_STEP_JMC) + { + if(!stack->m_call.DebuggingInfo().IsJMC()) + { + continue; + } + } + + CLR_DBG_Commands::Debugging_Execution_BreakpointDef hit = def; + + hit.m_flags = CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_STEP_OVER; + + StopOnBreakpoint( hit, stack, ip ); + } + } + } + + Breakpoint_StackFrame_Hard( stack, ip ); +} + +void CLR_RT_ExecutionEngine::Breakpoint_StackFrame_Hard( CLR_RT_StackFrame* stack, CLR_PMETADATA ip ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(stack->Prev() != NULL && ip != NULL) + { + CLR_UINT32 IPoffset = (CLR_UINT32)(ip - stack->m_IPstart); + + for(size_t pos=0; posm_owningThread->m_pid || def.m_pid == CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_PID_ANY) + { + if(def.m_md.m_data == stack->m_call.m_data && def.m_IP == IPoffset) + { + CLR_DBG_Commands::Debugging_Execution_BreakpointDef hit = def; + + hit.m_flags = CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_HARD; + + StopOnBreakpoint( hit, stack, ip ); + } + } + } + } + } +} + +void CLR_RT_ExecutionEngine::Breakpoint_StackFrame_Break( CLR_RT_StackFrame* stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_DBG_Commands::Debugging_Execution_BreakpointDef hit; NANOCLR_CLEAR(hit); + + Breakpoint_System_Event( hit, CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_BREAK, NULL, stack, NULL ); +} + +//--// + +void CLR_RT_ExecutionEngine::Breakpoint_Exception( CLR_RT_StackFrame* stack, CLR_UINT32 reason, CLR_PMETADATA ip ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_DBG_Commands::Debugging_Execution_BreakpointDef hit; NANOCLR_CLEAR(hit); + hit.m_depthExceptionHandler = reason; + + Breakpoint_System_Event( hit, CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_EXCEPTION_THROWN, NULL, stack, ip ); +} + +void CLR_RT_ExecutionEngine::Breakpoint_Exception_Uncaught( CLR_RT_Thread* th ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_DBG_Commands::Debugging_Execution_BreakpointDef hit; NANOCLR_CLEAR(hit); + + hit.m_depth = CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_DEPTH_UNCAUGHT; + hit.m_depthExceptionHandler = CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_DEPTH_UNCAUGHT; + + Breakpoint_System_Event( hit, CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_EXCEPTION_THROWN, th, NULL, NULL ); +} + +void CLR_RT_ExecutionEngine::Breakpoint_Exception_Intercepted( CLR_RT_StackFrame* stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_DBG_Commands::Debugging_Execution_BreakpointDef hit; NANOCLR_CLEAR(hit); + CLR_UINT16 event = CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_EXCEPTION_CAUGHT + | CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_EXCEPTION_UNWIND; + + hit.m_depthExceptionHandler = stack->m_depth; + + Breakpoint_System_Event( hit, event, NULL, stack, NULL ); +} + +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#if defined(NANOCLR_APPDOMAINS) + +CLR_RT_AppDomain* CLR_RT_ExecutionEngine::SetCurrentAppDomain( CLR_RT_AppDomain* appDomain ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_AppDomain* ad = m_appDomainCurrent; + + m_appDomainCurrent = appDomain; + + return ad; +} + +CLR_RT_AppDomain* CLR_RT_ExecutionEngine::GetCurrentAppDomain() +{ + NATIVE_PROFILE_CLR_CORE(); + return m_appDomainCurrent; +} + +void CLR_RT_ExecutionEngine::PrepareThreadsForAppDomainUnload( CLR_RT_AppDomain* appDomain, CLR_RT_DblLinkedList& threads) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_NODE(CLR_RT_Thread, th, threads) + { + bool fFoundDoomedAppDomain = false; + bool fInjectThreadAbort = false; + + NANOCLR_FOREACH_NODE(CLR_RT_StackFrame, stack, th->m_stackFrames) + { + if(!fFoundDoomedAppDomain) + { + if(stack->m_appDomain == appDomain) + { + //The first stack frame found in a doomed AppDomain + fFoundDoomedAppDomain = true; + fInjectThreadAbort = true; + stack->m_flags |= CLR_RT_StackFrame::c_AppDomainInjectException; + th ->m_flags |= CLR_RT_Thread::TH_F_ContainsDoomedAppDomain; + } + } + else //fFoundDoomedAppDomain + { + if(stack->m_flags & CLR_RT_StackFrame::c_AppDomainInjectException) + { + //This thread is already being unwound due to an unloading AppDomain + stack->m_flags &= ~CLR_RT_StackFrame::c_AppDomainInjectException; + fInjectThreadAbort = false; + } + } + } + NANOCLR_FOREACH_NODE_END(); + + if(fInjectThreadAbort) + { + (void)th->Abort(); + } + } + NANOCLR_FOREACH_NODE_END(); +} + +HRESULT CLR_RT_ExecutionEngine::UnloadAppDomain( CLR_RT_AppDomain* appDomain, CLR_RT_Thread* th ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + //Check to make sure the current thread does not contain any doomed AppDomains + NANOCLR_FOREACH_NODE(CLR_RT_StackFrame, stack, th->m_stackFrames) + { + if(!stack->m_appDomain->IsLoaded() || stack->m_appDomain == appDomain) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + NANOCLR_FOREACH_NODE_END(); + + PrepareThreadsForAppDomainUnload( appDomain, m_threadsReady ); + PrepareThreadsForAppDomainUnload( appDomain, m_threadsWaiting ); + + appDomain->m_state = CLR_RT_AppDomain::AppDomainState_Unloading; + CLR_EE_SET(UnloadingAppDomain); + + NANOCLR_NOCLEANUP(); +} + +#endif + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +CLR_UINT32 CLR_RT_ExecutionEngine::WaitSystemEvents( CLR_UINT32 powerLevel, CLR_UINT32 events, CLR_INT64 timeExpire ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_INT32 timeout; + + CLR_UINT32 res = 0; + + m_currentNextActivityTime = timeExpire + HAL_Time_CurrentTime(); + + timeout = (CLR_INT32)timeExpire / TIME_CONVERSION__TO_MILLISECONDS; + + if(timeout == 0) timeout = 1; + +#if defined(NANOCLR_TRACE_SYSTEMEVENTWAIT) + CLR_INT64 start = HAL_Time_CurrentTime(); +#endif + +#if defined(NANOCLR_STRESS_GC) + if(timeout > 100) + { + CLR_INT64 startGC = HAL_Time_CurrentTime(); + + + g_CLR_RT_ExecutionEngine.PerformHeapCompaction (); + + CLR_INT64 endGC = HAL_Time_CurrentTime(); + + timeout -= (CLR_INT32)((endGC - startGC) / TIME_CONVERSION__TO_MILLISECONDS); + } +#endif + + // UNDONE: FIXME + // ::Watchdog_GetSetEnabled( bool, bool ); + // TODO check if the watchdog needs to be feed here... don't think so + Watchdog_Reset(); + + res = ::Events_WaitForEvents( powerLevel, events, timeout ); + // UNDONE: FIXME + // ::Watchdog_GetSetEnabled( bool, bool ); + // TODO check if the watchdog needs to be feed here... don't think so + Watchdog_Reset(); + + +#if defined(NANOCLR_TRACE_SYSTEMEVENTWAIT) + CLR_INT64 stop = HAL_Time_CurrentTime(); + CLR_INT64 stop2 = HAL_Time_CurrentTime(); + + static CLR_INT64 totalRequested = 0; + static CLR_INT64 totalActual = 0; + static CLR_INT64 samples = 0; + + totalRequested += timeout; + totalActual += (stop - start) - (stop2 - stop); + samples += 1; + + if(samples == 10000) + { + CLR_Debug::Printf( "Wait %lld %lld\r\n", totalRequested / samples, totalActual / samples ); + + totalRequested = 0; + totalActual = 0; + samples = 0; + } +#endif + + m_currentNextActivityTime = 0; + + return res; +} + diff --git a/source/native/nf-interpreter/src/CLR/Core/GarbageCollector.cpp b/source/native/nf-interpreter/src/CLR/Core/GarbageCollector.cpp new file mode 100644 index 00000000..a79979da --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/GarbageCollector.cpp @@ -0,0 +1,828 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +CLR_RT_ProtectFromGC* CLR_RT_ProtectFromGC::s_first = NULL; + +void CLR_RT_ProtectFromGC::Initialize( CLR_RT_HeapBlock& ref ) +{ + NATIVE_PROFILE_CLR_CORE(); + m_next = s_first; s_first = this; + + m_data = (void**)&ref; + m_fpn = NULL; + + if(ref.IsForcedAlive()) + { + m_flags = c_HeapBlock; + } + else + { + m_flags = c_HeapBlock | c_ResetKeepAlive; + + ref.MarkForcedAlive(); + } +} + +void CLR_RT_ProtectFromGC::Initialize( void** data, Callback fpn ) +{ + NATIVE_PROFILE_CLR_CORE(); + m_next = s_first; s_first = this; + + m_data = data; + m_fpn = fpn; + m_flags = c_Generic; +} + +void CLR_RT_ProtectFromGC::Cleanup() +{ + NATIVE_PROFILE_CLR_CORE(); + s_first = m_next; + + if(m_flags & c_ResetKeepAlive) + { + CLR_RT_HeapBlock* obj = (CLR_RT_HeapBlock*)m_data; + + obj->UnmarkForcedAlive(); + } +} + +void CLR_RT_ProtectFromGC::Invoke() +{ + NATIVE_PROFILE_CLR_CORE(); + if(m_fpn) + { + m_fpn( *m_data ); + } + else if(m_data) + { + g_CLR_RT_GarbageCollector.CheckMultipleBlocks( (CLR_RT_HeapBlock*)m_data, 1 ); + } +} + +void CLR_RT_ProtectFromGC::InvokeAll() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_ProtectFromGC* ptr; + + ptr = s_first; + while(ptr) + { + ptr->Invoke(); + + ptr = ptr->m_next; + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#if defined(NANOCLR_TRACE_EARLYCOLLECTION) + +CLR_RT_AssertEarlyCollection* CLR_RT_AssertEarlyCollection::s_first = NULL; + +CLR_RT_AssertEarlyCollection::CLR_RT_AssertEarlyCollection( CLR_RT_HeapBlock* ptr ) +{ + NATIVE_PROFILE_CLR_CORE(); + m_next = s_first; s_first = this; + + m_ptr = ptr; +} + +CLR_RT_AssertEarlyCollection::~CLR_RT_AssertEarlyCollection() +{ + NATIVE_PROFILE_CLR_CORE(); + s_first = m_next; +} + +void CLR_RT_AssertEarlyCollection::Cancel() +{ + NATIVE_PROFILE_CLR_CORE(); + m_ptr = NULL; +} + +void CLR_RT_AssertEarlyCollection::CheckAll( CLR_RT_HeapBlock* ptr ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_AssertEarlyCollection* node; + + node = s_first; + while(node) + { + if(node->m_ptr == ptr) + { + CLR_Debug::Printf( "INTERNAL ERROR: %08x retired early!!!\r\n", ptr ); + +#if defined(_WIN32) + ::Sleep( 1000 ); + ::DebugBreak(); +#endif + } + + node = node->m_next; + } +} + +#endif + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +CLR_UINT32 CLR_RT_GarbageCollector::ExecuteGarbageCollection() +{ + NATIVE_PROFILE_CLR_CORE(); +#if defined(NANOCLR_PROFILE_NEW_ALLOCATIONS) + g_CLR_PRF_Profiler.RecordGarbageCollectionBegin(); +#endif + +#if defined(NANOCLR_GC_VERBOSE) + if(s_CLR_RT_fTrace_GC >= c_CLR_RT_Trace_Info) + { + CLR_Debug::Printf( " Memory: Start %s\r\n", HAL_Time_CurrentDateTimeToString() ); + } +#endif + + //////////////////////////////////////////////////////////////////////////////////////////////// + + CLR_RT_ExecutionEngine::ExecutionConstraint_Suspend(); + +#if defined(NANOCLR_TRACE_MEMORY_STATS) + + CLR_UINT32 stats_start = HAL_Time_CurrentSysTicks(); + +#endif + + g_CLR_RT_EventCache.EventCache_Cleanup(); + + Mark (); + MarkWeak(); + Sweep (); + + Heap_ComputeAliveVsDeadRatio(); + + CheckMemoryPressure(); + +#if defined(NANOCLR_TRACE_MEMORY_STATS) + if(s_CLR_RT_fTrace_MemoryStats >= c_CLR_RT_Trace_Info) + { + int milliSec = ((int)::HAL_Time_SysTicksToTime( HAL_Time_CurrentSysTicks() - stats_start ) + TIME_CONVERSION__TICKUNITS - 1) / TIME_CONVERSION__TICKUNITS; + + CLR_Debug::Printf( "GC: %dmsec %d bytes used, %d bytes available\r\n", milliSec, m_totalBytes - m_freeBytes, m_freeBytes ); + } + + if(s_CLR_RT_fTrace_MemoryStats >= c_CLR_RT_Trace_Info) + { + int countBlocks[ DATATYPE_FIRST_INVALID ]; NANOCLR_CLEAR(countBlocks); + int countArryBlocks[ DATATYPE_FIRST_INVALID ]; NANOCLR_CLEAR(countArryBlocks); + int dt; + + NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster,hc,g_CLR_RT_ExecutionEngine.m_heap) + { + CLR_RT_HeapBlock_Node* ptr = hc->m_payloadStart; + CLR_RT_HeapBlock_Node* end = hc->m_payloadEnd; + + while(ptr < end) + { + dt = ptr->DataType(); + if(dt < DATATYPE_FIRST_INVALID) + { + countBlocks[ dt ] += ptr->DataSize(); + + if(dt == DATATYPE_SZARRAY) + { + CLR_RT_HeapBlock_Array* arr = (CLR_RT_HeapBlock_Array*)ptr; + + if(arr != NULL) + { + dt = arr->m_typeOfElement; + + if(dt < DATATYPE_FIRST_INVALID) + { + countArryBlocks[ dt ] += ptr->DataSize(); + } + else + { + CLR_Debug::Printf("!!!!Unknown array type: %d\r\n", dt); + } + } + + } + } + + ptr += ptr->DataSize(); + } + } + NANOCLR_FOREACH_NODE_END(); + + for(dt = DATATYPE_VOID; dt < DATATYPE_FIRST_INVALID; dt++) + { + if(countBlocks[ dt ]) + { + CLR_Debug::Printf( "Type %02X (%-20s): %6d bytes\r\n", dt, c_CLR_RT_DataTypeLookup[ dt ].m_name, countBlocks[ dt ] * sizeof(CLR_RT_HeapBlock) ); + + if(dt == DATATYPE_SZARRAY) + { + for(int dt2 = DATATYPE_VOID; dt2 < DATATYPE_FIRST_INVALID; dt2++) + { + if(countArryBlocks[ dt2 ]) + { + CLR_Debug::Printf( " Type %02X (%-17s): %6d bytes\r\n", dt2, c_CLR_RT_DataTypeLookup[ dt2 ].m_name, countArryBlocks[ dt2 ] * sizeof(CLR_RT_HeapBlock) ); + } + } + } + } + } + } +#endif + + CLR_RT_ExecutionEngine::ExecutionConstraint_Resume(); + + m_numberOfGarbageCollections++; + + //////////////////////////////////////////////////////////////////////////////////////////////// + +#if defined(NANOCLR_GC_VERBOSE) + if(s_CLR_RT_fTrace_GC >= c_CLR_RT_Trace_Info) + { + CLR_Debug::Printf( " Memory: End %s\r\n", HAL_Time_CurrentDateTimeToString() ); + } +#endif + +#if defined(NANOCLR_PROFILE_NEW_ALLOCATIONS) + g_CLR_PRF_Profiler.RecordGarbageCollectionEnd(); +#endif + + return m_freeBytes; +} + +//--// + +void CLR_RT_GarbageCollector::MarkSlow() +{ + NATIVE_PROFILE_CLR_CORE(); + while(m_fOutOfStackSpaceForGC) + { + m_fOutOfStackSpaceForGC = false; + + //go through managed heap. + //find all objects that are not alive but are pointed to by a live object + //put them on the markstack. + for(CLR_RT_HeapCluster* hc = (CLR_RT_HeapCluster*)g_CLR_RT_ExecutionEngine.m_heap.FirstNode(); + hc->Next(); + hc = (CLR_RT_HeapCluster*)hc->Next() + ) + { + CLR_RT_HeapBlock* ptr = hc->m_payloadStart; + CLR_RT_HeapBlock* end = hc->m_payloadEnd; + + while(ptr < end) + { + if(ptr->IsAlive() && !ptr->IsEvent()) + { + CheckSingleBlock_Force( ptr ); + } + + ptr += ptr->DataSize(); + } + } + } +} + +void CLR_RT_GarbageCollector::Mark() +{ + NATIVE_PROFILE_CLR_CORE(); +#if defined(NANOCLR_VALIDATE_APPDOMAIN_ISOLATION) + CLR_RT_AppDomain* appDomainSav = g_CLR_RT_ExecutionEngine.GetCurrentAppDomain(); +#endif + + // + // Let's setup the proper workers. + // + m_funcSingleBlock = ComputeReachabilityGraphForSingleBlock; + m_funcMultipleBlocks = ComputeReachabilityGraphForMultipleBlocks; + + m_fOutOfStackSpaceForGC = false; + + //////////////////////////////////////////////////////////////////////////// + // + // Prepare the helper buffers. + // + m_weakDelegates_Reachable.DblLinkedList_Initialize(); + + CLR_RT_DblLinkedList markStackList; + MarkStack markStack; + MarkStackElement markStackBuffer[ c_minimumSpaceForGC ]; + + m_markStackList = &markStackList; + m_markStack = &markStack; + + m_markStack ->Initialize( markStackBuffer, ARRAYSIZE(markStackBuffer) ); + m_markStackList->DblLinkedList_Initialize(); + m_markStackList->LinkAtFront( m_markStack ); + + + //////////////////////////////////////////////////////////////////////////// + // + // Call global markers. + // +#if defined(NANOCLR_VALIDATE_APPDOMAIN_ISOLATION) + (void)g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( NULL ); +#endif + + CLR_RT_ProtectFromGC::InvokeAll(); + + g_CLR_HW_Hardware.PrepareForGC(); + + + //////////////////////////////////////////////////////////////////////////// + // + // Do the recursive marking! + // + { + // + // Mark all the events, so we keep the related threads/objects alive. + // + { + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Finalizer,fin,g_CLR_RT_ExecutionEngine.m_finalizersPending) + { +#if defined(NANOCLR_VALIDATE_APPDOMAIN_ISOLATION) + (void)g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( fin->m_appDomain ); +#endif + CheckSingleBlock( &fin->m_object ); + } + NANOCLR_FOREACH_NODE_END(); + } + + // + // Mark all the static fields. + // + +#if defined(NANOCLR_APPDOMAINS) + AppDomain_Mark(); +#endif + + Assembly_Mark(); + + // + // Walk through all the stack frames, marking the objects as we dig down. + // + Thread_Mark( g_CLR_RT_ExecutionEngine.m_threadsReady ); + Thread_Mark( g_CLR_RT_ExecutionEngine.m_threadsWaiting ); + +#if !defined(NANOCLR_APPDOMAINS) + CheckSingleBlock_Force( g_CLR_RT_ExecutionEngine.m_globalLock ); +#endif + + CheckSingleBlock_Force( g_CLR_RT_ExecutionEngine.m_currentUICulture ); + + +#if defined(NANOCLR_VALIDATE_APPDOMAIN_ISOLATION) + (void)g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( NULL ); +#endif //NANOCLR_VALIDATE_APPDOMAIN_ISOLATION + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + CheckSingleBlock_Force( g_CLR_RT_ExecutionEngine.m_scratchPadArray ); +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + if(m_fOutOfStackSpaceForGC) + { + MarkSlow(); + _ASSERTE(!m_fOutOfStackSpaceForGC); + } + } + // + // + // + //////////////////////////////////////////////////////////////////////////// + + + //////////////////////////////////////////////////////////////////////////// + // + // Prepare finalization of objects + // + { + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Finalizer,fin,g_CLR_RT_ExecutionEngine.m_finalizersAlive) + { + // + // If the object is dead, make it alive one last time and put it in the pending finalizers list. + // + if(fin->m_object->IsAlive() == false) + { +#if defined(NANOCLR_VALIDATE_APPDOMAIN_ISOLATION) + (void)g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( fin->m_appDomain ); +#endif + CheckSingleBlock( &fin->m_object ); + + g_CLR_RT_ExecutionEngine.m_finalizersPending.LinkAtBack( fin ); + } + } + NANOCLR_FOREACH_NODE_END(); + } + // + // + // + //////////////////////////////////////////////////////////////////////////// + + if(m_fOutOfStackSpaceForGC) + { + MarkSlow(); + } + + _ASSERTE(m_markStackList == &markStackList); + _ASSERTE(m_markStack == &markStack ); + + while((MarkStack*)m_markStackList->LastValidNode() != m_markStack) + { + MarkStack* markStackT = (MarkStack*)m_markStackList->LastValidNode(); + + markStackT->RemoveFromList(); + + CLR_RT_Memory::Release( markStackT ); + } + + m_markStackList = NULL; + m_markStack = NULL; + +#if defined(NANOCLR_VALIDATE_APPDOMAIN_ISOLATION) + (void)g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( appDomainSav ); +#endif +} + +void CLR_RT_GarbageCollector::MarkWeak() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_WeakReference,weak,g_CLR_RT_ExecutionEngine.m_weakReferences) + { + if(weak->m_identity.m_flags & CLR_RT_HeapBlock_WeakReference::WR_Restored) + { + if(weak->m_targetSerialized) + { + weak->MarkAlive(); + } + } + + if(weak->IsAlive()) + { + if(weak->m_targetDirect) + { + if(weak->m_targetDirect->IsAlive()) + { + // + // If the direct object is alive, keep the serialized version around too!! + // + if(weak->m_targetSerialized && weak->m_targetSerialized->IsAlive() == false) + { + weak->m_targetSerialized->MarkAlive(); + } + } + else + { + weak->m_targetDirect = NULL; + } + } + } + else + { + weak->Unlink(); + } + } + NANOCLR_FOREACH_NODE_END(); +} + +//--// + +void CLR_RT_GarbageCollector::Sweep() +{ + NATIVE_PROFILE_CLR_CORE(); + + //////////////////////////////////////////////////////////////////////////////////////////////// + // // + // At this point all the alive objects have been reached, let's start the clean up. // + // // + //////////////////////////////////////////////////////////////////////////////////////////////// + + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Delegate_List,weak,m_weakDelegates_Reachable) + { + CLR_UINT32 num = weak->m_length; + CLR_RT_HeapBlock* dlgs = weak->GetDelegates(); + + for(;num--; dlgs++) + { + CLR_RT_HeapBlock_Delegate* dlg = dlgs->DereferenceDelegate(); + if(dlg) + { + CLR_RT_HeapBlock* obj = dlg->m_object.Dereference(); + if(obj && obj->IsAlive() == false) + { + // + // Found a dead delegate, kill it!! + // + dlgs->SetObjectReference( NULL ); + continue; + } + + dlg->MarkAlive(); + } + } + } + NANOCLR_FOREACH_NODE_END(); + + RecoverEventsFromGC(); + + //--// + + // + // All the dead objects are marked as such, it's time to reclaim them. + // + { + NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster,hc,g_CLR_RT_ExecutionEngine.m_heap) + { + hc->RecoverFromGC(); + } + NANOCLR_FOREACH_NODE_END(); + } +} + +//--// + +void CLR_RT_GarbageCollector::CheckMemoryPressure() +{ + NATIVE_PROFILE_CLR_CORE(); + if(m_freeBytes > c_memoryThreshold2) + { + m_pressureCounter = 0; + } + else + { + bool fExit = false; + + // + // Drop all the restored objects that haven't been reclaimed by an application. + // + NANOCLR_FOREACH_NODE_BACKWARD(CLR_RT_HeapBlock_WeakReference,weak,g_CLR_RT_ExecutionEngine.m_weakReferences) + { + if(weak->m_identity.m_flags & CLR_RT_HeapBlock_WeakReference::WR_Restored) + { + if(weak->m_targetSerialized) + { + fExit = true; + } + } + } + NANOCLR_FOREACH_NODE_BACKWARD_END(); + + if(fExit || m_freeBytes > c_memoryThreshold) + { + m_pressureCounter = 0; + } + else + { + m_pressureCounter++; + + if(m_pressureCounter > c_pressureThreshold) + { + NANOCLR_FOREACH_NODE_BACKWARD(CLR_RT_HeapBlock_WeakReference,weak,g_CLR_RT_ExecutionEngine.m_weakReferences) + { + if(weak->m_targetSerialized && weak->m_targetDirect == NULL) + { +#if !defined(BUILD_RTM) + CLR_RT_ReflectionDef_Index val; + CLR_RT_TypeDef_Instance inst; + char rgBuffer[ 512 ]; + char* szBuffer = rgBuffer; + size_t iBuffer = MAXSTRLEN(rgBuffer); + + CLR_Debug::Printf( "DROPPING OBJECT " ); + + val.InitializeFromHash( weak->m_identity.m_selectorHash ); + + if(inst.InitializeFromReflection( val, NULL )) + { + g_CLR_RT_TypeSystem.BuildTypeName( inst, szBuffer, iBuffer ); rgBuffer[ MAXSTRLEN(rgBuffer) ] = 0; + + CLR_Debug::Printf( "%s:%d ", rgBuffer, weak->m_identity.m_id ); + } + + CLR_Debug::Printf( " [%d bytes] %s\r\n", weak->m_targetSerialized->m_numOfElements, (weak->m_targetDirect ? "DIRECT" : "") ); +#endif + + break; + } + } + NANOCLR_FOREACH_NODE_BACKWARD_END(); + } + } + } +} + +//--// + +#if defined(NANOCLR_APPDOMAINS) + +void CLR_RT_GarbageCollector::AppDomain_Mark() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_NODE(CLR_RT_AppDomain,appDomain,g_CLR_RT_ExecutionEngine.m_appDomains) + { +#if defined(NANOCLR_VALIDATE_APPDOMAIN_ISOLATION) + (void)g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( appDomain ); +#endif + + NANOCLR_FOREACH_NODE(CLR_RT_AppDomainAssembly,appDomainAssembly,appDomain->m_appDomainAssemblies) + { + CheckMultipleBlocks( appDomainAssembly->m_pStaticFields, appDomainAssembly->m_assembly->m_iStaticFields ); + } + NANOCLR_FOREACH_NODE_END(); + + CheckSingleBlock_Force( appDomain->m_globalLock ); + CheckSingleBlock_Force( appDomain->m_strName ); + CheckSingleBlock_Force( appDomain->m_outOfMemoryException ); + } + NANOCLR_FOREACH_NODE_END(); +} + +#endif + +void CLR_RT_GarbageCollector::Assembly_Mark() +{ + NATIVE_PROFILE_CLR_CORE(); +#if defined(NANOCLR_VALIDATE_APPDOMAIN_ISOLATION) + (void)g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( NULL ); +#endif + + NANOCLR_FOREACH_ASSEMBLY(g_CLR_RT_TypeSystem) + { + +#if !defined(NANOCLR_APPDOMAINS) + CheckMultipleBlocks( pASSM->m_pStaticFields, pASSM->m_iStaticFields ); +#endif + + CheckSingleBlock( &pASSM->m_pFile ); + } + NANOCLR_FOREACH_ASSEMBLY_END(); +} + +//--// + +void CLR_RT_GarbageCollector::Thread_Mark( CLR_RT_Thread* th ) +{ + NATIVE_PROFILE_CLR_CORE(); +#if defined(NANOCLR_VALIDATE_APPDOMAIN_ISOLATION) + (void)g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( th->m_dlg->m_appDomain ); +#endif + CheckSingleBlock ( &th->m_dlg ); + +#if defined(NANOCLR_VALIDATE_APPDOMAIN_ISOLATION) + (void)g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( th->CurrentAppDomain() ); +#endif + CheckSingleBlock_Force( &th->m_currentException ); + + for(int i=0; im_nestedExceptionsPos; i++) + { + CLR_RT_Thread::UnwindStack& us = th->m_nestedExceptions[ i ]; + +#if defined(NANOCLR_VALIDATE_APPDOMAIN_ISOLATION) + (void)g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( us.m_stack->m_appDomain ); +#endif + + CheckSingleBlock_Force( us.m_exception ); + } + + // + // Mark all the objects on the stack frames. + // + NANOCLR_FOREACH_NODE(CLR_RT_StackFrame,stack,th->m_stackFrames) + { +#if defined(NANOCLR_VALIDATE_APPDOMAIN_ISOLATION) + (void)g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( stack->m_appDomain ); +#endif +#ifndef CLR_NO_IL_INLINE + if(stack->m_inlineFrame) + { + CheckMultipleBlocks( stack->m_inlineFrame->m_frame.m_args , stack->m_inlineFrame->m_frame.m_call.m_target->numArgs ); + CheckMultipleBlocks( stack->m_inlineFrame->m_frame.m_locals , stack->m_inlineFrame->m_frame.m_call.m_target->numLocals ); + CheckMultipleBlocks( stack->m_inlineFrame->m_frame.m_evalStack, (int)(stack->m_inlineFrame->m_frame.m_evalPos - stack->m_inlineFrame->m_frame.m_evalStack)); + } +#endif + CheckMultipleBlocks( stack->m_arguments, stack->m_call.m_target->numArgs ); + CheckMultipleBlocks( stack->m_locals , stack->m_call.m_target->numLocals ); + CheckMultipleBlocks( stack->m_evalStack, stack->TopValuePosition() ); + } + NANOCLR_FOREACH_NODE_END(); + + // + // Mark locked objects. + // + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Lock,lock,th->m_locks) + { +#if defined(NANOCLR_VALIDATE_APPDOMAIN_ISOLATION) + (void)g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( lock->m_appDomain ); +#endif + CheckSingleBlock_Force( &lock->m_resource ); + } + NANOCLR_FOREACH_NODE_END(); + + // + // Mark the objects this thread is waiting for. + // +#if defined(NANOCLR_VALIDATE_APPDOMAIN_ISOLATION) + (void)g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( th->CurrentAppDomain() ); +#endif + + { + CLR_RT_HeapBlock_WaitForObject* wait = th->m_waitForObject; + + if(wait) + { + CheckMultipleBlocks( wait->GetWaitForObjects(), wait->m_cObjects ); + } + } +} + +void CLR_RT_GarbageCollector::Thread_Mark( CLR_RT_DblLinkedList& threads ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_NODE(CLR_RT_Thread,th,threads) + { + Thread_Mark( th ); + } + NANOCLR_FOREACH_NODE_END(); +} + +//--// + +void CLR_RT_GarbageCollector::RecoverEventsFromGC() +{ + NATIVE_PROFILE_CLR_CORE(); + + CLR_RT_HeapBlock_EndPoint::HandlerMethod_RecoverFromGC(); + CLR_RT_HeapBlock_NativeEventDispatcher::HandlerMethod_RecoverFromGC(); + + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Timer,timer,g_CLR_RT_ExecutionEngine.m_timers) + { + timer->RecoverFromGC(); + } + NANOCLR_FOREACH_NODE_END(); + + //--// + + NANOCLR_FOREACH_NODE(CLR_RT_Thread,th,g_CLR_RT_ExecutionEngine.m_threadsReady) + { + th->RecoverFromGC(); + } + NANOCLR_FOREACH_NODE_END(); + + NANOCLR_FOREACH_NODE(CLR_RT_Thread,th,g_CLR_RT_ExecutionEngine.m_threadsWaiting) + { + th->RecoverFromGC(); + } + NANOCLR_FOREACH_NODE_END(); + + NANOCLR_FOREACH_NODE(CLR_RT_Thread,th,g_CLR_RT_ExecutionEngine.m_threadsZombie) + { + th->RecoverFromGC(); + th->ReleaseWhenDeadEx(); // After the GC has happened, we have to check if any zombie thread can be reclaimed. + } + NANOCLR_FOREACH_NODE_END(); + +#if defined(NANOCLR_APPDOMAINS) + NANOCLR_FOREACH_NODE(CLR_RT_AppDomain,appDomain,g_CLR_RT_ExecutionEngine.m_appDomains) + { + appDomain->RecoverFromGC(); + } + NANOCLR_FOREACH_NODE_END(); +#endif +} + +//--// + +CLR_UINT32 CLR_RT_GarbageCollector::Heap_ComputeAliveVsDeadRatio() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_UINT32 totalBytes = 0; + CLR_UINT32 freeBlocks = 0; + + NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster,hc,g_CLR_RT_ExecutionEngine.m_heap) + { + CLR_RT_HeapBlock_Node* ptr = hc->m_payloadStart; + CLR_RT_HeapBlock_Node* end = hc->m_payloadEnd; + + totalBytes += (CLR_UINT32)((CLR_UINT8*)end - (CLR_UINT8*)ptr); + + NANOCLR_FOREACH_NODE_BACKWARD(CLR_RT_HeapBlock_Node,ptrFree,hc->m_freeList) + { + freeBlocks += ptrFree->DataSize(); + } + NANOCLR_FOREACH_NODE_BACKWARD_END(); + } + NANOCLR_FOREACH_NODE_END(); + + m_totalBytes = totalBytes; + m_freeBytes = freeBlocks * sizeof(CLR_RT_HeapBlock); + + return m_freeBytes; +} + diff --git a/source/native/nf-interpreter/src/CLR/Core/GarbageCollector_Compaction.cpp b/source/native/nf-interpreter/src/CLR/Core/GarbageCollector_Compaction.cpp new file mode 100644 index 00000000..82596063 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/GarbageCollector_Compaction.cpp @@ -0,0 +1,467 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +CLR_UINT32 CLR_RT_GarbageCollector::ExecuteCompaction() +{ + NATIVE_PROFILE_CLR_CORE(); +#if defined(NANOCLR_PROFILE_NEW_ALLOCATIONS) + g_CLR_PRF_Profiler.RecordHeapCompactionBegin(); +#endif + +#if defined(NANOCLR_TRACE_MEMORY_STATS) + if(s_CLR_RT_fTrace_MemoryStats >= c_CLR_RT_Trace_Info) + { + CLR_Debug::Printf( "GC: performing heap compaction\r\n" ); + } +#endif + + //////////////////////////////////////////////////////////////////////////////////////////////// + + CLR_RT_ExecutionEngine::ExecutionConstraint_Suspend(); + + Heap_Compact(); + + CLR_RT_ExecutionEngine::ExecutionConstraint_Resume(); + + m_numberOfCompactions++; + + //////////////////////////////////////////////////////////////////////////////////////////////// +#if defined(NANOCLR_PROFILE_NEW_ALLOCATIONS) + g_CLR_PRF_Profiler.RecordHeapCompactionEnd(); +#endif + +#if defined(NANOCLR_TRACE_MEMORY_STATS) + if(s_CLR_RT_fTrace_MemoryStats >= c_CLR_RT_Trace_Info) + { + CLR_Debug::Printf( "GC: heap compaction completed\r\n" ); + } +#endif + + return 0; +} + +//////////////////////////////////////////////////////////////////////////////// + +void CLR_RT_GarbageCollector::Heap_Compact() +{ + NATIVE_PROFILE_CLR_CORE(); + + ValidatePointers(); + + //--// + + RelocationRegion relocHelper[ c_minimumSpaceForCompact ]; + const size_t relocMax = ARRAYSIZE(relocHelper); + + Heap_Relocate_Prepare( relocHelper, relocMax ); + + RelocationRegion* relocBlocks = relocHelper; + RelocationRegion* relocCurrent = relocBlocks; + + //--// + + TestPointers_PopulateOld(); + + + CLR_RT_HeapCluster* freeRegion_hc = NULL;; + CLR_RT_HeapBlock_Node* freeRegion = NULL; + + CLR_RT_HeapCluster* currentSource_hc = (CLR_RT_HeapCluster*)g_CLR_RT_ExecutionEngine.m_heap.FirstNode(); + while(currentSource_hc->Next()) + { + CLR_RT_HeapBlock_Node* currentSource = currentSource_hc->m_payloadStart; + CLR_RT_HeapBlock_Node* currentSource_end = currentSource_hc->m_payloadEnd; + + if(!freeRegion) + { + // + // Move to the next first free region. + // + freeRegion_hc = (CLR_RT_HeapCluster*)g_CLR_RT_ExecutionEngine.m_heap.FirstNode(); + while(true) + { + CLR_RT_HeapCluster* freeRegion_hcNext = (CLR_RT_HeapCluster*)freeRegion_hc->Next(); if(!freeRegion_hcNext) break; + + freeRegion = freeRegion_hc->m_freeList.FirstNode(); if(freeRegion->Next()) break; + + freeRegion = NULL; + freeRegion_hc = freeRegion_hcNext; + } + if(!freeRegion) break; + } + + while(true) + { + // + // We can only move backward. + // + if(currentSource < freeRegion) + { + currentSource_hc = freeRegion_hc; + currentSource = freeRegion; + currentSource_end = freeRegion_hc->m_payloadEnd; + } + + while(currentSource < currentSource_end && currentSource->IsFlagSet( CLR_RT_HeapBlock::HB_Unmovable )) + { + currentSource += currentSource->DataSize(); + } + + if(currentSource == currentSource_end) break; + + ////////////////////////////////////////////////////// + // + // At this point, we have at least ONE movable block. + // + ////////////////////////////////////////////////////// + +#if NANOCLR_VALIDATE_HEAP >= NANOCLR_VALIDATE_HEAP_4_CompactionPlus + if(IsBlockInFreeList( g_CLR_RT_ExecutionEngine.m_heap, freeRegion, true ) == false) + { + CLR_Debug::Printf( "'freeRegion' is not in a free list!! %08x\r\n", freeRegion ); + + NANOCLR_DEBUG_STOP(); + } + + if(IsBlockInFreeList( g_CLR_RT_ExecutionEngine.m_heap, currentSource, false )) + { + CLR_Debug::Printf( "'currentSource' is in a free list!! %08x\r\n", currentSource ); + + NANOCLR_DEBUG_STOP(); + } +#endif + + if(m_relocCount >= relocMax) + { + ValidateHeap( g_CLR_RT_ExecutionEngine.m_heap ); + + Heap_Relocate(); + + ValidateHeap( g_CLR_RT_ExecutionEngine.m_heap ); + + relocBlocks = m_relocBlocks; + relocCurrent = relocBlocks; + + TestPointers_PopulateOld(); + } + + { + CLR_UINT32 move = 0; + CLR_UINT32 freeRegion_Size = freeRegion->DataSize(); + bool fSlide; + + relocCurrent->m_destination = (CLR_UINT8*)freeRegion; + relocCurrent->m_start = (CLR_UINT8*)currentSource; + relocCurrent->m_offset = (CLR_UINT32)(relocCurrent->m_destination - relocCurrent->m_start); + + + // + // Are the free block and the last moved block adjacent? + // + if(currentSource == freeRegion + freeRegion_Size) + { + while(currentSource < currentSource_end && currentSource->IsFlagSet( CLR_RT_HeapBlock::HB_Unmovable ) == false) + { + CLR_UINT32 len = currentSource->DataSize(); + + currentSource += len; + move += len; + } + + fSlide = true; + } + else + { + while(freeRegion_Size && currentSource < currentSource_end && currentSource->IsFlagSet( CLR_RT_HeapBlock::HB_Unmovable ) == false) + { + CLR_UINT32 len = currentSource->DataSize(); + + if(freeRegion_Size < len) + { + break; + } + + freeRegion_Size -= len; + currentSource += len; + move += len; + } + + fSlide = false; + } + + if(move) + { + // + // Skip forward to the next movable block. + // + while(currentSource < currentSource_end && currentSource->IsFlagSet( CLR_RT_HeapBlock::HB_Unmovable )) + { + currentSource += currentSource->DataSize(); + } + + CLR_UINT32 moveBytes = move * sizeof(*currentSource); + + relocCurrent->m_end = relocCurrent->m_start + moveBytes; + + //--// + + // + // Remove the old free block, copy the data, recreate the new free block. + // Merge with the following one if they are adjacent now. + // + CLR_RT_HeapBlock_Node* freeRegionNext = freeRegion->Next(); + + freeRegion->Unlink(); + + memmove( relocCurrent->m_destination, relocCurrent->m_start, moveBytes ); + + if(freeRegion_Size) + { + + freeRegion = freeRegion_hc->InsertInOrder( freeRegion + move, freeRegion_Size ); + + } + else + { + freeRegion = freeRegionNext; + + } + + if(fSlide == false) + { + CLR_RT_HeapBlock_Node* dst = currentSource_hc->InsertInOrder( (CLR_RT_HeapBlock_Node*)relocCurrent->m_start, move ); + + if(dst < freeRegion && freeRegion < (dst + dst->DataSize())) + { + freeRegion = dst; + } + + } + + CLR_RT_GarbageCollector::ValidateCluster( currentSource_hc ); + CLR_RT_GarbageCollector::ValidateCluster( freeRegion_hc ); + + relocCurrent++; + m_relocCount++; + } + else + { + freeRegion = freeRegion->Next(); + + } + + if(freeRegion->Next() == NULL) + { + + freeRegion = NULL; + freeRegion_hc = (CLR_RT_HeapCluster*)freeRegion_hc->Next(); + while(true) + { + CLR_RT_HeapCluster* freeRegion_hcNext = (CLR_RT_HeapCluster*)freeRegion_hc->Next(); if(!freeRegion_hcNext) break; + + freeRegion = freeRegion_hc->m_freeList.FirstNode(); if(freeRegion->Next()) break; + + freeRegion = NULL; + freeRegion_hc = freeRegion_hcNext; + } + if(!freeRegion) break; + + } + } + } + + currentSource_hc = (CLR_RT_HeapCluster*)currentSource_hc->Next(); + } + + if(m_relocCount) + { + ValidateHeap( g_CLR_RT_ExecutionEngine.m_heap ); + + Heap_Relocate(); + + ValidateHeap( g_CLR_RT_ExecutionEngine.m_heap ); + } +} + +void CLR_RT_GarbageCollector::Heap_Relocate_Prepare( RelocationRegion* blocks, size_t total ) +{ + NATIVE_PROFILE_CLR_CORE(); + m_relocBlocks = blocks; + m_relocTotal = total; + m_relocCount = 0; +} + +void CLR_RT_GarbageCollector::Heap_Relocate_AddBlock( CLR_UINT8* dst, CLR_UINT8* src, CLR_UINT32 length ) +{ + NATIVE_PROFILE_CLR_CORE(); + RelocationRegion* reloc = m_relocBlocks; + size_t count = m_relocCount; + + while(count) + { + if(reloc->m_start > src) + { + // + // Insert region, so they are sorted by start address. + // + memmove( &reloc[ 1 ], &reloc[ 0 ], count * sizeof(*reloc) ); + break; + } + + reloc++; + count--; + } + + reloc->m_start = src; + reloc->m_end = &src[ length ]; + reloc->m_destination = dst; + reloc->m_offset = (CLR_UINT32)(dst - src); + + if(++m_relocCount == m_relocTotal) + { + Heap_Relocate(); + } +} + +void CLR_RT_GarbageCollector::Heap_Relocate() +{ + NATIVE_PROFILE_CLR_CORE(); + if(m_relocCount) + { + RelocationRegion* relocBlocks = m_relocBlocks; + + CLR_UINT8* relocMinimum = relocBlocks->m_start; + CLR_UINT8* relocMaximum = relocBlocks->m_end; + + for(size_t i=0; i relocBlocks->m_start) relocMinimum = relocBlocks->m_start; + if(relocMaximum < relocBlocks->m_end ) relocMaximum = relocBlocks->m_end; + } + + m_relocMinimum = relocMinimum; + m_relocMaximum = relocMaximum; + + TestPointers_Remap(); + + Heap_Relocate_Pass( NULL ); + +#if defined(NANOCLR_PROFILE_NEW_ALLOCATIONS) + g_CLR_PRF_Profiler.TrackObjectRelocation(); +#endif + + ValidatePointers(); + + TestPointers_PopulateNew(); + + m_relocCount = 0; + } +} + +void CLR_RT_GarbageCollector::Heap_Relocate_Pass( RelocateFtn ftn ) +{ + NATIVE_PROFILE_CLR_CORE(); + + #if NANOCLR_VALIDATE_HEAP > NANOCLR_VALIDATE_HEAP_0_None + m_relocWorker = ftn; + #else + (void)ftn; + #endif + + NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster,hc,g_CLR_RT_ExecutionEngine.m_heap) + { + CLR_RT_HeapBlock_Node* ptr = hc->m_payloadStart; + CLR_RT_HeapBlock_Node* end = hc->m_payloadEnd; + + + while(ptr < end) + { + CLR_RT_HEAPBLOCK_RELOCATE(ptr); + + ptr += ptr->DataSize(); + } + } + NANOCLR_FOREACH_NODE_END(); + + g_CLR_RT_ExecutionEngine.Relocate(); +} + +//--// + +void CLR_RT_GarbageCollector::Heap_Relocate( CLR_RT_HeapBlock* lst, CLR_UINT32 len ) +{ + NATIVE_PROFILE_CLR_CORE(); + while(len--) + { + CLR_RT_HEAPBLOCK_RELOCATE(lst); + + lst++; + } +} + +void CLR_RT_GarbageCollector::Heap_Relocate( void** ref ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_UINT8* dst = (CLR_UINT8*)*ref; + +#if NANOCLR_VALIDATE_HEAP > NANOCLR_VALIDATE_HEAP_0_None + if(g_CLR_RT_GarbageCollector.m_relocWorker) + { + g_CLR_RT_GarbageCollector.m_relocWorker( ref ); + } + else +#endif + { + if(dst >= g_CLR_RT_GarbageCollector.m_relocMinimum && dst < g_CLR_RT_GarbageCollector.m_relocMaximum) + { + RelocationRegion* relocBlocks = g_CLR_RT_GarbageCollector.m_relocBlocks; + size_t left = 0; + size_t right = g_CLR_RT_GarbageCollector.m_relocCount; + + while(left < right) + { + size_t center = (left + right) / 2; + RelocationRegion& relocCurrent = relocBlocks[ center ]; + + if(dst < relocCurrent.m_start) + { + right = center; + } + else if(dst >= relocCurrent.m_end) + { + left = center+1; + } + else + { + *ref = (void*)(dst + relocCurrent.m_offset); + + return; + } + } + } + } +} + +#if NANOCLR_VALIDATE_HEAP >= NANOCLR_VALIDATE_HEAP_3_Compaction + +bool CLR_RT_GarbageCollector::Relocation_JustCheck( void** ref ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_UINT8* dst = (CLR_UINT8*)*ref; + + if(dst) + { + ValidateBlockNotInFreeList( g_CLR_RT_ExecutionEngine.m_heap, (CLR_RT_HeapBlock_Node*)dst ); + } + + return true; +} + +#endif + diff --git a/source/native/nf-interpreter/src/CLR/Core/GarbageCollector_ComputeReachabilityGraph.cpp b/source/native/nf-interpreter/src/CLR/Core/GarbageCollector_ComputeReachabilityGraph.cpp new file mode 100644 index 00000000..5e8ac82b --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/GarbageCollector_ComputeReachabilityGraph.cpp @@ -0,0 +1,300 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//--// + +void CLR_RT_GarbageCollector::MarkStack::Initialize( MarkStackElement* ptr, size_t num ) +{ + NATIVE_PROFILE_CLR_CORE(); + GenericNode_Initialize(); + + m_last = &ptr[ num-1 ]; + m_top = ptr; + + // + // Empty element to act a sentinel. + // + ptr->ptr = NULL; + ptr->num = 0; +#if defined(NANOCLR_VALIDATE_APPDOMAIN_ISOLATION) + ptr->appDomain = NULL; +#endif +} + +//--// + +bool CLR_RT_GarbageCollector::ComputeReachabilityGraphForSingleBlock( CLR_RT_HeapBlock** ptr ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock* obj = *ptr; if(obj == NULL || obj->IsAlive()) return true; + + return ComputeReachabilityGraphForMultipleBlocks( obj, 1 ); +} + + +bool CLR_RT_GarbageCollector::ComputeReachabilityGraphForMultipleBlocks( CLR_RT_HeapBlock* lst, CLR_UINT32 num ) +{ + NATIVE_PROFILE_CLR_CORE(); + + MarkStack * stackList; + MarkStackElement* stack; + MarkStackElement* stackLast; + +#define COMPUTEREACHABILITY_LOADSTATE() stackLast = g_CLR_RT_GarbageCollector.m_markStack->m_last; stack = g_CLR_RT_GarbageCollector.m_markStack->m_top; stackList = g_CLR_RT_GarbageCollector.m_markStack; +#define COMPUTEREACHABILITY_SAVESTATE() g_CLR_RT_GarbageCollector.m_markStack->m_last = stackLast; g_CLR_RT_GarbageCollector.m_markStack->m_top = stack; g_CLR_RT_GarbageCollector.m_markStack = stackList; + + COMPUTEREACHABILITY_LOADSTATE(); + + { + CLR_RT_HeapBlock* sub = NULL; + + while(true) + { + CLR_RT_HeapBlock* ptr = lst; + + if(num == 0) + { + if(stack->num == 0) + { + MarkStack* stackNext = (MarkStack*)stackList->Prev(); + + //finished with this MarkStack + if(stackNext->Prev() == NULL) + { + //finished marking + break; + } + else + { + COMPUTEREACHABILITY_SAVESTATE(); + g_CLR_RT_GarbageCollector.m_markStack = stackNext; + COMPUTEREACHABILITY_LOADSTATE(); + } + } + + ptr = stack->ptr; + + stack->ptr++; + stack->num--; + + if(stack->num == 0) + { + stack--; + +#if defined(NANOCLR_VALIDATE_APPDOMAIN_ISOLATION) + (void)g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( stack->appDomain ); +#endif + } + } + else if(num > 1) + { + if(stack == stackLast) + { + MarkStack* stackNext = (MarkStack*)stackList->Next(); + + if(stackNext->Next() != NULL) + { + COMPUTEREACHABILITY_SAVESTATE(); + g_CLR_RT_GarbageCollector.m_markStack = stackNext; + COMPUTEREACHABILITY_LOADSTATE(); + } + else + { + //try to allocate another stack list... + stackNext = NULL; + + //If there was no space for GC last time, don't bother trying to allocate again + if(!g_CLR_RT_GarbageCollector.m_fOutOfStackSpaceForGC) + { + for(int cElement = g_CLR_RT_GarbageCollector.c_minimumSpaceForGC; cElement >= 1; cElement /= 2) + { + CLR_UINT32 size = sizeof(MarkStack) + sizeof(MarkStackElement) * cElement; + + stackNext = (MarkStack*)CLR_RT_Memory::Allocate( size, CLR_RT_HeapBlock::HB_SpecialGCAllocation ); + + if(stackNext) + { + COMPUTEREACHABILITY_SAVESTATE(); + + stackNext->Initialize( (MarkStackElement*)(&stackNext[ 1 ]), (size_t)cElement ); + + g_CLR_RT_GarbageCollector.m_markStackList->LinkAtBack( stackNext ); + + g_CLR_RT_GarbageCollector.m_markStack = stackNext; + + COMPUTEREACHABILITY_LOADSTATE(); + + break; + } + } + } + + if(stackNext == NULL) + { + //Out of stack support space + //Set the failure flag and continue, ignoring lst, num + //The mark will complete later via MarkSlow + + g_CLR_RT_GarbageCollector.m_fOutOfStackSpaceForGC = true; + + lst = NULL; + num = 0; + continue; + } + } + } + + stack++; + + stack->ptr = lst+1; + stack->num = num-1; + +#if defined(NANOCLR_VALIDATE_APPDOMAIN_ISOLATION) + stack->appDomain = g_CLR_RT_ExecutionEngine.GetCurrentAppDomain(); +#endif + } + + + { + + lst = NULL; + num = 0; + + CLR_RT_HeapBlock::Debug_CheckPointer( ptr ); + + ptr->MarkAlive(); + + switch(ptr->DataType()) + { + case DATATYPE_OBJECT: + case DATATYPE_BYREF: + sub = ptr->Dereference(); + break; + + //--// + + #if defined(NANOCLR_APPDOMAINS) + case DATATYPE_TRANSPARENT_PROXY: + { + CLR_RT_AppDomain* appDomain = ptr->TransparentProxyAppDomain(); + + if(appDomain) + { + if(!appDomain->IsLoaded()) + { + //If the AppDomain is unloading, we no longer need to keep the reference around + ptr->SetTransparentProxyReference( NULL, NULL ); + } + else + { + #if defined(NANOCLR_VALIDATE_APPDOMAIN_ISOLATION) + (void)g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( ptr->TransparentProxyAppDomain() ); + #endif + sub = ptr->TransparentProxyDereference(); + } + } + } + break; + #endif + + //--// + + case DATATYPE_ARRAY_BYREF: + sub = (CLR_RT_HeapBlock*)ptr->Array(); + break; + + //--// + + case DATATYPE_CLASS: + case DATATYPE_VALUETYPE: + // + // This is the real object, mark all its fields. + // + lst = ptr + 1; + num = ptr->DataSize() - 1; + break; + + case DATATYPE_SZARRAY: + // + // If the array is full of reference types, mark each of them. + // + { + CLR_RT_HeapBlock_Array* array = (CLR_RT_HeapBlock_Array*)ptr; + + if(array->m_fReference) + { + lst = (CLR_RT_HeapBlock*)array->GetFirstElement(); + num = array->m_numOfElements; + } + } + break; + + case DATATYPE_REFLECTION: + break; + + case DATATYPE_DELEGATE_HEAD: + { + CLR_RT_HeapBlock_Delegate* dlg = (CLR_RT_HeapBlock_Delegate*)ptr; + + lst = &dlg->m_object; + num = 1; + } + break; + + case DATATYPE_BINARY_BLOB_HEAD: + { + CLR_RT_HeapBlock_BinaryBlob* blob = (CLR_RT_HeapBlock_BinaryBlob*)ptr; + + _ASSERTE(blob->BinaryBlobMarkingHandler() == NULL); + } + break; + + case DATATYPE_DELEGATELIST_HEAD: + { + CLR_RT_HeapBlock_Delegate_List* dlgList = (CLR_RT_HeapBlock_Delegate_List*)ptr; + + if(dlgList->m_flags & CLR_RT_HeapBlock_Delegate_List::c_Weak) + { + dlgList->ClearData(); + + g_CLR_RT_GarbageCollector.m_weakDelegates_Reachable.LinkAtBack( dlgList ); + } + else + { + lst = dlgList->GetDelegates(); + num = dlgList->m_length; + } + } + break; + + default: + // the remaining data types aren't to be handled + break; + } + + if(sub) + { + if(sub->IsAlive() == false) + { + lst = sub; + num = 1; + } + + sub = NULL; + } + + } + } + } + + COMPUTEREACHABILITY_SAVESTATE(); + + return true; +} + +//--// + diff --git a/source/native/nf-interpreter/src/CLR/Core/GarbageCollector_Info.cpp b/source/native/nf-interpreter/src/CLR/Core/GarbageCollector_Info.cpp new file mode 100644 index 00000000..741567c7 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/GarbageCollector_Info.cpp @@ -0,0 +1,322 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#if defined(NANOCLR_GC_VERBOSE) + +void CLR_RT_GarbageCollector::GC_Stats( int& resNumberObjects, int& resSizeObjects, int& resNumberEvents, int& resSizeEvents ) +{ + NATIVE_PROFILE_CLR_CORE(); + resNumberObjects = 0; + resSizeObjects = 0; + + resNumberEvents = 0; + resSizeEvents = 0; + + NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster,hc,g_CLR_RT_ExecutionEngine.m_heap) + { + CLR_RT_HeapBlock_Node* ptr = hc->m_payloadStart; + CLR_RT_HeapBlock_Node* end = hc->m_payloadEnd; + + while(ptr < end) + { + CLR_UINT16 size = ptr->DataSize(); + + hc->ValidateBlock( ptr ); + + if(ptr->DataType() != DATATYPE_FREEBLOCK) + { + if(ptr->IsEvent()) + { + resNumberEvents += 1; + resSizeEvents += size * sizeof(CLR_RT_HeapBlock); + } + else + { + resNumberObjects += 1; + resSizeObjects += size * sizeof(CLR_RT_HeapBlock); + } + } + + ptr += size; + } + } + NANOCLR_FOREACH_NODE_END(); +} + + +static void DumpTimeout( CLR_RT_Thread* th, CLR_INT64& t ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_Debug::Printf( ": %d", th ? th->m_pid : -1 ); + + if(t < TIMEOUT_INFINITE) + { + t -= HAL_Time_CurrentTime(); + + CLR_Debug::Printf( " %d", (int)t ); + } + else + { + CLR_Debug::Printf( " INFINITE" ); + } +} + +void CLR_RT_GarbageCollector::DumpThreads() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_NODE(CLR_RT_Thread,th,g_CLR_RT_ExecutionEngine.m_threadsReady) + { + th->DumpStack(); + } + NANOCLR_FOREACH_NODE_END(); + + NANOCLR_FOREACH_NODE(CLR_RT_Thread,th,g_CLR_RT_ExecutionEngine.m_threadsWaiting) + { + th->DumpStack(); + } + NANOCLR_FOREACH_NODE_END(); + + CLR_Debug::Printf( "\r\n" ); +} +#endif + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#if NANOCLR_VALIDATE_HEAP >= NANOCLR_VALIDATE_HEAP_3_Compaction + +void CLR_RT_GarbageCollector::ValidateCluster( CLR_RT_HeapCluster* hc ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock_Node* ptr = hc->m_payloadStart; + CLR_RT_HeapBlock_Node* end = hc->m_payloadEnd; + + while(ptr < end) + { + hc->ValidateBlock( ptr ); + + ptr += ptr->DataSize(); + } +} + +void CLR_RT_GarbageCollector::ValidateHeap( CLR_RT_DblLinkedList& lst ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster,hc,lst) + { + ValidateCluster( hc ); + } + NANOCLR_FOREACH_NODE_END(); +} + +void CLR_RT_GarbageCollector::ValidateBlockNotInFreeList( CLR_RT_DblLinkedList& lst, CLR_RT_HeapBlock_Node* dst ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster,hc,lst) + { + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Node,ptr,hc->m_freeList) + { + CLR_RT_HeapBlock_Node* ptrEnd = ptr + ptr->DataSize(); + + if(ptr <= dst && dst < ptrEnd) + { + CLR_Debug::Printf( "Pointer into free list!! %08x %08x %08x\r\n", dst, ptr, ptrEnd ); + + NANOCLR_DEBUG_STOP(); + } + } + NANOCLR_FOREACH_NODE_END(); + } + NANOCLR_FOREACH_NODE_END(); +} + +bool CLR_RT_GarbageCollector::IsBlockInFreeList( CLR_RT_DblLinkedList& lst, CLR_RT_HeapBlock_Node* dst, bool fExact ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster,hc,lst) + { + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Node,ptr,hc->m_freeList) + { + if(fExact) + { + if(ptr == dst) return true; + } + else + { + CLR_RT_HeapBlock_Node* ptrEnd = ptr + ptr->DataSize(); + + if(ptr <= dst && dst < ptrEnd) return true; + } + } + NANOCLR_FOREACH_NODE_END(); + } + NANOCLR_FOREACH_NODE_END(); + + return false; +} + +bool CLR_RT_GarbageCollector::IsBlockInHeap( CLR_RT_DblLinkedList& lst, CLR_RT_HeapBlock_Node* dst ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster,hc,lst) + { + if(hc->m_payloadStart <= dst && dst < hc->m_payloadEnd) return true; + } + NANOCLR_FOREACH_NODE_END(); + + return false; +} + +#endif + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#if NANOCLR_VALIDATE_HEAP >= NANOCLR_VALIDATE_HEAP_4_CompactionPlus + +CLR_RT_GarbageCollector::Rel_List CLR_RT_GarbageCollector::s_lstRecords; +CLR_RT_GarbageCollector::Rel_Map CLR_RT_GarbageCollector::s_mapOldToRecord; +CLR_RT_GarbageCollector::Rel_Map CLR_RT_GarbageCollector::s_mapNewToRecord; + +//--// + +bool CLR_RT_GarbageCollector::TestPointers_PopulateOld_Worker( void** ref ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_UINT32* dst = (CLR_UINT32*)*ref; + + if(dst) + { + RelocationRecord* ptr = new RelocationRecord(); + + s_lstRecords.push_back( ptr ); + + ptr->oldRef = ref; + ptr->oldPtr = dst; + + ptr->newRef = NULL; + ptr->newPtr = NULL; + + ptr->data = *dst; + + if(s_mapOldToRecord.find( ref ) != s_mapOldToRecord.end()) + { + CLR_Debug::Printf( "Duplicate base OLD: %08x\r\n", ref ); + } + + s_mapOldToRecord[ ref ] = ptr; + + if(IsBlockInFreeList( g_CLR_RT_ExecutionEngine.m_heap, (CLR_RT_HeapBlock_Node*)dst, false )) + { + CLR_Debug::Printf( "Some data points into a free list: %08x\r\n", dst ); + + NANOCLR_DEBUG_STOP(); + } + } + + return false; +} + +void CLR_RT_GarbageCollector::TestPointers_PopulateOld() +{ + NATIVE_PROFILE_CLR_CORE(); + Rel_List_Iter itLst; + + for(itLst = s_lstRecords.begin(); itLst != s_lstRecords.end(); itLst++) + { + RelocationRecord* ptr = *itLst; + + delete ptr; + } + + s_lstRecords .clear(); + s_mapOldToRecord.clear(); + s_mapNewToRecord.clear(); + + //--// + + Heap_Relocate_Pass( TestPointers_PopulateOld_Worker ); +} + +void CLR_RT_GarbageCollector::Relocation_UpdatePointer(void** ref) +{ + NATIVE_PROFILE_CLR_CORE(); + +} + +//--// + +void CLR_RT_GarbageCollector::TestPointers_Remap() +{ + NATIVE_PROFILE_CLR_CORE(); + Rel_Map_Iter it; + + for(it = s_mapOldToRecord.begin(); it != s_mapOldToRecord.end(); it++) + { + RelocationRecord* ptr = it->second; + void** ref = it->first ; CLR_RT_GarbageCollector::Relocation_UpdatePointer( (void**)&ref ); + CLR_UINT32* dst = ptr->oldPtr; CLR_RT_GarbageCollector::Relocation_UpdatePointer( (void**)&dst ); + + if(s_mapNewToRecord.find( ref ) != s_mapNewToRecord.end()) + { + CLR_Debug::Printf( "Duplicate base NEW: %08x\r\n", ref ); + } + + s_mapNewToRecord[ ref ] = ptr; + + ptr->newRef = ref; + ptr->newPtr = dst; + } +} + +//--// + +bool CLR_RT_GarbageCollector::TestPointers_PopulateNew_Worker( void** ref ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_UINT32* dst = (CLR_UINT32*)*ref; + + if(dst) + { + Rel_Map_Iter it = s_mapNewToRecord.find( ref ); + + if(it != s_mapNewToRecord.end()) + { + RelocationRecord* ptr = it->second; + + if(ptr->newPtr != dst) + { + CLR_Debug::Printf( "Bad pointer: %08x %08x\r\n", ptr->newPtr, dst ); + } + else if(ptr->data != *dst) + { + CLR_Debug::Printf( "Bad data: %08x %08x\r\n", ptr->data, *dst ); + } + + if(IsBlockInFreeList( g_CLR_RT_ExecutionEngine.m_heap, (CLR_RT_HeapBlock_Node*)dst, false )) + { + CLR_Debug::Printf( "Some data points into a free list: %08x\r\n", dst ); + + NANOCLR_DEBUG_STOP(); + } + } + else + { + CLR_Debug::Printf( "Bad base: %08x\r\n", ref ); + } + } + + return false; +} + +void CLR_RT_GarbageCollector::TestPointers_PopulateNew() +{ + NATIVE_PROFILE_CLR_CORE(); + Heap_Relocate_Pass( TestPointers_PopulateNew_Worker ); +} + +#endif diff --git a/source/native/nf-interpreter/src/CLR/Core/Hardware/Hardware-vs2019.vcxproj b/source/native/nf-interpreter/src/CLR/Core/Hardware/Hardware-vs2019.vcxproj new file mode 100644 index 00000000..a19015d7 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Hardware/Hardware-vs2019.vcxproj @@ -0,0 +1,159 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + {5D50772E-DAC8-407D-972F-37DEB4450B72} + Win32Proj + Hardware + 10.0.17763.0 + Hardware + + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + false + v142 + true + Unicode + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + false + v142 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(SolutionDir)$(Configuration)\ + $(IntDir) + + + $(SolutionDir)$(Configuration)\ + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/Hardware/Hardware-vs2019.vcxproj.filters b/source/native/nf-interpreter/src/CLR/Core/Hardware/Hardware-vs2019.vcxproj.filters new file mode 100644 index 00000000..c750e915 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Hardware/Hardware-vs2019.vcxproj.filters @@ -0,0 +1,22 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/Hardware/Hardware.cpp b/source/native/nf-interpreter/src/CLR/Core/Hardware/Hardware.cpp new file mode 100644 index 00000000..1c8c2a56 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Hardware/Hardware.cpp @@ -0,0 +1,175 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +HRESULT CLR_HW_Hardware::CreateInstance() +{ + NATIVE_PROFILE_CLR_HARDWARE(); + + NANOCLR_HEADER(); + + NANOCLR_CLEAR(g_CLR_HW_Hardware); + + g_CLR_HW_Hardware.m_fInitialized = false; + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT CLR_HW_Hardware::Hardware_Initialize() +{ + NATIVE_PROFILE_CLR_HARDWARE(); + + NANOCLR_HEADER(); + + if(m_fInitialized == false) + { + Time_Initialize(); + + m_interruptData.m_HalQueue.Initialize( (CLR_HW_Hardware::HalInterruptRecord*)&g_scratchInterruptDispatchingStorage, InterruptRecords() ); + + m_interruptData.m_applicationQueue.DblLinkedList_Initialize (); + + m_interruptData.m_queuedInterrupts = 0; + + m_DebuggerEventsMask = 0; + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + m_DebuggerEventsMask |= ExtractEventFromTransport( HalSystemConfig.DebuggerPort ); +#endif + + m_wakeupEvents = c_Default_WakeupEvents | m_DebuggerEventsMask; + m_powerLevel = PowerLevel__Active; + + m_fInitialized = true; + } + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +//--// + +HRESULT CLR_HW_Hardware::DeleteInstance() +{ + NATIVE_PROFILE_CLR_HARDWARE(); + + NANOCLR_HEADER(); + + g_CLR_HW_Hardware.Hardware_Cleanup(); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +void CLR_HW_Hardware::Hardware_Cleanup() +{ + NATIVE_PROFILE_CLR_HARDWARE(); + + if(m_fInitialized == true) + { + m_fInitialized = false; + } +} + +//--// + +void CLR_HW_Hardware::PrepareForGC() +{ + NATIVE_PROFILE_CLR_HARDWARE(); +} + +void CLR_HW_Hardware::ProcessActivity() +{ + NATIVE_PROFILE_CLR_HARDWARE(); + + for(int i=0; i<10; i++) + { + if(!HAL_CONTINUATION::Dequeue_And_Execute()) break; + } + + // UNDONE: FIXME: + //if(!msg.IsDebuggerInitialized()) + //{ + // msg.InitializeDebugger(); + //} + // UNDONE: FIXME:msg.PurgeCache(); + + // UNDONE: FIXME:dbg.PurgeCache(); + + uint32_t events = ::Events_Get( m_wakeupEvents ); + uint32_t eventsCLR = 0; + + if(events & m_DebuggerEventsMask) + { + //dbg.ProcessCommands(); + +#if defined(PLATFORM_ARM) || defined(PLATFORM_ESP32) + if(CLR_EE_DBG_IS(RebootPending)) + { +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Rebooting...\r\n" ); +#endif + + if(!CLR_EE_REBOOT_IS(ClrOnly)) + { + CLR_RT_ExecutionEngine::Reboot( false ); + } + } +#endif + } + + if(events & SYSTEM_EVENT_FLAG_COM_IN) + { + eventsCLR |= CLR_RT_ExecutionEngine::c_Event_SerialPortIn; + } + + if(events & SYSTEM_EVENT_FLAG_COM_OUT) + { + eventsCLR |= CLR_RT_ExecutionEngine::c_Event_SerialPortOut; + } + + if((events & SYSTEM_EVENT_HW_INTERRUPT) +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + || (!CLR_EE_DBG_IS(Stopped) && !g_CLR_HW_Hardware.m_interruptData.m_applicationQueue.IsEmpty()) +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + ) + { + ProcessInterrupts(); + } + + if(events & SYSTEM_EVENT_FLAG_SOCKET) + { + eventsCLR |= CLR_RT_ExecutionEngine::c_Event_Socket; + } + + if(events & SYSTEM_EVENT_FLAG_SPI_MASTER) + { + eventsCLR |= CLR_RT_ExecutionEngine::c_Event_SpiMaster; + } + + if(events & SYSTEM_EVENT_FLAG_I2C_MASTER) + { + eventsCLR |= CLR_RT_ExecutionEngine::c_Event_I2cMaster; + } + + if(events & SYSTEM_EVENT_FLAG_ONEWIRE_MASTER) + { + eventsCLR |= CLR_RT_ExecutionEngine::c_Event_OneWireMaster; + } + + if(events & SYSTEM_EVENT_FLAG_STORAGE_IO) + { + eventsCLR |= CLR_RT_ExecutionEngine::c_Event_StorageIo; + } + + if(eventsCLR) + { + g_CLR_RT_ExecutionEngine.SignalEvents( eventsCLR ); + } +} + +//--//--//--//--//--//--//--//--//--//--//--//--//--//--//--//--//--//--//--// + diff --git a/source/native/nf-interpreter/src/CLR/Core/Hardware/Hardware.vcxproj b/source/native/nf-interpreter/src/CLR/Core/Hardware/Hardware.vcxproj new file mode 100644 index 00000000..36a52f5c --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Hardware/Hardware.vcxproj @@ -0,0 +1,158 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + {5D50772E-DAC8-407D-972F-37DEB4450B72} + Win32Proj + Hardware + 10.0.17763.0 + + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\ + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\ + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/Hardware/Hardware.vcxproj.filters b/source/native/nf-interpreter/src/CLR/Core/Hardware/Hardware.vcxproj.filters new file mode 100644 index 00000000..c750e915 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Hardware/Hardware.vcxproj.filters @@ -0,0 +1,22 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/Hardware/Hardware_stub.cpp b/source/native/nf-interpreter/src/CLR/Core/Hardware/Hardware_stub.cpp new file mode 100644 index 00000000..3fef9f29 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Hardware/Hardware_stub.cpp @@ -0,0 +1,51 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +__nfweak HRESULT CLR_HW_Hardware::CreateInstance() +{ + NATIVE_PROFILE_CLR_HARDWARE(); + NANOCLR_HEADER(); + NANOCLR_NOCLEANUP_NOLABEL(); +} + +__nfweak HRESULT CLR_HW_Hardware::Hardware_Initialize() +{ + NATIVE_PROFILE_CLR_HARDWARE(); + NANOCLR_HEADER(); + NANOCLR_NOCLEANUP_NOLABEL(); +} + +//--// + +__nfweak HRESULT CLR_HW_Hardware::DeleteInstance() +{ + NATIVE_PROFILE_CLR_HARDWARE(); + NANOCLR_HEADER(); + NANOCLR_NOCLEANUP_NOLABEL(); +} + +__nfweak void CLR_HW_Hardware::Hardware_Cleanup() +{ + NATIVE_PROFILE_CLR_HARDWARE(); +} + +//--// + +__nfweak void CLR_HW_Hardware::PrepareForGC() +{ + NATIVE_PROFILE_CLR_HARDWARE(); +} + +__nfweak void CLR_HW_Hardware::ProcessActivity() +{ + NATIVE_PROFILE_CLR_HARDWARE(); +} + +//--//--//--//--//--//--//--//--//--//--//--//--//--//--//--//--//--//--//--// + diff --git a/source/native/nf-interpreter/src/CLR/Core/Hardware/Hardware_stub.vcxproj b/source/native/nf-interpreter/src/CLR/Core/Hardware/Hardware_stub.vcxproj new file mode 100644 index 00000000..193572cb --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Hardware/Hardware_stub.vcxproj @@ -0,0 +1,158 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + {31253D7F-147E-49A3-BC0D-E0ADE6CF040B} + Win32Proj + Hardware_stub + 10.0.17763.0 + + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/Hardware/Hardware_stub.vcxproj.filters b/source/native/nf-interpreter/src/CLR/Core/Hardware/Hardware_stub.vcxproj.filters new file mode 100644 index 00000000..d5de8ea4 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Hardware/Hardware_stub.vcxproj.filters @@ -0,0 +1,22 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/Interpreter.cpp b/source/native/nf-interpreter/src/CLR/Core/Interpreter.cpp new file mode 100644 index 00000000..dd7b41d1 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Interpreter.cpp @@ -0,0 +1,3140 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#if defined(NANOCLR_TRACE_EXCEPTIONS) && defined(_WIN32) + +struct BackTrackExecution +{ + CLR_RT_Assembly* m_assm; + CLR_RT_MethodDef_Index m_call; + CLR_PMETADATA m_IPstart; + CLR_PMETADATA m_IP; + int m_pid; + int m_depth; +}; + +static BackTrackExecution s_track[ 512 ]; +static int s_trackPos; + +#endif + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#if defined(NANOCLR_TRACE_STACK) + +bool g_CLR_RT_fBadStack; + +#define RESETSTACK() { g_CLR_RT_fBadStack = false; } +#define CHECKSTACK(stack,evalPos) { g_CLR_RT_fBadStack = stack->m_evalStackPos <= evalPos ; } +#define UPDATESTACK(stack,evalPos) { g_CLR_RT_fBadStack = false; stack->m_evalStackPos = &evalPos[ + 1]; } + + +#else + +#define RESETSTACK() +#define CHECKSTACK(stack,evalPos) +#define UPDATESTACK(stack,evalPos) { stack->m_evalStackPos = &evalPos[ +1 ]; } + +#endif + +//--// +#define EMPTYSTACK(stack,evalPos) { evalPos = &stack->m_evalStack [ -1 ]; RESETSTACK(); } +#define READCACHE(stack,evalPos,ip,fDirty) { evalPos = &stack->m_evalStackPos[ -1 ]; ip = stack->m_IP; fDirty = true ; RESETSTACK(); } +#define WRITEBACK(stack,evalPos,ip,fDirty) { stack->m_evalStackPos = &evalPos [ +1 ]; stack->m_IP = ip ; fDirty = false; RESETSTACK(); } + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +bool CLR_RT_HeapBlock::InitObject() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_HeapBlock* obj = this; + CLR_DataType dt = obj->DataType(); + const CLR_RT_DataTypeLookup& dtl = c_CLR_RT_DataTypeLookup[ dt ]; + + if(dtl.m_flags & CLR_RT_DataTypeLookup::c_OptimizedValueType) + { + obj->NumericByRef().u8 = 0; + return false; + } + + if(dt == DATATYPE_VALUETYPE && obj->IsBoxed() == false) + { + CLR_UINT32 num = obj->DataSize(); + + while(--num) + { + (++obj)->InitObject(); + } + + return false; + } + + if(dt == DATATYPE_OBJECT || dt == DATATYPE_BYREF) + { + CLR_RT_HeapBlock* ptr = obj->Dereference(); if(!ptr) return false; + + if(ptr->InitObject() == false) return false; + + obj->SetObjectReference( NULL ); + } + + return true; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +HRESULT CLR_RT_HeapBlock::Convert_Internal( CLR_DataType et ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_DataType dt = DataType(); + const CLR_RT_DataTypeLookup& dtlSrc = c_CLR_RT_DataTypeLookup[ dt ]; + const CLR_RT_DataTypeLookup& dtlDst = c_CLR_RT_DataTypeLookup[ et ]; + int scaleIn; + int scaleOut; + + // + // Extend to maximum precision. + // + switch(dt) + { + case DATATYPE_BOOLEAN : + case DATATYPE_I1 : + case DATATYPE_U1 : + + case DATATYPE_CHAR : + case DATATYPE_I2 : + case DATATYPE_U2 : + + case DATATYPE_I4 : + case DATATYPE_U4 : + { + CLR_UINT64 res = (CLR_UINT64)NumericByRef().u4; + + if((dtlSrc.m_flags & CLR_RT_DataTypeLookup::c_Signed) && (dtlDst.m_flags & CLR_RT_DataTypeLookup::c_Signed)) + { + CLR_UINT32 shift = 64 - dtlSrc.m_sizeInBits; + + res <<= shift; + res = (CLR_UINT64)((CLR_INT64 )res >> shift); + } + + NumericByRef().u8 = res; + } + // + // Fall-through!!! + // + case DATATYPE_I8: + case DATATYPE_U8: + scaleIn = 0; + break; + + case DATATYPE_R4: scaleIn = 1; break; + case DATATYPE_R8: scaleIn = 2; break; + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + //--// + + switch(et) + { + case DATATYPE_R4: scaleOut = 1; break; + case DATATYPE_R8: scaleOut = 2; break; + default : scaleOut = 0; break; + } + + //--// + + if(scaleOut != scaleIn) + { +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + + + double val = 0; + + if((dtlSrc.m_flags & CLR_RT_DataTypeLookup::c_Signed) == 0) scaleIn = -1; + if((dtlDst.m_flags & CLR_RT_DataTypeLookup::c_Signed) == 0) scaleOut = -1; + + switch(scaleIn) + { + case -1: val = (double)((CLR_UINT64_TEMP_CAST)NumericByRef().u8); break; + case 0: val = (double)((CLR_INT64_TEMP_CAST) NumericByRef().s8); break; + case 1: val = (double) NumericByRef().r4; break; + case 2: val = NumericByRef().r8; break; + } + + switch(scaleOut) + { + // Direct casting of negative double to CLR_UINT64 is returns zero for RVDS 3.1 compiler. + // Double cast looks as most portable way. + case -1: NumericByRef().u8 = (CLR_UINT64)(CLR_INT64 )val; break; + case 0: NumericByRef().s8 = (CLR_INT64 )val; break; + case 1: NumericByRef().r4 = (float )val; break; + case 2: NumericByRef().r8 = val; break; + } +#else + CLR_INT64 val = 0; + CLR_INT64 orig = 0; + + if((dtlSrc.m_flags & CLR_RT_DataTypeLookup::c_Signed) == 0) scaleIn = -1; + if((dtlDst.m_flags & CLR_RT_DataTypeLookup::c_Signed) == 0) scaleOut = -1; + + switch(scaleIn) + { + case -1: orig = ((CLR_INT64)((CLR_UINT64_TEMP_CAST)NumericByRef().u8)); val = orig << CLR_RT_HeapBlock::HB_DoubleShift; break; + case 0: orig = ((CLR_INT64)((CLR_INT64_TEMP_CAST) NumericByRef().s8)); val = orig << CLR_RT_HeapBlock::HB_DoubleShift; break; + case 1: orig = ((CLR_INT64)((CLR_INT32) NumericByRef().r4)); val = orig << (CLR_RT_HeapBlock::HB_DoubleShift - CLR_RT_HeapBlock::HB_FloatShift); break; + case 2: orig = ((CLR_INT64) NumericByRef().r8 ); val = orig; break; + } + + switch(scaleOut) + { + // Direct casting of negative double to CLR_UINT64 is returns zero for RVDS 3.1 compiler. + // Double cast looks as most portable way. + case -1: NumericByRef().u8 = (CLR_UINT64)(CLR_INT64 )(val >> CLR_RT_HeapBlock::HB_DoubleShift); break; + case 0: NumericByRef().s8 = (CLR_INT64 ) (val >> CLR_RT_HeapBlock::HB_DoubleShift); break; + case 1: NumericByRef().r4 = (CLR_INT64 ) (val >> (CLR_RT_HeapBlock::HB_DoubleShift - CLR_RT_HeapBlock::HB_FloatShift)); break; + case 2: NumericByRef().r8 = val; break; + } + + if(scaleIn < 1 && scaleOut > 0) + { + switch(scaleOut) + { + case 1: + { + CLR_INT32 r4 = (CLR_INT32)NumericByRef().r4; + + if((orig != (((CLR_INT64)r4) >> CLR_RT_HeapBlock::HB_FloatShift)) || + (orig > 0 && r4 < 0)) + { + NumericByRef().r4 = orig < 0 ? 0x80000000 : 0x7FFFFFFF; + + // + // Uncomment to produce an overflow exception for emulated floating points + // + // NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + } + } + break; + case 2: + { + CLR_INT64 r8 = (CLR_INT64)NumericByRef().r8; + + if((orig != (r8 >> CLR_RT_HeapBlock::HB_DoubleShift)) || + (orig > 0 && r8 < 0)) + { + NumericByRef().r8 = orig < 0 ? ULONGLONGCONSTANT(0x8000000000000000) : ULONGLONGCONSTANT(0x7FFFFFFFFFFFFFFF); + + // + // Uncomment to produce an overflow exception for emulated floating points + // + // NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + } + } + break; + } + } + else if(scaleIn == 2 && scaleOut == 1) + { + CLR_INT32 r4 = (CLR_INT64)NumericByRef().r4; + + if((orig != (((CLR_UINT64)r4) << (CLR_RT_HeapBlock::HB_DoubleShift - CLR_RT_HeapBlock::HB_FloatShift))) || + (orig > 0 && r4 < 0)) + { + NumericByRef().r4 = orig < 0 ? 0x80000000 : 0x7FFFFFFF; + + // + // Uncomment to produce an overflow exception for emulated floating points + // + //NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + } + } +#endif + + } + + //--// + + // + // This takes care of truncations. + // + ChangeDataType( et ); + Promote ( ); + + NANOCLR_NOCLEANUP(); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +CLR_RT_Thread::UnwindStack* CLR_RT_Thread::PushEH() +{ + NATIVE_PROFILE_CLR_CORE(); + if(m_nestedExceptionsPos < (int)ARRAYSIZE(m_nestedExceptions)) + { + memset(&m_nestedExceptions[ m_nestedExceptionsPos ], 0, sizeof(UnwindStack)); + return &m_nestedExceptions[ m_nestedExceptionsPos++ ]; + } + else + { +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "WARNING: TOO MANY NESTED EXCEPTIONS!!\r\n" ); +#endif + // clip the oldest exception in the nest + memmove(&m_nestedExceptions[0], &m_nestedExceptions[1], sizeof(m_nestedExceptions) - sizeof(m_nestedExceptions[0])); + return &m_nestedExceptions[ m_nestedExceptionsPos-1 ]; + } +} + +void CLR_RT_Thread::PopEH_Inner( CLR_RT_StackFrame* stack, CLR_PMETADATA ip ) +{ + NATIVE_PROFILE_CLR_CORE(); + // + // We could be jumping outside of a nested exception handler. + // + if(m_nestedExceptionsPos > 0) + { + // + // Different stack, don't pop. + // + if(m_nestedExceptions[ m_nestedExceptionsPos-1 ].m_stack != stack) return; + + // + // No longer check for same stack since nested exceptions will have different + // stacks + // + while(m_nestedExceptionsPos > 0) + { + UnwindStack& us = m_nestedExceptions[ m_nestedExceptionsPos-1 ]; + + // + // The new target is within the previous handler, don't pop. + // + if(ip && (us.m_currentBlockStart <= ip && ip < us.m_currentBlockEnd)) break; + +#ifndef CLR_NO_IL_INLINE + if(stack->m_inlineFrame) break; +#endif + + m_nestedExceptionsPos--; + } + } +} + +bool CLR_RT_Thread::FindEhBlock( CLR_RT_StackFrame* stack, CLR_PMETADATA from, CLR_PMETADATA to, CLR_RT_ExceptionHandler& eh, bool onlyFinallys) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_Assembly* assm = stack->m_call.m_assm; + CLR_RT_ExceptionHandler* ptrEhExt = NULL; + const CLR_RECORD_EH* ptrEh = NULL; + CLR_UINT32 numEh = 0; + + //FROM is always non-NULL and indicates the current IP + _ASSERTE(from); + //onlyFinallys is false when we're searching for a handler for an exception, and to should be NULL + _ASSERTE(FIMPLIES(!onlyFinallys, to==NULL)); + //onlyFinallys is true in Phase2, endfinally, leave, etc. to is NULL when we want to leave outside of the current stack frame, + //or non-NULL and pointing to an IL instruction that we are going to when finally's, if any, are processed. + +#if defined(NANOCLR_TRACE_EXCEPTIONS) + if(s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Annoying) + { + if(!onlyFinallys || s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Obnoxious) + { + CLR_Debug::Printf( "Unwinding at " ); CLR_RT_DUMP::METHOD( stack->m_call ); CLR_Debug::Printf( " [IP: %04x - %d]\r\n", (size_t)stack->m_IP, (stack->m_IP - stack->m_IPstart) ); + } + } +#endif + + if(stack->m_call.m_target->flags & CLR_RECORD_METHODDEF::MD_HasExceptionHandlers) + { + switch(stack->m_flags & CLR_RT_StackFrame::c_MethodKind_Mask) + { + case CLR_RT_StackFrame::c_MethodKind_Interpreted: + { + CLR_OFFSET ipMethod_Start; + CLR_OFFSET ipMethod_End; + + if(assm->FindMethodBoundaries( stack->m_call.Method(), ipMethod_Start, ipMethod_End )) + { + const CLR_RECORD_EH* ptrEh2; + CLR_UINT32 numEh2; + + CLR_RECORD_EH::ExtractEhFromByteCode( stack->m_IPstart + (ipMethod_End - ipMethod_Start), ptrEh2, numEh2 ); + + ptrEh = ptrEh2; // This allows the compiler to leave ptrEh and numEh in registers... + numEh = numEh2; // This allows the compiler to leave ptrEh and numEh in registers... + } + else + { + return false; + } + + ptrEhExt = NULL; + } + break; + + case CLR_RT_StackFrame::c_MethodKind_Native: + return false; + } + + // + // We're certain there's at least one EH. + // + while(numEh--) + { + if(ptrEh) + { + eh.ConvertFromEH( stack->m_call, stack->m_IPstart, ptrEh++ ); + + ptrEhExt = &eh; + } + +#if defined(NANOCLR_TRACE_EXCEPTIONS) + if(s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Annoying) + { + if(to == NULL || s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Obnoxious) + { + CLR_Debug::Printf( "Checking EH: %04X-%04X => %04X\r\n", (size_t)ptrEhExt->m_tryStart, (size_t)ptrEhExt->m_tryEnd, ptrEhExt->m_handlerStart - stack->m_IPstart ); + } + } +#endif + + if(ptrEhExt->IsFilter() && ptrEhExt->m_userFilterStart <= from && from < ptrEhExt->m_handlerStart) + { + //The IP was in the middle of this EH block's filter. + //Therefore, reset the IP to inside the original try block so we can try the next handler in this sequence: + // Try + // ... //2. set IP to here + // Catch When False + // Catch When False //1. from was in this filter + // Catch ... //3. This is the next EH block, and will be found correctly. + // ... + // End Try + from = ptrEhExt->m_tryStart; + } + else if(from >= ptrEhExt->m_tryStart && from < ptrEhExt->m_tryEnd) + { + if(onlyFinallys) + { + // + // Only execute the finally if this is an exception or we leave the block. + // + if(ptrEhExt->IsFinally() && (!to || (to < ptrEhExt->m_tryStart || to >= ptrEhExt->m_tryEnd))) + { +#if defined(NANOCLR_TRACE_EXCEPTIONS) + if(s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Obnoxious) + { + CLR_Debug::Printf( "Found match for a 'finally'\r\n" ); + } +#endif + + eh = *ptrEhExt; + return true; + } + } + else + { + if(ptrEhExt->IsCatchAll()) + { +#if defined(NANOCLR_TRACE_EXCEPTIONS) + if(s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Annoying) + { + CLR_Debug::Printf( "Found match for a 'catch all'\r\n" ); + } +#endif + + eh = *ptrEhExt; + return true; // Catch all... + } + else + { + if(ptrEhExt->IsFilter() || CLR_RT_ExecutionEngine::IsInstanceOf( m_currentException, ptrEhExt->m_typeFilter )) + { +#if defined(NANOCLR_TRACE_EXCEPTIONS) + if(s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Annoying) + { + if (ptrEhExt->IsFilter()) + { + CLR_Debug::Printf( "Trying a 'filter'\r\n" ); + } + else + { + CLR_Debug::Printf( "Found match for a 'catch'\r\n" ); + } + } +#endif + + eh = *ptrEhExt; + return true; + } + } + } + } + + ptrEhExt++; + } + } + +#if defined(NANOCLR_TRACE_EXCEPTIONS) + if(s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Annoying) + { + if(to == NULL || s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Obnoxious) + { + CLR_Debug::Printf( "No match\r\n" ); + } + } +#endif + + return false; +} + +//--// + +HRESULT CLR_RT_Thread::Execute() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + +#if defined(NANOCLR_APPDOMAINS) + CLR_RT_AppDomain* appDomainSav = g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( this->CurrentAppDomain() ); +#endif + + CLR_RT_Thread* currentThreadSav = g_CLR_RT_ExecutionEngine.m_currentThread; + + g_CLR_RT_ExecutionEngine.m_currentThread = this; + + if(m_currentException.Dereference() != NULL) + { + hr = CLR_E_PROCESS_EXCEPTION; + } + else + { + hr = S_OK; + } + + m_timeQuantumExpired = false; + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + _ASSERTE(!CLR_EE_DBG_IS( Stopped )); +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + ::Events_SetBoolTimer( (bool*)&m_timeQuantumExpired, CLR_RT_Thread::c_TimeQuantum_Milliseconds ); + + while(m_timeQuantumExpired == false && !CLR_EE_DBG_IS( Stopped )) + { + CLR_RT_StackFrame* stack; + + if(SUCCEEDED(hr)) + { + hr = Execute_Inner(); + if(SUCCEEDED(hr)) + { + NANOCLR_LEAVE(); + } + } + + switch(hr) + { + case CLR_E_THREAD_WAITING: + case CLR_E_RESCHEDULE: + NANOCLR_LEAVE(); + + case CLR_E_PROCESS_EXCEPTION: + CLR_RT_DUMP::POST_PROCESS_EXCEPTION( m_currentException ); + break; + + default: // Allocate a new exception. + stack = CurrentFrame(); + if(stack->Prev() != NULL) + { +#if defined(NANOCLR_TRACE_INSTRUCTIONS) && defined(PLATFORM_WINDOWS_EMULATOR) + for(int i = 0; i < ARRAYSIZE(s_track); i++) + { + BackTrackExecution& track = s_track[ (s_trackPos+i) % ARRAYSIZE(s_track) ]; + + CLR_Debug::Printf( " %3d ", track.m_depth ); + + CLR_RT_MethodDef_Instance inst; inst.InitializeFromIndex( track.m_call ); + + //track.m_assm->DumpOpcodeDirect( inst, track.m_IP, track.m_IPstart, track.m_pid ); + } + + CLR_Debug::Printf( "\r\n" ); +#endif + + (void)Library_corlib_native_System_Exception::CreateInstance( m_currentException, hr, stack ); + } + + hr = CLR_E_PROCESS_EXCEPTION; + break; + } + + // + // Process exception. + // + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(CLR_EE_DBG_IS( Stopped )) break; +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + NANOCLR_CHECK_HRESULT(ProcessException()); + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(CLR_EE_DBG_IS( Stopped )) break; +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + if(m_currentException.Dereference() != NULL) { break; } + } + + NANOCLR_SET_AND_LEAVE(CLR_S_QUANTUM_EXPIRED); + + NANOCLR_CLEANUP(); + +#if defined(NANOCLR_APPDOMAINS) + g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( appDomainSav ); +#endif + + g_CLR_RT_ExecutionEngine.m_currentThread = currentThreadSav; + + ::Events_SetBoolTimer( NULL, 0 ); + + NANOCLR_CLEANUP_END(); +} + +HRESULT CLR_RT_Thread::Execute_Inner() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + while(m_timeQuantumExpired == false && !CLR_EE_DBG_IS( Stopped )) + { + CLR_RT_StackFrame *stack = CurrentFrame(); + + #if defined(ENABLE_NATIVE_PROFILER) + if(stack->m_owningThread->m_fNativeProfiled == true) + { + Native_Profiler_Start(); + } + #endif + + if(stack->Prev() == NULL) + { + m_status = CLR_RT_Thread::TH_S_Terminated; + + NANOCLR_SET_AND_LEAVE(CLR_S_THREAD_EXITED); // End of Thread. + } + + if(stack->m_flags & CLR_RT_StackFrame::c_ProcessSynchronize) + { +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(stack->m_flags & CLR_RT_StackFrame::c_InvalidIP) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + // + // Thread cannot run if a lock request is still pending... + // + if(stack->m_flags & (CLR_RT_StackFrame::c_PendingSynchronizeGlobally | CLR_RT_StackFrame::c_PendingSynchronize)) + { + NANOCLR_SET_AND_LEAVE(CLR_E_THREAD_WAITING); + } + + if(stack->m_flags & CLR_RT_StackFrame::c_NeedToSynchronizeGlobally) + { + stack->m_flags &= ~CLR_RT_StackFrame::c_NeedToSynchronizeGlobally; + + if(FAILED(hr = stack->HandleSynchronized( true, true ))) + { + if(hr == CLR_E_THREAD_WAITING) + { + stack->m_flags |= CLR_RT_StackFrame::c_PendingSynchronizeGlobally; + } + + NANOCLR_LEAVE(); + } + + stack->m_flags |= CLR_RT_StackFrame::c_SynchronizedGlobally; + } + + if(stack->m_flags & CLR_RT_StackFrame::c_NeedToSynchronize) + { + stack->m_flags &= ~CLR_RT_StackFrame::c_NeedToSynchronize; + + if(FAILED(hr = stack->HandleSynchronized( true, false ))) + { + if(hr == CLR_E_THREAD_WAITING) + { + stack->m_flags |= CLR_RT_StackFrame::c_PendingSynchronize; + } + + NANOCLR_LEAVE(); + } + + stack->m_flags |= CLR_RT_StackFrame::c_Synchronized; + } + } + + { +#if defined(NANOCLR_PROFILE_NEW_CALLS) + CLR_PROF_HANDLER_CALLCHAIN( pm2, stack->m_callchain ); +#endif + + CLR_UINT32 methodKind = (stack->m_flags & CLR_RT_StackFrame::c_MethodKind_Mask); + + switch(methodKind) + { + case CLR_RT_StackFrame::c_MethodKind_Native: + CLR_RT_ExecutionEngine::ExecutionConstraint_Suspend(); + break; + + case CLR_RT_StackFrame::c_MethodKind_Interpreted: + //_ASSERTE((stack->m_flags & CLR_RT_StackFrame::c_InvalidIP) == 0); + stack->m_flags |= CLR_RT_StackFrame::c_ExecutingIL; + break; + } + + // perform systematic GC and compaction under memory pressure + // (g_CLR_RT_GarbageCollector.m_freeBytes refers to last time GC was run) + if(g_CLR_RT_GarbageCollector.m_freeBytes < g_CLR_RT_GarbageCollector.c_memoryThreshold2) + { + stack->m_flags |= CLR_RT_StackFrame::c_CompactAndRestartOnOutOfMemory; + } + + while(true) + { + { + #if defined(ENABLE_NATIVE_PROFILER) + if(stack->m_flags & CLR_RT_StackFrame::c_NativeProfiled) + { + Native_Profiler_Start(); + } + else if(stack->m_fNativeProfiled == false) + { + stack->m_owningThread->m_fNativeProfiled = false; + Native_Profiler_Stop(); + } + #endif + + hr = stack->m_nativeMethod( *stack ); + } + + // check for exception injected by native code + if(m_currentException.Dereference() != NULL) + { + hr = CLR_E_PROCESS_EXCEPTION; + } + + //The inner loop may push or pop more stack frames + stack = CurrentFrame(); + + if(stack->Prev() == NULL) + { + m_status = CLR_RT_Thread::TH_S_Terminated; + + NANOCLR_SET_AND_LEAVE(CLR_S_THREAD_EXITED); // End of Thread. + } + + if(hr == CLR_E_OUT_OF_MEMORY && (stack->m_flags & CLR_RT_StackFrame::c_CompactAndRestartOnOutOfMemory)) + { + stack->m_flags &= ~CLR_RT_StackFrame::c_CompactAndRestartOnOutOfMemory; + + g_CLR_RT_ExecutionEngine.PerformHeapCompaction(); + } + else + { + break; + } + } + + switch(methodKind) + { + case CLR_RT_StackFrame::c_MethodKind_Native: + CLR_RT_ExecutionEngine::ExecutionConstraint_Resume(); + break; + } + + if(FAILED(hr)) + { + // + // CLR_E_RESTART_EXECUTION is used to inject calls to methods from native code. + // + if(hr != CLR_E_RESTART_EXECUTION) NANOCLR_LEAVE(); + } + else + { + stack->m_flags &= ~CLR_RT_StackFrame::c_ExecutingIL; + + if(hr == S_OK) + { + CurrentFrame()->Pop(); + } + } + } + } + + NANOCLR_SET_AND_LEAVE(CLR_S_QUANTUM_EXPIRED); + + NANOCLR_CLEANUP(); + + #if defined(ENABLE_NATIVE_PROFILER) + Native_Profiler_Stop(); + #endif + + NANOCLR_CLEANUP_END(); +} + +HRESULT CLR_RT_Thread::Execute_DelegateInvoke( CLR_RT_StackFrame& stackArg ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_StackFrame* stack = &stackArg; + + const CLR_RECORD_METHODDEF* md; + CLR_RT_HeapBlock_Delegate* dlg; + CLR_RT_HeapBlock* array; + CLR_RT_HeapBlock* ptr; + CLR_UINT32 num; + + ptr = &stack->m_arguments[ 0 ]; if(ptr->DataType() != DATATYPE_OBJECT) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + dlg = ptr->DereferenceDelegate(); FAULT_ON_NULL(dlg); + + md = stack->m_call.m_target; + + switch(dlg->DataType()) + { + case DATATYPE_DELEGATE_HEAD: + array = ptr; + num = 1; + break; + + case DATATYPE_DELEGATELIST_HEAD: + { + CLR_RT_HeapBlock_Delegate_List* list = ptr->DereferenceDelegateList(); + + array = list->GetDelegates(); + num = list->m_length; + } + break; + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + while(true) + { + if(stack->m_customState >= num) // We have called all the delegates, let's return. + { + NANOCLR_SET_AND_LEAVE(S_OK); + } + + dlg = array[ stack->m_customState++ ].DereferenceDelegate(); + + if(dlg == NULL || dlg->DataType() != DATATYPE_DELEGATE_HEAD) continue; + + break; + } + + //--// + + stack->ResetStack(); + + { + CLR_RT_ProtectFromGC gc( *dlg ); + CLR_RT_MethodDef_Instance inst; inst.InitializeFromIndex( dlg->DelegateFtn() ); + bool fStaticMethod = (inst.m_target->flags & CLR_RECORD_METHODDEF::MD_Static) != 0; + + NANOCLR_CHECK_HRESULT(stack->MakeCall(inst, fStaticMethod ? NULL : &dlg->m_object, &stack->m_arguments[ 1 ], md->numArgs - 1 )); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_Thread::Execute_IL( CLR_RT_StackFrame& stackArg ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_StackFrame* stack = &stackArg; + + CLR_RT_Thread* th = stack->m_owningThread; + CLR_RT_Assembly* assm = stack->m_call.m_assm; + CLR_RT_HeapBlock* evalPos; + CLR_PMETADATA ip; + bool fCondition; + bool fDirty = false; + + READCACHE(stack,evalPos,ip,fDirty); + + while(true) + { +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(th->m_timeQuantumExpired == true) + { + NANOCLR_SET_AND_LEAVE( CLR_S_QUANTUM_EXPIRED ); + } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + +#if defined(NANOCLR_TRACE_EXCEPTIONS) && defined(_WIN32) + if(s_CLR_RT_fTrace_Exceptions >= c_CLR_RT_Trace_Annoying) + { + CLR_PROF_HANDLER_SUSPEND_TIME(); + + BackTrackExecution& track = s_track[ s_trackPos++ ]; s_trackPos %= ARRAYSIZE(s_track); + int depth = 0; + + NANOCLR_FOREACH_NODE_BACKWARD__DIRECT(CLR_RT_StackFrame,tmp,stack) + { + depth++; + } + NANOCLR_FOREACH_NODE_BACKWARD_END(); + + track.m_assm = assm; + track.m_call = stack->m_call; + track.m_IP = ip; + track.m_IPstart = stack->m_IPstart; + track.m_pid = stack->m_owningThread->m_pid; + track.m_depth = depth; + + CLR_PROF_HANDLER_RESUME_TIME(); + } +#endif + + assm->DumpOpcode( stack, ip ); + + CLR_OPCODE op = CLR_OPCODE(*ip++); + +Execute_RestartDecoding: + +#if defined(NANOCLR_OPCODE_STACKCHANGES) + if(op != CEE_PREFIX1) + { + NANOCLR_CHECK_HRESULT(CLR_Checks::VerifyStackOK( *stack, &evalPos[ 1 ], c_CLR_RT_OpcodeLookup[ op ].StackChanges() )); + } +#endif + + { + //////////////////////// + // + // +#if defined(PLATFORM_WINDOWS_EMULATOR) + if(s_CLR_RT_fTrace_SimulateSpeed > c_CLR_RT_Trace_None) + { + CLR_PROF_Handler::SuspendTime(); + + HAL_Windows_FastSleep( g_HAL_Configuration_Windows.TicksPerOpcode ); + + CLR_PROF_Handler::ResumeTime(); + } +#endif + // + // + //////////////////////// + + //--// + + + switch(op) + { +#define OPDEF(name,string,pop,push,oprType,opcType,l,s1,s2,ctrl) case name: + OPDEF(CEE_PREFIX1, "prefix1", Pop0, Push0, InlineNone, IInternal, 1, 0xFF, 0xFE, META) + { + op = CLR_OPCODE(*ip++ + 256); + goto Execute_RestartDecoding; + } + + OPDEF(CEE_BREAK, "break", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x01, BREAK) + break; + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_LDARG_0, "ldarg.0", Pop0, Push1, InlineNone, IMacro, 1, 0xFF, 0x02, NEXT) + // Stack: ... ... -> ... + { + evalPos++; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].Assign( stack->m_arguments[ 0 ] ); + + goto Execute_LoadAndPromote; + } + + OPDEF(CEE_LDARG_1, "ldarg.1", Pop0, Push1, InlineNone, IMacro, 1, 0xFF, 0x03, NEXT) + OPDEF(CEE_LDARG_2, "ldarg.2", Pop0, Push1, InlineNone, IMacro, 1, 0xFF, 0x04, NEXT) + OPDEF(CEE_LDARG_3, "ldarg.3", Pop0, Push1, InlineNone, IMacro, 1, 0xFF, 0x05, NEXT) + // Stack: ... ... -> ... + { + evalPos++; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].Assign( stack->m_arguments[ op - CEE_LDARG_0 ] ); + + goto Execute_LoadAndPromote; + } + + OPDEF(CEE_LDARG_S, "ldarg.s", Pop0, Push1, ShortInlineVar, IMacro, 1, 0xFF, 0x0E, NEXT) + // Stack: ... ... -> ... + { + FETCH_ARG_UINT8(arg,ip); + + evalPos++; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].Assign( stack->m_arguments[ arg ] ); + + goto Execute_LoadAndPromote; + } + + OPDEF(CEE_LDARG, "ldarg", Pop0, Push1, InlineVar, IPrimitive, 2, 0xFE, 0x09, NEXT) + // Stack: ... ... -> ... + { + FETCH_ARG_UINT16(arg,ip); + + evalPos++; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].Assign( stack->m_arguments[ arg ] ); + + goto Execute_LoadAndPromote; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_LDLOC_0, "ldloc.0", Pop0, Push1, InlineNone, IMacro, 1, 0xFF, 0x06, NEXT) + // Stack: ... ... -> ... + { + evalPos++; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].Assign( stack->m_locals[ 0 ] ); + + goto Execute_LoadAndPromote; + } + + OPDEF(CEE_LDLOC_1, "ldloc.1", Pop0, Push1, InlineNone, IMacro, 1, 0xFF, 0x07, NEXT) + // Stack: ... ... -> ... + { + evalPos++; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].Assign( stack->m_locals[ 1 ] ); + + goto Execute_LoadAndPromote; + } + + OPDEF(CEE_LDLOC_2, "ldloc.2", Pop0, Push1, InlineNone, IMacro, 1, 0xFF, 0x08, NEXT) + // Stack: ... ... -> ... + { + evalPos++; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].Assign( stack->m_locals[ 2 ] ); + + goto Execute_LoadAndPromote; + } + + OPDEF(CEE_LDLOC_3, "ldloc.3", Pop0, Push1, InlineNone, IMacro, 1, 0xFF, 0x09, NEXT) + // Stack: ... ... -> ... + { + evalPos++; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].Assign( stack->m_locals[ 3 ] ); + + goto Execute_LoadAndPromote; + } + + OPDEF(CEE_LDLOC_S, "ldloc.s", Pop0, Push1, ShortInlineVar, IMacro, 1, 0xFF, 0x11, NEXT) + // Stack: ... ... -> ... + { + FETCH_ARG_UINT8(arg,ip); + + evalPos++; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].Assign( stack->m_locals[ arg ] ); + + goto Execute_LoadAndPromote; + } + + OPDEF(CEE_LDLOC, "ldloc", Pop0, Push1, InlineVar, IPrimitive, 2, 0xFE, 0x0C, NEXT) + // Stack: ... ... -> ... + { + FETCH_ARG_UINT16(arg,ip); + + evalPos++; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].Assign( stack->m_locals[ arg ] ); + + goto Execute_LoadAndPromote; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_LDLOCA_S, "ldloca.s", Pop0, PushI, ShortInlineVar, IMacro, 1, 0xFF, 0x12, NEXT) + // Stack: ... ... -> ... + { + FETCH_ARG_UINT8(arg,ip); + + evalPos++; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].SetReference( stack->m_locals[ arg ] ); + break; + } + + OPDEF(CEE_LDLOCA, "ldloca", Pop0, PushI, InlineVar, IPrimitive, 2, 0xFE, 0x0D, NEXT) + // Stack: ... ... -> ... + { + FETCH_ARG_UINT16(arg,ip); + + evalPos++; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].SetReference( stack->m_locals[ arg ] ); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_LDARGA_S, "ldarga.s", Pop0, PushI, ShortInlineVar, IMacro, 1, 0xFF, 0x0F, NEXT) + // Stack: ... ... -> ... + { + FETCH_ARG_UINT8(arg,ip); + + evalPos++; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].SetReference( stack->m_arguments[ arg ] ); + break; + } + + OPDEF(CEE_LDARGA, "ldarga", Pop0, PushI, InlineVar, IPrimitive, 2, 0xFE, 0x0A, NEXT) + // Stack: ... ... -> ... + { + FETCH_ARG_UINT16(arg,ip); + + evalPos++; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].SetReference( stack->m_arguments[ arg ] ); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_STLOC_0, "stloc.0", Pop1, Push0, InlineNone, IMacro, 1, 0xFF, 0x0A, NEXT) + OPDEF(CEE_STLOC_1, "stloc.1", Pop1, Push0, InlineNone, IMacro, 1, 0xFF, 0x0B, NEXT) + OPDEF(CEE_STLOC_2, "stloc.2", Pop1, Push0, InlineNone, IMacro, 1, 0xFF, 0x0C, NEXT) + OPDEF(CEE_STLOC_3, "stloc.3", Pop1, Push0, InlineNone, IMacro, 1, 0xFF, 0x0D, NEXT) + // Stack: ... ... -> ... + { + stack->m_locals[ op - CEE_STLOC_0 ].AssignPreserveTypeCheckPinned( evalPos[ 0 ] ); + + evalPos--; CHECKSTACK(stack,evalPos); + break; + } + + OPDEF(CEE_STLOC_S, "stloc.s", Pop1, Push0, ShortInlineVar, IMacro, 1, 0xFF, 0x13, NEXT) + // Stack: ... ... -> ... + { + FETCH_ARG_UINT8(arg,ip); + + stack->m_locals[ arg ].AssignPreserveTypeCheckPinned( evalPos[ 0 ] ); + + evalPos--; CHECKSTACK(stack,evalPos); + break; + } + + OPDEF(CEE_STLOC, "stloc", Pop1, Push0, InlineVar, IPrimitive, 2, 0xFE, 0x0E, NEXT) + // Stack: ... ... -> ... + { + FETCH_ARG_UINT16(arg,ip); + + stack->m_locals[ arg ].AssignPreserveTypeCheckPinned( evalPos[ 0 ] ); + + evalPos--; CHECKSTACK(stack,evalPos); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_STARG_S, "starg.s", Pop1, Push0, ShortInlineVar, IMacro, 1, 0xFF, 0x10, NEXT) + // Stack: ... ... -> ... + { + FETCH_ARG_UINT8(arg,ip); + + stack->m_arguments[ arg ].AssignAndPreserveType( evalPos[ 0 ] ); + + evalPos--; CHECKSTACK(stack,evalPos); + break; + } + + OPDEF(CEE_STARG, "starg", Pop1, Push0, InlineVar, IPrimitive, 2, 0xFE, 0x0B, NEXT) + // Stack: ... ... -> ... + { + FETCH_ARG_UINT16(arg,ip); + + stack->m_arguments[ arg ].AssignAndPreserveType( evalPos[ 0 ] ); + + evalPos--; CHECKSTACK(stack,evalPos); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_LDNULL, "ldnull", Pop0, PushRef, InlineNone, IPrimitive, 1, 0xFF, 0x14, NEXT) + // Stack: ... ... -> ... + { + evalPos++; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].SetObjectReference( NULL ); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_LDC_I4_M1, "ldc.i4.m1", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x15, NEXT) + OPDEF(CEE_LDC_I4_0, "ldc.i4.0", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x16, NEXT) + OPDEF(CEE_LDC_I4_1, "ldc.i4.1", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x17, NEXT) + OPDEF(CEE_LDC_I4_2, "ldc.i4.2", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x18, NEXT) + OPDEF(CEE_LDC_I4_3, "ldc.i4.3", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x19, NEXT) + OPDEF(CEE_LDC_I4_4, "ldc.i4.4", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x1A, NEXT) + OPDEF(CEE_LDC_I4_5, "ldc.i4.5", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x1B, NEXT) + OPDEF(CEE_LDC_I4_6, "ldc.i4.6", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x1C, NEXT) + OPDEF(CEE_LDC_I4_7, "ldc.i4.7", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x1D, NEXT) + OPDEF(CEE_LDC_I4_8, "ldc.i4.8", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x1E, NEXT) + // Stack: ... ... -> ... + { + evalPos++; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].SetInteger( (CLR_INT32)op - (CLR_INT32)CEE_LDC_I4_0 ); + break; + } + + OPDEF(CEE_LDC_I4_S, "ldc.i4.s", Pop0, PushI, ShortInlineI, IMacro, 1, 0xFF, 0x1F, NEXT) + // Stack: ... ... -> ... + { + FETCH_ARG_INT8(arg,ip); + + evalPos++; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].SetInteger( (CLR_INT32)arg ); + break; + } + + OPDEF(CEE_LDC_I4, "ldc.i4", Pop0, PushI, InlineI, IPrimitive, 1, 0xFF, 0x20, NEXT) + // Stack: ... ... -> ... + { + FETCH_ARG_INT32(arg,ip); + + evalPos++; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].SetInteger( (CLR_INT32)arg ); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_LDC_I8, "ldc.i8", Pop0, PushI8, InlineI8, IPrimitive, 1, 0xFF, 0x21, NEXT) + // Stack: ... ... -> ... + { + FETCH_ARG_INT64(arg,ip); + + evalPos++; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].SetInteger( (CLR_INT64)arg ); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_LDC_R4, "ldc.r4", Pop0, PushR4, ShortInlineR, IPrimitive, 1, 0xFF, 0x22, NEXT) + // Stack: ... ... -> ... + { + FETCH_ARG_UINT32(arg,ip); + + evalPos++; CHECKSTACK(stack,evalPos); + +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + evalPos[ 0 ].SetFloatFromBits( arg ); +#else + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].SetFloatIEEE754( arg )); +#endif + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_LDC_R8, "ldc.r8", Pop0, PushR8, InlineR, IPrimitive, 1, 0xFF, 0x23, NEXT) + // Stack: ... ... -> ... + { + FETCH_ARG_UINT64(arg,ip); + + evalPos++; CHECKSTACK(stack,evalPos); +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + evalPos[ 0 ].SetDoubleFromBits( arg ); +#else + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].SetDoubleIEEE754( arg )); +#endif + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_DUP, "dup", Pop1, Push1+Push1, InlineNone, IPrimitive, 1, 0xFF, 0x25, NEXT) + // Stack: ... ... -> ... + { + evalPos++; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].Assign( evalPos[ -1 ] ); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_POP, "pop", Pop1, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x26, NEXT) + // Stack: ... ... -> ... + { + evalPos--; CHECKSTACK(stack,evalPos); + break; + } + + //----------------------------------------------------------------------------------------------------------// + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_BR_S, "br.s", Pop0, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x2B, BRANCH) + OPDEF(CEE_BR, "br", Pop0, Push0, InlineBrTarget, IPrimitive, 1, 0xFF, 0x38, BRANCH) + { + fCondition = true; + goto Execute_BR; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_BRFALSE_S, "brfalse.s", PopI, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x2C, COND_BRANCH) + OPDEF(CEE_BRFALSE, "brfalse", PopI, Push0, InlineBrTarget, IPrimitive, 1, 0xFF, 0x39, COND_BRANCH) + // Stack: ... ... -> ... + { + evalPos--; CHECKSTACK(stack,evalPos); + + fCondition = (evalPos[ 1 ].IsZero() == true); + goto Execute_BR; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_BRTRUE_S, "brtrue.s", PopI, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x2D, COND_BRANCH) + OPDEF(CEE_BRTRUE, "brtrue", PopI, Push0, InlineBrTarget, IPrimitive, 1, 0xFF, 0x3A, COND_BRANCH) + // Stack: ... ... -> ... + { + evalPos--; CHECKSTACK(stack,evalPos); + + fCondition = (evalPos[ 1 ].IsZero() == false); + goto Execute_BR; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_BEQ_S, "beq.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x2E, COND_BRANCH) + OPDEF(CEE_BEQ, "beq", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x3B, COND_BRANCH) + // Stack: ... ... -> ... + { + evalPos -= 2; CHECKSTACK(stack,evalPos); + + fCondition = (CLR_RT_HeapBlock::Compare_Signed_Values( evalPos[ 1 ], evalPos[ 2 ] ) == 0); + goto Execute_BR; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_BGE_S, "bge.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x2F, COND_BRANCH) + OPDEF(CEE_BGE, "bge", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x3C, COND_BRANCH) + // Stack: ... ... -> ... + { + evalPos -= 2; CHECKSTACK(stack,evalPos); + + fCondition = (CLR_RT_HeapBlock::Compare_Signed_Values( evalPos[ 1 ], evalPos[ 2 ] ) >= 0); + goto Execute_BR; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_BGT_S, "bgt.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x30, COND_BRANCH) + OPDEF(CEE_BGT, "bgt", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x3D, COND_BRANCH) + // Stack: ... ... -> ... + { + evalPos -= 2; CHECKSTACK(stack,evalPos); + + fCondition = (CLR_RT_HeapBlock::Compare_Signed_Values( evalPos[ 1 ], evalPos[ 2 ] ) > 0); + goto Execute_BR; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_BLE_S, "ble.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x31, COND_BRANCH) + OPDEF(CEE_BLE, "ble", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x3E, COND_BRANCH) + // Stack: ... ... -> ... + { + evalPos -= 2; CHECKSTACK(stack,evalPos); + + fCondition = (CLR_RT_HeapBlock::Compare_Signed_Values( evalPos[ 1 ], evalPos[ 2 ] ) <= 0); + goto Execute_BR; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_BLT_S, "blt.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x32, COND_BRANCH) + OPDEF(CEE_BLT, "blt", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x3F, COND_BRANCH) + // Stack: ... ... -> ... + { + evalPos -= 2; CHECKSTACK(stack,evalPos); + + fCondition = (CLR_RT_HeapBlock::Compare_Signed_Values( evalPos[ 1 ], evalPos[ 2 ] ) < 0); + goto Execute_BR; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_BNE_UN_S, "bne.un.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x33, COND_BRANCH) + OPDEF(CEE_BNE_UN, "bne.un", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x40, COND_BRANCH) + // Stack: ... ... -> ... + { + evalPos -= 2; CHECKSTACK(stack,evalPos); + + fCondition = (CLR_RT_HeapBlock::Compare_Unsigned_Values( evalPos[ 1 ], evalPos[ 2 ] ) != 0); + goto Execute_BR; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_BGE_UN_S, "bge.un.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x34, COND_BRANCH) + OPDEF(CEE_BGE_UN, "bge.un", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x41, COND_BRANCH) + // Stack: ... ... -> ... + { + evalPos -= 2; CHECKSTACK(stack,evalPos); + + fCondition = (CLR_RT_HeapBlock::Compare_Unsigned_Values( evalPos[ 1 ], evalPos[ 2 ] ) >= 0); + goto Execute_BR; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_BGT_UN_S, "bgt.un.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x35, COND_BRANCH) + OPDEF(CEE_BGT_UN, "bgt.un", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x42, COND_BRANCH) + // Stack: ... ... -> ... + { + evalPos -= 2; CHECKSTACK(stack,evalPos); + + fCondition = (CLR_RT_HeapBlock::Compare_Unsigned_Values( evalPos[ 1 ], evalPos[ 2 ] ) > 0); + goto Execute_BR; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_BLE_UN_S, "ble.un.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x36, COND_BRANCH) + OPDEF(CEE_BLE_UN, "ble.un", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x43, COND_BRANCH) + // Stack: ... ... -> ... + { + evalPos -= 2; CHECKSTACK(stack,evalPos); + + fCondition = (CLR_RT_HeapBlock::Compare_Unsigned_Values( evalPos[ 1 ], evalPos[ 2 ] ) <= 0); + goto Execute_BR; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_BLT_UN_S, "blt.un.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x37, COND_BRANCH) + OPDEF(CEE_BLT_UN, "blt.un", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x44, COND_BRANCH) + // Stack: ... ... -> ... + { + evalPos -= 2; CHECKSTACK(stack,evalPos); + + fCondition = (CLR_RT_HeapBlock::Compare_Unsigned_Values( evalPos[ 1 ], evalPos[ 2 ] ) < 0); + goto Execute_BR; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_SWITCH, "switch", PopI, Push0, InlineSwitch, IPrimitive, 1, 0xFF, 0x45, COND_BRANCH) + // Stack: ... ... -> ... + { + evalPos--; CHECKSTACK(stack,evalPos); + + FETCH_ARG_UINT8(arg,ip); + + CLR_UINT32 numCases = arg; + CLR_UINT32 caseSelected = evalPos[ 1 ].NumericByRef().u4; + + if(caseSelected < numCases) + { + CLR_PMETADATA ipsub = ip + (CLR_INT32)caseSelected * sizeof(CLR_INT16); + + FETCH_ARG_INT16(offset,ipsub); + + ip += offset; + } + + ip += (CLR_INT32)numCases * sizeof(CLR_INT16); + break; + } + + //----------------------------------------------------------------------------------------------------------// + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_LDIND_I1, "ldind.i1", PopI, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x46, NEXT) + OPDEF(CEE_LDIND_U1, "ldind.u1", PopI, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x47, NEXT) + OPDEF(CEE_LDIND_I2, "ldind.i2", PopI, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x48, NEXT) + OPDEF(CEE_LDIND_U2, "ldind.u2", PopI, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x49, NEXT) + OPDEF(CEE_LDIND_I4, "ldind.i4", PopI, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x4A, NEXT) + OPDEF(CEE_LDIND_U4, "ldind.u4", PopI, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x4B, NEXT) + OPDEF(CEE_LDIND_I8, "ldind.i8", PopI, PushI8, InlineNone, IPrimitive, 1, 0xFF, 0x4C, NEXT) + OPDEF(CEE_LDIND_I, "ldind.i", PopI, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x4D, NEXT) + OPDEF(CEE_LDIND_R4, "ldind.r4", PopI, PushR4, InlineNone, IPrimitive, 1, 0xFF, 0x4E, NEXT) + OPDEF(CEE_LDIND_R8, "ldind.r8", PopI, PushR8, InlineNone, IPrimitive, 1, 0xFF, 0x4F, NEXT) + OPDEF(CEE_LDIND_REF, "ldind.ref", PopI, PushRef, InlineNone, IPrimitive, 1, 0xFF, 0x50, NEXT) + // Stack: ... ...
-> ... + { + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].LoadFromReference( evalPos[ 0 ] )); + + goto Execute_LoadAndPromote; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_STIND_REF, "stind.ref", PopI+PopI, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x51, NEXT) + OPDEF(CEE_STIND_I1, "stind.i1", PopI+PopI, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x52, NEXT) + OPDEF(CEE_STIND_I2, "stind.i2", PopI+PopI, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x53, NEXT) + OPDEF(CEE_STIND_I4, "stind.i4", PopI+PopI, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x54, NEXT) + OPDEF(CEE_STIND_I8, "stind.i8", PopI+PopI8, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x55, NEXT) + OPDEF(CEE_STIND_R4, "stind.r4", PopI+PopR4, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x56, NEXT) + OPDEF(CEE_STIND_R8, "stind.r8", PopI+PopR8, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x57, NEXT) + OPDEF(CEE_STIND_I, "stind.i", PopI+PopI, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xDF, NEXT) + // Stack: ... ...
-> ... + { + int size = 0; + + evalPos -= 2; CHECKSTACK(stack,evalPos); + + switch(op) + { + case CEE_STIND_I : size = 4; break; + case CEE_STIND_I1 : size = 1; break; + case CEE_STIND_I2 : size = 2; break; + case CEE_STIND_I4 : size = 4; break; + case CEE_STIND_I8 : size = 8; break; + case CEE_STIND_R4 : size = 4; break; + case CEE_STIND_R8 : size = 8; break; + case CEE_STIND_REF: size = 0; break; + // the remaining op codes aren't to be handled + default: break; + } + + evalPos[ 2 ].Promote(); + + NANOCLR_CHECK_HRESULT(evalPos[ 2 ].StoreToReference( evalPos[ 1 ], size )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_ADD, "add", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x58, NEXT) + OPDEF(CEE_ADD_OVF, "add.ovf", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0xD6, NEXT) + OPDEF(CEE_ADD_OVF_UN, "add.ovf.un", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0xD7, NEXT) + // Stack: ... ... -> ... + { + evalPos--; CHECKSTACK(stack,evalPos); + + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].NumericAdd( evalPos[ 1 ] )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_SUB, "sub", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x59, NEXT) + OPDEF(CEE_SUB_OVF, "sub.ovf", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0xDA, NEXT) + OPDEF(CEE_SUB_OVF_UN, "sub.ovf.un", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0xDB, NEXT) + // Stack: ... ... -> ... + { + evalPos--; CHECKSTACK(stack,evalPos); + + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].NumericSub( evalPos[ 1 ] )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_MUL, "mul", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x5A, NEXT) + OPDEF(CEE_MUL_OVF, "mul.ovf", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0xD8, NEXT) + OPDEF(CEE_MUL_OVF_UN, "mul.ovf.un", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0xD9, NEXT) + // Stack: ... ... -> ... + { + evalPos--; CHECKSTACK(stack,evalPos); + + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].NumericMul( evalPos[ 1 ] )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_DIV, "div", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x5B, NEXT) + // Stack: ... ... -> ... + { + evalPos--; CHECKSTACK(stack,evalPos); + + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].NumericDiv( evalPos[ 1 ] )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_DIV_UN, "div.un", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x5C, NEXT) + // Stack: ... ... -> ... + { + evalPos--; CHECKSTACK(stack,evalPos); + + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].NumericDivUn( evalPos[ 1 ] )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_REM, "rem", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x5D, NEXT) + // Stack: ... ... -> ... + { + evalPos--; CHECKSTACK(stack,evalPos); + + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].NumericRem( evalPos[ 1 ] )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_REM_UN, "rem.un", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x5E, NEXT) + // Stack: ... ... -> ... + { + evalPos--; CHECKSTACK(stack,evalPos); + + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].NumericRemUn( evalPos[ 1 ] )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_AND, "and", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x5F, NEXT) + // Stack: ... ... -> ... + { + evalPos--; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].NumericByRef().u8 &= evalPos[ 1 ].NumericByRef().u8; + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_OR, "or", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x60, NEXT) + // Stack: ... ... -> ... + { + evalPos--; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].NumericByRef().u8 |= evalPos[ 1 ].NumericByRef().u8; + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_XOR, "xor", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x61, NEXT) + // Stack: ... ... -> ... + { + evalPos--; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].NumericByRef().u8 ^= evalPos[ 1 ].NumericByRef().u8; + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_SHL, "shl", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x62, NEXT) + // Stack: ... ... -> ... + { + evalPos--; CHECKSTACK(stack,evalPos); + + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].NumericShl( evalPos[ 1 ] )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_SHR, "shr", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x63, NEXT) + // Stack: ... ... -> ... + { + evalPos--; CHECKSTACK(stack,evalPos); + + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].NumericShr( evalPos[ 1 ] )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_SHR_UN, "shr.un", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x64, NEXT) + // Stack: ... ... -> ... + { + evalPos--; CHECKSTACK(stack,evalPos); + + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].NumericShrUn( evalPos[ 1 ] )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_NEG, "neg", Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x65, NEXT) + // Stack: ... ... -> ... + { + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].NumericNeg()); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_NOT, "not", Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x66, NEXT) + // Stack: ... ... -> ... + { + evalPos[ 0 ].NumericByRef().u8 = ~evalPos[ 0 ].NumericByRef().u8; + break; + } + + //----------------------------------------------------------------------------------------------------------// + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_CONV_I1, "conv.i1", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x67, NEXT) + OPDEF(CEE_CONV_OVF_I1, "conv.ovf.i1", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xB3, NEXT) + OPDEF(CEE_CONV_OVF_I1_UN, "conv.ovf.i1.un", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x82, NEXT) + // Stack: ... ... -> ... + { + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].Convert( DATATYPE_I1, op != CEE_CONV_I1, op == CEE_CONV_OVF_I1_UN )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_CONV_I2, "conv.i2", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x68, NEXT) + OPDEF(CEE_CONV_OVF_I2, "conv.ovf.i2", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xB5, NEXT) + OPDEF(CEE_CONV_OVF_I2_UN, "conv.ovf.i2.un", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x83, NEXT) + // Stack: ... ... -> ... + { + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].Convert( DATATYPE_I2, op != CEE_CONV_I2, op == CEE_CONV_OVF_I2_UN )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_CONV_I4, "conv.i4", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x69, NEXT) + OPDEF(CEE_CONV_OVF_I4, "conv.ovf.i4", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xB7, NEXT) + OPDEF(CEE_CONV_OVF_I4_UN, "conv.ovf.i4.un", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x84, NEXT) + // Stack: ... ... -> ... + { + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].Convert( DATATYPE_I4, op != CEE_CONV_I4, op == CEE_CONV_OVF_I4_UN )); + break; + } + + OPDEF(CEE_CONV_I, "conv.i", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xD3, NEXT) + OPDEF(CEE_CONV_OVF_I, "conv.ovf.i", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xD4, NEXT) + OPDEF(CEE_CONV_OVF_I_UN, "conv.ovf.i.un", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x8A, NEXT) + // Stack: ... ... -> ... + { + if ( evalPos[ 0 ].DataType() == DATATYPE_BYREF || evalPos[ 0 ].DataType() == DATATYPE_ARRAY_BYREF ) + { + break; + } + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].Convert( DATATYPE_I4, op != CEE_CONV_I, op == CEE_CONV_OVF_I_UN )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_CONV_I8, "conv.i8", Pop1, PushI8, InlineNone, IPrimitive, 1, 0xFF, 0x6A, NEXT) + OPDEF(CEE_CONV_OVF_I8, "conv.ovf.i8", Pop1, PushI8, InlineNone, IPrimitive, 1, 0xFF, 0xB9, NEXT) + OPDEF(CEE_CONV_OVF_I8_UN, "conv.ovf.i8.un", Pop1, PushI8, InlineNone, IPrimitive, 1, 0xFF, 0x85, NEXT) + // Stack: ... ... -> ... + { + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].Convert( DATATYPE_I8, op != CEE_CONV_I8, op == CEE_CONV_OVF_I8_UN )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_CONV_R4, "conv.r4", Pop1, PushR4, InlineNone, IPrimitive, 1, 0xFF, 0x6B, NEXT) + // Stack: ... ... -> ... + { + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].Convert( DATATYPE_R4, false, false )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_CONV_R_UN, "conv.r.un", Pop1, PushR8, InlineNone, IPrimitive, 1, 0xFF, 0x76, NEXT) + OPDEF(CEE_CONV_R8, "conv.r8", Pop1, PushR8, InlineNone, IPrimitive, 1, 0xFF, 0x6C, NEXT) + // Stack: ... ... -> ... + { + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].Convert( DATATYPE_R8, false, op == CEE_CONV_R_UN )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_CONV_U1, "conv.u1", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xD2, NEXT) + OPDEF(CEE_CONV_OVF_U1, "conv.ovf.u1", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xB4, NEXT) + OPDEF(CEE_CONV_OVF_U1_UN, "conv.ovf.u1.un", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x86, NEXT) + // Stack: ... ... -> ... + { + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].Convert( DATATYPE_U1, op != CEE_CONV_U1, op == CEE_CONV_OVF_U1_UN )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_CONV_U2, "conv.u2", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xD1, NEXT) + OPDEF(CEE_CONV_OVF_U2, "conv.ovf.u2", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xB6, NEXT) + OPDEF(CEE_CONV_OVF_U2_UN, "conv.ovf.u2.un", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x87, NEXT) + // Stack: ... ... -> ... + { + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].Convert( DATATYPE_U2, op != CEE_CONV_U2, op == CEE_CONV_OVF_U2_UN )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_CONV_U4, "conv.u4", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x6D, NEXT) + OPDEF(CEE_CONV_OVF_U4, "conv.ovf.u4", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xB8, NEXT) + OPDEF(CEE_CONV_OVF_U4_UN, "conv.ovf.u4.un", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x88, NEXT) + // Stack: ... ... -> ... + { + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].Convert( DATATYPE_U4, op != CEE_CONV_U4, op == CEE_CONV_OVF_U4_UN )); + break; + } + + OPDEF(CEE_CONV_U, "conv.u", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xE0, NEXT) + OPDEF(CEE_CONV_OVF_U, "conv.ovf.u", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xD5, NEXT) + OPDEF(CEE_CONV_OVF_U_UN, "conv.ovf.u.un", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x8B, NEXT) + // Stack: ... ... -> ... + { + if ( evalPos[ 0 ].DataType() == DATATYPE_BYREF || evalPos[ 0 ].DataType() == DATATYPE_ARRAY_BYREF ) + { + break; + } + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].Convert( DATATYPE_U4, op != CEE_CONV_U, op == CEE_CONV_OVF_U_UN )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_CONV_U8, "conv.u8", Pop1, PushI8, InlineNone, IPrimitive, 1, 0xFF, 0x6E, NEXT) + OPDEF(CEE_CONV_OVF_U8, "conv.ovf.u8", Pop1, PushI8, InlineNone, IPrimitive, 1, 0xFF, 0xBA, NEXT) + OPDEF(CEE_CONV_OVF_U8_UN, "conv.ovf.u8.un", Pop1, PushI8, InlineNone, IPrimitive, 1, 0xFF, 0x89, NEXT) + // Stack: ... ... -> ... + { + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].Convert( DATATYPE_U8, op != CEE_CONV_U8, op == CEE_CONV_OVF_U8_UN )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + //----------------------------------------------------------------------------------------------------------// + OPDEF(CEE_CALL, "call", VarPop, VarPush, InlineMethod, IPrimitive, 1, 0xFF, 0x28, CALL) + OPDEF(CEE_CALLVIRT, "callvirt", VarPop, VarPush, InlineMethod, IObjModel, 1, 0xFF, 0x6F, CALL) + + { + FETCH_ARG_COMPRESSED_METHODTOKEN(arg,ip); + + CLR_RT_MethodDef_Instance calleeInst; if(calleeInst.ResolveToken( arg, assm ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + CLR_RT_TypeDef_Index cls; + CLR_RT_HeapBlock* pThis; +#if defined(NANOCLR_APPDOMAINS) + bool fAppDomainTransition = false; +#endif + + pThis = &evalPos[1-calleeInst.m_target->numArgs]; // Point to the first arg, 'this' if an instance method + + if(calleeInst.m_target->flags & CLR_RECORD_METHODDEF::MD_DelegateInvoke) + { + CLR_RT_HeapBlock_Delegate* dlg = pThis->DereferenceDelegate(); FAULT_ON_NULL(dlg); + + if(dlg->DataType() == DATATYPE_DELEGATE_HEAD) + { + calleeInst.InitializeFromIndex( dlg->DelegateFtn() ); + + if((calleeInst.m_target->flags & CLR_RECORD_METHODDEF::MD_Static) == 0) + { + pThis->Assign( dlg->m_object ); + +#if defined(NANOCLR_APPDOMAINS) + fAppDomainTransition = pThis[ 0 ].IsTransparentProxy(); +#endif + } + else + { + memmove( &pThis[ 0 ], &pThis[ 1 ], calleeInst.m_target->numArgs * sizeof(CLR_RT_HeapBlock) ); + + evalPos--; + } + } + else + { + // + // The lookup for multicast delegates is done at a later stage... + // + } + } + else //Non delegate + { + CLR_RT_MethodDef_Index calleeReal; + + if((calleeInst.m_target->flags & CLR_RECORD_METHODDEF::MD_Static) == 0) + { + //Instance method, pThis[ 0 ] is valid + + if(op == CEE_CALL && pThis[ 0 ].Dereference() == NULL) + { + //CALL on a null instance is allowed, and should not throw a NullReferenceException on the call + //although a NullReferenceException is likely to be thrown soon thereafter if the call tries to access + //any member variables. + } + else + { + NANOCLR_CHECK_HRESULT(CLR_RT_TypeDescriptor::ExtractTypeIndexFromObject( pThis[ 0 ], cls )); + + //This test is for performance reasons. c# emits a callvirt on all instance methods to make sure that + //a NullReferenceException is thrown if 'this' is NULL. However, if the instance method isn't virtual + //we don't need to do the more expensive virtual method lookup. + if(op == CEE_CALLVIRT && (calleeInst.m_target->flags & (CLR_RECORD_METHODDEF::MD_Abstract | CLR_RECORD_METHODDEF::MD_Virtual))) + { + if(g_CLR_RT_EventCache.FindVirtualMethod( cls, calleeInst, calleeReal ) == false) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + calleeInst.InitializeFromIndex( calleeReal ); + } + +#if defined(NANOCLR_APPDOMAINS) + fAppDomainTransition = pThis[ 0 ].IsTransparentProxy(); +#endif + } + } + } + +#if defined(NANOCLR_APPDOMAINS) + if(fAppDomainTransition) + { + WRITEBACK(stack,evalPos,ip,fDirty); + + _ASSERTE(FIMPLIES(pThis->DataType() == DATATYPE_OBJECT, pThis->Dereference() != NULL)); + NANOCLR_CHECK_HRESULT(CLR_RT_StackFrame::PushAppDomainTransition( th, calleeInst, &pThis[ 0 ], &pThis[ 1 ])); + } + else +#endif //NANOCLR_APPDOMAINS + { +#ifndef CLR_NO_IL_INLINE + if(stack->PushInline(ip, assm, evalPos, calleeInst, pThis)) + { + fDirty = true; + break; + } +#endif + + WRITEBACK(stack,evalPos,ip,fDirty); + NANOCLR_CHECK_HRESULT(CLR_RT_StackFrame::Push( th, calleeInst, -1 )); + } + + goto Execute_Restart; + } + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_RET, "ret", VarPop, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x2A, RETURN) + { +#ifndef CLR_NO_IL_INLINE + if(stack->m_inlineFrame) + { + stack->m_evalStackPos = evalPos; + + stack->PopInline(); + + ip = stack->m_IP; + assm = stack->m_call.m_assm; + evalPos = stack->m_evalStackPos-1; + fDirty = true; + + break; + } +#endif + + WRITEBACK(stack,evalPos,ip,fDirty); + + // + // Same kind of handler, no need to pop back out, just restart execution in place. + // + if(stack->m_flags & CLR_RT_StackFrame::c_CallerIsCompatibleForRet) + { + CLR_RT_StackFrame* stackNext = stack->Caller(); + + stack->Pop(); + + stack = stackNext; + goto Execute_Reload; + } + else + { + stack->Pop(); + + NANOCLR_SET_AND_LEAVE(CLR_S_RESTART_EXECUTION); + } + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_CPOBJ, "cpobj", PopI+PopI, Push0, InlineType, IObjModel, 1, 0xFF, 0x70, NEXT) + OPDEF(CEE_STOBJ, "stobj", PopI+Pop1, Push0, InlineType, IPrimitive, 1, 0xFF, 0x81, NEXT) + // Stack: ... ... -> ... + { + ip += 2; // Skip argument, not used... + + evalPos -= 2; CHECKSTACK(stack,evalPos); + + // + // Reassign will make sure these are objects of the same type. + // + NANOCLR_CHECK_HRESULT(evalPos[ 1 ].Reassign( evalPos[ 2 ] )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_LDOBJ, "ldobj", PopI, Push1, InlineType, IObjModel, 1, 0xFF, 0x71, NEXT) + // Stack: ... ... -> ... + { + FETCH_ARG_COMPRESSED_TYPETOKEN(arg,ip); + + CLR_RT_TypeDef_Instance type; + CLR_RT_TypeDef_Index cls; + + if(type.ResolveToken( arg, assm ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + NANOCLR_CHECK_HRESULT(CLR_RT_TypeDescriptor::ExtractTypeIndexFromObject( evalPos[ 0 ], cls )); + + // Check this is an object of the requested type. + if(type.m_data != cls.m_data) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + UPDATESTACK(stack,evalPos); + + { + // + // Save the pointer to the object to load/copy and protect it from GC. + // + CLR_RT_HeapBlock safeSource; safeSource.Assign( evalPos[ 0 ] ); + CLR_RT_ProtectFromGC gc( safeSource ); + + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].LoadFromReference( safeSource )); + + } + + goto Execute_LoadAndPromote; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_LDSTR, "ldstr", Pop0, PushRef, InlineString, IObjModel, 1, 0xFF, 0x72, NEXT) + { + FETCH_ARG_COMPRESSED_STRINGTOKEN(arg,ip); + + evalPos++; CHECKSTACK(stack,evalPos); + + UPDATESTACK(stack,evalPos); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( evalPos[ 0 ], arg, assm )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_NEWOBJ, "newobj", VarPop, PushRef, InlineMethod, IObjModel, 1, 0xFF, 0x73, CALL) + // Stack: ... ... -> ... + { + FETCH_ARG_COMPRESSED_METHODTOKEN(arg,ip); + + CLR_RT_MethodDef_Instance calleeInst; if(calleeInst.ResolveToken( arg, assm ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + CLR_RT_TypeDef_Instance cls; + CLR_RT_HeapBlock* top; + CLR_INT32 changes; + + cls.InitializeFromMethod( calleeInst ); // This is the class to create! + + evalPos++; + + WRITEBACK(stack,evalPos,ip,fDirty); + + if(cls.m_target->IsDelegate()) + { + // + // Special case for delegates. LDFTN or LDVIRTFTN have already created the delegate object, just check that... + // + changes = -calleeInst.m_target->numArgs; + NANOCLR_CHECK_HRESULT(CLR_Checks::VerifyStackOK( *stack, stack->m_evalStackPos, changes )); // Check to see if we have enough parameters. + stack->m_evalStackPos += changes; + + top = stack->m_evalStackPos++; // Push back the result. + + if(top[ 1 ].DataType() != DATATYPE_OBJECT) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + CLR_RT_HeapBlock_Delegate* dlg = top[ 1 ].DereferenceDelegate(); + + if(dlg == NULL) + { + NANOCLR_CHECK_HRESULT(CLR_E_NULL_REFERENCE); + } + + dlg->m_cls = cls; + + CLR_RT_MethodDef_Instance dlgInst; + + if(dlgInst.InitializeFromIndex( dlg->DelegateFtn() ) == false) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + if((dlgInst.m_target->flags & CLR_RECORD_METHODDEF::MD_Static) == 0) + { + dlg->m_object.Assign( top[ 0 ] ); + } + + top->SetObjectReference( dlg ); + } + else + { + changes = calleeInst.m_target->numArgs; + NANOCLR_CHECK_HRESULT(CLR_Checks::VerifyStackOK( *stack, stack->m_evalStackPos, -changes )); // Check to see if we have enough parameters. + top = stack->m_evalStackPos; + + // + // We have to insert the 'this' pointer as argument 0, that means moving all the arguments up one slot... + // + top--; + while(--changes > 0) + { + top[ 0 ].Assign( top[ -1 ] ); top--; + } + top->SetObjectReference( NULL ); + + // Stack: ... ... -> ... + // ^ + // Top points here. + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObject( top[ 0 ], cls )); + + // + // This is to flag the fact that we need to copy back the 'this' pointer into our stack. + // + // See CLR_RT_StackFrame::Pop() + // + stack->m_flags |= CLR_RT_StackFrame::c_ExecutingConstructor; + + // + // Ok, creating a ValueType then calls its constructor. + // But the constructor will try to load the 'this' pointer and since it's a value type, it will be cloned. + // For the length of the constructor, change the type from an object pointer to a reference. + // + // See CLR_RT_StackFrame::Pop() + // + if((cls.m_target->flags & CLR_RECORD_TYPEDEF::TD_Semantics_Mask) == CLR_RECORD_TYPEDEF::TD_Semantics_ValueType) + { + if(top[ 0 ].DataType() == DATATYPE_OBJECT) + { + top[ 0 ].ChangeDataType( DATATYPE_BYREF ); + } + else + { + // + // This is to support the optimization on DateTime and TimeSpan: + // + // These are passed as built-ins. But we need to pass them as a reference, + // so push everything down and undo the "ExecutingConstructor" trick. + // + top = stack->m_evalStackPos++; + + changes = calleeInst.m_target->numArgs; + while(--changes > 0) + { + top[ 0 ].Assign( top[ -1 ] ); top--; + } + top[ 0 ].SetReference( top[ -1 ] ); + + stack->m_flags &= ~CLR_RT_StackFrame::c_ExecutingConstructor; + } + } + + if(FAILED(hr = CLR_RT_StackFrame::Push( th, calleeInst, -1 ))) + { + if(hr == CLR_E_NOT_SUPPORTED) + { + // no matter what, we are no longer executing a ctor + stack->m_flags &= ~CLR_RT_StackFrame::c_ExecutingConstructor; + } + + NANOCLR_LEAVE(); + } + + goto Execute_Restart; + } + + READCACHE(stack,evalPos,ip,fDirty); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_CASTCLASS, "castclass", PopRef, PushRef, InlineType, IObjModel, 1, 0xFF, 0x74, NEXT) + OPDEF(CEE_ISINST, "isinst", PopRef, PushI, InlineType, IObjModel, 1, 0xFF, 0x75, NEXT) + { + FETCH_ARG_COMPRESSED_TYPETOKEN(arg,ip); + + NANOCLR_CHECK_HRESULT(CLR_RT_ExecutionEngine::CastToType( evalPos[ 0 ], arg, assm, (op == CEE_ISINST) )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_THROW, "throw", PopRef, Push0, InlineNone, IObjModel, 1, 0xFF, 0x7A, THROW) + { + th->m_currentException.Assign( evalPos[ 0 ] ); + + EMPTYSTACK(stack, evalPos); + + Library_corlib_native_System_Exception::SetStackTrace( th->m_currentException, stack ); + + NANOCLR_CHECK_HRESULT(CLR_E_PROCESS_EXCEPTION); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_LDFLD, "ldfld", PopRef, Push1, InlineField, IObjModel, 1, 0xFF, 0x7B, NEXT) + // Stack: ... -> ... + { + FETCH_ARG_COMPRESSED_FIELDTOKEN(arg,ip); + + CLR_RT_FieldDef_Instance fieldInst; if(fieldInst.ResolveToken( arg, assm ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + CLR_RT_HeapBlock* obj = &evalPos[ 0 ]; + CLR_DataType dt = obj->DataType(); + + NANOCLR_CHECK_HRESULT(CLR_RT_TypeDescriptor::ExtractObjectAndDataType(obj, dt)); + + switch(dt) + { + case DATATYPE_CLASS: + case DATATYPE_VALUETYPE: + evalPos[ 0 ].Assign( obj[ fieldInst.CrossReference().m_offset ] ); + goto Execute_LoadAndPromote; + case DATATYPE_DATETIME: + case DATATYPE_TIMESPAN: + evalPos[ 0 ].SetInteger( (CLR_INT64)obj->NumericByRefConst().s8 ); + break; +#if defined(NANOCLR_APPDOMAINS) + case DATATYPE_TRANSPARENT_PROXY: + { + CLR_RT_HeapBlock val; + + NANOCLR_CHECK_HRESULT(obj->TransparentProxyValidate()); + + UPDATESTACK(stack,evalPos); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.GetCurrentAppDomain()->MarshalObject( obj->TransparentProxyDereference()[ fieldInst.CrossReference().m_offset ], val, obj->TransparentProxyAppDomain() )); + + evalPos[ 0 ].Assign( val ); + } + goto Execute_LoadAndPromote; +#endif + default: + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + break; + + } + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_LDFLDA, "ldflda", PopRef, PushI, InlineField, IObjModel, 1, 0xFF, 0x7C, NEXT) + // Stack: ... ->
... + { + FETCH_ARG_COMPRESSED_FIELDTOKEN(arg,ip); + + CLR_RT_FieldDef_Instance fieldInst; if(fieldInst.ResolveToken( arg, assm ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + CLR_RT_HeapBlock* obj = &evalPos[ 0 ]; + CLR_DataType dt = obj->DataType(); + + NANOCLR_CHECK_HRESULT(CLR_RT_TypeDescriptor::ExtractObjectAndDataType(obj, dt)); + +#if defined(NANOCLR_APPDOMAINS) + _ASSERTE(dt != DATATYPE_TRANSPARENT_PROXY); +#endif + if(dt == DATATYPE_CLASS || dt == DATATYPE_VALUETYPE) + { + evalPos[ 0 ].SetReference( obj[ fieldInst.CrossReference().m_offset ] ); + } + else if(dt == DATATYPE_DATETIME || dt == DATATYPE_TIMESPAN) // Special case. + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); // NOT SUPPORTED. + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_STFLD, "stfld", PopRef+Pop1, Push0, InlineField, IObjModel, 1, 0xFF, 0x7D, NEXT) + // Stack: ... ... -> ... + { + FETCH_ARG_COMPRESSED_FIELDTOKEN(arg,ip); + + evalPos -= 2; CHECKSTACK(stack,evalPos); + + CLR_RT_FieldDef_Instance fieldInst; if(fieldInst.ResolveToken( arg, assm ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + CLR_RT_HeapBlock* obj = &evalPos[ 1 ]; + CLR_DataType dt = obj->DataType(); + + NANOCLR_CHECK_HRESULT(CLR_RT_TypeDescriptor::ExtractObjectAndDataType(obj, dt)); + + switch(dt) + { + case DATATYPE_CLASS: + case DATATYPE_VALUETYPE: + obj[ fieldInst.CrossReference().m_offset ].AssignAndPreserveType( evalPos[ 2 ] ); + break; + case DATATYPE_DATETIME: // Special case. + case DATATYPE_TIMESPAN: // Special case. + obj->NumericByRef().s8 = evalPos[ 2 ].NumericByRefConst().s8; + break; + +#if defined(NANOCLR_APPDOMAINS) + case DATATYPE_TRANSPARENT_PROXY: + { + CLR_RT_HeapBlock val; + + UPDATESTACK(stack,evalPos); + + NANOCLR_CHECK_HRESULT(obj->TransparentProxyValidate()); + NANOCLR_CHECK_HRESULT(obj->TransparentProxyAppDomain()->MarshalObject( evalPos[ 2 ], val )); + + obj->TransparentProxyDereference()[ fieldInst.CrossReference().m_offset ].AssignAndPreserveType( val ); + } + break; +#endif + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + break; + } + + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_LDSFLD, "ldsfld", Pop0, Push1, InlineField, IObjModel, 1, 0xFF, 0x7E, NEXT) + // Stack: ... -> ... + { + FETCH_ARG_COMPRESSED_FIELDTOKEN(arg,ip); + + CLR_RT_FieldDef_Instance field; if(field.ResolveToken( arg, assm ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + CLR_RT_HeapBlock* ptr = CLR_RT_ExecutionEngine::AccessStaticField( field ); if(ptr == NULL) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + evalPos++; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].Assign( *ptr ); + + goto Execute_LoadAndPromote; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_LDSFLDA, "ldsflda", Pop0, PushI, InlineField, IObjModel, 1, 0xFF, 0x7F, NEXT) + // Stack: ... ->
... + { + FETCH_ARG_COMPRESSED_FIELDTOKEN(arg,ip); + + CLR_RT_FieldDef_Instance field; if(field.ResolveToken( arg, assm ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + CLR_RT_HeapBlock* ptr = CLR_RT_ExecutionEngine::AccessStaticField( field ); if(ptr == NULL) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + evalPos++; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].SetReference( *ptr ); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_STSFLD, "stsfld", Pop1, Push0, InlineField, IObjModel, 1, 0xFF, 0x80, NEXT) + // Stack: ... ... -> ... + { + FETCH_ARG_COMPRESSED_FIELDTOKEN(arg,ip); + + CLR_RT_FieldDef_Instance field; if(field.ResolveToken( arg, assm ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + CLR_RT_HeapBlock* ptr = CLR_RT_ExecutionEngine::AccessStaticField( field ); if(ptr == NULL) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + evalPos--; CHECKSTACK(stack,evalPos); + + ptr->AssignAndPreserveType( evalPos[ 1 ] ); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_BOX, "box", Pop1, PushRef, InlineType, IPrimitive, 1, 0xFF, 0x8C, NEXT) + OPDEF(CEE_UNBOX, "unbox", PopRef, PushI, InlineType, IPrimitive, 1, 0xFF, 0x79, NEXT) + { + FETCH_ARG_COMPRESSED_TYPETOKEN(arg,ip); + + CLR_RT_TypeDef_Instance typeInst; if(typeInst.ResolveToken( arg, assm ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + UPDATESTACK(stack,evalPos); + + if(op == CEE_BOX) + { + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].PerformBoxing( typeInst )); + } + else + { + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].PerformUnboxing( typeInst )); + } + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_UNBOX_ANY, "unbox.any", PopRef, Push1, InlineType, IObjModel, 1, 0xFF, 0xA5, NEXT) + { + //Stack: ... -> ..., value or obj + FETCH_ARG_COMPRESSED_TYPETOKEN(arg,ip); + + //When applied to the boxed form of a value type, the unbox.any instruction + //extracts the value contained within obj (of type O). (It is equivalent to unbox followed by ldobj.) + //When applied to a reference type, the unbox.any instruction has the same effect as castclass typeTok. + + CLR_RT_TypeDef_Instance typeInst; if(typeInst.ResolveToken( arg, assm ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + UPDATESTACK(stack,evalPos); + + if(((typeInst.m_target->flags & CLR_RECORD_TYPEDEF::TD_Semantics_Mask) == CLR_RECORD_TYPEDEF::TD_Semantics_ValueType) || + ((typeInst.m_target->flags & CLR_RECORD_TYPEDEF::TD_Semantics_Mask) == CLR_RECORD_TYPEDEF::TD_Semantics_Enum )) + { + //"unbox" + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].PerformUnboxing( typeInst )); + + //"ldobj" + { + CLR_RT_HeapBlock safeSource; safeSource.Assign( evalPos[ 0 ] ); + CLR_RT_ProtectFromGC gc( safeSource ); + + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].LoadFromReference( safeSource )); + + goto Execute_LoadAndPromote; + } + } + else + { + //"castclass" + NANOCLR_CHECK_HRESULT(CLR_RT_ExecutionEngine::CastToType( evalPos[ 0 ], arg, assm, false )); + } + + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_NEWARR, "newarr", PopI, PushRef, InlineType, IObjModel, 1, 0xFF, 0x8D, NEXT) + { + + FETCH_ARG_COMPRESSED_TYPETOKEN(arg,ip); + + CLR_UINT32 size = evalPos[ 0 ].NumericByRef().u4; + + UPDATESTACK(stack,evalPos); + + stack->m_flags &= ~CLR_RT_StackFrame::c_CompactAndRestartOnOutOfMemory; // we do not need this in this case + + for(int pass=0; pass<2; pass++) + { + hr = CLR_RT_HeapBlock_Array::CreateInstance( evalPos[ 0 ], size, assm, arg ); if(SUCCEEDED(hr)) break; + + // if we have an out of memory exception, perform a compaction and try again. + if (hr == CLR_E_OUT_OF_MEMORY && pass == 0) + { + WRITEBACK(stack, evalPos, ip, fDirty); + g_CLR_RT_ExecutionEngine.PerformHeapCompaction(); + READCACHE(stack, evalPos, ip, fDirty); + } + else + { + NANOCLR_SET_AND_LEAVE(hr); + } + } + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_LDLEN, "ldlen", PopRef, PushI, InlineNone, IObjModel, 1, 0xFF, 0x8E, NEXT) + // Stack: ... -> ... + { + NANOCLR_CHECK_HRESULT(CLR_Checks::VerifyArrayReference( evalPos[ 0 ] )); + + CLR_RT_HeapBlock_Array* array = evalPos[ 0 ].DereferenceArray(); + + evalPos[ 0 ].SetInteger( array->m_numOfElements ); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_LDELEMA, "ldelema", PopRef+PopI, PushI, InlineType, IObjModel, 1, 0xFF, 0x8F, NEXT) + // Stack: ... ->
... + { + ip += 2; // Skip argument, not used... + + evalPos--; CHECKSTACK(stack,evalPos); + + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].InitializeArrayReference( evalPos[ 0 ], evalPos[ 1 ].NumericByRef().s4 )); + + evalPos[ 0 ].FixArrayReferenceForValueTypes(); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_LDELEM_I1, "ldelem.i1", PopRef+PopI, PushI, InlineNone, IObjModel, 1, 0xFF, 0x90, NEXT) + OPDEF(CEE_LDELEM_U1, "ldelem.u1", PopRef+PopI, PushI, InlineNone, IObjModel, 1, 0xFF, 0x91, NEXT) + OPDEF(CEE_LDELEM_I2, "ldelem.i2", PopRef+PopI, PushI, InlineNone, IObjModel, 1, 0xFF, 0x92, NEXT) + OPDEF(CEE_LDELEM_U2, "ldelem.u2", PopRef+PopI, PushI, InlineNone, IObjModel, 1, 0xFF, 0x93, NEXT) + OPDEF(CEE_LDELEM_I4, "ldelem.i4", PopRef+PopI, PushI, InlineNone, IObjModel, 1, 0xFF, 0x94, NEXT) + OPDEF(CEE_LDELEM_U4, "ldelem.u4", PopRef+PopI, PushI, InlineNone, IObjModel, 1, 0xFF, 0x95, NEXT) + OPDEF(CEE_LDELEM_I8, "ldelem.i8", PopRef+PopI, PushI8, InlineNone, IObjModel, 1, 0xFF, 0x96, NEXT) + OPDEF(CEE_LDELEM_I, "ldelem.i", PopRef+PopI, PushI, InlineNone, IObjModel, 1, 0xFF, 0x97, NEXT) + OPDEF(CEE_LDELEM_R4, "ldelem.r4", PopRef+PopI, PushR4, InlineNone, IObjModel, 1, 0xFF, 0x98, NEXT) + OPDEF(CEE_LDELEM_R8, "ldelem.r8", PopRef+PopI, PushR8, InlineNone, IObjModel, 1, 0xFF, 0x99, NEXT) + OPDEF(CEE_LDELEM_REF, "ldelem.ref", PopRef+PopI, PushRef, InlineNone, IObjModel, 1, 0xFF, 0x9A, NEXT) + // Stack: ... -> ... + { + evalPos--; CHECKSTACK(stack,evalPos); + + // + // To load an element from an array, we first initialize a temporary reference to the element and then dereference it. + // + CLR_RT_HeapBlock ref; NANOCLR_CHECK_HRESULT(ref.InitializeArrayReference( evalPos[ 0 ], evalPos[ 1 ].NumericByRef().s4 )); + + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].LoadFromReference( ref )); + + goto Execute_LoadAndPromote; + } + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_LDELEM, "ldelem", PopRef+PopI, Push1, InlineType, IObjModel, 1, 0xFF, 0xA3, NEXT) + // Stack: ... -> + { + // treat this like ldelema + ldobj + // read the type token argument from the instruction and advance the instruction pointer accordingly + // LDELEMA doesn't need the type token, but the ldobj portion does + FETCH_ARG_COMPRESSED_TYPETOKEN(arg,ip); + + // + // move stack pointer back so that evalpos[0] is the array + evalPos--; + CHECKSTACK(stack,evalPos); + + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].InitializeArrayReference( evalPos[ 0 ], evalPos[ 1 ].NumericByRef().s4 )); + + evalPos[ 0 ].FixArrayReferenceForValueTypes(); + // + // + CLR_RT_TypeDef_Instance type; + CLR_RT_TypeDef_Index cls; + + if( !type.ResolveToken( arg, assm ) ) + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + NANOCLR_CHECK_HRESULT(CLR_RT_TypeDescriptor::ExtractTypeIndexFromObject( evalPos[ 0 ], cls )); + + // Check this is an object of the requested type. + if( type.m_data != cls.m_data ) + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + UPDATESTACK(stack,evalPos); + { + // Save the pointer to the object to load/copy and protect it from GC. + CLR_RT_HeapBlock safeSource; + safeSource.Assign( evalPos[ 0 ] ); + CLR_RT_ProtectFromGC gc( safeSource ); + + NANOCLR_CHECK_HRESULT(evalPos[ 0 ].LoadFromReference( safeSource )); + } + + goto Execute_LoadAndPromote; + // + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_STELEM_I, "stelem.i", PopRef+PopI+PopI, Push0, InlineNone, IObjModel, 1, 0xFF, 0x9B, NEXT) + OPDEF(CEE_STELEM_I1, "stelem.i1", PopRef+PopI+PopI, Push0, InlineNone, IObjModel, 1, 0xFF, 0x9C, NEXT) + OPDEF(CEE_STELEM_I2, "stelem.i2", PopRef+PopI+PopI, Push0, InlineNone, IObjModel, 1, 0xFF, 0x9D, NEXT) + OPDEF(CEE_STELEM_I4, "stelem.i4", PopRef+PopI+PopI, Push0, InlineNone, IObjModel, 1, 0xFF, 0x9E, NEXT) + OPDEF(CEE_STELEM_I8, "stelem.i8", PopRef+PopI+PopI8, Push0, InlineNone, IObjModel, 1, 0xFF, 0x9F, NEXT) + OPDEF(CEE_STELEM_R4, "stelem.r4", PopRef+PopI+PopR4, Push0, InlineNone, IObjModel, 1, 0xFF, 0xA0, NEXT) + OPDEF(CEE_STELEM_R8, "stelem.r8", PopRef+PopI+PopR8, Push0, InlineNone, IObjModel, 1, 0xFF, 0xA1, NEXT) + OPDEF(CEE_STELEM_REF, "stelem.ref", PopRef+PopI+PopRef, Push0, InlineNone, IObjModel, 1, 0xFF, 0xA2, NEXT) + // Stack: ... ... -> ... + { + evalPos -= 3; CHECKSTACK(stack,evalPos); + + // + // To load an element from an array, we first initialize a temporary reference to the element and then dereference it. + // + CLR_RT_HeapBlock ref; NANOCLR_CHECK_HRESULT(ref.InitializeArrayReference( evalPos[ 1 ], evalPos[ 2 ].NumericByRef().s4 )); + int size = 0; + + switch(op) + { + case CEE_STELEM_I : size = 4; break; + case CEE_STELEM_I1 : size = 1; break; + case CEE_STELEM_I2 : size = 2; break; + case CEE_STELEM_I4 : size = 4; break; + case CEE_STELEM_I8 : size = 8; break; + case CEE_STELEM_R4 : size = 4; break; + case CEE_STELEM_R8 : size = 8; break; + case CEE_STELEM_REF: size = 0; break; + // the remaining op cpdes aren't to be handled + default: break; + } + + evalPos[ 3 ].Promote(); + + NANOCLR_CHECK_HRESULT(evalPos[ 3 ].StoreToReference( ref, size )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_STELEM, "stelem", PopRef+PopI+Pop1, Push0, InlineType, IObjModel, 1, 0xFF, 0xA4, NEXT) + // Stack: ... ... -> ... + { + // Treat STELEM like ldelema + stobj + ip += 2; // Skip type argument, not used... + + evalPos -= 3; // "pop" args from evaluation stack + CHECKSTACK(stack,evalPos); + + NANOCLR_CHECK_HRESULT(evalPos[ 1 ].InitializeArrayReference( evalPos[ 1 ], evalPos[ 2 ].NumericByRef().s4 )); + evalPos[ 1 ].FixArrayReferenceForValueTypes(); + + // Reassign will make sure these are objects of the same type. + NANOCLR_CHECK_HRESULT(evalPos[ 1 ].Reassign( evalPos[ 3 ] )); + + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_LDTOKEN, "ldtoken", Pop0, PushI, InlineTok, IPrimitive, 1, 0xFF, 0xD0, NEXT) + { + FETCH_ARG_UINT32(arg,ip); + + evalPos++; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].SetObjectReference( NULL ); + + switch(CLR_TypeFromTk( arg )) + { + case TBL_TypeSpec: + { + CLR_RT_TypeSpec_Instance sig; if(sig.ResolveToken( arg, assm ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + evalPos[ 0 ].SetReflection( sig ); + } + break; + + case TBL_TypeRef: + case TBL_TypeDef: + { + CLR_RT_TypeDef_Instance cls; if(cls.ResolveToken( arg, assm ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + evalPos[ 0 ].SetReflection( cls ); + } + break; + + case TBL_FieldRef: + case TBL_FieldDef: + { + CLR_RT_FieldDef_Instance field; if(field.ResolveToken( arg, assm ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + evalPos[ 0 ].SetReflection( field ); + } + break; + + case TBL_MethodRef: + case TBL_MethodDef: + { + CLR_RT_MethodDef_Instance method; if(method.ResolveToken( arg, assm ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + evalPos[ 0 ].SetReflection( method ); + } + break; + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + break; + } + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_ENDFINALLY, "endfinally", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xDC, RETURN) + { + EMPTYSTACK(stack, evalPos); + WRITEBACK(stack,evalPos,ip,fDirty); + + NANOCLR_CHECK_HRESULT(th->ProcessException_EndFinally()); + + _ASSERTE(th->m_currentException.Dereference() == NULL); + stack = th->CurrentFrame(); + goto Execute_Reload; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_LEAVE, "leave", Pop0, Push0, InlineBrTarget, IPrimitive, 1, 0xFF, 0xDD, BRANCH) + OPDEF(CEE_LEAVE_S, "leave.s", Pop0, Push0, ShortInlineBrTarget,IPrimitive, 1, 0xFF, 0xDE, BRANCH) + { + CLR_INT32 arg; + + EMPTYSTACK(stack, evalPos); + + if(op == CEE_LEAVE) + { + NANOCLR_READ_UNALIGNED_INT16( arg, ip ); + } + else + { + NANOCLR_READ_UNALIGNED_INT8( arg, ip ); + } + + { + CLR_PMETADATA ipLeave = ip + arg; + CLR_RT_ExceptionHandler eh; + + th->PopEH( stack, ipLeave ); + + if(th->FindEhBlock( stack, ip-1, ipLeave, eh, true )) + { + UnwindStack* us = th->PushEH(); + _ASSERTE(us); + + us->m_stack = stack; + us->m_exception = NULL; + us->m_ip = ipLeave; + us->m_currentBlockStart = eh.m_handlerStart; + us->m_currentBlockEnd = eh.m_handlerEnd; + us->m_flags = UnwindStack::p_4_NormalCleanup; + + ip = eh.m_handlerStart; + break; + } + + ip = ipLeave; + + if(th->m_flags & CLR_RT_Thread::TH_F_Aborted) + { + _ASSERTE(th->m_currentException.Dereference() == NULL); + + (void)Library_corlib_native_System_Exception::CreateInstance( th->m_currentException, g_CLR_RT_WellKnownTypes.m_ThreadAbortException, S_OK, stack ); + + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } + } + + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_CEQ, "ceq", Pop1+Pop1, PushI, InlineNone, IPrimitive, 2, 0xFE, 0x01, NEXT) + { + evalPos--; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].SetInteger( CLR_RT_HeapBlock::Compare_Signed_Values( evalPos[ 0 ], evalPos[ 1 ] ) == 0 ? 1 : 0 ); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_CGT, "cgt", Pop1+Pop1, PushI, InlineNone, IPrimitive, 2, 0xFE, 0x02, NEXT) + { + evalPos--; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].SetInteger( CLR_RT_HeapBlock::Compare_Signed_Values( evalPos[ 0 ], evalPos[ 1 ] ) > 0 ? 1 : 0 ); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_CGT_UN, "cgt.un", Pop1+Pop1, PushI, InlineNone, IPrimitive, 2, 0xFE, 0x03, NEXT) + { + evalPos--; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].SetInteger( CLR_RT_HeapBlock::Compare_Unsigned_Values( evalPos[ 0 ], evalPos[ 1 ] ) > 0 ? 1 : 0 ); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_CLT, "clt", Pop1+Pop1, PushI, InlineNone, IPrimitive, 2, 0xFE, 0x04, NEXT) + { + evalPos--; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].SetInteger( CLR_RT_HeapBlock::Compare_Signed_Values( evalPos[ 0 ], evalPos[ 1 ] ) < 0 ? 1 : 0 ); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_CLT_UN, "clt.un", Pop1+Pop1, PushI, InlineNone, IPrimitive, 2, 0xFE, 0x05, NEXT) + { + evalPos--; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].SetInteger( CLR_RT_HeapBlock::Compare_Unsigned_Values( evalPos[ 0 ], evalPos[ 1 ] ) < 0 ? 1 : 0 ); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_LDFTN, "ldftn", Pop0, PushI, InlineMethod, IPrimitive, 2, 0xFE, 0x06, NEXT) + { + FETCH_ARG_COMPRESSED_METHODTOKEN(arg,ip); + + evalPos++; CHECKSTACK(stack,evalPos); + + CLR_RT_MethodDef_Instance method; if(method.ResolveToken( arg, assm ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + UPDATESTACK(stack,evalPos); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Delegate::CreateInstance( evalPos[ 0 ], method, stack )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_LDVIRTFTN, "ldvirtftn", PopRef, PushI, InlineMethod, IPrimitive, 2, 0xFE, 0x07, NEXT) + { + FETCH_ARG_COMPRESSED_METHODTOKEN(arg,ip); + + CLR_RT_MethodDef_Instance callee; if(callee.ResolveToken( arg, assm ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + CLR_RT_TypeDef_Index cls; + + NANOCLR_CHECK_HRESULT(CLR_RT_TypeDescriptor::ExtractTypeIndexFromObject( evalPos[ 0 ], cls )); + + CLR_RT_MethodDef_Index calleeReal; + + if(g_CLR_RT_EventCache.FindVirtualMethod( cls, callee, calleeReal ) == false) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + UPDATESTACK(stack,evalPos); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Delegate::CreateInstance( evalPos[ 0 ], calleeReal, stack )); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_INITOBJ, "initobj", PopI, Push0, InlineType, IObjModel, 2, 0xFE, 0x15, NEXT) + { + ip += 2; // Skip argument, not used... + + evalPos->InitObject(); evalPos--; CHECKSTACK(stack,evalPos); + + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_RETHROW, "rethrow", Pop0, Push0, InlineNone, IObjModel, 2, 0xFE, 0x1A, THROW) + { + if(th->m_nestedExceptionsPos == 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_STACK_UNDERFLOW); + } + else + { + UnwindStack& us = th->m_nestedExceptions[ --th->m_nestedExceptionsPos ]; + + if(us.m_exception) + { + th->m_currentException.SetObjectReference( us.m_exception ); + + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_STACK_UNDERFLOW); + } + } + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_SIZEOF, "sizeof", Pop0, PushI, InlineType, IPrimitive, 2, 0xFE, 0x1C, NEXT) + { + FETCH_ARG_COMPRESSED_TYPETOKEN(arg,ip); + + CLR_RT_TypeDef_Instance clsInst; if(clsInst.ResolveToken( arg, assm ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + CLR_INT32 len; + + if(clsInst.m_target->dataType) + { + len = sizeof(CLR_RT_HeapBlock); + } + else + { + len = (CLR_RT_HeapBlock::HB_Object_Fields_Offset + clsInst.CrossReference().m_totalFields) * sizeof(CLR_RT_HeapBlock); + } + + evalPos++; CHECKSTACK(stack,evalPos); + + evalPos[ 0 ].SetInteger( len ); + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_CONSTRAINED, "constrained.", Pop0, Push0, InlineType, IPrefix, 2, 0xFE, 0x16, META) + { + FETCH_ARG_COMPRESSED_TYPETOKEN(arg,ip); + + //nop + break; + } + + //----------------------------------------------------------------------------------------------------------// + + OPDEF(CEE_ENDFILTER, "endfilter", PopI, Push0, InlineNone, IPrimitive, 2, 0xFE, 0x11, RETURN) + { + + CHECKSTACK(stack,evalPos); + WRITEBACK(stack,evalPos,ip,fDirty); + + NANOCLR_CHECK_HRESULT(th->ProcessException_EndFilter()); + + stack = th->CurrentFrame(); + goto Execute_Reload; + } + + //----------------------------------------------------------------------------------------------------------// + + ////////////////////////////////////////////////////////////////////////////////////////// + // + // These opcodes do nothing... + // + OPDEF(CEE_NOP, "nop", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x00, NEXT) + OPDEF(CEE_UNALIGNED, "unaligned.", Pop0, Push0, ShortInlineI, IPrefix, 2, 0xFE, 0x12, META) + OPDEF(CEE_VOLATILE, "volatile.", Pop0, Push0, InlineNone, IPrefix, 2, 0xFE, 0x13, META) + OPDEF(CEE_TAILCALL, "tail.", Pop0, Push0, InlineNone, IPrefix, 2, 0xFE, 0x14, META) + break; + + ////////////////////////////////////////////////////////////////////////////////////////// + // + // Unsupported opcodes... + // + OPDEF(CEE_ARGLIST, "arglist", Pop0, PushI, InlineNone, IPrimitive, 2, 0xFE, 0x00, NEXT) + OPDEF(CEE_CPBLK, "cpblk", PopI+PopI+PopI, Push0, InlineNone, IPrimitive, 2, 0xFE, 0x17, NEXT) + OPDEF(CEE_JMP, "jmp", Pop0, Push0, InlineMethod, IPrimitive, 1, 0xFF, 0x27, CALL) + OPDEF(CEE_INITBLK, "initblk", PopI+PopI+PopI, Push0, InlineNone, IPrimitive, 2, 0xFE, 0x18, NEXT) + OPDEF(CEE_CALLI, "calli", VarPop, VarPush, InlineSig, IPrimitive, 1, 0xFF, 0x29, CALL) + OPDEF(CEE_CKFINITE, "ckfinite", Pop1, PushR8, InlineNone, IPrimitive, 1, 0xFF, 0xC3, NEXT) + OPDEF(CEE_LOCALLOC, "localloc", PopI, PushI, InlineNone, IPrimitive, 2, 0xFE, 0x0F, NEXT) + OPDEF(CEE_MKREFANY, "mkrefany", PopI, Push1, InlineType, IPrimitive, 1, 0xFF, 0xC6, NEXT) + OPDEF(CEE_REFANYTYPE, "refanytype", Pop1, PushI, InlineNone, IPrimitive, 2, 0xFE, 0x1D, NEXT) + OPDEF(CEE_REFANYVAL, "refanyval", Pop1, PushI, InlineType, IPrimitive, 1, 0xFF, 0xC2, NEXT) + OPDEF(CEE_READONLY, "readonly.", Pop0, Push0, InlineNone, IPrefix, 2, 0xFE, 0x1E, META) + + NANOCLR_CHECK_HRESULT(CLR_Checks::VerifyUnsupportedInstruction( op )); + break; + + ////////////////////////////////////////////////////////////////////////////////////////// + + default: + NANOCLR_CHECK_HRESULT(CLR_Checks::VerifyUnknownInstruction( op )); + break; +#undef OPDEF + } + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(stack->m_flags & CLR_RT_StackFrame::c_HasBreakpoint) + { + g_CLR_RT_ExecutionEngine.Breakpoint_StackFrame_Step( stack, ip ); + } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + continue; + + //--// + + Execute_LoadAndPromote: + + { + CLR_RT_HeapBlock& res = evalPos[ 0 ]; + + switch(res.DataType()) + { + case DATATYPE_VOID : break; + + case DATATYPE_BOOLEAN : res.ChangeDataType( DATATYPE_I4 ); res.NumericByRef().u4 = (CLR_UINT32)res.NumericByRef().u1; break; + case DATATYPE_I1 : res.ChangeDataType( DATATYPE_I4 ); res.NumericByRef().s4 = (CLR_INT32 )res.NumericByRef().s1; break; + case DATATYPE_U1 : res.ChangeDataType( DATATYPE_I4 ); res.NumericByRef().u4 = (CLR_UINT32)res.NumericByRef().u1; break; + + case DATATYPE_CHAR : res.ChangeDataType( DATATYPE_I4 ); res.NumericByRef().u4 = (CLR_UINT32)res.NumericByRef().u2; break; + case DATATYPE_I2 : res.ChangeDataType( DATATYPE_I4 ); res.NumericByRef().s4 = (CLR_INT32 )res.NumericByRef().s2; break; + case DATATYPE_U2 : res.ChangeDataType( DATATYPE_I4 ); res.NumericByRef().u4 = (CLR_UINT32)res.NumericByRef().u2; break; + + case DATATYPE_I4 : break; + case DATATYPE_U4 : break; + case DATATYPE_R4 : break; + + case DATATYPE_I8 : break; + case DATATYPE_U8 : break; + case DATATYPE_R8 : break; + case DATATYPE_DATETIME: break; + case DATATYPE_TIMESPAN: break; + case DATATYPE_STRING : break; + + case DATATYPE_OBJECT : + if(evalPos[ 0 ].IsAValueType()) + { + UPDATESTACK(stack,evalPos); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.CloneObject( evalPos[ 0 ], evalPos[ 0 ] )); + } + break; + + // the remaining data types aren't to be handled + default: break; + } + } + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(stack->m_flags & CLR_RT_StackFrame::c_HasBreakpoint) + { + g_CLR_RT_ExecutionEngine.Breakpoint_StackFrame_Step( stack, ip ); + } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + continue; + + //--// + + Execute_BR: + { + CLR_INT32 offset; + + if(c_CLR_RT_OpcodeLookup[ op ].m_opParam == CLR_OpcodeParam_ShortBrTarget) + { + NANOCLR_READ_UNALIGNED_INT8( offset, ip ); + } + else + { + NANOCLR_READ_UNALIGNED_INT16( offset, ip ); + } + + if(fCondition) ip += offset; + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(stack->m_flags & CLR_RT_StackFrame::c_HasBreakpoint) + { + g_CLR_RT_ExecutionEngine.Breakpoint_StackFrame_Step( stack, ip ); + } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + if(th->m_timeQuantumExpired) + { + NANOCLR_SET_AND_LEAVE( CLR_S_QUANTUM_EXPIRED ); + } + + continue; + } + + //--// + + Execute_Restart: + { + CLR_RT_StackFrame* stackNext = th->CurrentFrame(); + + #if defined(ENABLE_NATIVE_PROFILER) + if(stackNext->m_flags & CLR_RT_StackFrame::c_NativeProfiled) + { + stackNext->m_owningThread->m_fNativeProfiled = true; + Native_Profiler_Start(); + } + else if(stackNext->m_fNativeProfiled == false) + { + stackNext->m_owningThread->m_fNativeProfiled = false; + Native_Profiler_Stop(); + } + #endif + + if((stackNext->m_flags & CLR_RT_StackFrame::c_CallerIsCompatibleForCall) == 0) + { + NANOCLR_SET_AND_LEAVE( CLR_S_RESTART_EXECUTION ); + } + + // + // Same kind of handler, no need to pop back out, just restart execution in place. + // + stack->m_flags &= ~CLR_RT_StackFrame::c_ExecutingIL; + + stack = stackNext; + goto Execute_Reload; + } + + Execute_Reload: + { + stack->m_flags |= CLR_RT_StackFrame::c_ExecutingIL; + + assm = stack->m_call.m_assm; + + READCACHE(stack,evalPos,ip,fDirty); + continue; + } + } + } + + + NANOCLR_CLEANUP(); + + if(fDirty) + { + WRITEBACK(stack,evalPos,ip,fDirty); + } + + NANOCLR_CLEANUP_END(); +} + diff --git a/source/native/nf-interpreter/src/CLR/Core/InterruptHandler/InterruptHandler-vs2019.vcxproj b/source/native/nf-interpreter/src/CLR/Core/InterruptHandler/InterruptHandler-vs2019.vcxproj new file mode 100644 index 00000000..e250c980 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/InterruptHandler/InterruptHandler-vs2019.vcxproj @@ -0,0 +1,159 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + {D32EE397-7E49-452D-AC95-AFCB3C962E3D} + Win32Proj + InterruptHandler + 10.0.17763.0 + InterruptHandler + + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + false + v142 + true + Unicode + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + false + v142 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(SolutionDir)$(Configuration)\ + $(IntDir) + + + $(SolutionDir)$(Configuration)\ + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/InterruptHandler/InterruptHandler-vs2019.vcxproj.filters b/source/native/nf-interpreter/src/CLR/Core/InterruptHandler/InterruptHandler-vs2019.vcxproj.filters new file mode 100644 index 00000000..56780121 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/InterruptHandler/InterruptHandler-vs2019.vcxproj.filters @@ -0,0 +1,22 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/InterruptHandler/InterruptHandler.cpp b/source/native/nf-interpreter/src/CLR/Core/InterruptHandler/InterruptHandler.cpp new file mode 100644 index 00000000..feec3bef --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/InterruptHandler/InterruptHandler.cpp @@ -0,0 +1,147 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include + +//////////////////////////////////////////////////////////////////////////////////////////////////// + + //this method is called by Hardware_Initialize + //If you want to initialize your own interrupt handling related objects, put them here + +HRESULT CLR_HW_Hardware::ManagedHardware_Initialize() +{ + NATIVE_PROFILE_CLR_HARDWARE(); + + NANOCLR_HEADER(); + + m_interruptData.m_HalQueue.Initialize( (CLR_HW_Hardware::HalInterruptRecord*)&g_scratchInterruptDispatchingStorage, InterruptRecords() ); + + m_interruptData.m_applicationQueue.DblLinkedList_Initialize (); + + m_interruptData.m_queuedInterrupts = 0; + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT CLR_HW_Hardware::SpawnDispatcher() +{ + NATIVE_PROFILE_CLR_HARDWARE(); + + NANOCLR_HEADER(); + + CLR_RT_ApplicationInterrupt* interrupt; + CLR_RT_HeapBlock_NativeEventDispatcher* ioPort; + CLR_RT_HeapBlock_NativeEventDispatcher ::InterruptPortInterrupt *interruptData; + + // if reboot is in progress, just bail out + if(CLR_EE_DBG_IS( RebootPending )) + { + return S_OK; + } + + interrupt = (CLR_RT_ApplicationInterrupt*)m_interruptData.m_applicationQueue.FirstValidNode(); + + if((interrupt == NULL) || !g_CLR_RT_ExecutionEngine.EnsureSystemThread( g_CLR_RT_ExecutionEngine.m_interruptThread, ThreadPriority::System_Highest )) + { + return S_OK; + } + + interrupt->Unlink(); + + interruptData = &interrupt->m_interruptPortInterrupt; + ioPort = interruptData->context; + + CLR_RT_ProtectFromGC gc1 ( *ioPort ); + + NANOCLR_SET_AND_LEAVE(ioPort->StartDispatch( interrupt, g_CLR_RT_ExecutionEngine.m_interruptThread )); + + NANOCLR_CLEANUP(); + + if(FAILED(hr)) + { + ioPort->ThreadTerminationCallback( interrupt ); + } + + --m_interruptData.m_queuedInterrupts; + + NANOCLR_CLEANUP_END(); +} + +HRESULT CLR_HW_Hardware::TransferAllInterruptsToApplicationQueue() +{ + NATIVE_PROFILE_CLR_HARDWARE(); + + NANOCLR_HEADER(); + + while(true) + { + HalInterruptRecord* rec; + + { + GLOBAL_LOCK(); + + rec = m_interruptData.m_HalQueue.Peek(); + + GLOBAL_UNLOCK(); + } + + if(rec == NULL) break; + + CLR_RT_ApplicationInterrupt* queueRec = (CLR_RT_ApplicationInterrupt*)CLR_RT_Memory::Allocate_And_Erase( sizeof(CLR_RT_ApplicationInterrupt), CLR_RT_HeapBlock::HB_CompactOnFailure ); CHECK_ALLOCATION(queueRec); + + queueRec->m_interruptPortInterrupt.data1 = rec->m_data1; + queueRec->m_interruptPortInterrupt.data2 = rec->m_data2; + queueRec->m_interruptPortInterrupt.data3 = rec->m_data3; + queueRec->m_interruptPortInterrupt.time = rec->m_time; + queueRec->m_interruptPortInterrupt.context = (CLR_RT_HeapBlock_NativeEventDispatcher*)rec->m_context; + + m_interruptData.m_applicationQueue.LinkAtBack( queueRec ); ++m_interruptData.m_queuedInterrupts; + + { + GLOBAL_LOCK(); + + m_interruptData.m_HalQueue.Pop(); + + GLOBAL_UNLOCK(); + } + } + + if(m_interruptData.m_queuedInterrupts == 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_NO_INTERRUPT); + } + + NANOCLR_CLEANUP(); + + if(CLR_E_OUT_OF_MEMORY == hr) + { + // if there is no memory left discard all interrupts to avoid getting into a death spiral of OOM exceptions + { + GLOBAL_LOCK(); + + while(!m_interruptData.m_HalQueue.IsEmpty()) + { + m_interruptData.m_HalQueue.Pop(); + } + + GLOBAL_UNLOCK(); + } + } + + NANOCLR_CLEANUP_END(); +} + +HRESULT CLR_HW_Hardware::ProcessInterrupts() +{ + NATIVE_PROFILE_CLR_HARDWARE(); + + NANOCLR_HEADER(); + + NANOCLR_CHECK_HRESULT(TransferAllInterruptsToApplicationQueue()); + + SpawnDispatcher(); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/Core/InterruptHandler/InterruptHandler.vcxproj b/source/native/nf-interpreter/src/CLR/Core/InterruptHandler/InterruptHandler.vcxproj new file mode 100644 index 00000000..4d2c5fc3 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/InterruptHandler/InterruptHandler.vcxproj @@ -0,0 +1,158 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + {D32EE397-7E49-452D-AC95-AFCB3C962E3D} + Win32Proj + InterruptHandler + 10.0.17763.0 + + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\ + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\ + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/InterruptHandler/InterruptHandler.vcxproj.filters b/source/native/nf-interpreter/src/CLR/Core/InterruptHandler/InterruptHandler.vcxproj.filters new file mode 100644 index 00000000..56780121 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/InterruptHandler/InterruptHandler.vcxproj.filters @@ -0,0 +1,22 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/InterruptHandler/InterruptHandler_stub.cpp b/source/native/nf-interpreter/src/CLR/Core/InterruptHandler/InterruptHandler_stub.cpp new file mode 100644 index 00000000..83e44e2e --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/InterruptHandler/InterruptHandler_stub.cpp @@ -0,0 +1,33 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +__nfweak HRESULT CLR_HW_Hardware::ManagedHardware_Initialize() +{ + NATIVE_PROFILE_CLR_HARDWARE(); + NANOCLR_SYSTEM_STUB_RETURN(); +} + +__nfweak HRESULT CLR_HW_Hardware::SpawnDispatcher() +{ + NATIVE_PROFILE_CLR_HARDWARE(); + NANOCLR_SYSTEM_STUB_RETURN(); + +} + +__nfweak HRESULT CLR_HW_Hardware::TransferAllInterruptsToApplicationQueue() +{ + NATIVE_PROFILE_CLR_HARDWARE(); + NANOCLR_SYSTEM_STUB_RETURN(); +} + +__nfweak HRESULT CLR_HW_Hardware::ProcessInterrupts() +{ + NATIVE_PROFILE_CLR_HARDWARE(); + NANOCLR_SYSTEM_STUB_RETURN(); +} diff --git a/source/native/nf-interpreter/src/CLR/Core/InterruptHandler/InterruptHandler_stub.vcxproj b/source/native/nf-interpreter/src/CLR/Core/InterruptHandler/InterruptHandler_stub.vcxproj new file mode 100644 index 00000000..5216874f --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/InterruptHandler/InterruptHandler_stub.vcxproj @@ -0,0 +1,158 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + {5772D362-7277-49CF-9B49-42335A3154BD} + Win32Proj + InterruptHandler_stub + 10.0.17763.0 + + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/InterruptHandler/InterruptHandler_stub.vcxproj.filters b/source/native/nf-interpreter/src/CLR/Core/InterruptHandler/InterruptHandler_stub.vcxproj.filters new file mode 100644 index 00000000..9dc77bab --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/InterruptHandler/InterruptHandler_stub.vcxproj.filters @@ -0,0 +1,22 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/NativeEventDispatcher/NativeEventDispatcher.cpp b/source/native/nf-interpreter/src/CLR/Core/NativeEventDispatcher/NativeEventDispatcher.cpp new file mode 100644 index 00000000..198de873 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/NativeEventDispatcher/NativeEventDispatcher.cpp @@ -0,0 +1,289 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "stdafx.h" +#include +#include + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +CLR_RT_DblLinkedList CLR_RT_HeapBlock_NativeEventDispatcher::eventList; + +void CLR_RT_HeapBlock_NativeEventDispatcher::HandlerMethod_Initialize() +{ + NATIVE_PROFILE_CLR_IOPORT(); + + CLR_RT_HeapBlock_NativeEventDispatcher::eventList.DblLinkedList_Initialize(); +} + +void CLR_RT_HeapBlock_NativeEventDispatcher::HandlerMethod_RecoverFromGC() +{ + NATIVE_PROFILE_CLR_IOPORT(); + + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_NativeEventDispatcher, event, CLR_RT_HeapBlock_NativeEventDispatcher::eventList) + { + event->RecoverFromGC(); + } + NANOCLR_FOREACH_NODE_END(); +} + +void CLR_RT_HeapBlock_NativeEventDispatcher::HandlerMethod_CleanUp() +{ + NATIVE_PROFILE_CLR_IOPORT(); + + CLR_RT_HeapBlock_NativeEventDispatcher* event; + + while(NULL != (event = (CLR_RT_HeapBlock_NativeEventDispatcher*)CLR_RT_HeapBlock_NativeEventDispatcher::eventList.FirstValidNode())) + { + if(event->driverMethods != NULL) + { + event->driverMethods->cleanupProcessor(event); + } + + event->DetachAll(); + event->ReleaseWhenDeadEx(); + } +} + +HRESULT CLR_RT_HeapBlock_NativeEventDispatcher::CreateInstance( CLR_RT_HeapBlock& owner, CLR_RT_HeapBlock& eventRef ) +{ + NATIVE_PROFILE_CLR_IOPORT(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_NativeEventDispatcher* event = NULL; + + event = EVENTCACHE_EXTRACT_NODE(g_CLR_RT_EventCache,CLR_RT_HeapBlock_NativeEventDispatcher,DATATYPE_IO_PORT); CHECK_ALLOCATION(event); + + { + + CLR_RT_ProtectFromGC gc( *event ); + + event->Initialize(); + + eventList.LinkAtBack( event ); + + NANOCLR_CHECK_HRESULT(CLR_RT_ObjectToEvent_Source::CreateInstance( event, owner, eventRef )); + + } + + // Set pointer to driver custom data to NULL. It initialized later by users of CLR_RT_HeapBlock_NativeEventDispatcher + event->pDrvCustomData = NULL; + // Set pointers to drivers methods to NULL. + event->driverMethods = NULL; + + NANOCLR_CLEANUP(); + + if(FAILED(hr)) + { + if(event) + { + event->ReleaseWhenDead(); + } + } + + NANOCLR_CLEANUP_END(); +} + +HRESULT CLR_RT_HeapBlock_NativeEventDispatcher::ExtractInstance( CLR_RT_HeapBlock& ref, CLR_RT_HeapBlock_NativeEventDispatcher*& event ) +{ + NATIVE_PROFILE_CLR_IOPORT(); + + NANOCLR_HEADER(); + + CLR_RT_ObjectToEvent_Source* src = CLR_RT_ObjectToEvent_Source::ExtractInstance( ref ); FAULT_ON_NULL(src); + + event = (CLR_RT_HeapBlock_NativeEventDispatcher*)src->m_eventPtr; + + NANOCLR_NOCLEANUP(); +} + +void CLR_RT_HeapBlock_NativeEventDispatcher::RecoverFromGC() +{ + NATIVE_PROFILE_CLR_IOPORT(); + + CheckAll(); + + ReleaseWhenDeadEx(); +} + +bool CLR_RT_HeapBlock_NativeEventDispatcher::ReleaseWhenDeadEx() +{ + NATIVE_PROFILE_CLR_IOPORT(); + + if(!IsReadyForRelease()) return false; + + //remove any queued interrupts for this event + NANOCLR_FOREACH_NODE(CLR_RT_ApplicationInterrupt,interrupt,g_CLR_HW_Hardware.m_interruptData.m_applicationQueue) + { + if(this == interrupt->m_interruptPortInterrupt.context) + { + interrupt->Unlink(); + + --g_CLR_HW_Hardware.m_interruptData.m_queuedInterrupts; + + ThreadTerminationCallback( interrupt ); + } + } + NANOCLR_FOREACH_NODE_END(); + + return ReleaseWhenDead(); +} + +/************************************************************************************************************ +** Iterates over HAL queue and remove records that point to this instance of CLR_RT_HeapBlock_NativeEventDispatcher. +** This operation should be done from Dispose as part of destroying the CLR_RT_HeapBlock_NativeEventDispatcher +** +*************************************************************************************************************/ + +void CLR_RT_HeapBlock_NativeEventDispatcher::RemoveFromHALQueue() +{ + // Since we are going to analyze and update the queue we need to disable interrupts. + // Interrupt service routines add records to this queue. + GLOBAL_LOCK(); + CLR_UINT32 elemCount = g_CLR_HW_Hardware.m_interruptData.m_HalQueue.NumberOfElements(); + GLOBAL_UNLOCK(); + + // For all elements in the queue + for ( CLR_UINT32 curElem = 0; curElem < elemCount; curElem++ ) + { + // Retrieve the element ( actually remove it from the queue ) + GLOBAL_LOCK(); + CLR_HW_Hardware::HalInterruptRecord* testRec = g_CLR_HW_Hardware.m_interruptData.m_HalQueue.Pop(); + GLOBAL_UNLOCK(); + + // Check if context of this record points to the instance of CLR_RT_HeapBlock_NativeEventDispatcher + // If the "context" is the same as "this", then we skip the "Push" and record is removed. + if ( testRec->m_context != this ) + { + // If it is different from this instance of CLR_RT_HeapBlock_NativeEventDispatcher, thin push it back + GLOBAL_LOCK(); + CLR_HW_Hardware::HalInterruptRecord* newRec = g_CLR_HW_Hardware.m_interruptData.m_HalQueue.Push(); + GLOBAL_UNLOCK(); + + newRec->AssignFrom( *testRec ); + } + } +} + +void CLR_RT_HeapBlock_NativeEventDispatcher::SaveToHALQueue( uint32_t data1, uint32_t data2 ) +{ + NATIVE_PROFILE_CLR_IOPORT(); + + CLR_HW_Hardware::HalInterruptRecord* rec = g_CLR_HW_Hardware.m_interruptData.m_HalQueue.Push(); + + if(rec == NULL) + { + // remove the oldest interrupt to make room for the newest + g_CLR_HW_Hardware.m_interruptData.m_HalQueue.Pop(); + + rec = g_CLR_HW_Hardware.m_interruptData.m_HalQueue.Push(); + } + + if(rec) + { + rec->m_data1 = data1; + rec->m_data2 = data2; + rec->m_context = this; + rec->m_time = HAL_Time_CurrentTime(); + } + + ::Events_Set( SYSTEM_EVENT_HW_INTERRUPT ); +} + +void SaveNativeEventToHALQueue( CLR_RT_HeapBlock_NativeEventDispatcher *pContext, uint32_t data1, uint32_t data2 ) +{ + pContext->SaveToHALQueue( data1, data2 ); +} + +void CleanupNativeEventsFromHALQueue( CLR_RT_HeapBlock_NativeEventDispatcher *pContext ) +{ + pContext->RemoveFromHALQueue(); +} + +HRESULT CLR_RT_HeapBlock_NativeEventDispatcher::StartDispatch( CLR_RT_ApplicationInterrupt* appInterrupt, CLR_RT_Thread* th ) +{ + NATIVE_PROFILE_CLR_IOPORT(); + + NANOCLR_HEADER(); + + CLR_RT_StackFrame* stackTop; + CLR_RT_HeapBlock* args; + CLR_RT_HeapBlock_Delegate* dlg; + CLR_RT_HeapBlock* event; + const CLR_UINT64 c_UTCMask = 0x8000000000000000ULL; + + InterruptPortInterrupt& interrupt = appInterrupt->m_interruptPortInterrupt; + + NANOCLR_CHECK_HRESULT(RecoverManagedObject( event )); + dlg = event[ Library_nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher::FIELD__threadSpawn ].DereferenceDelegate(); FAULT_ON_NULL(dlg); + + NANOCLR_CHECK_HRESULT(th->PushThreadProcDelegate( dlg )); + + stackTop = th->CurrentFrame(); + + args = stackTop->m_arguments; + + if((stackTop->m_call.m_target->flags & CLR_RECORD_METHODDEF::MD_Static) == 0) + { + ++args; + } + + // + // set values for delegate arguments + // + args[0].SetInteger ( interrupt.data1 ); + args[1].SetInteger ( interrupt.data2 ); + args[2].SetInteger ( (CLR_UINT64)interrupt.time | c_UTCMask ); + args[2].ChangeDataType( DATATYPE_DATETIME ); + + th->m_terminationCallback = CLR_RT_HeapBlock_NativeEventDispatcher::ThreadTerminationCallback; + th->m_terminationParameter = appInterrupt; + + NANOCLR_NOCLEANUP(); +} + +void CLR_RT_HeapBlock_NativeEventDispatcher::ThreadTerminationCallback( void* arg ) +{ + NATIVE_PROFILE_CLR_IOPORT(); + + CLR_RT_ApplicationInterrupt* appInterrupt = (CLR_RT_ApplicationInterrupt*)arg; + CLR_RT_HeapBlock_NativeEventDispatcher::InterruptPortInterrupt& interrupt = appInterrupt->m_interruptPortInterrupt; + + FreeManagedEvent((interrupt.data1 >> 8) & 0xff, //category + (interrupt.data1 ) & 0xff, //subCategory + interrupt.data1 >> 16 , //data1 + interrupt.data2 ); + + interrupt.data1 = 0; + interrupt.data2 = 0; + + CLR_RT_Memory::Release( appInterrupt ); + + g_CLR_HW_Hardware.SpawnDispatcher(); +} + +HRESULT CLR_RT_HeapBlock_NativeEventDispatcher::RecoverManagedObject( CLR_RT_HeapBlock*& event ) +{ + NATIVE_PROFILE_CLR_IOPORT(); + + NANOCLR_HEADER(); + + // recover the managed object + NANOCLR_FOREACH_NODE(CLR_RT_ObjectToEvent_Source,ref,this->m_references) + { + if(ref->m_objectPtr) + { + event = ref->m_objectPtr; + NANOCLR_SET_AND_LEAVE(S_OK); + } + } + NANOCLR_FOREACH_NODE_END(); + + event = NULL; + + NANOCLR_SET_AND_LEAVE(CLR_E_PIN_DEAD); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/CLR/Core/NativeEventDispatcher/NativeEventDispatcher.vcxproj b/source/native/nf-interpreter/src/CLR/Core/NativeEventDispatcher/NativeEventDispatcher.vcxproj new file mode 100644 index 00000000..0874202a --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/NativeEventDispatcher/NativeEventDispatcher.vcxproj @@ -0,0 +1,158 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + {6DD5CA4F-2AE9-44D3-B9D7-A2A4A35FC5B2} + Win32Proj + NativeEventDispatcher + 10.0.17763.0 + + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\..\HAL\Include;..\..\..\PAL\Include;..\..\..\nanoFramework.Runtime.Events + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include;..\..\CorLib + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\..\HAL\Include;..\..\..\PAL\Include;..\..\..\nanoFramework.Runtime.Events + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include;..\..\CorLib + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/NativeEventDispatcher/NativeEventDispatcher.vcxproj.filters b/source/native/nf-interpreter/src/CLR/Core/NativeEventDispatcher/NativeEventDispatcher.vcxproj.filters new file mode 100644 index 00000000..2c106a47 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/NativeEventDispatcher/NativeEventDispatcher.vcxproj.filters @@ -0,0 +1,22 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/NativeEventDispatcher/NativeEventDispatcher_stub.cpp b/source/native/nf-interpreter/src/CLR/Core/NativeEventDispatcher/NativeEventDispatcher_stub.cpp new file mode 100644 index 00000000..1f739010 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/NativeEventDispatcher/NativeEventDispatcher_stub.cpp @@ -0,0 +1,106 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "stdafx.h" +#include + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +__nfweak void CLR_RT_HeapBlock_NativeEventDispatcher::HandlerMethod_Initialize() +{ + NATIVE_PROFILE_CLR_IOPORT(); +} + +__nfweak void CLR_RT_HeapBlock_NativeEventDispatcher::HandlerMethod_RecoverFromGC() +{ + NATIVE_PROFILE_CLR_IOPORT(); +} + +__nfweak void CLR_RT_HeapBlock_NativeEventDispatcher::HandlerMethod_CleanUp() +{ + NATIVE_PROFILE_CLR_IOPORT(); +} + +__nfweak void SaveNativeEventToHALQueue( CLR_RT_HeapBlock_NativeEventDispatcher *pContext, uint32_t data1, uint32_t data2 ) +{ + (void)pContext; + (void)data1; + (void)data2; + + NATIVE_PROFILE_CLR_IOPORT(); +} + +__nfweak void CleanupNativeEventsFromHALQueue( CLR_RT_HeapBlock_NativeEventDispatcher *pContext ) +{ + (void)pContext; + + NATIVE_PROFILE_CLR_IOPORT(); +} + +__nfweak HRESULT CLR_RT_HeapBlock_NativeEventDispatcher::CreateInstance( CLR_RT_HeapBlock& owner, CLR_RT_HeapBlock& portRef ) +{ + (void)owner; + (void)portRef; + + NATIVE_PROFILE_CLR_IOPORT(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +__nfweak HRESULT CLR_RT_HeapBlock_NativeEventDispatcher::ExtractInstance( CLR_RT_HeapBlock& ref, CLR_RT_HeapBlock_NativeEventDispatcher*& port ) +{ + (void)ref; + (void)port; + + NATIVE_PROFILE_CLR_IOPORT(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +__nfweak void CLR_RT_HeapBlock_NativeEventDispatcher::RecoverFromGC() +{ + NATIVE_PROFILE_CLR_IOPORT(); +} + +__nfweak bool CLR_RT_HeapBlock_NativeEventDispatcher::ReleaseWhenDeadEx() +{ + NATIVE_PROFILE_CLR_IOPORT(); + return true; +} + +__nfweak void CLR_RT_HeapBlock_NativeEventDispatcher::RemoveFromHALQueue() +{ + NATIVE_PROFILE_CLR_IOPORT(); +} + +__nfweak void CLR_RT_HeapBlock_NativeEventDispatcher::SaveToHALQueue( uint32_t data1, uint32_t data2 ) +{ + (void)data1; + (void)data2; + + NATIVE_PROFILE_CLR_IOPORT(); +} + +__nfweak HRESULT CLR_RT_HeapBlock_NativeEventDispatcher::StartDispatch( CLR_RT_ApplicationInterrupt* appInterrupt, CLR_RT_Thread* th ) +{ + (void)appInterrupt; + (void)th; + + NATIVE_PROFILE_CLR_IOPORT(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +__nfweak void CLR_RT_HeapBlock_NativeEventDispatcher::ThreadTerminationCallback( void* arg ) +{ + (void)arg; + + NATIVE_PROFILE_CLR_IOPORT(); +} + +__nfweak HRESULT CLR_RT_HeapBlock_NativeEventDispatcher::RecoverManagedObject( CLR_RT_HeapBlock*& port ) +{ + (void)port; + + NATIVE_PROFILE_CLR_IOPORT(); + NANOCLR_FEATURE_STUB_RETURN(); +} diff --git a/source/native/nf-interpreter/src/CLR/Core/NativeEventDispatcher/NativeEventDispatcher_stub.vcxproj b/source/native/nf-interpreter/src/CLR/Core/NativeEventDispatcher/NativeEventDispatcher_stub.vcxproj new file mode 100644 index 00000000..657d659a --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/NativeEventDispatcher/NativeEventDispatcher_stub.vcxproj @@ -0,0 +1,158 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + {5406EB0C-2243-47E1-9F21-F2D7CA277092} + Win32Proj + NativeEventDispatcher_stub + 10.0.17763.0 + + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/NativeEventDispatcher/NativeEventDispatcher_stub.vcxproj.filters b/source/native/nf-interpreter/src/CLR/Core/NativeEventDispatcher/NativeEventDispatcher_stub.vcxproj.filters new file mode 100644 index 00000000..de337611 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/NativeEventDispatcher/NativeEventDispatcher_stub.vcxproj.filters @@ -0,0 +1,22 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/RPC/CLR_RT_HeapBlock_EndPoint.cpp b/source/native/nf-interpreter/src/CLR/Core/RPC/CLR_RT_HeapBlock_EndPoint.cpp new file mode 100644 index 00000000..a529b6f8 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/RPC/CLR_RT_HeapBlock_EndPoint.cpp @@ -0,0 +1,130 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include + +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +CLR_RT_DblLinkedList CLR_RT_HeapBlock_EndPoint::m_endPoints; + +void CLR_RT_HeapBlock_EndPoint::HandlerMethod_Initialize() +{ + CLR_RT_HeapBlock_EndPoint::m_endPoints.DblLinkedList_Initialize(); +} + +void CLR_RT_HeapBlock_EndPoint::HandlerMethod_RecoverFromGC() +{ + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_EndPoint,endPoint,CLR_RT_HeapBlock_EndPoint::m_endPoints) + { + endPoint->RecoverFromGC(); + } + NANOCLR_FOREACH_NODE_END(); +} + +void CLR_RT_HeapBlock_EndPoint::HandlerMethod_CleanUp() +{ +} + +CLR_RT_HeapBlock_EndPoint* CLR_RT_HeapBlock_EndPoint::FindEndPoint( const CLR_RT_HeapBlock_EndPoint::Port& port ) +{ + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_EndPoint,endPoint,CLR_RT_HeapBlock_EndPoint::m_endPoints) + { + if((endPoint->m_addr.m_type == port.m_type) && (endPoint->m_addr.m_id == port.m_id)) return endPoint; //eliminate the need for another func. call; member variables are public + } + NANOCLR_FOREACH_NODE_END(); + + return NULL; +} + +bool CLR_RT_HeapBlock_EndPoint::Port::Compare( const CLR_RT_HeapBlock_EndPoint::Port& port ) +{ + return m_type == port.m_type && m_id == port.m_id; +} + +//--// + +HRESULT CLR_RT_HeapBlock_EndPoint::CreateInstance( const CLR_RT_HeapBlock_EndPoint::Port& port, CLR_RT_HeapBlock& owner, CLR_RT_HeapBlock& epRef ) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_EndPoint* endPoint = NULL; + + // + // Create a request and stop the calling thread. + // + endPoint = EVENTCACHE_EXTRACT_NODE(g_CLR_RT_EventCache,CLR_RT_HeapBlock_EndPoint,DATATYPE_ENDPOINT_HEAD); CHECK_ALLOCATION(endPoint); + + { + CLR_RT_ProtectFromGC gc( *endPoint ); + + endPoint->Initialize(); + + endPoint->m_seq = 0; + endPoint->m_addr = port; + + endPoint->m_messages.DblLinkedList_Initialize(); + + CLR_RT_HeapBlock_EndPoint::m_endPoints.LinkAtBack( endPoint ); + + NANOCLR_SET_AND_LEAVE(CLR_RT_ObjectToEvent_Source::CreateInstance( endPoint, owner, epRef )); + } + + NANOCLR_CLEANUP(); + + if(FAILED(hr)) + { + if(endPoint) endPoint->ReleaseWhenDeadEx(); + } + + NANOCLR_CLEANUP_END(); +} + +HRESULT CLR_RT_HeapBlock_EndPoint::ExtractInstance( CLR_RT_HeapBlock& ref, CLR_RT_HeapBlock_EndPoint*& endPoint ) +{ + NANOCLR_HEADER(); + + CLR_RT_ObjectToEvent_Source* src = CLR_RT_ObjectToEvent_Source::ExtractInstance( ref ); FAULT_ON_NULL(src); + + endPoint = (CLR_RT_HeapBlock_EndPoint*)src->m_eventPtr; + + NANOCLR_NOCLEANUP(); +} + +bool CLR_RT_HeapBlock_EndPoint::ReleaseWhenDeadEx() +{ + if(!IsReadyForRelease()) return false; + + m_messages.DblLinkedList_Release(); + + return ReleaseWhenDead(); +} + +//--// + +void CLR_RT_HeapBlock_EndPoint::RecoverFromGC() +{ + CheckAll(); + + ReleaseWhenDeadEx(); +} + +//--// + +CLR_RT_HeapBlock_EndPoint::Message* CLR_RT_HeapBlock_EndPoint::FindMessage( CLR_UINT32 cmd, const CLR_UINT32* seq ) +{ + NANOCLR_FOREACH_NODE(Message,msg,m_messages) + { + if(msg->m_cmd == cmd) + { + if(!seq ) return msg; + if(msg->m_addr.m_seq == *seq) return msg; + } + } + NANOCLR_FOREACH_NODE_END(); + + return NULL; +} + diff --git a/source/native/nf-interpreter/src/CLR/Core/RPC/RPC-vs2019.vcxproj b/source/native/nf-interpreter/src/CLR/Core/RPC/RPC-vs2019.vcxproj new file mode 100644 index 00000000..595bc5e5 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/RPC/RPC-vs2019.vcxproj @@ -0,0 +1,159 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + {ED4C887A-EC09-465B-B5D9-075450ADC52D} + Win32Proj + RPC + 10.0.17763.0 + RPC + + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + false + v142 + true + Unicode + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + false + v142 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(SolutionDir)$(Configuration)\ + $(IntDir) + + + $(SolutionDir)$(Configuration)\ + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/RPC/RPC-vs2019.vcxproj.filters b/source/native/nf-interpreter/src/CLR/Core/RPC/RPC-vs2019.vcxproj.filters new file mode 100644 index 00000000..b7ad3836 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/RPC/RPC-vs2019.vcxproj.filters @@ -0,0 +1,22 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/RPC/RPC.vcxproj b/source/native/nf-interpreter/src/CLR/Core/RPC/RPC.vcxproj new file mode 100644 index 00000000..16f7a84e --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/RPC/RPC.vcxproj @@ -0,0 +1,158 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + {ED4C887A-EC09-465B-B5D9-075450ADC52D} + Win32Proj + RPC + 10.0.17763.0 + + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\ + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\ + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/RPC/RPC.vcxproj.filters b/source/native/nf-interpreter/src/CLR/Core/RPC/RPC.vcxproj.filters new file mode 100644 index 00000000..b7ad3836 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/RPC/RPC.vcxproj.filters @@ -0,0 +1,22 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/RPC/RPC_stub.cpp b/source/native/nf-interpreter/src/CLR/Core/RPC/RPC_stub.cpp new file mode 100644 index 00000000..e0632f9b --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/RPC/RPC_stub.cpp @@ -0,0 +1,75 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include + +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +__nfweak void CLR_RT_HeapBlock_EndPoint::HandlerMethod_Initialize() +{ +} + +__nfweak void CLR_RT_HeapBlock_EndPoint::HandlerMethod_RecoverFromGC() +{ +} + +__nfweak void CLR_RT_HeapBlock_EndPoint::HandlerMethod_CleanUp() +{ +} + +__nfweak CLR_RT_HeapBlock_EndPoint* CLR_RT_HeapBlock_EndPoint::FindEndPoint( const CLR_RT_HeapBlock_EndPoint::Port& port ) +{ + (void)port; + + return NULL; +} + +__nfweak bool CLR_RT_HeapBlock_EndPoint::Port::Compare( const CLR_RT_HeapBlock_EndPoint::Port& port ) +{ + (void)port; + + return false; +} + +//--// + +__nfweak HRESULT CLR_RT_HeapBlock_EndPoint::CreateInstance( const CLR_RT_HeapBlock_EndPoint::Port& port, CLR_RT_HeapBlock& owner, CLR_RT_HeapBlock& epRef ) +{ + (void)port; + (void)owner; + (void)epRef; + + NANOCLR_FEATURE_STUB_RETURN(); +} + +__nfweak HRESULT CLR_RT_HeapBlock_EndPoint::ExtractInstance( CLR_RT_HeapBlock& ref, CLR_RT_HeapBlock_EndPoint*& endPoint ) +{ + (void)ref; + (void)endPoint; + + NANOCLR_FEATURE_STUB_RETURN(); +} + +__nfweak bool CLR_RT_HeapBlock_EndPoint::ReleaseWhenDeadEx() +{ + return true; +} + +//--// + +__nfweak void CLR_RT_HeapBlock_EndPoint::RecoverFromGC() +{ +} + +//--// + +__nfweak CLR_RT_HeapBlock_EndPoint::Message* CLR_RT_HeapBlock_EndPoint::FindMessage( CLR_UINT32 cmd, const CLR_UINT32* seq ) +{ + (void)cmd; + (void)seq; + + return NULL; +} diff --git a/source/native/nf-interpreter/src/CLR/Core/RPC/RPC_stub.vcxproj b/source/native/nf-interpreter/src/CLR/Core/RPC/RPC_stub.vcxproj new file mode 100644 index 00000000..6fd7ea13 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/RPC/RPC_stub.vcxproj @@ -0,0 +1,158 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + {D0B2ADFE-3347-4D73-9364-9C36935D12F8} + Win32Proj + RPC_stub + 10.0.17763.0 + + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/RPC/RPC_stub.vcxproj.filters b/source/native/nf-interpreter/src/CLR/Core/RPC/RPC_stub.vcxproj.filters new file mode 100644 index 00000000..a1ac8e56 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/RPC/RPC_stub.vcxproj.filters @@ -0,0 +1,22 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/Random.cpp b/source/native/nf-interpreter/src/CLR/Core/Random.cpp new file mode 100644 index 00000000..bb1dd1ec --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Random.cpp @@ -0,0 +1,51 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +__nfweak void CLR_RT_Random::Initialize() +{ + CLR_INT64 st = HAL_Time_CurrentTime(); + + srand((unsigned int)st); +} + +__nfweak void CLR_RT_Random::Initialize( int seed ) +{ + srand(seed); +} + +__nfweak uint32_t CLR_RT_Random::Next() +{ + return rand(); +} + +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + +__nfweak double CLR_RT_Random::NextDouble() +{ + // Next() will return value between 0 - 0x7FFFFFFF (inclusive) + return ((double)rand()) / ((double)0x7FFFFFFF); +} +#else + +__nfweak CLR_INT64 CLR_RT_Random::NextDouble() +{ + // Next() will return value between 0 - 0x7FFFFFFF (inclusive) + + return ((CLR_INT64 )rand() ) / ((CLR_INT64)0x7FFFFFFF >> CLR_RT_HeapBlock::HB_DoubleShift); +} + +#endif + +__nfweak void CLR_RT_Random::NextBytes( unsigned char* buffer, unsigned int count ) +{ + unsigned int i; + + for(i = 0; i < count; i++) + { + buffer[i] = (unsigned char)rand(); + } +} diff --git a/source/native/nf-interpreter/src/CLR/Core/Serialization/BinaryFormatter.cpp b/source/native/nf-interpreter/src/CLR/Core/Serialization/BinaryFormatter.cpp new file mode 100644 index 00000000..4e52dbed --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Serialization/BinaryFormatter.cpp @@ -0,0 +1,2016 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include +#include + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +//this method simply informs if Serialization is enabled +//the stub version of this method returns False +bool CLR_RT_BinaryFormatter::SerializationEnabled() +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + return true; +} + +CLR_RT_HeapBlock* CLR_RT_BinaryFormatter::TypeHandler::FixDereference( CLR_RT_HeapBlock* v ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + return (v && v->DataType() == DATATYPE_OBJECT) ? v->Dereference() : v; +} + +CLR_RT_HeapBlock* CLR_RT_BinaryFormatter::TypeHandler::FixNull( CLR_RT_HeapBlock* v ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + if(v && v->DataType() == DATATYPE_OBJECT && v->Dereference() == NULL) return NULL; + + return v; +} + +//--// + +HRESULT CLR_RT_BinaryFormatter::TypeHandler::TypeHandler_Initialize( CLR_RT_BinaryFormatter* bf, SerializationHintsAttribute* hints, CLR_RT_TypeDescriptor* expected ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + NANOCLR_CLEAR(*this); + + m_bf = bf; + + if(hints) + { + m_hints = *hints; + } + + if(expected) + { + m_typeExpected = &m_typeExpected_tmp; + + *m_typeExpected = *expected; + } + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT CLR_RT_BinaryFormatter::TypeHandler::SetValue( CLR_RT_HeapBlock* v ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + m_value = NULL; + m_type = NULL; + + v = TypeHandler::FixNull( v ); + if(v) + { + m_value = &m_value_tmp; + m_type = &m_type_tmp; + + m_value->Assign( *v ); + + NANOCLR_CHECK_HRESULT(m_type->InitializeFromObject( *v )); + +#if defined(NANOCLR_APPDOMAINS) + if(m_bf->m_flags & CLR_RT_BinaryFormatter::c_Flags_Marshal) + { + //MarshalByRefObjects are special for the AppDomain marshaler, and need to get marshaled regardless of whether or not they + //are serializable + + if((m_type->m_handlerCls.CrossReference().m_flags & CLR_RT_TypeDef_CrossReference::TD_CR_IsMarshalByRefObject) || + m_value->IsTransparentProxy()) + { + m_fIsMarshalByRefObject = true; + } + } + +#endif + + if((m_type->m_handlerCls.m_target->flags & CLR_RECORD_TYPEDEF::TD_Serializable) == 0) + { +#if defined(NANOCLR_APPDOMAINS) + + if(m_fIsMarshalByRefObject) NANOCLR_SET_AND_LEAVE(S_OK); + + //For marshaling, we want to throw an exception if we can't correctly marshal an object across AD boundaries + //In fact, this should probably be turned on for all serialization, but I don't know what other implications that + //would have + + if(m_bf->m_flags & CLR_RT_BinaryFormatter::c_Flags_Marshal) + { + NANOCLR_SET_AND_LEAVE(CLR_E_APPDOMAIN_MARSHAL_EXCEPTION); + } +#endif + m_value = NULL; + m_type = NULL; + } + } + + NANOCLR_NOCLEANUP(); +} + +//--// + +int CLR_RT_BinaryFormatter::TypeHandler::SignatureRequirements() +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + int res = c_Signature_Header | c_Signature_Type | c_Signature_Length; + CLR_RT_TypeDescriptor* td; + CLR_RT_TypeDescriptor sub; + + if(m_hints.m_arraySize != 0) + { + res &= ~c_Signature_Length; + } + + m_typeForced = NULL; + + if(m_typeExpected != NULL) + { + switch(m_typeExpected->m_flags) + { + case CLR_RT_DataTypeLookup::c_Primitive: + case CLR_RT_DataTypeLookup::c_Enum : + case CLR_RT_DataTypeLookup::c_ValueType: + res = 0; + break; + + default: + if(m_hints.m_flags & SF_FixedType) + { + res &= ~c_Signature_Type; + break; + } + + if(m_typeExpected->m_flags & CLR_RT_DataTypeLookup::c_Array) + { + sub.InitializeFromType( m_typeExpected->m_reflex.m_data.m_type ); + + td = ⊂ + } + else + { + td = m_typeExpected; + } + + if(td->m_handlerCls.m_target->flags & CLR_RECORD_TYPEDEF::TD_Sealed) + { + res &= ~c_Signature_Type; + break; + } + } + } + + if((res & c_Signature_Type) == 0) + { + m_typeForced = &m_typeForced_tmp; + *m_typeForced = *m_typeExpected; + + if(m_hints.m_flags & SF_PointerNeverNull) + { + res &= ~c_Signature_Header; + } + } + + return res; +} + +bool CLR_RT_BinaryFormatter::TypeHandler::CompareTypes( CLR_RT_TypeDescriptor* left, CLR_RT_TypeDescriptor* right ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + if(!left && !right) return true; + if(!left || !right) return false; + + return memcmp( left, right, sizeof(*left) ) == 0; +} + +CLR_DataType CLR_RT_BinaryFormatter::TypeHandler::GetDataType( CLR_RT_TypeDescriptor* type ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + return (CLR_DataType)type->m_handlerCls.m_target->dataType; +} + +CLR_UINT32 CLR_RT_BinaryFormatter::TypeHandler::GetSizeOfType( CLR_RT_TypeDescriptor* type ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + return c_CLR_RT_DataTypeLookup[ type->GetDataType() ].m_sizeInBits; +} + +bool CLR_RT_BinaryFormatter::TypeHandler::GetSignOfType( CLR_RT_TypeDescriptor* type ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + return (c_CLR_RT_DataTypeLookup[ type->GetDataType() ].m_flags & CLR_RT_DataTypeLookup::c_Signed) != 0; +} + +//--// + +HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitSignature( int& res ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + CLR_UINT32 idx; + int mask = SignatureRequirements(); + + if((mask & c_Signature_Type) == 0) + { + if(m_type && CompareTypes( m_type, m_typeForced ) == false) + { + while(true) + { + if(m_typeForced->m_flags == CLR_RT_DataTypeLookup::c_Enum) + { + break; + } + + if(m_typeForced->m_handlerCls.IsATypeHandler() && + m_type ->m_handlerCls.IsATypeHandler() ) + { + break; + } + + NANOCLR_SET_AND_LEAVE(CLR_E_SERIALIZATION_VIOLATION); + } + } + } + + if(m_value == NULL) + { + if(mask == 0) + { + // + // Special case for null strings (strings don't emit an hash): send a string of length -1. + // + if(m_typeExpected->GetDataType() == DATATYPE_STRING) + { + + NANOCLR_CHECK_HRESULT(m_bf->WriteCompressedUnsigned( 0xFFFFFFFF )); + + res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + } + + NANOCLR_SET_AND_LEAVE(CLR_E_SERIALIZATION_VIOLATION); + } + + + NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L1_Null, TE_L1 )); + + res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + } + + //--// + +#if defined(NANOCLR_APPDOMAINS) + if(m_fIsMarshalByRefObject) + { + CLR_RT_HeapBlock* valPtr = m_value->Dereference(); + + NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L1_Other, TE_L1 )); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L2_Other, TE_L2 )); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L3_MBRO , TE_L3 )); + + { + /* + The bit stream contains pointers to the MBRO and its AppDomain. Only the header is used, and no + duplicate detection is necessary -- all proxies pointing at the same object are equal. + which will get marshaled into either a proxy or MBRO, depending on the destination AppDomain. + Live pointers are stored, but this is ok since it is for marshaling only. The objects cannot + can collected during a GC due to the live object that is being marshaled. + */ + + _ASSERTE(CLR_EE_DBG_IS(NoCompaction)); + + CLR_RT_HeapBlock* ptr; + CLR_RT_AppDomain* appDomain; + + if(valPtr->DataType() == DATATYPE_TRANSPARENT_PROXY) + { + ptr = valPtr->TransparentProxyDereference(); + appDomain = valPtr->TransparentProxyAppDomain (); + } + else + { + ptr = valPtr; + appDomain = g_CLR_RT_ExecutionEngine.GetCurrentAppDomain(); + } + + NANOCLR_CHECK_HRESULT(m_bf->WriteBits( (CLR_UINT32)(size_t)ptr, 32)); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits( (CLR_UINT32)(size_t)appDomain, 32)); + } + + res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + } +#endif + + idx = m_bf->SearchDuplicate( m_value ); + if(idx != (CLR_UINT32)-1) + { + // + // No duplicates allowed for fixed-type objects. + // + if((mask & c_Signature_Header) == 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_SERIALIZATION_VIOLATION); + } + + NANOCLR_CHECK_HRESULT(m_bf->WriteBits ( TE_L1_Duplicate, TE_L1 )); + NANOCLR_CHECK_HRESULT(m_bf->WriteCompressedUnsigned( idx )); + + res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + } + + //--// + + NANOCLR_CHECK_HRESULT(EmitSignature_Inner( mask, m_type, m_value )); + + res = c_Action_ObjectData; NANOCLR_SET_AND_LEAVE(S_OK); + + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitSignature_Inner( int mask, CLR_RT_TypeDescriptor* type, CLR_RT_HeapBlock* value ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + // Unbox reflection types + if(value && value->DataType() == DATATYPE_OBJECT) + { + CLR_RT_HeapBlock* pObj = value->Dereference(); + + if(pObj && pObj->DataType() == DATATYPE_REFLECTION) + { + value = pObj; + } + } + + if(value && value->DataType() == DATATYPE_REFLECTION) + { + switch(value->ReflectionDataConst().m_kind) + { + case REFLECTION_TYPE: + case REFLECTION_TYPE_DELAYED: + if((mask & c_Signature_Header) != 0) + { + NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L1_Other, TE_L1 )); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L2_Other, TE_L2 )); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L3_Type , TE_L3 )); + } + break; + +#if defined(NANOCLR_APPDOMAINS) + case REFLECTION_ASSEMBLY: + case REFLECTION_CONSTRUCTOR: + case REFLECTION_METHOD: + case REFLECTION_FIELD: + if((m_bf->m_flags & CLR_RT_BinaryFormatter::c_Flags_Marshal) == 0) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + if((mask & c_Signature_Header) != 0) + { + NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L1_Other , TE_L1 )); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L2_Other , TE_L2 )); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L3_Reflection, TE_L3 )); + } + break; +#endif + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + } + else if(value && (type->m_flags & (CLR_RT_DataTypeLookup::c_Array | CLR_RT_DataTypeLookup::c_ArrayList))) + { + CLR_RT_HeapBlock_Array* array; + int sizeReal = -1; + + if(type->m_flags & CLR_RT_DataTypeLookup::c_Array) + { + + if((mask & c_Signature_Header) != 0) + { + NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L1_Other, TE_L1 )); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L2_Array, TE_L2 )); + } + + if((mask & c_Signature_Type) != 0) + { + NANOCLR_CHECK_HRESULT(m_bf->WriteBits( (CLR_UINT32)type->m_reflex.m_levels, TE_ArrayDepth )); + + CLR_RT_TypeDescriptor typeSub; typeSub.InitializeFromType( type->m_reflex.m_data.m_type ); + + NANOCLR_CHECK_HRESULT(EmitSignature_Inner( c_Signature_Header | c_Signature_Type, &typeSub, NULL )); + } + + + sizeReal = value->DereferenceArray()->m_numOfElements; + } + else + { + int capacity; + + if((mask & c_Signature_Header) != 0) + { + NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L1_Other , TE_L1 )); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L2_ArrayList, TE_L2 )); + } + + NANOCLR_CHECK_HRESULT(CLR_RT_ArrayListHelper::ExtractArrayFromArrayList( *value, array, sizeReal, capacity )); + } + + if((mask & c_Signature_Length) != 0) + { + int bitsMax = m_hints.m_bitPacked; + + if(bitsMax != 0) + { + if(sizeReal >= (1 << bitsMax)) + { + NANOCLR_SET_AND_LEAVE(CLR_E_SERIALIZATION_VIOLATION); + } + + NANOCLR_SET_AND_LEAVE(m_bf->WriteBits( (CLR_UINT32)sizeReal, bitsMax )); + } + else + { + NANOCLR_SET_AND_LEAVE(m_bf->WriteCompressedUnsigned( (CLR_UINT32)sizeReal )); + } + } + else + { + int sizeExpected = m_hints.m_arraySize; + + if(sizeExpected > 0 && sizeExpected != sizeReal) + { + NANOCLR_SET_AND_LEAVE(CLR_E_SERIALIZATION_VIOLATION); + } + } + } + else if(type->m_flags == CLR_RT_DataTypeLookup::c_Primitive || + type->m_flags == CLR_RT_DataTypeLookup::c_Enum ) + { + if((mask & c_Signature_Header) != 0) + { + NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L1_Other , TE_L1 )); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L2_Primitive, TE_L2 )); + } + + if((mask & c_Signature_Type) != 0) + { + NANOCLR_SET_AND_LEAVE(m_bf->WriteBits( CLR_RT_TypeSystem::MapDataTypeToElementType( type->GetDataType() ), TE_ElementType )); + } + } + else + { + if((mask & c_Signature_Header) != 0) + { + NANOCLR_CHECK_HRESULT(m_bf->WriteBits( TE_L1_Reference, TE_L1 )); + } + + if((mask & c_Signature_Type) != 0) + { + NANOCLR_SET_AND_LEAVE(m_bf->WriteType( type->m_handlerCls.CrossReference().m_hash )); + } + } + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT CLR_RT_BinaryFormatter::TypeHandler::ReadSignature( int& res ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + int mask = SignatureRequirements(); + + m_value = NULL; + m_type = NULL; + + if(m_typeForced) + { + m_type = &m_type_tmp; + + *m_type = *m_typeForced; + } + + if((mask & c_Signature_Header) != 0) + { + CLR_UINT32 levelOne; + CLR_UINT32 levelTwo; + CLR_UINT32 levelThree; + + + NANOCLR_CHECK_HRESULT(m_bf->ReadBits( levelOne, TE_L1 )); + + if(levelOne == TE_L1_Null) + { + if(m_hints.m_flags & SF_PointerNeverNull) + { + NANOCLR_SET_AND_LEAVE(CLR_E_SERIALIZATION_VIOLATION); + } + + res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + } + + if(levelOne == TE_L1_Duplicate) + { + CLR_RT_HeapBlock* dup; + CLR_UINT32 idx; + + NANOCLR_CHECK_HRESULT(m_bf->ReadCompressedUnsigned( idx )); + + dup = m_bf->GetDuplicate( idx ); + if(dup == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_SERIALIZATION_VIOLATION); + } + + m_value = &m_value_tmp; + m_value->SetObjectReference( dup ); + + m_type = &m_type_tmp; + NANOCLR_CHECK_HRESULT(m_type->InitializeFromObject( *m_value )); + + res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + } + + if(levelOne == TE_L1_Reference) + { + if((mask & c_Signature_Type) != 0) + { + CLR_RT_ReflectionDef_Index idx; + + NANOCLR_CHECK_HRESULT(m_bf->ReadType( idx )); + + m_type = &m_type_tmp; + NANOCLR_CHECK_HRESULT(m_type->InitializeFromReflection( idx )); + } + } + else + { + NANOCLR_CHECK_HRESULT(m_bf->ReadBits( levelTwo, TE_L2 )); + if(levelTwo == TE_L2_Primitive) + { + if((mask & c_Signature_Type) != 0) + { + CLR_UINT32 et; + + NANOCLR_CHECK_HRESULT(m_bf->ReadBits( et, TE_ElementType )); + + m_type = &m_type_tmp; + NANOCLR_CHECK_HRESULT(m_type->InitializeFromDataType( CLR_RT_TypeSystem::MapElementTypeToDataType( et ) )); + } + } + else if(levelTwo == TE_L2_Array) + { + if((mask & c_Signature_Type) != 0) + { + CLR_UINT32 depth; + + NANOCLR_CHECK_HRESULT(m_bf->ReadBits( depth, TE_ArrayDepth )); + + NANOCLR_CHECK_HRESULT(m_bf->ReadBits( levelOne, TE_L1 )); + + if(levelOne == TE_L1_Reference) + { + CLR_RT_ReflectionDef_Index idx; + + NANOCLR_CHECK_HRESULT(m_bf->ReadType( idx )); + + m_type = &m_type_tmp; + NANOCLR_CHECK_HRESULT(m_type->InitializeFromReflection( idx )); + } + else if(levelOne == TE_L1_Other) + { + NANOCLR_CHECK_HRESULT(m_bf->ReadBits( levelTwo, TE_L2 )); + + if(levelTwo == TE_L2_Primitive) + { + CLR_UINT32 et; + + NANOCLR_CHECK_HRESULT(m_bf->ReadBits( et, TE_ElementType )); + + m_type = &m_type_tmp; + NANOCLR_CHECK_HRESULT(m_type->InitializeFromDataType( CLR_RT_TypeSystem::MapElementTypeToDataType( et ) )); + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_SERIALIZATION_BADSTREAM); + } + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_SERIALIZATION_BADSTREAM); + } + + m_type->m_reflex.m_levels = depth; + m_type->ConvertToArray(); + } + } + else if(levelTwo == TE_L2_ArrayList) + { + if((mask & c_Signature_Type) != 0) + { + m_type = &m_type_tmp; + NANOCLR_CHECK_HRESULT(m_type->InitializeFromType( g_CLR_RT_WellKnownTypes.m_ArrayList )); + } + } + else if(levelTwo == TE_L2_Other) + { + NANOCLR_CHECK_HRESULT(m_bf->ReadBits( levelThree, TE_L3 )); + if(levelThree == TE_L3_Type) + { + m_type = &m_type_tmp; + NANOCLR_CHECK_HRESULT(m_type->InitializeFromType( g_CLR_RT_WellKnownTypes.m_Type )); + } +#if defined(NANOCLR_APPDOMAINS) + else if (levelThree == TE_L3_Reflection) + { + CLR_RT_ReflectionDef_Index value; + CLR_UINT64 data; + + _ASSERTE(m_bf->m_flags & CLR_RT_BinaryFormatter::c_Flags_Marshal); + + NANOCLR_CHECK_HRESULT(m_bf->ReadBits( data, 64 )); + + value.SetRawData( data ); + + m_value = &m_value_tmp; + NANOCLR_CHECK_HRESULT(m_value->SetReflection( value )); + + res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + } + else if (levelThree == TE_L3_MBRO) + { + CLR_UINT32 uintPtr; + CLR_UINT32 uintAppDomain; + CLR_RT_HeapBlock* ptr; + CLR_RT_AppDomain* appDomain; + + NANOCLR_CHECK_HRESULT(m_bf->ReadBits( uintPtr , 32 )); + NANOCLR_CHECK_HRESULT(m_bf->ReadBits( uintAppDomain, 32 )); + + _ASSERTE(CLR_EE_DBG_IS( NoCompaction )); + + ptr = (CLR_RT_HeapBlock*)(size_t)uintPtr; + appDomain = (CLR_RT_AppDomain*)(size_t)uintAppDomain; + + m_type = &m_type_tmp; + NANOCLR_CHECK_HRESULT(m_type->InitializeFromObject( *ptr )); + + m_value = &m_value_tmp; + if(appDomain != g_CLR_RT_ExecutionEngine.GetCurrentAppDomain()) + { + //The MarshalByRefObject lives in a separate AppDomain. + //We need to allocate a TRANSPARENT_PROXY object on the stack + + CLR_RT_HeapBlock* proxy = g_CLR_RT_ExecutionEngine.ExtractHeapBlocksForObjects( DATATYPE_TRANSPARENT_PROXY, 0, 1 ); CHECK_ALLOCATION(proxy); + + proxy->SetTransparentProxyReference( appDomain, ptr ); + + ptr = proxy; + } + + //Set the value reference to either the MBRO, or the proxy + m_value->SetObjectReference( ptr ); + + res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + } +#endif + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_SERIALIZATION_BADSTREAM); + } + } + } + } + + if(m_type->m_flags & (CLR_RT_DataTypeLookup::c_Array | CLR_RT_DataTypeLookup::c_ArrayList)) + { + CLR_UINT32 len; + + if(mask & c_Signature_Length) + { + int bitsMax = m_hints.m_bitPacked; + + if(bitsMax != 0) + { + NANOCLR_CHECK_HRESULT(m_bf->ReadBits( len, bitsMax )); + } + else + { + NANOCLR_CHECK_HRESULT(m_bf->ReadCompressedUnsigned( len )); + } + } + else + { + CLR_RT_TypeDescriptor sub; + + if(m_type->m_reflex.m_levels != 1) + { + // + // Only simple arrays can have variable size. + // + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + sub.InitializeFromType( m_type->m_reflex.m_data.m_type ); + + len = m_hints.m_arraySize; + + if(len == (CLR_UINT32)-1) + { + len = m_bf->BitsAvailable(); + + switch(TypeHandler::GetSizeOfType( &sub )) + { + case 1: break; + case 8: len /= 8; break; + case 16: len /= 16; break; + case 32: len /= 32; break; + case 64: len /= 64; break; + default: + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + } + } + + if(m_type->m_flags & CLR_RT_DataTypeLookup::c_ArrayList) + { + CLR_RT_HeapBlock_Array* array; + + m_value = &m_value_tmp; + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewArrayList( *m_value, len, array )); + } + else + { + m_value = &m_value_tmp; + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( *m_value, len, m_type->m_reflex )); + } + } + else + { + m_value = &m_value_tmp; + + if(m_type->m_handlerCls.IsATypeHandler()) + { + CLR_RT_ReflectionDef_Index idx; + + NANOCLR_CHECK_HRESULT(m_bf->ReadType( idx )); + + NANOCLR_CHECK_HRESULT(m_value->SetReflection( idx )); + + res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + } + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObject( *m_value, m_type->m_handlerCls )); + } + + res = c_Action_ObjectData; NANOCLR_SET_AND_LEAVE(S_OK); + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitValue( int& res ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* value = m_value->FixBoxingReference(); + CLR_UINT64 val; + CLR_UINT32 bits; + bool fSigned; + + // unbox reflection types + if(value->DataType() == DATATYPE_OBJECT) + { + CLR_RT_HeapBlock* obj = value->Dereference(); + + if(obj && obj->DataType() == DATATYPE_REFLECTION) + { + value = obj; + } + } + + if(value->DataType() == DATATYPE_REFLECTION) + { + switch(value->ReflectionDataConst().m_kind) + { + case REFLECTION_TYPE: + case REFLECTION_TYPE_DELAYED: + NANOCLR_CHECK_HRESULT(m_bf->WriteType( value->ReflectionDataConst() )); + break; +#if defined(NANOCLR_APPDOMAINS) + case REFLECTION_ASSEMBLY: + case REFLECTION_CONSTRUCTOR: + case REFLECTION_METHOD: + case REFLECTION_FIELD: + { + CLR_UINT64 data; + + _ASSERTE(m_bf->m_flags & CLR_RT_BinaryFormatter::c_Flags_Marshal); + + data = value->ReflectionDataConst().GetRawData(); + + NANOCLR_CHECK_HRESULT(m_bf->WriteBits( data, 64 )); + } + break; +#endif + } + + res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + } + + if(m_type->m_handlerCls.m_data == g_CLR_RT_WellKnownTypes.m_DateTime.m_data) + { + CLR_INT64* pVal = Library_corlib_native_System_DateTime::GetValuePtr( *value ); FAULT_ON_NULL(pVal); + + val = *(CLR_UINT64*)pVal; + bits = 64; + fSigned = false; + } + else if(m_type->m_handlerCls.m_data == g_CLR_RT_WellKnownTypes.m_TimeSpan.m_data) + { + CLR_INT64* pVal = Library_corlib_native_System_TimeSpan::GetValuePtr( *value ); FAULT_ON_NULL(pVal); + + val = *(CLR_UINT64*)pVal; + bits = 64; + fSigned = true; + } + else if(m_type->m_flags == CLR_RT_DataTypeLookup::c_Primitive || + m_type->m_flags == CLR_RT_DataTypeLookup::c_Enum ) + { + bits = TypeHandler::GetSizeOfType( m_type ); + if(bits == CLR_RT_DataTypeLookup::c_VariableSize) + { + const char* szText = value->RecoverString(); + CLR_UINT32 len = szText ? (CLR_UINT32)hal_strlen_s( szText ) : 0xFFFFFFFF; + + NANOCLR_CHECK_HRESULT(m_bf->WriteCompressedUnsigned( len )); + + if(len != (CLR_UINT32)-1) + { + NANOCLR_CHECK_HRESULT(m_bf->WriteArray( (CLR_UINT8*)szText, len )); + } + + res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + } + else if(bits == CLR_RT_DataTypeLookup::c_NA) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + CLR_RT_HeapBlock* v = FixDereference( value ); FAULT_ON_NULL(v); + + val = v->NumericByRefConst().u8; + + fSigned = TypeHandler::GetSignOfType( m_type ); + } + +#if defined(NANOCLR_APPDOMAINS) + else if(m_fIsMarshalByRefObject) + { + CLR_RT_HeapBlock* valPtr = value->Dereference(); + CLR_RT_AppDomain* appDomain = g_CLR_RT_ExecutionEngine.GetCurrentAppDomain(); + + if(valPtr->DataType() == DATATYPE_TRANSPARENT_PROXY) + { + appDomain = valPtr->TransparentProxyAppDomain(); + valPtr = valPtr->TransparentProxyDereference(); + } + + NANOCLR_CHECK_HRESULT(m_bf->WriteBits( (CLR_UINT32)(size_t)valPtr , 32 )); + NANOCLR_CHECK_HRESULT(m_bf->WriteBits( (CLR_UINT32)(size_t)appDomain, 32 )); + + NANOCLR_SET_AND_LEAVE(S_OK); + } +#endif + + else + { + NANOCLR_SET_AND_LEAVE(TrackObject( res )); + } + + { + CLR_UINT32 shift = 64 - bits; + + if(shift) + { + val <<= shift; + + if(fSigned) val = (CLR_UINT64)((CLR_INT64 )val >> shift); + else val = (CLR_UINT64)((CLR_UINT64)val >> shift); + } + } + + if(m_hints.m_bitPacked) bits = m_hints.m_bitPacked; + + val -= m_hints.m_rangeBias; + + if(fSigned) + { + CLR_INT64 valS = (CLR_INT64)val; + + if(m_hints.m_scale != 0) valS /= (CLR_INT64)m_hints.m_scale; + + if(bits != 64) + { + CLR_INT64 maxVal = (LONGLONGCONSTANT(1) << (bits-1)) - 1; + + if(valS < (-maxVal-1) || valS > maxVal) + { + NANOCLR_SET_AND_LEAVE(CLR_E_SERIALIZATION_VIOLATION); + } + } + + val = (CLR_UINT64)valS; + } + else + { + CLR_UINT64 valU = (CLR_UINT64)val; + + if(m_hints.m_scale != 0) valU /= (CLR_UINT64)m_hints.m_scale; + + if(bits != 64) + { + CLR_UINT64 maxVal = (ULONGLONGCONSTANT(1) << bits) - 1; + + if(valU > maxVal) + { + NANOCLR_SET_AND_LEAVE(CLR_E_SERIALIZATION_VIOLATION); + } + } + + val = (CLR_UINT64)valU; + } + + NANOCLR_CHECK_HRESULT(m_bf->WriteBits( val, bits )); + + res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_BinaryFormatter::TypeHandler::ReadValue( int& res ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + CLR_UINT64* dst; + CLR_UINT64 val; + CLR_UINT32 bits; + bool fSigned; + + if(m_type->m_handlerCls.m_data == g_CLR_RT_WellKnownTypes.m_DateTime.m_data) + { + CLR_INT64* pVal = Library_corlib_native_System_DateTime::GetValuePtr( *m_value ); FAULT_ON_NULL(pVal); + + dst = (CLR_UINT64*)pVal; + bits = 64; + fSigned = false; + } + else if(m_type->m_handlerCls.m_data == g_CLR_RT_WellKnownTypes.m_TimeSpan.m_data) + { + CLR_INT64* pVal = Library_corlib_native_System_TimeSpan::GetValuePtr( *m_value ); FAULT_ON_NULL(pVal); + + dst = (CLR_UINT64*)pVal; + bits = 64; + fSigned = true; + } + else if(m_type->m_flags == CLR_RT_DataTypeLookup::c_Primitive || + m_type->m_flags == CLR_RT_DataTypeLookup::c_Enum ) + { + bits = TypeHandler::GetSizeOfType( m_type ); + + if(bits == CLR_RT_DataTypeLookup::c_VariableSize) + { + CLR_UINT32 len; + + NANOCLR_CHECK_HRESULT(m_bf->ReadCompressedUnsigned( len )); + + if(len == 0xFFFFFFFF) + { + m_value->SetObjectReference( NULL ); + } + else + { + CLR_RT_HeapBlock_String* str = CLR_RT_HeapBlock_String::CreateInstance( *m_value, len ); CHECK_ALLOCATION(str); + char* dst = (char*)str->StringText(); + + NANOCLR_CHECK_HRESULT(m_bf->ReadArray( (CLR_UINT8*)dst, len )); + dst[ len ] = 0; + } + + res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + } + else if(bits == CLR_RT_DataTypeLookup::c_NA) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + else + { + m_value->SetDataId( CLR_RT_HEAPBLOCK_RAW_ID(m_type->GetDataType(),0,1) ); + m_value->ClearData( ); + + dst = (CLR_UINT64*)&m_value->NumericByRef().u8; + + fSigned = TypeHandler::GetSignOfType( m_type ); + } + } + else + { + NANOCLR_SET_AND_LEAVE(TrackObject( res )); + } + + if(m_hints.m_bitPacked) bits = m_hints.m_bitPacked; + + NANOCLR_CHECK_HRESULT(m_bf->ReadBits( val, bits )); + + if(bits != 64) + { + int revBits = 64 - bits; + + val <<= revBits; + + if(fSigned) val = (CLR_UINT64)((CLR_INT64)val >> revBits); + else val = ( val >> revBits); + } + + if(m_hints.m_scale != 0) + { + val *= m_hints.m_scale; + } + + *dst = val + m_hints.m_rangeBias; + + res = c_Action_None; NANOCLR_SET_AND_LEAVE(S_OK); + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT CLR_RT_BinaryFormatter::TypeHandler::TrackObject( int& res ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + if(m_type->m_flags & (CLR_RT_DataTypeLookup::c_Array | CLR_RT_DataTypeLookup::c_ArrayList)) + { + res = c_Action_ObjectElements; + } + else + { + res = c_Action_ObjectFields; + + if(m_typeExpected && m_typeExpected->m_flags == CLR_RT_DataTypeLookup::c_ValueType) + { + NANOCLR_SET_AND_LEAVE(S_OK); + } + } + + NANOCLR_SET_AND_LEAVE(m_bf->TrackDuplicate( m_value )); + + NANOCLR_NOCLEANUP(); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +HRESULT CLR_RT_BinaryFormatter::State::CreateInstance( CLR_RT_BinaryFormatter* parent, SerializationHintsAttribute* hints, CLR_RT_HeapBlock* type ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Instance inst; + CLR_RT_TypeDescriptor desc; + CLR_RT_TypeDescriptor* pDesc; + SerializationHintsAttribute hintsTmp; + + if(type && CLR_RT_ReflectionDef_Index::Convert( *type, inst, NULL )) + { + NANOCLR_CHECK_HRESULT(desc.InitializeFromType( inst )); + + pDesc = &desc; + + if(hints == NULL) + { + hints = &hintsTmp; + + NANOCLR_CLEAR(*hints); + + hints->m_flags = (SerializationFlags)(SF_PointerNeverNull | SF_FixedType); + } + } + else + { + pDesc = NULL; + } + + NANOCLR_SET_AND_LEAVE(CreateInstance( parent, hints, pDesc )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_BinaryFormatter::State::CreateInstance( CLR_RT_BinaryFormatter* parent, SerializationHintsAttribute* hints, CLR_RT_TypeDescriptor* type ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + State* ptr = EVENTCACHE_EXTRACT_NODE_INITTOZERO(g_CLR_RT_EventCache,State,DATATYPE_SERIALIZER_STATE); + + CHECK_ALLOCATION(ptr); + + parent->m_states.LinkAtBack( ptr ); + + ptr->m_parent = parent; + ptr->m_value_NeedProcessing = true; + ptr->m_value.TypeHandler_Initialize( parent, hints, type ); + + NANOCLR_NOCLEANUP(); +} + +void CLR_RT_BinaryFormatter::State::DestroyInstance() +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + g_CLR_RT_EventCache.Append_Node( this ); +} + +//--// + +HRESULT CLR_RT_BinaryFormatter::State::FindHints( SerializationHintsAttribute& hints, const CLR_RT_TypeDef_Instance& cls ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + NANOCLR_CLEAR(hints); + + if(cls.m_target->flags & CLR_RECORD_TYPEDEF::TD_HasAttributes) + { + CLR_RT_TypeDef_Instance inst; inst.InitializeFromIndex( g_CLR_RT_WellKnownTypes.m_SerializationHintsAttribute ); + CLR_RT_AttributeEnumerator en; en.Initialize( cls ); + + if(en.MatchNext( &inst, NULL )) + { + CLR_RT_AttributeParser parser; + + NANOCLR_CHECK_HRESULT(parser.Initialize( en )); + + while(true) + { + CLR_RT_AttributeParser::Value* val; + + NANOCLR_CHECK_HRESULT(parser.Next( val )); + + if(val == NULL) break; + } + } + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_BinaryFormatter::State::FindHints( SerializationHintsAttribute& hints, const CLR_RT_FieldDef_Instance& fld ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + NANOCLR_CLEAR(hints); + + if(fld.m_target->flags & CLR_RECORD_FIELDDEF::FD_HasAttributes) + { + CLR_RT_TypeDef_Instance inst; inst.InitializeFromIndex( g_CLR_RT_WellKnownTypes.m_SerializationHintsAttribute ); + CLR_RT_AttributeEnumerator en; en.Initialize( fld ); + + if(en.MatchNext( &inst, NULL )) + { + CLR_RT_AttributeParser parser; + + NANOCLR_CHECK_HRESULT(parser.Initialize( en )); + + while(true) + { + CLR_RT_AttributeParser::Value* val; + + NANOCLR_CHECK_HRESULT(parser.Next( val )); + + if(val == NULL) + { + break; + } + else + { + if (!strcmp( val->m_name, "Flags" )) hints.m_flags = (SerializationFlags)val->m_value.NumericByRef().u4; + else if(!strcmp( val->m_name, "ArraySize" )) hints.m_arraySize = val->m_value.NumericByRef().s4; + else if(!strcmp( val->m_name, "BitPacked" )) hints.m_bitPacked = val->m_value.NumericByRef().s4; + else if(!strcmp( val->m_name, "RangeBias" )) hints.m_rangeBias = val->m_value.NumericByRef().s8; + else if(!strcmp( val->m_name, "Scale" )) hints.m_scale = val->m_value.NumericByRef().u8; + } + } + } + } + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT CLR_RT_BinaryFormatter::State::AssignAndFixBoxing( CLR_RT_HeapBlock& dst ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* src = m_value.m_value; + CLR_DataType dt = dst.DataType(); + CLR_DataType dt2 = (dt == DATATYPE_ARRAY_BYREF) ? (CLR_DataType)dst.DereferenceArray()->m_typeOfElement : dt; + + if(c_CLR_RT_DataTypeLookup[ dt2 ].m_flags & CLR_RT_DataTypeLookup::c_OptimizedValueType) + { + if(src && (c_CLR_RT_DataTypeLookup[ src->DataType() ].m_flags & CLR_RT_DataTypeLookup::c_OptimizedValueType) == 0) + { + src = TypeHandler::FixNull( src ); + } + + if(src == NULL || (c_CLR_RT_DataTypeLookup[ src->DataType() ].m_flags & CLR_RT_DataTypeLookup::c_OptimizedValueType) == 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + } + else + { + if(src) + { + bool fBox = false; + + if(c_CLR_RT_DataTypeLookup[ src->DataType() ].m_flags & CLR_RT_DataTypeLookup::c_OptimizedValueType) + { + fBox = true; + } + else if(src->IsAValueType()) + { + if(dt == DATATYPE_ARRAY_BYREF) + { + fBox = (dt2 != DATATYPE_VALUETYPE); + } + else + { + fBox = !dst.IsAValueType(); + } + } + // + // Box reflection types + // + else if(src->DataType() == DATATYPE_REFLECTION) + { + const CLR_RT_ReflectionDef_Index* reflex; + const CLR_RT_TypeDef_Index* cls; + CLR_RT_HeapBlock *pDst = &dst; + + reflex = &(src->ReflectionDataConst()); + + switch(reflex->m_kind) + { + case REFLECTION_ASSEMBLY : cls = &g_CLR_RT_WellKnownTypes.m_Assembly ; break; + case REFLECTION_TYPE : cls = &g_CLR_RT_WellKnownTypes.m_Type ; break; + case REFLECTION_TYPE_DELAYED: cls = &g_CLR_RT_WellKnownTypes.m_Type ; break; + case REFLECTION_CONSTRUCTOR : cls = &g_CLR_RT_WellKnownTypes.m_ConstructorInfo; break; + case REFLECTION_METHOD : cls = &g_CLR_RT_WellKnownTypes.m_MethodInfo ; break; + case REFLECTION_FIELD : cls = &g_CLR_RT_WellKnownTypes.m_FieldInfo ; break; + } + + // + // Dereference array element and create boxed reflection type + // + if(dt == DATATYPE_ARRAY_BYREF) + { + CLR_RT_HeapBlock_Array* array = dst.DereferenceArray(); FAULT_ON_NULL(array); + + pDst = (CLR_RT_HeapBlock*)array->GetElement( dst.ArrayIndex() ); + } + + // + // Create boxed object reference for reflection type + // + g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*pDst, *cls); + + + // + // Set reflection type + // + pDst->Dereference()->SetReflection(*reflex); + + NANOCLR_SET_AND_LEAVE(S_OK); + } + + if(fBox) + { + NANOCLR_CHECK_HRESULT(m_value.m_value->PerformBoxing( m_value.m_type->m_handlerCls )); + } + } + else + { + src = &m_value.m_value_tmp; src->SetObjectReference( NULL ); + } + } + + if(dt == DATATYPE_ARRAY_BYREF) + { + NANOCLR_CHECK_HRESULT(src->StoreToReference( dst, 0 )); + } + else + { + dst.Assign( *src ); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_BinaryFormatter::State::GetValue() +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + State* prev = (State*)Prev(); + if(prev->Prev() == NULL) + { + NANOCLR_SET_AND_LEAVE(m_value.SetValue( &m_parent->m_value )); + } + + if(prev->m_fields_NeedProcessing) + { + NANOCLR_SET_AND_LEAVE(m_value.SetValue( prev->m_fields_Pointer )); + } + + if(prev->m_array_NeedProcessing) + { + CLR_RT_HeapBlock ref; ref.InitializeArrayReferenceDirect( *prev->m_array, prev->m_array_CurrentPos-1 ); + CLR_RT_HeapBlock val; + + NANOCLR_CHECK_HRESULT(val.LoadFromReference( ref )); + + NANOCLR_SET_AND_LEAVE(m_value.SetValue( &val )); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_BinaryFormatter::State::SetValueAndDestroyInstance() +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + if(m_parent->m_fDeserialize) + { + State* prev = (State*)Prev(); + + if(prev->Prev() == NULL) + { + NANOCLR_CHECK_HRESULT(AssignAndFixBoxing( m_parent->m_value )); + } + else + { + if(prev->m_fields_NeedProcessing) + { + NANOCLR_CHECK_HRESULT(AssignAndFixBoxing( *prev->m_fields_Pointer )); + } + + if(prev->m_array_NeedProcessing) + { + CLR_RT_HeapBlock ref; ref.InitializeArrayReferenceDirect( *prev->m_array, prev->m_array_CurrentPos-1 ); + + NANOCLR_CHECK_HRESULT(AssignAndFixBoxing( ref )); + } + } + } + + DestroyInstance(); + + NANOCLR_NOCLEANUP(); +} + +////////////////////////////////////////////////////////////////////////////////////////// + +HRESULT CLR_RT_BinaryFormatter::State::Advance() +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + if(m_value_NeedProcessing) + { + int res; + + m_value_NeedProcessing = false; + + if(m_parent->m_fDeserialize) + { + NANOCLR_CHECK_HRESULT(m_value.ReadSignature( res )); + +#if defined(NANOCLR_APPDOMAINS) + //Make sure that the type being deserialized is loaded in the current appDomain + { + if(m_parent->m_flags & CLR_RT_BinaryFormatter::c_Flags_Marshal) + { + CLR_RT_TypeDef_Index idx; idx.Clear(); + CLR_RT_HeapBlock* value = m_value.m_value; + + if(value && value->DataType() == DATATYPE_REFLECTION) + { + switch(value->ReflectionDataConst().m_kind) + { + case REFLECTION_TYPE: + idx.m_data = value->ReflectionDataConst().m_data.m_type.m_data; + break; + case REFLECTION_TYPE_DELAYED: + //should this be allowed for appdomain+marshaling??? + break; + case REFLECTION_ASSEMBLY: + { + CLR_RT_Assembly_Instance inst; + + if(!inst.InitializeFromIndex( value->ReflectionDataConst().m_data.m_assm )) + { + _ASSERTE(false); + } + + if(!g_CLR_RT_ExecutionEngine.GetCurrentAppDomain()->FindAppDomainAssembly( inst.m_assm )) + { + NANOCLR_SET_AND_LEAVE(CLR_E_APPDOMAIN_MARSHAL_EXCEPTION); + } + } + break; + case REFLECTION_CONSTRUCTOR: + case REFLECTION_METHOD: + { + CLR_RT_MethodDef_Instance inst; + + if(!inst.InitializeFromIndex( value->ReflectionDataConst().m_data.m_method )) + { + _ASSERTE(false); + } + + idx.Set( inst.Assembly(), inst.CrossReference().GetOwner() ); + } + break; + case REFLECTION_FIELD: + { + CLR_RT_FieldDef_Instance inst; + CLR_RT_TypeDescriptor desc; + + if(!inst.InitializeFromIndex( value->ReflectionDataConst().m_data.m_field )) + { + _ASSERTE(false); + } + + NANOCLR_CHECK_HRESULT(desc.InitializeFromFieldDefinition( inst )); + + idx = desc.m_handlerCls; + } + break; + } + } + else if(m_value.m_type) + { + idx = m_value.m_type->m_handlerCls; + } + + if(idx.m_data != 0) + { + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.GetCurrentAppDomain()->VerifyTypeIsLoaded( idx )); + } + } + } +#endif + + } + else + { + NANOCLR_CHECK_HRESULT(GetValue()); + + NANOCLR_CHECK_HRESULT(m_value.EmitSignature( res )); + } + + if(res != TypeHandler::c_Action_None) + { + if(m_parent->m_fDeserialize) + { + NANOCLR_CHECK_HRESULT(m_value.ReadValue( res )); + + } + else + { + NANOCLR_CHECK_HRESULT(m_value.EmitValue( res )); + } + + switch(res) + { + case TypeHandler::c_Action_None: + break; + + case TypeHandler::c_Action_ObjectFields: + { + m_fields_NeedProcessing = true; + m_fields_CurrentClass = m_value.m_type->m_handlerCls; + m_fields_CurrentField = 0; + m_fields_Pointer = NULL; + break; + } + + case TypeHandler::c_Action_ObjectElements: + { + m_array_NeedProcessing = true; + m_array_CurrentPos = 0; + + if(m_value.m_type->m_flags & CLR_RT_DataTypeLookup::c_ArrayList) + { + int capacity; + + NANOCLR_CHECK_HRESULT(CLR_RT_ArrayListHelper::ExtractArrayFromArrayList( *m_value.m_value, m_array, m_array_LastPos, capacity )); + + m_array_ExpectedType = NULL; + } + else + { + m_array = m_value.m_value->DereferenceArray(); + m_array_LastPos = m_array->m_numOfElements; + + m_array_ExpectedType = &m_array_ExpectedType_Tmp; + m_value.m_type->GetElementType( *m_array_ExpectedType ); + } + + break; + } + } + } + } + + if(m_fields_NeedProcessing) + { + NANOCLR_SET_AND_LEAVE(AdvanceToTheNextField()); + } + + if(m_array_NeedProcessing) + { + NANOCLR_SET_AND_LEAVE(AdvanceToTheNextElement()); + } + + NANOCLR_SET_AND_LEAVE(SetValueAndDestroyInstance()); + + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT CLR_RT_BinaryFormatter::State::AdvanceToTheNextField() +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + while(NANOCLR_INDEX_IS_VALID(m_fields_CurrentClass)) + { + if(m_fields_CurrentField < m_fields_CurrentClass.m_target->iFields_Num) + { + int offset = m_fields_CurrentClass.m_target->iFields_First + m_fields_CurrentField++; + CLR_RT_FieldDef_Index idx ; idx.Set( m_fields_CurrentClass.Assembly(), offset ); + CLR_RT_FieldDef_Instance inst; inst.InitializeFromIndex( idx ); + + m_fields_Pointer = m_value.m_value->Dereference() + inst.CrossReference().m_offset; + + if((inst.m_target->flags & CLR_RECORD_FIELDDEF::FD_NotSerialized) == 0) + { + SerializationHintsAttribute hints; + CLR_RT_TypeDescriptor desc; + + if(m_value.m_type->m_flags & CLR_RT_DataTypeLookup::c_Enum) + { + hints = m_value.m_hints; + } + else + { + NANOCLR_CHECK_HRESULT(FindHints( hints, inst )); + } + + NANOCLR_CHECK_HRESULT(desc.InitializeFromFieldDefinition( inst )); + + NANOCLR_SET_AND_LEAVE(State::CreateInstance( m_parent, &hints, &desc )); + } + } + else + { + m_fields_CurrentClass.SwitchToParent(); + m_fields_CurrentField = 0; + } + } + + NANOCLR_SET_AND_LEAVE(SetValueAndDestroyInstance()); + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT CLR_RT_BinaryFormatter::State::AdvanceToTheNextElement() +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + if(m_array_ExpectedType && (c_CLR_RT_DataTypeLookup[ m_array->m_typeOfElement ].m_flags & CLR_RT_DataTypeLookup::c_Numeric)) + { + CLR_UINT8* ptr = m_array->GetFirstElement(); + CLR_UINT32 bits = TypeHandler::GetSizeOfType( m_array_ExpectedType ); + int count = m_array_LastPos; + bool fDeserialize = m_parent->m_fDeserialize; + CLR_UINT32 size; + CLR_UINT64 val; + + size = bits / 8; if(size == 0) size = 1; + + while(count > 0) + { + if(fDeserialize) + { + NANOCLR_CHECK_HRESULT(m_parent->ReadBits( val, bits )); + + memcpy( ptr, &val, size ); + } + else + { + val = 0; memcpy( &val, ptr, size ); + + NANOCLR_CHECK_HRESULT(m_parent->WriteBits( val, bits )); + } + + ptr += size; + + count--; + } + } + else if(m_array_CurrentPos < m_array_LastPos) + { + m_array_CurrentPos++; + + SerializationHintsAttribute* hints; + + if(m_value.m_hints.m_flags & (SF_FixedType | SF_PointerNeverNull)) + { + hints = &m_value.m_hints; + } + else + { + hints = NULL; + } + + NANOCLR_SET_AND_LEAVE(State::CreateInstance( m_parent, hints, m_array_ExpectedType )); + } + + NANOCLR_SET_AND_LEAVE(SetValueAndDestroyInstance()); + + NANOCLR_NOCLEANUP(); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +HRESULT CLR_RT_BinaryFormatter::CreateInstance( CLR_UINT8* buf, int len, CLR_RT_BinaryFormatter*& res ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + CLR_RT_BinaryFormatter* ptr = EVENTCACHE_EXTRACT_NODE(g_CLR_RT_EventCache,CLR_RT_BinaryFormatter,DATATYPE_SERIALIZER_HEAD); + + res = ptr; CHECK_ALLOCATION(ptr); + + ptr->m_stream = NULL; // CLR_RT_HeapBlock_MemoryStream* m_stream; + ptr->m_idx = 0; // CLR_UINT32 m_idx; + ptr->m_lastTypeRead = 0; // CLR_UINT32 m_lastTypeRead; + ptr->m_duplicates.DblLinkedList_Initialize(); // CLR_RT_DblLinkedList m_duplicates; // EVENT HEAP - NO RELOCATION - list of CLR_RT_BinaryFormatter::DuplicateTracker + ptr->m_states .DblLinkedList_Initialize(); // CLR_RT_DblLinkedList m_states; // EVENT HEAP - NO RELOCATION - list of CLR_RT_BinaryFormatter::State + // + ptr->m_fDeserialize = (buf != NULL); // bool m_fDeserialize; + ptr->m_value.SetObjectReference( NULL ); // CLR_RT_HeapBlock m_value; + ptr->m_value_desc.TypeDescriptor_Initialize(); // CLR_RT_TypeDescriptor m_value_desc; + + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_MemoryStream::CreateInstance( ptr->m_stream, buf, len )); + + NANOCLR_NOCLEANUP(); +} + +void CLR_RT_BinaryFormatter::DestroyInstance() +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + m_states .DblLinkedList_PushToCache(); + m_duplicates.DblLinkedList_PushToCache(); + + CLR_RT_HeapBlock_MemoryStream::DeleteInstance( m_stream ); + + g_CLR_RT_EventCache.Append_Node( this ); +} + +HRESULT CLR_RT_BinaryFormatter::Advance() +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + while(true) + { + State* top = (State*)m_states.LastNode(); if(top->Prev() == NULL) break; + + NANOCLR_CHECK_HRESULT(top->Advance()); + } + + NANOCLR_NOCLEANUP(); +} + +//--// + +void CLR_RT_BinaryFormatter::PrepareForGC( void* data ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + if(data != NULL) + { + CLR_RT_BinaryFormatter* bf = (CLR_RT_BinaryFormatter*)data; + + g_CLR_RT_GarbageCollector.CheckSingleBlock_Force( &bf->m_value ); + + NANOCLR_FOREACH_NODE(CLR_RT_BinaryFormatter::State,state,bf->m_states) + { + g_CLR_RT_GarbageCollector.CheckSingleBlock_Force( state->m_value.m_value ); + } + NANOCLR_FOREACH_NODE_END(); + } +} + +HRESULT CLR_RT_BinaryFormatter::Serialize( CLR_RT_HeapBlock& refData, CLR_RT_HeapBlock& object, CLR_RT_HeapBlock* cls, CLR_UINT32 flags ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + CLR_RT_BinaryFormatter* bf = NULL; + CLR_RT_ProtectFromGC pgc( (void**)&bf, CLR_RT_BinaryFormatter::PrepareForGC ); + + refData.SetObjectReference( NULL ); + + NANOCLR_CHECK_HRESULT(CLR_RT_BinaryFormatter::CreateInstance( NULL, 0, bf )); + + NANOCLR_CHECK_HRESULT(State::CreateInstance( bf, NULL, cls )); + + bf->m_flags = flags; + bf->m_value.Assign( object ); + + NANOCLR_CHECK_HRESULT(bf->Advance()); + + NANOCLR_CHECK_HRESULT(bf->m_stream->ToArray( refData )); + + NANOCLR_CLEANUP(); + + if(bf) + { + bf->DestroyInstance(); + + bf = NULL; + } + + NANOCLR_CLEANUP_END(); +} + +HRESULT CLR_RT_BinaryFormatter::Deserialize( CLR_RT_HeapBlock& refData, CLR_RT_HeapBlock& object, CLR_RT_HeapBlock* cls, CLR_UINT32* unknownType, CLR_UINT32 flags ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* array = object.DereferenceArray(); + + refData.SetObjectReference( NULL ); + + if(array != NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_RT_BinaryFormatter::Deserialize( refData, array->GetFirstElement(), array->m_numOfElements, cls, unknownType, flags )); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_BinaryFormatter::Deserialize( CLR_RT_HeapBlock& refData, CLR_UINT8* data, CLR_UINT32 size, CLR_RT_HeapBlock* cls, CLR_UINT32* unknownType, CLR_UINT32 flags ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + CLR_RT_BinaryFormatter* bf = NULL; + CLR_RT_ProtectFromGC pgc( (void**)&bf, CLR_RT_BinaryFormatter::PrepareForGC ); + + refData.SetObjectReference( NULL ); + + NANOCLR_CHECK_HRESULT(CLR_RT_BinaryFormatter::CreateInstance( data, size, bf )); + + NANOCLR_CHECK_HRESULT(State::CreateInstance( bf, NULL, cls )); + + bf->m_flags = flags; + + NANOCLR_CHECK_HRESULT(bf->Advance()); + + refData.Assign( bf->m_value ); + + + NANOCLR_CLEANUP(); + + if(bf) + { + if(unknownType) + { + *unknownType = (hr == CLR_E_WRONG_TYPE) ? bf->m_lastTypeRead : 0; + } + + bf->DestroyInstance(); + + bf = NULL; + } + + NANOCLR_CLEANUP_END(); +} + +//--// + +HRESULT CLR_RT_BinaryFormatter::TrackDuplicate( CLR_RT_HeapBlock* object ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + DuplicateTracker* ptr = EVENTCACHE_EXTRACT_NODE(g_CLR_RT_EventCache,DuplicateTracker,DATATYPE_SERIALIZER_DUPLICATE); + + CHECK_ALLOCATION(ptr); + + m_duplicates.LinkAtBack( ptr ); + + ptr->m_ptr = TypeHandler::FixDereference( object ); + ptr->m_idx = m_idx++; + + NANOCLR_NOCLEANUP(); +} + +CLR_UINT32 CLR_RT_BinaryFormatter::SearchDuplicate( CLR_RT_HeapBlock* object ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + object = TypeHandler::FixDereference( object ); + + NANOCLR_FOREACH_NODE(DuplicateTracker,ptr,m_duplicates) + { + if(ptr->m_ptr == object) + { + return ptr->m_idx; + } + } + NANOCLR_FOREACH_NODE_END(); + + return (CLR_UINT32)-1; +} + +CLR_RT_HeapBlock* CLR_RT_BinaryFormatter::GetDuplicate( CLR_UINT32 idx ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FOREACH_NODE(DuplicateTracker,ptr,m_duplicates) + { + if(ptr->m_idx == idx) + { + return ptr->m_ptr; + } + } + NANOCLR_FOREACH_NODE_END(); + + return NULL; +} + +//--//--// + +int CLR_RT_BinaryFormatter::BitsAvailable( ) { return m_stream->BitsAvailable( ); } + +HRESULT CLR_RT_BinaryFormatter::ReadBits ( CLR_UINT32& res, int bits ) { return m_stream->ReadBits ( res, bits ); } +HRESULT CLR_RT_BinaryFormatter::WriteBits ( CLR_UINT32 val, int bits ) { return m_stream->WriteBits ( val, bits ); } + +HRESULT CLR_RT_BinaryFormatter::ReadBits ( CLR_UINT64& res, int bits ) { return m_stream->ReadBits ( res, bits ); } +HRESULT CLR_RT_BinaryFormatter::WriteBits ( CLR_UINT64 val, int bits ) { return m_stream->WriteBits ( val, bits ); } + +HRESULT CLR_RT_BinaryFormatter::ReadArray ( CLR_UINT8* buf, int bytes ) { return m_stream->ReadArray ( buf, bytes ); } +HRESULT CLR_RT_BinaryFormatter::WriteArray ( const CLR_UINT8* buf, int bytes ) { return m_stream->WriteArray ( buf, bytes ); } + +HRESULT CLR_RT_BinaryFormatter::ReadCompressedUnsigned( CLR_UINT32& val ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + CLR_UINT32 extra; + + NANOCLR_CHECK_HRESULT(m_stream->ReadBits( val, 8 )); + + if(val == 0xFF) + { + val = 0xFFFFFFFF; + } + else + { + int bits = 0; + + switch(val & 0xC0) + { + case 0x00: bits = 0; break; + case 0x40: bits = 0; break; + case 0x80: bits = 8; break; + case 0xC0: bits = 24; break; + } + + if(bits) + { + hr = m_stream->ReadBits( extra, bits ); + + val = ((val & ~0xC0) << bits) | extra; + } + } + + + NANOCLR_CLEANUP(); + + NANOCLR_CLEANUP_END(); +} + +HRESULT CLR_RT_BinaryFormatter::WriteCompressedUnsigned( CLR_UINT32 val ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + int bits; + + if(val == 0xFFFFFFFF) + { + bits = 8; + } + else if(val < 0x80) + { + bits = 8; + } + else if(val < 0x3F00) + { + val |= 0x8000; + bits = 16; + } + else if(val < 0x3F000000) + { + val |= 0xC0000000; + bits = 32; + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + } + + NANOCLR_CHECK_HRESULT(m_stream->WriteBits( val, bits )); + + + NANOCLR_CLEANUP(); + + NANOCLR_CLEANUP_END(); +} + +//--// + +HRESULT CLR_RT_BinaryFormatter::ReadType( CLR_RT_ReflectionDef_Index& val ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + NANOCLR_CHECK_HRESULT(m_stream->ReadBits( m_lastTypeRead, 32 )); + + val.InitializeFromHash( m_lastTypeRead ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_BinaryFormatter::WriteType( const CLR_RT_ReflectionDef_Index& val ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(WriteType( val.GetTypeHash() )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_BinaryFormatter::WriteType( CLR_UINT32 hash ) +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_HEADER(); + + if(hash == 0xFFFFFFFF || hash == 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + NANOCLR_SET_AND_LEAVE(m_stream->WriteBits( hash, 32 )); + + NANOCLR_NOCLEANUP(); +} + diff --git a/source/native/nf-interpreter/src/CLR/Core/Serialization/BinaryFormatter_stub.cpp b/source/native/nf-interpreter/src/CLR/Core/Serialization/BinaryFormatter_stub.cpp new file mode 100644 index 00000000..ead85bd4 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Serialization/BinaryFormatter_stub.cpp @@ -0,0 +1,389 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include + +__nfweak bool CLR_RT_BinaryFormatter::SerializationEnabled() +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + return false; +} + +__nfweak CLR_RT_HeapBlock* CLR_RT_BinaryFormatter::TypeHandler::FixDereference( CLR_RT_HeapBlock* v ) +{ + (void)v; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + return NULL; +} + +__nfweak CLR_RT_HeapBlock* CLR_RT_BinaryFormatter::TypeHandler::FixNull( CLR_RT_HeapBlock* v ) +{ + (void)v; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + return NULL; +} + +//--// + +__nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::TypeHandler_Initialize( CLR_RT_BinaryFormatter* bf, SerializationHintsAttribute* hints, CLR_RT_TypeDescriptor* expected ) +{ + (void)bf; + (void)hints; + (void)expected; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +__nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::SetValue( CLR_RT_HeapBlock* v ) +{ + (void)v; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +//--// + +__nfweak int CLR_RT_BinaryFormatter::TypeHandler::SignatureRequirements() +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + return 0; +} + +__nfweak bool CLR_RT_BinaryFormatter::TypeHandler::CompareTypes( CLR_RT_TypeDescriptor* left, CLR_RT_TypeDescriptor* right ) +{ + (void)left; + (void)right; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + return true; +} + +__nfweak CLR_DataType CLR_RT_BinaryFormatter::TypeHandler::GetDataType( CLR_RT_TypeDescriptor* type ) +{ + (void)type; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + return (CLR_DataType)0; +} + +__nfweak CLR_UINT32 CLR_RT_BinaryFormatter::TypeHandler::GetSizeOfType( CLR_RT_TypeDescriptor* type ) +{ + (void)type; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + return 0; +} + +__nfweak bool CLR_RT_BinaryFormatter::TypeHandler::GetSignOfType( CLR_RT_TypeDescriptor* type ) +{ + (void)type; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + return true; +} + +//--// + +__nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitSignature( int& res ) +{ + (void)res; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +__nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitSignature_Inner( int mask, CLR_RT_TypeDescriptor* type, CLR_RT_HeapBlock* value ) +{ + (void)mask; + (void)type; + (void)value; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +//--// + +__nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::ReadSignature( int& res ) +{ + (void)res; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +//--// + +__nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::EmitValue( int& res ) +{ + (void)res; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +__nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::ReadValue( int& res ) +{ + (void)res; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +//--// + +__nfweak HRESULT CLR_RT_BinaryFormatter::TypeHandler::TrackObject( int& res ) +{ + (void)res; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +__nfweak HRESULT CLR_RT_BinaryFormatter::State::CreateInstance( CLR_RT_BinaryFormatter* parent, SerializationHintsAttribute* hints, CLR_RT_HeapBlock* type ) +{ + (void)parent; + (void)hints; + (void)type; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +__nfweak HRESULT CLR_RT_BinaryFormatter::State::CreateInstance( CLR_RT_BinaryFormatter* parent, SerializationHintsAttribute* hints, CLR_RT_TypeDescriptor* type ) +{ + (void)parent; + (void)hints; + (void)type; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +__nfweak void CLR_RT_BinaryFormatter::State::DestroyInstance() +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); +} + +//--// + +__nfweak HRESULT CLR_RT_BinaryFormatter::State::FindHints( SerializationHintsAttribute& hints, const CLR_RT_TypeDef_Instance& cls ) +{ + (void)hints; + (void)cls; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +__nfweak HRESULT CLR_RT_BinaryFormatter::State::FindHints( SerializationHintsAttribute& hints, const CLR_RT_FieldDef_Instance& fld ) +{ + (void)hints; + (void)fld; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +//--// + +__nfweak HRESULT CLR_RT_BinaryFormatter::State::AssignAndFixBoxing( CLR_RT_HeapBlock& dst ) +{ + (void)dst; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +__nfweak HRESULT CLR_RT_BinaryFormatter::State::GetValue() +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +__nfweak HRESULT CLR_RT_BinaryFormatter::State::SetValueAndDestroyInstance() +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +////////////////////////////////////////////////////////////////////////////////////////// + +__nfweak HRESULT CLR_RT_BinaryFormatter::State::Advance() +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +//--// + +__nfweak HRESULT CLR_RT_BinaryFormatter::State::AdvanceToTheNextField() +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +//--// + +__nfweak HRESULT CLR_RT_BinaryFormatter::State::AdvanceToTheNextElement() +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +__nfweak HRESULT CLR_RT_BinaryFormatter::CreateInstance( CLR_UINT8* buf, int len, CLR_RT_BinaryFormatter*& res ) +{ + (void)buf; + (void)len; + (void)res; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +__nfweak void CLR_RT_BinaryFormatter::DestroyInstance() +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); +} + +__nfweak HRESULT CLR_RT_BinaryFormatter::Advance() +{ + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +//--// + +__nfweak void CLR_RT_BinaryFormatter::PrepareForGC( void* data ) +{ + (void)data; + + NATIVE_PROFILE_CLR_SERIALIZATION(); +} + +__nfweak HRESULT CLR_RT_BinaryFormatter::Serialize( CLR_RT_HeapBlock& refData, CLR_RT_HeapBlock& object, CLR_RT_HeapBlock* cls, CLR_UINT32 flags ) +{ + (void)refData; + (void)object; + (void)cls; + (void)flags; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +__nfweak HRESULT CLR_RT_BinaryFormatter::Deserialize( CLR_RT_HeapBlock& refData, CLR_RT_HeapBlock& object, CLR_RT_HeapBlock* cls, CLR_UINT32* unknownType, CLR_UINT32 flags ) +{ + (void)refData; + (void)object; + (void)cls; + (void)unknownType; + (void)flags; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +__nfweak HRESULT CLR_RT_BinaryFormatter::Deserialize( CLR_RT_HeapBlock& refData, CLR_UINT8* data, CLR_UINT32 size, CLR_RT_HeapBlock* cls, CLR_UINT32* unknownType, CLR_UINT32 flags ) +{ + (void)refData; + (void)data; + (void)size; + (void)cls; + (void)unknownType; + (void)flags; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +//--// + +__nfweak HRESULT CLR_RT_BinaryFormatter::TrackDuplicate( CLR_RT_HeapBlock* object ) +{ + (void)object; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +__nfweak CLR_UINT32 CLR_RT_BinaryFormatter::SearchDuplicate( CLR_RT_HeapBlock* object ) +{ + (void)object; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + return (CLR_UINT32)-1; +} + +__nfweak CLR_RT_HeapBlock* CLR_RT_BinaryFormatter::GetDuplicate( CLR_UINT32 idx ) +{ + (void)idx; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + return NULL; +} + +//--//--// + +__nfweak int CLR_RT_BinaryFormatter::BitsAvailable( ) { return 0; } + +__nfweak HRESULT CLR_RT_BinaryFormatter::ReadBits ( CLR_UINT32& res, int bits ) { (void)res; (void)bits; NANOCLR_FEATURE_STUB_RETURN(); } +__nfweak HRESULT CLR_RT_BinaryFormatter::WriteBits ( CLR_UINT32 val, int bits ) { (void)val; (void)bits; NANOCLR_FEATURE_STUB_RETURN(); } + +__nfweak HRESULT CLR_RT_BinaryFormatter::ReadBits ( CLR_UINT64& res, int bits ) { (void)res; (void)bits; NANOCLR_FEATURE_STUB_RETURN(); } +__nfweak HRESULT CLR_RT_BinaryFormatter::WriteBits ( CLR_UINT64 val, int bits ) { (void)val; (void)bits; NANOCLR_FEATURE_STUB_RETURN(); } + +__nfweak HRESULT CLR_RT_BinaryFormatter::ReadArray ( CLR_UINT8* buf, int bytes ) { (void)buf; (void)bytes; NANOCLR_FEATURE_STUB_RETURN(); } +__nfweak HRESULT CLR_RT_BinaryFormatter::WriteArray ( const CLR_UINT8* buf, int bytes ) { (void)buf; (void)bytes; NANOCLR_FEATURE_STUB_RETURN(); } + +__nfweak HRESULT CLR_RT_BinaryFormatter::ReadCompressedUnsigned( CLR_UINT32& val ) +{ + (void)val; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +__nfweak HRESULT CLR_RT_BinaryFormatter::WriteCompressedUnsigned( CLR_UINT32 val ) +{ + (void)val; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +//--// + +__nfweak HRESULT CLR_RT_BinaryFormatter::ReadType( CLR_RT_ReflectionDef_Index& val ) +{ + (void)val; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +__nfweak HRESULT CLR_RT_BinaryFormatter::WriteType( const CLR_RT_ReflectionDef_Index& val ) +{ + (void)val; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} + +__nfweak HRESULT CLR_RT_BinaryFormatter::WriteType( CLR_UINT32 hash ) +{ + (void)hash; + + NATIVE_PROFILE_CLR_SERIALIZATION(); + NANOCLR_FEATURE_STUB_RETURN(); +} diff --git a/source/native/nf-interpreter/src/CLR/Core/Serialization/Serialization-vs2019.vcxproj b/source/native/nf-interpreter/src/CLR/Core/Serialization/Serialization-vs2019.vcxproj new file mode 100644 index 00000000..6c89da12 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Serialization/Serialization-vs2019.vcxproj @@ -0,0 +1,159 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + {16BF6131-A3B8-4B97-B867-E45669FB48BD} + Win32Proj + Serialization + 10.0.17763.0 + Serialization + + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + false + v142 + true + Unicode + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + false + v142 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(SolutionDir)$(Configuration)\ + $(IntDir) + + + $(SolutionDir)$(Configuration)\ + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\CorLib;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include;..\..\CorLib + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\CorLib;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include;..\..\CorLib + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/Serialization/Serialization-vs2019.vcxproj.filters b/source/native/nf-interpreter/src/CLR/Core/Serialization/Serialization-vs2019.vcxproj.filters new file mode 100644 index 00000000..2e4ce595 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Serialization/Serialization-vs2019.vcxproj.filters @@ -0,0 +1,22 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/Serialization/Serialization.vcxproj b/source/native/nf-interpreter/src/CLR/Core/Serialization/Serialization.vcxproj new file mode 100644 index 00000000..44d5953f --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Serialization/Serialization.vcxproj @@ -0,0 +1,158 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + {16BF6131-A3B8-4B97-B867-E45669FB48BD} + Win32Proj + Serialization + 10.0.17763.0 + + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\ + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\ + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\CorLib;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include;..\..\CorLib + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\CorLib;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include;..\..\CorLib + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/Serialization/Serialization.vcxproj.filters b/source/native/nf-interpreter/src/CLR/Core/Serialization/Serialization.vcxproj.filters new file mode 100644 index 00000000..2e4ce595 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Serialization/Serialization.vcxproj.filters @@ -0,0 +1,22 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/Serialization/Serialization_stub.vcxproj b/source/native/nf-interpreter/src/CLR/Core/Serialization/Serialization_stub.vcxproj new file mode 100644 index 00000000..03df5555 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Serialization/Serialization_stub.vcxproj @@ -0,0 +1,158 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + {C337041D-344D-49FE-AD99-B137E7FD0188} + Win32Proj + Serialization_stub + 10.0.17763.0 + + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\..\targets\os\win32\Include;..\..\Include;..\..\..\HAL\Include;..\..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\Include + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/Serialization/Serialization_stub.vcxproj.filters b/source/native/nf-interpreter/src/CLR/Core/Serialization/Serialization_stub.vcxproj.filters new file mode 100644 index 00000000..4e5d8b8e --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Serialization/Serialization_stub.vcxproj.filters @@ -0,0 +1,22 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Core/Streams.cpp b/source/native/nf-interpreter/src/CLR/Core/Streams.cpp new file mode 100644 index 00000000..3b38e3b0 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Streams.cpp @@ -0,0 +1,297 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +HRESULT CLR_RT_HeapBlock_MemoryStream::CreateInstance( CLR_RT_HeapBlock_MemoryStream*& stream, CLR_UINT8* buf, int len ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + stream = EVENTCACHE_EXTRACT_NODE(g_CLR_RT_EventCache,CLR_RT_HeapBlock_MemoryStream,DATATYPE_MEMORY_STREAM_HEAD); CHECK_ALLOCATION(stream); + + NANOCLR_SET_AND_LEAVE(stream->Initialize( buf, len )); + + NANOCLR_NOCLEANUP(); +} + +void CLR_RT_HeapBlock_MemoryStream::DeleteInstance( CLR_RT_HeapBlock_MemoryStream*& stream ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(stream) + { + stream->Release(); + + g_CLR_RT_EventCache.Append_Node( stream ); + + stream = NULL; + } +} + +HRESULT CLR_RT_HeapBlock_MemoryStream::Initialize( CLR_UINT8* buf, CLR_UINT32 len ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + m_buffers.DblLinkedList_Initialize(); // CLR_RT_DblLinkedList m_buffers; // EVENT HEAP - NO RELOCATION - list of CLR_RT_HeapBlock_MemoryStream::Buffer + + CHECK_ALLOCATION(NewBuffer()); + + if(buf) + { + m_current->m_data = buf; + m_current->m_length = len; + } + + NANOCLR_NOCLEANUP(); +} + +void CLR_RT_HeapBlock_MemoryStream::Release() +{ + NATIVE_PROFILE_CLR_CORE(); + m_buffers.DblLinkedList_PushToCache(); +} + +//--// + +void CLR_RT_HeapBlock_MemoryStream::Rewind() +{ + NATIVE_PROFILE_CLR_CORE(); + m_current = (Buffer*)m_buffers.FirstNode(); + m_pos = -1; + m_avail = 0; +} + +void CLR_RT_HeapBlock_MemoryStream::Reset() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_NODE(Buffer,node,m_buffers) + { + node->m_length = 0; + } + NANOCLR_FOREACH_NODE_END(); + Rewind(); +} + +HRESULT CLR_RT_HeapBlock_MemoryStream::ToArray( CLR_RT_HeapBlock& ref ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_UINT32 tot; + CLR_RT_HeapBlock_Array* array; + CLR_UINT8* buf; + + tot = 0; + NANOCLR_FOREACH_NODE(Buffer,node,m_buffers) + { + tot += node->m_length; + } + NANOCLR_FOREACH_NODE_END(); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( ref, tot, g_CLR_RT_WellKnownTypes.m_UInt8 )); + + array = ref.DereferenceArray(); + buf = array->GetFirstElement(); + + NANOCLR_FOREACH_NODE(Buffer,node,m_buffers) + { + memcpy( buf, node->m_payload, node->m_length ); buf += node->m_length; + } + NANOCLR_FOREACH_NODE_END(); + + NANOCLR_NOCLEANUP(); +} + +//--// + +CLR_RT_HeapBlock_MemoryStream::Buffer* CLR_RT_HeapBlock_MemoryStream::NewBuffer() +{ + NATIVE_PROFILE_CLR_CORE(); + Buffer* ptr = EVENTCACHE_EXTRACT_NODE(g_CLR_RT_EventCache,Buffer,DATATYPE_MEMORY_STREAM_DATA); + + if(ptr) + { + m_current = ptr; + m_pos = -1; + m_avail = 0; + + ptr->m_data = ptr->m_payload; + ptr->m_length = 0; + + m_buffers.LinkAtBack( ptr ); + } + + return ptr; +} + +//--// + +int CLR_RT_HeapBlock_MemoryStream::BitsAvailable() +{ + NATIVE_PROFILE_CLR_CORE(); + int val = m_avail - 8 * m_pos - 8; + + NANOCLR_FOREACH_NODE__DIRECT(Buffer,ptr,m_current) + { + val += 8 * ptr->m_length; + } + NANOCLR_FOREACH_NODE_END(); + + return val; +} + +int CLR_RT_HeapBlock_MemoryStream::BitsWritten() +{ + NATIVE_PROFILE_CLR_CORE(); + int val = m_pos * 8 - m_avail + 8; + + NANOCLR_FOREACH_NODE_BACKWARD__DIRECT(Buffer,ptr,m_current->Prev()) + { + val += 8 * ptr->m_length; + } + NANOCLR_FOREACH_NODE_END(); + + return val; +} + +HRESULT CLR_RT_HeapBlock_MemoryStream::ReadBits( CLR_UINT64& res, CLR_UINT32 bits ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_UINT32* ptr = (CLR_UINT32*)&res; + + if(bits > 32) { NANOCLR_CHECK_HRESULT(ReadBits( ptr[ 1 ], bits - 32 )); bits = 32; } + else { ptr[ 1 ] = 0; } + + NANOCLR_SET_AND_LEAVE(ReadBits( ptr[ 0 ], bits )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock_MemoryStream::ReadBits( CLR_UINT32& res, CLR_UINT32 bits ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_UINT32 val = 0; + CLR_UINT32 pos = bits; + + while(bits > 0) + { + while(m_avail == 0) + { + m_pos++; + m_avail = 8; + + while(m_pos >= m_current->m_length) + { + m_current = (Buffer*)m_current->Next(); + + if(m_current->Next() == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + } + + m_pos = 0; + } + } + + CLR_UINT32 insert = (bits < m_avail) ? bits : m_avail; + CLR_UINT32 mask = (1 << insert) - 1; + + pos -= insert; val |= (((CLR_UINT32)m_current->m_data[ m_pos ] >> (m_avail - insert)) & mask) << pos; + bits -= insert; + m_avail -= insert; + } + + res = val; + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock_MemoryStream::WriteBits( CLR_UINT64 res, CLR_UINT32 bits ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(bits > 32) { NANOCLR_CHECK_HRESULT(WriteBits( (CLR_UINT32)(res >> 32), bits - 32 )); bits = 32; } + + NANOCLR_SET_AND_LEAVE(WriteBits( (CLR_UINT32)res, bits )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock_MemoryStream::WriteBits( CLR_UINT32 val, CLR_UINT32 bits ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_UINT32 pos = bits; + + while(bits > 0) + { + while(m_avail == 0) + { + m_pos++; + + if(m_pos < (int)sizeof(m_current->m_payload)) + { + m_current->m_length++; + m_current->m_payload[ m_pos ] = 0; + m_avail = 8; + break; + } + + CHECK_ALLOCATION(NewBuffer()); + } + + CLR_UINT32 insert = (bits < m_avail) ? bits : m_avail; + CLR_UINT32 mask = (1 << insert) - 1; + + pos -= insert; m_current->m_payload[ m_pos ] |= (CLR_UINT8)(((val >> pos) & mask) << (m_avail - insert)); + bits -= insert; + m_avail -= insert; + + } + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT CLR_RT_HeapBlock_MemoryStream::ReadArray( CLR_UINT8* buf, CLR_UINT32 bytes ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_UINT32 data; + + while(bytes-- > 0) + { + NANOCLR_CHECK_HRESULT(ReadBits( data, 8 )); + + *buf++ = (CLR_UINT8)data; + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_HeapBlock_MemoryStream::WriteArray( const CLR_UINT8* buf, CLR_UINT32 bytes ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + while(bytes-- > 0) + { + NANOCLR_CHECK_HRESULT(WriteBits( (CLR_UINT32)*buf++, 8 )); + } + + NANOCLR_NOCLEANUP(); +} + diff --git a/source/native/nf-interpreter/src/CLR/Core/StringTable.cpp b/source/native/nf-interpreter/src/CLR/Core/StringTable.cpp new file mode 100644 index 00000000..dddd76a4 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/StringTable.cpp @@ -0,0 +1,53 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "stdafx.h" + +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#include "StringTableData.cpp" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +void CLR_RT_Assembly::InitString() +{ + NATIVE_PROFILE_CLR_CORE(); +} + +const char* CLR_RT_Assembly::GetString( CLR_STRING i ) +{ + NATIVE_PROFILE_CLR_CORE(); + static const CLR_STRING iMax = 0xFFFF - c_CLR_StringTable_Size; + + if(i >= iMax) + { + return &c_CLR_StringTable_Data[ c_CLR_StringTable_Lookup[ (CLR_STRING)0xFFFF - i ] ]; + } + + return &(((const char*)GetTable( TBL_Strings ))[ i ]); +} + +#if defined(_WIN32) + +void CLR_RT_Assembly::InitString( std::map& map ) +{ + NATIVE_PROFILE_CLR_CORE(); + const CLR_STRING* array = c_CLR_StringTable_Lookup; + size_t len = c_CLR_StringTable_Size; + CLR_STRING idx = 0xFFFF; + + map.clear(); + + while(len-- > 0) + { + map[ &c_CLR_StringTable_Data[ *array++ ] ] = idx--; + } +} + +#endif + diff --git a/source/native/nf-interpreter/src/CLR/Core/StringTableData.cpp b/source/native/nf-interpreter/src/CLR/Core/StringTableData.cpp new file mode 100644 index 00000000..93610e8a --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/StringTableData.cpp @@ -0,0 +1,1741 @@ +// +// The StringTable was generated from the following +// specified in Microsoft.SPOT.Support.Settings: +// +// Microsoft.SPOT.Native.strings +// mscorlib.strings +// +#if defined(__GNUC__) +#include +#include +#endif + +const size_t c_CLR_StringTable_Size = 860; + +const CLR_STRING c_CLR_StringTable_Lookup[] = +{ + /* 0000 */ 0, + /* 0001 */ 7, + /* 0002 */ 13, + /* 0003 */ 19, + /* 0004 */ 23, + /* 0005 */ 56, + /* 0006 */ 61, + /* 0007 */ 65, + /* 0008 */ 73, + /* 0009 */ 82, + /* 000A */ 98, + /* 000B */ 109, + /* 000C */ 120, + /* 000D */ 129, + /* 000E */ 150, + /* 000F */ 160, + /* 0010 */ 187, + /* 0011 */ 194, + /* 0012 */ 207, + /* 0013 */ 218, + /* 0014 */ 238, + /* 0015 */ 259, + /* 0016 */ 277, + /* 0017 */ 299, + /* 0018 */ 327, + /* 0019 */ 337, + /* 001A */ 343, + /* 001B */ 353, + /* 001C */ 363, + /* 001D */ 368, + /* 001E */ 377, + /* 001F */ 390, + /* 0020 */ 409, + /* 0021 */ 422, + /* 0022 */ 440, + /* 0023 */ 452, + /* 0024 */ 472, + /* 0025 */ 479, + /* 0026 */ 493, + /* 0027 */ 498, + /* 0028 */ 504, + /* 0029 */ 514, + /* 002A */ 525, + /* 002B */ 544, + /* 002C */ 559, + /* 002D */ 569, + /* 002E */ 579, + /* 002F */ 591, + /* 0030 */ 596, + /* 0031 */ 609, + /* 0032 */ 616, + /* 0033 */ 629, + /* 0034 */ 642, + /* 0035 */ 652, + /* 0036 */ 660, + /* 0037 */ 666, + /* 0038 */ 671, + /* 0039 */ 680, + /* 003A */ 688, + /* 003B */ 695, + /* 003C */ 700, + /* 003D */ 706, + /* 003E */ 712, + /* 003F */ 718, + /* 0040 */ 724, + /* 0041 */ 732, + /* 0042 */ 746, + /* 0043 */ 754, + /* 0044 */ 770, + /* 0045 */ 780, + /* 0046 */ 791, + /* 0047 */ 798, + /* 0048 */ 818, + /* 0049 */ 834, + /* 004A */ 848, + /* 004B */ 861, + /* 004C */ 870, + /* 004D */ 878, + /* 004E */ 883, + /* 004F */ 890, + /* 0050 */ 907, + /* 0051 */ 911, + /* 0052 */ 916, + /* 0053 */ 929, + /* 0054 */ 944, + /* 0055 */ 968, + /* 0056 */ 980, + /* 0057 */ 993, + /* 0058 */ 1015, + /* 0059 */ 1024, + /* 005A */ 1039, + /* 005B */ 1058, + /* 005C */ 1071, + /* 005D */ 1075, + /* 005E */ 1085, + /* 005F */ 1098, + /* 0060 */ 1111, + /* 0061 */ 1124, + /* 0062 */ 1137, + /* 0063 */ 1149, + /* 0064 */ 1155, + /* 0065 */ 1175, + /* 0066 */ 1184, + /* 0067 */ 1199, + /* 0068 */ 1207, + /* 0069 */ 1217, + /* 006A */ 1226, + /* 006B */ 1234, + /* 006C */ 1246, + /* 006D */ 1262, + /* 006E */ 1270, + /* 006F */ 1277, + /* 0070 */ 1295, + /* 0071 */ 1304, + /* 0072 */ 1325, + /* 0073 */ 1331, + /* 0074 */ 1348, + /* 0075 */ 1357, + /* 0076 */ 1367, + /* 0077 */ 1376, + /* 0078 */ 1384, + /* 0079 */ 1399, + /* 007A */ 1425, + /* 007B */ 1446, + /* 007C */ 1452, + /* 007D */ 1458, + /* 007E */ 1470, + /* 007F */ 1475, + /* 0080 */ 1490, + /* 0081 */ 1497, + /* 0082 */ 1507, + /* 0083 */ 1521, + /* 0084 */ 1531, + /* 0085 */ 1544, + /* 0086 */ 1554, + /* 0087 */ 1563, + /* 0088 */ 1583, + /* 0089 */ 1588, + /* 008A */ 1592, + /* 008B */ 1607, + /* 008C */ 1621, + /* 008D */ 1643, + /* 008E */ 1662, + /* 008F */ 1684, + /* 0090 */ 1706, + /* 0091 */ 1718, + /* 0092 */ 1727, + /* 0093 */ 1744, + /* 0094 */ 1754, + /* 0095 */ 1763, + /* 0096 */ 1780, + /* 0097 */ 1789, + /* 0098 */ 1807, + /* 0099 */ 1820, + /* 009A */ 1826, + /* 009B */ 1832, + /* 009C */ 1838, + /* 009D */ 1847, + /* 009E */ 1854, + /* 009F */ 1871, + /* 00A0 */ 1884, + /* 00A1 */ 1897, + /* 00A2 */ 1917, + /* 00A3 */ 1934, + /* 00A4 */ 1944, + /* 00A5 */ 1947, + /* 00A6 */ 1960, + /* 00A7 */ 1968, + /* 00A8 */ 1982, + /* 00A9 */ 1994, + /* 00AA */ 2014, + /* 00AB */ 2030, + /* 00AC */ 2046, + /* 00AD */ 2068, + /* 00AE */ 2091, + /* 00AF */ 2100, + /* 00B0 */ 2109, + /* 00B1 */ 2124, + /* 00B2 */ 2136, + /* 00B3 */ 2155, + /* 00B4 */ 2166, + /* 00B5 */ 2193, + /* 00B6 */ 2221, + /* 00B7 */ 2231, + /* 00B8 */ 2247, + /* 00B9 */ 2264, + /* 00BA */ 2279, + /* 00BB */ 2293, + /* 00BC */ 2314, + /* 00BD */ 2332, + /* 00BE */ 2341, + /* 00BF */ 2351, + /* 00C0 */ 2361, + /* 00C1 */ 2373, + /* 00C2 */ 2387, + /* 00C3 */ 2402, + /* 00C4 */ 2427, + /* 00C5 */ 2438, + /* 00C6 */ 2448, + /* 00C7 */ 2459, + /* 00C8 */ 2467, + /* 00C9 */ 2477, + /* 00CA */ 2498, + /* 00CB */ 2514, + /* 00CC */ 2532, + /* 00CD */ 2547, + /* 00CE */ 2568, + /* 00CF */ 2580, + /* 00D0 */ 2595, + /* 00D1 */ 2609, + /* 00D2 */ 2630, + /* 00D3 */ 2640, + /* 00D4 */ 2657, + /* 00D5 */ 2675, + /* 00D6 */ 2683, + /* 00D7 */ 2701, + /* 00D8 */ 2717, + /* 00D9 */ 2729, + /* 00DA */ 2745, + /* 00DB */ 2754, + /* 00DC */ 2784, + /* 00DD */ 2797, + /* 00DE */ 2806, + /* 00DF */ 2817, + /* 00E0 */ 2847, + /* 00E1 */ 2852, + /* 00E2 */ 2857, + /* 00E3 */ 2867, + /* 00E4 */ 2887, + /* 00E5 */ 2897, + /* 00E6 */ 2902, + /* 00E7 */ 2915, + /* 00E8 */ 2926, + /* 00E9 */ 2938, + /* 00EA */ 2950, + /* 00EB */ 2960, + /* 00EC */ 2977, + /* 00ED */ 2989, + /* 00EE */ 3001, + /* 00EF */ 3015, + /* 00F0 */ 3027, + /* 00F1 */ 3039, + /* 00F2 */ 3057, + /* 00F3 */ 3072, + /* 00F4 */ 3088, + /* 00F5 */ 3104, + /* 00F6 */ 3117, + /* 00F7 */ 3123, + /* 00F8 */ 3128, + /* 00F9 */ 3140, + /* 00FA */ 3161, + /* 00FB */ 3170, + /* 00FC */ 3180, + /* 00FD */ 3188, + /* 00FE */ 3199, + /* 00FF */ 3224, + /* 0100 */ 3235, + /* 0101 */ 3251, + /* 0102 */ 3276, + /* 0103 */ 3296, + /* 0104 */ 3303, + /* 0105 */ 3325, + /* 0106 */ 3346, + /* 0107 */ 3354, + /* 0108 */ 3360, + /* 0109 */ 3366, + /* 010A */ 3372, + /* 010B */ 3390, + /* 010C */ 3397, + /* 010D */ 3409, + /* 010E */ 3416, + /* 010F */ 3437, + /* 0110 */ 3463, + /* 0111 */ 3470, + /* 0112 */ 3483, + /* 0113 */ 3504, + /* 0114 */ 3515, + /* 0115 */ 3526, + /* 0116 */ 3543, + /* 0117 */ 3554, + /* 0118 */ 3560, + /* 0119 */ 3579, + /* 011A */ 3598, + /* 011B */ 3611, + /* 011C */ 3630, + /* 011D */ 3643, + /* 011E */ 3648, + /* 011F */ 3652, + /* 0120 */ 3666, + /* 0121 */ 3678, + /* 0122 */ 3693, + /* 0123 */ 3698, + /* 0124 */ 3711, + /* 0125 */ 3715, + /* 0126 */ 3721, + /* 0127 */ 3730, + /* 0128 */ 3747, + /* 0129 */ 3766, + /* 012A */ 3771, + /* 012B */ 3775, + /* 012C */ 3784, + /* 012D */ 3795, + /* 012E */ 3807, + /* 012F */ 3823, + /* 0130 */ 3831, + /* 0131 */ 3844, + /* 0132 */ 3855, + /* 0133 */ 3865, + /* 0134 */ 3883, + /* 0135 */ 3894, + /* 0136 */ 3904, + /* 0137 */ 3922, + /* 0138 */ 3937, + /* 0139 */ 3961, + /* 013A */ 3986, + /* 013B */ 4007, + /* 013C */ 4020, + /* 013D */ 4024, + /* 013E */ 4033, + /* 013F */ 4040, + /* 0140 */ 4048, + /* 0141 */ 4054, + /* 0142 */ 4063, + /* 0143 */ 4081, + /* 0144 */ 4098, + /* 0145 */ 4105, + /* 0146 */ 4113, + /* 0147 */ 4118, + /* 0148 */ 4128, + /* 0149 */ 4139, + /* 014A */ 4163, + /* 014B */ 4185, + /* 014C */ 4208, + /* 014D */ 4215, + /* 014E */ 4232, + /* 014F */ 4239, + /* 0150 */ 4263, + /* 0151 */ 4271, + /* 0152 */ 4292, + /* 0153 */ 4298, + /* 0154 */ 4316, + /* 0155 */ 4333, + /* 0156 */ 4347, + /* 0157 */ 4364, + /* 0158 */ 4383, + /* 0159 */ 4397, + /* 015A */ 4402, + /* 015B */ 4408, + /* 015C */ 4412, + /* 015D */ 4429, + /* 015E */ 4448, + /* 015F */ 4452, + /* 0160 */ 4458, + /* 0161 */ 4472, + /* 0162 */ 4485, + /* 0163 */ 4507, + /* 0164 */ 4520, + /* 0165 */ 4525, + /* 0166 */ 4549, + /* 0167 */ 4555, + /* 0168 */ 4561, + /* 0169 */ 4569, + /* 016A */ 4576, + /* 016B */ 4586, + /* 016C */ 4608, + /* 016D */ 4613, + /* 016E */ 4622, + /* 016F */ 4630, + /* 0170 */ 4646, + /* 0171 */ 4662, + /* 0172 */ 4673, + /* 0173 */ 4680, + /* 0174 */ 4697, + /* 0175 */ 4714, + /* 0176 */ 4721, + /* 0177 */ 4730, + /* 0178 */ 4738, + /* 0179 */ 4756, + /* 017A */ 4780, + /* 017B */ 4802, + /* 017C */ 4822, + /* 017D */ 4828, + /* 017E */ 4837, + /* 017F */ 4843, + /* 0180 */ 4859, + /* 0181 */ 4875, + /* 0182 */ 4885, + /* 0183 */ 4899, + /* 0184 */ 4917, + /* 0185 */ 4932, + /* 0186 */ 4955, + /* 0187 */ 4962, + /* 0188 */ 4970, + /* 0189 */ 4976, + /* 018A */ 4996, + /* 018B */ 5018, + /* 018C */ 5041, + /* 018D */ 5060, + /* 018E */ 5077, + /* 018F */ 5092, + /* 0190 */ 5112, + /* 0191 */ 5130, + /* 0192 */ 5142, + /* 0193 */ 5160, + /* 0194 */ 5166, + /* 0195 */ 5184, + /* 0196 */ 5190, + /* 0197 */ 5197, + /* 0198 */ 5202, + /* 0199 */ 5213, + /* 019A */ 5225, + /* 019B */ 5240, + /* 019C */ 5259, + /* 019D */ 5287, + /* 019E */ 5297, + /* 019F */ 5301, + /* 01A0 */ 5313, + /* 01A1 */ 5333, + /* 01A2 */ 5343, + /* 01A3 */ 5356, + /* 01A4 */ 5365, + /* 01A5 */ 5370, + /* 01A6 */ 5381, + /* 01A7 */ 5385, + /* 01A8 */ 5392, + /* 01A9 */ 5397, + /* 01AA */ 5403, + /* 01AB */ 5410, + /* 01AC */ 5419, + /* 01AD */ 5431, + /* 01AE */ 5437, + /* 01AF */ 5442, + /* 01B0 */ 5448, + /* 01B1 */ 5461, + /* 01B2 */ 5474, + /* 01B3 */ 5487, + /* 01B4 */ 5493, + /* 01B5 */ 5504, + /* 01B6 */ 5517, + /* 01B7 */ 5524, + /* 01B8 */ 5531, + /* 01B9 */ 5545, + /* 01BA */ 5561, + /* 01BB */ 5569, + /* 01BC */ 5579, + /* 01BD */ 5588, + /* 01BE */ 5605, + /* 01BF */ 5613, + /* 01C0 */ 5620, + /* 01C1 */ 5639, + /* 01C2 */ 5680, + /* 01C3 */ 5709, + /* 01C4 */ 5740, + /* 01C5 */ 5774, + /* 01C6 */ 5807, + /* 01C7 */ 5839, + /* 01C8 */ 5871, + /* 01C9 */ 5905, + /* 01CA */ 5939, + /* 01CB */ 5973, + /* 01CC */ 5995, + /* 01CD */ 6014, + /* 01CE */ 6035, + /* 01CF */ 6066, + /* 01D0 */ 6076, + /* 01D1 */ 6094, + /* 01D2 */ 6111, + /* 01D3 */ 6143, + /* 01D4 */ 6167, + /* 01D5 */ 6193, + /* 01D6 */ 6239, + /* 01D7 */ 6251, + /* 01D8 */ 6268, + /* 01D9 */ 6284, + /* 01DA */ 6293, + /* 01DB */ 6304, + /* 01DC */ 6315, + /* 01DD */ 6319, + /* 01DE */ 6324, + /* 01DF */ 6331, + /* 01E0 */ 6356, + /* 01E1 */ 6363, + /* 01E2 */ 6384, + /* 01E3 */ 6399, + /* 01E4 */ 6411, + /* 01E5 */ 6423, + /* 01E6 */ 6428, + /* 01E7 */ 6439, + /* 01E8 */ 6448, + /* 01E9 */ 6458, + /* 01EA */ 6467, + /* 01EB */ 6478, + /* 01EC */ 6498, + /* 01ED */ 6504, + /* 01EE */ 6518, + /* 01EF */ 6528, + /* 01F0 */ 6536, + /* 01F1 */ 6551, + /* 01F2 */ 6561, + /* 01F3 */ 6568, + /* 01F4 */ 6580, + /* 01F5 */ 6587, + /* 01F6 */ 6599, + /* 01F7 */ 6608, + /* 01F8 */ 6616, + /* 01F9 */ 6624, + /* 01FA */ 6632, + /* 01FB */ 6644, + /* 01FC */ 6652, + /* 01FD */ 6660, + /* 01FE */ 6669, + /* 01FF */ 6678, + /* 0200 */ 6687, + /* 0201 */ 6696, + /* 0202 */ 6705, + /* 0203 */ 6721, + /* 0204 */ 6729, + /* 0205 */ 6740, + /* 0206 */ 6753, + /* 0207 */ 6775, + /* 0208 */ 6800, + /* 0209 */ 6811, + /* 020A */ 6827, + /* 020B */ 6841, + /* 020C */ 6862, + /* 020D */ 6886, + /* 020E */ 6894, + /* 020F */ 6900, + /* 0210 */ 6905, + /* 0211 */ 6913, + /* 0212 */ 6923, + /* 0213 */ 6934, + /* 0214 */ 6943, + /* 0215 */ 6952, + /* 0216 */ 6965, + /* 0217 */ 6970, + /* 0218 */ 6979, + /* 0219 */ 6987, + /* 021A */ 7003, + /* 021B */ 7011, + /* 021C */ 7027, + /* 021D */ 7036, + /* 021E */ 7053, + /* 021F */ 7060, + /* 0220 */ 7067, + /* 0221 */ 7074, + /* 0222 */ 7086, + /* 0223 */ 7099, + /* 0224 */ 7120, + /* 0225 */ 7127, + /* 0226 */ 7135, + /* 0227 */ 7150, + /* 0228 */ 7156, + /* 0229 */ 7172, + /* 022A */ 7182, + /* 022B */ 7190, + /* 022C */ 7195, + /* 022D */ 7203, + /* 022E */ 7211, + /* 022F */ 7236, + /* 0230 */ 7247, + /* 0231 */ 7260, + /* 0232 */ 7268, + /* 0233 */ 7281, + /* 0234 */ 7295, + /* 0235 */ 7301, + /* 0236 */ 7311, + /* 0237 */ 7313, + /* 0238 */ 7329, + /* 0239 */ 7331, + /* 023A */ 7336, + /* 023B */ 7341, + /* 023C */ 7348, + /* 023D */ 7355, + /* 023E */ 7362, + /* 023F */ 7372, + /* 0240 */ 7379, + /* 0241 */ 7392, + /* 0242 */ 7402, + /* 0243 */ 7411, + /* 0244 */ 7418, + /* 0245 */ 7428, + /* 0246 */ 7450, + /* 0247 */ 7465, + /* 0248 */ 7479, + /* 0249 */ 7485, + /* 024A */ 7492, + /* 024B */ 7499, + /* 024C */ 7511, + /* 024D */ 7526, + /* 024E */ 7535, + /* 024F */ 7552, + /* 0250 */ 7560, + /* 0251 */ 7566, + /* 0252 */ 7578, + /* 0253 */ 7584, + /* 0254 */ 7604, + /* 0255 */ 7626, + /* 0256 */ 7639, + /* 0257 */ 7653, + /* 0258 */ 7666, + /* 0259 */ 7675, + /* 025A */ 7695, + /* 025B */ 7718, + /* 025C */ 7742, + /* 025D */ 7759, + /* 025E */ 7783, + /* 025F */ 7809, + /* 0260 */ 7819, + /* 0261 */ 7832, + /* 0262 */ 7858, + /* 0263 */ 7871, + /* 0264 */ 7881, + /* 0265 */ 7893, + /* 0266 */ 7905, + /* 0267 */ 7920, + /* 0268 */ 7933, + /* 0269 */ 7946, + /* 026A */ 7956, + /* 026B */ 7966, + /* 026C */ 7978, + /* 026D */ 7996, + /* 026E */ 8012, + /* 026F */ 8030, + /* 0270 */ 8050, + /* 0271 */ 8071, + /* 0272 */ 8100, + /* 0273 */ 8109, + /* 0274 */ 8127, + /* 0275 */ 8146, + /* 0276 */ 8154, + /* 0277 */ 8167, + /* 0278 */ 8181, + /* 0279 */ 8195, + /* 027A */ 8212, + /* 027B */ 8221, + /* 027C */ 8239, + /* 027D */ 8249, + /* 027E */ 8257, + /* 027F */ 8271, + /* 0280 */ 8285, + /* 0281 */ 8295, + /* 0282 */ 8320, + /* 0283 */ 8338, + /* 0284 */ 8355, + /* 0285 */ 8379, + /* 0286 */ 8392, + /* 0287 */ 8419, + /* 0288 */ 8447, + /* 0289 */ 8464, + /* 028A */ 8473, + /* 028B */ 8483, + /* 028C */ 8490, + /* 028D */ 8509, + /* 028E */ 8524, + /* 028F */ 8536, + /* 0290 */ 8548, + /* 0291 */ 8563, + /* 0292 */ 8579, + /* 0293 */ 8591, + /* 0294 */ 8602, + /* 0295 */ 8614, + /* 0296 */ 8630, + /* 0297 */ 8646, + /* 0298 */ 8665, + /* 0299 */ 8681, + /* 029A */ 8694, + /* 029B */ 8709, + /* 029C */ 8728, + /* 029D */ 8741, + /* 029E */ 8760, + /* 029F */ 8772, + /* 02A0 */ 8788, + /* 02A1 */ 8802, + /* 02A2 */ 8813, + /* 02A3 */ 8822, + /* 02A4 */ 8831, + /* 02A5 */ 8840, + /* 02A6 */ 8859, + /* 02A7 */ 8870, + /* 02A8 */ 8890, + /* 02A9 */ 8910, + /* 02AA */ 8920, + /* 02AB */ 8940, + /* 02AC */ 8956, + /* 02AD */ 8974, + /* 02AE */ 8989, + /* 02AF */ 9001, + /* 02B0 */ 9012, + /* 02B1 */ 9028, + /* 02B2 */ 9045, + /* 02B3 */ 9055, + /* 02B4 */ 9066, + /* 02B5 */ 9078, + /* 02B6 */ 9088, + /* 02B7 */ 9098, + /* 02B8 */ 9118, + /* 02B9 */ 9133, + /* 02BA */ 9142, + /* 02BB */ 9159, + /* 02BC */ 9167, + /* 02BD */ 9194, + /* 02BE */ 9211, + /* 02BF */ 9236, + /* 02C0 */ 9257, + /* 02C1 */ 9265, + /* 02C2 */ 9279, + /* 02C3 */ 9302, + /* 02C4 */ 9319, + /* 02C5 */ 9333, + /* 02C6 */ 9344, + /* 02C7 */ 9356, + /* 02C8 */ 9371, + /* 02C9 */ 9384, + /* 02CA */ 9401, + /* 02CB */ 9414, + /* 02CC */ 9431, + /* 02CD */ 9448, + /* 02CE */ 9467, + /* 02CF */ 9483, + /* 02D0 */ 9503, + /* 02D1 */ 9518, + /* 02D2 */ 9531, + /* 02D3 */ 9539, + /* 02D4 */ 9550, + /* 02D5 */ 9562, + /* 02D6 */ 9575, + /* 02D7 */ 9596, + /* 02D8 */ 9617, + /* 02D9 */ 9645, + /* 02DA */ 9660, + /* 02DB */ 9677, + /* 02DC */ 9687, + /* 02DD */ 9699, + /* 02DE */ 9712, + /* 02DF */ 9723, + /* 02E0 */ 9739, + /* 02E1 */ 9749, + /* 02E2 */ 9763, + /* 02E3 */ 9781, + /* 02E4 */ 9791, + /* 02E5 */ 9800, + /* 02E6 */ 9837, + /* 02E7 */ 9860, + /* 02E8 */ 9871, + /* 02E9 */ 9882, + /* 02EA */ 9894, + /* 02EB */ 9911, + /* 02EC */ 9920, + /* 02ED */ 9941, + /* 02EE */ 9944, + /* 02EF */ 9950, + /* 02F0 */ 9954, + /* 02F1 */ 9970, + /* 02F2 */ 9986, + /* 02F3 */ 9998, + /* 02F4 */ 10011, + /* 02F5 */ 10025, + /* 02F6 */ 10039, + /* 02F7 */ 10055, + /* 02F8 */ 10066, + /* 02F9 */ 10076, + /* 02FA */ 10081, + /* 02FB */ 10095, + /* 02FC */ 10106, + /* 02FD */ 10115, + /* 02FE */ 10127, + /* 02FF */ 10138, + /* 0300 */ 10153, + /* 0301 */ 10164, + /* 0302 */ 10175, + /* 0303 */ 10189, + /* 0304 */ 10203, + /* 0305 */ 10217, + /* 0306 */ 10224, + /* 0307 */ 10232, + /* 0308 */ 10248, + /* 0309 */ 10254, + /* 030A */ 10271, + /* 030B */ 10279, + /* 030C */ 10294, + /* 030D */ 10303, + /* 030E */ 10310, + /* 030F */ 10315, + /* 0310 */ 10332, + /* 0311 */ 10341, + /* 0312 */ 10351, + /* 0313 */ 10358, + /* 0314 */ 10370, + /* 0315 */ 10379, + /* 0316 */ 10390, + /* 0317 */ 10400, + /* 0318 */ 10407, + /* 0319 */ 10414, + /* 031A */ 10431, + /* 031B */ 10436, + /* 031C */ 10449, + /* 031D */ 10460, + /* 031E */ 10466, + /* 031F */ 10482, + /* 0320 */ 10489, + /* 0321 */ 10498, + /* 0322 */ 10511, + /* 0323 */ 10519, + /* 0324 */ 10527, + /* 0325 */ 10537, + /* 0326 */ 10545, + /* 0327 */ 10559, + /* 0328 */ 10567, + /* 0329 */ 10574, + /* 032A */ 10582, + /* 032B */ 10590, + /* 032C */ 10606, + /* 032D */ 10617, + /* 032E */ 10626, + /* 032F */ 10639, + /* 0330 */ 10644, + /* 0331 */ 10652, + /* 0332 */ 10675, + /* 0333 */ 10696, + /* 0334 */ 10713, + /* 0335 */ 10725, + /* 0336 */ 10737, + /* 0337 */ 10752, + /* 0338 */ 10774, + /* 0339 */ 10788, + /* 033A */ 10800, + /* 033B */ 10819, + /* 033C */ 10834, + /* 033D */ 10851, + /* 033E */ 10864, + /* 033F */ 10877, + /* 0340 */ 10890, + /* 0341 */ 10903, + /* 0342 */ 10914, + /* 0343 */ 10920, + /* 0344 */ 10938, + /* 0345 */ 10959, + /* 0346 */ 10987, + /* 0347 */ 11015, + /* 0348 */ 11028, + /* 0349 */ 11057, + /* 034A */ 11082, + /* 034B */ 11099, + /* 034C */ 11108, + /* 034D */ 11119, + /* 034E */ 11137, + /* 034F */ 11150, + /* 0350 */ 11163, + /* 0351 */ 11179, + /* 0352 */ 11190, + /* 0353 */ 11213, + /* 0354 */ 11230, + /* 0355 */ 11247, + /* 0356 */ 11264, + /* 0357 */ 11269, + /* 0358 */ 11283, + /* 0359 */ 11297, + /* 035A */ 11303, + /* 035B */ 11311, +}; + +const char c_CLR_StringTable_Data[] = + /* 0000 */ ".cctor\0" + /* 0001 */ ".ctor\0" + /* 0002 */ "Abort\0" + /* 0003 */ "Abs\0" + /* 0004 */ "AccessedThroughPropertyAttribute\0" + /* 0005 */ "Acos\0" + /* 0006 */ "Add\0" + /* 0007 */ "AddDays\0" + /* 0008 */ "AddHours\0" + /* 0009 */ "AddMilliseconds\0" + /* 000A */ "AddMinutes\0" + /* 000B */ "AddSeconds\0" + /* 000C */ "AddTicks\0" + /* 000D */ "AnyPendingFinalizers\0" + /* 000E */ "AppDomain\0" + /* 000F */ "AppDomainUnloadedException\0" + /* 0010 */ "Append\0" + /* 0011 */ "AppendHelper\0" + /* 0012 */ "AppendLine\0" + /* 0013 */ "AppendTrailingZeros\0" + /* 0014 */ "ApplicationException\0" + /* 0015 */ "ArgumentException\0" + /* 0016 */ "ArgumentNullException\0" + /* 0017 */ "ArgumentOutOfRangeException\0" + /* 0018 */ "Arguments\0" + /* 0019 */ "Array\0" + /* 001A */ "ArrayList\0" + /* 001B */ "ArraySize\0" + /* 001C */ "Asin\0" + /* 001D */ "Assembly\0" + /* 001E */ "AssemblyInfo\0" + /* 001F */ "AssemblyMemoryInfo\0" + /* 0020 */ "AssemblyName\0" + /* 0021 */ "AssemblyNameFlags\0" + /* 0022 */ "AssemblyRef\0" + /* 0023 */ "AssemblyRefElements\0" + /* 0024 */ "Assert\0" + /* 0025 */ "AsyncCallback\0" + /* 0026 */ "Atan\0" + /* 0027 */ "Atan2\0" + /* 0028 */ "Attribute\0" + /* 0029 */ "Attributes\0" + /* 002A */ "AttributesElements\0" + /* 002B */ "AutoResetEvent\0" + /* 002C */ "Backlight\0" + /* 002D */ "BaseEvent\0" + /* 002E */ "BeginInvoke\0" + /* 002F */ "Bias\0" + /* 0030 */ "BinarySearch\0" + /* 0031 */ "Binder\0" + /* 0032 */ "BindingFlags\0" + /* 0033 */ "BitConverter\0" + /* 0034 */ "BitPacked\0" + /* 0035 */ "Boolean\0" + /* 0036 */ "Break\0" + /* 0037 */ "Byte\0" + /* 0038 */ "ByteCode\0" + /* 0039 */ "Ceiling\0" + /* 003A */ "Change\0" + /* 003B */ "Char\0" + /* 003C */ "Check\0" + /* 003D */ "Clear\0" + /* 003E */ "Clone\0" + /* 003F */ "Close\0" + /* 0040 */ "Combine\0" + /* 0041 */ "CombineArrays\0" + /* 0042 */ "Compare\0" + /* 0043 */ "CompareExchange\0" + /* 0044 */ "CompareTo\0" + /* 0045 */ "ComputeCRC\0" + /* 0046 */ "Concat\0" + /* 0047 */ "ConstraintException\0" + /* 0048 */ "ConstructorInfo\0" + /* 0049 */ "ContactHeight\0" + /* 004A */ "ContactWidth\0" + /* 004B */ "Contains\0" + /* 004C */ "Convert\0" + /* 004D */ "Copy\0" + /* 004E */ "CopyTo\0" + /* 004F */ "CopyToCollection\0" + /* 0050 */ "Cos\0" + /* 0051 */ "Cosh\0" + /* 0052 */ "CreateDomain\0" + /* 0053 */ "CreateInstance\0" + /* 0054 */ "CreateInstanceAndUnwrap\0" + /* 0055 */ "CultureInfo\0" + /* 0056 */ "CultureTypes\0" + /* 0057 */ "CurrentSystemTimeZone\0" + /* 0058 */ "DateTime\0" + /* 0059 */ "DateTimeFormat\0" + /* 005A */ "DateTimeFormatInfo\0" + /* 005B */ "DateTimeKind\0" + /* 005C */ "Day\0" + /* 005D */ "DayOfWeek\0" + /* 005E */ "DaylightBias\0" + /* 005F */ "DaylightDate\0" + /* 0060 */ "DaylightName\0" + /* 0061 */ "DaylightTime\0" + /* 0062 */ "DaysInMonth\0" + /* 0063 */ "Debug\0" + /* 0064 */ "DebuggableAttribute\0" + /* 0065 */ "Debugger\0" + /* 0066 */ "DebuggingModes\0" + /* 0067 */ "Decoder\0" + /* 0068 */ "Decrement\0" + /* 0069 */ "Delegate\0" + /* 006A */ "Dequeue\0" + /* 006B */ "Deserialize\0" + /* 006C */ "DictionaryEntry\0" + /* 006D */ "Dispose\0" + /* 006E */ "Double\0" + /* 006F */ "DoubleToInt64Bits\0" + /* 0070 */ "Duration\0" + /* 0071 */ "EditorBrowsableState\0" + /* 0072 */ "Empty\0" + /* 0073 */ "EnableGCMessages\0" + /* 0074 */ "Encoding\0" + /* 0075 */ "EndInvoke\0" + /* 0076 */ "EndPoint\0" + /* 0077 */ "Enqueue\0" + /* 0078 */ "EnsureCapacity\0" + /* 0079 */ "EnsureStringArrayResource\0" + /* 007A */ "EnsureStringResource\0" + /* 007B */ "Enter\0" + /* 007C */ "Entry\0" + /* 007D */ "EntryForKey\0" + /* 007E */ "Enum\0" + /* 007F */ "EnumeratorType\0" + /* 0080 */ "Equals\0" + /* 0081 */ "EventArgs\0" + /* 0082 */ "EventCategory\0" + /* 0083 */ "EventData\0" + /* 0084 */ "EventMessage\0" + /* 0085 */ "Exception\0" + /* 0086 */ "Exchange\0" + /* 0087 */ "ExecutionConstraint\0" + /* 0088 */ "Exit\0" + /* 0089 */ "Exp\0" + /* 008A */ "ExpandByABlock\0" + /* 008B */ "ExtendedTimer\0" + /* 008C */ "ExtendedWeakReference\0" + /* 008D */ "ExtensionAttribute\0" + /* 008E */ "ExtractRangeFromArray\0" + /* 008F */ "ExtractValueFromArray\0" + /* 0090 */ "FalseString\0" + /* 0091 */ "FieldDef\0" + /* 0092 */ "FieldDefElements\0" + /* 0093 */ "FieldInfo\0" + /* 0094 */ "FieldRef\0" + /* 0095 */ "FieldRefElements\0" + /* 0096 */ "Finalize\0" + /* 0097 */ "FindChunkForIndex\0" + /* 0098 */ "FindResource\0" + /* 0099 */ "Flags\0" + /* 009A */ "Floor\0" + /* 009B */ "Flush\0" + /* 009C */ "FlushAll\0" + /* 009D */ "Format\0" + /* 009E */ "FormatCustomized\0" + /* 009F */ "FormatDigits\0" + /* 00A0 */ "FormatNative\0" + /* 00A1 */ "FromBase64CharArray\0" + /* 00A2 */ "FromBase64String\0" + /* 00A3 */ "FromTicks\0" + /* 00A4 */ "GC\0" + /* 00A5 */ "GenericEvent\0" + /* 00A6 */ "Gesture\0" + /* 00A7 */ "GetAssemblies\0" + /* 00A8 */ "GetAssembly\0" + /* 00A9 */ "GetAssemblyFromHash\0" + /* 00AA */ "GetAssemblyHash\0" + /* 00AB */ "GetAssemblyInfo\0" + /* 00AC */ "GetAssemblyMemoryInfo\0" + /* 00AD */ "GetBase64EncodedLength\0" + /* 00AE */ "GetBytes\0" + /* 00AF */ "GetChars\0" + /* 00B0 */ "GetConstructor\0" + /* 00B1 */ "GetCultures\0" + /* 00B2 */ "GetDaylightChanges\0" + /* 00B3 */ "GetDecoder\0" + /* 00B4 */ "GetDelimitedStringResource\0" + /* 00B5 */ "GetDelimitedStringResources\0" + /* 00B6 */ "GetDomain\0" + /* 00B7 */ "GetDoubleNumber\0" + /* 00B8 */ "GetEffectiveDate\0" + /* 00B9 */ "GetElementType\0" + /* 00BA */ "GetEnumerator\0" + /* 00BB */ "GetExecutingAssembly\0" + /* 00BC */ "GetExpirationDate\0" + /* 00BD */ "GetField\0" + /* 00BE */ "GetFields\0" + /* 00BF */ "GetFormat\0" + /* 00C0 */ "GetHashCode\0" + /* 00C1 */ "GetInterfaces\0" + /* 00C2 */ "GetMachineTime\0" + /* 00C3 */ "GetManifestResourceNames\0" + /* 00C4 */ "GetMessage\0" + /* 00C5 */ "GetMethod\0" + /* 00C6 */ "GetMethods\0" + /* 00C7 */ "GetName\0" + /* 00C8 */ "GetObject\0" + /* 00C9 */ "GetObjectChunkFromId\0" + /* 00CA */ "GetObjectFromId\0" + /* 00CB */ "GetObjectInternal\0" + /* 00CC */ "GetObjectValue\0" + /* 00CD */ "GetParentCultureName\0" + /* 00CE */ "GetPosition\0" + /* 00CF */ "GetRawCertData\0" + /* 00D0 */ "GetRealFormat\0" + /* 00D1 */ "GetSatelliteAssembly\0" + /* 00D2 */ "GetString\0" + /* 00D3 */ "GetSystemVersion\0" + /* 00D4 */ "GetTimeZoneOffset\0" + /* 00D5 */ "GetType\0" + /* 00D6 */ "GetTypeFromHandle\0" + /* 00D7 */ "GetTypeFromHash\0" + /* 00D8 */ "GetTypeHash\0" + /* 00D9 */ "GetTypeInternal\0" + /* 00DA */ "GetTypes\0" + /* 00DB */ "GetTypesImplementingInterface\0" + /* 00DC */ "GetUtcOffset\0" + /* 00DD */ "GetValue\0" + /* 00DE */ "GetVersion\0" + /* 00DF */ "GloballySynchronizedAttribute\0" + /* 00E0 */ "Guid\0" + /* 00E1 */ "Hash\0" + /* 00E2 */ "Hashtable\0" + /* 00E3 */ "HashtableEnumerator\0" + /* 00E4 */ "HexToChar\0" + /* 00E5 */ "Hour\0" + /* 00E6 */ "IAsyncResult\0" + /* 00E7 */ "ICloneable\0" + /* 00E8 */ "ICollection\0" + /* 00E9 */ "IComparable\0" + /* 00EA */ "IComparer\0" + /* 00EB */ "ICustomFormatter\0" + /* 00EC */ "IDictionary\0" + /* 00ED */ "IDisposable\0" + /* 00EE */ "IEEERemainder\0" + /* 00EF */ "IEnumerable\0" + /* 00F0 */ "IEnumerator\0" + /* 00F1 */ "IEqualityComparer\0" + /* 00F2 */ "IEventListener\0" + /* 00F3 */ "IEventProcessor\0" + /* 00F4 */ "IFormatProvider\0" + /* 00F5 */ "IFormattable\0" + /* 00F6 */ "IList\0" + /* 00F7 */ "ILog\0" + /* 00F8 */ "IOException\0" + /* 00F9 */ "IOExceptionErrorCode\0" + /* 00FA */ "IReflect\0" + /* 00FB */ "Increment\0" + /* 00FC */ "IndexOf\0" + /* 00FD */ "IndexOfAny\0" + /* 00FE */ "IndexOutOfRangeException\0" + /* 00FF */ "Initialize\0" + /* 0100 */ "InitializeArray\0" + /* 0101 */ "InitializeForEventSource\0" + /* 0102 */ "InitializeHashTable\0" + /* 0103 */ "Insert\0" + /* 0104 */ "InsertGroupSeperators\0" + /* 0105 */ "InsertValueIntoArray\0" + /* 0106 */ "Install\0" + /* 0107 */ "Int16\0" + /* 0108 */ "Int32\0" + /* 0109 */ "Int64\0" + /* 010A */ "Int64BitsToDouble\0" + /* 010B */ "IntPtr\0" + /* 010C */ "Interlocked\0" + /* 010D */ "Intern\0" + /* 010E */ "InvalidCastException\0" + /* 010F */ "InvalidOperationException\0" + /* 0110 */ "Invoke\0" + /* 0111 */ "InvokeMember\0" + /* 0112 */ "IsDaylightSavingTime\0" + /* 0113 */ "IsEmulator\0" + /* 0114 */ "IsInfinity\0" + /* 0115 */ "IsInstanceOfType\0" + /* 0116 */ "IsInterned\0" + /* 0117 */ "IsNaN\0" + /* 0118 */ "IsNegativeInfinity\0" + /* 0119 */ "IsPositiveInfinity\0" + /* 011A */ "IsSubclassOf\0" + /* 011B */ "IsTransparentProxy\0" + /* 011C */ "IsTypeLoaded\0" + /* 011D */ "Join\0" + /* 011E */ "Key\0" + /* 011F */ "KeyCollection\0" + /* 0120 */ "LastIndexOf\0" + /* 0121 */ "LastIndexOfAny\0" + /* 0122 */ "Load\0" + /* 0123 */ "LoadInternal\0" + /* 0124 */ "Log\0" + /* 0125 */ "Log10\0" + /* 0126 */ "MakeRoom\0" + /* 0127 */ "ManualResetEvent\0" + /* 0128 */ "MarshalByRefObject\0" + /* 0129 */ "Math\0" + /* 012A */ "Max\0" + /* 012B */ "MaxValue\0" + /* 012C */ "MemberInfo\0" + /* 012D */ "MemberTypes\0" + /* 012E */ "MemberwiseClone\0" + /* 012F */ "Message\0" + /* 0130 */ "MetadataSize\0" + /* 0131 */ "MethodBase\0" + /* 0132 */ "MethodDef\0" + /* 0133 */ "MethodDefElements\0" + /* 0134 */ "MethodInfo\0" + /* 0135 */ "MethodRef\0" + /* 0136 */ "MethodRefElements\0" + /* 0137 */ "Microsoft.SPOT\0" + /* 0138 */ "Microsoft.SPOT.Hardware\0" + /* 0139 */ "Microsoft.SPOT.Messaging\0" + /* 013A */ "Microsoft.SPOT.Touch\0" + /* 013B */ "Milliseconds\0" + /* 013C */ "Min\0" + /* 013D */ "MinValue\0" + /* 013E */ "Minute\0" + /* 013F */ "Monitor\0" + /* 0140 */ "Month\0" + /* 0141 */ "MoveNext\0" + /* 0142 */ "MulticastDelegate\0" + /* 0143 */ "Native_Resources\0" + /* 0144 */ "Negate\0" + /* 0145 */ "NewGuid\0" + /* 0146 */ "Next\0" + /* 0147 */ "NextBytes\0" + /* 0148 */ "NextDouble\0" + /* 0149 */ "NotImplementedException\0" + /* 014A */ "NotSupportedException\0" + /* 014B */ "NullReferenceException\0" + /* 014C */ "Number\0" + /* 014D */ "NumberFormatInfo\0" + /* 014E */ "Object\0" + /* 014F */ "ObjectDisposedException\0" + /* 0150 */ "OnEvent\0" + /* 0151 */ "OutOfMemoryException\0" + /* 0152 */ "Parse\0" + /* 0153 */ "ParseAssemblyName\0" + /* 0154 */ "ParseCertificate\0" + /* 0155 */ "ParseNextChar\0" + /* 0156 */ "ParseQuoteString\0" + /* 0157 */ "ParseRepeatPattern\0" + /* 0158 */ "ParseTypeName\0" + /* 0159 */ "Peek\0" + /* 015A */ "Piezo\0" + /* 015B */ "Pop\0" + /* 015C */ "PostProcessFloat\0" + /* 015D */ "PostProcessInteger\0" + /* 015E */ "Pow\0" + /* 015F */ "Print\0" + /* 0160 */ "PriorityLevel\0" + /* 0161 */ "ProcessEvent\0" + /* 0162 */ "ProcessorArchitecture\0" + /* 0163 */ "PropertyInfo\0" + /* 0164 */ "Push\0" + /* 0165 */ "PushBackIntoRecoverList\0" + /* 0166 */ "Queue\0" + /* 0167 */ "Raise\0" + /* 0168 */ "RamSize\0" + /* 0169 */ "Random\0" + /* 016A */ "RangeBias\0" + /* 016B */ "ReRegisterForFinalize\0" + /* 016C */ "Read\0" + /* 016D */ "ReadByte\0" + /* 016E */ "Recover\0" + /* 016F */ "RecoverOrCreate\0" + /* 0170 */ "ReferenceEquals\0" + /* 0171 */ "Reflection\0" + /* 0172 */ "Rehash\0" + /* 0173 */ "RemotedException\0" + /* 0174 */ "RemotingServices\0" + /* 0175 */ "Remove\0" + /* 0176 */ "RemoveAt\0" + /* 0177 */ "Replace\0" + /* 0178 */ "ReplaceAllInChunk\0" + /* 0179 */ "ReplaceDecimalSeperator\0" + /* 017A */ "ReplaceInPlaceAtChunk\0" + /* 017B */ "ReplaceNegativeSign\0" + /* 017C */ "Reply\0" + /* 017D */ "ReplyRaw\0" + /* 017E */ "Reset\0" + /* 017F */ "ResourceManager\0" + /* 0180 */ "ResourceUtility\0" + /* 0181 */ "Resources\0" + /* 0182 */ "ResourcesData\0" + /* 0183 */ "ResourcesElements\0" + /* 0184 */ "ResourcesFiles\0" + /* 0185 */ "ResourcesFilesElements\0" + /* 0186 */ "Resume\0" + /* 0187 */ "RomSize\0" + /* 0188 */ "Round\0" + /* 0189 */ "RunClassConstructor\0" + /* 018A */ "RuntimeArgumentHandle\0" + /* 018B */ "RuntimeConstructorInfo\0" + /* 018C */ "RuntimeFieldHandle\0" + /* 018D */ "RuntimeFieldInfo\0" + /* 018E */ "RuntimeHelpers\0" + /* 018F */ "RuntimeMethodHandle\0" + /* 0190 */ "RuntimeMethodInfo\0" + /* 0191 */ "RuntimeType\0" + /* 0192 */ "RuntimeTypeHandle\0" + /* 0193 */ "SByte\0" + /* 0194 */ "SZArrayEnumerator\0" + /* 0195 */ "Scale\0" + /* 0196 */ "Second\0" + /* 0197 */ "Seek\0" + /* 0198 */ "SeekOrigin\0" + /* 0199 */ "SendMessage\0" + /* 019A */ "SendMessageRaw\0" + /* 019B */ "SerializationFlags\0" + /* 019C */ "SerializationHintsAttribute\0" + /* 019D */ "Serialize\0" + /* 019E */ "Set\0" + /* 019F */ "SetCapacity\0" + /* 01A0 */ "SetCurrentUICulture\0" + /* 01A1 */ "SetLength\0" + /* 01A2 */ "SetLocalTime\0" + /* 01A3 */ "SetValue\0" + /* 01A4 */ "Sign\0" + /* 01A5 */ "Signatures\0" + /* 01A6 */ "Sin\0" + /* 01A7 */ "Single\0" + /* 01A8 */ "Sinh\0" + /* 01A9 */ "Sleep\0" + /* 01AA */ "Source\0" + /* 01AB */ "SourceID\0" + /* 01AC */ "SpecifyKind\0" + /* 01AD */ "Split\0" + /* 01AE */ "Sqrt\0" + /* 01AF */ "Stack\0" + /* 01B0 */ "StandardBias\0" + /* 01B1 */ "StandardDate\0" + /* 01B2 */ "StandardName\0" + /* 01B3 */ "Start\0" + /* 01B4 */ "StartsWith\0" + /* 01B5 */ "StaticFields\0" + /* 01B6 */ "Stream\0" + /* 01B7 */ "String\0" + /* 01B8 */ "StringBuilder\0" + /* 01B9 */ "StringResources\0" + /* 01BA */ "Strings\0" + /* 01BB */ "Substring\0" + /* 01BC */ "Subtract\0" + /* 01BD */ "SuppressFinalize\0" + /* 01BE */ "Suspend\0" + /* 01BF */ "System\0" + /* 01C0 */ "System.Collections\0" + /* 01C1 */ "System.Collections.ICollection.get_Count\0" + /* 01C2 */ "System.Collections.IList.Add\0" + /* 01C3 */ "System.Collections.IList.Clear\0" + /* 01C4 */ "System.Collections.IList.Contains\0" + /* 01C5 */ "System.Collections.IList.IndexOf\0" + /* 01C6 */ "System.Collections.IList.Insert\0" + /* 01C7 */ "System.Collections.IList.Remove\0" + /* 01C8 */ "System.Collections.IList.RemoveAt\0" + /* 01C9 */ "System.Collections.IList.get_Item\0" + /* 01CA */ "System.Collections.IList.set_Item\0" + /* 01CB */ "System.ComponentModel\0" + /* 01CC */ "System.Diagnostics\0" + /* 01CD */ "System.Globalization\0" + /* 01CE */ "System.Globalization.Resources\0" + /* 01CF */ "System.IO\0" + /* 01D0 */ "System.Reflection\0" + /* 01D1 */ "System.Resources\0" + /* 01D2 */ "System.Runtime.CompilerServices\0" + /* 01D3 */ "System.Runtime.Remoting\0" + /* 01D4 */ "System.Runtime.Versioning\0" + /* 01D5 */ "System.Security.Cryptography.X509Certificates\0" + /* 01D6 */ "System.Text\0" + /* 01D7 */ "System.Threading\0" + /* 01D8 */ "SystemException\0" + /* 01D9 */ "SystemID\0" + /* 01DA */ "SystemInfo\0" + /* 01DB */ "SystemTime\0" + /* 01DC */ "Tan\0" + /* 01DD */ "Tanh\0" + /* 01DE */ "Target\0" + /* 01DF */ "TargetFrameworkAttribute\0" + /* 01E0 */ "Thread\0" + /* 01E1 */ "ThreadAbortException\0" + /* 01E2 */ "ThreadPriority\0" + /* 01E3 */ "ThreadStart\0" + /* 01E4 */ "ThreadState\0" + /* 01E5 */ "Time\0" + /* 01E6 */ "TimeEvents\0" + /* 01E7 */ "TimeSpan\0" + /* 01E8 */ "TimeStamp\0" + /* 01E9 */ "TimeZone\0" + /* 01EA */ "TimeZoneId\0" + /* 01EB */ "TimeZoneInformation\0" + /* 01EC */ "Timer\0" + /* 01ED */ "TimerCallback\0" + /* 01EE */ "Timestamp\0" + /* 01EF */ "ToArray\0" + /* 01F0 */ "ToBase64String\0" + /* 01F1 */ "ToBoolean\0" + /* 01F2 */ "ToByte\0" + /* 01F3 */ "ToByteArray\0" + /* 01F4 */ "ToChar\0" + /* 01F5 */ "ToCharArray\0" + /* 01F6 */ "ToDouble\0" + /* 01F7 */ "ToInt16\0" + /* 01F8 */ "ToInt32\0" + /* 01F9 */ "ToInt64\0" + /* 01FA */ "ToLocalTime\0" + /* 01FB */ "ToLower\0" + /* 01FC */ "ToSByte\0" + /* 01FD */ "ToSingle\0" + /* 01FE */ "ToString\0" + /* 01FF */ "ToUInt16\0" + /* 0200 */ "ToUInt32\0" + /* 0201 */ "ToUInt64\0" + /* 0202 */ "ToUniversalTime\0" + /* 0203 */ "ToUpper\0" + /* 0204 */ "TouchEvent\0" + /* 0205 */ "TouchGesture\0" + /* 0206 */ "TouchGestureEventArgs\0" + /* 0207 */ "TouchGestureEventHandler\0" + /* 0208 */ "TouchInput\0" + /* 0209 */ "TouchInputFlags\0" + /* 020A */ "TouchMessages\0" + /* 020B */ "TouchScreenEventArgs\0" + /* 020C */ "TouchScreenEventHandler\0" + /* 020D */ "Touches\0" + /* 020E */ "Trace\0" + /* 020F */ "Trim\0" + /* 0210 */ "TrimEnd\0" + /* 0211 */ "TrimStart\0" + /* 0212 */ "TrueString\0" + /* 0213 */ "Truncate\0" + /* 0214 */ "TryParse\0" + /* 0215 */ "TrySZIndexOf\0" + /* 0216 */ "Type\0" + /* 0217 */ "TypeCode\0" + /* 0218 */ "TypeDef\0" + /* 0219 */ "TypeDefElements\0" + /* 021A */ "TypeRef\0" + /* 021B */ "TypeRefElements\0" + /* 021C */ "TypeSpec\0" + /* 021D */ "TypeSpecElements\0" + /* 021E */ "UInt16\0" + /* 021F */ "UInt32\0" + /* 0220 */ "UInt64\0" + /* 0221 */ "UTF8Decoder\0" + /* 0222 */ "UTF8Encoding\0" + /* 0223 */ "UnknownTypeException\0" + /* 0224 */ "Unload\0" + /* 0225 */ "Utility\0" + /* 0226 */ "ValidateFormat\0" + /* 0227 */ "Value\0" + /* 0228 */ "ValueCollection\0" + /* 0229 */ "ValueType\0" + /* 022A */ "Version\0" + /* 022B */ "Void\0" + /* 022C */ "WaitAll\0" + /* 022D */ "WaitAny\0" + /* 022E */ "WaitForPendingFinalizers\0" + /* 022F */ "WaitHandle\0" + /* 0230 */ "WaitMultiple\0" + /* 0231 */ "WaitOne\0" + /* 0232 */ "WeakDelegate\0" + /* 0233 */ "WeakReference\0" + /* 0234 */ "Write\0" + /* 0235 */ "WriteByte\0" + /* 0236 */ "X\0" + /* 0237 */ "X509Certificate\0" + /* 0238 */ "Y\0" + /* 0239 */ "Year\0" + /* 023A */ "Zero\0" + /* 023B */ "_Build\0" + /* 023C */ "_Major\0" + /* 023D */ "_Minor\0" + /* 023E */ "_Revision\0" + /* 023F */ "_array\0" + /* 0240 */ "_arrayLength\0" + /* 0241 */ "_assembly\0" + /* 0242 */ "_buckets\0" + /* 0243 */ "_count\0" + /* 0244 */ "_endIndex\0" + /* 0245 */ "_frameworkDisplayName\0" + /* 0246 */ "_frameworkName\0" + /* 0247 */ "_growthFactor\0" + /* 0248 */ "_head\0" + /* 0249 */ "_index\0" + /* 024A */ "_items\0" + /* 024B */ "_loadFactor\0" + /* 024C */ "_maxLoadFactor\0" + /* 024D */ "_message\0" + /* 024E */ "_numberOfBuckets\0" + /* 024F */ "_random\0" + /* 0250 */ "_size\0" + /* 0251 */ "_startIndex\0" + /* 0252 */ "_tail\0" + /* 0253 */ "abbreviatedDayNames\0" + /* 0254 */ "abbreviatedMonthNames\0" + /* 0255 */ "amDesignator\0" + /* 0256 */ "dateSeparator\0" + /* 0257 */ "dateTimeInfo\0" + /* 0258 */ "dayNames\0" + /* 0259 */ "fullDateTimePattern\0" + /* 025A */ "generalLongTimePattern\0" + /* 025B */ "generalShortTimePattern\0" + /* 025C */ "get_AMDesignator\0" + /* 025D */ "get_AbbreviatedDayNames\0" + /* 025E */ "get_AbbreviatedMonthNames\0" + /* 025F */ "get_Angle\0" + /* 0260 */ "get_Assembly\0" + /* 0261 */ "get_AssemblyQualifiedName\0" + /* 0262 */ "get_BaseType\0" + /* 0263 */ "get_Build\0" + /* 0264 */ "get_CanRead\0" + /* 0265 */ "get_CanSeek\0" + /* 0266 */ "get_CanTimeout\0" + /* 0267 */ "get_CanWrite\0" + /* 0268 */ "get_Capacity\0" + /* 0269 */ "get_Chars\0" + /* 026A */ "get_Count\0" + /* 026B */ "get_Current\0" + /* 026C */ "get_CurrentDomain\0" + /* 026D */ "get_CurrentInfo\0" + /* 026E */ "get_CurrentThread\0" + /* 026F */ "get_CurrentTimeZone\0" + /* 0270 */ "get_CurrentUICulture\0" + /* 0271 */ "get_CurrentUICultureInternal\0" + /* 0272 */ "get_Date\0" + /* 0273 */ "get_DateSeparator\0" + /* 0274 */ "get_DateTimeFormat\0" + /* 0275 */ "get_Day\0" + /* 0276 */ "get_DayNames\0" + /* 0277 */ "get_DayOfWeek\0" + /* 0278 */ "get_DayOfYear\0" + /* 0279 */ "get_DaylightName\0" + /* 027A */ "get_Days\0" + /* 027B */ "get_DeclaringType\0" + /* 027C */ "get_Delta\0" + /* 027D */ "get_End\0" + /* 027E */ "get_ErrorCode\0" + /* 027F */ "get_FieldType\0" + /* 0280 */ "get_Flags\0" + /* 0281 */ "get_FrameworkDisplayName\0" + /* 0282 */ "get_FrameworkName\0" + /* 0283 */ "get_FriendlyName\0" + /* 0284 */ "get_FullDateTimePattern\0" + /* 0285 */ "get_FullName\0" + /* 0286 */ "get_GeneralLongTimePattern\0" + /* 0287 */ "get_GeneralShortTimePattern\0" + /* 0288 */ "get_GrowthFactor\0" + /* 0289 */ "get_Hour\0" + /* 028A */ "get_Hours\0" + /* 028B */ "get_Id\0" + /* 028C */ "get_InnerException\0" + /* 028D */ "get_IsAbstract\0" + /* 028E */ "get_IsAlive\0" + /* 028F */ "get_IsArray\0" + /* 0290 */ "get_IsAttached\0" + /* 0291 */ "get_IsBigEndian\0" + /* 0292 */ "get_IsClass\0" + /* 0293 */ "get_IsEnum\0" + /* 0294 */ "get_IsFinal\0" + /* 0295 */ "get_IsFixedSize\0" + /* 0296 */ "get_IsInterface\0" + /* 0297 */ "get_IsLittleEndian\0" + /* 0298 */ "get_IsNotPublic\0" + /* 0299 */ "get_IsPublic\0" + /* 029A */ "get_IsReadOnly\0" + /* 029B */ "get_IsSerializable\0" + /* 029C */ "get_IsStatic\0" + /* 029D */ "get_IsSynchronized\0" + /* 029E */ "get_IsValid\0" + /* 029F */ "get_IsValueType\0" + /* 02A0 */ "get_IsVirtual\0" + /* 02A1 */ "get_Issuer\0" + /* 02A2 */ "get_Item\0" + /* 02A3 */ "get_Keys\0" + /* 02A4 */ "get_Kind\0" + /* 02A5 */ "get_LastExpiration\0" + /* 02A6 */ "get_Length\0" + /* 02A7 */ "get_LongDatePattern\0" + /* 02A8 */ "get_LongTimePattern\0" + /* 02A9 */ "get_Major\0" + /* 02AA */ "get_ManagedThreadId\0" + /* 02AB */ "get_MaxCapacity\0" + /* 02AC */ "get_MaxLoadFactor\0" + /* 02AD */ "get_MemberType\0" + /* 02AE */ "get_Message\0" + /* 02AF */ "get_Method\0" + /* 02B0 */ "get_Millisecond\0" + /* 02B1 */ "get_Milliseconds\0" + /* 02B2 */ "get_Minor\0" + /* 02B3 */ "get_Minute\0" + /* 02B4 */ "get_Minutes\0" + /* 02B5 */ "get_Model\0" + /* 02B6 */ "get_Month\0" + /* 02B7 */ "get_MonthDayPattern\0" + /* 02B8 */ "get_MonthNames\0" + /* 02B9 */ "get_Name\0" + /* 02BA */ "get_NegativeSign\0" + /* 02BB */ "get_Now\0" + /* 02BC */ "get_NumberDecimalSeparator\0" + /* 02BD */ "get_NumberFormat\0" + /* 02BE */ "get_NumberGroupSeparator\0" + /* 02BF */ "get_NumberGroupSizes\0" + /* 02C0 */ "get_OEM\0" + /* 02C1 */ "get_OEMString\0" + /* 02C2 */ "get_OffsetToStringData\0" + /* 02C3 */ "get_PMDesignator\0" + /* 02C4 */ "get_ParamName\0" + /* 02C5 */ "get_Parent\0" + /* 02C6 */ "get_Payload\0" + /* 02C7 */ "get_PayloadRaw\0" + /* 02C8 */ "get_Position\0" + /* 02C9 */ "get_PositiveSign\0" + /* 02CA */ "get_Priority\0" + /* 02CB */ "get_PropertyName\0" + /* 02CC */ "get_PropertyType\0" + /* 02CD */ "get_RFC1123Pattern\0" + /* 02CE */ "get_ReadTimeout\0" + /* 02CF */ "get_ResourceManager\0" + /* 02D0 */ "get_ReturnType\0" + /* 02D1 */ "get_Revision\0" + /* 02D2 */ "get_SKU\0" + /* 02D3 */ "get_Second\0" + /* 02D4 */ "get_Seconds\0" + /* 02D5 */ "get_Selector\0" + /* 02D6 */ "get_ShortDatePattern\0" + /* 02D7 */ "get_ShortTimePattern\0" + /* 02D8 */ "get_SortableDateTimePattern\0" + /* 02D9 */ "get_StackTrace\0" + /* 02DA */ "get_StandardName\0" + /* 02DB */ "get_Start\0" + /* 02DC */ "get_Subject\0" + /* 02DD */ "get_SyncRoot\0" + /* 02DE */ "get_Target\0" + /* 02DF */ "get_ThreadState\0" + /* 02E0 */ "get_Ticks\0" + /* 02E1 */ "get_TimeOfDay\0" + /* 02E2 */ "get_TimeSeparator\0" + /* 02E3 */ "get_Today\0" + /* 02E4 */ "get_UTF8\0" + /* 02E5 */ "get_UniversalSortableDateTimePattern\0" + /* 02E6 */ "get_UseRFC4648Encoding\0" + /* 02E7 */ "get_UtcNow\0" + /* 02E8 */ "get_Values\0" + /* 02E9 */ "get_Version\0" + /* 02EA */ "get_WriteTimeout\0" + /* 02EB */ "get_Year\0" + /* 02EC */ "get_YearMonthPattern\0" + /* 02ED */ "ht\0" + /* 02EE */ "index\0" + /* 02EF */ "key\0" + /* 02F0 */ "longDatePattern\0" + /* 02F1 */ "longTimePattern\0" + /* 02F2 */ "m_AppDomain\0" + /* 02F3 */ "m_ChunkChars\0" + /* 02F4 */ "m_ChunkLength\0" + /* 02F5 */ "m_ChunkOffset\0" + /* 02F6 */ "m_ChunkPrevious\0" + /* 02F7 */ "m_Delegate\0" + /* 02F8 */ "m_HResult\0" + /* 02F9 */ "m_Id\0" + /* 02FA */ "m_MaxCapacity\0" + /* 02FB */ "m_Priority\0" + /* 02FC */ "m_Thread\0" + /* 02FD */ "m_appDomain\0" + /* 02FE */ "m_assembly\0" + /* 02FF */ "m_baseAssembly\0" + /* 0300 */ "m_baseName\0" + /* 0301 */ "m_callback\0" + /* 0302 */ "m_certificate\0" + /* 0303 */ "m_cultureInfo\0" + /* 0304 */ "m_cultureName\0" + /* 0305 */ "m_data\0" + /* 0306 */ "m_delta\0" + /* 0307 */ "m_effectiveDate\0" + /* 0308 */ "m_end\0" + /* 0309 */ "m_expirationDate\0" + /* 030A */ "m_flags\0" + /* 030B */ "m_friendlyName\0" + /* 030C */ "m_handle\0" + /* 030D */ "m_hash\0" + /* 030E */ "m_id\0" + /* 030F */ "m_innerException\0" + /* 0310 */ "m_issuer\0" + /* 0311 */ "m_message\0" + /* 0312 */ "m_name\0" + /* 0313 */ "m_paramName\0" + /* 0314 */ "m_parent\0" + /* 0315 */ "m_password\0" + /* 0316 */ "m_payload\0" + /* 0317 */ "m_rand\0" + /* 0318 */ "m_refs\0" + /* 0319 */ "m_resourceFileId\0" + /* 031A */ "m_rm\0" + /* 031B */ "m_rmFallback\0" + /* 031C */ "m_selector\0" + /* 031D */ "m_seq\0" + /* 031E */ "m_sessionHandle\0" + /* 031F */ "m_size\0" + /* 0320 */ "m_source\0" + /* 0321 */ "m_stackTrace\0" + /* 0322 */ "m_start\0" + /* 0323 */ "m_state\0" + /* 0324 */ "m_subject\0" + /* 0325 */ "m_ticks\0" + /* 0326 */ "m_ticksOffset\0" + /* 0327 */ "m_timer\0" + /* 0328 */ "m_type\0" + /* 0329 */ "m_value\0" + /* 032A */ "manager\0" + /* 032B */ "monthDayPattern\0" + /* 032C */ "monthNames\0" + /* 032D */ "mscorlib\0" + /* 032E */ "negativeSign\0" + /* 032F */ "next\0" + /* 0330 */ "numInfo\0" + /* 0331 */ "numberDecimalSeparator\0" + /* 0332 */ "numberGroupSeparator\0" + /* 0333 */ "numberGroupSizes\0" + /* 0334 */ "op_Addition\0" + /* 0335 */ "op_Equality\0" + /* 0336 */ "op_GreaterThan\0" + /* 0337 */ "op_GreaterThanOrEqual\0" + /* 0338 */ "op_Inequality\0" + /* 0339 */ "op_LessThan\0" + /* 033A */ "op_LessThanOrEqual\0" + /* 033B */ "op_Subtraction\0" + /* 033C */ "op_UnaryNegation\0" + /* 033D */ "op_UnaryPlus\0" + /* 033E */ "pmDesignator\0" + /* 033F */ "positiveSign\0" + /* 0340 */ "propertyName\0" + /* 0341 */ "returnType\0" + /* 0342 */ "s_ewr\0" + /* 0343 */ "s_rgbBase64Decode\0" + /* 0344 */ "s_rgchBase64Encoding\0" + /* 0345 */ "s_rgchBase64EncodingDefault\0" + /* 0346 */ "s_rgchBase64EncodingRFC4648\0" + /* 0347 */ "set_Capacity\0" + /* 0348 */ "set_CurrentUICultureInternal\0" + /* 0349 */ "set_FrameworkDisplayName\0" + /* 034A */ "set_GrowthFactor\0" + /* 034B */ "set_Item\0" + /* 034C */ "set_Length\0" + /* 034D */ "set_MaxLoadFactor\0" + /* 034E */ "set_Position\0" + /* 034F */ "set_Priority\0" + /* 0350 */ "set_ReadTimeout\0" + /* 0351 */ "set_Target\0" + /* 0352 */ "set_UseRFC4648Encoding\0" + /* 0353 */ "set_WriteTimeout\0" + /* 0354 */ "shortDatePattern\0" + /* 0355 */ "shortTimePattern\0" + /* 0356 */ "temp\0" + /* 0357 */ "ticksAtOrigin\0" + /* 0358 */ "timeSeparator\0" + /* 0359 */ "value\0" + /* 035A */ "value__\0" + /* 035B */ "yearMonthPattern\0" +; + diff --git a/source/native/nf-interpreter/src/CLR/Core/Thread.cpp b/source/native/nf-interpreter/src/CLR/Core/Thread.cpp new file mode 100644 index 00000000..4fe5d90f --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Thread.cpp @@ -0,0 +1,1275 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +HRESULT CLR_RT_SubThread::CreateInstance( CLR_RT_Thread* th, CLR_RT_StackFrame* stack, int priority, CLR_RT_SubThread*& sthRef ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_SubThread* sth = EVENTCACHE_EXTRACT_NODE(g_CLR_RT_EventCache,CLR_RT_SubThread,DATATYPE_SUBTHREAD); CHECK_ALLOCATION(sth); + + sth->m_owningThread = th; // CLR_RT_Thread* m_owningThread; + sth->m_owningStackFrame = stack; // CLR_RT_StackFrame* m_owningStackFrame; + sth->m_lockRequestsCount = 0; // CLR_UINT32 m_lockRequestsCount; + // + sth->m_priority = priority; // int m_priority; + + sth->m_timeConstraint = TIMEOUT_INFINITE; // CLR_INT64 m_timeConstraint; + sth->m_status = 0; // CLR_UINT32 m_status; + + th->m_subThreads.LinkAtBack( sth ); + + NANOCLR_CLEANUP(); + + sthRef = sth; + + NANOCLR_CLEANUP_END(); +} + +void CLR_RT_SubThread::DestroyInstance( CLR_RT_Thread* th, CLR_RT_SubThread* sthBase, int flags ) +{ + NATIVE_PROFILE_CLR_CORE(); + // + // You cannot destroy a subthread without destroying all the children subthreads. + // + while(true) + { + CLR_RT_SubThread* sth = th->CurrentSubThread(); if(sth->Prev() == NULL) break; + + // + // Release all the frames for this subthread. + // + while(true) + { + CLR_RT_StackFrame* stack = th->CurrentFrame(); if(stack->Prev() == NULL) break; + + if(stack == sth->m_owningStackFrame) break; + + stack->Pop(); + } + + // + // Release all the locks for this subthread. + // + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Lock,lock,th->m_locks) + { + lock->DestroyOwner( sth ); + } + NANOCLR_FOREACH_NODE_END(); + + // + // Release all the lock requests. + // + g_CLR_RT_ExecutionEngine.DeleteLockRequests( NULL, sth ); + + if(sth == sthBase && (flags & CLR_RT_SubThread::MODE_IncludeSelf) == 0) break; + + g_CLR_RT_EventCache.Append_Node( sth ); + + if(sth == sthBase) break; + } +} + +bool CLR_RT_SubThread::ChangeLockRequestCount( int diff ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_Thread* th = m_owningThread; + + this->m_lockRequestsCount += diff; + th ->m_lockRequestsCount += diff; + + if(th->m_lockRequestsCount == 0) + { + th->Restart( false ); + + return true; + } + else + { + th->m_status = CLR_RT_Thread::TH_S_Waiting; + + return false; + } +} + +void CLR_RT_Thread::BringExecCounterToDate( int iGlobalExecutionCounter, int iDebitForEachRun ) +{ + (void)iDebitForEachRun; + + // Normally the condition is false. It becomes true if thread was out of execution for some time. + // The value of (ThreadPriority::System_Highest + 1) is 33. + // 33 for ThreadPriority::Highest gives up to 16 cycles to catch up. + // 33 for ThreadPriority::Lowest we provide only 1 cycle to catch up. + // If thread was sleeping for some time we forefeet the time it was sleeping and not updating execution counter. + if ( m_executionCounter - iGlobalExecutionCounter > (int)((1 << ThreadPriority::System_Highest) + 1) ) + { + m_executionCounter = iGlobalExecutionCounter + (int)((1 << ThreadPriority::System_Highest) + 1); + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +bool CLR_RT_Thread::IsFinalizerThread() +{ + NATIVE_PROFILE_CLR_CORE(); + return g_CLR_RT_ExecutionEngine.m_finalizerThread == this; +} + +bool CLR_RT_Thread::CanThreadBeReused() +{ + NATIVE_PROFILE_CLR_CORE(); + return (m_flags & CLR_RT_Thread::TH_F_System) && + (m_status == CLR_RT_Thread::TH_S_Terminated || m_status == CLR_RT_Thread::TH_S_Unstarted ); +} + +HRESULT CLR_RT_Thread::PushThreadProcDelegate( CLR_RT_HeapBlock_Delegate* pDelegate ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_MethodDef_Instance inst; + +#if defined(NANOCLR_APPDOMAINS) + CLR_RT_AppDomain* appDomainSav = g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( pDelegate->m_appDomain ); +#endif + + if(pDelegate == NULL || pDelegate->DataType() != DATATYPE_DELEGATE_HEAD || inst.InitializeFromIndex( pDelegate->DelegateFtn() ) == false) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + +#if defined(NANOCLR_APPDOMAINS) + + if(!pDelegate->m_appDomain->IsLoaded()) + { + if(!IsFinalizerThread()) + { + NANOCLR_SET_AND_LEAVE(CLR_E_APPDOMAIN_EXITED); + } + + m_flags |= CLR_RT_Thread::TH_F_ContainsDoomedAppDomain; + } +#endif + + this->m_dlg = pDelegate; + this->m_status = TH_S_Ready; + + NANOCLR_CHECK_HRESULT(CLR_RT_StackFrame::Push( this, inst, inst.m_target->numArgs )); + + if((inst.m_target->flags & CLR_RECORD_METHODDEF::MD_Static) == 0) + { + CLR_RT_StackFrame* stackTop = this->CurrentFrame(); + + stackTop->m_arguments[ 0 ].Assign( pDelegate->m_object ); + } + + g_CLR_RT_ExecutionEngine.PutInProperList( this ); + + NANOCLR_CLEANUP(); + +#if defined(NANOCLR_APPDOMAINS) + g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( appDomainSav ); +#endif + + NANOCLR_CLEANUP_END(); +} + +HRESULT CLR_RT_Thread::CreateInstance( int pid, int priority, CLR_RT_Thread*& th, CLR_UINT32 flags ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_SubThread* sth; + + //--// + + th = EVENTCACHE_EXTRACT_NODE(g_CLR_RT_EventCache,CLR_RT_Thread,DATATYPE_THREAD); CHECK_ALLOCATION(th); + + { + CLR_RT_ProtectFromGC gc( (void**)&th, CLR_RT_Thread::ProtectFromGCCallback ); + + th->Initialize(); + + th->m_pid = pid; // int m_pid; + th->m_status = TH_S_Unstarted; // CLR_UINT32 m_status; + th->m_flags = flags; // CLR_UINT32 m_flags; + th->m_executionCounter = 0; // int m_executionCounter; + th->m_timeQuantumExpired = false; // bool m_timeQuantumExpired; + // + th->m_dlg = NULL; // CLR_RT_HeapBlock_Delegate* m_dlg; + th->m_currentException .SetObjectReference( NULL ); // CLR_RT_HeapBlock m_currentException; + // UnwindStack m_nestedExceptions[c_MaxStackUnwindDepth]; + th->m_nestedExceptionsPos = 0; // int m_nestedExceptionsPos; + + // + // //--// + // + th->m_terminationCallback = NULL; // ThreadTerminationCallback m_terminationCallback; + th->m_terminationParameter = NULL; // void* m_terminationParameter; + // + th->m_waitForEvents = 0; // CLR_UINT32 m_waitForEvents; + th->m_waitForEvents_Timeout = TIMEOUT_INFINITE; // CLR_INT64 m_waitForEvents_Timeout; + th->m_waitForEvents_IdleTimeWorkItem = TIMEOUT_ZERO; // CLR_INT64 m_waitForEvents_IdleTimeWorkItem; + // + th->m_locks .DblLinkedList_Initialize(); // CLR_RT_DblLinkedList m_locks; + th->m_lockRequestsCount = 0; // CLR_UINT32 m_lockRequestsCount; + th->m_waitForObject = NULL; + // + th->m_stackFrames .DblLinkedList_Initialize(); // CLR_RT_DblLinkedList m_stackFrames; + // + th->m_subThreads .DblLinkedList_Initialize(); // CLR_RT_DblLinkedList m_subThreads; + // + #if defined(ENABLE_NATIVE_PROFILER) + th->m_fNativeProfiled = false; + #endif + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + th->m_scratchPad = -1; // int m_scratchPad; + th->m_fHasJMCStepper = false; // bool m_fHasJMCStepper + + // For normal threads created in CLR m_realThread points to the thread object. + // If debugger creates managed thread for function evaluation, then m_realThread points to the thread that has focus in debugger + th->m_realThread = th; // CLR_RT_Thread* m_realThread +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + //--// + + NANOCLR_CHECK_HRESULT(CLR_RT_SubThread::CreateInstance( th, NULL, priority, sth )); + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(g_CLR_RT_ExecutionEngine.m_breakpointsNum) + { + // + // This needs to happen before the Push + // + g_CLR_RT_ExecutionEngine.Breakpoint_Thread_Created( th ); + } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_Thread::CreateInstance( int pid, CLR_RT_HeapBlock_Delegate* pDelegate, int priority, CLR_RT_Thread*& th, CLR_UINT32 flags ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_CHECK_HRESULT(CreateInstance( pid, priority, th, flags )); + + if(pDelegate) + { + NANOCLR_CHECK_HRESULT(th->PushThreadProcDelegate( pDelegate )); + } + + NANOCLR_NOCLEANUP(); +} + +void CLR_RT_Thread::DestroyInstance() +{ + NATIVE_PROFILE_CLR_CORE(); + DetachAll(); + + Passivate(); + + //Prevent ReleaseWhenDeadEx from keeping the thread alive + if(m_flags & CLR_RT_Thread::TH_F_System) + { + m_flags &= ~CLR_RT_Thread::TH_F_System; + OnThreadTerminated(); + } + + ReleaseWhenDeadEx(); +} + +bool CLR_RT_Thread::ReleaseWhenDeadEx() +{ + NATIVE_PROFILE_CLR_CORE(); + //maybe separate for shutdown.... + //These threads live forever?!!? + if(m_flags & CLR_RT_Thread::TH_F_System) return false; + + if(!IsReadyForRelease()) return false; + + if(this == g_CLR_RT_ExecutionEngine.m_finalizerThread) g_CLR_RT_ExecutionEngine.m_finalizerThread = NULL; + if(this == g_CLR_RT_ExecutionEngine.m_interruptThread) g_CLR_RT_ExecutionEngine.m_interruptThread = NULL; + if(this == g_CLR_RT_ExecutionEngine.m_timerThread ) g_CLR_RT_ExecutionEngine.m_timerThread = NULL; + if(this == g_CLR_RT_ExecutionEngine.m_cctorThread ) g_CLR_RT_ExecutionEngine.m_cctorThread = NULL; + + return ReleaseWhenDead(); +} + +//--// + +void CLR_RT_Thread::ProtectFromGCCallback( void* state ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_Thread* th = (CLR_RT_Thread*)state; + + g_CLR_RT_GarbageCollector.Thread_Mark( th ); +} + +//--// + +HRESULT CLR_RT_Thread::Suspend() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if((m_flags & CLR_RT_Thread::TH_F_Suspended) == 0 && m_status != CLR_RT_Thread::TH_S_Terminated) + { + m_flags |= CLR_RT_Thread::TH_F_Suspended; + + g_CLR_RT_ExecutionEngine.PutInProperList( this ); + } + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT CLR_RT_Thread::Resume() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if((m_flags & CLR_RT_Thread::TH_F_Suspended) != 0 && m_status != CLR_RT_Thread::TH_S_Terminated) + { + m_flags &= ~CLR_RT_Thread::TH_F_Suspended; + + g_CLR_RT_ExecutionEngine.PutInProperList( this ); + } + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT CLR_RT_Thread::Terminate() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + m_status = CLR_RT_Thread::TH_S_Terminated; + + //An exception is needed to ensure that StackFrame::Pop does not copy uninitialized data + //to callers evaluation stacks. This would likely be harmless, as the entire thread is about to be killed + //However, this is simply a safeguard to prevent possible problems if it ever happens that + //between the start and end of killing the thread, a GC gets run. + (void)Library_corlib_native_System_Exception::CreateInstance( m_currentException, g_CLR_RT_WellKnownTypes.m_ThreadAbortException, S_OK, CurrentFrame() ); + + g_CLR_RT_ExecutionEngine.PutInProperList( this ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT CLR_RT_Thread::Abort() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + // + // Only abort a non-terminated thread... + // + if(m_status != CLR_RT_Thread::TH_S_Terminated) + { + (void)Library_corlib_native_System_Exception::CreateInstance( m_currentException, g_CLR_RT_WellKnownTypes.m_ThreadAbortException, S_OK, CurrentFrame() ); + + m_flags |= CLR_RT_Thread::TH_F_Aborted; + + Restart( true ); + } + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +void CLR_RT_Thread::Restart( bool fDeleteEvent ) +{ + NATIVE_PROFILE_CLR_CORE(); + // + // Wake up and queue. + // + m_status = CLR_RT_Thread::TH_S_Ready; + + g_CLR_RT_ExecutionEngine.PutInProperList( this ); + + if(fDeleteEvent) + { + m_waitForEvents = 0; + m_waitForEvents_Timeout = TIMEOUT_INFINITE; + } +} + +void CLR_RT_Thread::OnThreadTerminated() +{ + NATIVE_PROFILE_CLR_CORE(); + SignalAll(); + + // + // Release all the subthreads. + // + CLR_RT_SubThread::DestroyInstance( this, NULL, 0 ); + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(g_CLR_RT_ExecutionEngine.m_breakpointsNum) + { + g_CLR_RT_ExecutionEngine.Breakpoint_Thread_Terminated( this ); + } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) +} + +void CLR_RT_Thread::Passivate() +{ + NATIVE_PROFILE_CLR_CORE(); + m_flags &= ~(CLR_RT_Thread::TH_F_Suspended | CLR_RT_Thread::TH_F_ContainsDoomedAppDomain | CLR_RT_Thread::TH_F_Aborted); + + g_CLR_RT_ExecutionEngine.m_threadsZombie.LinkAtFront( this ); + + m_waitForEvents = 0; + m_waitForEvents_Timeout = TIMEOUT_INFINITE; + + //--// + + if(m_waitForObject != NULL) + { + g_CLR_RT_EventCache.Append_Node( m_waitForObject ); + m_waitForObject = NULL; + } + + //--// + + if((m_flags & CLR_RT_Thread::TH_F_System) == 0) + { + m_status = CLR_RT_Thread::TH_S_Terminated; + OnThreadTerminated(); + } + else + { + m_status = CLR_RT_Thread::TH_S_Unstarted; + } + + m_currentException.SetObjectReference( NULL ); // Reset exception flag. + + // + // If the thread is associated with a timer, advance the state of the timer. + // + if(m_terminationCallback) + { + ThreadTerminationCallback terminationCallback = m_terminationCallback; m_terminationCallback = NULL; + + terminationCallback( m_terminationParameter ); + } + + if(m_status == CLR_RT_Thread::TH_S_Terminated || m_status == CLR_RT_Thread::TH_S_Unstarted) + { + //This is used by Static constructor thread. + m_dlg = NULL; + } + + ReleaseWhenDeadEx(); +} + +bool CLR_RT_Thread::CouldBeActivated() +{ + NATIVE_PROFILE_CLR_CORE(); + if(m_waitForEvents_Timeout != TIMEOUT_INFINITE) return true; + if(m_waitForEvents ) return true; + + return false; +} + +void CLR_RT_Thread::RecoverFromGC() +{ + NATIVE_PROFILE_CLR_CORE(); + CheckAll(); +} + +void CLR_RT_Thread::Relocate() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_dlg ); + + m_currentException.Relocate__HeapBlock(); + + for(int i=0; im_call ); CLR_Debug::Printf( " [IP: %04x]\r\n", (stack->m_IP - stack->m_IPstart) ); + } + NANOCLR_FOREACH_NODE_BACKWARD_END(); +} + +#endif + +//--// + +void CLR_RT_Thread::ProcessException_FilterPseudoFrameCopyVars(CLR_RT_StackFrame* to, CLR_RT_StackFrame* from) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_UINT8 numArgs = from->m_call.m_target->numArgs; + + if(numArgs) + { + memcpy( to->m_arguments, from->m_arguments, sizeof(CLR_RT_HeapBlock) * numArgs ); + } + + if(from->m_call.m_target->numLocals) + { + memcpy( to->m_locals, from->m_locals, sizeof(CLR_RT_HeapBlock) * from->m_call.m_target->numLocals ); + } +} + +HRESULT CLR_RT_Thread::ProcessException_EndFilter() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_StackFrame* stack = CurrentFrame(); + CLR_INT32 choice = stack->PopValue().NumericByRef().s4; + + + UnwindStack& us = m_nestedExceptions[ m_nestedExceptionsPos - 1 ]; + + ProcessException_FilterPseudoFrameCopyVars(us.m_handlerStack, stack); + + //Clear the stack variable so Pop doesn't remove us from the UnwindStack. + us.m_stack = NULL; + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + //We don't want to send any breakpoints until after we set the IP appropriately + bool fBreakpointsDisabledSav = CLR_EE_DBG_IS(BreakpointsDisabled); + CLR_EE_DBG_SET(BreakpointsDisabled); +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + stack->Pop(); + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(!fBreakpointsDisabledSav) + { + CLR_EE_DBG_CLR(BreakpointsDisabled); + } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + if(choice == 1) + { + //The filter signaled that it will handle this exception. Update the phase state + us.SetPhase(UnwindStack::p_2_RunningFinallys_0); +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + g_CLR_RT_ExecutionEngine.Breakpoint_Exception(us.m_handlerStack, CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_DEPTH_EXCEPTION_HANDLER_FOUND, us.m_handlerBlockStart); +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + } + else + { + //Store the IP so Phase1/FindEhBlock knows to start looking from the point of the filter we were executing. + us.m_ip = us.m_currentBlockStart; + } + + //Signal that this is a continuation of processing for the handler on top of the unwind stack. + us.m_flags |= UnwindStack::c_ContinueExceptionHandler; + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + //We must stop if we sent out a Catch Handler found message. + if(CLR_EE_DBG_IS( Stopped )) + { //If the debugger stopped because of the messages we sent, then we should break out of Execute_IL, drop down, + //and wait for the debugger to continue. + m_currentException.SetObjectReference(us.m_exception); + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + (void)ProcessException(); + + + // Swap results around. ProcessException must return a success code in Thread::Execute and set m_currentException to continue processing. + // Execute_IL must get a FAILED hr in order to break outside of the execution loop. + if(m_currentException.Dereference() == NULL) + { + //Return S_OK because exception handling is complete or handling is in-flight and needs to execute IL to continue. + NANOCLR_SET_AND_LEAVE(S_OK); + } + else + { + //Return PROCESS_EXCEPTION to break out of the IL loop to rerun ProcessException and/or abort from an unhandled exception + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_Thread::ProcessException_EndFinally() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_StackFrame* stack = CurrentFrame(); + UnwindStack& us = m_nestedExceptions[ m_nestedExceptionsPos - 1 ]; + + if(us.m_ip) + { + CLR_PMETADATA ipLeave = us.m_ip; + CLR_RT_ExceptionHandler eh; + + if(FindEhBlock( stack, stack->m_IP-1, ipLeave, eh, true )) + { + us.m_stack = stack; + us.m_exception = NULL; + us.m_ip = ipLeave; + us.m_currentBlockStart = eh.m_handlerStart; + us.m_currentBlockEnd = eh.m_handlerEnd; + //Leave is not valid to leave a finally block, and is the only thing that leaves m_ip set when executing IL. + //Therefore if we're here then we are not interfering with an unhandled exception and flags can be safely set. + us.SetPhase( UnwindStack::p_4_NormalCleanup ); + stack->m_IP = eh.m_handlerStart ; + } + else + { //We're truely done with finally's for now. Pop off the handler + m_nestedExceptionsPos--; + stack->m_IP = ipLeave; + } + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(stack->m_flags & CLR_RT_StackFrame::c_HasBreakpoint) + { + g_CLR_RT_ExecutionEngine.Breakpoint_StackFrame_Step( stack, stack->m_IP ); + } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + NANOCLR_SET_AND_LEAVE(S_OK); + } + else if(us.m_exception) + { + //This finally block was executed because an exception was thrown inside its protected block. + //Signal that this is a continuation of an already existing EH process. + us.m_flags |= UnwindStack::c_ContinueExceptionHandler; + + (void)ProcessException(); + //Similar to EndFilter, we need to swap the return codes around. Thread::Execute needs a success code or the thread will be aborted. + //ExecuteIL needs a failure code or we'll continue to execute IL when we possibly shouldn't. + if (m_currentException.Dereference() == NULL) + { + //Return S_OK because exception handling is complete or handling is in-flight and needs to execute IL to continue. + NANOCLR_SET_AND_LEAVE(S_OK); + } + else + { + //Return PROCESS_EXCEPTION to break out of the IL loop to rerun ProcessException and/or abort from an unhandled exception + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_Thread::ProcessException_Phase1() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + // Load the UnwindStack entry to process, as created/loaded by ProcessException + UnwindStack& us = m_nestedExceptions[ m_nestedExceptionsPos - 1 ]; + + CLR_RT_ExceptionHandler eh; + + // If we were executing a filter that returned false, there's not much point checking the stack frames above the point of the filter. + // Try to resume from the frame of the last filter executed. + CLR_RT_StackFrame* stack = us.m_handlerStack; + +#ifndef CLR_NO_IL_INLINE + CLR_RT_InlineFrame tmpInline; + tmpInline.m_IP = NULL; +#endif + + // If this is the first pass through _Phase1 then start at the top. + if(!stack) { stack = CurrentFrame(); } + + //Search for a willing catch handler. + while(stack->Caller() != NULL) + { +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(g_CLR_RT_ExecutionEngine.m_breakpointsNum && us.GetPhase() < UnwindStack::p_1_SearchingForHandler_2_SentUsersChance && stack->m_IP) + { //We have a debugger attached and we need to send some messages before we start searching. + //These messages should only get sent when the search reaches managed code. Stack::Push sets m_IP to NULL for native code, + //so therefore we need IP to be non-NULL + + us.m_handlerStack = stack; + + if(us.GetPhase() < UnwindStack::p_1_SearchingForHandler_1_SentFirstChance) + { + g_CLR_RT_ExecutionEngine.Breakpoint_Exception( stack, CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_DEPTH_EXCEPTION_FIRST_CHANCE, NULL ); + us.SetPhase(UnwindStack::p_1_SearchingForHandler_1_SentFirstChance); + + //Break out here, because of synchronization issues (false positives) with JMC checking. + if(CLR_EE_DBG_IS( Stopped )) { goto ContinueAndExit; } + } + + //In order to send the User's first chance message, we have to know that we're in JMC + //Do we have thread synchronization issues here? The debugger is sending out 3 Not My Code messages for a function, + //presumably the one on the top of the stack, but when we execute this, we're reading true. + if(stack->m_call.DebuggingInfo().IsJMC()) + { + g_CLR_RT_ExecutionEngine.Breakpoint_Exception( stack, CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_DEPTH_EXCEPTION_USERS_CHANCE, NULL ); + us.SetPhase( UnwindStack::p_1_SearchingForHandler_2_SentUsersChance ); + if(CLR_EE_DBG_IS(Stopped)) { goto ContinueAndExit; } + } + } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + if(stack->m_call.m_target->flags & CLR_RECORD_METHODDEF::MD_HasExceptionHandlers) + { + CLR_PMETADATA ip; + if (us.m_ip) + { + ip = us.m_ip; //Use the IP set by endfilter + us.m_ip = NULL; //Reset to prevent catch block & PopEH issues via 'leave' or 'endfinally' + } + else + { + ip = stack->m_IP; //Normal case: use the IP where the exception was thrown. + } + + if(ip) // No IP? Either out of memory during allocation of stack frame or native method. + { + if(FindEhBlock( stack, ip, NULL, eh, false )) + { //There are two cases here: + //1. We found a catch block... in this case, we want to break out and go to phase 2. + //2. We found a filter... in this case, we want to duplicate the stack and execute the filter. + + //Store the handler block address and stack frame. + //It's needed in Phase2 for when finally's are finished and we execute the catch handler + us.m_handlerBlockStart = eh.m_handlerStart; + us.m_handlerBlockEnd = eh.m_handlerEnd; + us.m_handlerStack = stack; + +#ifndef CLR_NO_IL_INLINE + if(tmpInline.m_IP) + { + us.m_flags |= UnwindStack::c_MagicCatchForInline; + } +#endif + + if (eh.IsFilter()) + { + CLR_RT_StackFrame* newStack = NULL; + + //Store the IP range that we're currently executing so leave/PopEH doesn't accidentally pop the filter off. + us.m_currentBlockStart = eh.m_userFilterStart; + us.m_currentBlockEnd = eh.m_handlerStart; + + //Create a pseudo-frame at the top of the stack so the filter can call other functions. + CLR_UINT8 numArgs = stack->m_call.m_target->numArgs; + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + //We don't want to send any breakpoints until after we set the IP appropriately + bool fBreakpointsDisabledSav = CLR_EE_DBG_IS(BreakpointsDisabled); + CLR_EE_DBG_SET(BreakpointsDisabled); +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + hr = CLR_RT_StackFrame::Push( stack->m_owningThread, stack->m_call, numArgs ); + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(!fBreakpointsDisabledSav) + { + CLR_EE_DBG_CLR(BreakpointsDisabled); + } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + if(FAILED(hr)) + { //We probably ran out of memory. In either case, don't run this handler. + //Set the IP so we'll try the next catch block. + us.m_ip = us.m_currentBlockStart; + continue; + } + + //stack is the original filter stack frame; newStack is the new pseudoframe + newStack = CurrentFrame(); + newStack->m_flags |= CLR_RT_StackFrame::c_PseudoStackFrameForFilter; + us.m_stack = newStack; + + //Copy local variables and arguments so the filter has access to them. + if(numArgs) + { + memcpy( newStack->m_arguments, stack->m_arguments, sizeof(CLR_RT_HeapBlock) * numArgs ); + } + + if (stack->m_call.m_target->numLocals) + { + memcpy( newStack->m_locals, stack->m_locals, sizeof(CLR_RT_HeapBlock) * stack->m_call.m_target->numLocals ); + } + + newStack->PushValueAndAssign( m_currentException ); + + //Set the ip to the handler + newStack->m_IP = eh.m_userFilterStart; + + //We are willing to execute IL again so clear the m_currentException flag. + m_currentException.SetObjectReference( NULL ); + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + g_CLR_RT_ExecutionEngine.Breakpoint_StackFrame_Push( newStack, CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_DEPTH_STEP_INTERCEPT ); +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + //Return a success value to break out of ProcessException and to signal that execution of IL can continue. + NANOCLR_SET_AND_LEAVE(S_OK); + } + else + { //We found a normal Catch or CatchAll block. We are all set to proceed onto the Unwinding phase. + //Note that we found a catch handler so we don't look for it again for this exception. + us.SetPhase( UnwindStack::p_2_RunningFinallys_0 ); + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(g_CLR_RT_ExecutionEngine.m_breakpointsNum) + { + g_CLR_RT_ExecutionEngine.Breakpoint_Exception( stack, CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_DEPTH_EXCEPTION_HANDLER_FOUND, eh.m_handlerStart ); + if(CLR_EE_DBG_IS(Stopped)) { goto ContinueAndExit; } + } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + //We want to continue running EH "goo" code so leave m_currentException set and return PROCESS_EXCEPTION + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } + } + } + } + + //We didn't find a catch block at this level... + //Check to see if we trickled up to a pseudoStack frame that we created to execute a handler + //Both of these shouldn't be set at once because of the two-pass handling mechanism. + if (stack->m_flags & CLR_RT_StackFrame::c_AppDomainTransition) + { + us.m_handlerStack = NULL; + us.SetPhase(UnwindStack::p_2_RunningFinallys_0); + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(g_CLR_RT_ExecutionEngine.m_breakpointsNum) + { + //Send the IP offset -1 for a catch handler in the case of an appdomain transition to mimic the desktop. + g_CLR_RT_ExecutionEngine.Breakpoint_Exception( stack, CLR_DBG_Commands::Debugging_Execution_BreakpointDef::c_DEPTH_EXCEPTION_HANDLER_FOUND, stack->m_IPstart - 1 ); + if(CLR_EE_DBG_IS(Stopped)) { goto ContinueAndExit; } + } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } + if (stack->m_flags & CLR_RT_StackFrame::c_PseudoStackFrameForFilter) + { + us.m_handlerStack = NULL; + us.SetPhase( UnwindStack::p_2_RunningFinallys_0 ); + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } + +#ifndef CLR_NO_IL_INLINE + if(stack->m_inlineFrame != NULL && tmpInline.m_IP == NULL) + { + stack->SaveStack(tmpInline); + stack->RestoreFromInlineStack(); + } + else + { + if(tmpInline.m_IP) + { + stack->RestoreStack(tmpInline); + tmpInline.m_IP = NULL; + } +#else + { +#endif + + stack = stack->Caller(); + } + } + + us.m_handlerStack = NULL; + us.SetPhase(UnwindStack::p_2_RunningFinallys_0); + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(g_CLR_RT_ExecutionEngine.m_breakpointsNum) + { + g_CLR_RT_ExecutionEngine.Breakpoint_Exception_Uncaught( this ); + if(CLR_EE_DBG_IS(Stopped)) { goto ContinueAndExit; } + } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + //We want to continue running EH "goo" code so leave m_currentException set and return PROCESS_EXCEPTION + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) +ContinueAndExit: +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + //There are multiple cases where we want to break out of this function, send debug messages, and then resume exactly where we were. + //All of those cases jump to here. + //However, there are cases where we may be stopped but we don't want to set this flag (i.e. pushing on a filter and completing a stepper) + //where we do not want to set this flag, so it cannot be in nanoCLR_Cleanup. + us.m_flags |= UnwindStack::c_ContinueExceptionHandler; + NANOCLR_SET_AND_LEAVE(S_OK); + + NANOCLR_CLEANUP(); + +#ifndef CLR_NO_IL_INLINE + if(tmpInline.m_IP) + { + stack->RestoreStack(tmpInline); + } +#endif + + NANOCLR_CLEANUP_END(); +} + +HRESULT CLR_RT_Thread::ProcessException_Phase2() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + /* + * Start running through the stack frames, running all finally handlers and popping them off until + * we hit our target catch handler, if any. + */ + + UnwindStack& us = m_nestedExceptions[ m_nestedExceptionsPos - 1 ]; + + CLR_RT_StackFrame* iterStack = CurrentFrame(); + + CLR_RT_ExceptionHandler eh; + + //Unwind the stack, running finally's as we go + while (iterStack->Caller() != NULL) + { +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if (g_CLR_RT_ExecutionEngine.m_breakpointsNum && iterStack == us.m_handlerStack && (us.m_flags & UnwindStack::c_MagicCatchForInteceptedException) != 0) + { + //We've reached the frame we want to "handle" this exception. However, since the handler doesn't really exist, we want to remove the UnwindStack entry. + m_nestedExceptionsPos--; + iterStack->ResetStack(); + + //We are willing to execute IL again so clear the m_currentException flag. + m_currentException.SetObjectReference( NULL ); + + //CPDE better reset the IP, or there are going to be issues. + iterStack->m_flags |= CLR_RT_StackFrame::c_InvalidIP; + + //Send the message to the debugger. + g_CLR_RT_ExecutionEngine.Breakpoint_Exception_Intercepted( iterStack ); + + //Return a success value to break out of ProcessException and to signal that execution of IL can continue. + NANOCLR_SET_AND_LEAVE(S_OK); + } + else +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(iterStack->m_call.m_target->flags & CLR_RECORD_METHODDEF::MD_HasExceptionHandlers) + { + if(iterStack->m_IP) // No IP? Either out of memory during allocation of iterStack frame or native method. + { + //handlerBlockStart is used to not execute finally's who's protected blocks contain the handler itself. + //NULL is used when we're not in the handler stack frame to make it work in the case of recursive functions with filtered handlers. + if(FindEhBlock( iterStack, iterStack->m_IP, (us.m_handlerStack == iterStack)? us.m_handlerBlockStart : NULL, eh, true )) + { + //We have a finally block to process + + us.m_stack = iterStack; + us.m_ip = NULL; + us.m_currentBlockStart = eh.m_handlerStart; + us.m_currentBlockEnd = eh.m_handlerEnd; + us.SetPhase(UnwindStack::p_2_RunningFinallys_0); + + m_currentException.SetObjectReference( NULL ); // Reset exception flag. + + iterStack->ResetStack(); + iterStack->m_IP = eh.m_handlerStart; + iterStack->m_flags &= ~CLR_RT_StackFrame::c_InvalidIP; + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) +#ifndef CLR_NO_IL_INLINE + if(iterStack->m_inlineFrame == NULL) +#endif + { + g_CLR_RT_ExecutionEngine.Breakpoint_StackFrame_Pop( iterStack, true ); + } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + NANOCLR_SET_AND_LEAVE(S_OK); + } + + if (iterStack == us.m_handlerStack) + { +#ifndef CLR_NO_IL_INLINE + if(iterStack->m_inlineFrame == NULL || 0 == (us.m_flags & UnwindStack::c_MagicCatchForInline)) +#endif + { + //We've popped off all stack frames above the target. + //Now we should run the exception handler. + + //Store the range of the block and the stack frame we're executing for PopEH + us.m_currentBlockStart = us.m_handlerBlockStart; + us.m_currentBlockEnd = us.m_handlerBlockEnd; + us.m_stack = us.m_handlerStack; + us.SetPhase( UnwindStack::p_3_RunningHandler ); + + //Set the IP and push the exception object on the stack. + iterStack->m_IP = us.m_handlerBlockStart; + iterStack->m_flags &= ~CLR_RT_StackFrame::c_InvalidIP; + + iterStack->ResetStack(); + iterStack->PushValue().SetObjectReference( us.m_exception ); + + //We are willing to execute IL again so clear the m_currentException flag. + m_currentException.SetObjectReference( NULL ); + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) +#ifndef CLR_NO_IL_INLINE + if(iterStack->m_inlineFrame == NULL) +#endif + { + g_CLR_RT_ExecutionEngine.Breakpoint_StackFrame_Pop( iterStack, true ); + } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + //Return a success value to break out of ProcessException and to signal that execution of IL can continue. + NANOCLR_SET_AND_LEAVE(S_OK); + } + } + } + } + + //We didn't find a finally block at this level... + //Check to see if we trickled up to a pseudoiterStack frame that we created to execute a filter handler: + if (iterStack->m_flags & CLR_RT_StackFrame::c_PseudoStackFrameForFilter) + { + //An exception was thrown while executing a filter block. + //The CLR should swallow the current exception, perform some filter-cleanup, act as if the filter returned false and + //continue looking for a handler for the old exception + m_nestedExceptionsPos--; + + UnwindStack& us = m_nestedExceptions[ m_nestedExceptionsPos - 1 ]; + + //Since there are no applicable handlers for this IP inside this filter block, and all finally's nested below the + //filter have executed, we should pop off our pseudoframe and try to find another catch block. + + //Copy the arguments and locals back to the original stack frame. + ProcessException_FilterPseudoFrameCopyVars( us.m_handlerStack, iterStack ); + + //Set IP so we can resume looking for the next filter. + us.m_ip = us.m_currentBlockStart; + + us.m_stack = NULL; //Prevent Pop from taking this handler off the stack. + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + //We don't want to send any breakpoints until after we set the IP appropriately + bool fBreakpointsDisabledSav = CLR_EE_DBG_IS(BreakpointsDisabled); + CLR_EE_DBG_SET(BreakpointsDisabled); +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + iterStack->Pop(); //No finally's for the current ip in this method, pop to the next. + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(!fBreakpointsDisabledSav) + { + CLR_EE_DBG_CLR(BreakpointsDisabled); + } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + m_currentException.SetObjectReference( us.m_exception ); //Drop current exception, use old one. + + //Set the continue flag, and leave with S_OK to loop around and get Phase1 called again via ProcessException + us.m_flags |= UnwindStack::c_ContinueExceptionHandler; + + //We are not ready to execute IL yet so do NOT clear m_currentException flag. + //There still remains hope for this thread so return S_OK so ProcessException can get called again via Thread::Execute + NANOCLR_SET_AND_LEAVE(S_OK); + } + +#if defined(NANOCLR_APPDOMAINS) + if(iterStack->m_flags & CLR_RT_StackFrame::c_AppDomainTransition) + { + //If we hit an AppDomain transition and haven't handled the exception, then a special case occurs. + //Exception handling stops at this point and the whole process needs to start over in the caller's AppDomain. + //We need to pop the handler off the unwind stack, pop the current stack frame, and then proceed to Phase1. + m_nestedExceptionsPos--; //Take off the pseudo-handler + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + bool fBreakpointsDisabledSav = CLR_EE_DBG_IS(BreakpointsDisabled); + CLR_EE_DBG_SET(BreakpointsDisabled); +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + +#ifndef CLR_NO_IL_INLINE + if(iterStack->m_inlineFrame) + { + iterStack->PopInline(); + } + else +#endif + { + iterStack->Pop(); //No finally's for the current ip in this method, pop to the next. + } + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(!fBreakpointsDisabledSav) + { + CLR_EE_DBG_CLR(BreakpointsDisabled); + } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + //We are not ready to execute IL yet so do NOT clear m_currentException flag. + //There still remains hope for this thread so return S_OK so ProcessException can get called again via Thread::Execute + NANOCLR_SET_AND_LEAVE(S_OK); + } +#endif + + us.m_stack = NULL; //Don't pop off the handler when we pop this stack frame + + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + //We don't want to send any breakpoints until after we set the IP appropriately + bool fBreakpointsDisabledSav = CLR_EE_DBG_IS(BreakpointsDisabled); + CLR_EE_DBG_SET(BreakpointsDisabled); +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + +#ifndef CLR_NO_IL_INLINE + if(iterStack->m_inlineFrame) + { + iterStack->PopInline(); + } + else +#endif + { + iterStack->Pop(); //No finally's for the current ip in this method, pop to the next. + } + iterStack = CurrentFrame(); + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + if(!fBreakpointsDisabledSav) + { + CLR_EE_DBG_CLR(BreakpointsDisabled); + } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + } + + //If we reached this point, we've unwound the entire thread and have an unhandled exception. + m_nestedExceptionsPos = 0; //We have an unhandled exception, we might as well clean the unwind stack. + + //At this point, no hope remains. + //m_currentException is still set, but we return PROCESS_EXCEPTION signalling that there is no hope for the thread, + //which causes Thread::Execute to terminate it. +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) +#if !defined(BUILD_RTM) + //special case thread abort exception + if((this->m_flags & CLR_RT_Thread::TH_F_Aborted) == 0) + { + CLR_Debug::Printf(" Uncaught exception \r\n" ); + //Perhaps some stronger notification is needed. Consider CLR 2.0's fail-fast work + //We could kill the application, and perhaps even store relevant data to dump to the user + //when they connect to the PC. Save the state so the debug API for the uncaught exception could be + //retrieved? + } +#endif //!BUILD_RTM +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_Thread::ProcessException() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + CLR_RT_StackFrame* stack = CurrentFrame(); + UnwindStack* us = NULL; + + // If the exception was thrown in the middle of an IL instruction, + // back up the pointer to point to the executing instruction, not the next one. + // Not an assert because the exception can be thrown by a native method. + if(stack->m_flags & CLR_RT_StackFrame::c_ExecutingIL) + { + stack->m_IP--; + stack->m_flags &= ~CLR_RT_StackFrame::c_ExecutingIL; + stack->m_flags |= CLR_RT_StackFrame::c_InvalidIP; + } + + // If we are supposed to continue with the old exception handler, then pull the state from it rather than create a new exception. + if (m_nestedExceptionsPos) + { + us = &m_nestedExceptions[ m_nestedExceptionsPos - 1 ]; + if (us->m_flags & UnwindStack::c_ContinueExceptionHandler) + { + //Reset the flag so we don't get false positives from new exceptions + us->m_flags &= ~UnwindStack::c_ContinueExceptionHandler; + m_currentException.SetObjectReference( us->m_exception ); + } + else + { + //Signal that we need a new handler pushed on the stack. + us = NULL; + } + } + + if (us == NULL) + { + //Push a new handler on the unwind stack that will last until its handler gets executed or + //something out-of-band forces the stack frame to get popped. + us = PushEH(); + + //decent failure case is currently not implemented + //a. Clearing the unwind stack and throwing a new exception is just asking for undefined behavior if this exception is caught + //and the IP in stack frames somewhere below are in a finally due to an exception that hasn't yet ran a catch block and + //endfinally gets executed. Execution would continue, thinking that nothing was wrong... a guranteed way to create hard-to-find bugs. + + //b. We could treat it as an unhandled exception, which would terminate the thread. It would be annoying, but it wouldn't lead to + //unexpected code execution leading to potentially more exceptions. + + //c. We could forcibly pop stack frames until there is room on the unwind stack and then throw a stack overflow exception. + //It gives a program a chance to recover, especially for 'always-on' type devices that are inconvenient for the user to perform a cold-boot. + //At any restartable point in the program, there could be a try { } catch-all { } block inside a loop, causing the app to immediately restart + //after an error that would normally terminate the thread. + + //A similar setup would be needed for leave, involving goto Execute_Restart to compensate for possible stack frame changes. Perhaps it could be + //implemented directly in PushEh to reduce common code. + + us->m_exception = m_currentException.Dereference(); + us->m_stack = stack; + us->m_flags = UnwindStack::p_1_SearchingForHandler_0; + } + + if (us->GetPhase() <= UnwindStack::p_1_SearchingForHandler_2_SentUsersChance) + { + NANOCLR_EXIT_ON_SUCCESS(ProcessException_Phase1()); // Leave if we're executing a filter. + } + + NANOCLR_SET_AND_LEAVE(ProcessException_Phase2()); //Leave if we're executing a finally or the catch block, or have an unhandled exception + + NANOCLR_NOCLEANUP(); +} + diff --git a/source/native/nf-interpreter/src/CLR/Core/TypeSystem.cpp b/source/native/nf-interpreter/src/CLR/Core/TypeSystem.cpp new file mode 100644 index 00000000..59a07629 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/TypeSystem.cpp @@ -0,0 +1,4420 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "stdafx.h" + +#include "Core.h" +#include "corhdr_private.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#define ITERATE_THROUGH_RECORDS(assm,i,tblName,tblNameUC) \ + const CLR_RECORD_##tblNameUC* src = (const CLR_RECORD_##tblNameUC*)assm->GetTable( TBL_##tblName );\ + CLR_RT_##tblName##_CrossReference* dst = assm->m_pCrossReference_##tblName;\ + for(i=0; im_pTablesSize[TBL_##tblName]; i++, src++, dst++) + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#if defined(_WIN32) +#define NANOCLR_TRACE_DEFAULT(win,arm) (win) +#else +#define NANOCLR_TRACE_DEFAULT(win,arm) (arm) +#endif + +#if defined(NANOCLR_TRACE_ERRORS) +int s_CLR_RT_fTrace_Errors = NANOCLR_TRACE_DEFAULT(c_CLR_RT_Trace_Info,c_CLR_RT_Trace_Info); +#endif + +#if defined(NANOCLR_TRACE_EXCEPTIONS) +int s_CLR_RT_fTrace_Exceptions = NANOCLR_TRACE_DEFAULT(c_CLR_RT_Trace_Info,c_CLR_RT_Trace_Info); +#endif + +#if defined(NANOCLR_TRACE_INSTRUCTIONS) +int s_CLR_RT_fTrace_Instructions = NANOCLR_TRACE_DEFAULT(c_CLR_RT_Trace_None,c_CLR_RT_Trace_None); +#endif + +#if defined(NANOCLR_GC_VERBOSE) +int s_CLR_RT_fTrace_Memory = NANOCLR_TRACE_DEFAULT(c_CLR_RT_Trace_None,c_CLR_RT_Trace_None); +#endif + +#if defined(NANOCLR_TRACE_MEMORY_STATS) +int s_CLR_RT_fTrace_MemoryStats = NANOCLR_TRACE_DEFAULT(c_CLR_RT_Trace_Info,c_CLR_RT_Trace_Info); +#endif + +#if defined(NANOCLR_GC_VERBOSE) +int s_CLR_RT_fTrace_GC = NANOCLR_TRACE_DEFAULT(c_CLR_RT_Trace_None,c_CLR_RT_Trace_None); +#endif + +#if defined(WIN32) +int s_CLR_RT_fTrace_SimulateSpeed = NANOCLR_TRACE_DEFAULT(c_CLR_RT_Trace_Info,c_CLR_RT_Trace_None); +#endif + +#if !defined(BUILD_RTM) +int s_CLR_RT_fTrace_AssemblyOverhead = NANOCLR_TRACE_DEFAULT(c_CLR_RT_Trace_Info,c_CLR_RT_Trace_Info); +#endif + +#if defined(WIN32) +int s_CLR_RT_fTrace_StopOnFAILED = NANOCLR_TRACE_DEFAULT(c_CLR_RT_Trace_None,c_CLR_RT_Trace_None); +#endif + +#if defined(WIN32) +int s_CLR_RT_fTrace_ARM_Execution = 0; + +int s_CLR_RT_fTrace_RedirectLinesPerFile; +std::wstring s_CLR_RT_fTrace_RedirectOutput; +std::wstring s_CLR_RT_fTrace_RedirectCallChain; + +std::wstring s_CLR_RT_fTrace_HeapDump_FilePrefix; +bool s_CLR_RT_fTrace_HeapDump_IncludeCreators = false; + +bool s_CLR_RT_fTimeWarp = false; +#endif + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +void CLR_RT_ReflectionDef_Index::Clear() +{ + NATIVE_PROFILE_CLR_CORE(); + m_kind = REFLECTION_INVALID; + m_levels = 0; + m_data.m_raw = 0; +} + +CLR_UINT32 CLR_RT_ReflectionDef_Index::GetTypeHash() const +{ + NATIVE_PROFILE_CLR_CORE(); + switch(m_kind) + { + case REFLECTION_TYPE: + { + CLR_RT_TypeDef_Instance inst; + + if(m_levels != 0) return 0; + + if(!inst.InitializeFromIndex( m_data.m_type )) return 0; + + return inst.CrossReference().m_hash; + } + + case REFLECTION_TYPE_DELAYED: + return m_data.m_raw; + } + + return 0; +} + +void CLR_RT_ReflectionDef_Index::InitializeFromHash( CLR_UINT32 hash ) +{ + NATIVE_PROFILE_CLR_CORE(); + m_kind = REFLECTION_TYPE_DELAYED; + m_levels = 0; + m_data.m_raw = hash; +} + +CLR_UINT64 CLR_RT_ReflectionDef_Index::GetRawData() const +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_UINT64 data; + _ASSERTE(sizeof(data) == sizeof(*this)); + + memcpy( &data, this, sizeof(data) ); + + return data; +} + +void CLR_RT_ReflectionDef_Index::SetRawData( CLR_UINT64 data ) +{ + NATIVE_PROFILE_CLR_CORE(); + _ASSERTE(sizeof(data) == sizeof(*this)); + + memcpy( this, &data, sizeof(data) ); +} + +bool CLR_RT_ReflectionDef_Index::Convert( CLR_RT_HeapBlock& ref, CLR_RT_Assembly_Instance& inst ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(ref.DataType() == DATATYPE_REFLECTION) + { + return inst.InitializeFromIndex( ref.ReflectionDataConst().m_data.m_assm ); + } + + return false; +} + +bool CLR_RT_ReflectionDef_Index::Convert( CLR_RT_HeapBlock& ref, CLR_RT_TypeDef_Instance& inst, CLR_UINT32* levels ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(ref.DataType() == DATATYPE_REFLECTION) + { + return inst.InitializeFromReflection( ref.ReflectionDataConst(), levels ); + } + + return false; +} + +bool CLR_RT_ReflectionDef_Index::Convert( CLR_RT_HeapBlock& ref, CLR_RT_MethodDef_Instance& inst ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(ref.DataType() == DATATYPE_REFLECTION) + { + switch(ref.ReflectionData().m_kind) + { + case REFLECTION_CONSTRUCTOR: + case REFLECTION_METHOD: + return inst.InitializeFromIndex( ref.ReflectionDataConst().m_data.m_method ); + } + } + + return false; +} + +bool CLR_RT_ReflectionDef_Index::Convert( CLR_RT_HeapBlock& ref, CLR_RT_FieldDef_Instance& inst ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(ref.DataType() == DATATYPE_REFLECTION && ref.ReflectionData().m_kind == REFLECTION_FIELD) + { + return inst.InitializeFromIndex( ref.ReflectionDataConst().m_data.m_field ); + } + + return false; +} + +bool CLR_RT_ReflectionDef_Index::Convert( CLR_RT_HeapBlock& ref, CLR_UINT32& hash ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(ref.DataType() != DATATYPE_REFLECTION) return false; + + hash = ref.ReflectionData().GetTypeHash(); + + return hash != 0; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +void CLR_RT_SignatureParser::Initialize_TypeSpec( CLR_RT_Assembly* assm, const CLR_RECORD_TYPESPEC* ts ) +{ + NATIVE_PROFILE_CLR_CORE(); + Initialize_TypeSpec( assm, assm->GetSignature( ts->sig ) ); +} + +void CLR_RT_SignatureParser::Initialize_TypeSpec( CLR_RT_Assembly* assm, CLR_PMETADATA ts ) +{ + NATIVE_PROFILE_CLR_CORE(); + m_assm = assm; + m_sig = ts; + + m_type = CLR_RT_SignatureParser::c_TypeSpec; + m_flags = 0; + m_count = 1; +} + +//--// + +void CLR_RT_SignatureParser::Initialize_Interfaces( CLR_RT_Assembly* assm, const CLR_RECORD_TYPEDEF* td ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(td->interfaces != CLR_EmptyIndex) + { + CLR_PMETADATA sig = assm->GetSignature( td->interfaces ); + + m_count = (*sig++); + m_sig = sig; + } + else + { + m_count = 0; + m_sig = NULL; + } + + m_type = CLR_RT_SignatureParser::c_Interfaces; + m_flags = 0; + + m_assm = assm; +} + +//--// + +void CLR_RT_SignatureParser::Initialize_FieldDef( CLR_RT_Assembly* assm, const CLR_RECORD_FIELDDEF* fd ) +{ + NATIVE_PROFILE_CLR_CORE(); + Initialize_FieldDef( assm, assm->GetSignature( fd->sig ) ); +} + +void CLR_RT_SignatureParser::Initialize_FieldDef( CLR_RT_Assembly* assm, CLR_PMETADATA fd ) +{ + NATIVE_PROFILE_CLR_CORE(); + m_type = CLR_RT_SignatureParser::c_Field; + m_flags = (*fd++); + m_count = 1; + + m_assm = assm; + m_sig = fd; +} + +//--// + +void CLR_RT_SignatureParser::Initialize_MethodSignature( CLR_RT_Assembly* assm, const CLR_RECORD_METHODDEF* md ) +{ + NATIVE_PROFILE_CLR_CORE(); + Initialize_MethodSignature( assm, assm->GetSignature( md->sig ) ); +} + +void CLR_RT_SignatureParser::Initialize_MethodSignature( CLR_RT_Assembly* assm, CLR_PMETADATA md ) +{ + NATIVE_PROFILE_CLR_CORE(); + m_type = CLR_RT_SignatureParser::c_Method; + m_flags = (*md++); + m_count = (*md++) + 1; + + m_assm = assm; + m_sig = md; +} + +//--// + +void CLR_RT_SignatureParser::Initialize_MethodLocals( CLR_RT_Assembly* assm, const CLR_RECORD_METHODDEF* md ) +{ + NATIVE_PROFILE_CLR_CORE(); + // + // WARNING!!! + // + // If you change this method, change "CLR_RT_ExecutionEngine::InitializeLocals" too. + // + + m_assm = assm; + m_sig = assm->GetSignature( md->locals ); + + m_type = CLR_RT_SignatureParser::c_Locals; + m_flags = 0; + m_count = md->numLocals; +} + +//--// + +void CLR_RT_SignatureParser::Initialize_Objects( CLR_RT_HeapBlock* lst, int count, bool fTypes ) +{ + NATIVE_PROFILE_CLR_CORE(); + m_lst = lst; + + m_type = CLR_RT_SignatureParser::c_Object; + m_flags = fTypes ? 1 : 0; + m_count = count; +} + +//--// + +HRESULT CLR_RT_SignatureParser::Advance( Element& res ) +{ + NATIVE_PROFILE_CLR_CORE(); + // + // WARNING!!! + // + // If you change this method, change "CLR_RT_ExecutionEngine::InitializeLocals" too. + // + + NANOCLR_HEADER(); + + _ASSERTE(m_count > 0); + + m_count--; + + res.m_fByRef = false; + res.m_levels = 0; + + switch(m_type) + { + case c_Interfaces: + { + CLR_RT_TypeDef_Instance cls; + + res.m_dt = DATATYPE_CLASS; + + if(cls.ResolveToken( CLR_TkFromStream( m_sig ), m_assm ) == false) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + res.m_cls = cls; + } + break; + + case c_Object: + { + CLR_RT_TypeDescriptor desc; + CLR_RT_HeapBlock* ptr = m_lst++; + + if(m_flags) + { + // Reflection types are now boxed, so unbox first + if(ptr->DataType() == DATATYPE_OBJECT) + { + ptr = ptr->Dereference(); + } + if(ptr->DataType() != DATATYPE_REFLECTION) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + NANOCLR_CHECK_HRESULT(desc.InitializeFromReflection( ptr->ReflectionDataConst() )); + } + else + { + switch(ptr->DataType()) + { + case DATATYPE_BYREF: + case DATATYPE_ARRAY_BYREF: + res.m_fByRef = true; + break; + + default: + // the remaining data types aren't to be handled + break; + } + + NANOCLR_CHECK_HRESULT(desc.InitializeFromObject( *ptr )); + } + + desc.m_handlerCls.InitializeFromIndex( desc.m_reflex.m_data.m_type ); + + res.m_levels = desc.m_reflex.m_levels; + res.m_dt = (CLR_DataType)desc.m_handlerCls.m_target->dataType; + res.m_cls = desc.m_reflex.m_data.m_type; + + // + // Special case for Object types. + // + if(res.m_cls.m_data == g_CLR_RT_WellKnownTypes.m_Object.m_data) + { + res.m_dt = DATATYPE_OBJECT; + } + } + break; + + default: + while(true) + { + res.m_dt = CLR_UncompressElementType( m_sig ); + + switch(res.m_dt) + { + case DATATYPE_BYREF: + if(res.m_fByRef) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + res.m_fByRef = true; + break; + + case DATATYPE_SZARRAY: + res.m_levels++; + break; + + case DATATYPE_CLASS : + case DATATYPE_VALUETYPE: + { + CLR_UINT32 tk = CLR_TkFromStream( m_sig ); + + if(CLR_TypeFromTk( tk ) == TBL_TypeSpec) + { + CLR_RT_SignatureParser sub; sub.Initialize_TypeSpec( m_assm, m_assm->GetTypeSpec( CLR_DataFromTk( tk ) ) ); + int extraLevels = res.m_levels; + + NANOCLR_CHECK_HRESULT(sub.Advance( res )); + + res.m_levels += extraLevels; + } + else + { + CLR_RT_TypeDef_Instance cls; + + if(cls.ResolveToken( tk, m_assm ) == false) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + res.m_cls = cls; + } + + NANOCLR_SET_AND_LEAVE(S_OK); + } + + case DATATYPE_OBJECT: + res.m_cls = g_CLR_RT_WellKnownTypes.m_Object; + + NANOCLR_SET_AND_LEAVE(S_OK); + + case DATATYPE_VOID: + res.m_cls = g_CLR_RT_WellKnownTypes.m_Void; + + NANOCLR_SET_AND_LEAVE(S_OK); + + default: + { + const CLR_RT_TypeDef_Index* cls = c_CLR_RT_DataTypeLookup[ res.m_dt ].m_cls; + + if(cls) + { + res.m_cls = *cls; + NANOCLR_SET_AND_LEAVE(S_OK); + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + } + } + } + break; + } + + NANOCLR_NOCLEANUP(); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +bool CLR_RT_Assembly_Instance::InitializeFromIndex( const CLR_RT_Assembly_Index& idx ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(NANOCLR_INDEX_IS_VALID(idx)) + { + m_data = idx.m_data; + m_assm = g_CLR_RT_TypeSystem.m_assemblies[ Assembly()-1 ]; + + return true; + } + + m_data = 0; + m_assm = NULL; + + return false; +} + +void CLR_RT_Assembly_Instance::Clear() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_Assembly_Index::Clear(); + + m_assm = NULL; +} + +////////////////////////////// + +bool CLR_RT_TypeSpec_Instance::InitializeFromIndex( const CLR_RT_TypeSpec_Index& idx ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(NANOCLR_INDEX_IS_VALID(idx)) + { + m_data = idx.m_data; + m_assm = g_CLR_RT_TypeSystem.m_assemblies[ Assembly()-1 ] ; + m_target = m_assm->GetSignature( m_assm->GetTypeSpec ( TypeSpec() )->sig ); + + return true; + } + + m_data = 0; + m_assm = NULL; + m_target = NULL; + + return false; +} + +void CLR_RT_TypeSpec_Instance::Clear() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_TypeSpec_Index::Clear(); + + m_assm = NULL; + m_target = NULL; +} + +bool CLR_RT_TypeSpec_Instance::ResolveToken( CLR_UINT32 tk, CLR_RT_Assembly* assm ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(assm && CLR_TypeFromTk( tk ) == TBL_TypeSpec) + { + CLR_UINT32 idx = CLR_DataFromTk( tk ); + + Set( assm->m_idx, idx ); + + m_assm = assm; + m_target = assm->GetSignature( assm->GetTypeSpec( idx )->sig ); + + return true; + } + + Clear(); + + return false; +} + +////////////////////////////// + +bool CLR_RT_TypeDef_Instance::InitializeFromReflection( const CLR_RT_ReflectionDef_Index& reflex, CLR_UINT32* levels ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_TypeDef_Index cls; + const CLR_RT_TypeDef_Index* ptr = NULL; + + if(levels) *levels = reflex.m_levels; + + switch(reflex.m_kind) + { + case REFLECTION_TYPE: + if(reflex.m_levels > 0 && levels == NULL) + { + ptr = &g_CLR_RT_WellKnownTypes.m_Array; + } + else + { + ptr = &reflex.m_data.m_type; + } + break; + + case REFLECTION_TYPE_DELAYED: + if(g_CLR_RT_TypeSystem.FindTypeDef( reflex.m_data.m_raw, cls )) + { + ptr = &cls; + } + break; + } + + return ptr ? InitializeFromIndex( *ptr ) : false; +} + +bool CLR_RT_TypeDef_Instance::InitializeFromIndex( const CLR_RT_TypeDef_Index& idx ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(NANOCLR_INDEX_IS_VALID(idx)) + { + m_data = idx.m_data; + m_assm = g_CLR_RT_TypeSystem.m_assemblies[ Assembly()-1 ]; + m_target = m_assm->GetTypeDef ( Type () ); + + return true; + } + + m_data = 0; + m_assm = NULL; + m_target = NULL; + + return false; +} + +bool CLR_RT_TypeDef_Instance::InitializeFromMethod( const CLR_RT_MethodDef_Instance& md ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(NANOCLR_INDEX_IS_VALID(md)) + { + CLR_IDX idxAssm = md.Assembly(); + CLR_IDX idxType = md.CrossReference().GetOwner(); + + Set( idxAssm, idxType ); + + m_assm = g_CLR_RT_TypeSystem.m_assemblies[ idxAssm-1 ]; + m_target = m_assm->GetTypeDef ( idxType ); + + return true; + } + + Clear(); + + return false; +} + +bool CLR_RT_TypeDef_Instance::InitializeFromField( const CLR_RT_FieldDef_Instance& fd ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(NANOCLR_INDEX_IS_VALID(fd)) + { + CLR_RT_Assembly* assm = fd.m_assm; + const CLR_RECORD_TYPEDEF* td = (const CLR_RECORD_TYPEDEF*)assm->GetTable( TBL_TypeDef ); + CLR_IDX idxField = fd.Field(); + int i = assm->m_pTablesSize[ TBL_TypeDef ]; + + if(fd.m_target->flags & CLR_RECORD_FIELDDEF::FD_Static) + { + for(;i; i--, td++) + { + if(td->sFields_First <= idxField && idxField < td->sFields_First + td->sFields_Num) + { + break; + } + } + } + else + { + for(;i; i--, td++) + { + if(td->iFields_First <= idxField && idxField < td->iFields_First + td->iFields_Num) + { + break; + } + } + } + + if(i) + { + CLR_IDX idxAssm = fd.Assembly(); + CLR_IDX idxType = assm->m_pTablesSize[ TBL_TypeDef ] - i; + + Set( idxAssm, idxType ); + + m_assm = g_CLR_RT_TypeSystem.m_assemblies[ idxAssm-1 ]; + m_target = m_assm->GetTypeDef ( idxType ); + + return true; + } + } + + Clear(); + + return false; +} + +bool CLR_RT_TypeDef_Instance::IsATypeHandler() +{ + NATIVE_PROFILE_CLR_CORE(); + return (m_data == g_CLR_RT_WellKnownTypes.m_Type.m_data || m_data == g_CLR_RT_WellKnownTypes.m_TypeStatic.m_data); +} + +void CLR_RT_TypeDef_Instance::Clear() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_TypeDef_Index::Clear(); + + m_assm = NULL; + m_target = NULL; +} + +bool CLR_RT_TypeDef_Instance::ResolveToken( CLR_UINT32 tk, CLR_RT_Assembly* assm ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(assm) + { + CLR_UINT32 idx = CLR_DataFromTk( tk ); + + switch( CLR_TypeFromTk( tk ) ) + { + case TBL_TypeRef: + m_data = assm->m_pCrossReference_TypeRef[ idx ].m_target.m_data; + m_assm = g_CLR_RT_TypeSystem.m_assemblies[ Assembly()-1 ]; + m_target = m_assm->GetTypeDef ( Type () ); + return true; + + case TBL_TypeDef: + Set( assm->m_idx, idx ); + + m_assm = assm; + m_target = assm->GetTypeDef( idx ); + return true; + + default: + // the remaining data types aren't to be handled + break; + } + } + + Clear(); + + return false; +} + +//--// + +bool CLR_RT_TypeDef_Instance::SwitchToParent() +{ + NATIVE_PROFILE_CLR_CORE(); + if(NANOCLR_INDEX_IS_VALID(*this)) + { + CLR_IDX extends = m_target->extends; + + if(extends != CLR_EmptyIndex) + { + CLR_RT_TypeDef_Index tmp; + const CLR_RT_TypeDef_Index* cls; + + if(extends & 0x8000) // TypeRef + { + cls = &m_assm->m_pCrossReference_TypeRef[ extends & 0x7FFF ].m_target; + } + else + { + tmp.Set( Assembly(), extends ); + + cls = &tmp; + } + + return InitializeFromIndex( *cls ); + } + } + + Clear(); + + return false; +} + +bool CLR_RT_TypeDef_Instance::HasFinalizer() const +{ + NATIVE_PROFILE_CLR_CORE(); + return NANOCLR_INDEX_IS_VALID(*this) && (CrossReference().m_flags & CLR_RT_TypeDef_CrossReference::TD_CR_HasFinalizer); +} + +////////////////////////////// + +bool CLR_RT_FieldDef_Instance::InitializeFromIndex( const CLR_RT_FieldDef_Index& idx ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(NANOCLR_INDEX_IS_VALID(idx)) + { + m_data = idx.m_data; + m_assm = g_CLR_RT_TypeSystem.m_assemblies[ Assembly()-1 ]; + m_target = m_assm->GetFieldDef ( Field () ); + + return true; + } + + m_data = 0; + m_assm = NULL; + m_target = NULL; + + return false; +} + +void CLR_RT_FieldDef_Instance::Clear() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_FieldDef_Index::Clear(); + + m_assm = NULL; + m_target = NULL; +} + +bool CLR_RT_FieldDef_Instance::ResolveToken( CLR_UINT32 tk, CLR_RT_Assembly* assm ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(assm) + { + CLR_UINT32 idx = CLR_DataFromTk( tk ); + + switch(CLR_TypeFromTk( tk )) + { + case TBL_FieldRef: + m_data = assm->m_pCrossReference_FieldRef[ idx ].m_target.m_data; + m_assm = g_CLR_RT_TypeSystem.m_assemblies[ Assembly()-1 ]; + m_target = m_assm->GetFieldDef ( Field () ); + return true; + + case TBL_FieldDef: + Set( assm->m_idx, idx ); + + m_assm = assm; + m_target = m_assm->GetFieldDef( idx ); + return true; + + default: + // the remaining data types aren't to be handled + break; + } + } + + Clear(); + + return false; +} + +////////////////////////////// + +bool CLR_RT_MethodDef_Instance::InitializeFromIndex( const CLR_RT_MethodDef_Index& idx ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(NANOCLR_INDEX_IS_VALID(idx)) + { + m_data = idx.m_data; + m_assm = g_CLR_RT_TypeSystem.m_assemblies[ Assembly()-1 ]; + m_target = m_assm->GetMethodDef ( Method () ); + + return true; + } + + m_data = 0; + m_assm = NULL; + m_target = NULL; + + return false; +} + +void CLR_RT_MethodDef_Instance::Clear() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_MethodDef_Index::Clear(); + + m_assm = NULL; + m_target = NULL; +} + +bool CLR_RT_MethodDef_Instance::ResolveToken( CLR_UINT32 tk, CLR_RT_Assembly* assm ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(assm) + { + CLR_UINT32 idx = CLR_DataFromTk( tk ); + + switch(CLR_TypeFromTk( tk )) + { + case TBL_MethodRef: + m_data = assm->m_pCrossReference_MethodRef[ idx ].m_target.m_data; + m_assm = g_CLR_RT_TypeSystem.m_assemblies[ Assembly()-1 ]; + m_target = m_assm->GetMethodDef ( Method () ); + return true; + + case TBL_MethodDef: + Set( assm->m_idx, idx ); + + m_assm = assm; + m_target = m_assm->GetMethodDef( idx ); + return true; + + default: + // the remaining data types aren't to be handled + break; + } + } + + Clear(); + + return false; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +void CLR_RT_TypeDescriptor::TypeDescriptor_Initialize() +{ + NATIVE_PROFILE_CLR_CORE(); + m_flags = 0; // CLR_UINT32 m_flags; + m_handlerCls.Clear(); // CLR_RT_TypeDef_Instance m_handlerCls; + // + m_reflex .Clear(); // CLR_RT_ReflectionDef_Index m_reflex; +} + +HRESULT CLR_RT_TypeDescriptor::InitializeFromDataType( CLR_DataType dt ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(dt >= DATATYPE_FIRST_INVALID) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + else + { + const CLR_RT_DataTypeLookup& dtl = c_CLR_RT_DataTypeLookup[ dt ]; + + m_flags = dtl.m_flags & CLR_RT_DataTypeLookup::c_SemanticMask2; + + if(dtl.m_cls) + { + if(m_handlerCls.InitializeFromIndex( *dtl.m_cls ) == false) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + m_reflex.m_kind = REFLECTION_TYPE; + m_reflex.m_levels = 0; + m_reflex.m_data.m_type = *dtl.m_cls; + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_TypeDescriptor::InitializeFromReflection( const CLR_RT_ReflectionDef_Index& reflex ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Instance inst; + CLR_UINT32 levels; + + if(inst.InitializeFromReflection( reflex, &levels ) == false) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + NANOCLR_CHECK_HRESULT(InitializeFromType( inst )); + + if(levels) + { + m_reflex.m_levels = levels; + + ConvertToArray(); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_TypeDescriptor::InitializeFromTypeSpec( const CLR_RT_TypeSpec_Index& sig ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_TypeSpec_Instance inst; + CLR_RT_SignatureParser parser; + + if(inst.InitializeFromIndex( sig ) == false) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + parser.Initialize_TypeSpec( inst.m_assm, inst.m_target ); + + NANOCLR_SET_AND_LEAVE(InitializeFromSignatureParser( parser )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_TypeDescriptor::InitializeFromType( const CLR_RT_TypeDef_Index& cls ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(m_handlerCls.InitializeFromIndex( cls ) == false) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + else + { + const CLR_RT_DataTypeLookup& dtl = c_CLR_RT_DataTypeLookup[ m_handlerCls.m_target->dataType ]; + + m_flags = dtl.m_flags & CLR_RT_DataTypeLookup::c_SemanticMask; + + m_reflex.m_kind = REFLECTION_TYPE; + m_reflex.m_levels = 0; + m_reflex.m_data.m_type = m_handlerCls; + + if(m_flags == CLR_RT_DataTypeLookup::c_Primitive) + { + if((m_handlerCls.m_target->flags & CLR_RECORD_TYPEDEF::TD_Semantics_Mask) == CLR_RECORD_TYPEDEF::TD_Semantics_Enum) + { + m_flags = CLR_RT_DataTypeLookup::c_Enum; + } + } + else + { + switch(m_handlerCls.m_target->flags & CLR_RECORD_TYPEDEF::TD_Semantics_Mask) + { + case CLR_RECORD_TYPEDEF::TD_Semantics_ValueType: m_flags = CLR_RT_DataTypeLookup::c_ValueType; break; + case CLR_RECORD_TYPEDEF::TD_Semantics_Class : m_flags = CLR_RT_DataTypeLookup::c_Class ; break; + case CLR_RECORD_TYPEDEF::TD_Semantics_Interface: m_flags = CLR_RT_DataTypeLookup::c_Interface; break; + case CLR_RECORD_TYPEDEF::TD_Semantics_Enum : m_flags = CLR_RT_DataTypeLookup::c_Enum ; break; + } + } + + if(m_handlerCls.m_data == g_CLR_RT_WellKnownTypes.m_Array.m_data) + { + m_flags |= CLR_RT_DataTypeLookup::c_Array; + } + + if(m_handlerCls.m_data == g_CLR_RT_WellKnownTypes.m_ArrayList.m_data) + { + m_flags |= CLR_RT_DataTypeLookup::c_ArrayList; + } + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_TypeDescriptor::InitializeFromFieldDefinition( const CLR_RT_FieldDef_Instance& fd ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_SignatureParser parser; parser.Initialize_FieldDef( fd.m_assm, fd.m_target ); + + NANOCLR_SET_AND_LEAVE(InitializeFromSignatureParser( parser )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_TypeDescriptor::InitializeFromSignatureParser( CLR_RT_SignatureParser& parser ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_SignatureParser::Element res; + + if(parser.Available() <= 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + } + + NANOCLR_CHECK_HRESULT(parser.Advance( res )); + + NANOCLR_CHECK_HRESULT(InitializeFromType( res.m_cls )); + + if(res.m_levels) + { + m_reflex.m_levels = res.m_levels; + + ConvertToArray(); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_TypeDescriptor::InitializeFromObject( const CLR_RT_HeapBlock& ref ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + const CLR_RT_HeapBlock* obj = &ref; + CLR_DataType dt; + + + while(true) + { + dt = (CLR_DataType)obj->DataType(); + + if(dt == DATATYPE_BYREF || + dt == DATATYPE_OBJECT ) + { + obj = obj->Dereference(); FAULT_ON_NULL(obj); + } +#if defined(NANOCLR_APPDOMAINS) + else if(dt == DATATYPE_TRANSPARENT_PROXY) + { + NANOCLR_CHECK_HRESULT(obj->TransparentProxyValidate()); + obj = obj->TransparentProxyDereference(); + } +#endif + else + { + break; + } + } + + { + const CLR_RT_TypeDef_Index* cls = NULL; + const CLR_RT_ReflectionDef_Index* reflex = NULL; + + switch(dt) + { + case DATATYPE_SZARRAY: + reflex = &obj->ReflectionDataConst(); + cls = &reflex->m_data.m_type; + break; + + case DATATYPE_VALUETYPE: + case DATATYPE_CLASS: + cls = &obj->ObjectCls(); + break; + + case DATATYPE_DELEGATE_HEAD: + { + CLR_RT_HeapBlock_Delegate* dlg = (CLR_RT_HeapBlock_Delegate*)obj; + + cls = NANOCLR_INDEX_IS_VALID(dlg->m_cls) ? &dlg->m_cls : &g_CLR_RT_WellKnownTypes.m_Delegate; + } + break; + + case DATATYPE_DELEGATELIST_HEAD: + { + CLR_RT_HeapBlock_Delegate_List* dlgLst = (CLR_RT_HeapBlock_Delegate_List*)obj; + + cls = NANOCLR_INDEX_IS_VALID(dlgLst->m_cls) ? &dlgLst->m_cls : &g_CLR_RT_WellKnownTypes.m_MulticastDelegate; + } + break; + + //--// + + case DATATYPE_WEAKCLASS: + { + cls = &g_CLR_RT_WellKnownTypes.m_WeakReference; + } + break; + + //--// + + case DATATYPE_REFLECTION: + reflex = &(obj->ReflectionDataConst()); + + switch(reflex->m_kind) + { + case REFLECTION_ASSEMBLY : cls = &g_CLR_RT_WellKnownTypes.m_Assembly ; break; + case REFLECTION_TYPE : cls = &g_CLR_RT_WellKnownTypes.m_Type ; break; + case REFLECTION_TYPE_DELAYED: cls = &g_CLR_RT_WellKnownTypes.m_Type ; break; + case REFLECTION_CONSTRUCTOR : cls = &g_CLR_RT_WellKnownTypes.m_ConstructorInfo; break; + case REFLECTION_METHOD : cls = &g_CLR_RT_WellKnownTypes.m_MethodInfo ; break; + case REFLECTION_FIELD : cls = &g_CLR_RT_WellKnownTypes.m_FieldInfo ; break; + } + + break; + + //--// + + case DATATYPE_ARRAY_BYREF: + { + CLR_RT_HeapBlock_Array* array = obj->Array(); FAULT_ON_NULL(array); + + if(array->m_fReference) + { + obj = (CLR_RT_HeapBlock*)array->GetElement( obj->ArrayIndex() ); + + NANOCLR_SET_AND_LEAVE(InitializeFromObject( *obj )); + } + + reflex = &array->ReflectionDataConst(); + cls = &reflex->m_data.m_type; + } + break; + + //--// + + default: + NANOCLR_SET_AND_LEAVE(InitializeFromDataType( dt )); + } + + if(cls) + { + NANOCLR_CHECK_HRESULT(InitializeFromType( *cls )); + } + + if(reflex) + { + m_reflex = *reflex; + } + + if(dt == DATATYPE_SZARRAY) + { + ConvertToArray(); + } + } + + NANOCLR_NOCLEANUP(); +} + +//////////////////////////////////////// + +void CLR_RT_TypeDescriptor::ConvertToArray() +{ + NATIVE_PROFILE_CLR_CORE(); + m_flags &= CLR_RT_DataTypeLookup::c_SemanticMask; + m_flags |= CLR_RT_DataTypeLookup::c_Array; + + m_handlerCls.InitializeFromIndex( g_CLR_RT_WellKnownTypes.m_Array ); +} + +bool CLR_RT_TypeDescriptor::ShouldEmitHash() +{ + NATIVE_PROFILE_CLR_CORE(); + if(m_flags & (CLR_RT_DataTypeLookup::c_Array | CLR_RT_DataTypeLookup::c_ArrayList)) + { + return true; + } + + if(m_flags & (CLR_RT_DataTypeLookup::c_Primitive | CLR_RT_DataTypeLookup::c_ValueType | CLR_RT_DataTypeLookup::c_Enum)) + { + return false; + } + + if(m_handlerCls.CrossReference().m_hash != 0) + { + return true; + } + + return false; +} + +bool CLR_RT_TypeDescriptor::GetElementType( CLR_RT_TypeDescriptor& sub ) +{ + NATIVE_PROFILE_CLR_CORE(); + switch(m_reflex.m_levels) + { + case 0: + return false; + + case 1: + sub.InitializeFromType( m_reflex.m_data.m_type ); + break; + + default: + sub = *this; + sub.m_reflex.m_levels--; + break; + } + + return true; +} + +//////////////////////////////////////// + +HRESULT CLR_RT_TypeDescriptor::ExtractObjectAndDataType( CLR_RT_HeapBlock*& ref, CLR_DataType& dt ) +{ + NATIVE_PROFILE_CLR_CORE(); + + NANOCLR_HEADER(); + + while(true) + { + dt = (CLR_DataType)ref->DataType(); + + if(dt == DATATYPE_BYREF || + dt == DATATYPE_OBJECT ) + { + ref = ref->Dereference(); FAULT_ON_NULL(ref); + } + else + { + break; + } + } + + NANOCLR_NOCLEANUP(); +} + + +HRESULT CLR_RT_TypeDescriptor::ExtractTypeIndexFromObject( const CLR_RT_HeapBlock& ref, CLR_RT_TypeDef_Index& res ) +{ + NATIVE_PROFILE_CLR_CORE(); + + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* obj = (CLR_RT_HeapBlock*)&ref; + CLR_DataType dt; + + NANOCLR_CHECK_HRESULT(CLR_RT_TypeDescriptor::ExtractObjectAndDataType(obj, dt)); + + if(dt == DATATYPE_VALUETYPE || dt == DATATYPE_CLASS) + { + res = obj->ObjectCls(); + } + else + { + const CLR_RT_DataTypeLookup& dtl = c_CLR_RT_DataTypeLookup[ dt ]; + + if(dtl.m_cls) + { + res = *dtl.m_cls; + } + else + { + res.Clear(); + } + } + + if(NANOCLR_INDEX_IS_INVALID(res)) + { + CLR_RT_TypeDescriptor desc; + + NANOCLR_CHECK_HRESULT(desc.InitializeFromObject( ref )) + + // If desc.InitializeFromObject( ref ) call succeded, then we use m_handlerCls for res + res = desc.m_handlerCls; + + if(NANOCLR_INDEX_IS_INVALID(res)) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + } + + NANOCLR_NOCLEANUP(); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////////////////////////// + +// +// Keep this string less than 8-character long (including terminator) because it's stuffed into an 8-byte structure. +// +static const char c_MARKER_ASSEMBLY_V1[] = "NFMRK1"; + +bool CLR_RECORD_ASSEMBLY::GoodHeader() const +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RECORD_ASSEMBLY header = *this; header.headerCRC = 0; + + if(SUPPORT_ComputeCRC( &header, sizeof(header), 0 ) != this->headerCRC) return false; + + if(this->stringTableVersion != c_CLR_StringTable_Version) return false; + + return memcmp( marker, c_MARKER_ASSEMBLY_V1, sizeof(c_MARKER_ASSEMBLY_V1) ) == 0; +} + +bool CLR_RECORD_ASSEMBLY::GoodAssembly() const +{ + NATIVE_PROFILE_CLR_CORE(); + if(!GoodHeader()) return false; + return SUPPORT_ComputeCRC( &this[ 1 ], this->TotalSize() - sizeof(*this), 0 ) == this->assemblyCRC; +} + +#if defined(WIN32) + +void CLR_RECORD_ASSEMBLY::ComputeCRC() +{ + NATIVE_PROFILE_CLR_CORE(); + memcpy( marker, c_MARKER_ASSEMBLY_V1, sizeof(marker) ); + + headerCRC = 0; + assemblyCRC = SUPPORT_ComputeCRC( &this[ 1 ], this->TotalSize() - sizeof(*this), 0 ); + headerCRC = SUPPORT_ComputeCRC( this , sizeof(*this), 0 ); +} + +#endif + +CLR_UINT32 CLR_RECORD_ASSEMBLY::ComputeAssemblyHash( const char* name, const CLR_RECORD_VERSION& ver ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_UINT32 assemblyHASH; + + assemblyHASH = SUPPORT_ComputeCRC( name, (int)hal_strlen_s( name ), 0 ); + assemblyHASH = SUPPORT_ComputeCRC( &ver, sizeof( ver ), assemblyHASH ); + + return assemblyHASH; +} + +//--// + +CLR_PMETADATA CLR_RECORD_EH::ExtractEhFromByteCode( CLR_PMETADATA ipEnd, const CLR_RECORD_EH*& ptrEh, CLR_UINT32& numEh ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_UINT32 num = *(--ipEnd); ipEnd -= sizeof(CLR_RECORD_EH) * num; + + numEh = num; + ptrEh = (const CLR_RECORD_EH*)ipEnd; + + return ipEnd; +} + +CLR_UINT32 CLR_RECORD_EH::GetToken() const +{ + NATIVE_PROFILE_CLR_CORE(); + if(classToken & 0x8000) + { + return CLR_TkFromType( TBL_TypeRef, classToken & 0x7FFF ); + } + else + { + return CLR_TkFromType( TBL_TypeDef, classToken ); + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +bool CLR_RT_ExceptionHandler::ConvertFromEH( const CLR_RT_MethodDef_Instance& owner, CLR_PMETADATA ipStart, const CLR_RECORD_EH* ehPtr ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RECORD_EH eh; memcpy( &eh, ehPtr, sizeof(eh) ); + + switch(eh.mode) + { + case CLR_RECORD_EH::EH_Finally: + m_typeFilter.Clear(); + break; + + case CLR_RECORD_EH::EH_Filter: + m_userFilterStart = ipStart + eh.filterStart; + break; + + case CLR_RECORD_EH::EH_CatchAll: + m_typeFilter = g_CLR_RT_WellKnownTypes.m_Object; + break; + + case CLR_RECORD_EH::EH_Catch: + { + CLR_RT_TypeDef_Instance cls; + if(cls.ResolveToken( eh.GetToken(), owner.m_assm ) == false) return false; + m_typeFilter = cls; + } + break; + + default: + return false; + } + + if(owner.m_target->RVA == CLR_EmptyIndex) return false; + + m_ehType = eh.mode; + m_tryStart = ipStart + eh.tryStart; + m_tryEnd = ipStart + eh.tryEnd; + m_handlerStart = ipStart + eh.handlerStart; + m_handlerEnd = ipStart + eh.handlerEnd; + + return true; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +bool CLR_RT_Assembly::IsSameAssembly( const CLR_RT_Assembly& assm ) const +{ + if( + m_header->headerCRC == assm.m_header->headerCRC && + m_header->assemblyCRC == assm.m_header->assemblyCRC + ) + { + return true; + } + + return false; +} + +void CLR_RT_Assembly::Assembly_Initialize( CLR_RT_Assembly::Offsets& offsets ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_UINT8* buffer = (CLR_UINT8*)this; + int i; + + m_szName = GetString( m_header->assemblyName ); + + //--// + buffer += offsets.iBase ; + m_pCrossReference_AssemblyRef = (CLR_RT_AssemblyRef_CrossReference*)buffer; buffer += offsets.iAssemblyRef ; + m_pCrossReference_TypeRef = (CLR_RT_TypeRef_CrossReference *)buffer; buffer += offsets.iTypeRef ; + m_pCrossReference_FieldRef = (CLR_RT_FieldRef_CrossReference *)buffer; buffer += offsets.iFieldRef ; + m_pCrossReference_MethodRef = (CLR_RT_MethodRef_CrossReference *)buffer; buffer += offsets.iMethodRef ; + m_pCrossReference_TypeDef = (CLR_RT_TypeDef_CrossReference *)buffer; buffer += offsets.iTypeDef ; + m_pCrossReference_FieldDef = (CLR_RT_FieldDef_CrossReference *)buffer; buffer += offsets.iFieldDef ; + m_pCrossReference_MethodDef = (CLR_RT_MethodDef_CrossReference *)buffer; buffer += offsets.iMethodDef ; + +#if !defined(NANOCLR_APPDOMAINS) + m_pStaticFields = (CLR_RT_HeapBlock *)buffer; buffer += offsets.iStaticFields ; + + memset( m_pStaticFields, 0, offsets.iStaticFields ); +#endif + + //--// + + { + ITERATE_THROUGH_RECORDS(this,i,TypeDef,TYPEDEF) + { + dst->m_flags = 0; + dst->m_totalFields = 0; + dst->m_hash = 0; + } + } + + { + ITERATE_THROUGH_RECORDS(this,i,FieldDef,FIELDDEF) + { + dst->m_offset = CLR_EmptyIndex; + } + } + + { + ITERATE_THROUGH_RECORDS(this,i,MethodDef,METHODDEF) + { + dst->m_data = CLR_EmptyIndex; + } + } + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + { + m_pDebuggingInfo_MethodDef = (CLR_RT_MethodDef_DebuggingInfo*)buffer; buffer += offsets.iDebuggingInfoMethods; + + memset( m_pDebuggingInfo_MethodDef, 0, offsets.iDebuggingInfoMethods ); + } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) +} + +HRESULT CLR_RT_Assembly::CreateInstance( const CLR_RECORD_ASSEMBLY* header, CLR_RT_Assembly*& assm ) +{ + NATIVE_PROFILE_CLR_CORE(); + // + // We have to use this trick, otherwise the C++ compiler will try to all the constructor for Assembly. + // + NANOCLR_HEADER(); + + CLR_UINT8 buf[ sizeof(CLR_RT_Assembly) ]; + CLR_RT_Assembly* skeleton = (CLR_RT_Assembly*)buf; + + NANOCLR_CLEAR(*skeleton); + + if(header->GoodAssembly() == false) NANOCLR_MSG_SET_AND_LEAVE(CLR_E_FAIL, L"Failed in type system: assembly is not good.\n"); + + skeleton->m_header = header; + + + // + // Compute overall size for assembly data structure. + // + { + for(uint32_t i = 0; im_pTablesSize)-1; i++) + { + skeleton->m_pTablesSize[ i ] = header->SizeOfTable ( (CLR_TABLESENUM)i ); + } + + skeleton->m_pTablesSize[ TBL_AssemblyRef ] /= sizeof(CLR_RECORD_ASSEMBLYREF ); + skeleton->m_pTablesSize[ TBL_TypeRef ] /= sizeof(CLR_RECORD_TYPEREF ); + skeleton->m_pTablesSize[ TBL_FieldRef ] /= sizeof(CLR_RECORD_FIELDREF ); + skeleton->m_pTablesSize[ TBL_MethodRef ] /= sizeof(CLR_RECORD_METHODREF ); + skeleton->m_pTablesSize[ TBL_TypeDef ] /= sizeof(CLR_RECORD_TYPEDEF ); + skeleton->m_pTablesSize[ TBL_FieldDef ] /= sizeof(CLR_RECORD_FIELDDEF ); + skeleton->m_pTablesSize[ TBL_MethodDef ] /= sizeof(CLR_RECORD_METHODDEF ); + skeleton->m_pTablesSize[ TBL_Attributes ] /= sizeof(CLR_RECORD_ATTRIBUTE ); + skeleton->m_pTablesSize[ TBL_TypeSpec ] /= sizeof(CLR_RECORD_TYPESPEC ); + skeleton->m_pTablesSize[ TBL_Resources ] /= sizeof(CLR_RECORD_RESOURCE ); + skeleton->m_pTablesSize[ TBL_ResourcesFiles ] /= sizeof(CLR_RECORD_RESOURCE_FILE); + } + + //--// + + // + // Count static fields. + // + { + const CLR_RECORD_TYPEDEF* src = (const CLR_RECORD_TYPEDEF*)skeleton->GetTable( TBL_TypeDef ); + + for(int i=0; im_pTablesSize[ TBL_TypeDef ]; i++, src++) + { + skeleton->m_iStaticFields += src->sFields_Num; + } + } + + //--// + + { + CLR_RT_Assembly::Offsets offsets; + + offsets.iBase = ROUNDTOMULTIPLE(sizeof(CLR_RT_Assembly) , CLR_UINT32); + offsets.iAssemblyRef = ROUNDTOMULTIPLE(skeleton->m_pTablesSize[ TBL_AssemblyRef ] * sizeof(CLR_RT_AssemblyRef_CrossReference), CLR_UINT32); + offsets.iTypeRef = ROUNDTOMULTIPLE(skeleton->m_pTablesSize[ TBL_TypeRef ] * sizeof(CLR_RT_TypeRef_CrossReference ), CLR_UINT32); + offsets.iFieldRef = ROUNDTOMULTIPLE(skeleton->m_pTablesSize[ TBL_FieldRef ] * sizeof(CLR_RT_FieldRef_CrossReference ), CLR_UINT32); + offsets.iMethodRef = ROUNDTOMULTIPLE(skeleton->m_pTablesSize[ TBL_MethodRef ] * sizeof(CLR_RT_MethodRef_CrossReference ), CLR_UINT32); + offsets.iTypeDef = ROUNDTOMULTIPLE(skeleton->m_pTablesSize[ TBL_TypeDef ] * sizeof(CLR_RT_TypeDef_CrossReference ), CLR_UINT32); + offsets.iFieldDef = ROUNDTOMULTIPLE(skeleton->m_pTablesSize[ TBL_FieldDef ] * sizeof(CLR_RT_FieldDef_CrossReference ), CLR_UINT32); + offsets.iMethodDef = ROUNDTOMULTIPLE(skeleton->m_pTablesSize[ TBL_MethodDef ] * sizeof(CLR_RT_MethodDef_CrossReference ), CLR_UINT32); + + if(skeleton->m_header->numOfPatchedMethods > 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_ASSM_PATCHING_NOT_SUPPORTED); + } + +#if !defined(NANOCLR_APPDOMAINS) + offsets.iStaticFields = ROUNDTOMULTIPLE(skeleton->m_iStaticFields * sizeof(CLR_RT_HeapBlock ), CLR_UINT32); +#endif + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + offsets.iDebuggingInfoMethods = ROUNDTOMULTIPLE(skeleton->m_pTablesSize[ TBL_MethodDef ] * sizeof(CLR_RT_MethodDef_DebuggingInfo ), CLR_UINT32); +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + size_t iTotalRamSize = offsets.iBase + + offsets.iAssemblyRef + + offsets.iTypeRef + + offsets.iFieldRef + + offsets.iMethodRef + + offsets.iTypeDef + + offsets.iFieldDef + + offsets.iMethodDef; + +#if !defined(NANOCLR_APPDOMAINS) + iTotalRamSize += offsets.iStaticFields; +#endif + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + iTotalRamSize += offsets.iDebuggingInfoMethods; +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + //--// + + assm = EVENTCACHE_EXTRACT_NODE_AS_BYTES(g_CLR_RT_EventCache,CLR_RT_Assembly,DATATYPE_ASSEMBLY,0,(CLR_UINT32)iTotalRamSize); CHECK_ALLOCATION(assm); + + { + // + // We don't want to blow away the block header... + // + CLR_RT_HeapBlock* src = skeleton; + CLR_RT_HeapBlock* dst = assm; + + memset( &dst[ 1 ], 0, iTotalRamSize-sizeof(CLR_RT_HeapBlock) ); + memcpy( &dst[ 1 ], &src[ 1 ], sizeof(*assm)-sizeof(CLR_RT_HeapBlock) ); + } + + assm->Assembly_Initialize( offsets ); + +#if !defined(BUILD_RTM) + CLR_Debug::Printf( " Assembly: %s (%d.%d.%d.%d) ", assm->m_szName, header->version.iMajorVersion, header->version.iMinorVersion, header->version.iBuildNumber, header->version.iRevisionNumber ); + + if(s_CLR_RT_fTrace_AssemblyOverhead >= c_CLR_RT_Trace_Info) + { + size_t iMetaData = header->SizeOfTable( TBL_AssemblyRef ) + + header->SizeOfTable( TBL_TypeRef ) + + header->SizeOfTable( TBL_FieldRef ) + + header->SizeOfTable( TBL_MethodRef ) + + header->SizeOfTable( TBL_TypeDef ) + + header->SizeOfTable( TBL_FieldDef ) + + header->SizeOfTable( TBL_MethodDef ) + + header->SizeOfTable( TBL_Attributes ) + + header->SizeOfTable( TBL_TypeSpec ) + + header->SizeOfTable( TBL_Signatures ); + + CLR_Debug::Printf( " (%d RAM - %d ROM - %d METADATA)\r\n\r\n", iTotalRamSize, header->TotalSize(), iMetaData ); + + CLR_Debug::Printf( " AssemblyRef = %8d bytes (%8d elements)\r\n", offsets.iAssemblyRef , skeleton->m_pTablesSize[ TBL_AssemblyRef ] ); + CLR_Debug::Printf( " TypeRef = %8d bytes (%8d elements)\r\n", offsets.iTypeRef , skeleton->m_pTablesSize[ TBL_TypeRef ] ); + CLR_Debug::Printf( " FieldRef = %8d bytes (%8d elements)\r\n", offsets.iFieldRef , skeleton->m_pTablesSize[ TBL_FieldRef ] ); + CLR_Debug::Printf( " MethodRef = %8d bytes (%8d elements)\r\n", offsets.iMethodRef , skeleton->m_pTablesSize[ TBL_MethodRef ] ); + CLR_Debug::Printf( " TypeDef = %8d bytes (%8d elements)\r\n", offsets.iTypeDef , skeleton->m_pTablesSize[ TBL_TypeDef ] ); + CLR_Debug::Printf( " FieldDef = %8d bytes (%8d elements)\r\n", offsets.iFieldDef , skeleton->m_pTablesSize[ TBL_FieldDef ] ); + CLR_Debug::Printf( " MethodDef = %8d bytes (%8d elements)\r\n", offsets.iMethodDef , skeleton->m_pTablesSize[ TBL_MethodDef ] ); +#if !defined(NANOCLR_APPDOMAINS) + CLR_Debug::Printf( " StaticFields = %8d bytes (%8d elements)\r\n", offsets.iStaticFields , skeleton->m_iStaticFields ); +#endif + CLR_Debug::Printf( "\r\n" ); + + CLR_Debug::Printf( " Attributes = %8d bytes (%8d elements)\r\n", skeleton->m_pTablesSize[ TBL_Attributes ] * sizeof(CLR_RECORD_ATTRIBUTE), skeleton->m_pTablesSize[ TBL_Attributes ] ); + CLR_Debug::Printf( " TypeSpec = %8d bytes (%8d elements)\r\n", skeleton->m_pTablesSize[ TBL_TypeSpec ] * sizeof(CLR_RECORD_TYPESPEC ), skeleton->m_pTablesSize[ TBL_TypeSpec ] ); + CLR_Debug::Printf( " Resources = %8d bytes (%8d elements)\r\n", skeleton->m_pTablesSize[ TBL_Resources ] * sizeof(CLR_RECORD_RESOURCE ), skeleton->m_pTablesSize[ TBL_Resources ] ); + CLR_Debug::Printf( " Resources Files = %8d bytes (%8d elements)\r\n", skeleton->m_pTablesSize[ TBL_ResourcesFiles ] * sizeof(CLR_RECORD_RESOURCE ), skeleton->m_pTablesSize[ TBL_ResourcesFiles ] ); + CLR_Debug::Printf( " Resources Data = %8d bytes\r\n" , skeleton->m_pTablesSize[ TBL_ResourcesData ] ); + CLR_Debug::Printf( " Strings = %8d bytes\r\n" , skeleton->m_pTablesSize[ TBL_Strings ] ); + CLR_Debug::Printf( " Signatures = %8d bytes\r\n" , skeleton->m_pTablesSize[ TBL_Signatures ] ); + CLR_Debug::Printf( " ByteCode = %8d bytes\r\n" , skeleton->m_pTablesSize[ TBL_ByteCode ] ); + CLR_Debug::Printf( "\r\n\r\n" ); + } +#endif + } + + NANOCLR_NOCLEANUP(); +} + + +#if defined(WIN32) +HRESULT CLR_RT_Assembly::CreateInstance( const CLR_RECORD_ASSEMBLY* header, CLR_RT_Assembly*& assm, const wchar_t* szName ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + std::string strPath; + + NANOCLR_CHECK_HRESULT(CLR_RT_Assembly::CreateInstance( header, assm )); + + if(szName != NULL) + { + CLR_RT_UnicodeHelper::ConvertToUTF8( szName, strPath ); + + assm->m_strPath = new std::string( strPath ); + } + + NANOCLR_NOCLEANUP(); +} +#endif + +bool CLR_RT_Assembly::Resolve_AssemblyRef( bool fOutput ) +{ + NATIVE_PROFILE_CLR_CORE(); + bool fGot = true; + int i; + + ITERATE_THROUGH_RECORDS(this,i,AssemblyRef,ASSEMBLYREF) + { + const char* szName = GetString( src->name ); + + if(dst->m_target == NULL) + { + bool fExact = true; + + // + // Exact matching if this is a patch and the reference is toward the patched assembly. + // + if(m_header->flags & CLR_RECORD_ASSEMBLY::c_Flags_Patch) + { + if(!strcmp( szName, m_szName )) + { + fExact = true; + } + } + + CLR_RT_Assembly* target = g_CLR_RT_TypeSystem.FindAssembly( szName, &src->version, fExact ); + + if(target == NULL || (target->m_flags & CLR_RT_Assembly::Resolved) == 0) + { +#if !defined(BUILD_RTM) + if(fOutput) + { + CLR_Debug::Printf( "Assembly: %s (%d.%d.%d.%d)", m_szName, m_header->version.iMajorVersion, m_header->version.iMinorVersion, m_header->version.iBuildNumber, m_header->version.iRevisionNumber ); + + CLR_Debug::Printf( " needs assembly '%s' (%d.%d.%d.%d)\r\n", szName, src->version.iMajorVersion, src->version.iMinorVersion, src->version.iBuildNumber, src->version.iRevisionNumber ); + } +#endif + + fGot = false; + } + else + { + dst->m_target = target; + } + } + } + + return fGot; +} + +void CLR_RT_Assembly::DestroyInstance() +{ + NATIVE_PROFILE_CLR_CORE(); + if(m_idx) + { + g_CLR_RT_TypeSystem.m_assemblies[ m_idx-1 ] = NULL; + } + +#if defined(WIN32) + if(this->m_strPath != NULL) + { + delete this->m_strPath; + this->m_strPath = NULL; + } +#endif + + //--// + + g_CLR_RT_EventCache.Append_Node( this ); +} + +//--// +HRESULT CLR_RT_Assembly::Resolve_TypeRef() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + int i; + + ITERATE_THROUGH_RECORDS(this,i,TypeRef,TYPEREF) + { + if(src->scope & 0x8000) // Flag for TypeRef + { + CLR_RT_TypeDef_Instance inst; + + if(inst.InitializeFromIndex( m_pCrossReference_TypeRef[ src->scope & 0x7FFF ].m_target ) == false) + { +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Resolve: unknown scope: %08x\r\n", src->scope ); +#endif + +#if defined(_WIN32) + NANOCLR_CHARMSG_SET_AND_LEAVE(CLR_E_FAIL, "Resolve: unknown scope: %08x\r\n", src->scope); +#else + NANOCLR_MSG1_SET_AND_LEAVE(CLR_E_FAIL, L"Resolve: unknown scope: %08x\r\n", src->scope); +#endif + } + + const char* szName = GetString( src->name ); + if(inst.m_assm->FindTypeDef( szName, inst.Type(), dst->m_target ) == false) + { +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Resolve: unknown type: %s\r\n", szName ); +#endif + +#if defined(_WIN32) + NANOCLR_CHARMSG_SET_AND_LEAVE(CLR_E_FAIL, "Resolve: unknown type: %s\r\n", szName); +#else + NANOCLR_MSG1_SET_AND_LEAVE(CLR_E_FAIL, L"Resolve: unknown type: %s\r\n", szName); +#endif + } + } + else + { + CLR_RT_Assembly* assm = m_pCrossReference_AssemblyRef[ src->scope ].m_target; + if(assm == NULL) + { + NANOCLR_MSG_SET_AND_LEAVE(CLR_E_FAIL, L"Resolve: assm is null\n"); + } + + const char* szNameSpace = GetString( src->nameSpace ); + const char* szName = GetString( src->name ); + if(assm->FindTypeDef( szName, szNameSpace, dst->m_target ) == false) + { +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Resolve: unknown type: %s.%s\r\n", szNameSpace, szName ); +#endif + +#if defined(_WIN32) + NANOCLR_CHARMSG_SET_AND_LEAVE(CLR_E_FAIL, "Resolve: unknown type: %s.%s\r\n", szNameSpace, szName); +#else + NANOCLR_MSG1_SET_AND_LEAVE(CLR_E_FAIL, L"Resolve: unknown type: %s\r\n", szName); +#endif + } + } + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_Assembly::Resolve_FieldRef() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + int i; + + ITERATE_THROUGH_RECORDS(this,i,FieldRef,FIELDREF) + { + CLR_RT_TypeDef_Instance inst; + + if(inst.InitializeFromIndex( m_pCrossReference_TypeRef[ src->container ].m_target ) == false) + { +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Resolve Field: unknown scope: %08x\r\n", src->container ); +#endif + +#if defined(_WIN32) + NANOCLR_CHARMSG_SET_AND_LEAVE(CLR_E_FAIL, "Resolve Field: unknown scope: %08x\r\n", src->container); +#else + NANOCLR_MSG1_SET_AND_LEAVE(CLR_E_FAIL, L"Resolve Field: unknown scope: %08x\r\n", src->container); +#endif + } + + const char* szName = GetString( src->name ); + + if(inst.m_assm->FindFieldDef( inst.m_target, szName, this, src->sig, dst->m_target ) == false) + { +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Resolve: unknown field: %s\r\n", szName ); +#endif + +#if defined(_WIN32) + NANOCLR_CHARMSG_SET_AND_LEAVE(CLR_E_FAIL, "Resolve: unknown field: %s\r\n", szName); +#else + NANOCLR_MSG1_SET_AND_LEAVE(CLR_E_FAIL, L"Resolve: unknown field: %s\r\n", szName); +#endif + } + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_Assembly::Resolve_MethodRef() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + int i; + + ITERATE_THROUGH_RECORDS(this,i,MethodRef,METHODREF) + { + CLR_RT_TypeDef_Instance inst; + + if(inst.InitializeFromIndex( m_pCrossReference_TypeRef[ src->container ].m_target ) == false) + { +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Resolve Field: unknown scope: %08x\r\n", src->container ); +#endif + +#if defined(_WIN32) + NANOCLR_CHARMSG_SET_AND_LEAVE(CLR_E_FAIL, "Resolve Field: unknown scope: %08x\r\n", src->container); +#else + NANOCLR_MSG1_SET_AND_LEAVE(CLR_E_FAIL, L"Resolve Field: unknown scope: %08x\r\n", src->container); +#endif + } + + const char* name = GetString( src->name ); + bool fGot = false; + + while(NANOCLR_INDEX_IS_VALID(inst)) + { + if(inst.m_assm->FindMethodDef( inst.m_target, name, this, src->sig, dst->m_target )) + { + fGot = true; + break; + } + + inst.SwitchToParent(); + } + + if(fGot == false) + { + inst.InitializeFromIndex( m_pCrossReference_TypeRef[ src->container ].m_target ); + + const CLR_RECORD_TYPEDEF* qTD = inst.m_target; + CLR_RT_Assembly* qASSM = inst.m_assm; + +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Resolve: unknown method: %s.%s.%s\r\n", qASSM->GetString( qTD->nameSpace ), qASSM->GetString( qTD->name ), name ); +#endif + +#if defined(_WIN32) + NANOCLR_CHARMSG_SET_AND_LEAVE(CLR_E_FAIL, "Resolve: unknown method: %s\r\n", name); +#else + NANOCLR_MSG1_SET_AND_LEAVE(CLR_E_FAIL, L"Resolve: unknown method: %s\r\n", name); +#endif + } + } + + NANOCLR_NOCLEANUP(); +} + +void CLR_RT_Assembly::Resolve_Link() +{ + NATIVE_PROFILE_CLR_CORE(); + int iStaticFields = 0; + int idxType; + + ITERATE_THROUGH_RECORDS(this,idxType,TypeDef,TYPEDEF) + { + int num; + int i; + + // + // Link static fields. + // + { + CLR_RT_FieldDef_CrossReference* fd = &m_pCrossReference_FieldDef[ src->sFields_First ]; + + num = src->sFields_Num; + + for(; num; num--, fd++) + { + fd->m_offset = iStaticFields++; + } + } + + // + // Link instance fields. + // + { + CLR_RT_TypeDef_Index idx ; idx.Set( m_idx, idxType ); + CLR_RT_TypeDef_Instance inst; inst.InitializeFromIndex( idx ); + CLR_IDX tot = 0; + + do + { + if(inst.m_target->flags & CLR_RECORD_TYPEDEF::TD_HasFinalizer) + { + dst->m_flags |= CLR_RT_TypeDef_CrossReference::TD_CR_HasFinalizer; + } + +#if defined(NANOCLR_APPDOMAINS) + if(inst.m_data == g_CLR_RT_WellKnownTypes.m_MarshalByRefObject.m_data) + { + dst->m_flags |= CLR_RT_TypeDef_CrossReference::TD_CR_IsMarshalByRefObject; + } +#endif + + tot += inst.m_target->iFields_Num; + } + while(inst.SwitchToParent()); + + dst->m_totalFields = tot; + + //--// + + CLR_RT_FieldDef_CrossReference* fd = &m_pCrossReference_FieldDef[ src->iFields_First ]; + + num = src->iFields_Num; + i = tot - num + CLR_RT_HeapBlock::HB_Object_Fields_Offset; // Take into account the offset from the beginning of the object. + + for(; num; num--, i++, fd++) + { + fd->m_offset = i; + } + } + + // + // Link methods. + // + { + CLR_RT_MethodDef_CrossReference* md = &m_pCrossReference_MethodDef[ src->methods_First ]; + + int num = src->vMethods_Num + src->iMethods_Num + src->sMethods_Num; + + for(; num; num--, md++) + { + md->m_data = idxType; + } + } + } +} + +//--// + +#if defined(NANOCLR_APPDOMAINS) + +HRESULT CLR_RT_AppDomain::CreateInstance( const char* szName, CLR_RT_AppDomain*& appDomain ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + CLR_RT_HeapBlock name; name.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc( name ); + + if(!szName || szName[ 0 ] == '\0') NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + //Check to see that the name does not already exist. + NANOCLR_FOREACH_NODE(CLR_RT_AppDomain,appDomain,g_CLR_RT_ExecutionEngine.m_appDomains) + { + if(!strcmp( appDomain->m_strName->StringText(), szName )) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + NANOCLR_FOREACH_NODE_END(); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( name, szName )); + + appDomain = EVENTCACHE_EXTRACT_NODE(g_CLR_RT_EventCache,CLR_RT_AppDomain,DATATYPE_APPDOMAIN_HEAD); CHECK_ALLOCATION(appDomain); + + appDomain->AppDomain_Initialize(); + + appDomain->m_strName = name.DereferenceString(); + + g_CLR_RT_ExecutionEngine.m_appDomains.LinkAtBack( appDomain ); + + NANOCLR_NOCLEANUP(); +} + +void CLR_RT_AppDomain::RecoverFromGC() +{ + NATIVE_PROFILE_CLR_CORE(); + CheckAll(); + + /* + AppDomains can be zombied and stay around forever. It is worth looking into cleaning up dead AppDomains, but this + needs to be done with great care. First, enumerations of AppDomains must not be allowed. Second, the AppDomain must really be dead. + This is much harder to ensure. Everything that is needed to be checked for explicit AD unloading (stack frames, finalizable objects) + must be checked, but also other things that can cause the AppDomain to be alive, like timers, manaaged drivers, transparent proxies, etc.. + */ + + if(m_state == CLR_RT_AppDomain::AppDomainState_Unloaded) + { + //We could actually clean up here. Since the AppDomain is now officially loaded, + //we can remove all object_to_event_dst references, and null out the + //pointers in the managed AppDomain class, provided that calling any method on the + //AppDomain will result in a AppDomainDisposed exception. However, it's probably + //not worth the effort, the majority of the resources have been already cleaned + //up, from AppDomain_Uninitialize + + if(IsReadyForRelease()) + { + DestroyInstance(); + } + } +} + +void CLR_RT_AppDomain::AppDomain_Initialize() +{ + NATIVE_PROFILE_CLR_CORE(); + Initialize(); + + m_appDomainAssemblies.DblLinkedList_Initialize(); + + m_state = CLR_RT_AppDomain::AppDomainState_Loaded; + m_id = g_CLR_RT_ExecutionEngine.m_appDomainIdNext++; + m_globalLock = NULL; + m_strName = NULL; + m_outOfMemoryException = NULL; + m_appDomainAssemblyLastAccess = NULL; +} + +void CLR_RT_AppDomain::AppDomain_Uninitialize() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_NODE(CLR_RT_AppDomainAssembly,appDomainAssembly,m_appDomainAssemblies) + { + appDomainAssembly->DestroyInstance(); + } + NANOCLR_FOREACH_NODE_END(); +} + +void CLR_RT_AppDomain::DestroyInstance() +{ + NATIVE_PROFILE_CLR_CORE(); + AppDomain_Uninitialize(); + + Unlink(); + + g_CLR_RT_EventCache.Append_Node( this ); +} + +HRESULT CLR_RT_AppDomain::LoadAssembly( CLR_RT_Assembly* assm ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_AppDomain* appDomainSav = g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( this ); + CLR_RT_AppDomainAssembly* appDomainAssembly = NULL; + int i; + + FAULT_ON_NULL( assm ); + + //check to make sure the assembly is not already loaded + if(FindAppDomainAssembly( assm ) != NULL) NANOCLR_SET_AND_LEAVE(S_OK); + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + g_CLR_RT_ExecutionEngine.Breakpoint_Assemblies_Loaded(); +#endif + + //Next, make sure that all dependent assemblies are loaded. + { + ITERATE_THROUGH_RECORDS(assm,i,AssemblyRef,ASSEMBLYREF) + { + NANOCLR_CHECK_HRESULT(LoadAssembly( dst->m_target )); + } + } + + NANOCLR_CHECK_HRESULT(CLR_RT_AppDomainAssembly::CreateInstance( this, assm, appDomainAssembly )); + + if(m_outOfMemoryException == NULL) + { + //Allocate an out of memory exception. We should never get into a case where an out of memory exception + //cannot be thrown. + CLR_RT_HeapBlock exception; + + _ASSERTE(!strcmp( assm->m_szName, "mscorlib" )); //always the first assembly to be loaded + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex( exception, g_CLR_RT_WellKnownTypes.m_OutOfMemoryException )); + + m_outOfMemoryException = exception.Dereference(); + } + + NANOCLR_CLEANUP(); + + if(FAILED(hr)) + { + if(appDomainAssembly) + { + appDomainAssembly->DestroyInstance(); + } + } + + (void)g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( appDomainSav ); + + NANOCLR_CLEANUP_END(); +} + + +HRESULT CLR_RT_AppDomain::GetManagedObject( CLR_RT_HeapBlock& res ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_AppDomain* appDomainSav = g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( this ); + + res.SetObjectReference( NULL ); + + //Check if a managed object is already present, and use it + NANOCLR_FOREACH_NODE(CLR_RT_ObjectToEvent_Source,ref,m_references) + { + CLR_RT_HeapBlock* obj = ref->m_objectPtr; + + _ASSERTE(FIMPLIES(obj, obj->DataType() == DATATYPE_CLASS || obj->DataType() == DATATYPE_VALUETYPE)); + + if(obj && obj->ObjectCls().m_data == g_CLR_RT_WellKnownTypes.m_AppDomain.m_data) + { + //managed appDomain is found. Use it. + res.SetObjectReference( ref->m_objectPtr ); + + NANOCLR_SET_AND_LEAVE(S_OK); + } + } + NANOCLR_FOREACH_NODE_END(); + + { + //Create the managed AppDomain in the destination AppDomain + CLR_RT_HeapBlock* pRes; + CLR_RT_ProtectFromGC gc( res ); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex( res, g_CLR_RT_WellKnownTypes.m_AppDomain )); + + pRes = res.Dereference(); + + NANOCLR_CHECK_HRESULT(CLR_RT_ObjectToEvent_Source::CreateInstance( this, *pRes, pRes[ Library_corlib_native_System_AppDomain::FIELD___appDomain ] )); + + pRes[ Library_corlib_native_System_AppDomain::FIELD___friendlyName ].SetObjectReference( m_strName ); + } + + NANOCLR_CLEANUP(); + + g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( appDomainSav ); + + NANOCLR_CLEANUP_END(); +} + +CLR_RT_AppDomainAssembly* CLR_RT_AppDomain::FindAppDomainAssembly( CLR_RT_Assembly* assm ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(m_appDomainAssemblyLastAccess != NULL && m_appDomainAssemblyLastAccess->m_assembly == assm) + { + return m_appDomainAssemblyLastAccess; + } + + NANOCLR_FOREACH_NODE(CLR_RT_AppDomainAssembly,appDomainAssembly,m_appDomainAssemblies) + { + if(appDomainAssembly->m_assembly == assm) + { + m_appDomainAssemblyLastAccess = appDomainAssembly; + + return appDomainAssembly; + } + } + NANOCLR_FOREACH_NODE_END(); + + return NULL; +} + +void CLR_RT_AppDomain::Relocate() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_globalLock ); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_strName ); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_outOfMemoryException ); +} + +HRESULT CLR_RT_AppDomain::VerifyTypeIsLoaded( const CLR_RT_TypeDef_Index& idx ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Instance inst; + + if(!inst.InitializeFromIndex( idx )) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER ); + if(!FindAppDomainAssembly ( inst.m_assm )) NANOCLR_SET_AND_LEAVE(CLR_E_APPDOMAIN_MARSHAL_EXCEPTION); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_AppDomain::MarshalObject( CLR_RT_HeapBlock& src, CLR_RT_HeapBlock& dst, CLR_RT_AppDomain* appDomainSrc ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + //This function marshals an object from appDomainSrc to 'this' AppDomain + //If appDomainSrc == NULL, this uses the current AppDomain + + CLR_RT_AppDomain* appDomainDst = this; + CLR_RT_HeapBlock* proxySrc = NULL; + CLR_RT_HeapBlock* mbroSrc = NULL; + bool fSimpleAssign = false; + CLR_RT_TypeDef_Index idxVerify = g_CLR_RT_WellKnownTypes.m_Object; + CLR_DataType dtSrc = src.DataType(); + CLR_RT_AppDomain* appDomainSav = g_CLR_RT_ExecutionEngine.GetCurrentAppDomain(); + + if(!appDomainSrc) + { + appDomainSrc = appDomainSav; + } + + // + //DATATYPE_LAST_PRIMITIVE_TO_MARSHAL note + //We should think about allowing STRINGS to be shared across AD boundaries + //Strings are read-only and it is safe to do this with some small restrictions + //First, as with the Assembly unloading, some strings can actually point within an + //assembly. If we allow assemblies to be unloaded (and why shouldn't we, if they are + //not in any AppDomain, than we need to deal with this case). If we just + //get copy the string on constructor, then we do not need to marshal strings + //across AD boundaries. + // + fSimpleAssign = (appDomainSrc == appDomainDst); + fSimpleAssign = fSimpleAssign || (dtSrc <= DATATYPE_LAST_PRIMITIVE_TO_MARSHAL); + fSimpleAssign = fSimpleAssign || (dtSrc == DATATYPE_OBJECT && src.Dereference() == NULL); + +#if !defined(NANOCLR_NO_ASSEMBLY_STRINGS) + fSimpleAssign = fSimpleAssign || (dtSrc == DATATYPE_STRING && !src.StringAssembly()); +#endif + + if(!fSimpleAssign) + { + if(dtSrc == DATATYPE_OBJECT) + { + CLR_RT_HeapBlock* ptr = src.Dereference(); + + switch(ptr->DataType()) + { + case DATATYPE_TRANSPARENT_PROXY: + { + proxySrc = ptr; + + NANOCLR_CHECK_HRESULT(proxySrc->TransparentProxyValidate()); + + idxVerify = proxySrc->TransparentProxyDereference()->ObjectCls(); + + if(proxySrc->TransparentProxyAppDomain() != appDomainDst) + { + //marshalling a transparent proxy object to a third AppDomain + //This makes the marshaling a simple assign of the DATATYPE_TRANSPARENT_PROXY heapblock + fSimpleAssign = true; + } + } + break; + case DATATYPE_CLASS: + { + CLR_RT_TypeDef_Instance inst; + + if(inst.InitializeFromIndex( ptr->ObjectCls() )) + { + if((inst.CrossReference().m_flags & CLR_RT_TypeDef_CrossReference::TD_CR_IsMarshalByRefObject) != 0) + { + idxVerify = inst; + + mbroSrc = ptr; + } + } + } + break; + } + } + } + + NANOCLR_CHECK_HRESULT(appDomainDst->VerifyTypeIsLoaded( idxVerify )); + + if(fSimpleAssign) + { + dst.Assign( src ); + } + else if(proxySrc != NULL) + { + //src is OBJECT->TRANSPARENT_PROXY->CLASS, and we are marshalling into 'this' appDomain + //dst is OBJECT->CLASS + _ASSERTE(proxySrc->TransparentProxyAppDomain() == appDomainDst); + + dst.SetObjectReference( proxySrc->TransparentProxyDereference() ); + } + else if(mbroSrc != NULL) + { + //src is a MarshalByRefObject that we are marshalling outside of its AppDomain + //src is OBJECT->CLASS + //dst is OBJECT->TRANSPARENT_PROXY->CLASS + + (void)g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( appDomainDst ); + CLR_RT_HeapBlock* proxyDst = g_CLR_RT_ExecutionEngine.ExtractHeapBlocksForObjects( DATATYPE_TRANSPARENT_PROXY, 0, 1 ); CHECK_ALLOCATION(proxyDst); + + proxyDst->SetTransparentProxyReference( appDomainSrc, mbroSrc ); + dst.SetObjectReference( proxyDst ); + } + else + { + CLR_RT_HeapBlock blk; blk.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc( blk ); + bool fNoCompaction = CLR_EE_DBG_IS(NoCompaction); + + //Need to prevent compaction between serialization/deserialization. + //Doesn't seem that currently compaction can actually occur during this time, + //but just to be safe, we should prevent it. + + CLR_EE_DBG_SET(NoCompaction); + NANOCLR_CHECK_HRESULT(CLR_RT_BinaryFormatter::Serialize( blk, src, NULL, CLR_RT_BinaryFormatter::c_Flags_Marshal )); + + (void)g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( appDomainDst ); + hr = CLR_RT_BinaryFormatter::Deserialize( dst, blk, NULL, NULL, CLR_RT_BinaryFormatter::c_Flags_Marshal ); + + CLR_EE_DBG_RESTORE(NoCompaction,fNoCompaction); + } + + NANOCLR_CLEANUP(); + + (void)g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( appDomainSav ); + + NANOCLR_CLEANUP_END(); +} + +HRESULT CLR_RT_AppDomain::MarshalParameters( CLR_RT_HeapBlock* callerArgs, CLR_RT_HeapBlock* calleeArgs, int count, bool fOnReturn, CLR_RT_AppDomain* appDomainSrc ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* src = fOnReturn ? calleeArgs : callerArgs; + CLR_RT_HeapBlock* dst = fOnReturn ? callerArgs : calleeArgs; + + while(count-- > 0) + { + CLR_DataType dtSrc = src->DataType(); + CLR_DataType dtDst = dst->DataType(); + + if(dtSrc == DATATYPE_BYREF || dtSrc == DATATYPE_ARRAY_BYREF) + { + CLR_RT_HeapBlock srcObj; + CLR_RT_HeapBlock dstObj; + + if(fOnReturn) + { + srcObj.Assign( *src->Dereference() ); + + NANOCLR_CHECK_HRESULT(MarshalObject( srcObj, dstObj, appDomainSrc )); + + //Move the marshaled object back into dst heapblock + if(dtDst == DATATYPE_BYREF) + { + dst->Dereference()->Assign( dstObj ); + } + else + { + dstObj.StoreToReference( *dst, 0 ); + } + } + else //!fOnReturn + { + CLR_RT_HeapBlock* dstPtr = NULL; + + if(dtSrc == DATATYPE_BYREF) + { + srcObj.Assign( *src->Dereference() ); + } + else + { + srcObj.LoadFromReference( *src ); + } + + NANOCLR_CHECK_HRESULT(MarshalObject( srcObj, dstObj, appDomainSrc )); + + //Need to copy DstObj onto the heap. + dstPtr = g_CLR_RT_ExecutionEngine.ExtractHeapBlocksForObjects( DATATYPE_OBJECT, 0, 1 ); FAULT_ON_NULL(dstPtr); + + _ASSERTE(c_CLR_RT_DataTypeLookup[ dstObj.DataType() ].m_sizeInBytes != CLR_RT_DataTypeLookup::c_NA); + + dstPtr->Assign( dstObj ); + + //Turn the OBJECT back into a BYREF + dst->SetReference( *dstPtr ); + } + } + else //Not BYREF + { + if(!fOnReturn) + { + NANOCLR_CHECK_HRESULT(MarshalObject( *src, *dst, appDomainSrc )); + } + } + + src++; + dst++; + } + + NANOCLR_NOCLEANUP(); +} + + +HRESULT CLR_RT_AppDomain::GetAssemblies( CLR_RT_HeapBlock& ref ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + int count = 0; + CLR_RT_HeapBlock* pArray = NULL; + + for(int pass=0; pass<2; pass++) + { + NANOCLR_FOREACH_ASSEMBLY_IN_APPDOMAIN( this ) + { + if(pASSM->m_header->flags & CLR_RECORD_ASSEMBLY::c_Flags_Patch) continue; + + if(pass == 0) + { + count++; + } + else + { + CLR_RT_HeapBlock* hbObj; + CLR_RT_Assembly_Index idx; idx.Set( pASSM->m_idx ); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*pArray, g_CLR_RT_WellKnownTypes.m_Assembly)); + hbObj = pArray->Dereference(); + + hbObj->SetReflection( idx ); + + pArray++; + } + } + NANOCLR_FOREACH_ASSEMBLY_IN_APPDOMAIN_END(); + + if(pass == 0) + { + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( ref, count, g_CLR_RT_WellKnownTypes.m_Assembly )); + + pArray = (CLR_RT_HeapBlock*)ref.DereferenceArray()->GetFirstElement(); + } + } + + NANOCLR_NOCLEANUP(); +} + +bool CLR_RT_AppDomain::IsLoaded() +{ + NATIVE_PROFILE_CLR_CORE(); + return m_state == CLR_RT_AppDomain::AppDomainState_Loaded; +} + +//--// + +HRESULT CLR_RT_AppDomainAssembly::CreateInstance( CLR_RT_AppDomain* appDomain, CLR_RT_Assembly* assm, CLR_RT_AppDomainAssembly*& appDomainAssembly ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + int size = CONVERTFROMSIZETOHEAPBLOCKS(sizeof(CLR_RT_AppDomainAssembly)) + assm->m_iStaticFields; + + appDomainAssembly = EVENTCACHE_EXTRACT_NODE_AS_BLOCKS(g_CLR_RT_EventCache,CLR_RT_AppDomainAssembly,DATATYPE_APPDOMAIN_ASSEMBLY,CLR_RT_HeapBlock::HB_InitializeToZero,size); CHECK_ALLOCATION(appDomainAssembly); + + NANOCLR_CHECK_HRESULT(appDomainAssembly->AppDomainAssembly_Initialize( appDomain, assm )); + + NANOCLR_CLEANUP(); + + if(FAILED(hr)) + { + if(appDomainAssembly) + { + appDomainAssembly->DestroyInstance(); + } + } + + NANOCLR_CLEANUP_END(); +} + +HRESULT CLR_RT_AppDomainAssembly::AppDomainAssembly_Initialize( CLR_RT_AppDomain* appDomain, CLR_RT_Assembly* assm ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_AppDomain* appDomainSav = g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( appDomain ); + + m_appDomain = appDomain; + m_assembly = assm; + m_flags = 0; + m_pStaticFields = (CLR_RT_HeapBlock*)&this[ 1 ]; + + /* + The AppDomainAssembly gets linked before it is actually initialized, for two reasons. First, it needs to be + attached to the AppDomain in case a GC runs during the allocation of fields. Second, this assembly needs to be + loaded in the AppDomain when the static constructors are run. + */ + + appDomain->m_appDomainAssemblies.LinkAtBack( this ); + + NANOCLR_CHECK_HRESULT(assm->Resolve_AllocateStaticFields( m_pStaticFields )); + + if(!CLR_EE_DBG_IS_MASK(StateInitialize,StateMask)) + { + //Only in the non-boot case should we do this. Otherwise, debug events can occur out of order (thread creation of the + //static constructor before thread creation of the main thread. + g_CLR_RT_ExecutionEngine.SpawnStaticConstructor( g_CLR_RT_ExecutionEngine.m_cctorThread ); + } + + NANOCLR_CLEANUP(); + + if(FAILED(hr)) + { + Unlink(); + } + + g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( appDomainSav ); + + NANOCLR_CLEANUP_END(); +} + +void CLR_RT_AppDomainAssembly::DestroyInstance() +{ + NATIVE_PROFILE_CLR_CORE(); + Unlink(); + + g_CLR_RT_EventCache.Append_Node( this ); +} + +void CLR_RT_AppDomainAssembly::Relocate() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_GarbageCollector::Heap_Relocate( m_pStaticFields, m_assembly->m_iStaticFields ); +} + +#endif //NANOCLR_APPDOMAINS + +//--// + + +struct TypeIndexLookup +{ + const char* nameSpace; + const char* name; + CLR_RT_TypeDef_Index* ptr; +}; + +static const TypeIndexLookup c_TypeIndexLookup[] = +{ +#define TIL(ns,nm,fld) { ns, nm, &g_CLR_RT_WellKnownTypes.fld } + TIL( "System" , "Boolean" , m_Boolean ), + TIL( "System" , "Char" , m_Char ), + TIL( "System" , "SByte" , m_Int8 ), + TIL( "System" , "Byte" , m_UInt8 ), + TIL( "System" , "Int16" , m_Int16 ), + TIL( "System" , "UInt16" , m_UInt16 ), + TIL( "System" , "Int32" , m_Int32 ), + TIL( "System" , "UInt32" , m_UInt32 ), + TIL( "System" , "Int64" , m_Int64 ), + TIL( "System" , "UInt64" , m_UInt64 ), + TIL( "System" , "Single" , m_Single ), + TIL( "System" , "Double" , m_Double ), + TIL( "System" , "DateTime" , m_DateTime ), + TIL( "System" , "TimeSpan" , m_TimeSpan ), + TIL( "System" , "String" , m_String ), + + TIL( "System" , "Void" , m_Void ), + TIL( "System" , "Object" , m_Object ), + TIL( "System" , "ValueType" , m_ValueType ), + TIL( "System" , "Enum" , m_Enum ), + + TIL( "System" , "AppDomainUnloadedException" , m_AppDomainUnloadedException ), + TIL( "System" , "ArgumentNullException" , m_ArgumentNullException ), + TIL( "System" , "ArgumentException" , m_ArgumentException ), + TIL( "System" , "ArgumentOutOfRangeException" , m_ArgumentOutOfRangeException ), + TIL( "System" , "Exception" , m_Exception ), + TIL( "System" , "IndexOutOfRangeException" , m_IndexOutOfRangeException ), + TIL( "System" , "InvalidCastException" , m_InvalidCastException ), + TIL( "System" , "InvalidOperationException" , m_InvalidOperationException ), + TIL( "System" , "NotSupportedException" , m_NotSupportedException ), + TIL( "System" , "NotImplementedException" , m_NotImplementedException ), + TIL( "System" , "NullReferenceException" , m_NullReferenceException ), + TIL( "System" , "OutOfMemoryException" , m_OutOfMemoryException ), + TIL( "System" , "ObjectDisposedException" , m_ObjectDisposedException ), + TIL( "System.Threading" , "ThreadAbortException" , m_ThreadAbortException ), + TIL( "nanoFramework.Runtime.Native" , "ConstraintException" , m_ConstraintException ), + + TIL( "System" , "Delegate" , m_Delegate ), + TIL( "System" , "MulticastDelegate" , m_MulticastDelegate ), + + TIL( "System" , "Array" , m_Array ), + TIL( "System.Collections" , "ArrayList" , m_ArrayList ), + TIL( "System" , "ICloneable" , m_ICloneable ), + TIL( "System.Collections" , "IList" , m_IList ), + + TIL( "System.Reflection" , "Assembly" , m_Assembly ), + TIL( "System" , "Type" , m_TypeStatic ), + TIL( "System" , "RuntimeType" , m_Type ), + TIL( "System.Reflection" , "RuntimeConstructorInfo" , m_ConstructorInfo ), + TIL( "System.Reflection" , "RuntimeMethodInfo" , m_MethodInfo ), + TIL( "System.Reflection" , "RuntimeFieldInfo" , m_FieldInfo ), + + TIL( "System" , "WeakReference" , m_WeakReference ), + + TIL( "Microsoft.SPOT" , "SerializationHintsAttribute" , m_SerializationHintsAttribute ), + + TIL( "Microsoft.SPOT.Hardware" , "WatchdogException" , m_WatchdogException ), + + TIL( "System.Net.NetworkInformation" , "NetworkInterface" , m_NetworkInterface ), + TIL( "System.Net.NetworkInformation" , "Wireless80211Configuration" , m_Wireless80211Configuration ), + TIL( "System.Net.NetworkInformation" , "WirelessAPConfiguration" , m_WirelessAPConfiguration ), + TIL( "System.Net.NetworkInformation" , "WirelessAPStation" , m_WirelessAPStation ), + +#if defined(NANOCLR_APPDOMAINS) + TIL( "System" , "AppDomain" , m_AppDomain ), + TIL( "System" , "MarshalByRefObject" , m_MarshalByRefObject ), +#endif + + TIL( "System.Threading" , "Thread" , m_Thread ), + TIL( "System.Resources" , "ResourceManager" , m_ResourceManager ), + + TIL( "System.Net.Sockets" , "SocketException" , m_SocketException ), + + TIL( "Windows.Devices.I2c" , "I2cTransferResult" , m_I2cTransferResult ), + +#undef TIL +}; + + +//--// + + +struct MethodIndexLookup +{ + const char* name; + CLR_RT_TypeDef_Index* type; + CLR_RT_MethodDef_Index* method; +}; + +static const MethodIndexLookup c_MethodIndexLookup[] = +{ + #define MIL(nm,type,method) { nm, &g_CLR_RT_WellKnownTypes.type, &g_CLR_RT_WellKnownMethods.method } + + MIL( "GetObjectFromId" , m_ResourceManager, m_ResourceManager_GetObjectFromId ), + MIL( "GetObjectChunkFromId", m_ResourceManager, m_ResourceManager_GetObjectChunkFromId ), + + #undef MIL +}; + +void CLR_RT_Assembly::Resolve_TypeDef() +{ + NATIVE_PROFILE_CLR_CORE(); + const TypeIndexLookup* tilOuterClass = NULL; + const TypeIndexLookup* til = c_TypeIndexLookup; + + for(size_t i=0; iptr; + + if(NANOCLR_INDEX_IS_INVALID(dst)) + { + if(til->nameSpace == NULL) + { + if(tilOuterClass) + { + FindTypeDef( til->name, tilOuterClass->ptr->Type(), dst ); + } + } + else + { + FindTypeDef( til->name, til->nameSpace, dst ); + } + } + + if(til->nameSpace != NULL) + { + tilOuterClass = til; + } + } +} + +void CLR_RT_Assembly::Resolve_MethodDef() +{ + NATIVE_PROFILE_CLR_CORE(); + const CLR_RECORD_METHODDEF* md = GetMethodDef( 0 ); + + for(int i=0; itype; + CLR_RT_MethodDef_Index& idxMethod = *mil->method; + + if(NANOCLR_INDEX_IS_VALID(idxType) && NANOCLR_INDEX_IS_INVALID(idxMethod)) + { + CLR_RT_TypeDef_Instance instType; + + _SIDE_ASSERTE(instType.InitializeFromIndex( idxType )); + + if(instType.m_assm == this) + { + if(!strcmp( GetString(md->name), mil->name )) + { + idxMethod.m_data = idx.m_data; + } + } + } + } + + if(md->flags & CLR_RECORD_METHODDEF::MD_EntryPoint) + { + g_CLR_RT_TypeSystem.m_entryPoint = idx; + } + } +} + +HRESULT CLR_RT_Assembly::Resolve_AllocateStaticFields( CLR_RT_HeapBlock* pStaticFields ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + const CLR_RECORD_FIELDDEF* fd = GetFieldDef( 0 ); + + for(int i=0; iflags & CLR_RECORD_FIELDDEF::FD_Static) + { + CLR_RT_FieldDef_CrossReference& res = m_pCrossReference_FieldDef[ i ]; + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.InitializeReference( pStaticFields[ res.m_offset ], fd, this )); + } + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_Assembly::PrepareForExecution() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if((m_flags & CLR_RT_Assembly::PreparingForExecution) != 0) + { + //Circular dependency + _ASSERTE(false); + + NANOCLR_MSG_SET_AND_LEAVE(CLR_E_FAIL, L"Failed to prepare type system for execution\n"); + } + + if((m_flags & CLR_RT_Assembly::PreparedForExecution) == 0) + { + int i; + + m_flags |= CLR_RT_Assembly::PreparingForExecution; + + ITERATE_THROUGH_RECORDS(this,i,AssemblyRef,ASSEMBLYREF) + { + _ASSERTE(dst->m_target != NULL); + + if(dst->m_target != NULL) + { + NANOCLR_CHECK_HRESULT(dst->m_target->PrepareForExecution()); + } + } + + if(m_header->patchEntryOffset != 0xFFFFFFFF) + { + CLR_PMETADATA ptr = GetResourceData( m_header->patchEntryOffset ); + +#if defined(WIN32) + CLR_Debug::Printf( "Simulating jump into patch code...\r\n" ); +#else + ((void (*)())ptr)(); +#endif + } + +#if defined(NANOCLR_APPDOMAINS) + //Temporary solution. All Assemblies get added to the current AppDomain + //Which assemblies get loaded at boot, and when assemblies get added to AppDomain at runtime is + //not yet determined/implemented + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.GetCurrentAppDomain()->LoadAssembly( this )); +#endif + } + + NANOCLR_CLEANUP(); + + //Only try once. If this fails, then what? + m_flags |= CLR_RT_Assembly::PreparedForExecution; + m_flags &= ~CLR_RT_Assembly::PreparingForExecution; + + NANOCLR_CLEANUP_END(); +} + +//--// + +CLR_UINT32 CLR_RT_Assembly::ComputeAssemblyHash() +{ + NATIVE_PROFILE_CLR_CORE(); + return m_header->ComputeAssemblyHash( m_szName, m_header->version ); +} + +CLR_UINT32 CLR_RT_Assembly::ComputeAssemblyHash( const CLR_RECORD_ASSEMBLYREF* ar ) +{ + NATIVE_PROFILE_CLR_CORE(); + return m_header->ComputeAssemblyHash( GetString( ar->name ), ar->version ); +} + +//--// + +bool CLR_RT_Assembly::FindTypeDef( const char* name, const char* nameSpace, CLR_RT_TypeDef_Index& idx ) +{ + NATIVE_PROFILE_CLR_CORE(); + const CLR_RECORD_TYPEDEF* target = GetTypeDef( 0 ); + int tblSize = m_pTablesSize[ TBL_TypeDef ]; + + for(int i=0; ienclosingType == CLR_EmptyIndex) + { + const char* szNameSpace = GetString( target->nameSpace ); + const char* szName = GetString( target->name ); + + if(!strcmp( szName, name ) && !strcmp( szNameSpace, nameSpace )) + { + idx.Set( m_idx, i ); + + return true; + } + } + } + + idx.Clear(); + + return false; +} + +bool CLR_RT_Assembly::FindTypeDef( const char* name, CLR_IDX scope, CLR_RT_TypeDef_Index& idx ) +{ + NATIVE_PROFILE_CLR_CORE(); + const CLR_RECORD_TYPEDEF* target = GetTypeDef( 0 ); + int tblSize = m_pTablesSize[ TBL_TypeDef ]; + + for(int i=0; ienclosingType == scope) + { + const char* szName = GetString( target->name ); + + if(!strcmp( szName, name )) + { + idx.Set( m_idx, i ); + + return true; + } + } + } + + idx.Clear(); + + return false; +} + +bool CLR_RT_Assembly::FindTypeDef( CLR_UINT32 hash, CLR_RT_TypeDef_Index& idx ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_TypeDef_CrossReference* p = m_pCrossReference_TypeDef; + CLR_UINT32 tblSize = m_pTablesSize[ TBL_TypeDef ]; + CLR_UINT32 i; + + for(i=0; im_hash == hash) break; + } + + if(i != tblSize) + { + idx.Set( m_idx, i ); + + return true; + } + else + { + idx.Clear(); + + return false; + } +} + +//--// + +static bool local_FindFieldDef( CLR_RT_Assembly* assm, CLR_UINT32 first, CLR_UINT32 num, const char* szText, CLR_RT_Assembly* base, CLR_IDX sig, CLR_RT_FieldDef_Index& res ) +{ + NATIVE_PROFILE_CLR_CORE(); + const CLR_RECORD_FIELDDEF* fd = assm->GetFieldDef( first ); + + for(CLR_UINT32 i=0; iGetString( fd->name ); + + if(!strcmp( fieldName, szText )) + { + if(base) + { + CLR_RT_SignatureParser parserLeft ; parserLeft .Initialize_FieldDef( assm, fd ); + CLR_RT_SignatureParser parserRight; parserRight.Initialize_FieldDef( base, base->GetSignature( sig ) ); + + if(CLR_RT_TypeSystem::MatchSignature( parserLeft, parserRight ) == false) continue; + } + + res.Set( assm->m_idx, first + i ); + + return true; + } + } + + res.Clear(); + + return false; +} + +bool CLR_RT_Assembly::FindFieldDef( const CLR_RECORD_TYPEDEF* td, const char* name, CLR_RT_Assembly* base, CLR_IDX sig, CLR_RT_FieldDef_Index& idx ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(local_FindFieldDef( this, td->iFields_First, td->iFields_Num, name, base, sig, idx )) return true; + if(local_FindFieldDef( this, td->sFields_First, td->sFields_Num, name, base, sig, idx )) return true; + + idx.Clear(); + + return false; +} + +bool CLR_RT_Assembly::FindMethodDef( const CLR_RECORD_TYPEDEF* td, const char* name, CLR_RT_Assembly* base, CLR_SIG sig, CLR_RT_MethodDef_Index& idx ) +{ + NATIVE_PROFILE_CLR_CORE(); + int i; + int num = td->vMethods_Num + td->iMethods_Num + td->sMethods_Num; + const CLR_RECORD_METHODDEF* md = GetMethodDef( td->methods_First ); + + for(i=0; iname ); + + if(!strcmp( methodName, name )) + { + bool fMatch = true; + + if(CLR_SIG_INVALID != sig) + { + CLR_RT_SignatureParser parserLeft ; parserLeft .Initialize_MethodSignature( this, md ); + CLR_RT_SignatureParser parserRight; parserRight.Initialize_MethodSignature( base, base->GetSignature( sig ) ); + + fMatch = CLR_RT_TypeSystem::MatchSignature( parserLeft, parserRight ); + } + + if(fMatch) + { + idx.Set( m_idx, i + td->methods_First ); + + return true; + } + } + } + + idx.Clear(); + + return false; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +bool CLR_RT_Assembly::FindMethodBoundaries( CLR_IDX i, CLR_OFFSET& start, CLR_OFFSET& end ) +{ + NATIVE_PROFILE_CLR_CORE(); + const CLR_RECORD_METHODDEF* p = GetMethodDef( i ); + + if(p->RVA == CLR_EmptyIndex) return false; + + start = p->RVA; + + while(true) + { + p++; + i++; + + if(i == m_pTablesSize[ TBL_MethodDef ]) + { + end = m_pTablesSize[ TBL_ByteCode ]; + break; + } + + if(p->RVA != CLR_EmptyIndex) + { + end = p->RVA; + break; + } + } + + return true; +} + +bool CLR_RT_Assembly::FindNextStaticConstructor( CLR_RT_MethodDef_Index& idx ) +{ + NATIVE_PROFILE_CLR_CORE(); + _ASSERTE(m_idx == idx.Assembly()); + + for(int i=idx.Method(); iflags & CLR_RECORD_METHODDEF::MD_StaticConstructor) + { + return true; + } + } + + idx.Clear(); + return false; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +HRESULT CLR_RT_Assembly::Resolve_ComputeHashes() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + const CLR_RECORD_TYPEDEF* src = GetTypeDef( 0 ); + CLR_RT_TypeDef_CrossReference* dst = m_pCrossReference_TypeDef; + + for(int i=0; iGetFieldDef( target->iFields_First ); + + for(int j=0; jiFields_Num; j++, fd++) + { + if((fd->flags & CLR_RECORD_FIELDDEF::FD_NotSerialized) == 0) + { + CLR_RT_SignatureParser parser; parser.Initialize_FieldDef( inst.m_assm, fd ); + CLR_RT_SignatureParser::Element res; + + NANOCLR_CHECK_HRESULT(parser.Advance( res )); + + while(res.m_levels-- > 0) + { + hash = ComputeHashForType( DATATYPE_SZARRAY, hash ); + } + + hash = ComputeHashForType( res.m_dt, hash ); + + if( (res.m_dt == DATATYPE_VALUETYPE) || + (res.m_dt == DATATYPE_CLASS)) + { + hash = ComputeHashForName( res.m_cls, hash ); + } + + const char* fieldName = inst.m_assm->GetString( fd->name ); + + hash = SUPPORT_ComputeCRC( fieldName, (CLR_UINT32)hal_strlen_s(fieldName), hash ); + } + } + + inst.SwitchToParent(); + } + + dst->m_hash = hash ? hash : 0xFFFFFFFF; // Don't allow zero as an hash value!! + } + + NANOCLR_NOCLEANUP(); +} + +CLR_UINT32 CLR_RT_Assembly::ComputeHashForName( const CLR_RT_TypeDef_Index& td, CLR_UINT32 hash ) +{ + NATIVE_PROFILE_CLR_CORE(); + char rgBuffer[ 512 ]; + char* szBuffer = rgBuffer; + size_t iBuffer = MAXSTRLEN(rgBuffer); + + g_CLR_RT_TypeSystem.BuildTypeName( td, szBuffer, iBuffer ); + + CLR_UINT32 hashPost = SUPPORT_ComputeCRC( rgBuffer, (int)(MAXSTRLEN(rgBuffer) - iBuffer), hash ); + + return hashPost; +} + +CLR_UINT32 CLR_RT_Assembly::ComputeHashForType( CLR_DataType et, CLR_UINT32 hash ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_UINT8 val = (CLR_UINT8)CLR_RT_TypeSystem::MapDataTypeToElementType( et ); + + CLR_UINT32 hashPost = SUPPORT_ComputeCRC( &val, sizeof(val), hash ); + + return hashPost; +} + +//--// + +CLR_RT_HeapBlock* CLR_RT_Assembly::GetStaticField( const int index ) +{ + NATIVE_PROFILE_CLR_CORE(); + +#if defined(NANOCLR_APPDOMAINS) + + CLR_RT_AppDomainAssembly* adAssm = g_CLR_RT_ExecutionEngine.GetCurrentAppDomain()->FindAppDomainAssembly( this ); + + _ASSERTE(adAssm); + + return &adAssm->m_pStaticFields[ index ]; + +#else + + return &m_pStaticFields[ index ]; + +#endif +} + +//--// + +void CLR_RT_Assembly::Relocate() +{ + NATIVE_PROFILE_CLR_CORE(); + +#if !defined(NANOCLR_APPDOMAINS) + CLR_RT_GarbageCollector::Heap_Relocate( m_pStaticFields, m_iStaticFields ); +#endif + + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_header ); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_szName ); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_pFile ); + CLR_RT_GarbageCollector::Heap_Relocate( (void**)&m_nativeCode ); +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +void CLR_RT_TypeSystem::TypeSystem_Initialize() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_CLEAR(g_CLR_RT_TypeSystem); + NANOCLR_CLEAR(g_CLR_RT_WellKnownTypes); +} + +void CLR_RT_TypeSystem::TypeSystem_Cleanup() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_ASSEMBLY(*this) + { + pASSM->DestroyInstance(); + + *ppASSM = NULL; + } + NANOCLR_FOREACH_ASSEMBLY_END(); + + m_assembliesMax = 0; +} + +//--// + +void CLR_RT_TypeSystem::Link( CLR_RT_Assembly* assm ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_ASSEMBLY_NULL(*this) + { + *ppASSM = assm; + + assm->m_idx = idx; + + PostLinkageProcessing( assm ); + + if(m_assembliesMax < idx) m_assembliesMax = idx; + + return; + } + NANOCLR_FOREACH_ASSEMBLY_NULL_END(); +} + +void CLR_RT_TypeSystem::PostLinkageProcessing( CLR_RT_Assembly* assm ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(!strcmp( assm->m_szName, "mscorlib" )) + { + m_assemblyMscorlib = assm; + } + if(!strcmp( assm->m_szName, "nanoFramework.Runtime.Native" )) + { + m_assemblyNative = assm; + } +} + +CLR_RT_Assembly* CLR_RT_TypeSystem::FindAssembly( const char* szName, const CLR_RECORD_VERSION* ver, bool fExact ) +{ + NATIVE_PROFILE_CLR_CORE(); + + NANOCLR_FOREACH_ASSEMBLY(*this) + { + if(!strcmp(pASSM->m_szName, szName)) + { + // if there is no version information, anything goes + if(NULL == ver) + { + return pASSM; + } + // exact match must take into accoutn all numbers + else if(fExact) + { + if(0 == memcmp( &pASSM->m_header->version, ver, sizeof(*ver) )) + { + return pASSM; + } + } + // if excet match is not required but still we have version we will enforce only the first two number because by convention + // we increse the minor numbers when native assemblies change CRC + else if( + ver->iMajorVersion == pASSM->m_header->version.iMajorVersion && + ver->iMinorVersion == pASSM->m_header->version.iMinorVersion + ) + { + return pASSM; + } + } + } + NANOCLR_FOREACH_ASSEMBLY_END(); + + return NULL; +} + +bool CLR_RT_TypeSystem::FindTypeDef( const char* name, const char* nameSpace, CLR_RT_Assembly* assm, CLR_RT_TypeDef_Index& res ) +{ + NATIVE_PROFILE_CLR_CORE(); + + if(assm) + { + NANOCLR_FOREACH_ASSEMBLY_IN_CURRENT_APPDOMAIN(*this) + { + if(pASSM->IsSameAssembly( *assm ) && pASSM->FindTypeDef( name, nameSpace, res )) return true; + } + NANOCLR_FOREACH_ASSEMBLY_IN_CURRENT_APPDOMAIN_END(); + + res.Clear(); + + return false; + } + + return FindTypeDef( name, nameSpace, res); +} + +bool CLR_RT_TypeSystem::FindTypeDef( const char* name, const char* nameSpace, CLR_RT_TypeDef_Index& res ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_ASSEMBLY_IN_CURRENT_APPDOMAIN(*this) + { + if(pASSM->FindTypeDef( name, nameSpace, res )) return true; + } + NANOCLR_FOREACH_ASSEMBLY_IN_CURRENT_APPDOMAIN_END(); + + res.Clear(); + return false; +} + +bool CLR_RT_TypeSystem::FindTypeDef( CLR_UINT32 hash, CLR_RT_TypeDef_Index& res ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_FOREACH_ASSEMBLY_IN_CURRENT_APPDOMAIN(*this) + { + if(pASSM->FindTypeDef( hash, res )) return true; + } + NANOCLR_FOREACH_ASSEMBLY_IN_CURRENT_APPDOMAIN_END(); + + res.Clear(); + return false; +} + +bool CLR_RT_TypeSystem::FindTypeDef( const char* szClass, CLR_RT_Assembly* assm, CLR_RT_TypeDef_Index& res ) +{ + (void)szClass; + (void)assm; + (void)res; + + NATIVE_PROFILE_CLR_CORE(); + + char rgName [ MAXTYPENAMELEN ]; + char rgNamespace[ MAXTYPENAMELEN ]; + + if(hal_strlen_s(szClass) < ARRAYSIZE(rgNamespace)) + { + const char* szPtr = szClass; + const char* szPtr_LastDot = NULL; + const char* szPtr_FirstSubType = NULL; + char c; + size_t len; + + while(true) + { + c = szPtr[ 0 ]; if(!c) break; + + if(c == '.') + { + szPtr_LastDot = szPtr; + } + else if(c == '+') + { + szPtr_FirstSubType = szPtr; + break; + } + + szPtr++; + } + + if(szPtr_LastDot) + { + len = szPtr_LastDot++ - szClass ; hal_strncpy_s( rgNamespace, ARRAYSIZE(rgNamespace), szClass , len ); + len = szPtr - szPtr_LastDot; hal_strncpy_s( rgName , ARRAYSIZE(rgName ), szPtr_LastDot, len ); + } + else + { + rgNamespace[ 0 ] = 0; + hal_strcpy_s( rgName, ARRAYSIZE(rgName), szClass ); + } + + + if(FindTypeDef( rgName, rgNamespace, assm, res )) + { + // + // Found the containing type, let's look for the nested type. + // + if(szPtr_FirstSubType) + { + CLR_RT_TypeDef_Instance inst; + + do + { + szPtr = ++szPtr_FirstSubType; + + while(true) + { + c = szPtr_FirstSubType[ 0 ]; if(!c) break; + + if(c == '+') break; + + szPtr_FirstSubType++; + } + + len = szPtr_FirstSubType - szPtr; hal_strncpy_s( rgName, ARRAYSIZE(rgName), szPtr, len ); + + inst.InitializeFromIndex( res ); + + if(inst.m_assm->FindTypeDef( rgName, res.Type(), res ) == false) + { + return false; + } + + } while(c == '+'); + } + + return true; + } + } + + res.Clear(); + + return false; +} + +bool CLR_RT_TypeSystem::FindTypeDef( const char* szClass, CLR_RT_Assembly* assm, CLR_RT_ReflectionDef_Index& reflex ) +{ + (void)szClass; + (void)assm; + (void)reflex; + + NATIVE_PROFILE_CLR_CORE(); + + // UNDONE: FIXME + // char rgName [ MAXTYPENAMELEN ]; + // char rgNamespace[ MAXTYPENAMELEN ]; + // CLR_RT_TypeDef_Index res; + + // if(hal_strlen_s(szClass) < ARRAYSIZE(rgNamespace)) + // { + // const char* szPtr = szClass; + // const char* szPtr_LastDot = NULL; + // const char* szPtr_FirstSubType = NULL; + // char c; + // size_t len; + // bool arrayType = false; + + // while(true) + // { + // c = szPtr[ 0 ]; if(!c) break; + + // if(c == '.') + // { + // szPtr_LastDot = szPtr; + // } + // else if(c == '+') + // { + // szPtr_FirstSubType = szPtr; + // break; + // } + // else if(c == '[') + // { + // char ch = szPtr[ 1 ]; + // if (ch == ']') + // { + // arrayType = true; + // break; + // } + // } + + // szPtr++; + // } + + // if(szPtr_LastDot) + // { + // len = szPtr_LastDot++ - szClass ; hal_strncpy_s( rgNamespace, ARRAYSIZE(rgNamespace), szClass , len ); + // len = szPtr - szPtr_LastDot; hal_strncpy_s( rgName , ARRAYSIZE(rgName ), szPtr_LastDot, len ); + // } + // else + // { + // rgNamespace[ 0 ] = 0; + // hal_strcpy_s( rgName, ARRAYSIZE(rgName), szClass ); + // } + + // if(FindTypeDef( rgName, rgNamespace, assm, res )) + // { + // // + // // Found the containing type, let's look for the nested type. + // // + // if(szPtr_FirstSubType) + // { + // CLR_RT_TypeDef_Instance inst; + + // do + // { + // szPtr = ++szPtr_FirstSubType; + + // while(true) + // { + // c = szPtr_FirstSubType[ 0 ]; if(!c) break; + + // if(c == '+') break; + + // szPtr_FirstSubType++; + // } + + // len = szPtr_FirstSubType - szPtr; hal_strncpy_s( rgName, ARRAYSIZE(rgName), szPtr, len ); + + // inst.InitializeFromIndex( res ); + + // if(inst.m_assm->FindTypeDef( rgName, res.Type(), res ) == false) + // { + // return false; + // } + + // } while(c == '+'); + // } + + // reflex.m_kind = REFLECTION_TYPE; + // // make sure this works for multidimensional arrays. + // reflex.m_levels = arrayType ? 1 : 0; + // reflex.m_data.m_type = res; + // return true; + // } + // } + // + //res.Clear(); + + return false; +} + +//--// + +int +#if defined(_MSC_VER) +__cdecl +#endif +CompareResource( const void* p1, const void* p2 ) +{ + NATIVE_PROFILE_CLR_CORE(); + const CLR_RECORD_RESOURCE* resource1 = (const CLR_RECORD_RESOURCE*)p1; + const CLR_RECORD_RESOURCE* resource2 = (const CLR_RECORD_RESOURCE*)p2; + + return (int)resource1->id - (int)resource2->id; +} + +HRESULT CLR_RT_TypeSystem::LocateResourceFile( CLR_RT_Assembly_Instance assm, const char* name, CLR_INT32& idxResourceFile ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_Assembly* pAssm = assm.m_assm; + + for(idxResourceFile = 0; idxResourceFile < pAssm->m_pTablesSize[ TBL_ResourcesFiles ]; idxResourceFile++) + { + const CLR_RECORD_RESOURCE_FILE* resourceFile = pAssm->GetResourceFile( idxResourceFile ); + + if(!strcmp( pAssm->GetString( resourceFile->name ), name )) + { + NANOCLR_SET_AND_LEAVE(S_OK); + } + } + + idxResourceFile = -1; + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_TypeSystem::LocateResource( CLR_RT_Assembly_Instance assm, CLR_INT32 idxResourceFile, CLR_INT16 id, const CLR_RECORD_RESOURCE*& res, CLR_UINT32& size ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_Assembly* pAssm = assm.m_assm; + const CLR_RECORD_RESOURCE_FILE* resourceFile; + CLR_RECORD_RESOURCE resourceT; + const CLR_RECORD_RESOURCE* resNext; + const CLR_RECORD_RESOURCE* resZero; + + res = NULL; + size = 0; + + if(idxResourceFile < 0 || idxResourceFile >= pAssm->m_pTablesSize[ TBL_ResourcesFiles ]) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + resourceFile = pAssm->GetResourceFile( idxResourceFile ); + + _ASSERTE(resourceFile->numberOfResources > 0); + + resZero = pAssm->GetResource( resourceFile->offset ); + + resourceT.id = id; + + res = (const CLR_RECORD_RESOURCE*)bsearch( &resourceT, resZero, resourceFile->numberOfResources, sizeof(CLR_RECORD_RESOURCE), CompareResource ); + + if(res != NULL) + { + //compute size here... + //assert not the last resource + _ASSERTE(res + 1 <= pAssm->GetResource( pAssm->m_pTablesSize[ TBL_Resources ] - 1)); + resNext = res+1; + + size = resNext->offset - res->offset; + + //deal with alignment. + size -= (resNext->flags & CLR_RECORD_RESOURCE::FLAGS_PaddingMask); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_TypeSystem::ResolveAll() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + bool fOutput = false; + + while(true) + { + bool fGot = false; + bool fNeedResolution = false; + + NANOCLR_FOREACH_ASSEMBLY(*this) + { + if((pASSM->m_flags & CLR_RT_Assembly::Resolved) == 0) + { + fNeedResolution = true; + + if(pASSM->Resolve_AssemblyRef( fOutput )) + { + fGot = true; + + pASSM->m_flags |= CLR_RT_Assembly::Resolved; + + NANOCLR_CHECK_HRESULT(pASSM->Resolve_TypeRef ()); + NANOCLR_CHECK_HRESULT(pASSM->Resolve_FieldRef ()); + NANOCLR_CHECK_HRESULT(pASSM->Resolve_MethodRef ()); + /********************/pASSM->Resolve_TypeDef () ; + /********************/pASSM->Resolve_MethodDef () ; + /********************/pASSM->Resolve_Link () ; + NANOCLR_CHECK_HRESULT(pASSM->Resolve_ComputeHashes ()); + +#if !defined(NANOCLR_APPDOMAINS) + NANOCLR_CHECK_HRESULT(pASSM->Resolve_AllocateStaticFields( pASSM->m_pStaticFields )); +#endif + + pASSM->m_flags |= CLR_RT_Assembly::ResolutionCompleted; + } + } + } + NANOCLR_FOREACH_ASSEMBLY_END(); + + if(fOutput == true) + { + NANOCLR_SET_AND_LEAVE(CLR_E_TYPE_UNAVAILABLE); + } + + if(fGot == false) + { + if(fNeedResolution) + { +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Link failure: some assembly references cannot be resolved!!\r\n\r\n" ); +#endif + + fOutput = true; + } + else + { + break; + } + } + } + +#if !defined(BUILD_RTM) + + if(s_CLR_RT_fTrace_AssemblyOverhead >= c_CLR_RT_Trace_Info) + { + { + int pTablesSize[ TBL_Max ]; memset( pTablesSize, 0, sizeof(pTablesSize) ); + CLR_RT_Assembly::Offsets offsets ; memset( &offsets , 0, sizeof(offsets ) ); + + size_t iStaticFields = 0 ; + size_t iTotalRamSize = 0 ; + size_t iTotalRomSize = 0 ; + size_t iMetaData = 0 ; + + NANOCLR_FOREACH_ASSEMBLY(*this) + { + offsets.iBase += ROUNDTOMULTIPLE(sizeof(CLR_RT_Assembly) , CLR_UINT32); + offsets.iAssemblyRef += ROUNDTOMULTIPLE(pASSM->m_pTablesSize[ TBL_AssemblyRef ] * sizeof(CLR_RT_AssemblyRef_CrossReference), CLR_UINT32); + offsets.iTypeRef += ROUNDTOMULTIPLE(pASSM->m_pTablesSize[ TBL_TypeRef ] * sizeof(CLR_RT_TypeRef_CrossReference ), CLR_UINT32); + offsets.iFieldRef += ROUNDTOMULTIPLE(pASSM->m_pTablesSize[ TBL_FieldRef ] * sizeof(CLR_RT_FieldRef_CrossReference ), CLR_UINT32); + offsets.iMethodRef += ROUNDTOMULTIPLE(pASSM->m_pTablesSize[ TBL_MethodRef ] * sizeof(CLR_RT_MethodRef_CrossReference ), CLR_UINT32); + offsets.iTypeDef += ROUNDTOMULTIPLE(pASSM->m_pTablesSize[ TBL_TypeDef ] * sizeof(CLR_RT_TypeDef_CrossReference ), CLR_UINT32); + offsets.iFieldDef += ROUNDTOMULTIPLE(pASSM->m_pTablesSize[ TBL_FieldDef ] * sizeof(CLR_RT_FieldDef_CrossReference ), CLR_UINT32); + offsets.iMethodDef += ROUNDTOMULTIPLE(pASSM->m_pTablesSize[ TBL_MethodDef ] * sizeof(CLR_RT_MethodDef_CrossReference ), CLR_UINT32); + +#if !defined(NANOCLR_APPDOMAINS) + offsets.iStaticFields += ROUNDTOMULTIPLE(pASSM->m_iStaticFields * sizeof(CLR_RT_HeapBlock ), CLR_UINT32); +#endif + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + offsets.iDebuggingInfoMethods += ROUNDTOMULTIPLE(pASSM->m_pTablesSize[ TBL_MethodDef ] * sizeof(CLR_RT_MethodDef_DebuggingInfo ), CLR_UINT32); +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + iMetaData += pASSM->m_header->SizeOfTable( TBL_AssemblyRef ) + + pASSM->m_header->SizeOfTable( TBL_TypeRef ) + + pASSM->m_header->SizeOfTable( TBL_FieldRef ) + + pASSM->m_header->SizeOfTable( TBL_MethodRef ) + + pASSM->m_header->SizeOfTable( TBL_TypeDef ) + + pASSM->m_header->SizeOfTable( TBL_FieldDef ) + + pASSM->m_header->SizeOfTable( TBL_MethodDef ) + + pASSM->m_header->SizeOfTable( TBL_Attributes ) + + pASSM->m_header->SizeOfTable( TBL_TypeSpec ) + + pASSM->m_header->SizeOfTable( TBL_Signatures ); + + for(int tbl=0; tblm_pTablesSize[ tbl ]; + } + + iTotalRomSize += pASSM->m_header->TotalSize(); + + iStaticFields += pASSM->m_iStaticFields; + } + NANOCLR_FOREACH_ASSEMBLY_END(); + + iTotalRamSize = offsets.iBase + + offsets.iAssemblyRef + + offsets.iTypeRef + + offsets.iFieldRef + + offsets.iMethodRef + + offsets.iTypeDef + + offsets.iFieldDef + + offsets.iMethodDef; + +#if !defined(NANOCLR_APPDOMAINS) + iTotalRamSize += offsets.iStaticFields; +#endif + + CLR_Debug::Printf( "\r\nTotal: (%d RAM - %d ROM - %d METADATA)\r\n\r\n", iTotalRamSize, iTotalRomSize, iMetaData ); + + CLR_Debug::Printf( " AssemblyRef = %8d bytes (%8d elements)\r\n", offsets.iAssemblyRef , pTablesSize[TBL_AssemblyRef] ); + CLR_Debug::Printf( " TypeRef = %8d bytes (%8d elements)\r\n", offsets.iTypeRef , pTablesSize[TBL_TypeRef ] ); + CLR_Debug::Printf( " FieldRef = %8d bytes (%8d elements)\r\n", offsets.iFieldRef , pTablesSize[TBL_FieldRef ] ); + CLR_Debug::Printf( " MethodRef = %8d bytes (%8d elements)\r\n", offsets.iMethodRef , pTablesSize[TBL_MethodRef ] ); + CLR_Debug::Printf( " TypeDef = %8d bytes (%8d elements)\r\n", offsets.iTypeDef , pTablesSize[TBL_TypeDef ] ); + CLR_Debug::Printf( " FieldDef = %8d bytes (%8d elements)\r\n", offsets.iFieldDef , pTablesSize[TBL_FieldDef ] ); + CLR_Debug::Printf( " MethodDef = %8d bytes (%8d elements)\r\n", offsets.iMethodDef , pTablesSize[TBL_MethodDef ] ); + +#if !defined(NANOCLR_APPDOMAINS) + CLR_Debug::Printf( " StaticFields = %8d bytes (%8d elements)\r\n", offsets.iStaticFields , iStaticFields ); +#endif + + CLR_Debug::Printf( "\r\n" ); + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + CLR_Debug::Printf( " DebuggingInfo = %8d bytes\r\n", offsets.iDebuggingInfoMethods ); + CLR_Debug::Printf( "\r\n" ); +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + CLR_Debug::Printf( " Attributes = %8d bytes (%8d elements)\r\n", pTablesSize[ TBL_Attributes ] * sizeof(CLR_RECORD_ATTRIBUTE ), pTablesSize[ TBL_Attributes ] ); + CLR_Debug::Printf( " TypeSpec = %8d bytes (%8d elements)\r\n", pTablesSize[ TBL_TypeSpec ] * sizeof(CLR_RECORD_TYPESPEC ), pTablesSize[ TBL_TypeSpec ] ); + CLR_Debug::Printf( " Resources Files = %8d bytes (%8d elements)\r\n", pTablesSize[ TBL_ResourcesFiles ] * sizeof(CLR_RECORD_RESOURCE_FILE ), pTablesSize[ TBL_ResourcesFiles ] ); + CLR_Debug::Printf( " Resources = %8d bytes (%8d elements)\r\n", pTablesSize[ TBL_Resources ] * sizeof(CLR_RECORD_RESOURCE ), pTablesSize[ TBL_Resources ] ); + CLR_Debug::Printf( " Resources Data = %8d bytes\r\n" , pTablesSize[ TBL_ResourcesData ] ); + CLR_Debug::Printf( " Strings = %8d bytes\r\n" , pTablesSize[ TBL_Strings ] ); + CLR_Debug::Printf( " Signatures = %8d bytes\r\n" , pTablesSize[ TBL_Signatures ] ); + CLR_Debug::Printf( " ByteCode = %8d bytes\r\n" , pTablesSize[ TBL_ByteCode ] ); + CLR_Debug::Printf( "\r\n\r\n" ); + } + } + +#endif + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_TypeSystem::PrepareForExecutionHelper( const char* szAssembly ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_FOREACH_ASSEMBLY(*this) + { + if(!strcmp( szAssembly, pASSM->m_szName )) + { + NANOCLR_CHECK_HRESULT(pASSM->PrepareForExecution()); + } + } + + NANOCLR_FOREACH_ASSEMBLY_END(); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_TypeSystem::PrepareForExecution() +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + CLR_EE_DBG_SET(BreakpointsDisabled); +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + +#if !defined(NANOCLR_APPDOMAINS) + if(g_CLR_RT_ExecutionEngine.m_outOfMemoryException == NULL) + { + CLR_RT_HeapBlock exception; + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex( exception, g_CLR_RT_WellKnownTypes.m_OutOfMemoryException )); + + g_CLR_RT_ExecutionEngine.m_outOfMemoryException = exception.Dereference(); + } +#endif + + // Load Runtime.Events to setup EventSink for other assemblies using it + NANOCLR_CHECK_HRESULT(PrepareForExecutionHelper( "nanoFramework.Runtime.Events" )); + + // Load Runtime.Native for other assemblies using it + NANOCLR_CHECK_HRESULT(PrepareForExecutionHelper( "nanoFramework.Runtime.Native" )); + + NANOCLR_FOREACH_ASSEMBLY(*this) + { + NANOCLR_CHECK_HRESULT(pASSM->PrepareForExecution()); + } + NANOCLR_FOREACH_ASSEMBLY_END(); + + NANOCLR_CLEANUP(); + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + CLR_EE_DBG_CLR(BreakpointsDisabled); + + g_CLR_RT_ExecutionEngine.Breakpoint_Assemblies_Loaded(); +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + NANOCLR_CLEANUP_END(); +} + +//--// + +bool CLR_RT_TypeSystem::MatchSignature( CLR_RT_SignatureParser& parserLeft, CLR_RT_SignatureParser& parserRight ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(parserLeft.m_type != parserRight.m_type ) return false; + if(parserLeft.m_flags != parserRight.m_flags) return false; + + return MatchSignatureDirect( parserLeft, parserRight, false ); +} + +bool CLR_RT_TypeSystem::MatchSignatureDirect( CLR_RT_SignatureParser& parserLeft, CLR_RT_SignatureParser& parserRight, bool fIsInstanceOfOK ) +{ + NATIVE_PROFILE_CLR_CORE(); + while(true) + { + int iAvailLeft = parserLeft .Available(); + int iAvailRight = parserRight.Available(); + + if(iAvailLeft != iAvailRight) return false; + + if(!iAvailLeft) return true; + + CLR_RT_SignatureParser::Element resLeft; if(FAILED(parserLeft .Advance( resLeft ))) return false; + CLR_RT_SignatureParser::Element resRight; if(FAILED(parserRight.Advance( resRight ))) return false; + + if(!MatchSignatureElement( resLeft, resRight, fIsInstanceOfOK )) return false; + } + + return true; +} + +bool CLR_RT_TypeSystem::MatchSignatureElement( CLR_RT_SignatureParser::Element& resLeft, CLR_RT_SignatureParser::Element& resRight, bool fIsInstanceOfOK ) +{ + NATIVE_PROFILE_CLR_CORE(); + if(fIsInstanceOfOK) + { + CLR_RT_ReflectionDef_Index idxLeft ; CLR_RT_TypeDescriptor descLeft; + CLR_RT_ReflectionDef_Index idxRight; CLR_RT_TypeDescriptor descRight; + + idxLeft.m_kind = REFLECTION_TYPE; + idxLeft.m_levels = resLeft.m_levels; + idxLeft.m_data.m_type = resLeft.m_cls; + + idxRight.m_kind = REFLECTION_TYPE; + idxRight.m_levels = resRight.m_levels; + idxRight.m_data.m_type = resRight.m_cls; + + if(FAILED(descLeft .InitializeFromReflection( idxLeft ))) return false; + if(FAILED(descRight.InitializeFromReflection( idxRight ))) return false; + + if(!CLR_RT_ExecutionEngine::IsInstanceOf( descRight, descLeft )) return false; + } + else + { + if(resLeft.m_fByRef != resRight.m_fByRef ) return false; + if(resLeft.m_levels != resRight.m_levels ) return false; + if(resLeft.m_dt != resRight.m_dt ) return false; + if(resLeft.m_cls.m_data != resRight.m_cls.m_data) return false; + } + + return true; +} + +//--// + +HRESULT CLR_RT_TypeSystem::QueueStringToBuffer( char*& szBuffer, size_t& iBuffer, const char* szText ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(szText) + { + if(CLR_SafeSprintf( szBuffer, iBuffer, "%s", szText ) == false) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + } + else + { + szBuffer[ 0 ] = 0; + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_TypeSystem::BuildTypeName( const CLR_RT_TypeDef_Index& cls, char*& szBuffer, size_t& iBuffer ) +{ + NATIVE_PROFILE_CLR_CORE(); + return BuildTypeName( cls, szBuffer, iBuffer, CLR_RT_TypeSystem::TYPENAME_FLAGS_FULL, 0 ); +} + +HRESULT CLR_RT_TypeSystem::BuildTypeName ( const CLR_RT_TypeDef_Index& cls, char*& szBuffer, size_t& iBuffer, CLR_UINT32 flags, CLR_UINT32 levels ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Instance inst; + CLR_RT_Assembly* assm; + const CLR_RECORD_TYPEDEF* td; + bool fFullName; + + if(inst.InitializeFromIndex( cls ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + assm = inst.m_assm; + td = inst.m_target; + fFullName = flags & CLR_RT_TypeSystem::TYPENAME_FLAGS_FULL; + + if(fFullName && td->enclosingType != CLR_EmptyIndex) + { + CLR_RT_TypeDef_Index clsSub; clsSub.Set( inst.Assembly(), td->enclosingType ); + + NANOCLR_CHECK_HRESULT(BuildTypeName( clsSub, szBuffer, iBuffer, flags, 0 )); + + NANOCLR_CHECK_HRESULT(QueueStringToBuffer( szBuffer, iBuffer, (flags & CLR_RT_TypeSystem::TYPENAME_NESTED_SEPARATOR_DOT) ? "." : "+" )); + } + + if(fFullName && td->nameSpace != CLR_EmptyIndex) + { + const char* szNameSpace = assm->GetString( td->nameSpace ); + + if(szNameSpace[ 0 ]) + { + NANOCLR_CHECK_HRESULT(QueueStringToBuffer( szBuffer, iBuffer, szNameSpace )); + NANOCLR_CHECK_HRESULT(QueueStringToBuffer( szBuffer, iBuffer, "." )); + } + } + + NANOCLR_CHECK_HRESULT(QueueStringToBuffer( szBuffer, iBuffer, assm->GetString( td->name ) )); + + while(levels-- > 0) + { + NANOCLR_CHECK_HRESULT(QueueStringToBuffer( szBuffer, iBuffer, "[]" )); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_TypeSystem::BuildMethodName( const CLR_RT_MethodDef_Index& md, char*& szBuffer, size_t& iBuffer ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_MethodDef_Instance inst; + CLR_RT_TypeDef_Instance instOwner; + + if(inst .InitializeFromIndex ( md ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + if(instOwner.InitializeFromMethod( inst ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + NANOCLR_CHECK_HRESULT(BuildTypeName( instOwner, szBuffer, iBuffer )); + + CLR_SafeSprintf( szBuffer, iBuffer, "::%s", inst.m_assm->GetString( inst.m_target->name ) ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_TypeSystem::BuildFieldName( const CLR_RT_FieldDef_Index& fd, char*& szBuffer, size_t& iBuffer ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_FieldDef_Instance inst; + CLR_RT_TypeDef_Instance instOwner; + + if(inst .InitializeFromIndex( fd ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + if(instOwner.InitializeFromField( inst ) == false) NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + + NANOCLR_CHECK_HRESULT(BuildTypeName( instOwner, szBuffer, iBuffer )); + + CLR_SafeSprintf( szBuffer, iBuffer, "::%s", inst.m_assm->GetString( inst.m_target->name ) ); + + NANOCLR_NOCLEANUP(); +} + +//--// + +bool CLR_RT_TypeSystem::FindVirtualMethodDef( const CLR_RT_TypeDef_Index& cls, const CLR_RT_MethodDef_Index& calleeMD, CLR_RT_MethodDef_Index& idx ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_MethodDef_Instance calleeInst; + + if(calleeInst.InitializeFromIndex( calleeMD )) + { + const char* calleeName = calleeInst.m_assm->GetString( calleeInst.m_target->name ); + + CLR_RT_TypeDef_Instance inst; inst.InitializeFromMethod( calleeInst ); + + if((inst.m_target->flags & CLR_RECORD_TYPEDEF::TD_Semantics_Mask) == CLR_RECORD_TYPEDEF::TD_Semantics_Interface) + { + // + // It's an interface method, it could be that the class is implementing explicitly the method. + // Prepend the Interface name to the method name and try again. + // + char rgBuffer[ 512 ]; + char* szBuffer = rgBuffer; + size_t iBuffer = MAXSTRLEN(rgBuffer); + + BuildTypeName ( inst, szBuffer, iBuffer, CLR_RT_TypeSystem::TYPENAME_FLAGS_FULL | CLR_RT_TypeSystem::TYPENAME_NESTED_SEPARATOR_DOT, 0 ); + QueueStringToBuffer( szBuffer, iBuffer, "." ); + QueueStringToBuffer( szBuffer, iBuffer, calleeName ); + + if(FindVirtualMethodDef( cls, calleeMD, rgBuffer, idx )) return true; + } + + if(FindVirtualMethodDef( cls, calleeMD, calleeName, idx )) return true; + } + + idx.Clear(); + + return false; +} + +bool CLR_RT_TypeSystem::FindVirtualMethodDef( const CLR_RT_TypeDef_Index& cls, const CLR_RT_MethodDef_Index& calleeMD, const char* calleeName, CLR_RT_MethodDef_Index& idx ) +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_RT_TypeDef_Instance clsInst ; clsInst .InitializeFromIndex( cls ); + CLR_RT_MethodDef_Instance calleeInst; calleeInst.InitializeFromIndex( calleeMD ); + + CLR_RT_Assembly* calleeAssm = calleeInst.m_assm; + const CLR_RECORD_METHODDEF* calleeMDR = calleeInst.m_target; + CLR_UINT8 calleeNumArgs = calleeMDR->numArgs; + + while(NANOCLR_INDEX_IS_VALID(clsInst)) + { + CLR_RT_Assembly* targetAssm = clsInst.m_assm; + const CLR_RECORD_TYPEDEF* targetTDR = clsInst.m_target; + const CLR_RECORD_METHODDEF* targetMDR = targetAssm->GetMethodDef( targetTDR->methods_First ); + int num = targetTDR->vMethods_Num + targetTDR->iMethods_Num; + + for(int i=0; inumArgs == calleeNumArgs && (targetMDR->flags & CLR_RECORD_METHODDEF::MD_Abstract) == 0) + { + const char* targetName = targetAssm->GetString( targetMDR->name ); + + if(!strcmp( targetName, calleeName )) + { + CLR_RT_SignatureParser parserLeft ; parserLeft .Initialize_MethodSignature( calleeAssm, calleeMDR ); + CLR_RT_SignatureParser parserRight; parserRight.Initialize_MethodSignature( targetAssm, targetMDR ); + + if(CLR_RT_TypeSystem::MatchSignature( parserLeft, parserRight )) + { + idx.Set( targetAssm->m_idx, i + targetTDR->methods_First ); + + return true; + } + } + } + } + + clsInst.SwitchToParent(); + } + + idx.Clear(); + + return false; +} + +CLR_DataType CLR_RT_TypeSystem::MapElementTypeToDataType( CLR_UINT32 et ) +{ + NATIVE_PROFILE_CLR_CORE(); + const CLR_RT_DataTypeLookup* ptr = c_CLR_RT_DataTypeLookup; + + for(CLR_UINT32 num = 0; numm_convertToElementType == et) return (CLR_DataType)num; + } + + if(et == ELEMENT_TYPE_I) return DATATYPE_I4; + if(et == ELEMENT_TYPE_U) return DATATYPE_U4; + + return DATATYPE_FIRST_INVALID; +} + +CLR_UINT32 CLR_RT_TypeSystem::MapDataTypeToElementType( CLR_DataType dt ) +{ + NATIVE_PROFILE_CLR_CORE(); + return c_CLR_RT_DataTypeLookup[ dt ].m_convertToElementType; +} + +//--// + +void CLR_RT_AttributeEnumerator::Initialize( CLR_RT_Assembly* assm ) +{ + NATIVE_PROFILE_CLR_CORE(); + m_assm = assm; // CLR_RT_Assembly* m_assm; + m_ptr = NULL; // const CLR_RECORD_ATTRIBUTE* m_ptr; + m_num = 0; // int m_num; + // CLR_RECORD_ATTRIBUTE m_data; + m_match.Clear(); // CLR_RT_MethodDef_Index m_match; +} + +void CLR_RT_AttributeEnumerator::Initialize( const CLR_RT_TypeDef_Instance& inst ) +{ + NATIVE_PROFILE_CLR_CORE(); + m_data.ownerType = TBL_TypeDef; + m_data.ownerIdx = inst.Type(); + + Initialize( inst.m_assm ); +} + +void CLR_RT_AttributeEnumerator::Initialize( const CLR_RT_FieldDef_Instance& inst ) +{ + NATIVE_PROFILE_CLR_CORE(); + m_data.ownerType = TBL_FieldDef; + m_data.ownerIdx = inst.Field(); + + Initialize( inst.m_assm ); +} + +void CLR_RT_AttributeEnumerator::Initialize( const CLR_RT_MethodDef_Instance& inst ) +{ + NATIVE_PROFILE_CLR_CORE(); + m_data.ownerType = TBL_MethodDef; + m_data.ownerIdx = inst.Method(); + + Initialize( inst.m_assm ); +} + +bool CLR_RT_AttributeEnumerator::Advance() +{ + NATIVE_PROFILE_CLR_CORE(); + const CLR_RECORD_ATTRIBUTE* ptr = m_ptr; + int num = m_num; + CLR_UINT32 key = m_data.Key(); + bool fRes = false; + + if(ptr == NULL) + { + ptr = m_assm->GetAttribute( 0 ) - 1; + num = m_assm->m_pTablesSize[ TBL_Attributes ]; + } + + while(num) + { + ptr++; + num--; + + if(ptr->Key() == key) + { + CLR_IDX tk = ptr->constructor; + if(tk & 0x8000) + { + m_match = m_assm->m_pCrossReference_MethodRef[ tk & 0x7FFF ].m_target; + } + else + { + m_match.Set( m_assm->m_idx, tk ); + } + + m_blob = m_assm->GetSignature( ptr->data ); + + fRes = true; + break; + } + } + + m_ptr = ptr; + m_num = num; + + return fRes; +} + +void CLR_RT_AttributeEnumerator::GetCurrent( CLR_RT_TypeDef_Instance* instTD ) +{ + CLR_RT_MethodDef_Instance md; + + md.InitializeFromIndex ( m_match ); + instTD->InitializeFromMethod( md ); +} + +bool CLR_RT_AttributeEnumerator::MatchNext( const CLR_RT_TypeDef_Instance* instTD, const CLR_RT_MethodDef_Instance* instMD ) +{ + NATIVE_PROFILE_CLR_CORE(); + while(Advance()) + { + if(instMD) + { + if(m_match.m_data != instMD->m_data) continue; + } + + if(instTD) + { + CLR_RT_MethodDef_Instance md; + CLR_RT_TypeDef_Instance td; + + md.InitializeFromIndex ( m_match ); + td.InitializeFromMethod( md ); + + if(td.m_data != instTD->m_data) continue; + } + + return true; + } + + return false; +} + +//--// + +HRESULT CLR_RT_AttributeParser::Initialize( const CLR_RT_AttributeEnumerator& en ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(m_md.InitializeFromIndex ( en.m_match ) == false || + m_td.InitializeFromMethod( m_md ) == false ) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + m_parser.Initialize_MethodSignature( m_md.m_assm, m_md.m_target ); + m_parser.Advance( m_res ); // Skip return value. + + m_assm = en.m_assm; + m_blob = en.m_blob; + + m_currentPos = 0; + m_fixed_Count = m_md.m_target->numArgs - 1; + m_named_Count = -1; + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_AttributeParser::Next( Value*& res ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if(m_currentPos == m_fixed_Count) + { + NANOCLR_READ_UNALIGNED_UINT16(m_named_Count,m_blob); + } + + if(m_currentPos < m_fixed_Count) + { + m_lastValue.m_mode = Value::c_ConstructorArgument; + m_lastValue.m_name = NULL; + + // + // attribute contructor support is currently not implemented + // + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + } + else if(m_currentPos < m_fixed_Count + m_named_Count) + { + CLR_UINT32 kind; NANOCLR_READ_UNALIGNED_UINT8(kind,m_blob); + + m_lastValue.m_name = GetString(); + + if(kind == SERIALIZATION_TYPE_FIELD) + { + CLR_RT_FieldDef_Index fd; + CLR_RT_FieldDef_Instance inst; + + m_lastValue.m_mode = Value::c_NamedField; + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.FindFieldDef( m_td, m_lastValue.m_name, fd )); + + inst.InitializeFromIndex( fd ); + + m_parser.Initialize_FieldDef( inst.m_assm, inst.m_target ); + } + else + { + m_lastValue.m_mode = Value::c_NamedProperty; + + // + //attribute contructor support is currently not implemented + // + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + } + } + else + { + res = NULL; + NANOCLR_SET_AND_LEAVE(S_OK); + } + + + NANOCLR_CHECK_HRESULT(m_parser.Advance( m_res )); + + res = &m_lastValue; + + // + // Check for Enums. + // + if(m_res.m_dt == DATATYPE_VALUETYPE) + { + CLR_RT_TypeDef_Instance td; td.InitializeFromIndex( m_res.m_cls ); + + if((td.m_target->flags & CLR_RECORD_TYPEDEF::TD_Semantics_Mask) == CLR_RECORD_TYPEDEF::TD_Semantics_Enum) + { + m_res.m_dt = (CLR_DataType)td.m_target->dataType; + } + } + + // + // Skip value info. + // + m_blob += sizeof(CLR_UINT8); + + { + const CLR_RT_DataTypeLookup& dtl = c_CLR_RT_DataTypeLookup[ m_res.m_dt ]; + + if(dtl.m_flags & CLR_RT_DataTypeLookup::c_Numeric) + { + m_lastValue.m_value.SetDataId( CLR_RT_HEAPBLOCK_RAW_ID(m_res.m_dt, 0, 1) ); + + CLR_UINT32 size = (dtl.m_sizeInBits + 7) / 8; + +// FIXME GJS - the numeric values, what is their endiannes??? In the MSTV code there is a BIG endian fix but it looks like it will not work, so was it ever used? + memcpy( &m_lastValue.m_value.NumericByRef(), m_blob, size ); m_blob += size; + } + else if(m_res.m_dt == DATATYPE_STRING) + { + CLR_UINT32 tk; NANOCLR_READ_UNALIGNED_UINT16(tk,m_blob); + + CLR_RT_HeapBlock_String::CreateInstance( m_lastValue.m_value, CLR_TkFromType( TBL_Strings, tk ), m_assm ); + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + } + + m_lastValue.m_pos = m_currentPos++; + + NANOCLR_NOCLEANUP(); +} + +const char* CLR_RT_AttributeParser::GetString() +{ + NATIVE_PROFILE_CLR_CORE(); + CLR_UINT32 tk; NANOCLR_READ_UNALIGNED_UINT16(tk,m_blob); + + return m_assm->GetString( tk ); +} + diff --git a/source/native/nf-interpreter/src/CLR/Core/TypeSystemLookup.cpp b/source/native/nf-interpreter/src/CLR/Core/TypeSystemLookup.cpp new file mode 100644 index 00000000..7be8e054 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/TypeSystemLookup.cpp @@ -0,0 +1,1774 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" +#include "corhdr_private.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#define DT_NA CLR_RT_DataTypeLookup::c_NA +#define DT_VS CLR_RT_DataTypeLookup::c_VariableSize + +#define DT_PRIM CLR_RT_DataTypeLookup::c_Primitive +#define DT_ITF CLR_RT_DataTypeLookup::c_Interface +#define DT_CLASS CLR_RT_DataTypeLookup::c_Class +#define DT_VALUE CLR_RT_DataTypeLookup::c_ValueType +#define DT_ENUM CLR_RT_DataTypeLookup::c_Enum + +#define DT_ARRAY CLR_RT_DataTypeLookup::c_Array +#define DT_ARLST CLR_RT_DataTypeLookup::c_ArrayList + +#define DT_REF CLR_RT_DataTypeLookup::c_Reference +#define DT_NUM CLR_RT_DataTypeLookup::c_Numeric +#define DT_INT CLR_RT_DataTypeLookup::c_Integer +#define DT_SGN CLR_RT_DataTypeLookup::c_Signed +#define DT_DIR CLR_RT_DataTypeLookup::c_Direct +#define DT_OPT CLR_RT_DataTypeLookup::c_OptimizedValueType +#define DT_MT CLR_RT_DataTypeLookup::c_ManagedType + +#define DT_U1 sizeof(CLR_UINT8) +#define DT_I1 sizeof(CLR_INT8) +#define DT_U2 sizeof(CLR_UINT16) +#define DT_I2 sizeof(CLR_INT16) +#define DT_U4 sizeof(CLR_UINT32) +#define DT_I4 sizeof(CLR_INT32) +#define DT_U8 sizeof(CLR_UINT64) +#define DT_I8 sizeof(CLR_INT64) +#define DT_BL sizeof(CLR_RT_HeapBlock) + +#define DT_T(x) (CLR_UINT8)DATATYPE_##x +#define DT_CNV(x) (CLR_UINT8)ELEMENT_TYPE_##x +#define DT_CLS(x) &g_CLR_RT_WellKnownTypes.x + +#define DT_NOREL(x) NULL +#define DT_REL(x) (CLR_RT_HeapBlockRelocate)&x + +#if defined(WIN32) || defined(NANOCLR_TRACE_MEMORY_STATS) +#define DT_OPT_NAME(x) , #x +#else +#define DT_OPT_NAME(x) +#endif + +#define DATATYPE_NOT_SUPPORTED { DT_NA, DT_NA, DT_NA, DT_T(FIRST_INVALID), DT_CNV(END), NULL, DT_NOREL(CLR_RT_HeapBlock) DT_OPT_NAME(NOT_SUPPORTED) }, + +const CLR_RT_DataTypeLookup c_CLR_RT_DataTypeLookup[] = +{ +//// m_flags, m_sizeInBits, m_sizeInBytes, m_promoteTo, m_convertToElementType, m_cls, m_relocate, m_name +//// +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + { DT_NA , DT_NA, DT_NA, DT_T(VOID ), DT_CNV(VOID ), NULL , DT_NOREL(CLR_RT_HeapBlock ) DT_OPT_NAME(VOID ) }, // DATATYPE_VOID + // + { DT_NUM | DT_INT | DT_PRIM | DT_DIR | DT_OPT | DT_MT, 1, DT_U1, DT_T(I4 ), DT_CNV(BOOLEAN ), DT_CLS(m_Boolean ), DT_NOREL(CLR_RT_HeapBlock ) DT_OPT_NAME(BOOLEAN ) }, // DATATYPE_BOOLEAN + { DT_NUM | DT_INT | DT_SGN | DT_PRIM | DT_DIR | DT_OPT | DT_MT, 8, DT_I1, DT_T(I4 ), DT_CNV(I1 ), DT_CLS(m_Int8 ), DT_NOREL(CLR_RT_HeapBlock ) DT_OPT_NAME(I1 ) }, // DATATYPE_I1 + { DT_NUM | DT_INT | DT_PRIM | DT_DIR | DT_OPT | DT_MT, 8, DT_U1, DT_T(I4 ), DT_CNV(U1 ), DT_CLS(m_UInt8 ), DT_NOREL(CLR_RT_HeapBlock ) DT_OPT_NAME(U1 ) }, // DATATYPE_U1 + // + { DT_NUM | DT_INT | DT_PRIM | DT_DIR | DT_OPT | DT_MT, 16, DT_U2, DT_T(I4 ), DT_CNV(CHAR ), DT_CLS(m_Char ), DT_NOREL(CLR_RT_HeapBlock ) DT_OPT_NAME(char ) }, // DATATYPE_CHAR + { DT_NUM | DT_INT | DT_SGN | DT_PRIM | DT_DIR | DT_OPT | DT_MT, 16, DT_I2, DT_T(I4 ), DT_CNV(I2 ), DT_CLS(m_Int16 ), DT_NOREL(CLR_RT_HeapBlock ) DT_OPT_NAME(I2 ) }, // DATATYPE_I2 + { DT_NUM | DT_INT | DT_PRIM | DT_DIR | DT_OPT | DT_MT, 16, DT_U2, DT_T(I4 ), DT_CNV(U2 ), DT_CLS(m_UInt16 ), DT_NOREL(CLR_RT_HeapBlock ) DT_OPT_NAME(U2 ) }, // DATATYPE_U2 + // + { DT_NUM | DT_INT | DT_SGN | DT_PRIM | DT_DIR | DT_OPT | DT_MT, 32, DT_I4, DT_T(I4 ), DT_CNV(I4 ), DT_CLS(m_Int32 ), DT_NOREL(CLR_RT_HeapBlock ) DT_OPT_NAME(I4 ) }, // DATATYPE_I4 + { DT_NUM | DT_INT | DT_PRIM | DT_DIR | DT_OPT | DT_MT, 32, DT_U4, DT_T(I4 ), DT_CNV(U4 ), DT_CLS(m_UInt32 ), DT_NOREL(CLR_RT_HeapBlock ) DT_OPT_NAME(U4 ) }, // DATATYPE_U4 + { DT_NUM | DT_SGN | DT_PRIM | DT_DIR | DT_OPT | DT_MT, 32, DT_I4, DT_T(R4 ), DT_CNV(R4 ), DT_CLS(m_Single ), DT_NOREL(CLR_RT_HeapBlock ) DT_OPT_NAME(R4 ) }, // DATATYPE_R4 + // + { DT_NUM | DT_INT | DT_SGN | DT_PRIM | DT_DIR | DT_OPT | DT_MT, 64, DT_I8, DT_T(I8 ), DT_CNV(I8 ), DT_CLS(m_Int64 ), DT_NOREL(CLR_RT_HeapBlock ) DT_OPT_NAME(I8 ) }, // DATATYPE_I8 + { DT_NUM | DT_INT | DT_PRIM | DT_DIR | DT_OPT | DT_MT, 64, DT_U8, DT_T(I8 ), DT_CNV(U8 ), DT_CLS(m_UInt64 ), DT_NOREL(CLR_RT_HeapBlock ) DT_OPT_NAME(U8 ) }, // DATATYPE_U8 + { DT_NUM | DT_SGN | DT_PRIM | DT_DIR | DT_OPT | DT_MT, 64, DT_I8, DT_T(R8 ), DT_CNV(R8 ), DT_CLS(m_Double ), DT_NOREL(CLR_RT_HeapBlock ) DT_OPT_NAME(R8 ) }, // DATATYPE_R8 + { DT_INT | DT_SGN | DT_VALUE | DT_DIR | DT_OPT | DT_MT, 64, DT_BL, DT_T(DATETIME ), DT_CNV(END ), DT_CLS(m_DateTime ), DT_NOREL(CLR_RT_HeapBlock ) DT_OPT_NAME(DATETIME ) }, // DATATYPE_DATETIME + { DT_INT | DT_SGN | DT_VALUE | DT_DIR | DT_OPT | DT_MT, 64, DT_BL, DT_T(TIMESPAN ), DT_CNV(END ), DT_CLS(m_TimeSpan ), DT_NOREL(CLR_RT_HeapBlock ) DT_OPT_NAME(TIMESPAN ) }, // DATATYPE_TIMESPAN + { DT_REF | DT_PRIM | DT_DIR | DT_MT, DT_VS, DT_BL, DT_T(STRING ), DT_CNV(STRING ), DT_CLS(m_String ), DT_REL (CLR_RT_HeapBlock ::Relocate_String ) DT_OPT_NAME(STRING ) }, // DATATYPE_STRING + // + { DT_REF | DT_DIR | DT_MT, DT_NA, DT_BL, DT_T(OBJECT ), DT_CNV(OBJECT ), DT_CLS(m_Object ), DT_REL (CLR_RT_HeapBlock ::Relocate_Obj ) DT_OPT_NAME(OBJECT ) }, // DATATYPE_OBJECT + { DT_REF | DT_CLASS | DT_MT, DT_NA, DT_BL, DT_T(CLASS ), DT_CNV(CLASS ), NULL , DT_REL (CLR_RT_HeapBlock ::Relocate_Cls ) DT_OPT_NAME(CLASS ) }, // DATATYPE_CLASS + { DT_REF | DT_VALUE | DT_MT, DT_NA, DT_BL, DT_T(VALUETYPE ), DT_CNV(VALUETYPE), NULL , DT_REL (CLR_RT_HeapBlock ::Relocate_Cls ) DT_OPT_NAME(VALUETYPE ) }, // DATATYPE_VALUETYPE + { DT_REF | DT_CLASS | DT_ARRAY | DT_MT, DT_NA, DT_BL, DT_T(SZARRAY ), DT_CNV(SZARRAY ), DT_CLS(m_Array ), DT_REL (CLR_RT_HeapBlock_Array ::Relocate ) DT_OPT_NAME(SZARRAY ) }, // DATATYPE_SZARRAY + { DT_REF | DT_MT, DT_NA, DT_NA, DT_T(BYREF ), DT_CNV(BYREF ), NULL , DT_REL (CLR_RT_HeapBlock ::Relocate_Ref ) DT_OPT_NAME(BYREF ) }, // DATATYPE_BYREF + // + //////////////////////////////////// + // + { DT_NA , DT_NA, DT_NA, DT_T(FREEBLOCK ), DT_CNV(END ), NULL , DT_NOREL(CLR_RT_HeapBlock ) DT_OPT_NAME(FREEBLOCK ) }, // DATATYPE_FREEBLOCK + { DT_NA , DT_NA, DT_NA, DT_T(CACHEDBLOCK ), DT_CNV(END ), NULL , DT_NOREL(CLR_RT_HeapBlock_Node ) DT_OPT_NAME(CACHEDBLOCK ) }, // DATATYPE_CACHEDBLOCK + { DT_REF , DT_NA, DT_NA, DT_T(ASSEMBLY ), DT_CNV(END ), NULL , DT_REL (CLR_RT_Assembly ::Relocate ) DT_OPT_NAME(ASSEMBLY ) }, // DATATYPE_ASSEMBLY + { DT_REF | DT_MT, DT_NA, DT_BL, DT_T(WEAKCLASS ), DT_CNV(END ), NULL , DT_REL (CLR_RT_HeapBlock_WeakReference::Relocate ) DT_OPT_NAME(WEAKCLASS ) }, // DATATYPE_WEAKCLASS + { DT_MT, DT_NA, DT_NA, DT_T(REFLECTION ), DT_CNV(END ), NULL , DT_NOREL(CLR_RT_HeapBlock ) DT_OPT_NAME(REFLECTION ) }, // DATATYPE_REFLECTION + { DT_MT, DT_NA, DT_NA, DT_T(ARRAY_BYREF ), DT_CNV(END ), NULL , DT_REL (CLR_RT_HeapBlock ::Relocate_ArrayRef) DT_OPT_NAME(ARRAY_BYREF ) }, // DATATYPE_ARRAY_BYREF + { DT_REF | DT_MT, DT_NA, DT_BL, DT_T(DELEGATE_HEAD ), DT_CNV(END ), NULL , DT_REL (CLR_RT_HeapBlock_Delegate ::Relocate ) DT_OPT_NAME(DELEGATE_HEAD ) }, // DATATYPE_DELEGATE_HEAD + { DT_REF | DT_MT, DT_NA, DT_NA, DT_T(DELEGATELIST_HEAD ), DT_CNV(END ), NULL , DT_REL (CLR_RT_HeapBlock_Delegate_List::Relocate ) DT_OPT_NAME(DELEGATELIST_HEAD ) }, // DATATYPE_DELEGATELIST_HEAD + { DT_REF , DT_NA, DT_NA, DT_T(OBJECT_TO_EVENT ), DT_CNV(END ), NULL , DT_REL (CLR_RT_ObjectToEvent_Source ::Relocate ) DT_OPT_NAME(OBJECT_TO_EVENT ) }, // DATATYPE_OBJECT_TO_EVENT + { DT_REF , DT_NA, DT_NA, DT_T(BINARY_BLOB_HEAD ), DT_CNV(END ), NULL , DT_REL (CLR_RT_HeapBlock_BinaryBlob ::Relocate ) DT_OPT_NAME(BINARY_BLOB_HEAD ) }, // DATATYPE_BINARY_BLOB_HEAD + // + { DT_REF , DT_NA, DT_NA, DT_T(THREAD ), DT_CNV(END ), NULL , DT_REL (CLR_RT_Thread ::Relocate ) DT_OPT_NAME(THREAD ) }, // DATATYPE_THREAD + { DT_REF , DT_NA, DT_NA, DT_T(SUBTHREAD ), DT_CNV(END ), NULL , DT_REL (CLR_RT_SubThread ::Relocate ) DT_OPT_NAME(SUBTHREAD ) }, // DATATYPE_SUBTHREAD + { DT_REF , DT_NA, DT_NA, DT_T(STACK_FRAME ), DT_CNV(END ), NULL , DT_REL (CLR_RT_StackFrame ::Relocate ) DT_OPT_NAME(STACK_FRAME ) }, // DATATYPE_STACK_FRAME + { DT_REF , DT_NA, DT_NA, DT_T(TIMER_HEAD ), DT_CNV(END ), NULL , DT_NOREL(CLR_RT_HeapBlock_Timer ) DT_OPT_NAME(TIMER_HEAD ) }, // DATATYPE_TIMER_HEAD + { DT_REF , DT_NA, DT_NA, DT_T(LOCK_HEAD ), DT_CNV(END ), NULL , DT_REL (CLR_RT_HeapBlock_Lock ::Relocate ) DT_OPT_NAME(LOCK_HEAD ) }, // DATATYPE_LOCK_HEAD + { DT_REF , DT_NA, DT_NA, DT_T(LOCK_OWNER_HEAD ), DT_CNV(END ), NULL , DT_REL (CLR_RT_HeapBlock_Lock ::Relocate_Owner ) DT_OPT_NAME(LOCK_OWNER_HEAD ) }, // DATATYPE_LOCK_OWNER_HEAD + { DT_REF , DT_NA, DT_NA, DT_T(LOCK_REQUEST_HEAD ), DT_CNV(END ), NULL , DT_REL (CLR_RT_HeapBlock_LockRequest ::Relocate ) DT_OPT_NAME(LOCK_REQUEST_HEAD ) }, // DATATYPE_LOCK_REQUEST_HEAD + { DT_REF , DT_NA, DT_NA, DT_T(WAIT_FOR_OBJECT_HEAD), DT_CNV(END ), NULL , DT_REL (CLR_RT_HeapBlock_WaitForObject::Relocate ) DT_OPT_NAME(WAIT_FOR_OBJECT_HEAD) }, // DATATYPE_WAIT_FOR_OBJECT_HEAD + { DT_REF , DT_NA, DT_NA, DT_T(FINALIZER_HEAD ), DT_CNV(END ), NULL , DT_REL (CLR_RT_HeapBlock_Finalizer ::Relocate ) DT_OPT_NAME(FINALIZER_HEAD ) }, // DATATYPE_FINALIZER_HEAD + { DT_NA , DT_NA, DT_NA, DT_T(MEMORY_STREAM_HEAD ), DT_CNV(END ), NULL , DT_NOREL(CLR_RT_HeapBlock_MemoryStream ) DT_OPT_NAME(MEMORY_STREAM_HEAD ) }, // DATATYPE_MEMORY_STREAM_HEAD + { DT_NA , DT_NA, DT_NA, DT_T(MEMORY_STREAM_DATA ), DT_CNV(END ), NULL , DT_NOREL(CLR_RT_HeapBlock_MemoryStream ) DT_OPT_NAME(MEMORY_STREAM_DATA ) }, // DATATYPE_MEMORY_STREAM_DATA + // + { DT_NA , DT_NA, DT_NA, DT_T(SERIALIZER_HEAD ), DT_CNV(END ), NULL , DT_NOREL(CLR_RT_BinaryFormatter ) DT_OPT_NAME(SERIALIZER_HEAD ) }, // DATATYPE_SERIALIZER_HEAD + { DT_NA , DT_NA, DT_NA, DT_T(SERIALIZER_DUPLICATE), DT_CNV(END ), NULL , DT_NOREL(CLR_RT_BinaryFormatter ) DT_OPT_NAME(SERIALIZER_DUPLICATE) }, // DATATYPE_SERIALIZER_DUPLICATE + { DT_NA , DT_NA, DT_NA, DT_T(SERIALIZER_STATE ), DT_CNV(END ), NULL , DT_NOREL(CLR_RT_BinaryFormatter ) DT_OPT_NAME(SERIALIZER_STATE ) }, // DATATYPE_SERIALIZER_STATE + // + { DT_REF , DT_NA, DT_NA, DT_T(ENDPOINT_HEAD ), DT_CNV(END ), NULL , DT_NOREL(CLR_RT_HeapBlock_EndPoint ) DT_OPT_NAME(ENDPOINT_HEAD ) }, // DATATYPE_ENDPOINT_HEAD + // + DATATYPE_NOT_SUPPORTED + DATATYPE_NOT_SUPPORTED + DATATYPE_NOT_SUPPORTED + + { DT_REF , DT_NA, DT_NA, DT_T(IO_PORT ), DT_CNV(END ), NULL , DT_NOREL(CLR_RT_HeapBlock_NativeEventDispatcher ) DT_OPT_NAME(IO_PORT ) }, // DATATYPE_IO_PORT + + DATATYPE_NOT_SUPPORTED //VTU_PORT + +#if defined(NANOCLR_APPDOMAINS) + { DT_REF , DT_NA, DT_NA, DT_T(APPDOMAIN_HEAD ), DT_CNV(END ), NULL , DT_REL (CLR_RT_AppDomain::Relocate ) DT_OPT_NAME(APPDOMAIN_HEAD ) }, // DATATYPE_APPDOMAIN_HEAD + { DT_REF | DT_MT, DT_NA, DT_NA, DT_T(TRANSPARENT_PROXY ), DT_CNV(END ), NULL , DT_REL (CLR_RT_HeapBlock::Relocate_TransparentProxy ) DT_OPT_NAME(TRANSPARENT_PROXY ) }, // DATATYPE_TRANSPARENT_PROXY + { DT_REF , DT_NA, DT_NA, DT_T(APPDOMAIN_ASSEMBLY ), DT_CNV(END ), NULL , DT_REL (CLR_RT_AppDomainAssembly::Relocate ) DT_OPT_NAME(APPDOMAIN_ASSEMBLY ) }, // DATATYPE_APPDOMAIN_ASSEMBLY +#else + DATATYPE_NOT_SUPPORTED + DATATYPE_NOT_SUPPORTED + DATATYPE_NOT_SUPPORTED +#endif + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#define InlineBrTarget CLR_OpcodeParam_BrTarget +#define InlineField CLR_OpcodeParam_Field +#define InlineI CLR_OpcodeParam_I +#define InlineI8 CLR_OpcodeParam_I8 +#define InlineMethod CLR_OpcodeParam_Method +#define InlineNone CLR_OpcodeParam_None +#define InlineR CLR_OpcodeParam_R +#define InlineSig CLR_OpcodeParam_Sig +#define InlineString CLR_OpcodeParam_String +#define InlineSwitch CLR_OpcodeParam_Switch +#define InlineTok CLR_OpcodeParam_Tok +#define InlineType CLR_OpcodeParam_Type +#define InlineVar CLR_OpcodeParam_Var +#define ShortInlineBrTarget CLR_OpcodeParam_ShortBrTarget +#define ShortInlineI CLR_OpcodeParam_ShortI +#define ShortInlineR CLR_OpcodeParam_ShortR +#define ShortInlineVar CLR_OpcodeParam_ShortVar + +#define Pop0 0 +#define Pop1 1 +#define PopI 1 +#define PopI8 1 +#define PopR4 1 +#define PopR8 1 +#define PopRef 1 + +#define Push0 0 +#define Push1 1 +#define PushI 1 +#define PushI8 1 +#define PushR4 1 +#define PushR8 1 +#define PushRef 1 + +#define VarPop 0 +#define VarPush 0 + +#if defined(NANOCLR_OPCODE_NAMES) +#define OPDEF_NAME(name) name, +#else +#define OPDEF_NAME(name) +#endif + +#if defined(NANOCLR_OPCODE_STACKCHANGES) +#define OPDEF_STACKCHANGE(pop,push) ((pop) << 4) | (push), +#else +#define OPDEF_STACKCHANGE(pop,push) +#endif + +#if defined(NANOCLR_OPCODE_PARSER) +#define OPDEF_EX(lo,dt,index,flags) , lo, dt, index, flags +#else +#define OPDEF_EX(lo,dt,index,flags) +#endif + +#define OPDEF(name,string,pop,push,oprType,opcType,l,s1,s2,ctrl) OPDEF_NAME(string) OPDEF_STACKCHANGE(pop,push) oprType + +//--// + +const CLR_RT_OpcodeLookup c_CLR_RT_OpcodeLookup[] = +{ + { + OPDEF(CEE_NOP, "nop", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x00, NEXT) + + OPDEF_EX(LO_Nop, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER) + }, + { + OPDEF(CEE_BREAK, "break", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x01, BREAK) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER) + }, + { + OPDEF(CEE_LDARG_0, "ldarg.0", Pop0, Push1, InlineNone, IMacro, 1, 0xFF, 0x02, NEXT) + + OPDEF_EX(LO_LoadArgument, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_INDEX) + }, + { + OPDEF(CEE_LDARG_1, "ldarg.1", Pop0, Push1, InlineNone, IMacro, 1, 0xFF, 0x03, NEXT) + + OPDEF_EX(LO_LoadArgument, DATATYPE_FIRST_INVALID, 1, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_INDEX) + }, + { + OPDEF(CEE_LDARG_2, "ldarg.2", Pop0, Push1, InlineNone, IMacro, 1, 0xFF, 0x04, NEXT) + + OPDEF_EX(LO_LoadArgument, DATATYPE_FIRST_INVALID, 2, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_INDEX) + }, + { + OPDEF(CEE_LDARG_3, "ldarg.3", Pop0, Push1, InlineNone, IMacro, 1, 0xFF, 0x05, NEXT) + + OPDEF_EX(LO_LoadArgument, DATATYPE_FIRST_INVALID, 3, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_INDEX) + }, + { + OPDEF(CEE_LDLOC_0, "ldloc.0", Pop0, Push1, InlineNone, IMacro, 1, 0xFF, 0x06, NEXT) + + OPDEF_EX(LO_LoadLocal, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_INDEX) + }, + { + OPDEF(CEE_LDLOC_1, "ldloc.1", Pop0, Push1, InlineNone, IMacro, 1, 0xFF, 0x07, NEXT) + + OPDEF_EX(LO_LoadLocal, DATATYPE_FIRST_INVALID, 1, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_INDEX) + }, + { + OPDEF(CEE_LDLOC_2, "ldloc.2", Pop0, Push1, InlineNone, IMacro, 1, 0xFF, 0x08, NEXT) + + OPDEF_EX(LO_LoadLocal, DATATYPE_FIRST_INVALID, 2, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_INDEX) + }, + { + OPDEF(CEE_LDLOC_3, "ldloc.3", Pop0, Push1, InlineNone, IMacro, 1, 0xFF, 0x09, NEXT) + + OPDEF_EX(LO_LoadLocal, DATATYPE_FIRST_INVALID, 3, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_INDEX) + }, + { + OPDEF(CEE_STLOC_0, "stloc.0", Pop1, Push0, InlineNone, IMacro, 1, 0xFF, 0x0A, NEXT) + + OPDEF_EX(LO_StoreLocal, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_INDEX) + }, + { + OPDEF(CEE_STLOC_1, "stloc.1", Pop1, Push0, InlineNone, IMacro, 1, 0xFF, 0x0B, NEXT) + + OPDEF_EX(LO_StoreLocal, DATATYPE_FIRST_INVALID, 1, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_INDEX) + }, + { + OPDEF(CEE_STLOC_2, "stloc.2", Pop1, Push0, InlineNone, IMacro, 1, 0xFF, 0x0C, NEXT) + + OPDEF_EX(LO_StoreLocal, DATATYPE_FIRST_INVALID, 2, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_INDEX) + }, + { + OPDEF(CEE_STLOC_3, "stloc.3", Pop1, Push0, InlineNone, IMacro, 1, 0xFF, 0x0D, NEXT) + + OPDEF_EX(LO_StoreLocal, DATATYPE_FIRST_INVALID, 3, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_INDEX) + }, + { + OPDEF(CEE_LDARG_S, "ldarg.s", Pop0, Push1, ShortInlineVar, IMacro, 1, 0xFF, 0x0E, NEXT) + + OPDEF_EX(LO_LoadArgument, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_INDEX) + }, + { + OPDEF(CEE_LDARGA_S, "ldarga.s", Pop0, PushI, ShortInlineVar, IMacro, 1, 0xFF, 0x0F, NEXT) + + OPDEF_EX(LO_LoadArgumentAddress, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_INDEX) + }, + { + OPDEF(CEE_STARG_S, "starg.s", Pop1, Push0, ShortInlineVar, IMacro, 1, 0xFF, 0x10, NEXT) + + OPDEF_EX(LO_StoreArgument, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_INDEX) + }, + { + OPDEF(CEE_LDLOC_S, "ldloc.s", Pop0, Push1, ShortInlineVar, IMacro, 1, 0xFF, 0x11, NEXT) + + OPDEF_EX(LO_LoadLocal, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_INDEX) + }, + { + OPDEF(CEE_LDLOCA_S, "ldloca.s", Pop0, PushI, ShortInlineVar, IMacro, 1, 0xFF, 0x12, NEXT) + + OPDEF_EX(LO_LoadLocalAddress, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_INDEX) + }, + { + OPDEF(CEE_STLOC_S, "stloc.s", Pop1, Push0, ShortInlineVar, IMacro, 1, 0xFF, 0x13, NEXT) + + OPDEF_EX(LO_StoreLocal, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_INDEX) + }, + { + OPDEF(CEE_LDNULL, "ldnull", Pop0, PushRef, InlineNone, IPrimitive, 1, 0xFF, 0x14, NEXT) + + OPDEF_EX(LO_LoadNull, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER) + }, + { + OPDEF(CEE_LDC_I4_M1, "ldc.i4.m1", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x15, NEXT) + + OPDEF_EX(LO_LoadConstant_I4, DATATYPE_FIRST_INVALID, -1, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_I4) + }, + { + OPDEF(CEE_LDC_I4_0, "ldc.i4.0", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x16, NEXT) + + OPDEF_EX(LO_LoadConstant_I4, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_I4) + }, + { + OPDEF(CEE_LDC_I4_1, "ldc.i4.1", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x17, NEXT) + + OPDEF_EX(LO_LoadConstant_I4, DATATYPE_FIRST_INVALID, 1, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_I4) + }, + { + OPDEF(CEE_LDC_I4_2, "ldc.i4.2", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x18, NEXT) + + OPDEF_EX(LO_LoadConstant_I4, DATATYPE_FIRST_INVALID, 2, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_I4) + }, + { + OPDEF(CEE_LDC_I4_3, "ldc.i4.3", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x19, NEXT) + + OPDEF_EX(LO_LoadConstant_I4, DATATYPE_FIRST_INVALID, 3, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_I4) + }, + { + OPDEF(CEE_LDC_I4_4, "ldc.i4.4", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x1A, NEXT) + + OPDEF_EX(LO_LoadConstant_I4, DATATYPE_FIRST_INVALID, 4, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_I4) + }, + { + OPDEF(CEE_LDC_I4_5, "ldc.i4.5", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x1B, NEXT) + + OPDEF_EX(LO_LoadConstant_I4, DATATYPE_FIRST_INVALID, 5, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_I4) + }, + { + OPDEF(CEE_LDC_I4_6, "ldc.i4.6", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x1C, NEXT) + + OPDEF_EX(LO_LoadConstant_I4, DATATYPE_FIRST_INVALID, 6, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_I4) + }, + { + OPDEF(CEE_LDC_I4_7, "ldc.i4.7", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x1D, NEXT) + + OPDEF_EX(LO_LoadConstant_I4, DATATYPE_FIRST_INVALID, 7, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_I4) + }, + { + OPDEF(CEE_LDC_I4_8, "ldc.i4.8", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x1E, NEXT) + + OPDEF_EX(LO_LoadConstant_I4, DATATYPE_FIRST_INVALID, 8, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_I4) + }, + { + OPDEF(CEE_LDC_I4_S, "ldc.i4.s", Pop0, PushI, ShortInlineI, IMacro, 1, 0xFF, 0x1F, NEXT) + + OPDEF_EX(LO_LoadConstant_I4, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_I4) + }, + { + OPDEF(CEE_LDC_I4, "ldc.i4", Pop0, PushI, InlineI, IPrimitive, 1, 0xFF, 0x20, NEXT) + + OPDEF_EX(LO_LoadConstant_I4, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_I4) + }, + { + OPDEF(CEE_LDC_I8, "ldc.i8", Pop0, PushI8, InlineI8, IPrimitive, 1, 0xFF, 0x21, NEXT) + + OPDEF_EX(LO_LoadConstant_I8, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_I8) + }, + { + OPDEF(CEE_LDC_R4, "ldc.r4", Pop0, PushR4, ShortInlineR, IPrimitive, 1, 0xFF, 0x22, NEXT) + + OPDEF_EX(LO_LoadConstant_R4, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_R4) + }, + { + OPDEF(CEE_LDC_R8, "ldc.r8", Pop0, PushR8, InlineR, IPrimitive, 1, 0xFF, 0x23, NEXT) + + OPDEF_EX(LO_LoadConstant_R8, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_R8) + }, + { + OPDEF(CEE_UNUSED49, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x24, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_DUP, "dup", Pop1, Push1+Push1, InlineNone, IPrimitive, 1, 0xFF, 0x25, NEXT) + + OPDEF_EX(LO_Dup, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER) + }, + { + OPDEF(CEE_POP, "pop", Pop1, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x26, NEXT) + + OPDEF_EX(LO_Pop, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER) + }, + { + OPDEF(CEE_JMP, "jmp", Pop0, Push0, InlineMethod, IPrimitive, 1, 0xFF, 0x27, CALL) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_CALL, "call", VarPop, VarPush, InlineMethod, IPrimitive, 1, 0xFF, 0x28, CALL) + + OPDEF_EX(LO_Call, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_CALLI, "calli", VarPop, VarPush, InlineSig, IPrimitive, 1, 0xFF, 0x29, CALL) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_RET, "ret", VarPop, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x2A, RETURN) + + OPDEF_EX(LO_Ret, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_ALWAYS) + }, + { + OPDEF(CEE_BR_S, "br.s", Pop0, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x2B, BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_ALWAYS | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_BRFALSE_S, "brfalse.s", PopI, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x2C, COND_BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFFALSE | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_BRTRUE_S, "brtrue.s", PopI, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x2D, COND_BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFTRUE | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_BEQ_S, "beq.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x2E, COND_BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFEQUAL | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_BGE_S, "bge.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x2F, COND_BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFGREATEROREQUAL | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_BGT_S, "bgt.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x30, COND_BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFGREATER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_BLE_S, "ble.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x31, COND_BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFLESSOREQUAL | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_BLT_S, "blt.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x32, COND_BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFLESS | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_BNE_UN_S, "bne.un.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x33, COND_BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFNOTEQUAL | CLR_RT_OpcodeLookup::COND_UNSIGNED | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_BGE_UN_S, "bge.un.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x34, COND_BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFGREATEROREQUAL | CLR_RT_OpcodeLookup::COND_UNSIGNED | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_BGT_UN_S, "bgt.un.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x35, COND_BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFGREATER | CLR_RT_OpcodeLookup::COND_UNSIGNED | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_BLE_UN_S, "ble.un.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x36, COND_BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFLESSOREQUAL | CLR_RT_OpcodeLookup::COND_UNSIGNED | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_BLT_UN_S, "blt.un.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x37, COND_BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFLESS | CLR_RT_OpcodeLookup::COND_UNSIGNED | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_BR, "br", Pop0, Push0, InlineBrTarget, IPrimitive, 1, 0xFF, 0x38, BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_ALWAYS | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_BRFALSE, "brfalse", PopI, Push0, InlineBrTarget, IPrimitive, 1, 0xFF, 0x39, COND_BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFFALSE | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_BRTRUE, "brtrue", PopI, Push0, InlineBrTarget, IPrimitive, 1, 0xFF, 0x3A, COND_BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFTRUE | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_BEQ, "beq", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x3B, COND_BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFEQUAL | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_BGE, "bge", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x3C, COND_BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFGREATEROREQUAL | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_BGT, "bgt", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x3D, COND_BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFGREATER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_BLE, "ble", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x3E, COND_BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFLESSOREQUAL | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_BLT, "blt", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x3F, COND_BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFLESS | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_BNE_UN, "bne.un", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x40, COND_BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFNOTEQUAL | CLR_RT_OpcodeLookup::COND_UNSIGNED | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_BGE_UN, "bge.un", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x41, COND_BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFGREATEROREQUAL | CLR_RT_OpcodeLookup::COND_UNSIGNED | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_BGT_UN, "bgt.un", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x42, COND_BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFGREATER | CLR_RT_OpcodeLookup::COND_UNSIGNED | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_BLE_UN, "ble.un", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x43, COND_BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFLESSOREQUAL | CLR_RT_OpcodeLookup::COND_UNSIGNED | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_BLT_UN, "blt.un", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x44, COND_BRANCH) + + OPDEF_EX(LO_Branch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFLESS | CLR_RT_OpcodeLookup::COND_UNSIGNED | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_SWITCH, "switch", PopI, Push0, InlineSwitch, IPrimitive, 1, 0xFF, 0x45, COND_BRANCH) + + OPDEF_EX(LO_Switch, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFMATCH | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET) + }, + { + OPDEF(CEE_LDIND_I1, "ldind.i1", PopI, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x46, NEXT) + + OPDEF_EX(LO_LoadIndirect, DATATYPE_I1, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_LDIND_U1, "ldind.u1", PopI, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x47, NEXT) + + OPDEF_EX(LO_LoadIndirect, DATATYPE_U1, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_LDIND_I2, "ldind.i2", PopI, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x48, NEXT) + + OPDEF_EX(LO_LoadIndirect, DATATYPE_U2, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_LDIND_U2, "ldind.u2", PopI, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x49, NEXT) + + OPDEF_EX(LO_LoadIndirect, DATATYPE_U2, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_LDIND_I4, "ldind.i4", PopI, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x4A, NEXT) + + OPDEF_EX(LO_LoadIndirect, DATATYPE_I4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_LDIND_U4, "ldind.u4", PopI, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x4B, NEXT) + + OPDEF_EX(LO_LoadIndirect, DATATYPE_U4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_LDIND_I8, "ldind.i8", PopI, PushI8, InlineNone, IPrimitive, 1, 0xFF, 0x4C, NEXT) + + OPDEF_EX(LO_LoadIndirect, DATATYPE_I8, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_LDIND_I, "ldind.i", PopI, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x4D, NEXT) + + OPDEF_EX(LO_LoadIndirect, DATATYPE_I4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_LDIND_R4, "ldind.r4", PopI, PushR4, InlineNone, IPrimitive, 1, 0xFF, 0x4E, NEXT) + + OPDEF_EX(LO_LoadIndirect, DATATYPE_R4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_LDIND_R8, "ldind.r8", PopI, PushR8, InlineNone, IPrimitive, 1, 0xFF, 0x4F, NEXT) + + OPDEF_EX(LO_LoadIndirect, DATATYPE_R8, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_LDIND_REF, "ldind.ref", PopI, PushRef, InlineNone, IPrimitive, 1, 0xFF, 0x50, NEXT) + + OPDEF_EX(LO_LoadIndirect, DATATYPE_OBJECT, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_STIND_REF, "stind.ref", PopI+PopI, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x51, NEXT) + + OPDEF_EX(LO_StoreIndirect, DATATYPE_OBJECT, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_STIND_I1, "stind.i1", PopI+PopI, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x52, NEXT) + + OPDEF_EX(LO_StoreIndirect, DATATYPE_I1, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_STIND_I2, "stind.i2", PopI+PopI, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x53, NEXT) + + OPDEF_EX(LO_StoreIndirect, DATATYPE_I2, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_STIND_I4, "stind.i4", PopI+PopI, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x54, NEXT) + + OPDEF_EX(LO_StoreIndirect, DATATYPE_I4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_STIND_I8, "stind.i8", PopI+PopI8, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x55, NEXT) + + OPDEF_EX(LO_StoreIndirect, DATATYPE_I8, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_STIND_R4, "stind.r4", PopI+PopR4, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x56, NEXT) + + OPDEF_EX(LO_StoreIndirect, DATATYPE_R4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_STIND_R8, "stind.r8", PopI+PopR8, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x57, NEXT) + + OPDEF_EX(LO_StoreIndirect, DATATYPE_R8, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_ADD, "add", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x58, NEXT) + + OPDEF_EX(LO_Add, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER) + }, + { + OPDEF(CEE_SUB, "sub", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x59, NEXT) + + OPDEF_EX(LO_Sub, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER) + }, + { + OPDEF(CEE_MUL, "mul", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x5A, NEXT) + + OPDEF_EX(LO_Mul, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER) + }, + { + OPDEF(CEE_DIV, "div", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x5B, NEXT) + + OPDEF_EX(LO_Div, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER) + }, + { + OPDEF(CEE_DIV_UN, "div.un", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x5C, NEXT) + + OPDEF_EX(LO_Div, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_UNSIGNED) + }, + { + OPDEF(CEE_REM, "rem", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x5D, NEXT) + + OPDEF_EX(LO_Rem, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER) + }, + { + OPDEF(CEE_REM_UN, "rem.un", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x5E, NEXT) + + OPDEF_EX(LO_Rem, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_UNSIGNED) + }, + { + OPDEF(CEE_AND, "and", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x5F, NEXT) + + OPDEF_EX(LO_And, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER) + }, + { + OPDEF(CEE_OR, "or", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x60, NEXT) + + OPDEF_EX(LO_Or, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER) + }, + { + OPDEF(CEE_XOR, "xor", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x61, NEXT) + + OPDEF_EX(LO_Xor, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER) + }, + { + OPDEF(CEE_SHL, "shl", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x62, NEXT) + + OPDEF_EX(LO_Shl, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER) + }, + { + OPDEF(CEE_SHR, "shr", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x63, NEXT) + + OPDEF_EX(LO_Shr, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER) + }, + { + OPDEF(CEE_SHR_UN, "shr.un", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x64, NEXT) + + OPDEF_EX(LO_Shr, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_UNSIGNED) + }, + { + OPDEF(CEE_NEG, "neg", Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x65, NEXT) + + OPDEF_EX(LO_Neg, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER) + }, + { + OPDEF(CEE_NOT, "not", Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x66, NEXT) + + OPDEF_EX(LO_Not, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER) + }, + { + OPDEF(CEE_CONV_I1, "conv.i1", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x67, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_I1, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_I2, "conv.i2", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x68, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_I2, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_I4, "conv.i4", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x69, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_I4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_I8, "conv.i8", Pop1, PushI8, InlineNone, IPrimitive, 1, 0xFF, 0x6A, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_I8, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_R4, "conv.r4", Pop1, PushR4, InlineNone, IPrimitive, 1, 0xFF, 0x6B, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_R4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_R8, "conv.r8", Pop1, PushR8, InlineNone, IPrimitive, 1, 0xFF, 0x6C, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_R8, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_U4, "conv.u4", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x6D, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_U4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_U8, "conv.u8", Pop1, PushI8, InlineNone, IPrimitive, 1, 0xFF, 0x6E, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_U8, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CALLVIRT, "callvirt", VarPop, VarPush, InlineMethod, IObjModel, 1, 0xFF, 0x6F, CALL) + + OPDEF_EX(LO_CallVirt, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_CPOBJ, "cpobj", PopI+PopI, Push0, InlineType, IObjModel, 1, 0xFF, 0x70, NEXT) + + OPDEF_EX(LO_CopyObject, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_LDOBJ, "ldobj", PopI, Push1, InlineType, IObjModel, 1, 0xFF, 0x71, NEXT) + + OPDEF_EX(LO_LoadObject, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_LDSTR, "ldstr", Pop0, PushRef, InlineString, IObjModel, 1, 0xFF, 0x72, NEXT) + + OPDEF_EX(LO_LoadString, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_NEWOBJ, "newobj", VarPop, PushRef, InlineMethod, IObjModel, 1, 0xFF, 0x73, CALL) + + OPDEF_EX(LO_NewObject, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_CASTCLASS, "castclass", PopRef, PushRef, InlineType, IObjModel, 1, 0xFF, 0x74, NEXT) + + OPDEF_EX(LO_CastClass, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_ISINST, "isinst", PopRef, PushI, InlineType, IObjModel, 1, 0xFF, 0x75, NEXT) + + OPDEF_EX(LO_IsInst, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_CONV_R_UN, "conv.r.un", Pop1, PushR8, InlineNone, IPrimitive, 1, 0xFF, 0x76, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_R4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_UNSIGNED | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_UNUSED58, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x77, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED1, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x78, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNBOX, "unbox", PopRef, PushI, InlineType, IPrimitive, 1, 0xFF, 0x79, NEXT) + + OPDEF_EX(LO_Unbox, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_THROW, "throw", PopRef, Push0, InlineNone, IObjModel, 1, 0xFF, 0x7A, THROW) + + OPDEF_EX(LO_Throw, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_ALWAYS | CLR_RT_OpcodeLookup::STACK_RESET) + }, + { + OPDEF(CEE_LDFLD, "ldfld", PopRef, Push1, InlineField, IObjModel, 1, 0xFF, 0x7B, NEXT) + + OPDEF_EX(LO_LoadField, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_LDFLDA, "ldflda", PopRef, PushI, InlineField, IObjModel, 1, 0xFF, 0x7C, NEXT) + + OPDEF_EX(LO_LoadFieldAddress, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_STFLD, "stfld", PopRef+Pop1, Push0, InlineField, IObjModel, 1, 0xFF, 0x7D, NEXT) + + OPDEF_EX(LO_StoreField, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_LDSFLD, "ldsfld", Pop0, Push1, InlineField, IObjModel, 1, 0xFF, 0x7E, NEXT) + + OPDEF_EX(LO_LoadStaticField, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_LDSFLDA, "ldsflda", Pop0, PushI, InlineField, IObjModel, 1, 0xFF, 0x7F, NEXT) + + OPDEF_EX(LO_LoadStaticFieldAddress, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_STSFLD, "stsfld", Pop1, Push0, InlineField, IObjModel, 1, 0xFF, 0x80, NEXT) + + OPDEF_EX(LO_StoreStaticField, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_STOBJ, "stobj", PopI+Pop1, Push0, InlineType, IPrimitive, 1, 0xFF, 0x81, NEXT) + + OPDEF_EX(LO_StoreObject, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_CONV_OVF_I1_UN, "conv.ovf.i1.un", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x82, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_I1, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW | CLR_RT_OpcodeLookup::COND_UNSIGNED | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_OVF_I2_UN, "conv.ovf.i2.un", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x83, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_I2, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW | CLR_RT_OpcodeLookup::COND_UNSIGNED | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_OVF_I4_UN, "conv.ovf.i4.un", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x84, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_I4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW | CLR_RT_OpcodeLookup::COND_UNSIGNED | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_OVF_I8_UN, "conv.ovf.i8.un", Pop1, PushI8, InlineNone, IPrimitive, 1, 0xFF, 0x85, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_I8, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW | CLR_RT_OpcodeLookup::COND_UNSIGNED | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_OVF_U1_UN, "conv.ovf.u1.un", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x86, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_U1, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW | CLR_RT_OpcodeLookup::COND_UNSIGNED | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_OVF_U2_UN, "conv.ovf.u2.un", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x87, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_U2, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW | CLR_RT_OpcodeLookup::COND_UNSIGNED | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_OVF_U4_UN, "conv.ovf.u4.un", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x88, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_U4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW | CLR_RT_OpcodeLookup::COND_UNSIGNED | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_OVF_U8_UN, "conv.ovf.u8.un", Pop1, PushI8, InlineNone, IPrimitive, 1, 0xFF, 0x89, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_U8, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW | CLR_RT_OpcodeLookup::COND_UNSIGNED | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_OVF_I_UN, "conv.ovf.i.un", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x8A, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_I4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW | CLR_RT_OpcodeLookup::COND_UNSIGNED | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_OVF_U_UN, "conv.ovf.u.un", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x8B, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_U4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW | CLR_RT_OpcodeLookup::COND_UNSIGNED | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_BOX, "box", Pop1, PushRef, InlineType, IPrimitive, 1, 0xFF, 0x8C, NEXT) + + OPDEF_EX(LO_Box, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_NEWARR, "newarr", PopI, PushRef, InlineType, IObjModel, 1, 0xFF, 0x8D, NEXT) + + OPDEF_EX(LO_NewArray, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_LDLEN, "ldlen", PopRef, PushI, InlineNone, IObjModel, 1, 0xFF, 0x8E, NEXT) + + OPDEF_EX(LO_LoadLength, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER) + }, + { + OPDEF(CEE_LDELEMA, "ldelema", PopRef+PopI, PushI, InlineType, IObjModel, 1, 0xFF, 0x8F, NEXT) + + OPDEF_EX(LO_LoadElementAddress, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_LDELEM_I1, "ldelem.i1", PopRef+PopI, PushI, InlineNone, IObjModel, 1, 0xFF, 0x90, NEXT) + + OPDEF_EX(LO_LoadElement, DATATYPE_I1, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_LDELEM_U1, "ldelem.u1", PopRef+PopI, PushI, InlineNone, IObjModel, 1, 0xFF, 0x91, NEXT) + + OPDEF_EX(LO_LoadElement, DATATYPE_U1, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_LDELEM_I2, "ldelem.i2", PopRef+PopI, PushI, InlineNone, IObjModel, 1, 0xFF, 0x92, NEXT) + + OPDEF_EX(LO_LoadElement, DATATYPE_I2, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_LDELEM_U2, "ldelem.u2", PopRef+PopI, PushI, InlineNone, IObjModel, 1, 0xFF, 0x93, NEXT) + + OPDEF_EX(LO_LoadElement, DATATYPE_U2, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_LDELEM_I4, "ldelem.i4", PopRef+PopI, PushI, InlineNone, IObjModel, 1, 0xFF, 0x94, NEXT) + + OPDEF_EX(LO_LoadElement, DATATYPE_I4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_LDELEM_U4, "ldelem.u4", PopRef+PopI, PushI, InlineNone, IObjModel, 1, 0xFF, 0x95, NEXT) + + OPDEF_EX(LO_LoadElement, DATATYPE_U4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_LDELEM_I8, "ldelem.i8", PopRef+PopI, PushI8, InlineNone, IObjModel, 1, 0xFF, 0x96, NEXT) + + OPDEF_EX(LO_LoadElement, DATATYPE_I8, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_LDELEM_I, "ldelem.i", PopRef+PopI, PushI, InlineNone, IObjModel, 1, 0xFF, 0x97, NEXT) + + OPDEF_EX(LO_LoadElement, DATATYPE_I4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_LDELEM_R4, "ldelem.r4", PopRef+PopI, PushR4, InlineNone, IObjModel, 1, 0xFF, 0x98, NEXT) + + OPDEF_EX(LO_LoadElement, DATATYPE_R4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_LDELEM_R8, "ldelem.r8", PopRef+PopI, PushR8, InlineNone, IObjModel, 1, 0xFF, 0x99, NEXT) + + OPDEF_EX(LO_LoadElement, DATATYPE_R8, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_LDELEM_REF, "ldelem.ref", PopRef+PopI, PushRef, InlineNone, IObjModel, 1, 0xFF, 0x9A, NEXT) + + OPDEF_EX(LO_LoadElement, DATATYPE_OBJECT, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_STELEM_I, "stelem.i", PopRef+PopI+PopI, Push0, InlineNone, IObjModel, 1, 0xFF, 0x9B, NEXT) + + OPDEF_EX(LO_StoreElement, DATATYPE_I4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_STELEM_I1, "stelem.i1", PopRef+PopI+PopI, Push0, InlineNone, IObjModel, 1, 0xFF, 0x9C, NEXT) + + OPDEF_EX(LO_StoreElement, DATATYPE_I1, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_STELEM_I2, "stelem.i2", PopRef+PopI+PopI, Push0, InlineNone, IObjModel, 1, 0xFF, 0x9D, NEXT) + + OPDEF_EX(LO_StoreElement, DATATYPE_I2, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_STELEM_I4, "stelem.i4", PopRef+PopI+PopI, Push0, InlineNone, IObjModel, 1, 0xFF, 0x9E, NEXT) + + OPDEF_EX(LO_StoreElement, DATATYPE_I4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_STELEM_I8, "stelem.i8", PopRef+PopI+PopI8, Push0, InlineNone, IObjModel, 1, 0xFF, 0x9F, NEXT) + + OPDEF_EX(LO_StoreElement, DATATYPE_I8, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_STELEM_R4, "stelem.r4", PopRef+PopI+PopR4, Push0, InlineNone, IObjModel, 1, 0xFF, 0xA0, NEXT) + + OPDEF_EX(LO_StoreElement, DATATYPE_R4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_STELEM_R8, "stelem.r8", PopRef+PopI+PopR8, Push0, InlineNone, IObjModel, 1, 0xFF, 0xA1, NEXT) + + OPDEF_EX(LO_StoreElement, DATATYPE_R8, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_STELEM_REF, "stelem.ref", PopRef+PopI+PopRef, Push0, InlineNone, IObjModel, 1, 0xFF, 0xA2, NEXT) + + OPDEF_EX(LO_StoreElement, DATATYPE_OBJECT, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_LDELEM, "ldelem", PopRef+PopI, Push1, InlineType, IObjModel, 1, 0xFF, 0xA3, NEXT) + OPDEF_EX(LO_LoadElement, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_STELEM, "stelem", PopRef+PopI+Pop1, Push0, InlineType, IObjModel, 1, 0xFF, 0xA4, NEXT) + + OPDEF_EX(LO_StoreElement, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_UNBOX_ANY, "unbox.any", PopRef, Push1, InlineType, IObjModel, 1, 0xFF, 0xA5, NEXT) + + OPDEF_EX(LO_Unbox, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_UNUSED5, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xA6, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED6, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xA7, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED7, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xA8, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED8, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xA9, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED9, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xAA, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED10, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xAB, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED11, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xAC, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED12, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xAD, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED13, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xAE, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED14, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xAF, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED15, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xB0, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED16, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xB1, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED17, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xB2, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_CONV_OVF_I1, "conv.ovf.i1", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xB3, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_I1, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_OVF_U1, "conv.ovf.u1", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xB4, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_U1, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_OVF_I2, "conv.ovf.i2", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xB5, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_I2, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_OVF_U2, "conv.ovf.u2", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xB6, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_U2, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_OVF_I4, "conv.ovf.i4", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xB7, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_I4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_OVF_U4, "conv.ovf.u4", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xB8, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_U4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_OVF_I8, "conv.ovf.i8", Pop1, PushI8, InlineNone, IPrimitive, 1, 0xFF, 0xB9, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_I8, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_OVF_U8, "conv.ovf.u8", Pop1, PushI8, InlineNone, IPrimitive, 1, 0xFF, 0xBA, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_U8, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_UNUSED50, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xBB, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED18, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xBC, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED19, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xBD, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED20, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xBE, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED21, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xBF, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED22, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xC0, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED23, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xC1, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_REFANYVAL, "refanyval", Pop1, PushI, InlineType, IPrimitive, 1, 0xFF, 0xC2, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_CKFINITE, "ckfinite", Pop1, PushR8, InlineNone, IPrimitive, 1, 0xFF, 0xC3, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED24, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xC4, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED25, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xC5, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_MKREFANY, "mkrefany", PopI, Push1, InlineType, IPrimitive, 1, 0xFF, 0xC6, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED59, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xC7, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED60, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xC8, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED61, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xC9, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED62, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xCA, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED63, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xCB, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED64, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xCC, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED65, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xCD, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED66, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xCE, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED67, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xCF, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_LDTOKEN, "ldtoken", Pop0, PushI, InlineTok, IPrimitive, 1, 0xFF, 0xD0, NEXT) + + OPDEF_EX(LO_LoadToken, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_CONV_U2, "conv.u2", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xD1, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_U2, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_U1, "conv.u1", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xD2, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_U1, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_I, "conv.i", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xD3, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_I4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_OVF_I, "conv.ovf.i", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xD4, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_I4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_OVF_U, "conv.ovf.u", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xD5, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_U4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_ADD_OVF, "add.ovf", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0xD6, NEXT) + + OPDEF_EX(LO_Add, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW) + }, + { + OPDEF(CEE_ADD_OVF_UN, "add.ovf.un", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0xD7, NEXT) + + OPDEF_EX(LO_Add, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW | CLR_RT_OpcodeLookup::COND_UNSIGNED) + }, + { + OPDEF(CEE_MUL_OVF, "mul.ovf", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0xD8, NEXT) + + OPDEF_EX(LO_Mul, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW) + }, + { + OPDEF(CEE_MUL_OVF_UN, "mul.ovf.un", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0xD9, NEXT) + + OPDEF_EX(LO_Mul, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW | CLR_RT_OpcodeLookup::COND_UNSIGNED) + }, + { + OPDEF(CEE_SUB_OVF, "sub.ovf", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0xDA, NEXT) + + OPDEF_EX(LO_Sub, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW) + }, + { + OPDEF(CEE_SUB_OVF_UN, "sub.ovf.un", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0xDB, NEXT) + + OPDEF_EX(LO_Sub, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::COND_OVERFLOW | CLR_RT_OpcodeLookup::COND_UNSIGNED) + }, + { + OPDEF(CEE_ENDFINALLY, "endfinally", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xDC, RETURN) + + OPDEF_EX(LO_EndFinally, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_ALWAYS | CLR_RT_OpcodeLookup::STACK_RESET) + }, + { + OPDEF(CEE_LEAVE, "leave", Pop0, Push0, InlineBrTarget, IPrimitive, 1, 0xFF, 0xDD, BRANCH) + + OPDEF_EX(LO_Leave, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_ALWAYS | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET | CLR_RT_OpcodeLookup::STACK_RESET) + }, + { + OPDEF(CEE_LEAVE_S, "leave.s", Pop0, Push0, ShortInlineBrTarget,IPrimitive, 1, 0xFF, 0xDE, BRANCH) + + OPDEF_EX(LO_Leave, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_ALWAYS | CLR_RT_OpcodeLookup::ATTRIB_HAS_TARGET | CLR_RT_OpcodeLookup::STACK_RESET) + }, + { + OPDEF(CEE_STIND_I, "stind.i", PopI+PopI, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xDF, NEXT) + + OPDEF_EX(LO_StoreIndirect, DATATYPE_I4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_CONV_U, "conv.u", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xE0, NEXT) + + OPDEF_EX(LO_Convert, DATATYPE_U4, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_DT) + }, + { + OPDEF(CEE_UNUSED26, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xE1, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED27, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xE2, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED28, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xE3, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED29, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xE4, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED30, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xE5, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED31, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xE6, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED32, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xE7, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED33, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xE8, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED34, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xE9, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED35, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xEA, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED36, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xEB, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED37, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xEC, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED38, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xED, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED39, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xEE, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED40, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xEF, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED41, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xF0, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED42, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xF1, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED43, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xF2, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED44, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xF3, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED45, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xF4, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED46, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xF5, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED47, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xF6, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED48, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xF7, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_PREFIX7, "prefix7", Pop0, Push0, InlineNone, IInternal, 1, 0xFF, 0xF8, META) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_PREFIX6, "prefix6", Pop0, Push0, InlineNone, IInternal, 1, 0xFF, 0xF9, META) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_PREFIX5, "prefix5", Pop0, Push0, InlineNone, IInternal, 1, 0xFF, 0xFA, META) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_PREFIX4, "prefix4", Pop0, Push0, InlineNone, IInternal, 1, 0xFF, 0xFB, META) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_PREFIX3, "prefix3", Pop0, Push0, InlineNone, IInternal, 1, 0xFF, 0xFC, META) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_PREFIX2, "prefix2", Pop0, Push0, InlineNone, IInternal, 1, 0xFF, 0xFD, META) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_PREFIX1, "prefix1", Pop0, Push0, InlineNone, IInternal, 1, 0xFF, 0xFE, META) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_PREFIXREF, "prefixref", Pop0, Push0, InlineNone, IInternal, 1, 0xFF, 0xFF, META) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_ARGLIST, "arglist", Pop0, PushI, InlineNone, IPrimitive, 2, 0xFE, 0x00, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_CEQ, "ceq", Pop1+Pop1, PushI, InlineNone, IPrimitive, 2, 0xFE, 0x01, NEXT) + + OPDEF_EX(LO_Set, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFEQUAL) + }, + { + OPDEF(CEE_CGT, "cgt", Pop1+Pop1, PushI, InlineNone, IPrimitive, 2, 0xFE, 0x02, NEXT) + + OPDEF_EX(LO_Set, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFGREATER) + }, + { + OPDEF(CEE_CGT_UN, "cgt.un", Pop1+Pop1, PushI, InlineNone, IPrimitive, 2, 0xFE, 0x03, NEXT) + + OPDEF_EX(LO_Set, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFGREATER | CLR_RT_OpcodeLookup::COND_UNSIGNED) + }, + { + OPDEF(CEE_CLT, "clt", Pop1+Pop1, PushI, InlineNone, IPrimitive, 2, 0xFE, 0x04, NEXT) + + OPDEF_EX(LO_Set, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFLESS) + }, + { + OPDEF(CEE_CLT_UN, "clt.un", Pop1+Pop1, PushI, InlineNone, IPrimitive, 2, 0xFE, 0x05, NEXT) + + OPDEF_EX(LO_Set, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_IFLESS | CLR_RT_OpcodeLookup::COND_UNSIGNED) + }, + { + OPDEF(CEE_LDFTN, "ldftn", Pop0, PushI, InlineMethod, IPrimitive, 2, 0xFE, 0x06, NEXT) + + OPDEF_EX(LO_LoadFunction, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_LDVIRTFTN, "ldvirtftn", PopRef, PushI, InlineMethod, IPrimitive, 2, 0xFE, 0x07, NEXT) + + OPDEF_EX(LO_LoadVirtFunction, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_UNUSED56, "unused", Pop0, Push0, InlineNone, IPrimitive, 2, 0xFE, 0x08, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_LDARG, "ldarg", Pop0, Push1, InlineVar, IPrimitive, 2, 0xFE, 0x09, NEXT) + + OPDEF_EX(LO_LoadArgument, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_INDEX) + }, + { + OPDEF(CEE_LDARGA, "ldarga", Pop0, PushI, InlineVar, IPrimitive, 2, 0xFE, 0x0A, NEXT) + + OPDEF_EX(LO_LoadArgumentAddress, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_INDEX) + }, + { + OPDEF(CEE_STARG, "starg", Pop1, Push0, InlineVar, IPrimitive, 2, 0xFE, 0x0B, NEXT) + + OPDEF_EX(LO_StoreArgument, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_INDEX) + }, + { + OPDEF(CEE_LDLOC, "ldloc", Pop0, Push1, InlineVar, IPrimitive, 2, 0xFE, 0x0C, NEXT) + + OPDEF_EX(LO_LoadLocal, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_INDEX) + }, + { + OPDEF(CEE_LDLOCA, "ldloca", Pop0, PushI, InlineVar, IPrimitive, 2, 0xFE, 0x0D, NEXT) + + OPDEF_EX(LO_LoadLocalAddress, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_INDEX) + }, + { + OPDEF(CEE_STLOC, "stloc", Pop1, Push0, InlineVar, IPrimitive, 2, 0xFE, 0x0E, NEXT) + + OPDEF_EX(LO_StoreLocal, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_INDEX) + }, + { + OPDEF(CEE_LOCALLOC, "localloc", PopI, PushI, InlineNone, IPrimitive, 2, 0xFE, 0x0F, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED57, "unused", Pop0, Push0, InlineNone, IPrimitive, 2, 0xFE, 0x10, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_ENDFILTER, "endfilter", PopI, Push0, InlineNone, IPrimitive, 2, 0xFE, 0x11, RETURN) + + OPDEF_EX(LO_EndFilter, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_ALWAYS | CLR_RT_OpcodeLookup::STACK_RESET) + }, + { + OPDEF(CEE_UNALIGNED, "unaligned.", Pop0, Push0, ShortInlineI, IPrefix, 2, 0xFE, 0x12, META) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_VOLATILE, "volatile.", Pop0, Push0, InlineNone, IPrefix, 2, 0xFE, 0x13, META) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_TAILCALL, "tail.", Pop0, Push0, InlineNone, IPrefix, 2, 0xFE, 0x14, META) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_INITOBJ, "initobj", PopI, Push0, InlineType, IObjModel, 2, 0xFE, 0x15, NEXT) + + OPDEF_EX(LO_InitObject, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_CONSTRAINED, "constrained.", Pop0, Push0, InlineType, IPrefix, 2, 0xFE, 0x16, META) + + OPDEF_EX(LO_Nop, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_NEVER | CLR_RT_OpcodeLookup::ATTRIB_HAS_TOKEN) + }, + { + OPDEF(CEE_CPBLK, "cpblk", PopI+PopI+PopI, Push0, InlineNone, IPrimitive, 2, 0xFE, 0x17, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_INITBLK, "initblk", PopI+PopI+PopI, Push0, InlineNone, IPrimitive, 2, 0xFE, 0x18, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED69, "unused", Pop0, Push0, InlineNone, IPrimitive, 2, 0xFE, 0x19, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_RETHROW, "rethrow", Pop0, Push0, InlineNone, IObjModel, 2, 0xFE, 0x1A, THROW) + + OPDEF_EX(LO_Rethrow, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_ALWAYS) + }, + { + OPDEF(CEE_UNUSED51, "unused", Pop0, Push0, InlineNone, IPrimitive, 2, 0xFE, 0x1B, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_SIZEOF, "sizeof", Pop0, PushI, InlineType, IPrimitive, 2, 0xFE, 0x1C, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_REFANYTYPE, "refanytype", Pop1, PushI, InlineNone, IPrimitive, 2, 0xFE, 0x1D, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_READONLY, "readonly.", Pop0, Push0, InlineNone, IPrefix, 2, 0xFE, 0x1E, META) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED53, "unused", Pop0, Push0, InlineNone, IPrimitive, 2, 0xFE, 0x1F, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED54, "unused", Pop0, Push0, InlineNone, IPrimitive, 2, 0xFE, 0x20, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED55, "unused", Pop0, Push0, InlineNone, IPrimitive, 2, 0xFE, 0x21, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, + { + OPDEF(CEE_UNUSED70, "unused", Pop0, Push0, InlineNone, IPrimitive, 2, 0xFE, 0x22, NEXT) + + OPDEF_EX(LO_Unsupported, DATATYPE_FIRST_INVALID, 0, CLR_RT_OpcodeLookup::COND_BRANCH_THROW) + }, +}; + +#undef OPDEF_NAME +#undef OPDEF_STACKCHANGE +#undef OPDEF_EX +#undef OPDEF + +//--// + +#undef LoadString // Legacy Windows macro, whatever... + +#if defined(NANOCLR_OPCODE_NAMES) +#define OPDEF_NAME(name) #name, +#else +#define OPDEF_NAME(name) +#endif + +#define OPDEF(name,flags) OPDEF_NAME(name) flags + +#define VAL_NONE 0 +#define VAL_RP CLR_RT_LogicalOpcodeLookup::RESTARTPOINT_NEXT +#define VAL_EX CLR_RT_LogicalOpcodeLookup::EXCEPTION +#define VAL_EX_ZERO CLR_RT_LogicalOpcodeLookup::EXCEPTION_IF_ZERO +#define VAL_EX_OVF CLR_RT_LogicalOpcodeLookup::EXCEPTION_IF_OVERFLOW + +const CLR_RT_LogicalOpcodeLookup c_CLR_RT_LogicalOpcodeLookup[] = +{ + OPDEF(Not , VAL_NONE ), // LO_Not = 0x00, + OPDEF(And , VAL_NONE ), // LO_And = 0x01, + OPDEF(Or , VAL_NONE ), // LO_Or = 0x02, + OPDEF(Xor , VAL_NONE ), // LO_Xor = 0x03, + OPDEF(Shl , VAL_NONE ), // LO_Shl = 0x04, + OPDEF(Shr , VAL_NONE ), // LO_Shr = 0x05, + + OPDEF(Neg , VAL_NONE ), // LO_Neg = 0x06, + OPDEF(Add , VAL_EX_OVF ), // LO_Add = 0x07, + OPDEF(Sub , VAL_EX_OVF ), // LO_Sub = 0x08, + OPDEF(Mul , VAL_EX_OVF ), // LO_Mul = 0x09, + OPDEF(Div , VAL_EX_ZERO ), // LO_Div = 0x0A, + OPDEF(Rem , VAL_EX_ZERO ), // LO_Rem = 0x0B, + + OPDEF(Box , VAL_EX ), // LO_Box = 0x0C, + OPDEF(Unbox , VAL_EX ), // LO_Unbox = 0x0D, + + OPDEF(Branch , VAL_NONE ), // LO_Branch = 0x0E, + OPDEF(Set , VAL_NONE ), // LO_Set = 0x0F, + OPDEF(Switch , VAL_NONE ), // LO_Switch = 0x10, + + OPDEF(LoadFunction , VAL_EX ), // LO_LoadFunction = 0x11, + OPDEF(LoadVirtFunction , VAL_EX ), // LO_LoadVirtFunction = 0x12, + + OPDEF(Call , VAL_EX | VAL_RP), // LO_Call = 0x13, + OPDEF(CallVirt , VAL_EX | VAL_RP), // LO_CallVirt = 0x14, + OPDEF(Ret , VAL_NONE ), // LO_Ret = 0x15, + + OPDEF(NewObject , VAL_EX | VAL_RP), // LO_NewObject = 0x16, + OPDEF(CastClass , VAL_EX ), // LO_CastClass = 0x17, + OPDEF(IsInst , VAL_NONE ), // LO_IsInst = 0x18, + + OPDEF(Dup , VAL_NONE ), // LO_Dup = 0x19, + OPDEF(Pop , VAL_NONE ), // LO_Pop = 0x1A, + + OPDEF(Throw , VAL_EX ), // LO_Throw = 0x1B, + OPDEF(Rethrow , VAL_EX ), // LO_Rethrow = 0x1C, + OPDEF(Leave , VAL_NONE ), // LO_Leave = 0x1D, + OPDEF(EndFinally , VAL_EX ), // LO_EndFinally = 0x1E, + + OPDEF(Convert , VAL_EX_OVF ), // LO_Convert = 0x1F, + + OPDEF(StoreArgument , VAL_NONE ), // LO_StoreArgument = 0x20, + OPDEF(LoadArgument , VAL_NONE ), // LO_LoadArgument = 0x21, + OPDEF(LoadArgumentAddress , VAL_NONE ), // LO_LoadArgumentAddress = 0x22, + + OPDEF(StoreLocal , VAL_NONE ), // LO_StoreLocal = 0x23, + OPDEF(LoadLocal , VAL_NONE ), // LO_LoadLocal = 0x24, + OPDEF(LoadLocalAddress , VAL_NONE ), // LO_LoadLocalAddress = 0x25, + + OPDEF(LoadConstant_I4 , VAL_NONE ), // LO_LoadConstant_I4 = 0x26, + OPDEF(LoadConstant_I8 , VAL_NONE ), // LO_LoadConstant_I8 = 0x27, + OPDEF(LoadConstant_R4 , VAL_NONE ), // LO_LoadConstant_R4 = 0x28, + OPDEF(LoadConstant_R8 , VAL_NONE ), // LO_LoadConstant_R8 = 0x29, + + OPDEF(LoadNull , VAL_NONE ), // LO_LoadNull = 0x2A, + OPDEF(LoadString , VAL_EX ), // LO_LoadString = 0x2B, + OPDEF(LoadToken , VAL_NONE ), // LO_LoadToken = 0x2C, + + OPDEF(NewArray , VAL_EX ), // LO_NewArray = 0x2D, + OPDEF(LoadLength , VAL_EX ), // LO_LoadLength = 0x2E, + + OPDEF(StoreElement , VAL_EX ), // LO_StoreElement = 0x2F, + OPDEF(LoadElement , VAL_EX ), // LO_LoadElement = 0x30, + OPDEF(LoadElementAddress , VAL_EX ), // LO_LoadElementAddress = 0x31, + + OPDEF(StoreField , VAL_EX ), // LO_StoreField = 0x32, + OPDEF(LoadField , VAL_EX ), // LO_LoadField = 0x33, + OPDEF(LoadFieldAddress , VAL_EX ), // LO_LoadFieldAddress = 0x34, + + OPDEF(StoreStaticField , VAL_NONE ), // LO_StoreStaticField = 0x35, + OPDEF(LoadStaticField , VAL_NONE ), // LO_LoadStaticField = 0x36, + OPDEF(LoadStaticFieldAddress, VAL_NONE ), // LO_LoadStaticFieldAddress = 0x37, + + OPDEF(StoreIndirect , VAL_EX ), // LO_StoreIndirect = 0x38, + OPDEF(LoadIndirect , VAL_EX ), // LO_LoadIndirect = 0x39, + + OPDEF(InitObject , VAL_NONE ), // LO_InitObject = 0x3A, + OPDEF(LoadObject , VAL_EX ), // LO_LoadObject = 0x3B, + OPDEF(CopyObject , VAL_EX ), // LO_CopyObject = 0x3C, + OPDEF(StoreObject , VAL_EX ), // LO_StoreObject = 0x3D, + + OPDEF(Nop , VAL_NONE ), // LO_Nop = 0x3E, + + OPDEF(EndFilter , VAL_EX ), // LO_EndFilter = 0x3F, + + OPDEF(Unsupported , VAL_NONE ), // LO_Unsupported = 0x40, +}; + diff --git a/source/native/nf-interpreter/src/CLR/Core/Various.cpp b/source/native/nf-interpreter/src/CLR/Core/Various.cpp new file mode 100644 index 00000000..b810979a --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/Various.cpp @@ -0,0 +1,126 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +void CLR_RT_GetVersion( unsigned short int* pMajor, unsigned short int* pMinor, unsigned short int* pBuild, unsigned short int* pRevision ) +{ + NATIVE_PROFILE_CLR_CORE(); + if (pMajor) *pMajor = VERSION_MAJOR; + if (pMinor) *pMinor = VERSION_MINOR; + if (pBuild) *pBuild = VERSION_BUILD; + if (pRevision) *pRevision = VERSION_REVISION; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +HRESULT CLR_RT_ArrayListHelper::PrepareArrayList( CLR_RT_HeapBlock& thisRef, int count, int capacity ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* pThis = thisRef.Dereference(); FAULT_ON_NULL(pThis); + + if(count > capacity || capacity < 1) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + } + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( pThis[ FIELD___items ], capacity, g_CLR_RT_WellKnownTypes.m_Object )); + + pThis[ FIELD___size ].NumericByRef().s4 = count; + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_ArrayListHelper::ExtractArrayFromArrayList( CLR_RT_HeapBlock & thisRef, CLR_RT_HeapBlock_Array* & array, int& count, int& capacity ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* pThis; + CLR_RT_HeapBlock* items; + + pThis = thisRef.Dereference(); FAULT_ON_NULL(pThis); + items = &pThis[ FIELD___items ]; + + if(items->DataType() != DATATYPE_OBJECT) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + array = items->DereferenceArray(); FAULT_ON_NULL(array); + + if(array->DataType() != DATATYPE_SZARRAY) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + capacity = array->m_numOfElements; + count = pThis[ FIELD___size ].NumericByRef().s4; + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT CLR_RT_ByteArrayReader::Init( const unsigned char* src, unsigned int srcSize ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if (src == NULL || srcSize == 0) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + source = src; + sourceSize = srcSize; + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_ByteArrayReader::Read( void* dst, unsigned int size ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if (size > sourceSize) NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + + memcpy( dst, source, size ); + + source += size; + sourceSize -= size; + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_ByteArrayReader::Read1Byte( void* dst ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if (1 > sourceSize) NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + + *(unsigned char*)dst = *source; + + source++; + sourceSize--; + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_ByteArrayReader::Skip( unsigned int size ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + if (size > sourceSize) NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + + source += size; + sourceSize -= size; + + NANOCLR_NOCLEANUP(); +} + diff --git a/source/native/nf-interpreter/src/CLR/Core/corhdr_private.h b/source/native/nf-interpreter/src/CLR/Core/corhdr_private.h new file mode 100644 index 00000000..b9e98a54 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/corhdr_private.h @@ -0,0 +1,111 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _NANOCLR_CORHDR_H_ +#define _NANOCLR_CORHDR_H_ + +///////////////////////////////////////////////////////////////////////////// +// +// !!!! Lifted verbatim from corhdr.h !!!!! +// https://github.com/dotnet/coreclr/blob/master/src/inc/corhdr.h +// + +//***************************************************************************** +// +// Element type for Cor signature +// +//***************************************************************************** + +typedef enum CorElementType +{ + ELEMENT_TYPE_END = 0x0, + ELEMENT_TYPE_VOID = 0x1, + ELEMENT_TYPE_BOOLEAN = 0x2, + ELEMENT_TYPE_CHAR = 0x3, + ELEMENT_TYPE_I1 = 0x4, + ELEMENT_TYPE_U1 = 0x5, + ELEMENT_TYPE_I2 = 0x6, + ELEMENT_TYPE_U2 = 0x7, + ELEMENT_TYPE_I4 = 0x8, + ELEMENT_TYPE_U4 = 0x9, + ELEMENT_TYPE_I8 = 0xa, + ELEMENT_TYPE_U8 = 0xb, + ELEMENT_TYPE_R4 = 0xc, + ELEMENT_TYPE_R8 = 0xd, + ELEMENT_TYPE_STRING = 0xe, + + // every type above PTR will be simple type + ELEMENT_TYPE_PTR = 0xf, // PTR + ELEMENT_TYPE_BYREF = 0x10, // BYREF + + // Please use ELEMENT_TYPE_VALUETYPE. ELEMENT_TYPE_VALUECLASS is deprecated. + ELEMENT_TYPE_VALUETYPE = 0x11, // VALUETYPE + ELEMENT_TYPE_CLASS = 0x12, // CLASS + ELEMENT_TYPE_VAR = 0x13, // a class type variable VAR + ELEMENT_TYPE_ARRAY = 0x14, // MDARRAY ... ... + ELEMENT_TYPE_GENERICINST = 0x15, // instantiated type + ELEMENT_TYPE_TYPEDBYREF = 0x16, // This is a simple type. + + ELEMENT_TYPE_I = 0x18, // native integer size + ELEMENT_TYPE_U = 0x19, // native unsigned integer size + ELEMENT_TYPE_FNPTR = 0x1B, // FNPTR + ELEMENT_TYPE_OBJECT = 0x1C, // Shortcut for System.Object + ELEMENT_TYPE_SZARRAY = 0x1D, // Shortcut for single dimension zero lower bound array + // SZARRAY + ELEMENT_TYPE_MVAR = 0x1e, // a method type variable MVAR + + // This is only for binding + ELEMENT_TYPE_CMOD_REQD = 0x1F, // required C modifier : E_T_CMOD_REQD + ELEMENT_TYPE_CMOD_OPT = 0x20, // optional C modifier : E_T_CMOD_OPT + + // This is for signatures generated internally (which will not be persisted in any way). + ELEMENT_TYPE_INTERNAL = 0x21, // INTERNAL + + // Note that this is the max of base type excluding modifiers + ELEMENT_TYPE_MAX = 0x22, // first invalid element type + + + ELEMENT_TYPE_MODIFIER = 0x40, + ELEMENT_TYPE_SENTINEL = 0x01 | ELEMENT_TYPE_MODIFIER, // sentinel for varargs + ELEMENT_TYPE_PINNED = 0x05 | ELEMENT_TYPE_MODIFIER, + ELEMENT_TYPE_R4_HFA = 0x06 | ELEMENT_TYPE_MODIFIER, // used only internally for R4 HFA types + ELEMENT_TYPE_R8_HFA = 0x07 | ELEMENT_TYPE_MODIFIER, // used only internally for R8 HFA types + +} CorElementType; + +//***************************************************************************** +// +// Serialization types for Custom attribute support +// +//***************************************************************************** + +typedef enum CorSerializationType +{ + SERIALIZATION_TYPE_UNDEFINED = 0, + SERIALIZATION_TYPE_BOOLEAN = ELEMENT_TYPE_BOOLEAN, + SERIALIZATION_TYPE_CHAR = ELEMENT_TYPE_CHAR, + SERIALIZATION_TYPE_I1 = ELEMENT_TYPE_I1, + SERIALIZATION_TYPE_U1 = ELEMENT_TYPE_U1, + SERIALIZATION_TYPE_I2 = ELEMENT_TYPE_I2, + SERIALIZATION_TYPE_U2 = ELEMENT_TYPE_U2, + SERIALIZATION_TYPE_I4 = ELEMENT_TYPE_I4, + SERIALIZATION_TYPE_U4 = ELEMENT_TYPE_U4, + SERIALIZATION_TYPE_I8 = ELEMENT_TYPE_I8, + SERIALIZATION_TYPE_U8 = ELEMENT_TYPE_U8, + SERIALIZATION_TYPE_R4 = ELEMENT_TYPE_R4, + SERIALIZATION_TYPE_R8 = ELEMENT_TYPE_R8, + SERIALIZATION_TYPE_STRING = ELEMENT_TYPE_STRING, + SERIALIZATION_TYPE_SZARRAY = ELEMENT_TYPE_SZARRAY, // Shortcut for single dimension zero lower bound array + SERIALIZATION_TYPE_TYPE = 0x50, + SERIALIZATION_TYPE_TAGGED_OBJECT= 0x51, + SERIALIZATION_TYPE_FIELD = 0x53, + SERIALIZATION_TYPE_PROPERTY = 0x54, + SERIALIZATION_TYPE_ENUM = 0x55 +} CorSerializationType; + +///////////////////////////////////////////////////////////////////////////// + +#endif // _NANOCLR_CORHDR_H_ + diff --git a/source/native/nf-interpreter/src/CLR/Core/nanoSupport_CRC32.c b/source/native/nf-interpreter/src/CLR/Core/nanoSupport_CRC32.c new file mode 100644 index 00000000..b4e11c10 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Core/nanoSupport_CRC32.c @@ -0,0 +1,65 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include + +///////////////////////////////////////////////////////////////////////////// +// +// CRC 32 table for use under ZModem protocol, IEEE 802 +// G(x) = x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 +// +static const unsigned int c_CRCTable[256] = +{ + 0x00000000, 0x04C11DB7, 0x09823B6E, 0x0D4326D9, 0x130476DC, 0x17C56B6B, 0x1A864DB2, 0x1E475005, + 0x2608EDB8, 0x22C9F00F, 0x2F8AD6D6, 0x2B4BCB61, 0x350C9B64, 0x31CD86D3, 0x3C8EA00A, 0x384FBDBD, + 0x4C11DB70, 0x48D0C6C7, 0x4593E01E, 0x4152FDA9, 0x5F15ADAC, 0x5BD4B01B, 0x569796C2, 0x52568B75, + 0x6A1936C8, 0x6ED82B7F, 0x639B0DA6, 0x675A1011, 0x791D4014, 0x7DDC5DA3, 0x709F7B7A, 0x745E66CD, + 0x9823B6E0, 0x9CE2AB57, 0x91A18D8E, 0x95609039, 0x8B27C03C, 0x8FE6DD8B, 0x82A5FB52, 0x8664E6E5, + 0xBE2B5B58, 0xBAEA46EF, 0xB7A96036, 0xB3687D81, 0xAD2F2D84, 0xA9EE3033, 0xA4AD16EA, 0xA06C0B5D, + 0xD4326D90, 0xD0F37027, 0xDDB056FE, 0xD9714B49, 0xC7361B4C, 0xC3F706FB, 0xCEB42022, 0xCA753D95, + 0xF23A8028, 0xF6FB9D9F, 0xFBB8BB46, 0xFF79A6F1, 0xE13EF6F4, 0xE5FFEB43, 0xE8BCCD9A, 0xEC7DD02D, + 0x34867077, 0x30476DC0, 0x3D044B19, 0x39C556AE, 0x278206AB, 0x23431B1C, 0x2E003DC5, 0x2AC12072, + 0x128E9DCF, 0x164F8078, 0x1B0CA6A1, 0x1FCDBB16, 0x018AEB13, 0x054BF6A4, 0x0808D07D, 0x0CC9CDCA, + 0x7897AB07, 0x7C56B6B0, 0x71159069, 0x75D48DDE, 0x6B93DDDB, 0x6F52C06C, 0x6211E6B5, 0x66D0FB02, + 0x5E9F46BF, 0x5A5E5B08, 0x571D7DD1, 0x53DC6066, 0x4D9B3063, 0x495A2DD4, 0x44190B0D, 0x40D816BA, + 0xACA5C697, 0xA864DB20, 0xA527FDF9, 0xA1E6E04E, 0xBFA1B04B, 0xBB60ADFC, 0xB6238B25, 0xB2E29692, + 0x8AAD2B2F, 0x8E6C3698, 0x832F1041, 0x87EE0DF6, 0x99A95DF3, 0x9D684044, 0x902B669D, 0x94EA7B2A, + 0xE0B41DE7, 0xE4750050, 0xE9362689, 0xEDF73B3E, 0xF3B06B3B, 0xF771768C, 0xFA325055, 0xFEF34DE2, + 0xC6BCF05F, 0xC27DEDE8, 0xCF3ECB31, 0xCBFFD686, 0xD5B88683, 0xD1799B34, 0xDC3ABDED, 0xD8FBA05A, + 0x690CE0EE, 0x6DCDFD59, 0x608EDB80, 0x644FC637, 0x7A089632, 0x7EC98B85, 0x738AAD5C, 0x774BB0EB, + 0x4F040D56, 0x4BC510E1, 0x46863638, 0x42472B8F, 0x5C007B8A, 0x58C1663D, 0x558240E4, 0x51435D53, + 0x251D3B9E, 0x21DC2629, 0x2C9F00F0, 0x285E1D47, 0x36194D42, 0x32D850F5, 0x3F9B762C, 0x3B5A6B9B, + 0x0315D626, 0x07D4CB91, 0x0A97ED48, 0x0E56F0FF, 0x1011A0FA, 0x14D0BD4D, 0x19939B94, 0x1D528623, + 0xF12F560E, 0xF5EE4BB9, 0xF8AD6D60, 0xFC6C70D7, 0xE22B20D2, 0xE6EA3D65, 0xEBA91BBC, 0xEF68060B, + 0xD727BBB6, 0xD3E6A601, 0xDEA580D8, 0xDA649D6F, 0xC423CD6A, 0xC0E2D0DD, 0xCDA1F604, 0xC960EBB3, + 0xBD3E8D7E, 0xB9FF90C9, 0xB4BCB610, 0xB07DABA7, 0xAE3AFBA2, 0xAAFBE615, 0xA7B8C0CC, 0xA379DD7B, + 0x9B3660C6, 0x9FF77D71, 0x92B45BA8, 0x9675461F, 0x8832161A, 0x8CF30BAD, 0x81B02D74, 0x857130C3, + 0x5D8A9099, 0x594B8D2E, 0x5408ABF7, 0x50C9B640, 0x4E8EE645, 0x4A4FFBF2, 0x470CDD2B, 0x43CDC09C, + 0x7B827D21, 0x7F436096, 0x7200464F, 0x76C15BF8, 0x68860BFD, 0x6C47164A, 0x61043093, 0x65C52D24, + 0x119B4BE9, 0x155A565E, 0x18197087, 0x1CD86D30, 0x029F3D35, 0x065E2082, 0x0B1D065B, 0x0FDC1BEC, + 0x3793A651, 0x3352BBE6, 0x3E119D3F, 0x3AD08088, 0x2497D08D, 0x2056CD3A, 0x2D15EBE3, 0x29D4F654, + 0xC5A92679, 0xC1683BCE, 0xCC2B1D17, 0xC8EA00A0, 0xD6AD50A5, 0xD26C4D12, 0xDF2F6BCB, 0xDBEE767C, + 0xE3A1CBC1, 0xE760D676, 0xEA23F0AF, 0xEEE2ED18, 0xF0A5BD1D, 0xF464A0AA, 0xF9278673, 0xFDE69BC4, + 0x89B8FD09, 0x8D79E0BE, 0x803AC667, 0x84FBDBD0, 0x9ABC8BD5, 0x9E7D9662, 0x933EB0BB, 0x97FFAD0C, + 0xAFB010B1, 0xAB710D06, 0xA6322BDF, 0xA2F33668, 0xBCB4666D, 0xB8757BDA, 0xB5365D03, 0xB1F740B4 +}; + +/////////////////////////////////////////////////////////////////////////////////////////////////////////// +// This is declared with GCC weak attribute so it can be replaced with an implementation at target level // +// Currently this is happening with the STM32 targets as all chips feature a CRC hardware unit // +/////////////////////////////////////////////////////////////////////////////////////////////////////////// +__nfweak unsigned int SUPPORT_ComputeCRC(const void* rgBlock, int nLength, unsigned int crc) +{ + const unsigned char* ptr = (const unsigned char*)rgBlock; + + while(nLength-- > 0) + { + crc = c_CRCTable[((crc >> 24) ^ (*ptr++)) & 0xFF] ^ (crc << 8); + } + + return crc; +}; diff --git a/source/native/nf-interpreter/src/CLR/Debugger/CMakeLists.txt b/source/native/nf-interpreter/src/CLR/Debugger/CMakeLists.txt new file mode 100644 index 00000000..ab90ee1a --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Debugger/CMakeLists.txt @@ -0,0 +1,16 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append Wire Protocol files to source +# list(APPEND DEBUGGER_WIRE_PROTOCOL_SOURCES_LIST "${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_Commands.c") +# list(APPEND DEBUGGER_WIRE_PROTOCOL_SOURCES_LIST "${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_App_Interface.c") +# make Wire Protocol files list global +# set(DEBUGGER_WIRE_PROTOCOL_SOURCES ${DEBUGGER_WIRE_PROTOCOL_SOURCES_LIST} CACHE INTERNAL "CLR debugger Wire Protocol source files list") + + +# append Wire Protocol include directory +list(APPEND DEBUGGER_WIRE_PROTOCOL_INCLUDE_DIRS_LIST "${CMAKE_CURRENT_SOURCE_DIR}") +# make include dirs global +set(DEBUGGER_WIRE_PROTOCOL_INCLUDE_DIRS ${DEBUGGER_WIRE_PROTOCOL_INCLUDE_DIRS_LIST} CACHE INTERNAL "CLR debugger Wire Protocol include dirs list") diff --git a/source/native/nf-interpreter/src/CLR/Debugger/Debugger.cpp b/source/native/nf-interpreter/src/CLR/Debugger/Debugger.cpp new file mode 100644 index 00000000..cf320930 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Debugger/Debugger.cpp @@ -0,0 +1,3417 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include +#include +#include +#include +#include +#include +#include "Debugger.h" +#include + +#define __min(a,b) (((a) < (b)) ? (a) : (b)) + +#if 0 +#define TRACE0( msg, ...) debug_printf( msg ) +#define TRACE( msg, ...) debug_printf( msg, __VA_ARGS__ ) +char const* const AccessMemoryModeNames[] = { +"AccessMemory_Check", +"AccessMemory_Read", +"AccessMemory_Write", +"AccessMemory_Erase" +}; +#else +#define TRACE0(msg,...) +#define TRACE(msg,...) +#endif + +//--// + +BlockStorageDevice* CLR_DBG_Debugger::m_deploymentStorageDevice = NULL; + +//--// + +void CLR_DBG_Debugger::Debugger_WaitForCommands() +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Waiting for debug commands...\r\n" ); +#endif + + while( !CLR_EE_DBG_IS(RebootPending) && !CLR_EE_DBG_IS(ExitPending) ) + { + g_CLR_RT_ExecutionEngine.DebuggerLoop(); + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +HRESULT CLR_DBG_Debugger::CreateInstance() +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + NANOCLR_HEADER(); + + g_CLR_DBG_Debugger = (CLR_DBG_Debugger*)&g_scratchDebugger[0]; + + + + CLR_RT_Memory::ZeroFill( g_CLR_DBG_Debugger, sizeof(CLR_DBG_Debugger) ); + + g_CLR_DBG_Debugger->m_messaging = (CLR_Messaging*)&g_scratchDebuggerMessaging[0]; + + NANOCLR_CHECK_HRESULT(g_CLR_DBG_Debugger->Debugger_Initialize(HalSystemConfig.DebuggerPort)); + + BlockStorageStream stream; + memset(&stream, 0, sizeof(BlockStorageStream)); + + if (BlockStorageStream_Initialize(&stream, BlockUsage_DEPLOYMENT )) + { + m_deploymentStorageDevice = stream.Device; + } + else + { + m_deploymentStorageDevice = NULL; + } + + // UNDONE: FIXME: MFUpdate_Initialize(); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_DBG_Debugger::Debugger_Initialize( COM_HANDLE port ) +{ + (void)port; + + NATIVE_PROFILE_CLR_DEBUGGER(); + NANOCLR_HEADER(); + + m_messaging->Initialize( c_Debugger_Lookup_Request, c_Debugger_Lookup_Request_count, c_Debugger_Lookup_Reply, c_Debugger_Lookup_Reply_count ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +//--// + +HRESULT CLR_DBG_Debugger::DeleteInstance() +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + NANOCLR_HEADER(); + + g_CLR_DBG_Debugger->Debugger_Cleanup(); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +void CLR_DBG_Debugger::Debugger_Cleanup() +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + m_messaging->Cleanup(); +} + +//--// + +// void CLR_DBG_Debugger::ProcessCommands() +// { +// NATIVE_PROFILE_CLR_DEBUGGER(); +// m_messaging->m_controller.AdvanceState(); +// } + +void CLR_DBG_Debugger::BroadcastEvent( unsigned int cmd, unsigned int payloadSize, unsigned char* payload, unsigned int flags ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + WP_PrepareAndSendProtocolMessage( cmd, payloadSize, payload, flags ); +} + +//--// + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + +#if defined(NANOCLR_APPDOMAINS) + +CLR_RT_AppDomain* CLR_DBG_Debugger::GetAppDomainFromID( CLR_UINT32 id ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + NANOCLR_FOREACH_NODE(CLR_RT_AppDomain, appDomain, g_CLR_RT_ExecutionEngine.m_appDomains) + { + if(appDomain->m_id == id) return appDomain; + } + NANOCLR_FOREACH_NODE_END(); + + return NULL; +} +#endif //NANOCLR_APPDOMAINS + +CLR_RT_Thread* CLR_DBG_Debugger::GetThreadFromPid( CLR_INT32 pid ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + NANOCLR_FOREACH_NODE(CLR_RT_Thread,th,g_CLR_RT_ExecutionEngine.m_threadsReady) + { + if(th->m_pid == pid) return th; + } + NANOCLR_FOREACH_NODE_END(); + + NANOCLR_FOREACH_NODE(CLR_RT_Thread,th,g_CLR_RT_ExecutionEngine.m_threadsWaiting) + { + if(th->m_pid == pid) return th; + } + NANOCLR_FOREACH_NODE_END(); + + return NULL; +} + +HRESULT CLR_DBG_Debugger::CreateListOfThreads( CLR_DBG_Commands::Debugging_Thread_List::Reply*& cmdReply, int& totLen ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + NANOCLR_HEADER(); + + CLR_UINT32* pidDst; + int num; + + num = g_CLR_RT_ExecutionEngine.m_threadsReady .NumOfNodes() + + g_CLR_RT_ExecutionEngine.m_threadsWaiting.NumOfNodes(); + + totLen = sizeof(*cmdReply) + (num-1) * sizeof(CLR_UINT32); + + cmdReply = (CLR_DBG_Commands::Debugging_Thread_List::Reply*)CLR_RT_Memory::Allocate_And_Erase( totLen, true ); CHECK_ALLOCATION(cmdReply); + + cmdReply->m_num = num; + + pidDst = cmdReply->m_pids; + + NANOCLR_FOREACH_NODE(CLR_RT_Thread,thSrc,g_CLR_RT_ExecutionEngine.m_threadsReady) + { + *pidDst++ = thSrc->m_pid; + } + NANOCLR_FOREACH_NODE_END(); + + NANOCLR_FOREACH_NODE(CLR_RT_Thread,thSrc,g_CLR_RT_ExecutionEngine.m_threadsWaiting) + { + *pidDst++ = thSrc->m_pid; + } + NANOCLR_FOREACH_NODE_END(); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_DBG_Debugger::CreateListOfCalls( CLR_INT32 pid, CLR_DBG_Commands::Debugging_Thread_Stack::Reply*& cmdReply, int& totLen ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + NANOCLR_HEADER(); + + CLR_RT_Thread* th = GetThreadFromPid( pid ); FAULT_ON_NULL(th); + + for(int pass=0; pass<2; pass++) + { + int num = 0; + + NANOCLR_FOREACH_NODE(CLR_RT_StackFrame,call,th->m_stackFrames) + { + if(pass == 1) + { + int tmp = num; + +#ifndef CLR_NO_IL_INLINE + if(call->m_inlineFrame) + { + CLR_DBG_Commands::Debugging_Thread_Stack::Reply::Call& dst = cmdReply->m_data[ tmp++ ]; + + dst.m_md = call->m_inlineFrame->m_frame.m_call; + dst.m_IP = (CLR_UINT32)(call->m_inlineFrame->m_frame.m_IP - call->m_inlineFrame->m_frame.m_IPStart); +#if defined(NANOCLR_APPDOMAINS) + dst.m_appDomainID = call->m_appDomain->m_id; + dst.m_flags = call->m_flags; +#endif + } +#endif + CLR_DBG_Commands::Debugging_Thread_Stack::Reply::Call& dst = cmdReply->m_data[ tmp ]; + + dst.m_md = call->m_call; + dst.m_IP = (CLR_UINT32)(call->m_IP - call->m_IPstart); + + if(dst.m_IP && call != th->CurrentFrame()) + { + //With the exception of when the IP is 0, for a breakpoint on Push, + //The call->m_IP is the next instruction to execute, not the currently executing one. + //For non-leaf frames, this will return the IP within the call. + dst.m_IP--; + } + +#if defined(NANOCLR_APPDOMAINS) + dst.m_appDomainID = call->m_appDomain->m_id; + dst.m_flags = call->m_flags; +#endif + } + +#ifndef CLR_NO_IL_INLINE + if(call->m_inlineFrame) + { + num++; + } +#endif + + num++; + } + NANOCLR_FOREACH_NODE_END(); + + if(pass == 0) + { + totLen = sizeof(*cmdReply) + (num-1) * sizeof(CLR_DBG_Commands::Debugging_Thread_Stack::Reply::Call); + + cmdReply = (CLR_DBG_Commands::Debugging_Thread_Stack::Reply*)CLR_RT_Memory::Allocate_And_Erase( totLen, CLR_RT_HeapBlock::HB_CompactOnFailure ); CHECK_ALLOCATION(cmdReply); + + cmdReply->m_num = num; + cmdReply->m_status = th->m_status; + cmdReply->m_flags = th->m_flags; + } + } + + NANOCLR_NOCLEANUP(); +} + +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +bool CLR_DBG_Debugger::Monitor_Ping( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + bool fStopOnBoot = true; + + // + // There's someone on the other side!! + // + CLR_EE_DBG_SET( Enabled ); + + if((msg->m_header.m_flags & WP_Flags_c_Reply ) == 0) + { + Monitor_Ping_Reply cmdReply; + Monitor_Ping_Command *cmd = (Monitor_Ping_Command*)msg->m_payload; + + // default is to stop the debugger (backwards compatibility) + fStopOnBoot = (cmd != NULL) && (cmd->m_dbg_flags & Monitor_Ping_c_Ping_DbgFlag_Stop); + + cmdReply.m_source = Monitor_Ping_c_Ping_Source_NanoCLR; + + cmdReply.m_dbg_flags = CLR_EE_DBG_IS(StateProgramExited) != 0 ? Monitor_Ping_c_Ping_DbgFlag_AppExit : 0; + + #if defined(WP_IMPLEMENTS_CRC32) + cmdReply.m_dbg_flags |= Monitor_Ping_c_Ping_WPFlag_SupportsCRC32; + #endif + + // Wire Protocol packet size + #if (WP_PACKET_SIZE == 512) + cmdReply.m_dbg_flags |= Monitor_Ping_c_PacketSize_0512; + #elif (WP_PACKET_SIZE == 256) + cmdReply.m_dbg_flags |= Monitor_Ping_c_PacketSize_0256; + #elif (WP_PACKET_SIZE == 128) + cmdReply.m_dbg_flags |= Monitor_Ping_c_PacketSize_0128; + #elif (WP_PACKET_SIZE == 1024) + cmdReply.m_dbg_flags |= Monitor_Ping_c_PacketSize_1024; + #endif + + WP_ReplyToCommand( msg, true, false, &cmdReply, sizeof(cmdReply) ); + } + else + { + Monitor_Ping_Reply *cmdReply = (Monitor_Ping_Reply*)msg->m_payload; + + // default is to stop the debugger (backwards compatibility) + fStopOnBoot = (cmdReply != NULL) && (cmdReply->m_dbg_flags & Monitor_Ping_c_Ping_DbgFlag_Stop); + } + + if(CLR_EE_DBG_IS_MASK(StateInitialize, StateMask)) + { + if(fStopOnBoot) CLR_EE_DBG_SET(Stopped); + else CLR_EE_DBG_CLR(Stopped); + } + + return true; +} + +bool CLR_DBG_Debugger::Monitor_FlashSectorMap( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + if((msg->m_header.m_flags & WP_Flags_c_Reply) == 0) + { + struct Flash_BlockRegionInfo + { + unsigned int StartAddress; + unsigned int NumBlocks; + unsigned int BytesPerBlock; + unsigned int Usage; + + } *pData = NULL; + + unsigned int rangeCount = 0; + unsigned int rangeIndex = 0; + + // get the number of available block storage devices + unsigned int numDevices = BlockStorageList_GetNumDevices(); + + // get an array of pointer to all the storage devices in the list and then request the device info + BlockStorageDevice** devices = (BlockStorageDevice**) platform_malloc(numDevices * sizeof(BlockStorageDevice*)); + DeviceBlockInfo** deviceInfos = (DeviceBlockInfo**) platform_malloc(numDevices * sizeof(DeviceBlockInfo*)); + + for(unsigned int i = 0; i < numDevices; i++) + { + if(i == 0) + { + devices[i] = BlockStorageList_GetFirstDevice(); + } + else + { + devices[i] = BlockStorageList_GetNextDevice(devices[i-1]); + } + // sanity check + if(devices[i] == NULL) + { + WP_ReplyToCommand( msg, true, false, NULL, 0 ); + return false; + } + deviceInfos[i] = BlockStorageDevice_GetDeviceInfo(devices[i]); + } + + for(int cnt = 0; cnt < 2; cnt++) + { + if(cnt == 1) + { + pData = (struct Flash_BlockRegionInfo*)platform_malloc(rangeCount * sizeof(struct Flash_BlockRegionInfo)); + + if(pData == NULL) + { + WP_ReplyToCommand( msg, true, false, NULL, 0 ); + return false; + } + } + for(unsigned int i = 0; i < numDevices; i++) + { + for(unsigned int j = 0; j < deviceInfos[i]->NumRegions; j++) + { + const BlockRegionInfo* pRegion = &deviceInfos[i]->Regions[ j ]; + + for(unsigned int k = 0; k < pRegion->NumBlockRanges; k++) + { + + if(cnt == 0) + { + rangeCount++; + } + else + { + pData[ rangeIndex ].StartAddress = BlockRegionInfo_BlockAddress(pRegion, pRegion->BlockRanges[ k ].StartBlock); + pData[ rangeIndex ].NumBlocks = BlockRange_GetBlockCount(pRegion->BlockRanges[k]); + pData[ rangeIndex ].BytesPerBlock = pRegion->BytesPerBlock; + pData[ rangeIndex ].Usage = pRegion->BlockRanges[ k ].RangeType & BlockRange_USAGE_MASK; + rangeIndex++; + } + } + } + } + } + + + WP_ReplyToCommand( msg, true, false, (void*)pData, rangeCount * sizeof (struct Flash_BlockRegionInfo) ); + + platform_free(pData); + platform_free(devices); + platform_free(deviceInfos); + } + + return true; + +} + +//--// + + + + + + + +bool CLR_DBG_Debugger::CheckPermission( ByteAddress address, int mode ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + bool hasPermission = false; + unsigned int regionIndex, rangeIndex; + + BlockStorageDevice_FindRegionFromAddress(m_deploymentStorageDevice, address, ®ionIndex, &rangeIndex); + const BlockRange& range = BlockStorageDevice_GetDeviceInfo(m_deploymentStorageDevice)->Regions[ regionIndex ].BlockRanges[ rangeIndex ]; + + + switch(mode) + { + case AccessMemory_Check: + hasPermission = true; + break; + case AccessMemory_Read: +#if defined(BUILD_RTM) + if(!DebuggerPort_IsUsingSsl(HalSystemConfig.DebuggerPort)) + break; +#endif + switch(range.RangeType) + { + case BlockRange_BLOCKTYPE_CONFIG: // fall through + case BlockRange_BLOCKTYPE_BOOTSTRAP: // fall through + case BlockRange_BLOCKTYPE_CODE: // fall through + case BlockRange_BLOCKTYPE_DIRTYBIT: // fall through + case BlockRange_BLOCKTYPE_DEPLOYMENT: // fall through + case BlockRange_BLOCKTYPE_FILESYSTEM: // fall through + case BlockRange_BLOCKTYPE_STORAGE_A: // fall through + case BlockRange_BLOCKTYPE_STORAGE_B: + case BlockRange_BLOCKTYPE_SIMPLE_A: + case BlockRange_BLOCKTYPE_SIMPLE_B: + case BlockRange_BLOCKTYPE_UPDATE: + + hasPermission = true; + break; + } + break; + case AccessMemory_Write: +#if defined(BUILD_RTM) + if(!DebuggerPort_IsUsingSsl(HalSystemConfig.DebuggerPort)) + break; +#endif + if(BlockRange_IsDeployment(range) || BlockRange_IsConfig(range)) + { + hasPermission = true; + } + else + { + hasPermission = DebuggerPort_IsUsingSsl(HalSystemConfig.DebuggerPort) == true; + } + break; + case AccessMemory_Erase: +#if defined(BUILD_RTM) + if(!DebuggerPort_IsUsingSsl(HalSystemConfig.DebuggerPort)) + break; +#endif + switch(range.RangeType) + { + case BlockRange_BLOCKTYPE_DEPLOYMENT: + case BlockRange_BLOCKTYPE_FILESYSTEM: + case BlockRange_BLOCKTYPE_STORAGE_A: + case BlockRange_BLOCKTYPE_STORAGE_B: + case BlockRange_BLOCKTYPE_SIMPLE_A: + case BlockRange_BLOCKTYPE_SIMPLE_B: + case BlockRange_BLOCKTYPE_UPDATE: + case BlockRange_BLOCKTYPE_CONFIG: + hasPermission = true; + break; + } + break; + default: + hasPermission = false; + break; + } + + return hasPermission; +} + +bool CLR_DBG_Debugger::AccessMemory( CLR_UINT32 location, unsigned int lengthInBytes, unsigned char* buf, int mode, unsigned int* errorCode ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + TRACE("AccessMemory( 0x%08X, 0x%08x, 0x%08X, %s)\n", location, lengthInBytes, buf, AccessMemoryModeNames[mode] ); + + bool success = false; + + // reset error code + *errorCode = AccessMemoryErrorCode_NoError; + + //--// + unsigned int iRegion, iRange; + + if (BlockStorageDevice_FindRegionFromAddress(m_deploymentStorageDevice, location, &iRegion, &iRange)) + { + const DeviceBlockInfo* deviceInfo = BlockStorageDevice_GetDeviceInfo(m_deploymentStorageDevice); + + // start from the block where the sector sits. + ByteAddress accessAddress = location; + + unsigned char* bufPtr = buf; + signed int accessLenInBytes = lengthInBytes; + signed int blockOffset = BlockRegionInfo_OffsetFromBlock(((BlockRegionInfo*)(&deviceInfo->Regions[iRegion])), accessAddress); + + for(;iRegion < deviceInfo->NumRegions; iRegion++) + { + const BlockRegionInfo *pRegion = &deviceInfo->Regions[ iRegion ]; + + unsigned int blockIndex = BlockRegionInfo_BlockIndexFromAddress(pRegion, accessAddress); + unsigned int accessMaxLength = pRegion->BytesPerBlock - blockOffset; + + blockOffset = 0; + + for(;blockIndex < pRegion->NumBlocks; blockIndex++) + { + //accessMaxLength =the current largest number of bytes can be read from the block from the address to its block boundary. + unsigned int NumOfBytes = __min(accessMaxLength, (unsigned int)accessLenInBytes); + + accessMaxLength = pRegion->BytesPerBlock; + + if(blockIndex > pRegion->BlockRanges[ iRange ].EndBlock) + { + iRange++; + + if(iRange >= pRegion->NumBlockRanges) + { + ASSERT(false); + break; + } + } + + // since AccessMemory_Check is always true and will not break from here, no need to check AccessMemory_Check to free memory. + if(!CheckPermission( accessAddress, mode )) + { + TRACE0("=> Permission check failed!\n"); + + // set error code + *errorCode = AccessMemoryErrorCode_PermissionDenied; + + // done here + return success; + } + + switch(mode) + { + case AccessMemory_Check: + case AccessMemory_Read: + if(deviceInfo->Attribute & MediaAttribute_SupportsXIP) + { + memcpy( (unsigned char*)bufPtr, (const void*)accessAddress, NumOfBytes ); + success = true; + } + else + { + if (mode == AccessMemory_Check) + { + bufPtr = (unsigned char*) CLR_RT_Memory::Allocate( lengthInBytes, true ); + + if(!bufPtr) + { + TRACE0( "=> Failed to allocate data buffer\n"); + + // set error code + *errorCode = AccessMemoryErrorCode_PermissionDenied; + + // done here + return success; + } + } + + success = BlockStorageDevice_Read(m_deploymentStorageDevice, accessAddress , NumOfBytes, (unsigned char *)bufPtr); + + if (mode == AccessMemory_Check) + { + *(unsigned int*)buf = SUPPORT_ComputeCRC( bufPtr, NumOfBytes, *(unsigned int*)buf ); + + CLR_RT_Memory::Release( bufPtr ); + } + } + break; + + case AccessMemory_Write: + success = BlockStorageDevice_Write(m_deploymentStorageDevice, accessAddress , NumOfBytes, (unsigned char *)bufPtr, false); + break; + + case AccessMemory_Erase: + if (BlockStorageDevice_IsBlockErased(m_deploymentStorageDevice, accessAddress, NumOfBytes)) + { + // block is erased, we are good + success = true; + } + else + { + // need to erase block + success = BlockStorageDevice_EraseBlock(m_deploymentStorageDevice, accessAddress); + } + break; + + default: + break; + } + + if(!success) + { + // set error code + *errorCode = AccessMemoryErrorCode_RequestedOperationFailed; + + break; + } + + accessLenInBytes -= NumOfBytes; + + if (accessLenInBytes <= 0) + { + break; + } + + bufPtr += NumOfBytes; + accessAddress += NumOfBytes; + } + + blockIndex = 0; + iRange = 0; + + if ((accessLenInBytes <= 0) || (!success)) + { + break; + } + } + } + else + { + //--// RAM write + ByteAddress sectAddr = location; + + #if defined(_WIN32) + + bool proceed = false; + void * temp; + temp = (void *) sectAddr; + + switch(mode) + { + case AccessMemory_Check: + break; + + case AccessMemory_Read: + proceed = IsBadReadPtr( temp, lengthInBytes ) == false; + break; + + case AccessMemory_Write: + proceed = IsBadWritePtr( temp, lengthInBytes ) == false; + break; + } + + if(proceed) + #else + + unsigned int sectAddrEnd = sectAddr + lengthInBytes; + unsigned int ramStartAddress = HalSystemConfig.RAM1.Base; + unsigned int ramEndAddress = ramStartAddress + HalSystemConfig.RAM1.Size ; + + if((sectAddr =ramEndAddress) || (sectAddrEnd >ramEndAddress) ) + { + TRACE(" Invalid address %x and range %x Ram Start %x, Ram end %x\r\n", sectAddr, lengthInBytes, ramStartAddress, ramEndAddress); + return success; + } + else + #endif + { + switch(mode) + { + case AccessMemory_Check: + break; + + case AccessMemory_Read: + memcpy( buf, (const void*)sectAddr, lengthInBytes ); + break; + + case AccessMemory_Write: + unsigned char * memPtr; + memPtr = (unsigned char*)sectAddr; + memcpy( memPtr, buf, lengthInBytes ); + break; + + case AccessMemory_Erase: + memPtr = (unsigned char*)sectAddr; + if (lengthInBytes !=0) + memset( memPtr, 0xFF, lengthInBytes ); + break; + + default: + break; + } + } + } + + TRACE0( "=> SUCCESS\n"); + + return success; +} + +bool CLR_DBG_Debugger::Monitor_ReadMemory( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Monitor_ReadMemory* cmd = (CLR_DBG_Commands::Monitor_ReadMemory*)msg->m_payload; + CLR_DBG_Commands::Monitor_ReadMemory::Reply* cmdReply = NULL; + + uint32_t allocationSize = 0; + uint32_t len = cmd->m_length; + + // adjust length, if bigger than the WP packet size + if (len > WP_PACKET_SIZE) + { + len = WP_PACKET_SIZE; + } + + if (m_deploymentStorageDevice != NULL) + { + // start computing allocation size, fist the ErrorCode field... + allocationSize = offsetof(CLR_DBG_Commands::Monitor_ReadMemory::Reply, m_data); + // ... and the buffer + allocationSize += len; + + // allocate memory + cmdReply = (CLR_DBG_Commands::Monitor_ReadMemory::Reply*)platform_malloc(allocationSize); + + // sanity check + if(cmdReply != NULL) + { + // clear allocated memory + memset(cmdReply, 0, allocationSize); + + g_CLR_DBG_Debugger->AccessMemory( cmd->m_address, len, (unsigned char*)&cmdReply->m_data, AccessMemory_Read, &cmdReply->ErrorCode ); + + WP_ReplyToCommand( msg, true, false, cmdReply, allocationSize ); + + // free allocated memory + platform_free(cmdReply); + + // done here + return true; + } + } + + return false; +} + +bool CLR_DBG_Debugger::Monitor_WriteMemory( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Monitor_WriteMemory* cmd = (CLR_DBG_Commands::Monitor_WriteMemory*)msg->m_payload; + CLR_DBG_Commands::Monitor_WriteMemory::Reply cmdReply; + + if (m_deploymentStorageDevice != NULL) + { + + g_CLR_DBG_Debugger->AccessMemory( cmd->m_address, cmd->m_length, cmd->m_data, AccessMemory_Write, &cmdReply.ErrorCode ); + + WP_ReplyToCommand(msg, true, false, &cmdReply, sizeof(cmdReply)); + + return true; + } + + return false; +} + +bool CLR_DBG_Debugger::Monitor_CheckMemory( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Monitor_CheckMemory* cmd = (CLR_DBG_Commands::Monitor_CheckMemory*)msg->m_payload; + CLR_DBG_Commands::Monitor_CheckMemory::Reply cmdReply; + unsigned int errorCode; + + g_CLR_DBG_Debugger->AccessMemory( cmd->m_address, cmd->m_length, (unsigned char*)&cmdReply.m_crc, AccessMemory_Check, &errorCode ); + + WP_ReplyToCommand( msg, true, false, &cmdReply, sizeof(cmdReply) ); + + return true; + +} + +bool CLR_DBG_Debugger::Monitor_EraseMemory( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Monitor_EraseMemory* cmd = (CLR_DBG_Commands::Monitor_EraseMemory*)msg->m_payload; + CLR_DBG_Commands::Monitor_EraseMemory::Reply cmdReply; + + if (m_deploymentStorageDevice != NULL) + { + g_CLR_DBG_Debugger->AccessMemory( cmd->m_address, cmd->m_length, NULL, AccessMemory_Erase, &cmdReply.ErrorCode ); + + WP_ReplyToCommand(msg, true, false, &cmdReply, sizeof(cmdReply)); + + return true; + } + + return false; +} + +bool CLR_DBG_Debugger::Monitor_Execute( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + + CLR_DBG_Commands::Monitor_Execute* cmd = (CLR_DBG_Commands::Monitor_Execute*)msg->m_payload; + +#if defined(BUILD_RTM) + if(!DebuggerPort_IsUsingSsl(HalSystemConfig.DebuggerPort)) + return false; +#endif + + WP_ReplyToCommand(msg, true, false, NULL, 0); + + ((void (*)())(size_t)cmd->m_address)(); + + return true; +} + +bool CLR_DBG_Debugger::Monitor_Reboot( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Monitor_Reboot* cmd = (CLR_DBG_Commands::Monitor_Reboot*)msg->m_payload; + + if(NULL != cmd) + { + if(CLR_DBG_Commands::Monitor_Reboot::c_EnterBootloader == (cmd->m_flags & CLR_DBG_Commands::Monitor_Reboot::c_EnterBootloader)) + { + WP_ReplyToCommand(msg, true, false, NULL, 0); + + Events_WaitForEvents( 0, 100 ); // give message a little time to be flushed + + HAL_EnterBooterMode(); + } + + g_CLR_RT_ExecutionEngine.m_iReboot_Options = cmd->m_flags; + } + + CLR_EE_DBG_SET( RebootPending ); + + WP_ReplyToCommand(msg, true, false, NULL, 0); + + return true; +} + +bool CLR_DBG_Debugger::Monitor_MemoryMap( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + MemoryMap_Range map[2]; + + map[0].m_address = HalSystemConfig.RAM1.Base; + map[0].m_length = HalSystemConfig.RAM1.Size; + map[0].m_flags = Monitor_MemoryMap_c_RAM; + + map[1].m_address = HalSystemConfig.FLASH1.Base; + map[1].m_length = HalSystemConfig.FLASH1.Size; + map[1].m_flags = Monitor_MemoryMap_c_FLASH; + + WP_ReplyToCommand(msg, true, false, map, sizeof(map)); + + return true; +} + +bool CLR_DBG_Debugger::Monitor_DeploymentMap( WP_Message* msg) +{ + (void)msg; + + return true; +} + +bool CLR_DBG_Debugger::Monitor_QueryConfiguration( WP_Message* message) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + bool success = false; + + // include handling of configuration block only if feature is available + #if (HAS_CONFIG_BLOCK == TRUE) + + Monitor_QueryConfiguration_Command *cmd = (Monitor_QueryConfiguration_Command*)message->m_payload; + int size = 0; + int sizeOfBlock = 0; + + HAL_Configuration_NetworkInterface* configNetworkInterface; + HAL_Configuration_Wireless80211* configWireless80211NetworkInterface; + HAL_Configuration_X509CaRootBundle* x509Certificate; + + switch((DeviceConfigurationOption)cmd->Configuration) + { + case DeviceConfigurationOption_Network: + + configNetworkInterface = (HAL_Configuration_NetworkInterface*)platform_malloc(sizeof(HAL_Configuration_NetworkInterface)); + memset(configNetworkInterface, 0, sizeof(HAL_Configuration_NetworkInterface)); + + if(ConfigurationManager_GetConfigurationBlock(configNetworkInterface, (DeviceConfigurationOption)cmd->Configuration, cmd->BlockIndex) == true) + { + size = sizeof(HAL_Configuration_NetworkInterface); + success = true; + + WP_ReplyToCommand( message, success, false, (uint8_t*)configNetworkInterface, size ); + } + platform_free(configNetworkInterface); + break; + + case DeviceConfigurationOption_Wireless80211Network: + + configWireless80211NetworkInterface = (HAL_Configuration_Wireless80211*)platform_malloc(sizeof(HAL_Configuration_Wireless80211)); + memset(configWireless80211NetworkInterface, 0, sizeof(HAL_Configuration_Wireless80211)); + + if(ConfigurationManager_GetConfigurationBlock(configWireless80211NetworkInterface, (DeviceConfigurationOption)cmd->Configuration, cmd->BlockIndex) == true) + { + size = sizeof(HAL_Configuration_Wireless80211); + success = true; + + WP_ReplyToCommand( message, success, false, (uint8_t*)configWireless80211NetworkInterface, size ); + } + platform_free(configWireless80211NetworkInterface); + break; + + case DeviceConfigurationOption_X509CaRootBundle: + + if(g_TargetConfiguration.CertificateStore->Count > cmd->BlockIndex ) + { + // because X509 certificate has a variable length need to compute the block size in two steps + sizeOfBlock = offsetof(HAL_Configuration_X509CaRootBundle, Certificate); + sizeOfBlock += g_TargetConfiguration.CertificateStore->Certificates[cmd->BlockIndex]->CertificateSize; + } + + x509Certificate = (HAL_Configuration_X509CaRootBundle*)platform_malloc(sizeOfBlock); + memset(x509Certificate, 0, sizeof(sizeOfBlock)); + + if(ConfigurationManager_GetConfigurationBlock(x509Certificate, (DeviceConfigurationOption)cmd->Configuration, cmd->BlockIndex) == true) + { + size = sizeOfBlock; + success = true; + + WP_ReplyToCommand( message, success, false, (uint8_t*)x509Certificate, size ); + } + platform_free(x509Certificate); + break; + + case DeviceConfigurationOption_WirelessNetworkAP: + // TODO missing implementation for now + break; + + default: + break; + } + + if(!success) + { + WP_ReplyToCommand( message, success, false, NULL, size ); + } + + #else + + (void)message; + + #endif // (HAS_CONFIG_BLOCK == TRUE) + + return success; +} + +bool CLR_DBG_Debugger::Monitor_UpdateConfiguration(WP_Message* message) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + bool success = false; + + // include handling of configuration block only if feature is available + #if (HAS_CONFIG_BLOCK == TRUE) + + Monitor_UpdateConfiguration_Command* cmd = (Monitor_UpdateConfiguration_Command*)message->m_payload; + Monitor_UpdateConfiguration_Reply cmdReply; + + switch((DeviceConfigurationOption)cmd->Configuration) + { + case DeviceConfigurationOption_Network: + case DeviceConfigurationOption_Wireless80211Network: + case DeviceConfigurationOption_X509CaRootBundle: + case DeviceConfigurationOption_All: + if(ConfigurationManager_StoreConfigurationBlock(cmd->Data, (DeviceConfigurationOption)cmd->Configuration, cmd->BlockIndex, cmd->Length, cmd->Offset) == true) + { + cmdReply.ErrorCode = 0; + success = true; + } + else + { + cmdReply.ErrorCode = 100; + } + break; + + default: + cmdReply.ErrorCode = 10; + } + + WP_ReplyToCommand(message, success, false, &cmdReply, sizeof(cmdReply)); + + #else + + (void)message; + + #endif // (HAS_CONFIG_BLOCK == TRUE) + + return success; +} + +//--// + +bool CLR_DBG_Debugger::Debugging_Execution_BasePtr( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Execution_BasePtr::Reply cmdReply; + + cmdReply.m_EE = (CLR_UINT32)(size_t)&g_CLR_RT_ExecutionEngine; + + WP_ReplyToCommand( msg, true, false, &cmdReply, sizeof(cmdReply) ); + + return true; +} + +bool CLR_DBG_Debugger::Debugging_Execution_ChangeConditions( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Execution_ChangeConditions* cmd = (CLR_DBG_Commands::Debugging_Execution_ChangeConditions*)msg->m_payload; + + g_CLR_RT_ExecutionEngine.m_iDebugger_Conditions |= cmd->FlagsToSet; + g_CLR_RT_ExecutionEngine.m_iDebugger_Conditions &= ~cmd->FlagsToReset; + + // updating the debugging execution conditions requires sometime to propagate + // make sure we allow enough time for that to happen + OS_DELAY(100); + + if((msg->m_header.m_flags & WP_Flags_c_NonCritical) == 0) + { + CLR_DBG_Commands::Debugging_Execution_ChangeConditions::Reply cmdReply; + + cmdReply.CurrentState = g_CLR_RT_ExecutionEngine.m_iDebugger_Conditions; + + WP_ReplyToCommand( msg, true, false, &cmdReply, sizeof(cmdReply) ); + } + + return true; +} + +//--// + +static void GetClrReleaseInfo(CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::ClrInfo& clrInfo) +{ + NFReleaseInfo::Init( + clrInfo.m_clrReleaseInfo, + VERSION_MAJOR, + VERSION_MINOR, + VERSION_BUILD, + VERSION_REVISION, + OEMSYSTEMINFOSTRING, + ARRAYSIZE(OEMSYSTEMINFOSTRING), + TARGETNAMESTRING, + ARRAYSIZE(TARGETNAMESTRING), + PLATFORMNAMESTRING, + ARRAYSIZE(PLATFORMNAMESTRING) + ); + + if ( g_CLR_RT_TypeSystem.m_assemblyMscorlib && + g_CLR_RT_TypeSystem.m_assemblyMscorlib->m_header) + { + const CLR_RECORD_VERSION* mscorlibVer = & (g_CLR_RT_TypeSystem.m_assemblyMscorlib->m_header->version); + NFVersion::Init( clrInfo.m_TargetFrameworkVersion, + mscorlibVer->iMajorVersion, mscorlibVer->iMinorVersion, + mscorlibVer->iBuildNumber, mscorlibVer->iRevisionNumber + ); + } + else + { + NFVersion::Init( clrInfo.m_TargetFrameworkVersion, 0, 0, 0, 0 ); + } +} + +static bool GetInteropNativeAssemblies( uint8_t* &data, int* size) +{ + extern const CLR_RT_NativeAssemblyData *g_CLR_InteropAssembliesNativeData[]; + + int nativeAssembliesCount = 0; + CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::NativeAssemblyDetails* interopNativeAssemblies = NULL; + + // because the Interop assemblies list is assembled during the build we have to count how many are there before allocating memory for the array + for ( int i = 0; g_CLR_InteropAssembliesNativeData[i]; i++ ) + { + if (g_CLR_InteropAssembliesNativeData[i] != NULL) + { + nativeAssembliesCount++; + } + } + + interopNativeAssemblies = (CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::NativeAssemblyDetails*)platform_malloc(sizeof(CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::NativeAssemblyDetails) * nativeAssembliesCount); + + // check for malloc failure + if(interopNativeAssemblies == NULL) + { + return false; + } + + // fill the array + for ( int i = 0; i < nativeAssembliesCount; i++ ) + { + if (g_CLR_InteropAssembliesNativeData[i] != NULL) + { + interopNativeAssemblies[i].CheckSum = g_CLR_InteropAssembliesNativeData[i]->m_checkSum; + hal_strcpy_s((char*)interopNativeAssemblies[i].AssemblyName, ARRAYSIZE(interopNativeAssemblies[i].AssemblyName), g_CLR_InteropAssembliesNativeData[i]->m_szAssemblyName); + + NFVersion::Init(interopNativeAssemblies[i].Version, + g_CLR_InteropAssembliesNativeData[i]->m_Version.iMajorVersion, g_CLR_InteropAssembliesNativeData[i]->m_Version.iMinorVersion, + g_CLR_InteropAssembliesNativeData[i]->m_Version.iBuildNumber, g_CLR_InteropAssembliesNativeData[i]->m_Version.iRevisionNumber + ); + } + } + + data = (uint8_t*)interopNativeAssemblies; + + *size = (sizeof(CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::NativeAssemblyDetails) * nativeAssembliesCount); + + return true; +} + +//--// + +bool CLR_DBG_Debugger::Debugging_Execution_QueryCLRCapabilities( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities* cmd = (CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities*)msg->m_payload; + + CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::ReplyUnion reply; + reply.u_capsFlags = 0; + + CLR_UINT8* data = NULL; + int size = 0; + bool fSuccess = true; + bool freeAllocFlag = false; + + // set the compiler info string here +#if defined(__GNUC__) +#define COMPILER_INFO "GNU ARM GCC" + const size_t len = MIN(sizeof(COMPILER_INFO), sizeof(reply.u_SoftwareVersion.CompilerInfo)-1); +#else +#define COMPILER_INFO "UNKNOWN" + const size_t len = 0; +#endif + + memset(&reply, 0, sizeof(reply)); + + switch(cmd->m_cmd) + { + case CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::c_CapabilityFlags: + +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + reply.u_capsFlags |= CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::c_CapabilityFlags_FloatingPoint; +#endif + + reply.u_capsFlags |= CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::c_CapabilityFlags_ExceptionFilters; + + // the current version ONLY suports incremental deployment + reply.u_capsFlags |= CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::c_CapabilityFlags_IncrementalDeployment; + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + reply.u_capsFlags |= CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::c_CapabilityFlags_SourceLevelDebugging; + + reply.u_capsFlags |= CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::c_CapabilityFlags_ThreadCreateEx; +#endif + +#if defined(NANOCLR_PROFILE_NEW) + reply.u_capsFlags |= CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::c_CapabilityFlags_Profiling; +#if defined(NANOCLR_PROFILE_NEW_CALLS) + reply.u_capsFlags |= CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::c_CapabilityFlags_Profiling_Calls; +#endif +#if defined(NANOCLR_PROFILE_NEW_ALLOCATIONS) + reply.u_capsFlags |= CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::c_CapabilityFlags_Profiling_Allocations; +#endif +#endif + +#if defined(NANOCLR_APPDOMAINS) + reply.u_capsFlags |= CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::c_CapabilityFlags_AppDomains; +#endif + + if (CPU_IsSoftRebootSupported()) + { + reply.u_capsFlags |= CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::c_CapabilityFlags_SoftReboot; + } + + if (::Target_ConfigUpdateRequiresErase()) + { + reply.u_capsFlags |= CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::c_CapabilityFlags_ConfigBlockRequiresErase; + } + + if (::Target_HasNanoBooter()) + { + reply.u_capsFlags |= CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::c_CapabilityFlags_HasNanoBooter; + } + + reply.u_capsFlags |= (::GetPlatformCapabilities() & + ( CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::c_CapabilityFlags_PlatformCapabiliy_0 | + CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::c_CapabilityFlags_PlatformCapabiliy_1)); + + reply.u_capsFlags |= (::GetTargetCapabilities() & + ( CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::c_CapabilityFlags_TargetCapabiliy_0 | + CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::c_CapabilityFlags_TargetCapabiliy_1)); + + data = (CLR_UINT8*)&reply.u_capsFlags; + size = sizeof(reply.u_capsFlags); + break; + + case CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::c_CapabilityVersion: +#if defined(__GNUC__) + // this is returning the GNU GCC compiler version in coded format: MAJOR x 10000 + MINOR x 100 + PATCH + // example: v6.3.1 shows as 6 x 10000 + 3 x 100 + 1 = 60301 + reply.u_SoftwareVersion.CompilerVersion = (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__); +#else + reply.u_SoftwareVersion.CompilerVersion = -1; +#endif + +#if defined(__DATE__) + hal_strncpy_s( reply.u_SoftwareVersion.BuildDate, sizeof(reply.u_SoftwareVersion.BuildDate), __DATE__, hal_strlen_s(__DATE__) ); +#else +#error "__DATE__ with build timestamp needs to be defined" +#endif + + hal_strncpy_s( (char*)&reply.u_SoftwareVersion.CompilerInfo[ 0 ], sizeof(reply.u_SoftwareVersion.CompilerInfo), COMPILER_INFO, len ); + + data = (CLR_UINT8*)&reply.u_SoftwareVersion; + size = sizeof(reply.u_SoftwareVersion); + break; + + case CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::c_HalSystemInfo: + if(GetHalSystemInfo( reply.u_HalSystemInfo ) == true) + { + data = (CLR_UINT8*)&reply.u_HalSystemInfo; + size = sizeof(reply.u_HalSystemInfo); + } + else + { + fSuccess = false; + } + break; + + case CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::c_ClrInfo: + GetClrReleaseInfo(reply.u_ClrInfo); + data = (CLR_UINT8*)&reply.u_ClrInfo; + size = sizeof(reply.u_ClrInfo); + break; + + case CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::c_TargetReleaseInfo: + if(Target_GetReleaseInfo(reply.u_TargetReleaseInfo) == true) + { + data = (CLR_UINT8*)&reply.u_TargetReleaseInfo; + size = sizeof(reply.u_TargetReleaseInfo); + } + else + { + fSuccess = false; + } + break; + + case CLR_DBG_Commands::Debugging_Execution_QueryCLRCapabilities::c_InteropNativeAssemblies: + if(GetInteropNativeAssemblies(data, &size) == true) + { + // signal need to free memory + freeAllocFlag = true; + } + else + { + fSuccess = false; + } + break; + + default: + fSuccess = false; + break; + } + + WP_ReplyToCommand( msg, fSuccess, false, data, size ); + + // check if we need to free data pointer + if(freeAllocFlag) + { + platform_free(data); + } + + return true; +} + + +bool CLR_DBG_Debugger::Debugging_Execution_Allocate( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Execution_Allocate* cmd = (CLR_DBG_Commands::Debugging_Execution_Allocate*)msg->m_payload; + CLR_DBG_Commands::Debugging_Execution_Allocate::Reply reply; + + reply.m_address = (CLR_UINT32)(size_t)CLR_RT_Memory::Allocate( cmd->m_size, CLR_RT_HeapBlock::HB_CompactOnFailure ); + + if(!reply.m_address) return false; + + WP_ReplyToCommand( msg, true, false, &reply, sizeof(reply) ); + + return true; +} + +bool CLR_DBG_Debugger::Debugging_UpgradeToSsl(WP_Message* msg) +{ + + CLR_DBG_Commands::Debugging_UpgradeToSsl* cmd = (CLR_DBG_Commands::Debugging_UpgradeToSsl*)msg->m_payload; + CLR_DBG_Commands::Debugging_UpgradeToSsl::Reply reply; + + if(!DebuggerPort_IsSslSupported(HalSystemConfig.DebuggerPort)) + { + return false; + } + + reply.m_success = 1; + + WP_ReplyToCommand( msg, true, true, &reply, sizeof(reply) ); + + Events_WaitForEvents(0, 300); + + return true == DebuggerPort_UpgradeToSsl(HalSystemConfig.DebuggerPort, cmd->m_flags); +} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + +static bool FillValues( CLR_RT_HeapBlock* ptr, CLR_DBG_Commands::Debugging_Value*& array, size_t num, CLR_RT_HeapBlock* reference, CLR_RT_TypeDef_Instance* pTD ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + if(!ptr) return true; + + if(!array || num == 0) return false; + + CLR_DBG_Commands::Debugging_Value* dst = array++; num--; + CLR_RT_TypeDescriptor desc; + + memset( dst, 0, sizeof(*dst) ); + + dst->m_referenceID = (reference != NULL) ? reference : ptr; + dst->m_dt = ptr->DataType (); + dst->m_flags = ptr->DataFlags(); + dst->m_size = ptr->DataSize (); + + if(pTD != NULL) + { + dst->m_td = *pTD; + } + else if(SUCCEEDED(desc.InitializeFromObject( *ptr ))) + { + dst->m_td = desc.m_handlerCls; + } + + switch(dst->m_dt) + { + case DATATYPE_BOOLEAN : + case DATATYPE_I1 : + case DATATYPE_U1 : + + case DATATYPE_CHAR : + case DATATYPE_I2 : + case DATATYPE_U2 : + + case DATATYPE_I4 : + case DATATYPE_U4 : + case DATATYPE_R4 : + + case DATATYPE_I8 : + case DATATYPE_U8 : + case DATATYPE_R8 : + case DATATYPE_DATETIME : + case DATATYPE_TIMESPAN : + case DATATYPE_REFLECTION: + // + // Primitives or optimized value types. + // + memcpy( dst->m_builtinValue, (void*)&ptr->NumericByRefConst().u1, 8 ); + break; + + case DATATYPE_STRING: + { + const char* text = ptr->StringText(); + + if(text != NULL) + { + dst->m_charsInString = text; + dst->m_bytesInString = (CLR_UINT32)hal_strlen_s( text ); + + hal_strncpy_s( (char*)dst->m_builtinValue, ARRAYSIZE(dst->m_builtinValue), text, __min(dst->m_bytesInString, MAXSTRLEN(dst->m_builtinValue)) ); + } + else + { + dst->m_charsInString = NULL; + dst->m_bytesInString = 0; + dst->m_builtinValue[0] = 0; + } + } + break; + + + case DATATYPE_OBJECT: + case DATATYPE_BYREF : + return FillValues( ptr->Dereference(), array, num, NULL, pTD ); + + + case DATATYPE_CLASS : + case DATATYPE_VALUETYPE: + dst->m_td = ptr->ObjectCls(); + break; + + case DATATYPE_SZARRAY: + { + CLR_RT_HeapBlock_Array* ptr2 = (CLR_RT_HeapBlock_Array*)ptr; + + dst->m_array_numOfElements = ptr2->m_numOfElements; + dst->m_array_depth = ptr2->ReflectionDataConst().m_levels; + dst->m_array_typeIndex = ptr2->ReflectionDataConst().m_data.m_type; + } + break; + + //////////////////////////////////////// + + case DATATYPE_WEAKCLASS : + break; + + case DATATYPE_ARRAY_BYREF : + dst->m_arrayref_referenceID = ptr->Array (); + dst->m_arrayref_index = ptr->ArrayIndex(); + + break; + + case DATATYPE_DELEGATE_HEAD : + break; + + case DATATYPE_DELEGATELIST_HEAD : + break; + + case DATATYPE_FREEBLOCK : + case DATATYPE_CACHEDBLOCK : + case DATATYPE_ASSEMBLY : + case DATATYPE_OBJECT_TO_EVENT : + case DATATYPE_BINARY_BLOB_HEAD : + + case DATATYPE_THREAD : + case DATATYPE_SUBTHREAD : + case DATATYPE_STACK_FRAME : + case DATATYPE_TIMER_HEAD : + case DATATYPE_LOCK_HEAD : + case DATATYPE_LOCK_OWNER_HEAD : + case DATATYPE_LOCK_REQUEST_HEAD : + case DATATYPE_WAIT_FOR_OBJECT_HEAD : + case DATATYPE_FINALIZER_HEAD : + case DATATYPE_MEMORY_STREAM_HEAD : + case DATATYPE_MEMORY_STREAM_DATA : + + case DATATYPE_SERIALIZER_HEAD : + case DATATYPE_SERIALIZER_DUPLICATE : + case DATATYPE_SERIALIZER_STATE : + + case DATATYPE_ENDPOINT_HEAD : + +#if defined(NANOCLR_APPDOMAINS) + case DATATYPE_APPDOMAIN_HEAD : + case DATATYPE_TRANSPARENT_PROXY : + case DATATYPE_APPDOMAIN_ASSEMBLY : +#endif + + break; + } + + return true; +} + +bool CLR_DBG_Debugger::GetValue( WP_Message* msg, CLR_RT_HeapBlock* ptr, CLR_RT_HeapBlock* reference, CLR_RT_TypeDef_Instance *pTD ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + CLR_DBG_Commands::Debugging_Value reply[ 4 ]; + CLR_DBG_Commands::Debugging_Value* array = reply; + + if(FillValues( ptr, array, ARRAYSIZE(reply), reference, pTD )) + { + WP_ReplyToCommand( msg, true, false, reply, (int)((size_t)array - (size_t)reply) ); + + return true; + } + + WP_ReplyToCommand(msg, false, false, NULL, 0); + + return false; +} + +//--// + +bool CLR_DBG_Debugger::Debugging_Execution_SetCurrentAppDomain( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); +#if defined(NANOCLR_APPDOMAINS) + + CLR_DBG_Commands::Debugging_Execution_SetCurrentAppDomain* cmd = (CLR_DBG_Commands::Debugging_Execution_SetCurrentAppDomain*)msg->m_payload; + CLR_RT_AppDomain* appDomain = g_CLR_DBG_Debugger->GetAppDomainFromID( cmd->m_id ); + + if(appDomain) + { + g_CLR_RT_ExecutionEngine.SetCurrentAppDomain( appDomain ); + } + + WP_ReplyToCommand(msg, appDomain != NULL, false, NULL, 0); + + return true; +#else + (void)msg; + return false; +#endif +} + +bool CLR_DBG_Debugger::Debugging_Execution_Breakpoints( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Execution_Breakpoints* cmd = (CLR_DBG_Commands::Debugging_Execution_Breakpoints*)msg->m_payload; + + g_CLR_RT_ExecutionEngine.InstallBreakpoints( cmd->m_data, (msg->m_header.m_size - sizeof(cmd->m_flags)) / sizeof(CLR_DBG_Commands::Debugging_Execution_BreakpointDef) ); + + WP_ReplyToCommand(msg, true, false, NULL, 0); + + return true; +} + +bool CLR_DBG_Debugger::Debugging_Execution_BreakpointStatus( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Execution_BreakpointStatus::Reply reply; + + if(g_CLR_RT_ExecutionEngine.DequeueActiveBreakpoint( reply.m_lastHit ) == false) + { + memset( &reply.m_lastHit, 0, sizeof(reply.m_lastHit) ); + } + + WP_ReplyToCommand( msg, true, false, &reply, sizeof(reply) ); + + return true; +} + +//--// + +CLR_RT_Assembly* CLR_DBG_Debugger::IsGoodAssembly( CLR_IDX idxAssm ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + NANOCLR_FOREACH_ASSEMBLY(g_CLR_RT_TypeSystem) + { + if(pASSM->m_idx == idxAssm) return pASSM; + } + NANOCLR_FOREACH_ASSEMBLY_END(); + + return NULL; +} + +bool CLR_DBG_Debugger::CheckTypeDef( const CLR_RT_TypeDef_Index& td, CLR_RT_TypeDef_Instance& inst ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + CLR_RT_Assembly* assm = IsGoodAssembly( td.Assembly() ); + + if(assm && td.Type() < assm->m_pTablesSize[ TBL_TypeDef ]) + { + return inst.InitializeFromIndex( td ); + } + + return false; +} + +bool CLR_DBG_Debugger::CheckFieldDef( const CLR_RT_FieldDef_Index& fd, CLR_RT_FieldDef_Instance& inst ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + CLR_RT_Assembly* assm = IsGoodAssembly( fd.Assembly() ); + + if(assm && fd.Field() < assm->m_pTablesSize[ TBL_FieldDef ]) + { + return inst.InitializeFromIndex( fd ); + } + + return false; +} + +bool CLR_DBG_Debugger::CheckMethodDef( const CLR_RT_MethodDef_Index& md, CLR_RT_MethodDef_Instance& inst ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + CLR_RT_Assembly* assm = IsGoodAssembly( md.Assembly() ); + + if(assm && md.Method() < assm->m_pTablesSize[ TBL_MethodDef ]) + { + return inst.InitializeFromIndex( md ); + } + + return false; +} + +CLR_RT_StackFrame* CLR_DBG_Debugger::CheckStackFrame( CLR_INT32 pid, CLR_UINT32 depth, bool& isInline ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + CLR_RT_Thread* th = GetThreadFromPid( pid ); + + isInline = false; + + if(th) + { + NANOCLR_FOREACH_NODE(CLR_RT_StackFrame,call,th->m_stackFrames) + { +#ifndef CLR_NO_IL_INLINE + if(call->m_inlineFrame) + { + if(depth-- == 0) + { + isInline = true; + return call; + } + } +#endif + + if(depth-- == 0) return call; + } + NANOCLR_FOREACH_NODE_END(); + } + + return NULL; +} + +//--// + +static HRESULT Debugging_Thread_Create_Helper( CLR_RT_MethodDef_Index& md, CLR_RT_Thread*& th, CLR_INT32 pid ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock ref; ref.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc( ref ); + CLR_RT_Thread* realThread = (pid != 0) ? CLR_DBG_Debugger::GetThreadFromPid( pid ) : NULL; + + th = NULL; + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Delegate::CreateInstance( ref, md, NULL )); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewThread( th, ref.DereferenceDelegate(), ThreadPriority::Highest, -1 )); + + + if (realThread) + { + th->m_realThread = realThread; + } + + { + CLR_RT_StackFrame* stack = th->CurrentFrame(); + const CLR_RECORD_METHODDEF* target = stack->m_call.m_target; + CLR_UINT8 numArgs = target->numArgs; + + if(numArgs) + { + CLR_RT_SignatureParser parser; parser.Initialize_MethodSignature( stack->m_call.m_assm, target ); + CLR_RT_SignatureParser::Element res; + CLR_RT_HeapBlock* args = stack->m_arguments; + + if(parser.m_flags & PIMAGE_CEE_CS_CALLCONV_HASTHIS) + { + args->SetObjectReference( NULL ); + + numArgs--; + args++; + } + + // + // Skip return value. + // + NANOCLR_CHECK_HRESULT(parser.Advance( res )); + + // + // None of the arguments can be ByRef. + // + { + CLR_RT_SignatureParser parser2 = parser; + + for(;parser2.Available() > 0;) + { + NANOCLR_CHECK_HRESULT(parser2.Advance( res )); + + if(res.m_fByRef) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + } + } + + for(CLR_UINT8 i=0; iTerminate(); + th = NULL; + } + } + + NANOCLR_CLEANUP_END(); +} + +bool CLR_DBG_Debugger::Debugging_Thread_CreateEx( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Thread_CreateEx* cmd = (CLR_DBG_Commands::Debugging_Thread_CreateEx*)msg->m_payload; + CLR_DBG_Commands::Debugging_Thread_CreateEx::Reply cmdReply; + CLR_RT_Thread* th; + + if(SUCCEEDED(Debugging_Thread_Create_Helper( cmd->m_md, th, cmd->m_pid ))) + { + th->m_scratchPad = cmd->m_scratchPad; + + cmdReply.m_pid = th->m_pid; + } + else + { + cmdReply.m_pid = -1; + } + + WP_ReplyToCommand( msg, true, false, &cmdReply, sizeof(cmdReply) ); + + return true; +} + +bool CLR_DBG_Debugger::Debugging_Thread_List( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Thread_List::Reply* cmdReply = NULL; + int len = 0; + + if(FAILED(g_CLR_DBG_Debugger->CreateListOfThreads( cmdReply, len ))) + { + WP_ReplyToCommand( msg, false, false, NULL, 0); + } + else + { + WP_ReplyToCommand( msg, true, false, cmdReply, len ); + } + + CLR_RT_Memory::Release( cmdReply ); + + return true; +} + +bool CLR_DBG_Debugger::Debugging_Thread_Stack( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Thread_Stack* cmd = (CLR_DBG_Commands::Debugging_Thread_Stack*)msg->m_payload; + CLR_DBG_Commands::Debugging_Thread_Stack::Reply* cmdReply = NULL; + int len = 0; + + if(FAILED(g_CLR_DBG_Debugger->CreateListOfCalls( cmd->m_pid, cmdReply, len ))) + { + WP_ReplyToCommand(msg, false, false, NULL, 0); + } + else + { + WP_ReplyToCommand( msg, true, false, cmdReply, len ); + } + + CLR_RT_Memory::Release( cmdReply ); + + return true; +} + +bool CLR_DBG_Debugger::Debugging_Thread_Kill( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Thread_Kill* cmd = (CLR_DBG_Commands::Debugging_Thread_Kill*)msg->m_payload; + CLR_DBG_Commands::Debugging_Thread_Kill::Reply cmdReply; + CLR_RT_Thread* th = g_CLR_DBG_Debugger->GetThreadFromPid( cmd->m_pid ); + + if(th) + { + th->Terminate(); + + cmdReply.m_result = 1; + } + else + { + cmdReply.m_result = 0; + } + + WP_ReplyToCommand( msg, true, false, &cmdReply, sizeof(cmdReply) ); + + return true; +} + +bool CLR_DBG_Debugger::Debugging_Thread_Suspend( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Thread_Suspend* cmd = (CLR_DBG_Commands::Debugging_Thread_Suspend*)msg->m_payload; + CLR_RT_Thread* th = g_CLR_DBG_Debugger->GetThreadFromPid( cmd->m_pid ); + + if(th) + { + th->Suspend(); + } + + WP_ReplyToCommand(msg, th != NULL, false, NULL, 0); + + return true; +} + +bool CLR_DBG_Debugger::Debugging_Thread_Resume( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Thread_Resume* cmd = (CLR_DBG_Commands::Debugging_Thread_Resume*)msg->m_payload; + CLR_RT_Thread* th = g_CLR_DBG_Debugger->GetThreadFromPid( cmd->m_pid ); + + if(th) + { + th->Resume(); + } + + WP_ReplyToCommand(msg, th != NULL, false, NULL, 0); + + return true; +} + +bool CLR_DBG_Debugger::Debugging_Thread_Get( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + CLR_DBG_Debugger* dbg = (CLR_DBG_Debugger*)&g_scratchDebugger[0]; + CLR_DBG_Commands::Debugging_Thread_Get* cmd = (CLR_DBG_Commands::Debugging_Thread_Get*)msg->m_payload; + CLR_RT_Thread* th = dbg->GetThreadFromPid( cmd->m_pid ); + CLR_RT_HeapBlock* pThread; + bool fFound = false; + + if(th == NULL) return false; + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + //If we are a thread spawned by the debugger to perform evaluations, + //return the thread object that correspond to thread that has focus in debugger. + th = th->m_realThread; +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + //Find an existing managed thread, if it exists + //making sure to only return the managed object association with the current appdomain + //to prevent leaking of managed Thread objects across AD boundaries. + + NANOCLR_FOREACH_NODE(CLR_RT_ObjectToEvent_Source,src,th->m_references) + { + CLR_RT_HeapBlock* pManagedThread = src->m_objectPtr; + _ASSERTE(pManagedThread != NULL); + +#if defined(NANOCLR_APPDOMAINS) + { + CLR_RT_ObjectToEvent_Source* appDomainSrc = CLR_RT_ObjectToEvent_Source::ExtractInstance( pManagedThread[ Library_corlib_native_System_Threading_Thread::FIELD___appDomain ] ); + + if(appDomainSrc == NULL) break; + + fFound = (appDomainSrc->m_eventPtr == g_CLR_RT_ExecutionEngine.GetCurrentAppDomain()); + } +#else + fFound = true; +#endif + + if(fFound) + { + pThread = pManagedThread; + + break; + } + } + NANOCLR_FOREACH_NODE_END(); + + if(!fFound) + { + pThread = (CLR_RT_HeapBlock*)platform_malloc(sizeof(CLR_RT_HeapBlock)); + + //Create the managed thread. + //This implies that there is no state in the managed object. This is not exactly true, as the managed thread + //contains the priority as well as the delegate to start. However, that state is really just used as a placeholder for + //the data before the thread is started. Once the thread is started, they are copied over to the unmanaged thread object + //and no longer used. The managed object is then used simply as a wrapper for the unmanaged thread. Therefore, it is safe + //to simply make another managed thread here. + if(SUCCEEDED(g_CLR_RT_ExecutionEngine.NewObjectFromIndex( *pThread, g_CLR_RT_WellKnownTypes.m_Thread ))) + { + CLR_RT_HeapBlock* pRes = pThread->Dereference(); + + int pri = th->GetThreadPriority(); + + pRes[Library_corlib_native_System_Threading_Thread::FIELD___priority].NumericByRef().s4 = pri; + + if(SUCCEEDED(CLR_RT_ObjectToEvent_Source::CreateInstance( th, *pRes, pRes[ Library_corlib_native_System_Threading_Thread::FIELD___thread ] ))) + { +#if defined(NANOCLR_APPDOMAINS) + CLR_RT_ObjectToEvent_Source::CreateInstance( g_CLR_RT_ExecutionEngine.GetCurrentAppDomain(), *pRes, pRes[ Library_corlib_native_System_Threading_Thread::FIELD___appDomain ] ); +#endif + fFound = true; + } + + } + } + + if(!fFound) return false; + + return g_CLR_DBG_Debugger->GetValue( msg, pThread, NULL, NULL ); +} + +bool CLR_DBG_Debugger::Debugging_Thread_GetException( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Thread_GetException* cmd = (CLR_DBG_Commands::Debugging_Thread_GetException*)msg->m_payload; + CLR_RT_Thread* th = g_CLR_DBG_Debugger->GetThreadFromPid( cmd->m_pid ); + CLR_RT_HeapBlock* blk = NULL; + + if(th) + { + blk = &th->m_currentException; + } + + return g_CLR_DBG_Debugger->GetValue( msg, blk, NULL, NULL ); +} + +bool CLR_DBG_Debugger::Debugging_Thread_Unwind( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Thread_Unwind* cmd = (CLR_DBG_Commands::Debugging_Thread_Unwind*)msg->m_payload; + CLR_RT_StackFrame* call; + CLR_RT_Thread* th; + bool isInline = false; + + if((call = g_CLR_DBG_Debugger->CheckStackFrame( cmd->m_pid, cmd->m_depth, isInline )) != NULL) + { + _ASSERTE((call->m_flags & CLR_RT_StackFrame::c_MethodKind_Native) == 0); + + th = call->m_owningThread; + _ASSERTE(th->m_nestedExceptionsPos); + + CLR_RT_Thread::UnwindStack& us = th->m_nestedExceptions[ th->m_nestedExceptionsPos - 1 ]; + _ASSERTE(th->m_currentException.Dereference() == us.m_exception); + _ASSERTE(us.m_flags & CLR_RT_Thread::UnwindStack::c_ContinueExceptionHandler); + + us.m_handlerStack = call; + us.m_flags |= CLR_RT_Thread::UnwindStack::c_MagicCatchForInteceptedException; + + us.SetPhase(CLR_RT_Thread::UnwindStack::p_2_RunningFinallys_0); + } + + return true; +} + +//--// + +bool CLR_DBG_Debugger::Debugging_Stack_Info( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Stack_Info* cmd = (CLR_DBG_Commands::Debugging_Stack_Info*)msg->m_payload; + CLR_DBG_Commands::Debugging_Stack_Info::Reply cmdReply; + CLR_RT_StackFrame* call; + bool isInline = false; + + if((call = g_CLR_DBG_Debugger->CheckStackFrame( cmd->m_pid, cmd->m_depth, isInline )) != NULL) + { +#ifndef CLR_NO_IL_INLINE + if(isInline) + { + cmdReply.m_md = call->m_inlineFrame->m_frame.m_call; + cmdReply.m_IP = (CLR_UINT32)(call->m_inlineFrame->m_frame.m_IP - call->m_inlineFrame->m_frame.m_IPStart); + cmdReply.m_numOfArguments = call->m_inlineFrame->m_frame.m_call.m_target->numArgs; + cmdReply.m_numOfLocals = call->m_inlineFrame->m_frame.m_call.m_target->numLocals; + cmdReply.m_depthOfEvalStack = (CLR_UINT32)(call->m_evalStack - call->m_inlineFrame->m_frame.m_evalStack); + } + else +#endif + { + cmdReply.m_md = call->m_call; + cmdReply.m_IP = (CLR_UINT32)(call->m_IP - call->m_IPstart); + cmdReply.m_numOfArguments = call->m_call.m_target->numArgs; + cmdReply.m_numOfLocals = call->m_call.m_target->numLocals; + cmdReply.m_depthOfEvalStack = (CLR_UINT32) call->TopValuePosition(); + } + + WP_ReplyToCommand( msg, true, false, &cmdReply, sizeof(cmdReply) ); + + return true; + } + + WP_ReplyToCommand(msg, false, false, NULL, 0); + + return true; +} + +bool CLR_DBG_Debugger::Debugging_Stack_SetIP( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Stack_SetIP* cmd = (CLR_DBG_Commands::Debugging_Stack_SetIP*)msg->m_payload; + CLR_RT_StackFrame* call; + bool isInline = false; + + if((call = g_CLR_DBG_Debugger->CheckStackFrame( cmd->m_pid, cmd->m_depth, isInline )) != NULL) + { +#ifndef CLR_NO_IL_INLINE + if(isInline) + { + WP_ReplyToCommand(msg, false, false, NULL, 0); + + return true; + } + else +#endif + { + call->m_IP = call->m_IPstart + cmd->m_IP; + call->m_evalStackPos = call->m_evalStack + cmd->m_depthOfEvalStack; + } + + call->m_flags &= ~CLR_RT_StackFrame::c_InvalidIP; + + WP_ReplyToCommand(msg, true, false, NULL, 0); + + return true; + } + + WP_ReplyToCommand(msg, false, false, NULL, 0); + + return true; +} + +//--// + +static bool IsBlockEnumMaybe( CLR_RT_HeapBlock* blk ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + const CLR_UINT32 c_MaskForPrimitive = CLR_RT_DataTypeLookup::c_Integer | CLR_RT_DataTypeLookup::c_Numeric; + + CLR_RT_TypeDescriptor desc; + + if(FAILED(desc.InitializeFromObject( *blk ))) return false; + + const CLR_RT_DataTypeLookup& dtl = c_CLR_RT_DataTypeLookup[ desc.m_handlerCls.m_target->dataType ]; + + return (dtl.m_flags & c_MaskForPrimitive) == c_MaskForPrimitive; +} + +static bool SetBlockHelper( CLR_RT_HeapBlock* blk, CLR_DataType dt, CLR_UINT8* builtinValue ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + bool fCanAssign = false; + + if(blk) + { + CLR_DataType dtDst; + CLR_RT_HeapBlock src; + + dtDst = blk->DataType(); + + src.SetDataId( CLR_RT_HEAPBLOCK_RAW_ID(dt, 0, 1) ); + memcpy( (void*)&src.NumericByRef().u1, builtinValue, sizeof(CLR_UINT64) ); + + if(dtDst == dt) + { + fCanAssign = true; + } + else + { + if(dt == DATATYPE_REFLECTION) + { + fCanAssign = (dtDst == DATATYPE_OBJECT && blk->Dereference() == NULL); + } + else if(dt == DATATYPE_OBJECT) + { + fCanAssign = (src .Dereference() == NULL && dtDst == DATATYPE_REFLECTION); + } + else + { + _ASSERTE(c_CLR_RT_DataTypeLookup[ dtDst ].m_flags & CLR_RT_DataTypeLookup::c_Numeric); + + if(c_CLR_RT_DataTypeLookup[ dtDst ].m_sizeInBytes == sizeof(CLR_INT32) && + c_CLR_RT_DataTypeLookup[ dt ].m_sizeInBytes < sizeof(CLR_INT32)) + { + dt = dtDst; + fCanAssign = true; + } + } + } + + if(fCanAssign) + { + blk->ChangeDataType( dt ); + memcpy( (void*)&blk->NumericByRef().u1, builtinValue, sizeof(CLR_UINT64) ); + } + } + + return fCanAssign; +} + +static CLR_RT_HeapBlock* GetScratchPad_Helper( int idx ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + CLR_RT_HeapBlock_Array* array = g_CLR_RT_ExecutionEngine.m_scratchPadArray; + CLR_RT_HeapBlock tmp; + CLR_RT_HeapBlock ref; + + tmp.SetObjectReference( array ); + + if(SUCCEEDED(ref.InitializeArrayReference( tmp, idx ))) + { + return (CLR_RT_HeapBlock*)array->GetElement( idx ); + } + + return NULL; +} + +//--// + +bool CLR_DBG_Debugger::Debugging_Value_ResizeScratchPad( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Value_ResizeScratchPad* cmd = (CLR_DBG_Commands::Debugging_Value_ResizeScratchPad*)msg->m_payload; + CLR_RT_HeapBlock ref; + bool fRes = true; + + if(cmd->m_size == 0) + { + g_CLR_RT_ExecutionEngine.m_scratchPadArray = NULL; + } + else + { + if(SUCCEEDED(CLR_RT_HeapBlock_Array::CreateInstance( ref, cmd->m_size, g_CLR_RT_WellKnownTypes.m_Object ))) + { + CLR_RT_HeapBlock_Array* pOld = g_CLR_RT_ExecutionEngine.m_scratchPadArray; + CLR_RT_HeapBlock_Array* pNew = ref.DereferenceArray(); + + if(pOld) + { + memcpy( pNew->GetFirstElement(), pOld->GetFirstElement(), sizeof(CLR_RT_HeapBlock) * __min( pNew->m_numOfElements, pOld->m_numOfElements ) ); + } + + g_CLR_RT_ExecutionEngine.m_scratchPadArray = pNew; + } + else + { + fRes = false; + } + } + + WP_ReplyToCommand(msg, fRes, false, NULL, 0); + + return false; +} + +bool CLR_DBG_Debugger::Debugging_Value_GetStack( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Value_GetStack* cmd = (CLR_DBG_Commands::Debugging_Value_GetStack*)msg->m_payload; + CLR_RT_StackFrame* call; + bool isInline = false; + + if((call = g_CLR_DBG_Debugger->CheckStackFrame( cmd->m_pid, cmd->m_depth, isInline )) != NULL) + { + CLR_RT_HeapBlock* array; + CLR_UINT32 num; +#ifndef CLR_NO_IL_INLINE + CLR_RT_MethodDef_Instance& md = isInline ? call->m_inlineFrame->m_frame.m_call : call->m_call; +#else + CLR_RT_MethodDef_Instance& md = call->m_call; +#endif + + switch(cmd->m_kind) + { + case CLR_DBG_Commands::Debugging_Value_GetStack::c_Argument: +#ifndef CLR_NO_IL_INLINE + array = isInline ? call->m_inlineFrame->m_frame.m_args : call->m_arguments; + num = isInline ? md.m_target->numArgs : md.m_target->numArgs; +#else + array = call->m_arguments; + num = call->m_call.m_target->numArgs; +#endif + break; + + case CLR_DBG_Commands::Debugging_Value_GetStack::c_Local: +#ifndef CLR_NO_IL_INLINE + array = isInline ? call->m_inlineFrame->m_frame.m_locals : call->m_locals; + num = isInline ? md.m_target->numLocals : md.m_target->numLocals; +#else + array = call->m_locals; + num = call->m_call.m_target->numLocals; +#endif + break; + + case CLR_DBG_Commands::Debugging_Value_GetStack::c_EvalStack: +#ifndef CLR_NO_IL_INLINE + array = isInline ? call->m_inlineFrame->m_frame.m_evalStack : call->m_evalStack; + num = isInline ? (CLR_UINT32)(call->m_evalStack - call->m_inlineFrame->m_frame.m_evalStack) : (CLR_UINT32)call->TopValuePosition(); +#else + array = call->m_evalStack; + num = (CLR_UINT32)call->TopValuePosition(); +#endif + break; + + default: + return false; + } + + if(cmd->m_index >= num) return false; + + CLR_RT_HeapBlock* blk = &array[ cmd->m_index ]; + CLR_RT_HeapBlock* reference = NULL; + CLR_RT_HeapBlock tmp; + CLR_RT_TypeDef_Instance* pTD = NULL; + CLR_RT_TypeDef_Instance td; + + if(cmd->m_kind != CLR_DBG_Commands::Debugging_Value_GetStack::c_EvalStack && IsBlockEnumMaybe( blk )) + { + CLR_UINT32 iElement = cmd->m_index; + CLR_RT_SignatureParser parser; + CLR_RT_SignatureParser::Element res; + CLR_RT_TypeDescriptor desc; + + if(cmd->m_kind == CLR_DBG_Commands::Debugging_Value_GetStack::c_Argument) + { + parser.Initialize_MethodSignature( md.m_assm, md.m_target ); + + iElement++; // Skip the return value, always at the head of the signature. + + if(parser.m_flags & PIMAGE_CEE_CS_CALLCONV_HASTHIS) + { + if(iElement == 0) return false; // The requested argument is the "this" argument, it can never be a primitive. + + iElement--; + } + } + else + { + parser.Initialize_MethodLocals( md.m_assm, md.m_target ); + } + + do + { + parser.Advance( res ); + } + while(iElement--); + + // + // Arguments to a methods come from the eval stack and we don't fix up the eval stack for each call. + // So some arguments have the wrong datatype, since an eval stack push always promotes to 32 bits. + // + if(c_CLR_RT_DataTypeLookup[ blk->DataType() ].m_sizeInBytes == sizeof(CLR_INT32) && + c_CLR_RT_DataTypeLookup[ res.m_dt ].m_sizeInBytes < sizeof(CLR_INT32) ) + { + tmp.Assign ( *blk ); + tmp.ChangeDataType( res.m_dt ); + + reference = blk; blk = &tmp; + } + + // + // Check for enum. + // + desc.InitializeFromType( res.m_cls ); + + if(desc.m_handlerCls.m_target->IsEnum()) + { + td = desc.m_handlerCls; pTD = &td; + } + } + + return g_CLR_DBG_Debugger->GetValue( msg, blk, reference, pTD ); + } + + return false; +} + +bool CLR_DBG_Debugger::Debugging_Value_GetField( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Value_GetField* cmd = (CLR_DBG_Commands::Debugging_Value_GetField*)msg->m_payload; + CLR_RT_HeapBlock* blk = cmd->m_heapblock; + CLR_RT_HeapBlock* reference = NULL; + CLR_RT_HeapBlock tmp; + CLR_RT_TypeDescriptor desc; + CLR_RT_TypeDef_Instance td; + CLR_RT_TypeDef_Instance* pTD = NULL; + CLR_RT_FieldDef_Instance inst; + CLR_UINT32 offset; + + if(blk != NULL && cmd->m_offset > 0) + { + if(FAILED(desc.InitializeFromObject( *blk ))) return false; + + td = desc.m_handlerCls; + offset = cmd->m_offset - 1; + + while(true) + { + CLR_UINT32 iFields = td.m_target->iFields_Num; + CLR_UINT32 totalFields = td.CrossReference().m_totalFields; + CLR_UINT32 dFields = totalFields - iFields; + + if(offset >= dFields) + { + offset -= dFields; + break; + } + + if(!td.SwitchToParent()) return false; + } + + cmd->m_fd.Set( td.Assembly(), td.m_target->iFields_First + offset ); + } + + if(!g_CLR_DBG_Debugger->CheckFieldDef( cmd->m_fd, inst )) return false; + + if(blk == NULL) + { + blk = CLR_RT_ExecutionEngine::AccessStaticField( cmd->m_fd ); + } + else + { + if(cmd->m_offset == 0) + { + cmd->m_offset = inst.CrossReference().m_offset; + } + + if(cmd->m_offset == 0) return false; + + switch(blk->DataType()) + { + case DATATYPE_CLASS : + case DATATYPE_VALUETYPE: + break; + + default: + if(FAILED(blk->EnsureObjectReference( blk ))) return false; + break; + } + + switch(blk->DataType()) + { + case DATATYPE_DATETIME: // Special case. + case DATATYPE_TIMESPAN: // Special case. + tmp.SetInteger( (CLR_INT64)blk->NumericByRefConst().s8 ); + reference = blk; blk = &tmp; + break; + + default: + blk = &blk[ cmd->m_offset ]; + break; + } + } + + if(IsBlockEnumMaybe( blk )) + { + if(SUCCEEDED(desc.InitializeFromFieldDefinition( inst ))) + { + if(desc.m_handlerCls.m_target->IsEnum()) + { + pTD = &desc.m_handlerCls; + } + } + } + + return g_CLR_DBG_Debugger->GetValue( msg, blk, reference, pTD ); +} + +bool CLR_DBG_Debugger::Debugging_Value_GetArray( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Value_GetArray* cmd = (CLR_DBG_Commands::Debugging_Value_GetArray*)msg->m_payload; + CLR_RT_HeapBlock* blk = NULL; + CLR_RT_HeapBlock* reference = NULL; + CLR_RT_HeapBlock tmp; + CLR_RT_HeapBlock ref; + CLR_RT_TypeDef_Instance* pTD = NULL; + CLR_RT_TypeDef_Instance td; + + tmp.SetObjectReference( cmd->m_heapblock ); + + if(SUCCEEDED(ref.InitializeArrayReference( tmp, cmd->m_index ))) + { + CLR_RT_HeapBlock_Array* array = ref.Array(); + + if(array->m_fReference) + { + blk = (CLR_RT_HeapBlock*)array->GetElement( cmd->m_index ); + } + else + { + if(FAILED(tmp.LoadFromReference( ref ))) return false; + + blk = &tmp; reference = (CLR_RT_HeapBlock*)-1; + } + + if(IsBlockEnumMaybe( blk )) + { + if(td.InitializeFromIndex( array->ReflectionDataConst().m_data.m_type )) + { + if(td.m_target->IsEnum()) + { + pTD = &td; + } + } + } + } + + return g_CLR_DBG_Debugger->GetValue( msg, blk, reference, pTD ); +} + +bool CLR_DBG_Debugger::Debugging_Value_GetBlock( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Value_GetBlock* cmd = (CLR_DBG_Commands::Debugging_Value_GetBlock*)msg->m_payload; + CLR_RT_HeapBlock* blk = cmd->m_heapblock; + + return g_CLR_DBG_Debugger->GetValue( msg, blk, NULL, NULL ); +} + +bool CLR_DBG_Debugger::Debugging_Value_GetScratchPad( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Value_GetScratchPad* cmd = (CLR_DBG_Commands::Debugging_Value_GetScratchPad*)msg->m_payload; + CLR_RT_HeapBlock* blk = GetScratchPad_Helper( cmd->m_idx ); + + return g_CLR_DBG_Debugger->GetValue( msg, blk, NULL, NULL ); +} + +bool CLR_DBG_Debugger::Debugging_Value_SetBlock( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Value_SetBlock* cmd = (CLR_DBG_Commands::Debugging_Value_SetBlock*)msg->m_payload; + CLR_RT_HeapBlock* blk = cmd->m_heapblock; + + WP_ReplyToCommand(msg, SetBlockHelper( blk, (CLR_DataType)cmd->m_dt, cmd->m_builtinValue ), false, NULL, 0); + + return true; +} + +bool CLR_DBG_Debugger::Debugging_Value_SetArray( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Value_SetArray* cmd = (CLR_DBG_Commands::Debugging_Value_SetArray*)msg->m_payload; + CLR_RT_HeapBlock_Array* array = cmd->m_heapblock; + CLR_RT_HeapBlock tmp; + bool fSuccess = false; + + tmp.SetObjectReference( cmd->m_heapblock ); + + // + // We can only set values in arrays of primitive types. + // + if(array != NULL && !array->m_fReference) + { + CLR_RT_HeapBlock ref; + + if(SUCCEEDED(ref.InitializeArrayReference( tmp, cmd->m_index ))) + { + if(SUCCEEDED(tmp.LoadFromReference( ref ))) + { + if(SetBlockHelper( &tmp, tmp.DataType(), cmd->m_builtinValue )) + { + if(SUCCEEDED(tmp.StoreToReference( ref, 0 ))) + { + fSuccess = true; + } + } + } + } + } + + WP_ReplyToCommand(msg, fSuccess, false, NULL, 0); + + return true; +} + +//--// + +bool CLR_DBG_Debugger::Debugging_Value_AllocateObject( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Value_AllocateObject* cmd = (CLR_DBG_Commands::Debugging_Value_AllocateObject*)msg->m_payload; + CLR_RT_HeapBlock* blk = NULL; + CLR_RT_HeapBlock* ptr = GetScratchPad_Helper( cmd->m_index ); + + if(ptr) + { + if(SUCCEEDED(g_CLR_RT_ExecutionEngine.NewObjectFromIndex( *ptr, cmd->m_td ))) + { + blk = ptr; + } + } + + return g_CLR_DBG_Debugger->GetValue( msg, blk, NULL, NULL ); +} + +bool CLR_DBG_Debugger::Debugging_Value_AllocateString( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Value_AllocateString* cmd = (CLR_DBG_Commands::Debugging_Value_AllocateString*)msg->m_payload; + CLR_RT_HeapBlock* blk = NULL; + CLR_RT_HeapBlock* ptr = GetScratchPad_Helper( cmd->m_index ); + + if(ptr) + { + CLR_RT_HeapBlock_String* str = CLR_RT_HeapBlock_String::CreateInstance( *ptr, cmd->m_size ); + + if(str) + { + char* dst = (char*)str->StringText(); + + // + // Fill the string with spaces, it will be set at a later stage. + // + memset( dst, ' ', cmd->m_size ); dst[ cmd->m_size ] = 0; + + blk = ptr; + } + } + + return g_CLR_DBG_Debugger->GetValue( msg, blk, NULL, NULL ); +} + +bool CLR_DBG_Debugger::Debugging_Value_AllocateArray( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Value_AllocateArray* cmd = (CLR_DBG_Commands::Debugging_Value_AllocateArray*)msg->m_payload; + CLR_RT_HeapBlock* blk = NULL; + CLR_RT_HeapBlock* ptr = GetScratchPad_Helper( cmd->m_index ); + + if(ptr) + { + CLR_RT_ReflectionDef_Index reflex; + + reflex.m_kind = REFLECTION_TYPE; + reflex.m_levels = cmd->m_depth; + reflex.m_data.m_type = cmd->m_td; + + if(SUCCEEDED(CLR_RT_HeapBlock_Array::CreateInstance( *ptr, cmd->m_numOfElements, reflex ))) + { + blk = ptr; + } + } + + return g_CLR_DBG_Debugger->GetValue( msg, blk, NULL, NULL ); +} + +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + +#if defined(NANOCLR_PROFILE_NEW) +bool CLR_DBG_Debugger::Profiling_Command( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + CLR_DBG_Debugger* dbg = (CLR_DBG_Debugger*)&g_scratchDebugger[0]; + CLR_DBG_Commands::Profiling_Command* cmd = (CLR_DBG_Commands::Profiling_Command*)msg->m_payload; + CLR_UINT8 command = cmd->m_command; + + switch(command) + { + case CLR_DBG_Commands::Profiling_Command::c_Command_ChangeConditions: + return dbg->Profiling_ChangeConditions( msg ); + + case CLR_DBG_Commands::Profiling_Command::c_Command_FlushStream: + return dbg->Profiling_FlushStream( msg ); + + default: + return false; + } +} + +bool CLR_DBG_Debugger::Profiling_ChangeConditions( WP_Message* msg ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + CLR_DBG_Commands::Profiling_Command* parent_cmd = (CLR_DBG_Commands::Profiling_Command*)msg->m_payload; + CLR_DBG_Commands::Profiling_ChangeConditions* cmd = (CLR_DBG_Commands::Profiling_ChangeConditions*)&parent_cmd[1]; + + g_CLR_RT_ExecutionEngine.m_iProfiling_Conditions |= cmd->m_set; + g_CLR_RT_ExecutionEngine.m_iProfiling_Conditions &= ~cmd->m_reset; + + CLR_DBG_Commands::Profiling_Command::Reply cmdReply; + + cmdReply.m_raw = g_CLR_RT_ExecutionEngine.m_iProfiling_Conditions; + + WP_ReplyToCommand( msg, true, false, &cmdReply, sizeof(cmdReply) ); + + _ASSERTE(FIMPLIES(CLR_EE_PRF_IS(Allocations), CLR_EE_PRF_IS(Enabled))); + _ASSERTE(FIMPLIES(CLR_EE_PRF_IS(Calls) , CLR_EE_PRF_IS(Enabled))); + + if((cmd->m_set & CLR_RT_ExecutionEngine::c_fProfiling_Enabled) != 0) + { + g_CLR_PRF_Profiler.SendMemoryLayout(); + } + + return true; +} + +bool CLR_DBG_Debugger::Profiling_FlushStream( WP_Message* msg ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + CLR_DBG_Commands::Profiling_Command::Reply cmdReply; + + g_CLR_PRF_Profiler.Stream_Flush(); + + cmdReply.m_raw = 0; + + WP_ReplyToCommand( msg, true, false, &cmdReply, sizeof(cmdReply) ); + + return true; +} + +#endif //#if defined(NANOCLR_PROFILE_NEW) + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + +//--// + +struct AnalyzeObject +{ + CLR_RT_HeapBlock* m_ptr; + bool m_fNull; + bool m_fBoxed; + bool m_fCanBeNull; + CLR_RT_TypeDescriptor m_desc; + CLR_RT_HeapBlock m_value; +}; + +static HRESULT AnalyzeObject_Helper( CLR_RT_HeapBlock* ptr, AnalyzeObject& ao ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + NANOCLR_HEADER(); + + if(ptr && ptr->DataType() == DATATYPE_BYREF) ptr = ptr->Dereference(); + + ao.m_ptr = ptr; + + if(ptr == NULL || (ptr->DataType() == DATATYPE_OBJECT && ptr->Dereference() == NULL)) + { + ao.m_fNull = true; + ao.m_fBoxed = false; + ao.m_fCanBeNull = true; + } + else + { + NANOCLR_CHECK_HRESULT(ao.m_desc.InitializeFromObject( *ptr )); + + ao.m_fNull = false; + ao.m_fBoxed = (ptr->DataType() == DATATYPE_OBJECT && ptr->Dereference()->IsBoxed()); + + switch(ao.m_desc.m_flags & CLR_RT_DataTypeLookup::c_SemanticMask2 & ~CLR_RT_DataTypeLookup::c_SemanticMask) + { + case CLR_RT_DataTypeLookup::c_Array: + case CLR_RT_DataTypeLookup::c_ArrayList: + ao.m_fCanBeNull = true; + break; + default: + { + switch(ao.m_desc.m_flags & CLR_RT_DataTypeLookup::c_SemanticMask) + { + case CLR_RT_DataTypeLookup::c_Primitive: + case CLR_RT_DataTypeLookup::c_ValueType: + case CLR_RT_DataTypeLookup::c_Enum: + ao.m_fCanBeNull = ao.m_fBoxed || (ao.m_desc.m_handlerCls.m_data == g_CLR_RT_WellKnownTypes.m_String.m_data); + break; + + default: + ao.m_fCanBeNull = true; + break; + } + + break; + } + } + } + + NANOCLR_NOCLEANUP(); +} + +static HRESULT Assign_Helper( CLR_RT_HeapBlock* blkDst, CLR_RT_HeapBlock* blkSrc ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + NANOCLR_HEADER(); + + AnalyzeObject aoDst; + AnalyzeObject aoSrc; + CLR_RT_HeapBlock srcVal; srcVal.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc( srcVal ); + + NANOCLR_CHECK_HRESULT(AnalyzeObject_Helper( blkDst, aoDst )); + NANOCLR_CHECK_HRESULT(AnalyzeObject_Helper( blkSrc, aoSrc )); + + if(aoSrc.m_fNull) + { + if(aoDst.m_fCanBeNull == false) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + NANOCLR_CHECK_HRESULT(srcVal.StoreToReference( *blkDst, 0 )); + } + else + { + NANOCLR_CHECK_HRESULT(srcVal.LoadFromReference( *blkSrc )); + + if(aoDst.m_fNull) + { + if(aoSrc.m_fCanBeNull == false) + { + NANOCLR_CHECK_HRESULT(srcVal.PerformBoxing( aoSrc.m_desc.m_handlerCls )); + } + + blkDst->Assign( srcVal ); + } + else + { + if(srcVal.IsAValueType()) + { + if(blkDst->IsAValueType() == false) + { + NANOCLR_CHECK_HRESULT(srcVal.PerformBoxing( aoSrc.m_desc.m_handlerCls )); + } + } + else + { + if(blkDst->IsAValueType() == true) + { + NANOCLR_CHECK_HRESULT(srcVal.PerformUnboxing( aoSrc.m_desc.m_handlerCls )); + } + } + + NANOCLR_CHECK_HRESULT(blkDst->Reassign( srcVal )); + } + } + + NANOCLR_NOCLEANUP(); +} + + +bool CLR_DBG_Debugger::Debugging_Value_Assign( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Value_Assign* cmd = (CLR_DBG_Commands::Debugging_Value_Assign*)msg->m_payload; + CLR_RT_HeapBlock* blkDst = cmd->m_heapblockDst; + CLR_RT_HeapBlock* blkSrc = cmd->m_heapblockSrc; + + if(blkDst && FAILED(Assign_Helper( blkDst, blkSrc ))) + { + blkDst = NULL; + } + + return g_CLR_DBG_Debugger->GetValue( msg, blkDst, NULL, NULL ); +} + +//--// + +bool CLR_DBG_Debugger::Debugging_TypeSys_Assemblies( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_RT_Assembly_Index assemblies[ CLR_RT_TypeSystem::c_MaxAssemblies ]; + int num = 0; + + NANOCLR_FOREACH_ASSEMBLY(g_CLR_RT_TypeSystem) + { + assemblies[ num++ ].Set( pASSM->m_idx ); + } + NANOCLR_FOREACH_ASSEMBLY_END(); + + WP_ReplyToCommand( msg, true, false, assemblies, sizeof(CLR_RT_Assembly_Index) * num ); + + return true; +} + +bool CLR_DBG_Debugger::Debugging_TypeSys_AppDomains( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); +#if defined(NANOCLR_APPDOMAINS) + + int num = 0; + CLR_UINT32 appDomainIDs[ 256 ]; + + NANOCLR_FOREACH_NODE(CLR_RT_AppDomain, appDomain, g_CLR_RT_ExecutionEngine.m_appDomains) + { + appDomainIDs[ num++ ] = appDomain->m_id; + + if(num >= ARRAYSIZE(appDomainIDs)) break; + } + NANOCLR_FOREACH_NODE_END(); + + WP_ReplyToCommand( msg, true, false, appDomainIDs, sizeof(CLR_UINT32) * num ); + + return true; +#else + (void)msg; + return false; +#endif +} + +//--// + +bool CLR_DBG_Debugger::Debugging_Resolve_AppDomain( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); +#if defined(NANOCLR_APPDOMAINS) + + CLR_DBG_Commands::Debugging_Resolve_AppDomain* cmd = (CLR_DBG_Commands::Debugging_Resolve_AppDomain*)msg->m_payload; + CLR_RT_AppDomain* appDomain = g_CLR_DBG_Debugger->GetAppDomainFromID( cmd->m_id ); + CLR_UINT32 numAssemblies = 0; + CLR_DBG_Commands::Debugging_Resolve_AppDomain::Reply* cmdReply; + CLR_UINT8 buf[ sizeof(CLR_DBG_Commands::Debugging_Resolve_AppDomain::Reply) + sizeof(CLR_RT_Assembly_Index)*CLR_RT_TypeSystem::c_MaxAssemblies ]; + size_t count; + const char* name; + CLR_RT_Assembly_Index* pAssemblyIndex; + + if(appDomain) + { + cmdReply = (CLR_DBG_Commands::Debugging_Resolve_AppDomain::Reply*)&buf; + + cmdReply->m_state = appDomain->m_state; + + name = appDomain->m_strName->StringText(); + count = __min( hal_strlen_s( name ) + 1, sizeof(cmdReply->m_szName) - 1 ); + + hal_strncpy_s( cmdReply->m_szName, ARRAYSIZE(cmdReply->m_szName), name, count ); + + pAssemblyIndex = (CLR_RT_Assembly_Index*)(&cmdReply->m_assemblies); + + NANOCLR_FOREACH_ASSEMBLY_IN_APPDOMAIN(appDomain) + { + pAssemblyIndex->Set( pASSM->m_idx ); + pAssemblyIndex++; + numAssemblies++; + } + NANOCLR_FOREACH_ASSEMBLY_IN_APPDOMAIN_END(); + + WP_ReplyToCommand( msg, true, false, cmdReply, sizeof(*cmdReply) + sizeof(CLR_RT_Assembly_Index) * (numAssemblies - 1) ); + } + else + { + WP_ReplyToCommand(msg, false, false, NULL, 0); + } + + return true; +#else + (void)msg; + return false; +#endif +} + +bool CLR_DBG_Debugger::Debugging_Resolve_Assembly( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Resolve_Assembly* cmd = (CLR_DBG_Commands::Debugging_Resolve_Assembly*)msg->m_payload; + CLR_DBG_Commands::Debugging_Resolve_Assembly::Reply cmdReply; + CLR_RT_Assembly* assm = g_CLR_DBG_Debugger->IsGoodAssembly( cmd->m_idx.Assembly() ); + + if(assm) + { +#if defined(_WIN32) + //append path + if(assm->m_strPath != NULL) + { + sprintf_s( cmdReply.m_szName, ARRAYSIZE(cmdReply.m_szName), "%s,%s", assm->m_szName, assm->m_strPath->c_str() ); + } + else +#endif + { + hal_strncpy_s( cmdReply.m_szName, ARRAYSIZE(cmdReply.m_szName), assm->m_szName, MAXSTRLEN(cmdReply.m_szName) ); + } + + cmdReply.m_flags = assm->m_flags; + cmdReply.m_version = assm->m_header->version; + + WP_ReplyToCommand( msg, true, false, &cmdReply, sizeof(cmdReply) ); + + return true; + } + + WP_ReplyToCommand(msg, false, false, NULL, 0); + + return true; +} + +bool CLR_DBG_Debugger::Debugging_Resolve_Type( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Resolve_Type* cmd = (CLR_DBG_Commands::Debugging_Resolve_Type*)msg->m_payload; + CLR_DBG_Commands::Debugging_Resolve_Type::Reply cmdReply; + CLR_RT_TypeDef_Instance inst; + + if(g_CLR_DBG_Debugger->CheckTypeDef( cmd->m_td, inst )) + { + char* szBuffer = cmdReply.m_type; + size_t iBuffer = MAXSTRLEN(cmdReply.m_type); + + if(SUCCEEDED(g_CLR_RT_TypeSystem.BuildTypeName( inst, szBuffer, iBuffer ))) + { + WP_ReplyToCommand( msg, true, false, &cmdReply, sizeof(cmdReply) ); + + return true; + } + } + + WP_ReplyToCommand(msg, false, false, NULL, 0); + + return true; +} + +bool CLR_DBG_Debugger::Debugging_Resolve_Field( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Resolve_Field* cmd = (CLR_DBG_Commands::Debugging_Resolve_Field*)msg->m_payload; + CLR_DBG_Commands::Debugging_Resolve_Field::Reply cmdReply; + CLR_RT_FieldDef_Instance inst; + + if(g_CLR_DBG_Debugger->CheckFieldDef( cmd->m_fd, inst )) + { + char* szBuffer = cmdReply.m_name; + size_t iBuffer = MAXSTRLEN(cmdReply.m_name); + + if(SUCCEEDED(g_CLR_RT_TypeSystem.BuildFieldName( inst, szBuffer, iBuffer ))) + { + CLR_RT_TypeDef_Instance instClass; instClass.InitializeFromField( inst ); + + cmdReply.m_td = instClass; + cmdReply.m_index = inst.CrossReference().m_offset; + + WP_ReplyToCommand( msg, true, false, &cmdReply, sizeof(cmdReply) ); + + return true; + } + } + + WP_ReplyToCommand(msg, false, false, NULL, 0); + + return true; +} + +bool CLR_DBG_Debugger::Debugging_Resolve_Method( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Resolve_Method* cmd = (CLR_DBG_Commands::Debugging_Resolve_Method*)msg->m_payload; + CLR_DBG_Commands::Debugging_Resolve_Method::Reply cmdReply; + CLR_RT_MethodDef_Instance inst; + CLR_RT_TypeDef_Instance instOwner; + + if(g_CLR_DBG_Debugger->CheckMethodDef( cmd->m_md, inst ) && instOwner.InitializeFromMethod( inst )) + { + char* szBuffer = cmdReply.m_method; + size_t iBuffer = MAXSTRLEN(cmdReply.m_method); + + cmdReply.m_td = instOwner; + + CLR_SafeSprintf( szBuffer, iBuffer, "%s", inst.m_assm->GetString( inst.m_target->name ) ); + + WP_ReplyToCommand( msg, true, false, &cmdReply, sizeof(cmdReply) ); + + return true; + } + + WP_ReplyToCommand(msg, false, false, NULL, 0); + + return true; +} + +bool CLR_DBG_Debugger::Debugging_Resolve_VirtualMethod( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Resolve_VirtualMethod* cmd = (CLR_DBG_Commands::Debugging_Resolve_VirtualMethod*)msg->m_payload; + CLR_DBG_Commands::Debugging_Resolve_VirtualMethod::Reply cmdReply; + CLR_RT_TypeDef_Index cls; + CLR_RT_MethodDef_Index md; + + cmdReply.m_md.Clear(); + + if(SUCCEEDED(CLR_RT_TypeDescriptor::ExtractTypeIndexFromObject( *cmd->m_obj, cls ))) + { + if(g_CLR_RT_EventCache.FindVirtualMethod( cls, cmd->m_md, md )) + { + cmdReply.m_md = md; + } + } + + WP_ReplyToCommand( msg, true, false, &cmdReply, sizeof(cmdReply) ); + + return true; +} + + +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + +//--// + + +bool CLR_DBG_Debugger::Debugging_Deployment_Status( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Deployment_Status::Reply* cmdReply; + CLR_UINT32 totLength; + CLR_UINT32 deploySectorsNum = 0; + CLR_UINT32 deploySectorStart = 0; + CLR_UINT32 deployLength = 0; + + // find the first device in list with DEPLOYMENT blocks + if (m_deploymentStorageDevice != NULL) + { + BlockStorageStream stream; + + if(BlockStorageStream_InitializeWithBlockStorageDevice(&stream, BlockUsage_DEPLOYMENT, m_deploymentStorageDevice )) + { + do + { + if(deploySectorsNum == 0) + { + deploySectorStart = BlockStorageStream_CurrentAddress(&stream); + } + deployLength += stream.Length; + deploySectorsNum ++; + } + while(BlockStorageStream_NextStream(&stream) && stream.BaseAddress == (deploySectorStart + deployLength)); + } + + totLength = sizeof(CLR_DBG_Commands::Debugging_Deployment_Status::Reply); + + cmdReply = (CLR_DBG_Commands::Debugging_Deployment_Status::Reply*)CLR_RT_Memory::Allocate( totLength, true ); + + if(!cmdReply) return false; + + CLR_RT_Memory::ZeroFill( cmdReply, totLength ); + + cmdReply->EntryPoint = g_CLR_RT_TypeSystem.m_entryPoint.m_data; + cmdReply->StorageStart = deploySectorStart; + cmdReply->StorageLength = deployLength; + + WP_ReplyToCommand( msg, true, false, cmdReply, totLength ); + + CLR_RT_Memory::Release( cmdReply ); + + return true; + } + else + { + WP_ReplyToCommand( msg, false, false, NULL, 0 ); + return false; + } +} + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + +bool CLR_DBG_Debugger::Debugging_Info_SetJMC_Method( const CLR_RT_MethodDef_Index& idx, bool fJMC ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + CLR_RT_MethodDef_Instance inst; + + if(!CheckMethodDef( idx, inst ) ) return false; + if(inst.m_target->RVA == CLR_EmptyIndex) return false; + + inst.DebuggingInfo().SetJMC( fJMC ); + + return true; +} + +bool CLR_DBG_Debugger::Debugging_Info_SetJMC_Type( const CLR_RT_TypeDef_Index& idx, bool fJMC ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + const CLR_RECORD_TYPEDEF* td; + CLR_RT_TypeDef_Instance inst; + int totMethods; + CLR_RT_MethodDef_Index md; + + if(!CheckTypeDef( idx, inst )) return false; + + td = inst.m_target; + totMethods = td->vMethods_Num + td->iMethods_Num + td->sMethods_Num; + + for(int i=0; imethods_First + i ); + + Debugging_Info_SetJMC_Method( md, fJMC ); + } + + return true; +} + +bool CLR_DBG_Debugger::Debugging_Info_SetJMC( WP_Message* msg) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + CLR_DBG_Commands::Debugging_Info_SetJMC* cmd = (CLR_DBG_Commands::Debugging_Info_SetJMC*)msg->m_payload; + bool fJMC = (cmd->m_fIsJMC != 0); + + switch(cmd->m_kind) + { + case REFLECTION_ASSEMBLY: + { + CLR_RT_Assembly* assm = g_CLR_DBG_Debugger->IsGoodAssembly( cmd->m_data.m_assm.Assembly() ); + + if(!assm) return false; + + for(int i=0; im_pTablesSize[ TBL_TypeDef ]; i++) + { + CLR_RT_TypeDef_Index idx; + + idx.Set( cmd->m_data.m_assm.Assembly(), i ); + + g_CLR_DBG_Debugger->Debugging_Info_SetJMC_Type( idx, fJMC ); + } + + return true; + } + + case REFLECTION_TYPE: + return g_CLR_DBG_Debugger->Debugging_Info_SetJMC_Type( cmd->m_data.m_type, fJMC ); + + case REFLECTION_METHOD: + return g_CLR_DBG_Debugger->Debugging_Info_SetJMC_Method( cmd->m_data.m_method, fJMC ); + + default: + return false; + } +} + +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) diff --git a/source/native/nf-interpreter/src/CLR/Debugger/Debugger.h b/source/native/nf-interpreter/src/CLR/Debugger/Debugger.h new file mode 100644 index 00000000..5c82eff7 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Debugger/Debugger.h @@ -0,0 +1,101 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _DEBUGGER_H_ +#define _DEBUGGER_H_ + +// enum with CLR debugging commands +// backwards compatible with .NETMF +typedef enum CLR_DBG_Commands_Debugging +{ + CLR_DBG_Commands_c_Debugging_Execution_BasePtr = 0x00020000, // Returns the pointer for the ExecutionEngine object. + CLR_DBG_Commands_c_Debugging_Execution_ChangeConditions = 0x00020001, // Sets/resets the state of the debugger. + CLR_DBG_Commands_c_Debugging_Execution_SecurityKey = 0x00020002, // Sets security key. + CLR_DBG_Commands_c_Debugging_Execution_Unlock = 0x00020003, // Unlock the low-level command, for mfg. test programs. + CLR_DBG_Commands_c_Debugging_Execution_Allocate = 0x00020004, // Permanently allocate some memory. + CLR_DBG_Commands_c_Debugging_Execution_Breakpoints = 0x00020005, // Sets breakpoints. + CLR_DBG_Commands_c_Debugging_Execution_BreakpointHit = 0x00020006, // Notification that a breakpoint was hit. + CLR_DBG_Commands_c_Debugging_Execution_BreakpointStatus = 0x00020007, // Queries last breakpoint hit. + CLR_DBG_Commands_c_Debugging_Execution_QueryCLRCapabilities = 0x00020008, // Queries capabilities of the CLR. + CLR_DBG_Commands_c_Debugging_Execution_SetCurrentAppDomain = 0x00020009, // Sets the current AppDomain. This is required before + // performing certain debugging operations, such as + // accessing a static field, or doing function evaluation, + + CLR_DBG_Commands_c_Debugging_Thread_Create = 0x00020010, // OBSOLETE - Use c_Debugging_Thread_CreateEx instead. + CLR_DBG_Commands_c_Debugging_Thread_List = 0x00020011, // Lists the active/waiting threads. + CLR_DBG_Commands_c_Debugging_Thread_Stack = 0x00020012, // Lists the call stack for a thread. + CLR_DBG_Commands_c_Debugging_Thread_Kill = 0x00020013, // Kills a thread. + CLR_DBG_Commands_c_Debugging_Thread_Suspend = 0x00020014, // Suspends the execution of a thread. + CLR_DBG_Commands_c_Debugging_Thread_Resume = 0x00020015, // Resumes the execution of a thread. + CLR_DBG_Commands_c_Debugging_Thread_GetException = 0x00020016, // Gets the current exception. + CLR_DBG_Commands_c_Debugging_Thread_Unwind = 0x00020017, // Unwinds to given stack frame. + CLR_DBG_Commands_c_Debugging_Thread_CreateEx = 0x00020018, // Creates a new thread but Thread.CurrentThread will return the identity of the passed thread. + CLR_DBG_Commands_c_Debugging_Thread_Get = 0x00021000, // Gets the current thread. + + CLR_DBG_Commands_c_Debugging_Stack_Info = 0x00020020, // Gets more info on a stack frame. + CLR_DBG_Commands_c_Debugging_Stack_SetIP = 0x00020021, // Sets the IP on a given thread. + + CLR_DBG_Commands_c_Debugging_Value_ResizeScratchPad = 0x00020030, // Resizes the scratchpad area. + CLR_DBG_Commands_c_Debugging_Value_GetStack = 0x00020031, // Reads a value from the stack frame. + CLR_DBG_Commands_c_Debugging_Value_GetField = 0x00020032, // Reads a value from an object's field. + CLR_DBG_Commands_c_Debugging_Value_GetArray = 0x00020033, // Reads a value from an array's element. + CLR_DBG_Commands_c_Debugging_Value_GetBlock = 0x00020034, // Reads a value from a heap block. + CLR_DBG_Commands_c_Debugging_Value_GetScratchPad = 0x00020035, // Reads a value from the scratchpad area. + CLR_DBG_Commands_c_Debugging_Value_SetBlock = 0x00020036, // Writes a value to a heap block. + CLR_DBG_Commands_c_Debugging_Value_SetArray = 0x00020037, // Writes a value to an array's element. + CLR_DBG_Commands_c_Debugging_Value_AllocateObject = 0x00020038, // Creates a new instance of an object. + CLR_DBG_Commands_c_Debugging_Value_AllocateString = 0x00020039, // Creates a new instance of a string. + CLR_DBG_Commands_c_Debugging_Value_AllocateArray = 0x0002003A, // Creates a new instance of an array. + CLR_DBG_Commands_c_Debugging_Value_Assign = 0x0002003B, // Assigns a value to another value. + + CLR_DBG_Commands_c_Debugging_TypeSys_Assemblies = 0x00020040, // Lists all the assemblies in the system. + CLR_DBG_Commands_c_Debugging_TypeSys_AppDomains = 0x00020044, // Lists all the AppDomans loaded. + + CLR_DBG_Commands_c_Debugging_Resolve_Assembly = 0x00020050, // Resolves an assembly. + CLR_DBG_Commands_c_Debugging_Resolve_Type = 0x00020051, // Resolves a type to a string. + CLR_DBG_Commands_c_Debugging_Resolve_Field = 0x00020052, // Resolves a field to a string. + CLR_DBG_Commands_c_Debugging_Resolve_Method = 0x00020053, // Resolves a method to a string. + CLR_DBG_Commands_c_Debugging_Resolve_VirtualMethod = 0x00020054, // Resolves a virtual method to the actual implementation. + CLR_DBG_Commands_c_Debugging_Resolve_AppDomain = 0x00020055, // Resolves an AppDomain to it's name, and list its loaded assemblies. + + + CLR_DBG_Commands_c_Debugging_MFUpdate_Start = 0x00020056, // + CLR_DBG_Commands_c_Debugging_MFUpdate_AddPacket = 0x00020057, // + CLR_DBG_Commands_c_Debugging_MFUpdate_Install = 0x00020058, // + CLR_DBG_Commands_c_Debugging_MFUpdate_AuthCommand = 0x00020059, // + CLR_DBG_Commands_c_Debugging_MFUpdate_Authenticate = 0x00020060, // + CLR_DBG_Commands_c_Debugging_MFUpdate_GetMissingPkts = 0x00020061, // + + CLR_DBG_Commands_c_Debugging_UpgradeToSsl = 0x00020069, // + + //--// + + CLR_DBG_Commands_c_Debugging_Button_Report = 0x00020080, // Reports a button press/release. + CLR_DBG_Commands_c_Debugging_Button_Inject = 0x00020081, // Injects a button press/release. + + CLR_DBG_Commands_c_Debugging_Deployment_Status = 0x000200B0, // Returns entryPoint and boundary of deployment area. + + CLR_DBG_Commands_c_Debugging_Info_SetJMC = 0x000200C0, // Sets code to be flagged as JMC (Just my code). + + CLR_DBG_Commands_c_Profiling_Command = 0x00030000, // Various incoming commands regarding profiling + CLR_DBG_Commands_c_Profiling_Stream = 0x00030001, // Stream for MFProfiler information. + +}CLR_DBG_Commands_Debugging; + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH nanoFramework.Tools.Debugger.WireProtocol.AccessMemoryErrorCodes (in managed code) !!! // +////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// enum with AccessMemoryErrorCodes +typedef enum AccessMemoryErrorCodes +{ + AccessMemoryErrorCode_NoError = 0x0000, // no error + AccessMemoryErrorCode_PermissionDenied = 0x0010, // permission denied to execute operation + AccessMemoryErrorCode_FailedToAllocateReadBuffer = 0x0020, // failed to allocate buffer for read operation. better check heap + AccessMemoryErrorCode_RequestedOperationFailed = 0x0030, // the requested operation failed + +}AccessMemoryErrorCodes; + +#endif //_DEBUGGER_H_ diff --git a/source/native/nf-interpreter/src/CLR/Debugger/Debugger.vcxproj b/source/native/nf-interpreter/src/CLR/Debugger/Debugger.vcxproj new file mode 100644 index 00000000..281ab691 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Debugger/Debugger.vcxproj @@ -0,0 +1,169 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + + + {58e950cc-2ff6-423c-b006-a70a19272f20} + false + false + + + {6dabcbf1-245a-4e76-bd36-8bc300c7dd82} + + + + {DD397EC4-844B-4B59-A67B-CAD6B46F1F00} + Win32Proj + Debugger + 10.0.17763.0 + + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\ + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\ + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;VERSION_MAJOR=0;VERSION_MINOR=0;VERSION_BUILD=0;VERSION_REVISION=0;OEMSYSTEMINFOSTRING="WIN_32";TARGETNAMESTRING="CLR_WIN32";PLATFORMNAMESTRING="WIN32";%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\CorLib;..\..\HAL\Include;..\..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;VERSION_MAJOR=0;VERSION_MINOR=0;VERSION_BUILD=0;VERSION_REVISION=0;OEMSYSTEMINFOSTRING="WIN_32";TARGETNAMESTRING="CLR_WIN32";PLATFORMNAMESTRING="WIN32";%(PreprocessorDefinitions) + ..\Include;..\CorLib + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;VERSION_MAJOR=0;VERSION_MINOR=0;VERSION_BUILD=0;VERSION_REVISION=0;OEMSYSTEMINFOSTRING="WIN_32";TARGETNAMESTRING="CLR_WIN32";PLATFORMNAMESTRING="WIN32";%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\CorLib;..\..\HAL\Include;..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\Include;..\CorLib + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Debugger/Debugger.vcxproj.filters b/source/native/nf-interpreter/src/CLR/Debugger/Debugger.vcxproj.filters new file mode 100644 index 00000000..808f2bd0 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Debugger/Debugger.vcxproj.filters @@ -0,0 +1,25 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Debugger/Debugger_full.cpp b/source/native/nf-interpreter/src/CLR/Debugger/Debugger_full.cpp new file mode 100644 index 00000000..9ab70cb0 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Debugger/Debugger_full.cpp @@ -0,0 +1,108 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include +#include + +#define DEFINE_CMD(cmd) { CLR_DBG_Debugger::Debugging_##cmd, CLR_DBG_Commands::c_Debugging_##cmd } +#define DEFINE_CMD2(cmd) { CLR_DBG_Debugger::Monitor_##cmd , CLR_DBG_Commands::c_Monitor_##cmd } +#define DEFINE_CMD3(cmd) { &CLR_DBG_Debugger::Profiling_##cmd, CLR_DBG_Commands::c_Profiling_##cmd } + +const CLR_Messaging_CommandHandlerLookup c_Debugger_Lookup_Request[] = +{ + DEFINE_CMD(Execution_QueryCLRCapabilities), + DEFINE_CMD2(Ping ), + DEFINE_CMD2(ReadMemory ), + DEFINE_CMD2(WriteMemory), + DEFINE_CMD2(CheckMemory), + DEFINE_CMD2(EraseMemory), + DEFINE_CMD2(QueryConfiguration), + DEFINE_CMD2(UpdateConfiguration), + // + DEFINE_CMD2(Execute ), + DEFINE_CMD2(Reboot ), + DEFINE_CMD2(MemoryMap ), + DEFINE_CMD2(FlashSectorMap), + DEFINE_CMD2(DeploymentMap), + // + DEFINE_CMD(Execution_BasePtr ), + DEFINE_CMD(Execution_ChangeConditions), + // + DEFINE_CMD(Execution_Allocate ), + + DEFINE_CMD(UpgradeToSsl), + + + + + + + + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + DEFINE_CMD(Execution_SetCurrentAppDomain), + DEFINE_CMD(Execution_Breakpoints ), + DEFINE_CMD(Execution_BreakpointStatus ), + // + DEFINE_CMD(Thread_CreateEx ), + DEFINE_CMD(Thread_List ), + DEFINE_CMD(Thread_Stack ), + DEFINE_CMD(Thread_Kill ), + DEFINE_CMD(Thread_Suspend ), + DEFINE_CMD(Thread_Resume ), + DEFINE_CMD(Thread_GetException ), + DEFINE_CMD(Thread_Unwind ), + DEFINE_CMD(Thread_Get ), + // + DEFINE_CMD(Stack_Info ), + DEFINE_CMD(Stack_SetIP ), + // + DEFINE_CMD(Value_ResizeScratchPad ), + DEFINE_CMD(Value_GetStack ), + DEFINE_CMD(Value_GetField ), + DEFINE_CMD(Value_GetArray ), + DEFINE_CMD(Value_GetBlock ), + DEFINE_CMD(Value_GetScratchPad ), + DEFINE_CMD(Value_SetBlock ), + DEFINE_CMD(Value_SetArray ), + DEFINE_CMD(Value_AllocateObject ), + DEFINE_CMD(Value_AllocateString ), + DEFINE_CMD(Value_AllocateArray ), + DEFINE_CMD(Value_Assign ), + // + DEFINE_CMD(TypeSys_Assemblies ), + DEFINE_CMD(TypeSys_AppDomains ), + // + DEFINE_CMD(Resolve_AppDomain ), + DEFINE_CMD(Resolve_Assembly ), + DEFINE_CMD(Resolve_Type ), + DEFINE_CMD(Resolve_Field ), + DEFINE_CMD(Resolve_Method ), + DEFINE_CMD(Resolve_VirtualMethod ), +#endif + // +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + DEFINE_CMD(Deployment_Status ), + DEFINE_CMD(Info_SetJMC ), +#endif + // +#if defined(NANOCLR_PROFILE_NEW) + DEFINE_CMD3(Command), +#endif + // +}; + +const CLR_Messaging_CommandHandlerLookup c_Debugger_Lookup_Reply[] = +{ + DEFINE_CMD2(Ping), +}; + +#undef DEFINE_CMD +#undef DEFINE_CMD2 +#undef DEFINE_CMD3 + +const CLR_UINT32 c_Debugger_Lookup_Request_count = ARRAYSIZE(c_Debugger_Lookup_Request); +const CLR_UINT32 c_Debugger_Lookup_Reply_count = ARRAYSIZE(c_Debugger_Lookup_Reply); + diff --git a/source/native/nf-interpreter/src/CLR/Debugger/Debugger_minimal.cpp b/source/native/nf-interpreter/src/CLR/Debugger/Debugger_minimal.cpp new file mode 100644 index 00000000..c63267cc --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Debugger/Debugger_minimal.cpp @@ -0,0 +1,48 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#define DEFINE_CMD(cmd) { CLR_DBG_Debugger::Debugging_##cmd, CLR_DBG_Commands::c_Debugging_##cmd } +#define DEFINE_CMD2(cmd) { CLR_DBG_Debugger::Monitor_##cmd , CLR_DBG_Commands::c_Monitor_##cmd } + +const CLR_Messaging_CommandHandlerLookup c_Debugger_Lookup_Request[] = +{ + DEFINE_CMD2(Ping ), + DEFINE_CMD2(Reboot ), + DEFINE_CMD(Execution_QueryCLRCapabilities), + + DEFINE_CMD2(ReadMemory ), + DEFINE_CMD2(WriteMemory), + DEFINE_CMD2(EraseMemory), + DEFINE_CMD2(QueryConfiguration), + DEFINE_CMD2(UpdateConfiguration), + // + DEFINE_CMD2(Execute ), + DEFINE_CMD2(MemoryMap ), + DEFINE_CMD2(FlashSectorMap), + + DEFINE_CMD(UpgradeToSsl), + + + + + + + +}; + +const CLR_Messaging_CommandHandlerLookup c_Debugger_Lookup_Reply[] = +{ + DEFINE_CMD2(Ping), +}; + +#undef DEFINE_CMD +#undef DEFINE_CMD2 + +const CLR_UINT32 c_Debugger_Lookup_Request_count = ARRAYSIZE(c_Debugger_Lookup_Request); +const CLR_UINT32 c_Debugger_Lookup_Reply_count = ARRAYSIZE(c_Debugger_Lookup_Reply); diff --git a/source/native/nf-interpreter/src/CLR/Debugger/Debugger_stub.cpp b/source/native/nf-interpreter/src/CLR/Debugger/Debugger_stub.cpp new file mode 100644 index 00000000..13df702f --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Debugger/Debugger_stub.cpp @@ -0,0 +1,105 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +__nfweak void CLR_DBG_Debugger::Debugger_WaitForCommands() +{ + NATIVE_PROFILE_CLR_DEBUGGER(); +} + +__nfweak void CLR_DBG_Debugger::PurgeCache() +{ + NATIVE_PROFILE_CLR_DEBUGGER(); +} + +__nfweak HRESULT CLR_DBG_Debugger::CreateInstance() +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + g_CLR_DBG_Debugger = (CLR_DBG_Debugger*)&g_scratchDebugger[0]; + NANOCLR_SYSTEM_STUB_RETURN(); +} + +//--// + +__nfweak HRESULT CLR_DBG_Debugger::DeleteInstance() +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + NANOCLR_SYSTEM_STUB_RETURN(); +} + +__nfweak void CLR_DBG_Debugger::BroadcastEvent( unsigned int cmd, unsigned int payloadSize, unsigned char* payload, unsigned int flags ) +{ + (void)cmd; + (void)payloadSize; + (void)payload; + (void)flags; + + NATIVE_PROFILE_CLR_DEBUGGER(); +} + +__nfweak void NFReleaseInfo::Init( + NFReleaseInfo& NFReleaseInfo, + unsigned short int major, + unsigned short int minor, + unsigned short int build, + unsigned short int revision, + const char *info, + size_t infoLen, + const char *target, + size_t targetLen, + const char *platform, + size_t platformLen) +{ + size_t len; + + NFVersion::Init( NFReleaseInfo.Version, major, minor, build, revision ); + + // better set these to empty strings, in case there is nothing to fill in + NFReleaseInfo.InfoString[ 0 ] = 0; + NFReleaseInfo.TargetName[ 0 ] = 0; + NFReleaseInfo.PlatformName[ 0 ] = 0; + + // fill each one, if it was provided + if (NULL != info) + { + len = MIN(infoLen, sizeof(NFReleaseInfo.InfoString) - 1); + memcpy(NFReleaseInfo.InfoString, info, len); + NFReleaseInfo.InfoString[len] = 0; + } + + if (NULL != target) + { + len = MIN(targetLen, sizeof(NFReleaseInfo.TargetName) - 1); + memcpy(NFReleaseInfo.TargetName, target, len); + NFReleaseInfo.TargetName[len] = 0; + } + + if (NULL != platform) + { + len = MIN(platformLen, sizeof(NFReleaseInfo.PlatformName) - 1); + memcpy(NFReleaseInfo.PlatformName, platform, len); + NFReleaseInfo.PlatformName[len] = 0; + } +} + +__nfweak bool SOCKETS_DbgInitialize( int ComPortNum ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + (void)ComPortNum; + return true; +} + +__nfweak bool SOCKETS_DbgUninitialize( int ComPortNum ) +{ + NATIVE_PROFILE_CLR_DEBUGGER(); + + (void)ComPortNum; + return true; +} diff --git a/source/native/nf-interpreter/src/CLR/Debugger/Debugger_stub.vcxproj b/source/native/nf-interpreter/src/CLR/Debugger/Debugger_stub.vcxproj new file mode 100644 index 00000000..0bc8b206 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Debugger/Debugger_stub.vcxproj @@ -0,0 +1,158 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + {6DABCBF1-245A-4E76-BD36-8BC300C7DD82} + Win32Proj + Debugger_stub + 10.0.17763.0 + + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\..\HAL\Include;..\..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + ..\Include + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\..\HAL\Include;..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\Include + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Debugger/Debugger_stub.vcxproj.filters b/source/native/nf-interpreter/src/CLR/Debugger/Debugger_stub.vcxproj.filters new file mode 100644 index 00000000..3397cd3f --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Debugger/Debugger_stub.vcxproj.filters @@ -0,0 +1,22 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Diagnostics/Diagnostics-vs2019.vcxproj b/source/native/nf-interpreter/src/CLR/Diagnostics/Diagnostics-vs2019.vcxproj new file mode 100644 index 00000000..1aaf7502 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Diagnostics/Diagnostics-vs2019.vcxproj @@ -0,0 +1,162 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + + + + + + {A5E9AE41-F4FA-40CE-AD82-A7861EBA007B} + Win32Proj + Diagnostics + 10.0.17763.0 + Diagnostics + + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + false + v142 + true + Unicode + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + false + v142 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(SolutionDir)$(Configuration)\ + $(IntDir) + + + $(SolutionDir)$(Configuration)\ + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\CorLib;..\..\HAL\Include;..\..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\CorLib;..\..\HAL\Include;..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Diagnostics/Diagnostics-vs2019.vcxproj.filters b/source/native/nf-interpreter/src/CLR/Diagnostics/Diagnostics-vs2019.vcxproj.filters new file mode 100644 index 00000000..b2219695 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Diagnostics/Diagnostics-vs2019.vcxproj.filters @@ -0,0 +1,33 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Header Files + + + + + Source Files + + + Source Files + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Diagnostics/Diagnostics.h b/source/native/nf-interpreter/src/CLR/Diagnostics/Diagnostics.h new file mode 100644 index 00000000..aabf7238 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Diagnostics/Diagnostics.h @@ -0,0 +1,18 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include +#include +//#include +//#include +//#include +//#include + +#include +#if !defined(_WIN32) +#include +#endif // !defined(_WIN32) +//#include + diff --git a/source/native/nf-interpreter/src/CLR/Diagnostics/Diagnostics.vcxproj b/source/native/nf-interpreter/src/CLR/Diagnostics/Diagnostics.vcxproj new file mode 100644 index 00000000..cb2c02bd --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Diagnostics/Diagnostics.vcxproj @@ -0,0 +1,161 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + + + + + + {A5E9AE41-F4FA-40CE-AD82-A7861EBA007B} + Win32Proj + Diagnostics + 10.0.17763.0 + + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\ + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\ + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\CorLib;..\..\HAL\Include;..\..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\CorLib;..\..\HAL\Include;..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Diagnostics/Diagnostics.vcxproj.filters b/source/native/nf-interpreter/src/CLR/Diagnostics/Diagnostics.vcxproj.filters new file mode 100644 index 00000000..b2219695 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Diagnostics/Diagnostics.vcxproj.filters @@ -0,0 +1,33 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Header Files + + + + + Source Files + + + Source Files + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Diagnostics/Diagnostics_stub.cpp b/source/native/nf-interpreter/src/CLR/Diagnostics/Diagnostics_stub.cpp new file mode 100644 index 00000000..cfb883d5 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Diagnostics/Diagnostics_stub.cpp @@ -0,0 +1,561 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Diagnostics.h" + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#if defined(_WIN32) + +__nfweak void CLR_Debug::RedirectToString( std::string* str ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +#endif + +__nfweak HRESULT NANOCLR_DEBUG_PROCESS_EXCEPTION( HRESULT hr, const char* szFunc, const char* szFile, int line ) +{ + (void)szFunc; + (void)szFile; + (void)line; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + return hr; +} + +__nfweak bool CLR_SafeSprintfV( char*& szBuffer, size_t& iBuffer, const char* format, va_list arg ) +{ + (void)szBuffer; + (void)iBuffer; + (void)format; + (void)arg; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + + return FALSE; +} + +__nfweak bool CLR_SafeSprintf( char*& szBuffer, size_t& iBuffer, const char* format, ... ) +{ + (void)szBuffer; + (void)iBuffer; + (void)format; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + + return FALSE; +} + +//--// + +__nfweak void CLR_Debug::Flush() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_Debug::Emit( const char *text, int len ) +{ + (void)text; + (void)len; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak int CLR_Debug::PrintfV( const char *format, va_list arg ) +{ + (void)format; + (void)arg; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + return 0; +} + +__nfweak int CLR_Debug::Printf( const char *format, ... ) +{ + (void)format; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + return 0; +} + +//--// + +__nfweak CLR_UINT32 CLR_ReadTokenCompressed( const CLR_UINT8*& ip, CLR_OPCODE opcode ) +{ + (void)ip; + (void)opcode; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + return 0; +} + +__nfweak const CLR_UINT8* CLR_SkipBodyOfOpcode( const CLR_UINT8* ip, CLR_OPCODE opcode ) +{ + (void)ip; + (void)opcode; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + return 0; +} + +__nfweak const CLR_UINT8* CLR_SkipBodyOfOpcodeCompressed( const CLR_UINT8* ip, CLR_OPCODE opcode ) +{ + (void)ip; + (void)opcode; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + return 0; +} + +#if defined(NANOCLR_TRACE_INSTRUCTIONS) + +__nfweak void CLR_RT_Assembly::DumpToken( CLR_UINT32 tk ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_RT_Assembly::DumpSignature( CLR_SIG sig ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_RT_Assembly::DumpSignature( const CLR_UINT8*& p ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_RT_Assembly::DumpSignatureToken( const CLR_UINT8*& p ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +//--// + +__nfweak void CLR_RT_Assembly::DumpOpcode( CLR_RT_StackFrame* stack, CLR_PMETADATA ip ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_RT_Assembly::DumpOpcodeDirect( CLR_RT_MethodDef_Instance& call, CLR_PMETADATA ip, CLR_PMETADATA ipStart, int pid ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +#endif + +#if defined(NANOCLR_TRACE_CALLS) + +__nfweak void CLR_RT_Assembly::DumpCall( CLR_RT_StackFrame& stack, bool fPush ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_RT_Assembly::DumpCall( CLR_RT_MethodDef_Instance& md, const char* szPrefix ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +#endif + +/////////////////////////////////////////////////////////////////////////////////////////////////// + +#if defined(NANOCLR_TRACE_ERRORS) + +__nfweak void CLR_RT_DUMP::TYPE( const CLR_RT_TypeDef_Index& cls ) +{ + (void)cls; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_RT_DUMP::TYPE( const CLR_RT_ReflectionDef_Index& reflex ) +{ + (void)reflex; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_RT_DUMP::METHOD( const CLR_RT_MethodDef_Index& method ) +{ + (void)method; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_RT_DUMP::FIELD( const CLR_RT_FieldDef_Index& field ) +{ + (void)field; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_RT_DUMP::OBJECT( CLR_RT_HeapBlock* ptr, const char* text ) +{ + (void)ptr; + (void)text; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +#endif + +//--// + +#if defined(NANOCLR_TRACE_EXCEPTIONS) + +__nfweak void CLR_RT_DUMP::EXCEPTION( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock& ref ) +{ + (void)stack; + (void)ref; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_RT_DUMP::POST_PROCESS_EXCEPTION( CLR_RT_HeapBlock& ref ) +{ + (void)ref; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +#endif + +//--// + +__nfweak const char* CLR_RT_DUMP::GETERRORMESSAGE( HRESULT hrError ) +{ + (void)hrError; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + return NULL; +} + +//--// + +#if defined(NANOCLR_PROFILE_NEW_CALLS) + +__nfweak void* CLR_PROF_CounterCallChain::Prepare( CLR_PROF_Handler* handler ) +{ + (void)handler; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + return NULL; +} + +__nfweak void CLR_PROF_CounterCallChain::Complete( CLR_UINT64& t, CLR_PROF_Handler* handler ) +{ + (void)t; + (void)handler; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_PROF_CounterCallChain::Enter( CLR_RT_StackFrame* stack ) +{ + (void)stack; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_PROF_CounterCallChain::Leave() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} +#endif + +//--// + +#if defined(NANOCLR_PROFILE_HANDLER) + +__nfweak void CLR_PROF_Handler::Constructor() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +#if defined(NANOCLR_PROFILE_NEW_CALLS) +__nfweak void CLR_PROF_Handler::Constructor( CLR_PROF_CounterCallChain& target ) +{ + (void)target; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} +#endif + +__nfweak void CLR_PROF_Handler::Destructor() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + + +__nfweak void CLR_PROF_Handler::Init( void* target ) +{ + (void)target; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + + +//--// + +__nfweak void CLR_PROF_Handler::Calibrate() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_PROF_Handler::SuspendTime() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak CLR_UINT64 CLR_PROF_Handler::GetFrozenTime() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + return 0; +} + +__nfweak CLR_UINT64 CLR_PROF_Handler::ResumeTime() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + return 0; +} + +__nfweak CLR_UINT64 CLR_PROF_Handler::ResumeTime( CLR_INT64 t ) +{ + (void)t; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + return 0; +} + +#endif //#if defined(NANOCLR_PROFILE_HANDLER) + +//////////////////////////////////////////////////////////////////////////////// + +//--// + +#if defined(NANOCLR_PROFILE_NEW) + +__nfweak CLR_PRF_Profiler g_CLR_PRF_Profiler; + +__nfweak HRESULT CLR_PRF_Profiler::CreateInstance() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + return S_OK; +} + +__nfweak HRESULT CLR_PRF_Profiler::DeleteInstance() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + return S_OK; +} + +__nfweak HRESULT CLR_PRF_Profiler::Profiler_Cleanup() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + return S_OK; +} + +__nfweak void CLR_PRF_Profiler::SendMemoryLayout() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak HRESULT CLR_PRF_Profiler::DumpHeap() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + return S_OK; +} + +__nfweak HRESULT CLR_PRF_Profiler::DumpRoots() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + return S_OK; +} + +__nfweak void CLR_PRF_Profiler::DumpRoot(CLR_RT_HeapBlock* root, CLR_UINT32 type, CLR_UINT32 flags, CLR_RT_MethodDef_Index* source) +{ + (void)root; + (void)type; + (void)flags; + (void)source; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_PRF_Profiler::DumpObject(CLR_RT_HeapBlock* ptr) +{ + (void)ptr; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak CLR_RT_HeapBlock* CLR_PRF_Profiler::FindReferencedObject(CLR_RT_HeapBlock* ref) +{ + (void)ref; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + return NULL; +} + +__nfweak void CLR_PRF_Profiler::DumpEndOfRefsList() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_PRF_Profiler::DumpPointer(void* ptr) +{ + (void)ptr; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_PRF_Profiler::DumpSingleReference(CLR_RT_HeapBlock* ptr) +{ + (void)ptr; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_PRF_Profiler::DumpListOfReferences(CLR_RT_HeapBlock* firstItem, CLR_UINT16 count) +{ + (void)firstItem; + (void)count; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_PRF_Profiler::DumpListOfReferences(CLR_RT_DblLinkedList& list) +{ + (void)list; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +//--// + +__nfweak void CLR_PRF_Profiler::Timestamp() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +//--// + +__nfweak HRESULT CLR_PRF_Profiler::RecordContextSwitch(CLR_RT_Thread* nextThread) +{ + (void)nextThread; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + return S_OK; +} + +__nfweak HRESULT CLR_PRF_Profiler::RecordFunctionCall(CLR_RT_Thread* th, CLR_RT_MethodDef_Index md) +{ + (void)th; + (void)md; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + return S_OK; +} + +__nfweak HRESULT CLR_PRF_Profiler::RecordFunctionReturn(CLR_RT_Thread* th, CLR_PROF_CounterCallChain& prof) +{ + (void)th; + (void)prof; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + return S_OK; +} + +//--// + +__nfweak void CLR_PRF_Profiler::TrackObjectCreation( CLR_RT_HeapBlock* ptr ) +{ + (void)ptr; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_PRF_Profiler::TrackObjectDeletion( CLR_RT_HeapBlock* ptr ) +{ + (void)ptr; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_PRF_Profiler::TrackObjectRelocation() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_PRF_Profiler::RecordGarbageCollectionBegin() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_PRF_Profiler::RecordGarbageCollectionEnd() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_PRF_Profiler::RecordHeapCompactionBegin() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_PRF_Profiler::RecordHeapCompactionEnd() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +//--// + +__nfweak void CLR_PRF_Profiler::SendTrue() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_PRF_Profiler::SendFalse() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_PRF_Profiler::PackAndWriteBits(CLR_UINT32 value) +{ + (void)value; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_PRF_Profiler::PackAndWriteBits(const CLR_RT_TypeDef_Index& typeDef) +{ + (void)typeDef; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +__nfweak void CLR_PRF_Profiler::PackAndWriteBits(const CLR_RT_MethodDef_Index& methodDef) +{ + (void)methodDef; + + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +} + +//--// + +__nfweak HRESULT CLR_PRF_Profiler::Stream_Send() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + return S_OK; +} + +__nfweak HRESULT CLR_PRF_Profiler::Stream_Flush() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + return S_OK; +} + +#endif //#if defined(NANOCLR_PROFILE_NEW) diff --git a/source/native/nf-interpreter/src/CLR/Diagnostics/Diagnostics_stub.vcxproj b/source/native/nf-interpreter/src/CLR/Diagnostics/Diagnostics_stub.vcxproj new file mode 100644 index 00000000..0776978b --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Diagnostics/Diagnostics_stub.vcxproj @@ -0,0 +1,161 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + + + + {C97A9845-02DC-46E4-B219-BF5EA8FB28E3} + Win32Proj + Diagnostics_stub + 10.0.17763.0 + + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\CorLib;..\..\HAL\Include;..\..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + ..\Include;..\CorLib + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\CorLib;..\..\HAL\Include;..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\Include;..\CorLib + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Diagnostics/Diagnostics_stub.vcxproj.filters b/source/native/nf-interpreter/src/CLR/Diagnostics/Diagnostics_stub.vcxproj.filters new file mode 100644 index 00000000..7fa5fc72 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Diagnostics/Diagnostics_stub.vcxproj.filters @@ -0,0 +1,27 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Header Files + + + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Diagnostics/Info.cpp b/source/native/nf-interpreter/src/CLR/Diagnostics/Info.cpp new file mode 100644 index 00000000..ca54f55b --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Diagnostics/Info.cpp @@ -0,0 +1,859 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Diagnostics.h" + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#if defined(_WIN32) + +static std::string* s_redirectedString = NULL; + +void CLR_Debug::RedirectToString( std::string* str ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + s_redirectedString = str; +} + +static std::string s_messageString = ""; + +void CLR_Debug::SaveMessage(std::string str) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + + // clear LR & CR + int pos; + if ((pos = str.find('\n')) != std::string::npos) + { + str.erase(pos); + } + if ((pos = str.find('\r')) != std::string::npos) + { + str.erase(pos); + } + + s_messageString = str; +} + +HRESULT NANOCLR_DEBUG_PROCESS_EXCEPTION( HRESULT hr, const char* szFunc, const char* szFile, int line ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + switch(hr) + { + case CLR_E_ENTRY_NOT_FOUND: + case CLR_E_PROCESS_EXCEPTION: + case CLR_E_THREAD_WAITING: + case CLR_E_RESTART_EXECUTION: + case CLR_E_RESCHEDULE: + case CLR_E_OUT_OF_MEMORY: + return hr; + } + + if(s_CLR_RT_fTrace_StopOnFAILED >= c_CLR_RT_Trace_Info) + { + if(::IsDebuggerPresent()) + { + ::DebugBreak(); + } + } + return hr; +} + +#else + +#if defined(NANOCLR_TRACE_HRESULT) +HRESULT NANOCLR_DEBUG_PROCESS_EXCEPTION( HRESULT hr, const char* szFunc, const char* szFile, int line ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + switch(hr) + { + case CLR_E_ENTRY_NOT_FOUND: + + case CLR_E_PROCESS_EXCEPTION: + case CLR_E_THREAD_WAITING: + case CLR_E_RESTART_EXECUTION: + return hr; + } + + CLR_Debug::Printf( "HRESULT %08x: %s %s:%d\r\n", hr, szFunc, szFile, line ); + return hr; +} +#endif + +#endif + +//--// + +bool CLR_SafeSprintfV( char*& szBuffer, size_t& iBuffer, const char* format, va_list arg ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + + int chars = vsnprintf( szBuffer, iBuffer, format, arg ); + bool fRes = (chars >= 0); + + if(fRes == false) chars = (int)iBuffer; + + szBuffer += chars; szBuffer[ 0 ] = 0; + iBuffer -= chars; + + return fRes; +} + +bool CLR_SafeSprintf( char*& szBuffer, size_t& iBuffer, const char* format, ... ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + va_list arg; + bool fRes; + + va_start( arg, format ); + + fRes = CLR_SafeSprintfV( szBuffer, iBuffer, format, arg ); + + va_end( arg ); + + return fRes; +} + + +//--// + +void CLR_Debug::Flush() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + DebuggerPort_Flush( HalSystemConfig.DebugTextPort ); +} + +void CLR_Debug::Emit( const char *text, int len ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + static char s_buffer[ 128 ]; + static int s_chars = 0; + + if(CLR_EE_DBG_IS( RebootPending)) return; + + if(len == -1) len = (int)hal_strlen_s( text ); + +#if defined(_WIN32) + if(s_redirectedString) + { + s_redirectedString->append( text, len ); + return; + } + + if(s_CLR_RT_fTrace_RedirectOutput.size()) + { + static HANDLE hFile = INVALID_HANDLE_VALUE; + static int lines = 0; + static int num = 0; + + if(hFile == INVALID_HANDLE_VALUE) + { + std::wstring file = s_CLR_RT_fTrace_RedirectOutput; + + if(s_CLR_RT_fTrace_RedirectLinesPerFile) + { + wchar_t rgBuf[ 64 ]; + + swprintf( rgBuf, ARRAYSIZE(rgBuf), L".%08d", num++ ); + + file.append( rgBuf ); + } + + hFile = ::CreateFileW( file.c_str(), GENERIC_WRITE, FILE_SHARE_READ | FILE_SHARE_WRITE, 0, CREATE_ALWAYS, 0, 0 ); + + lines = 0; + } + + if(hFile != INVALID_HANDLE_VALUE) + { + unsigned long dwWritten; + + ::WriteFile( hFile, text, (unsigned long)len, &dwWritten, NULL ); + + if(s_CLR_RT_fTrace_RedirectLinesPerFile) + { + while((text = strchr( text, '\n' )) != NULL) + { + lines++; + text++; + + if(text[ 0 ] == 0) + { + if(lines > s_CLR_RT_fTrace_RedirectLinesPerFile) + { + ::CloseHandle( hFile ); hFile = INVALID_HANDLE_VALUE; + } + + break; + } + } + } + + return; + } + } +#endif + + while(len > 0) + { + int avail = MAXSTRLEN(s_buffer) - s_chars; + + if(len < avail) avail = len; + + memcpy( &s_buffer[ s_chars ], text, avail ); + + s_chars += avail; + text += avail; + len -= avail; + s_buffer[ s_chars ] = 0; + + if(s_chars > 80 || strchr( s_buffer, '\n' )) + { + Watchdog_Reset(); + +#if defined(PLATFORM_WINDOWS_EMULATOR) + HAL_Windows_Debug_Print( s_buffer ); +#endif + + if(CLR_EE_DBG_IS( Enabled ) && !CLR_EE_DBG_IS( Quiet )) + { + CLR_EE_DBG_EVENT_BROADCAST( CLR_DBG_Commands::c_Monitor_Message, s_chars, s_buffer, WP_Flags_c_NonCritical | WP_Flags_c_NoCaching ); + } + + if(HalSystemConfig.DebugTextPort != HalSystemConfig.DebuggerPort) + { +#if !defined(_WIN32) + DebuggerPort_Write( HalSystemConfig.DebugTextPort, s_buffer, s_chars, 0 ); // skip null terminator and don't bother retrying + DebuggerPort_Flush( HalSystemConfig.DebugTextPort ); // skip null terminator +#endif + } + + s_chars = 0; + } + } +} + +int CLR_Debug::PrintfV( const char *format, va_list arg ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + +#if defined(_WIN32) + char buffer[512]; + char* szBuffer = buffer; + int16_t bufferSize = MAXSTRLEN(buffer); + size_t iBuffer = bufferSize; +#else + // this should be more than enough for the existing output needs + const int16_t c_BufferSize = 512; + + char* buffer = (char*)platform_malloc(c_BufferSize); + char* szBuffer = buffer; + size_t iBuffer = c_BufferSize; + int16_t bufferSize = c_BufferSize; +#endif + + bool fRes = CLR_SafeSprintfV(szBuffer, iBuffer, format, arg ); + + _ASSERTE(fRes); + + iBuffer = bufferSize - iBuffer; + + Emit( buffer, (int)iBuffer ); + +#if defined(_WIN32) + OutputDebugStringA(buffer); + + std::string outputString(buffer, iBuffer); + SaveMessage(outputString); + +#endif + +#if !defined(_WIN32) + if(buffer != NULL) + { + platform_free(buffer); + } +#endif + + return (int)iBuffer; +} + +int CLR_Debug::Printf( const char *format, ... ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + va_list arg; + int chars; + + va_start( arg, format ); + + chars = CLR_Debug::PrintfV( format, arg ); + + va_end( arg ); + + return chars; +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#if defined(_WIN32) + +const CLR_UINT8 c_CLR_opParamSize[] = +{ + 4, // CLR_OpcodeParam_Field + 4, // CLR_OpcodeParam_Method + 4, // CLR_OpcodeParam_Type + 4, // CLR_OpcodeParam_String + 4, // CLR_OpcodeParam_Tok + 4, // CLR_OpcodeParam_Sig + 4, // CLR_OpcodeParam_BrTarget + 1, // CLR_OpcodeParam_ShortBrTarget + 4, // CLR_OpcodeParam_I + 8, // CLR_OpcodeParam_I8 + 0, // CLR_OpcodeParam_None + 8, // CLR_OpcodeParam_R + 4, // CLR_OpcodeParam_Switch + 2, // CLR_OpcodeParam_Var + 1, // CLR_OpcodeParam_ShortI + 4, // CLR_OpcodeParam_ShortR + 1, // CLR_OpcodeParam_ShortVar +}; + +const CLR_UINT8 c_CLR_opParamSizeCompressed[] = +{ + 2, // CLR_OpcodeParam_Field + 2, // CLR_OpcodeParam_Method + 2, // CLR_OpcodeParam_Type + 2, // CLR_OpcodeParam_String + 4, // CLR_OpcodeParam_Tok + 4, // CLR_OpcodeParam_Sig + 2, // CLR_OpcodeParam_BrTarget + 1, // CLR_OpcodeParam_ShortBrTarget + 4, // CLR_OpcodeParam_I + 8, // CLR_OpcodeParam_I8 + 0, // CLR_OpcodeParam_None + 8, // CLR_OpcodeParam_R + 1, // CLR_OpcodeParam_Switch + 2, // CLR_OpcodeParam_Var + 1, // CLR_OpcodeParam_ShortI + 4, // CLR_OpcodeParam_ShortR + 1, // CLR_OpcodeParam_ShortVar +}; + +CLR_UINT32 CLR_ReadTokenCompressed( const CLR_UINT8*& ip, CLR_OPCODE opcode ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + CLR_UINT32 arg; + const CLR_UINT8* ptr = ip; + + switch(c_CLR_RT_OpcodeLookup[ opcode ].m_opParam) + { + case CLR_OpcodeParam_Field : NANOCLR_READ_UNALIGNED_COMPRESSED_FIELDTOKEN ( arg, ptr ); break; + case CLR_OpcodeParam_Method: NANOCLR_READ_UNALIGNED_COMPRESSED_METHODTOKEN( arg, ptr ); break; + case CLR_OpcodeParam_Type : NANOCLR_READ_UNALIGNED_COMPRESSED_TYPETOKEN ( arg, ptr ); break; + case CLR_OpcodeParam_String: NANOCLR_READ_UNALIGNED_COMPRESSED_STRINGTOKEN( arg, ptr ); break; + case CLR_OpcodeParam_Tok : + case CLR_OpcodeParam_Sig : NANOCLR_READ_UNALIGNED_UINT32 ( arg, ptr ); break; + default : arg = 0; break; + } + + ip = ptr; + + return arg; +} + +// +// SkipBodyOfOpcode skips past the opcode argument & returns the address of the +// next instruction in the instruction stream. Note that this is +// not necessarily the next instruction which will be executed. +// +// ip -> address of argument for the opcode specified in +// the instruction stream. Note that this is not an +// instruction boundary, it is past the opcode. +// +const CLR_UINT8* CLR_SkipBodyOfOpcode( const CLR_UINT8* ip, CLR_OPCODE opcode ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + CLR_OpcodeParam opParam = c_CLR_RT_OpcodeLookup[ opcode ].m_opParam; + + if(opParam == CLR_OpcodeParam_Switch) + { + CLR_UINT32 numcases; NANOCLR_READ_UNALIGNED_UINT32( numcases, ip ); + + ip += numcases * sizeof(CLR_UINT32); + } + else + { + ip += c_CLR_opParamSize[ opParam ]; + } + + return ip; +} + +const CLR_UINT8* CLR_SkipBodyOfOpcodeCompressed( const CLR_UINT8* ip, CLR_OPCODE opcode ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + CLR_OpcodeParam opParam = c_CLR_RT_OpcodeLookup[ opcode ].m_opParam; + + if(opParam == CLR_OpcodeParam_Switch) + { + CLR_UINT32 numcases; NANOCLR_READ_UNALIGNED_UINT8(numcases, ip); + + ip += numcases * sizeof(CLR_UINT16); + } + else + { + ip += c_CLR_opParamSizeCompressed[ opParam ]; + } + + return ip; +} + +#endif + +//////////////////////////////////////////////////////////////////////////////////////////////////// +#define LOOKUP_ELEMENT(idx,tblName,tblNameUC) \ + const CLR_RECORD_##tblNameUC* p = Get##tblName( idx ) + +#define LOOKUP_ELEMENT_REF(idx,tblName,tblNameUC,tblName2) \ + const CLR_RECORD_##tblNameUC* p = Get##tblName( idx );\ + const CLR_RT_##tblName2##_Index* s = &m_pCrossReference_##tblName[ idx ].m_target; if(s->m_data == 0) s = NULL + +#define LOOKUP_ELEMENT_IDX(idx,tblName,tblNameUC) \ + const CLR_RECORD_##tblNameUC* p = Get##tblName( idx );\ + CLR_RT_##tblName##_Index s; s.Set( m_idx, idx ) + +#if defined(NANOCLR_TRACE_INSTRUCTIONS) + +void CLR_RT_Assembly::DumpToken( CLR_UINT32 tk ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + CLR_UINT32 idx = CLR_DataFromTk( tk ); + + switch(CLR_TypeFromTk(tk)) + { + case TBL_AssemblyRef: { LOOKUP_ELEMENT ( idx, AssemblyRef, ASSEMBLYREF ); { CLR_Debug::Printf( "[%s]" , GetString( p->name ) ); } break; } + case TBL_TypeRef : { LOOKUP_ELEMENT_REF( idx, TypeRef , TYPEREF , TypeDef ); if(s) { CLR_RT_DUMP::TYPE ( *s ); } else { CLR_Debug::Printf( "%s.%s", GetString( p->nameSpace ), GetString( p->name ) ); } break; } + case TBL_FieldRef : { LOOKUP_ELEMENT_REF( idx, FieldRef , FIELDREF , FieldDef ); if(s) { CLR_RT_DUMP::FIELD ( *s ); } else { CLR_Debug::Printf( "%s" , GetString( p->name ) ); } break; } + case TBL_MethodRef : { LOOKUP_ELEMENT_REF( idx, MethodRef , METHODREF , MethodDef); if(s) { CLR_RT_DUMP::METHOD( *s ); } else { CLR_Debug::Printf( "%s" , GetString( p->name ) ); } break; } + case TBL_TypeDef : { LOOKUP_ELEMENT_IDX( idx, TypeDef , TYPEDEF ); CLR_RT_DUMP::TYPE ( s ); break; } + case TBL_FieldDef : { LOOKUP_ELEMENT_IDX( idx, FieldDef , FIELDDEF ); CLR_RT_DUMP::FIELD ( s ); break; } + case TBL_MethodDef : { LOOKUP_ELEMENT_IDX( idx, MethodDef , METHODDEF ); CLR_RT_DUMP::METHOD( s ); break; } + case TBL_Strings : { const char* p = GetString( idx ); CLR_Debug::Printf( "'%s'" , p ); break; } + + default: + CLR_Debug::Printf( "[%08x]", tk ); + } +} + +void CLR_RT_Assembly::DumpSignature( CLR_SIG sig ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + const CLR_UINT8* p = GetSignature( sig ); + CLR_UINT32 len; + + CLR_CorCallingConvention cc = (CLR_CorCallingConvention)*p++; + + switch(cc & PIMAGE_CEE_CS_CALLCONV_MASK) + { + case PIMAGE_CEE_CS_CALLCONV_FIELD: + CLR_Debug::Printf( "FIELD " ); + DumpSignature( p ); + break; + + case PIMAGE_CEE_CS_CALLCONV_LOCAL_SIG: + break; + + case PIMAGE_CEE_CS_CALLCONV_DEFAULT: + len = *p++; + + CLR_Debug::Printf( "METHOD " ); + DumpSignature( p ); + CLR_Debug::Printf( "(" ); + + while(len-- > 0) + { + CLR_Debug::Printf( " " ); + DumpSignature( p ); + if(len) CLR_Debug::Printf( "," ); + else CLR_Debug::Printf( " " ); + } + CLR_Debug::Printf( ")" ); + break; + } +} + +void CLR_RT_Assembly::DumpSignature( const CLR_UINT8*& p ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + CLR_DataType opt = CLR_UncompressElementType( p ); + + switch(opt) + { + case DATATYPE_VOID : CLR_Debug::Printf( "VOID" ); break; + case DATATYPE_BOOLEAN : CLR_Debug::Printf( "BOOLEAN" ); break; + case DATATYPE_CHAR : CLR_Debug::Printf( "char" ); break; + case DATATYPE_I1 : CLR_Debug::Printf( "I1" ); break; + case DATATYPE_U1 : CLR_Debug::Printf( "U1" ); break; + case DATATYPE_I2 : CLR_Debug::Printf( "I2" ); break; + case DATATYPE_U2 : CLR_Debug::Printf( "U2" ); break; + case DATATYPE_I4 : CLR_Debug::Printf( "I4" ); break; + case DATATYPE_U4 : CLR_Debug::Printf( "U4" ); break; + case DATATYPE_I8 : CLR_Debug::Printf( "I8" ); break; + case DATATYPE_U8 : CLR_Debug::Printf( "U8" ); break; + case DATATYPE_R4 : CLR_Debug::Printf( "R4" ); break; + case DATATYPE_R8 : CLR_Debug::Printf( "R8" ); break; + case DATATYPE_STRING : CLR_Debug::Printf( "STRING" ); break; + case DATATYPE_BYREF : CLR_Debug::Printf( "BYREF " ); DumpSignature ( p ); break; + case DATATYPE_VALUETYPE : CLR_Debug::Printf( "VALUETYPE " ); DumpSignatureToken( p ); break; + case DATATYPE_CLASS : CLR_Debug::Printf( "CLASS " ); DumpSignatureToken( p ); break; + case DATATYPE_OBJECT : CLR_Debug::Printf( "OBJECT" ); break; + case DATATYPE_SZARRAY : CLR_Debug::Printf( "SZARRAY " ); DumpSignature ( p ); break; + + default : CLR_Debug::Printf( "[UNKNOWN: %08x]", opt ); break; + } + +} + +void CLR_RT_Assembly::DumpSignatureToken( const CLR_UINT8*& p ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + CLR_UINT32 tk = CLR_TkFromStream( p ); + + CLR_Debug::Printf( "[%08x]", tk ); +} + +//--// + +void CLR_RT_Assembly::DumpOpcode( CLR_RT_StackFrame* stack, CLR_PMETADATA ip ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + if(s_CLR_RT_fTrace_Instructions < c_CLR_RT_Trace_Info) return; + + CLR_RT_MethodDef_Instance inst; + + if(s_CLR_RT_fTrace_Instructions >= c_CLR_RT_Trace_Verbose) + { + inst = stack->m_call; + } + else + { + inst.Clear(); + } + + DumpOpcodeDirect( inst, ip, stack->m_IPstart, stack->m_owningThread->m_pid ); +} + +void CLR_RT_Assembly::DumpOpcodeDirect( CLR_RT_MethodDef_Instance& call, CLR_PMETADATA ip, CLR_PMETADATA ipStart, int pid ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + CLR_Debug::Printf( " [%04x:%04x:%08x", pid, (int)(ip - ipStart), (size_t)ip ); + + if(NANOCLR_INDEX_IS_VALID(call)) + { + CLR_Debug::Printf( ":" ); + CLR_RT_DUMP::METHOD( call ); + } + + CLR_OPCODE op = CLR_ReadNextOpcodeCompressed( ip ); + CLR_OpcodeParam opParam = c_CLR_RT_OpcodeLookup[ op ].m_opParam; + + CLR_Debug::Printf( "] %-12s", c_CLR_RT_OpcodeLookup[ op ].m_name ); + + if(IsOpParamToken( opParam )) + { + DumpToken( CLR_ReadTokenCompressed( ip, op ) ); + } + else + { + CLR_UINT32 argLo; + CLR_UINT32 argHi; + + switch(c_CLR_opParamSizeCompressed[ opParam ]) + { + case 8: NANOCLR_READ_UNALIGNED_UINT32( argLo, ip ); NANOCLR_READ_UNALIGNED_UINT32( argHi, ip ); CLR_Debug::Printf( "%08X,%08X", argHi, argLo ); break; + case 4: NANOCLR_READ_UNALIGNED_UINT32( argLo, ip ); CLR_Debug::Printf( "%08X" , argLo ); break; + case 2: NANOCLR_READ_UNALIGNED_UINT16( argLo, ip ); CLR_Debug::Printf( "%04X" , argLo ); break; + case 1: NANOCLR_READ_UNALIGNED_UINT8 ( argLo, ip ); CLR_Debug::Printf( "%02X" , argLo ); break; + } + } + + CLR_Debug::Printf( "\r\n" ); +} + +#endif // defined(NANOCLR_TRACE_INSTRUCTIONS) + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#if defined(NANOCLR_TRACE_ERRORS) + +void CLR_RT_DUMP::TYPE( const CLR_RT_TypeDef_Index& cls ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + char rgBuffer[ 512 ]; + char* szBuffer = rgBuffer; + size_t iBuffer = MAXSTRLEN(rgBuffer); + + g_CLR_RT_TypeSystem.BuildTypeName( cls, szBuffer, iBuffer ); rgBuffer[ MAXSTRLEN(rgBuffer) ] = 0; + + CLR_Debug::Printf( "%s", rgBuffer ); +} + +void CLR_RT_DUMP::TYPE( const CLR_RT_ReflectionDef_Index& reflex ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + CLR_RT_TypeDef_Instance inst; + CLR_UINT32 levels; + + if(inst.InitializeFromReflection( reflex, &levels )) + { + CLR_RT_DUMP::TYPE( inst ); + + while(levels-- > 0) + { + CLR_Debug::Printf( "[]" ); + } + } +} + +void CLR_RT_DUMP::METHOD( const CLR_RT_MethodDef_Index& method ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + char rgBuffer[ 512 ]; + char* szBuffer = rgBuffer; + size_t iBuffer = MAXSTRLEN(rgBuffer); + + g_CLR_RT_TypeSystem.BuildMethodName( method, szBuffer, iBuffer ); + + CLR_Debug::Printf( "%s", rgBuffer ); +} + +void CLR_RT_DUMP::FIELD( const CLR_RT_FieldDef_Index& field ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + char rgBuffer[ 512 ]; + char* szBuffer = rgBuffer; + size_t iBuffer = MAXSTRLEN(rgBuffer); + + g_CLR_RT_TypeSystem.BuildFieldName( field, szBuffer, iBuffer ); + + CLR_Debug::Printf( "%s", rgBuffer ); +} + +void CLR_RT_DUMP::OBJECT( CLR_RT_HeapBlock* ptr, const char* text ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + #define PELEMENT_TO_STRING(elem) case DATATYPE_##elem: CLR_Debug::Printf( "%s", #elem ); break + + CLR_Debug::Printf( "%s - ", text ); + + while(ptr->DataType() == DATATYPE_OBJECT && ptr->Dereference()) + { + ptr = ptr->Dereference(); + + CLR_Debug::Printf( "PTR " ); + } + + CLR_Debug::Printf( "%04x blocks at %08x [%02x] ", ptr->DataSize(), (int)(size_t)ptr, ptr->DataType() ); + + switch(ptr->DataType()) + { + case DATATYPE_CLASS: + case DATATYPE_VALUETYPE: + { + CLR_RT_DUMP::TYPE( ptr->ObjectCls() ); + } + break; + + case DATATYPE_STRING: + { + CLR_Debug::Printf( "'%s'", ptr->StringText() ); + } + break; + + case DATATYPE_SZARRAY: + { + CLR_RT_HeapBlock_Array* array = (CLR_RT_HeapBlock_Array*)ptr; + + CLR_RT_DUMP::TYPE( array->ReflectionData() ); + } + break; + + case DATATYPE_DELEGATE_HEAD: + { + CLR_RT_HeapBlock_Delegate* dlg = (CLR_RT_HeapBlock_Delegate*)ptr; + + CLR_RT_DUMP::METHOD( dlg->DelegateFtn() ); + } + break; + + + PELEMENT_TO_STRING(BOOLEAN); + PELEMENT_TO_STRING(CHAR ); + PELEMENT_TO_STRING(I1 ); + PELEMENT_TO_STRING(U1 ); + PELEMENT_TO_STRING(I2 ); + PELEMENT_TO_STRING(U2 ); + PELEMENT_TO_STRING(I4 ); + PELEMENT_TO_STRING(U4 ); + PELEMENT_TO_STRING(I8 ); + PELEMENT_TO_STRING(U8 ); + PELEMENT_TO_STRING(R4 ); + PELEMENT_TO_STRING(R8 ); + + PELEMENT_TO_STRING(FREEBLOCK ); + PELEMENT_TO_STRING(CACHEDBLOCK ); + PELEMENT_TO_STRING(ASSEMBLY ); + PELEMENT_TO_STRING(WEAKCLASS ); + PELEMENT_TO_STRING(REFLECTION ); + PELEMENT_TO_STRING(ARRAY_BYREF ); + PELEMENT_TO_STRING(DELEGATELIST_HEAD ); + PELEMENT_TO_STRING(OBJECT_TO_EVENT ); + PELEMENT_TO_STRING(BINARY_BLOB_HEAD ); + + PELEMENT_TO_STRING(THREAD ); + PELEMENT_TO_STRING(SUBTHREAD ); + PELEMENT_TO_STRING(STACK_FRAME ); + PELEMENT_TO_STRING(TIMER_HEAD ); + PELEMENT_TO_STRING(LOCK_HEAD ); + PELEMENT_TO_STRING(LOCK_OWNER_HEAD ); + PELEMENT_TO_STRING(LOCK_REQUEST_HEAD ); + PELEMENT_TO_STRING(WAIT_FOR_OBJECT_HEAD ); + PELEMENT_TO_STRING(FINALIZER_HEAD ); + PELEMENT_TO_STRING(MEMORY_STREAM_HEAD ); + PELEMENT_TO_STRING(MEMORY_STREAM_DATA ); + + default: + // the remaining data types aren't to be handled + break; + } + + CLR_Debug::Printf( "\r\n" ); + + #undef PELEMENT_TO_STRING +} + +#endif // defined(NANOCLR_TRACE_ERRORS) + +//--// + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#if defined(NANOCLR_TRACE_EXCEPTIONS) + +void CLR_RT_DUMP::EXCEPTION( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock& ref ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + const char* msg; + + CLR_RT_HeapBlock* obj = Library_corlib_native_System_Exception::GetTarget( ref ); if(!obj) return; + + CLR_Debug::Printf( " ++++ Exception " ); CLR_RT_DUMP::TYPE( obj->ObjectCls() ); CLR_Debug::Printf( " - %s (%d) ++++\r\n", CLR_RT_DUMP::GETERRORMESSAGE( Library_corlib_native_System_Exception::GetHResult( obj ) ), stack.m_owningThread->m_pid ); + + msg = Library_corlib_native_System_Exception::GetMessage( obj ); + + CLR_Debug::Printf( " ++++ Message: %s\r\n", msg == NULL ? "" : msg ); + + CLR_UINT32 depth; + Library_corlib_native_System_Exception::StackTrace* stackTrace = Library_corlib_native_System_Exception::GetStackTrace( obj, depth ); if(!stackTrace) return; + + while(depth-- > 0) + { + CLR_Debug::Printf( " ++++ " ); CLR_RT_DUMP::METHOD( stackTrace->m_md ); CLR_Debug::Printf( " [IP: %04x] ++++\r\n", stackTrace->m_IP ); + + stackTrace++; + } +} + +void CLR_RT_DUMP::POST_PROCESS_EXCEPTION( CLR_RT_HeapBlock& ref ) +{ + (void)ref; +} + +const char* CLR_RT_DUMP::GETERRORMESSAGE( HRESULT hrError ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +#define CASE_HRESULT_TO_STRING(hr) case hr: return #hr + switch(hrError) + { + CASE_HRESULT_TO_STRING(CLR_E_UNKNOWN_INSTRUCTION); + CASE_HRESULT_TO_STRING(CLR_E_UNSUPPORTED_INSTRUCTION); + CASE_HRESULT_TO_STRING(CLR_E_STACK_OVERFLOW); + CASE_HRESULT_TO_STRING(CLR_E_STACK_UNDERFLOW); + CASE_HRESULT_TO_STRING(CLR_E_ENTRY_NOT_FOUND); + CASE_HRESULT_TO_STRING(CLR_E_ASSM_WRONG_CHECKSUM); + CASE_HRESULT_TO_STRING(CLR_E_ASSM_PATCHING_NOT_SUPPORTED); + CASE_HRESULT_TO_STRING(CLR_E_SHUTTING_DOWN); + CASE_HRESULT_TO_STRING(CLR_E_OBJECT_DISPOSED); + CASE_HRESULT_TO_STRING(CLR_E_WATCHDOG_TIMEOUT); + CASE_HRESULT_TO_STRING(CLR_E_NULL_REFERENCE); + CASE_HRESULT_TO_STRING(CLR_E_WRONG_TYPE); + CASE_HRESULT_TO_STRING(CLR_E_TYPE_UNAVAILABLE); + CASE_HRESULT_TO_STRING(CLR_E_INVALID_CAST); + CASE_HRESULT_TO_STRING(CLR_E_OUT_OF_RANGE); + CASE_HRESULT_TO_STRING(CLR_E_SERIALIZATION_VIOLATION); + CASE_HRESULT_TO_STRING(CLR_E_SERIALIZATION_BADSTREAM); + CASE_HRESULT_TO_STRING(CLR_E_DIVIDE_BY_ZERO); + CASE_HRESULT_TO_STRING(CLR_E_BUSY); + CASE_HRESULT_TO_STRING(CLR_E_PROCESS_EXCEPTION); + CASE_HRESULT_TO_STRING(CLR_E_THREAD_WAITING); + CASE_HRESULT_TO_STRING(CLR_E_LOCK_SYNCHRONIZATION_EXCEPTION); + CASE_HRESULT_TO_STRING(CLR_E_APPDOMAIN_EXITED); + CASE_HRESULT_TO_STRING(CLR_E_APPDOMAIN_MARSHAL_EXCEPTION); + CASE_HRESULT_TO_STRING(CLR_E_UNKNOWN_TYPE); + CASE_HRESULT_TO_STRING(CLR_E_ARGUMENT_NULL); + CASE_HRESULT_TO_STRING(CLR_E_IO); + CASE_HRESULT_TO_STRING(CLR_E_ENTRYPOINT_NOT_FOUND); + CASE_HRESULT_TO_STRING(CLR_E_DRIVER_NOT_REGISTERED); + CASE_HRESULT_TO_STRING(CLR_E_PIN_UNAVAILABLE); + CASE_HRESULT_TO_STRING(CLR_E_PIN_DEAD); + CASE_HRESULT_TO_STRING(CLR_E_INVALID_OPERATION); + CASE_HRESULT_TO_STRING(CLR_E_WRONG_INTERRUPT_TYPE); + CASE_HRESULT_TO_STRING(CLR_E_NO_INTERRUPT); + CASE_HRESULT_TO_STRING(CLR_E_DISPATCHER_ACTIVE); + CASE_HRESULT_TO_STRING(CLR_E_FILE_IO); + CASE_HRESULT_TO_STRING(CLR_E_INVALID_DRIVER); + CASE_HRESULT_TO_STRING(CLR_E_FILE_NOT_FOUND); + CASE_HRESULT_TO_STRING(CLR_E_DIRECTORY_NOT_FOUND); + CASE_HRESULT_TO_STRING(CLR_E_VOLUME_NOT_FOUND); + CASE_HRESULT_TO_STRING(CLR_E_PATH_TOO_LONG); + CASE_HRESULT_TO_STRING(CLR_E_DIRECTORY_NOT_EMPTY); + CASE_HRESULT_TO_STRING(CLR_E_UNAUTHORIZED_ACCESS); + CASE_HRESULT_TO_STRING(CLR_E_PATH_ALREADY_EXISTS); + CASE_HRESULT_TO_STRING(CLR_E_TOO_MANY_OPEN_HANDLES); + CASE_HRESULT_TO_STRING(CLR_E_NOT_SUPPORTED); + CASE_HRESULT_TO_STRING(CLR_E_RESCHEDULE); + CASE_HRESULT_TO_STRING(CLR_E_OUT_OF_MEMORY); + CASE_HRESULT_TO_STRING(CLR_E_RESTART_EXECUTION); + CASE_HRESULT_TO_STRING(CLR_E_TIMEOUT); + CASE_HRESULT_TO_STRING(CLR_E_FAIL); + //--// + CASE_HRESULT_TO_STRING(CLR_S_THREAD_EXITED); + CASE_HRESULT_TO_STRING(CLR_S_QUANTUM_EXPIRED); + CASE_HRESULT_TO_STRING(CLR_S_NO_READY_THREADS); + CASE_HRESULT_TO_STRING(CLR_S_NO_THREADS); + CASE_HRESULT_TO_STRING(CLR_S_RESTART_EXECUTION); + } +#undef CASE_HRESULT_TO_STRING + + static char s_tmp[ 32 ]; + + snprintf( s_tmp, MAXSTRLEN(s_tmp), "0x%08x", hrError ); + + return s_tmp; +} + +#if defined(_WIN32) +const char* CLR_RT_DUMP::GETERRORDETAIL() +{ + return s_messageString.c_str(); +} +#endif + +#endif // defined(NANOCLR_TRACE_EXCEPTIONS) + +//--// + diff --git a/source/native/nf-interpreter/src/CLR/Diagnostics/Profile.cpp b/source/native/nf-interpreter/src/CLR/Diagnostics/Profile.cpp new file mode 100644 index 00000000..0d63a9de --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Diagnostics/Profile.cpp @@ -0,0 +1,268 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Diagnostics.h" + +//--// + +#if defined(NANOCLR_PROFILE_NEW_CALLS) + +void* CLR_PROF_CounterCallChain::Prepare( CLR_PROF_Handler* handler ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + if(m_owningHandler) + { + CLR_UINT64 t = handler->GetFrozenTime() - m_owningHandler->m_time_start; + + Complete( t, m_owningHandler ); + + handler->m_target_Mode = CLR_PROF_Handler::c_Mode_Ignore; + + return NULL; + } + else + { + m_owningHandler = handler; + + handler->m_target_Mode = CLR_PROF_Handler::c_Mode_CallChain; + + return this; + } +} + +void CLR_PROF_CounterCallChain::Complete( CLR_UINT64& t, CLR_PROF_Handler* handler ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + if(m_owningHandler) + { + m_time_exclusive += t; + + m_owningHandler->m_target = NULL; + m_owningHandler = NULL; + } +} + +void CLR_PROF_CounterCallChain::Enter( CLR_RT_StackFrame* stack ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + CLR_PROF_Handler::SuspendTime(); + + NANOCLR_CLEAR(*this); + + m_owningStackFrame = stack; + + CLR_PROF_Handler::ResumeTime(); +} + +void CLR_PROF_CounterCallChain::Leave() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + CLR_PROF_Handler::SuspendTime(); + CLR_PROF_Handler::ResumeTime(); +} + +#endif + +//--// + +#if defined(NANOCLR_PROFILE_HANDLER) + + bool CLR_PROF_Handler::s_initialized; + CLR_PROF_Handler* CLR_PROF_Handler::s_current; +volatile CLR_UINT64 CLR_PROF_Handler::s_time_overhead; +volatile CLR_UINT64 CLR_PROF_Handler::s_time_freeze; +volatile CLR_UINT64 CLR_PROF_Handler::s_time_adjusted; + +//--// + + +// TODO: roll this entire function into the HAL so that +// hardware with a HighRes counter can be used, this +// implementation is easy enough to move to the HAL as +// a support function for systems with only a lowres +// counter +static CLR_UINT64 GetPerformanceCounter() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +#if defined(_WIN32) + return 0; // UNDONE: FIXME: return HAL_Windows_GetPerformanceTicks(); +#else + static CLR_UINT32 rollover = 0; + static CLR_UINT32 lastValue = 0; + + CLR_UINT32 value = ::PAL_PerformanceCounter(); + + if(lastValue > value) rollover++; + + lastValue = value; + + return ((CLR_UINT64)rollover << 32) | (CLR_UINT64)value; +#endif +} + +//--// + +void CLR_PROF_Handler::Constructor() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + SuspendTime(); + + m_target_Mode = c_Mode_Ignore; + + Init( NULL ); +} + +#if defined(NANOCLR_PROFILE_NEW_CALLS) +void CLR_PROF_Handler::Constructor( CLR_PROF_CounterCallChain& target ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + SuspendTime(); + + Init( target.Prepare( this ) ); +} +#endif + +void CLR_PROF_Handler::Destructor() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + SuspendTime(); + + CLR_UINT64 t = GetFrozenTime() - m_time_start; + + if(m_target_Mode == c_Mode_Ignore) + { + s_time_adjusted += t; + } + else + { + if(m_containing) + { + m_containing->m_time_correction += t; + } + + if(m_target) + { + switch(m_target_Mode) + { +#if defined(NANOCLR_PROFILE_NEW_CALLS) + case c_Mode_CallChain: ((CLR_PROF_CounterCallChain*)m_target)->Complete( t, this ); break; +#endif + } + } + } + + s_current = m_containing; + + ResumeTime(); +} + + +void CLR_PROF_Handler::Init( void* target ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + m_target = target; + m_containing = s_current; s_current = this; + + if(m_target) + { + if(m_containing && m_containing->m_target == NULL) + { + m_target = NULL; + } + } + + if(m_target == NULL) + { + m_target_Mode = c_Mode_Ignore; + } + + m_time_correction = 0; + m_time_start = ResumeTime(); +} + +static void TestCalibrate( CLR_PROF_CounterCallChain& cnt ) +{ + CLR_PROF_Handler c( cnt ); +} + +void CLR_PROF_Handler::Calibrate() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); +#if defined(PLATFORM_ARM) || defined(PLATFORM_ESP32) + const int c_training = 10; +#else + const int c_training = 1024; +#endif + + if(s_initialized) return; + + s_current = NULL; + s_time_overhead = 0; + s_time_freeze = 0; + s_time_adjusted = 0; + +#if defined(PLATFORM_ARM) || defined(PLATFORM_ESP32) + ::PAL_PerformanceCounter_Initialize(); +#endif + + int i; + CLR_PROF_CounterCallChain tmp; + + for(i=0; i 100 && i > c_training/2) + { + i--; + continue; + } + + s_time_overhead += diff; + } + + s_time_adjusted = GetPerformanceCounter(); + + s_initialized = true; +} + +void CLR_PROF_Handler::SuspendTime() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + s_time_freeze = GetPerformanceCounter(); +} + +CLR_UINT64 CLR_PROF_Handler::GetFrozenTime() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + return s_time_freeze - s_time_adjusted; +} + +CLR_UINT64 CLR_PROF_Handler::ResumeTime() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + CLR_UINT64 res = GetFrozenTime(); + + s_time_adjusted = (GetPerformanceCounter() - res) + s_time_overhead; + + return res; +} + +CLR_UINT64 CLR_PROF_Handler::ResumeTime( CLR_INT64 t ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + s_time_adjusted += t; + + return ResumeTime(); +} +#endif //defined(NANOCLR_PROFILE_HANDLER) + +//--// + diff --git a/source/native/nf-interpreter/src/CLR/Diagnostics/Profiler.cpp b/source/native/nf-interpreter/src/CLR/Diagnostics/Profiler.cpp new file mode 100644 index 00000000..d29473c1 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Diagnostics/Profiler.cpp @@ -0,0 +1,858 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "Diagnostics.h" + +#if defined(NANOCLR_PROFILE_NEW) + +CLR_PRF_Profiler g_CLR_PRF_Profiler; + +HRESULT CLR_PRF_Profiler::CreateInstance() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + NANOCLR_HEADER(); + + g_CLR_PRF_Profiler.m_packetSeqId = 0; + g_CLR_PRF_Profiler.m_stream = NULL; + g_CLR_PRF_Profiler.m_lastTimestamp = (CLR_UINT32)((CLR_UINT64)(HAL_Time_CurrentTime() + ((1ull << CLR_PRF_CMDS::Bits::TimestampShift) - 1)) + >> CLR_PRF_CMDS::Bits::TimestampShift); + g_CLR_PRF_Profiler.m_currentAssembly = 0; + g_CLR_PRF_Profiler.m_currentThreadPID = 0; + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_MemoryStream::CreateInstance(g_CLR_PRF_Profiler.m_stream, NULL, 0)); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_PRF_Profiler::DeleteInstance() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + return g_CLR_PRF_Profiler.Profiler_Cleanup(); +} + +HRESULT CLR_PRF_Profiler::Profiler_Cleanup() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + CLR_RT_HeapBlock_MemoryStream::DeleteInstance(m_stream); + return S_OK; +} + +void CLR_PRF_Profiler::SendMemoryLayout() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + //Send Memory Layout + m_stream->WriteBits( CLR_PRF_CMDS::c_Profiling_Memory_Layout, CLR_PRF_CMDS::Bits::CommandHeader ); + PackAndWriteBits( 0 ); + PackAndWriteBits(s_CLR_RT_Heap.m_size); + Stream_Send(); +} + +HRESULT CLR_PRF_Profiler::DumpHeap() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + NANOCLR_HEADER(); + + CLR_PROF_HANDLER_CALLCHAIN_VOID(perf); + + CLR_UINT32 heapSize = 0; + + if(CLR_EE_PRF_IS_NOT(Enabled)) { NANOCLR_SET_AND_LEAVE(S_OK); } + + { + //Send HeapDump Begin Marker + m_stream->WriteBits( CLR_PRF_CMDS::c_Profiling_HeapDump_Start, CLR_PRF_CMDS::Bits::CommandHeader ); + NANOCLR_CHECK_HRESULT(Stream_Send()); + } + + DumpRoots(); + + NANOCLR_FOREACH_NODE(CLR_RT_HeapCluster,hc,g_CLR_RT_ExecutionEngine.m_heap) + { + CLR_RT_HeapBlock_Node* ptr; + CLR_UINT32 size; + CLR_RT_HeapBlock_Node* end = hc->m_payloadEnd; + + for(ptr = hc->m_payloadStart, size = ptr->DataSize(); ptr < end; ptr+= size, size = ptr->DataSize()) + { + if(ptr->DataType() != DATATYPE_FREEBLOCK && ptr->DataType() != DATATYPE_CACHEDBLOCK) + { + heapSize += ptr->DataSize(); + } + DumpObject(ptr); + //Don't let the stream get too big. + NANOCLR_CHECK_HRESULT(Stream_Send()); + } + } + NANOCLR_FOREACH_NODE_END(); + + { + //Send HeapDump End Marker + m_stream->WriteBits( CLR_PRF_CMDS::c_Profiling_HeapDump_Stop, CLR_PRF_CMDS::Bits::CommandHeader ); + PackAndWriteBits( heapSize ); + NANOCLR_CHECK_HRESULT(Stream_Send()); + } + + NANOCLR_CLEANUP(); + + //Flush out all data we've collected. Stopping the device without informing the program is a bad idea. + Stream_Flush(); + + NANOCLR_CLEANUP_END(); +} + +HRESULT CLR_PRF_Profiler::DumpRoots() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + NANOCLR_HEADER(); + + //Root proto: + //8bits: CLR_PRF_CMDS::c_Profiling_HeapDump_Root + //32bits: Address of Root + //3bits: Source of Root: Finalizer, AppDomain, Assembly, Thread, Stack? + //Only when source is Stack??: 32bits: CLR_RT_MethodDef_Index + + //Iterate through all the finalizers + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Finalizer,fin,g_CLR_RT_ExecutionEngine.m_finalizersPending) + { + _ASSERTE(fin->m_object); + _ASSERTE(fin->m_object->DataType() != DATATYPE_FREEBLOCK); + _ASSERTE(fin->m_object->DataType() != DATATYPE_CACHEDBLOCK); + + DumpRoot(fin->m_object, CLR_PRF_CMDS::RootTypes::Root_Finalizer, 0, NULL); + } + NANOCLR_FOREACH_NODE_END(); + + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Finalizer,fin,g_CLR_RT_ExecutionEngine.m_finalizersAlive) + { + _ASSERTE(fin->m_object); + _ASSERTE(fin->m_object->DataType() != DATATYPE_FREEBLOCK); + _ASSERTE(fin->m_object->DataType() != DATATYPE_CACHEDBLOCK); + + DumpRoot(fin->m_object, CLR_PRF_CMDS::RootTypes::Root_Finalizer, 0, NULL); + } + NANOCLR_FOREACH_NODE_END(); + +#if defined(NANOCLR_APPDOMAINS) + //Iterate through all the appdomains + NANOCLR_FOREACH_NODE(CLR_RT_AppDomain,appDomain,g_CLR_RT_ExecutionEngine.m_appDomains) + { + DumpRoot(appDomain, CLR_PRF_CMDS::RootTypes::Root_AppDomain, 0, NULL); + } + NANOCLR_FOREACH_NODE_END(); +#endif + + //Iterate through all the assemblies. + NANOCLR_FOREACH_ASSEMBLY(g_CLR_RT_TypeSystem) + { + DumpRoot( pASSM, CLR_PRF_CMDS::RootTypes::Root_Assembly, 0, NULL ); + } + NANOCLR_FOREACH_ASSEMBLY_END(); + + { //Iterate through all threads. + CLR_RT_DblLinkedList* threadLists[ 2 ] = { &g_CLR_RT_ExecutionEngine.m_threadsReady, &g_CLR_RT_ExecutionEngine.m_threadsWaiting }; + for(int list = 0; list < 2; list++) + { + NANOCLR_FOREACH_NODE(CLR_RT_Thread,th,*threadLists[ list ]) + { + DumpRoot( th, CLR_PRF_CMDS::RootTypes::Root_Thread, 0, NULL ); + } + NANOCLR_FOREACH_NODE_END(); + } + } + + NANOCLR_CHECK_HRESULT(Stream_Send()); + + NANOCLR_NOCLEANUP(); +} + +void CLR_PRF_Profiler::DumpRoot( CLR_RT_HeapBlock* root, CLR_UINT32 type, CLR_UINT32 flags, CLR_RT_MethodDef_Index* source ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + m_stream->WriteBits( CLR_PRF_CMDS::c_Profiling_HeapDump_Root, CLR_PRF_CMDS::Bits::CommandHeader ); + DumpPointer( root ); + m_stream->WriteBits( type, CLR_PRF_CMDS::Bits::RootTypes ); + + _ASSERTE(!flags); + if(type == CLR_PRF_CMDS::RootTypes::Root_Stack) + { + PackAndWriteBits(*source); + } else { + _ASSERTE(source == NULL); + } +} + +void CLR_PRF_Profiler::DumpObject( CLR_RT_HeapBlock* ptr ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + //Object Proto: + // Free blocked and cached blocks are considered free memory and are not dumped. + // All other types: + // 8 bits - Profiling_HeapDump_Object + // 32 bit pointer + // 16 bit size + // 8 bit - DataType() const + // 32 bits are TypeDef info >>>> iff DataType == CLASSTYPE || DataType == VALUETYPE || DataType == SZARRAY <<<< + // 16 bits are Array Level info >>>> iff DataType == SZARRAY <<<< + // 1 bit - Reference Follows + // 0 - No more references. End of Packet + // 1 - 32-bit pointer to reference follows. Repeat. + + CLR_DataType dt = ptr->DataType(); + _ASSERTE(dt < DATATYPE_FIRST_INVALID); + _ASSERTE(sizeof(CLR_RT_HeapBlock) == 12); //HeapBlockObjectPacket in ProfilerPackets.cs assumes sizeof(CLR_RT_HeapBlock) == 12 + + if(dt != DATATYPE_FREEBLOCK && dt != DATATYPE_CACHEDBLOCK) + { + m_stream->WriteBits( CLR_PRF_CMDS::c_Profiling_HeapDump_Object, CLR_PRF_CMDS::Bits::CommandHeader ); + DumpPointer( ptr ); + PackAndWriteBits( ptr->DataSize() ); + m_stream->WriteBits( (CLR_UINT32)dt,CLR_PRF_CMDS::Bits::DataType ); + + switch(dt) + { + case DATATYPE_BOOLEAN: + case DATATYPE_I1: + case DATATYPE_U1: + case DATATYPE_CHAR: + case DATATYPE_I2: + case DATATYPE_U2: + case DATATYPE_I4: + case DATATYPE_U4: + case DATATYPE_R4: + case DATATYPE_I8: + case DATATYPE_U8: + case DATATYPE_R8: + case DATATYPE_DATETIME: + case DATATYPE_TIMESPAN: + case DATATYPE_STRING: + //Boxed primitives.. All are non-pointer types -- no references. + case DATATYPE_REFLECTION: + //Has a reference to an assembly, but it's unlikely to be the only thing keeping the assembly alive. + case DATATYPE_BINARY_BLOB_HEAD: + //Unknown/unmanaged data-type. No references. + case DATATYPE_SUBTHREAD: + //Owned by a DATATYPE_THREAD; Don't dump back-reference. + case DATATYPE_MEMORY_STREAM_DATA: + //No references at all -- usually, and when not, its a pointer to an externally shown character buffer used for deserialization. + case DATATYPE_IO_PORT: + //No references for normal GPIO; there is a structure for interrupts, but that doesn't seem to be stored on the managed heap. + case DATATYPE_TIMER_HEAD: + case DATATYPE_LOCK_OWNER_HEAD: + case DATATYPE_LOCK_REQUEST_HEAD: + case DATATYPE_SERIALIZER_DUPLICATE: + case DATATYPE_SERIALIZER_STATE: + //No unique forward-looking references. + break; + + case DATATYPE_OBJECT: + case DATATYPE_BYREF: + case DATATYPE_ARRAY_BYREF: +#if defined(NANOCLR_APPDOMAINS) + case DATATYPE_TRANSPARENT_PROXY: +#endif + { + DumpSingleReference( ptr ); + break; + } + + case DATATYPE_CLASS: + case DATATYPE_VALUETYPE: + { + CLR_RT_TypeDef_Index idx = ptr->ObjectCls(); + _ASSERTE(NANOCLR_INDEX_IS_VALID(idx)); + PackAndWriteBits( idx ); + DumpSingleReference( ptr->ObjectLock() ); + DumpListOfReferences( ptr + 1, ptr->DataSize() - 1 ); //All items in list should have DataSize() == 1 therefore ptr->DataSize() - 1 == number of items in list. + break; + } + + case DATATYPE_SZARRAY: + { + //Special case needed to dump out array data type and levels. + CLR_RT_HeapBlock_Array* array = (CLR_RT_HeapBlock_Array*)ptr; + + PackAndWriteBits( array->ReflectionDataConst().m_data.m_type ); + PackAndWriteBits( array->ReflectionDataConst().m_levels ); + + if(array->m_fReference) + { + DumpListOfReferences( (CLR_RT_HeapBlock*)array->GetFirstElement(), array->m_numOfElements ); + } + break; + } + + case DATATYPE_ASSEMBLY: + { + CLR_RT_Assembly* assembly = (CLR_RT_Assembly*)ptr; + DumpSingleReference( assembly->m_pFile ); +#if !defined(NANOCLR_APPDOMAINS) + DumpListOfReferences( assembly->m_pStaticFields, assembly->m_iStaticFields ); +#endif + break; + } + + case DATATYPE_WEAKCLASS: + { + CLR_RT_HeapBlock_WeakReference* wr = (CLR_RT_HeapBlock_WeakReference*)ptr; + DumpSingleReference( wr->m_targetDirect ); + break; + } + + case DATATYPE_DELEGATE_HEAD: + { + CLR_RT_HeapBlock_Delegate* dlg = (CLR_RT_HeapBlock_Delegate*)ptr; + DumpSingleReference( &dlg->m_object ); + break; + } + + case DATATYPE_DELEGATELIST_HEAD: + { + CLR_RT_HeapBlock_Delegate_List* dlgList = (CLR_RT_HeapBlock_Delegate_List*)ptr; + DumpListOfReferences( dlgList->GetDelegates(), dlgList->m_length ); + break; + } + + case DATATYPE_THREAD: + { + CLR_RT_Thread* th = (CLR_RT_Thread*)ptr; + + DumpSingleReference( th->m_dlg ); + DumpSingleReference( th->m_currentException.Dereference() ); + + for(int i=0; im_nestedExceptionsPos; i++) + { + CLR_RT_HeapBlock* except = th->m_nestedExceptions[ i ].m_exception; + _ASSERTE(!except || except->DataType() == DATATYPE_CLASS || except->DataType() == DATATYPE_OBJECT); + DumpSingleReference( except ); + } + + DumpListOfReferences( th->m_locks); + DumpSingleReference ( th->m_waitForObject ); + DumpListOfReferences( th->m_stackFrames ); + DumpListOfReferences( th->m_subThreads ); + break; + } + + case DATATYPE_STACK_FRAME: + { + CLR_RT_StackFrame* stack = (CLR_RT_StackFrame*)ptr; + DumpListOfReferences( stack->m_arguments, stack->m_call.m_target->numArgs ); + DumpListOfReferences( stack->m_locals , stack->m_call.m_target->numLocals ); + DumpListOfReferences( stack->m_evalStack, stack->TopValuePosition() ); + break; + } + + case DATATYPE_OBJECT_TO_EVENT: + { + CLR_RT_ObjectToEvent_Source* otes = (CLR_RT_ObjectToEvent_Source*)ptr; + DumpSingleReference( otes->m_eventPtr ); //The managed object should reference this obj, which references the event. + break; + } + + case DATATYPE_LOCK_HEAD: + { + //Object points to Lock Head, Thread points to Lock Head, Lock Head points to list of lock owners and requests + CLR_RT_HeapBlock_Lock* lock = (CLR_RT_HeapBlock_Lock*)ptr; + DumpListOfReferences( lock->m_owners ); + DumpListOfReferences( lock->m_requests ); + break; + } + + case DATATYPE_ENDPOINT_HEAD: + { + CLR_RT_HeapBlock_EndPoint* ep = (CLR_RT_HeapBlock_EndPoint*)ptr; + DumpListOfReferences( ep->m_messages ); + break; + } + + case DATATYPE_WAIT_FOR_OBJECT_HEAD: + { + CLR_RT_HeapBlock_WaitForObject* wfo = (CLR_RT_HeapBlock_WaitForObject*)ptr; + DumpListOfReferences(wfo->GetWaitForObjects(), wfo->m_cObjects); + break; + } + + case DATATYPE_FINALIZER_HEAD: + { + CLR_RT_HeapBlock_Finalizer* f = (CLR_RT_HeapBlock_Finalizer*)ptr; + DumpSingleReference( f->m_object ); + break; + } + + case DATATYPE_MEMORY_STREAM_HEAD: + { + CLR_RT_HeapBlock_MemoryStream* ms = (CLR_RT_HeapBlock_MemoryStream*)ptr; + DumpListOfReferences( ms->m_buffers ); + break; + } + + case DATATYPE_SERIALIZER_HEAD: + { + CLR_RT_BinaryFormatter* bf = (CLR_RT_BinaryFormatter*)ptr; + DumpSingleReference ( bf->m_stream ); + DumpListOfReferences( bf->m_duplicates ); + DumpListOfReferences( bf->m_states ); + break; + } + +#if defined(NANOCLR_APPDOMAINS) + case DATATYPE_APPDOMAIN_HEAD: + { + CLR_RT_AppDomain* appDomain = (CLR_RT_AppDomain*)ptr; + DumpListOfReferences( appDomain->m_appDomainAssemblies ); + DumpSingleReference ( appDomain->m_globalLock ); + DumpSingleReference ( appDomain->m_strName ); + DumpSingleReference ( appDomain->m_outOfMemoryException ); + break; + } + + case DATATYPE_APPDOMAIN_ASSEMBLY: + { + CLR_RT_AppDomainAssembly* appDomainAssembly = (CLR_RT_AppDomainAssembly*)ptr; + DumpListOfReferences( appDomainAssembly->m_pStaticFields, appDomainAssembly->m_assembly->m_iStaticFields ); + break; + } +#endif + + default: + _ASSERTE(false); + break; + } + DumpEndOfRefsList(); + } //if(dt != DATATYPE_FREEBLOCK && dt != DATATYPE_CACHEDBLOCK) +} + +CLR_RT_HeapBlock* CLR_PRF_Profiler::FindReferencedObject(CLR_RT_HeapBlock* ref) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + while(ref) + { + CLR_DataType dt = ref->DataType(); + switch(dt) + { + case DATATYPE_BYREF: + case DATATYPE_OBJECT: + ref = ref->Dereference(); + break; +#if defined(NANOCLR_APPDOMAINS) + case DATATYPE_TRANSPARENT_PROXY: + ref = ref->TransparentProxyDereference(); + break; +#endif + case DATATYPE_ARRAY_BYREF: + ref = ref->Array(); + default: + return ref; + } + } + return NULL; +} + +void CLR_PRF_Profiler::DumpEndOfRefsList() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + SendFalse(); +} + +void CLR_PRF_Profiler::DumpPointer(void* ptr) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + PackAndWriteBits( (CLR_UINT32)((CLR_UINT8*)ptr - s_CLR_RT_Heap.m_location) ); +} + +void CLR_PRF_Profiler::DumpSingleReference(CLR_RT_HeapBlock* ptr) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + ptr = FindReferencedObject(ptr); + if(ptr) + { + SendTrue(); + DumpPointer(ptr); + } +} + +void CLR_PRF_Profiler::DumpListOfReferences(CLR_RT_HeapBlock* firstItem, CLR_UINT16 count) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + CLR_RT_HeapBlock* ptr; + for(ptr = firstItem; count > 0; ptr += ptr->DataSize(), count--) + { + DumpSingleReference(ptr); + } +} + +void CLR_PRF_Profiler::DumpListOfReferences(CLR_RT_DblLinkedList& list) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_Node, ptr, list) + { + DumpSingleReference(ptr); + } + NANOCLR_FOREACH_NODE_END(); +} + +//--// + +void CLR_PRF_Profiler::Timestamp() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + //Send Profiling Timestamp + CLR_UINT32 time = (CLR_UINT32)((HAL_Time_CurrentTime() + ((CLR_UINT64)((1ull << CLR_PRF_CMDS::Bits::TimestampShift) - 1))) + >> CLR_PRF_CMDS::Bits::TimestampShift); + if(time > m_lastTimestamp) + { + m_stream->WriteBits(CLR_PRF_CMDS::c_Profiling_Timestamp, CLR_PRF_CMDS::Bits::CommandHeader); + PackAndWriteBits(time - m_lastTimestamp); + Stream_Send(); + m_lastTimestamp = time; + } +} + +//--// + +#if defined(NANOCLR_PROFILE_NEW_CALLS) +HRESULT CLR_PRF_Profiler::RecordContextSwitch(CLR_RT_Thread* nextThread) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + NANOCLR_HEADER(); + _ASSERTE(nextThread); + + CLR_PROF_HANDLER_CALLCHAIN_VOID(perf); + + if(CLR_EE_PRF_IS(Calls)) + { + Timestamp(); + m_stream->WriteBits( CLR_PRF_CMDS::c_Profiling_Calls_CtxSwitch, CLR_PRF_CMDS::Bits::CommandHeader ); + PackAndWriteBits( nextThread->m_pid ); + m_currentThreadPID = nextThread->m_pid; + NANOCLR_CHECK_HRESULT(Stream_Send()); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_PRF_Profiler::RecordFunctionCall(CLR_RT_Thread* th, CLR_RT_MethodDef_Index md) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + NANOCLR_HEADER(); + _ASSERTE(th); + + if(CLR_EE_PRF_IS(Calls)) + { + CLR_PROF_HANDLER_CALLCHAIN_VOID(perf); + + if(th->m_pid != m_currentThreadPID) + { + NANOCLR_CHECK_HRESULT(RecordContextSwitch( th )); + } + else + { + Timestamp(); + } + + _ASSERTE(th->m_pid == m_currentThreadPID); + + m_stream->WriteBits(CLR_PRF_CMDS::c_Profiling_Calls_Call, CLR_PRF_CMDS::Bits::CommandHeader); + + if(md.Assembly() == m_currentAssembly) + { + SendFalse(); + } + else + { + SendTrue(); + m_currentAssembly = md.Assembly(); + PackAndWriteBits(m_currentAssembly); + } + PackAndWriteBits(md.Method()); + NANOCLR_CHECK_HRESULT(Stream_Send()); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_PRF_Profiler::RecordFunctionReturn(CLR_RT_Thread* th, CLR_PROF_CounterCallChain& prof) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + NANOCLR_HEADER(); + _ASSERTE(th); + + if(CLR_EE_PRF_IS(Calls)) + { + CLR_PROF_HANDLER_CALLCHAIN_VOID(perf); + + if(th->m_pid != m_currentThreadPID) + { + NANOCLR_CHECK_HRESULT(RecordContextSwitch( th )); + } + else + { + Timestamp(); + } + + _ASSERTE(th->m_pid == m_currentThreadPID); + + m_stream->WriteBits(CLR_PRF_CMDS::c_Profiling_Calls_Return, CLR_PRF_CMDS::Bits::CommandHeader); + PackAndWriteBits((CLR_UINT32)(prof.m_time_exclusive >> CLR_PRF_CMDS::Bits::CallTimingShift)); + NANOCLR_CHECK_HRESULT(Stream_Send()); + } + + NANOCLR_NOCLEANUP(); +} +#endif + +//--// + +#if defined(NANOCLR_PROFILE_NEW_ALLOCATIONS) + +void CLR_PRF_Profiler::TrackObjectCreation( CLR_RT_HeapBlock* ptr ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + _ASSERTE(ptr); + if(CLR_EE_PRF_IS(Allocations)) + { + CLR_PROF_HANDLER_CALLCHAIN_VOID(perf); + + CLR_UINT8 dt = ptr->DataType(); + if(dt != DATATYPE_STACK_FRAME && dt != DATATYPE_BINARY_BLOB_HEAD) + { + Timestamp(); + m_stream->WriteBits( CLR_PRF_CMDS::c_Profiling_Allocs_Alloc, CLR_PRF_CMDS::Bits::CommandHeader ); + DumpPointer( ptr ); + PackAndWriteBits( ptr->DataSize() ); + m_stream->WriteBits( (CLR_UINT32)dt, CLR_PRF_CMDS::Bits::DataType ); + if(dt == DATATYPE_CLASS || dt == DATATYPE_VALUETYPE) + { + PackAndWriteBits( ptr->ObjectCls() ); + } + else if(dt == DATATYPE_SZARRAY) + { + CLR_RT_HeapBlock_Array* array = (CLR_RT_HeapBlock_Array*)ptr; + PackAndWriteBits( array->ReflectionDataConst().m_data.m_type ); + PackAndWriteBits( array->ReflectionDataConst().m_levels ); + } + Stream_Send(); + } + } +} + +void CLR_PRF_Profiler::TrackObjectDeletion( CLR_RT_HeapBlock* ptr ) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + _ASSERTE(ptr); + + if(CLR_EE_PRF_IS(Allocations)) + { + CLR_PROF_HANDLER_CALLCHAIN_VOID(perf); + + CLR_UINT8 dt = ptr->DataType(); + if(dt != DATATYPE_STACK_FRAME && dt != DATATYPE_CACHEDBLOCK ) + { + Timestamp(); + m_stream->WriteBits( CLR_PRF_CMDS::c_Profiling_Allocs_Delete, CLR_PRF_CMDS::Bits::CommandHeader ); + DumpPointer( ptr ); + Stream_Send(); + } + } +} + +void CLR_PRF_Profiler::TrackObjectRelocation() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + if(CLR_EE_PRF_IS(Allocations)) + { + CLR_PROF_HANDLER_CALLCHAIN_VOID(perf); + + CLR_RT_GarbageCollector::RelocationRegion* relocBlocks = g_CLR_RT_GarbageCollector.m_relocBlocks; + size_t relocCount = g_CLR_RT_GarbageCollector.m_relocCount; + + Timestamp(); + m_stream->WriteBits(CLR_PRF_CMDS::c_Profiling_Allocs_Relloc, CLR_PRF_CMDS::Bits::CommandHeader); + PackAndWriteBits(( CLR_UINT32)relocCount ); + + for(size_t i = 0; i < relocCount; i++) + { + DumpPointer( relocBlocks[ i ].m_start); + DumpPointer( relocBlocks[ i ].m_end ); + PackAndWriteBits( relocBlocks[i].m_offset ); + } + } +} + +void CLR_PRF_Profiler::RecordGarbageCollectionBegin() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + if(CLR_EE_PRF_IS(Allocations)) + { + CLR_PROF_HANDLER_CALLCHAIN_VOID(perf); + + Timestamp(); + m_stream->WriteBits( CLR_PRF_CMDS::c_Profiling_GarbageCollect_Begin, CLR_PRF_CMDS::Bits::CommandHeader ); + PackAndWriteBits( g_CLR_RT_GarbageCollector.m_freeBytes ); + Stream_Send(); + } +} + +void CLR_PRF_Profiler::RecordGarbageCollectionEnd() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + if(CLR_EE_PRF_IS(Allocations)) + { + CLR_PROF_HANDLER_CALLCHAIN_VOID(perf); + + Timestamp(); + m_stream->WriteBits( CLR_PRF_CMDS::c_Profiling_GarbageCollect_End, CLR_PRF_CMDS::Bits::CommandHeader ); + PackAndWriteBits( g_CLR_RT_GarbageCollector.m_freeBytes ); + Stream_Send(); + } +} + +void CLR_PRF_Profiler::RecordHeapCompactionBegin() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + if(CLR_EE_PRF_IS(Allocations)) + { + CLR_PROF_HANDLER_CALLCHAIN_VOID(perf); + + Timestamp(); + m_stream->WriteBits( CLR_PRF_CMDS::c_Profiling_HeapCompact_Begin, CLR_PRF_CMDS::Bits::CommandHeader ); + PackAndWriteBits( g_CLR_RT_GarbageCollector.m_freeBytes ); + Stream_Send(); + } +} + +void CLR_PRF_Profiler::RecordHeapCompactionEnd() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + if(CLR_EE_PRF_IS(Allocations)) + { + CLR_PROF_HANDLER_CALLCHAIN_VOID(perf); + + Timestamp(); + m_stream->WriteBits( CLR_PRF_CMDS::c_Profiling_HeapCompact_End, CLR_PRF_CMDS::Bits::CommandHeader ); + PackAndWriteBits( g_CLR_RT_GarbageCollector.m_freeBytes ); + Stream_Send(); + } +} + +#endif + +//--// + +void CLR_PRF_Profiler::SendTrue() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + m_stream->WriteBits( (CLR_UINT32)1, 1 ); +} + +void CLR_PRF_Profiler::SendFalse() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + m_stream->WriteBits( (CLR_UINT32)0, 1 ); +} + +void CLR_PRF_Profiler::PackAndWriteBits(CLR_UINT32 value) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + /* In three different scenarios tested, sending nibbles instead of bytes and 2-bit hunks resulted + * in the most efficiency over the wire. It also involves less code than 2-bit hunks that I expected to win, + * so that's the method used. + */ + _ASSERTE(sizeof(CLR_UINT32) == 4); + + const CLR_UINT32 SHIFT_PER_NIBBLE = 2; //2^2 = 4 bits per nibble + CLR_UINT32 nibbles = 1; + if( value & 0xF0000000) { nibbles = 8; } + else if(value & 0x0F000000) { nibbles = 7; } + else if(value & 0x00F00000) { nibbles = 6; } + else if(value & 0x000F0000) { nibbles = 5; } + else if(value & 0x0000F000) { nibbles = 4; } + else if(value & 0x00000F00) { nibbles = 3; } + else if(value & 0x000000F0) { nibbles = 2; } + + m_stream->WriteBits( nibbles - 1, CLR_PRF_CMDS::Bits::NibbleCount ); + m_stream->WriteBits( value, nibbles << SHIFT_PER_NIBBLE ); +} + +void CLR_PRF_Profiler::PackAndWriteBits(const CLR_RT_TypeDef_Index& typeDef) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + PackAndWriteBits( typeDef.Assembly() ); + PackAndWriteBits( typeDef.Type() ); +} + +void CLR_PRF_Profiler::PackAndWriteBits(const CLR_RT_MethodDef_Index& methodDef) +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + PackAndWriteBits( methodDef.Assembly() ); + PackAndWriteBits( methodDef.Method() ); +} + +//--// + +HRESULT CLR_PRF_Profiler::Stream_Send() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + NANOCLR_HEADER(); + + const int BUFFER_THRESHOLD_BYTES = CLR_RT_HeapBlock_MemoryStream::Buffer::c_PayloadSize * 2 / 3; + const int BUFFER_THRESHOLD_BITS = BUFFER_THRESHOLD_BYTES << 3; + + if(m_stream->BitsWritten() >= BUFFER_THRESHOLD_BITS) + { + NANOCLR_CHECK_HRESULT(Stream_Flush()); + } + //else { Stream isn't above threshold; allow to cache. } + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_PRF_Profiler::Stream_Flush() +{ + NATIVE_PROFILE_CLR_DIAGNOSTICS(); + NANOCLR_HEADER(); + + //These need to be paired; If this function is ever used to send multiple stream types, each should get their own packet sequence id. + const CLR_UINT32 messageType = CLR_DBG_Commands::c_Profiling_Stream; + + CLR_UINT8 buffer[ 2*sizeof(CLR_UINT16) + CLR_RT_HeapBlock_MemoryStream::Buffer::c_PayloadSize ]; + CLR_DBG_Commands::Profiling_Stream* packet = (CLR_DBG_Commands::Profiling_Stream*)buffer; + + NANOCLR_FOREACH_NODE(CLR_RT_HeapBlock_MemoryStream::Buffer, ptr, m_stream->m_buffers) + { + int payloadLength = ptr->m_length; + if(payloadLength > 0) + { + _ASSERTE(sizeof(ptr->m_payload) == CLR_RT_HeapBlock_MemoryStream::Buffer::c_PayloadSize); + + int bitLength = payloadLength * 8; + if(ptr == m_stream->m_current) + { + bitLength -= m_stream->m_avail; + } + + packet->m_bitLen = bitLength; + packet->m_seqId = m_packetSeqId++; + memcpy(&packet[ 1 ], ptr->m_payload, payloadLength); + + int packetLength = sizeof(CLR_DBG_Commands::Profiling_Stream) + payloadLength; + if(!CLR_EE_DBG_EVENT_SEND(messageType, packetLength, buffer, WP_Flags_c_NonCritical)) + { + _ASSERTE(false); + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + } + + //Don't go past the cursor. + if(ptr == m_stream->m_current) { break; } + } + NANOCLR_FOREACH_NODE_END(); + + m_stream->Reset(); + + NANOCLR_NOCLEANUP(); +} + +#endif //#if defined(NANOCLR_PROFILE_NEW) + diff --git a/source/native/nf-interpreter/src/CLR/Helpers/Base64/base64.c b/source/native/nf-interpreter/src/CLR/Helpers/Base64/base64.c new file mode 100644 index 00000000..7c07298a --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Helpers/Base64/base64.c @@ -0,0 +1,104 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) https://www.mycplus.com. All Rights Reserved. +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////////////////////// +// we are using the function declarations matching the mbedTLS ones BUT with weak attribute // +// if the image includes the mbedTLS, these will be replaced by the strong ones from there // +// thus there will be no duplicate code // +////////////////////////////////////////////////////////////////////////////////////////////// + +#include "base64.h" + +void build_decoding_table(char *decoding_table ) +{ + if(decoding_table != NULL) + { + for (int i = 0; i < 64; i++) + decoding_table[(unsigned char) base64_enc_map[i]] = i; + } +} + +__nfweak int mbedtls_base64_encode( + unsigned char *dst, + size_t dlen, + size_t *olen, + const unsigned char *src, size_t slen ) +{ + // parameter not used + (void)dlen; + + for (unsigned int i = 0, j = 0; i < slen;) + { + int octet_a = i < slen ? (unsigned char)src[i++] : 0; + int octet_b = i < slen ? (unsigned char)src[i++] : 0; + int octet_c = i < slen ? (unsigned char)src[i++] : 0; + + int triple = (octet_a << 0x10) + (octet_b << 0x08) + octet_c; + + dst[j++] = base64_enc_map[(triple >> 3 * 6) & 0x3F]; + dst[j++] = base64_enc_map[(triple >> 2 * 6) & 0x3F]; + dst[j++] = base64_enc_map[(triple >> 1 * 6) & 0x3F]; + dst[j++] = base64_enc_map[(triple >> 0 * 6) & 0x3F]; + } + + for (unsigned int i = 0; i < mod_table[slen % 3]; i++) + dst[*olen - 1 - i] = '='; + + // add terminator + dst[*olen] = 0; + + return 0; +} + +__nfweak int mbedtls_base64_decode( + unsigned char *dst, + size_t dlen, + size_t *olen, + const unsigned char *src, size_t slen ) +{ + // parameter not used + (void)dlen; + + char *decoding_table = (char*)platform_malloc(256); + + if (decoding_table == NULL) + { + // OK to return anything but 0 + // we are forced to use mbedTLS behaviour anyway + return -1; + } + + build_decoding_table(decoding_table); + + if (slen % 4 != 0) + { + // OK to return anything but 0 + // we are forced to use mbedTLS behaviour anyway + return -1; + } + + for (unsigned int i = 0, j = 0; i < slen;) { + + int sextet_a = src[i] == '=' ? 0 & i++ : decoding_table[src[i++]]; + int sextet_b = src[i] == '=' ? 0 & i++ : decoding_table[src[i++]]; + int sextet_c = src[i] == '=' ? 0 & i++ : decoding_table[src[i++]]; + int sextet_d = src[i] == '=' ? 0 & i++ : decoding_table[src[i++]]; + + int triple = (sextet_a << 3 * 6) + + (sextet_b << 2 * 6) + + (sextet_c << 1 * 6) + + (sextet_d << 0 * 6); + + if (j < *olen) dst[j++] = (triple >> 2 * 8) & 0xFF; + if (j < *olen) dst[j++] = (triple >> 1 * 8) & 0xFF; + if (j < *olen) dst[j++] = (triple >> 0 * 8) & 0xFF; + } + + // free table + platform_free(decoding_table); + + return( 0 ); +} diff --git a/source/native/nf-interpreter/src/CLR/Helpers/Base64/base64.h b/source/native/nf-interpreter/src/CLR/Helpers/Base64/base64.h new file mode 100644 index 00000000..03ab6e61 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Helpers/Base64/base64.h @@ -0,0 +1,46 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) ARM Limited. All Rights Reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef __BASE64_H__ +#define __BASE64_H__ + +#include +#include +#include + +////////////////////////////////////////////////////////////////////////////////////////////// +// we are using the function declarations matching the mbedTLS ones BUT with weak attribute // +// if the image includes the mbedTLS, these will be replaced by the strong ones from there // +// thus there will be no duplicate code // +////////////////////////////////////////////////////////////////////////////////////////////// + +#ifdef __cplusplus +extern "C" { +#endif + +int mbedtls_base64_encode( unsigned char *dst, size_t dlen, size_t *olen, + const unsigned char *src, size_t slen ); +int mbedtls_base64_decode( unsigned char *dst, size_t dlen, size_t *olen, + const unsigned char *src, size_t slen ); + +static const unsigned char base64_enc_map[64] = +{ + 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', + 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', + 'U', 'V', 'W', 'X', 'Y', 'Z', 'a', 'b', 'c', 'd', + 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', + 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', + 'y', 'z', '0', '1', '2', '3', '4', '5', '6', '7', + '8', '9', '+', '/' +}; + +static const unsigned int mod_table[3] = {0, 2, 1}; + +#ifdef __cplusplus +} +#endif + +#endif //__BASE64_H__ diff --git a/source/native/nf-interpreter/src/CLR/Helpers/TinyPrintf/printf.c b/source/native/nf-interpreter/src/CLR/Helpers/TinyPrintf/printf.c new file mode 100644 index 00000000..ab902bfc --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Helpers/TinyPrintf/printf.c @@ -0,0 +1,496 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2001, 2002 Georges Menie. All rights reserved. +// Portions Copyright (c) 2009-2013 Daniel D Miller. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "printf.h" + +// ASCII character set... +#define NUL 0x00 +#define STX 0x02 +#define ETX 0x03 +#define EOT 0x04 +#define ACK 0x06 +#define BS 0x08 +#define LF 0x0A +#define CR 0x0D +#define DLE 0x10 +#define ESC 0x1B +#define SPC 0x20 +#define MAX_PRN 0x7E +#define DEL 0x7F + +//extern int putchar (int c); + +static unsigned int use_leading_plus = 0 ; + +static int max_output_len = -1 ; +static int curr_output_len = 0 ; + +unsigned int fixed_overrun = 0 ; +int last_bad_char = 0 ; +unsigned int invalid_char = 0 ; + +static void printchar (char **str, int c) +{ + if (max_output_len >= 0 && curr_output_len >= max_output_len) { + fixed_overrun++ ; + return ; + } + + // check for overrun of our stuff_talkf[] buffer +// if (curr_output_len >= TALK_LINE_LEN) { +// fixed_overrun++ ; +// return ; +// } + if (c > MAX_PRN) { + invalid_char++ ; + last_bad_char = c ; + c = '?' ; + } else + if (c < SPC) { // ASCII 32 = Space + switch (c) { + case CR: + case LF: + case STX: + case ETX: + break; + + default: + invalid_char++ ; + last_bad_char = c ; + c = '?' ; + break; + } + } + + if (str) { + **str = (char) c; + ++(*str); + curr_output_len++ ; + } +} + +//**************************************************************************** +// This version returns the length of the output string. +// It is more useful when implementing a walking-string function. +//**************************************************************************** +static const double round_nums[8] = { + 0.5, + 0.05, + 0.005, + 0.0005, + 0.00005, + 0.000005, + 0.0000005, + 0.00000005 +}; + +static unsigned dbl2stri(char *outbfr, double dbl, unsigned dec_digits) +{ + static char local_bfr[128] ; + char *output = (outbfr == 0) ? local_bfr : outbfr ; + + //******************************************* + // extract negative info + //******************************************* + if (dbl < 0.0) { + *output++ = '-' ; + dbl *= -1.0 ; + } else { + if (use_leading_plus) { + *output++ = '+' ; + } + + } + + // handling rounding by adding .5LSB to the floating-point data + if (dec_digits < 8) { + dbl += round_nums[dec_digits] ; + } + + //************************************************************************** + // construct fractional multiplier for specified number of digits. + //************************************************************************** + unsigned long long mult = 1 ; + unsigned int idx ; + for (idx=0; idx < dec_digits; idx++) + mult *= 10 ; + + // printf("mult=%u\n", mult) ; + unsigned int wholeNum = (unsigned int) dbl ; + unsigned long long decimalNum = (unsigned long long) ((dbl - wholeNum) * mult); + + //******************************************* + // convert integer portion + //******************************************* + char tbfr[40] ; + idx = 0 ; + while (wholeNum != 0) { + tbfr[idx++] = '0' + (wholeNum % 10) ; + wholeNum /= 10 ; + } + // printf("%.3f: whole=%s, dec=%d\n", dbl, tbfr, decimalNum) ; + if (idx == 0) { + *output++ = '0' ; + } else { + while (idx > 0) { + *output++ = tbfr[idx-1] ; //lint !e771 + idx-- ; + } + } + if (dec_digits > 0) { + *output++ = '.' ; + + //******************************************* + // convert fractional portion + //******************************************* + idx = 0 ; + while (decimalNum != 0) { + tbfr[idx++] = '0' + (decimalNum % 10) ; + decimalNum /= 10 ; + } + // pad the decimal portion with 0s as necessary; + // We wouldn't want to report 3.093 as 3.93, would we?? + while (idx < dec_digits) { + tbfr[idx++] = '0' ; + } + // printf("decimal=%s\n", tbfr) ; + if (idx == 0) { + *output++ = '0' ; + } else { + while (idx > 0) { + *output++ = tbfr[idx-1] ; + idx-- ; + } + } + } + *output = 0 ; + + // prepare output + output = (outbfr == 0) ? local_bfr : outbfr ; + return strlen(output) ; +} + +//**************************************************************************** +#define PAD_RIGHT 1 +#define PAD_ZERO 2 + +static int prints (char **out, const char *string, int width, int pad) +{ + // [831326121984], width=0, pad=0 + // printf("[%s], width=%u, pad=%u\n", string, width, pad) ; + register int pc = 0, padchar = ' '; + if (width > 0) { + int len = 0; + const char *ptr; + for (ptr = string; *ptr; ++ptr) + ++len; + if (len >= width) + width = 0; + else + width -= len; + if (pad & PAD_ZERO) + padchar = '0'; + } + if (!(pad & PAD_RIGHT)) { + for (; width > 0; --width) { + printchar (out, padchar); + ++pc; + } + } + for (; *string; ++string) { + printchar (out, *string); + ++pc; + } + for (; width > 0; --width) { + printchar (out, padchar); + ++pc; + } + return pc; +} + +//**************************************************************************** +/* the following should be enough for 32 bit int */ +// -2,147,483,648 +#define PRINT_BUF_LEN 12 + +static int printi (char **out, int i, unsigned int base, int sign, int width, int pad, int letbase) +{ + char print_buf[PRINT_BUF_LEN]; + char *s; + int t, neg = 0, pc = 0; + unsigned u = (unsigned) i; + if (i == 0) { + print_buf[0] = '0'; + print_buf[1] = '\0'; + return prints (out, print_buf, width, pad); + } + if (sign && base == 10 && i < 0) { + neg = 1; + u = (unsigned) -i; + } + // make sure print_buf is NULL-term + s = print_buf + PRINT_BUF_LEN - 1; + *s = '\0'; + + while (u) { + t = u % base; //lint !e573 !e737 !e713 Warning 573: Signed-unsigned mix with divide + if (t >= 10) + t += letbase - '0' - 10; + *--s = (char) t + '0'; + u /= base; //lint !e573 !e737 Signed-unsigned mix with divide + } + if (neg) { + if (width && (pad & PAD_ZERO)) { + printchar (out, '-'); + ++pc; + --width; + } + else { + *--s = '-'; + } + } else { + if (use_leading_plus) { + *--s = '+'; + } + } + return pc + prints (out, s, width, pad); +} + +//**************************************************************************** +/* the following should be enough for 64 bit int, without commas */ +// _UI64_MAX +// Maximum value for a variable of type unsigned __int64 +// xx..xx..xx..xx.. +// 18446744073709551615 (0xffffffffffffffff) +// -9223372036854775808 +// 18,446,744,073,709,551,615 +#define PRINT_LLBUF_LEN 22 + +static int printlli (char **out, long long i, unsigned int base, int sign, int width, int pad, int letbase) +{ + char print_buf[PRINT_LLBUF_LEN]; + char *s; + int t, neg = 0, pc = 0; + unsigned long long u = (unsigned long long) i; + if (i == 0) { + print_buf[0] = '0'; + print_buf[1] = '\0'; + return prints (out, print_buf, width, pad); + } + if (sign && base == 10 && i < 0) { + neg = 1; + u = (unsigned long long) -i; + } + // make sure print_buf is NULL-term + s = print_buf + PRINT_LLBUF_LEN - 1; + *s = '\0'; + + while (u) { + t = u % base; //lint !e573 !e737 !e713 Warning 573: Signed-unsigned mix with divide + if (t >= 10) + t += letbase - '0' - 10; + *--s = (char) t + '0'; + u /= base; //lint !e573 !e737 Signed-unsigned mix with divide + } + if (neg) { + if (width && (pad & PAD_ZERO)) { + printchar (out, '-'); + ++pc; + --width; + } + else { + *--s = '-'; + } + } else { + if (use_leading_plus) { + *--s = '+'; + } + } + return pc + prints (out, s, width, pad); +} + +//**************************************************************************** +static int print (char **out, const char *format, va_list va) +{ + int post_decimal ; + int width, pad ; + unsigned dec_width = 6 ; + int pc = 0; + char scr[2]; + + use_leading_plus = 0 ; // start out with this clear + for (; *format != 0; ++format) { + if (*format == '%') { + dec_width = 6 ; + ++format; + width = pad = 0; + if (*format == '\0') + break; + if (*format == '%') + goto out_lbl; + if (*format == '-') { + ++format; + pad = PAD_RIGHT; + } + if (*format == '+') { + ++format; + use_leading_plus = 1 ; + } + while (*format == '0') { + ++format; + pad |= PAD_ZERO; + } + post_decimal = 0 ; + if (*format == '.' || + (*format >= '0' && *format <= '9')) { + + while (1) { + if (*format == '.') { + post_decimal = 1 ; + dec_width = 0 ; + format++ ; + } else if ((*format >= '0' && *format <= '9')) { + if (post_decimal) { + dec_width *= 10; + dec_width += (unsigned int) (char) (*format - '0'); + } else { + width *= 10; + width += *format - '0'; + } + format++ ; + } else { + break; + } + } + } + unsigned int use_longlong = 0 ; + if (*format == 'l') { + ++format; + if (*format == 'l') { + ++format; + use_longlong = 1 ; + } + } + switch (*format) { + case 's': + { + char *s = va_arg(va, char *); + pc += prints (out, s ? s : "(null)", width, pad); + use_leading_plus = 0 ; // reset this flag after printing one value + } + break; + case 'd': + if (use_longlong) { + pc += printlli(out, va_arg(va, long long), 10, 1, width, pad, 'a'); + } + else { + pc += printi (out, va_arg(va, int), 10, 1, width, pad, 'a'); + } + use_leading_plus = 0 ; // reset this flag after printing one value + break; + case 'x': + if (use_longlong) { + pc += printlli(out, va_arg(va, long long), 16, 0, width, pad, 'a'); + } + else { + pc += printi (out, va_arg(va, int), 16, 0, width, pad, 'a'); + } + use_leading_plus = 0 ; // reset this flag after printing one value + break; + case 'X': + if (use_longlong) { + pc += printlli(out, va_arg(va, long long), 16, 0, width, pad, 'A'); + } + else { + pc += printi (out, va_arg(va, int), 16, 0, width, pad, 'A'); + } + use_leading_plus = 0 ; // reset this flag after printing one value + break; + case 'p': + case 'u': + if (use_longlong) { + pc += printlli(out, va_arg(va, unsigned long long), 10, 0, width, pad, 'a'); + } + else { + pc += printi (out, va_arg(va, unsigned int), 10, 0, width, pad, 'a'); + } + use_leading_plus = 0 ; // reset this flag after printing one value + break; + case 'c': + /* char are converted to int then pushed on the stack */ + scr[0] = (char)va_arg(va, int); + scr[1] = '\0'; + pc += prints (out, scr, width, pad); + use_leading_plus = 0 ; // reset this flag after printing one value + break; + + case 'f': + { + char bfr[81] ; + dbl2stri(bfr, va_arg(va, double), dec_width) ; + // stuff_talkf("[%s], width=%u, dec_width=%u\n", bfr, width, dec_width) ; + pc += prints (out, bfr, width, pad); + use_leading_plus = 0 ; // reset this flag after printing one value + } + break; + + default: + printchar (out, '%'); + printchar (out, *format); + use_leading_plus = 0 ; // reset this flag after printing one value + break; + } + } else + // if (*format == '\\') { + // + // } else + { +out_lbl: + printchar (out, *format); + ++pc; + } + } // for each char in format string + if (out) //lint !e850 + **out = '\0'; + return pc; +} + +//**************************************************************************** +int tiny_sprintf (char *out, const char *format, ...) +{ + max_output_len = -1 ; + curr_output_len = 0 ; + + va_list va; + va_start(va,format); + int count = print (&out, format, va); + va_end(va); + + return count; +} + +//**************************************************************************** +int tiny_snprintf(char *out, unsigned int max_len, const char *format, ...) +{ + max_output_len = (int) max_len ; + curr_output_len = 0 ; + + va_list va; + va_start(va,format); + int count = print (&out, format, va); + va_end(va); + + return count; +} + +int tiny_vsnprintf(char *out, unsigned int max_len, const char *format, va_list va) +{ + max_output_len = (int) max_len; + curr_output_len = 0; + + return print(&out, format, va); +} diff --git a/source/native/nf-interpreter/src/CLR/Helpers/TinyPrintf/printf.h b/source/native/nf-interpreter/src/CLR/Helpers/TinyPrintf/printf.h new file mode 100644 index 00000000..4ff4c076 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Helpers/TinyPrintf/printf.h @@ -0,0 +1,32 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2001, 2002 Georges Menie. All rights reserved. +// Portions Copyright (c) 2009-2013 Daniel D Miller. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef __TFP_PRINTF__ +#define __TFP_PRINTF__ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +int tiny_sprintf (char *out, const char *format, ...); +int tiny_snprintf(char *out, unsigned int max_len, const char *format, ...); +int tiny_vsnprintf(char *out, unsigned int max_len, const char *format, va_list va); + +#ifdef __cplusplus +} +#endif + +// the defines below allow using the regular calls to sprintf +#define sprintf tiny_sprintf +#define snprintf tiny_snprintf +#define vsnprintf tiny_vsnprintf + +#endif diff --git a/source/native/nf-interpreter/src/CLR/Include/WireProtocol.h b/source/native/nf-interpreter/src/CLR/Include/WireProtocol.h new file mode 100644 index 00000000..6a69c753 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/WireProtocol.h @@ -0,0 +1,211 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIREPROTOCOL_H_ +#define _WIREPROTOCOL_H_ + +#include +#include +#include +#include +#include + +#if !defined(_WIN32) +#include +#endif + +#ifndef min +#define min(a,b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef ARRAYSIZE +#define ARRAYSIZE(x) (sizeof(x)/sizeof(x[0])) +#endif + +#define MARKER_DEBUGGER_V1 "NFDBGV1" // Used to identify the debugger at boot time. +#define MARKER_PACKET_V1 "NFPKTV1" // Used to identify the start of a packet. + +#ifndef WP_PACKET_SIZE +// no Wire Protocol defined at target_common, set to default as 1024 +#define WP_PACKET_SIZE 1024U +#endif + +// enum with Wire Protocol flags +// backwards compatible with .NETMF +typedef enum WP_Flags +{ + WP_Flags_c_NonCritical = 0x0001, // This doesn't need an acknowledge. + WP_Flags_c_Reply = 0x0002, // This is the result of a command. + WP_Flags_c_BadHeader = 0x0004, + WP_Flags_c_BadPayload = 0x0008, + WP_Flags_c_Spare0010 = 0x0010, + WP_Flags_c_Spare0020 = 0x0020, + WP_Flags_c_Spare0040 = 0x0040, + WP_Flags_c_Spare0080 = 0x0080, + WP_Flags_c_Spare0100 = 0x0100, + WP_Flags_c_Spare0200 = 0x0200, + WP_Flags_c_Spare0400 = 0x0400, + WP_Flags_c_Spare0800 = 0x0800, + WP_Flags_c_Spare1000 = 0x1000, + WP_Flags_c_NoCaching = 0x2000, + WP_Flags_c_NACK = 0x4000, + WP_Flags_c_ACK = 0x8000 +}WP_Flags; + +// enum with machine states for Wire Procotol receiver +typedef enum ReceiveState +{ + ReceiveState_Idle = (1 << 0), + ReceiveState_Initialize = (2 << 0), + ReceiveState_WaitingForHeader = (3 << 0), + ReceiveState_ReadingHeader = (4 << 0), + ReceiveState_CompleteHeader = (5 << 0), + ReceiveState_ReadingPayload = (6 << 0), + ReceiveState_CompletePayload = (7 << 0), +}ReceiveState; + +// enum with CLR monitor commands +// backwards compatible with .NETMF +typedef enum CLR_DBG_Commands_Monitor +{ + CLR_DBG_Commands_c_Monitor_Ping = 0x00000000, // The payload is empty, this command is used to let the other side know we are here... + CLR_DBG_Commands_c_Monitor_Message = 0x00000001, // The payload is composed of the string characters, no zero at the end. + CLR_DBG_Commands_c_Monitor_ReadMemory = 0x00000002, + CLR_DBG_Commands_c_Monitor_WriteMemory = 0x00000003, + CLR_DBG_Commands_c_Monitor_CheckMemory = 0x00000004, + CLR_DBG_Commands_c_Monitor_EraseMemory = 0x00000005, + CLR_DBG_Commands_c_Monitor_Execute = 0x00000006, + CLR_DBG_Commands_c_Monitor_Reboot = 0x00000007, + CLR_DBG_Commands_c_Monitor_MemoryMap = 0x00000008, + CLR_DBG_Commands_c_Monitor_ProgramExit = 0x00000009, // The payload is empty, this command is used to tell the PC of a program termination + CLR_DBG_Commands_c_Monitor_CheckSignature = 0x0000000A, + CLR_DBG_Commands_c_Monitor_DeploymentMap = 0x0000000B, + CLR_DBG_Commands_c_Monitor_FlashSectorMap = 0x0000000C, + CLR_DBG_Commands_c_Monitor_OemInfo = 0x0000000E, + CLR_DBG_Commands_c_Monitor_QueryConfiguration = 0x0000000F, + CLR_DBG_Commands_c_Monitor_UpdateConfiguration = 0x00000010, +}CLR_DBG_Commands_Monitor; + +// structure for Wire Protocol packet +// backwards compatible with .NETMF +typedef struct WP_Packet +{ + uint8_t m_signature[8]; + uint32_t m_crcHeader; + uint32_t m_crcData; + + uint32_t m_cmd; + uint16_t m_seq; + uint16_t m_seqReply; + uint32_t m_flags; + uint32_t m_size; +}WP_Packet; + +typedef struct WP_Controller +{ + uint8_t* m_szMarker; + + uint16_t m_lastOutboundMessage; + + bool (*AdvanceState)(void); + void (*Initialize)(void* szMarker, void* phy, void* app, void* state ); + //bool (*SendProtocolMessage)( const void* msg ); + bool (*SendProtocolMessage)( uint32_t cmd, uint32_t flags, uint32_t payloadSize, uint8_t* payload); + +}WP_Controller; + +// structure for Wire Protocol message +// backwards compatible with .NETMF equivalent in names and types to help code reuse +typedef struct WP_Message +{ + WP_Packet m_header; + uint8_t* m_payload; + + uint8_t* m_pos; + uint16_t m_size; + uint64_t m_payloadTicks; + int m_rxState; + + void (*Initialize)(WP_Controller* parent); + void (*PrepareReception)(void); + void (*PrepareRequest)(unsigned int cmd, unsigned int flags, unsigned int payloadSize, unsigned char* payload); + void (*PrepareReply)(const void** req, unsigned int flags, unsigned int payloadSize, unsigned char* payload); + void (*SetPayload)(unsigned char* payload); + void (*Release)(void); + bool (*Process)(void); + + bool (*VerifyHeader)(void); + bool (*VerifyPayload)(void); + void (*ReplyBadPacket)(unsigned int flags); + +}WP_Message; + + +// enum with flags for Monitor ping source and debugger flags +/////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Monitor_Ping (in debugger library code) !!! // +/////////////////////////////////////////////////////////////////////// +typedef enum Monitor_Ping_Source_Flags +{ + Monitor_Ping_c_Ping_Source_NanoCLR = 0x00010000, + Monitor_Ping_c_Ping_Source_NanoBooter = 0x00010001, + + Monitor_Ping_c_Ping_DbgFlag_Stop = 0x00000001, + Monitor_Ping_c_Ping_DbgFlag_AppExit = 0x00000004, + + // flags specific to Wire Protocol capabilities + Monitor_Ping_c_Ping_WPFlag_SupportsCRC32 = 0x00000010, + + // Wire Protocol packet size (3rd position) + Monitor_Ping_c_PacketSize_1024 = 0x00000100, + Monitor_Ping_c_PacketSize_0512 = 0x00000200, + Monitor_Ping_c_PacketSize_0256 = 0x00000300, + Monitor_Ping_c_PacketSize_0128 = 0x00000400, + +}Monitor_Ping_Source_Flags; + + +// structure to hold 'standard' version information +// equivalent with .NETMF MFVersion +typedef struct VersionInfo +{ + unsigned short usMajor; + unsigned short usMinor; + unsigned short usBuild; + unsigned short usRevision; + +}VersionInfo; + +// structure to hold nanoFramework release information +// equivalent with .NETMF MfReleaseInfo +typedef struct ReleaseInfo +{ + + VersionInfo version; + uint8_t InfoString[128]; + uint8_t TargetName[32]; + uint8_t PlatformName[32]; + +}ReleaseInfo; + +// structure for Wire Protocol command handler lookup +typedef struct CommandHandlerLookup +{ + // command code goes here + uint32_t command; + + // pointer to handler function + void* handler; + +}CommandHandlerLookup; + +// This structure is never used, its purpose is to generate a compiler error in case the size of any structure changes. +struct WP_CompileCheck +{ + char buf1[ sizeof(WP_Packet) == 8 * 4 ? 1 : -1 ]; +}; + +#endif // _WIREPROTOCOL_H_ diff --git a/source/native/nf-interpreter/src/CLR/Include/WireProtocol_App_Interface.h b/source/native/nf-interpreter/src/CLR/Include/WireProtocol_App_Interface.h new file mode 100644 index 00000000..fa3c1335 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/WireProtocol_App_Interface.h @@ -0,0 +1,20 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIREPROTOCOL_APP_INTERFACE_H_ +#define _WIREPROTOCOL_APP_INTERFACE_H_ + +#include "WireProtocol.h" + +////////////////////////////////////////// +extern uint8_t receptionBuffer[sizeof(WP_Packet) + WP_PACKET_SIZE]; +extern void ReplyToCommand(WP_Message* message, int fSuccess, int fCritical, void* ptr, int size); + +////////////////////////////////////////// +int WP_App_ProcessHeader(WP_Message* message); +int WP_App_ProcessPayload(WP_Message* message); + +#endif // _WIREPROTOCOL_APP_INTERFACE_H_ + diff --git a/source/native/nf-interpreter/src/CLR/Include/WireProtocol_HAL_Interface.h b/source/native/nf-interpreter/src/CLR/Include/WireProtocol_HAL_Interface.h new file mode 100644 index 00000000..9bcbb463 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/WireProtocol_HAL_Interface.h @@ -0,0 +1,17 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIREPROTOCOL_HAL_INTERFACE_H_ +#define _WIREPROTOCOL_HAL_INTERFACE_H_ + +#include "WireProtocol.h" + +////////////////////////////////////////// +int WP_ReceiveBytes(uint8_t* ptr, unsigned short* size); +int WP_TransmitMessage(WP_Message* message); +void WP_CheckAvailableIncomingData(); + +#endif // _WIREPROTOCOL_HAL_INTERFACE_H_ + diff --git a/source/native/nf-interpreter/src/CLR/Include/WireProtocol_Message.h b/source/native/nf-interpreter/src/CLR/Include/WireProtocol_Message.h new file mode 100644 index 00000000..703058b3 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/WireProtocol_Message.h @@ -0,0 +1,65 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIREPROTOCOL_MESSAGE_H_ +#define _WIREPROTOCOL_MESSAGE_H_ + +#include "WireProtocol.h" +#include "WireProtocol_App_Interface.h" +#include "WireProtocol_HAL_Interface.h" + +//////////////////////////////////////////////////////////////////////////////////////////////////// +#define TRACE_ERRORS 1 +#define TRACE_HEADERS 2 +#define TRACE_STATE 4 +#define TRACE_NODATA 8 + +#if TRACE_MASK != 0 +#define TRACE0( f, msg ) if((f) & TRACE_MASK ) debug_printf( msg ) +#define TRACE( f, msg, ...) if((f) & TRACE_MASK ) debug_printf( msg, __VA_ARGS__ ) +#else +#define TRACE0(msg,...) +#define TRACE(msg,...) +#endif + +//////////////////////////////////////////////////// +// function declarations (related with WP_Message) + +#ifdef __cplusplus +extern "C" { +#endif + +void WP_Message_Initialize(WP_Message* message); +void WP_Message_PrepareReception(WP_Message* message); +void WP_Message_PrepareRequest(WP_Message* message, uint32_t cmd, uint32_t flags, uint32_t payloadSize, uint8_t* payload); +void WP_Message_PrepareReply(WP_Message* message, const WP_Packet* req, uint32_t flags, uint32_t payloadSize, uint8_t* payload); +void WP_Message_SetPayload(WP_Message* message, uint8_t* payload); +void WP_Message_Release(WP_Message* message); +int WP_Message_VerifyHeader(WP_Message* message); +int WP_Message_VerifyPayload(WP_Message* message); +void WP_Message_ReplyBadPacket(uint32_t flags); +int WP_Message_Process(WP_Message* message); + +#ifdef __cplusplus +} +#endif + +////////////////////////////////////////// +// helper functions + +#ifdef __cplusplus +extern "C" { +#endif + +void WP_ReplyToCommand(WP_Message* message, int fSuccess, int fCritical, void* ptr, int size); +void WP_SendProtocolMessage(WP_Message *message); +void WP_PrepareAndSendProtocolMessage(uint32_t cmd, uint32_t payloadSize, uint8_t* payload, uint32_t flags); + +#ifdef __cplusplus +} +#endif + +#endif // _WIREPROTOCOL_MESSAGE_H_ diff --git a/source/native/nf-interpreter/src/CLR/Include/WireProtocol_MonitorCommands.h b/source/native/nf-interpreter/src/CLR/Include/WireProtocol_MonitorCommands.h new file mode 100644 index 00000000..f2cea51c --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/WireProtocol_MonitorCommands.h @@ -0,0 +1,198 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIREPROTOCOL_COMMANDS_H_ +#define _WIREPROTOCOL_COMMANDS_H_ + +#include "WireProtocol.h" +#include "WireProtocol_Message.h" + +////////////////////////////////////////// +// enums + +// structure for Monitor Reboot options +// backwards compatible with .NETMF +typedef enum Monitor_Reboot_Options +{ + Monitor_Reboot_c_NormalReboot = 0, + Monitor_Reboot_c_EnterBootloader = 1, + Monitor_Reboot_c_ClrRebootOnly = 2, + Monitor_Reboot_c_ClrStopDebugger = 4 +}Monitor_Reboot_Options; + +// structure for Access Memory operations +typedef enum AccessMemory_Operations +{ + // check if memory space is erased + AccessMemory_Check = 0x00, + + // read block of data starting at a given address + AccessMemory_Read = 0x01, + + // write block of data starting at a given address + AccessMemory_Write = 0x02, + + // erase sector/block/page at a given address + AccessMemory_Erase = 0x03, + + + AccessMemory_Mask = 0x0F + +}AccessMemory_Operations; + +typedef enum MemoryMap_Options +{ + Monitor_MemoryMap_c_RAM = 0x00000001, + Monitor_MemoryMap_c_FLASH = 0x00000002, + +}MemoryMap_Options; + + +////////////////////////////////////////// +// typedefs + +// structure for Monitor Ping Reply +// backwards compatible with .NETMF +typedef struct Monitor_Ping_Reply +{ + uint32_t m_source; + uint32_t m_dbg_flags; + +}Monitor_Ping_Reply; + +// structure for command Monitor Ping +// backwards compatible with .NETMF +typedef struct Monitor_Ping_Command +{ + uint32_t m_source; + uint32_t m_dbg_flags; + +}Monitor_Ping_Command; + + +// structure with reply for OEM information command +typedef struct Monitor_OemInfo_Reply +{ + ReleaseInfo m_releaseInfo; + +}Monitor_OemInfo_Reply; + +typedef struct CLR_DBG_Commands_Monitor_ReadMemory +{ + uint32_t address; + uint32_t length; + unsigned char data[1]; + +}CLR_DBG_Commands_Monitor_ReadMemory; + +typedef struct CLR_DBG_Commands_Monitor_WriteMemory +{ + uint32_t address; + uint32_t length; + unsigned char data[1]; + +}CLR_DBG_Commands_Monitor_WriteMemory; + +typedef struct Monitor_Reboot_Command +{ + uint32_t m_flags; + +}Monitor_Reboot_Command; + +typedef struct CLR_DBG_Commands_Monitor_EraseMemory +{ + uint32_t address; + uint32_t length; + +}CLR_DBG_Commands_Monitor_EraseMemory; + +typedef struct CLR_DBG_Commands_Monitor_CheckMemory +{ + uint32_t address; + uint32_t length; + +}CLR_DBG_Commands_Monitor_CheckMemory; + +typedef struct CLR_DBG_Commands_Monitor_CheckMemory_Reply +{ + uint32_t crc; + +}CLR_DBG_Commands_Monitor_CheckMemory_Reply; + +typedef struct CLR_DBG_Commands_Monitor_EraseMemory_Reply +{ + uint32_t ErrorCode; + +}CLR_DBG_Commands_Monitor_EraseMemory_Reply; + +typedef struct CLR_DBG_Commands_Monitor_WriteMemory_Reply +{ + uint32_t ErrorCode; + +}CLR_DBG_Commands_Monitor_WriteMemory_Reply; + +typedef struct MemoryMap_Range +{ + uint32_t m_address; + uint32_t m_length; + uint32_t m_flags; + +}MemoryMap_Range; + + +typedef struct CLR_DBG_Commands_Monitor_MemoryMap +{ + MemoryMap_Range m_map[1]; + +}CLR_DBG_Commands_Monitor_MemoryMap; + +typedef struct Monitor_QueryConfiguration_Command +{ + uint32_t Configuration; + uint32_t BlockIndex; + +}Monitor_QueryConfiguration_Command; + +typedef struct Monitor_UpdateConfiguration_Command +{ + uint32_t Configuration; + uint32_t BlockIndex; + uint32_t Length; + uint32_t Offset; + uint8_t Data[1]; + +}Monitor_UpdateConfiguration_Command; + +typedef struct Monitor_UpdateConfiguration_Reply +{ + uint32_t ErrorCode; + +}Monitor_UpdateConfiguration_Reply; + +////////////////////////////////////////// +// function declarations (commands) + +#ifdef __cplusplus +extern "C" { +#endif + +int Monitor_Ping(WP_Message* message); +int Monitor_OemInfo(WP_Message* message); +int Monitor_WriteMemory(WP_Message* message); +int Monitor_ReadMemory(WP_Message* message); +int Monitor_Reboot(WP_Message* message); +int Monitor_EraseMemory(WP_Message* message); +int Monitor_QueryConfiguration(WP_Message* message); +int Monitor_UpdateConfiguration(WP_Message* message); +int Monitor_CheckMemory(WP_Message* message); +int Monitor_MemoryMap(WP_Message* message); +int Monitor_FlashSectorMap(WP_Message* message); + +#ifdef __cplusplus +} +#endif + +#endif //_WIREPROTOCOL_COMMANDS_H_ diff --git a/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Application.h b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Application.h new file mode 100644 index 00000000..6cba90eb --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Application.h @@ -0,0 +1,40 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _NANOCLR_APPLICATION_H_ +#define _NANOCLR_APPLICATION_H_ + +#include + +typedef struct CLR_SETTINGS +{ + // this is the maximum number of context switches that execution engine thread scheduler can handle + // higher number: more threads and timers can be handled + unsigned short MaxContextSwitches; + + // set this to TRUE if the default behaviour is for the execution engine to wait for a debugger to be connected + // when building is set for RTM this configuration is ignored + bool WaitForDebugger; + + // set this to TRUE if a connection from a debugger is to be awaited after the execution engine terminates + // this is required for launching a debug session in Visual Studio + // when building is set for RTM this configuration is ignored + bool EnterDebuggerLoopAfterExit; +}CLR_SETTINGS; + +#ifdef __cplusplus +extern "C" { +#endif + + extern void ClrStartup(CLR_SETTINGS params); + + extern void ClrExit(); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Checks.h b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Checks.h new file mode 100644 index 00000000..a2398d8d --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Checks.h @@ -0,0 +1,68 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _NANOCLR_CHECKS_H_ +#define _NANOCLR_CHECKS_H_ + +#include + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +struct CLR_RT_DUMP +{ +#undef DECL_POSTFIX +#if defined(NANOCLR_TRACE_ERRORS) +#define DECL_POSTFIX +#else +#define DECL_POSTFIX {} +#endif + + static void TYPE ( const CLR_RT_TypeDef_Index& cls ) DECL_POSTFIX; + static void TYPE ( const CLR_RT_ReflectionDef_Index& reflex ) DECL_POSTFIX; + static void METHOD( const CLR_RT_MethodDef_Index& method ) DECL_POSTFIX; + static void FIELD ( const CLR_RT_FieldDef_Index& field ) DECL_POSTFIX; + static void OBJECT( CLR_RT_HeapBlock* ptr , const char* text ) DECL_POSTFIX; + + //--// + +#undef DECL_POSTFIX +#if defined(NANOCLR_TRACE_EXCEPTIONS) +#define DECL_POSTFIX +#else +#define DECL_POSTFIX {} +#endif + static void EXCEPTION ( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock& ref ) DECL_POSTFIX; + static void POST_PROCESS_EXCEPTION( CLR_RT_HeapBlock& ref ) DECL_POSTFIX; + + static const char* GETERRORMESSAGE( HRESULT hrError ); +#if defined(_WIN32) + static const char* GETERRORDETAIL (); +#endif +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +struct CLR_Checks +{ + static HRESULT VerifyStackOK( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock* top, int num ) { return S_OK; } + + static HRESULT VerifyObject ( CLR_RT_HeapBlock& top ); + + static HRESULT VerifyArrayReference ( CLR_RT_HeapBlock& ref ); + + static HRESULT VerifyUnknownInstruction ( CLR_OPCODE op ); + static HRESULT VerifyUnsupportedInstruction( CLR_OPCODE op ); +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#endif // _NANOCLR_CHECKS_H_ diff --git a/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Debugging.h b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Debugging.h new file mode 100644 index 00000000..08f08ec7 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Debugging.h @@ -0,0 +1,1166 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _NANOCLR_DEBUGGING_H_ +#define _NANOCLR_DEBUGGING_H_ + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#include +#include +#include + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +//#if defined(_MSC_VER) +struct CLR_DBG_Commands +{ + static const unsigned int c_Monitor_Ping = 0x00000000; // The payload is empty, this command is used to let the other side know we are here... + static const unsigned int c_Monitor_Message = 0x00000001; // The payload is composed of the string characters, no zero at the end. + static const unsigned int c_Monitor_ReadMemory = 0x00000002; + static const unsigned int c_Monitor_WriteMemory = 0x00000003; + static const unsigned int c_Monitor_CheckMemory = 0x00000004; + static const unsigned int c_Monitor_EraseMemory = 0x00000005; + static const unsigned int c_Monitor_Execute = 0x00000006; + static const unsigned int c_Monitor_Reboot = 0x00000007; + static const unsigned int c_Monitor_MemoryMap = 0x00000008; + static const unsigned int c_Monitor_ProgramExit = 0x00000009; // The payload is empty, this command is used to tell the PC of a program termination + static const unsigned int c_Monitor_CheckSignature = 0x0000000A; + static const unsigned int c_Monitor_DeploymentMap = 0x0000000B; + static const unsigned int c_Monitor_FlashSectorMap = 0x0000000C; + static const unsigned int c_Monitor_OemInfo = 0x0000000E; + static const unsigned int c_Monitor_QueryConfiguration = 0x0000000F; + static const unsigned int c_Monitor_UpdateConfiguration= 0x00000010; + + //--// + + + + + + + + + + + + + + + + + + + + + + struct Monitor_OemInfo + { + struct Reply + { + NFReleaseInfo m_releaseInfo; + }; + }; + + ///////////////////////////////////////////////////////////////////////////////////////////////////////// + // !!! KEEP IN SYNC WITH nanoFramework.Tools.Debugger.WireProtocol.RebootOptions (in managed code) !!! // + ///////////////////////////////////////////////////////////////////////////////////////////////////////// + struct Monitor_Reboot + { + static const unsigned int c_NormalReboot = 0; + static const unsigned int c_EnterBootloader = 1; + static const unsigned int c_ClrOnly = 2; + static const unsigned int c_WaitForDebugger = 4; + + unsigned int m_flags; + }; + + struct Monitor_ReadMemory + { + unsigned int m_address; + unsigned int m_length; + + struct Reply + { + unsigned int ErrorCode; + unsigned char m_data[ 1 ]; + }; + }; + + struct Monitor_WriteMemory + { + unsigned int m_address; + unsigned int m_length; + unsigned char m_data[ 1 ]; + + struct Reply + { + unsigned int ErrorCode; + }; + }; + + struct Monitor_Signature + { + unsigned int m_keyIndex; + unsigned int m_length; + unsigned char m_signature[ 1 ]; + }; + + struct Monitor_CheckMemory + { + unsigned int m_address; + unsigned int m_length; + + struct Reply + { + unsigned int m_crc; + }; + }; + + struct Monitor_EraseMemory + { + unsigned int m_address; + unsigned int m_length; + + struct Reply + { + unsigned int ErrorCode; + }; + }; + + struct Monitor_Execute + { + unsigned int m_address; + }; + + + + + + + + + + + + + + + + + + struct Monitor_DeploymentMap + { + static const CLR_UINT32 c_CRC_Erased_Sentinel = 0x0; + + struct FlashSector + { + CLR_UINT32 m_start; + CLR_UINT32 m_length; + + CLR_UINT32 m_crc; + }; + + struct Reply + { + + FlashSector m_data[ 1 ]; + }; + }; + + + + + struct Monitor_SignatureKeyUpdate + { + unsigned int m_keyIndex; + unsigned char m_newKeySignature[ 128 ]; + unsigned char m_newKey[ 260 ]; + unsigned int m_reserveLength; + unsigned char m_reserveData[ 1 ]; + }; + + //--------------------------------------------------------------// + + static const unsigned int c_Debugging_Execution_BasePtr = 0x00020000; // Returns the pointer for the ExecutionEngine object. + static const unsigned int c_Debugging_Execution_ChangeConditions = 0x00020001; // Sets/resets the state of the debugger. + static const unsigned int c_Debugging_Execution_SecurityKey = 0x00020002; // Sets security key. + static const unsigned int c_Debugging_Execution_Unlock = 0x00020003; // Unlock the low-level command, for mfg. test programs. + static const unsigned int c_Debugging_Execution_Allocate = 0x00020004; // Permanently allocate some memory. + static const unsigned int c_Debugging_Execution_Breakpoints = 0x00020005; // Sets breakpoints. + static const unsigned int c_Debugging_Execution_BreakpointHit = 0x00020006; // Notification that a breakpoint was hit. + static const unsigned int c_Debugging_Execution_BreakpointStatus = 0x00020007; // Queries last breakpoint hit. + static const unsigned int c_Debugging_Execution_QueryCLRCapabilities = 0x00020008; // Queries capabilities of the CLR. + static const unsigned int c_Debugging_Execution_SetCurrentAppDomain = 0x00020009; // Sets the current AppDomain. This is required before + // performing certain debugging operations, such as + // accessing a static field, or doing function evaluation, + + static const unsigned int c_Debugging_Thread_Create = 0x00020010; // OBSOLETE - Use c_Debugging_Thread_CreateEx instead. + static const unsigned int c_Debugging_Thread_List = 0x00020011; // Lists the active/waiting threads. + static const unsigned int c_Debugging_Thread_Stack = 0x00020012; // Lists the call stack for a thread. + static const unsigned int c_Debugging_Thread_Kill = 0x00020013; // Kills a thread. + static const unsigned int c_Debugging_Thread_Suspend = 0x00020014; // Suspends the execution of a thread. + static const unsigned int c_Debugging_Thread_Resume = 0x00020015; // Resumes the execution of a thread. + static const unsigned int c_Debugging_Thread_GetException = 0x00020016; // Gets the current exception. + static const unsigned int c_Debugging_Thread_Unwind = 0x00020017; // Unwinds to given stack frame. + static const unsigned int c_Debugging_Thread_CreateEx = 0x00020018; // Creates a new thread but Thread.CurrentThread will return the identity of the passed thread. + static const unsigned int c_Debugging_Thread_Get = 0x00021000; // Gets the current thread. + + static const unsigned int c_Debugging_Stack_Info = 0x00020020; // Gets more info on a stack frame. + static const unsigned int c_Debugging_Stack_SetIP = 0x00020021; // Sets the IP on a given thread. + + static const unsigned int c_Debugging_Value_ResizeScratchPad = 0x00020030; // Resizes the scratchpad area. + static const unsigned int c_Debugging_Value_GetStack = 0x00020031; // Reads a value from the stack frame. + static const unsigned int c_Debugging_Value_GetField = 0x00020032; // Reads a value from an object's field. + static const unsigned int c_Debugging_Value_GetArray = 0x00020033; // Reads a value from an array's element. + static const unsigned int c_Debugging_Value_GetBlock = 0x00020034; // Reads a value from a heap block. + static const unsigned int c_Debugging_Value_GetScratchPad = 0x00020035; // Reads a value from the scratchpad area. + static const unsigned int c_Debugging_Value_SetBlock = 0x00020036; // Writes a value to a heap block. + static const unsigned int c_Debugging_Value_SetArray = 0x00020037; // Writes a value to an array's element. + static const unsigned int c_Debugging_Value_AllocateObject = 0x00020038; // Creates a new instance of an object. + static const unsigned int c_Debugging_Value_AllocateString = 0x00020039; // Creates a new instance of a string. + static const unsigned int c_Debugging_Value_AllocateArray = 0x0002003A; // Creates a new instance of an array. + static const unsigned int c_Debugging_Value_Assign = 0x0002003B; // Assigns a value to another value. + + static const unsigned int c_Debugging_TypeSys_Assemblies = 0x00020040; // Lists all the assemblies in the system. + static const unsigned int c_Debugging_TypeSys_AppDomains = 0x00020044; // Lists all the AppDomans loaded. + + static const unsigned int c_Debugging_Resolve_Assembly = 0x00020050; // Resolves an assembly. + static const unsigned int c_Debugging_Resolve_Type = 0x00020051; // Resolves a type to a string. + static const unsigned int c_Debugging_Resolve_Field = 0x00020052; // Resolves a field to a string. + static const unsigned int c_Debugging_Resolve_Method = 0x00020053; // Resolves a method to a string. + static const unsigned int c_Debugging_Resolve_VirtualMethod = 0x00020054; // Resolves a virtual method to the actual implementation. + static const unsigned int c_Debugging_Resolve_AppDomain = 0x00020055; // Resolves an AppDomain to it's name, and list its loaded assemblies. + + + + + + + + + + static const unsigned int c_Debugging_UpgradeToSsl = 0x00020069; // + + //--// + + static const unsigned int c_Debugging_Button_Report = 0x00020080; // Reports a button press/release. + static const unsigned int c_Debugging_Button_Inject = 0x00020081; // Injects a button press/release. + + static const unsigned int c_Debugging_Deployment_Status = 0x000200B0; // Returns entryPoint and boundary of deployment area. + + static const unsigned int c_Debugging_Info_SetJMC = 0x000200C0; // Sets code to be flagged as JMC (Just my code). + + static const unsigned int c_Profiling_Command = 0x00030000; // Various incoming commands regarding profiling + static const unsigned int c_Profiling_Stream = 0x00030001; // Stream for MFProfiler information. + + //--// + + struct Debugging_Execution_Unlock + { + unsigned char m_command[ 128 ]; + unsigned char m_hash [ 128 ]; + }; + + struct Debugging_Execution_QueryCLRCapabilities + { + static const CLR_UINT32 c_CapabilityFlags = 1; + static const CLR_UINT32 c_CapabilityVersion = 3; + static const CLR_UINT32 c_HalSystemInfo = 5; + static const CLR_UINT32 c_ClrInfo = 6; + static const CLR_UINT32 c_TargetReleaseInfo = 7; + static const CLR_UINT32 c_InteropNativeAssemblies = 8; + + static const CLR_UINT32 c_CapabilityFlags_FloatingPoint = 0x00000001; + static const CLR_UINT32 c_CapabilityFlags_SourceLevelDebugging = 0x00000002; + static const CLR_UINT32 c_CapabilityFlags_AppDomains = 0x00000004; + static const CLR_UINT32 c_CapabilityFlags_ExceptionFilters = 0x00000008; + static const CLR_UINT32 c_CapabilityFlags_IncrementalDeployment = 0x00000010; + static const CLR_UINT32 c_CapabilityFlags_SoftReboot = 0x00000020; + static const CLR_UINT32 c_CapabilityFlags_Profiling = 0x00000040; + static const CLR_UINT32 c_CapabilityFlags_Profiling_Allocations = 0x00000080; + static const CLR_UINT32 c_CapabilityFlags_Profiling_Calls = 0x00000100; + static const CLR_UINT32 c_CapabilityFlags_ThreadCreateEx = 0x00000400; + static const CLR_UINT32 c_CapabilityFlags_ConfigBlockRequiresErase = 0x00000800; + static const CLR_UINT32 c_CapabilityFlags_HasNanoBooter = 0x00001000; + static const CLR_UINT32 c_CapabilityFlags_PlatformCapabiliy_0 = 0x00010000; + static const CLR_UINT32 c_CapabilityFlags_PlatformCapabiliy_1 = 0x00020000; + static const CLR_UINT32 c_CapabilityFlags_TargetCapabiliy_0 = 0x00040000; + static const CLR_UINT32 c_CapabilityFlags_TargetCapabiliy_1 = 0x00080000; + + CLR_UINT32 m_cmd; + + struct __nfpack SoftwareVersion + { + char BuildDate[ 22 ]; + char CompilerInfo[16]; + unsigned int CompilerVersion; + }; + + struct __nfpack ClrInfo + { + NFReleaseInfo m_clrReleaseInfo; + NFVersion m_TargetFrameworkVersion; + }; + + struct __nfpack NativeAssemblyDetails + { + uint32_t CheckSum; + NFVersion Version; + uint8_t AssemblyName[128]; + + }; + + union ReplyUnion + { + CLR_UINT32 u_capsFlags; + SoftwareVersion u_SoftwareVersion; + HalSystemInfo u_HalSystemInfo; + ClrInfo u_ClrInfo; + NFReleaseInfo u_TargetReleaseInfo; + }; + }; + + //--// + + struct Debugging_Messaging_Query + { + CLR_RT_HeapBlock_EndPoint::Address m_addr; + + struct Reply + { + CLR_UINT32 m_found; + CLR_RT_HeapBlock_EndPoint::Address m_addr; + }; + }; + + struct Debugging_Messaging_Send + { + CLR_RT_HeapBlock_EndPoint::Address m_addr; + unsigned char m_data[ 1 ]; + + struct Reply + { + CLR_UINT32 m_found; + CLR_RT_HeapBlock_EndPoint::Address m_addr; + }; + }; + + struct Debugging_Messaging_Reply + { + CLR_RT_HeapBlock_EndPoint::Address m_addr; + unsigned char m_data[ 1 ]; + + struct Reply + { + CLR_UINT32 m_found; + CLR_RT_HeapBlock_EndPoint::Address m_addr; + }; + }; + + //--// + + + struct Debugging_Execution_BasePtr + { + struct Reply + { + CLR_UINT32 m_EE; + }; + }; + + struct Debugging_Execution_ChangeConditions + { + CLR_UINT32 FlagsToSet; + CLR_UINT32 FlagsToReset; + + struct Reply + { + CLR_UINT32 CurrentState; + }; + }; + + struct Debugging_Execution_SecurityKey + { + CLR_UINT8 m_key[ 32 ]; + }; + + struct Debugging_Execution_Allocate + { + CLR_UINT32 m_size; + + struct Reply + { + CLR_UINT32 m_address; + }; + }; + + struct Debugging_UpgradeToSsl + { + CLR_UINT32 m_flags; + + struct Reply + { + CLR_UINT32 m_success; + }; + }; + + + //struct Debugging_MFUpdate_Start + //{ + // char m_provider[64]; + // CLR_UINT32 m_updateId; + // CLR_UINT32 m_updateType; + // CLR_UINT32 m_updateSubType; + // CLR_UINT32 m_updateSize; + // CLR_UINT32 m_updatePacketSize; + // CLR_UINT16 m_versionMajor; + // CLR_UINT16 m_versionMinor; + + // struct Reply + // { + // CLR_INT32 m_updateHandle; + // }; + //}; + + //struct Debugging_MFUpdate_AuthCommand + //{ + // CLR_UINT32 m_updateHandle; + // CLR_UINT32 m_authCommand; + // CLR_UINT32 m_authArgsSize; + // CLR_UINT8 m_authArgs[1]; + + // struct Reply + // { + // CLR_INT32 m_success; + // CLR_UINT32 m_responseSize; + // CLR_UINT8 m_response[1]; + // }; + //}; + + //struct Debugging_MFUpdate_Authenticate + //{ + // CLR_UINT32 m_updateHandle; + // CLR_UINT32 m_authenticationLen; + // CLR_UINT8 m_authenticationData[1]; + + // struct Reply + // { + // CLR_INT32 m_success; + // }; + //}; + + //struct Debugging_MFUpdate_GetMissingPkts + //{ + // CLR_UINT32 m_updateHandle; + // + // struct Reply + // { + // CLR_INT32 m_success; + // CLR_INT32 m_missingPktCount; + // CLR_UINT32 m_missingPkts[1]; + // }; + //}; + + //struct Debugging_MFUpdate_AddPacket + //{ + // CLR_INT32 m_updateHandle; + // CLR_UINT32 m_packetIndex; + // CLR_UINT32 m_packetValidation; + // CLR_UINT32 m_packetLength; + // CLR_UINT8 m_packetData[1]; + + // struct Reply + // { + // CLR_UINT32 m_success; + // }; + //}; + + //struct Debugging_MFUpdate_Install + //{ + // CLR_INT32 m_updateHandle; + // CLR_UINT32 m_updateValidationSize; + // CLR_UINT8 m_updateValidation[1]; + + // struct Reply + // { + // CLR_UINT32 m_success; + // }; + //}; + + + struct Debugging_Execution_BreakpointDef + { + static const CLR_UINT16 c_STEP_IN = 0x0001; + static const CLR_UINT16 c_STEP_OVER = 0x0002; + static const CLR_UINT16 c_STEP_OUT = 0x0004; + static const CLR_UINT16 c_HARD = 0x0008; + static const CLR_UINT16 c_EXCEPTION_THROWN = 0x0010; + static const CLR_UINT16 c_EXCEPTION_CAUGHT = 0x0020; + static const CLR_UINT16 c_EXCEPTION_UNCAUGHT = 0x0040; + static const CLR_UINT16 c_THREAD_TERMINATED = 0x0080; + static const CLR_UINT16 c_THREAD_CREATED = 0x0100; + static const CLR_UINT16 c_ASSEMBLIES_LOADED = 0x0200; + static const CLR_UINT16 c_LAST_BREAKPOINT = 0x0400; + static const CLR_UINT16 c_STEP_JMC = 0x0800; + static const CLR_UINT16 c_BREAK = 0x1000; + static const CLR_UINT16 c_EVAL_COMPLETE = 0x2000; + static const CLR_UINT16 c_EXCEPTION_UNWIND = 0x4000; + static const CLR_UINT16 c_EXCEPTION_FINALLY = 0x8000; + + static const CLR_UINT16 c_STEP = c_STEP_IN | c_STEP_OVER | c_STEP_OUT; + + static const CLR_INT32 c_PID_ANY = 0x7FFFFFFF; + + static const CLR_UINT32 c_DEPTH_EXCEPTION_FIRST_CHANCE = 0x00000000; + static const CLR_UINT32 c_DEPTH_EXCEPTION_USERS_CHANCE = 0x00000001; + static const CLR_UINT32 c_DEPTH_EXCEPTION_HANDLER_FOUND = 0x00000002; + + static const CLR_UINT32 c_DEPTH_STEP_NORMAL = 0x00000010; + static const CLR_UINT32 c_DEPTH_STEP_RETURN = 0x00000020; + static const CLR_UINT32 c_DEPTH_STEP_CALL = 0x00000030; + static const CLR_UINT32 c_DEPTH_STEP_EXCEPTION_FILTER = 0x00000040; + static const CLR_UINT32 c_DEPTH_STEP_EXCEPTION_HANDLER = 0x00000050; + static const CLR_UINT32 c_DEPTH_STEP_INTERCEPT = 0x00000060; + static const CLR_UINT32 c_DEPTH_STEP_EXIT = 0x00000070; + + static const CLR_UINT32 c_DEPTH_UNCAUGHT = 0xFFFFFFFF; + + + CLR_UINT16 m_id; + CLR_UINT16 m_flags; + + CLR_INT32 m_pid; + CLR_UINT32 m_depth; + + // + // m_IPStart, m_IPEnd are used for optimizing stepping operations. + // A STEP_IN | STEP_OVER breakpoint will be hit in the given stack frame + // only if the IP is outside of the given range [m_IPStart m_IPEnd). + // + CLR_UINT32 m_IPStart; + CLR_UINT32 m_IPEnd; + + CLR_RT_MethodDef_Index m_md; + CLR_UINT32 m_IP; + + CLR_RT_TypeDef_Index m_td; + + CLR_UINT32 m_depthExceptionHandler; + }; + + struct Debugging_Execution_Breakpoints + { + CLR_UINT32 m_flags; + + Debugging_Execution_BreakpointDef m_data[ 1 ]; + }; + + struct Debugging_Execution_BreakpointHit + { + Debugging_Execution_BreakpointDef m_hit; + }; + + struct Debugging_Execution_BreakpointStatus + { + struct Reply + { + Debugging_Execution_BreakpointDef m_lastHit; + }; + }; + + struct Debugging_Execution_SetCurrentAppDomain + { + CLR_UINT32 m_id; + }; + + //--//--// + + struct Debugging_Thread_CreateEx + { + CLR_RT_MethodDef_Index m_md; + int m_scratchPad; + CLR_UINT32 m_pid; + + struct Reply + { + CLR_UINT32 m_pid; + }; + }; + + //--// + + struct Debugging_Thread_List + { + struct Reply + { + CLR_UINT32 m_num; + CLR_UINT32 m_pids[ 1 ]; + }; + }; + + //--// + + struct Debugging_Thread_Stack + { + CLR_UINT32 m_pid; + + struct Reply + { + struct Call + { + CLR_RT_MethodDef_Index m_md; + CLR_UINT32 m_IP; +#if defined(NANOCLR_APPDOMAINS) + CLR_UINT32 m_appDomainID; + CLR_UINT32 m_flags; +#endif + + }; + + CLR_UINT32 m_num; + CLR_UINT32 m_status; + CLR_UINT32 m_flags; + Call m_data[ 1 ]; + }; + }; + + struct Debugging_Thread_Kill + { + CLR_UINT32 m_pid; + + struct Reply + { + int m_result; + }; + }; + + struct Debugging_Thread_Suspend + { + CLR_UINT32 m_pid; + }; + + struct Debugging_Thread_Resume + { + CLR_UINT32 m_pid; + }; + + struct Debugging_Thread_Get + { + CLR_UINT32 m_pid; + + // + // The reply is an array of Debugging_Value + // + }; + + struct Debugging_Thread_GetException + { + CLR_UINT32 m_pid; + + // + // The reply is an array of Debugging_Value + // + }; + + struct Debugging_Thread_Unwind + { + CLR_UINT32 m_pid; + CLR_UINT32 m_depth; + }; + + //--// + + struct Debugging_Stack_Info + { + CLR_UINT32 m_pid; + CLR_UINT32 m_depth; + + struct Reply + { + CLR_RT_MethodDef_Index m_md; + CLR_UINT32 m_IP; + CLR_UINT32 m_numOfArguments; + CLR_UINT32 m_numOfLocals; + CLR_UINT32 m_depthOfEvalStack; + }; + }; + + struct Debugging_Stack_SetIP + { + CLR_UINT32 m_pid; + CLR_UINT32 m_depth; + + CLR_UINT32 m_IP; + CLR_UINT32 m_depthOfEvalStack; + }; + + //--// + + struct Debugging_Value + { + CLR_RT_HeapBlock* m_referenceID; + CLR_UINT32 m_dt; // CLR_RT_HeapBlock::DataType () + CLR_UINT32 m_flags; // CLR_RT_HeapBlock::DataFlags() + CLR_UINT32 m_size; // CLR_RT_HeapBlock::DataSize () + + // + // For primitive types + // + CLR_UINT8 m_builtinValue[ 128 ]; // Space for string preview... + + // + // For DATATYPE_STRING + // + CLR_UINT32 m_bytesInString; + const char* m_charsInString; + + // + // For DATATYPE_VALUETYPE or DATATYPE_CLASSTYPE + // + CLR_RT_TypeDef_Index m_td; + + // + // For DATATYPE_SZARRAY + // + CLR_UINT32 m_array_numOfElements; + CLR_UINT32 m_array_depth; + CLR_RT_TypeDef_Index m_array_typeIndex; + + // + // For values from an array. + // + CLR_RT_HeapBlock_Array* m_arrayref_referenceID; + CLR_UINT32 m_arrayref_index; + }; + + struct Debugging_Value_ResizeScratchPad + { + CLR_UINT32 m_size; + }; + + struct Debugging_Value_GetStack + { + static const CLR_UINT32 c_Local = 0; + static const CLR_UINT32 c_Argument = 1; + static const CLR_UINT32 c_EvalStack = 2; + + CLR_UINT32 m_pid; + CLR_UINT32 m_depth; + CLR_UINT32 m_kind; + CLR_UINT32 m_index; + + + // + // The reply is an array of Debugging_Value + // + }; + + struct Debugging_Value_GetField + { + CLR_RT_HeapBlock* m_heapblock; + CLR_UINT32 m_offset; + CLR_RT_FieldDef_Index m_fd; + + + // + // The reply is an array of Debugging_Value + // + }; + + struct Debugging_Value_GetArray + { + CLR_RT_HeapBlock* m_heapblock; + CLR_UINT32 m_index; + + + // + // The reply is an array of Debugging_Value + // + }; + + struct Debugging_Value_GetBlock + { + CLR_RT_HeapBlock* m_heapblock; + + + // + // The reply is an array of Debugging_Value + // + }; + + struct Debugging_Value_GetScratchPad + { + CLR_UINT32 m_idx; + + + // + // The reply is an array of Debugging_Value + // + }; + + struct Debugging_Value_SetBlock + { + CLR_RT_HeapBlock* m_heapblock; + CLR_UINT32 m_dt; // CLR_RT_HeapBlock::DataType () + CLR_UINT8 m_builtinValue[ 8 ]; + }; + + struct Debugging_Value_SetArray + { + CLR_RT_HeapBlock_Array* m_heapblock; + CLR_UINT32 m_index; + CLR_UINT8 m_builtinValue[ 8 ]; + }; + + //--// + + struct Debugging_Value_AllocateObject + { + int m_index; + CLR_RT_TypeDef_Index m_td; + + // + // The reply is an array of Debugging_Value + // + }; + + struct Debugging_Value_AllocateString + { + int m_index; + CLR_UINT32 m_size; + + // + // The reply is an array of Debugging_Value + // + }; + + struct Debugging_Value_AllocateArray + { + int m_index; + CLR_RT_TypeDef_Index m_td; + CLR_UINT32 m_depth; + CLR_UINT32 m_numOfElements; + + // + // The reply is an array of Debugging_Value + // + }; + + struct Debugging_Value_Assign + { + CLR_RT_HeapBlock* m_heapblockSrc; + CLR_RT_HeapBlock* m_heapblockDst; + + // + // The reply is an array of Debugging_Value + // + }; + + //--// + + struct Debugging_TypeSys_Assemblies + { + // + // The reply is just an array of CLR_RT_Assembly_Index. + // + }; + + struct Debugging_TypeSys_AppDomains + { + // + // The reply is just an array of AppDomainIDs + // + }; + + //--// + + struct Debugging_Resolve_AppDomain + { + CLR_UINT32 m_id; + + struct Reply + { + CLR_UINT32 m_state; + char m_szName[ 512 ]; + CLR_UINT32 m_assemblies[ 1 ]; //Array of CLR_RT_Assembly_Index + }; + }; + + struct Debugging_Resolve_Assembly + { + CLR_RT_Assembly_Index m_idx; + + struct Reply + { + CLR_UINT32 m_flags; + CLR_RECORD_VERSION m_version; + char m_szName[ 512 ]; + }; + }; + + struct Debugging_Resolve_Type + { + CLR_RT_TypeDef_Index m_td; + + struct Reply + { + char m_type[ 512 ]; + }; + }; + + struct Debugging_Resolve_Field + { + CLR_RT_FieldDef_Index m_fd; + + struct Reply + { + CLR_RT_TypeDef_Index m_td; + CLR_UINT32 m_index; + char m_name[ 512 ]; + }; + }; + + struct Debugging_Resolve_Method + { + CLR_RT_MethodDef_Index m_md; + + struct Reply + { + CLR_RT_TypeDef_Index m_td; + char m_method[ 512 ]; + }; + }; + + struct Debugging_Resolve_VirtualMethod + { + CLR_RT_MethodDef_Index m_md; + CLR_RT_HeapBlock* m_obj; + + struct Reply + { + CLR_RT_MethodDef_Index m_md; + }; + }; + + //--// + + struct Debugging_Deployment_Status + { + struct FlashSector + { + CLR_UINT32 Start; + CLR_UINT32 Length; + }; + + struct Reply + { + CLR_UINT32 EntryPoint; + CLR_UINT32 StorageStart; + CLR_UINT32 StorageLength; + + // FlashSector SectorData[ 1 ]; + }; + }; + + //--// + + struct Debugging_Info_SetJMC + { + CLR_UINT32 m_fIsJMC; + CLR_UINT32 m_kind; // CLR_ReflectionType + + union + { + CLR_RT_Assembly_Index m_assm; + CLR_RT_TypeDef_Index m_type; + CLR_RT_MethodDef_Index m_method; + CLR_UINT32 m_raw; + } m_data; + }; + + struct Profiling_Command + { + static const CLR_UINT8 c_Command_ChangeConditions = 0x01; + static const CLR_UINT8 c_Command_FlushStream = 0x02; + + CLR_UINT8 m_command; + + struct Reply + { + CLR_UINT32 m_raw; + }; + }; + + struct Profiling_ChangeConditions + { + CLR_UINT32 m_set; + CLR_UINT32 m_reset; + }; + + struct Profiling_Stream + { + CLR_UINT16 m_seqId; + CLR_UINT16 m_bitLen; + }; + +}; +//#endif + +struct CLR_DBG_Debugger +{ + CLR_Messaging* m_messaging; + static BlockStorageDevice* m_deploymentStorageDevice; + + + //--// + + static void Debugger_WaitForCommands(); + + static HRESULT CreateInstance(); + + HRESULT Debugger_Initialize( COM_HANDLE port ); + + static HRESULT DeleteInstance(); + + void Debugger_Cleanup(); + + static void BroadcastEvent( unsigned int cmd, unsigned int payloadSize, unsigned char* payload, unsigned int flags ); + + void PurgeCache (); + +private: + + bool CheckPermission( ByteAddress address, int mode ); + + bool AccessMemory( CLR_UINT32 location, unsigned int lengthInBytes, unsigned char* buf, int mode, unsigned int* errorCode ); + +#if defined(NANOCLR_APPDOMAINS) + CLR_RT_AppDomain* GetAppDomainFromID ( CLR_UINT32 id ); +#endif + + CLR_RT_StackFrame* CheckStackFrame ( CLR_INT32 pid, CLR_UINT32 depth, bool& isInline ); + HRESULT CreateListOfThreads( CLR_DBG_Commands::Debugging_Thread_List ::Reply*& cmdReply, int& totLen ); + HRESULT CreateListOfCalls ( CLR_INT32 pid, CLR_DBG_Commands::Debugging_Thread_Stack::Reply*& cmdReply, int& totLen ); + + CLR_RT_Assembly* IsGoodAssembly( CLR_IDX idxAssm ); + bool CheckTypeDef ( const CLR_RT_TypeDef_Index& td , CLR_RT_TypeDef_Instance& inst ); + bool CheckFieldDef ( const CLR_RT_FieldDef_Index& fd , CLR_RT_FieldDef_Instance& inst ); + bool CheckMethodDef( const CLR_RT_MethodDef_Index& md , CLR_RT_MethodDef_Instance& inst ); + + bool GetValue( WP_Message* msg, CLR_RT_HeapBlock* ptr, CLR_RT_HeapBlock* reference, CLR_RT_TypeDef_Instance* pTD ); + + bool AllocateAndQueueMessage( CLR_UINT32 cmd, unsigned int length, unsigned char* data, CLR_RT_HeapBlock_EndPoint::Port port, CLR_RT_HeapBlock_EndPoint::Address addr, CLR_UINT32 found ); + + bool ProcessHeader ( WP_Message* msg ); + bool ProcessPayload ( WP_Message* msg ); + + +public: + static CLR_RT_Thread* GetThreadFromPid ( CLR_INT32 pid ); + + static bool Monitor_Ping ( WP_Message* msg ); + static bool Monitor_Reboot ( WP_Message* msg ); + static bool Debugging_Execution_QueryCLRCapabilities( WP_Message* msg ); + + static bool Monitor_ReadMemory ( WP_Message* msg ); + static bool Monitor_WriteMemory ( WP_Message* msg ); + static bool Monitor_CheckMemory ( WP_Message* msg ); + static bool Monitor_EraseMemory ( WP_Message* msg ); + static bool Monitor_Execute ( WP_Message* msg ); + static bool Monitor_MemoryMap ( WP_Message* msg ); + static bool Monitor_FlashSectorMap ( WP_Message* msg ); + static bool Monitor_DeploymentMap ( WP_Message* msg ); + static bool Monitor_QueryConfiguration ( WP_Message* msg ); + static bool Monitor_UpdateConfiguration ( WP_Message* msg ); + + + static bool Debugging_Execution_BasePtr ( WP_Message* msg ); + static bool Debugging_Execution_ChangeConditions ( WP_Message* msg ); + + static bool Debugging_Execution_Allocate ( WP_Message* msg ); + + static bool Debugging_UpgradeToSsl ( WP_Message* msg ); + + + + + + + + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + static bool Debugging_Execution_Breakpoints ( WP_Message* msg ); + static bool Debugging_Execution_BreakpointStatus ( WP_Message* msg ); + static bool Debugging_Execution_SetCurrentAppDomain ( WP_Message* msg ); + + static bool Debugging_Thread_CreateEx ( WP_Message* msg ); + static bool Debugging_Thread_List ( WP_Message* msg ); + static bool Debugging_Thread_Stack ( WP_Message* msg ); + static bool Debugging_Thread_Kill ( WP_Message* msg ); + static bool Debugging_Thread_Suspend ( WP_Message* msg ); + static bool Debugging_Thread_Resume ( WP_Message* msg ); + static bool Debugging_Thread_GetException ( WP_Message* msg ); + static bool Debugging_Thread_Unwind ( WP_Message* msg ); + static bool Debugging_Thread_Get ( WP_Message* msg ); + + static bool Debugging_Stack_Info ( WP_Message* msg ); + static bool Debugging_Stack_SetIP ( WP_Message* msg ); + + static bool Debugging_Value_ResizeScratchPad ( WP_Message* msg ); + static bool Debugging_Value_GetStack ( WP_Message* msg ); + static bool Debugging_Value_GetField ( WP_Message* msg ); + static bool Debugging_Value_GetArray ( WP_Message* msg ); + static bool Debugging_Value_GetBlock ( WP_Message* msg ); + static bool Debugging_Value_GetScratchPad ( WP_Message* msg ); + static bool Debugging_Value_SetBlock ( WP_Message* msg ); + static bool Debugging_Value_SetArray ( WP_Message* msg ); + static bool Debugging_Value_AllocateObject ( WP_Message* msg ); + static bool Debugging_Value_AllocateString ( WP_Message* msg ); + static bool Debugging_Value_AllocateArray ( WP_Message* msg ); + static bool Debugging_Value_Assign ( WP_Message* msg ); + + static bool Debugging_TypeSys_Assemblies ( WP_Message* msg ); + static bool Debugging_TypeSys_AppDomains ( WP_Message* msg ); + + static bool Debugging_Resolve_AppDomain ( WP_Message* msg ); + static bool Debugging_Resolve_Assembly ( WP_Message* msg ); + static bool Debugging_Resolve_Type ( WP_Message* msg ); + static bool Debugging_Resolve_Field ( WP_Message* msg ); + static bool Debugging_Resolve_Method ( WP_Message* msg ); + static bool Debugging_Resolve_VirtualMethod ( WP_Message* msg ); +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + static bool Debugging_Deployment_Status ( WP_Message* msg ); + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + static bool Debugging_Info_SetJMC ( WP_Message* msg ); + + bool Debugging_Info_SetJMC_Type ( const CLR_RT_TypeDef_Index& idx, bool fJMC ); + bool Debugging_Info_SetJMC_Method ( const CLR_RT_MethodDef_Index& idx, bool fJMC ); +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + static bool Profiling_Command ( WP_Message* msg ); + bool Profiling_ChangeConditions ( WP_Message* msg ); + bool Profiling_FlushStream ( WP_Message* msg ); +}; + +//--// + +extern CLR_UINT32 g_scratchDebugger[]; +extern CLR_UINT32 g_scratchDebuggerMessaging[]; +extern CLR_DBG_Debugger *g_CLR_DBG_Debugger; + +//--// + +extern const CLR_Messaging_CommandHandlerLookup c_Debugger_Lookup_Request[]; +extern const CLR_Messaging_CommandHandlerLookup c_Debugger_Lookup_Reply[]; +extern const CLR_UINT32 c_Debugger_Lookup_Request_count; +extern const CLR_UINT32 c_Debugger_Lookup_Reply_count; + +//--// + +#endif // _NANOCLR_DEBUGGING_H_ + diff --git a/source/native/nf-interpreter/src/CLR/Include/nanoCLR_ErrorCodes.h b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_ErrorCodes.h new file mode 100644 index 00000000..e757a622 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_ErrorCodes.h @@ -0,0 +1,27 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _NANOCLR_ERRORCODES_H_ +#define _NANOCLR_ERRORCODES_H_ +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#include + +// +// PARSER error codes. +// +#define CLR_E_PARSER_BAD_TEXT_SIGNATURE MAKE_HRESULT(SEVERITY_ERROR, 0x0101, 0x0001) +#define CLR_E_PARSER_BAD_CUSTOM_ATTRIBUTE MAKE_HRESULT(SEVERITY_ERROR, 0x0101, 0x0002) +#define CLR_E_PARSER_UNSUPPORTED_MULTIDIM_ARRAY MAKE_HRESULT(SEVERITY_ERROR, 0x0101, 0x0003) +#define CLR_E_PARSER_UNKNOWN_MEMBER_REF MAKE_HRESULT(SEVERITY_ERROR, 0x0101, 0x0004) +#define CLR_E_PARSER_MISSING_FIELD MAKE_HRESULT(SEVERITY_ERROR, 0x0101, 0x0005) +#define CLR_E_PARSER_MISSING_METHOD MAKE_HRESULT(SEVERITY_ERROR, 0x0101, 0x0006) +#define CLR_E_PARSER_MISSING_INTERFACE MAKE_HRESULT(SEVERITY_ERROR, 0x0101, 0x0007) +#define CLR_E_PARSER_MISSING_TOKEN MAKE_HRESULT(SEVERITY_ERROR, 0x0101, 0x0008) +#define CLR_E_PARSER_UNSUPPORTED_GENERICS MAKE_HRESULT(SEVERITY_ERROR, 0x0101, 0x0009) + + +#endif // _NANOCLR_ERRORCODES_H_ + diff --git a/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Hardware.h b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Hardware.h new file mode 100644 index 00000000..8bbee835 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Hardware.h @@ -0,0 +1,132 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _NANOCLR_HARDWARE_H_ +#define _NANOCLR_HARDWARE_H_ + +#include +#include +//#include + +//--// + + + + + + + + + + + + + + + + + + + + + + + + +#if defined(_WIN32) +#include "nanoCLR_Win32.h" +#endif + +//--// + +struct CLR_HW_Hardware +{ + static const CLR_UINT32 c_Default_PowerLevel = PowerLevel__Sleep; + static const CLR_UINT32 c_Default_WakeupEvents = SYSTEM_EVENT_FLAG_COM_IN | + SYSTEM_EVENT_FLAG_COM_OUT | + SYSTEM_EVENT_FLAG_STORAGE_IO | + SYSTEM_EVENT_FLAG_SYSTEM_TIMER | + SYSTEM_EVENT_FLAG_SPI_MASTER | + SYSTEM_EVENT_FLAG_I2C_MASTER | + SYSTEM_EVENT_HW_INTERRUPT | + SYSTEM_EVENT_FLAG_SOCKET | + SYSTEM_EVENT_FLAG_DEBUGGER_ACTIVITY | + SYSTEM_EVENT_FLAG_MESSAGING_ACTIVITY| + SYSTEM_EVENT_FLAG_ONEWIRE_MASTER; + + //--// + + struct HalInterruptRecord + { + CLR_INT64 m_time; + CLR_RT_HeapBlock_Node* m_context; + + CLR_UINT32 m_data1; + CLR_UINT32 m_data2; + CLR_UINT32 m_data3; + + void AssignFrom( const HalInterruptRecord &recFrom ) + { + m_time = recFrom.m_time; + m_context = recFrom.m_context; + m_data1 = recFrom.m_data1; + m_data2 = recFrom.m_data2; + } + }; + + struct InterruptData + { + Hal_Queue_UnknownSize m_HalQueue; + CLR_RT_DblLinkedList m_applicationQueue; + CLR_UINT32 m_queuedInterrupts; + }; + + //--// + + bool m_fInitialized; + + InterruptData m_interruptData; + + CLR_UINT32 m_DebuggerEventsMask; + + PowerLevel_type m_powerLevel; + CLR_UINT32 m_wakeupEvents; + + //--// + + static HRESULT CreateInstance(); + + HRESULT Hardware_Initialize(); + + static HRESULT DeleteInstance(); + + void Hardware_Cleanup(); + + void PrepareForGC (); + void ProcessActivity(); + + HRESULT ManagedHardware_Initialize(); + HRESULT ProcessInterrupts(); + HRESULT SpawnDispatcher(); + HRESULT TransferAllInterruptsToApplicationQueue(); +}; + +extern CLR_HW_Hardware g_CLR_HW_Hardware; + +//--// + + +//////////////////////////////////////////////////////////////////////////////////////// +// keep under control the size of the HalInterruptRecord, since we will use externally +// defined arrays to handle those data structures in the interrupt dispatching + +CT_ASSERT(sizeof(CLR_HW_Hardware::HalInterruptRecord) == 24) + +//////////////////////////////////////////////////////////////////////////////////////// + +//--// + +#endif // _NANOCLR_HARDWARE_H_ + diff --git a/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Interop.h b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Interop.h new file mode 100644 index 00000000..ae4b5029 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Interop.h @@ -0,0 +1,473 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _NANOCLR_INTEROP_H_ +#define _NANOCLR_INTEROP_H_ + +#include +#include + + +/////////////////////////////////////////////////////////////////////////////////////////////////// + + extern HRESULT NANOCLR_DEBUG_PROCESS_EXCEPTION( HRESULT hr, const char* szFunc, const char* szFile, int line ); + +#if defined(_WIN32) + +#define NANOCLR_LEAVE() { if(FAILED(hr)) NANOCLR_DEBUG_PROCESS_EXCEPTION( hr, NULL, NULL, 0 ); goto nanoCLR_Cleanup; } +#define NANOCLR_RETURN() return hr + +#else + +#if defined(NANOCLR_TRACE_HRESULT) + +#define NANOCLR_LEAVE() { if(FAILED(hr)) NANOCLR_DEBUG_PROCESS_EXCEPTION( hr, __func__, __FILE__, __LINE__ ); goto nanoCLR_Cleanup; } +#define NANOCLR_RETURN() return hr + +#else + +#define NANOCLR_LEAVE() goto nanoCLR_Cleanup +#define NANOCLR_RETURN() return hr + +#endif + +#endif + + +#define NANOCLR_HEADER() HRESULT hr +#define NANOCLR_CHECK_HRESULT(expr) { if(FAILED(hr = (expr))) NANOCLR_LEAVE(); } +#define NANOCLR_EXIT_ON_SUCCESS(expr) { if(SUCCEEDED(hr = (expr))) NANOCLR_LEAVE(); } +#define NANOCLR_SET_AND_LEAVE(expr) { hr = (expr); NANOCLR_LEAVE(); } +#if defined(_MSC_VER) +#define NANOCLR_MSG_SET_AND_LEAVE(expr, msg) { wprintf(msg); hr = (expr); NANOCLR_LEAVE(); } +#define NANOCLR_MSG1_SET_AND_LEAVE(expr, msg, ...) { wprintf(msg, __VA_ARGS__); hr = (expr); NANOCLR_LEAVE(); } +#define NANOCLR_CHARMSG_SET_AND_LEAVE(expr, msg, ...) { printf(msg, __VA_ARGS__); hr = (expr); NANOCLR_LEAVE(); } +#else +#define NANOCLR_MSG_SET_AND_LEAVE(expr, msg) { hr = (expr); NANOCLR_LEAVE(); } +#define NANOCLR_MSG1_SET_AND_LEAVE(expr, msg, arg) { hr = (expr); NANOCLR_LEAVE(); } +#endif +#define NANOCLR_CLEANUP() hr = S_OK; nanoCLR_Cleanup: +#define NANOCLR_CLEANUP_END() NANOCLR_RETURN() +#define NANOCLR_NOCLEANUP() NANOCLR_CLEANUP(); NANOCLR_CLEANUP_END() +#define NANOCLR_NOCLEANUP_NOLABEL() hr = S_OK; NANOCLR_RETURN() +#define FAULT_ON_NULL(ptr) if(!(ptr)) NANOCLR_SET_AND_LEAVE(CLR_E_NULL_REFERENCE) +#define FAULT_ON_NULL_ARG(ptr) if(!(ptr)) NANOCLR_SET_AND_LEAVE(CLR_E_ARGUMENT_NULL) + + +// Correspondence between CLR C# and C++ native types: +// CLR Type C/C++ type C/C++ Ref Type + +// System.Byte unsigned char unsigned char& +// System.UInt16 unsigned short int unsigned short int& +// System.UInt32 unsigned int unsigned int& +// System.UInt64 unsigned __int64 unsigned __int64& +// System.Char char char & +// System.SByte signed char signed char & +// System.Int16 signed short int signed short int& +// System.Int32 signed int signed int& +// System.Int64 signed __int64 signed __int64& +// System.Single float float& +// System.Double double double& +// System.String const char * char * +// System.Byte[] unsigned char * Same as C/C++ type + +// Forward declaration for managed stack frame. +// This is internal CLR type, reference to managed stack frame is exposed to marshaling code. +struct CLR_RT_StackFrame; +/********************************************************************** +** +** Forward structure declarations . +** CLR_RT_HeapBlock - generic structure that keeps C# basic types +** CLR_RT_HeapBlock_NativeEventDispatcher - Object that supports managed callback initiated by Interrupts +**********************************************************************/ +struct CLR_RT_HeapBlock; +struct CLR_RT_HeapBlock_NativeEventDispatcher; + +// Do not support marshaling of struct and class. For these types we create params of CLR_RT_HeapBlock* +// and then set it to zero. +typedef CLR_RT_HeapBlock* UNSUPPORTED_TYPE; + +#define CLR_RT_HEAP_BLOCK_SIZE 12 + +#define NANOCLR_NATIVE_DECLARE(mtd) static HRESULT mtd( CLR_RT_StackFrame& stack ) + +typedef HRESULT (*CLR_RT_MethodHandler)( CLR_RT_StackFrame& stack ); + +struct CLR_RT_NativeAssemblyData + +{ // Assembly name or static name provided by driver developer to enable interrups. + const char *m_szAssemblyName; + + // Check sum for the assembly. + unsigned int m_checkSum; + + // Pointer to array of functions that implement native methods. + // It could be different type of the function depending if it is assembly Interop Method + // or function enabling Interrupts by user driver. + const void *m_pNativeMethods; + + // Assembly version + CLR_RECORD_VERSION m_Version; +}; + +// Looks up in interop assemblies table for assembly with specified name. +const CLR_RT_NativeAssemblyData *GetAssemblyNativeData( const char *lpszAssemblyName ); + +// C++ by value parameters ( not reference types ). +/********************************************************************** +** +** Functions: Interop_Marshal_* +** +** Synopsis: This group of functions retrienves by value parameters ( not reference types ) +** Each function gets reference to managed stack frame in index of parameter to extract. +** The C++ value is returned in "param". +** +** Arguments: [stackFrame] - Reference to the managed stack frame. +** [paramIndex] - Index of parameter passed from managed code. This parameter will be updated now. +** [param] - Reference to native C++ variable. Filled by the function. +** This variable is filled with value passed from managed code. +** +** Returns: S_OK on success or error in case of paramter mismatch or invalid data passed from managed code. +**********************************************************************/ + +HRESULT Interop_Marshal_bool ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, bool ¶m ); +HRESULT Interop_Marshal_UINT8 ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, unsigned char ¶m ); +HRESULT Interop_Marshal_UINT16( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, unsigned short int ¶m ); +HRESULT Interop_Marshal_UINT32( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, unsigned int ¶m ); +HRESULT Interop_Marshal_UINT64( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, unsigned __int64 ¶m ); +HRESULT Interop_Marshal_CHAR ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, char ¶m ); +HRESULT Interop_Marshal_INT8 ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, signed char ¶m ); +HRESULT Interop_Marshal_INT16 ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, signed short int ¶m ); +HRESULT Interop_Marshal_INT32 ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, signed int ¶m ); +HRESULT Interop_Marshal_INT64 ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, signed __int64 ¶m ); +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) +HRESULT Interop_Marshal_float ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, float ¶m ); +HRESULT Interop_Marshal_double( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, double ¶m ); + +#else +HRESULT Interop_Marshal_float ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, signed int ¶m ); +HRESULT Interop_Marshal_double( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, signed __int64 ¶m ); +#endif + +HRESULT Interop_Marshal_LPCSTR( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, const char* ¶m ); +// For unsupported types we set param to NULL. +HRESULT Interop_Marshal_UNSUPPORTED_TYPE( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, UNSUPPORTED_TYPE ¶m ); +/********************************************************************** +** +** Functions: Interop_Marshal_*_ARRAY +** +** Synopsis: This group of functions retrienves C++ by value parameters ( not reference types ) +** Each function gets reference to managed stack frame in index of parameter to extract. +** The C++ value is returned in "param". +** +** Arguments: [stackFrame] - Reference to the managed stack frame. +** [paramIndex] - Index of parameter passed from managed code. This parameter will be updated now. +** [pByteParam] - Reference to pointer filled by the function. +** On return pParam points to native C++ array with values passed from managed code. +** This variable is filled with value passed from managed code. +** [arraySize] - Count of elements in array. Filled by the function. +** +** Returns: S_OK on success or error in case of paramter mismatch or invalid data passed from managed code. +**********************************************************************/ + + +template class CLR_RT_TypedArray + +{ + T *m_pData; + unsigned int m_ElemCount; + +friend HRESULT Interop_Marshal_bool_ARRAY ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray &typedArray ); +friend HRESULT Interop_Marshal_UINT8_ARRAY ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray &typedArray ); +friend HRESULT Interop_Marshal_UINT16_ARRAY( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray &typedArray ); +friend HRESULT Interop_Marshal_UINT32_ARRAY( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray &typedArray ); +friend HRESULT Interop_Marshal_UINT64_ARRAY( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray &typedArray ); +friend HRESULT Interop_Marshal_CHAR_ARRAY ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray &typedArray ); +friend HRESULT Interop_Marshal_INT8_ARRAY ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray &typedArray ); +friend HRESULT Interop_Marshal_INT16_ARRAY ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray &typedArray ); +friend HRESULT Interop_Marshal_INT32_ARRAY ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray &typedArray ); +friend HRESULT Interop_Marshal_INT64_ARRAY ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray &typedArray ); + +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) +friend HRESULT Interop_Marshal_float_ARRAY ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray &typedArray ); +friend HRESULT Interop_Marshal_double_ARRAY( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray &typedArray ); +#else +friend HRESULT Interop_Marshal_float_ARRAY ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray &typedArray ); +friend HRESULT Interop_Marshal_double_ARRAY( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray &typedArray ); + +#endif + + +public : + CLR_RT_TypedArray() { m_pData = NULL; m_ElemCount = 0; } + + T GetValue( unsigned int i ) { return m_pData[ i ];} + void SetValue( unsigned int i, T &val ) { m_pData[ i ] = val; } + T& operator[]( unsigned int i ) { return m_pData[ i ];} + + unsigned int GetSize() { return m_ElemCount; } + + // Direct access to buffer is provided for cases when other + // native functions require access to buffer and cannot use CLR_RT_TypedArray object + T *GetBuffer() { return m_pData; } + + }; + +typedef CLR_RT_TypedArray CLR_RT_TypedArray_CHAR; +typedef CLR_RT_TypedArray CLR_RT_TypedArray_UINT8; +typedef CLR_RT_TypedArray CLR_RT_TypedArray_UINT16; +typedef CLR_RT_TypedArray CLR_RT_TypedArray_UINT32; +typedef CLR_RT_TypedArray CLR_RT_TypedArray_UINT64; +typedef CLR_RT_TypedArray CLR_RT_TypedArray_INT8; +typedef CLR_RT_TypedArray CLR_RT_TypedArray_INT16; +typedef CLR_RT_TypedArray CLR_RT_TypedArray_INT32; +typedef CLR_RT_TypedArray CLR_RT_TypedArray_INT64; +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) +typedef CLR_RT_TypedArray CLR_RT_TypedArray_float; +typedef CLR_RT_TypedArray CLR_RT_TypedArray_double; +#else +typedef CLR_RT_TypedArray CLR_RT_TypedArray_float; +typedef CLR_RT_TypedArray CLR_RT_TypedArray_double; + + +#endif + +HRESULT Interop_Marshal_bool_ARRAY ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_UINT8 &typedArray ); +HRESULT Interop_Marshal_UINT8_ARRAY ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_UINT8 &typedArray ); +HRESULT Interop_Marshal_UINT16_ARRAY( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_UINT16 &typedArray ); +HRESULT Interop_Marshal_UINT32_ARRAY( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_UINT32 &typedArray ); +HRESULT Interop_Marshal_UINT64_ARRAY( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_UINT64 &typedArray ); +HRESULT Interop_Marshal_CHAR_ARRAY ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_CHAR &typedArray ); +HRESULT Interop_Marshal_INT8_ARRAY ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_INT8 &typedArray ); +HRESULT Interop_Marshal_INT16_ARRAY ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_INT16 &typedArray ); +HRESULT Interop_Marshal_INT32_ARRAY ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_INT32 &typedArray ); +HRESULT Interop_Marshal_INT64_ARRAY ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_INT64 &typedArray ); +HRESULT Interop_Marshal_float_ARRAY ( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_float &typedArray ); +HRESULT Interop_Marshal_double_ARRAY( const CLR_RT_StackFrame &stackFrame, unsigned int paramIndex, CLR_RT_TypedArray_double &typedArray ); + +/********************************************************************** +** +** Functions: SetResult_* +** +** Synopsis: This group of functions set value returned by managed method call. +** Value passed to this function will be the return value of the managed function. +** +** Arguments: [stackFrame] - Reference to the managed stack frame. +** [value] - Return value. This value is stored on managed stack frame and passed to managed code. +**********************************************************************/ + +void SetResult_bool ( CLR_RT_StackFrame &stackFrame, bool value ); +void SetResult_CHAR ( CLR_RT_StackFrame &stackFrame, char value ); +void SetResult_INT8 ( CLR_RT_StackFrame &stackFrame, signed char value ); +void SetResult_INT16 ( CLR_RT_StackFrame &stackFrame, signed short int value ); +void SetResult_INT32 ( CLR_RT_StackFrame &stackFrame, signed int value ); +void SetResult_INT64 ( CLR_RT_StackFrame &stackFrame, signed __int64 value ); +void SetResult_UINT8 ( CLR_RT_StackFrame &stackFrame, unsigned char value ); +void SetResult_UINT16( CLR_RT_StackFrame &stackFrame, unsigned short int value ); +void SetResult_UINT32( CLR_RT_StackFrame &stackFrame, unsigned int value ); +void SetResult_UINT64( CLR_RT_StackFrame &stackFrame, unsigned __int64 value ); +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) +void SetResult_float ( CLR_RT_StackFrame &stackFrame, float value ); +void SetResult_double( CLR_RT_StackFrame &stackFrame, double value ); +#else +void SetResult_float ( CLR_RT_StackFrame &stackFrame, signed int value ); +void SetResult_double( CLR_RT_StackFrame &stackFrame, signed __int64 value ); + +#endif + +void SetResult_LPCSTR( CLR_RT_StackFrame &stackFrame, const char* value ); + +/********************************************************************** +** +** Functions: Interop_Marshal_LoadRef_* +** +** Synopsis: This group of functions pointer to reference parameter passed from managed code. +** On return of this function pParam points to reference parameter of managed code. +** Native code can retrieve and modidy the reference parameter using pParam +** +** Arguments: [stackFrame] - Reference to the managed stack frame. +** [paramIndex] - Index of parameter passed from managed code. This parameter will be updated now. +** [pByteParam] - Reference to pointer filled by the function. +** On return pParam points to native C++ array with values passed from managed code. +** This variable is filled with value passed from managed code. +** [pParam] - Address of reference parameter passed from managed code. Filled by the function. +** +** Returns: S_OK on success or error in case of paramter mismatch or invalid data passed from managed code. +**********************************************************************/ +HRESULT Interop_Marshal_bool_ByRef ( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, unsigned char *&pParam ); +HRESULT Interop_Marshal_UINT8_ByRef ( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, unsigned char *&pParam ); +HRESULT Interop_Marshal_UINT16_ByRef( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, unsigned short int *&pParam ); +HRESULT Interop_Marshal_UINT32_ByRef( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, unsigned int *&pParam ); +HRESULT Interop_Marshal_UINT64_ByRef( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, unsigned __int64 *&pParam ); +HRESULT Interop_Marshal_CHAR_ByRef ( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, char *&pParam ); +HRESULT Interop_Marshal_INT8_ByRef ( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, signed char *&pParam ); +HRESULT Interop_Marshal_INT16_ByRef ( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, signed short int *&pParam ); +HRESULT Interop_Marshal_INT32_ByRef ( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, signed int *&pParam ); +HRESULT Interop_Marshal_INT64_ByRef ( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, signed __int64 *&pParam ); +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) +HRESULT Interop_Marshal_float_ByRef ( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, float *&pParam ); +HRESULT Interop_Marshal_double_ByRef( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, double *&pParam ); +#else +HRESULT Interop_Marshal_float_ByRef ( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, signed int *&pParam ); +HRESULT Interop_Marshal_double_ByRef( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, signed __int64 *&pParam ); + +#endif + + +// For unsuppoted types return NULL reference + +HRESULT Interop_Marshal_UNSUPPORTED_TYPE_ByRef( const CLR_RT_StackFrame &stackFrame, void *pHeapBlock, unsigned int paramIndex, UNSUPPORTED_TYPE *&pParam ); +/********************************************************************** +** +** Function: Interop_Marshal_StoreRef +** +** Synopsis: This function is used to store updated parameter or basic type passed by reference from managed code. +** It stores data from heap block pointed by pVoidHeapBlock back to the managed stack frame. +** +** Arguments: [stackFrame] - Reference to the managed stack frame. +** [pVoidHeapBlock] - Pointer to heap block that keeps updated basic type value +** [paramIndex] - Index of parameter passed from managed code. This parameter will be updated now. +** +** Returns: S_OK on success or error from StoreToReference. Error return would cause exception thrown in managed code. +**********************************************************************/ +HRESULT Interop_Marshal_StoreRef( CLR_RT_StackFrame &stackFrame, void *pVoidHeapBlock, unsigned int paramIndex ); + +/********************************************************************** +** +** Function: Interop_Marshal_RetrieveManagedObject +** +** Synopsis: Retrieves pointer to managed object from managed stack frame. +** +** Arguments: [stackFrame] - Reference to the managed stack frame. +** +** Returns: Pointer to managed object or NULL in case of error. +**********************************************************************/ +CLR_RT_HeapBlock* Interop_Marshal_RetrieveManagedObject( CLR_RT_StackFrame &stackFrame ); + +/********************************************************************** +** +** Functions: Interop_Marshal_GetField_ +** +** Synopsis: Retrieves C++ reference ( pointer ) to the field in managed object. +** +** Arguments: [pThis] - Pointer to the managed object retrieved by Interop_Marshal_RetrieveManagedObject. +** [fieldIndex] - Field index. +** +** Returns: Reference to the field. +**********************************************************************/ +bool &Interop_Marshal_GetField_bool ( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ); +unsigned char &Interop_Marshal_GetField_UINT8 ( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ); +unsigned short int &Interop_Marshal_GetField_UINT16( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ); +unsigned int &Interop_Marshal_GetField_UINT32( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ); +unsigned __int64 &Interop_Marshal_GetField_UINT64( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ); +char &Interop_Marshal_GetField_CHAR ( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ); +signed char &Interop_Marshal_GetField_INT8 ( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ); +signed short int &Interop_Marshal_GetField_INT16 ( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ); +signed int &Interop_Marshal_GetField_INT32 ( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ); +signed __int64 &Interop_Marshal_GetField_INT64 ( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ); +//----------------- Float point types - float and double +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) +float &Interop_Marshal_GetField_float ( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ); +double &Interop_Marshal_GetField_double( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ); +#else +signed int &Interop_Marshal_GetField_float ( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ); +signed __int64 &Interop_Marshal_GetField_double( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ); +#endif + +// For all other unsupported types we always return NULL reference. +UNSUPPORTED_TYPE &Interop_Marshal_GetField_UNSUPPORTED_TYPE( CLR_RT_HeapBlock *pThis, unsigned int fieldIndex ); + +/********************************************************************** +** +** Function Signatures that should be supported by drivers to enable managed callbacks. +** +** InitializeInterruptsProc +** This driver function is called in native code by constructor of managed NativeEventDispatcher object. +** Parameters: +** [pContext] - Pointer to the context that should be passed to the ISR ( INterrupt Service Routine ). +** [userData] - User data passed to constructor of NativeEventDispatcher. +**********************************************************************/ +typedef HRESULT (*InitializeInterruptsProc )( CLR_RT_HeapBlock_NativeEventDispatcher *pContext, unsigned __int64 userData ); + +/********************************************************************** +** EnableorDisableInterruptsProc +** This function is called by EnableInterrupt/DisableInterrupt functions of managed NativeEventDispatcher object. +** It should enable or disable HW interrupts. +** [pContext] - Pointer to the context, same as passed to InitializeInterruptsProc +** [fEnable] - If "true" - enable interrupts +** If "false" - disable interrupts +**********************************************************************/ +typedef HRESULT (*EnableorDisableInterruptsProc)( CLR_RT_HeapBlock_NativeEventDispatcher *pContext, bool fEnable ); + +/********************************************************************** +** +** CleanupInterruptsProc +** This function is called to release hardware that generates interrups and release associated resources +** [pContext] - Pointer to the context, same as passed to InitializeInterruptsProc +** +**********************************************************************/ +typedef HRESULT (*CleanupInterruptsProc)( CLR_RT_HeapBlock_NativeEventDispatcher *pContext ); + +/********************************************************************** +** +** InterruptServiceProc +** This is the prototype for the interrupt service routie. +** [pContext] - Pointer to the context, same as passed to InitializeInterruptsProc +** +** This function should call SaveNativeEventToHALQueue in order to create managed callback. +** The minimal implementation for this function would be: +** static void ISR_TestProc( CLR_RT_HeapBlock_NativeEventDispatcher *pContext ) +** +** { +** GLOBAL_LOCK(); +** // To do - Initialize userData1 and userData2 to userData. +** unsigned int userData1; +** unsigned int userData2; +** // Saves data to queue. Each call to SaveNativeEventToHALQueue initiates managed callback. +** SaveNativeEventToHALQueue( pContext, userData1, userData2 ); +** } +**********************************************************************/ +typedef HRESULT (*InterruptServiceProc)( CLR_RT_HeapBlock_NativeEventDispatcher *pContext ); + + + +/********************************************************************** +** +** Structure that keeps pointers to driver functions. +** The driver functions are accessed by CLR through global instance of this structure. +** See Spot_InteropSample_Native_Microsoft_SPOT_Interop_TestCallback.cpp file for use of this structure. +** +**********************************************************************/ +struct CLR_RT_DriverInterruptMethods + +{ + InitializeInterruptsProc initProcessor; + EnableorDisableInterruptsProc enableProcessor; + CleanupInterruptsProc cleanupProcessor; +}; + +// Randomly generated 32 bit number. +// This check sum validates that m_pNativeMethods points to CLR_RT_DriverInterruptMethods structure +#define DRIVER_INTERRUPT_METHODS_CHECKSUM 0xf32f4c3e + +// Creates instance of CLR_RT_HeapBlock_NativeEventDispatcher. +CLR_RT_HeapBlock_NativeEventDispatcher *CreateNativeEventInstance( CLR_RT_StackFrame& stack ); + +// Saves data from ISR. The data from this queue is used to call managed callbacks. +// Should be called from ISR. + void SaveNativeEventToHALQueue( CLR_RT_HeapBlock_NativeEventDispatcher *pContext, uint32_t data1, uint32_t data2 ); + +// Cleans up the data in the queue after interrupts were closed and no managed callbacks are expected. + void CleanupNativeEventsFromHALQueue( CLR_RT_HeapBlock_NativeEventDispatcher *pContext ); + +void CLR_RetrieveCurrentMethod( unsigned int& assmIdx, unsigned int& methodIdx ); + +void CLR_SoftReboot(); + +void CLR_DebuggerBreak(); + +#endif // _NANOCLR_INTEROP_H_ + + diff --git a/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Messaging.h b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Messaging.h new file mode 100644 index 00000000..854e056e --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Messaging.h @@ -0,0 +1,143 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _NANOCLR_MESSAGING_H_ +#define _NANOCLR_MESSAGING_H_ + +#include +#include + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +typedef bool (*CLR_Messaging_CommandHandler)( WP_Message* msg ); + +struct CLR_Messaging_CommandHandlerLookup +{ + CLR_Messaging_CommandHandler hnd; + unsigned int cmd; +}; + +struct CLR_Messaging_CommandHandlerLookups +{ + const CLR_Messaging_CommandHandlerLookup* table; + CLR_UINT32 size; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +struct CLR_Messaging_Commands +{ + static const unsigned int c_Messaging_Query = 0x00020090; // Checks the presence of an EndPoint. + static const unsigned int c_Messaging_Send = 0x00020091; // Sends a message to an EndPoint. + static const unsigned int c_Messaging_Reply = 0x00020092; // Response from an EndPoint. + + struct Messaging_Query + { + CLR_RT_HeapBlock_EndPoint::Address m_addr; + + struct Reply + { + CLR_UINT32 m_found; + CLR_RT_HeapBlock_EndPoint::Address m_addr; + }; + }; + + struct Messaging_Send + { + CLR_RT_HeapBlock_EndPoint::Address m_addr; + unsigned char m_data[ 1 ]; + + struct Reply + { + CLR_UINT32 m_found; + CLR_RT_HeapBlock_EndPoint::Address m_addr; + }; + }; + + struct Messaging_Reply + { + CLR_RT_HeapBlock_EndPoint::Address m_addr; + unsigned char m_data[ 1 ]; + + struct Reply + { + CLR_UINT32 m_found; + CLR_RT_HeapBlock_EndPoint::Address m_addr; + }; + }; + +}; + + +struct CLR_Messaging +{ + struct CachedMessage : public CLR_RT_HeapBlock_Node + { + static const CLR_UINT32 c_Processed = 0x00000001; + + CLR_UINT32 m_flags; + + CLR_UINT32 m_size; + CLR_INT64 m_lastSeen; + WP_Message m_message; + }; + + //--// + + CLR_Messaging_CommandHandlerLookups m_Lookup_Requests[ 2 ]; + CLR_Messaging_CommandHandlerLookups m_Lookup_Replies[ 2 ]; + + COM_HANDLE m_port; + + //--// + + static HRESULT CreateInstance(); + + void Initialize(const CLR_Messaging_CommandHandlerLookup* requestLookup, const CLR_UINT32 requestLookupCount, const CLR_Messaging_CommandHandlerLookup* replyLookup, const CLR_UINT32 replyLookupCount ); + void Cleanup(); + + static HRESULT DeleteInstance(); + + //void ProcessCommands(); + + bool SendEvent ( unsigned int cmd, unsigned int payloadSize, unsigned char* payload, unsigned int flags ); + static void BroadcastEvent( unsigned int cmd, unsigned int payloadSize, unsigned char* payload, unsigned int flags ); + + static bool App_ProcessHeader ( void* state, WP_Message* msg ); + static bool App_ProcessPayload( void* state, WP_Message* msg ); + static bool App_Release ( void* state, WP_Message* msg ); + + bool IsDebuggerInitialized() { return m_fDebuggerInitialized; } + void InitializeDebugger() { m_fDebuggerInitialized = (DebuggerPort_Initialize( m_port ) == true); } + +private: + + bool m_fInitialized; + bool m_fDebuggerInitialized; + + bool AllocateAndQueueMessage( CLR_UINT32 cmd, unsigned int length, unsigned char* data, CLR_RT_HeapBlock_EndPoint::Port port, CLR_RT_HeapBlock_EndPoint::Address addr, CLR_UINT32 found ); + + bool ProcessHeader ( WP_Message* msg ); + + + + + + + +public: + bool ProcessPayload( WP_Message* msg ); + static bool Messaging_Query ( WP_Message* msg ); + static bool Messaging_Query__Reply ( WP_Message* msg ); + static bool Messaging_Send ( WP_Message* msg ); + static bool Messaging_Send__Reply ( WP_Message* msg ); + static bool Messaging_Reply ( WP_Message* msg ); + static bool Messaging_Reply__Reply ( WP_Message* msg ); +}; + +//--// + +#endif // _NANOCLR_MESSAGING_H_ + diff --git a/source/native/nf-interpreter/src/CLR/Include/nanoCLR_ParseOptions.h b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_ParseOptions.h new file mode 100644 index 00000000..497e0a1c --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_ParseOptions.h @@ -0,0 +1,136 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _NANOCLR_PARSEOPTIONS_H_ +#define _NANOCLR_PARSEOPTIONS_H_ + +#include + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#if defined(_WIN32) + +struct CLR_RT_ParseOptions +{ + typedef std::map< std::wstring, CLR_RT_Buffer* > BufferMap; + typedef BufferMap::iterator BufferMapIter; + + struct Parameter + { + const wchar_t* m_szName; + const wchar_t* m_szDescription; + + Parameter( const wchar_t* szName, const wchar_t* szDescription ); + + virtual bool Parse( const wchar_t* val ) = 0; + }; + + typedef std::vector< Parameter* > ParameterList; + typedef ParameterList::iterator ParameterListIter; + + CLR_RT_StringVector CommandLineArgs; + + //--// + + struct Parameter_Generic : Parameter + { + std::wstring m_data; + + Parameter_Generic( const wchar_t* szName, const wchar_t* szDescription ); + + virtual bool Parse( const wchar_t* arg ); + }; + + struct Parameter_String : Parameter + { + std::wstring m_dataParsed; + std::wstring* m_dataPtr; + + Parameter_String( std::wstring* data, const wchar_t* szName, const wchar_t* szDescription ); + + virtual bool Parse( const wchar_t* arg ); + }; + + struct Parameter_Boolean : Parameter + { + bool m_dataParsed; + bool* m_dataPtr; + + Parameter_Boolean( bool* data, const wchar_t* szName, const wchar_t* szDescription ); + + virtual bool Parse( const wchar_t* arg ); + }; + + struct Parameter_Integer : Parameter + { + int m_dataParsed; + int* m_dataPtr; + + Parameter_Integer( int* data, const wchar_t* szName, const wchar_t* szDescription ); + + virtual bool Parse( const wchar_t* arg ); + }; + + struct Parameter_Float : Parameter + { + float m_dataParsed; + float* m_dataPtr; + + Parameter_Float( float* data, const wchar_t* szName, const wchar_t* szDescription ); + + virtual bool Parse( const wchar_t* arg ); + }; + + //--// + + struct Command + { + const wchar_t* m_szName; + const wchar_t* m_szDescription; + ParameterList m_params; + + Command( const wchar_t* szName, const wchar_t* szDescription ); + + virtual bool Parse( CLR_RT_StringVector& argv, size_t& pos, CLR_RT_ParseOptions& options ); + + virtual HRESULT Execute(); + }; + + typedef std::list< Command* > CommandList; + typedef CommandList::iterator CommandListIter; + + //--// + + struct Command_SetFlag : Command + { + bool m_dataParsed; + bool* m_dataPtr; + + Command_SetFlag( bool* data, const wchar_t* szName, const wchar_t* szDescription ); + + virtual bool Parse( CLR_RT_StringVector& argv, size_t& pos, CLR_RT_ParseOptions& options ); + }; + + //--// + + bool m_fVerbose; + CommandList m_commands; + + //--// + + CLR_RT_ParseOptions(); + + HRESULT ExtractOptionsFromFile( const wchar_t* szFileName ); + + HRESULT ReprocessOptions(); + HRESULT ProcessOptions( CLR_RT_StringVector& vec ); + void PushArguments ( int argc, wchar_t* argv[], CLR_RT_StringVector& vec ); + + virtual void Usage(); +}; + +#endif + +#endif // _NANOCLR_PARSEOPTIONS_H_ diff --git a/source/native/nf-interpreter/src/CLR/Include/nanoCLR_PlatformDef.h b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_PlatformDef.h new file mode 100644 index 00000000..e3059cf1 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_PlatformDef.h @@ -0,0 +1,246 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _NANOCLR_PLATFORMDEF_H_ +#define _NANOCLR_PLATFORMDEF_H_ + +//#include + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// DEFINITIONS +#define NANOCLR_VALIDATE_HEAP_0_None 0 // No Trace +#define NANOCLR_VALIDATE_HEAP_1_HeapBlocksAndUnlink 1 // Validate HeapBlocks and Unlink. +#define NANOCLR_VALIDATE_HEAP_2_DblLinkedList 2 // Validate a DblLinkedList before each operation. +#define NANOCLR_VALIDATE_HEAP_3_Compaction 3 // Trace Compaction +#define NANOCLR_VALIDATE_HEAP_4_CompactionPlus 4 // Trace Compaction Plus + +#define NANOCLR_MAX_ASSEMBLY_NAME 128 + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// FEATURES + + +#if defined(PLATFORM_EMULATED_FLOATINGPOINT) +#define NANOCLR_EMULATED_FLOATINGPOINT // use the fixed point floating point notation in the clr codes +#endif + +#if defined(NANOCLR_USE_APPDOMAINS) +#define NANOCLR_APPDOMAINS // enables application doman support +#endif +#define NANOCLR_TRACE_EXCEPTIONS // enables exception dump support +#define NANOCLR_TRACE_ERRORS // enables rich exception dump support +#if defined(DEBUG) || defined(_DEBUG) +#define NANOCLR_TRACE_STACK // enables rich eval stack tracing +#endif +//#define TINYCLR_TRACE_INSTRUCTIONS 1 // enables tracing of instructions execution +//#define NANOCLR_TRACE_HRESULT // enable tracing of HRESULTS from interop libraries + +//-o-//-o-//-o-//-o-//-o-//-o-// +// PLATFORMS +//-o-//-o-//-o-//-o-//-o-//-o-// + + +//--// +// Setting the threshold value to start Garbagge collector +// PLATFORM_DEPENDENT_HEAP_SIZE_THRESHOLD should set in the file platform.settings file, eg sam7x_ek.settings. +// defaults are 32Kb and 48 kb for lower and upper threshold respectively + +#ifdef PLATFORM_DEPENDENT_HEAP_SIZE_THRESHOLD +#define HEAP_SIZE_THRESHOLD PLATFORM_DEPENDENT_HEAP_SIZE_THRESHOLD +#else +#define HEAP_SIZE_THRESHOLD 48 * 1024 +#endif + +#ifdef PLATFORM_DEPENDENT_HEAP_SIZE_THRESHOLD_UPPER +#define HEAP_SIZE_THRESHOLD_UPPER PLATFORM_DEPENDENT_HEAP_SIZE_THRESHOLD_UPPER +#else +#define HEAP_SIZE_THRESHOLD_UPPER HEAP_SIZE_THRESHOLD + 16 * 1024 +#endif + +//--// + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// WINDOWS +#if defined(_WIN32) + +#define NANOCLR_GC_VERBOSE +#define NANOCLR_TRACE_MEMORY_STATS +#define NANOCLR_PROFILE_NEW +#define NANOCLR_PROFILE_NEW_CALLS +#define NANOCLR_PROFILE_NEW_ALLOCATIONS +#if defined(DEBUG) || defined(_DEBUG) +#define NANOCLR_VALIDATE_HEAP NANOCLR_VALIDATE_HEAP_2_DblLinkedList +//#define NANOCLR_TRACE_MALLOC +#define NANOCLR_FILL_MEMORY_WITH_DIRTY_PATTERN +#define NANOCLR_TRACE_EARLYCOLLECTION +#define NANOCLR_DELEGATE_PRESERVE_STACK +//#define NANOCLR_VALIDATE_APPDOMAIN_ISOLATION +#define NANOCLR_TRACE_HRESULT // enable tracing of HRESULTS from interop libraries +#else //RELEASE +#define NANOCLR_VALIDATE_HEAP NANOCLR_VALIDATE_HEAP_0_None +#endif +#define NANOCLR_ENABLE_SOURCELEVELDEBUGGING +#endif + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// ARM & ESP32 +#if defined(PLATFORM_ARM) || defined(PLATFORM_ESP32) +// #define NANOCLR_STRESS_GC +// #define NANOCLR_GC_VERBOSE +// #define NANOCLR_PROFILE_NEW +// #define NANOCLR_PROFILE_NEW_CALLS +// #define NANOCLR_PROFILE_NEW_ALLOCATIONS +// #define NANOCLR_TRACE_MEMORY_STATS +// #define NANOCLR_FORCE_GC_BEFORE_EVERY_ALLOCATION +#define NANOCLR_VALIDATE_HEAP NANOCLR_VALIDATE_HEAP_0_CompactionPlus +#endif + +//-o-//-o-//-o-//-o-//-o-//-o-// +// RULES AND DEPENDENCIES +//-o-//-o-//-o-//-o-//-o-//-o-// + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// GENERAL RTM RULES +#if defined(BUILD_RTM) || defined(PLATFORM_NO_CLR_TRACE) +#undef NANOCLR_TRACE_MEMORY_STATS +#undef NANOCLR_TRACE_EXCEPTIONS +#undef NANOCLR_TRACE_ERRORS +#undef NANOCLR_TRACE_EARLYCOLLECTION +#undef NANOCLR_VALIDATE_HEAP +#undef NANOCLR_FILL_MEMORY_WITH_DIRTY_PATTERN +#endif + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// TRACE DEPENDENCIES +#if defined(_WIN32) +#define NANOCLR_OPCODE_NAMES +#define NANOCLR_OPCODE_PARSER +#define NANOCLR_OPCODE_STACKCHANGES +#endif + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#if !defined(NANOCLR_VALIDATE_HEAP) +#define NANOCLR_VALIDATE_HEAP NANOCLR_VALIDATE_HEAP_0_None +#endif + +#if defined(NANOCLR_PROFILE_NEW_CALLS) && !defined(NANOCLR_PROFILE_HANDLER) +#define NANOCLR_PROFILE_HANDLER +#endif + +#if defined(NANOCLR_PROFILE_NEW_CALLS) && !defined(NANOCLR_PROFILE_NEW) +#define NANOCLR_PROFILE_NEW +#endif + +#if defined(NANOCLR_PROFILE_NEW_ALLOCATIONS) && !defined(NANOCLR_PROFILE_NEW) +#define NANOCLR_PROFILE_NEW +#endif + +//-o-//-o-//-o-//-o-//-o-//-o-// +// CODE +//-o-//-o-//-o-//-o-//-o-//-o-// + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// LANGUAGE +#if defined(_WIN32) +#define PROHIBIT_ALL_CONSTRUCTORS(cls) \ + private: \ + cls(); \ + cls( cls& ); \ + cls& operator=( const cls& ) + +#define PROHIBIT_COPY_CONSTRUCTORS(cls) \ + public: \ + cls() {} \ + private: \ + cls( cls& ); \ + cls& operator=( const cls& ) + +#define PROHIBIT_COPY_CONSTRUCTORS2(cls) \ + private: \ + cls( cls& ); \ + cls& operator=( const cls& ) + +#define LONGLONGCONSTANT(v) (v##I64) +#define ULONGLONGCONSTANT(v) (v##UI64) +#endif + +#if defined(PLATFORM_ARM) | defined(PLATFORM_ESP32) +#define PROHIBIT_ALL_CONSTRUCTORS(cls) \ + private: \ + cls(); \ + cls( cls& ); \ + cls& operator=( const cls& ) + +#define PROHIBIT_COPY_CONSTRUCTORS(cls) \ + public: \ + cls() {} \ + private: \ + cls( cls& ); \ + cls& operator=( const cls& ) + +#define PROHIBIT_COPY_CONSTRUCTORS2(cls) \ + private: \ + cls( cls& ); \ + cls& operator=( const cls& ) + +#define LONGLONGCONSTANT(v) (v##ll) +#define ULONGLONGCONSTANT(v) (v##ull) +#endif + +//////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////// +// INCLUDES +#if defined(_WIN32) + +#define _WIN32_WINNT 0x0501 + +//Unsafe string functions be avoided, but there isn't a safe crt for the arm, so +//a bunch of macros, cleanup code needs to be done first + +#include +#include +#include + +#include + +#include +#include +#include +#include + +#else + +#include + +#include +#include +#include +#include +#include + +#ifndef MAKE_HRESULT +#define MAKE_HRESULT(sev,fac,code) \ + ((HRESULT) (((unsigned long)(sev)<<31) | ((unsigned long)(fac)<<16) | ((unsigned long)(code))) ) +#endif + +#ifndef SEVERITY_SUCCESS +#define SEVERITY_SUCCESS 0 +#endif + +#ifndef SEVERITY_ERROR +#define SEVERITY_ERROR 1 +#endif + +#endif + +/////////////////////////////////////////////////////////////////////////////////////////////////// + +#include + +/////////////////////////////////////////////////////////////////////////////////////////////////// + +#endif // _NANOCLR_PLATFORMDEF_H_ diff --git a/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Profiling.h b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Profiling.h new file mode 100644 index 00000000..4bcc9f0c --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Profiling.h @@ -0,0 +1,219 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _NANOCLR_PROFILING_H_ +#define _NANOCLR_PROFILING_H_ + +#if defined(NANOCLR_PROFILE_NEW) + +/* + * See RFC2234 for Augmented Backus Naur form documentation. + * All terminal literals are bits, not ASCII characters. + * Bits are packed such that the first bit goes to the most significant bit, + * the second goes to the second-most significant, etc. + +short = 16BIT +int = 32BIT +long = 64BIT +pointer = 32BIT +datatype = 8BIT +typedef-idx = 32BIT +method-idx = 32BIT + nanoCLR Method_Idx value for identifying a specific function + +stream-packet = sequence-id length stream-payload + A chunk of data sent out over the WireProtocol. + +sequence-id = short + Number used to order the packets + +length = short + Number in bits in stream-payload + +stream-payload = *profiler-packet + Payload is a sequence of profiler packets. + +profiling-stream = *stream-payload + The reconstructed stream of data to be processed. + +profiler-packet = timestamp-packet / memory-layout-packet heapdump-start-packet / heapdump-root-packet / + heapdump-object-packet / heapdump-stop-packet + +timestamp-header = "0000001" +timestamp-time = long +timestamp-packet = timestamp-header timestamp-time + Marks time intervals to allow object lifetime estimates and histograms + +memory-layout-packet = memory-layout-header memory-layout-heap-address memory-layout-heap-length +memory-layout-header = "00000010" +memory-layout-heap-address = pointer +memory-layout-heap-length = int + Contains heap layout information useful for showing memory usage statistics. + +heapdump = heapdump-start-packet *heapdump-root-packet *heapdump-object-packet heapdump-stop-packet + Heapdumps always occur in this form. All roots are listed before all objects, and both roots and objects fall between + a pair of 'start' and 'stop' packets. Heap dumps may be split up across stream-payload boundaries, but they may not be + nested, and packets may not be sent in any other order. + +heapdump-start-header = "00000011" +heapdump-start-packet = heapdump-start-header + Marks the beginning of a heap dump. Multiple can exist in the same profiling-stream + if and only if there is a heapdump-stop-packet between every pair of heapdump-start-packets. + +heapdump-root-packet = heapdump-root-header ( heapdump-root-stack / heapdump-root-other ) +heapdump-root-header = "00000011" + +heapdump-root-stack = heapdump-root-stack-header method-idx +heapdump-root-stack-header = "101" + +heapdump-root-other = heapdump-root-finalizer / heapdump-root-appdomain / heapdump-root-assembly / heapdump-root-thread +heapdump-root-finalizer = "001" +heapdump-root-appdomain = "010" +heapdump-root-assembly = "011" +heapdump-root-thread = "100" + +heapdump-object-packet = heapdump-object-header heapdump-object-type heapdump-object-references +heapdump-object-header = heapdump-object-address heapdump-object-size +heapdump-object-address = pointer +heapdump-object-size = short + Size is the number of HeapBlock chunks used, not the number of bytes used. + +heapdump-object-type = heapdump-object-classvaluetype / heapdump-object-array / heapdump-object-other + +heapdump-object-classvaluetype = heapdump-object-classvaluetype-header heapdump-object-classvaluetype-typedef +heapdump-object-classvaluetype-header = "00010001" / "00010010" +heapdump-object-classvaluetype-typedef = typedef-idx + +heapdump-object-array = heapdump-object-array-header heapdump-object-array-datatype heapdump-object-array-levels +heapdump-object-array-header = "00010011" +heapdump-object-array-typedef = typedef-idx +heapdump-object-array-levels = short + Rank of the array + +heapdump-object-special-cases = heapdump-object-classvaluetype-header / heapdump-object-array-header +heapdump-object-other = datatype + datatype must not be one of ; If it is, the appropriate special case should be used instead. + +heapdump-object-references = *heapdump-object-reference heapdump-object-end-of-references +heapdump-object-reference = "1" pointer +heapdump-object-end-of-references = "0" + +heapdump-stop-packet = heapdump-stop-header heapdump-stop-blocks-used + Used to mark the end of a specific heap-dump. Must not follow another + unless another came first. + +heapdump-stop-header = "00000110" +heapdump-stop-blocks-used = int + Reports how many heap-blocks were used by objects, including objects that might have been filtered out from reporting. + + */ + +class CLR_PRF_CMDS +{ + public: + static const CLR_UINT32 c_Profiling_Timestamp = 0x01; + static const CLR_UINT32 c_Profiling_Memory_Layout = 0x02; + + static const CLR_UINT32 c_Profiling_HeapDump_Start = 0x03; + static const CLR_UINT32 c_Profiling_HeapDump_Root = 0x04; + static const CLR_UINT32 c_Profiling_HeapDump_Object = 0x05; + static const CLR_UINT32 c_Profiling_HeapDump_Stop = 0x06; + + static const CLR_UINT32 c_Profiling_Calls_Call = 0x07; + static const CLR_UINT32 c_Profiling_Calls_Return = 0x08; + static const CLR_UINT32 c_Profiling_Calls_CtxSwitch = 0x09; + + static const CLR_UINT32 c_Profiling_Allocs_Alloc = 0x0a; + static const CLR_UINT32 c_Profiling_Allocs_Relloc = 0x0b; + static const CLR_UINT32 c_Profiling_Allocs_Delete = 0x0c; + + static const CLR_UINT32 c_Profiling_GarbageCollect_Begin = 0x0d; + static const CLR_UINT32 c_Profiling_GarbageCollect_End = 0x0e; + + static const CLR_UINT32 c_Profiling_HeapCompact_Begin = 0x0f; + static const CLR_UINT32 c_Profiling_HeapCompact_End = 0x10; + + class Bits + { + public: + static const CLR_UINT32 CommandHeader = 8; + static const CLR_UINT32 DataType = 8; + static const CLR_UINT32 NibbleCount = 3; + static const CLR_UINT32 RootTypes = 3; + static const CLR_UINT32 TimestampShift = 8; + static const CLR_UINT32 CallTimingShift = 4; + }; + + class RootTypes + { + public: + static const CLR_UINT32 Root_Finalizer = 0x01; + static const CLR_UINT32 Root_AppDomain = 0x02; + static const CLR_UINT32 Root_Assembly = 0x03; + static const CLR_UINT32 Root_Thread = 0x04; + static const CLR_UINT32 Root_Stack = 0x05; + }; +}; + +struct CLR_PRF_Profiler +{ + // This is not implemented: + // Write formatter functions to send only as many bits as needed for uint32,uint64 numbers, cast bytes, etc. + static HRESULT CreateInstance(); + static HRESULT DeleteInstance(); + + HRESULT Stream_Send(); + HRESULT Stream_Flush(); + + HRESULT Profiler_Cleanup(); + HRESULT DumpHeap(); + +#if defined(NANOCLR_PROFILE_NEW_CALLS) + HRESULT RecordContextSwitch( CLR_RT_Thread* nextThread ); + HRESULT RecordFunctionCall( CLR_RT_Thread* th, CLR_RT_MethodDef_Index md ); + HRESULT RecordFunctionReturn( CLR_RT_Thread* th, CLR_PROF_CounterCallChain& prof ); +#endif + +#if defined(NANOCLR_PROFILE_NEW_ALLOCATIONS) + void TrackObjectCreation( CLR_RT_HeapBlock* ptr ); + void TrackObjectDeletion( CLR_RT_HeapBlock* ptr ); + void TrackObjectRelocation(); + void RecordGarbageCollectionBegin(); + void RecordGarbageCollectionEnd(); + void RecordHeapCompactionBegin(); + void RecordHeapCompactionEnd(); +#endif + + void SendMemoryLayout(); + +private: + void SendTrue(); + void SendFalse(); + void Timestamp(); + void PackAndWriteBits( CLR_UINT32 value ); + void PackAndWriteBits( const CLR_RT_TypeDef_Index& typeDef ); + void PackAndWriteBits( const CLR_RT_MethodDef_Index& methodDef ); + CLR_RT_HeapBlock* FindReferencedObject( CLR_RT_HeapBlock* ref ); + HRESULT DumpRoots(); + void DumpRoot( CLR_RT_HeapBlock* root, CLR_UINT32 type, CLR_UINT32 flags, CLR_RT_MethodDef_Index* source ); + void DumpObject( CLR_RT_HeapBlock* ptr ); + void DumpEndOfRefsList(); + void DumpPointer( void* ref ); + void DumpSingleReference( CLR_RT_HeapBlock* ptr ); + void DumpListOfReferences( CLR_RT_DblLinkedList& list ); + void DumpListOfReferences( CLR_RT_HeapBlock* firstItem, CLR_UINT16 count ); + + CLR_RT_HeapBlock_MemoryStream* m_stream; + CLR_UINT16 m_packetSeqId; + CLR_UINT32 m_lastTimestamp; + CLR_IDX m_currentAssembly; + int m_currentThreadPID; +}; + +extern CLR_PRF_Profiler g_CLR_PRF_Profiler; + +#endif //defined(NANOCLR_PROFILE_NEW) +#endif // _NANOCLR_PROFILING_H_ + diff --git a/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Runtime.h b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Runtime.h new file mode 100644 index 00000000..72c940d6 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Runtime.h @@ -0,0 +1,3246 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _NANOCLR_RUNTIME_H_ +#define _NANOCLR_RUNTIME_H_ + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include +#include + +struct CLR_RADIAN +{ + short cos; + short sin; +}; + +extern const CLR_RADIAN c_CLR_radians[]; + +//--// + +#if defined(_WIN32) + +#include +#include +#include +#include +#include +#include +#include + +typedef std::set< std::wstring > CLR_RT_StringSet; +typedef CLR_RT_StringSet::iterator CLR_RT_StringSetIter; + +typedef std::map< std::string,int > CLR_RT_StringMap; +typedef CLR_RT_StringMap::iterator CLR_RT_StringMapIter; + +typedef std::vector< std::wstring > CLR_RT_StringVector; +typedef CLR_RT_StringVector::iterator CLR_RT_StringVectorIter; + +typedef std::map< std::wstring, CLR_UINT32 > CLR_RT_SymbolToAddressMap; +typedef CLR_RT_SymbolToAddressMap::iterator CLR_RT_SymbolToAddressMapIter; + +typedef std::map< CLR_UINT32, std::wstring > CLR_RT_AddressToSymbolMap; +typedef CLR_RT_AddressToSymbolMap::iterator CLR_RT_AddressToSymbolMapIter; + +#else + +#if NANOCLR_VALIDATE_HEAP >= NANOCLR_VALIDATE_HEAP_4_CompactionPlus +#include +#include +#endif + +#endif // #if defined(_WIN32) + +#if defined(_MSC_VER) +#pragma pack(push, NANOCLR_RUNTIME_H, 4) +#endif + +#if defined(_WIN32) +//--// + +#define _COM_SMRT_PTR(i) typedef _com_ptr_t<_com_IIID> i ## Ptr +#define _COM_SMRT_PTR_2(i,u) typedef _com_ptr_t<_com_IIID> i ## Ptr + + +_COM_SMRT_PTR(IXMLDOMDocument); +_COM_SMRT_PTR(IXMLDOMNode); + +class CLR_XmlUtil +{ + IXMLDOMDocumentPtr m_xddDoc; + IXMLDOMNodePtr m_xdnRoot; + HANDLE m_hEvent; // Used to abort a download. + unsigned long m_dwTimeout; // Used to limit a download. + + void Init (); + void Clean(); + + HRESULT LoadPost( /*[in] */ const wchar_t* szRootTag , + /*[out]*/ bool& fLoaded , + /*[out]*/ bool* fFound ); + + HRESULT CreateParser(); + +public: + CLR_XmlUtil( /*[in]*/ const CLR_XmlUtil& xml ); + CLR_XmlUtil( /*[in]*/ IXMLDOMDocument* xddDoc , /*[in]*/ const wchar_t* szRootTag = NULL ); + CLR_XmlUtil( /*[in]*/ IXMLDOMNode* xdnRoot = NULL, /*[in]*/ const wchar_t* szRootTag = NULL ); + + ~CLR_XmlUtil(); + + + CLR_XmlUtil& operator=( /*[in]*/ const CLR_XmlUtil& xml ); + CLR_XmlUtil& operator=( /*[in]*/ IXMLDOMNode* xdnRoot ); + + HRESULT DumpError(); + + HRESULT New ( /*[in]*/ IXMLDOMNode* xdnRoot , /*[in] */ bool fDeep = false ); + HRESULT New ( /*[in]*/ const wchar_t* szRootTag, /*[in] */ const wchar_t* szEncoding = L"utf-8" /*L"unicode"*/ ); + HRESULT Load ( /*[in ]*/ const wchar_t* szFile , /*[in]*/ const wchar_t* szRootTag, /*[out]*/ bool& fLoaded, /*[out]*/ bool* fFound = NULL ); + HRESULT LoadAsStream( /*[in ]*/ IUnknown* pStream , /*[in]*/ const wchar_t* szRootTag, /*[out]*/ bool& fLoaded, /*[out]*/ bool* fFound = NULL ); + HRESULT LoadAsString( /*[in ]*/ BSTR bstrData, /*[in]*/ const wchar_t* szRootTag, /*[out]*/ bool& fLoaded, /*[out]*/ bool* fFound = NULL ); + HRESULT Save ( /*[in ]*/ const wchar_t* szFile ); + HRESULT SaveAsStream( /*[out]*/ IUnknown* *ppStream ); + HRESULT SaveAsString( /*[out]*/ BSTR *pbstrData ); + + HRESULT SetTimeout( /*[in]*/ unsigned long dwTimeout ); + HRESULT Abort ( ); + + HRESULT SetVersionAndEncoding( /*[in]*/ const wchar_t* szVersion, /*[in]*/ const wchar_t* szEncoding ); + + HRESULT GetDocument ( /*[out]*/ IXMLDOMDocument* * pVal ) const; + HRESULT GetRoot ( /*[out]*/ IXMLDOMNode* * pVal ) const; + HRESULT GetNodes ( /*[in]*/ const wchar_t* szTag, /*[out]*/ IXMLDOMNodeList* * pVal ) const; + HRESULT GetNode ( /*[in]*/ const wchar_t* szTag, /*[out]*/ IXMLDOMNode* * pVal ) const; + HRESULT CreateNode ( /*[in]*/ const wchar_t* szTag, /*[out]*/ IXMLDOMNode* * pVal, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + + HRESULT GetAttribute ( /*[in]*/ const wchar_t* szTag, /*[in]*/ const wchar_t* szAttr, /*[out]*/ IXMLDOMAttribute* * pValue, /*[out]*/ bool& fFound, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + HRESULT GetAttribute ( /*[in]*/ const wchar_t* szTag, /*[in]*/ const wchar_t* szAttr, /*[out]*/ _bstr_t& bstrValue, /*[out]*/ bool& fFound, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + HRESULT GetAttribute ( /*[in]*/ const wchar_t* szTag, /*[in]*/ const wchar_t* szAttr, /*[out]*/ std::wstring& szValue, /*[out]*/ bool& fFound, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + HRESULT GetAttribute ( /*[in]*/ const wchar_t* szTag, /*[in]*/ const wchar_t* szAttr, /*[out]*/ signed int& lValue, /*[out]*/ bool& fFound, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + HRESULT GetValue ( /*[in]*/ const wchar_t* szTag, /*[out]*/ _variant_t& vValue, /*[out]*/ bool& fFound, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + HRESULT GetValue ( /*[in]*/ const wchar_t* szTag, /*[out]*/ _bstr_t& bstrValue, /*[out]*/ bool& fFound, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + HRESULT GetValue ( /*[in]*/ const wchar_t* szTag, /*[out]*/ std::wstring& szValue, /*[out]*/ bool& fFound, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + + HRESULT ModifyAttribute( /*[in]*/ const wchar_t* szTag, /*[in]*/ const wchar_t* szAttr, /*[in] */ const _bstr_t& bstrValue, /*[out]*/ bool& fFound, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + HRESULT ModifyAttribute( /*[in]*/ const wchar_t* szTag, /*[in]*/ const wchar_t* szAttr, /*[in] */ const std::wstring& szValue, /*[out]*/ bool& fFound, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + HRESULT ModifyAttribute( /*[in]*/ const wchar_t* szTag, /*[in]*/ const wchar_t* szAttr, /*[in] */ const wchar_t* szValue, /*[out]*/ bool& fFound, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + HRESULT ModifyAttribute( /*[in]*/ const wchar_t* szTag, /*[in]*/ const wchar_t* szAttr, /*[in] */ signed int lValue, /*[out]*/ bool& fFound, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + HRESULT ModifyValue ( /*[in]*/ const wchar_t* szTag, /*[in] */ const _variant_t& vValue, /*[out]*/ bool& fFound, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + HRESULT ModifyValue ( /*[in]*/ const wchar_t* szTag, /*[in] */ const _bstr_t& bstrValue, /*[out]*/ bool& fFound, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + HRESULT ModifyValue ( /*[in]*/ const wchar_t* szTag, /*[in] */ const std::wstring& szValue, /*[out]*/ bool& fFound, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + + HRESULT PutAttribute ( /*[in]*/ const wchar_t* szTag, /*[in]*/ const wchar_t* szAttr, /*[in] */ IXMLDOMAttribute* * pValue, /*[out]*/ bool& fFound, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + HRESULT PutAttribute ( /*[in]*/ const wchar_t* szTag, /*[in]*/ const wchar_t* szAttr, /*[in] */ const _bstr_t& bstrValue, /*[out]*/ bool& fFound, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + HRESULT PutAttribute ( /*[in]*/ const wchar_t* szTag, /*[in]*/ const wchar_t* szAttr, /*[in] */ const std::wstring& szValue, /*[out]*/ bool& fFound, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + HRESULT PutAttribute ( /*[in]*/ const wchar_t* szTag, /*[in]*/ const wchar_t* szAttr, /*[in] */ const wchar_t* szValue, /*[out]*/ bool& fFound, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + HRESULT PutAttribute ( /*[in]*/ const wchar_t* szTag, /*[in]*/ const wchar_t* szAttr, /*[in] */ signed int lValue, /*[out]*/ bool& fFound, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + HRESULT PutValue ( /*[in]*/ const wchar_t* szTag, /*[in] */ const _variant_t& vValue, /*[out]*/ bool& fFound, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + HRESULT PutValue ( /*[in]*/ const wchar_t* szTag, /*[in] */ const _bstr_t& bstrValue, /*[out]*/ bool& fFound, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + HRESULT PutValue ( /*[in]*/ const wchar_t* szTag, /*[in] */ const std::wstring& szValue, /*[out]*/ bool& fFound, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + HRESULT PutValue ( /*[in]*/ const wchar_t* szTag, /*[in] */ const wchar_t* szValue, /*[out]*/ bool& fFound, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + + HRESULT RemoveAttribute( /*[in]*/ const wchar_t* szTag, /*[in]*/ const wchar_t* szAttr, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + HRESULT RemoveValue ( /*[in]*/ const wchar_t* szTag, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); + HRESULT RemoveNode ( /*[in]*/ const wchar_t* szTag, /*[in]*/ IXMLDOMNode* pxdnNode = NULL ); +}; + +//--// + + +typedef std::vector< CLR_UINT8 > CLR_RT_Buffer; + +struct CLR_RT_FileStore +{ + static HRESULT LoadFile( const wchar_t* szFile, CLR_RT_Buffer& vec ); + static HRESULT SaveFile( const wchar_t* szFile, const CLR_RT_Buffer& vec ); + static HRESULT SaveFile( const wchar_t* szFile, const CLR_UINT8* buf, size_t size ); + + static HRESULT ExtractTokensFromFile( const wchar_t* szFileName, CLR_RT_StringVector& vec, const wchar_t* separators = L" \t", bool fNoComments = true ); + + static void ExtractTokens ( const CLR_RT_Buffer& buf , CLR_RT_StringVector& vec, const wchar_t* separators = L" \t", bool fNoComments = true ); + static void ExtractTokensFromBuffer( wchar_t* szLine, CLR_RT_StringVector& vec, const wchar_t* separators = L" \t", bool fNoComments = true ); + static void ExtractTokensFromString( const wchar_t* szLine, CLR_RT_StringVector& vec, const wchar_t* separators = L" \t" ); +}; + +#endif + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +#if !defined(MAX) +#define MAX(a,b) (a > b ? a : b) +#endif +#if !defined(MIN) +#define MIN(a,b) (a < b ? a : b) +#endif +#define ABS(x) (x > 0 ? x : (-x)) +#define FLOOR32(x) ((CLR_INT32)x) +#define FRAC(x) (x - FLOOR32(x)) + +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +struct CLR_RT_HeapBlock; +struct CLR_RT_HeapBlock_Node; + +struct CLR_RT_HeapBlock_WeakReference; +struct CLR_RT_HeapBlock_String; +struct CLR_RT_HeapBlock_Array; +struct CLR_RT_HeapBlock_Delegate; +struct CLR_RT_HeapBlock_Delegate_List; +struct CLR_RT_HeapBlock_BinaryBlob; + +struct CLR_RT_HeapBlock_Button; +struct CLR_RT_HeapBlock_Lock; +struct CLR_RT_HeapBlock_LockRequest; +struct CLR_RT_HeapBlock_Timer; +struct CLR_RT_HeapBlock_WaitForObject; +struct CLR_RT_HeapBlock_Finalizer; +struct CLR_RT_HeapBlock_MemoryStream; + +struct CLR_RT_HeapCluster; +struct CLR_RT_GarbageCollector; + +struct CLR_RT_DblLinkedList; + +#if defined(NANOCLR_APPDOMAINS) +struct CLR_RT_AppDomain; +struct CLR_RT_AppDomainAssembly; +#endif //NANOCLR_APPDOMAINS + +struct CLR_RT_Assembly; +struct CLR_RT_TypeSystem; +struct CLR_RT_TypeDescriptor; + +struct CLR_RT_Assembly_Instance; +struct CLR_RT_TypeSpec_Instance; +struct CLR_RT_TypeDef_Instance; +struct CLR_RT_MethodDef_Instance; +struct CLR_RT_FieldDef_Instance; + +struct CLR_RT_StackFrame; +struct CLR_RT_SubThread; +struct CLR_RT_Thread; +struct CLR_RT_ExecutionEngine; + +struct CLR_RT_ExecutionEngine_PerfCounters; + +struct CLR_HW_Hardware; + +typedef void (*CLR_RT_MarkingHandler )( CLR_RT_HeapBlock_BinaryBlob* ptr ); +typedef void (*CLR_RT_RelocationHandler)( CLR_RT_HeapBlock_BinaryBlob* ptr ); +typedef void (*CLR_RT_HardwareHandler )(); + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#if defined(NANOCLR_PROFILE_HANDLER) + +struct CLR_PROF_CounterSimple; +struct CLR_PROF_Counter; +struct CLR_PROF_Counter_Value; +struct CLR_PROF_Counter_Value2; +struct CLR_PROF_Handler; + +#if defined(NANOCLR_PROFILE_NEW_CALLS) + +struct CLR_PROF_CounterCallChain +{ + CLR_UINT64 m_time_exclusive; + CLR_RT_StackFrame* m_owningStackFrame; + CLR_PROF_Handler* m_owningHandler; + + + //--// + + void* Prepare ( CLR_PROF_Handler* handler ); + void Complete( CLR_UINT64& t, CLR_PROF_Handler* handler ); + + void Enter( CLR_RT_StackFrame* stack ); + void Leave( ); + + //--// + + PROHIBIT_COPY_CONSTRUCTORS(CLR_PROF_CounterCallChain); +}; +#endif + +//--// + +struct CLR_PROF_Handler +{ + static const int c_Mode_Ignore = 0; + static const int c_Mode_Plain = 1; + static const int c_Mode_Simple = 2; +#if defined(NANOCLR_PROFILE_NEW_CALLS) + static const int c_Mode_CallChain = 3; +#endif + + static bool s_initialized; + static CLR_PROF_Handler* s_current; + static volatile CLR_UINT64 s_time_overhead; + static volatile CLR_UINT64 s_time_freeze; + static volatile CLR_UINT64 s_time_adjusted; + + int m_target_Mode; + void* m_target; + + CLR_PROF_Handler* m_containing; + CLR_UINT64 m_time_correction; + CLR_UINT64 m_time_start; + + //--// + + CLR_PROF_Handler( ) { Constructor( ); } + +#if defined(NANOCLR_PROFILE_NEW_CALLS) + CLR_PROF_Handler( CLR_PROF_CounterCallChain& target ) { Constructor( target ); } +#endif + + ~CLR_PROF_Handler() { Destructor(); } + + //--// + + static void Calibrate ( ); + static void SuspendTime ( ); + static CLR_UINT64 GetFrozenTime( ); + static CLR_UINT64 ResumeTime ( ); + static CLR_UINT64 ResumeTime ( CLR_INT64 t ); + + //--// + +private: + void Constructor( ); +#if defined(NANOCLR_PROFILE_NEW_CALLS) + void Constructor( CLR_PROF_CounterCallChain& target ); +#endif + + void Destructor(); + + void Init( void* target ); + + PROHIBIT_COPY_CONSTRUCTORS2(CLR_PROF_Handler); +}; + +//--// + +#define CLR_PROF_HANDLER_SUSPEND_TIME() CLR_PROF_Handler::SuspendTime() +#define CLR_PROF_HANDLER_RESUME_TIME() CLR_PROF_Handler::ResumeTime() + +#else + +#define CLR_PROF_HANDLER_SUSPEND_TIME() +#define CLR_PROF_HANDLER_RESUME_TIME() + +#endif + +#if defined(NANOCLR_PROFILE_NEW_CALLS) + +#define CLR_PROF_HANDLER_CALLCHAIN_VOID(v) CLR_PROF_Handler v +#define CLR_PROF_HANDLER_CALLCHAIN(v,t) CLR_PROF_Handler v( t ) + +#else + +#define CLR_PROF_HANDLER_CALLCHAIN_VOID(v) +#define CLR_PROF_HANDLER_CALLCHAIN(v,t) + +#endif + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +struct CLR_RT_MemoryRange +{ + unsigned char* m_location; + unsigned int m_size; + + bool LimitToRange( CLR_RT_MemoryRange& filtered, unsigned char* address, unsigned int length ) const; +}; + +extern CLR_RT_MemoryRange s_CLR_RT_Heap; + +//--// + +struct CLR_RT_Memory +{ + static void ZeroFill( void* buf, size_t len ) { memset( buf, 0, len ); } + + //--// + + static void Reset ( ); + static void* SubtractFromSystem( size_t len ); + static void Release ( void* ptr ); + static void* Allocate ( size_t len, CLR_UINT32 flags = 0 ); + static void* ReAllocate ( void* ptr, size_t len ); + static void* Allocate_And_Erase( size_t len, CLR_UINT32 flags = 0 ); +}; + +//--// + +struct CLR_RT_Random +{ +public: + void Initialize(); + void Initialize( int seed ); + + uint32_t Next(); + +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + double NextDouble(); +#else + CLR_INT64 NextDouble(); +#endif + void NextBytes( unsigned char* buffer, unsigned int count ); +}; + +//--// + +extern void CLR_RT_GetVersion( unsigned short int* pMajor, unsigned short int* pMinor, unsigned short int* pBuild, unsigned short int* pRevision ); + +#define NANOCLR_CLEAR(ref) CLR_RT_Memory::ZeroFill( &ref, sizeof(ref) ) + +//--// + +static const int c_CLR_RT_Trace_None = 0; +static const int c_CLR_RT_Trace_Info = 1; +static const int c_CLR_RT_Trace_Verbose = 2; +static const int c_CLR_RT_Trace_Annoying = 3; +static const int c_CLR_RT_Trace_Obnoxious = 4; + +extern int s_CLR_RT_fTrace_Errors; +extern int s_CLR_RT_fTrace_Exceptions; +extern int s_CLR_RT_fTrace_Instructions; +extern int s_CLR_RT_fTrace_Memory; +extern int s_CLR_RT_fTrace_MemoryStats; +extern int s_CLR_RT_fTrace_StopOnFAILED; +extern int s_CLR_RT_fTrace_GC; +extern int s_CLR_RT_fTrace_GC_Depth; +extern int s_CLR_RT_fTrace_SimulateSpeed; +extern int s_CLR_RT_fTrace_AssemblyOverhead; + +#if defined(_WIN32) +extern int s_CLR_RT_fTrace_ARM_Execution; + +extern int s_CLR_RT_fTrace_RedirectLinesPerFile; +extern std::wstring s_CLR_RT_fTrace_RedirectOutput; +extern std::wstring s_CLR_RT_fTrace_RedirectCallChain; + +extern std::wstring s_CLR_RT_fTrace_HeapDump_FilePrefix; +extern bool s_CLR_RT_fTrace_HeapDump_IncludeCreators; + +extern bool s_CLR_RT_fTimeWarp; + +#endif + +static const int MAXHOSTNAMELEN = 256; // Typical of many sockets implementations, incl. Windows +static const int MAXTYPENAMELEN = 256; // Including terminating null byte. Enforced in MetadataProcessor. The standard imposes no limit, but we necessarily do. + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#define NANOCLR_INDEX_IS_VALID(idx) ((idx).m_data != 0) +#define NANOCLR_INDEX_IS_INVALID(idx) ((idx).m_data == 0) + +// +// IMPORTANT: THE ASSEMBLY IDX IN ALL THE CLR_RT_*_Index STRUCTURES SHOULD ALWAYS BE ENCODED THE SAME WAY!!! +// +// For details, go to "bool CLR_RT_GarbageCollector::ComputeReachabilityGraphForMultipleBlocks( CLR_RT_HeapBlock* lstExt, CLR_UINT32 numExt )" +// + +struct CLR_RT_Assembly_Index +{ + CLR_UINT32 m_data; + + //--// + + void Clear() + { + m_data = 0; + } + + void Set( CLR_UINT32 idxAssm ) + { + m_data = idxAssm << 16; + } + + //--// + + CLR_IDX Assembly() const { return (CLR_IDX)(m_data >> 16); } +}; + +struct CLR_RT_TypeSpec_Index +{ + CLR_UINT32 m_data; + + //--// + + void Clear() + { + m_data = 0; + } + + void Set( CLR_UINT32 idxAssm, CLR_UINT32 idxType ) + { + m_data = idxAssm << 16 | idxType; + } + + //--// + + CLR_IDX Assembly() const { return (CLR_IDX)(m_data >> 16); } + CLR_IDX TypeSpec() const { return (CLR_IDX)(m_data ); } +}; + +struct CLR_RT_TypeDef_Index +{ + CLR_UINT32 m_data; + + //--// + + void Clear() + { + m_data = 0; + } + + void Set( CLR_UINT32 idxAssm, CLR_UINT32 idxType ) + { + m_data = idxAssm << 16 | idxType; + } + + //--// + + CLR_IDX Assembly() const { return (CLR_IDX)(m_data >> 16); } + CLR_IDX Type () const { return (CLR_IDX)(m_data ); } +}; + +struct CLR_RT_FieldDef_Index +{ + CLR_UINT32 m_data; + + //--// + + void Clear() + { + m_data = 0; + } + + void Set( CLR_UINT32 idxAssm, CLR_UINT32 idxField ) + { + m_data = idxAssm << 16 | idxField; + } + + //--// + + CLR_IDX Assembly() const { return (CLR_IDX)(m_data >> 16); } + CLR_IDX Field () const { return (CLR_IDX)(m_data ); } +}; + +struct CLR_RT_MethodDef_Index +{ + CLR_UINT32 m_data; + + //--// + + void Clear() + { + m_data = 0; + } + + void Set( CLR_UINT32 idxAssm, CLR_UINT32 idxMethod ) + { + m_data = idxAssm << 16 | idxMethod; + } + + //--// + + CLR_IDX Assembly() const { return (CLR_IDX)(m_data >> 16); } + CLR_IDX Method () const { return (CLR_IDX)(m_data ); } +}; + +struct CLR_RT_ReflectionDef_Index +{ + CLR_UINT16 m_kind; // CLR_ReflectionType + CLR_UINT16 m_levels; + + union + { + CLR_RT_Assembly_Index m_assm; + CLR_RT_TypeDef_Index m_type; + CLR_RT_MethodDef_Index m_method; + CLR_RT_FieldDef_Index m_field; + CLR_UINT32 m_raw; + } m_data; + + //--// + + void Clear(); + + CLR_UINT32 GetTypeHash() const; + + void InitializeFromHash( CLR_UINT32 hash ); + + CLR_UINT64 GetRawData( ) const; + void SetRawData( CLR_UINT64 data ); + + //--// + + static bool Convert( CLR_RT_HeapBlock& ref, CLR_RT_Assembly_Instance& inst ); + static bool Convert( CLR_RT_HeapBlock& ref, CLR_RT_TypeDef_Instance& inst, CLR_UINT32* levels ); + static bool Convert( CLR_RT_HeapBlock& ref, CLR_RT_MethodDef_Instance& inst ); + static bool Convert( CLR_RT_HeapBlock& ref, CLR_RT_FieldDef_Instance& inst ); + static bool Convert( CLR_RT_HeapBlock& ref, CLR_UINT32& hash ); +}; + + +//--// + +struct CLR_RT_AssemblyRef_CrossReference +{ + CLR_RT_Assembly* m_target; // EVENT HEAP - NO RELOCATION - +}; + +struct CLR_RT_TypeRef_CrossReference +{ + CLR_RT_TypeDef_Index m_target; +}; + +struct CLR_RT_FieldRef_CrossReference +{ + CLR_RT_FieldDef_Index m_target; +}; + +struct CLR_RT_MethodRef_CrossReference +{ + CLR_RT_MethodDef_Index m_target; +}; + +struct CLR_RT_FieldDef_CrossReference +{ + CLR_IDX m_offset; +}; + +struct CLR_RT_TypeDef_CrossReference +{ + static const CLR_UINT32 TD_CR_StaticConstructorCalled = 0x0001; + static const CLR_UINT32 TD_CR_HasFinalizer = 0x0002; + static const CLR_UINT32 TD_CR_IsMarshalByRefObject = 0x0004; + + CLR_UINT16 m_flags; + CLR_IDX m_totalFields; + CLR_UINT32 m_hash; +}; + +struct CLR_RT_MethodDef_CrossReference +{ + static const CLR_UINT16 MD_CR_Patched = 0x8000; + static const CLR_UINT16 MD_CR_OwnerMask = 0x7FFF; + + CLR_UINT16 m_data; + + CLR_IDX GetOwner () const { return (CLR_IDX)(m_data); } +}; + +struct CLR_RT_MethodDef_Patch +{ + CLR_IDX m_orig; + CLR_IDX m_patched; +}; + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + +struct CLR_RT_MethodDef_DebuggingInfo +{ + static const CLR_UINT8 MD_DI_JustMyCode = 0x01; + static const CLR_UINT8 MD_DI_HasBreakpoint = 0x02; + + CLR_UINT8 m_flags; + + bool IsJMC () const { return IsFlagSet( MD_DI_JustMyCode ) ; } + bool HasBreakpoint() const { return IsFlagSet( MD_DI_HasBreakpoint ); } + + void SetJMC ( bool b ) { SetResetFlags( b, MD_DI_JustMyCode ); } + void SetBreakpoint( bool b ) { SetResetFlags( b, MD_DI_HasBreakpoint ); } + +private: + void SetFlags ( CLR_UINT8 flags ) { m_flags |= flags ; } + void ResetFlags ( CLR_UINT8 flags ) { m_flags &= ~flags ; } + bool IsFlagSet ( CLR_UINT8 flags ) const { return (m_flags & flags) != 0 ; } + void SetResetFlags( bool b, CLR_UINT8 flags ) { if(b) SetFlags( flags ); else ResetFlags( flags ); } +}; + +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#include + +//TODO: Change this to an extern method that is defined in the HAL +#if defined(PLATFORM_WINDOWS_EMULATOR) + #define SYSTEM_CLOCK_HZ g_HAL_Configuration_Windows.SystemClock + #define SLOW_CLOCKS_PER_SECOND g_HAL_Configuration_Windows.SlowClockPerSecond +#endif + +//////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////// + +struct CLR_RT_UnicodeHelper +{ + static const CLR_UINT32 SURROGATE_HALFSHIFT = 10; + static const CLR_UINT32 SURROGATE_HALFBASE = 0x00010000; + static const CLR_UINT32 SURROGATE_HALFMASK = 0x000003FF; + +#ifdef HIGH_SURROGATE_START +#undef HIGH_SURROGATE_START +#undef HIGH_SURROGATE_END +#undef LOW_SURROGATE_START +#undef LOW_SURROGATE_END +#endif + static const CLR_UINT16 HIGH_SURROGATE_START = 0xD800; + static const CLR_UINT16 HIGH_SURROGATE_END = 0xDBFF; + static const CLR_UINT16 LOW_SURROGATE_START = 0xDC00; + static const CLR_UINT16 LOW_SURROGATE_END = 0xDFFF; + + const CLR_UINT8* m_inputUTF8; + const CLR_UINT16* m_inputUTF16; + + CLR_UINT8* m_outputUTF8; + int m_outputUTF8_size; + + CLR_UINT16* m_outputUTF16; + int m_outputUTF16_size; + + //--// + + void SetInputUTF8 ( const char* src ) { m_inputUTF8 = (const CLR_UINT8*)src; } + void SetInputUTF16( const CLR_UINT16* src ) { m_inputUTF16 = src; } + + int CountNumberOfCharacters( int max = -1 ); + int CountNumberOfBytes ( int max = -1 ); + + //--// + + bool ConvertFromUTF8( int iMaxChars, bool fJustMove, int iMaxBytes = -1 ); + bool ConvertToUTF8 ( int iMaxChars, bool fJustMove ); + + bool MoveBackwardInUTF8( const char* utf8StringStart, int iMaxChars ); + +#if defined(_WIN32) + static void ConvertToUTF8 ( const std::wstring& src, std:: string& dst ); + static void ConvertFromUTF8( const std:: string& src, std::wstring& dst ); +#endif +}; + +class UnicodeString +{ +private: + CLR_RT_UnicodeHelper m_unicodeHelper; + CLR_RT_HeapBlock m_uHeapBlock; + CLR_UINT16* m_wCharArray; + int m_length; /// Length in wide characters (not bytes). + +public: + UnicodeString(); + ~UnicodeString(); + + HRESULT Assign( const char* string ); + operator const wchar_t*() { return (const wchar_t*)m_wCharArray; } + unsigned int Length(){ return m_length; } + +private: + void Release(); +}; + +//--// + +struct CLR_RT_ArrayListHelper +{ + static const int c_defaultCapacity = 2; + + static const int FIELD___items = 1; + static const int FIELD___size = 2; + + //--// + + static HRESULT PrepareArrayList ( CLR_RT_HeapBlock& pThisRef, int count, int capacity ); + static HRESULT ExtractArrayFromArrayList( CLR_RT_HeapBlock& pThisRef, CLR_RT_HeapBlock_Array* & array, int& count, int& capacity ); +}; + +//--// + +struct CLR_RT_ByteArrayReader +{ + HRESULT Init( const unsigned char* src, unsigned int srcSize ); + + HRESULT Read( void* dst, unsigned int size ); + HRESULT Read1Byte( void* dst ); + + HRESULT Skip( unsigned int size ); + + bool IsValid() { return (source && sourceSize > 0); } + + const unsigned char* source; + unsigned int sourceSize; +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +struct CLR_RT_SignatureParser +{ + static const int c_TypeSpec = 0; + static const int c_Interfaces = 1; + static const int c_Field = 2; + static const int c_Method = 3; + static const int c_Locals = 4; + static const int c_Object = 5; + + struct Element + { + bool m_fByRef; + int m_levels; + CLR_DataType m_dt; + CLR_RT_TypeDef_Index m_cls; + }; + + CLR_RT_HeapBlock* m_lst; + CLR_RT_Assembly* m_assm; + CLR_PMETADATA m_sig; + + int m_type; + CLR_UINT32 m_flags; + int m_count; + + //--// + + void Initialize_TypeSpec ( CLR_RT_Assembly* assm, const CLR_RECORD_TYPESPEC* ts ); + void Initialize_Interfaces ( CLR_RT_Assembly* assm, const CLR_RECORD_TYPEDEF* td ); + void Initialize_FieldDef ( CLR_RT_Assembly* assm, const CLR_RECORD_FIELDDEF* fd ); + void Initialize_MethodSignature( CLR_RT_Assembly* assm, const CLR_RECORD_METHODDEF* md ); + void Initialize_MethodLocals ( CLR_RT_Assembly* assm, const CLR_RECORD_METHODDEF* md ); + + void Initialize_TypeSpec ( CLR_RT_Assembly* assm, CLR_PMETADATA ts ); + void Initialize_FieldDef ( CLR_RT_Assembly* assm, CLR_PMETADATA fd ); + void Initialize_MethodSignature( CLR_RT_Assembly* assm, CLR_PMETADATA md ); + + void Initialize_Objects ( CLR_RT_HeapBlock* lst, int count, bool fTypes ); + + int Available() const { return m_count; } + + HRESULT Advance( Element& res ); +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#define NANOCLR_FOREACH_ASSEMBLY(ts) \ + { \ + CLR_RT_Assembly** ppASSM = (ts).m_assemblies; \ + size_t iASSM = (ts).m_assembliesMax; \ + for( ;iASSM--; ppASSM++) \ + { \ + CLR_RT_Assembly* pASSM = *ppASSM; \ + if(pASSM) + +#define NANOCLR_FOREACH_ASSEMBLY_END() \ + } \ + } + +#define NANOCLR_FOREACH_ASSEMBLY_NULL(ts) \ + { \ + CLR_RT_Assembly** ppASSM = (ts).m_assemblies; \ + size_t iASSM = ARRAYSIZE((ts).m_assemblies); \ + CLR_IDX idx = 1; \ + for( ;iASSM--; ppASSM++,idx++) \ + { \ + if(*ppASSM == NULL) + +#define NANOCLR_FOREACH_ASSEMBLY_NULL_END() \ + } \ + } + +#if defined(NANOCLR_APPDOMAINS) + #define NANOCLR_FOREACH_ASSEMBLY_IN_APPDOMAIN(ad) \ + NANOCLR_FOREACH_NODE(CLR_RT_AppDomainAssembly, appDomainAssembly, (ad)->m_appDomainAssemblies) \ + { \ + CLR_RT_Assembly* pASSM = appDomainAssembly->m_assembly; + + #define NANOCLR_FOREACH_ASSEMBLY_IN_APPDOMAIN_END() \ + } \ + NANOCLR_FOREACH_NODE_END() + + #define NANOCLR_FOREACH_ASSEMBLY_IN_CURRENT_APPDOMAIN(ts) NANOCLR_FOREACH_ASSEMBLY_IN_APPDOMAIN(g_CLR_RT_ExecutionEngine.GetCurrentAppDomain()) + #define NANOCLR_FOREACH_ASSEMBLY_IN_CURRENT_APPDOMAIN_END() NANOCLR_FOREACH_ASSEMBLY_IN_APPDOMAIN_END() +#else + #define NANOCLR_FOREACH_ASSEMBLY_IN_APPDOMAIN(ts, ad) NANOCLR_FOREACH_ASSEMBLY(ts) + #define NANOCLR_FOREACH_ASSEMBLY_IN_APPDOMAIN_END() NANOCLR_FOREACH_ASSEMBLY_END() + #define NANOCLR_FOREACH_ASSEMBLY_IN_CURRENT_APPDOMAIN(ts) NANOCLR_FOREACH_ASSEMBLY(ts) + #define NANOCLR_FOREACH_ASSEMBLY_IN_CURRENT_APPDOMAIN_END() NANOCLR_FOREACH_ASSEMBLY_END() +#endif +// This type is needed on PC only for Interop code generation. For device code forward declaration only +class CLR_RT_VectorOfManagedElements; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +struct CLR_RT_Assembly : public CLR_RT_HeapBlock_Node // EVENT HEAP - NO RELOCATION - +{ + struct Offsets + { + size_t iBase; + size_t iAssemblyRef; + size_t iTypeRef; + size_t iFieldRef; + size_t iMethodRef; + size_t iTypeDef; + size_t iFieldDef; + size_t iMethodDef; + + #if !defined(NANOCLR_APPDOMAINS) + size_t iStaticFields; + #endif + + #if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + size_t iDebuggingInfoMethods; + #endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + }; + + //--// + + ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // NEED TO KEEP THESE IN SYNC WITH Enum 'Commands.DebuggingResolveAssembly.ResolvedStatus' on debugger library code // + ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + + static const CLR_UINT32 Resolved = 0x00000001; + static const CLR_UINT32 ResolutionCompleted = 0x00000002; + static const CLR_UINT32 PreparedForExecution = 0x00000004; + static const CLR_UINT32 Deployed = 0x00000008; + static const CLR_UINT32 PreparingForExecution = 0x00000010; + static const CLR_UINT32 StaticConstructorsExecuted = 0x00000020; + + CLR_UINT32 m_idx; // Relative to the type system (for static fields access). + CLR_UINT32 m_flags; + + const CLR_RECORD_ASSEMBLY* m_header; // ANY HEAP - DO RELOCATION - + const char* m_szName; // ANY HEAP - DO RELOCATION - + + const CLR_RT_MethodHandler* m_nativeCode; + + int m_pTablesSize[ TBL_Max ]; + + #if !defined(NANOCLR_APPDOMAINS) + CLR_RT_HeapBlock* m_pStaticFields; // EVENT HEAP - NO RELOCATION - (but the data they point to has to be relocated) + #endif + + int m_iStaticFields; + + CLR_RT_HeapBlock_Array* m_pFile; // ANY HEAP - DO RELOCATION - + + CLR_RT_AssemblyRef_CrossReference* m_pCrossReference_AssemblyRef; // EVENT HEAP - NO RELOCATION - (but the data they point to has to be relocated) + CLR_RT_TypeRef_CrossReference * m_pCrossReference_TypeRef ; // EVENT HEAP - NO RELOCATION - (but the data they point to has to be relocated) + CLR_RT_FieldRef_CrossReference * m_pCrossReference_FieldRef ; // EVENT HEAP - NO RELOCATION - (but the data they point to has to be relocated) + CLR_RT_MethodRef_CrossReference * m_pCrossReference_MethodRef ; // EVENT HEAP - NO RELOCATION - (but the data they point to has to be relocated) + CLR_RT_TypeDef_CrossReference * m_pCrossReference_TypeDef ; // EVENT HEAP - NO RELOCATION - (but the data they point to has to be relocated) + CLR_RT_FieldDef_CrossReference * m_pCrossReference_FieldDef ; // EVENT HEAP - NO RELOCATION - (but the data they point to has to be relocated) + CLR_RT_MethodDef_CrossReference * m_pCrossReference_MethodDef ; // EVENT HEAP - NO RELOCATION - (but the data they point to has to be relocated) + + #if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + CLR_RT_MethodDef_DebuggingInfo * m_pDebuggingInfo_MethodDef ; //EVENT HEAP - NO RELOCATION - (but the data they point to has to be relocated) + #endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + #if defined(NANOCLR_TRACE_STACK_HEAVY) && defined(_WIN32) + int m_maxOpcodes; + int* m_stackDepth; + #endif + + + #if defined(_WIN32) + std::string* m_strPath; + #endif + + //--// + + static void InitString(); + + bool IsSameAssembly( const CLR_RT_Assembly& assm ) const; + + #if defined(_WIN32) + + static void InitString( std::map& map ); + static HRESULT CreateInstance ( const CLR_RECORD_ASSEMBLY* data, CLR_RT_Assembly*& assm, const wchar_t* szName ); + + #endif + + //--// + + static HRESULT CreateInstance ( const CLR_RECORD_ASSEMBLY* data, CLR_RT_Assembly*& assm ); + void DestroyInstance( ); + + void Assembly_Initialize( CLR_RT_Assembly::Offsets& offsets ); + + bool Resolve_AssemblyRef ( bool fOutput ); + HRESULT Resolve_TypeRef ( ); + HRESULT Resolve_FieldRef ( ); + HRESULT Resolve_MethodRef ( ); + void Resolve_TypeDef ( ); + void Resolve_MethodDef ( ); + void Resolve_Link ( ); + HRESULT Resolve_ComputeHashes ( ); + HRESULT Resolve_AllocateStaticFields ( CLR_RT_HeapBlock* pStaticFields ); + + HRESULT PrepareForExecution(); + + CLR_UINT32 ComputeAssemblyHash( ); + CLR_UINT32 ComputeAssemblyHash( const CLR_RECORD_ASSEMBLYREF* ar ); + + + bool FindTypeDef ( const char* name, const char* nameSpace , CLR_RT_TypeDef_Index& idx ); + bool FindTypeDef ( const char* name, CLR_IDX scope , CLR_RT_TypeDef_Index& idx ); + bool FindTypeDef ( CLR_UINT32 hash , CLR_RT_TypeDef_Index& idx ); + + bool FindFieldDef ( const CLR_RECORD_TYPEDEF* src, const char* name, CLR_RT_Assembly* base, CLR_SIG sig, CLR_RT_FieldDef_Index& idx ); + bool FindMethodDef( const CLR_RECORD_TYPEDEF* src, const char* name, CLR_RT_Assembly* base, CLR_SIG sig, CLR_RT_MethodDef_Index& idx ); + + bool FindNextStaticConstructor( CLR_RT_MethodDef_Index& idx ); + + bool FindMethodBoundaries( CLR_IDX i, CLR_OFFSET& start, CLR_OFFSET& end ); + + void Relocate(); + + //--// + + CLR_RT_HeapBlock* GetStaticField( const int index ); + + //--// + + CLR_PMETADATA GetTable( CLR_TABLESENUM tbl ) { return (CLR_PMETADATA)m_header + m_header->startOfTables[ tbl ]; } + + #define NANOCLR_ASSEMBLY_RESOLVE(cls,tbl,idx) (const cls *)((CLR_UINT8*)m_header + m_header->startOfTables[ tbl ] + (sizeof(cls) * idx)) + const CLR_RECORD_ASSEMBLYREF * GetAssemblyRef ( CLR_IDX i ) { return NANOCLR_ASSEMBLY_RESOLVE(CLR_RECORD_ASSEMBLYREF , TBL_AssemblyRef , i); } + const CLR_RECORD_TYPEREF * GetTypeRef ( CLR_IDX i ) { return NANOCLR_ASSEMBLY_RESOLVE(CLR_RECORD_TYPEREF , TBL_TypeRef , i); } + const CLR_RECORD_FIELDREF * GetFieldRef ( CLR_IDX i ) { return NANOCLR_ASSEMBLY_RESOLVE(CLR_RECORD_FIELDREF , TBL_FieldRef , i); } + const CLR_RECORD_METHODREF * GetMethodRef ( CLR_IDX i ) { return NANOCLR_ASSEMBLY_RESOLVE(CLR_RECORD_METHODREF , TBL_MethodRef , i); } + const CLR_RECORD_TYPEDEF * GetTypeDef ( CLR_IDX i ) { return NANOCLR_ASSEMBLY_RESOLVE(CLR_RECORD_TYPEDEF , TBL_TypeDef , i); } + const CLR_RECORD_FIELDDEF * GetFieldDef ( CLR_IDX i ) { return NANOCLR_ASSEMBLY_RESOLVE(CLR_RECORD_FIELDDEF , TBL_FieldDef , i); } + const CLR_RECORD_METHODDEF * GetMethodDef ( CLR_IDX i ) { return NANOCLR_ASSEMBLY_RESOLVE(CLR_RECORD_METHODDEF , TBL_MethodDef , i); } + const CLR_RECORD_ATTRIBUTE * GetAttribute ( CLR_IDX i ) { return NANOCLR_ASSEMBLY_RESOLVE(CLR_RECORD_ATTRIBUTE , TBL_Attributes , i); } + const CLR_RECORD_TYPESPEC * GetTypeSpec ( CLR_IDX i ) { return NANOCLR_ASSEMBLY_RESOLVE(CLR_RECORD_TYPESPEC , TBL_TypeSpec , i); } + const CLR_RECORD_RESOURCE_FILE* GetResourceFile( CLR_IDX i ) { return NANOCLR_ASSEMBLY_RESOLVE(CLR_RECORD_RESOURCE_FILE, TBL_ResourcesFiles, i); } + const CLR_RECORD_RESOURCE * GetResource ( CLR_IDX i ) { return NANOCLR_ASSEMBLY_RESOLVE(CLR_RECORD_RESOURCE , TBL_Resources , i); } + CLR_PMETADATA GetResourceData( CLR_UINT32 i ) { return NANOCLR_ASSEMBLY_RESOLVE(CLR_UINT8 , TBL_ResourcesData , i); } + const char* GetString ( CLR_STRING i ); + CLR_PMETADATA GetSignature ( CLR_SIG i ) { return NANOCLR_ASSEMBLY_RESOLVE(CLR_UINT8 , TBL_Signatures , i); } + CLR_PMETADATA GetByteCode ( CLR_OFFSET i ) { return NANOCLR_ASSEMBLY_RESOLVE(CLR_UINT8 , TBL_ByteCode , i); } + #undef NANOCLR_ASSEMBLY_RESOLVE + + //--// + + #undef DECL_POSTFIX + #if defined(NANOCLR_TRACE_INSTRUCTIONS) + #define DECL_POSTFIX + #else + #define DECL_POSTFIX {} + #endif + + public: + void DumpOpcode ( CLR_RT_StackFrame* stack, CLR_PMETADATA ip ) DECL_POSTFIX; + void DumpOpcodeDirect( CLR_RT_MethodDef_Instance& call , CLR_PMETADATA ip, CLR_PMETADATA ipStart, int pid ) DECL_POSTFIX; + + private: + void DumpToken ( CLR_UINT32 tk ) DECL_POSTFIX; + void DumpSignature ( CLR_SIG sig ) DECL_POSTFIX; + void DumpSignature ( CLR_PMETADATA& p ) DECL_POSTFIX; + void DumpSignatureToken( CLR_PMETADATA& p ) DECL_POSTFIX; + + //--// + + #if defined(_WIN32) + static FILE* s_output; + static FILE* s_toclose; + + public: + static void Dump_SetDevice ( FILE *&outputDeviceFile, const wchar_t* szFileName ); + static void Dump_SetDevice ( const wchar_t* szFileName ); + + static void Dump_CloseDevice( FILE *&outputDeviceFile); + static void Dump_CloseDevice( ); + + static void Dump_Printf ( FILE *outputDeviceFile, const char *format, ... ); + static void Dump_Printf ( const char *format, ... ); + + static void Dump_Indent( const CLR_RECORD_METHODDEF* md, size_t offset, size_t level ); + + void Dump( bool fNoByteCode ); + + unsigned int GenerateSignatureForNativeMethods(); + + bool AreInternalMethodsPresent( const CLR_RECORD_TYPEDEF* td ); + void GenerateSkeleton( const wchar_t* szFileName, const wchar_t* szProjectName ); + void GenerateSkeletonFromComplientNames( const wchar_t* szFileName, const wchar_t* szProjectName ); + + void BuildParametersList( CLR_PMETADATA pMetaData, CLR_RT_VectorOfManagedElements &elemPtrArray ); + void GenerateSkeletonStubFieldsDef( const CLR_RECORD_TYPEDEF *pClsType, FILE *pFileStubHead, std::string strIndent, std::string strMngClassName ); + void GenerateSkeletonStubCode( const wchar_t* szFilePath, FILE *pFileDotNetProj ); + + void BuildMethodName_NoInterop(const CLR_RECORD_METHODDEF* md, std::string& name, CLR_RT_StringMap& mapMethods); + void GenerateSkeleton_NoInterop(LPCWSTR szFileName, LPCWSTR szProjectName); + + void BuildMethodName( const CLR_RECORD_METHODDEF* md, std::string& name , CLR_RT_StringMap& mapMethods ); + void BuildClassName ( const CLR_RECORD_TYPEREF* tr, std::string& cls_name, bool fEscape ); + void BuildClassName ( const CLR_RECORD_TYPEDEF* td, std::string& cls_name, bool fEscape ); + void BuildTypeName ( const CLR_RECORD_TYPEDEF* td, std::string& type_name ); + + #endif + private: + + #if defined(_WIN32) + void Dump_Token ( CLR_UINT32 tk ); + void Dump_FieldOwner ( CLR_UINT32 idx ); + void Dump_MethodOwner ( CLR_UINT32 idx ); + void Dump_Signature ( CLR_SIG sig ); + void Dump_Signature ( CLR_PMETADATA& p ); + void Dump_SignatureToken( CLR_PMETADATA& p ); + #endif + + //--// + + PROHIBIT_ALL_CONSTRUCTORS(CLR_RT_Assembly); + + //--// + + private: + + CLR_UINT32 ComputeHashForName( const CLR_RT_TypeDef_Index& td, CLR_UINT32 hash ); + + static CLR_UINT32 ComputeHashForType( CLR_DataType dt, CLR_UINT32 hash ); +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +//--// + +#if defined(NANOCLR_APPDOMAINS) + +struct CLR_RT_AppDomain : public CLR_RT_ObjectToEvent_Destination // EVENT HEAP - NO RELOCATION - +{ + enum AppDomainState + { + AppDomainState_Loaded, + AppDomainState_Unloading, + AppDomainState_Unloaded + }; + + AppDomainState m_state; + int m_id; + CLR_RT_DblLinkedList m_appDomainAssemblies; + CLR_RT_HeapBlock* m_globalLock; // OBJECT HEAP - DO RELOCATION - + CLR_RT_HeapBlock_String* m_strName; // OBJECT HEAP - DO RELOCATION - + CLR_RT_HeapBlock* m_outOfMemoryException; // OBJECT HEAP - DO RELOCATION - + CLR_RT_AppDomainAssembly* m_appDomainAssemblyLastAccess; // EVENT HEAP - NO RELOCATION - + bool m_fCanBeUnloaded; + + static HRESULT CreateInstance ( const char* szName, CLR_RT_AppDomain*& appDomain); + + void DestroyInstance (); + void AppDomain_Initialize (); + void AppDomain_Uninitialize(); + bool IsLoaded (); + + void Relocate (); + void RecoverFromGC(); + + CLR_RT_AppDomainAssembly* FindAppDomainAssembly( CLR_RT_Assembly* assm ); + + HRESULT MarshalObject ( CLR_RT_HeapBlock& src , CLR_RT_HeapBlock& dst, CLR_RT_AppDomain* appDomainSrc = NULL ); + HRESULT MarshalParameters( CLR_RT_HeapBlock* callerArgs, CLR_RT_HeapBlock* calleeArgs, int count, bool fOnReturn, CLR_RT_AppDomain* appDomainSrc = NULL ); + + HRESULT VerifyTypeIsLoaded( const CLR_RT_TypeDef_Index& idx ); + HRESULT GetAssemblies ( CLR_RT_HeapBlock& ref ); + HRESULT LoadAssembly ( CLR_RT_Assembly* assm ); + HRESULT GetManagedObject ( CLR_RT_HeapBlock& obj ); +}; + +struct CLR_RT_AppDomainAssembly : public CLR_RT_HeapBlock_Node //EVENT HEAP - NO RELOCATION - +{ + static const CLR_UINT32 StaticConstructorsExecuted = 0x00000001; + + CLR_UINT32 m_flags; + CLR_RT_AppDomain* m_appDomain; // EVENT HEAP - NO RELOCATION - + CLR_RT_Assembly* m_assembly; // EVENT HEAP - NO RELOCATION - + CLR_RT_HeapBlock* m_pStaticFields; // EVENT HEAP - NO RELOCATION - (but the data they point to has to be relocated) + + + static HRESULT CreateInstance( CLR_RT_AppDomain* appDomain, CLR_RT_Assembly* assm, CLR_RT_AppDomainAssembly*& appDomainAssembly ); + + void DestroyInstance(); + HRESULT AppDomainAssembly_Initialize( CLR_RT_AppDomain* appDomain, CLR_RT_Assembly* assm ); + + void Relocate(); +}; + +#endif //NANOCLR_APPDOMAINS + +//--// + +struct CLR_RT_WellKnownTypes +{ + CLR_RT_TypeDef_Index m_Boolean; + CLR_RT_TypeDef_Index m_Int8; + CLR_RT_TypeDef_Index m_UInt8; + + CLR_RT_TypeDef_Index m_Char; + CLR_RT_TypeDef_Index m_Int16; + CLR_RT_TypeDef_Index m_UInt16; + + CLR_RT_TypeDef_Index m_Int32; + CLR_RT_TypeDef_Index m_UInt32; + CLR_RT_TypeDef_Index m_Single; + + CLR_RT_TypeDef_Index m_Int64; + CLR_RT_TypeDef_Index m_UInt64; + CLR_RT_TypeDef_Index m_Double; + CLR_RT_TypeDef_Index m_DateTime; + CLR_RT_TypeDef_Index m_TimeSpan; + CLR_RT_TypeDef_Index m_String; + + CLR_RT_TypeDef_Index m_Void; + CLR_RT_TypeDef_Index m_Object; + CLR_RT_TypeDef_Index m_ValueType; + CLR_RT_TypeDef_Index m_Enum; + + CLR_RT_TypeDef_Index m_AppDomainUnloadedException; + CLR_RT_TypeDef_Index m_ArgumentNullException; + CLR_RT_TypeDef_Index m_ArgumentException; + CLR_RT_TypeDef_Index m_ArgumentOutOfRangeException; + CLR_RT_TypeDef_Index m_Exception; + CLR_RT_TypeDef_Index m_IndexOutOfRangeException; + CLR_RT_TypeDef_Index m_ThreadAbortException; + CLR_RT_TypeDef_Index m_InvalidOperationException; + CLR_RT_TypeDef_Index m_InvalidCastException; + CLR_RT_TypeDef_Index m_NotSupportedException; + CLR_RT_TypeDef_Index m_NotImplementedException; + CLR_RT_TypeDef_Index m_NullReferenceException; + CLR_RT_TypeDef_Index m_OutOfMemoryException; + CLR_RT_TypeDef_Index m_ObjectDisposedException; + CLR_RT_TypeDef_Index m_ConstraintException; + CLR_RT_TypeDef_Index m_WatchdogException; + + CLR_RT_TypeDef_Index m_Delegate; + CLR_RT_TypeDef_Index m_MulticastDelegate; + + CLR_RT_TypeDef_Index m_Array; + CLR_RT_TypeDef_Index m_ArrayList; + CLR_RT_TypeDef_Index m_ICloneable; + CLR_RT_TypeDef_Index m_IList; + + CLR_RT_TypeDef_Index m_Assembly; + CLR_RT_TypeDef_Index m_TypeStatic; + CLR_RT_TypeDef_Index m_Type; + CLR_RT_TypeDef_Index m_ConstructorInfo; + CLR_RT_TypeDef_Index m_MethodInfo; + CLR_RT_TypeDef_Index m_FieldInfo; + + CLR_RT_TypeDef_Index m_WeakReference; + + CLR_RT_TypeDef_Index m_SerializationHintsAttribute; + + CLR_RT_TypeDef_Index m_NetworkInterface; + CLR_RT_TypeDef_Index m_Wireless80211Configuration; + CLR_RT_TypeDef_Index m_WirelessAPConfiguration; + CLR_RT_TypeDef_Index m_WirelessAPStation; + +#if defined(NANOCLR_APPDOMAINS) + CLR_RT_TypeDef_Index m_AppDomain; + CLR_RT_TypeDef_Index m_MarshalByRefObject; +#endif + + CLR_RT_TypeDef_Index m_Thread; + CLR_RT_TypeDef_Index m_ResourceManager; + + CLR_RT_TypeDef_Index m_SocketException; + + CLR_RT_TypeDef_Index m_I2cTransferResult; + + PROHIBIT_COPY_CONSTRUCTORS(CLR_RT_WellKnownTypes); +}; + +extern CLR_RT_WellKnownTypes g_CLR_RT_WellKnownTypes; + +struct CLR_RT_WellKnownMethods +{ + CLR_RT_MethodDef_Index m_ResourceManager_GetObjectFromId; + CLR_RT_MethodDef_Index m_ResourceManager_GetObjectChunkFromId; + + PROHIBIT_COPY_CONSTRUCTORS(CLR_RT_WellKnownMethods); +}; + +extern CLR_RT_WellKnownMethods g_CLR_RT_WellKnownMethods; + +//--// + +typedef void (CLR_RT_HeapBlock::*CLR_RT_HeapBlockRelocate)(); + +struct CLR_RT_DataTypeLookup +{ + static const CLR_UINT8 c_NA = 0x00; + static const CLR_UINT8 c_VariableSize = 0xFF; + + static const CLR_UINT32 c_Primitive = 0x00000001; + static const CLR_UINT32 c_Interface = 0x00000002; + static const CLR_UINT32 c_Class = 0x00000004; + static const CLR_UINT32 c_ValueType = 0x00000008; + static const CLR_UINT32 c_Enum = 0x00000010; + static const CLR_UINT32 c_SemanticMask = 0x0000001F; + + static const CLR_UINT32 c_Array = 0x00000020; + static const CLR_UINT32 c_ArrayList = 0x00000040; + static const CLR_UINT32 c_SemanticMask2 = 0x0000007F; + + static const CLR_UINT32 c_Reference = 0x00010000; + static const CLR_UINT32 c_Numeric = 0x00020000; + static const CLR_UINT32 c_Integer = 0x00040000; + static const CLR_UINT32 c_Signed = 0x00080000; + static const CLR_UINT32 c_Direct = 0x00100000; // This isn't an indirect reference. + static const CLR_UINT32 c_OptimizedValueType = 0x00200000; // A value type that is kept in a single HeapBlock. + static const CLR_UINT32 c_ManagedType = 0x00400000; // this dt represents a managed type, or a pointer to a managed type + // More specificly, TypeDescriptor::InitializeFromObject will succeed + // when starting from an object of with this dt + + CLR_UINT32 m_flags; + CLR_UINT8 m_sizeInBits; + CLR_UINT8 m_sizeInBytes; + CLR_UINT8 m_promoteTo; + CLR_UINT8 m_convertToElementType; + + CLR_RT_TypeDef_Index* m_cls; + CLR_RT_HeapBlockRelocate m_relocate; + +#if defined(_WIN32) || defined(NANOCLR_TRACE_MEMORY_STATS) + const char* m_name; +#endif +}; + +extern const CLR_RT_DataTypeLookup c_CLR_RT_DataTypeLookup[]; + +//--// + +struct CLR_RT_OpcodeLookup +{ + static const CLR_UINT16 COND_BRANCH_NEVER = 0x0000; + static const CLR_UINT16 COND_BRANCH_ALWAYS = 0x0001; + static const CLR_UINT16 COND_BRANCH_IFTRUE = 0x0002; + static const CLR_UINT16 COND_BRANCH_IFFALSE = 0x0003; + static const CLR_UINT16 COND_BRANCH_IFEQUAL = 0x0004; + static const CLR_UINT16 COND_BRANCH_IFNOTEQUAL = 0x0005; + static const CLR_UINT16 COND_BRANCH_IFGREATER = 0x0006; + static const CLR_UINT16 COND_BRANCH_IFGREATEROREQUAL = 0x0007; + static const CLR_UINT16 COND_BRANCH_IFLESS = 0x0008; + static const CLR_UINT16 COND_BRANCH_IFLESSOREQUAL = 0x0009; + static const CLR_UINT16 COND_BRANCH_IFMATCH = 0x000A; + static const CLR_UINT16 COND_BRANCH_THROW = 0x000B; + static const CLR_UINT16 COND_BRANCH_MASK = 0x000F; + + static const CLR_UINT16 COND_OVERFLOW = 0x0010; + static const CLR_UINT16 COND_UNSIGNED = 0x0020; + + static const CLR_UINT16 STACK_RESET = 0x0080; + + static const CLR_UINT16 ATTRIB_HAS_TARGET = 0x0100; + static const CLR_UINT16 ATTRIB_HAS_DT = 0x0200; + static const CLR_UINT16 ATTRIB_HAS_INDEX = 0x0400; + static const CLR_UINT16 ATTRIB_HAS_TOKEN = 0x0800; + static const CLR_UINT16 ATTRIB_HAS_I4 = 0x1000; + static const CLR_UINT16 ATTRIB_HAS_R4 = 0x2000; + static const CLR_UINT16 ATTRIB_HAS_I8 = 0x4000; + static const CLR_UINT16 ATTRIB_HAS_R8 = 0x8000; + +#if defined(NANOCLR_OPCODE_NAMES) + const char* m_name; +#endif + +#if defined(NANOCLR_OPCODE_STACKCHANGES) + CLR_UINT8 m_stackChanges; +#endif + + CLR_OpcodeParam m_opParam; + + //--// + +#if defined(NANOCLR_OPCODE_PARSER) + CLR_LOGICAL_OPCODE m_logicalOpcode; + CLR_DataType m_dt; + CLR_INT8 m_index; + CLR_UINT16 m_flags; +#endif +#if defined(NANOCLR_OPCODE_STACKCHANGES) + CLR_UINT32 StackPop () const { return m_stackChanges >> 4; } + CLR_UINT32 StackPush () const { return m_stackChanges & 0xF; } + CLR_INT32 StackChanges() const { return StackPush() - StackPop(); } +#endif + +#if defined(NANOCLR_OPCODE_NAMES) + const char* Name() const { return m_name; } +#else + const char* Name() const { return ""; } +#endif +}; + +extern const CLR_RT_OpcodeLookup c_CLR_RT_OpcodeLookup[]; + +//--// + +struct CLR_RT_LogicalOpcodeLookup +{ + static const CLR_UINT32 RESTARTPOINT_NEXT = 0x00000001; + static const CLR_UINT32 EXCEPTION = 0x00000002; + static const CLR_UINT32 EXCEPTION_IF_OVERFLOW = 0x00000010; + static const CLR_UINT32 EXCEPTION_IF_ZERO = 0x00000020; + static const CLR_UINT32 EXCEPTION_ON_CAST = 0x00000040; + +#if defined(NANOCLR_OPCODE_NAMES) + const char* m_name; +#endif + + CLR_UINT32 m_flags; + + +#if defined(NANOCLR_OPCODE_NAMES) + const char* Name() const { return m_name; } +#else + const char* Name() const { return ""; } +#endif +}; + +extern const CLR_RT_LogicalOpcodeLookup c_CLR_RT_LogicalOpcodeLookup[]; + +//--// + + +struct CLR_RT_TypeSystem // EVENT HEAP - NO RELOCATION - +{ + struct CompatibilityLookup + { + const char* name; + CLR_RECORD_VERSION version; + }; + + //--// + + static const int c_MaxAssemblies = 64; + + //--// + + static const CLR_UINT32 TYPENAME_FLAGS_FULL = 0x1; + static const CLR_UINT32 TYPENAME_NESTED_SEPARATOR_DOT = 0x2; + + //--// + + CLR_RT_Assembly* m_assemblies[ c_MaxAssemblies ]; // EVENT HEAP - NO RELOCATION - array of CLR_RT_Assembly + size_t m_assembliesMax; + CLR_RT_Assembly* m_assemblyMscorlib; + CLR_RT_Assembly* m_assemblyNative; + + CLR_RT_MethodDef_Index m_entryPoint; + + //--// + + void TypeSystem_Initialize(); + void TypeSystem_Cleanup(); + + void Link ( CLR_RT_Assembly* assm ); + void PostLinkageProcessing( CLR_RT_Assembly* assm ); + + HRESULT ResolveAll ( ); + HRESULT PrepareForExecution ( ); + HRESULT PrepareForExecutionHelper( const char* szAssembly ); + + CLR_RT_Assembly* FindAssembly( const char* name, const CLR_RECORD_VERSION* ver, bool fExact ); + + bool FindTypeDef ( const char* name, const char* nameSpace, CLR_RT_Assembly* assm, CLR_RT_TypeDef_Index& res ); + bool FindTypeDef ( const char* name, CLR_RT_Assembly* assm, CLR_RT_TypeDef_Index& res ); + bool FindTypeDef ( const char* name, const char* nameSpace, CLR_RT_TypeDef_Index& res ); + bool FindTypeDef ( CLR_UINT32 hash , CLR_RT_TypeDef_Index& res ); + bool FindTypeDef ( const char* name , CLR_RT_TypeDef_Index& res ); + bool FindTypeDef ( const char* name , CLR_RT_Assembly* assm, CLR_RT_ReflectionDef_Index& reflex ); + + HRESULT LocateResourceFile( CLR_RT_Assembly_Instance assm, const char* name, CLR_INT32& idxResourceFile ); + HRESULT LocateResource ( CLR_RT_Assembly_Instance assm, CLR_INT32 idxResourceFile, CLR_INT16 id, const CLR_RECORD_RESOURCE*& res, CLR_UINT32& size ); + + HRESULT BuildTypeName ( const CLR_RT_TypeDef_Index& cls, char*& szBuffer, size_t& size, CLR_UINT32 flags, CLR_UINT32 levels ); + HRESULT BuildTypeName ( const CLR_RT_TypeDef_Index& cls, char*& szBuffer, size_t& size ); + HRESULT BuildMethodName ( const CLR_RT_MethodDef_Index& md , char*& szBuffer, size_t& size ); + HRESULT BuildFieldName ( const CLR_RT_FieldDef_Index& fd , char*& szBuffer, size_t& size ); + HRESULT QueueStringToBuffer( char*& szBuffer, size_t& size, const char* szText ); + + bool FindVirtualMethodDef( const CLR_RT_TypeDef_Index& cls, const CLR_RT_MethodDef_Index& calleeMD , CLR_RT_MethodDef_Index& idx ); + bool FindVirtualMethodDef( const CLR_RT_TypeDef_Index& cls, const CLR_RT_MethodDef_Index& calleeMD, const char* calleeName, CLR_RT_MethodDef_Index& idx ); + + static bool MatchSignature ( CLR_RT_SignatureParser& parserLeft , CLR_RT_SignatureParser& parserRight ); + static bool MatchSignatureDirect ( CLR_RT_SignatureParser& parserLeft , CLR_RT_SignatureParser& parserRight , bool fIsInstanceOfOK ); + static bool MatchSignatureElement( CLR_RT_SignatureParser::Element& resLeft, CLR_RT_SignatureParser::Element& resRight, bool fIsInstanceOfOK ); + + static CLR_DataType MapElementTypeToDataType( CLR_UINT32 et ); + static CLR_UINT32 MapDataTypeToElementType( CLR_DataType dt ); + +#if defined(_WIN32) + void Dump( const wchar_t* szFileName, bool fNoByteCode ); +#endif + + //--// + + PROHIBIT_COPY_CONSTRUCTORS(CLR_RT_TypeSystem); +}; + +extern CLR_RT_TypeSystem g_CLR_RT_TypeSystem; + +//--// + +struct CLR_RT_Assembly_Instance : public CLR_RT_Assembly_Index +{ + CLR_RT_Assembly* m_assm; + + //--// + + bool InitializeFromIndex( const CLR_RT_Assembly_Index& idx ); + void Clear ( ); +}; + +struct CLR_RT_TypeSpec_Instance : public CLR_RT_TypeSpec_Index +{ + CLR_RT_Assembly* m_assm; + CLR_PMETADATA m_target; + + //--// + + bool InitializeFromIndex( const CLR_RT_TypeSpec_Index& idx ); + void Clear ( ); + + bool ResolveToken( CLR_UINT32 tk, CLR_RT_Assembly* assm ); +}; + +//--// + +struct CLR_RT_TypeDef_Instance : public CLR_RT_TypeDef_Index +{ + CLR_RT_Assembly* m_assm; + const CLR_RECORD_TYPEDEF* m_target; + + //--// + + bool InitializeFromReflection ( const CLR_RT_ReflectionDef_Index& reflex, CLR_UINT32* levels ); + bool InitializeFromIndex ( const CLR_RT_TypeDef_Index& idx ); + bool InitializeFromMethod ( const CLR_RT_MethodDef_Instance& md ); + bool InitializeFromField ( const CLR_RT_FieldDef_Instance& fd ); + + void Clear ( ); + + bool ResolveToken( CLR_UINT32 tk, CLR_RT_Assembly* assm ); + + //--// + + CLR_RT_TypeDef_CrossReference& CrossReference() const { return m_assm->m_pCrossReference_TypeDef[ Type() ]; } + + bool SwitchToParent(); + bool HasFinalizer () const; + + bool IsATypeHandler(); +}; + +//--// + +struct CLR_RT_FieldDef_Instance : public CLR_RT_FieldDef_Index +{ + CLR_RT_Assembly* m_assm; + const CLR_RECORD_FIELDDEF* m_target; + + //--// + + bool InitializeFromIndex( const CLR_RT_FieldDef_Index& idx ); + void Clear ( ); + + bool ResolveToken( CLR_UINT32 tk, CLR_RT_Assembly* assm ); + + //--// + + CLR_RT_FieldDef_CrossReference& CrossReference() const { return m_assm->m_pCrossReference_FieldDef[ Field() ]; } +}; + +//--// + +struct CLR_RT_MethodDef_Instance : public CLR_RT_MethodDef_Index +{ + CLR_RT_Assembly* m_assm; + const CLR_RECORD_METHODDEF* m_target; + + //--// + + bool InitializeFromIndex( const CLR_RT_MethodDef_Index& idx ); + void Clear ( ); + + bool ResolveToken( CLR_UINT32 tk, CLR_RT_Assembly* assm ); + + //--// + + CLR_RT_MethodDef_CrossReference& CrossReference() const { return m_assm->m_pCrossReference_MethodDef[ Method() ]; } + CLR_UINT32 Hits() const { return 0; } + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + CLR_RT_MethodDef_DebuggingInfo& DebuggingInfo() const { return m_assm->m_pDebuggingInfo_MethodDef[ Method() ]; } +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) +}; + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +struct CLR_RT_AttributeEnumerator +{ + CLR_RT_Assembly* m_assm; + const CLR_RECORD_ATTRIBUTE* m_ptr; + int m_num; + CLR_RECORD_ATTRIBUTE m_data; + + CLR_RT_MethodDef_Index m_match; + CLR_PMETADATA m_blob; + + void Initialize( const CLR_RT_TypeDef_Instance & inst ); + void Initialize( const CLR_RT_FieldDef_Instance & inst ); + void Initialize( const CLR_RT_MethodDef_Instance& inst ); + + bool Advance(); + + bool MatchNext( const CLR_RT_TypeDef_Instance* instTD, const CLR_RT_MethodDef_Instance* instMD ); + + void GetCurrent(CLR_RT_TypeDef_Instance* instTD); + +private: + void Initialize( CLR_RT_Assembly* assm ); +}; + +struct CLR_RT_AttributeParser +{ + struct Value + { + static const int c_ConstructorArgument = 1; + static const int c_NamedField = 2; + static const int c_NamedProperty = 3; + + int m_mode; + CLR_RT_HeapBlock m_value; + + int m_pos; + const char* m_name; + }; + + //--// + + CLR_RT_Assembly* m_assm; + CLR_PMETADATA m_blob; + + CLR_RT_MethodDef_Instance m_md; + CLR_RT_TypeDef_Instance m_td; + CLR_RT_SignatureParser m_parser; + CLR_RT_SignatureParser::Element m_res; + + int m_currentPos; + int m_fixed_Count; + int m_named_Count; + Value m_lastValue; + + //--// + + HRESULT Initialize( const CLR_RT_AttributeEnumerator& en ); + + HRESULT Next( Value*& res ); + +private: + const char* GetString(); +}; + +//////////////////////////////////////////////////////////////////////////////// + +struct CLR_RT_TypeDescriptor +{ + CLR_UINT32 m_flags; + CLR_RT_TypeDef_Instance m_handlerCls; + + CLR_RT_ReflectionDef_Index m_reflex; + + CLR_DataType GetDataType() const { return (CLR_DataType)m_handlerCls.m_target->dataType; } + + //--// + + void TypeDescriptor_Initialize(); + + HRESULT InitializeFromDataType ( CLR_DataType dt ); + HRESULT InitializeFromReflection ( const CLR_RT_ReflectionDef_Index& reflex ); + HRESULT InitializeFromTypeSpec ( const CLR_RT_TypeSpec_Index& sig ); + HRESULT InitializeFromType ( const CLR_RT_TypeDef_Index& cls ); + HRESULT InitializeFromFieldDefinition( const CLR_RT_FieldDef_Instance& fd ); + HRESULT InitializeFromSignatureParser( CLR_RT_SignatureParser& parser ); + HRESULT InitializeFromObject ( const CLR_RT_HeapBlock& ref ); + + void ConvertToArray(); + bool ShouldEmitHash(); + + bool GetElementType( CLR_RT_TypeDescriptor& sub ); + + static HRESULT ExtractTypeIndexFromObject( const CLR_RT_HeapBlock& ref, CLR_RT_TypeDef_Index& res ); + static HRESULT ExtractObjectAndDataType( CLR_RT_HeapBlock*& ref, CLR_DataType& dt ); +}; + +#include + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +struct CLR_RT_HeapCluster : public CLR_RT_HeapBlock_Node // EVENT HEAP - NO RELOCATION - +{ + CLR_RT_DblLinkedList m_freeList; // list of CLR_RT_HeapBlock_Node + CLR_RT_HeapBlock_Node* m_payloadStart; + CLR_RT_HeapBlock_Node* m_payloadEnd; + + //--// + + void HeapCluster_Initialize( CLR_UINT32 size, CLR_UINT32 blockSize ); // Memory is not erased by the caller. + + CLR_RT_HeapBlock* ExtractBlocks( CLR_UINT32 dataType, CLR_UINT32 flags, CLR_UINT32 length ); + + void RecoverFromGC(); + + CLR_RT_HeapBlock_Node* InsertInOrder( CLR_RT_HeapBlock_Node* node, CLR_UINT32 size ); + + //--// + + #undef DECL_POSTFIX + #if NANOCLR_VALIDATE_HEAP >= NANOCLR_VALIDATE_HEAP_1_HeapBlocksAndUnlink + #define DECL_POSTFIX + #else + #define DECL_POSTFIX {} + #endif + void ValidateBlock( CLR_RT_HeapBlock* ptr ) DECL_POSTFIX; + + //--// + + PROHIBIT_ALL_CONSTRUCTORS(CLR_RT_HeapCluster); +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +//--// + +#ifndef CLR_NO_IL_INLINE +struct CLR_RT_InlineFrame +{ + CLR_RT_HeapBlock* m_locals; + CLR_RT_HeapBlock* m_args; + CLR_RT_HeapBlock* m_evalStack; + CLR_RT_HeapBlock* m_evalPos; + CLR_RT_MethodDef_Instance m_call; + CLR_PMETADATA m_IP; + CLR_PMETADATA m_IPStart; +}; + +struct CLR_RT_InlineBuffer +{ + union + { + CLR_RT_InlineBuffer* m_pNext; + + CLR_RT_InlineFrame m_frame; + }; +}; +#endif + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +struct CLR_RT_StackFrame : public CLR_RT_HeapBlock_Node // EVENT HEAP - NO RELOCATION - +{ + static const int c_OverheadForNewObjOrInteropMethod = 2; // We need to have more slots in the stack to process a 'newobj' opcode. + static const int c_MinimumStack = 10; + + + static const CLR_UINT32 c_MethodKind_Native = 0x00000000; + static const CLR_UINT32 c_MethodKind_Interpreted = 0x00000001; + static const CLR_UINT32 c_UNUSED_00000002 = 0x00000002; // c_MethodKind_Jitted + static const CLR_UINT32 c_MethodKind_Mask = 0x00000003; + + static const CLR_UINT32 c_NativeProfiled = 0x00000004; + static const CLR_UINT32 c_MethodKind_Inlined = 0x00000008; + + static const CLR_UINT32 c_ExecutingConstructor = 0x00000010; + static const CLR_UINT32 c_CompactAndRestartOnOutOfMemory = 0x00000020; + static const CLR_UINT32 c_CallOnPop = 0x00000040; + static const CLR_UINT32 c_CalledOnPop = 0x00000080; + + static const CLR_UINT32 c_NeedToSynchronize = 0x00000100; + static const CLR_UINT32 c_PendingSynchronize = 0x00000200; + static const CLR_UINT32 c_Synchronized = 0x00000400; + static const CLR_UINT32 c_UNUSED_00000800 = 0x00000800; + + static const CLR_UINT32 c_NeedToSynchronizeGlobally = 0x00001000; + static const CLR_UINT32 c_PendingSynchronizeGlobally = 0x00002000; + static const CLR_UINT32 c_SynchronizedGlobally = 0x00004000; + static const CLR_UINT32 c_UNUSED_00008000 = 0x00008000; + + static const CLR_UINT32 c_ExecutingIL = 0x00010000; + static const CLR_UINT32 c_CallerIsCompatibleForCall = 0x00020000; + static const CLR_UINT32 c_CallerIsCompatibleForRet = 0x00040000; + static const CLR_UINT32 c_PseudoStackFrameForFilter = 0x00080000; + + static const CLR_UINT32 c_InlineMethodHasReturnValue = 0x00100000; + static const CLR_UINT32 c_UNUSED_00200000 = 0x00200000; + static const CLR_UINT32 c_UNUSED_00400000 = 0x00400000; + static const CLR_UINT32 c_UNUSED_00800000 = 0x00800000; + + static const CLR_UINT32 c_UNUSED_01000000 = 0x01000000; + static const CLR_UINT32 c_UNUSED_02000000 = 0x02000000; + + static const CLR_UINT32 c_AppDomainMethodInvoke = 0x04000000; + static const CLR_UINT32 c_AppDomainInjectException = 0x08000000; + static const CLR_UINT32 c_AppDomainTransition = 0x10000000; + static const CLR_UINT32 c_InvalidIP = 0x20000000; + static const CLR_UINT32 c_UNUSED_40000000 = 0x40000000; + static const CLR_UINT32 c_HasBreakpoint = 0x80000000; + + static const CLR_UINT32 c_ProcessSynchronize = c_NeedToSynchronize | c_PendingSynchronize | + c_NeedToSynchronizeGlobally | c_PendingSynchronizeGlobally ; + + //--// + + /////////////////////////////////////////////////////////////////////////////////////////// + // + // These fields have to be aligned + // + CLR_RT_Thread* m_owningThread; // EVENT HEAP - NO RELOCATION - + CLR_RT_HeapBlock* m_evalStack; // EVENT HEAP - NO RELOCATION - + CLR_RT_HeapBlock* m_arguments; // EVENT HEAP - NO RELOCATION - + CLR_RT_HeapBlock* m_locals; // EVENT HEAP - NO RELOCATION - + CLR_PMETADATA m_IP; // ANY HEAP - DO RELOCATION - + // + /////////////////////////////////////////////////////////////////////////////////////////// + + CLR_RT_SubThread* m_owningSubThread; // EVENT HEAP - NO RELOCATION - + CLR_UINT32 m_flags; + + CLR_RT_MethodDef_Instance m_call; + + CLR_RT_MethodHandler m_nativeMethod; + CLR_PMETADATA m_IPstart; // ANY HEAP - DO RELOCATION - + + CLR_RT_HeapBlock* m_evalStackPos; // EVENT HEAP - NO RELOCATION - + CLR_RT_HeapBlock* m_evalStackEnd; // EVENT HEAP - NO RELOCATION - + + union + { + CLR_UINT32 m_customState; + void* m_customPointer; + }; + + + #ifndef CLR_NO_IL_INLINE + CLR_RT_InlineBuffer* m_inlineFrame; + #endif + + #if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + CLR_UINT32 m_depth; + #endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + #if defined(NANOCLR_PROFILE_NEW_CALLS) + CLR_PROF_CounterCallChain m_callchain; + #endif + + #if defined(NANOCLR_APPDOMAINS) + CLR_RT_AppDomain* m_appDomain; + #endif + + #if defined(ENABLE_NATIVE_PROFILER) + bool m_fNativeProfiled; + #endif + + CLR_RT_HeapBlock m_extension[ 1 ]; + + //////////////////////////////////////// + + static HRESULT Push( CLR_RT_Thread* th, const CLR_RT_MethodDef_Instance& callInst, CLR_INT32 extraBlocks ); + + void Pop(); + + #ifndef CLR_NO_IL_INLINE + bool PushInline( CLR_PMETADATA& ip, CLR_RT_Assembly*& assm, CLR_RT_HeapBlock*& evalPos, CLR_RT_MethodDef_Instance& calleeInst, CLR_RT_HeapBlock* pThis); + void PopInline ( ); + + void RestoreFromInlineStack(); + void RestoreStack(CLR_RT_InlineFrame& frame); + void SaveStack(CLR_RT_InlineFrame& frame); + #endif + + + #if defined(NANOCLR_APPDOMAINS) + static HRESULT PushAppDomainTransition( CLR_RT_Thread* th, const CLR_RT_MethodDef_Instance& callInst, CLR_RT_HeapBlock* pThis, CLR_RT_HeapBlock* pArgs ); + HRESULT PopAppDomainTransition( ); + #endif + + HRESULT FixCall(); + HRESULT MakeCall ( CLR_RT_MethodDef_Instance md, CLR_RT_HeapBlock* blkThis, CLR_RT_HeapBlock* blkArgs, int nArgs ); + + HRESULT HandleSynchronized( bool fAcquire, bool fGlobal ); + + void SetResult ( CLR_INT32 val, CLR_DataType dataType ); + void SetResult_I1 ( CLR_UINT8 val ); + void SetResult_I2 ( CLR_INT16 val ); + void SetResult_I4 ( CLR_INT32 val ); + void SetResult_I8 ( CLR_INT64& val ); + void SetResult_U1 ( CLR_INT8 val ); + void SetResult_U2 ( CLR_UINT16 val ); + void SetResult_U4 ( CLR_UINT32 val ); + void SetResult_U8 ( CLR_UINT64& val ); + + #if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + void SetResult_R4 ( float val ); + void SetResult_R8 ( double val ); + #else + void SetResult_R4 ( CLR_INT32 val ); + void SetResult_R8 ( CLR_INT64 val ); + #endif + + void SetResult_Boolean( bool val ); + void SetResult_Object ( CLR_RT_HeapBlock* val ); + HRESULT SetResult_String ( const char* val ); + + HRESULT SetupTimeoutFromTicks( CLR_RT_HeapBlock& input, CLR_INT64*& output ); + + void ConvertResultToBoolean(); + void NegateResult (); + + HRESULT NotImplementedStub(); + + void Relocate(); + + //////////////////////////////////////// + + CLR_RT_HeapBlock& ThisRef() const { return m_arguments[ 0 ]; } + CLR_RT_HeapBlock* This() const { return ThisRef().Dereference(); } + + CLR_RT_HeapBlock& Arg0() const { return m_arguments[ 0 ]; } + CLR_RT_HeapBlock& Arg1() const { return m_arguments[ 1 ]; } + CLR_RT_HeapBlock& Arg2() const { return m_arguments[ 2 ]; } + CLR_RT_HeapBlock& Arg3() const { return m_arguments[ 3 ]; } + CLR_RT_HeapBlock& Arg4() const { return m_arguments[ 4 ]; } + CLR_RT_HeapBlock& Arg5() const { return m_arguments[ 5 ]; } + CLR_RT_HeapBlock& Arg6() const { return m_arguments[ 6 ]; } + CLR_RT_HeapBlock& Arg7() const { return m_arguments[ 7 ]; } + + CLR_RT_HeapBlock& ArgN( CLR_INT32 n ) const { return m_arguments[ n ]; } + + CLR_RT_HeapBlock& TopValue () { return m_evalStackPos[ -1 ]; } + CLR_RT_HeapBlock& PushValue () { _ASSERTE(m_evalStackPos < m_evalStackEnd); return * m_evalStackPos++; } + CLR_RT_HeapBlock& PopValue () { _ASSERTE(m_evalStackPos > m_evalStack ); return *--m_evalStackPos; } + void ResetStack () { m_evalStackPos = m_evalStack ; } + int TopValuePosition () { return (int)(m_evalStackPos - m_evalStack); } + + CLR_RT_MethodDef_Instance& MethodCall() { return m_call; } + + CLR_RT_HeapBlock& PushValueAndClear() + { + CLR_RT_HeapBlock& val = PushValue(); + + val.SetObjectReference( NULL ); + + return val; + } + + CLR_RT_HeapBlock& PushValueAndAssign( const CLR_RT_HeapBlock& value ) + { + CLR_RT_HeapBlock& top = PushValue(); + + top.Assign( value ); + + return top; + } + + + inline void PushValueI4( CLR_INT32 val ) { SetResult_I4( val ); } + + //--// + + CLR_RT_StackFrame* Caller() { return (CLR_RT_StackFrame*)Prev(); } + CLR_RT_StackFrame* Callee() { return (CLR_RT_StackFrame*)Next(); } + + PROHIBIT_ALL_CONSTRUCTORS(CLR_RT_StackFrame); +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +// +// This CT_ASSERT macro generates a compiler error in case these fields get out of alignment. +// +// The use of offsetof below throwns an "invalid offset warning" because CLR_RT_StackFrame is not POD type +// C+17 is the first standard that allow this, so until we are using it we have to disable it to keep GCC happy + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Winvalid-offsetof" +#endif + +CT_ASSERT( offsetof(CLR_RT_StackFrame,m_owningThread) + sizeof(CLR_UINT32) == offsetof(CLR_RT_StackFrame,m_evalStack ) ) +CT_ASSERT( offsetof(CLR_RT_StackFrame,m_evalStack ) + sizeof(CLR_UINT32) == offsetof(CLR_RT_StackFrame,m_arguments ) ) +CT_ASSERT( offsetof(CLR_RT_StackFrame,m_arguments ) + sizeof(CLR_UINT32) == offsetof(CLR_RT_StackFrame,m_locals ) ) +CT_ASSERT( offsetof(CLR_RT_StackFrame,m_locals ) + sizeof(CLR_UINT32) == offsetof(CLR_RT_StackFrame,m_IP ) ) + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +//////////////////////////////////////////////////////////////////////////////// + +struct CLR_RT_ProtectFromGC +{ + static const CLR_UINT32 c_Generic = 0x00000001; + static const CLR_UINT32 c_HeapBlock = 0x00000002; + static const CLR_UINT32 c_ResetKeepAlive = 0x00000004; + + typedef void (*Callback)( void* state ); + + static CLR_RT_ProtectFromGC* s_first; + + CLR_RT_ProtectFromGC* m_next; + void** m_data; + Callback m_fpn; + CLR_UINT32 m_flags; + + CLR_RT_ProtectFromGC ( CLR_RT_HeapBlock& ref ) { Initialize( ref ); } + CLR_RT_ProtectFromGC ( void** data, Callback fpn ) { Initialize( data, fpn ); } + ~CLR_RT_ProtectFromGC( ) { Cleanup ( ); } + + static void InvokeAll(); + +private: + void Initialize( CLR_RT_HeapBlock& ref ); + void Initialize( void** data, Callback fpn ); + void Cleanup ( ); + + void Invoke(); +}; + +//////////////////////////////////////// + +#if defined(NANOCLR_TRACE_EARLYCOLLECTION) + +struct CLR_RT_AssertEarlyCollection +{ + static CLR_RT_AssertEarlyCollection* s_first; + + CLR_RT_AssertEarlyCollection* m_next; + CLR_RT_HeapBlock* m_ptr; + + CLR_RT_AssertEarlyCollection( CLR_RT_HeapBlock* ptr ); + ~CLR_RT_AssertEarlyCollection(); + + void Cancel(); + + static void CheckAll( CLR_RT_HeapBlock* ptr ); +}; + +#define NANOCLR_FAULT_ON_EARLY_COLLECTION(ptr) CLR_RT_AssertEarlyCollection aec##ptr( ptr ) +#define NANOCLR_CANCEL_EARLY_COLLECTION(ptr) aec##ptr.Cancel() +#define NANOCLR_CHECK_EARLY_COLLECTION(ptr) CLR_RT_AssertEarlyCollection::CheckAll( ptr ) + +#else + +#define NANOCLR_FAULT_ON_EARLY_COLLECTION(ptr) +#define NANOCLR_CANCEL_EARLY_COLLECTION(ptr) +#define NANOCLR_CHECK_EARLY_COLLECTION(ptr) + +#endif + +//////////////////////////////////////// + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +struct CLR_RT_GarbageCollector +{ + typedef bool (*MarkSingleFtn )( CLR_RT_HeapBlock** ptr ); + typedef bool (*MarkMultipleFtn)( CLR_RT_HeapBlock* lstExt, CLR_UINT32 numExt ); + typedef bool (*RelocateFtn )( void** ref ); + + struct MarkStackElement + { + CLR_RT_HeapBlock* ptr; + CLR_UINT32 num; + #if defined(NANOCLR_VALIDATE_APPDOMAIN_ISOLATION) + CLR_RT_AppDomain* appDomain; + #endif + }; + + struct MarkStack : CLR_RT_HeapBlock_Node + { + MarkStackElement* m_last; + MarkStackElement* m_top; + + void Initialize( MarkStackElement* ptr, size_t num ); + }; + + struct RelocationRegion + { + CLR_UINT8* m_start; + CLR_UINT8* m_end; + CLR_UINT8* m_destination; + CLR_UINT32 m_offset; + }; + + //--// + + static const int c_minimumSpaceForGC = 128; + static const int c_minimumSpaceForCompact = 128; + static const CLR_UINT32 c_pressureThreshold = 10; + static const CLR_UINT32 c_memoryThreshold = HEAP_SIZE_THRESHOLD; + static const CLR_UINT32 c_memoryThreshold2 = HEAP_SIZE_THRESHOLD_UPPER; + + static const CLR_UINT32 c_StartGraphEvent = 0x00000001; + static const CLR_UINT32 c_StopGraphEvent = 0x00000002; + static const CLR_UINT32 c_DumpGraphHeapEvent = 0x00000004; + static const CLR_UINT32 c_DumpPerfCountersEvent = 0x00000008; + + CLR_UINT32 m_numberOfGarbageCollections; + CLR_UINT32 m_numberOfCompactions; + + CLR_RT_DblLinkedList m_weakDelegates_Reachable; // list of CLR_RT_HeapBlock_Delegate_List + + + CLR_UINT32 m_totalBytes; + CLR_UINT32 m_freeBytes; + CLR_UINT32 m_pressureCounter; + + CLR_RT_DblLinkedList* m_markStackList; + MarkStack* m_markStack; + + RelocationRegion* m_relocBlocks; + size_t m_relocTotal; + size_t m_relocCount; + CLR_UINT8* m_relocMinimum; + CLR_UINT8* m_relocMaximum; + #if NANOCLR_VALIDATE_HEAP > NANOCLR_VALIDATE_HEAP_0_None + RelocateFtn m_relocWorker; + #endif + + MarkSingleFtn m_funcSingleBlock; + MarkMultipleFtn m_funcMultipleBlocks; + + bool m_fOutOfStackSpaceForGC; + + #if defined(_WIN32) + CLR_UINT32 m_events; + #endif + + //--// + + CLR_UINT32 ExecuteGarbageCollection(); + CLR_UINT32 ExecuteCompaction (); + + void Mark (); + void MarkWeak (); + void Sweep (); + void CheckMemoryPressure(); + + #if defined(NANOCLR_APPDOMAINS) + void AppDomain_Mark(); + #endif + + void Assembly_Mark(); + + void Thread_Mark( CLR_RT_DblLinkedList& threads ); + void Thread_Mark( CLR_RT_Thread* thread ); + + void Heap_Compact (); + CLR_UINT32 Heap_ComputeAliveVsDeadRatio(); + + void RecoverEventsFromGC(); + + void Heap_Relocate_Prepare ( RelocationRegion* blocks, size_t total ); + void Heap_Relocate_AddBlock( CLR_UINT8* dst, CLR_UINT8* src, CLR_UINT32 length ); + void Heap_Relocate ( ); + + //--// + + static void Heap_Relocate( CLR_RT_HeapBlock* lst, CLR_UINT32 len ); + static void Heap_Relocate( void** ref ); + + //--// + + #if NANOCLR_VALIDATE_HEAP >= NANOCLR_VALIDATE_HEAP_3_Compaction + + static bool Relocation_JustCheck( void** ref ); + + void ValidatePointers() { Heap_Relocate_Pass( Relocation_JustCheck ); } + + static void ValidateCluster ( CLR_RT_HeapCluster* hc ); + static void ValidateHeap ( CLR_RT_DblLinkedList& lst ); + static void ValidateBlockNotInFreeList( CLR_RT_DblLinkedList& lst, CLR_RT_HeapBlock_Node* dst ); + static bool IsBlockInFreeList ( CLR_RT_DblLinkedList& lst, CLR_RT_HeapBlock_Node* dst, bool fExact ); + static bool IsBlockInHeap ( CLR_RT_DblLinkedList& lst, CLR_RT_HeapBlock_Node* dst ); + + #else + + void ValidatePointers() {} + + static void ValidateCluster ( CLR_RT_HeapCluster* hc ) {} + static void ValidateHeap ( CLR_RT_DblLinkedList& lst ) {} + static void ValidateBlockNotInFreeList( CLR_RT_DblLinkedList& lst, CLR_RT_HeapBlock_Node* dst ) {} + + #endif + + #if NANOCLR_VALIDATE_HEAP >= NANOCLR_VALIDATE_HEAP_4_CompactionPlus + + struct RelocationRecord + { + void** oldRef; + CLR_UINT32* oldPtr; + + void** newRef; + CLR_UINT32* newPtr; + + CLR_UINT32 data; + }; + + typedef std::list Rel_List; + typedef Rel_List::iterator Rel_List_Iter; + + typedef std::map< void**, RelocationRecord* > Rel_Map; + typedef Rel_Map::iterator Rel_Map_Iter; + + static Rel_List s_lstRecords; + static Rel_Map s_mapOldToRecord; + static Rel_Map s_mapNewToRecord; + + void Relocation_UpdatePointer(void** ref); + + static bool TestPointers_PopulateOld_Worker( void** ref ); + static bool TestPointers_PopulateNew_Worker( void** ref ); + + void TestPointers_PopulateOld(); + void TestPointers_Remap (); + void TestPointers_PopulateNew(); + + #else + + void TestPointers_PopulateOld() {} + void TestPointers_Remap () {} + void TestPointers_PopulateNew() {} + + #endif + + //--// + + #if defined(NANOCLR_GC_VERBOSE) + + void GC_Stats( int& resNumberObjects, int& resSizeObjects, int& resNumberEvents, int& resSizeEvents ); + + void DumpThreads ( ); + + #else + + void GC_Stats( int& resNumberObjects, int& resSizeObjects, int& resNumberEvents, int& resSizeEvents ) + { + resNumberObjects = 0; + resSizeObjects = 0; + resNumberEvents = 0; + resSizeEvents = 0; + } + + void DumpThreads ( ) {} + + #endif + + //--// + + bool CheckSingleBlock( CLR_RT_HeapBlock** ptr ) { return m_funcSingleBlock( ( CLR_RT_HeapBlock* *)ptr ); } + bool CheckSingleBlock( CLR_RT_HeapBlock_Array** ptr ) { return m_funcSingleBlock( (CLR_RT_HeapBlock* *)ptr ); } + bool CheckSingleBlock( CLR_RT_HeapBlock_Delegate** ptr ) { return m_funcSingleBlock( (CLR_RT_HeapBlock* *)ptr ); } + + bool CheckSingleBlock_Force( CLR_RT_HeapBlock* ptr ) { return ptr ? m_funcMultipleBlocks( ptr, 1 ) : true; } + bool CheckMultipleBlocks ( CLR_RT_HeapBlock* lst, CLR_UINT32 num ) { return lst ? m_funcMultipleBlocks( lst, num ) : true; } + + //--// + + static bool ComputeReachabilityGraphForSingleBlock ( CLR_RT_HeapBlock** ptr ); + static bool ComputeReachabilityGraphForMultipleBlocks( CLR_RT_HeapBlock* lst, CLR_UINT32 num ); + + //--// + + PROHIBIT_COPY_CONSTRUCTORS(CLR_RT_GarbageCollector); + + //--// + + private: + + void Heap_Relocate_Pass( RelocateFtn ftn ); + + void MarkSlow(); +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +extern CLR_RT_GarbageCollector g_CLR_RT_GarbageCollector; + +//--// + +struct CLR_RT_SubThread : public CLR_RT_HeapBlock_Node // EVENT HEAP - NO RELOCATION - +{ + static const int MODE_IncludeSelf = 0x00000001; + static const int MODE_CheckLocks = 0x00000002; + + static const int STATUS_Triggered = 0x00000001; + + CLR_RT_Thread* m_owningThread; // EVENT HEAP - NO RELOCATION - + CLR_RT_StackFrame* m_owningStackFrame; + CLR_UINT32 m_lockRequestsCount; + + int m_priority; + CLR_INT64 m_timeConstraint; + CLR_UINT32 m_status; + + //--// + + static HRESULT CreateInstance ( CLR_RT_Thread* th, CLR_RT_StackFrame* stack , int priority, CLR_RT_SubThread*& sth ); + static void DestroyInstance( CLR_RT_Thread* th, CLR_RT_SubThread* sthBase, int flags ); + + bool ChangeLockRequestCount( int diff ); + + //--// + + PROHIBIT_ALL_CONSTRUCTORS(CLR_RT_SubThread); +}; + +//--// + +struct CLR_RT_ExceptionHandler +{ + union { + CLR_RT_TypeDef_Index m_typeFilter; + CLR_PMETADATA m_userFilterStart; + }; + CLR_PMETADATA m_tryStart; + CLR_PMETADATA m_tryEnd; + CLR_PMETADATA m_handlerStart; + CLR_PMETADATA m_handlerEnd; + + CLR_UINT16 m_ehType; + //--// + + bool ConvertFromEH( const CLR_RT_MethodDef_Instance& owner, CLR_PMETADATA ipStart, const CLR_RECORD_EH* ehPtr ); + + bool IsCatch() const { return m_ehType == CLR_RECORD_EH::EH_Catch ; } + bool IsCatchAll() const { return m_ehType == CLR_RECORD_EH::EH_CatchAll ; } + bool IsFilter() const { return m_ehType == CLR_RECORD_EH::EH_Filter ; } + bool IsFinally() const { return m_ehType == CLR_RECORD_EH::EH_Finally ; } + +}; + + +// +// Directly from the .NET enumerator. +// +struct ThreadPriority +{ + /*========================================================================= + ** Constants for thread priorities. + =========================================================================*/ + static const int Lowest = 0; + static const int BelowNormal = 1; + static const int Normal = 2; + static const int AboveNormal = 3; + static const int Highest = 4; + // One more priority for internal creation of managed code threads. + // We do not expose this priority to C# applications. + static const int System_Highest = 5; +}; + +struct CLR_RT_Thread : public CLR_RT_ObjectToEvent_Destination // EVENT HEAP - NO RELOCATION - +{ + typedef void (*ThreadTerminationCallback)( void* arg ); + + struct UnwindStack + { + CLR_RT_StackFrame* m_stack; + CLR_RT_HeapBlock* m_exception; + CLR_PMETADATA m_ip; + + CLR_PMETADATA m_currentBlockStart; + CLR_PMETADATA m_currentBlockEnd; + CLR_PMETADATA m_handlerBlockStart; + CLR_PMETADATA m_handlerBlockEnd; + + CLR_RT_StackFrame* m_handlerStack; + CLR_UINT8 m_flags; + + static const CLR_UINT8 p_Phase_Mask = 0x07; + static const CLR_UINT8 p_1_SearchingForHandler_0 = 0x01; + static const CLR_UINT8 p_1_SearchingForHandler_1_SentFirstChance = 0x02; + static const CLR_UINT8 p_1_SearchingForHandler_2_SentUsersChance = 0x03; + static const CLR_UINT8 p_2_RunningFinallys_0 = 0x04; + static const CLR_UINT8 p_2_RunningFinallys_1_SentUnwindBegin = 0x05; + static const CLR_UINT8 p_3_RunningHandler = 0x06; + static const CLR_UINT8 p_4_NormalCleanup = 0x07; + + static const CLR_UINT8 c_MagicCatchForInline = 0x20; + static const CLR_UINT8 c_MagicCatchForInteceptedException = 0x40; + static const CLR_UINT8 c_ContinueExceptionHandler = 0x80; + + CLR_UINT8 inline GetPhase() { return m_flags & p_Phase_Mask; } + void inline SetPhase(CLR_UINT8 phase) + { + _ASSERTE((phase & ~p_Phase_Mask) == 0); + m_flags = (m_flags & ~p_Phase_Mask) | phase; + } + + }; + + static const CLR_UINT32 TH_S_Ready = 0x00000000; + static const CLR_UINT32 TH_S_Waiting = 0x00000001; + static const CLR_UINT32 TH_S_Terminated = 0x00000002; + static const CLR_UINT32 TH_S_Unstarted = 0x00000003; + + static const CLR_UINT32 TH_F_Suspended = 0x00000001; + static const CLR_UINT32 TH_F_Aborted = 0x00000002; + static const CLR_UINT32 TH_F_System = 0x00000004; + static const CLR_UINT32 TH_F_ContainsDoomedAppDomain = 0x00000008; + + static const CLR_INT32 TH_WAIT_RESULT_INIT = -1; + static const CLR_INT32 TH_WAIT_RESULT_HANDLE_0 = 0; + static const CLR_INT32 TH_WAIT_RESULT_TIMEOUT = 0x102; //WaitHandle.WaitTimeout + static const CLR_INT32 TH_WAIT_RESULT_HANDLE_ALL = 0x103; + + static const CLR_UINT32 c_TimeQuantum_Milliseconds = 20; + static const int c_MaxStackUnwindDepth = 6; + + int m_pid; + CLR_UINT32 m_status; + CLR_UINT32 m_flags; + int m_executionCounter; + volatile bool m_timeQuantumExpired; + + CLR_RT_HeapBlock_Delegate* m_dlg; // OBJECT HEAP - DO RELOCATION - + CLR_RT_HeapBlock m_currentException; // OBJECT HEAP - DO RELOCATION - + UnwindStack m_nestedExceptions[ c_MaxStackUnwindDepth ]; + int m_nestedExceptionsPos; + + //--// + + // + // For example, timers are implemented in terms of Threads. If not NULL, this is a worker thread for a timer. + // + ThreadTerminationCallback m_terminationCallback; + void* m_terminationParameter; // EVENT HEAP - NO RELOCATION - + + CLR_UINT32 m_waitForEvents; + CLR_INT64 m_waitForEvents_Timeout; + CLR_INT64 m_waitForEvents_IdleTimeWorkItem; + + CLR_RT_DblLinkedList m_locks; // EVENT HEAP - NO RELOCATION - list of CLR_RT_HeapBlock_Lock + CLR_UINT32 m_lockRequestsCount; + + CLR_RT_HeapBlock_WaitForObject* m_waitForObject; // EVENT HEAP - NO RELOCATION, but the objects they point to do + CLR_INT32 m_waitForObject_Result; + + CLR_RT_DblLinkedList m_stackFrames; // EVENT HEAP - NO RELOCATION - list of CLR_RT_StackFrame + + CLR_RT_DblLinkedList m_subThreads; // EVENT HEAP - NO RELOCATION - list of CLR_RT_SubThread + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + int m_scratchPad; + bool m_fHasJMCStepper; + + CLR_RT_Thread* m_realThread; // Normally, this points to the CLR_RT_Thread object that contains it. + // However, if this thread was spawned on behalf of the debugger to evaluate + // a property or function call, it points to the object coresponding to the + // thread that is currently selected in the debugger. +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + +#if defined(ENABLE_NATIVE_PROFILER) + bool m_fNativeProfiled; +#endif + + //--// + + static HRESULT CreateInstance( int pid, CLR_RT_HeapBlock_Delegate* pDelegate, int priority, CLR_RT_Thread*& th, CLR_UINT32 flags ); + static HRESULT CreateInstance( int pid, int priority, CLR_RT_Thread*& th, CLR_UINT32 flags ); + HRESULT PushThreadProcDelegate( CLR_RT_HeapBlock_Delegate* pDelegate ); + + void DestroyInstance(); + + HRESULT Execute (); + + HRESULT Suspend (); + HRESULT Resume (); + HRESULT Terminate(); + HRESULT Abort (); + + void Restart( bool fDeleteEvent ); + + void Passivate(); + + bool CouldBeActivated(); + + void RecoverFromGC(); + + void Relocate(); + + UnwindStack* PushEH ( ); + void PopEH_Inner( CLR_RT_StackFrame* stack, CLR_PMETADATA ip ); + bool FindEhBlock( CLR_RT_StackFrame* stack, CLR_PMETADATA from, CLR_PMETADATA to, CLR_RT_ExceptionHandler& eh, bool onlyFinallys ); + + + HRESULT ProcessException ( ); + HRESULT ProcessException_EndFilter ( ); + HRESULT ProcessException_EndFinally ( ); + HRESULT ProcessException_Phase1 ( ); + HRESULT ProcessException_Phase2 ( ); + void ProcessException_FilterPseudoFrameCopyVars(CLR_RT_StackFrame* to, CLR_RT_StackFrame* from); + + static void ProtectFromGCCallback( void* state ); + + static HRESULT Execute_DelegateInvoke( CLR_RT_StackFrame& stack ); + static HRESULT Execute_IL ( CLR_RT_StackFrame& stack ); + + //--// + + CLR_RT_StackFrame* FirstFrame () const { return (CLR_RT_StackFrame*)m_stackFrames.FirstNode(); } + CLR_RT_StackFrame* CurrentFrame() const { return (CLR_RT_StackFrame*)m_stackFrames.LastNode (); } + + CLR_RT_SubThread* CurrentSubThread() const { return (CLR_RT_SubThread*)m_subThreads.LastNode(); } + +#if defined(NANOCLR_APPDOMAINS) + CLR_RT_AppDomain* CurrentAppDomain() const { CLR_RT_StackFrame* stack = CurrentFrame(); return stack->Prev() ? stack->m_appDomain : NULL; } +#endif + + // Just return priority, no way to set it through this function. + int GetThreadPriority() const { return CurrentSubThread()->m_priority; } + // Here we set it. This function is called if managed code changes thread priority. + void SetThreadPriority( int threadPri ) { CurrentSubThread()->m_priority = threadPri; } + + int GetExecutionCounter() const { return CurrentSubThread()->m_priority + m_executionCounter; } + + // QuantumDebit is update for execution counter for each quantum: + // System_Highest - 1 + // Highest - 2 + // Above Normal - 4 + // Normal - 8 + // Below Normal - 16 + // Lowest - 32 + int GetQuantumDebit() const { return 1 << ( ThreadPriority::System_Highest - GetThreadPriority() ); } + + // If thread was sleeping and get too far behind on updating of m_executionCounter + // Then we make m_executionCounter 4 quantums above m_GlobalExecutionCounter; + void BringExecCounterToDate( int iGlobalExecutionCounter, int iDebitForEachRun ); + + void PopEH( CLR_RT_StackFrame* stack, CLR_PMETADATA ip ) { if(m_nestedExceptionsPos) PopEH_Inner( stack, ip ); } + +#if defined(NANOCLR_TRACE_CALLS) + void DumpStack(); +#else + void DumpStack() {} +#endif + + bool IsFinalizerThread(); + bool ReleaseWhenDeadEx(); + void OnThreadTerminated(); + bool CanThreadBeReused(); + + //--// + + PROHIBIT_ALL_CONSTRUCTORS(CLR_RT_Thread); + + //--// + +private: + + HRESULT Execute_Inner(); +}; + +//////////////////////////////////////////////////////////////////////////////// + +extern size_t LinkArraySize (); +extern size_t LinkMRUArraySize(); +extern size_t PayloadArraySize(); +extern size_t InterruptRecords(); +#ifndef CLR_NO_IL_INLINE +extern size_t InlineBufferCount(); +#endif + + +extern CLR_UINT32 g_scratchVirtualMethodTableLink []; +extern CLR_UINT32 g_scratchVirtualMethodTableLinkMRU []; +extern CLR_UINT32 g_scratchVirtualMethodPayload []; +extern CLR_UINT32 g_scratchInterruptDispatchingStorage[]; +#ifndef CLR_NO_IL_INLINE +extern CLR_UINT32 g_scratchInlineBuffer []; +#endif + +//////////////////////////////////////////////////////////////////////////////// + +struct CLR_RT_EventCache +{ + struct BoundedList + { + CLR_RT_DblLinkedList m_blocks; + }; + +#if defined(NANOCLR_USE_AVLTREE_FOR_METHODLOOKUP) + + struct Payload + { + // + // The first two fields compose the key, the last field is the value. + // + CLR_RT_MethodDef_Index m_mdVirtual; // The definition of the virtual method. + CLR_RT_TypeDef_Index m_cls; // The class of the instance we need to resolve. + CLR_RT_MethodDef_Index m_md; // The actual implementation of the virtual method. + + //--// + + int Compare( Payload& right ) + { + if(m_mdVirtual.m_data == right.m_mdVirtual.m_data) + { + if(m_cls.m_data == right.m_cls.m_data) return 0; + + return m_cls.m_data < right.m_cls.m_data ? -1 : 1; + } + + return m_mdVirtual.m_data < right.m_mdVirtual.m_data ? -1 : 1; + } + }; + + struct LookupEntry : public CLR_RT_AVLTree::Entry + { + Payload m_payload; + + //--// + + static int Callback_Compare( void* state, CLR_RT_AVLTree::Entry* left, CLR_RT_AVLTree::Entry* right ); + }; + + struct VirtualMethodTable + { + CLR_RT_AVLTree m_tree; + LookupEntry* m_entries; + + CLR_RT_DblLinkedList m_list_freeItems; // list of CLR_RT_EventCache::LookupEntry + CLR_RT_DblLinkedList m_list_inUse; // list of CLR_RT_EventCache::LookupEntry + + //--// + + void Initialize(); + + bool FindVirtualMethod( const CLR_RT_TypeDef_Index& cls, const CLR_RT_MethodDef_Index& mdVirtual, CLR_RT_MethodDef_Index& md ); + + //--// + + static CLR_RT_AVLTree::Entry* Callback_NewNode ( void* state, CLR_RT_AVLTree::Entry* payload ); + static void Callback_FreeNode( void* state, CLR_RT_AVLTree::Entry* node ); + static void Callback_Reassign( void* state, CLR_RT_AVLTree::Entry* from, CLR_RT_AVLTree::Entry* to ); + + //--// + +#if defined(_WIN32) + void DumpTree ( ); + bool ConsistencyCheck( ); + bool ConsistencyCheck( LookupEntry* node, int& depth ); +#else + void DumpTree () { } + bool ConsistencyCheck() { return true; } +#endif + }; + +#else + + struct Link + { + CLR_UINT16 m_next; + CLR_UINT16 m_prev; + }; + + struct Payload + { + struct Key + { + CLR_RT_MethodDef_Index m_mdVirtual; // The definition of the virtual method. + CLR_RT_TypeDef_Index m_cls; // The class of the instance we need to resolve. + }; + + Key m_key; + CLR_RT_MethodDef_Index m_md; // The actual implementation of the virtual method. + }; + + struct VirtualMethodTable + { + Link* m_entries; + Link* m_entriesMRU; + Payload* m_payloads; + + //--// + + void Initialize(); + + bool FindVirtualMethod( const CLR_RT_TypeDef_Index& cls, const CLR_RT_MethodDef_Index& mdVirtual, CLR_RT_MethodDef_Index& md ); + + private: + + CLR_UINT32 GetNewEntry() { return m_entriesMRU[ LinkMRUArraySize() - 1 ].m_prev; } + + static void MoveEntryToTop( Link* entries, CLR_UINT32 slot, CLR_UINT32 idx ); + }; +#endif + + //--// + + static const CLR_UINT16 c_maxFastLists = 40; + + // the scratch array is used to avoid bringing in arm ABI methods (for semihosting) + // struct arrays require initialization with the v3.0 compiler and this is done with ABI methods, + // unless of course you provide a work around lik this ;-) + unsigned int m_scratch[ (sizeof(BoundedList) * c_maxFastLists + 3) / sizeof(unsigned int) ]; + BoundedList* m_events; + + VirtualMethodTable m_lookup_VirtualMethod; +#ifndef CLR_NO_IL_INLINE + CLR_RT_InlineBuffer* m_inlineBufferStart; +#endif + + //--// + + void EventCache_Initialize(); + CLR_UINT32 EventCache_Cleanup (); + + void Append_Node ( CLR_RT_HeapBlock* node ); + CLR_RT_HeapBlock* Extract_Node_Slow ( CLR_UINT32 dataType, CLR_UINT32 flags, CLR_UINT32 blocks ); + CLR_RT_HeapBlock* Extract_Node_Fast ( CLR_UINT32 dataType, CLR_UINT32 flags, CLR_UINT32 blocks ); + CLR_RT_HeapBlock* Extract_Node_Bytes( CLR_UINT32 dataType, CLR_UINT32 flags, CLR_UINT32 bytes ); + CLR_RT_HeapBlock* Extract_Node ( CLR_UINT32 dataType, CLR_UINT32 flags, CLR_UINT32 blocks ); + + bool FindVirtualMethod( const CLR_RT_TypeDef_Index& cls, const CLR_RT_MethodDef_Index& mdVirtual, CLR_RT_MethodDef_Index& md ); + +#ifndef CLR_NO_IL_INLINE + bool GetInlineFrameBuffer(CLR_RT_InlineBuffer** ppBuffer); + bool FreeInlineBuffer(CLR_RT_InlineBuffer* pBuffer); +#endif + + //--// + +#define EVENTCACHE_EXTRACT_NODE_AS_BYTES(ev,cls,type,flags,size) (cls*)((ev).Extract_Node_Bytes( type, flags, size )) +#define EVENTCACHE_EXTRACT_NODE_AS_BLOCKS(ev,cls,type,flags,size) (cls*)((ev).Extract_Node( type, flags, size )) +#define EVENTCACHE_EXTRACT_NODE(ev,cls,type) EVENTCACHE_EXTRACT_NODE_AS_BLOCKS(ev,cls,type, 0,CONVERTFROMSIZETOHEAPBLOCKS(sizeof(cls))) +#define EVENTCACHE_EXTRACT_NODE_NOALLOC(ev,cls,type) EVENTCACHE_EXTRACT_NODE_AS_BLOCKS(ev,cls,type,CLR_RT_HeapBlock::HB_NoGcOnFailure ,CONVERTFROMSIZETOHEAPBLOCKS(sizeof(cls))) +#define EVENTCACHE_EXTRACT_NODE_INITTOZERO(ev,cls,type) EVENTCACHE_EXTRACT_NODE_AS_BLOCKS(ev,cls,type,CLR_RT_HeapBlock::HB_InitializeToZero,CONVERTFROMSIZETOHEAPBLOCKS(sizeof(cls))) + + //--// + + PROHIBIT_COPY_CONSTRUCTORS(CLR_RT_EventCache); +}; + +extern CLR_RT_EventCache g_CLR_RT_EventCache; + +////////////////////////////////////////////////////////////////////////////////////// +// keep under control the size of the Link and Payload, since we will use externally +// defined arrays to handle those data structures in the Virtual Method cache + +#if defined(NANOCLR_USE_AVLTREE_FOR_METHODLOOKUP) +CT_ASSERT( sizeof(CLR_RT_EventCache::LookupEntry) == 12 ) +#else +CT_ASSERT( sizeof(CLR_RT_EventCache::Link) == 4 ) +CT_ASSERT( sizeof(CLR_RT_EventCache::Payload) == 12 ) +#endif + +////////////////////////////////////////////////////////////////////////////////////// + +//--// + +#include +#include +//#include + +//--// + +#if defined(NANOCLR_TRACE_STACK) + +// +// If this is set, no memory allocation should be allowed, it could lead to a GC while in an inconsistent state!! +// +extern bool g_CLR_RT_fBadStack; + +#endif + +//--// + +struct CLR_RT_ExecutionEngine +{ + static const CLR_UINT32 c_Event_SerialPortIn = 0x00000002; + static const CLR_UINT32 c_Event_SerialPortOut = 0x00000004; + static const CLR_UINT32 c_Event_EndPoint = 0x00000008; + static const CLR_UINT32 c_Event_StorageIo = 0x00000020; + static const CLR_UINT32 c_Event_I2cMaster = 0x00000080; + static const CLR_UINT32 c_Event_SpiMaster = 0x00000100; + static const CLR_UINT32 c_Event_OneWireMaster = 0x00000200; + static const CLR_UINT32 c_Event_AppDomain = 0x02000000; + static const CLR_UINT32 c_Event_Socket = 0x20000000; + static const CLR_UINT32 c_Event_IdleCPU = 0x40000000; + static const CLR_UINT32 c_Event_LowMemory = 0x80000000; // Wait for a low-memory condition. + + + //////////////////////////////////////////////////////////////////////////////////////////////// + + static const CLR_UINT32 c_Compile_CPP = 0x00000001; + static const CLR_UINT32 c_Compile_ARM = 0x00000002; + + //////////////////////////////////////////////////////////////////////////////////////////////// + + static const int c_HeapState_Normal = 0x00000000; + static const int c_HeapState_UnderGC = 0x00000001; + + //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // NEED TO KEEP THESE IN SYNC WITH Enum 'Commands.Debugging_Execution_ChangeConditions...' on debugger library code // + //////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + + static const int c_fDebugger_StateInitialize = 0x00000000; + static const int c_fDebugger_StateResolutionFailed = 0x00000001; + static const int c_fDebugger_StateProgramRunning = 0x00000400; + static const int c_fDebugger_StateProgramExited = 0x00000800; + static const int c_fDebugger_StateMask = c_fDebugger_StateProgramRunning + c_fDebugger_StateProgramExited; + // + static const int c_fDebugger_BreakpointsDisabled = 0x00001000; + // + static const int c_fDebugger_Quiet = 0x00010000; // Do not spew debug text to the debugger + static const int c_fDebugger_ExitPending = 0x00020000; + // + static const int c_fDebugger_PauseTimers = 0x04000000; // Threads associated with timers are created in "suspended" mode. + static const int c_fDebugger_NoCompaction = 0x08000000; // Don't perform compaction during execution. + // + static const int c_fDebugger_SourceLevelDebugging = 0x10000000; + static const int c_fDebugger_RebootPending = 0x20000000; + static const int c_fDebugger_Enabled = 0x40000000; + static const int c_fDebugger_Stopped = 0x80000000; + + volatile int m_iDebugger_Conditions; + + //////////////////////////////////////////////////////////////////////////////////////////////// + + static const int c_fExecution_GC_Pending = 0x00000001; //Not currently used + static const int c_fExecution_Compaction_Pending = 0x00000002; +#if defined(NANOCLR_APPDOMAINS) + static const int c_fExecution_UnloadingAppDomain = 0x00000004; +#endif + + int m_iExecution_Conditions; + + int m_iReboot_Options; + + //////////////////////////////////////////////////////////////////////////////////////////////// + + static const int c_fProfiling_Enabled = 0x00000001; + static const int c_fProfiling_Allocations = 0x00000002; + static const int c_fProfiling_Calls = 0x00000004; + static const int c_fProfiling_CLRTypes = 0x00000008; //Don't dump out certain types, like ASSEMBLY, or THREAD, or BINARY_BLOB, etc. + int m_iProfiling_Conditions; + + enum + { EXECUTION_COUNTER_MAXIMUM = 0x70000000, // Threshold value when we increase all execution counters to avoid overflow + EXECUTION_COUNTER_ADJUSTMENT = 0x60000000 // The update ( increase ) value for all executioin counters after threshold is reached. + }; + //////////////////////////////////////////////////////////////////////////////////////////////// + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + static const int c_MaxBreakpointsActive = 5; + + size_t m_breakpointsNum; + CLR_DBG_Commands::Debugging_Execution_BreakpointDef* m_breakpoints; + CLR_DBG_Commands::Debugging_Execution_BreakpointDef m_breakpointsActive[ c_MaxBreakpointsActive ]; + size_t m_breakpointsActiveNum; +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + +#if !defined(BUILD_RTM) || defined(_WIN32) + bool m_fPerformGarbageCollection; //Should the EE do a GC every context switch + bool m_fPerformHeapCompaction; //Should the EE do a Compaction following every GC +#endif + +#if defined(NANOCLR_APPDOMAINS) + static const int c_AppDomainId_Invalid = 0; + + CLR_RT_DblLinkedList m_appDomains; + CLR_RT_AppDomain* m_appDomainCurrent; + int m_appDomainIdNext; + + CLR_RT_AppDomain* SetCurrentAppDomain( CLR_RT_AppDomain* appDomain ); + CLR_RT_AppDomain* GetCurrentAppDomain( ); + + HRESULT UnloadAppDomain ( CLR_RT_AppDomain* appDomain, CLR_RT_Thread* th ); + void PrepareThreadsForAppDomainUnload( CLR_RT_AppDomain* appDomain, CLR_RT_DblLinkedList& threads ); + + void TryToUnloadAppDomains_Helper_Threads ( CLR_RT_DblLinkedList& threads ); + void TryToUnloadAppDomains_Helper_Finalizers( CLR_RT_DblLinkedList& finalizers, bool fAlive ); + bool TryToUnloadAppDomains ( ); +#endif //NANOCLR_APPDOMAINS + +#define CLR_EE_DBG_IS( Cond ) ((g_CLR_RT_ExecutionEngine.m_iDebugger_Conditions & CLR_RT_ExecutionEngine::c_fDebugger_##Cond) != 0) +#define CLR_EE_DBG_IS_NOT( Cond ) ((g_CLR_RT_ExecutionEngine.m_iDebugger_Conditions & CLR_RT_ExecutionEngine::c_fDebugger_##Cond) == 0) +#define CLR_EE_DBG_SET( Cond ) g_CLR_RT_ExecutionEngine.m_iDebugger_Conditions |= CLR_RT_ExecutionEngine::c_fDebugger_##Cond +#define CLR_EE_DBG_CLR( Cond ) g_CLR_RT_ExecutionEngine.m_iDebugger_Conditions &= ~CLR_RT_ExecutionEngine::c_fDebugger_##Cond +#define CLR_EE_DBG_SET_MASK( Cond, Mask ) CLR_EE_DBG_CLR( Mask ); CLR_EE_DBG_SET( Cond ); +#define CLR_EE_DBG_RESTORE( Cond, f ) ((f) ? CLR_EE_DBG_SET( Cond ) : CLR_EE_DBG_CLR( Cond ) ) +#define CLR_EE_DBG_IS_MASK( Cond, Mask ) ((g_CLR_RT_ExecutionEngine.m_iDebugger_Conditions & CLR_RT_ExecutionEngine::c_fDebugger_##Mask) == CLR_RT_ExecutionEngine::c_fDebugger_##Cond) + +#define CLR_EE_PRF_IS( Cond ) ((g_CLR_RT_ExecutionEngine.m_iProfiling_Conditions & CLR_RT_ExecutionEngine::c_fProfiling_##Cond) != 0) +#define CLR_EE_PRF_IS_NOT( Cond ) ((g_CLR_RT_ExecutionEngine.m_iProfiling_Conditions & CLR_RT_ExecutionEngine::c_fProfiling_##Cond) == 0) + +#define CLR_EE_IS( Cond ) ((g_CLR_RT_ExecutionEngine.m_iExecution_Conditions & CLR_RT_ExecutionEngine::c_fExecution_##Cond) != 0) +#define CLR_EE_IS_NOT( Cond ) ((g_CLR_RT_ExecutionEngine.m_iExecution_Conditions & CLR_RT_ExecutionEngine::c_fExecution_##Cond) == 0) +#define CLR_EE_SET( Cond ) g_CLR_RT_ExecutionEngine.m_iExecution_Conditions |= CLR_RT_ExecutionEngine::c_fExecution_##Cond +#define CLR_EE_CLR( Cond ) g_CLR_RT_ExecutionEngine.m_iExecution_Conditions &= ~CLR_RT_ExecutionEngine::c_fExecution_##Cond + +#define CLR_EE_REBOOT_IS( Cond ) ((g_CLR_RT_ExecutionEngine.m_iReboot_Options & CLR_DBG_Commands::Monitor_Reboot::c_##Cond) == CLR_DBG_Commands::Monitor_Reboot::c_##Cond) +#define CLR_EE_REBOOT_CLR g_CLR_RT_ExecutionEngine.m_iReboot_Options = CLR_DBG_Commands::Monitor_Reboot::c_ClrOnly + +#define CLR_EE_DBG_EVENT_SEND( cmd, size, payload, flags ) ((g_CLR_DBG_Debugger->m_messaging != NULL) ? g_CLR_DBG_Debugger->m_messaging->SendEvent( cmd, size, (unsigned char*)payload, flags ) : false) + +#define CLR_EE_DBG_EVENT_BROADCAST( cmd, size, payload, flags ) CLR_EE_DBG_EVENT_SEND( cmd, size, payload, flags ) + + //////////////////////////////////////////////////////////////////////////////////////////////// + + // + // Used to subtract system time (GC, compaction, other) from ExecutionConstraint checks. + // + struct ExecutionConstraintCompensation + { + CLR_INT32 m_recursion; + CLR_INT32 m_start; + CLR_INT32 m_cumulative; + + void Suspend() + { + if(m_recursion++ == 0) + { + m_start = HAL_Time_CurrentSysTicks(); + } + } + + void Resume() + { + if(m_recursion) + { + if(--m_recursion == 0) + { + m_cumulative += (HAL_Time_CurrentSysTicks() - m_start); + } + } + } + + CLR_INT64 Adjust( CLR_INT64 time ) const + { + // FIXME: evaluate if the caller code can be adjusted to use SysTicks instead of 100ns ticks + return time + ::HAL_Time_SysTicksToTime( m_cumulative ); + } + }; + + static ExecutionConstraintCompensation s_compensation; + + //--// + + CLR_INT64 m_maximumTimeToActive; + + //--// + + CLR_INT64 m_startTime; + CLR_INT64 m_currentNextActivityTime; + bool m_timerCache; + CLR_UINT64 m_timerCacheNextTimeout; + + CLR_RT_DblLinkedList m_heap; // list of CLR_RT_HeapCluster + CLR_RT_HeapCluster* m_lastHcUsed; + int m_heapState; + + CLR_RT_DblLinkedList m_weakReferences; // OBJECT HEAP - DO RELOCATION - list of CLR_RT_HeapBlock_WeakReference + + CLR_RT_DblLinkedList m_timers; // EVENT HEAP - NO RELOCATION - list of CLR_RT_HeapBlock_Timer + CLR_UINT32 m_raisedEvents; + + CLR_RT_DblLinkedList m_threadsReady; // EVENT HEAP - NO RELOCATION - list of CLR_RT_Thread + CLR_RT_DblLinkedList m_threadsWaiting; // EVENT HEAP - NO RELOCATION - list of CLR_RT_Thread + CLR_RT_DblLinkedList m_threadsZombie; // EVENT HEAP - NO RELOCATION - list of CLR_RT_Thread + int m_lastPid; + CLR_RT_Thread* m_currentThread; + + CLR_RT_DblLinkedList m_finalizersAlive; // EVENT HEAP - NO RELOCATION - list of CLR_RT_HeapBlock_Finalizer + CLR_RT_DblLinkedList m_finalizersPending; // EVENT HEAP - NO RELOCATION - list of CLR_RT_HeapBlock_Finalizer + CLR_RT_Thread* m_finalizerThread; // EVENT HEAP - NO RELOCATION - + CLR_RT_Thread* m_cctorThread; // EVENT HEAP - NO RELOCATION - + +#if !defined(NANOCLR_APPDOMAINS) + CLR_RT_HeapBlock* m_globalLock; // OBJECT HEAP - DO RELOCATION - + CLR_RT_HeapBlock* m_outOfMemoryException; // OBJECT HEAP - DO RELOCATION - +#endif + + CLR_RT_HeapBlock* m_currentUICulture; // OBJECT HEAP - DO RELOCATION - + + //--// + + CLR_RT_Thread* m_interruptThread; // EVENT HEAP - NO RELOCATION + CLR_RT_Thread* m_timerThread; // EVENT HEAP - NO RELOCATION + + //--// + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + CLR_RT_HeapBlock_Array* m_scratchPadArray; // OBJECT HEAP - DO RELOCATION - +#endif + + bool m_fShuttingDown; + + //--// + + static HRESULT CreateInstance(); + + HRESULT ExecutionEngine_Initialize(); + + static HRESULT DeleteInstance(); + + void ExecutionEngine_Cleanup(); + + HRESULT StartHardware(); + + static void Reboot( bool fHard ); + + void JoinAllThreadsAndExecuteFinalizer(); + + void LoadDownloadedAssemblies(); + + static void ExecutionConstraint_Suspend(); + static void ExecutionConstraint_Resume (); + + CLR_UINT32 PerformGarbageCollection(); + void PerformHeapCompaction (); + + void Relocate(); + + HRESULT ScheduleThreads( int maxContextSwitch ); + + CLR_UINT32 WaitForActivity( CLR_UINT32 powerLevel, CLR_UINT32 events, CLR_INT64 timeout_ms ); + CLR_UINT32 WaitForActivity( ); + + HRESULT Execute ( wchar_t* entryPointArgs, int maxContextSwitch ); + + HRESULT WaitForDebugger(); + + static CLR_RT_HeapBlock* AccessStaticField( const CLR_RT_FieldDef_Index& fd ); + + void ProcessTimeEvent( CLR_UINT32 event ); + + static void InvalidateTimerCache(); + + static CLR_INT64 GetUptime(); + + CLR_RT_HeapBlock* ExtractHeapBlocksForArray( CLR_RT_TypeDef_Instance& inst, CLR_UINT32 length, const CLR_RT_ReflectionDef_Index& reflex ); + CLR_RT_HeapBlock* ExtractHeapBlocksForClassOrValueTypes( CLR_UINT32 dataType, CLR_UINT32 flags, const CLR_RT_TypeDef_Index& cls, CLR_UINT32 length ); + CLR_RT_HeapBlock* ExtractHeapBytesForObjects ( CLR_UINT32 dataType, CLR_UINT32 flags, CLR_UINT32 length ); + CLR_RT_HeapBlock* ExtractHeapBlocksForObjects ( CLR_UINT32 dataType, CLR_UINT32 flags, CLR_UINT32 length ); + CLR_RT_HeapBlock_Node* ExtractHeapBlocksForEvents ( CLR_UINT32 dataType, CLR_UINT32 flags, CLR_UINT32 length ); + + HRESULT NewThread ( CLR_RT_Thread*& th, CLR_RT_HeapBlock_Delegate* pDelegate, int priority, CLR_INT32 id, CLR_UINT32 flags = 0 ); + void PutInProperList( CLR_RT_Thread* th ); + CLR_INT32 GetNextThreadId( ); + + HRESULT InitializeReference( CLR_RT_HeapBlock& ref, CLR_RT_SignatureParser& parser ); + HRESULT InitializeReference( CLR_RT_HeapBlock& ref, const CLR_RECORD_FIELDDEF* target, CLR_RT_Assembly* assm ); + + HRESULT InitializeLocals( CLR_RT_HeapBlock* locals, CLR_RT_Assembly* assm, const CLR_RECORD_METHODDEF* md ); + + HRESULT NewObjectFromIndex( CLR_RT_HeapBlock& reference, const CLR_RT_TypeDef_Index& cls ); + HRESULT NewObject ( CLR_RT_HeapBlock& reference, const CLR_RT_TypeDef_Instance& inst ); + HRESULT NewObject ( CLR_RT_HeapBlock& reference, CLR_UINT32 token, CLR_RT_Assembly* assm ); + + HRESULT CloneObject ( CLR_RT_HeapBlock& reference , const CLR_RT_HeapBlock& source ); + HRESULT CopyValueType( CLR_RT_HeapBlock* destination, const CLR_RT_HeapBlock* source ); + + HRESULT NewArrayList ( CLR_RT_HeapBlock& ref, int size, CLR_RT_HeapBlock_Array*& array ); + + + HRESULT FindFieldDef( CLR_RT_TypeDef_Instance& inst , const char* szText , CLR_RT_FieldDef_Index& res ); + HRESULT FindFieldDef( CLR_RT_HeapBlock& reference, const char* szText , CLR_RT_FieldDef_Index& res ); + HRESULT FindField ( CLR_RT_HeapBlock& reference, const char* szText, CLR_RT_HeapBlock*& field ); + HRESULT SetField ( CLR_RT_HeapBlock& reference, const char* szText, CLR_RT_HeapBlock& value ); + HRESULT GetField ( CLR_RT_HeapBlock& reference, const char* szText, CLR_RT_HeapBlock& value ); + + + HRESULT LockObject ( CLR_RT_HeapBlock& reference, CLR_RT_SubThread* sth, const CLR_INT64& timeExpire, bool fForce ); + HRESULT UnlockObject ( CLR_RT_HeapBlock& reference, CLR_RT_SubThread* sth ); + void DeleteLockRequests( CLR_RT_Thread* thTarget , CLR_RT_SubThread* sthTarget ); + + HRESULT Sleep( CLR_RT_Thread* caller, const CLR_INT64& timeExpire ); + + HRESULT WaitEvents ( CLR_RT_Thread* caller, const CLR_INT64& timeExpire, CLR_UINT32 events, bool& fSuccess ); + void SignalEvents( CLR_RT_DblLinkedList& threads, CLR_UINT32 events ); + void SignalEvents( CLR_UINT32 events ); + + + HRESULT InitTimeout( CLR_INT64& timeExpire, const CLR_INT64& timeout ); + HRESULT InitTimeout( CLR_INT64& timeExpire, CLR_INT32 timeout ); + + static bool IsInstanceOf( CLR_RT_TypeDescriptor& desc, CLR_RT_TypeDescriptor& descTarget ); + static bool IsInstanceOf( const CLR_RT_TypeDef_Index& cls , const CLR_RT_TypeDef_Index& clsTarget ); + static bool IsInstanceOf( CLR_RT_HeapBlock& obj , const CLR_RT_TypeDef_Index& clsTarget ); + static bool IsInstanceOf( CLR_RT_HeapBlock& obj , CLR_RT_Assembly* assm, CLR_UINT32 token ); + + static HRESULT CastToType( CLR_RT_HeapBlock& ref, CLR_UINT32 tk, CLR_RT_Assembly* assm, bool fUpdate ); + + void DebuggerLoop(); + +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + void SetDebuggingInfoBreakpoints( bool fSet ); + void InstallBreakpoints ( CLR_DBG_Commands::Debugging_Execution_BreakpointDef* data, size_t num ); + void StopOnBreakpoint ( CLR_DBG_Commands::Debugging_Execution_BreakpointDef& def , CLR_RT_Thread* th ); + void StopOnBreakpoint ( CLR_DBG_Commands::Debugging_Execution_BreakpointDef& def , CLR_RT_StackFrame* stack, CLR_PMETADATA ip ); + void Breakpoint_System_Event ( CLR_DBG_Commands::Debugging_Execution_BreakpointDef& def , CLR_UINT16 event, CLR_RT_Thread* th, CLR_RT_StackFrame* stack, CLR_PMETADATA ip ); + bool DequeueActiveBreakpoint ( CLR_DBG_Commands::Debugging_Execution_BreakpointDef& def ); + + void Breakpoint_Assemblies_Loaded(); + + void Breakpoint_Threads_Prepare ( CLR_RT_DblLinkedList& threads ); + void Breakpoint_Thread_Terminated( CLR_RT_Thread* th ); + void Breakpoint_Thread_Created ( CLR_RT_Thread* th ); + + void Breakpoint_StackFrame_Break ( CLR_RT_StackFrame* stack ); + void Breakpoint_StackFrame_Push ( CLR_RT_StackFrame* stack, CLR_UINT32 reason ); + void Breakpoint_StackFrame_Pop ( CLR_RT_StackFrame* stack, bool stepEH ); + void Breakpoint_StackFrame_Step ( CLR_RT_StackFrame* stack, CLR_PMETADATA ip ); + void Breakpoint_StackFrame_Hard ( CLR_RT_StackFrame* stack, CLR_PMETADATA ip ); + + void Breakpoint_Exception ( CLR_RT_StackFrame* stack, CLR_UINT32 reason, CLR_PMETADATA ip ); + void Breakpoint_Exception_Intercepted( CLR_RT_StackFrame* stack ); + void Breakpoint_Exception_Uncaught ( CLR_RT_Thread* th ); +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + //--// + + bool IsTimeExpired( const CLR_INT64& timeExpire, CLR_INT64& timeoutMin ); + + bool IsThereEnoughIdleTime( CLR_UINT32 expectedMsec ); + + void SpawnTimer(); + void SpawnFinalizer(); + void SpawnStaticConstructor( CLR_RT_Thread *&pCctorThread ); +#if defined(NANOCLR_APPDOMAINS) + bool SpawnStaticConstructorHelper( CLR_RT_AppDomain* appDomain, CLR_RT_AppDomainAssembly* appDomainAssembly, const CLR_RT_MethodDef_Index& idx ); +#else + bool SpawnStaticConstructorHelper( CLR_RT_Assembly* assembly, const CLR_RT_MethodDef_Index& idx ); +#endif + static void FinalizerTerminationCallback( void* arg ); + static void StaticConstructorTerminationCallback( void* arg ); + bool EnsureSystemThread( CLR_RT_Thread*& thread, int priority ); + + CLR_INT64 ProcessTimer(); + + //--// + + PROHIBIT_COPY_CONSTRUCTORS(CLR_RT_ExecutionEngine); + + //--// + +private: + + HRESULT AllocateHeaps(); + + void DeleteLockRequests( CLR_RT_Thread* thTarget, CLR_RT_SubThread* sthTarget, CLR_RT_DblLinkedList& threads ); + + CLR_RT_HeapBlock* ExtractHeapBlocks ( CLR_RT_DblLinkedList& heap, CLR_UINT32 dataType, CLR_UINT32 flags, CLR_UINT32 length ); + + CLR_RT_HeapBlock_Lock* FindLockObject( CLR_RT_DblLinkedList& threads, CLR_RT_HeapBlock& object ); + CLR_RT_HeapBlock_Lock* FindLockObject( CLR_RT_HeapBlock& object ); + + void CheckTimers ( CLR_INT64& timeoutMin ); + void CheckThreads ( CLR_INT64& timeoutMin, CLR_RT_DblLinkedList& threads ); + + void ProcessHardware(); + + + void ReleaseAllThreads( CLR_RT_DblLinkedList& threads ); + void AbortAllThreads ( CLR_RT_DblLinkedList& threads ); + + void InsertThreadRoundRobin( CLR_RT_DblLinkedList& threads, CLR_RT_Thread* th ); + + CLR_UINT32 WaitSystemEvents( CLR_UINT32 powerLevel, CLR_UINT32 events, CLR_INT64 timeExpire ); + +#if defined(_WIN32) + HRESULT CreateEntryPointArgs( CLR_RT_HeapBlock& args, wchar_t* szCommandLineArgs ); +#endif + + // The lowest value for execution counter in threads. + int m_GlobalExecutionCounter; + + // Increase the value of m_executionCounter for all threads by iUpdateValue. + // This ensures that counter does not underflow. + void AdjustExecutionCounter( CLR_RT_DblLinkedList &threadList, int iUpdateValue ); +public : + + // This function updates execution counter in pThread and makes it last to execute. + // It is used to Thread.Sleep(0) imlementation. The thread is still ready, but is last to execute. + void UpdateToLowestExecutionCounter( CLR_RT_Thread *pThread ) const; + + void RetrieveCurrentMethod( CLR_UINT32& assmIdx, CLR_UINT32& methodIdx ); +}; + +extern CLR_RT_ExecutionEngine g_CLR_RT_ExecutionEngine; +extern CLR_UINT32 g_buildCRC; + +//--// + +// +// CT_ASSERT macro generates a compiler error in case the size of any structure changes. +// +CT_ASSERT( sizeof(CLR_RT_HeapBlock) == 12 ) +CT_ASSERT( sizeof(CLR_RT_HeapBlock_Raw) == sizeof(CLR_RT_HeapBlock) ) + +#if defined(NANOCLR_TRACE_MEMORY_STATS) +#define NANOCLR_TRACE_MEMORY_STATS_EXTRA_SIZE 4 +#else +#define NANOCLR_TRACE_MEMORY_STATS_EXTRA_SIZE 0 +#endif + +#if defined(__GNUC__) // Gcc compiler uses 8 bytes for a function pointer + CT_ASSERT( sizeof(CLR_RT_DataTypeLookup) == 20 + NANOCLR_TRACE_MEMORY_STATS_EXTRA_SIZE ) + +#elif defined(PLATFORM_WINDOWS_EMULATOR) || defined(NANOCLR_TRACE_MEMORY_STATS) + CT_ASSERT( sizeof(CLR_RT_DataTypeLookup) == 16 + 4 ) + +#else + +! ERROR + +#endif + +//--// + +#if defined(_MSC_VER) +#pragma pack(pop, NANOCLR_RUNTIME_H) +#endif + +#endif // _NANOCLR_RUNTIME_H_ + diff --git a/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Runtime__HeapBlock.h b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Runtime__HeapBlock.h new file mode 100644 index 00000000..374c811e --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Runtime__HeapBlock.h @@ -0,0 +1,2443 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _NANOCLR_RUNTIME__HEAPBLOCK_H_ +#define _NANOCLR_RUNTIME__HEAPBLOCK_H_ + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#define CLR_RT_HEAPBLOCK_RAW_ID( dataType, flags, size ) ( (dataType & 0x000000FF) | ((flags & 0x000000FF) << 8) | ((size & 0x0000FFFF) << 16)) +#define CLR_RT_HEAPBLOCK_ASSIGN_INTEGER32_SIGNED( dataType, num ) { m_id.raw = CLR_RT_HEAPBLOCK_RAW_ID( dataType, 0, 1 ); m_data.numeric.s4 = (CLR_INT32)num; } +#define CLR_RT_HEAPBLOCK_ASSIGN_INTEGER64_SIGNED( dataType, num ) { m_id.raw = CLR_RT_HEAPBLOCK_RAW_ID( dataType, 0, 1 ); m_data.numeric.s8 = num; } + +#define CLR_RT_HEAPBLOCK_ASSIGN_INTEGER32_UNSIGNED(dataType,num) { m_id.raw = CLR_RT_HEAPBLOCK_RAW_ID( dataType, 0, 1 ); m_data.numeric.u4 = (CLR_UINT32)num; } +#define CLR_RT_HEAPBLOCK_ASSIGN_INTEGER64_UNSIGNED(dataType,num) { m_id.raw = CLR_RT_HEAPBLOCK_RAW_ID( dataType, 0, 1 ); m_data.numeric.u8 = num; } + +#define CLR_RT_HEAPBLOCK_ASSIGN_FLOAT32(dataType,num) { m_id.raw = CLR_RT_HEAPBLOCK_RAW_ID( dataType, 0, 1 ); m_data.numeric.r4 = num; } +#define CLR_RT_HEAPBLOCK_ASSIGN_FLOAT64(dataType,num) { m_id.raw = CLR_RT_HEAPBLOCK_RAW_ID( dataType, 0, 1 ); m_data.numeric.r8 = num; } + +//////////////////////////////////////////////////////////// + +#define CLR_RT_HEAPBLOCK_RELOCATE(ptr) \ +{ \ + CLR_DataType dt = ptr->DataType(); \ + \ + if(dt > DATATYPE_LAST_NONPOINTER && dt < DATATYPE_FIRST_INVALID) \ + { \ + CLR_RT_HeapBlockRelocate rel = c_CLR_RT_DataTypeLookup[ dt ].m_relocate; \ + if(rel) \ + { \ + (ptr->*rel)(); \ + } \ + } \ +} + + +//////////////////////////////////////////////////////////// + +// +// This is used in memory move operations. +// +struct CLR_RT_HeapBlock_Raw +{ + CLR_UINT32 data[ 3 ]; +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +struct CLR_RT_HeapBlock +{ + friend struct CLR_RT_HeapBlock_Node; + friend struct CLR_RT_DblLinkedList; + + friend struct MethodCompiler; + //--// + +#if defined(NANOCLR_EMULATED_FLOATINGPOINT) +/*********************************************************/ +// Keep in Sync with nanoHAL.h +//#define HAL_FLOAT_SHIFT 10 +//#define HAL_FLOAT_PRECISION 1000 +//#define HAL_DOUBLE_SHIFT 16 +//#define HAL_DOUBLE_PRECISION 10000 +/*********************************************************/ + + static const int HB_FloatShift = 10; + static const int HB_DoubleShift = 16; + + static const CLR_INT32 HB_FloatUnit = (1 << HB_FloatShift ); + static const CLR_INT64 HB_DoubleUnit = (ULONGLONGCONSTANT(1) << HB_DoubleShift); + + static const CLR_INT32 HB_FloatMask = ((1 << HB_FloatShift) - 1); + static const CLR_INT64 HB_DoubleMask = ((ULONGLONGCONSTANT(1) << HB_DoubleShift) - 1); + +#endif + + + + static const CLR_UINT32 HB_Alive = 0x01; + static const CLR_UINT32 HB_KeepAlive = 0x02; + static const CLR_UINT32 HB_Event = 0x04; + static const CLR_UINT32 HB_Pinned = 0x08; + static const CLR_UINT32 HB_Boxed = 0x10; + static const CLR_UINT32 HB_Unused20 = 0x20; + //If more bits are needed, HB_Signaled and HB_SignalAutoReset can be freed for use with a little work. + //It is not necessary that any heapblock can be waited upon. Currently, only Threads (Thread.Join), + //ManualResetEvent, and AutoResetEvent are waitable objects. + static const CLR_UINT32 HB_Signaled = 0x40; + static const CLR_UINT32 HB_SignalAutoReset = 0x80; + + static const CLR_UINT32 HB_Unmovable = HB_Pinned | HB_Event; + + // + // These are special flags used to control allocation. + // + static const CLR_UINT32 HB_InitializeToZero = 0x00100; + static const CLR_UINT32 HB_NoGcOnFailure = 0x00200; + static const CLR_UINT32 HB_SpecialGCAllocation = 0x00400; + static const CLR_UINT32 HB_CompactOnFailure = 0x00800; + + static const CLR_UINT32 HB_NoGcOnFailedAllocation = HB_SpecialGCAllocation | HB_NoGcOnFailure; + static const CLR_UINT32 HB_MaxSize = 0x0000FFFF; + + static const CLR_UINT32 HB_Object_Fields_Offset = 1; + + //--// + +private: + + union CLR_RT_HeapBlock_Id + { + struct Type + { + CLR_UINT8 dataType; // CLR_DataType + CLR_UINT8 flags; // HB_* + CLR_UINT16 size; + } type; + + CLR_UINT32 raw; + } m_id; + + union CLR_RT_HeapBlock_AtomicData + { + struct NodeLink + { + CLR_RT_HeapBlock_Node* nextBlock; + CLR_RT_HeapBlock_Node* prevBlock; + } nodeLink; + + union Numeric + { + CLR_UINT8 u1; + CLR_UINT16 u2; + CLR_UINT32 u4; + + struct U8 + { + CLR_UINT32 LL; + CLR_UINT32 HH; + + operator CLR_UINT64() const + { + return ((CLR_UINT64)HH << 32 | (CLR_UINT64)LL ); + } + + U8& operator=( const CLR_UINT64 num ) + { + LL = (CLR_UINT32)((ULONGLONGCONSTANT(0x00000000FFFFFFFF) & num) ); + HH = (CLR_UINT32)((ULONGLONGCONSTANT(0xFFFFFFFF00000000) & num) >> 32); + return *this; + } + U8& operator+=( const U8& num ) + { + CLR_UINT64 value = (CLR_UINT64)*this; // uses conversion + value += (CLR_UINT64)num; // uses conversion and then built-in type __int64 + *this = value; // uses assignment operator (operator=) + return *this; + } + + U8& operator-=( const U8& num ) + { + CLR_UINT64 value = (CLR_UINT64)*this; // uses conversion + value -= (CLR_UINT64)num; // uses conversion and then built-in type __int64 + *this = value; // uses assignment operator (operator=) + return *this; + } + + + U8 operator*( const U8& num) + { + CLR_UINT64 value = (CLR_UINT64)*this; + U8 ret_value; + value *= (CLR_UINT64)num; // uses conversion and then built-in type __int64 + ret_value = value; + return ret_value; + } + + U8 operator/( const U8& num ) + { + CLR_UINT64 value = (CLR_UINT64)*this; + U8 ret_value; + value /= (CLR_UINT64)num; // uses conversion and then built-in type __int64 + ret_value = value; + return ret_value; + } + + U8 operator~( ) + { + U8 ret_value; + ret_value.LL = ~LL; + ret_value.HH = ~HH; + return ret_value; + } + + + U8& operator%=( const U8& num ) + { + CLR_UINT64 value = (CLR_UINT64)*this; // uses conversion + value %= (CLR_UINT64)num; // uses conversion and then built-in type __int64 + *this = value; // uses assignment operator (operator=) + return *this; + } + + U8& operator&=( const U8& num ) + { + LL &= num.LL; + HH &= num.HH; + return *this; + } + + U8& operator|=( const U8& num ) + { + LL |= num.LL; + HH |= num.HH; + return *this; + } + + U8& operator^=( const U8& num ) + { + LL ^= num.LL; + HH ^= num.HH; + return *this; + } + + U8& operator>>=( const CLR_UINT32 num ) + { + + CLR_UINT64 value = (CLR_UINT64)*this; // uses conversion + value >>= num; // uses conversion and then built-in type __int64 + *this = value; // uses assignment operator (operator=) + return *this; + } + + U8& operator<<=( const CLR_UINT32 num ) + { + CLR_UINT64 value = (CLR_UINT64)*this; // uses conversion + value <<= num; // uses conversion and then built-in type __int64 + *this = value; // uses assignment operator (operator=) + return *this; + } + + bool operator<( const U8& num ) + { + CLR_UINT64 value = (CLR_UINT64)*this; // uses conversion + return ( value < (CLR_UINT64)num ); + } + + bool operator>( const U8& num ) + { + CLR_UINT64 value = (CLR_UINT64)*this; // uses conversion + return ( value > (CLR_UINT64)num ); + } + + bool operator==( const U8& num ) + { + CLR_UINT64 value = (CLR_UINT64)*this; // uses conversion + return ( value ==(CLR_UINT64)num ); + } + + bool operator==( const CLR_UINT64 num ) + { + CLR_UINT64 value = (CLR_UINT64)*this; // uses conversion + return ( value == num ); + } + + } u8; + // + CLR_INT8 s1; + CLR_INT16 s2; + CLR_INT32 s4; + + struct S8 + { + CLR_UINT32 LL; + CLR_UINT32 HH; + + operator CLR_INT64() const + { + return (((CLR_UINT64)HH) << 32 | (CLR_UINT64)LL); + } + + S8& operator=( const CLR_INT64 num ) + { + LL = (CLR_UINT32) (( ULONGLONGCONSTANT(0x00000000FFFFFFFF) & num) ); + HH = (CLR_UINT32) (( ULONGLONGCONSTANT(0xFFFFFFFF00000000) & num) >> 32 ); + return *this; + } + + S8& operator+=( const S8& num ) + { + CLR_INT64 value = (CLR_INT64)*this; // uses conversion + value += (CLR_INT64)num; // uses conversion and then built-in type __int64 + *this = value; // uses assignment operator (operator=) + return *this; + } + + S8& operator-=( const S8& num ) + { + CLR_INT64 value = (CLR_INT64)*this; // uses conversion + value -= (CLR_INT64)num; // uses conversion and then built-in type __int64 + *this = value; // uses assignment operator (operator=) + return *this; + } + + S8 operator*( const S8& num) + { + CLR_INT64 value = (CLR_INT64)*this; + S8 ret_value; + value *= (CLR_INT64)num; // uses conversion and then built-in type __int64 + ret_value = value; + return ret_value; + } + + S8 operator/( const S8& num ) + { + CLR_INT64 value = (CLR_INT64)*this; + S8 ret_value; + value /= (CLR_INT64)num; // uses conversion and then built-in type __int64 + ret_value = value; + return ret_value; + } + + S8 operator~() + { + S8 ret_value; + ret_value.LL = ~LL; + ret_value.HH = ~HH; + return ret_value; + } + + + + S8& operator%=( const S8& num ) + { + CLR_INT64 value = (CLR_INT64)*this; // uses conversion + value %= (CLR_INT64)num; // uses conversion and then built-in type __int64 + *this = value; // uses assignment operator (operator=) + return *this; + } + + S8& operator&=( const S8& num ) + { + LL &= num.LL; + HH &= num.HH; + return *this; + } + + S8& operator|=( const S8& num ) + { + LL |= num.LL; + HH |= num.HH; + return *this; + } + + S8& operator^=( const S8& num ) + { + LL ^= num.LL; + HH ^= num.HH; + return *this; + } + + S8& operator>>=( const CLR_UINT32 num ) + { + CLR_INT64 value = (CLR_INT64)*this; // uses conversion + value >>= num; // uses conversion and then built-in type __int64 + *this = value; // uses assignment operator (operator=) + return *this; + } + + S8& operator<<=( const CLR_UINT32 num ) + { + CLR_INT64 value = (CLR_INT64)*this; // uses conversion + value <<= num; // uses conversion and then built-in type __int64 + *this = value; // uses assignment operator (operator=) + return *this; + } + + bool operator<( const S8& num ) + { + CLR_INT64 value = (CLR_INT64)*this; // uses conversion + return ( value < (CLR_INT64)num ); + } + + bool operator>( const S8& num ) + { + CLR_INT64 value = (CLR_INT64)*this; // uses conversion + return ( value > (CLR_INT64)num ); + } + + bool operator==( const S8& num ) + { + CLR_INT64 value = (CLR_INT64)*this; // uses conversion + return ( value == (CLR_INT64)num ); + } + + + bool operator==( const CLR_INT64 num ) + { + CLR_INT64 value = (CLR_INT64)*this; // uses conversion + return ( value == num ); + } + + } s8; + // + + #if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + + float r4; + + struct R8 + { + CLR_UINT32 LL; + CLR_UINT32 HH; + + operator double() const + { + double ret_val; + + #if defined(__GNUC__) + /// + /// UNDONE: FIXME: This code fixes an optimization problem with the gcc compiler. + /// When the optimization level is greater than zero, the gcc compiler + /// code will not work with the unsigned int* conversion, it requires you + /// to copy byte by byte. + /// + CLR_UINT8* tmp = (CLR_UINT8*)&ret_val; + CLR_UINT8* src = (CLR_UINT8*)&LL; + uint32_t i; + + for(i=0; i( const R8& num ) + { + double value = (double)*this; // uses conversion + return ( value > (double)num ); + } + + bool operator==( const R8& num ) + { + double value = (double)*this; // uses conversion + return ( value == (double)num ); + } + + bool operator==( const double num ) + { + double value = (double)*this; // uses conversion + return ( value == num ); + } + + } r8; + + #else + /// not using floating point lib, emulated one + + struct R4 { + + CLR_INT32 LL; + + operator CLR_INT32 () const + { + return LL; + } + + R4& operator=( const CLR_INT32 num ) + { + LL = num; + return *this; + } + R4& operator+=( const R4& num ) + { + LL += num.LL; + return *this; + } + + R4& operator-=( const R4& num ) + { + LL -= num.LL; + return *this; + } + + + R4& operator%=( const R4& num ) + { + LL %= num.LL; + return *this; + } + + + R4 operator*( const R4& num ) + { + R4 ret_value; + ret_value.LL = (CLR_INT32)(((CLR_INT64)LL * (CLR_INT64)num.LL) >> HB_FloatShift ); + return ret_value; + } + + R4 operator/( const R4& num ) + { + R4 ret_value; + ret_value.LL = (CLR_INT32)((((CLR_INT64)LL) << HB_FloatShift) / (CLR_INT64)num.LL); + return ret_value; + } + + } r4; + + struct R8 + { + CLR_UINT32 LL; + CLR_UINT32 HH; + + operator CLR_INT64() const + { + return ((CLR_INT64)HH << 32 | (CLR_INT64)LL ); + } + + R8& operator=( const CLR_INT64 num ) + { + LL = (CLR_UINT32) (( ULONGLONGCONSTANT(0x00000000FFFFFFFF) & num) ); + HH = (CLR_UINT32) (( ULONGLONGCONSTANT(0xFFFFFFFF00000000) & num) >> 32 ); + return *this; + } + + R8& operator+=( const R8& num ) + { + CLR_INT64 value = (CLR_INT64)*this; // uses conversion + value += (CLR_INT64)num; + *this = value; + return *this; + } + + R8& operator-=( const R8& num ) + { + CLR_INT64 value = (CLR_INT64)*this; // uses conversion + value -= (CLR_INT64)num; + *this = value; + return *this; + } + + R8 operator*( const R8& num) + { + CLR_UINT64 op1 = (CLR_INT64) *this; + CLR_UINT64 op2 = (CLR_INT64) num; + CLR_UINT64 res = 0; + R8 ret_value; + + bool fNegate = false; + + if((CLR_INT64)op1 < (CLR_INT64)res) + { + op1 = -(CLR_INT64)op1; + fNegate = !fNegate; + } + + if((CLR_INT64)op2 < (CLR_INT64)res) + { + op2 = -(CLR_INT64)op2; + fNegate = !fNegate; + } + + CLR_UINT64 v; + + #define ACCUMULATE(res,op,part) v = op1 * (CLR_UINT16)(op2 >> (16 * part)); res += (16 * part - HB_DoubleShift >= 0) ? (v << (16 * part - HB_DoubleShift)) : (v >> (HB_DoubleShift - 16 * part)) + + ACCUMULATE(res,+=,0); + ACCUMULATE(res,+=,1); + ACCUMULATE(res,+=,2); + ACCUMULATE(res,+=,3); + + #undef ACCUMULATE + + ret_value = (CLR_INT64)res; + + if(fNegate && (CLR_INT64)ret_value != 0) + { + ret_value = -(CLR_INT64)ret_value; + } + + return ret_value; + } + + R8 operator/( const R8& num ) + { + CLR_INT64 value = (CLR_INT64)*this; + R8 ret_value; + + value = (value / num) << HB_DoubleShift; + + ret_value = value; + + return ret_value; + } + + bool operator==( const R8& num ) + { + CLR_INT64 value = (CLR_INT64)*this; // uses conversion + return ( value == (CLR_INT64)num ); + } + + + bool operator==( const CLR_INT64 num ) + { + CLR_INT64 value = (CLR_INT64)*this; // uses conversion + return ( value == num ); + } + R8& operator%=( const R8& num ) + { + CLR_INT64 value = (CLR_INT64)*this; // uses conversion + + value = (CLR_INT64)((value % (CLR_INT64)num)) ; // uses conversion and then built-in type double + *this = value; // uses assignment operator (operator=) + + return *this; + } + + } r8; + + #endif + } numeric; + + // The macro CT_ASSERT is used to validate that members of Numeric union start at zero offset in union. + // This presumption is used in CRL_RT_Interop code. + // This macro does not add any code or data member, it is pure compiler time validation. + // This is not a valid check for Big Endian. + // Addr: 0011223344556677 Number: 0xAABBCCDD + // MemBE: AABBCCDD + // MemLE: DDCCBBAA + // So for LE DD,Addr 00 is the low byte. + // For BE it is certainly not true, hence this check will not work. Will Interop? FIXME GJS - verify interop + CT_ASSERT_UNIQUE_NAME( offsetof( Numeric, s1 ) == 0, s1 ) + CT_ASSERT_UNIQUE_NAME( offsetof( Numeric, s2 ) == 0, s2 ) + CT_ASSERT_UNIQUE_NAME( offsetof( Numeric, s4 ) == 0, s4 ) + CT_ASSERT_UNIQUE_NAME( offsetof( Numeric, u1 ) == 0, u1 ) + CT_ASSERT_UNIQUE_NAME( offsetof( Numeric, u2 ) == 0, u2 ) + CT_ASSERT_UNIQUE_NAME( offsetof( Numeric, u4 ) == 0, u4 ) + CT_ASSERT_UNIQUE_NAME( offsetof( Numeric, r4 ) == 0, r4 ) + CT_ASSERT_UNIQUE_NAME( offsetof( Numeric, s8 ) == 0, s8 ) + CT_ASSERT_UNIQUE_NAME( offsetof( Numeric, u8 ) == 0, u8 ) + CT_ASSERT_UNIQUE_NAME( offsetof( Numeric, r8 ) == 0, r8 ) + + struct String + { + const char* m_text; +#if !defined(NANOCLR_NO_ASSEMBLY_STRINGS) + CLR_RT_Assembly* m_assm; +#endif + } string; + + //--// + + struct ObjectReference + { + CLR_RT_HeapBlock* ptr; + } objectReference; + + struct ArrayReference + { + CLR_RT_HeapBlock_Array* array; + CLR_UINT32 index; + } arrayReference; + + struct ObjectHeader + { + CLR_RT_TypeDef_Index cls; + CLR_RT_HeapBlock_Lock* lock; + } objectHeader; + +#if defined(NANOCLR_APPDOMAINS) + struct TransparentProxy + { + CLR_RT_HeapBlock* ptr; //points to a DATATYPE_CLASS derived from MBRO + CLR_RT_AppDomain* appDomain; //EVENT HEAP -- NO RELOCATION + } transparentProxy; +#endif + + //--// + + CLR_RT_ReflectionDef_Index reflection; + + //--// + + struct BinaryBlob + { + CLR_RT_MarkingHandler m_mark; + CLR_RT_RelocationHandler m_relocate; + } binaryBlob; + + } m_data; + +public: + + //--// + + void InitializeToZero(); + + //--// + + CLR_DataType DataType () const { return (CLR_DataType)m_id.type.dataType; } + CLR_UINT8 DataFlags() const { return m_id.type.flags ; } + CLR_UINT16 DataSize () const { return m_id.type.size ; } + + // Returns number of bytes actually used in CLR_RT_HeapBlock_AtomicData + CLR_UINT32 GetAtomicDataUsedBytes() const; + + void SetDataId ( CLR_UINT32 id ) { m_id.raw = id; } + void ChangeDataType ( CLR_UINT32 dataType ) { m_id.type.dataType = dataType; } + void ChangeDataFlags( CLR_UINT32 flags ) { m_id.type.flags = flags; } + + void ClearData() + { + m_data.nodeLink.nextBlock = NULL; + m_data.nodeLink.prevBlock = NULL; + } + + void SetFlags ( CLR_UINT8 flags ) { m_id.type.flags |= flags ; } + void ResetFlags( CLR_UINT8 flags ) { m_id.type.flags &= ~flags ; } + bool IsFlagSet ( CLR_UINT8 flags ) const { return (m_id.type.flags & flags) != 0; } + + //--// + +#if defined(NANOCLR_FILL_MEMORY_WITH_DIRTY_PATTERN) + + void Debug_ClearBlock ( int data ); + void Debug_CheckPointer( ) const; + static void Debug_CheckPointer( void* ptr ); + +#else + + void Debug_ClearBlock ( int data ) {} + void Debug_CheckPointer( ) const {} + static void Debug_CheckPointer( void* ptr ) {} + +#endif + + //--// + + bool IsAlive () const { return IsFlagSet ( HB_Alive ); } + bool IsEvent () const { return IsFlagSet ( HB_Event ); } + bool IsForcedAlive () const { return IsFlagSet ( HB_KeepAlive ); } + + bool IsPinned () const { return IsFlagSet ( HB_Pinned ); } + void Pin () { SetFlags ( HB_Pinned ); } + void Unpin () { ResetFlags( HB_Pinned ); } + + void MarkDead () { ResetFlags( HB_Alive ); } + void MarkAlive () { SetFlags ( HB_Alive ); } + + void MarkForcedAlive () { SetFlags ( HB_KeepAlive ); } + void UnmarkForcedAlive() { ResetFlags( HB_KeepAlive ); } + + bool IsBoxed () const { return IsFlagSet ( HB_Boxed ); } + void Box () { SetFlags ( HB_Boxed ); } + void Unbox () { ResetFlags( HB_Boxed ); } + + //--// + + void SetBoolean( bool val ) { CLR_RT_HEAPBLOCK_ASSIGN_INTEGER32_SIGNED( DATATYPE_BOOLEAN, val ? 1 : 0 ); } + void SetInteger( const CLR_INT32 num, CLR_UINT8 dataType ) { CLR_RT_HEAPBLOCK_ASSIGN_INTEGER32_SIGNED( dataType , num ); } + + void SetInteger( const CLR_INT8 num ) { CLR_RT_HEAPBLOCK_ASSIGN_INTEGER32_SIGNED (DATATYPE_I1, num); } + void SetInteger( const CLR_INT16 num ) { CLR_RT_HEAPBLOCK_ASSIGN_INTEGER32_SIGNED (DATATYPE_I2, num); } + void SetInteger( const CLR_INT32 num ) { CLR_RT_HEAPBLOCK_ASSIGN_INTEGER32_SIGNED (DATATYPE_I4, num); } + void SetInteger( const CLR_INT64& num ) { CLR_RT_HEAPBLOCK_ASSIGN_INTEGER64_SIGNED (DATATYPE_I8, num); } + void SetInteger( const CLR_UINT8 num ) { CLR_RT_HEAPBLOCK_ASSIGN_INTEGER32_UNSIGNED(DATATYPE_U1, num); } + void SetInteger( const CLR_UINT16 num ) { CLR_RT_HEAPBLOCK_ASSIGN_INTEGER32_UNSIGNED(DATATYPE_U2, num); } + void SetInteger( const CLR_UINT32 num ) { CLR_RT_HEAPBLOCK_ASSIGN_INTEGER32_UNSIGNED(DATATYPE_U4, num); } + void SetInteger( const CLR_UINT64& num ) { CLR_RT_HEAPBLOCK_ASSIGN_INTEGER64_UNSIGNED(DATATYPE_U8, num); } + +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + void SetFloat ( const float num ) { CLR_RT_HEAPBLOCK_ASSIGN_FLOAT32 (DATATYPE_R4, num); } + void SetDouble ( const double num ) { CLR_RT_HEAPBLOCK_ASSIGN_FLOAT64 (DATATYPE_R8, num); } + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstrict-aliasing" +#endif + + void SetFloatFromBits ( const CLR_UINT32 num ) { SetFloat ( *(const float *)&num ); } + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + void SetDoubleFromBits( const CLR_UINT64& num ) { SetDouble( *(const double*)&num ); } +#else + void SetFloat ( const CLR_INT32 num ) { CLR_RT_HEAPBLOCK_ASSIGN_FLOAT32 (DATATYPE_R4, num); } + void SetDouble ( const CLR_INT64& num ) { CLR_RT_HEAPBLOCK_ASSIGN_FLOAT64 (DATATYPE_R8, num); } + HRESULT SetFloatIEEE754 ( const CLR_UINT32 num ); + HRESULT SetDoubleIEEE754( const CLR_UINT64& num ); +#endif + + + void SetObjectReference( const CLR_RT_HeapBlock* ptr ) + { + m_id.raw = CLR_RT_HEAPBLOCK_RAW_ID(DATATYPE_OBJECT, 0, 1); + m_data.objectReference.ptr = (CLR_RT_HeapBlock*)ptr; + } + +#if defined(NANOCLR_APPDOMAINS) + CLR_RT_AppDomain* TransparentProxyAppDomain () const { return m_data.transparentProxy.appDomain; } + CLR_RT_HeapBlock* TransparentProxyDereference() const { return Dereference() ; } + + void SetTransparentProxyReference( CLR_RT_AppDomain* appDomain, CLR_RT_HeapBlock* ptr ); + HRESULT TransparentProxyValidate() const; + + bool IsTransparentProxy() const { return IsAReferenceOfThisType( DATATYPE_TRANSPARENT_PROXY ); } +#endif + + void SetReference( CLR_RT_HeapBlock& dst ) + { + CLR_RT_HeapBlock* obj; + + // + // ValueTypes are implemented as pointers to objects, + // so getting a reference to a ValueType has to be treated like getting a reference to object, not to its holder! + // + if(dst.IsAValueType()) + { + obj = dst.Dereference(); + } + else + { + obj = &dst; + } + + m_id.raw = CLR_RT_HEAPBLOCK_RAW_ID(DATATYPE_BYREF, 0, 1); + m_data.objectReference.ptr = obj; + } + + bool IsAReferenceOfThisType( CLR_DataType dataType ) const + { + if(DataType() == DATATYPE_OBJECT) + { + CLR_RT_HeapBlock* obj = Dereference(); + + if(obj && obj->DataType() == dataType) return true; + } + + return false; + } + + bool IsAValueType() const + { + if(DataType() == DATATYPE_OBJECT) + { + CLR_RT_HeapBlock* obj = Dereference(); + + if(obj && obj->DataType() == DATATYPE_VALUETYPE && obj->IsBoxed() == false) return true; + } + + return false; + } + + bool SameHeader( const CLR_RT_HeapBlock& right ) const + { + return this->m_data.numeric.u8 == right.m_data.numeric.u8; + } + + //--// + + CLR_RT_HeapBlock_Array* RecoverArrayHeader() const + { + return (DataType() == DATATYPE_ARRAY_BYREF) ? m_data.arrayReference.array : NULL; + } + + //--// + + const char* RecoverString() const + { + if(DataType() == DATATYPE_OBJECT) + { + const CLR_RT_HeapBlock* ptr = m_data.objectReference.ptr; + + if(ptr) + { + return ptr->StringText(); + } + } + + return NULL; + } + + //--// + const CLR_RT_HeapBlock_AtomicData& DataByRefConst() const { return m_data; } + + CLR_RT_HeapBlock_AtomicData::Numeric& NumericByRef () { return m_data.numeric; } + const CLR_RT_HeapBlock_AtomicData::Numeric& NumericByRefConst() const { return m_data.numeric; } + + //--// + + const char* StringText() const { return m_data.string.m_text; } + +#if defined(NANOCLR_NO_ASSEMBLY_STRINGS) + void SetStringText( const char* szText ) + { + m_data.string.m_text = szText; + } +#else + void SetStringText( const char* szText, CLR_RT_Assembly* assm ) + { + m_data.string.m_text = szText; + m_data.string.m_assm = assm; + } + + CLR_RT_Assembly* StringAssembly() const { return m_data.string.m_assm; } +#endif + + //--// + + const CLR_RT_TypeDef_Index& ObjectCls ( ) const { return m_data.objectHeader.cls ; } + CLR_RT_HeapBlock_Lock* ObjectLock ( ) const { return m_data.objectHeader.lock ; } + void SetObjectLock( CLR_RT_HeapBlock_Lock* lock ) { m_data.objectHeader.lock = lock; } + + HRESULT SetObjectCls( const CLR_RT_TypeDef_Index& cls ); + + //--// + + const CLR_RT_ReflectionDef_Index& ReflectionDataConst() const { return m_data.reflection; } + CLR_RT_ReflectionDef_Index& ReflectionData () { return m_data.reflection; } + + //--// + + CLR_RT_HeapBlock_Array* Array () const { return m_data.arrayReference.array ; } + CLR_UINT32 ArrayIndex () const { return m_data.arrayReference.index ; } + void ArrayIndexIncrement() { m_data.arrayReference.index++; } + + //--// + + CLR_RT_MarkingHandler BinaryBlobMarkingHandler () const { return m_data.binaryBlob.m_mark ; } + CLR_RT_RelocationHandler BinaryBlobRelocationHandler() const { return m_data.binaryBlob.m_relocate; } + + void SetBinaryBlobHandlers( CLR_RT_MarkingHandler mark, CLR_RT_RelocationHandler relocate ) + { + m_data.binaryBlob.m_mark = mark ; + m_data.binaryBlob.m_relocate = relocate; + } + + //--// + //--// + + CLR_RT_HeapBlock* Dereference() const { return m_data.objectReference.ptr; } + + CLR_RT_HeapBlock_WeakReference* DereferenceWeakReference() const { return (CLR_RT_HeapBlock_WeakReference*)Dereference(); } + CLR_RT_HeapBlock_String * DereferenceString () const { return (CLR_RT_HeapBlock_String *)Dereference(); } + CLR_RT_HeapBlock_Array * DereferenceArray () const { return (CLR_RT_HeapBlock_Array *)Dereference(); } + CLR_RT_HeapBlock_Delegate * DereferenceDelegate () const { return (CLR_RT_HeapBlock_Delegate *)Dereference(); } + CLR_RT_HeapBlock_Delegate_List* DereferenceDelegateList () const { return (CLR_RT_HeapBlock_Delegate_List*)Dereference(); } + CLR_RT_HeapBlock_BinaryBlob * DereferenceBinaryBlob () const { return (CLR_RT_HeapBlock_BinaryBlob *)Dereference(); } + + //--// + + void AssignId( const CLR_RT_HeapBlock& value ) + { + _ASSERTE(value.DataSize() == 1); + + m_id = value.m_id; + } + + void AssignData( const CLR_RT_HeapBlock& value ) + { + _ASSERTE(value.DataSize() == 1); + + m_data = value.m_data; + } + + void Assign( const CLR_RT_HeapBlock& value ) + { + _ASSERTE(value.DataSize() == 1); + + value.Debug_CheckPointer(); + + CLR_RT_HeapBlock_Raw* src = (CLR_RT_HeapBlock_Raw*) this; + CLR_RT_HeapBlock_Raw* dst = (CLR_RT_HeapBlock_Raw*)&value; + + *src = *dst; + } + + void AssignAndPreserveType( const CLR_RT_HeapBlock& value ) + { + _ASSERTE(value.DataSize() == 1); + + this->m_data = value.m_data; + + if(this->DataType() > DATATYPE_LAST_PRIMITIVE_TO_PRESERVE) this->m_id = value.m_id; + } + + void AssignPreserveTypeCheckPinned( const CLR_RT_HeapBlock& value ) + { + _ASSERTE(value.DataSize() == 1); + + + { // If local variable does not have pinned type - move source data into it + if (!IsPinned()) + { + AssignAndPreserveType( value ); + } + else // IsPinned() is true; + { AssignAndPinReferencedObject( value ); + } + } + } + + // This function is called for assigning to "pinned" reference variables. + // Since it is rare case, the code is not inlined to save code size. + void AssignAndPinReferencedObject( const CLR_RT_HeapBlock& value ); + + HRESULT Convert( CLR_DataType et, bool fOverflow, bool fUnsigned ) + { + // + // For V1, we don't throw on overflow. + // + return Convert_Internal( et ); + } + + bool InitObject(); + + //--// + + static CLR_INT32 Compare_Unsigned_Values( const CLR_RT_HeapBlock& left, const CLR_RT_HeapBlock& right ) { return Compare_Values( left, right, false ); } + static CLR_INT32 Compare_Signed_Values ( const CLR_RT_HeapBlock& left, const CLR_RT_HeapBlock& right ) { return Compare_Values( left, right, true ); } + + //--// + + + HRESULT SetReflection( const CLR_RT_ReflectionDef_Index& reflex ); + HRESULT SetReflection( const CLR_RT_Assembly_Index& assm ); + HRESULT SetReflection( const CLR_RT_TypeSpec_Index& sig ); + HRESULT SetReflection( const CLR_RT_TypeDef_Index& cls ); + HRESULT SetReflection( const CLR_RT_FieldDef_Index& fd ); + HRESULT SetReflection( const CLR_RT_MethodDef_Index& md ); + + + HRESULT InitializeArrayReference ( CLR_RT_HeapBlock& ref , int index ); + void InitializeArrayReferenceDirect( CLR_RT_HeapBlock_Array& array, int index ); + void FixArrayReferenceForValueTypes( ); + + HRESULT LoadFromReference ( CLR_RT_HeapBlock& ref ); + HRESULT StoreToReference ( CLR_RT_HeapBlock& ref, int size ); + HRESULT Reassign ( const CLR_RT_HeapBlock& value ); + HRESULT PerformBoxingIfNeeded( ); + HRESULT PerformBoxing ( const CLR_RT_TypeDef_Instance& cls ); + HRESULT PerformUnboxing ( const CLR_RT_TypeDef_Instance& cls ); + CLR_RT_HeapBlock* FixBoxingReference ( ); + HRESULT EnsureObjectReference( CLR_RT_HeapBlock*& obj ); + + //--// + + bool IsZero () const; + void Promote(); + + static CLR_UINT32 GetHashCode ( CLR_RT_HeapBlock* ptr, bool fRecurse, CLR_UINT32 crc ); + static bool ObjectsEqual ( const CLR_RT_HeapBlock& left, const CLR_RT_HeapBlock& right, bool fSameReference ); + + static CLR_INT32 Compare_Values( const CLR_RT_HeapBlock& left, const CLR_RT_HeapBlock& right, bool fSigned ); + + HRESULT Convert_Internal( CLR_DataType et ); + HRESULT NumericAdd ( const CLR_RT_HeapBlock& right ); + HRESULT NumericSub ( const CLR_RT_HeapBlock& right ); + HRESULT NumericMul ( const CLR_RT_HeapBlock& right ); + HRESULT NumericDiv ( const CLR_RT_HeapBlock& right ); + HRESULT NumericDivUn ( const CLR_RT_HeapBlock& right ); + HRESULT NumericRem ( const CLR_RT_HeapBlock& right ); + HRESULT NumericRemUn ( const CLR_RT_HeapBlock& right ); + HRESULT NumericShl ( const CLR_RT_HeapBlock& right ); + HRESULT NumericShr ( const CLR_RT_HeapBlock& right ); + HRESULT NumericShrUn ( const CLR_RT_HeapBlock& right ); + HRESULT NumericNeg ( ); + + CLR_RT_HeapBlock* ExtractValueBlock( int offset ); + void ReadValue ( CLR_INT64& val, int offset ); + void WriteValue ( const CLR_INT64& val, int offset ); + + void Relocate__HeapBlock(); + void Relocate_String (); + void Relocate_Obj (); + void Relocate_Cls (); + void Relocate_Ref (); + void Relocate_ArrayRef (); + +#if defined(NANOCLR_APPDOMAINS) + void Relocate_TransparentProxy(); +#endif + +private: + CLR_RT_HeapBlock& operator=( const CLR_RT_HeapBlock& ); + + +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +//--// + +#define NANOCLR_FOREACH_NODE(cls,ptr,lst) \ + { \ + cls* ptr; \ + cls* ptr##Next; \ + \ + for(ptr = (cls*)(lst).FirstNode(); (ptr##Next = (cls*)ptr->Next()) != NULL; ptr = ptr##Next) \ + { NANOCLR_FAULT_ON_EARLY_COLLECTION( ptr##Next ); + +#define NANOCLR_FOREACH_NODE__NODECL(cls,ptr,lst) \ + { \ + cls* ptr##Next; \ + \ + for(ptr = (cls*)(lst).FirstNode(); (ptr##Next = (cls*)ptr->Next()) != NULL; ptr = ptr##Next) \ + { NANOCLR_FAULT_ON_EARLY_COLLECTION( ptr##Next ); + +#define NANOCLR_FOREACH_NODE__DIRECT(cls,ptr,startNode) \ + { \ + cls* ptr; \ + cls* ptr##Next; \ + \ + for(ptr = (cls*)(startNode); (ptr##Next = (cls*)ptr->Next()) != NULL; ptr = ptr##Next) \ + { NANOCLR_FAULT_ON_EARLY_COLLECTION( ptr##Next ); + +#define NANOCLR_FOREACH_NODE_PREPARE_RELOAD(ptr) \ + NANOCLR_CANCEL_EARLY_COLLECTION(ptr##Next) + +#define NANOCLR_FOREACH_NODE_RELOAD(cls,ptr) \ + ptr##Next = (cls*)ptr->Next() + +#define NANOCLR_FOREACH_NODE_RESTART(cls,ptr,lst) \ + ptr##Next = (cls*)(lst).FirstNode(); continue + +#define NANOCLR_FOREACH_NODE_END() \ + } \ + } + + +#define NANOCLR_FOREACH_NODE_BACKWARD(cls,ptr,lst) \ + { \ + cls* ptr; \ + cls* ptr##Prev; \ + \ + for(ptr = (cls*)(lst).LastNode(); (ptr##Prev = (cls*)ptr->Prev()) != NULL; ptr = ptr##Prev) \ + { NANOCLR_FAULT_ON_EARLY_COLLECTION( ptr##Prev ); + +#define NANOCLR_FOREACH_NODE_BACKWARD__NODECL(cls,ptr,lst) \ + { \ + cls* ptr##Prev; \ + \ + for(ptr = (cls*)(lst).LastNode(); (ptr##Prev = (cls*)ptr->Prev()) != NULL; ptr = ptr##Prev) \ + { NANOCLR_FAULT_ON_EARLY_COLLECTION( ptr##Prev ); + +#define NANOCLR_FOREACH_NODE_BACKWARD__DIRECT(cls,ptr,startNode) \ + { \ + cls* ptr; \ + cls* ptr##Prev; \ + \ + for(ptr = (cls*)(startNode); (ptr##Prev = (cls*)ptr->Prev()) != NULL; ptr = ptr##Prev) \ + { NANOCLR_FAULT_ON_EARLY_COLLECTION( ptr##Prev ); + +#define NANOCLR_FOREACH_NODE_BACKWARD_RESTART(cls,ptr,lst) \ + ptr##Prev = (cls*)(lst).LastNode(); continue + +#define NANOCLR_FOREACH_NODE_BACKWARD_PREPARE_RELOAD(ptr) \ + NANOCLR_CANCEL_EARLY_COLLECTION(ptr##Prev) + +#define NANOCLR_FOREACH_NODE_BACKWARD_RELOAD(cls,ptr) \ + ptr##Prev = (cls*)ptr->Prev() + +#define NANOCLR_FOREACH_NODE_BACKWARD_END() \ + } \ + } + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +struct CLR_RT_HeapBlock_Node : public CLR_RT_HeapBlock +{ + friend struct CLR_RT_DblLinkedList; + + void GenericNode_Initialize() + { + ClearData(); + } + + CLR_RT_HeapBlock_Node* Next () const { return m_data.nodeLink.nextBlock; } + CLR_RT_HeapBlock_Node* Prev () const { return m_data.nodeLink.prevBlock; } + + void SetNext( CLR_RT_HeapBlock_Node* next ) { m_data.nodeLink.nextBlock = next; } + void SetPrev( CLR_RT_HeapBlock_Node* prev ) { m_data.nodeLink.prevBlock = prev; } + + // + // The ARM compiler cannot inline these methods, + // it keeps injecting a call to a 4 instruction-long function (arg!!). + // + // So we'll have to use the explicit check... + // + //bool IsValidForward () const { return Next() != NULL; } + //bool IsValidBackward() const { return Prev() != NULL; } + + //--// + +#if NANOCLR_VALIDATE_HEAP >= NANOCLR_VALIDATE_HEAP_1_HeapBlocksAndUnlink + void ConsistencyCheck_Nodes( CLR_RT_HeapBlock_Node* prev, CLR_RT_HeapBlock_Node* next ) + { + if( prev && next) return; + if(!prev && !next) return; + + CLR_Debug::Printf( "Bad node!!\r\n" ); + + NANOCLR_DEBUG_STOP(); + } + +#else + + void ConsistencyCheck_Nodes( CLR_RT_HeapBlock_Node* prev, CLR_RT_HeapBlock_Node* next ) {} + +#endif + + void RemoveFromList() + { + CLR_RT_HeapBlock_Node* prev = m_data.nodeLink.prevBlock; + CLR_RT_HeapBlock_Node* next = m_data.nodeLink.nextBlock; + + ConsistencyCheck_Nodes( prev, next ); + + if(prev) prev->m_data.nodeLink.nextBlock = next; + if(next) next->m_data.nodeLink.prevBlock = prev; + } + + void Unlink() + { + CLR_RT_HeapBlock_Node* prev = m_data.nodeLink.prevBlock; + CLR_RT_HeapBlock_Node* next = m_data.nodeLink.nextBlock; + + ConsistencyCheck_Nodes( prev, next ); + + if(prev) prev->m_data.nodeLink.nextBlock = next; + if(next) next->m_data.nodeLink.prevBlock = prev; + + m_data.nodeLink.prevBlock = NULL; + m_data.nodeLink.nextBlock = NULL; + } + + //--// + + void Relocate(); +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +struct CLR_RT_DblLinkedList +{ +private: + // + // Logically, a list starts with a CLR_RT_HeapBlock_Node with only the Next() set and ends with a node with only Prev() set. + // This can be collapsed to have the two nodes overlap. + // + CLR_RT_HeapBlock_Node* m_first; // ANY HEAP - DO RELOCATION - + CLR_RT_HeapBlock_Node* m_null; + CLR_RT_HeapBlock_Node* m_last; // ANY HEAP - DO RELOCATION - + + //--// + +public: + void DblLinkedList_Initialize (); + void DblLinkedList_PushToCache(); + void DblLinkedList_Release (); + + int NumOfNodes (); + + void Relocate (); + + //--// + + CLR_RT_HeapBlock_Node* FirstNode () const { return m_first ; } + CLR_RT_HeapBlock_Node* LastNode () const { return m_last ; } + bool IsEmpty () const { return m_first == Tail(); } + + CLR_RT_HeapBlock_Node* FirstValidNode() const { CLR_RT_HeapBlock_Node* res = m_first; return res->Next() ? res : NULL; } + CLR_RT_HeapBlock_Node* LastValidNode () const { CLR_RT_HeapBlock_Node* res = m_last ; return res->Prev() ? res : NULL; } + + // Check that node pNode is not "dummy" tail or head node. + static bool IsValidListNode( CLR_RT_HeapBlock_Node* pNode ) + { + return pNode->m_data.nodeLink.nextBlock != NULL && pNode->m_data.nodeLink.prevBlock != NULL; + } + + CLR_RT_HeapBlock_Node* Head() const { return (CLR_RT_HeapBlock_Node*)((size_t)&m_first - offsetof(CLR_RT_HeapBlock, m_data.nodeLink.nextBlock)); } + CLR_RT_HeapBlock_Node* Tail() const { return (CLR_RT_HeapBlock_Node*)((size_t)&m_last - offsetof(CLR_RT_HeapBlock, m_data.nodeLink.prevBlock)); } + +#if NANOCLR_VALIDATE_HEAP >= NANOCLR_VALIDATE_HEAP_2_DblLinkedList + void ValidateList(); +#else + void ValidateList() {}; +#endif + + //--// + +private: + void Insert( CLR_RT_HeapBlock_Node* prev, CLR_RT_HeapBlock_Node* next, CLR_RT_HeapBlock_Node* node ) + { + node->m_data.nodeLink.nextBlock = next; + node->m_data.nodeLink.prevBlock = prev; + + next->m_data.nodeLink.prevBlock = node; + prev->m_data.nodeLink.nextBlock = node; + } + +public: + void InsertBeforeNode( CLR_RT_HeapBlock_Node* node, CLR_RT_HeapBlock_Node* nodeNew ) + { + ValidateList(); + + if(node && nodeNew && node != nodeNew) + { + nodeNew->RemoveFromList(); + + Insert( node->Prev(), node, nodeNew ); + } + } + + void InsertAfterNode( CLR_RT_HeapBlock_Node* node, CLR_RT_HeapBlock_Node* nodeNew ) + { + ValidateList(); + + if(node && nodeNew && node != nodeNew) + { + nodeNew->RemoveFromList(); + + Insert( node, node->Next(), nodeNew ); + } + } + + void LinkAtFront( CLR_RT_HeapBlock_Node* node ) + { + InsertAfterNode( Head(), node ); + } + + void LinkAtBack( CLR_RT_HeapBlock_Node* node ) + { + InsertBeforeNode( Tail(), node ); + } + + CLR_RT_HeapBlock_Node* ExtractFirstNode() + { + ValidateList(); + + CLR_RT_HeapBlock_Node* node = FirstValidNode(); + + if(node) node->Unlink(); + + return node; + } + + CLR_RT_HeapBlock_Node* ExtractLastNode() + { + ValidateList(); + + CLR_RT_HeapBlock_Node* node = LastValidNode(); + + if(node) node->Unlink(); + + return node; + } + + //--// + + PROHIBIT_COPY_CONSTRUCTORS(CLR_RT_DblLinkedList); +}; + + +struct CLR_RT_AVLTree +{ + struct Owner; + + enum Skew + { + SKEW_LEFT = -1, + SKEW_NONE = 0, + SKEW_RIGHT = 1, + }; + + enum Result + { + RES_OK = 0, + RES_BALANCE = 1, + RES_NOTFOUND = 2, + RES_DUPLICATE = 3, + RES_ERROR = 4, + }; + + struct Entry : public CLR_RT_HeapBlock_Node + { + Entry* m_left; + Entry* m_right; + Skew m_skew; + }; + + typedef int (*ComparerFtn)( void* state, Entry* left, Entry* right ); + typedef Entry* (*NewNodeFtn )( void* state, Entry* payload ); + typedef void (*FreeNodeFtn)( void* state, Entry* node ); + typedef void (*ReassignFtn)( void* state, Entry* from, Entry* to ); + + struct OwnerInfo + { + ComparerFtn m_ftn_compare; + NewNodeFtn m_ftn_newNode; + FreeNodeFtn m_ftn_freeNode; + ReassignFtn m_ftn_reassignNode; + void* m_state; + }; + + //--// + + Entry* m_root; + OwnerInfo m_owner; + + //--// + + void Initialize(); + + Result Insert( Entry* newDatum ); + Result Remove( Entry* oldDatum ); + Entry* Find ( Entry* srcDatum ); + +private: + static void RotateLeft ( Entry*& n ); + static void RotateRight ( Entry*& n ); + + static Result LeftGrown ( Entry*& n ); + static Result RightGrown ( Entry*& n ); + + static Result LeftShrunk ( Entry*& n ); + static Result RightShrunk ( Entry*& n ); + + bool FindHighest ( Entry*& n, Entry* target, Result& res ); + bool FindLowest ( Entry*& n, Entry* target, Result& res ); + + Result Insert( Entry*& n, Entry* newDatum ); + Result Remove( Entry*& n, Entry* oldDatum ); +}; + + +//////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////// + +struct CLR_RT_HeapBlock_String : public CLR_RT_HeapBlock +{ + static CLR_RT_HeapBlock_String* CreateInstance( CLR_RT_HeapBlock& reference, CLR_UINT32 length ); + static HRESULT CreateInstance( CLR_RT_HeapBlock& reference, const char* szText ); + static HRESULT CreateInstance( CLR_RT_HeapBlock& reference, const char* szText, CLR_UINT32 length ); + static HRESULT CreateInstance( CLR_RT_HeapBlock& reference, CLR_UINT32 token , CLR_RT_Assembly* assm ); + static HRESULT CreateInstance( CLR_RT_HeapBlock& reference, const char* szText, CLR_RT_Assembly* assm ); + static HRESULT CreateInstance( CLR_RT_HeapBlock& reference, CLR_UINT16* szText, CLR_UINT32 length ); + + static CLR_RT_HeapBlock_String* GetStringEmpty(); +}; + +struct CLR_RT_HeapBlock_Array : public CLR_RT_HeapBlock +{ + CLR_UINT32 m_numOfElements; + CLR_UINT8 m_typeOfElement; + CLR_UINT8 m_sizeOfElement; + CLR_UINT8 m_fReference; + CLR_UINT8 m_pad; + + //--// + + static HRESULT CreateInstance( CLR_RT_HeapBlock& reference, CLR_UINT32 length, const CLR_RT_ReflectionDef_Index& reflex ); + static HRESULT CreateInstance( CLR_RT_HeapBlock& reference, CLR_UINT32 length, const CLR_RT_TypeDef_Index& cls ); + static HRESULT CreateInstance( CLR_RT_HeapBlock& reference, CLR_UINT32 length, CLR_RT_Assembly* assm , CLR_UINT32 tk ); + + CLR_UINT8* GetFirstElement() { return ((CLR_UINT8*)&this[ 1 ]); } + + CLR_UINT8* GetElement( CLR_UINT32 index ) { return GetFirstElement() + m_sizeOfElement * index; } + + CLR_UINT16* GetFirstElementUInt16() { return ((CLR_UINT16*)&this[ 1 ]); } + + CLR_UINT16* GetElementUInt16( CLR_UINT32 index ) { return GetFirstElementUInt16() + m_sizeOfElement * index; } + + HRESULT ClearElements( int index, int length ); + + //--// + + void Relocate(); + + //--// + + static bool CheckRange( int index, int length, int numOfElements ); + + static HRESULT IndexOf( CLR_RT_HeapBlock_Array* array, CLR_RT_HeapBlock& match, int start, int stop, bool fForward, int& index ); + static HRESULT Copy( CLR_RT_HeapBlock_Array* arraySrc, int indexSrc, CLR_RT_HeapBlock_Array* arrayDst, int indexDst, int length ); +}; + +struct CLR_RT_HeapBlock_Delegate : public CLR_RT_HeapBlock_Node // OBJECT HEAP - DO RELOCATION - +{ + CLR_RT_TypeDef_Index m_cls; + CLR_RT_MethodDef_Index m_ftn; +#if defined(NANOCLR_DELEGATE_PRESERVE_STACK) + CLR_UINT32 m_numOfStackFrames; +#endif + CLR_RT_HeapBlock m_object; // ANY HEAP - DO RELOCATION - + +#if defined(NANOCLR_APPDOMAINS) + CLR_RT_AppDomain* m_appDomain; +#endif + + //--// + + const CLR_RT_MethodDef_Index& DelegateFtn () const { return m_ftn ; } +#if defined(NANOCLR_DELEGATE_PRESERVE_STACK) + CLR_UINT32 DelegateNumOfStackFrames() const { return m_numOfStackFrames ; } + CLR_RT_MethodDef_Index* GetStackFrames() { return (CLR_RT_MethodDef_Index*)&this[ 1 ]; } +#endif + //--// + + static HRESULT CreateInstance( CLR_RT_HeapBlock& reference, const CLR_RT_MethodDef_Index& ftn, CLR_RT_StackFrame* call ); + + void Relocate(); +}; + +struct CLR_RT_HeapBlock_Delegate_List : public CLR_RT_HeapBlock_Node // OBJECT HEAP - DO RELOCATION - +{ + static const CLR_UINT32 c_Weak = 0x00000001; + + CLR_RT_TypeDef_Index m_cls; + CLR_UINT32 m_length; + CLR_UINT32 m_flags; + + CLR_RT_HeapBlock* GetDelegates() { return &this[ 1 ]; } // ANY HEAP - DO RELOCATION - + + //--// + + static HRESULT CreateInstance( CLR_RT_HeapBlock_Delegate_List*& list, CLR_UINT32 length ); + + static HRESULT Combine( CLR_RT_HeapBlock& reference, CLR_RT_HeapBlock& delegateSrc, CLR_RT_HeapBlock& delegateNew, bool fWeak ); + static HRESULT Remove ( CLR_RT_HeapBlock& reference, CLR_RT_HeapBlock& delegateSrc, CLR_RT_HeapBlock& delegateOld ); + + void Relocate(); + +private: + + static HRESULT Change( CLR_RT_HeapBlock& reference, CLR_RT_HeapBlock& delegateSrc, CLR_RT_HeapBlock& delegateTarget, bool fCombine, bool fWeak ); + + CLR_RT_HeapBlock* CopyAndCompress( CLR_RT_HeapBlock* src, CLR_RT_HeapBlock* dst, CLR_UINT32 num ); +}; + +//--// + +struct CLR_RT_HeapBlock_BinaryBlob : public CLR_RT_HeapBlock +{ + friend struct CLR_RT_Memory; + + //--// + + CLR_RT_Assembly* m_assembly; + + void* GetData( ) { return (void*)&this[ 1 ] ; } + static CLR_RT_HeapBlock_BinaryBlob* GetBlob( void* data ) { return (CLR_RT_HeapBlock_BinaryBlob*)data - 1; } + + //--// + + static HRESULT CreateInstance( CLR_RT_HeapBlock& reference, CLR_UINT32 length, CLR_RT_MarkingHandler mark, CLR_RT_RelocationHandler relocate, CLR_UINT32 flags ); + + void Release( bool fEvent ); + + void Relocate(); + +private: + static CLR_RT_HeapBlock_BinaryBlob* Allocate( CLR_UINT32 length, CLR_UINT32 flags ); +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////// + +struct CLR_RT_ObjectToEvent_Destination : public CLR_RT_HeapBlock_Node // EVENT HEAP - NO RELOCATION - +{ + CLR_RT_DblLinkedList m_references; // EVENT HEAP - NO RELOCATION - list of CLR_RT_ObjectToEvent_Source + + //--// + + void Initialize (); + void CheckAll (); + void SignalAll (); + void DetachAll (); + bool IsReadyForRelease(); + bool ReleaseWhenDead (); +}; + +struct CLR_RT_ObjectToEvent_Source : public CLR_RT_HeapBlock_Node // EVENT HEAP - NO RELOCATION - +{ + CLR_RT_ObjectToEvent_Destination* m_eventPtr; // EVENT HEAP - NO RELOCATION - Pointer to the event referenced. + + CLR_RT_HeapBlock* m_objectPtr; // OBJECT HEAP - DO RELOCATION - Pointer to the object to keep alive. + CLR_RT_HeapBlock* m_referencePtr; // OBJECT HEAP - DO RELOCATION - Pointer to the HeapBlock referencing this structure. + + //--// + + static HRESULT CreateInstance ( CLR_RT_ObjectToEvent_Destination* event, CLR_RT_HeapBlock& object, CLR_RT_HeapBlock& reference ); + static CLR_RT_ObjectToEvent_Source* ExtractInstance( CLR_RT_HeapBlock& reference ); + + void EnsureObjectIsAlive(); + void Detach (); + + void Relocate (); +}; + +//////////////////////////////////////// + +struct CLR_RT_HeapBlock_Button : public CLR_RT_HeapBlock_Node // EVENT HEAP - NO RELOCATION - +{ + int m_key; + bool m_fPressed; +}; + +//--// + +struct CLR_RT_HeapBlock_Lock : public CLR_RT_HeapBlock_Node // EVENT HEAP - NO RELOCATION - +{ + struct Owner : public CLR_RT_HeapBlock_Node // EVENT HEAP - NO RELOCATION - + { + CLR_RT_SubThread* m_owningSubThread; // EVENT HEAP - NO RELOCATION - + CLR_UINT32 m_recursion; + }; + + CLR_RT_Thread* m_owningThread; // EVENT HEAP - NO RELOCATION - + + CLR_RT_HeapBlock m_resource; // OBJECT HEAP - DO RELOCATION - + +#if defined(NANOCLR_APPDOMAINS) + CLR_RT_AppDomain* m_appDomain; // EVENT HEAP - NO RELOCATION - +#endif + + CLR_RT_DblLinkedList m_owners; // EVENT HEAP - NO RELOCATION - list of CLR_RT_HeapBlock_Lock::Owner + CLR_RT_DblLinkedList m_requests; // EVENT HEAP - NO RELOCATION - list of CLR_RT_HeapBlock_LockRequest + + //--// + + static HRESULT CreateInstance ( CLR_RT_HeapBlock_Lock*& lock, CLR_RT_Thread* th, CLR_RT_HeapBlock& resource ); + static HRESULT IncrementOwnership( CLR_RT_HeapBlock_Lock* lock, CLR_RT_SubThread* sth, const CLR_INT64& timeExpire, bool fForce ); + static HRESULT DecrementOwnership( CLR_RT_HeapBlock_Lock* lock, CLR_RT_SubThread* sth ); + + void DestroyOwner( CLR_RT_SubThread* sth ); + void ChangeOwner ( ); + + void Relocate (); + void Relocate_Owner(); +}; + +struct CLR_RT_HeapBlock_LockRequest : public CLR_RT_HeapBlock_Node // EVENT HEAP - NO RELOCATION - +{ + CLR_RT_SubThread* m_subthreadWaiting; // EVENT HEAP - NO RELOCATION - + CLR_INT64 m_timeExpire; + bool m_fForce; + + //--// + + static HRESULT CreateInstance( CLR_RT_HeapBlock_Lock* lock, CLR_RT_SubThread* sth, const CLR_INT64& timeExpire, bool fForce ); +}; + +struct CLR_RT_HeapBlock_Timer : public CLR_RT_ObjectToEvent_Destination // EVENT HEAP - NO RELOCATION - +{ + static const CLR_UINT32 c_NoFixedChange = 0x00000000; + static const CLR_UINT32 c_SecondChange = 0x00000001; + static const CLR_UINT32 c_MinuteChange = 0x00000002; + static const CLR_UINT32 c_HourChange = 0x00000003; + static const CLR_UINT32 c_DayChange = 0x00000004; + static const CLR_UINT32 c_TimeZoneChange = 0x00000005; + static const CLR_UINT32 c_SetTimeChange = 0x00000006; + static const CLR_UINT32 c_AnyChange = 0x0000000F; + + static const CLR_UINT32 c_Triggered = 0x00000010; + static const CLR_UINT32 c_Executing = 0x00000020; + + static const CLR_UINT32 c_ACTION_Create = 0x00010000; + static const CLR_UINT32 c_ACTION_Change = 0x00020000; + static const CLR_UINT32 c_ACTION_Destroy = 0x00040000; + static const CLR_UINT32 c_UNUSED_00080000 = 0x00080000; + + static const CLR_UINT32 c_INPUT_Int32 = 0x00100000; + static const CLR_UINT32 c_INPUT_TimeSpan = 0x00200000; + + static const CLR_UINT32 c_UNUSED_10000000 = 0x10000000; + static const CLR_UINT32 c_Recurring = 0x40000000; + static const CLR_UINT32 c_EnabledTimer = 0x80000000; + + //--// + + static const CLR_INT32 c_TickPerMillisecond = 10000; + //--// + + CLR_UINT32 m_flags; + CLR_INT64 m_timeExpire; + CLR_INT64 m_timeFrequency; + CLR_INT64 m_timeLastExpiration; + CLR_INT64 m_ticksLastExpiration; + + //--// + + static HRESULT CreateInstance ( CLR_UINT32 flags, CLR_RT_HeapBlock& owner, CLR_RT_HeapBlock& tmRef ); + static HRESULT ExtractInstance( CLR_RT_HeapBlock& ref , CLR_RT_HeapBlock_Timer*& timer ); + static HRESULT ConfigureObject( CLR_RT_StackFrame& stack, CLR_UINT32 flags ); + static bool CheckDisposed ( CLR_RT_StackFrame& stack ); + + void AdjustNextFixedExpire( const SYSTEMTIME& systemTime, bool fNext ); + + void Trigger (); + void Reschedule (); + void RecoverFromGC(); + void SpawnTimer ( CLR_RT_Thread* thread ); + + static void ThreadTerminationCallback( void* param ); +}; + +struct CLR_RT_HeapBlock_EndPoint : public CLR_RT_ObjectToEvent_Destination // EVENT HEAP - NO RELOCATION - +{ + struct Port + { + CLR_UINT32 m_type; + CLR_UINT32 m_id; + + bool Compare( const Port& port ); + }; + + struct Address + { + CLR_UINT32 m_seq; + Port m_from; + Port m_to; + }; + + + struct Message : public CLR_RT_HeapBlock_Node + { + CLR_UINT32 m_cmd; + Address m_addr; + + CLR_UINT32 m_found; + CLR_UINT32 m_length; + + CLR_UINT8 m_data[ 1 ]; + }; + + Port m_addr; + CLR_RT_DblLinkedList m_messages; + CLR_UINT32 m_seq; + + //--// + + static CLR_RT_DblLinkedList m_endPoints; + + static void HandlerMethod_Initialize (); + static void HandlerMethod_RecoverFromGC(); + static void HandlerMethod_CleanUp (); + + static CLR_RT_HeapBlock_EndPoint* FindEndPoint( const CLR_RT_HeapBlock_EndPoint::Port& port ); + + static HRESULT CreateInstance ( const CLR_RT_HeapBlock_EndPoint::Port& port, CLR_RT_HeapBlock& owner, CLR_RT_HeapBlock& epRef ); + static HRESULT ExtractInstance( CLR_RT_HeapBlock& ref , CLR_RT_HeapBlock_EndPoint*& endPoint ); + + bool ReleaseWhenDeadEx(); + void RecoverFromGC (); + + Message* FindMessage( CLR_UINT32 cmd, const CLR_UINT32* seq ); +}; + +//--// + +struct CLR_RT_HeapBlock_WaitForObject : public CLR_RT_HeapBlock_Node // EVENT HEAP - NO RELOCATION - +{ + CLR_INT64 m_timeExpire; + CLR_UINT32 m_cObjects; + bool m_fWaitAll; + + CLR_RT_HeapBlock* GetWaitForObjects() { return &this[ 1 ]; } // EVENT HEAP - DO RELOCATION - + + //--// + + static HRESULT WaitForSignal ( CLR_RT_StackFrame& stack, const CLR_INT64& timeExpire, CLR_RT_HeapBlock& object ); + static HRESULT WaitForSignal ( CLR_RT_StackFrame& stack, const CLR_INT64& timeExpire, CLR_RT_HeapBlock* objects, CLR_UINT32 cObjects, bool fWaitAll ); + static void SignalObject ( CLR_RT_HeapBlock& object ); + + void Relocate(); + +private: + static bool TryWaitForSignal ( CLR_RT_Thread* caller, CLR_RT_HeapBlock* objects, CLR_UINT32 cObjects, bool fWaitAll ); + static void TryWaitForSignal ( CLR_RT_Thread* caller ); + static HRESULT CreateInstance ( CLR_RT_Thread* caller, const CLR_INT64& timeExpire, CLR_RT_HeapBlock* objects, CLR_UINT32 cObjects, bool fWaitAll ); +}; + +//--// + +struct CLR_RT_HeapBlock_Finalizer : public CLR_RT_HeapBlock_Node // EVENT HEAP - NO RELOCATION - +{ + CLR_RT_HeapBlock* m_object; // OBJECT HEAP - DO RELOCATION - + CLR_RT_MethodDef_Index m_md; + +#if defined(NANOCLR_APPDOMAINS) + CLR_RT_AppDomain* m_appDomain; +#endif + + //--// + + static HRESULT CreateInstance( CLR_RT_HeapBlock* object, const CLR_RT_TypeDef_Instance& inst ); + + void Relocate(); + + static void SuppressFinalize( CLR_RT_HeapBlock* object ); + +private: + static void RemoveInstance( CLR_RT_HeapBlock* object, CLR_RT_DblLinkedList& lst ); +}; + +//--// + +struct CLR_RT_HeapBlock_MemoryStream : public CLR_RT_HeapBlock_Node // EVENT HEAP - NO RELOCATION - +{ + struct Buffer : public CLR_RT_HeapBlock_Node // EVENT HEAP - NO RELOCATION - + { + static const int c_NumOfBlocks = 32; + static const int c_PayloadSize = c_NumOfBlocks * sizeof(CLR_RT_HeapBlock) - sizeof(CLR_UINT8*) - sizeof(int); + + CLR_UINT8* m_data; + int m_length; + CLR_UINT8 m_payload[ c_PayloadSize ]; + }; + + //--// + + CLR_RT_DblLinkedList m_buffers; // EVENT HEAP - NO RELOCATION - list of CLR_RT_HeapBlock_MemoryStream::Buffer + + Buffer* m_current; + int m_pos; + CLR_UINT32 m_avail; + + //--// + + static HRESULT CreateInstance( CLR_RT_HeapBlock_MemoryStream*& stream, CLR_UINT8* buf, int len ); + static void DeleteInstance( CLR_RT_HeapBlock_MemoryStream*& stream ); + + void Release(); + + void Rewind(); + void Reset(); + + HRESULT ToArray ( CLR_RT_HeapBlock& ref ); + + int BitsAvailable(); + int BitsWritten (); + + HRESULT ReadBits ( CLR_UINT32& val, CLR_UINT32 bits ); + HRESULT WriteBits ( CLR_UINT32 val, CLR_UINT32 bits ); + + HRESULT ReadBits ( CLR_UINT64& val, CLR_UINT32 bits ); + HRESULT WriteBits ( CLR_UINT64 val, CLR_UINT32 bits ); + + HRESULT ReadArray ( CLR_UINT8* buf, CLR_UINT32 bytes ); + HRESULT WriteArray( const CLR_UINT8* buf, CLR_UINT32 bytes ); + +private: + + HRESULT Initialize( CLR_UINT8* buf, CLR_UINT32 len ); + + Buffer* NewBuffer(); +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////// + +struct CLR_RT_HeapBlock_WeakReference_Identity +{ + CLR_UINT32 m_crc; + CLR_UINT32 m_flags; + CLR_UINT32 m_length; + + CLR_UINT32 m_selectorHash; + CLR_UINT32 m_id; + CLR_INT32 m_priority; + + CLR_UINT32 ComputeCRC( const CLR_UINT8* ptr, CLR_UINT32 len ) const; +}; + +struct CLR_RT_HeapBlock_WeakReference : public CLR_RT_HeapBlock_Node // OBJECT HEAP - DO RELOCATION - +{ + static const CLR_UINT32 WR_SurviveBoot = 0x00000001; + static const CLR_UINT32 WR_SurvivePowerdown = 0x00000002; + static const CLR_UINT32 WR_ArrayOfBytes = 0x00000004; + static const CLR_UINT32 WR_Unused_00000008 = 0x00000008; + static const CLR_UINT32 WR_Unused_00000010 = 0x00000010; + static const CLR_UINT32 WR_Unused_00000020 = 0x00000020; + static const CLR_UINT32 WR_Unused_00000040 = 0x00000040; + static const CLR_UINT32 WR_Unused_00000080 = 0x00000080; + static const CLR_UINT32 WR_Unused_00000100 = 0x00000100; + static const CLR_UINT32 WR_Unused_00000200 = 0x00000200; + static const CLR_UINT32 WR_Unused_00000400 = 0x00000400; + static const CLR_UINT32 WR_Unused_00000800 = 0x00000800; + static const CLR_UINT32 WR_Unused_00001000 = 0x00001000; + static const CLR_UINT32 WR_Unused_00002000 = 0x00002000; + static const CLR_UINT32 WR_Unused_00004000 = 0x00004000; + static const CLR_UINT32 WR_Unused_00008000 = 0x00008000; + static const CLR_UINT32 WR_Unused_00010000 = 0x00010000; + static const CLR_UINT32 WR_Unused_00020000 = 0x00020000; + static const CLR_UINT32 WR_Unused_00040000 = 0x00040000; + static const CLR_UINT32 WR_Unused_00080000 = 0x00080000; + static const CLR_UINT32 WR_Unused_00100000 = 0x00100000; + static const CLR_UINT32 WR_Unused_00200000 = 0x00200000; + static const CLR_UINT32 WR_Unused_00400000 = 0x00400000; + static const CLR_UINT32 WR_Unused_00800000 = 0x00800000; + static const CLR_UINT32 WR_Unused_01000000 = 0x01000000; + static const CLR_UINT32 WR_Unused_02000000 = 0x02000000; + static const CLR_UINT32 WR_Unused_04000000 = 0x04000000; + static const CLR_UINT32 WR_Unused_08000000 = 0x08000000; + static const CLR_UINT32 WR_Unused_10000000 = 0x10000000; + static const CLR_UINT32 WR_Persisted = 0x20000000; + static const CLR_UINT32 WR_Restored = 0x40000000; + + //--// + + CLR_RT_HeapBlock_WeakReference_Identity m_identity; + + CLR_RT_HeapBlock* m_targetDirect; // OBJECT HEAP - DO RELOCATION - + CLR_RT_HeapBlock_Array* m_targetSerialized; // OBJECT HEAP - DO RELOCATION - + CLR_RT_HeapBlock_Array* m_targetCopied; // OBJECT HEAP - NO RELOCATION - + + //--// + + static HRESULT CreateInstance( CLR_RT_HeapBlock_WeakReference*& weakref ); + + static void RecoverObjects ( CLR_RT_DblLinkedList& lstHeap ); + static bool PrepareForRecovery( CLR_RT_HeapBlock_Node* ptr, CLR_RT_HeapBlock_Node* end, CLR_UINT32 blockSize ); + + HRESULT SetTarget( CLR_RT_HeapBlock& targetReference ); + HRESULT GetTarget( CLR_RT_HeapBlock& targetReference ); + + void InsertInPriorityOrder(); + + void Relocate(); +}; + +//--// + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + +struct CLR_RT_Persistence_Manager +{ + static const CLR_UINT32 c_Erased = 0xFFFFFFFF; + + struct ObjectHeader + { + static const CLR_UINT32 c_Version = 0x504F5631; // POV1 = Persisted Object V1 + + static const CLR_UINT32 c_InUseBlock = 0xFFFFFFFF; + static const CLR_UINT32 c_DeletedBlock = 0x00000000; + + CLR_UINT32 m_signature; + CLR_UINT32 m_status; + + CLR_UINT32 m_crcIdentity; + CLR_RT_HeapBlock_WeakReference_Identity m_identity; + + CLR_RT_HeapBlock_Array m_object; + + //--// + + static ObjectHeader* Find( FLASH_WORD* start, FLASH_WORD* end ); + + bool Initialize( CLR_RT_HeapBlock_WeakReference* ref ); + + bool HasGoodSignature() const { return m_signature == c_Version ; } + bool IsInUse () const { return m_status == c_InUseBlock; } + + bool IsGood( bool fIncludeData ) const; + + void Delete(); + + CLR_UINT32 Length( ) const; + static CLR_UINT32 Length( const CLR_RT_HeapBlock_WeakReference* ref ); + static CLR_UINT32 Length( CLR_UINT32 data ); + + ObjectHeader* Next() const; + + private: + CLR_UINT32 ComputeCRC() const; + + //--// + }; + + struct BankHeader + { + static const CLR_UINT32 c_Version = 0x50535631; // PSV1 = Persisted Storage V1 + + static const CLR_UINT32 c_InUseBank = 0xFFFFFFFF; + static const CLR_UINT32 c_DeletedBank = 0x00000000; + + CLR_UINT32 m_signature; + CLR_UINT32 m_status; + + CLR_UINT32 m_sequenceNumber; + + //--// + + static BankHeader* Find( FLASH_WORD* start, FLASH_WORD* end ); + + void Initialize(); + + bool HasGoodSignature() const { return m_signature == c_Version; } + bool IsInUse () const { return m_status == c_InUseBank; } + + bool IsGood() const; + + void Delete(); + + ObjectHeader* FirstObjectHeader() const { return (ObjectHeader*)&this[ 1 ]; } + }; + + struct Bank + { + static const CLR_UINT32 c_SafetyMargin = 10; + + static const FLASH_WORD c_Erased = 0xFFFFFFFF; + static const FLASH_WORD c_Invalidated = 0x00000000; + + //--// + + CLR_UINT32 m_totalBytes; + CLR_UINT32 m_totalSafeBytes; + + BlockStorageStream m_stream; + + BankHeader* m_bankHeader; + + FLASH_WORD* m_start; + FLASH_WORD* m_end; + + FLASH_WORD* m_current; + + //--// + + bool IsGood() const; + + bool Initialize( unsigned int kind ); + + bool Erase ( int& sectorIndex ); + void EraseAll( ); + + bool Format ( ); + bool SetSequence( CLR_UINT32 sequenceNumber ); + + void Switch( Bank& other ); + + CLR_RT_Persistence_Manager::ObjectHeader* RecoverHeader( CLR_RT_HeapBlock_WeakReference* ref ); + bool WriteHeader ( CLR_RT_HeapBlock_WeakReference* ref, ObjectHeader*& pOH, FLASH_WORD*& pData ); + + //--// + + BankHeader* GetBankHeader() const { return m_bankHeader; } + + //--// + + void ReloadNonXIPBufferData(); + + bool WriteNonXIPData(FLASH_WORD* dst, CLR_UINT32 length); + + static bool FindBankWriteNonXIPData(FLASH_WORD* dst, CLR_UINT32 length); + //--// + + static bool CanWrite ( FLASH_WORD* dst, CLR_UINT32 length ); + static bool Write ( FLASH_WORD* dst, const FLASH_WORD* src , CLR_UINT32 length ); + static void Invalidate( FLASH_WORD* dst, FLASH_WORD match, CLR_UINT32 length ); + + static FLASH_WORD* IncrementPointer( FLASH_WORD* ptr, CLR_UINT32 length ) + { + return (FLASH_WORD*)((CLR_UINT8*)ptr + length); + } + static FLASH_WORD* DecrementPointer( FLASH_WORD* ptr, CLR_UINT32 length ) { return (FLASH_WORD*)((CLR_UINT8*)ptr - length); } + }; + + //--// + + static const CLR_UINT32 STATE_FlushNextObject = 0; + static const CLR_UINT32 STATE_Idle = 1; + static const CLR_UINT32 STATE_Erase = 2; + static const CLR_UINT32 STATE_EraseSector = 3; + static const CLR_UINT32 STATE_CopyToOtherBank = 4; + static const CLR_UINT32 STATE_CopyBackToRam = 5; + static const CLR_UINT32 STATE_SwitchBank = 6; + + static const CLR_UINT32 c_MaxWriteBurst = 128; + + //--// + + HAL_COMPLETION m_completion; + + unsigned int m_margin_BurstWrite; + unsigned int m_margin_BlockErase; + + Bank m_bankA; + Bank m_bankB; + + CLR_UINT32 m_state; + + CLR_RT_HeapBlock_WeakReference* m_pending_object; + ObjectHeader* m_pending_header; + CLR_UINT32 m_pending_size; + FLASH_WORD* m_pending_src; + FLASH_WORD* m_pending_dst; + + int m_eraseIndex; + + //--// + + void Initialize(); + void Uninitialize(); + void EraseAll (); + + void InvalidateEntry( CLR_RT_HeapBlock_WeakReference* weak ); + + void Relocate(); + + ObjectHeader* RecoverHeader( CLR_RT_HeapBlock_WeakReference* ref ); + + static void Callback( void* arg ); + + #if !defined(BUILD_RTM) + void GenerateStatistics( CLR_UINT32& totalSize, CLR_UINT32& inUse ); + #endif + + void Flush(); + + //--// + + #undef DECL_POSTFIX + #if defined(NANOCLR_TRACE_PERSISTENCE) + #define DECL_POSTFIX + #else + #define DECL_POSTFIX {} + #endif + + static void Trace_Emit( char* szText ) DECL_POSTFIX; + + static void Trace_Printf( const char* format, ... ) DECL_POSTFIX; + + static void Trace_DumpIdentity( char*& szBuffer, size_t& iBuffer, CLR_RT_HeapBlock_WeakReference_Identity* identity ) DECL_POSTFIX; + + static void Trace_DumpState( const char* szText, FLASH_WORD* dst, ObjectHeader* oh, CLR_RT_HeapBlock_WeakReference* wr ) DECL_POSTFIX; + + //--// + + private: + + bool AdvanceState( bool force ); + + void EnqueueNextCallback(); +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +extern CLR_RT_Persistence_Manager g_CLR_RT_Persistence_Manager; + +//--// + + +struct CLR_RT_ApplicationInterrupt; + +//--// + +//struct GPIO_PortParams +//{ +// GPIO_INT_EDGE m_interruptMode; +// GPIO_RESISTOR m_resistorMode; +// bool m_glitchFilterEnable; +// bool m_initialState; +// bool m_initialDirectionOutput; +// +// //--// +// +// static const CLR_UINT8 c_Input = 0x01; // GPIO_ATTRIBUTE_INPUT +// static const CLR_UINT8 c_Output = 0x02; // GPIO_ATTRIBUTE_OUTPUT +// static const CLR_UINT8 c_AlternateA = 0x04; // GPIO_ATTRIBUTE_ALTERNATE_A +// static const CLR_UINT8 c_AlternateB = 0x08; // GPIO_ATTRIBUTE_ALTERNATE_B +// +// static const CLR_UINT8 c_InterruptDisabled = 0x10; +// static const CLR_UINT8 c_Disposed = 0x20; +//}; + + +struct CLR_RT_HeapBlock_NativeEventDispatcher : public CLR_RT_ObjectToEvent_Destination // EVENT HEAP - NO RELOCATION - +{ + static void HandlerMethod_Initialize (); + static void HandlerMethod_RecoverFromGC (); + static void HandlerMethod_CleanUp (); + + static CLR_RT_DblLinkedList eventList; + + + struct InterruptPortInterrupt + { + CLR_INT64 time; + CLR_RT_HeapBlock_NativeEventDispatcher* context; + CLR_UINT32 data1; + CLR_UINT32 data2; + CLR_UINT32 data3; + }; + + // Pointer to Hardware driver methods + CLR_RT_DriverInterruptMethods *driverMethods; + //--// + // Pointer to custom data used by device drivers. + void *pDrvCustomData; + + + + //--// + + static HRESULT CreateInstance ( CLR_RT_HeapBlock& owner, CLR_RT_HeapBlock& portRef ); + static HRESULT ExtractInstance( CLR_RT_HeapBlock& ref, CLR_RT_HeapBlock_NativeEventDispatcher*& port ); + + HRESULT StartDispatch ( CLR_RT_ApplicationInterrupt* interrupt, CLR_RT_Thread* th ); + HRESULT RecoverManagedObject( CLR_RT_HeapBlock*& port ); + + static void ThreadTerminationCallback( void* arg ); + void SaveToHALQueue( uint32_t data1, uint32_t data2 ); + void RemoveFromHALQueue(); + + void RecoverFromGC (); + bool ReleaseWhenDeadEx(); +}; + +//--// + +struct CLR_RT_ApplicationInterrupt : public CLR_RT_HeapBlock_Node +{ + CLR_RT_HeapBlock_NativeEventDispatcher ::InterruptPortInterrupt m_interruptPortInterrupt; +}; + +//--// + +#define Library_corlib_native_System_Collections_ArrayList__FIELD___items 1 +#define Library_corlib_native_System_Collections_ArrayList__FIELD___size 2 + +struct CLR_RT_HeapBlock_ArrayList : public CLR_RT_HeapBlock +{ +public: + HRESULT GetItem( CLR_INT32 index, CLR_RT_HeapBlock*& value ); + HRESULT SetItem( CLR_INT32 index, CLR_RT_HeapBlock* value ); + + HRESULT Add( CLR_RT_HeapBlock* value, CLR_INT32& index ); + HRESULT Clear(); + HRESULT Insert( CLR_INT32 index, CLR_RT_HeapBlock* value ); + HRESULT RemoveAt( CLR_INT32 index ); + HRESULT SetCapacity( CLR_UINT32 newCapacity ); + + //--// + + __inline CLR_INT32 GetSize() { return ((CLR_RT_HeapBlock*)this)[ Library_corlib_native_System_Collections_ArrayList__FIELD___size ].NumericByRef().s4; } + +private: + + // Keep in-sync with _defaultCapacity in System.Collections.ArrayList class in ArrayList.cs + static const CLR_INT32 c_DefaultCapacity = 4; + + HRESULT EnsureCapacity( CLR_INT32 min, CLR_INT32 currentCapacity ); + + __inline CLR_RT_HeapBlock_Array* GetItems() { return ((CLR_RT_HeapBlock*)this)[ Library_corlib_native_System_Collections_ArrayList__FIELD___items ].DereferenceArray(); } + + __inline void SetItems( CLR_RT_HeapBlock_Array* items ) { ((CLR_RT_HeapBlock*)this)[ Library_corlib_native_System_Collections_ArrayList__FIELD___items ].SetObjectReference( items ); } + __inline void SetSize ( CLR_INT32 size ) { ((CLR_RT_HeapBlock*)this)[ Library_corlib_native_System_Collections_ArrayList__FIELD___size ].SetInteger ( size ); } +}; + +#if (NANOCLR_SYSTEM_COLLECTIONS == TRUE) + +#define Library_nf_system_collections_System_Collections_Queue__FIELD___array 1 +#define Library_nf_system_collections_System_Collections_Queue__FIELD___head 2 +#define Library_nf_system_collections_System_Collections_Queue__FIELD___tail 3 +#define Library_nf_system_collections_System_Collections_Queue__FIELD___size 4 + +struct CLR_RT_HeapBlock_Queue : public CLR_RT_HeapBlock +{ +public: + HRESULT Dequeue( CLR_RT_HeapBlock*& value ); + HRESULT Enqueue( CLR_RT_HeapBlock* value ); + + HRESULT Peek( CLR_RT_HeapBlock*& value ); + HRESULT Clear(); + + HRESULT CopyTo( CLR_RT_HeapBlock_Array* toArray, CLR_INT32 index ); + + //--// + + __inline CLR_INT32 GetSize() { return ((CLR_RT_HeapBlock*)this)[ Library_nf_system_collections_System_Collections_Queue__FIELD___size ].NumericByRef().s4; } + +private: + + // Keep in-sync with _defaultCapacity in System.Collections.Queue class in Queue.cs + static const CLR_INT32 c_DefaultCapacity = 4; + + static HRESULT ObjArrayMemcpy( CLR_RT_HeapBlock_Array* arraySrc, int indexSrc, CLR_RT_HeapBlock_Array* arrayDst, int indexDst, int length ); + + __inline CLR_RT_HeapBlock_Array* GetArray() { return ((CLR_RT_HeapBlock*)this)[ Library_nf_system_collections_System_Collections_Queue__FIELD___array ].DereferenceArray(); } + __inline CLR_INT32 Head () { return ((CLR_RT_HeapBlock*)this)[ Library_nf_system_collections_System_Collections_Queue__FIELD___head ].NumericByRef().s4; } + __inline CLR_INT32 GetTail () { return ((CLR_RT_HeapBlock*)this)[ Library_nf_system_collections_System_Collections_Queue__FIELD___tail ].NumericByRef().s4; } + + __inline void SetArray( CLR_RT_HeapBlock_Array* array ) { ((CLR_RT_HeapBlock*)this)[ Library_nf_system_collections_System_Collections_Queue__FIELD___array ].SetObjectReference( array ); } + __inline void SetHead ( CLR_INT32 head ) { ((CLR_RT_HeapBlock*)this)[ Library_nf_system_collections_System_Collections_Queue__FIELD___head ].SetInteger ( head ); } + __inline void SetTail ( CLR_INT32 tail ) { ((CLR_RT_HeapBlock*)this)[ Library_nf_system_collections_System_Collections_Queue__FIELD___tail ].SetInteger ( tail ); } + __inline void SetSize ( CLR_INT32 size ) { ((CLR_RT_HeapBlock*)this)[ Library_nf_system_collections_System_Collections_Queue__FIELD___size ].SetInteger ( size ); } +}; + + +#define Library_nf_system_collections_System_Collections_Stack__FIELD___array 1 +#define Library_nf_system_collections_System_Collections_Stack__FIELD___size 2 + +struct CLR_RT_HeapBlock_Stack : public CLR_RT_HeapBlock +{ +public: + HRESULT Pop( CLR_RT_HeapBlock*& value ); + HRESULT Push( CLR_RT_HeapBlock* value ); + + HRESULT Peek( CLR_RT_HeapBlock*& value ); + HRESULT Clear(); + + //--// + + __inline CLR_INT32 GetSize() { return ((CLR_RT_HeapBlock*)this)[ Library_nf_system_collections_System_Collections_Stack__FIELD___size ].NumericByRef().s4; } + +protected: + + // Keep in-sync with _defaultCapacity in System.Collections.Stack class in Stack.cs + static const CLR_INT32 c_DefaultCapacity = 4; + + __inline CLR_RT_HeapBlock_Array* GetArray() { return ((CLR_RT_HeapBlock*)this)[ Library_nf_system_collections_System_Collections_Stack__FIELD___array ].DereferenceArray(); } + + __inline void SetArray( CLR_RT_HeapBlock_Array* array ) { ((CLR_RT_HeapBlock*)this)[ Library_nf_system_collections_System_Collections_Stack__FIELD___array ].SetObjectReference( array ); } + __inline void SetSize ( CLR_INT32 size ) { ((CLR_RT_HeapBlock*)this)[ Library_nf_system_collections_System_Collections_Stack__FIELD___size ].SetInteger ( size ); } +}; + +#endif // (NANOCLR_SYSTEM_COLLECTIONS == TRUE) + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#endif // _NANOCLR_RUNTIME__HEAPBLOCK_H_ + diff --git a/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Runtime__Serialization.h b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Runtime__Serialization.h new file mode 100644 index 00000000..32fd47d5 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Runtime__Serialization.h @@ -0,0 +1,285 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _NANOCLR_RUNTIME__SERIALIZATION_H_ +#define _NANOCLR_RUNTIME__SERIALIZATION_H_ + +struct CLR_RT_BinaryFormatter : public CLR_RT_HeapBlock_Node // EVENT HEAP - NO RELOCATION - +{ + ////////////////////////////////////////////////////////////////// + // + // Keep in sync with definitions in Reflection.cs!!!! + // Keep in sync with definitions in Reflection.cs!!!! + // Keep in sync with definitions in Reflection.cs!!!! + // + static const int TE_L1 = 2; + static const CLR_UINT32 TE_L1_Null = 0x00000000; + static const CLR_UINT32 TE_L1_Duplicate = 0x00000001; // N bits for the duplicate id. + static const CLR_UINT32 TE_L1_Reference = 0x00000002; // 32 bits for the type. + static const CLR_UINT32 TE_L1_Other = 0x00000003; + + static const int TE_L2 = 2; + static const CLR_UINT32 TE_L2_Primitive = 0x00000000; // 4 bits for the type. + static const CLR_UINT32 TE_L2_Array = 0x00000001; + static const CLR_UINT32 TE_L2_ArrayList = 0x00000002; + static const CLR_UINT32 TE_L2_Other = 0x00000003; + + static const int TE_L3 = 4; + static const CLR_UINT32 TE_L3_Type = 0x00000000; // 32 bits for the type. + static const CLR_UINT32 TE_L3_Reflection = 0x00000001; // CLR_RT_ReflectionDef_Index. Valid in marshaling only. + static const CLR_UINT32 TE_L3_MBRO = 0x00000002; // 32 bits for the pointer to the MBRO class, 32 bits for the pointer to the AppDomain + + static const int TE_ElementType = 4; + static const int TE_ArrayDepth = 4; + + static const CLR_UINT32 c_Flags_None = 0x00000000; + static const CLR_UINT32 c_Flags_Marshal = 0x00000001; + + // + //--// + // + enum SerializationFlags + { + SF_Encrypted = 0x00000001, + SF_Compressed = 0x00000002, // Value uses range compression (max 2^30 values). + SF_Optional = 0x00000004, // If the value cannot be deserialized, skip it. + + SF_PointerNeverNull = 0x00000010, + SF_ElementsNeverNull = 0x00000020, + + SF_FixedType = 0x00000100, + }; + // + struct SerializationHintsAttribute + { + SerializationFlags m_flags; + + int m_arraySize; // -1 == extend to the end of the stream. + + int m_bitPacked; // In bits. + CLR_INT64 m_rangeBias; + CLR_UINT64 m_scale; // For time, it's in ticks. + }; + // + ////////////////////////////////////////////////////////////////// + + struct TypeHandler + { + // + // Type of signatures: + // + // 1) NULL + // + // Invalid for NeverNull + // + // 2) DUPLICATE + // + // Invalid for Sealed/FixedType + NeverNull + // + // 3) PRIMITIVE + // + // optional for FixedType + // PRIMITIVE optional for FixedType + NeverNull + // + // 4) REFERENCE + // + // optional for Sealed/FixedType + // REFERENCE optional for Sealed/FixedType + NeverNull + // + // 5) ARRAYLIST + // + // optional for FixedSize + // ARRAYLIST optional for FixedType + NeverNull + // + // 6) ARRAY + // + // optional for FixedSize + // optional for FixedType + // ARRAY optional for FixedType + NeverNull + // + // 7) REFLECTION + // + // only valid for marshaling + // + // 8) MBRO + // pointer to the DATATYPE_CLASS of the MarshalByRefObject on the object heap + // It is the responsibility of the caller (CLR_RT_AppDomain::MarshalObject) to ensure that + // this pointer is kept alive, and not moved during the marshaling process + // pointer to the AppDomain that this MBRO object lives in. + // It is the responsiblity of the caller (CLR_RT_AppDomain::MarshalObject) to ensure that + // the AppDomain does not get unloaded during the marshaling process. + // + + // Always match type if FixedTyped is specified. + // + static const int c_Signature_Header = 0x01; + static const int c_Signature_Type = 0x02; + static const int c_Signature_Length = 0x04; + + static const int c_Action_None = 0; + static const int c_Action_ObjectData = 1; + static const int c_Action_ObjectFields = 2; + static const int c_Action_ObjectElements = 3; + + //--// + + CLR_RT_HeapBlock* m_value; + SerializationHintsAttribute m_hints; + CLR_RT_TypeDescriptor* m_type; + + CLR_RT_TypeDescriptor* m_typeExpected; + CLR_RT_TypeDescriptor* m_typeForced; + + CLR_RT_BinaryFormatter* m_bf; + + CLR_RT_HeapBlock m_value_tmp; + CLR_RT_TypeDescriptor m_type_tmp; + CLR_RT_TypeDescriptor m_typeExpected_tmp; + CLR_RT_TypeDescriptor m_typeForced_tmp; + +#if defined(NANOCLR_APPDOMAINS) + bool m_fIsMarshalByRefObject; +#endif + + //--// + + HRESULT TypeHandler_Initialize( CLR_RT_BinaryFormatter* bf, SerializationHintsAttribute* hints, CLR_RT_TypeDescriptor* expected ); + + HRESULT SetValue( CLR_RT_HeapBlock* v ); + + //--// + + int SignatureRequirements(); + + bool CompareTypes( CLR_RT_TypeDescriptor* left, CLR_RT_TypeDescriptor* right ); + + static CLR_DataType GetDataType ( CLR_RT_TypeDescriptor* type ); + static CLR_UINT32 GetSizeOfType( CLR_RT_TypeDescriptor* type ); + static bool GetSignOfType( CLR_RT_TypeDescriptor* type ); + + static CLR_RT_HeapBlock* FixDereference( CLR_RT_HeapBlock* v ); + static CLR_RT_HeapBlock* FixNull ( CLR_RT_HeapBlock* v ); + + //--// + + HRESULT EmitSignature ( int& res ); + HRESULT EmitSignature_Inner( int mask, CLR_RT_TypeDescriptor* type, CLR_RT_HeapBlock* value ); + HRESULT ReadSignature ( int& res ); + HRESULT EmitValue ( int& res ); + HRESULT ReadValue ( int& res ); + + HRESULT TrackObject ( int& res ); + }; + + struct State : public CLR_RT_HeapBlock_Node // EVENT HEAP - NO RELOCATION - + { + CLR_RT_BinaryFormatter* m_parent; + + bool m_value_NeedProcessing; + TypeHandler m_value; + + bool m_fields_NeedProcessing; + CLR_RT_TypeDef_Instance m_fields_CurrentClass; + int m_fields_CurrentField; + CLR_RT_HeapBlock* m_fields_Pointer; + + bool m_array_NeedProcessing; + CLR_RT_TypeDescriptor* m_array_ExpectedType; + CLR_RT_TypeDescriptor m_array_ExpectedType_Tmp; + CLR_RT_HeapBlock_Array* m_array; + int m_array_CurrentPos; + int m_array_LastPos; + + //--// + + static HRESULT CreateInstance( CLR_RT_BinaryFormatter* parent, SerializationHintsAttribute* hints, CLR_RT_HeapBlock* type ); + static HRESULT CreateInstance( CLR_RT_BinaryFormatter* parent, SerializationHintsAttribute* hints, CLR_RT_TypeDescriptor* type ); + + void DestroyInstance(); + + HRESULT FindHints( SerializationHintsAttribute& hints, const CLR_RT_TypeDef_Instance& cls ); + HRESULT FindHints( SerializationHintsAttribute& hints, const CLR_RT_FieldDef_Instance& fld ); + + //--// + + HRESULT AssignAndFixBoxing( CLR_RT_HeapBlock& dst ); + + HRESULT GetValue (); + HRESULT SetValueAndDestroyInstance(); + + //--// + + HRESULT Advance (); + HRESULT AdvanceToTheNextField (); + HRESULT AdvanceToTheNextElement(); + }; + + + struct DuplicateTracker : public CLR_RT_HeapBlock_Node // EVENT HEAP - NO RELOCATION - + { + CLR_RT_HeapBlock* m_ptr; + CLR_UINT32 m_idx; + }; + + //--// + + CLR_RT_HeapBlock_MemoryStream* m_stream; + CLR_UINT32 m_idx; + CLR_UINT32 m_lastTypeRead; + CLR_RT_DblLinkedList m_duplicates; // EVENT HEAP - NO RELOCATION - list of CLR_RT_BinaryFormatter::DuplicateTracker + CLR_RT_DblLinkedList m_states; // EVENT HEAP - NO RELOCATION - list of CLR_RT_BinaryFormatter::State + + bool m_fDeserialize; + CLR_RT_HeapBlock m_value; + CLR_RT_TypeDescriptor m_value_desc; + + CLR_UINT32 m_flags; + + //--// + + static bool SerializationEnabled(); + + static HRESULT CreateInstance( CLR_UINT8* buf, int len, CLR_RT_BinaryFormatter*& res ); + + void DestroyInstance(); + HRESULT Advance (); + + static HRESULT Serialize ( CLR_RT_HeapBlock& refData, CLR_RT_HeapBlock& object , CLR_RT_HeapBlock* cls , CLR_UINT32 flags ); + static HRESULT Deserialize( CLR_RT_HeapBlock& refData, CLR_RT_HeapBlock& object , CLR_RT_HeapBlock* cls, CLR_UINT32* unknownType, CLR_UINT32 flags ); + static HRESULT Deserialize( CLR_RT_HeapBlock& refData, CLR_UINT8* data, CLR_UINT32 size, CLR_RT_HeapBlock* cls, CLR_UINT32* unknownType, CLR_UINT32 flags ); + + HRESULT TrackDuplicate ( CLR_RT_HeapBlock* object ); + CLR_UINT32 SearchDuplicate( CLR_RT_HeapBlock* object ); + CLR_RT_HeapBlock* GetDuplicate ( CLR_UINT32 idx ); + + //--// + + int BitsAvailable ( ); + + HRESULT ReadBits ( CLR_UINT32& val, int bits ); + HRESULT WriteBits ( CLR_UINT32 val, int bits ); + + HRESULT ReadBits ( CLR_UINT64& val, int bits ); + HRESULT WriteBits ( CLR_UINT64 val, int bits ); + + HRESULT ReadArray ( CLR_UINT8* buf, int bytes ); + HRESULT WriteArray ( const CLR_UINT8* buf, int bytes ); + + HRESULT ReadCompressedUnsigned ( CLR_UINT32& val ); + HRESULT WriteCompressedUnsigned( CLR_UINT32 val ); + + HRESULT ReadType ( CLR_RT_ReflectionDef_Index& val ); + HRESULT WriteType ( const CLR_RT_ReflectionDef_Index& val ); + HRESULT WriteType ( CLR_UINT32 val ); + + //--// + +private: + + static void PrepareForGC( void* data ); +}; + +#endif // _NANOCLR_RUNTIME__SERIALIZATION_H_ + diff --git a/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Types.h b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Types.h new file mode 100644 index 00000000..bae4648d --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Types.h @@ -0,0 +1,1148 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _NANOCLR_TYPES_H_ +#define _NANOCLR_TYPES_H_ + +#include + +/////////////////////////////////////////////////////////////////////////////////////////////////// + +#define FAULT_ON_NULL_HR(ptr,hr) if(!(ptr) ) NANOCLR_SET_AND_LEAVE((hr) ) +#define CHECK_ALLOCATION(ptr) if(!(ptr) ) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY) +#define CHECK_SIZE_RANGE(len) if( len > CLR_RT_HeapBlock::HB_MaxSize) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE ) + +#define FIMPLIES(x,y) ((!(x)) || (y)) +#define FINRANGE(val,lo,hi) (((val) >= (lo)) && ((val) <= (hi))) + +/////////////////////////////////////////////////////////////////////////////////////////////////// + +#define NANOCLR_INTEROP_STUB_RETURN(stack) return stack.NotImplementedStub() +#define NANOCLR_SYSTEM_STUB_RETURN() return S_OK +#define NANOCLR_FEATURE_STUB_RETURN() return CLR_E_NOTIMPL + +////////////////////////////////////////////////// + +#define NANOCLR_PARAMCHECK_BEGIN() \ +{ \ + HRESULT hrInner = S_OK; + +#define NANOCLR_PARAMCHECK_POINTER(ptr) \ + { \ + if(ptr == NULL) \ + { \ + hrInner = CLR_E_NULL_REFERENCE; \ + } \ + } + +#define NANOCLR_PARAMCHECK_POINTER_AND_SET(ptr,val) \ + { \ + if(ptr == NULL) \ + { \ + hrInner = CLR_E_NULL_REFERENCE; \ + } \ + else \ + { \ + *ptr = val; \ + } \ + } + +#define NANOCLR_PARAMCHECK_NOTNULL(ptr) \ + { \ + if(ptr == NULL) \ + { \ + hrInner = CLR_E_INVALID_PARAMETER; \ + } \ + } + +#define NANOCLR_PARAMCHECK_STRING_NOT_EMPTY(ptr) \ + { \ + if(ptr == NULL || ptr[ 0 ] == 0) \ + { \ + hrInner = CLR_E_INVALID_PARAMETER; \ + } \ + } + +#define NANOCLR_PARAMCHECK_END() \ + { NANOCLR_CHECK_HRESULT(hrInner); } \ +} + + +/////////////////////////////////////////////////////////////////////////////////////////////////// + +#if defined(_MSC_VER) +#pragma pack(push, NANOCLR_TYPES_H, 4) +#endif + +enum CLR_OPCODE +{ +#define OPDEF(c,s,pop,push,args,type,l,s1,s2,ctrl) c, +#include "opcode.def" +#undef OPDEF +CEE_COUNT, /* number of instructions and macros pre-defined */ +}; + +#if defined (__GNUC__) +#define __int64 long long +#endif + +typedef unsigned char CLR_UINT8; +typedef unsigned short CLR_UINT16; +typedef unsigned int CLR_UINT32; +typedef unsigned __int64 CLR_UINT64; +typedef signed char CLR_INT8; +typedef signed short CLR_INT16; +typedef signed int CLR_INT32; +typedef signed __int64 CLR_INT64; + +typedef CLR_UINT16 CLR_OFFSET; +typedef CLR_UINT32 CLR_OFFSET_LONG; +typedef CLR_UINT16 CLR_IDX; +typedef CLR_UINT16 CLR_STRING; +typedef CLR_UINT16 CLR_SIG; +typedef const CLR_UINT8* CLR_PMETADATA; + + +//--// +//may need to change later +typedef CLR_INT64 CLR_INT64_TEMP_CAST; +typedef CLR_UINT64 CLR_UINT64_TEMP_CAST; + +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) +typedef double CLR_DOUBLE_TEMP_CAST; +#else +typedef CLR_INT64 CLR_DOUBLE_TEMP_CAST; +#endif + +#define CLR_SIG_INVALID 0xFFFF + +enum CLR_LOGICAL_OPCODE +{ + LO_Not = 0x00, + LO_And = 0x01, + LO_Or = 0x02, + LO_Xor = 0x03, + LO_Shl = 0x04, + LO_Shr = 0x05, + + LO_Neg = 0x06, + LO_Add = 0x07, + LO_Sub = 0x08, + LO_Mul = 0x09, + LO_Div = 0x0A, + LO_Rem = 0x0B, + + LO_Box = 0x0C, + LO_Unbox = 0x0D, + + LO_Branch = 0x0E, + LO_Set = 0x0F, + LO_Switch = 0x10, + + LO_LoadFunction = 0x11, + LO_LoadVirtFunction = 0x12, + + LO_Call = 0x13, + LO_CallVirt = 0x14, + LO_Ret = 0x15, + + LO_NewObject = 0x16, + LO_CastClass = 0x17, + LO_IsInst = 0x18, + + LO_Dup = 0x19, + LO_Pop = 0x1A, + + LO_Throw = 0x1B, + LO_Rethrow = 0x1C, + LO_Leave = 0x1D, + LO_EndFinally = 0x1E, + + LO_Convert = 0x1F, + + LO_StoreArgument = 0x20, + LO_LoadArgument = 0x21, + LO_LoadArgumentAddress = 0x22, + + LO_StoreLocal = 0x23, + LO_LoadLocal = 0x24, + LO_LoadLocalAddress = 0x25, + + LO_LoadConstant_I4 = 0x26, + LO_LoadConstant_I8 = 0x27, + LO_LoadConstant_R4 = 0x28, + LO_LoadConstant_R8 = 0x29, + + LO_LoadNull = 0x2A, + LO_LoadString = 0x2B, + LO_LoadToken = 0x2C, + + LO_NewArray = 0x2D, + LO_LoadLength = 0x2E, + + LO_StoreElement = 0x2F, + LO_LoadElement = 0x30, + LO_LoadElementAddress = 0x31, + + LO_StoreField = 0x32, + LO_LoadField = 0x33, + LO_LoadFieldAddress = 0x34, + + LO_StoreStaticField = 0x35, + LO_LoadStaticField = 0x36, + LO_LoadStaticFieldAddress = 0x37, + + LO_StoreIndirect = 0x38, + LO_LoadIndirect = 0x39, + + LO_InitObject = 0x3A, + LO_LoadObject = 0x3B, + LO_CopyObject = 0x3C, + LO_StoreObject = 0x3D, + + LO_Nop = 0x3E, + + LO_EndFilter = 0x3F, + + LO_Unsupported = 0x40, + + LO_FIRST = LO_Not, + LO_LAST = LO_EndFilter, +}; + +/////////////////////////////////////////////////////////////////////////////////////////////////// + +static const CLR_IDX CLR_EmptyIndex = 0xFFFF; +static const CLR_UINT32 CLR_EmptyToken = 0xFFFFFFFF; +static const size_t CLR_MaxStreamSize_AssemblyRef = 0x0000FFFF; +static const size_t CLR_MaxStreamSize_TypeRef = 0x0000FFFF; +static const size_t CLR_MaxStreamSize_FieldRef = 0x0000FFFF; +static const size_t CLR_MaxStreamSize_MethodRef = 0x0000FFFF; +static const size_t CLR_MaxStreamSize_TypeDef = 0x0000FFFF; +static const size_t CLR_MaxStreamSize_FieldDef = 0x0000FFFF; +static const size_t CLR_MaxStreamSize_MethodDef = 0x0000FFFF; +static const size_t CLR_MaxStreamSize_Attributes = 0x0000FFFF; +static const size_t CLR_MaxStreamSize_TypeSpec = 0x0000FFFF; +static const size_t CLR_MaxStreamSize_Resources = 0x0000FFFF; +static const size_t CLR_MaxStreamSize_ResourcesData = 0xFFFFFFFF; +static const size_t CLR_MaxStreamSize_Strings = 0x0000FFFF; +static const size_t CLR_MaxStreamSize_Signatures = 0x0000FFFF; +static const size_t CLR_MaxStreamSize_ByteCode = 0x0000FFFF; +static const size_t CLR_MaxStreamSize_ResourcesFiles = 0x0000FFFF; + +enum CLR_OpcodeParam +{ + CLR_OpcodeParam_Field = 0, + CLR_OpcodeParam_Method = 1, + CLR_OpcodeParam_Type = 2, + CLR_OpcodeParam_String = 3, + CLR_OpcodeParam_Tok = 4, + CLR_OpcodeParam_Sig = 5, + CLR_OpcodeParam_BrTarget = 6, + CLR_OpcodeParam_ShortBrTarget = 7, + CLR_OpcodeParam_I = 8, + CLR_OpcodeParam_I8 = 9, + CLR_OpcodeParam_None = 10, + CLR_OpcodeParam_R = 11, + CLR_OpcodeParam_Switch = 12, + CLR_OpcodeParam_Var = 13, + CLR_OpcodeParam_ShortI = 14, + CLR_OpcodeParam_ShortR = 15, + CLR_OpcodeParam_ShortVar = 16, +}; + +#define CanCompressOpParamToken(opParam) (opParam >= CLR_OpcodeParam_Field && opParam <= CLR_OpcodeParam_String) +#define IsOpParamToken(opParam) (opParam >= CLR_OpcodeParam_Field && opParam <= CLR_OpcodeParam_Sig) + +//--// + +enum CLR_FlowControl +{ + CLR_FlowControl_NEXT = 0, + CLR_FlowControl_CALL = 1, + CLR_FlowControl_RETURN = 2, + CLR_FlowControl_BRANCH = 3, + CLR_FlowControl_COND_BRANCH = 4, + CLR_FlowControl_THROW = 5, + CLR_FlowControl_BREAK = 6, + CLR_FlowControl_META = 7, +}; + +//--// + +#define c_CLR_StringTable_Version 1 + +/////////////////////////////////////////////////////////////////////////////////////////////////// + +enum CLR_TABLESENUM +{ + TBL_AssemblyRef = 0x00000000, + TBL_TypeRef = 0x00000001, + TBL_FieldRef = 0x00000002, + TBL_MethodRef = 0x00000003, + TBL_TypeDef = 0x00000004, + TBL_FieldDef = 0x00000005, + TBL_MethodDef = 0x00000006, + TBL_Attributes = 0x00000007, + TBL_TypeSpec = 0x00000008, + TBL_Resources = 0x00000009, + TBL_ResourcesData = 0x0000000A, + TBL_Strings = 0x0000000B, + TBL_Signatures = 0x0000000C, + TBL_ByteCode = 0x0000000D, + TBL_ResourcesFiles = 0x0000000E, + TBL_EndOfAssembly = 0x0000000F, + TBL_Max = 0x00000010, +}; + +enum CLR_CorCallingConvention +{ + ///////////////////////////////////////////////////////////////////////////////////////////// + // + // This is based on CorCallingConvention. + // + PIMAGE_CEE_CS_CALLCONV_DEFAULT = 0x0, + + PIMAGE_CEE_CS_CALLCONV_VARARG = 0x5, + PIMAGE_CEE_CS_CALLCONV_FIELD = 0x6, + PIMAGE_CEE_CS_CALLCONV_LOCAL_SIG = 0x7, + PIMAGE_CEE_CS_CALLCONV_PROPERTY = 0x8, + PIMAGE_CEE_CS_CALLCONV_UNMGD = 0x9, + PIMAGE_CEE_CS_CALLCONV_GENERICINST = 0xa, // generic method instantiation + PIMAGE_CEE_CS_CALLCONV_NATIVEVARARG = 0xb, // used ONLY for 64bit vararg PInvoke calls + PIMAGE_CEE_CS_CALLCONV_MAX = 0xc, // first invalid calling convention + + // The high bits of the calling convention convey additional info + PIMAGE_CEE_CS_CALLCONV_MASK = 0x0f, // Calling convention is bottom 4 bits + PIMAGE_CEE_CS_CALLCONV_HASTHIS = 0x20, // Top bit indicates a 'this' parameter + PIMAGE_CEE_CS_CALLCONV_EXPLICITTHIS = 0x40, // This parameter is explicitly in the signature + PIMAGE_CEE_CS_CALLCONV_GENERIC = 0x10, // Generic method sig with explicit number of type arguments (precedes ordinary parameter count) + // + // End of overlap with CorCallingConvention. + // + ///////////////////////////////////////////////////////////////////////////////////////////// +}; + +enum CLR_DataType // KEEP IN SYNC WITH Microsoft.SPOT.DataType!! +{ + DATATYPE_VOID , // 0 bytes + + DATATYPE_BOOLEAN , // 1 byte + DATATYPE_I1 , // 1 byte + DATATYPE_U1 , // 1 byte + + DATATYPE_CHAR , // 2 bytes + DATATYPE_I2 , // 2 bytes + DATATYPE_U2 , // 2 bytes + + DATATYPE_I4 , // 4 bytes + DATATYPE_U4 , // 4 bytes + DATATYPE_R4 , // 4 bytes + + DATATYPE_I8 , // 8 bytes + DATATYPE_U8 , // 8 bytes + DATATYPE_R8 , // 8 bytes + DATATYPE_DATETIME , // 8 bytes // Shortcut for System.DateTime + DATATYPE_TIMESPAN , // 8 bytes // Shortcut for System.TimeSpan + DATATYPE_STRING , + + DATATYPE_LAST_NONPOINTER = DATATYPE_TIMESPAN, // This is the last type that doesn't need to be relocated. + DATATYPE_LAST_PRIMITIVE_TO_PRESERVE = DATATYPE_R8 , // All the above types don't need fix-up on assignment. +#if defined(NANOCLR_NO_ASSEMBLY_STRINGS) + DATATYPE_LAST_PRIMITIVE_TO_MARSHAL = DATATYPE_STRING, // All the above types can be marshaled by assignment. +#else + DATATYPE_LAST_PRIMITIVE_TO_MARSHAL = DATATYPE_TIMESPAN, // All the above types can be marshaled by assignment. +#endif + DATATYPE_LAST_PRIMITIVE = DATATYPE_STRING , // All the above types don't need fix-up on assignment. + + DATATYPE_OBJECT , // Shortcut for System.Object + DATATYPE_CLASS , // CLASS + DATATYPE_VALUETYPE , // VALUETYPE + DATATYPE_SZARRAY , // Shortcut for single dimension zero lower bound array SZARRAY + DATATYPE_BYREF , // BYREF + + //////////////////////////////////////// + + DATATYPE_FREEBLOCK , + DATATYPE_CACHEDBLOCK , + DATATYPE_ASSEMBLY , + DATATYPE_WEAKCLASS , + DATATYPE_REFLECTION , + DATATYPE_ARRAY_BYREF , + DATATYPE_DELEGATE_HEAD , + DATATYPE_DELEGATELIST_HEAD , + DATATYPE_OBJECT_TO_EVENT , + DATATYPE_BINARY_BLOB_HEAD , + + DATATYPE_THREAD , + DATATYPE_SUBTHREAD , + DATATYPE_STACK_FRAME , + DATATYPE_TIMER_HEAD , + DATATYPE_LOCK_HEAD , + DATATYPE_LOCK_OWNER_HEAD , + DATATYPE_LOCK_REQUEST_HEAD , + DATATYPE_WAIT_FOR_OBJECT_HEAD , + DATATYPE_FINALIZER_HEAD , + DATATYPE_MEMORY_STREAM_HEAD , // SubDataType? + DATATYPE_MEMORY_STREAM_DATA , // SubDataType? + + DATATYPE_SERIALIZER_HEAD , // SubDataType? + DATATYPE_SERIALIZER_DUPLICATE , // SubDataType? + DATATYPE_SERIALIZER_STATE , // SubDataType? + + DATATYPE_ENDPOINT_HEAD , + + //These constants are shared by Debugger.dll, and cannot be conditionally compiled away. + //This adds a couple extra bytes to the lookup table. But frankly, the lookup table should probably + //be shrunk to begin with. Most of the datatypes are used just to tag memory. + //For those datatypes, perhaps we should use a subDataType instead (probably what the comments above are about). + + DATATYPE_RADIO_LAST = DATATYPE_ENDPOINT_HEAD + 3, + + DATATYPE_IO_PORT , + DATATYPE_IO_PORT_LAST = DATATYPE_RADIO_LAST + 1, + + DATATYPE_VTU_PORT_LAST = DATATYPE_IO_PORT_LAST + 1, + +#if defined(NANOCLR_APPDOMAINS) + DATATYPE_APPDOMAIN_HEAD , + DATATYPE_TRANSPARENT_PROXY , + DATATYPE_APPDOMAIN_ASSEMBLY , +#endif + DATATYPE_APPDOMAIN_LAST = DATATYPE_VTU_PORT_LAST + 3, + + DATATYPE_FIRST_INVALID , + + // Type modifies. This is exact copy of VALUES ELEMENT_TYPE_* from CorHdr.h + // + + DATATYPE_TYPE_MODIFIER = 0x40, + DATATYPE_TYPE_SENTINEL = 0x01 | DATATYPE_TYPE_MODIFIER, // sentinel for varargs + DATATYPE_TYPE_PINNED = 0x05 | DATATYPE_TYPE_MODIFIER, + DATATYPE_TYPE_R4_HFA = 0x06 | DATATYPE_TYPE_MODIFIER, // used only internally for R4 HFA types + DATATYPE_TYPE_R8_HFA = 0x07 | DATATYPE_TYPE_MODIFIER, // used only internally for R8 HFA types +}; + +enum CLR_ReflectionType +{ + REFLECTION_INVALID = 0x00, + REFLECTION_ASSEMBLY = 0x01, + REFLECTION_TYPE = 0x02, + REFLECTION_TYPE_DELAYED = 0x03, + REFLECTION_CONSTRUCTOR = 0x04, + REFLECTION_METHOD = 0x05, + REFLECTION_FIELD = 0x06, +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +inline CLR_UINT32 CLR_DataFromTk( CLR_UINT32 tk ) { return tk & 0x00FFFFFF; } +inline CLR_TABLESENUM CLR_TypeFromTk( CLR_UINT32 tk ) { return (CLR_TABLESENUM)(tk >> 24); } +inline CLR_UINT32 CLR_TkFromType( CLR_TABLESENUM tbl, CLR_UINT32 data ) { return ((((CLR_UINT32)tbl) << 24) & 0xFF000000) | (data & 0x00FFFFFF); } +#if 0 +// Used on LE host to target BE +inline CLR_UINT32 CLR_TkFromType( CLR_TABLESENUM tbl, CLR_UINT32 data ) { return ( ((CLR_UINT32)(tbl) & 0xFF) | (data & 0xFFFFFF00)); } +inline CLR_UINT32 CLR_DataFromTk( CLR_UINT32 tk ) { return tk & 0xFFFFFF00; } +inline CLR_TABLESENUM CLR_TypeFromTk( CLR_UINT32 tk ) { return (CLR_TABLESENUM)(tk&0xFF); } +#endif +//--// + +inline CLR_UINT32 CLR_UncompressStringToken( CLR_UINT32 tk ) +{ + return CLR_TkFromType( TBL_Strings, tk ); +} + +inline CLR_UINT32 CLR_UncompressTypeToken( CLR_UINT32 tk ) +{ + static const CLR_TABLESENUM c_lookup[3] = { TBL_TypeDef, TBL_TypeRef, TBL_TypeSpec }; + return CLR_TkFromType( c_lookup[(tk >> 14) & 3], 0x3fff & tk ); +} + +inline CLR_UINT32 CLR_UncompressFieldToken( CLR_UINT32 tk ) +{ + static const CLR_TABLESENUM c_lookup[2] = { TBL_FieldDef, TBL_FieldRef }; + return CLR_TkFromType( c_lookup[(tk >> 15) & 1], 0x7fff & tk ); +} + +inline CLR_UINT32 CLR_UncompressMethodToken( CLR_UINT32 tk ) +{ + static const CLR_TABLESENUM c_lookup[ 2 ] = { TBL_MethodDef, TBL_MethodRef }; + return CLR_TkFromType( c_lookup[ (tk >> 15) & 1 ], 0x7fff & tk ); +} + +#if defined(_WIN32) + + CLR_UINT32 CLR_ReadTokenCompressed( CLR_PMETADATA& ip, CLR_OPCODE opcode ); + +#endif + +//--// + +HRESULT CLR_CompressTokenHelper( const CLR_TABLESENUM *tables, CLR_UINT16 cTables, CLR_UINT32& tk); + +inline HRESULT CLR_CompressStringToken( CLR_UINT32& tk) +{ + static const CLR_TABLESENUM c_lookup[ 1 ] = { TBL_Strings }; + + return CLR_CompressTokenHelper( c_lookup, ARRAYSIZE(c_lookup), tk ); +} + +inline HRESULT CLR_CompressTypeToken( CLR_UINT32& tk ) +{ + static const CLR_TABLESENUM c_lookup[ 3 ] = { TBL_TypeDef, TBL_TypeRef, TBL_TypeSpec }; + + return CLR_CompressTokenHelper( c_lookup, ARRAYSIZE(c_lookup), tk ); +} + +inline HRESULT CLR_CompressFieldToken( CLR_UINT32& tk ) +{ + static const CLR_TABLESENUM c_lookup[ 2 ] = { TBL_FieldDef, TBL_FieldRef }; + + return CLR_CompressTokenHelper( c_lookup, ARRAYSIZE(c_lookup), tk ); +} + +inline HRESULT CLR_CompressMethodToken( CLR_UINT32& tk ) +{ + static const CLR_TABLESENUM c_lookup[ 2 ] = { TBL_MethodDef, TBL_MethodRef }; + + return CLR_CompressTokenHelper( c_lookup, ARRAYSIZE(c_lookup), tk ); +} + +//--// + +inline bool CLR_CompressData( CLR_UINT32 val, CLR_UINT8*& p ) +{ + CLR_UINT8* ptr = p; + + if(val <= 0x7F) + { + *ptr++ = (CLR_UINT8)(val); + } + else if(val <= 0x3FFF) + { + *ptr++ = (CLR_UINT8)((val >> 8) | 0x80); + *ptr++ = (CLR_UINT8)((val ) ); + } + else if(val <= 0x1FFFFFFF) + { + *ptr++ = (CLR_UINT8)((val >> 24) | 0xC0); + *ptr++ = (CLR_UINT8)((val >> 16) ); + *ptr++ = (CLR_UINT8)((val >> 8) ); + *ptr++ = (CLR_UINT8)((val ) ); + } + else + { + return false; + } + + p = ptr; + + return true; +} + +inline CLR_UINT32 CLR_UncompressData( const CLR_UINT8*& p ) +{ + CLR_PMETADATA ptr = p; + CLR_UINT32 val = *ptr++; + // Handle smallest data inline. + if((val & 0x80) == 0x00) // 0??? ???? + { + } + else if((val & 0xC0) == 0x80) // 10?? ???? + { + val = (val & 0x3F) << 8; + val |= (CLR_UINT32)*ptr++ ; + } + else // 110? ???? + { + val = (val & 0x1F) << 24; + val |= (CLR_UINT32)*ptr++ << 16; + val |= (CLR_UINT32)*ptr++ << 8; + val |= (CLR_UINT32)*ptr++ << 0; + } +#if 0 + // Handle smallest data inline. + if((val & 0x80) == 0x00) // 0??? ???? + { + } + else if((val & 0xC0) == 0x80) // 10?? ???? + { + val = (val & 0x3F); + val |= ((CLR_UINT32)*ptr++ <<8); + } + else // 110? ???? + { + val = (val & 0x1F) ; + val |= (CLR_UINT32)*ptr++ << 8; + val |= (CLR_UINT32)*ptr++ << 16; + val |= (CLR_UINT32)*ptr++ << 24; + } + +#endif + + p = ptr; + + return val; +} + +inline CLR_DataType CLR_UncompressElementType( const CLR_UINT8*& p ) +{ + return (CLR_DataType)*p++; +} + +inline CLR_UINT32 CLR_TkFromStream( const CLR_UINT8*& p ) +{ + static const CLR_TABLESENUM c_lookup[ 4 ] = { TBL_TypeDef, TBL_TypeRef, TBL_TypeSpec, TBL_Max }; + + CLR_UINT32 data = CLR_UncompressData( p ); + + return CLR_TkFromType( c_lookup[ data & 3 ], data >> 2 ); +} + +//--//--//--// + +#if defined(__GNUC__) + +#define NANOCLR_READ_UNALIGNED_UINT8(arg,ip) arg = *(const CLR_UINT8 *)ip; ip += sizeof(CLR_UINT8 ) +template __inline void NANOCLR_READ_UNALIGNED_UINT16(T& arg, CLR_PMETADATA& ip) +{ + arg = (CLR_UINT16)(*(const CLR_UINT8 *)ip) ; ip += sizeof(CLR_UINT8); + arg |= (CLR_UINT16)(*(const CLR_UINT8 *)ip) << 8; ip += sizeof(CLR_UINT8); +} +template __inline void NANOCLR_READ_UNALIGNED_UINT32(T& arg, CLR_PMETADATA& ip) +{ + arg = (CLR_UINT32)(*(const CLR_UINT8 *)ip) ; ip += sizeof(CLR_UINT8); + arg |= (CLR_UINT32)(*(const CLR_UINT8 *)ip) << 8; ip += sizeof(CLR_UINT8); + arg |= (CLR_UINT32)(*(const CLR_UINT8 *)ip) << 16; ip += sizeof(CLR_UINT8); + arg |= (CLR_UINT32)(*(const CLR_UINT8 *)ip) << 24; ip += sizeof(CLR_UINT8); +} +template __inline void NANOCLR_READ_UNALIGNED_UINT64(T& arg, CLR_PMETADATA& ip) +{ + arg = (CLR_UINT64)(*(const CLR_UINT8 *)ip) ; ip += sizeof(CLR_UINT8); + arg |= (CLR_UINT64)(*(const CLR_UINT8 *)ip) << 8; ip += sizeof(CLR_UINT8); + arg |= (CLR_UINT64)(*(const CLR_UINT8 *)ip) << 16; ip += sizeof(CLR_UINT8); + arg |= (CLR_UINT64)(*(const CLR_UINT8 *)ip) << 24; ip += sizeof(CLR_UINT8); + arg |= (CLR_UINT64)(*(const CLR_UINT8 *)ip) << 32; ip += sizeof(CLR_UINT8); + arg |= (CLR_UINT64)(*(const CLR_UINT8 *)ip) << 40; ip += sizeof(CLR_UINT8); + arg |= (CLR_UINT64)(*(const CLR_UINT8 *)ip) << 48; ip += sizeof(CLR_UINT8); + arg |= (CLR_UINT64)(*(const CLR_UINT8 *)ip) << 56; ip += sizeof(CLR_UINT8); +} + +#define NANOCLR_READ_UNALIGNED_INT8(arg,ip) arg = *(const CLR_INT8 * )ip; ip += sizeof(CLR_INT8 ) +template __inline void NANOCLR_READ_UNALIGNED_INT16(T& arg, CLR_PMETADATA& ip) +{ + arg = (CLR_UINT16)(*(const CLR_UINT8 *)ip) ; ip += sizeof(CLR_UINT8); + arg |= (CLR_UINT16)(*(const CLR_UINT8 *)ip) << 8; ip += sizeof(CLR_UINT8); + arg = (CLR_INT16)arg; +} +template __inline void NANOCLR_READ_UNALIGNED_INT32(T& arg, CLR_PMETADATA& ip) +{ + arg = (CLR_UINT32)(*(const CLR_UINT8 *)ip) ; ip += sizeof(CLR_UINT8); + arg |= (CLR_UINT32)(*(const CLR_UINT8 *)ip) << 8; ip += sizeof(CLR_UINT8); + arg |= (CLR_UINT32)(*(const CLR_UINT8 *)ip) << 16; ip += sizeof(CLR_UINT8); + arg |= (CLR_UINT32)(*(const CLR_UINT8 *)ip) << 24; ip += sizeof(CLR_UINT8); + arg = (CLR_INT32)arg; +} +template __inline void NANOCLR_READ_UNALIGNED_INT64(T& arg, CLR_PMETADATA& ip) +{ + arg = (CLR_UINT64)(*(const CLR_UINT8 *)ip) ; ip += sizeof(CLR_UINT8); + arg |= (CLR_UINT64)(*(const CLR_UINT8 *)ip) << 8; ip += sizeof(CLR_UINT8); + arg |= (CLR_UINT64)(*(const CLR_UINT8 *)ip) << 16; ip += sizeof(CLR_UINT8); + arg |= (CLR_UINT64)(*(const CLR_UINT8 *)ip) << 24; ip += sizeof(CLR_UINT8); + arg |= (CLR_UINT64)(*(const CLR_UINT8 *)ip) << 32; ip += sizeof(CLR_UINT8); + arg |= (CLR_UINT64)(*(const CLR_UINT8 *)ip) << 40; ip += sizeof(CLR_UINT8); + arg |= (CLR_UINT64)(*(const CLR_UINT8 *)ip) << 48; ip += sizeof(CLR_UINT8); + arg |= (CLR_UINT64)(*(const CLR_UINT8 *)ip) << 56; ip += sizeof(CLR_UINT8); + arg = (CLR_INT64)arg; +} + + +#elif defined(_MSC_VER) + +#define NANOCLR_READ_UNALIGNED_UINT8(arg,ip) arg = *(__declspec(align(1)) const CLR_UINT8 *)ip; ip += sizeof(CLR_UINT8 ) +#define NANOCLR_READ_UNALIGNED_UINT16(arg,ip) arg = *(__declspec(align(1)) const CLR_UINT16*)ip; ip += sizeof(CLR_UINT16) +#define NANOCLR_READ_UNALIGNED_UINT32(arg,ip) arg = *(__declspec(align(1)) const CLR_UINT32*)ip; ip += sizeof(CLR_UINT32) +#define NANOCLR_READ_UNALIGNED_UINT64(arg,ip) arg = *(__declspec(align(1)) const CLR_UINT64*)ip; ip += sizeof(CLR_UINT64) + +#define NANOCLR_READ_UNALIGNED_INT8(arg,ip) arg = *(__declspec(align(1)) const CLR_INT8 * )ip; ip += sizeof(CLR_INT8 ) +#define NANOCLR_READ_UNALIGNED_INT16(arg,ip) arg = *(__declspec(align(1)) const CLR_INT16* )ip; ip += sizeof(CLR_INT16 ) +#define NANOCLR_READ_UNALIGNED_INT32(arg,ip) arg = *(__declspec(align(1)) const CLR_INT32* )ip; ip += sizeof(CLR_INT32 ) +#define NANOCLR_READ_UNALIGNED_INT64(arg,ip) arg = *(__declspec(align(1)) const CLR_INT64* )ip; ip += sizeof(CLR_INT64 ) + +//--// + +#define NANOCLR_WRITE_UNALIGNED_UINT8(ip,arg) *(__declspec(align(1)) CLR_UINT8 *)ip = arg; ip += sizeof(CLR_UINT8 ) +#define NANOCLR_WRITE_UNALIGNED_UINT16(ip,arg) *(__declspec(align(1)) CLR_UINT16*)ip = arg; ip += sizeof(CLR_UINT16) +#define NANOCLR_WRITE_UNALIGNED_UINT32(ip,arg) *(__declspec(align(1)) CLR_UINT32*)ip = arg; ip += sizeof(CLR_UINT32) +#define NANOCLR_WRITE_UNALIGNED_UINT64(ip,arg) *(__declspec(align(1)) CLR_UINT64*)ip = arg; ip += sizeof(CLR_UINT64) + +#define NANOCLR_WRITE_UNALIGNED_INT8(ip,arg) *(__declspec(align(1)) CLR_INT8 * )ip = arg; ip += sizeof(CLR_INT8 ) +#define NANOCLR_WRITE_UNALIGNED_INT16(ip,arg) *(__declspec(align(1)) CLR_INT16* )ip = arg; ip += sizeof(CLR_INT16 ) +#define NANOCLR_WRITE_UNALIGNED_INT32(ip,arg) *(__declspec(align(1)) CLR_INT32* )ip = arg; ip += sizeof(CLR_INT32 ) +#define NANOCLR_WRITE_UNALIGNED_INT64(ip,arg) *(__declspec(align(1)) CLR_INT64* )ip = arg; ip += sizeof(CLR_INT64 ) + +#else // TODO: __packed is compiler specific... Which compiler is this for? + +#define NANOCLR_READ_UNALIGNED_UINT8(arg,ip) arg = *(__packed CLR_UINT8 *)ip; ip += sizeof(CLR_UINT8 ) +#define NANOCLR_READ_UNALIGNED_UINT16(arg,ip) arg = *(__packed CLR_UINT16*)ip; ip += sizeof(CLR_UINT16) +#define NANOCLR_READ_UNALIGNED_UINT32(arg,ip) arg = *(__packed CLR_UINT32*)ip; ip += sizeof(CLR_UINT32) +#define NANOCLR_READ_UNALIGNED_UINT64(arg,ip) arg = *(__packed CLR_UINT64*)ip; ip += sizeof(CLR_UINT64) +#define NANOCLR_READ_UNALIGNED_INT8(arg,ip) arg = *(__packed CLR_INT8 * )ip; ip += sizeof(CLR_INT8 ) +#define NANOCLR_READ_UNALIGNED_INT16(arg,ip) arg = *(__packed CLR_INT16* )ip; ip += sizeof(CLR_INT16 ) +#define NANOCLR_READ_UNALIGNED_INT32(arg,ip) arg = *(__packed CLR_INT32* )ip; ip += sizeof(CLR_INT32 ) +#define NANOCLR_READ_UNALIGNED_INT64(arg,ip) arg = *(__packed CLR_INT64* )ip; ip += sizeof(CLR_INT64 ) + +//--// + +#define NANOCLR_WRITE_UNALIGNED_UINT8(ip,arg) *(__packed CLR_UINT8 *)ip = arg; ip += sizeof(CLR_UINT8 ) +#define NANOCLR_WRITE_UNALIGNED_UINT16(ip,arg) *(__packed CLR_UINT16*)ip = arg; ip += sizeof(CLR_UINT16) +#define NANOCLR_WRITE_UNALIGNED_UINT32(ip,arg) *(__packed CLR_UINT32*)ip = arg; ip += sizeof(CLR_UINT32) +#define NANOCLR_WRITE_UNALIGNED_UINT64(ip,arg) *(__packed CLR_UINT64*)ip = arg; ip += sizeof(CLR_UINT64) + +#define NANOCLR_WRITE_UNALIGNED_INT8(ip,arg) *(__packed CLR_INT8 * )ip = arg; ip += sizeof(CLR_INT8 ) +#define NANOCLR_WRITE_UNALIGNED_INT16(ip,arg) *(__packed CLR_INT16* )ip = arg; ip += sizeof(CLR_INT16 ) +#define NANOCLR_WRITE_UNALIGNED_INT32(ip,arg) *(__packed CLR_INT32* )ip = arg; ip += sizeof(CLR_INT32 ) +#define NANOCLR_WRITE_UNALIGNED_INT64(ip,arg) *(__packed CLR_INT64* )ip = arg; ip += sizeof(CLR_INT64 ) + +#endif + +//--// +#define NANOCLR_READ_UNALIGNED_OPCODE(op,ip) op = CLR_OPCODE(*ip++); if(op == CEE_PREFIX1) { opcode = CLR_OPCODE(*ip++ + 256); } + +#define NANOCLR_READ_UNALIGNED_COMPRESSED_FIELDTOKEN(arg,ip) NANOCLR_READ_UNALIGNED_UINT16( arg, ip ); arg = CLR_UncompressFieldToken ( arg ) +#define NANOCLR_READ_UNALIGNED_COMPRESSED_METHODTOKEN(arg,ip) NANOCLR_READ_UNALIGNED_UINT16( arg, ip ); arg = CLR_UncompressMethodToken( arg ) +#define NANOCLR_READ_UNALIGNED_COMPRESSED_TYPETOKEN(arg,ip) NANOCLR_READ_UNALIGNED_UINT16( arg, ip ); arg = CLR_UncompressTypeToken ( arg ) +#define NANOCLR_READ_UNALIGNED_COMPRESSED_STRINGTOKEN(arg,ip) NANOCLR_READ_UNALIGNED_UINT16( arg, ip ); arg = CLR_UncompressStringToken( arg ) + + +//--// + +inline CLR_OPCODE CLR_ReadNextOpcode( CLR_PMETADATA& ip ) +{ + CLR_PMETADATA ptr = ip; + CLR_OPCODE opcode = CLR_OPCODE(*ptr++); + + if(opcode == CEE_PREFIX1) + { + opcode = CLR_OPCODE(*ptr++ + 256); + } + + ip = ptr; + + return opcode; +} + +inline CLR_OPCODE CLR_ReadNextOpcodeCompressed( CLR_PMETADATA& ip ) +{ + CLR_PMETADATA ptr = ip; + CLR_OPCODE opcode = CLR_OPCODE(*ptr++); + + if(opcode == CEE_PREFIX1) + { + opcode = CLR_OPCODE(*ptr++ + 256); + } + + ip = ptr; + + return opcode; +} + +//--// + +#define FETCH_ARG_UINT8(arg,ip) CLR_UINT32 arg; NANOCLR_READ_UNALIGNED_UINT8 ( arg, ip ) +#define FETCH_ARG_UINT16(arg,ip) CLR_UINT32 arg; NANOCLR_READ_UNALIGNED_UINT16( arg, ip ) +#define FETCH_ARG_UINT32(arg,ip) CLR_UINT32 arg; NANOCLR_READ_UNALIGNED_UINT32( arg, ip ) +#define FETCH_ARG_UINT64(arg,ip) CLR_UINT64 arg; NANOCLR_READ_UNALIGNED_UINT64( arg, ip ) + +#define FETCH_ARG_INT8(arg,ip) CLR_INT32 arg; NANOCLR_READ_UNALIGNED_INT8 ( arg, ip ) +#define FETCH_ARG_INT16(arg,ip) CLR_INT32 arg; NANOCLR_READ_UNALIGNED_INT16( arg, ip ) +#define FETCH_ARG_INT32(arg,ip) CLR_INT32 arg; NANOCLR_READ_UNALIGNED_INT32( arg, ip ) +#define FETCH_ARG_INT64(arg,ip) CLR_INT64 arg; NANOCLR_READ_UNALIGNED_INT64( arg, ip ) + +#define FETCH_ARG_COMPRESSED_STRINGTOKEN(arg,ip) CLR_UINT32 arg; NANOCLR_READ_UNALIGNED_COMPRESSED_STRINGTOKEN( arg, ip ) +#define FETCH_ARG_COMPRESSED_FIELDTOKEN(arg,ip) CLR_UINT32 arg; NANOCLR_READ_UNALIGNED_COMPRESSED_FIELDTOKEN ( arg, ip ) +#define FETCH_ARG_COMPRESSED_TYPETOKEN(arg,ip) CLR_UINT32 arg; NANOCLR_READ_UNALIGNED_COMPRESSED_TYPETOKEN ( arg, ip ) +#define FETCH_ARG_COMPRESSED_METHODTOKEN(arg,ip) CLR_UINT32 arg; NANOCLR_READ_UNALIGNED_COMPRESSED_METHODTOKEN( arg, ip ) +#define FETCH_ARG_TOKEN(arg,ip) CLR_UINT32 arg; NANOCLR_READ_UNALIGNED_UINT32 ( arg, ip ) + +//--// + +#if defined(_WIN32) + + CLR_PMETADATA CLR_SkipBodyOfOpcode ( CLR_PMETADATA ip, CLR_OPCODE opcode ); + CLR_PMETADATA CLR_SkipBodyOfOpcodeCompressed( CLR_PMETADATA ip, CLR_OPCODE opcode ); + +#endif + +//////////////////////////////////////////////////////////////////////////////////////////////////// + + extern bool CLR_SafeSprintfV( char*& szBuffer, size_t& iBuffer, const char* format, va_list arg ); + extern bool CLR_SafeSprintf ( char*& szBuffer, size_t& iBuffer, const char* format, ... ); + +#if !defined(BUILD_RTM) + +#define NANOCLR_DEBUG_STOP() _ASSERTE(false) + +#else + +#define NANOCLR_DEBUG_STOP() CPU_Reset() + +#endif + +//--// + +struct CLR_Debug +{ + static int PrintfV( const char *format, va_list arg ); + static int Printf ( const char *format, ... ); + static void Emit ( const char *text, int len ); + static void Flush ( ); + + //--// + + typedef int (*OutputHandler)( const char *format, ... ); + +#if defined(_WIN32) + static void RedirectToString( std::string* str ); + static void SaveMessage (std::string str ); +#endif +}; + +//////////////////////////////////////////////////////////////////////////////// + +struct CLR_RECORD_VERSION +{ + CLR_UINT16 iMajorVersion; + CLR_UINT16 iMinorVersion; + CLR_UINT16 iBuildNumber; + CLR_UINT16 iRevisionNumber; +}; + +struct CLR_RECORD_ASSEMBLY +{ + static const CLR_UINT32 c_Flags_NeedReboot = 0x00000001; + static const CLR_UINT32 c_Flags_Patch = 0x00000002; + + CLR_UINT8 marker[ 8 ]; + // + CLR_UINT32 headerCRC; + CLR_UINT32 assemblyCRC; + CLR_UINT32 flags; + // + CLR_UINT32 nativeMethodsChecksum; + CLR_UINT32 patchEntryOffset; + // + CLR_RECORD_VERSION version; + // + CLR_STRING assemblyName; // TBL_Strings + CLR_UINT16 stringTableVersion; + // + CLR_OFFSET_LONG startOfTables[ TBL_Max ]; + CLR_UINT32 numOfPatchedMethods; + // + //For every table, a number of bytes that were padded to the end of the table + //to align to unsigned long. Each table starts at a unsigned long boundary, and ends + //at a unsigned long boundary. Some of these tables will, by construction, have + //no padding, and all will have values in the range [0-3]. This isn't the most + //compact form to hold this information, but it only costs 16 bytes/assembly. + //Trying to only align some of the tables is just much more hassle than it's worth. + //And, of course, this field also has to be unsigned long-aligned. + CLR_UINT8 paddingOfTables[ ((TBL_Max-1)+3)/4*4 ]; + //--// + + bool GoodHeader () const; + bool GoodAssembly() const; + +#if defined(_WIN32) + void ComputeCRC(); +#endif + + CLR_OFFSET_LONG SizeOfTable( CLR_TABLESENUM tbl ) const { return startOfTables[ tbl+1 ] - startOfTables[ tbl ] - paddingOfTables[ tbl ]; } + + CLR_OFFSET_LONG TotalSize() const { return startOfTables[ TBL_EndOfAssembly ]; } + + //--// + + static CLR_UINT32 ComputeAssemblyHash( const char* name, const CLR_RECORD_VERSION& ver ); +}; + +struct CLR_RECORD_ASSEMBLYREF +{ + CLR_STRING name; // TBL_Strings + CLR_UINT16 pad; + // + CLR_RECORD_VERSION version; +}; + +struct CLR_RECORD_TYPEREF +{ + CLR_STRING name; // TBL_Strings + CLR_STRING nameSpace; // TBL_Strings + // + CLR_IDX scope; // TBL_AssemblyRef | TBL_TypeRef // 0x8000 + CLR_UINT16 pad; +}; + +struct CLR_RECORD_FIELDREF +{ + CLR_STRING name; // TBL_Strings + CLR_IDX container; // TBL_TypeRef + // + CLR_SIG sig; // TBL_Signatures + CLR_UINT16 pad; +}; + +struct CLR_RECORD_METHODREF +{ + CLR_STRING name; // TBL_Strings + CLR_IDX container; // TBL_TypeRef + // + CLR_SIG sig; // TBL_Signatures + CLR_UINT16 pad; +}; + +struct CLR_RECORD_TYPEDEF +{ + static const CLR_UINT16 TD_Scope_Mask = 0x0007; + static const CLR_UINT16 TD_Scope_NotPublic = 0x0000; // Class is not public scope. + static const CLR_UINT16 TD_Scope_Public = 0x0001; // Class is public scope. + static const CLR_UINT16 TD_Scope_NestedPublic = 0x0002; // Class is nested with public visibility. + static const CLR_UINT16 TD_Scope_NestedPrivate = 0x0003; // Class is nested with private visibility. + static const CLR_UINT16 TD_Scope_NestedFamily = 0x0004; // Class is nested with family visibility. + static const CLR_UINT16 TD_Scope_NestedAssembly = 0x0005; // Class is nested with assembly visibility. + static const CLR_UINT16 TD_Scope_NestedFamANDAssem = 0x0006; // Class is nested with family and assembly visibility. + static const CLR_UINT16 TD_Scope_NestedFamORAssem = 0x0007; // Class is nested with family or assembly visibility. + + static const CLR_UINT16 TD_Serializable = 0x0008; + + static const CLR_UINT16 TD_Semantics_Mask = 0x0030; + static const CLR_UINT16 TD_Semantics_Class = 0x0000; + static const CLR_UINT16 TD_Semantics_ValueType = 0x0010; + static const CLR_UINT16 TD_Semantics_Interface = 0x0020; + static const CLR_UINT16 TD_Semantics_Enum = 0x0030; + + static const CLR_UINT16 TD_Abstract = 0x0040; + static const CLR_UINT16 TD_Sealed = 0x0080; + + static const CLR_UINT16 TD_SpecialName = 0x0100; + static const CLR_UINT16 TD_Delegate = 0x0200; + static const CLR_UINT16 TD_MulticastDelegate = 0x0400; + + static const CLR_UINT16 TD_Patched = 0x0800; + + static const CLR_UINT16 TD_BeforeFieldInit = 0x1000; + static const CLR_UINT16 TD_HasSecurity = 0x2000; + static const CLR_UINT16 TD_HasFinalizer = 0x4000; + static const CLR_UINT16 TD_HasAttributes = 0x8000; + + + CLR_STRING name; // TBL_Strings + CLR_STRING nameSpace; // TBL_Strings + // + CLR_IDX extends; // TBL_TypeDef | TBL_TypeRef // 0x8000 + CLR_IDX enclosingType; // TBL_TypeDef + // + CLR_SIG interfaces; // TBL_Signatures + CLR_IDX methods_First; // TBL_MethodDef + // + CLR_UINT8 vMethods_Num; + CLR_UINT8 iMethods_Num; + CLR_UINT8 sMethods_Num; + CLR_UINT8 dataType; + // + CLR_IDX sFields_First; // TBL_FieldDef + CLR_IDX iFields_First; // TBL_FieldDef + // + CLR_UINT8 sFields_Num; + CLR_UINT8 iFields_Num; + CLR_UINT16 flags; + + //--// + + bool IsEnum () const { return (flags & (TD_Semantics_Mask )) == TD_Semantics_Enum; } + bool IsDelegate() const { return (flags & (TD_Delegate | TD_MulticastDelegate)) != 0 ; } +}; + +struct CLR_RECORD_FIELDDEF +{ + static const CLR_UINT16 FD_Scope_Mask = 0x0007; + static const CLR_UINT16 FD_Scope_PrivateScope = 0x0000; // Member not referenceable. + static const CLR_UINT16 FD_Scope_Private = 0x0001; // Accessible only by the parent type. + static const CLR_UINT16 FD_Scope_FamANDAssem = 0x0002; // Accessible by sub-types only in this Assembly. + static const CLR_UINT16 FD_Scope_Assembly = 0x0003; // Accessibly by anyone in the Assembly. + static const CLR_UINT16 FD_Scope_Family = 0x0004; // Accessible only by type and sub-types. + static const CLR_UINT16 FD_Scope_FamORAssem = 0x0005; // Accessibly by sub-types anywhere, plus anyone in assembly. + static const CLR_UINT16 FD_Scope_Public = 0x0006; // Accessibly by anyone who has visibility to this scope. + + static const CLR_UINT16 FD_NotSerialized = 0x0008; // Field does not have to be serialized when type is remoted. + + static const CLR_UINT16 FD_Static = 0x0010; // Defined on type, else per instance. + static const CLR_UINT16 FD_InitOnly = 0x0020; // Field may only be initialized, not written to after init. + static const CLR_UINT16 FD_Literal = 0x0040; // Value is compile time constant. + + static const CLR_UINT16 FD_SpecialName = 0x0100; // field is special. Name describes how. + static const CLR_UINT16 FD_HasDefault = 0x0200; // Field has default. + static const CLR_UINT16 FD_HasFieldRVA = 0x0400; // Field has RVA. + + static const CLR_UINT16 FD_NoReflection = 0x0800; // field does not allow reflection + + static const CLR_UINT16 FD_HasAttributes = 0x8000; + + + CLR_STRING name; // TBL_Strings + CLR_SIG sig; // TBL_Signatures + // + CLR_SIG defaultValue; // TBL_Signatures + CLR_UINT16 flags; +}; + +struct CLR_RECORD_METHODDEF +{ + static const CLR_UINT32 MD_Scope_Mask = 0x00000007; + static const CLR_UINT32 MD_Scope_PrivateScope = 0x00000000; // Member not referenceable. + static const CLR_UINT32 MD_Scope_Private = 0x00000001; // Accessible only by the parent type. + static const CLR_UINT32 MD_Scope_FamANDAssem = 0x00000002; // Accessible by sub-types only in this Assembly. + static const CLR_UINT32 MD_Scope_Assem = 0x00000003; // Accessibly by anyone in the Assembly. + static const CLR_UINT32 MD_Scope_Family = 0x00000004; // Accessible only by type and sub-types. + static const CLR_UINT32 MD_Scope_FamORAssem = 0x00000005; // Accessibly by sub-types anywhere, plus anyone in assembly. + static const CLR_UINT32 MD_Scope_Public = 0x00000006; // Accessibly by anyone who has visibility to this scope. + + static const CLR_UINT32 MD_Static = 0x00000010; // Defined on type, else per instance. + static const CLR_UINT32 MD_Final = 0x00000020; // Method may not be overridden. + static const CLR_UINT32 MD_Virtual = 0x00000040; // Method virtual. + static const CLR_UINT32 MD_HideBySig = 0x00000080; // Method hides by name+sig, else just by name. + + static const CLR_UINT32 MD_VtableLayoutMask = 0x00000100; + static const CLR_UINT32 MD_ReuseSlot = 0x00000000; // The default. + static const CLR_UINT32 MD_NewSlot = 0x00000100; // Method always gets a new slot in the vtable. + static const CLR_UINT32 MD_Abstract = 0x00000200; // Method does not provide an implementation. + static const CLR_UINT32 MD_SpecialName = 0x00000400; // Method is special. Name describes how. + static const CLR_UINT32 MD_NativeProfiled = 0x00000800; + + static const CLR_UINT32 MD_Constructor = 0x00001000; + static const CLR_UINT32 MD_StaticConstructor = 0x00002000; + static const CLR_UINT32 MD_Finalizer = 0x00004000; + + static const CLR_UINT32 MD_DelegateConstructor = 0x00010000; + static const CLR_UINT32 MD_DelegateInvoke = 0x00020000; + static const CLR_UINT32 MD_DelegateBeginInvoke = 0x00040000; + static const CLR_UINT32 MD_DelegateEndInvoke = 0x00080000; + + static const CLR_UINT32 MD_Synchronized = 0x01000000; + static const CLR_UINT32 MD_GloballySynchronized = 0x02000000; + static const CLR_UINT32 MD_Patched = 0x04000000; + static const CLR_UINT32 MD_EntryPoint = 0x08000000; + static const CLR_UINT32 MD_RequireSecObject = 0x10000000; // Method calls another method containing security code. + static const CLR_UINT32 MD_HasSecurity = 0x20000000; // Method has security associate with it. + static const CLR_UINT32 MD_HasExceptionHandlers = 0x40000000; + static const CLR_UINT32 MD_HasAttributes = 0x80000000; + + + CLR_STRING name; // TBL_Strings + CLR_OFFSET RVA; + // + CLR_UINT32 flags; + // + CLR_UINT8 retVal; + CLR_UINT8 numArgs; + CLR_UINT8 numLocals; + CLR_UINT8 lengthEvalStack; + // + CLR_SIG locals; // TBL_Signatures + CLR_SIG sig; // TBL_Signatures +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstrict-aliasing" +#endif +// pragma required here because compiler is not too happy with the cast to CLR_UINT32* from a CLR_UINT16 variable + +struct CLR_RECORD_ATTRIBUTE +{ + CLR_UINT16 ownerType; // one of TBL_TypeDef, TBL_MethodDef, or TBL_FieldDef. + CLR_UINT16 ownerIdx; // TBL_TypeDef | TBL_MethodDef | TBL_FielfDef + CLR_UINT16 constructor; + CLR_SIG data; // TBL_Signatures + + CLR_UINT32 Key() const { return *(CLR_UINT32*)&ownerType; } +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +struct CLR_RECORD_TYPESPEC +{ + CLR_SIG sig; // TBL_Signatures + CLR_UINT16 pad; +}; + +struct CLR_RECORD_EH +{ + static const CLR_UINT16 EH_Catch = 0x0000; + static const CLR_UINT16 EH_CatchAll = 0x0001; + static const CLR_UINT16 EH_Finally = 0x0002; + static const CLR_UINT16 EH_Filter = 0x0003; + + //--// + + CLR_UINT16 mode; + union { + CLR_IDX classToken; // TBL_TypeDef | TBL_TypeRef + CLR_OFFSET filterStart; + }; + CLR_OFFSET tryStart; + CLR_OFFSET tryEnd; + CLR_OFFSET handlerStart; + CLR_OFFSET handlerEnd; + + //--// + + static CLR_PMETADATA ExtractEhFromByteCode( CLR_PMETADATA ipEnd, const CLR_RECORD_EH*& ptrEh, CLR_UINT32& numEh ); + + CLR_UINT32 GetToken() const; +}; + +CT_ASSERT_UNIQUE_NAME( sizeof(CLR_RECORD_EH) == 12, CLR_RECORD_EH ) + +struct CLR_RECORD_RESOURCE_FILE +{ + static const CLR_UINT32 CURRENT_VERSION = 2; + + CLR_UINT32 version; + CLR_UINT32 sizeOfHeader; + CLR_UINT32 sizeOfResourceHeader; + CLR_UINT32 numberOfResources; + CLR_STRING name; // TBL_Strings + CLR_UINT16 pad; + CLR_UINT32 offset; // TBL_Resource +}; + +struct CLR_RECORD_RESOURCE +{ + static const CLR_UINT8 RESOURCE_Invalid = 0x00; + static const CLR_UINT8 RESOURCE_Bitmap = 0x01; + static const CLR_UINT8 RESOURCE_Font = 0x02; + static const CLR_UINT8 RESOURCE_String = 0x03; + static const CLR_UINT8 RESOURCE_Binary = 0x04; + + static const CLR_UINT8 FLAGS_PaddingMask = 0x03; + static const CLR_INT16 SENTINEL_ID = 0x7FFF; + + // + // Sorted on id + // + CLR_INT16 id; + CLR_UINT8 kind; + CLR_UINT8 flags; + CLR_UINT32 offset; +}; + +#if defined(_MSC_VER) +#pragma pack(pop, NANOCLR_TYPES_H) +#endif + +#endif // _NANOCLR_TYPES_H_ + diff --git a/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Win32.h b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Win32.h new file mode 100644 index 00000000..b4fae5be --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/nanoCLR_Win32.h @@ -0,0 +1,42 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _NANOCLR_WIN32_H_ +#define _NANOCLR_WIN32_H_ + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +void HAL_Windows_FastSleep( signed __int64 ticks ); + +bool HAL_Windows_IsShutdownPending(); + +void HAL_Windows_AcquireGlobalLock(); +void HAL_Windows_ReleaseGlobalLock(); +bool HAL_Windows_HasGlobalLock(); + +unsigned __int64 HAL_Windows_GetPerformanceTicks(); + +void HAL_Windows_Debug_Print( char* szText ); + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +class HAL_Mutex +{ + CRITICAL_SECTION m_data; + +public: + HAL_Mutex(); + ~HAL_Mutex(); + + //--// + + void Lock (); + void Unlock(); +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#endif // _NANOCLR_WIN32_H_ + diff --git a/source/native/nf-interpreter/src/CLR/Include/nanoPackStruct.h b/source/native/nf-interpreter/src/CLR/Include/nanoPackStruct.h new file mode 100644 index 00000000..c275b407 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/nanoPackStruct.h @@ -0,0 +1,21 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// +#ifndef _NANO_PACKSTRUCT_H_ +#define _NANO_PACKSTRUCT_H_ 1 + +// definition of PACK attribute for structs +#if defined(_MSC_VER) +// VC++ doesn't support this attribute the same way so it's definition ends up being an empty one +// for VC++ the equivalent is #pragma pack +#define __nfpack + +#elif defined(__GNUC__) +#define __nfpack __attribute__((__packed__)) + +#else +#error "Unknow platform. Please add definition for attribute to tell compiler to pack the struct." +#endif + +#endif // _NANO_PACKSTRUCT_H_ diff --git a/source/native/nf-interpreter/src/CLR/Include/nanoSupport.h b/source/native/nf-interpreter/src/CLR/Include/nanoSupport.h new file mode 100644 index 00000000..f7b46d0d --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/nanoSupport.h @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _SUPPORT_NANOSUPPORT_H_ +#define _SUPPORT_NANOSUPPORT_H_ + +#if defined(__cplusplus) +extern "C" { +#endif + +unsigned int SUPPORT_ComputeCRC(const void* rgBlock, int nLength, unsigned int crc); + +#if defined(__cplusplus) +} +#endif + +#endif // _SUPPORT_NANOSUPPORT_H_ diff --git a/source/native/nf-interpreter/src/CLR/Include/nanoWeak.h b/source/native/nf-interpreter/src/CLR/Include/nanoWeak.h new file mode 100644 index 00000000..a4cd9cac --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/nanoWeak.h @@ -0,0 +1,21 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _NANO_WEAK_H_ +#define _NANO_WEAK_H_ 1 + +// definition of WEAK attribute for stub functions +#if defined(_MSC_VER) +// because VC++ doesn't support this attribute it's definition end up being an empty one +#define __nfweak + +#elif defined(__GNUC__) +#define __nfweak __attribute__((weak)) + +#else +#error "Unknow platform. Please add definition for weak attribute." +#endif + +#endif // _NANO_WEAK_H_ diff --git a/source/native/nf-interpreter/src/CLR/Include/nf_errors_exceptions.h b/source/native/nf-interpreter/src/CLR/Include/nf_errors_exceptions.h new file mode 100644 index 00000000..5d7bd40c --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/nf_errors_exceptions.h @@ -0,0 +1,171 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef __NF_ERRORS_H__ +#define __NF_ERRORS_H__ + +#if !defined(WIN32) && !defined(_WIN32) + +typedef int HRESULT; + +// +// Severity values +// + +#define SEVERITY_SUCCESS 0 +#define SEVERITY_ERROR 1 + + +// +// Generic test for success on any status value (non-negative numbers +// indicate success). +// + +#define SUCCEEDED(Status) ((HRESULT)(Status) >= 0) + +// +// and the inverse +// + +#define FAILED(Status) ((HRESULT)(Status)<0) + + +// +// Success codes +// +#define S_OK ((HRESULT)0x00000000L) +#define S_FALSE ((HRESULT)0x00000001L) + + +// +// Return the code +// + +#define HRESULT_CODE(hr) ((hr) & 0xFFFF) + +// +// Return the facility +// + +#define HRESULT_FACILITY(hr) (((hr) >> 16) & 0x1fff) + +// +// Return the severity +// + +#define HRESULT_SEVERITY(hr) (((hr) >> 31) & 0x1) + +// +// Create an HRESULT value from component pieces +// + +#define MAKE_HRESULT(sev,fac,code) ((HRESULT) (((unsigned long)(sev)<<31) | ((unsigned long)(fac)<<16) | ((unsigned long)(code))) ) + +#endif // !defined(WIN32) && !defined(_WIN32) + +//--// + +// +// These are denormalized HRESULTs, only the 8 most significant bits are set, to allow use of MOV ,# by the compiler. +// + +#define CLR_E_UNKNOWN_INSTRUCTION MAKE_HRESULT( SEVERITY_ERROR , 0x0100, 0x0000 ) +#define CLR_E_UNSUPPORTED_INSTRUCTION MAKE_HRESULT( SEVERITY_ERROR , 0x0200, 0x0000 ) + +#define CLR_E_STACK_OVERFLOW MAKE_HRESULT( SEVERITY_ERROR , 0x1100, 0x0000 ) +#define CLR_E_STACK_UNDERFLOW MAKE_HRESULT( SEVERITY_ERROR , 0x1200, 0x0000 ) + +#define CLR_E_ENTRY_NOT_FOUND MAKE_HRESULT( SEVERITY_ERROR , 0x1500, 0x0000 ) +#define CLR_E_ASSM_WRONG_CHECKSUM MAKE_HRESULT( SEVERITY_ERROR , 0x1600, 0x0000 ) +#define CLR_E_ASSM_PATCHING_NOT_SUPPORTED MAKE_HRESULT( SEVERITY_ERROR , 0x1700, 0x0000 ) +#define CLR_E_SHUTTING_DOWN MAKE_HRESULT( SEVERITY_ERROR , 0x1800, 0x0000 ) +#define CLR_E_OBJECT_DISPOSED MAKE_HRESULT( SEVERITY_ERROR , 0x1900, 0x0000 ) +#define CLR_E_WATCHDOG_TIMEOUT MAKE_HRESULT( SEVERITY_ERROR , 0x1A00, 0x0000 ) + +#define CLR_E_NULL_REFERENCE MAKE_HRESULT( SEVERITY_ERROR , 0x2100, 0x0000 ) +#define CLR_E_WRONG_TYPE MAKE_HRESULT( SEVERITY_ERROR , 0x2200, 0x0000 ) +#define CLR_E_TYPE_UNAVAILABLE MAKE_HRESULT( SEVERITY_ERROR , 0x2300, 0x0000 ) +#define CLR_E_INVALID_CAST MAKE_HRESULT( SEVERITY_ERROR , 0x2400, 0x0000 ) +#define CLR_E_OUT_OF_RANGE MAKE_HRESULT( SEVERITY_ERROR , 0x2500, 0x0000 ) + +#define CLR_E_SERIALIZATION_VIOLATION MAKE_HRESULT( SEVERITY_ERROR , 0x2700, 0x0000 ) +#define CLR_E_SERIALIZATION_BADSTREAM MAKE_HRESULT( SEVERITY_ERROR , 0x2800, 0x0000 ) +#define CLR_E_INDEX_OUT_OF_RANGE MAKE_HRESULT( SEVERITY_ERROR , 0x2900, 0x0000 ) + +#define CLR_E_DIVIDE_BY_ZERO MAKE_HRESULT( SEVERITY_ERROR , 0x3100, 0x0000 ) + +#define CLR_E_BUSY MAKE_HRESULT( SEVERITY_ERROR , 0x3300, 0x0000 ) + +#define CLR_E_PROCESS_EXCEPTION MAKE_HRESULT( SEVERITY_ERROR , 0x4100, 0x0000 ) + +#define CLR_E_THREAD_WAITING MAKE_HRESULT( SEVERITY_ERROR , 0x4200, 0x0000 ) + +#define CLR_E_LOCK_SYNCHRONIZATION_EXCEPTION MAKE_HRESULT( SEVERITY_ERROR , 0x4400, 0x0000 ) + +#define CLR_E_APPDOMAIN_EXITED MAKE_HRESULT( SEVERITY_ERROR , 0x4800, 0x0000 ) +#define CLR_E_APPDOMAIN_MARSHAL_EXCEPTION MAKE_HRESULT( SEVERITY_ERROR , 0x4900, 0x0000 ) +#define CLR_E_NOTIMPL MAKE_HRESULT( SEVERITY_ERROR , 0x4a00, 0x0000 ) + +#define CLR_E_UNKNOWN_TYPE MAKE_HRESULT( SEVERITY_ERROR , 0x4d00, 0x0000 ) +#define CLR_E_ARGUMENT_NULL MAKE_HRESULT( SEVERITY_ERROR , 0x4e00, 0x0000 ) +#define CLR_E_IO MAKE_HRESULT( SEVERITY_ERROR , 0x4f00, 0x0000 ) + +#define CLR_E_ENTRYPOINT_NOT_FOUND MAKE_HRESULT( SEVERITY_ERROR , 0x5000, 0x0000 ) +#define CLR_E_DRIVER_NOT_REGISTERED MAKE_HRESULT( SEVERITY_ERROR , 0x5100, 0x0000 ) + + +// +// Gp IO error codes +// +#define CLR_E_PIN_UNAVAILABLE MAKE_HRESULT( SEVERITY_ERROR , 0x5400, 0x0000 ) +#define CLR_E_PIN_DEAD MAKE_HRESULT( SEVERITY_ERROR , 0x5500, 0x0000 ) +#define CLR_E_INVALID_OPERATION MAKE_HRESULT( SEVERITY_ERROR , 0x5600, 0x0000 ) +#define CLR_E_WRONG_INTERRUPT_TYPE MAKE_HRESULT( SEVERITY_ERROR , 0x5700, 0x0000 ) +#define CLR_E_NO_INTERRUPT MAKE_HRESULT( SEVERITY_ERROR , 0x5800, 0x0000 ) +#define CLR_E_DISPATCHER_ACTIVE MAKE_HRESULT( SEVERITY_ERROR , 0x5900, 0x0000 ) + +// +// IO error codes +// (Keep in-sync with IOExceptionErrorCode enum in IOException.cs) +// +#define CLR_E_FILE_IO MAKE_HRESULT( SEVERITY_ERROR , 0x6000, 0x0000 ) +#define CLR_E_INVALID_DRIVER MAKE_HRESULT( SEVERITY_ERROR , 0x6100, 0x0000 ) +#define CLR_E_FILE_NOT_FOUND MAKE_HRESULT( SEVERITY_ERROR , 0x6200, 0x0000 ) +#define CLR_E_DIRECTORY_NOT_FOUND MAKE_HRESULT( SEVERITY_ERROR , 0x6300, 0x0000 ) +#define CLR_E_VOLUME_NOT_FOUND MAKE_HRESULT( SEVERITY_ERROR , 0x6400, 0x0000 ) +#define CLR_E_PATH_TOO_LONG MAKE_HRESULT( SEVERITY_ERROR , 0x6500, 0x0000 ) +#define CLR_E_DIRECTORY_NOT_EMPTY MAKE_HRESULT( SEVERITY_ERROR , 0x6600, 0x0000 ) +#define CLR_E_UNAUTHORIZED_ACCESS MAKE_HRESULT( SEVERITY_ERROR , 0x6700, 0x0000 ) +#define CLR_E_PATH_ALREADY_EXISTS MAKE_HRESULT( SEVERITY_ERROR , 0x6800, 0x0000 ) +#define CLR_E_TOO_MANY_OPEN_HANDLES MAKE_HRESULT( SEVERITY_ERROR , 0x6900, 0x0000 ) + +// +// General error codes +// + +#define CLR_E_NOT_FOUND MAKE_HRESULT( SEVERITY_ERROR , 0x7500, 0x0000 ) +#define CLR_E_BUFFER_TOO_SMALL MAKE_HRESULT( SEVERITY_ERROR , 0x7600, 0x0000 ) +#define CLR_E_NOT_SUPPORTED MAKE_HRESULT( SEVERITY_ERROR , 0x7700, 0x0000 ) +#define CLR_E_HMAC_NOT_SUPPORTED MAKE_HRESULT( SEVERITY_ERROR , 0x7701, 0x0000 ) +#define CLR_E_RESCHEDULE MAKE_HRESULT( SEVERITY_ERROR , 0x7800, 0x0000 ) + +#define CLR_E_OUT_OF_MEMORY MAKE_HRESULT( SEVERITY_ERROR , 0x7A00, 0x0000 ) +#define CLR_E_RESTART_EXECUTION MAKE_HRESULT( SEVERITY_ERROR , 0x7B00, 0x0000 ) + +#define CLR_E_INVALID_PARAMETER MAKE_HRESULT( SEVERITY_ERROR , 0x7D00, 0x0000 ) +#define CLR_E_TIMEOUT MAKE_HRESULT( SEVERITY_ERROR , 0x7E00, 0x0000 ) +#define CLR_E_FAIL MAKE_HRESULT( SEVERITY_ERROR , 0x7F00, 0x0000 ) + +//--// + +#define CLR_S_THREAD_EXITED MAKE_HRESULT( SEVERITY_SUCCESS, 0x0100, 0x0000 ) +#define CLR_S_QUANTUM_EXPIRED MAKE_HRESULT( SEVERITY_SUCCESS, 0x0200, 0x0000 ) +#define CLR_S_NO_READY_THREADS MAKE_HRESULT( SEVERITY_SUCCESS, 0x0300, 0x0000 ) +#define CLR_S_NO_THREADS MAKE_HRESULT( SEVERITY_SUCCESS, 0x0400, 0x0000 ) +#define CLR_S_RESTART_EXECUTION MAKE_HRESULT( SEVERITY_SUCCESS, 0x0500, 0x0000 ) + + +#endif // __NF_ERRORS_H__ + diff --git a/source/native/nf-interpreter/src/CLR/Include/opcode.def b/source/native/nf-interpreter/src/CLR/Include/opcode.def new file mode 100644 index 00000000..9f909fc3 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/opcode.def @@ -0,0 +1,359 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +/***************************************************************************** + ** ** + ** Opcode.def - COM+ Intrinsic Opcodes and Macros. ** + ** ** + ** This is the master table from which all opcode lists ** + ** are derived. New instructions must be added to this ** + ** table and generators run to produce the lookup tables ** + ** used by the interpreter loop. ** + ** ** + ** Stack Behaviour is describing the number of 4 byte ** + ** slots pushed and Poped. ** + ** ** + *****************************************************************************/ + + +#ifndef __OPCODE_DEF_ +#define __OPCODE_DEF_ + +#define MOOT 0x00 // Marks unused second byte when encoding single +#define STP1 0xFE // Prefix code 1 for Standard Map +#define REFPRE 0xFF // Prefix for Reference Code Encoding +#define RESERVED_PREFIX_START 0xF7 + +#endif + +// If the first byte of the standard encoding is 0xFF, then +// the second byte can be used as 1 byte encoding. Otherwise l b b +// the encoding is two bytes. e y y +// n t t +// g e e +// (unused) t +// Canonical Name String Name Stack Behaviour Operand Params Opcode Kind h 1 2 Control Flow +// ------------------------------------------------------------------------------------------------------------------------------------------------------- +OPDEF(CEE_NOP, "nop", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x00, NEXT) +OPDEF(CEE_BREAK, "break", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x01, BREAK) +OPDEF(CEE_LDARG_0, "ldarg.0", Pop0, Push1, InlineNone, IMacro, 1, 0xFF, 0x02, NEXT) +OPDEF(CEE_LDARG_1, "ldarg.1", Pop0, Push1, InlineNone, IMacro, 1, 0xFF, 0x03, NEXT) +OPDEF(CEE_LDARG_2, "ldarg.2", Pop0, Push1, InlineNone, IMacro, 1, 0xFF, 0x04, NEXT) +OPDEF(CEE_LDARG_3, "ldarg.3", Pop0, Push1, InlineNone, IMacro, 1, 0xFF, 0x05, NEXT) +OPDEF(CEE_LDLOC_0, "ldloc.0", Pop0, Push1, InlineNone, IMacro, 1, 0xFF, 0x06, NEXT) +OPDEF(CEE_LDLOC_1, "ldloc.1", Pop0, Push1, InlineNone, IMacro, 1, 0xFF, 0x07, NEXT) +OPDEF(CEE_LDLOC_2, "ldloc.2", Pop0, Push1, InlineNone, IMacro, 1, 0xFF, 0x08, NEXT) +OPDEF(CEE_LDLOC_3, "ldloc.3", Pop0, Push1, InlineNone, IMacro, 1, 0xFF, 0x09, NEXT) +OPDEF(CEE_STLOC_0, "stloc.0", Pop1, Push0, InlineNone, IMacro, 1, 0xFF, 0x0A, NEXT) +OPDEF(CEE_STLOC_1, "stloc.1", Pop1, Push0, InlineNone, IMacro, 1, 0xFF, 0x0B, NEXT) +OPDEF(CEE_STLOC_2, "stloc.2", Pop1, Push0, InlineNone, IMacro, 1, 0xFF, 0x0C, NEXT) +OPDEF(CEE_STLOC_3, "stloc.3", Pop1, Push0, InlineNone, IMacro, 1, 0xFF, 0x0D, NEXT) +OPDEF(CEE_LDARG_S, "ldarg.s", Pop0, Push1, ShortInlineVar, IMacro, 1, 0xFF, 0x0E, NEXT) +OPDEF(CEE_LDARGA_S, "ldarga.s", Pop0, PushI, ShortInlineVar, IMacro, 1, 0xFF, 0x0F, NEXT) +OPDEF(CEE_STARG_S, "starg.s", Pop1, Push0, ShortInlineVar, IMacro, 1, 0xFF, 0x10, NEXT) +OPDEF(CEE_LDLOC_S, "ldloc.s", Pop0, Push1, ShortInlineVar, IMacro, 1, 0xFF, 0x11, NEXT) +OPDEF(CEE_LDLOCA_S, "ldloca.s", Pop0, PushI, ShortInlineVar, IMacro, 1, 0xFF, 0x12, NEXT) +OPDEF(CEE_STLOC_S, "stloc.s", Pop1, Push0, ShortInlineVar, IMacro, 1, 0xFF, 0x13, NEXT) +OPDEF(CEE_LDNULL, "ldnull", Pop0, PushRef, InlineNone, IPrimitive, 1, 0xFF, 0x14, NEXT) +OPDEF(CEE_LDC_I4_M1, "ldc.i4.m1", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x15, NEXT) +OPDEF(CEE_LDC_I4_0, "ldc.i4.0", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x16, NEXT) +OPDEF(CEE_LDC_I4_1, "ldc.i4.1", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x17, NEXT) +OPDEF(CEE_LDC_I4_2, "ldc.i4.2", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x18, NEXT) +OPDEF(CEE_LDC_I4_3, "ldc.i4.3", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x19, NEXT) +OPDEF(CEE_LDC_I4_4, "ldc.i4.4", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x1A, NEXT) +OPDEF(CEE_LDC_I4_5, "ldc.i4.5", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x1B, NEXT) +OPDEF(CEE_LDC_I4_6, "ldc.i4.6", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x1C, NEXT) +OPDEF(CEE_LDC_I4_7, "ldc.i4.7", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x1D, NEXT) +OPDEF(CEE_LDC_I4_8, "ldc.i4.8", Pop0, PushI, InlineNone, IMacro, 1, 0xFF, 0x1E, NEXT) +OPDEF(CEE_LDC_I4_S, "ldc.i4.s", Pop0, PushI, ShortInlineI, IMacro, 1, 0xFF, 0x1F, NEXT) +OPDEF(CEE_LDC_I4, "ldc.i4", Pop0, PushI, InlineI, IPrimitive, 1, 0xFF, 0x20, NEXT) +OPDEF(CEE_LDC_I8, "ldc.i8", Pop0, PushI8, InlineI8, IPrimitive, 1, 0xFF, 0x21, NEXT) +OPDEF(CEE_LDC_R4, "ldc.r4", Pop0, PushR4, ShortInlineR, IPrimitive, 1, 0xFF, 0x22, NEXT) +OPDEF(CEE_LDC_R8, "ldc.r8", Pop0, PushR8, InlineR, IPrimitive, 1, 0xFF, 0x23, NEXT) +OPDEF(CEE_UNUSED49, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x24, NEXT) +OPDEF(CEE_DUP, "dup", Pop1, Push1+Push1, InlineNone, IPrimitive, 1, 0xFF, 0x25, NEXT) +OPDEF(CEE_POP, "pop", Pop1, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x26, NEXT) +OPDEF(CEE_JMP, "jmp", Pop0, Push0, InlineMethod, IPrimitive, 1, 0xFF, 0x27, CALL) +OPDEF(CEE_CALL, "call", VarPop, VarPush, InlineMethod, IPrimitive, 1, 0xFF, 0x28, CALL) +OPDEF(CEE_CALLI, "calli", VarPop, VarPush, InlineSig, IPrimitive, 1, 0xFF, 0x29, CALL) +OPDEF(CEE_RET, "ret", VarPop, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x2A, RETURN) +OPDEF(CEE_BR_S, "br.s", Pop0, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x2B, BRANCH) +OPDEF(CEE_BRFALSE_S, "brfalse.s", PopI, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x2C, COND_BRANCH) +OPDEF(CEE_BRTRUE_S, "brtrue.s", PopI, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x2D, COND_BRANCH) +OPDEF(CEE_BEQ_S, "beq.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x2E, COND_BRANCH) +OPDEF(CEE_BGE_S, "bge.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x2F, COND_BRANCH) +OPDEF(CEE_BGT_S, "bgt.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x30, COND_BRANCH) +OPDEF(CEE_BLE_S, "ble.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x31, COND_BRANCH) +OPDEF(CEE_BLT_S, "blt.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x32, COND_BRANCH) +OPDEF(CEE_BNE_UN_S, "bne.un.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x33, COND_BRANCH) +OPDEF(CEE_BGE_UN_S, "bge.un.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x34, COND_BRANCH) +OPDEF(CEE_BGT_UN_S, "bgt.un.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x35, COND_BRANCH) +OPDEF(CEE_BLE_UN_S, "ble.un.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x36, COND_BRANCH) +OPDEF(CEE_BLT_UN_S, "blt.un.s", Pop1+Pop1, Push0, ShortInlineBrTarget,IMacro, 1, 0xFF, 0x37, COND_BRANCH) +OPDEF(CEE_BR, "br", Pop0, Push0, InlineBrTarget, IPrimitive, 1, 0xFF, 0x38, BRANCH) +OPDEF(CEE_BRFALSE, "brfalse", PopI, Push0, InlineBrTarget, IPrimitive, 1, 0xFF, 0x39, COND_BRANCH) +OPDEF(CEE_BRTRUE, "brtrue", PopI, Push0, InlineBrTarget, IPrimitive, 1, 0xFF, 0x3A, COND_BRANCH) +OPDEF(CEE_BEQ, "beq", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x3B, COND_BRANCH) +OPDEF(CEE_BGE, "bge", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x3C, COND_BRANCH) +OPDEF(CEE_BGT, "bgt", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x3D, COND_BRANCH) +OPDEF(CEE_BLE, "ble", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x3E, COND_BRANCH) +OPDEF(CEE_BLT, "blt", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x3F, COND_BRANCH) +OPDEF(CEE_BNE_UN, "bne.un", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x40, COND_BRANCH) +OPDEF(CEE_BGE_UN, "bge.un", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x41, COND_BRANCH) +OPDEF(CEE_BGT_UN, "bgt.un", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x42, COND_BRANCH) +OPDEF(CEE_BLE_UN, "ble.un", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x43, COND_BRANCH) +OPDEF(CEE_BLT_UN, "blt.un", Pop1+Pop1, Push0, InlineBrTarget, IMacro, 1, 0xFF, 0x44, COND_BRANCH) +OPDEF(CEE_SWITCH, "switch", PopI, Push0, InlineSwitch, IPrimitive, 1, 0xFF, 0x45, COND_BRANCH) +OPDEF(CEE_LDIND_I1, "ldind.i1", PopI, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x46, NEXT) +OPDEF(CEE_LDIND_U1, "ldind.u1", PopI, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x47, NEXT) +OPDEF(CEE_LDIND_I2, "ldind.i2", PopI, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x48, NEXT) +OPDEF(CEE_LDIND_U2, "ldind.u2", PopI, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x49, NEXT) +OPDEF(CEE_LDIND_I4, "ldind.i4", PopI, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x4A, NEXT) +OPDEF(CEE_LDIND_U4, "ldind.u4", PopI, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x4B, NEXT) +OPDEF(CEE_LDIND_I8, "ldind.i8", PopI, PushI8, InlineNone, IPrimitive, 1, 0xFF, 0x4C, NEXT) +OPDEF(CEE_LDIND_I, "ldind.i", PopI, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x4D, NEXT) +OPDEF(CEE_LDIND_R4, "ldind.r4", PopI, PushR4, InlineNone, IPrimitive, 1, 0xFF, 0x4E, NEXT) +OPDEF(CEE_LDIND_R8, "ldind.r8", PopI, PushR8, InlineNone, IPrimitive, 1, 0xFF, 0x4F, NEXT) +OPDEF(CEE_LDIND_REF, "ldind.ref", PopI, PushRef, InlineNone, IPrimitive, 1, 0xFF, 0x50, NEXT) +OPDEF(CEE_STIND_REF, "stind.ref", PopI+PopI, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x51, NEXT) +OPDEF(CEE_STIND_I1, "stind.i1", PopI+PopI, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x52, NEXT) +OPDEF(CEE_STIND_I2, "stind.i2", PopI+PopI, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x53, NEXT) +OPDEF(CEE_STIND_I4, "stind.i4", PopI+PopI, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x54, NEXT) +OPDEF(CEE_STIND_I8, "stind.i8", PopI+PopI8, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x55, NEXT) +OPDEF(CEE_STIND_R4, "stind.r4", PopI+PopR4, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x56, NEXT) +OPDEF(CEE_STIND_R8, "stind.r8", PopI+PopR8, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x57, NEXT) +OPDEF(CEE_ADD, "add", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x58, NEXT) +OPDEF(CEE_SUB, "sub", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x59, NEXT) +OPDEF(CEE_MUL, "mul", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x5A, NEXT) +OPDEF(CEE_DIV, "div", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x5B, NEXT) +OPDEF(CEE_DIV_UN, "div.un", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x5C, NEXT) +OPDEF(CEE_REM, "rem", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x5D, NEXT) +OPDEF(CEE_REM_UN, "rem.un", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x5E, NEXT) +OPDEF(CEE_AND, "and", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x5F, NEXT) +OPDEF(CEE_OR, "or", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x60, NEXT) +OPDEF(CEE_XOR, "xor", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x61, NEXT) +OPDEF(CEE_SHL, "shl", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x62, NEXT) +OPDEF(CEE_SHR, "shr", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x63, NEXT) +OPDEF(CEE_SHR_UN, "shr.un", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x64, NEXT) +OPDEF(CEE_NEG, "neg", Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x65, NEXT) +OPDEF(CEE_NOT, "not", Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0x66, NEXT) +OPDEF(CEE_CONV_I1, "conv.i1", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x67, NEXT) +OPDEF(CEE_CONV_I2, "conv.i2", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x68, NEXT) +OPDEF(CEE_CONV_I4, "conv.i4", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x69, NEXT) +OPDEF(CEE_CONV_I8, "conv.i8", Pop1, PushI8, InlineNone, IPrimitive, 1, 0xFF, 0x6A, NEXT) +OPDEF(CEE_CONV_R4, "conv.r4", Pop1, PushR4, InlineNone, IPrimitive, 1, 0xFF, 0x6B, NEXT) +OPDEF(CEE_CONV_R8, "conv.r8", Pop1, PushR8, InlineNone, IPrimitive, 1, 0xFF, 0x6C, NEXT) +OPDEF(CEE_CONV_U4, "conv.u4", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x6D, NEXT) +OPDEF(CEE_CONV_U8, "conv.u8", Pop1, PushI8, InlineNone, IPrimitive, 1, 0xFF, 0x6E, NEXT) +OPDEF(CEE_CALLVIRT, "callvirt", VarPop, VarPush, InlineMethod, IObjModel, 1, 0xFF, 0x6F, CALL) +OPDEF(CEE_CPOBJ, "cpobj", PopI+PopI, Push0, InlineType, IObjModel, 1, 0xFF, 0x70, NEXT) +OPDEF(CEE_LDOBJ, "ldobj", PopI, Push1, InlineType, IObjModel, 1, 0xFF, 0x71, NEXT) +OPDEF(CEE_LDSTR, "ldstr", Pop0, PushRef, InlineString, IObjModel, 1, 0xFF, 0x72, NEXT) +OPDEF(CEE_NEWOBJ, "newobj", VarPop, PushRef, InlineMethod, IObjModel, 1, 0xFF, 0x73, CALL) +OPDEF(CEE_CASTCLASS, "castclass", PopRef, PushRef, InlineType, IObjModel, 1, 0xFF, 0x74, NEXT) +OPDEF(CEE_ISINST, "isinst", PopRef, PushI, InlineType, IObjModel, 1, 0xFF, 0x75, NEXT) +OPDEF(CEE_CONV_R_UN, "conv.r.un", Pop1, PushR8, InlineNone, IPrimitive, 1, 0xFF, 0x76, NEXT) +OPDEF(CEE_UNUSED58, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x77, NEXT) +OPDEF(CEE_UNUSED1, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0x78, NEXT) +OPDEF(CEE_UNBOX, "unbox", PopRef, PushI, InlineType, IPrimitive, 1, 0xFF, 0x79, NEXT) +OPDEF(CEE_THROW, "throw", PopRef, Push0, InlineNone, IObjModel, 1, 0xFF, 0x7A, THROW) +OPDEF(CEE_LDFLD, "ldfld", PopRef, Push1, InlineField, IObjModel, 1, 0xFF, 0x7B, NEXT) +OPDEF(CEE_LDFLDA, "ldflda", PopRef, PushI, InlineField, IObjModel, 1, 0xFF, 0x7C, NEXT) +OPDEF(CEE_STFLD, "stfld", PopRef+Pop1, Push0, InlineField, IObjModel, 1, 0xFF, 0x7D, NEXT) +OPDEF(CEE_LDSFLD, "ldsfld", Pop0, Push1, InlineField, IObjModel, 1, 0xFF, 0x7E, NEXT) +OPDEF(CEE_LDSFLDA, "ldsflda", Pop0, PushI, InlineField, IObjModel, 1, 0xFF, 0x7F, NEXT) +OPDEF(CEE_STSFLD, "stsfld", Pop1, Push0, InlineField, IObjModel, 1, 0xFF, 0x80, NEXT) +OPDEF(CEE_STOBJ, "stobj", PopI+Pop1, Push0, InlineType, IPrimitive, 1, 0xFF, 0x81, NEXT) +OPDEF(CEE_CONV_OVF_I1_UN, "conv.ovf.i1.un", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x82, NEXT) +OPDEF(CEE_CONV_OVF_I2_UN, "conv.ovf.i2.un", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x83, NEXT) +OPDEF(CEE_CONV_OVF_I4_UN, "conv.ovf.i4.un", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x84, NEXT) +OPDEF(CEE_CONV_OVF_I8_UN, "conv.ovf.i8.un", Pop1, PushI8, InlineNone, IPrimitive, 1, 0xFF, 0x85, NEXT) +OPDEF(CEE_CONV_OVF_U1_UN, "conv.ovf.u1.un", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x86, NEXT) +OPDEF(CEE_CONV_OVF_U2_UN, "conv.ovf.u2.un", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x87, NEXT) +OPDEF(CEE_CONV_OVF_U4_UN, "conv.ovf.u4.un", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x88, NEXT) +OPDEF(CEE_CONV_OVF_U8_UN, "conv.ovf.u8.un", Pop1, PushI8, InlineNone, IPrimitive, 1, 0xFF, 0x89, NEXT) +OPDEF(CEE_CONV_OVF_I_UN, "conv.ovf.i.un", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x8A, NEXT) +OPDEF(CEE_CONV_OVF_U_UN, "conv.ovf.u.un", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0x8B, NEXT) +OPDEF(CEE_BOX, "box", Pop1, PushRef, InlineType, IPrimitive, 1, 0xFF, 0x8C, NEXT) +OPDEF(CEE_NEWARR, "newarr", PopI, PushRef, InlineType, IObjModel, 1, 0xFF, 0x8D, NEXT) +OPDEF(CEE_LDLEN, "ldlen", PopRef, PushI, InlineNone, IObjModel, 1, 0xFF, 0x8E, NEXT) +OPDEF(CEE_LDELEMA, "ldelema", PopRef+PopI, PushI, InlineType, IObjModel, 1, 0xFF, 0x8F, NEXT) +OPDEF(CEE_LDELEM_I1, "ldelem.i1", PopRef+PopI, PushI, InlineNone, IObjModel, 1, 0xFF, 0x90, NEXT) +OPDEF(CEE_LDELEM_U1, "ldelem.u1", PopRef+PopI, PushI, InlineNone, IObjModel, 1, 0xFF, 0x91, NEXT) +OPDEF(CEE_LDELEM_I2, "ldelem.i2", PopRef+PopI, PushI, InlineNone, IObjModel, 1, 0xFF, 0x92, NEXT) +OPDEF(CEE_LDELEM_U2, "ldelem.u2", PopRef+PopI, PushI, InlineNone, IObjModel, 1, 0xFF, 0x93, NEXT) +OPDEF(CEE_LDELEM_I4, "ldelem.i4", PopRef+PopI, PushI, InlineNone, IObjModel, 1, 0xFF, 0x94, NEXT) +OPDEF(CEE_LDELEM_U4, "ldelem.u4", PopRef+PopI, PushI, InlineNone, IObjModel, 1, 0xFF, 0x95, NEXT) +OPDEF(CEE_LDELEM_I8, "ldelem.i8", PopRef+PopI, PushI8, InlineNone, IObjModel, 1, 0xFF, 0x96, NEXT) +OPDEF(CEE_LDELEM_I, "ldelem.i", PopRef+PopI, PushI, InlineNone, IObjModel, 1, 0xFF, 0x97, NEXT) +OPDEF(CEE_LDELEM_R4, "ldelem.r4", PopRef+PopI, PushR4, InlineNone, IObjModel, 1, 0xFF, 0x98, NEXT) +OPDEF(CEE_LDELEM_R8, "ldelem.r8", PopRef+PopI, PushR8, InlineNone, IObjModel, 1, 0xFF, 0x99, NEXT) +OPDEF(CEE_LDELEM_REF, "ldelem.ref", PopRef+PopI, PushRef, InlineNone, IObjModel, 1, 0xFF, 0x9A, NEXT) +OPDEF(CEE_STELEM_I, "stelem.i", PopRef+PopI+PopI, Push0, InlineNone, IObjModel, 1, 0xFF, 0x9B, NEXT) +OPDEF(CEE_STELEM_I1, "stelem.i1", PopRef+PopI+PopI, Push0, InlineNone, IObjModel, 1, 0xFF, 0x9C, NEXT) +OPDEF(CEE_STELEM_I2, "stelem.i2", PopRef+PopI+PopI, Push0, InlineNone, IObjModel, 1, 0xFF, 0x9D, NEXT) +OPDEF(CEE_STELEM_I4, "stelem.i4", PopRef+PopI+PopI, Push0, InlineNone, IObjModel, 1, 0xFF, 0x9E, NEXT) +OPDEF(CEE_STELEM_I8, "stelem.i8", PopRef+PopI+PopI8, Push0, InlineNone, IObjModel, 1, 0xFF, 0x9F, NEXT) +OPDEF(CEE_STELEM_R4, "stelem.r4", PopRef+PopI+PopR4, Push0, InlineNone, IObjModel, 1, 0xFF, 0xA0, NEXT) +OPDEF(CEE_STELEM_R8, "stelem.r8", PopRef+PopI+PopR8, Push0, InlineNone, IObjModel, 1, 0xFF, 0xA1, NEXT) +OPDEF(CEE_STELEM_REF, "stelem.ref", PopRef+PopI+PopRef, Push0, InlineNone, IObjModel, 1, 0xFF, 0xA2, NEXT) +OPDEF(CEE_LDELEM, "ldelem", PopRef+PopI, Push1, InlineType, IObjModel, 1, 0xFF, 0xA3, NEXT) +OPDEF(CEE_STELEM, "stelem", PopRef+PopI+Pop1, Push0, InlineType, IObjModel, 1, 0xFF, 0xA4, NEXT) +OPDEF(CEE_UNBOX_ANY, "unbox.any", PopRef, Push1, InlineType, IObjModel, 1, 0xFF, 0xA5, NEXT) +OPDEF(CEE_UNUSED5, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xA6, NEXT) +OPDEF(CEE_UNUSED6, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xA7, NEXT) +OPDEF(CEE_UNUSED7, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xA8, NEXT) +OPDEF(CEE_UNUSED8, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xA9, NEXT) +OPDEF(CEE_UNUSED9, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xAA, NEXT) +OPDEF(CEE_UNUSED10, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xAB, NEXT) +OPDEF(CEE_UNUSED11, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xAC, NEXT) +OPDEF(CEE_UNUSED12, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xAD, NEXT) +OPDEF(CEE_UNUSED13, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xAE, NEXT) +OPDEF(CEE_UNUSED14, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xAF, NEXT) +OPDEF(CEE_UNUSED15, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xB0, NEXT) +OPDEF(CEE_UNUSED16, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xB1, NEXT) +OPDEF(CEE_UNUSED17, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xB2, NEXT) +OPDEF(CEE_CONV_OVF_I1, "conv.ovf.i1", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xB3, NEXT) +OPDEF(CEE_CONV_OVF_U1, "conv.ovf.u1", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xB4, NEXT) +OPDEF(CEE_CONV_OVF_I2, "conv.ovf.i2", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xB5, NEXT) +OPDEF(CEE_CONV_OVF_U2, "conv.ovf.u2", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xB6, NEXT) +OPDEF(CEE_CONV_OVF_I4, "conv.ovf.i4", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xB7, NEXT) +OPDEF(CEE_CONV_OVF_U4, "conv.ovf.u4", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xB8, NEXT) +OPDEF(CEE_CONV_OVF_I8, "conv.ovf.i8", Pop1, PushI8, InlineNone, IPrimitive, 1, 0xFF, 0xB9, NEXT) +OPDEF(CEE_CONV_OVF_U8, "conv.ovf.u8", Pop1, PushI8, InlineNone, IPrimitive, 1, 0xFF, 0xBA, NEXT) +OPDEF(CEE_UNUSED50, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xBB, NEXT) +OPDEF(CEE_UNUSED18, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xBC, NEXT) +OPDEF(CEE_UNUSED19, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xBD, NEXT) +OPDEF(CEE_UNUSED20, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xBE, NEXT) +OPDEF(CEE_UNUSED21, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xBF, NEXT) +OPDEF(CEE_UNUSED22, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xC0, NEXT) +OPDEF(CEE_UNUSED23, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xC1, NEXT) +OPDEF(CEE_REFANYVAL, "refanyval", Pop1, PushI, InlineType, IPrimitive, 1, 0xFF, 0xC2, NEXT) +OPDEF(CEE_CKFINITE, "ckfinite", Pop1, PushR8, InlineNone, IPrimitive, 1, 0xFF, 0xC3, NEXT) +OPDEF(CEE_UNUSED24, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xC4, NEXT) +OPDEF(CEE_UNUSED25, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xC5, NEXT) +OPDEF(CEE_MKREFANY, "mkrefany", PopI, Push1, InlineType, IPrimitive, 1, 0xFF, 0xC6, NEXT) +OPDEF(CEE_UNUSED59, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xC7, NEXT) +OPDEF(CEE_UNUSED60, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xC8, NEXT) +OPDEF(CEE_UNUSED61, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xC9, NEXT) +OPDEF(CEE_UNUSED62, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xCA, NEXT) +OPDEF(CEE_UNUSED63, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xCB, NEXT) +OPDEF(CEE_UNUSED64, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xCC, NEXT) +OPDEF(CEE_UNUSED65, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xCD, NEXT) +OPDEF(CEE_UNUSED66, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xCE, NEXT) +OPDEF(CEE_UNUSED67, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xCF, NEXT) +OPDEF(CEE_LDTOKEN, "ldtoken", Pop0, PushI, InlineTok, IPrimitive, 1, 0xFF, 0xD0, NEXT) +OPDEF(CEE_CONV_U2, "conv.u2", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xD1, NEXT) +OPDEF(CEE_CONV_U1, "conv.u1", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xD2, NEXT) +OPDEF(CEE_CONV_I, "conv.i", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xD3, NEXT) +OPDEF(CEE_CONV_OVF_I, "conv.ovf.i", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xD4, NEXT) +OPDEF(CEE_CONV_OVF_U, "conv.ovf.u", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xD5, NEXT) +OPDEF(CEE_ADD_OVF, "add.ovf", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0xD6, NEXT) +OPDEF(CEE_ADD_OVF_UN, "add.ovf.un", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0xD7, NEXT) +OPDEF(CEE_MUL_OVF, "mul.ovf", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0xD8, NEXT) +OPDEF(CEE_MUL_OVF_UN, "mul.ovf.un", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0xD9, NEXT) +OPDEF(CEE_SUB_OVF, "sub.ovf", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0xDA, NEXT) +OPDEF(CEE_SUB_OVF_UN, "sub.ovf.un", Pop1+Pop1, Push1, InlineNone, IPrimitive, 1, 0xFF, 0xDB, NEXT) +OPDEF(CEE_ENDFINALLY, "endfinally", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xDC, RETURN) +OPDEF(CEE_LEAVE, "leave", Pop0, Push0, InlineBrTarget, IPrimitive, 1, 0xFF, 0xDD, BRANCH) +OPDEF(CEE_LEAVE_S, "leave.s", Pop0, Push0, ShortInlineBrTarget,IPrimitive, 1, 0xFF, 0xDE, BRANCH) +OPDEF(CEE_STIND_I, "stind.i", PopI+PopI, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xDF, NEXT) +OPDEF(CEE_CONV_U, "conv.u", Pop1, PushI, InlineNone, IPrimitive, 1, 0xFF, 0xE0, NEXT) +OPDEF(CEE_UNUSED26, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xE1, NEXT) +OPDEF(CEE_UNUSED27, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xE2, NEXT) +OPDEF(CEE_UNUSED28, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xE3, NEXT) +OPDEF(CEE_UNUSED29, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xE4, NEXT) +OPDEF(CEE_UNUSED30, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xE5, NEXT) +OPDEF(CEE_UNUSED31, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xE6, NEXT) +OPDEF(CEE_UNUSED32, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xE7, NEXT) +OPDEF(CEE_UNUSED33, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xE8, NEXT) +OPDEF(CEE_UNUSED34, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xE9, NEXT) +OPDEF(CEE_UNUSED35, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xEA, NEXT) +OPDEF(CEE_UNUSED36, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xEB, NEXT) +OPDEF(CEE_UNUSED37, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xEC, NEXT) +OPDEF(CEE_UNUSED38, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xED, NEXT) +OPDEF(CEE_UNUSED39, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xEE, NEXT) +OPDEF(CEE_UNUSED40, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xEF, NEXT) +OPDEF(CEE_UNUSED41, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xF0, NEXT) +OPDEF(CEE_UNUSED42, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xF1, NEXT) +OPDEF(CEE_UNUSED43, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xF2, NEXT) +OPDEF(CEE_UNUSED44, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xF3, NEXT) +OPDEF(CEE_UNUSED45, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xF4, NEXT) +OPDEF(CEE_UNUSED46, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xF5, NEXT) +OPDEF(CEE_UNUSED47, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xF6, NEXT) +OPDEF(CEE_UNUSED48, "unused", Pop0, Push0, InlineNone, IPrimitive, 1, 0xFF, 0xF7, NEXT) +OPDEF(CEE_PREFIX7, "prefix7", Pop0, Push0, InlineNone, IInternal, 1, 0xFF, 0xF8, META) +OPDEF(CEE_PREFIX6, "prefix6", Pop0, Push0, InlineNone, IInternal, 1, 0xFF, 0xF9, META) +OPDEF(CEE_PREFIX5, "prefix5", Pop0, Push0, InlineNone, IInternal, 1, 0xFF, 0xFA, META) +OPDEF(CEE_PREFIX4, "prefix4", Pop0, Push0, InlineNone, IInternal, 1, 0xFF, 0xFB, META) +OPDEF(CEE_PREFIX3, "prefix3", Pop0, Push0, InlineNone, IInternal, 1, 0xFF, 0xFC, META) +OPDEF(CEE_PREFIX2, "prefix2", Pop0, Push0, InlineNone, IInternal, 1, 0xFF, 0xFD, META) +OPDEF(CEE_PREFIX1, "prefix1", Pop0, Push0, InlineNone, IInternal, 1, 0xFF, 0xFE, META) +OPDEF(CEE_PREFIXREF, "prefixref", Pop0, Push0, InlineNone, IInternal, 1, 0xFF, 0xFF, META) + +OPDEF(CEE_ARGLIST, "arglist", Pop0, PushI, InlineNone, IPrimitive, 2, 0xFE, 0x00, NEXT) +OPDEF(CEE_CEQ, "ceq", Pop1+Pop1, PushI, InlineNone, IPrimitive, 2, 0xFE, 0x01, NEXT) +OPDEF(CEE_CGT, "cgt", Pop1+Pop1, PushI, InlineNone, IPrimitive, 2, 0xFE, 0x02, NEXT) +OPDEF(CEE_CGT_UN, "cgt.un", Pop1+Pop1, PushI, InlineNone, IPrimitive, 2, 0xFE, 0x03, NEXT) +OPDEF(CEE_CLT, "clt", Pop1+Pop1, PushI, InlineNone, IPrimitive, 2, 0xFE, 0x04, NEXT) +OPDEF(CEE_CLT_UN, "clt.un", Pop1+Pop1, PushI, InlineNone, IPrimitive, 2, 0xFE, 0x05, NEXT) +OPDEF(CEE_LDFTN, "ldftn", Pop0, PushI, InlineMethod, IPrimitive, 2, 0xFE, 0x06, NEXT) +OPDEF(CEE_LDVIRTFTN, "ldvirtftn", PopRef, PushI, InlineMethod, IPrimitive, 2, 0xFE, 0x07, NEXT) +OPDEF(CEE_UNUSED56, "unused", Pop0, Push0, InlineNone, IPrimitive, 2, 0xFE, 0x08, NEXT) +OPDEF(CEE_LDARG, "ldarg", Pop0, Push1, InlineVar, IPrimitive, 2, 0xFE, 0x09, NEXT) +OPDEF(CEE_LDARGA, "ldarga", Pop0, PushI, InlineVar, IPrimitive, 2, 0xFE, 0x0A, NEXT) +OPDEF(CEE_STARG, "starg", Pop1, Push0, InlineVar, IPrimitive, 2, 0xFE, 0x0B, NEXT) +OPDEF(CEE_LDLOC, "ldloc", Pop0, Push1, InlineVar, IPrimitive, 2, 0xFE, 0x0C, NEXT) +OPDEF(CEE_LDLOCA, "ldloca", Pop0, PushI, InlineVar, IPrimitive, 2, 0xFE, 0x0D, NEXT) +OPDEF(CEE_STLOC, "stloc", Pop1, Push0, InlineVar, IPrimitive, 2, 0xFE, 0x0E, NEXT) +OPDEF(CEE_LOCALLOC, "localloc", PopI, PushI, InlineNone, IPrimitive, 2, 0xFE, 0x0F, NEXT) +OPDEF(CEE_UNUSED57, "unused", Pop0, Push0, InlineNone, IPrimitive, 2, 0xFE, 0x10, NEXT) +OPDEF(CEE_ENDFILTER, "endfilter", PopI, Push0, InlineNone, IPrimitive, 2, 0xFE, 0x11, RETURN) +OPDEF(CEE_UNALIGNED, "unaligned.", Pop0, Push0, ShortInlineI, IPrefix, 2, 0xFE, 0x12, META) +OPDEF(CEE_VOLATILE, "volatile.", Pop0, Push0, InlineNone, IPrefix, 2, 0xFE, 0x13, META) +OPDEF(CEE_TAILCALL, "tail.", Pop0, Push0, InlineNone, IPrefix, 2, 0xFE, 0x14, META) +OPDEF(CEE_INITOBJ, "initobj", PopI, Push0, InlineType, IObjModel, 2, 0xFE, 0x15, NEXT) +OPDEF(CEE_CONSTRAINED, "constrained.", Pop0, Push0, InlineType, IPrefix, 2, 0xFE, 0x16, META) +OPDEF(CEE_CPBLK, "cpblk", PopI+PopI+PopI, Push0, InlineNone, IPrimitive, 2, 0xFE, 0x17, NEXT) +OPDEF(CEE_INITBLK, "initblk", PopI+PopI+PopI, Push0, InlineNone, IPrimitive, 2, 0xFE, 0x18, NEXT) +OPDEF(CEE_UNUSED69, "unused", Pop0, Push0, InlineNone, IPrimitive, 2, 0xFE, 0x19, NEXT) +OPDEF(CEE_RETHROW, "rethrow", Pop0, Push0, InlineNone, IObjModel, 2, 0xFE, 0x1A, THROW) +OPDEF(CEE_UNUSED51, "unused", Pop0, Push0, InlineNone, IPrimitive, 2, 0xFE, 0x1B, NEXT) +OPDEF(CEE_SIZEOF, "sizeof", Pop0, PushI, InlineType, IPrimitive, 2, 0xFE, 0x1C, NEXT) +OPDEF(CEE_REFANYTYPE, "refanytype", Pop1, PushI, InlineNone, IPrimitive, 2, 0xFE, 0x1D, NEXT) +OPDEF(CEE_READONLY, "readonly.", Pop0, Push0, InlineNone, IPrefix, 2, 0xFE, 0x1E, META) +OPDEF(CEE_UNUSED53, "unused", Pop0, Push0, InlineNone, IPrimitive, 2, 0xFE, 0x1F, NEXT) +OPDEF(CEE_UNUSED54, "unused", Pop0, Push0, InlineNone, IPrimitive, 2, 0xFE, 0x20, NEXT) +OPDEF(CEE_UNUSED55, "unused", Pop0, Push0, InlineNone, IPrimitive, 2, 0xFE, 0x21, NEXT) +OPDEF(CEE_UNUSED70, "unused", Pop0, Push0, InlineNone, IPrimitive, 2, 0xFE, 0x22, NEXT) + +// These are not real opcodes, but they are handy internally in the EE + +OPDEF(CEE_ILLEGAL, "illegal", Pop0, Push0, InlineNone, IInternal, 0, MOOT, MOOT, META) +OPDEF(CEE_MACRO_END, "endmac", Pop0, Push0, InlineNone, IInternal, 0, MOOT, MOOT, META) + +#ifndef OPALIAS +#define _OPALIAS_DEFINED_ +#define OPALIAS(canonicalName, stringName, realOpcode) +#endif + +OPALIAS(CEE_BRNULL, "brnull", CEE_BRFALSE) +OPALIAS(CEE_BRNULL_S, "brnull.s", CEE_BRFALSE_S) +OPALIAS(CEE_BRZERO, "brzero", CEE_BRFALSE) +OPALIAS(CEE_BRZERO_S, "brzero.s", CEE_BRFALSE_S) +OPALIAS(CEE_BRINST, "brinst", CEE_BRTRUE) +OPALIAS(CEE_BRINST_S, "brinst.s", CEE_BRTRUE_S) +OPALIAS(CEE_LDIND_U8, "ldind.u8", CEE_LDIND_I8) +OPALIAS(CEE_LDELEM_U8, "ldelem.u8", CEE_LDELEM_I8) +OPALIAS(CEE_LDELEM_ANY, "ldelem.any", CEE_LDELEM) +OPALIAS(CEE_STELEM_ANY, "stelem.any", CEE_STELEM) +OPALIAS(CEE_LDC_I4_M1x, "ldc.i4.M1", CEE_LDC_I4_M1) +OPALIAS(CEE_ENDFAULT, "endfault", CEE_ENDFINALLY) + +#ifdef _OPALIAS_DEFINED_ +#undef OPALIAS +#undef _OPALIAS_DEFINED_ +#endif + diff --git a/source/native/nf-interpreter/src/CLR/Include/stdafx.h b/source/native/nf-interpreter/src/CLR/Include/stdafx.h new file mode 100644 index 00000000..d680969b --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Include/stdafx.h @@ -0,0 +1,11 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//////////////////////////////////////////////////////////////////////////// +// This is header file is empty on purpose. // +// It has to exist here in order to keep Visual Studio C++ compiler happy // +// to use pre-processed headers for WIN32 projects // +//////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/src/CLR/Messaging/Messaging-vs2019.vcxproj b/source/native/nf-interpreter/src/CLR/Messaging/Messaging-vs2019.vcxproj new file mode 100644 index 00000000..5349bd2f --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Messaging/Messaging-vs2019.vcxproj @@ -0,0 +1,164 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + + {2337c4a4-3ab4-4014-9c29-9ebe32f4510e} + false + false + + + + {131001E3-0201-451F-A87B-951D1C5C3EEE} + Win32Proj + Messaging + 10.0.17763.0 + Messaging + + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + false + v142 + true + Unicode + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + false + v142 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(SolutionDir)$(Configuration)\ + $(IntDir) + + + $(SolutionDir)$(Configuration)\ + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\CorLib;..\..\HAL\Include;..\..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\CorLib;..\..\HAL\Include;..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Messaging/Messaging-vs2019.vcxproj.filters b/source/native/nf-interpreter/src/CLR/Messaging/Messaging-vs2019.vcxproj.filters new file mode 100644 index 00000000..2056f148 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Messaging/Messaging-vs2019.vcxproj.filters @@ -0,0 +1,22 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Messaging/Messaging.cpp b/source/native/nf-interpreter/src/CLR/Messaging/Messaging.cpp new file mode 100644 index 00000000..e870e3dd --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Messaging/Messaging.cpp @@ -0,0 +1,416 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include +#include +#include +#include +#include + +// the Arm 3.0 compiler drags in a bunch of ABI methods (for initialization) if struct arrays are not initialized +CLR_UINT32 g_scratchMessaging[ sizeof(CLR_Messaging) ]; +CLR_Messaging *g_CLR_Messaging; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +//--// + +static const CLR_Messaging_CommandHandlerLookup c_Messaging_Lookup_Request[] = +{ + { CLR_Messaging::Messaging_Query, CLR_Messaging_Commands::c_Messaging_Query }, + { CLR_Messaging::Messaging_Send, CLR_Messaging_Commands::c_Messaging_Send }, + { CLR_Messaging::Messaging_Reply, CLR_Messaging_Commands::c_Messaging_Reply }, +}; + +static const CLR_Messaging_CommandHandlerLookup c_Messaging_Lookup_Reply[] = +{ + { CLR_Messaging::Messaging_Query, CLR_Messaging_Commands::c_Messaging_Query }, + { CLR_Messaging::Messaging_Send, CLR_Messaging_Commands::c_Messaging_Send }, + { CLR_Messaging::Messaging_Reply, CLR_Messaging_Commands::c_Messaging_Reply }, +}; + + +//--// + +bool CLR_Messaging::AllocateAndQueueMessage( CLR_UINT32 cmd, unsigned int length, unsigned char* data, CLR_RT_HeapBlock_EndPoint::Port port, CLR_RT_HeapBlock_EndPoint::Address addr, CLR_UINT32 found ) +{ + NATIVE_PROFILE_CLR_MESSAGING(); + CLR_RT_HeapBlock_EndPoint::Message* rpc; + CLR_RT_HeapBlock_EndPoint* ep; + + if((ep = CLR_RT_HeapBlock_EndPoint::FindEndPoint( port )) == NULL) return false; + + { + CLR_RT_ProtectFromGC gc( *ep ); + + if((rpc = (CLR_RT_HeapBlock_EndPoint::Message*)CLR_RT_Memory::Allocate( sizeof(*rpc) + length, CLR_RT_HeapBlock::HB_CompactOnFailure )) == NULL) return false; + + rpc->ClearData(); + + rpc->m_cmd = cmd;; + rpc->m_addr = addr; + rpc->m_length = length; + rpc->m_found = found; + + if(data) memcpy( rpc->m_data, data, length ); + + ep->m_messages.LinkAtBack( rpc ); + + g_CLR_RT_ExecutionEngine.SignalEvents( CLR_RT_ExecutionEngine::c_Event_EndPoint ); + } + + return true; +} + + +bool CLR_Messaging::Messaging_Query( WP_Message* msg ) +{ + NATIVE_PROFILE_CLR_MESSAGING(); + CLR_Messaging_Commands::Messaging_Query* cmd = (CLR_Messaging_Commands::Messaging_Query*)msg->m_payload; + CLR_Messaging_Commands::Messaging_Query::Reply res; + CLR_RT_HeapBlock_EndPoint* ep = CLR_RT_HeapBlock_EndPoint::FindEndPoint( cmd->m_addr.m_to ); + + res.m_found = (ep != NULL); + res.m_addr = cmd->m_addr; + + WP_ReplyToCommand(msg, true, false, &res, sizeof(res)); + + return true; +} + +bool CLR_Messaging::Messaging_Query__Reply( WP_Message* msg ) +{ + NATIVE_PROFILE_CLR_MESSAGING(); + + CLR_Messaging_Commands::Messaging_Query::Reply* cmd = (CLR_Messaging_Commands::Messaging_Query::Reply*)msg->m_payload; + + g_CLR_Messaging->AllocateAndQueueMessage( CLR_Messaging_Commands::c_Messaging_Query, 0, NULL, cmd->m_addr.m_from, cmd->m_addr, cmd->m_found ); + + return true; +} + +//--// + +bool CLR_Messaging::Messaging_Send( WP_Message* msg ) +{ + NATIVE_PROFILE_CLR_MESSAGING(); + CLR_Messaging_Commands::Messaging_Send* cmd = (CLR_Messaging_Commands::Messaging_Send*)msg->m_payload; + CLR_Messaging_Commands::Messaging_Send::Reply res; + CLR_UINT32 len; + bool fRes; + + len = msg->m_header.m_size - sizeof(cmd->m_addr); + + fRes = g_CLR_Messaging->AllocateAndQueueMessage( CLR_Messaging_Commands::c_Messaging_Send, len, cmd->m_data, cmd->m_addr.m_to, cmd->m_addr, false ); + + res.m_found = true; + res.m_addr = cmd->m_addr; + + WP_ReplyToCommand( msg, fRes, false, &res, sizeof(res) ); + + return true; +} + +bool CLR_Messaging::Messaging_Send__Reply( WP_Message* msg ) +{ + (void)msg; + + NATIVE_PROFILE_CLR_MESSAGING(); + // + // retransmission support is currently not implemented + // + + return true; +} + +//--// + +bool CLR_Messaging::Messaging_Reply( WP_Message* msg ) +{ + NATIVE_PROFILE_CLR_MESSAGING(); + CLR_Messaging_Commands::Messaging_Reply* cmd = (CLR_Messaging_Commands::Messaging_Reply*)msg->m_payload; + CLR_Messaging_Commands::Messaging_Reply::Reply res; + bool fRes; + CLR_UINT32 len; + + len = msg->m_header.m_size - sizeof(cmd->m_addr); + fRes = g_CLR_Messaging->AllocateAndQueueMessage( CLR_Messaging_Commands::c_Messaging_Reply, len, cmd->m_data, cmd->m_addr.m_from, cmd->m_addr, false ); + + res.m_found = true; + res.m_addr = cmd->m_addr; + + WP_ReplyToCommand( msg, fRes, false, &res, sizeof(res) ); + + return true; +} + +bool CLR_Messaging::Messaging_Reply__Reply( WP_Message* msg ) +{ + (void)msg; + + NATIVE_PROFILE_CLR_MESSAGING(); + // + // retransmission support is currently not implemented + // + + return true; +} + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + + +//--// + +bool CLR_Messaging::App_ProcessHeader( void* state, WP_Message* msg ) +{ + NATIVE_PROFILE_CLR_MESSAGING(); + CLR_Messaging* pThis = (CLR_Messaging*)state; + + Watchdog_Reset(); + + if( !pThis->ProcessHeader( msg ) ) + { + TRACE0("ProcessHeader() indicated invalid header!\n"); + return false; + } + + if(msg->m_header.m_size) + { + void* ptr = CLR_RT_Memory::Allocate( msg->m_header.m_size, CLR_RT_HeapBlock::HB_CompactOnFailure ); + + if(ptr == NULL) + { + TRACE0("Failed to allocate 0x%08X bytes for message payload!\n"); + return false; + } + + msg->m_payload = (unsigned char*)ptr; + } + + return true; +} + +bool CLR_Messaging::App_ProcessPayload( void* state, WP_Message* msg ) +{ + NATIVE_PROFILE_CLR_MESSAGING(); + CLR_Messaging* pThis = (CLR_Messaging*)state; + + Watchdog_Reset(); + + if(pThis->ProcessPayload( msg ) == false) + { + return false; + } + + return true; +} + +bool CLR_Messaging::App_Release( void* state, WP_Message* msg ) +{ + (void)state; + + NATIVE_PROFILE_CLR_MESSAGING(); + if(msg->m_payload != NULL) + { + CLR_RT_Memory::Release( msg->m_payload ); + + msg->m_payload = NULL; + } + + return true; +} + +//--// + + + + + + + + + + + + + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +HRESULT CLR_Messaging::CreateInstance() +{ + NATIVE_PROFILE_CLR_MESSAGING(); + NANOCLR_HEADER(); + + g_CLR_Messaging = (CLR_Messaging*)&g_scratchMessaging[ 0 ]; + + CLR_RT_Memory::ZeroFill( g_CLR_Messaging, sizeof(CLR_Messaging) ); + + g_CLR_Messaging->Initialize( + NULL, + 0, + NULL, + 0 + ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +//--// + +void CLR_Messaging::Initialize( + const CLR_Messaging_CommandHandlerLookup* requestLookup, + const CLR_UINT32 requestLookupCount, + const CLR_Messaging_CommandHandlerLookup* replyLookup, + const CLR_UINT32 replyLookupCount + ) +{ + if(m_fInitialized) return; + + m_Lookup_Requests[ 0 ].table = c_Messaging_Lookup_Request; + m_Lookup_Requests[ 0 ].size = ARRAYSIZE(c_Messaging_Lookup_Request); + + m_Lookup_Replies[ 0 ].table = c_Messaging_Lookup_Reply; + m_Lookup_Replies[ 0 ].size = ARRAYSIZE(c_Messaging_Lookup_Reply); + + m_port = HalSystemConfig.DebuggerPort; + + m_Lookup_Requests[ 1 ].table = requestLookup; + m_Lookup_Requests[ 1 ].size = requestLookupCount; + + m_Lookup_Replies[ 1 ].table = replyLookup; + m_Lookup_Replies[ 1 ].size = replyLookupCount; + + m_fDebuggerInitialized = (DebuggerPort_Initialize( HalSystemConfig.DebuggerPort ) != false); + + m_fInitialized = true; + +} + +HRESULT CLR_Messaging::DeleteInstance() +{ + NATIVE_PROFILE_CLR_MESSAGING(); + NANOCLR_HEADER(); + + g_CLR_Messaging->Cleanup(); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +void CLR_Messaging::Cleanup() +{ + NATIVE_PROFILE_CLR_MESSAGING(); + + if(!m_fInitialized) return; + + // Some devices cannot reset the USB controller so we need to allow them to skip uninitialization + // of the debug transport + if(!g_fDoNotUninitializeDebuggerPort) + { + DebuggerPort_Uninitialize( m_port ); + } + + m_fDebuggerInitialized = false; + + m_fInitialized = false; +} + +//--// + + + + + + + + + + +bool CLR_Messaging::ProcessHeader( WP_Message* msg ) +{ + (void)msg; + + NATIVE_PROFILE_CLR_MESSAGING(); + TRACE("MSG: 0x%08X\n", msg->m_header.m_cmd ); + return true; +} + +bool CLR_Messaging::ProcessPayload( WP_Message* msg ) +{ + NATIVE_PROFILE_CLR_MESSAGING(); + if(msg->m_header.m_flags & WP_Flags_c_NACK) + { + // + // Bad packet... + // + return true; + } + + //--// + + const CLR_Messaging_CommandHandlerLookups* tables; + int tableCount = 0; + + if(msg->m_header.m_flags & WP_Flags_c_Reply) + { + tables = m_Lookup_Replies; + tableCount = ARRAYSIZE(m_Lookup_Replies); + } + else + { + tables = m_Lookup_Requests; + tableCount = ARRAYSIZE(m_Lookup_Requests); + } + + while(tableCount-- > 0) + { + size_t num = tables->size; + const CLR_Messaging_CommandHandlerLookup* cmd = tables->table; + + while(num-- > 0 && cmd != NULL) + { + if(cmd->cmd == msg->m_header.m_cmd) + { + WP_ReplyToCommand(msg, (*(cmd->hnd))( msg ), false, NULL, 0); + return true; + } + + cmd++; + } + tables++; + } + + WP_ReplyToCommand(msg, false, false, NULL, 0); + + return true; +} + +// wrapper function for CLR_Messaging::ProcessPayload( +extern "C" int CLR_Messaging_ProcessPayload(WP_Message* msg) +{ + bool retValue = g_CLR_DBG_Debugger->m_messaging->ProcessPayload(msg); + return retValue; +} + +//--// + +bool CLR_Messaging::SendEvent( unsigned int cmd, unsigned int payloadSize, unsigned char* payload, unsigned int flags ) +{ + NATIVE_PROFILE_CLR_MESSAGING(); + WP_PrepareAndSendProtocolMessage(cmd, payloadSize, payload, flags); + + // FIXME: returning true to keep compatibility with previous code base + // improve this in a future revision + return true; +} + +void CLR_Messaging::BroadcastEvent( unsigned int cmd, unsigned int payloadSize, unsigned char* payload, unsigned int flags ) +{ + NATIVE_PROFILE_CLR_MESSAGING(); + WP_PrepareAndSendProtocolMessage(cmd, payloadSize, payload, flags); +} + +//--// diff --git a/source/native/nf-interpreter/src/CLR/Messaging/Messaging.vcxproj b/source/native/nf-interpreter/src/CLR/Messaging/Messaging.vcxproj new file mode 100644 index 00000000..b39a55b6 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Messaging/Messaging.vcxproj @@ -0,0 +1,163 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + + {2337c4a4-3ab4-4014-9c29-9ebe32f4510e} + false + false + + + + {131001E3-0201-451F-A87B-951D1C5C3EEE} + Win32Proj + Messaging + 10.0.17763.0 + + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\ + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\ + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\CorLib;..\..\HAL\Include;..\..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\CorLib;..\..\HAL\Include;..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Messaging/Messaging.vcxproj.filters b/source/native/nf-interpreter/src/CLR/Messaging/Messaging.vcxproj.filters new file mode 100644 index 00000000..2056f148 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Messaging/Messaging.vcxproj.filters @@ -0,0 +1,22 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Messaging/Messaging_stub.cpp b/source/native/nf-interpreter/src/CLR/Messaging/Messaging_stub.cpp new file mode 100644 index 00000000..3d93cbfe --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Messaging/Messaging_stub.cpp @@ -0,0 +1,51 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +__nfweak CLR_Messaging *g_CLR_Messaging; + +__nfweak CLR_UINT32 g_scratchMessaging[sizeof(CLR_Messaging) ]; + +__nfweak HRESULT CLR_Messaging::CreateInstance() +{ + NATIVE_PROFILE_CLR_MESSAGING(); + g_CLR_Messaging = (CLR_Messaging*)&g_scratchMessaging[0]; + NANOCLR_SYSTEM_STUB_RETURN(); +} + +__nfweak HRESULT CLR_Messaging::DeleteInstance() +{ + NATIVE_PROFILE_CLR_MESSAGING(); + NANOCLR_SYSTEM_STUB_RETURN(); +} + +__nfweak bool CLR_Messaging::SendEvent( unsigned int cmd, unsigned int payloadSize, unsigned char* payload, unsigned int flags ) +{ + (void)cmd; + (void)payloadSize; + (void)payload; + (void)flags; + + NATIVE_PROFILE_CLR_MESSAGING(); + return true; +} + +__nfweak void CLR_Messaging::Initialize(const CLR_Messaging_CommandHandlerLookup* requestLookup, const CLR_UINT32 requestLookupCount, const CLR_Messaging_CommandHandlerLookup* replyLookup, const CLR_UINT32 replyLookupCount ) +{ + (void)requestLookup; + (void)requestLookupCount; + (void)replyLookup; + (void)replyLookupCount; + + NATIVE_PROFILE_CLR_MESSAGING(); +} + +__nfweak void CLR_Messaging::Cleanup() +{ + NATIVE_PROFILE_CLR_MESSAGING(); +} diff --git a/source/native/nf-interpreter/src/CLR/Messaging/Messaging_stub.vcxproj b/source/native/nf-interpreter/src/CLR/Messaging/Messaging_stub.vcxproj new file mode 100644 index 00000000..49e8e57d --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Messaging/Messaging_stub.vcxproj @@ -0,0 +1,158 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + {8ACD05E8-42FB-4A49-9D8B-79239F0EED25} + Win32Proj + Messaging_stub + 10.0.17763.0 + + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\..\HAL\Include;..\..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + ..\Include + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\..\HAL\Include;..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\Include + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Messaging/Messaging_stub.vcxproj.filters b/source/native/nf-interpreter/src/CLR/Messaging/Messaging_stub.vcxproj.filters new file mode 100644 index 00000000..ca8c8999 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Messaging/Messaging_stub.vcxproj.filters @@ -0,0 +1,22 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Startup/CLRStartup.cpp b/source/native/nf-interpreter/src/CLR/Startup/CLRStartup.cpp new file mode 100644 index 00000000..37ecaa8f --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Startup/CLRStartup.cpp @@ -0,0 +1,459 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "CLRStartup.h" +#include +#include +#include +#include +#include + +void ClrExit() +{ + NATIVE_PROFILE_CLR_STARTUP(); + CLR_EE_DBG_SET(ExitPending); +} + +void ClrReboot() +{ + NATIVE_PROFILE_CLR_STARTUP(); + CLR_EE_REBOOT_CLR; + CLR_EE_DBG_SET(RebootPending); +} + +// the CLR Startup code on Windows version is different +#ifndef WIN32 + +struct Settings +{ + CLR_SETTINGS m_clrOptions; + bool m_fInitialized; + + //--// + + HRESULT Initialize(CLR_SETTINGS params) + { + NANOCLR_HEADER(); + + m_clrOptions = params; + + NANOCLR_CHECK_HRESULT(CLR_RT_ExecutionEngine::CreateInstance()); +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Created EE.\r\n" ); +#endif + +#if !defined(BUILD_RTM) + if(params.WaitForDebugger) + { + CLR_EE_DBG_SET( Stopped ); + } +#endif + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.StartHardware()); +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Started Hardware.\r\n" ); +#endif + + m_fInitialized = true; + + NANOCLR_NOCLEANUP(); + } + + HRESULT LoadAssembly( const CLR_RECORD_ASSEMBLY* header, CLR_RT_Assembly*& assm ) + { + NANOCLR_HEADER(); + + const CLR_RT_NativeAssemblyData *pNativeAssmData; + + NANOCLR_CHECK_HRESULT(CLR_RT_Assembly::CreateInstance( header, assm )); + + // Get handlers for native functions in assembly + pNativeAssmData = GetAssemblyNativeData( assm->m_szName ); + + // If pNativeAssmData not NULL- means this assembly has native calls and there is pointer to table with native calls. + if ( pNativeAssmData != NULL ) + { + // First verify that check sum in assembly object matches hardcoded check sum. + if ( assm->m_header->nativeMethodsChecksum != pNativeAssmData->m_checkSum ) + { + CLR_Debug::Printf("\r\n\r\n***********************************************************************\r\n"); + CLR_Debug::Printf("* *\r\n"); + CLR_Debug::Printf("* ERROR!!!! Firmware version does not match managed code version!!!! *\r\n"); + CLR_Debug::Printf("* *\r\n"); + CLR_Debug::Printf("* *\r\n"); + CLR_Debug::Printf("* Invalid native checksum: %s 0x%08X!=0x%08X *\r\n", + assm->m_szName, + assm->m_header->nativeMethodsChecksum, + pNativeAssmData->m_checkSum + ); + CLR_Debug::Printf("* *\r\n"); + CLR_Debug::Printf("***********************************************************************\r\n"); + + NANOCLR_SET_AND_LEAVE(CLR_E_ASSM_WRONG_CHECKSUM); + } + + // Assembly has valid pointer to table with native methods. Save it. + assm->m_nativeCode = (const CLR_RT_MethodHandler *)pNativeAssmData->m_pNativeMethods; + } + g_CLR_RT_TypeSystem.Link( assm ); + NANOCLR_NOCLEANUP(); + } + + + HRESULT Load() + { + NANOCLR_HEADER(); + + // clear flag (in case EE wasn't restarted) + CLR_EE_DBG_CLR(StateResolutionFailed); + +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Create TS.\r\n" ); +#endif + //NANOCLR_CHECK_HRESULT(LoadKnownAssemblies( (char*)&__deployment_start__, (char*)&__deployment_end__ )); + +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Loading Deployment Assemblies.\r\n" ); +#endif + + NANOCLR_CHECK_HRESULT(LoadDeploymentAssemblies()); + + //--// + +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Resolving.\r\n" ); +#endif + NANOCLR_CHECK_HRESULT(g_CLR_RT_TypeSystem.ResolveAll()); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_TypeSystem.PrepareForExecution()); + +#if defined(NANOCLR_PROFILE_HANDLER) + CLR_PROF_Handler::Calibrate(); +#endif + + NANOCLR_CLEANUP(); + +#if !defined(BUILD_RTM) + if(FAILED(hr)) + { + CLR_Debug::Printf( "Error: %08x\r\n", hr ); + + if(hr == CLR_E_TYPE_UNAVAILABLE) + { + // exception occurred during type resolution + CLR_EE_DBG_SET(StateResolutionFailed); + } + } +#endif + + NANOCLR_CLEANUP_END(); + } + + HRESULT LoadKnownAssemblies( char* start, char* end ) + { + //--// + NANOCLR_HEADER(); + char *assStart = start; + char *assEnd = end; + const CLR_RECORD_ASSEMBLY* header; + +#if !defined(BUILD_RTM) + CLR_Debug::Printf(" Loading start at %x, end %x\r\n", (unsigned int)assStart, (unsigned int)assEnd); +#endif + + g_buildCRC = SUPPORT_ComputeCRC( assStart, (unsigned int)assEnd -(unsigned int) assStart, 0 ); + + + header = (const CLR_RECORD_ASSEMBLY*)assStart; + + while((char*)header + sizeof(CLR_RECORD_ASSEMBLY) < assEnd && header->GoodAssembly()) + { + CLR_RT_Assembly* assm; + + // Creates instance of assembly, sets pointer to native functions, links to g_CLR_RT_TypeSystem + NANOCLR_CHECK_HRESULT(LoadAssembly( header, assm )); + + header = (const CLR_RECORD_ASSEMBLY*)ROUNDTOMULTIPLE((size_t)header + header->TotalSize(), CLR_UINT32); + } + + NANOCLR_NOCLEANUP(); + } + + + HRESULT ContiguousBlockAssemblies(BlockStorageStream stream) + { + NANOCLR_HEADER(); + + const CLR_RECORD_ASSEMBLY* header; + unsigned char* assembliesBuffer; + uint32_t headerInBytes = sizeof(CLR_RECORD_ASSEMBLY); + unsigned char* headerBuffer = NULL; + + // for the context it's being used (read the assemblies) + // XIP and memory mapped block regions are equivalent so they can be ORed + bool isXIP = (stream.Flags & BLOCKSTORAGESTREAM_c_BlockStorageStream__XIP) || + (stream.Flags & BLOCKSTORAGESTREAM_c_BlockStorageStream__MemoryMapped); + + if(!isXIP) + { + headerBuffer = (unsigned char*)platform_malloc(headerInBytes); + + if (headerBuffer == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // clear the buffer + memset(headerBuffer, 0, headerInBytes); + } + + while(stream.CurrentIndex < stream.Length) + { + // check if there is enough stream length to continue + if((stream.Length - stream.CurrentIndex ) < headerInBytes) + { + // not enough stream to read, leave now + break; + } + + if(!BlockStorageStream_Read(&stream, &headerBuffer, headerInBytes )) + { + // failed to read + break; + } + + header = (const CLR_RECORD_ASSEMBLY*)headerBuffer; + + // check header first before read + if(!header->GoodHeader()) + { + // check failed, try to continue to the next + continue; + } + + unsigned int assemblySizeInByte = ROUNDTOMULTIPLE(header->TotalSize(), CLR_UINT32); + + if(!isXIP) + { + // setup buffer for assembly + ///////////////////////////////////////////////////////////////////////////////////// + // because we need to map to the functions, the assembly needs to remain on memory // + // so platform_free can't be called for this // + ///////////////////////////////////////////////////////////////////////////////////// + assembliesBuffer = (unsigned char*)platform_malloc(assemblySizeInByte); + + if (assembliesBuffer == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // clear the buffer + memset(assembliesBuffer, 0, assemblySizeInByte); + } + + // advance stream beyond header + BlockStorageStream_Seek(&stream, -headerInBytes, BlockStorageStream_SeekCurrent); + + // read the assembly + if(!BlockStorageStream_Read(&stream, &assembliesBuffer, assemblySizeInByte)) + { + // something wrong with the read, can't continue + break; + } + + header = (const CLR_RECORD_ASSEMBLY*)assembliesBuffer; + + if(!header->GoodAssembly()) + { + // check failed, try to continue to the next + + if(!isXIP && assembliesBuffer != NULL) + { + // release the assembliesBuffer + platform_free(assembliesBuffer); + } + + continue; + } + + // we have good Assembly + CLR_RT_Assembly* assm; + +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Attaching deployed file.\r\n" ); +#endif + + // Creates instance of assembly, sets pointer to native functions, links to g_CLR_RT_TypeSystem + if (FAILED(LoadAssembly(header, assm))) + { + // load failed, try to continue to the next + + if(!isXIP && assembliesBuffer != NULL) + { + // release the assembliesBuffer which has being used and leave + platform_free(assembliesBuffer); + } + + continue; + } + + // load successfull, mark as deployed + assm->m_flags |= CLR_RT_Assembly::Deployed; + } + + if(!isXIP && headerBuffer != NULL) + { + // release the headerbuffer which has being used and leave + platform_free(headerBuffer); + } + + NANOCLR_NOCLEANUP(); + } + + HRESULT LoadDeploymentAssemblies() + { + NANOCLR_HEADER(); + + // perform initialization of BlockStorageStream structure + BlockStorageStream stream; + memset(&stream, 0, sizeof(BlockStorageStream)); + + // init the stream for deployment storage + if (!BlockStorageStream_Initialize(&stream, BlockUsage_DEPLOYMENT)) + { +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "ERROR: failed to initialize DEPLOYMENT storage\r\n" ); +#endif + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + } + + NANOCLR_CHECK_HRESULT(ContiguousBlockAssemblies(stream)); + + NANOCLR_NOCLEANUP(); + } + + void Cleanup() + { + CLR_RT_ExecutionEngine::DeleteInstance(); + + memset( &g_CLR_RT_ExecutionEngine, 0, sizeof(g_CLR_RT_ExecutionEngine)); + memset( &g_CLR_RT_WellKnownTypes, 0, sizeof(g_CLR_RT_WellKnownTypes)); + memset( &g_CLR_RT_WellKnownMethods, 0, sizeof(g_CLR_RT_WellKnownMethods)); + memset( &g_CLR_RT_TypeSystem, 0, sizeof(g_CLR_RT_TypeSystem)); + memset( &g_CLR_RT_EventCache, 0, sizeof(g_CLR_RT_EventCache)); + memset( &g_CLR_RT_GarbageCollector, 0, sizeof(g_CLR_RT_GarbageCollector)); + memset( &g_CLR_HW_Hardware, 0, sizeof(g_CLR_HW_Hardware)); + + m_fInitialized = false; + } + + Settings() + { + m_fInitialized = false; + } + +}; + + +static Settings s_ClrSettings; + +void ClrStartup(CLR_SETTINGS params) +{ + NATIVE_PROFILE_CLR_STARTUP(); + Settings settings; + ASSERT(sizeof(CLR_RT_HeapBlock_Raw) == sizeof(CLR_RT_HeapBlock)); + bool softReboot; + + do + { + softReboot = false; + + CLR_RT_Assembly::InitString(); + +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "\r\nnanoCLR (Build %d.%d.%d.%d)\r\n\r\n", VERSION_MAJOR, VERSION_MINOR, VERSION_BUILD, VERSION_REVISION ); + CLR_Debug::Printf( "\r\n%s\r\n\r\n", OEMSYSTEMINFOSTRING ); +#endif + + CLR_RT_Memory::Reset(); + +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Starting...\r\n" ); +#endif + + + HRESULT hr; + + if(SUCCEEDED(hr = s_ClrSettings.Initialize(params))) + { + if(SUCCEEDED(hr = s_ClrSettings.Load())) + { +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Ready.\r\n" ); +#endif + + (void)g_CLR_RT_ExecutionEngine.Execute( NULL, params.MaxContextSwitches ); + +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Done.\r\n" ); +#endif + } + } + + // process setting of power mode, if reboot was requested along with a power mode "higher" then PowerLevel__Active + if(CLR_EE_REBOOT_IS( ClrOnly ) && g_CLR_HW_Hardware.m_powerLevel > PowerLevel__Active) + { + CPU_SetPowerMode(g_CLR_HW_Hardware.m_powerLevel); + } + + if( CLR_EE_DBG_IS_NOT( RebootPending )) + { +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + CLR_EE_DBG_SET_MASK(StateProgramExited, StateMask); + CLR_EE_DBG_EVENT_BROADCAST(CLR_DBG_Commands::c_Monitor_ProgramExit, 0, NULL, WP_Flags_c_NonCritical); +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + +#if !defined(BUILD_RTM) + if(params.EnterDebuggerLoopAfterExit) + { + CLR_DBG_Debugger::Debugger_WaitForCommands(); + } +#endif + } + + // DO NOT USE 'ELSE IF' here because the state can change in Debugger_WaitForCommands() call + + if( CLR_EE_DBG_IS( RebootPending )) + { + if(CLR_EE_REBOOT_IS( ClrOnly )) + { + softReboot = true; + + params.WaitForDebugger = CLR_EE_REBOOT_IS(WaitForDebugger); + + s_ClrSettings.Cleanup(); + + nanoHAL_Uninitialize(); + + //re-init the hal for the reboot (initially it is called in bootentry) + nanoHAL_Initialize(); + } + else + { + CPU_Reset(); + } + } + + } while( softReboot ); + + #if !defined(BUILD_RTM) + CLR_Debug::Printf( "Exiting.\r\n" ); + #endif + + CPU_Reset(); +} + +#endif // WIN32 diff --git a/source/native/nf-interpreter/src/CLR/Startup/CLRStartup.h b/source/native/nf-interpreter/src/CLR/Startup/CLRStartup.h new file mode 100644 index 00000000..68b0212c --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Startup/CLRStartup.h @@ -0,0 +1,28 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef __CLRSTARTUP_H__ +#define __CLRSTARTUP_H__ + +///////////////////////////////////////////////////////////////////////////// + +#include +#include +//#include +//#include +//#include +#include +// +//#include +// +//#include +//#include +//#include +//#include +//#include +//#include + +#endif // __CLRSTARTUP_H__ + diff --git a/source/native/nf-interpreter/src/CLR/Startup/Startup.vcxproj b/source/native/nf-interpreter/src/CLR/Startup/Startup.vcxproj new file mode 100644 index 00000000..0f3388cb --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Startup/Startup.vcxproj @@ -0,0 +1,170 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + + + + + {89cf8bdb-9c8a-4d18-bc3e-4312c5bd34b1} + false + false + false + + + + {2A840DC3-FFA8-4562-BD13-AB2B0BA02CB6} + Win32Proj + StartUp + 10.0.17763.0 + Startup + + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\..\HAL\Include;..\..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\..\HAL\Include;..\..\PAL\Include + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\..\HAL\Include;..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\..\HAL\Include;..\..\PAL\Include + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/Startup/Startup.vcxproj.filters b/source/native/nf-interpreter/src/CLR/Startup/Startup.vcxproj.filters new file mode 100644 index 00000000..3c321f80 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/Startup/Startup.vcxproj.filters @@ -0,0 +1,27 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + + + Header Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/System.Math/nf_native_system_math.cpp b/source/native/nf-interpreter/src/CLR/System.Math/nf_native_system_math.cpp new file mode 100644 index 00000000..78101de5 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/System.Math/nf_native_system_math.cpp @@ -0,0 +1,70 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "nf_native_system_math.h" + + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + Library_nf_native_system_math_System_Math::Abs___STATIC__R8__R8, + Library_nf_native_system_math_System_Math::Abs___STATIC__R4__R4, + Library_nf_native_system_math_System_Math::Acos___STATIC__R8__R8, + Library_nf_native_system_math_System_Math::Acos___STATIC__R4__R4, + Library_nf_native_system_math_System_Math::Asin___STATIC__R8__R8, + Library_nf_native_system_math_System_Math::Asin___STATIC__R4__R4, + Library_nf_native_system_math_System_Math::Atan___STATIC__R8__R8, + Library_nf_native_system_math_System_Math::Atan___STATIC__R4__R4, + Library_nf_native_system_math_System_Math::Atan2___STATIC__R8__R8__R8, + Library_nf_native_system_math_System_Math::Atan2___STATIC__R4__R4__R4, + Library_nf_native_system_math_System_Math::Ceiling___STATIC__R8__R8, + Library_nf_native_system_math_System_Math::Ceiling___STATIC__R4__R4, + Library_nf_native_system_math_System_Math::Cos___STATIC__R8__R8, + Library_nf_native_system_math_System_Math::Cos___STATIC__R4__R4, + Library_nf_native_system_math_System_Math::Cosh___STATIC__R8__R8, + Library_nf_native_system_math_System_Math::Cosh___STATIC__R4__R4, + Library_nf_native_system_math_System_Math::IEEERemainder___STATIC__R8__R8__R8, + Library_nf_native_system_math_System_Math::IEEERemainder___STATIC__R4__R4__R4, + Library_nf_native_system_math_System_Math::Exp___STATIC__R8__R8, + Library_nf_native_system_math_System_Math::Exp___STATIC__R4__R4, + Library_nf_native_system_math_System_Math::Floor___STATIC__R8__R8, + Library_nf_native_system_math_System_Math::Floor___STATIC__R4__R4, + Library_nf_native_system_math_System_Math::Log___STATIC__R8__R8, + Library_nf_native_system_math_System_Math::Log___STATIC__R4__R4, + Library_nf_native_system_math_System_Math::Log10___STATIC__R8__R8, + Library_nf_native_system_math_System_Math::Log10___STATIC__R4__R4, + Library_nf_native_system_math_System_Math::Max___STATIC__R8__R8__R8, + Library_nf_native_system_math_System_Math::Max___STATIC__R4__R4__R4, + Library_nf_native_system_math_System_Math::Min___STATIC__R8__R8__R8, + Library_nf_native_system_math_System_Math::Min___STATIC__R4__R4__R4, + Library_nf_native_system_math_System_Math::Pow___STATIC__R8__R8__R8, + Library_nf_native_system_math_System_Math::Pow___STATIC__R4__R4__R4, + Library_nf_native_system_math_System_Math::Round___STATIC__R8__R8, + Library_nf_native_system_math_System_Math::Round___STATIC__R4__R4, + Library_nf_native_system_math_System_Math::Sign___STATIC__I4__R8, + Library_nf_native_system_math_System_Math::Sign___STATIC__I4__R4, + Library_nf_native_system_math_System_Math::Sin___STATIC__R8__R8, + Library_nf_native_system_math_System_Math::Sin___STATIC__R4__R4, + Library_nf_native_system_math_System_Math::Sinh___STATIC__R8__R8, + Library_nf_native_system_math_System_Math::Sinh___STATIC__R4__R4, + Library_nf_native_system_math_System_Math::Sqrt___STATIC__R8__R8, + Library_nf_native_system_math_System_Math::Sqrt___STATIC__R4__R4, + Library_nf_native_system_math_System_Math::Tan___STATIC__R8__R8, + Library_nf_native_system_math_System_Math::Tan___STATIC__R4__R4, + Library_nf_native_system_math_System_Math::Tanh___STATIC__R8__R8, + Library_nf_native_system_math_System_Math::Tanh___STATIC__R4__R4, + Library_nf_native_system_math_System_Math::Truncate___STATIC__R8__R8, + Library_nf_native_system_math_System_Math::Truncate___STATIC__R4__R4, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Math = +{ + "System.Math", + 0xC5A2A195, + method_lookup, + { 100, 0, 4, 3 } +}; diff --git a/source/native/nf-interpreter/src/CLR/System.Math/nf_native_system_math.h b/source/native/nf-interpreter/src/CLR/System.Math/nf_native_system_math.h new file mode 100644 index 00000000..9d91affa --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/System.Math/nf_native_system_math.h @@ -0,0 +1,70 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _NF_NATIVE_SYSTEM_MATH_H_ +#define _NF_NATIVE_SYSTEM_MATH_H_ + +#include +#include +// #include + +struct Library_nf_native_system_math_System_Math +{ + NANOCLR_NATIVE_DECLARE(Abs___STATIC__R8__R8); + NANOCLR_NATIVE_DECLARE(Abs___STATIC__R4__R4); + NANOCLR_NATIVE_DECLARE(Acos___STATIC__R8__R8); + NANOCLR_NATIVE_DECLARE(Acos___STATIC__R4__R4); + NANOCLR_NATIVE_DECLARE(Asin___STATIC__R8__R8); + NANOCLR_NATIVE_DECLARE(Asin___STATIC__R4__R4); + NANOCLR_NATIVE_DECLARE(Atan___STATIC__R8__R8); + NANOCLR_NATIVE_DECLARE(Atan___STATIC__R4__R4); + NANOCLR_NATIVE_DECLARE(Atan2___STATIC__R8__R8__R8); + NANOCLR_NATIVE_DECLARE(Atan2___STATIC__R4__R4__R4); + NANOCLR_NATIVE_DECLARE(Ceiling___STATIC__R8__R8); + NANOCLR_NATIVE_DECLARE(Ceiling___STATIC__R4__R4); + NANOCLR_NATIVE_DECLARE(Cos___STATIC__R8__R8); + NANOCLR_NATIVE_DECLARE(Cos___STATIC__R4__R4); + NANOCLR_NATIVE_DECLARE(Cosh___STATIC__R8__R8); + NANOCLR_NATIVE_DECLARE(Cosh___STATIC__R4__R4); + NANOCLR_NATIVE_DECLARE(IEEERemainder___STATIC__R8__R8__R8); + NANOCLR_NATIVE_DECLARE(IEEERemainder___STATIC__R4__R4__R4); + NANOCLR_NATIVE_DECLARE(Exp___STATIC__R8__R8); + NANOCLR_NATIVE_DECLARE(Exp___STATIC__R4__R4); + NANOCLR_NATIVE_DECLARE(Floor___STATIC__R8__R8); + NANOCLR_NATIVE_DECLARE(Floor___STATIC__R4__R4); + NANOCLR_NATIVE_DECLARE(Log___STATIC__R8__R8); + NANOCLR_NATIVE_DECLARE(Log___STATIC__R4__R4); + NANOCLR_NATIVE_DECLARE(Log10___STATIC__R8__R8); + NANOCLR_NATIVE_DECLARE(Log10___STATIC__R4__R4); + NANOCLR_NATIVE_DECLARE(Max___STATIC__R8__R8__R8); + NANOCLR_NATIVE_DECLARE(Max___STATIC__R4__R4__R4); + NANOCLR_NATIVE_DECLARE(Min___STATIC__R8__R8__R8); + NANOCLR_NATIVE_DECLARE(Min___STATIC__R4__R4__R4); + NANOCLR_NATIVE_DECLARE(Pow___STATIC__R8__R8__R8); + NANOCLR_NATIVE_DECLARE(Pow___STATIC__R4__R4__R4); + NANOCLR_NATIVE_DECLARE(Round___STATIC__R8__R8); + NANOCLR_NATIVE_DECLARE(Round___STATIC__R4__R4); + NANOCLR_NATIVE_DECLARE(Sign___STATIC__I4__R8); + NANOCLR_NATIVE_DECLARE(Sign___STATIC__I4__R4); + NANOCLR_NATIVE_DECLARE(Sin___STATIC__R8__R8); + NANOCLR_NATIVE_DECLARE(Sin___STATIC__R4__R4); + NANOCLR_NATIVE_DECLARE(Sinh___STATIC__R8__R8); + NANOCLR_NATIVE_DECLARE(Sinh___STATIC__R4__R4); + NANOCLR_NATIVE_DECLARE(Sqrt___STATIC__R8__R8); + NANOCLR_NATIVE_DECLARE(Sqrt___STATIC__R4__R4); + NANOCLR_NATIVE_DECLARE(Tan___STATIC__R8__R8); + NANOCLR_NATIVE_DECLARE(Tan___STATIC__R4__R4); + NANOCLR_NATIVE_DECLARE(Tanh___STATIC__R8__R8); + NANOCLR_NATIVE_DECLARE(Tanh___STATIC__R4__R4); + NANOCLR_NATIVE_DECLARE(Truncate___STATIC__R8__R8); + NANOCLR_NATIVE_DECLARE(Truncate___STATIC__R4__R4); + + //--// + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Math; + +#endif //_NF_NATIVE_SYSTEM_MATH_H_ diff --git a/source/native/nf-interpreter/src/CLR/System.Math/nf_native_system_math_System_Math.cpp b/source/native/nf-interpreter/src/CLR/System.Math/nf_native_system_math_System_Math.cpp new file mode 100644 index 00000000..7b42b113 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/System.Math/nf_native_system_math_System_Math.cpp @@ -0,0 +1,1481 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "nf_native_system_math.h" + +#if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + #include "nanoPAL_NativeDouble.h" + + HRESULT Library_nf_native_system_math_System_Math::Max___STATIC__R4__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + float x = stack.Arg0().NumericByRefConst().r4; + float y = stack.Arg1().NumericByRefConst().r4; + float res = x >= y ? x : y; + + stack.SetResult_R4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + } + + HRESULT Library_nf_native_system_math_System_Math::Max___STATIC__R8__R8__R8( CLR_RT_StackFrame& stack ) + { + #if (DP_FLOATINGPOINT == TRUE) + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double x = stack.Arg0().NumericByRefConst().r8; + double y = stack.Arg1().NumericByRefConst().r8; + double res = x >= y ? x : y; + + stack.SetResult_R8( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + + #else + return stack.NotImplementedStub(); + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Min___STATIC__R4__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + float x = stack.Arg0().NumericByRefConst().r4; + float y = stack.Arg1().NumericByRefConst().r4; + float res = x <= y ? x : y; + + stack.SetResult_R4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + } + + HRESULT Library_nf_native_system_math_System_Math::Min___STATIC__R8__R8__R8( CLR_RT_StackFrame& stack ) + { + #if (DP_FLOATINGPOINT == TRUE) + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double x = stack.Arg0().NumericByRefConst().r8; + double y = stack.Arg1().NumericByRefConst().r8; + double res = x <= y ? x : y; + + stack.SetResult_R8( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + + #else + return stack.NotImplementedStub(); + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Abs___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + #if (DP_FLOATINGPOINT == TRUE) + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double d = stack.Arg0().NumericByRefConst().r8; + double res = fabs( d ); + + stack.SetResult_R8( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + + #else + return stack.NotImplementedStub(); + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Abs___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + float d = stack.Arg0().NumericByRefConst().r4; + float res = fabsf( d ); + + stack.SetResult_R4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + } + + HRESULT Library_nf_native_system_math_System_Math::Acos___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + + #if (DP_FLOATINGPOINT == TRUE) + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double d = stack.Arg0().NumericByRefConst().r8; + double res = acos( d ); + + stack.SetResult_R8( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + + #else + return stack.NotImplementedStub(); + #endif + + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Acos___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + float d = stack.Arg0().NumericByRefConst().r4; + float res = acosf( d ); + + stack.SetResult_R4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Asin___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + + #if (DP_FLOATINGPOINT == TRUE) + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double d = stack.Arg0().NumericByRefConst().r8; + double res = asin( d ); + + stack.SetResult_R8( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + + #else + return stack.NotImplementedStub(); + #endif + + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Asin___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + float d = stack.Arg0().NumericByRefConst().r4; + float res = asinf( d ); + + stack.SetResult_R4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Atan___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + + #if (DP_FLOATINGPOINT == TRUE) + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double d = stack.Arg0().NumericByRefConst().r8; + double res = atan( d ); + + stack.SetResult_R8( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + + #else + return stack.NotImplementedStub(); + #endif + + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Atan___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + float d = stack.Arg0().NumericByRefConst().r4; + float res = atanf( d ); + + stack.SetResult_R4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Atan2___STATIC__R8__R8__R8( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + + #if (DP_FLOATINGPOINT == TRUE) + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double x = stack.Arg0().NumericByRefConst().r8; + double y = stack.Arg1().NumericByRefConst().r8; + double res = atan2( x, y ); + + stack.SetResult_R8( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + + #else + return stack.NotImplementedStub(); + #endif + + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Atan2___STATIC__R4__R4__R4( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + float x = stack.Arg0().NumericByRefConst().r4; + float y = stack.Arg1().NumericByRefConst().r4; + float res = atan2f( x, y ); + + stack.SetResult_R4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Ceiling___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + + #if (DP_FLOATINGPOINT == TRUE) + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double d = stack.Arg0().NumericByRefConst().r8; + double res = ceil( d ); + + stack.SetResult_R8( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + + #else + return stack.NotImplementedStub(); + #endif + + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Ceiling___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + float d = stack.Arg0().NumericByRefConst().r4; + float res = ceilf( d ); + + stack.SetResult_R4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Cos___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + + #if (DP_FLOATINGPOINT == TRUE) + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double d = stack.Arg0().NumericByRefConst().r8; + double res = cos( d ); + + stack.SetResult_R8( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + + #else + return stack.NotImplementedStub(); + #endif + + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Cos___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + float d = stack.Arg0().NumericByRefConst().r4; + float res = cosf( d ); + + stack.SetResult_R4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Cosh___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + + #if (DP_FLOATINGPOINT == TRUE) + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double d = stack.Arg0().NumericByRefConst().r8; + double res = cosh( d ); + + stack.SetResult_R8( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + + #else + return stack.NotImplementedStub(); + #endif + + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Cosh___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + float d = stack.Arg0().NumericByRefConst().r4; + float res = coshf( d ); + + stack.SetResult_R4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::IEEERemainder___STATIC__R8__R8__R8( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + + #if (DP_FLOATINGPOINT == TRUE) + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double x = stack.Arg0().NumericByRefConst().r8; + double y = stack.Arg1().NumericByRefConst().r8; + double res = remainder(x, y); + + stack.SetResult_R8( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + + #else + return stack.NotImplementedStub(); + #endif + + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::IEEERemainder___STATIC__R4__R4__R4( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + float x = stack.Arg0().NumericByRefConst().r4; + float y = stack.Arg1().NumericByRefConst().r4; + float res = remainderf(x, y); + + stack.SetResult_R4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Exp___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + + #if (DP_FLOATINGPOINT == TRUE) + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double d = stack.Arg0().NumericByRefConst().r8; + double res = exp( d ); + + stack.SetResult_R8( res ); + + NANOCLR_NOCLEANUP_NOLABEL();; + + #else + return stack.NotImplementedStub(); + #endif + + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Exp___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + float d = stack.Arg0().NumericByRefConst().r4; + float res = expf( d ); + + stack.SetResult_R4( res ); + + NANOCLR_NOCLEANUP_NOLABEL();; + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Floor___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + + #if (DP_FLOATINGPOINT == TRUE) + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double d = stack.Arg0().NumericByRefConst().r8; + double res = floor( d ); + + stack.SetResult_R8( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + + #else + return stack.NotImplementedStub(); + #endif + + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Floor___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + float d = stack.Arg0().NumericByRefConst().r4; + float res = floorf( d ); + + stack.SetResult_R4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Log___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + + #if (DP_FLOATINGPOINT == TRUE) + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double d = stack.Arg0().NumericByRefConst().r8; + double res = log( d ); + + stack.SetResult_R8( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + + #else + return stack.NotImplementedStub(); + #endif + + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Log___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + float d = stack.Arg0().NumericByRefConst().r4; + float res = logf( d ); + + stack.SetResult_R4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Log10___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + + #if (DP_FLOATINGPOINT == TRUE) + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double d = stack.Arg0().NumericByRefConst().r8; + double res = log10( d ); + + stack.SetResult_R8( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + + #else + return stack.NotImplementedStub(); + #endif + + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Log10___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + float d = stack.Arg0().NumericByRefConst().r4; + float res = log10f( d ); + + stack.SetResult_R4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Pow___STATIC__R8__R8__R8( CLR_RT_StackFrame& stack ) + { + #if (DP_FLOATINGPOINT == TRUE) + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double x = stack.Arg0().NumericByRefConst().r8; + double y = stack.Arg1().NumericByRefConst().r8; + + double res = pow( x, y ); + + stack.SetResult_R8( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + #else + return stack.NotImplementedStub(); + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Pow___STATIC__R4__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + float x = stack.Arg0().NumericByRefConst().r4; + float y = stack.Arg1().NumericByRefConst().r4; + + float res = powf( x, y ); + + stack.SetResult_R4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + } + + HRESULT Library_nf_native_system_math_System_Math::Round___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + #if (DP_FLOATINGPOINT == TRUE) + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double d = stack.Arg0().NumericByRefConst().r8; + double hi = d + 0.5; + double res = floor( hi ); + + //If the number was in the middle of two integers, we need to round to the even one. + if(res==hi) + { + if(fmod( res, 2.0 ) != 0) + { + //Rounding up made the number odd so we should round down. + res -= 1.0; + } + } + + stack.SetResult_R8( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + + #else + return stack.NotImplementedStub(); + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Round___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + float d = stack.Arg0().NumericByRefConst().r4; + float hi = d + 0.5; + float res = floorf( hi ); + + //If the number was in the middle of two integers, we need to round to the even one. + if(res==hi) + { + if(fmodf( res, 2.0 ) != 0) + { + //Rounding up made the number odd so we should round down. + res -= 1.0; + } + } + stack.SetResult_R4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + } + + HRESULT Library_nf_native_system_math_System_Math::Sign___STATIC__I4__R8( CLR_RT_StackFrame& stack ) + { + #if (DP_FLOATINGPOINT == TRUE) + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double d = stack.Arg0().NumericByRefConst().r8; + int32_t res; + if (d < 0) res = -1; + else if (d > 0) res = +1; + else res = 0; + + stack.SetResult_I4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + #else + return stack.NotImplementedStub(); + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Sign___STATIC__I4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + float d = stack.Arg0().NumericByRefConst().r4; + int32_t res; + if (d < 0) res = -1; + else if (d > 0) res = +1; + else res = 0; + + stack.SetResult_I4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + } + + HRESULT Library_nf_native_system_math_System_Math::Sin___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + + #if (DP_FLOATINGPOINT == TRUE) + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double d = stack.Arg0().NumericByRefConst().r8; + double res = sin( d ); + + stack.SetResult_R8( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + + #else + return stack.NotImplementedStub(); + #endif + + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Sin___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + float d = stack.Arg0().NumericByRefConst().r4; + float res = sinf( d ); + + stack.SetResult_R4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Sinh___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + + #if (DP_FLOATINGPOINT == TRUE) + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double d = stack.Arg0().NumericByRefConst().r8; + double res = sinh( d ); + + stack.SetResult_R8( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + + #else + return stack.NotImplementedStub(); + #endif + + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Sinh___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + float d = stack.Arg0().NumericByRefConst().r4; + float res = sinhf( d ); + + stack.SetResult_R4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Sqrt___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + + #if (DP_FLOATINGPOINT == TRUE) + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double d = stack.Arg0().NumericByRefConst().r8; + double res = sqrt( d ); + + stack.SetResult_R8( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + + #else + return stack.NotImplementedStub(); + #endif + + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Sqrt___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + float d = stack.Arg0().NumericByRefConst().r4; + float res = sqrtf( d ); + + stack.SetResult_R4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Tan___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + + #if (DP_FLOATINGPOINT == TRUE) + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double d = stack.Arg0().NumericByRefConst().r8; + double res = tan( d ); + + stack.SetResult_R8( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + + #else + return stack.NotImplementedStub(); + #endif + + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Tan___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + float d = stack.Arg0().NumericByRefConst().r4; + float res = tanf( d ); + + stack.SetResult_R4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Tanh___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + + #if (DP_FLOATINGPOINT == TRUE) + + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double d = stack.Arg0().NumericByRefConst().r8; + double res = tanh( d ); + + stack.SetResult_R8( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + + #else + return stack.NotImplementedStub(); + #endif + + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Tanh___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + #if (NANOCLR_LIGHT_MATH == TRUE) + return stack.NotImplementedStub(); + #else + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + float d = stack.Arg0().NumericByRefConst().r4; + float res = tanhf( d ); + + stack.SetResult_R4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Truncate___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + #if (DP_FLOATINGPOINT == TRUE) + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + double d = stack.Arg0().NumericByRefConst().r8; + double res = 0.0; + modf(d, &res); + + stack.SetResult_R8( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + + #else + return stack.NotImplementedStub(); + #endif + } + + HRESULT Library_nf_native_system_math_System_Math::Truncate___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + float d = stack.Arg0().NumericByRefConst().r4; + float res = 0.0; + modff(d, &res); + + stack.SetResult_R4( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + } + +#else + + /// No floating point + HRESULT Library_nf_native_system_math_System_Math::Max___STATIC__R4__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Max___STATIC__R8__R8__R8( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Min___STATIC__R4__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Min___STATIC__R8__R8__R8( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Abs___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Abs___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Acos___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Acos___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Asin___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Asin___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Atan___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Atan___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Atan2___STATIC__R8__R8__R8( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Atan2___STATIC__R4__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Ceiling___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_INT64 d = stack.Arg0().NumericByRefConst().r8; + + CLR_INT64 res = (CLR_INT64)(d + (CLR_INT64)CLR_RT_HeapBlock::HB_DoubleMask) & (~CLR_RT_HeapBlock::HB_DoubleMask); + + stack.SetResult_I8( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + } + + HRESULT Library_nf_native_system_math_System_Math::Ceiling___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Cos___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Cos___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Cosh___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Cosh___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::IEEERemainder___STATIC__R8__R8__R8( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::IEEERemainder___STATIC__R4__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Exp___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Exp___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Floor___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_INT64 d = stack.Arg0().NumericByRefConst().r8; + CLR_INT64 res = (CLR_INT64)( d & (~CLR_RT_HeapBlock::HB_DoubleMask) ); + stack.SetResult_I8( res ); + + NANOCLR_NOCLEANUP_NOLABEL(); + } + + HRESULT Library_nf_native_system_math_System_Math::Floor___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Log___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Log___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Log10___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Log10___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Pow___STATIC__R8__R8__R8( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Pow___STATIC__R4__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Round___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_INT64 d = stack.Arg0().NumericByRefConst().r8; + + //for negative number we have to be banker's round, if -0.5, round to 0, but 0.5 to 0 + if (d <0) d =d + 1; + CLR_INT64 res = (CLR_INT64)(d + (CLR_INT64)(CLR_RT_HeapBlock::HB_DoubleMask>>1) ) & (~CLR_RT_HeapBlock::HB_DoubleMask); + + stack.SetResult_I8( res ); + + + NANOCLR_NOCLEANUP_NOLABEL(); + } + + HRESULT Library_nf_native_system_math_System_Math::Round___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Sign___STATIC__I4__R8( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Sign___STATIC__I4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Sin___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Sin___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Sinh___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Sinh___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Sqrt___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Sqrt___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Tan___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Tan___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Tanh___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Tanh___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Truncate___STATIC__R8__R8( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + + HRESULT Library_nf_native_system_math_System_Math::Truncate___STATIC__R4__R4( CLR_RT_StackFrame& stack ) + { + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); + } + +#endif // NANOCLR_EMULATED_FLOATINGPOINT diff --git a/source/native/nf-interpreter/src/CLR/WireProtocol/WireProtocol-vs2019.vcxproj b/source/native/nf-interpreter/src/CLR/WireProtocol/WireProtocol-vs2019.vcxproj new file mode 100644 index 00000000..afefd6ed --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/WireProtocol/WireProtocol-vs2019.vcxproj @@ -0,0 +1,161 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + + + + + {2337C4A4-3AB4-4014-9C29-9EBE32F4510E} + Win32Proj + WireProtocol + 10.0.17763.0 + WireProtocol + + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + false + v142 + true + Unicode + + + StaticLibrary + true + v142 + Unicode + + + StaticLibrary + false + v142 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(SolutionDir)$(Configuration)\ + $(IntDir) + + + $(SolutionDir)$(Configuration)\ + $(IntDir) + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\..\HAL\Include;..\..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\..\HAL\Include;..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/WireProtocol/WireProtocol-vs2019.vcxproj.filters b/source/native/nf-interpreter/src/CLR/WireProtocol/WireProtocol-vs2019.vcxproj.filters new file mode 100644 index 00000000..a163610f --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/WireProtocol/WireProtocol-vs2019.vcxproj.filters @@ -0,0 +1,34 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/WireProtocol/WireProtocol.vcxproj b/source/native/nf-interpreter/src/CLR/WireProtocol/WireProtocol.vcxproj new file mode 100644 index 00000000..5b9a87b2 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/WireProtocol/WireProtocol.vcxproj @@ -0,0 +1,160 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + + + + + + + + {2337C4A4-3AB4-4014-9C29-9EBE32F4510E} + Win32Proj + WireProtocol + 10.0.17763.0 + + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + StaticLibrary + true + v141 + Unicode + + + StaticLibrary + false + v141 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\ + + + $(SolutionDir)$(Configuration)\ + $(Configuration)\ + + + $(BinDir) + $(IntDir) + + + $(BinDir) + $(IntDir) + + + + + + Level3 + Disabled + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\..\HAL\Include;..\..\PAL\Include + + + Windows + + + + + + + Level3 + Disabled + _DEBUG;_LIB;%(PreprocessorDefinitions) + + + Windows + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions) + ..\..\..\targets\os\win32\Include;..\Include;..\..\HAL\Include;..\..\PAL\Include + + + Windows + true + true + + + + + Level3 + + + MaxSpeed + true + true + NDEBUG;_LIB;%(PreprocessorDefinitions) + + + Windows + true + true + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/WireProtocol/WireProtocol.vcxproj.filters b/source/native/nf-interpreter/src/CLR/WireProtocol/WireProtocol.vcxproj.filters new file mode 100644 index 00000000..a163610f --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/WireProtocol/WireProtocol.vcxproj.filters @@ -0,0 +1,34 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/src/CLR/WireProtocol/WireProtocol_App_Interface.c b/source/native/nf-interpreter/src/CLR/WireProtocol/WireProtocol_App_Interface.c new file mode 100644 index 00000000..00f04a07 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/WireProtocol/WireProtocol_App_Interface.c @@ -0,0 +1,33 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "WireProtocol_App_Interface.h" + +//////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////// +// The functions below are the ones that need to be ported to client applications, +// tipically nanoBooter and CLR debugger +// +// +///////////////////////////////////////////////////////////////////////////////////////////////// + +// provided as weak to be replaced by actual implementation in the client application +__nfweak int WP_App_ProcessHeader(WP_Message* message) +{ + (void)(message); + + // default to false + return false; +} + +// provided as weak to be replaced by actual implementation in the client application +__nfweak int WP_App_ProcessPayload(WP_Message* message) +{ + (void)(message); + + // default to false + return false; +} diff --git a/source/native/nf-interpreter/src/CLR/WireProtocol/WireProtocol_HAL_Interface.c b/source/native/nf-interpreter/src/CLR/WireProtocol/WireProtocol_HAL_Interface.c new file mode 100644 index 00000000..f27f0035 --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/WireProtocol/WireProtocol_HAL_Interface.c @@ -0,0 +1,40 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "WireProtocol_HAL_Interface.h" + +///////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////// +// The functions below are the ones that need to be ported to new channels/HALs when required +// +// Please check the reference implementation provided for ChibiOS in: +// RTOS\ChibiOS\WireProtocol_HAL_Interface.c +// +///////////////////////////////////////////////////////////////////////////////////////////////// + +// provided as weak to be replaced by actual implementation by HAL interface +__nfweak int WP_ReceiveBytes(uint8_t* ptr, unsigned short* size) +{ + (void)(ptr); + (void)(size); + + // default to false + return false; +} + +// provided as weak to be replaced by actual implementation by HAL interface +__nfweak int WP_TransmitMessage(WP_Message* message) +{ + (void)(message); + + // default to false + return false; +} + +// provided as weak to be replaced by actual implementation by HAL interface +__nfweak void WP_CheckAvailableIncomingData() +{ +} diff --git a/source/native/nf-interpreter/src/CLR/WireProtocol/WireProtocol_Message.c b/source/native/nf-interpreter/src/CLR/WireProtocol/WireProtocol_Message.c new file mode 100644 index 00000000..0e024e0c --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/WireProtocol/WireProtocol_Message.c @@ -0,0 +1,395 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include "WireProtocol_Message.h" + +uint8_t receptionBuffer[sizeof(WP_Packet) + WP_PACKET_SIZE]; +static uint16_t lastOutboundMessage; +static uint8_t* marker; + +// timeout to receive WP payload before bailing out +// 5 secs (100 nsecs units) +static const uint64_t c_PayloadTimeout = 50000000; + +extern void debug_printf( const char* format, ... ); +extern uint64_t HAL_Time_SysTicksToTime_C(unsigned int sysTicks); + +////////////////////////////////////////// +// helper functions + +void WP_ReplyToCommand(WP_Message* message, int fSuccess, int fCritical, void* ptr, int size) +{ + WP_Message msgReply; + uint32_t flags = 0; + + // + // Make sure we reply only once! + // + if(message->m_header.m_flags & WP_Flags_c_NonCritical) return; + message->m_header.m_flags |= WP_Flags_c_NonCritical; + + // + // No caching in the request, no caching in the reply... + // + if(message->m_header.m_flags & WP_Flags_c_NoCaching) flags |= WP_Flags_c_NoCaching; + + if(fSuccess ) flags |= WP_Flags_c_ACK; + else flags |= WP_Flags_c_NACK; + if(!fCritical) flags |= WP_Flags_c_NonCritical; + + if(fSuccess == false) + { + ptr = NULL; + size = 0; + } + + WP_Message_Initialize(&msgReply); + + WP_Message_PrepareReply(&msgReply, &message->m_header, flags, size, (uint8_t*)ptr ); + + WP_TransmitMessage(&msgReply); +} + +void WP_Message_Initialize(WP_Message* message) +{ + memset(&message->m_header, 0, sizeof(message->m_header)); + message->m_payload = NULL; + message->m_pos = NULL; + message->m_size = 0; + message->m_payloadTicks = 0; + message->m_rxState = ReceiveState_Idle; +} + +void WP_Message_PrepareReception(WP_Message* message) +{ + message->m_rxState = ReceiveState_Initialize; +} + +void WP_Message_PrepareRequest(WP_Message* message, uint32_t cmd, uint32_t flags, uint32_t payloadSize, uint8_t* payload) +{ + memcpy(&message->m_header.m_signature, marker ? marker : (uint8_t*)MARKER_PACKET_V1, sizeof(message->m_header.m_signature)); + +#if defined(WP_IMPLEMENTS_CRC32) + message->m_header.m_crcData = SUPPORT_ComputeCRC(payload, payloadSize, 0); +#else + message->m_header.m_crcData = 0; +#endif + message->m_header.m_cmd = cmd; + message->m_header.m_seq = lastOutboundMessage++; + message->m_header.m_seqReply = 0; + message->m_header.m_flags = flags; + message->m_header.m_size = payloadSize; + message->m_payload = payload; + + // + // The CRC for the header is computed setting the CRC field to zero and then running the CRC algorithm. + // + message->m_header.m_crcHeader = 0; +#if defined(WP_IMPLEMENTS_CRC32) + message->m_header.m_crcHeader = SUPPORT_ComputeCRC((uint8_t*)&message->m_header, sizeof(message->m_header), 0); +#endif +} + + +void WP_Message_PrepareReply(WP_Message* message, const WP_Packet* req, uint32_t flags, uint32_t payloadSize, uint8_t* payload) +{ + memcpy(&message->m_header.m_signature, marker ? marker : (uint8_t*)MARKER_PACKET_V1, sizeof(message->m_header.m_signature)); + +#if defined(WP_IMPLEMENTS_CRC32) + message->m_header.m_crcData = SUPPORT_ComputeCRC(payload, payloadSize, 0); +#else + message->m_header.m_crcData = 0; +#endif + message->m_header.m_cmd = req->m_cmd; + message->m_header.m_seq = lastOutboundMessage++; + message->m_header.m_seqReply = req->m_seq; + message->m_header.m_flags = flags | WP_Flags_c_Reply; + message->m_header.m_size = payloadSize; + message->m_payload = payload; + + // + // The CRC for the header is computed setting the CRC field to zero and then running the CRC algorithm. + // + message->m_header.m_crcHeader = 0; +#if defined(WP_IMPLEMENTS_CRC32) + message->m_header.m_crcHeader = SUPPORT_ComputeCRC((uint8_t*)&message->m_header, sizeof(message->m_header), 0); +#endif +} + +void WP_Message_SetPayload(WP_Message* message, uint8_t* payload) +{ + message->m_payload = payload; +} + +void WP_Message_Release(WP_Message* message) +{ + if(message->m_payload) + { + message->m_payload = NULL; + } +} + +int WP_Message_VerifyHeader(WP_Message* message) +{ + message->m_header.m_crcHeader = 0; + +#if defined(WP_IMPLEMENTS_CRC32) + + uint32_t crc = message->m_header.m_crcHeader; + + uint32_t computedCrc = SUPPORT_ComputeCRC((uint8_t*)&message->m_header, sizeof(message->m_header), 0); + message->m_header.m_crcHeader = crc; + + if(computedCrc != crc) + { + TRACE( TRACE_ERRORS, "Header CRC check failed: computed: 0x%08X; got: 0x%08X\n", computedCrc, message->m_header.m_crcHeader ); + return false; + } + +#endif + + return true; +} + +int WP_Message_VerifyPayload(WP_Message* message) +{ + if(message->m_payload == NULL && message->m_header.m_size) + { + return false; + } + +#if defined(WP_IMPLEMENTS_CRC32) + + uint32_t computedCrc = SUPPORT_ComputeCRC(message->m_payload, message->m_header.m_size, 0); + if(computedCrc != message->m_header.m_crcData) + { + TRACE( TRACE_ERRORS, "Payload CRC check failed: computed: 0x%08X; got: 0x%08X\n", computedCrc, message->m_header.m_crcData ); + return false; + } + +#endif + + return true; +} + +void WP_Message_ReplyBadPacket(uint32_t flags) +{ + WP_Message message; + WP_Message_Initialize(&message); + WP_Message_PrepareRequest(&message, 0, WP_Flags_c_NonCritical | WP_Flags_c_NACK | flags, 0, NULL); + + WP_TransmitMessage(&message); +} + +int WP_Message_Process(WP_Message* message) +{ + uint8_t* buf = (uint8_t*)&message->m_header; + uint16_t len; + + while(true) + { + switch(message->m_rxState) + { + case ReceiveState_Idle: + TRACE0( TRACE_STATE, "RxState==IDLE\n"); + return true; + + case ReceiveState_Initialize: + TRACE0( TRACE_STATE, "RxState==INIT\n"); + WP_Message_Release(message); + + message->m_rxState = ReceiveState_WaitingForHeader; + message->m_pos = (uint8_t*)&message->m_header; + message->m_size = sizeof(message->m_header); + break; + + case ReceiveState_WaitingForHeader: + TRACE0( TRACE_STATE, "RxState==WaitForHeader\n"); + if(WP_ReceiveBytes(message->m_pos, &message->m_size) == false) + { + // didn't receive the expected amount of bytes, returning false + TRACE0( TRACE_NODATA, "ReceiveBytes returned false - bailing out\n"); + return false; + } + + // Synch to the start of a message. + while(true) + { + len = sizeof(message->m_header) - message->m_size; + if(len <= 0) + { + break; + } + + size_t lenCmp = min(len, sizeof(message->m_header.m_signature)); + + if(memcmp(&message->m_header, MARKER_DEBUGGER_V1, lenCmp) == 0) + { + break; + } + if(memcmp(&message->m_header, MARKER_PACKET_V1, lenCmp) == 0) + { + break; + } + + memmove(&buf[0], &buf[1], len-1); + + message->m_pos--; + message->m_size++; + } + + if(len >= sizeof(message->m_header.m_signature)) + { + message->m_rxState = ReceiveState_ReadingHeader; + } + break; + + case ReceiveState_ReadingHeader: + TRACE0( TRACE_STATE, "RxState==ReadingHeader\n"); + if(WP_ReceiveBytes(message->m_pos, &message->m_size) == false) + { + // didn't receive the expected amount of bytes, returning false + TRACE0( TRACE_NODATA, "ReceiveBytes returned false - bailing out\n"); + return false; + } + + if(message->m_size == 0) + { + message->m_rxState = ReceiveState_CompleteHeader; + } + break; + + case ReceiveState_CompleteHeader: + { + TRACE0( TRACE_STATE, "RxState=CompleteHeader\n"); + bool fBadPacket = true; + + if(WP_Message_VerifyHeader(message)) + { + TRACE( TRACE_HEADERS, "RXMSG: 0x%08X, 0x%08X, 0x%08X\n", message->m_header.m_cmd, message->m_header.m_flags, message->m_header.m_size ); + + if(WP_App_ProcessHeader(message)) + { + fBadPacket = false; + + if(message->m_header.m_size) + { + if(message->m_payload == NULL) // Bad, no buffer... + { + message->m_rxState = ReceiveState_Initialize; + } + else + { + message->m_payloadTicks = HAL_Time_CurrentSysTicks(); + message->m_rxState = ReceiveState_ReadingPayload; + message->m_pos = message->m_payload; + message->m_size = message->m_header.m_size; + } + } + else + { + message->m_rxState = ReceiveState_CompletePayload; + } + } + } + + if(fBadPacket) + { + if((message->m_header.m_flags & WP_Flags_c_NonCritical) == 0) + { + WP_Message_ReplyBadPacket(WP_Flags_c_BadHeader); + } + + message->m_rxState = ReceiveState_Initialize; + } + } + break; + + case ReceiveState_ReadingPayload: + { + TRACE( TRACE_STATE, "RxState=ReadingPayload. Expecting %d bytes.\n", message->m_size); + + uint64_t curTicks = HAL_Time_CurrentSysTicks(); + + // If the time between consecutive payload bytes exceeds the timeout threshold then assume that + // the rest of the payload is not coming. Reinitialize to synch on the next header. + + if(HAL_Time_SysTicksToTime_C( curTicks - message->m_payloadTicks ) < c_PayloadTimeout) + { + message->m_payloadTicks = curTicks; + + if(WP_ReceiveBytes(message->m_pos, &message->m_size) == false) + { + // didn't receive the expected amount of bytes, returning false + TRACE0( TRACE_NODATA, "ReceiveBytes returned false - bailing out\n"); + return false; + } + + if(message->m_size == 0) + { + message->m_rxState = ReceiveState_CompletePayload; + } + } + else + { + TRACE0( TRACE_ERRORS, "RxError: Payload InterCharacterTimeout exceeded\n"); + message->m_rxState = ReceiveState_Initialize; + } + } + break; + + case ReceiveState_CompletePayload: + TRACE0( TRACE_STATE, "RxState=CompletePayload\n"); + if(WP_Message_VerifyPayload(message) == true) + { + WP_App_ProcessPayload(message); + } + else + { + WP_Message_ReplyBadPacket(WP_Flags_c_BadPayload); + } + + message->m_rxState = ReceiveState_Initialize; + break; + + default: + // unknow state + TRACE0( TRACE_ERRORS, "RxState=UNKNOWN!!\n"); + return false; + } + } +} + +void WP_SendProtocolMessage(WP_Message *message) +{ + TRACE( TRACE_HEADERS, "TXMSG: 0x%08X, 0x%08X, 0x%08X\n", message->m_header.m_cmd, message->m_header.m_flags, message->m_header.m_size ); + WP_TransmitMessage(message); +} + +void WP_PrepareAndSendProtocolMessage(uint32_t cmd, uint32_t payloadSize, uint8_t* payload, uint32_t flags) +{ + WP_Message message; + WP_Message_Initialize(&message); + WP_Message_PrepareRequest(&message, cmd, flags, payloadSize, payload); + + TRACE( TRACE_HEADERS, "TXMSG: 0x%08X, 0x%08X, 0x%08X\n", message.m_header.m_cmd, message.m_header.m_flags, message.m_header.m_size ); + WP_TransmitMessage(&message); +} + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// weak implementations of the functions (to be replaced with _strong_ implementations if and when required) // + +__nfweak void debug_printf( const char* format, ... ) +{ + (void)format; + + return; +} + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/src/CLR/WireProtocol/WireProtocol_MonitorCommands.c b/source/native/nf-interpreter/src/CLR/WireProtocol/WireProtocol_MonitorCommands.c new file mode 100644 index 00000000..040c554a --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/WireProtocol/WireProtocol_MonitorCommands.c @@ -0,0 +1,108 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "WireProtocol_MonitorCommands.h" + +//////////////////////////////////////////////////// + +// provided as weak to be replaced by actual implementation by application +__nfweak int Monitor_Ping(WP_Message* message) +{ + (void)(message); + + // default to false + return false; +} + +// provided as weak to be replaced by actual implementation by application +__nfweak int Monitor_OemInfo(WP_Message* message) +{ + (void)(message); + + // default to false + return false; +} + +// provided as weak to be replaced by actual implementation by application +__nfweak int Monitor_ReadMemory(WP_Message* message) +{ + (void)(message); + + // default to false + return false; +} + +// provided as weak to be replaced by actual implementation by application +__nfweak int Monitor_WriteMemory(WP_Message* message) +{ + (void)(message); + + // default to false + return false; +} + +// provided as weak to be replaced by actual implementation by application +__nfweak int Monitor_Reboot(WP_Message* message) +{ + (void)(message); + + // default to false + return false; +} + +// provided as weak to be replaced by actual implementation by application +__nfweak int Monitor_EraseMemory(WP_Message* message) +{ + (void)(message); + + // default to false + return false; +} + +// provided as weak to be replaced by actual implementation by application +__nfweak int Monitor_QueryConfiguration(WP_Message* message) +{ + (void)(message); + + // default to false + return false; +} + +// provided as weak to be replaced by actual implementation by application +__nfweak int Monitor_UpdateConfiguration(WP_Message* message) +{ + (void)(message); + + // default to false + return false; +} + +// provided as weak to be replaced by actual implementation by application +__nfweak int Monitor_CheckMemory(WP_Message* message) +{ + (void)(message); + + // default to false + return false; +} + +// provided as weak to be replaced by actual implementation by application +__nfweak int Monitor_MemoryMap(WP_Message* message) +{ + (void)(message); + + // default to false + return false; +} + +// provided as weak to be replaced by actual implementation by application +__nfweak int Monitor_FlashSectorMap(WP_Message* message) +{ + (void)(message); + + // default to false + return false; +} diff --git a/source/native/nf-interpreter/src/CLR/WireProtocol/targetHAL_time.cpp b/source/native/nf-interpreter/src/CLR/WireProtocol/targetHAL_time.cpp new file mode 100644 index 00000000..d3c5a5ac --- /dev/null +++ b/source/native/nf-interpreter/src/CLR/WireProtocol/targetHAL_time.cpp @@ -0,0 +1,22 @@ + +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include + +extern "C" { + + uint64_t HAL_Time_SysTicksToTime_C(unsigned int sysTicks) + { + return 0; + } + + unsigned int HAL_Time_CurrentSysTicks() + { + // TODO need to check if using the Win32 100ns ticks works + return 0; // UNDONE: FIXME: EmulatorNative::GetITimeDriver()->CurrentTicks(); + } +} diff --git a/source/native/nf-interpreter/src/DeviceInterfaces/Networking.Sntp/nf_lwipopts_sntp.h b/source/native/nf-interpreter/src/DeviceInterfaces/Networking.Sntp/nf_lwipopts_sntp.h new file mode 100644 index 00000000..55d0603c --- /dev/null +++ b/source/native/nf-interpreter/src/DeviceInterfaces/Networking.Sntp/nf_lwipopts_sntp.h @@ -0,0 +1,37 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +// lwIP options related with SNTP + +#ifndef __NF_LWIPOPTS_SNTP_H__ +#define __NF_LWIPOPTS_SNTP_H__ + +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +extern void SetSystemTimeFromUnixEpoch(uint32_t seconds); + +#ifdef __cplusplus +} +#endif + +// SNTP servers can be IP or full address and are resolved at +#define SNTP_SERVER_DNS 1 + +// use two servers +#define SNTP_MAX_SERVERS 2 + +// call to set the system time with seconds (Unix Epoch time) +#define SNTP_SET_SYSTEM_TIME SetSystemTimeFromUnixEpoch + +// need to declare this here to keep compiler happy +__nfweak char* ctime (const time_t * timer); + +#endif // __NF_LWIPOPTS_SNTP_H__ diff --git a/source/native/nf-interpreter/src/DeviceInterfaces/Networking.Sntp/nf_networking_sntp.cpp b/source/native/nf-interpreter/src/DeviceInterfaces/Networking.Sntp/nf_networking_sntp.cpp new file mode 100644 index 00000000..2156bf7e --- /dev/null +++ b/source/native/nf-interpreter/src/DeviceInterfaces/Networking.Sntp/nf_networking_sntp.cpp @@ -0,0 +1,27 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "nf_networking_sntp.h" + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + Library_nf_networking_sntp_nanoFramework_Networking_Sntp::Start___STATIC__VOID, + Library_nf_networking_sntp_nanoFramework_Networking_Sntp::Stop___STATIC__VOID, + Library_nf_networking_sntp_nanoFramework_Networking_Sntp::UpdateNow___STATIC__VOID, + Library_nf_networking_sntp_nanoFramework_Networking_Sntp::get_IsStarted___STATIC__BOOLEAN, + Library_nf_networking_sntp_nanoFramework_Networking_Sntp::get_Server1___STATIC__STRING, + Library_nf_networking_sntp_nanoFramework_Networking_Sntp::set_Server1___STATIC__VOID__STRING, + Library_nf_networking_sntp_nanoFramework_Networking_Sntp::get_Server2___STATIC__STRING, + Library_nf_networking_sntp_nanoFramework_Networking_Sntp::set_Server2___STATIC__VOID__STRING, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Networking_Sntp = +{ + "nanoFramework.Networking.Sntp", + 0xB617FDFB, + method_lookup, + { 100, 0, 4, 3 } +}; diff --git a/source/native/nf-interpreter/src/DeviceInterfaces/Networking.Sntp/nf_networking_sntp.h b/source/native/nf-interpreter/src/DeviceInterfaces/Networking.Sntp/nf_networking_sntp.h new file mode 100644 index 00000000..d6313818 --- /dev/null +++ b/source/native/nf-interpreter/src/DeviceInterfaces/Networking.Sntp/nf_networking_sntp.h @@ -0,0 +1,42 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#ifndef _NF_NETWORKING_SNTP_H_ +#define _NF_NETWORKING_SNTP_H_ + +#include +#include +#include +#include + +extern "C" +{ +#ifdef CC32XX +#include +#else +#include +#endif +} + +struct Library_nf_networking_sntp_nanoFramework_Networking_Sntp +{ + NANOCLR_NATIVE_DECLARE(Start___STATIC__VOID); + NANOCLR_NATIVE_DECLARE(Stop___STATIC__VOID); + NANOCLR_NATIVE_DECLARE(UpdateNow___STATIC__VOID); + NANOCLR_NATIVE_DECLARE(get_IsStarted___STATIC__BOOLEAN); + NANOCLR_NATIVE_DECLARE(get_Server1___STATIC__STRING); + NANOCLR_NATIVE_DECLARE(set_Server1___STATIC__VOID__STRING); + NANOCLR_NATIVE_DECLARE(get_Server2___STATIC__STRING); + NANOCLR_NATIVE_DECLARE(set_Server2___STATIC__VOID__STRING); + + //--// + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Networking_Sntp; + +#endif //_NF_NETWORKING_SNTP_H_ diff --git a/source/native/nf-interpreter/src/DeviceInterfaces/Networking.Sntp/nf_networking_sntp_nanoFramework_Networking_Sntp.cpp b/source/native/nf-interpreter/src/DeviceInterfaces/Networking.Sntp/nf_networking_sntp_nanoFramework_Networking_Sntp.cpp new file mode 100644 index 00000000..4064338f --- /dev/null +++ b/source/native/nf-interpreter/src/DeviceInterfaces/Networking.Sntp/nf_networking_sntp_nanoFramework_Networking_Sntp.cpp @@ -0,0 +1,113 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#include "nf_networking_sntp.h" + + +HRESULT Library_nf_networking_sntp_nanoFramework_Networking_Sntp::Start___STATIC__VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + + sntp_init(); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nf_networking_sntp_nanoFramework_Networking_Sntp::Stop___STATIC__VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + + sntp_stop(); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nf_networking_sntp_nanoFramework_Networking_Sntp::UpdateNow___STATIC__VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + + // this is just a stop and start of the SNTP client + sntp_stop(); + sntp_init(); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nf_networking_sntp_nanoFramework_Networking_Sntp::get_IsStarted___STATIC__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + stack.SetResult_Boolean(sntp_enabled()); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_networking_sntp_nanoFramework_Networking_Sntp::get_Server1___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + stack.SetResult_String(sntp_getservername(0)); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_networking_sntp_nanoFramework_Networking_Sntp::set_Server1___STATIC__VOID__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get server name as string + char* serverName = (char*)stack.Arg0().RecoverString(); FAULT_ON_NULL(serverName); + + sntp_setservername(0, serverName); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_networking_sntp_nanoFramework_Networking_Sntp::get_Server2___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + stack.SetResult_String(sntp_getservername(1)); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_networking_sntp_nanoFramework_Networking_Sntp::set_Server2___STATIC__VOID__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get server name as string + char* serverName = (char*)stack.Arg0().RecoverString(); FAULT_ON_NULL(serverName); + + sntp_setservername(1, serverName); + } + NANOCLR_NOCLEANUP(); +} + +// need this declared as "C" because we are calling it from lwIP +extern "C" +{ +void SetSystemTimeFromUnixEpoch(uint32_t seconds) +{ + HAL_Time_SetUtcTime(((uint64_t)seconds * TIME_CONVERSION__TO_SECONDS) + TIME_UNIX_EPOCH_AS_TICKS); +} +} diff --git a/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native.cpp b/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native.cpp new file mode 100644 index 00000000..c9c94b58 --- /dev/null +++ b/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native.cpp @@ -0,0 +1,305 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "sys_net_native.h" + + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_sys_net_native_System_Net_NetworkInformation_Wireless80211Configuration::GetWireless82011ConfigurationCount___STATIC__I4, + Library_sys_net_native_System_Net_NetworkInformation_Wireless80211Configuration::GetWireless82011Configuration___STATIC__SystemNetNetworkInformationWireless80211Configuration__I4, + Library_sys_net_native_System_Net_NetworkInformation_Wireless80211Configuration::UpdateConfiguration___STATIC__VOID, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration::GetWirelessAPConfigurationCount___STATIC__I4, + Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration::GetWirelessAPConfiguration___STATIC__SystemNetNetworkInformationWirelessAPConfiguration__I4, + Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration::UpdateConfiguration___STATIC__VOID, + Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration::NativeGetConnectedClients___STATIC__SZARRAY_SystemNetNetworkInformationWirelessAPStation__I4, + Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration::NativeDeauthStation___STATIC__STRING__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface::InitializeNetworkInterfaceSettings___VOID, + Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface::UpdateConfiguration___VOID__I4, + NULL, + Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface::GetNetworkInterfaceCount___STATIC__I4, + Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface::GetNetworkInterface___STATIC__SystemNetNetworkInformationNetworkInterface__U4, + Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface::IPAddressFromString___STATIC__U4__STRING, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_sys_net_native_System_Net_Security_CertificateManager::AddCaCertificateBundle___STATIC__BOOLEAN__SZARRAY_U1, + Library_sys_net_native_System_Net_Security_SslNative::SecureServerInit___STATIC__I4__I4__I4__SystemSecurityCryptographyX509CertificatesX509Certificate__SystemSecurityCryptographyX509CertificatesX509Certificate, + Library_sys_net_native_System_Net_Security_SslNative::SecureClientInit___STATIC__I4__I4__I4__SystemSecurityCryptographyX509CertificatesX509Certificate__SystemSecurityCryptographyX509CertificatesX509Certificate, + Library_sys_net_native_System_Net_Security_SslNative::SecureAccept___STATIC__VOID__I4__OBJECT, + Library_sys_net_native_System_Net_Security_SslNative::SecureConnect___STATIC__VOID__I4__STRING__OBJECT, + Library_sys_net_native_System_Net_Security_SslNative::SecureRead___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4, + Library_sys_net_native_System_Net_Security_SslNative::SecureWrite___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4, + Library_sys_net_native_System_Net_Security_SslNative::SecureCloseSocket___STATIC__I4__OBJECT, + Library_sys_net_native_System_Net_Security_SslNative::ExitSecureContext___STATIC__I4__I4, + Library_sys_net_native_System_Net_Security_SslNative::DataAvailable___STATIC__I4__OBJECT, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_sys_net_native_System_Net_Sockets_NativeSocket::socket___STATIC__I4__I4__I4__I4, + Library_sys_net_native_System_Net_Sockets_NativeSocket::bind___STATIC__VOID__OBJECT__SystemNetEndPoint, + Library_sys_net_native_System_Net_Sockets_NativeSocket::connect___STATIC__VOID__OBJECT__SystemNetEndPoint__BOOLEAN, + Library_sys_net_native_System_Net_Sockets_NativeSocket::send___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4, + Library_sys_net_native_System_Net_Sockets_NativeSocket::recv___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4, + Library_sys_net_native_System_Net_Sockets_NativeSocket::close___STATIC__I4__OBJECT, + Library_sys_net_native_System_Net_Sockets_NativeSocket::listen___STATIC__VOID__OBJECT__I4, + Library_sys_net_native_System_Net_Sockets_NativeSocket::accept___STATIC__I4__OBJECT, + Library_sys_net_native_System_Net_Sockets_NativeSocket::getaddrinfo___STATIC__VOID__STRING__BYREF_STRING__BYREF_SZARRAY_SZARRAY_U1, + Library_sys_net_native_System_Net_Sockets_NativeSocket::shutdown___STATIC__VOID__OBJECT__I4__BYREF_I4, + Library_sys_net_native_System_Net_Sockets_NativeSocket::sendto___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4__SystemNetEndPoint, + Library_sys_net_native_System_Net_Sockets_NativeSocket::recvfrom___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4__BYREF_SystemNetEndPoint, + Library_sys_net_native_System_Net_Sockets_NativeSocket::getpeername___STATIC__VOID__OBJECT__BYREF_SystemNetEndPoint, + Library_sys_net_native_System_Net_Sockets_NativeSocket::getsockname___STATIC__VOID__OBJECT__BYREF_SystemNetEndPoint, + Library_sys_net_native_System_Net_Sockets_NativeSocket::getsockopt___STATIC__VOID__OBJECT__I4__I4__SZARRAY_U1, + Library_sys_net_native_System_Net_Sockets_NativeSocket::setsockopt___STATIC__VOID__OBJECT__I4__I4__SZARRAY_U1, + Library_sys_net_native_System_Net_Sockets_NativeSocket::poll___STATIC__BOOLEAN__OBJECT__I4__I4, + Library_sys_net_native_System_Net_Sockets_NativeSocket::ioctl___STATIC__VOID__OBJECT__U4__BYREF_U4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_sys_net_native_System_Security_Cryptography_X509Certificates_X509Certificate::ParseCertificate___STATIC__VOID__SZARRAY_U1__STRING__BYREF_STRING__BYREF_STRING__BYREF_mscorlibSystemDateTime__BYREF_mscorlibSystemDateTime, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_sys_net_native_System_Security_Cryptography_X509Certificates_X509Certificate2::DecodePrivateKeyNative___STATIC__VOID__SZARRAY_U1__STRING, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Net = +{ + "System.Net", + 0x0B718489, + method_lookup, + { 100, 1, 3, 0 } +}; diff --git a/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native.h b/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native.h new file mode 100644 index 00000000..8c013b80 --- /dev/null +++ b/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native.h @@ -0,0 +1,336 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#ifndef _SYS_NET_NATIVE_H_ +#define _SYS_NET_NATIVE_H_ + +#include +#include +#include +#include +#include + +struct Library_sys_net_native_System_Net_NetworkInformation_Wireless80211Configuration +{ + static const int FIELD___configurationIndex = 1; + static const int FIELD___id = 2; + static const int FIELD___authentication = 3; + static const int FIELD___encryption = 4; + static const int FIELD___radio = 5; + static const int FIELD___password = 6; + static const int FIELD___ssid = 7; + static const int FIELD___options = 8; + + NANOCLR_NATIVE_DECLARE(GetWireless82011ConfigurationCount___STATIC__I4); + NANOCLR_NATIVE_DECLARE(GetWireless82011Configuration___STATIC__SystemNetNetworkInformationWireless80211Configuration__I4); + NANOCLR_NATIVE_DECLARE(UpdateConfiguration___STATIC__VOID); + + //--// + +}; + +struct Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration +{ + static const int FIELD___apConfigurationIndex = 1; + static const int FIELD___apId = 2; + static const int FIELD___apAuthentication = 3; + static const int FIELD___apEncryption = 4; + static const int FIELD___apRadio = 5; + static const int FIELD___apPassword = 6; + static const int FIELD___apSsid = 7; + static const int FIELD___options = 8; + static const int FIELD___apChannel = 9; + static const int FIELD___apMaxConnections = 10; + + NANOCLR_NATIVE_DECLARE(GetWirelessAPConfigurationCount___STATIC__I4); + NANOCLR_NATIVE_DECLARE(GetWirelessAPConfiguration___STATIC__SystemNetNetworkInformationWirelessAPConfiguration__I4); + NANOCLR_NATIVE_DECLARE(UpdateConfiguration___STATIC__VOID); + NANOCLR_NATIVE_DECLARE(NativeGetConnectedClients___STATIC__SZARRAY_SystemNetNetworkInformationWirelessAPStation__I4); + NANOCLR_NATIVE_DECLARE(NativeDeauthStation___STATIC__STRING__I4); + + //--// + +}; + +struct Library_sys_net_native_System_Net_NetworkInformation_NetworkChange +{ + static const int FIELD_STATIC__NetworkAddressChanged = 0; + static const int FIELD_STATIC__NetworkAvailabilityChanged = 1; + static const int FIELD_STATIC__NetworkAPStationChanged = 2; + + + //--// + +}; + +struct Library_sys_net_native_System_Net_NetworkInformation_NetworkChange__NetworkEvent +{ + static const int FIELD__EventType = 3; + static const int FIELD__Flags = 4; + static const int FIELD__Index = 5; + static const int FIELD__Data = 6; + static const int FIELD__Time = 7; + + + //--// + +}; + +struct Library_sys_net_native_System_Net_IPAddress +{ + static const int FIELD_STATIC__Any = 3; + static const int FIELD_STATIC__Loopback = 4; + + static const int FIELD___address = 1; + static const int FIELD___family = 2; + static const int FIELD___numbers = 3; + + + //--// + +}; + +struct Library_sys_net_native_System_Net_IPEndPoint +{ + static const int FIELD___address = 1; + static const int FIELD___port = 2; + + + //--// + +}; + +struct Library_sys_net_native_System_Net_IPHostEntry +{ + static const int FIELD__hostName = 1; + static const int FIELD__addressList = 2; + + + //--// + +}; + +struct Library_sys_net_native_System_Net_NetworkInformation_NetworkAPStationEventArgs +{ + static const int FIELD___stationIndex = 1; + static const int FIELD___isConnected = 2; + + + //--// + +}; + +struct Library_sys_net_native_System_Net_NetworkInformation_NetworkAvailabilityEventArgs +{ + static const int FIELD___isAvailable = 1; + + + //--// + +}; + +struct Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface +{ + static const int FIELD___interfaceIndex = 1; + static const int FIELD___macAddress = 2; + static const int FIELD___startupAddressMode = 3; + static const int FIELD___specificConfigId = 4; + static const int FIELD___automaticDns = 5; + static const int FIELD___ipv4Address = 6; + static const int FIELD___ipv4NetMask = 7; + static const int FIELD___ipv4GatewayAddress = 8; + static const int FIELD___ipv4dnsAddress1 = 9; + static const int FIELD___ipv4dnsAddress2 = 10; + static const int FIELD___ipv6Address = 11; + static const int FIELD___ipv6NetMask = 12; + static const int FIELD___ipv6GatewayAddress = 13; + static const int FIELD___ipv6dnsAddress1 = 14; + static const int FIELD___ipv6dnsAddress2 = 15; + static const int FIELD___networkInterfaceType = 16; + + NANOCLR_NATIVE_DECLARE(InitializeNetworkInterfaceSettings___VOID); + NANOCLR_NATIVE_DECLARE(UpdateConfiguration___VOID__I4); + NANOCLR_NATIVE_DECLARE(GetNetworkInterfaceCount___STATIC__I4); + NANOCLR_NATIVE_DECLARE(GetNetworkInterface___STATIC__SystemNetNetworkInformationNetworkInterface__U4); + NANOCLR_NATIVE_DECLARE(IPAddressFromString___STATIC__U4__STRING); + + //--// + +}; + +struct Library_sys_net_native_System_Net_NetworkInformation_WirelessAPStation +{ + static const int FIELD___macAddress = 1; + static const int FIELD___rssi = 2; + static const int FIELD___phyModes = 3; + + + //--// + +}; + +struct Library_sys_net_native_System_Net_Security_CertificateManager +{ + NANOCLR_NATIVE_DECLARE(AddCaCertificateBundle___STATIC__BOOLEAN__SZARRAY_U1); + + //--// + +}; + +struct Library_sys_net_native_System_Net_Security_SslNative +{ + NANOCLR_NATIVE_DECLARE(SecureServerInit___STATIC__I4__I4__I4__SystemSecurityCryptographyX509CertificatesX509Certificate__SystemSecurityCryptographyX509CertificatesX509Certificate); + NANOCLR_NATIVE_DECLARE(SecureClientInit___STATIC__I4__I4__I4__SystemSecurityCryptographyX509CertificatesX509Certificate__SystemSecurityCryptographyX509CertificatesX509Certificate); + NANOCLR_NATIVE_DECLARE(SecureAccept___STATIC__VOID__I4__OBJECT); + NANOCLR_NATIVE_DECLARE(SecureConnect___STATIC__VOID__I4__STRING__OBJECT); + NANOCLR_NATIVE_DECLARE(SecureRead___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4); + NANOCLR_NATIVE_DECLARE(SecureWrite___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4); + NANOCLR_NATIVE_DECLARE(SecureCloseSocket___STATIC__I4__OBJECT); + NANOCLR_NATIVE_DECLARE(ExitSecureContext___STATIC__I4__I4); + NANOCLR_NATIVE_DECLARE(DataAvailable___STATIC__I4__OBJECT); + + //--// + + static HRESULT ReadWriteHelper( CLR_RT_StackFrame& stack, bool isWrite ); + static HRESULT InitHelper ( CLR_RT_StackFrame& stack, bool isServer ); + static HRESULT ThrowOnError ( CLR_RT_StackFrame& stack, int err ); + static void ThrowError ( CLR_RT_StackFrame& stack, int errorCode ); + +}; + +struct Library_sys_net_native_System_Net_Sockets_NetworkStream +{ + static const int FIELD___socket = 1; + static const int FIELD___socketType = 2; + static const int FIELD___remoteEndPoint = 3; + static const int FIELD___ownsSocket = 4; + static const int FIELD___disposed = 5; + + + //--// + +}; + +struct Library_sys_net_native_System_Net_Security_SslStream +{ + static const int FIELD___sslVerification = 6; + static const int FIELD___sslContext = 7; + static const int FIELD___isServer = 8; + + + //--// + +}; + +struct Library_sys_net_native_System_Net_SocketAddress +{ + static const int FIELD__m_Buffer = 1; + static const int FIELD___address = 2; + + + //--// + +}; + +struct Library_sys_net_native_System_Net_Sockets_NativeSocket +{ + NANOCLR_NATIVE_DECLARE(socket___STATIC__I4__I4__I4__I4); + NANOCLR_NATIVE_DECLARE(bind___STATIC__VOID__OBJECT__SystemNetEndPoint); + NANOCLR_NATIVE_DECLARE(connect___STATIC__VOID__OBJECT__SystemNetEndPoint__BOOLEAN); + NANOCLR_NATIVE_DECLARE(send___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4); + NANOCLR_NATIVE_DECLARE(recv___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4); + NANOCLR_NATIVE_DECLARE(close___STATIC__I4__OBJECT); + NANOCLR_NATIVE_DECLARE(listen___STATIC__VOID__OBJECT__I4); + NANOCLR_NATIVE_DECLARE(accept___STATIC__I4__OBJECT); + NANOCLR_NATIVE_DECLARE(getaddrinfo___STATIC__VOID__STRING__BYREF_STRING__BYREF_SZARRAY_SZARRAY_U1); + NANOCLR_NATIVE_DECLARE(shutdown___STATIC__VOID__OBJECT__I4__BYREF_I4); + NANOCLR_NATIVE_DECLARE(sendto___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4__SystemNetEndPoint); + NANOCLR_NATIVE_DECLARE(recvfrom___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4__BYREF_SystemNetEndPoint); + NANOCLR_NATIVE_DECLARE(getpeername___STATIC__VOID__OBJECT__BYREF_SystemNetEndPoint); + NANOCLR_NATIVE_DECLARE(getsockname___STATIC__VOID__OBJECT__BYREF_SystemNetEndPoint); + NANOCLR_NATIVE_DECLARE(getsockopt___STATIC__VOID__OBJECT__I4__I4__SZARRAY_U1); + NANOCLR_NATIVE_DECLARE(setsockopt___STATIC__VOID__OBJECT__I4__I4__SZARRAY_U1); + NANOCLR_NATIVE_DECLARE(poll___STATIC__BOOLEAN__OBJECT__I4__I4); + NANOCLR_NATIVE_DECLARE(ioctl___STATIC__VOID__OBJECT__U4__BYREF_U4); + + //--// + static HRESULT MarshalSockAddress( struct SOCK_sockaddr* addrDst, CLR_UINT32& addrLenDst, const CLR_RT_HeapBlock& blkEndPointAddress ); + static HRESULT MarshalSockAddress( CLR_RT_HeapBlock& blkDst, const struct SOCK_sockaddr* addrSrc, CLR_UINT32 addrLenSrc ); + static HRESULT SendRecvHelper( CLR_RT_StackFrame& stack, bool fSend, bool fAddress ); + static HRESULT SockOptHelper( CLR_RT_StackFrame& stack, bool fGet ); + static HRESULT SockNameHelper( CLR_RT_StackFrame& stack, bool fPeer ); + static HRESULT BindConnectHelper( CLR_RT_StackFrame& stack, bool fBind ); + static HRESULT ThrowOnError( CLR_RT_StackFrame& stack, CLR_INT32 err ); + static void ThrowError( CLR_RT_StackFrame& stack, CLR_INT32 errorCode ); + + static CLR_INT32 Helper__SelectSocket( CLR_INT32 socket, CLR_INT32 mode ); + + /* WARNING!!! + * The value of this constant is the offset for the m_Handle field in the System.Net.Sockets.Socket class. + * It is defined here to avoid a circular reference issue. + */ + static const int FIELD__m_Handle = 1; + + static const int DISPOSED_HANDLE = -1; +}; + +struct Library_sys_net_native_System_Net_Sockets_Socket +{ + static const int FIELD__m_Handle = 1; + static const int FIELD__m_fBlocking = 2; + static const int FIELD__m_localEndPoint = 3; + static const int FIELD__m_recvTimeout = 4; + static const int FIELD__m_sendTimeout = 5; + static const int FIELD___socketType = 6; + static const int FIELD___nonBlockingConnectInProgress = 7; + static const int FIELD___nonBlockingConnectRightEndPoint = 8; + static const int FIELD___rightEndPoint = 9; + + + //--// + +}; + +struct Library_sys_net_native_System_Net_Sockets_SocketException +{ + static const int FIELD___errorCode = 5; + + + //--// + +}; + +struct Library_sys_net_native_System_Security_Cryptography_X509Certificates_X509Certificate +{ + static const int FIELD___certificate = 1; + static const int FIELD___password = 2; + static const int FIELD___issuer = 3; + static const int FIELD___subject = 4; + static const int FIELD___effectiveDate = 5; + static const int FIELD___expirationDate = 6; + static const int FIELD___handle = 7; + static const int FIELD___sessionHandle = 8; + + NANOCLR_NATIVE_DECLARE(ParseCertificate___STATIC__VOID__SZARRAY_U1__STRING__BYREF_STRING__BYREF_STRING__BYREF_mscorlibSystemDateTime__BYREF_mscorlibSystemDateTime); + + //--// + +}; + +struct Library_sys_net_native_System_Security_Cryptography_X509Certificates_X509Certificate2 +{ + static const int FIELD___privateKey = 9; + + NANOCLR_NATIVE_DECLARE(DecodePrivateKeyNative___STATIC__VOID__SZARRAY_U1__STRING); + + //--// + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Net; + +#endif //_SYS_NET_NATIVE_H_ diff --git a/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_NetworkInformation_NetworkInterface.cpp b/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_NetworkInformation_NetworkInterface.cpp new file mode 100644 index 00000000..f77c5689 --- /dev/null +++ b/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_NetworkInformation_NetworkInterface.cpp @@ -0,0 +1,277 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "sys_net_native.h" + +void Network_PostEvent( unsigned int eventType, unsigned int flags, unsigned int index) +{ + PostManagedEvent( EVENT_NETWORK, eventType, flags, index ); +} + +HRESULT Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface::InitializeNetworkInterfaceSettings___VOID( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + HAL_Configuration_NetworkInterface config; + CLR_RT_HeapBlock* pConfig = stack.Arg0().Dereference(); _ASSERTE(pConfig != NULL); + + CLR_UINT32 interfaceIndex = pConfig[ FIELD___interfaceIndex ].NumericByRefConst().u4; + + NANOCLR_CLEAR(config); + + // load network interface configuration from storage + if(!ConfigurationManager_GetConfigurationBlock((void*)&config, DeviceConfigurationOption_Network, interfaceIndex)) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + _ASSERTE(config.StartupAddressMode > 0); + + // now load adapter configuration on top of the stored config + NANOCLR_CHECK_HRESULT(SOCK_CONFIGURATION_LoadAdapterConfiguration(&config, interfaceIndex)); + + pConfig[ FIELD___ipv4Address ].SetInteger( (CLR_UINT32)config.IPv4Address); + pConfig[ FIELD___ipv4GatewayAddress ].SetInteger( (CLR_UINT32)config.IPv4GatewayAddress); + pConfig[ FIELD___ipv4NetMask ].SetInteger( (CLR_UINT32)config.IPv4NetMask); + pConfig[ FIELD___ipv4dnsAddress1 ].SetInteger( (CLR_UINT32)config.IPv4DNSAddress1); + pConfig[ FIELD___ipv4dnsAddress2 ].SetInteger( (CLR_UINT32)config.IPv4DNSAddress2); + + // FIXME IPV6 + // pConfig[ FIELD___ipv6Address ].SetInteger( (CLR_UINT32)config.IPv6Address); + // pConfig[ FIELD___ipv6GatewayAddress ].SetInteger( (CLR_UINT32)config.IPv6GatewayAddress); + // pConfig[ FIELD___ipv6NetMask ].SetInteger( (CLR_UINT32)config.IPv6NetMask); + // pConfig[ FIELD___ipv6dnsAddress1 ].SetInteger( (CLR_UINT32)config.IPv6DNSAddress1); + // pConfig[ FIELD___ipv6dnsAddress2 ].SetInteger( (CLR_UINT32)config.IPv6DNSAddress2); + + pConfig[ FIELD___automaticDns ].SetInteger( (CLR_UINT32)config.AutomaticDNS); + pConfig[ FIELD___networkInterfaceType ].SetInteger( (CLR_UINT32)config.InterfaceType); + pConfig[ FIELD___specificConfigId ].SetInteger( (CLR_UINT32)config.SpecificConfigId); + pConfig[ FIELD___startupAddressMode ].SetInteger( (CLR_UINT32)config.StartupAddressMode); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( pConfig[ FIELD___macAddress ], NETIF_MAX_HWADDR_LEN, g_CLR_RT_WellKnownTypes.m_UInt8)); + memcpy(pConfig[ FIELD___macAddress ].DereferenceArray()->GetFirstElement(), config.MacAddress, NETIF_MAX_HWADDR_LEN); + + NANOCLR_NOCLEANUP(); +} + +inline bool operator!=(const HAL_Configuration_NetworkInterface &lhs, const HAL_Configuration_NetworkInterface &rhs) { + if (lhs.IPv4Address != rhs.IPv4Address) { + return true; + } + + if (lhs.IPv4GatewayAddress != rhs.IPv4GatewayAddress) { + return true; + } + + if (lhs.IPv4NetMask != rhs.IPv4NetMask) { + return true; + } + + if (lhs.IPv4DNSAddress1 != rhs.IPv4DNSAddress1) { + return true; + } + + if (lhs.IPv4DNSAddress2 != rhs.IPv4DNSAddress2) { + return true; + } + + if (lhs.AutomaticDNS != rhs.AutomaticDNS) { + return true; + } + + if (lhs.InterfaceType != rhs.InterfaceType) { + return true; + } + + if (lhs.SpecificConfigId != rhs.SpecificConfigId) { + return true; + } + + if (lhs.StartupAddressMode != rhs.StartupAddressMode) { + return true; + } + + if (memcmp(lhs.MacAddress, rhs.MacAddress, sizeof(rhs.MacAddress))) { + return true; + } + + if (memcmp(lhs.IPv6Address, rhs.IPv6Address, sizeof(rhs.IPv6Address))) { + return true; + } + + if (memcmp(lhs.IPv6NetMask, rhs.IPv6NetMask, sizeof(rhs.IPv6NetMask))) { + return true; + } + + if (memcmp(lhs.IPv6GatewayAddress, rhs.IPv6GatewayAddress, sizeof(rhs.IPv6GatewayAddress))) { + return true; + } + + if (memcmp(lhs.IPv6DNSAddress1, rhs.IPv6DNSAddress1, sizeof(rhs.IPv6DNSAddress1))) { + return true; + } + + if (memcmp(lhs.IPv6DNSAddress2, rhs.IPv6DNSAddress2, sizeof(rhs.IPv6DNSAddress2))) { + return true; + } + + return false; +} + +HRESULT Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface::UpdateConfiguration___VOID__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + HAL_Configuration_NetworkInterface config, storageConfig; + bool configChanged; + CLR_RT_HeapBlock* pConfig = stack.Arg0().Dereference(); _ASSERTE(pConfig != NULL); + CLR_UINT32 interfaceIndex = pConfig[ FIELD___interfaceIndex ].NumericByRefConst().u4; + CLR_UINT32 updateFlags = stack.Arg1().NumericByRef().u4; + CLR_RT_HeapBlock_Array* pMACAddress = pConfig[ FIELD___macAddress ].DereferenceArray(); + + NANOCLR_CLEAR(config); + NANOCLR_CLEAR(storageConfig); + + config.IPv4Address = pConfig[ FIELD___ipv4Address ].NumericByRef().u4; + config.IPv4GatewayAddress = pConfig[ FIELD___ipv4GatewayAddress ].NumericByRef().u4; + config.IPv4NetMask = pConfig[ FIELD___ipv4NetMask ].NumericByRef().u4; + config.IPv4DNSAddress1 = pConfig[ FIELD___ipv4dnsAddress1 ].NumericByRef().u4; + config.IPv4DNSAddress2 = pConfig[ FIELD___ipv4dnsAddress2 ].NumericByRef().u4; + + // FIXME IPV6 + // config.IPv6Address = pConfig[ FIELD___ipv6Address ].NumericByRef().u4; + // config.IPv6GatewayAddress = pConfig[ FIELD___ipv6GatewayAddress ].NumericByRef().u4; + // config.IPv6NetMask = pConfig[ FIELD___ipv6NetMask ].NumericByRef().u4; + // config.IPv6DNSAddress1 = pConfig[ FIELD___ipv6dnsAddress1 ].NumericByRef().u4; + // config.IPv6DNSAddress2 = pConfig[ FIELD___ipv6dnsAddress2 ].NumericByRef().u4; + + config.AutomaticDNS = pConfig[ FIELD___automaticDns ].NumericByRef().u4; + config.InterfaceType = (NetworkInterfaceType) pConfig[ FIELD___networkInterfaceType ].NumericByRef().u4; + config.SpecificConfigId = (CLR_UINT32) pConfig[ FIELD___specificConfigId ].NumericByRef().u4; + config.StartupAddressMode = (AddressMode) pConfig[ FIELD___startupAddressMode ].NumericByRef().u4; + + if(pMACAddress != NULL) + { + memcpy( &config.MacAddress, pMACAddress->GetFirstElement(), NETIF_MAX_HWADDR_LEN ); + } + + // load network interface configuration from storage + if(!ConfigurationManager_GetConfigurationBlock((void*)&storageConfig, DeviceConfigurationOption_Network, interfaceIndex)) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + + // save the configuration only if there has been a change + configChanged = (config != storageConfig); + + // store configuration, updating the configuration block + if(configChanged && ConfigurationManager_UpdateConfigurationBlock(&config, DeviceConfigurationOption_Network, interfaceIndex) != TRUE) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + + NANOCLR_CHECK_HRESULT(SOCK_CONFIGURATION_UpdateAdapterConfiguration(&config, interfaceIndex, updateFlags)); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface::GetNetworkInterfaceCount___STATIC__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + // grab the count right from the structure + stack.SetResult_I4( g_TargetConfiguration.NetworkInterfaceConfigs->Count ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface::GetNetworkInterface___STATIC__SystemNetNetworkInformationNetworkInterface__U4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + HAL_Configuration_NetworkInterface config; + CLR_RT_HeapBlock* pConfig; + CLR_UINT32 interfaceIndex = stack.Arg0().NumericByRef().u4; + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + + NANOCLR_CLEAR(config); + + // load network interface configuration from storage + if(!ConfigurationManager_GetConfigurationBlock((void*)&config, DeviceConfigurationOption_Network, interfaceIndex)) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + _ASSERTE(config.StartupAddressMode > 0); + + // now load adapter configuration on top of the stored config + NANOCLR_CHECK_HRESULT(SOCK_CONFIGURATION_LoadConfiguration(&config, interfaceIndex)); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex( top, g_CLR_RT_WellKnownTypes.m_NetworkInterface )); + + pConfig = top.Dereference(); FAULT_ON_NULL(pConfig); + + pConfig[ FIELD___ipv4Address ].SetInteger( (CLR_UINT32)config.IPv4Address); + pConfig[ FIELD___ipv4GatewayAddress ].SetInteger( (CLR_UINT32)config.IPv4GatewayAddress); + pConfig[ FIELD___ipv4NetMask ].SetInteger( (CLR_UINT32)config.IPv4NetMask); + pConfig[ FIELD___ipv4dnsAddress1 ].SetInteger( (CLR_UINT32)config.IPv4DNSAddress1); + pConfig[ FIELD___ipv4dnsAddress2 ].SetInteger( (CLR_UINT32)config.IPv4DNSAddress2); + + // FIXME IPV6 + // pConfig[ FIELD___ipv6Address ].SetInteger( (CLR_UINT32)config.IPv6Address); + // pConfig[ FIELD___ipv6GatewayAddress ].SetInteger( (CLR_UINT32)config.IPv6GatewayAddress); + // pConfig[ FIELD___ipv6NetMask ].SetInteger( (CLR_UINT32)config.IPv6NetMask); + // pConfig[ FIELD___ipv6dnsAddress1 ].SetInteger( (CLR_UINT32)config.IPv6DNSAddress1); + // pConfig[ FIELD___ipv6dnsAddress2 ].SetInteger( (CLR_UINT32)config.IPv6DNSAddress2); + + pConfig[ FIELD___automaticDns ].SetInteger( (CLR_UINT32)config.AutomaticDNS); + pConfig[ FIELD___networkInterfaceType ].SetInteger( (CLR_UINT32)config.InterfaceType); + pConfig[ FIELD___specificConfigId ].SetInteger( (CLR_UINT32)config.SpecificConfigId); + pConfig[ FIELD___startupAddressMode ].SetInteger( (CLR_UINT32)config.StartupAddressMode); + pConfig[ FIELD___interfaceIndex ].SetInteger( (CLR_UINT32)interfaceIndex); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( pConfig[ FIELD___macAddress ], NETIF_MAX_HWADDR_LEN, g_CLR_RT_WellKnownTypes.m_UInt8 )); + memcpy( pConfig[ FIELD___macAddress ].DereferenceArray()->GetFirstElement(), config.MacAddress, NETIF_MAX_HWADDR_LEN ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_net_native_System_Net_NetworkInformation_NetworkInterface::IPAddressFromString___STATIC__U4__STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + LPCSTR szName = stack.Arg0().RecoverString(); + struct SOCK_addrinfo hints; + struct SOCK_addrinfo* addr = NULL; + struct SOCK_sockaddr_in* addr_in; + int ret; + + memset( &hints, 0, sizeof(hints) ); + + ret = SOCK_getaddrinfo( szName, NULL, &hints, &addr ); + + // getaddrinfo returns a winsock error code rather than SOCK_SOCKET_ERROR, so pass this on to the exception handling + if(ret != 0 || addr == NULL || addr->ai_family != SOCK_AF_INET) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + + _ASSERTE(addr->ai_addr != NULL); + _ASSERTE(addr->ai_addrlen >= sizeof(SOCK_sockaddr_in)); + + addr_in = (struct SOCK_sockaddr_in*)addr->ai_addr; + + stack.PushValue().SetInteger( (CLR_UINT32)addr_in->sin_addr.S_un.S_addr ); + + NANOCLR_CLEANUP(); + + if( addr ) SOCK_freeaddrinfo( addr ); + + NANOCLR_CLEANUP_END(); +} diff --git a/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_NetworkInformation_Wireless80211Configuration.cpp b/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_NetworkInformation_Wireless80211Configuration.cpp new file mode 100644 index 00000000..0935dbb7 --- /dev/null +++ b/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_NetworkInformation_Wireless80211Configuration.cpp @@ -0,0 +1,103 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "sys_net_native.h" + +HRESULT Library_sys_net_native_System_Net_NetworkInformation_Wireless80211Configuration::GetWireless82011ConfigurationCount___STATIC__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + // grab the count right from the structure + stack.SetResult_I4(g_TargetConfiguration.Wireless80211Configs->Count); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_sys_net_native_System_Net_NetworkInformation_Wireless80211Configuration::GetWireless82011Configuration___STATIC__SystemNetNetworkInformationWireless80211Configuration__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + HAL_Configuration_Wireless80211 config; + CLR_RT_HeapBlock* pConfig; + CLR_UINT32 configurationIndex = stack.Arg0().NumericByRef().u4; + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + + NANOCLR_CLEAR(config); + + // load wireless 802.11 configuration from the storage + if(!ConfigurationManager_GetConfigurationBlock((void*)&config, DeviceConfigurationOption_Wireless80211Network, configurationIndex)) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + + // create new object for configuration + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_Wireless80211Configuration)); + + // load from stack + pConfig = top.Dereference(); FAULT_ON_NULL(pConfig); + + // fill in fields from config struct + pConfig[FIELD___id].SetInteger((CLR_UINT32)config.Id); + pConfig[FIELD___authentication].SetInteger((CLR_UINT32)config.Authentication); + pConfig[FIELD___encryption].SetInteger((CLR_UINT32)config.Encryption); + pConfig[FIELD___radio].SetInteger((CLR_UINT32)config.Radio); + pConfig[FIELD___options].SetInteger((CLR_UINT8)config.Flags); + + // the following ones are strings so a simple assignment isn't enough, need to create a managed string instance and copy over + // make sure the terminators are there + config.Password[WIRELESS82011_CONFIG_MAX_PASSWORD_LEN - 1] = 0; + config.Ssid[WIRELESS82011_CONFIG_MAX_SSID_LEN - 1] = 0; + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance(pConfig[FIELD___password], (const char*)config.Password)); + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance(pConfig[FIELD___ssid], (const char*)config.Ssid)); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_net_native_System_Net_NetworkInformation_Wireless80211Configuration::UpdateConfiguration___STATIC__VOID( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + HAL_Configuration_Wireless80211 config; + CLR_RT_HeapBlock* pConfig = stack.Arg0().Dereference(); _ASSERTE(pConfig != NULL); + + CLR_UINT32 configurationIndex = pConfig[FIELD___configurationIndex].NumericByRefConst().u4; + + CLR_RT_HeapBlock_String* hbPassword = NULL; + CLR_RT_HeapBlock_String* hbSsid = NULL; + CLR_UINT32 ssidLength; + CLR_UINT32 passwordLength; + + NANOCLR_CLEAR(config); + + config.Id = (CLR_UINT32)pConfig[FIELD___id].NumericByRef().u4; + config.Authentication = (AuthenticationType)pConfig[FIELD___authentication].NumericByRef().u4; + config.Encryption = (EncryptionType)pConfig[FIELD___encryption].NumericByRef().u4; + config.Radio = (RadioType)pConfig[FIELD___radio].NumericByRef().u4; + config.Flags = (uint8_t)pConfig[FIELD___options].NumericByRef().u1; + + // the following ones are strings + // make sure the terminators are there + hbPassword = pConfig[FIELD___password].DereferenceString(); FAULT_ON_NULL(hbPassword); + passwordLength = hal_strlen_s(hbPassword->StringText()); + if (passwordLength >= sizeof(config.Password)) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + hal_strncpy_s((char*)config.Password, WIRELESS82011_CONFIG_MAX_PASSWORD_LEN, hbPassword->StringText(), passwordLength); + + hbSsid = pConfig[FIELD___ssid].DereferenceString(); FAULT_ON_NULL(hbSsid); + ssidLength = hal_strlen_s(hbSsid->StringText()); + if (ssidLength >= sizeof(config.Ssid)) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + hal_strncpy_s((char*)config.Ssid, WIRELESS82011_CONFIG_MAX_SSID_LEN, hbSsid->StringText(), ssidLength); + + // store configuration + if(ConfigurationManager_UpdateConfigurationBlock(&config, DeviceConfigurationOption_Wireless80211Network, configurationIndex) != TRUE) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration.cpp b/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration.cpp new file mode 100644 index 00000000..97035bb9 --- /dev/null +++ b/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration.cpp @@ -0,0 +1,235 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "sys_net_native.h" + + +HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration::GetWirelessAPConfigurationCount___STATIC__I4( CLR_RT_StackFrame& stack ) +{ +#ifdef PLATFORM_ESP32 + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + // grab the count right from the structure + stack.SetResult_I4(g_TargetConfiguration.WirelessAPConfigs->Count); + + NANOCLR_NOCLEANUP_NOLABEL(); +#else + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +#endif +} + +HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration::GetWirelessAPConfiguration___STATIC__SystemNetNetworkInformationWirelessAPConfiguration__I4( CLR_RT_StackFrame& stack ) +{ +#ifdef PLATFORM_ESP32 + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + HAL_Configuration_WirelessAP config; + CLR_RT_HeapBlock* pConfig; + CLR_UINT32 configurationIndex = stack.Arg0().NumericByRef().u4; + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + + NANOCLR_CLEAR(config); + + // load wireless AP configuration from the storage + if(!ConfigurationManager_GetConfigurationBlock((void*)&config, DeviceConfigurationOption_WirelessNetworkAP, configurationIndex)) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + + // create new object for configuration + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_WirelessAPConfiguration)); + + // load from stack + pConfig = top.Dereference(); FAULT_ON_NULL(pConfig); + + // fill in fields from config struct + pConfig[FIELD___apId].SetInteger((CLR_UINT32)config.Id); + pConfig[FIELD___apAuthentication].SetInteger((CLR_UINT32)config.Authentication); + pConfig[FIELD___apEncryption].SetInteger((CLR_UINT32)config.Encryption); + pConfig[FIELD___apRadio].SetInteger((CLR_UINT32)config.Radio); + pConfig[FIELD___options].SetInteger((CLR_UINT8)config.Flags); + pConfig[FIELD___apChannel].SetInteger((CLR_UINT8)config.Channel); + pConfig[FIELD___apMaxConnections].SetInteger((CLR_UINT8)config.MaxConnections); + + // the following ones are strings so a simple assignment isn't enough, need to create a managed string instance and copy over + // make sure the terminators are there + config.Password[WIRELESS82011_CONFIG_MAX_PASSWORD_LEN - 1] = 0; + config.Ssid[WIRELESS82011_CONFIG_MAX_SSID_LEN - 1] = 0; + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance(pConfig[FIELD___apPassword], (const char*)config.Password)); + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance(pConfig[FIELD___apSsid], (const char*)config.Ssid)); + + NANOCLR_NOCLEANUP(); +#else + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +#endif +} + +HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration::UpdateConfiguration___STATIC__VOID( CLR_RT_StackFrame& stack ) +{ +#ifdef PLATFORM_ESP32 + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + HAL_Configuration_WirelessAP config; + CLR_RT_HeapBlock* pConfig = stack.Arg0().Dereference(); _ASSERTE(pConfig != NULL); + + CLR_UINT32 configurationIndex = pConfig[FIELD___apConfigurationIndex].NumericByRefConst().u4; + + CLR_RT_HeapBlock_String* hbPassword = NULL; + CLR_RT_HeapBlock_String* hbSsid = NULL; + CLR_UINT32 ssidLength; + CLR_UINT32 passwordLength; + + NANOCLR_CLEAR(config); + + config.Id = (CLR_UINT32)pConfig[FIELD___apId].NumericByRef().u4; + config.Authentication = (AuthenticationType)pConfig[FIELD___apAuthentication].NumericByRef().u4; + config.Encryption = (EncryptionType)pConfig[FIELD___apEncryption].NumericByRef().u4; + config.Radio = (RadioType)pConfig[FIELD___apRadio].NumericByRef().u4; + config.Flags = (uint8_t)pConfig[FIELD___options].NumericByRef().u1; + config.Channel = (uint8_t)pConfig[FIELD___apChannel].NumericByRef().u1; + config.MaxConnections = (uint8_t)pConfig[FIELD___apMaxConnections].NumericByRef().u1; + + // the following ones are strings + // make sure the terminators are there + hbPassword = pConfig[FIELD___apPassword].DereferenceString(); FAULT_ON_NULL(hbPassword); + passwordLength = hal_strlen_s(hbPassword->StringText()); + if (passwordLength >= sizeof(config.Password)) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + hal_strncpy_s((char*)config.Password, WIRELESS82011_CONFIG_MAX_PASSWORD_LEN, hbPassword->StringText(), passwordLength); + + hbSsid = pConfig[FIELD___apSsid].DereferenceString(); FAULT_ON_NULL(hbSsid); + ssidLength = hal_strlen_s(hbSsid->StringText()); + if (ssidLength >= sizeof(config.Ssid)) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + hal_strncpy_s((char*)config.Ssid, WIRELESS82011_CONFIG_MAX_SSID_LEN, hbSsid->StringText(), ssidLength); + + // store configuration + if(ConfigurationManager_UpdateConfigurationBlock(&config, DeviceConfigurationOption_WirelessNetworkAP, configurationIndex) != TRUE) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + + NANOCLR_NOCLEANUP(); +#else + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +#endif +} + + +HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration::NativeGetConnectedClients___STATIC__SZARRAY_SystemNetNetworkInformationWirelessAPStation__I4(CLR_RT_StackFrame& stack) +{ +#ifdef PLATFORM_ESP32 + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Index apStationTypeDef; + CLR_RT_HeapBlock* apStation; + CLR_RT_HeapBlock* hbObj; + + uint16_t stationCount = 0; + + uint8_t mac[6]; + uint8_t rssi; + uint32_t phyModes = 0; + + CLR_RT_HeapBlock& top = stack.PushValue(); + + // Get index of station info required or if index == 0 then return all connected stations + uint16_t index = (uint16_t)stack.Arg0().NumericByRef().u4; + + + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef("WirelessAPStation", "System.Net.NetworkInformation", apStationTypeDef); + + // Count stations connected + for (int x = 0; x < Network_Interface_Max_Stations(); x++) + { + if (index != 0 && x != index) continue; + + if (Network_Interface_Get_Station(x, mac, &rssi, &phyModes)) + { + stationCount++; + } + } + + // Create an array of + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance(top, stationCount, apStationTypeDef)); + + // get a pointer to the first object in the array (which is of type ) + apStation = (CLR_RT_HeapBlock*)top.DereferenceArray()->GetFirstElement(); + + // Create Array + if (stationCount > 0) + { + for (int x = 0; x < Network_Interface_Max_Stations(); x++) + { + if (index != 0 && x != index) continue; + + if (Network_Interface_Get_Station(x, mac, &rssi, &phyModes)) + { + // create an instance of + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*apStation, apStationTypeDef)); + + // dereference the object in order to reach its fields + hbObj = apStation->Dereference(); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance(hbObj[Library_sys_net_native_System_Net_NetworkInformation_WirelessAPStation::FIELD___macAddress], 6, g_CLR_RT_WellKnownTypes.m_UInt8)); + memcpy(hbObj[Library_sys_net_native_System_Net_NetworkInformation_WirelessAPStation::FIELD___macAddress].DereferenceArray()->GetFirstElement(), mac, 6); + + + CLR_RT_HeapBlock& rssiFieldRef = hbObj[Library_sys_net_native_System_Net_NetworkInformation_WirelessAPStation::FIELD___rssi]; + CLR_INT8* pRes2 = (CLR_INT8*)&rssiFieldRef.NumericByRef().s1; + *pRes2 = rssi; + + CLR_RT_HeapBlock& phyModesFieldRef = hbObj[Library_sys_net_native_System_Net_NetworkInformation_WirelessAPStation::FIELD___phyModes]; + CLR_INT32* pRes3 = (CLR_INT32*)&phyModesFieldRef.NumericByRef().s4; + *pRes3 = phyModes; + + apStation++; + } + } + } + + NANOCLR_NOCLEANUP(); +#else + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +#endif +} + +HRESULT Library_sys_net_native_System_Net_NetworkInformation_WirelessAPConfiguration::NativeDeauthStation___STATIC__STRING__I4(CLR_RT_StackFrame& stack) +{ +#ifdef PLATFORM_ESP32 + NANOCLR_HEADER(); + + uint16_t index = (uint16_t)stack.Arg0().NumericByRef().u4; + + Network_Interface_Deauth_Station(index); + + NANOCLR_NOCLEANUP_NOLABEL(); +#else + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +#endif +} diff --git a/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_Security_CertificateManager.cpp b/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_Security_CertificateManager.cpp new file mode 100644 index 00000000..4946f4df --- /dev/null +++ b/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_Security_CertificateManager.cpp @@ -0,0 +1,51 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "sys_net_native.h" + +HRESULT Library_sys_net_native_System_Net_Security_CertificateManager::AddCaCertificateBundle___STATIC__BOOLEAN__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* arrayCA = stack.Arg0().DereferenceArray(); + + CLR_UINT8* certificateBinary; + uint32_t certificateSize; + + // we only have one CA root bundle, so this is fixed to 0 + uint32_t configIndex = 0; + + // check for empty array + FAULT_ON_NULL(arrayCA); + + certificateSize = (int)arrayCA->m_numOfElements; + + // get a pointer to the the binary data for the certificate + certificateBinary = arrayCA->GetFirstElement(); + + if(g_TargetConfiguration.CertificateStore->Count == 0) + { + // not found, add the certificate bundle + if(ConfigurationManager_StoreConfigurationBlock(certificateBinary, DeviceConfigurationOption_X509CaRootBundle, configIndex, certificateSize, 0) != TRUE) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + } + else + { + // update the configuration block + if(ConfigurationManager_UpdateConfigurationBlock(certificateBinary, DeviceConfigurationOption_X509CaRootBundle, configIndex) != TRUE) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + } + + // reach here, we should be OK + stack.SetResult_Boolean(TRUE); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_Security_SslNative.cpp b/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_Security_SslNative.cpp new file mode 100644 index 00000000..d6ce05bc --- /dev/null +++ b/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_Security_SslNative.cpp @@ -0,0 +1,631 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#include "sys_net_native.h" + + +struct SSL_SeedConfig +{ + HAL_DRIVER_CONFIG_HEADER Header; + + //--// + + uint64_t SeedCounter; + uint8_t SslSeedKey[ 260 ]; + + //--// + static const char * GetDriverName() { return "SSL_SEED_KEY"; } +}; + +struct SSL_SeedDriver +{ + SSL_SeedConfig Config; + + bool Initialized; + HAL_COMPLETION m_completion; +}; + +static SSL_SeedDriver g_SSL_SeedData; + +// TODO - save seed value +static void UpdateSslSeedValue(void* arg) +{ + (void)arg; + + // if(!HAL_CONFIG_BLOCK::UpdateBlockWithName( g_SSL_SeedData.Config.GetDriverName(), &g_SSL_SeedData.Config, sizeof(g_SSL_SeedData.Config), TRUE )) + // { + // ASSERT(FALSE); + // CPU_Reset(); + // } +} + +// TODO generate ramdom seed for encryption +// Maybe move this to specicfic provider files + +static void GenerateNewSslSeed() +{ +// uint8_t signature[ 128 ]; +// uint8_t IVPtr[ BLOCK_SIZE ]; +// bool success; + +// uint64_t data[ 2 ] = { ++g_SSL_SeedData.Config.SeedCounter, HAL_Time_CurrentTicks() }; + +// memset( &IVPtr[ 0 ], 0, sizeof(IVPtr) ); + +// // Encrypts a buffer using a symmetric algorithm. +// // BOOL Crypto_Encrypt(BYTE *Key, BYTE *IV, DWORD cbIVSize, BYTE* pPlainText, DWORD cbPlainText, BYTE *pCypherText, DWORD cbCypherText); +// //success = Crypto_Encrypt( (BYTE*)&g_SSL_SeedData.Config.SslSeedKey[ 0 ], (uint8_t*)IVPtr, sizeof(IVPtr), (uint8_t*)&data, sizeof(data), signature, sizeof(signature) ) == CRYPTO_SUCCESS ? S_OK : CLR_E_FAIL; + +// // ASSERT(success); + +// ssl_rand_seed(signature, sizeof(signature)); + +// if(!g_SSL_SeedData.m_completion.IsLinked()) +// { +// g_SSL_SeedData.m_completion.EnqueueDelta( 5 * 1000000ul ); // 5 seconds +// } +} + +//--// + +void Time_GetDateTime(DATE_TIME_INFO* dt) +{ + NATIVE_PROFILE_CLR_NETWORK(); + SYSTEMTIME st; + + HAL_Time_ToSystemTime( HAL_Time_CurrentTime(), &st ); + +// TODO check if offset needed for security date time, maybe needed to certificate validation +// dt->tzOffset = Time_GetTimeZoneOffset() * 60; + dt->tzOffset = 0; + + dt->year = st.wYear; + dt->month = st.wMonth; + dt->day = st.wDay; + dt->hour = st.wHour; + dt->minute = st.wMinute; + dt->second = st.wSecond; + dt->msec = st.wMilliseconds; + + dt->dlsTime = 0; + } + +// Initalise SSL as a server +HRESULT Library_sys_net_native_System_Net_Security_SslNative::SecureServerInit___STATIC__I4__I4__I4__SystemSecurityCryptographyX509CertificatesX509Certificate__SystemSecurityCryptographyX509CertificatesX509Certificate( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + return InitHelper( stack, true ); +} + +// Initalise SSL as a client +HRESULT Library_sys_net_native_System_Net_Security_SslNative::SecureClientInit___STATIC__I4__I4__I4__SystemSecurityCryptographyX509CertificatesX509Certificate__SystemSecurityCryptographyX509CertificatesX509Certificate( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + return InitHelper( stack, false ); +} + +// +// Server - socket connected now accept connection by doing the server SSL handshake +// +HRESULT Library_sys_net_native_System_Net_Security_SslNative::SecureAccept___STATIC__VOID__I4__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_INT32 sslContext = stack.Arg0().NumericByRef().s4; + CLR_RT_HeapBlock* socket = stack.Arg1().Dereference(); + CLR_INT32 timeout_ms = -1; // wait forever + CLR_RT_HeapBlock hbTimeout; + + int result = 0; + CLR_INT32 handle; + bool fRes = true; + CLR_INT64 *timeout; + + FAULT_ON_NULL(socket); + + handle = socket[ Library_sys_net_native_System_Net_Sockets_NativeSocket::FIELD__m_Handle ].NumericByRef().s4; + + /* Because we could have been a rescheduled call due to a prior call that would have blocked, we need to see + * if our handle has been shutdown before continuing. */ + if (handle == Library_sys_net_native_System_Net_Sockets_NativeSocket::DISPOSED_HANDLE) + { + ThrowError(stack, CLR_E_OBJECT_DISPOSED); + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } + + // !! need to cast to CLR_INT64 otherwise it wont setup a proper timeout infinite + hbTimeout.SetInteger( (CLR_INT64)timeout_ms * TIME_CONVERSION__TO_MILLISECONDS ); + + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks( hbTimeout, timeout )); + + + // first make sure we have data to read or ability to write + while(true) + { + result = SSL_Accept( handle, sslContext ); + + if(result == SOCK_EWOULDBLOCK || result == SOCK_TRY_AGAIN) + { + // non-blocking - allow other threads to run while we wait for socket activity + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_Socket, fRes )); + } + else + { + break; + } + } + + stack.PopValue(); // Timeout + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, result )); + + NANOCLR_NOCLEANUP(); +} + +// +// Client - Natve socket connected, now do client side SSL handshake +// +HRESULT Library_sys_net_native_System_Net_Security_SslNative::SecureConnect___STATIC__VOID__I4__STRING__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_INT32 sslContext = stack.Arg0().NumericByRef().s4; + CLR_RT_HeapBlock* hb = stack.Arg1().DereferenceString(); + CLR_RT_HeapBlock* socket = stack.Arg2().Dereference(); + CLR_RT_HeapBlock hbTimeout; + + int result; + const char * szName; + CLR_INT32 handle; + bool fRes = true; + CLR_INT64 * timeout; + + FAULT_ON_NULL(socket); + + handle = socket[ Library_sys_net_native_System_Net_Sockets_NativeSocket::FIELD__m_Handle ].NumericByRef().s4; + + /* Because we could have been a rescheduled call due to a prior call that would have blocked, we need to see + * if our handle has been shutdown before continuing. */ + if (handle == Library_sys_net_native_System_Net_Sockets_NativeSocket::DISPOSED_HANDLE) + { + ThrowError( stack, CLR_E_OBJECT_DISPOSED ); + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } + + FAULT_ON_NULL_ARG(hb); + + szName = hb->StringText(); + + // Infinite Timeout + // !! need to cast to CLR_INT64 otherwise it wont setup a proper timeout infinite + hbTimeout.SetInteger( (CLR_INT64)-1 ); + + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks( hbTimeout, timeout )); + + while(true) + { + result = SSL_Connect( handle, szName, sslContext ); + + if(result == SOCK_EWOULDBLOCK || result == SOCK_TRY_AGAIN) + { + // non-blocking - allow other threads to run while we wait for socket activity + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_Socket, fRes )); + + if(result < 0) break; + } + else + { + break; + } + } + + stack.PopValue(); // Timeout + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, result )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_net_native_System_Net_Security_SslNative::SecureRead___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + return ReadWriteHelper( stack, false ); +} + +HRESULT Library_sys_net_native_System_Net_Security_SslNative::SecureWrite___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + return ReadWriteHelper( stack, true ); +} + +HRESULT Library_sys_net_native_System_Net_Security_SslNative::SecureCloseSocket___STATIC__I4__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + int result; + CLR_INT32 handle; + + CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); FAULT_ON_NULL(socket); + + handle = socket[ Library_sys_net_native_System_Net_Sockets_NativeSocket::FIELD__m_Handle ].NumericByRef().s4; + + result = SSL_CloseSocket( handle ); + + stack.SetResult_I4( result ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_net_native_System_Net_Security_SslNative::ExitSecureContext___STATIC__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_INT32 sslContext = stack.Arg0().NumericByRef().s4; + + int result = SSL_ExitContext( sslContext ) == TRUE ? 0 : -1; + + stack.SetResult_I4( result ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_sys_net_native_System_Net_Security_SslNative::DataAvailable___STATIC__I4__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); + int result; + CLR_INT32 handle; + + FAULT_ON_NULL(socket); + + handle = socket[ Library_sys_net_native_System_Net_Sockets_NativeSocket::FIELD__m_Handle ].NumericByRef().s4; + + result = SSL_DataAvailable( handle ); + + // ThrowOnError expects anything other than 0 to be a failure - so return 0 if we don't have an error + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, result >= 0 ? 0 : result )); + + stack.SetResult_I4( result ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_net_native_System_Net_Security_SslNative::ReadWriteHelper( CLR_RT_StackFrame& stack, bool isWrite ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); + CLR_RT_HeapBlock_Array* arrData = stack.Arg1().DereferenceArray(); + CLR_INT32 offset = stack.Arg2().NumericByRef().s4; + CLR_INT32 count = stack.Arg3().NumericByRef().s4; + CLR_INT32 timeout_ms = stack.Arg4().NumericByRef().s4; + CLR_UINT8* buffer; + CLR_RT_HeapBlock hbTimeout; + + CLR_INT32 totReadWrite; + bool fRes = true; + CLR_INT64 *timeout; + int result = 0; + CLR_INT32 handle; + + if(count == 0) + { + stack.SetResult_I4( 0 ); + NANOCLR_SET_AND_LEAVE(S_OK); + } + + FAULT_ON_NULL(socket); + + handle = socket[ Library_sys_net_native_System_Net_Sockets_NativeSocket::FIELD__m_Handle ].NumericByRef().s4; + + // Check not Disposed + if (handle == Library_sys_net_native_System_Net_Sockets_NativeSocket::DISPOSED_HANDLE) + { + ThrowError( stack, CLR_E_OBJECT_DISPOSED ); + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } + + FAULT_ON_NULL(arrData); + + // !! need to cast to CLR_INT64 otherwise it wont setup a proper timeout infinite + hbTimeout.SetInteger( (CLR_INT64)timeout_ms * TIME_CONVERSION__TO_MILLISECONDS ); + + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks( hbTimeout, timeout )); + + // + // Push "totReadWrite" onto the eval stack. + // + if(stack.m_customState == 1) + { + stack.PushValueI4( 0 ); + + stack.m_customState = 2; + } + + totReadWrite = stack.m_evalStack[ 1 ].NumericByRef().s4; + + buffer = arrData->GetElement( offset + totReadWrite ); + count -= totReadWrite; + + if((offset + count + totReadWrite) > (int)arrData->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_INDEX_OUT_OF_RANGE); + + while(count > 0) + { + // first make sure we have data to read or ability to write + while(fRes) + { + if(!isWrite) + { + // check SSL_DataAvailable() in case SSL has already read and buffered socket data + result = SSL_DataAvailable(handle); + + if((result > 0) || ((result < 0) && (SOCK_getlasterror() != SOCK_EWOULDBLOCK))) + { + break; + } + } + + result = Library_sys_net_native_System_Net_Sockets_NativeSocket::Helper__SelectSocket( handle, isWrite ? 1 : 0 ); + + if((result > 0) || ((result < 0) && (SOCK_getlasterror() != SOCK_EWOULDBLOCK))) + { + break; + } + + // non-blocking - allow other threads to run while we wait for socket activity + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_Socket, fRes )); + + // timeout expired + if(!fRes) + { + result = SOCK_SOCKET_ERROR; + + ThrowError(stack, SOCK_ETIMEDOUT); + + NANOCLR_SET_AND_LEAVE( CLR_E_PROCESS_EXCEPTION ); + } + } + + // socket is in the excepted state, so let's bail out + if(SOCK_SOCKET_ERROR == result) + { + break; + } + + if(isWrite) + { + result = SSL_Write( handle, (const char*)buffer, count ); + } + else + { + result = SSL_Read( handle, (char*)buffer, count ); + + if(result == SSL_RESULT__WOULD_BLOCK) + { + continue; + } + } + + // ThrowOnError expects anything other than 0 to be a failure - so return 0 if we don't have an error + if(result <= 0) + { + break; + } + + buffer += result; + totReadWrite += result; + count -= result; + + + // read is non-blocking if we have any data + if(!isWrite && (totReadWrite > 0)) + { + break; + } + + stack.m_evalStack[ 1 ].NumericByRef().s4 = totReadWrite; + } + + stack.PopValue(); // totReadWrite + stack.PopValue(); // Timeout + + if(result < 0) + { + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, result )); + } + + stack.SetResult_I4( totReadWrite ); + + NANOCLR_NOCLEANUP(); + +} + + +HRESULT Library_sys_net_native_System_Net_Security_SslNative::InitHelper( CLR_RT_StackFrame& stack, bool isServer ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Index x509Certificate2TypeDef; + + CLR_INT32 sslContext = -1; + CLR_INT32 sslMode = stack.Arg0().NumericByRef().s4; + CLR_INT32 sslVerify = stack.Arg1().NumericByRef().s4; + CLR_RT_HeapBlock *hbCert = stack.Arg2().Dereference(); + CLR_RT_HeapBlock* caCert = stack.Arg3().Dereference(); + CLR_RT_HeapBlock_Array* arrCert = NULL; + CLR_RT_HeapBlock_Array* privateKey = NULL; + CLR_UINT8* sslCert = NULL; + int result; + bool isFirstCall = false; + const char * password = ""; + uint8_t* pk = NULL; + + if(!g_SSL_SeedData.Initialized) + { +// bool fOK = FALSE; + + isFirstCall = true; + +// FIXME +// #if !defined(_WIN32) && !defined(WIN32) && !defined(_WIN32_WCE) +// int i; + +// // TODO save seed data +// // if(!HAL_CONFIG_BLOCK::ApplyConfig( g_SSL_SeedData.Config.GetDriverName(), &g_SSL_SeedData.Config, sizeof(g_SSL_SeedData.Config) )) +// // { +// // return CLR_E_NOT_SUPPORTED; +// // } + +// // validate the security key (make sure it isn't all 0x00 or all 0xFF +// for(i=1; iPin(); + + // there is a client certificate, find if it's a X509Certificate2 + if(hbCert->ObjectCls().Type() == x509Certificate2TypeDef.Type()) + { + // get private key + privateKey = hbCert[ Library_sys_net_native_System_Security_Cryptography_X509Certificates_X509Certificate2::FIELD___privateKey ].DereferenceArray(); + pk = privateKey->GetFirstElement(); + } + + // get certificate + sslCert = arrCert->GetFirstElement(); + + // get password + CLR_RT_HeapBlock *hbPwd = hbCert[ Library_sys_net_native_System_Security_Cryptography_X509Certificates_X509Certificate::FIELD___password ].Dereference();// FAULT_ON_NULL(hbPwd); + password = hbPwd->StringText(); + } + + if(isServer) + { + result = (SSL_ServerInit( sslMode, sslVerify, (const char*)sslCert, sslCert == NULL ? 0 : arrCert->m_numOfElements, pk, pk == NULL ? 0 : privateKey->m_numOfElements, password, hal_strlen_s(password), sslContext ) ? 0 : -1); + } + else + { + result = (SSL_ClientInit( sslMode, sslVerify, (const char*)sslCert, sslCert == NULL ? 0 : arrCert->m_numOfElements, pk, pk == NULL ? 0 : privateKey->m_numOfElements, password, hal_strlen_s(password), sslContext ) ? 0 : -1); + } + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, result )); + + if(isFirstCall) + { + GenerateNewSslSeed(); + } + + if(caCert != NULL) + { + arrCert = caCert[ Library_sys_net_native_System_Security_Cryptography_X509Certificates_X509Certificate::FIELD___certificate ].DereferenceArray(); //FAULT_ON_NULL(arrCert); + + // If arrCert == NULL then the certificate is an X509Certificate2 which uses a certificate handle + if(arrCert == NULL) + { + CLR_INT32 sessionCtx = 0; + + arrCert = caCert[ Library_sys_net_native_System_Security_Cryptography_X509Certificates_X509Certificate::FIELD___handle ].DereferenceArray(); FAULT_ON_NULL(arrCert); + + sslCert = arrCert->GetFirstElement(); + + arrCert = caCert[ Library_sys_net_native_System_Security_Cryptography_X509Certificates_X509Certificate::FIELD___sessionHandle ].DereferenceArray(); FAULT_ON_NULL(arrCert); + + sessionCtx = *(int32_t*)arrCert->GetFirstElement(); + + // pass the session handle down as the password paramter and the certificate handle as the data parameter + result = (SSL_AddCertificateAuthority( sslContext, (const char*)sslCert, arrCert->m_numOfElements, (LPCSTR)&sessionCtx ) ? 0 : -1); + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, result )); + } + else + { + + arrCert->Pin(); + + sslCert = arrCert->GetFirstElement(); + + CLR_RT_HeapBlock *hbPwd = caCert[ Library_sys_net_native_System_Security_Cryptography_X509Certificates_X509Certificate::FIELD___password ].Dereference(); FAULT_ON_NULL(hbPwd); + + LPCSTR szCAPwd = hbPwd->StringText(); + + result = (SSL_AddCertificateAuthority( sslContext, (const char*)sslCert, arrCert->m_numOfElements, szCAPwd ) ? 0 : -1); + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, result )); + } + } + + stack.SetResult_I4( sslContext ); + + NANOCLR_CLEANUP(); + + if(FAILED(hr) && (sslContext != -1)) + { + SSL_ExitContext( sslContext ); + } + + NANOCLR_CLEANUP_END(); +} + +void Library_sys_net_native_System_Net_Security_SslNative::ThrowError( CLR_RT_StackFrame& stack, int errorCode ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + CLR_RT_HeapBlock& res = stack.m_owningThread->m_currentException; + + if((Library_corlib_native_System_Exception::CreateInstance( res, g_CLR_RT_WellKnownTypes.m_SocketException, CLR_E_FAIL, &stack )) == S_OK) + { + res.Dereference()[ Library_sys_net_native_System_Net_Sockets_SocketException::FIELD___errorCode ].SetInteger( errorCode ); + } +} + +HRESULT Library_sys_net_native_System_Net_Security_SslNative::ThrowOnError( CLR_RT_StackFrame& stack, int res ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + if(res != 0) + { + ThrowError( stack, res ); + + NANOCLR_SET_AND_LEAVE( CLR_E_PROCESS_EXCEPTION ); + } + + NANOCLR_NOCLEANUP(); +} + diff --git a/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_Sockets_NativeSocket.cpp b/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_Sockets_NativeSocket.cpp new file mode 100644 index 00000000..08dab47c --- /dev/null +++ b/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native_System_Net_Sockets_NativeSocket.cpp @@ -0,0 +1,876 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#include "sys_net_native.h" + +HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::socket___STATIC__I4__I4__I4__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_INT32 family = stack.Arg0().NumericByRef().s4; + CLR_INT32 type = stack.Arg1().NumericByRef().s4; + CLR_INT32 protocol = stack.Arg2().NumericByRef().s4; + + CLR_INT32 nonBlocking = 1; + CLR_INT32 sock = SOCK_socket( family, type, protocol ); + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, sock )); + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, SOCK_ioctl( sock, SOCK_FIONBIO, &nonBlocking ) )); + + stack.SetResult_I4( sock ); + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::bind___STATIC__VOID__OBJECT__SystemNetEndPoint( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + return BindConnectHelper( stack, true ); + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::connect___STATIC__VOID__OBJECT__SystemNetEndPoint__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + return BindConnectHelper( stack, false ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::send___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + return SendRecvHelper( stack, true, false ); +} + +HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::recv___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + return SendRecvHelper( stack, false, false ); +} + +HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::close___STATIC__I4__OBJECT( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_INT32 handle, ret; + + CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); FAULT_ON_NULL(socket); + + handle = socket[ FIELD__m_Handle ].NumericByRef().s4; + + ret = SOCK_close( handle ); + + //If a socket gets closed, we need to make sure to wake up any threads that are waiting on it. + Events_Set( SYSTEM_EVENT_FLAG_SOCKET ); + + stack.SetResult_I4( ret ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::listen___STATIC__VOID__OBJECT__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); + CLR_INT32 handle; + CLR_INT32 backlog = stack.Arg1().NumericByRef().s4; + CLR_INT32 ret; + + FAULT_ON_NULL(socket); + handle = socket[ FIELD__m_Handle ].NumericByRef().s4; + + ret = SOCK_listen( handle, backlog ); + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, ret )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::accept___STATIC__I4__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); + CLR_INT32 handle; + CLR_INT32 ret; + CLR_INT32 nonBlocking = 1; + + FAULT_ON_NULL(socket); + handle = socket[ FIELD__m_Handle ].NumericByRef().s4; + + + /* Because we could have been a rescheduled call due to a prior call that would have blocked, we need to see + * if our handle has been shutdown before continuing. */ + if (handle == DISPOSED_HANDLE) + { + ThrowError(stack, CLR_E_OBJECT_DISPOSED); + NANOCLR_SET_AND_LEAVE (CLR_E_PROCESS_EXCEPTION); + } + + ret = SOCK_accept( handle, NULL, NULL ); + + if(ret != SOCK_SOCKET_ERROR) + { + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, SOCK_ioctl( ret, SOCK_FIONBIO, &nonBlocking ) )); + } + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, ret )); + + stack.SetResult_I4( ret ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::getaddrinfo___STATIC__VOID__STRING__BYREF_STRING__BYREF_SZARRAY_SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + LPCSTR szName = stack.Arg0().RecoverString(); + struct SOCK_addrinfo hints; + struct SOCK_addrinfo* addr = NULL; + struct SOCK_addrinfo* addrT; + CLR_UINT32 cAddresses = 0; + CLR_RT_HeapBlock* pAddress; + CLR_INT32 timeout_ms = 30000; + CLR_RT_HeapBlock hbTimeout; + CLR_INT32 ret; + bool fRes = true; + CLR_INT64* timeout; + uint32_t socketError = SOCK_SOCKET_ERROR; + + // !! need to cast to CLR_INT64 otherwise it wont setup a proper timeout infinite + hbTimeout.SetInteger( (CLR_INT64)timeout_ms * TIME_CONVERSION__TO_MILLISECONDS ); + + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks( hbTimeout, timeout )); + + do + { + memset( &hints, 0, sizeof(hints) ); + + ret = SOCK_getaddrinfo( szName, NULL, &hints, &addr ); + + if(ret == SOCK_SOCKET_ERROR) + { + // get last error from socket + socketError = SOCK_getlasterror(); + + if(socketError == SOCK_EWOULDBLOCK) + { + // non-blocking - allow other threads to run while we wait for handle activity + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_Socket, fRes )); + } + else + { + break; + } + } + else + { + // return without error, clear socket error + socketError = 0; + + // done here + break; + } + } + while(fRes); + + // timeout expired + if(!fRes) + { + ret = SOCK_SOCKET_ERROR; + + ThrowError( stack, SOCK_ETIMEDOUT ); + + NANOCLR_SET_AND_LEAVE( CLR_E_PROCESS_EXCEPTION ); + } + else + { + // error wasn't a timeout so use socket error + ret = socketError; + } + + // getaddrinfo returns a winsock error code rather than SOCK_SOCKET_ERROR, so pass this on to the exception handling + if(ret != 0) + { + ThrowError( stack, ret ); + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } + + { + CLR_RT_HeapBlock hbCanonicalName; + CLR_RT_HeapBlock hbAddresses; + + hbCanonicalName.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc( hbCanonicalName ); + + hbAddresses.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc2( hbAddresses ); + + for(int pass = 0; pass < 2; pass++) + { + cAddresses = 0; + + for(addrT = addr; addrT != NULL; addrT = addrT->ai_next) + { + if(pass == 1) + { + if(addrT->ai_canonname && addrT->ai_canonname[ 0 ]) + { + //allocate return string + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( hbCanonicalName, addrT->ai_canonname )); + NANOCLR_CHECK_HRESULT(hbCanonicalName.StoreToReference( stack.Arg1(), 0 )); + } + + //allocate address and store into array + pAddress = (CLR_RT_HeapBlock*)hbAddresses.DereferenceArray()->GetElement( cAddresses ); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( *pAddress, (CLR_UINT32)addrT->ai_addrlen, g_CLR_RT_WellKnownTypes.m_UInt8 )); + + //copy address. + memcpy( pAddress->DereferenceArray()->GetFirstElement(), addrT->ai_addr, addrT->ai_addrlen ); + } + + cAddresses++; + } + + if(pass == 0) + { + //allocate array of byte arrays + CLR_RT_ReflectionDef_Index idx; + + idx.m_kind = REFLECTION_TYPE; + idx.m_levels = 2; + idx.m_data.m_type.m_data = g_CLR_RT_WellKnownTypes.m_UInt8.m_data; + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( hbAddresses, cAddresses, idx )); + + NANOCLR_CHECK_HRESULT(hbAddresses.StoreToReference( stack.Arg2(), 0 )); + } + } + } + + stack.PopValue(); // Timeout + + NANOCLR_CLEANUP(); + + if( addr ) SOCK_freeaddrinfo( addr ); + + NANOCLR_CLEANUP_END(); +} + +HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::shutdown___STATIC__VOID__OBJECT__I4__BYREF_I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); + CLR_INT32 handle; + CLR_INT32 how = stack.Arg1().NumericByRef().s4; + CLR_INT32 ret; + + FAULT_ON_NULL(socket); + handle = socket[ FIELD__m_Handle ].NumericByRef().s4; + + ret = SOCK_shutdown( handle, how ); + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, ret )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::sendto___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4__SystemNetEndPoint( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + return SendRecvHelper( stack, true, true ); +} + +HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::recvfrom___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4__BYREF_SystemNetEndPoint( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + return SendRecvHelper( stack, false, true ); +} + +HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::getpeername___STATIC__VOID__OBJECT__BYREF_SystemNetEndPoint( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + return SockNameHelper( stack, true ); +} + +HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::getsockname___STATIC__VOID__OBJECT__BYREF_SystemNetEndPoint( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + return SockNameHelper( stack, false ); +} + +HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::getsockopt___STATIC__VOID__OBJECT__I4__I4__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + return SockOptHelper( stack, true ); +} + +HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::setsockopt___STATIC__VOID__OBJECT__I4__I4__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + return SockOptHelper( stack, false ); +} + +HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::poll___STATIC__BOOLEAN__OBJECT__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); + CLR_INT32 handle; + CLR_INT32 mode = stack.Arg1().NumericByRef().s4; + CLR_INT32 timeout_us = stack.Arg2().NumericByRef().s4; + CLR_RT_HeapBlock hbTimeout; + + CLR_INT32 res = 0; + bool fRes = true; + + CLR_INT64* timeout; + + FAULT_ON_NULL(socket); + handle = socket[ FIELD__m_Handle ].NumericByRef().s4; + + /* Because we could have been a rescheduled call due to a prior call that would have blocked, we need to see + * if our handle has been shutdown before continuing. */ + if (handle == DISPOSED_HANDLE) + { + ThrowError( stack, CLR_E_OBJECT_DISPOSED ); + NANOCLR_SET_AND_LEAVE (CLR_E_PROCESS_EXCEPTION); + } + + if(timeout_us < 0) + { + // Infinite Timeout + // !! need to cast to CLR_INT64 otherwise it wont setup a proper timeout infinite + hbTimeout.SetInteger( (CLR_INT64)-1 ); + } + else + { + // !! need to cast to CLR_INT64 otherwise it wont setup a proper timeout infinite + hbTimeout.SetInteger( (CLR_INT64)timeout_us * TIME_CONVERSION__TO_MILLISECONDS / 1000 ); + } + + + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks( hbTimeout, timeout )); + + while(fRes) + { + res = Helper__SelectSocket( handle, mode ); + + if(res != 0) break; + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_Socket, fRes )); + } + + stack.PopValue(); //timer + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, res )); + + stack.SetResult_Boolean( res != 0 ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::ioctl___STATIC__VOID__OBJECT__U4__BYREF_U4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); + CLR_INT32 handle; + CLR_INT32 cmd = stack.Arg1().NumericByRef().s4; + CLR_RT_HeapBlock blkArg; + CLR_INT32 ret; + + FAULT_ON_NULL(socket); + handle = socket[ FIELD__m_Handle ].NumericByRef().s4; + + _SIDE_ASSERTE(SUCCEEDED(blkArg.LoadFromReference( stack.Arg2() ))); + + ret = SOCK_ioctl( handle, cmd, (CLR_INT32*)&blkArg.NumericByRef().s4 ); + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, ret )); + + _SIDE_ASSERTE(SUCCEEDED(blkArg.StoreToReference( stack.Arg2(), 0 ))); + + NANOCLR_NOCLEANUP(); +} + +//--// + +HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::BindConnectHelper( CLR_RT_StackFrame& stack, bool fBind ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); + + CLR_INT32 handle; + SOCK_sockaddr addr; + CLR_UINT32 addrLen = sizeof(addr); + CLR_INT32 ret; + bool fThrowOnWouldBlock = false; + + FAULT_ON_NULL(socket); + handle = socket[ FIELD__m_Handle ].NumericByRef().s4; + + NANOCLR_CHECK_HRESULT(MarshalSockAddress( &addr, addrLen, stack.Arg1() )); + + if(fBind) + { + ret = SOCK_bind( handle, &addr, addrLen ); + } + else + { + ret = SOCK_connect( handle, &addr, addrLen ); + + fThrowOnWouldBlock = (stack.Arg2().NumericByRefConst().s4 != 0); + + if(!fThrowOnWouldBlock && SOCK_getsocklasterror( handle ) == SOCK_EWOULDBLOCK) + { + NANOCLR_SET_AND_LEAVE(S_OK); + } + } + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, ret )); + + NANOCLR_NOCLEANUP(); +} + +CLR_INT32 Library_sys_net_native_System_Net_Sockets_NativeSocket::Helper__SelectSocket(CLR_INT32 handle, CLR_INT32 mode ) +{ + struct SOCK_timeval timeval; + SOCK_fd_set* readfds = NULL; + SOCK_fd_set* writefds = NULL; + SOCK_fd_set* exceptfds = NULL; + SOCK_fd_set fds; + SOCK_fd_set fdsExcept; + CLR_INT32 res = 0; + + switch(mode) + { + case 0: + readfds = &fds; + break; + case 1: + writefds = &fds; + break; + default: + _ASSERTE(FALSE); + // fall through + case 2: + exceptfds = &fds; + break; + } + + fds.fd_count = 1; + fds.fd_array[ 0 ] = handle; + + // This Poll method is a little handicapped in the sense that it only allows the caller to wait + // for a read, a write or an except. This causes a problem when there is a socket exception. The + // poll will continue to block forever because the select statement wasn't looking for exceptions + // Therefore, we will force the select call to look for the except case if it is not already doing it. + if(exceptfds == NULL) + { + fdsExcept.fd_count = 1; + fdsExcept.fd_array[ 0 ] = handle; + exceptfds = &fdsExcept; + } + + timeval.tv_sec = 0; + timeval.tv_usec = 0; + + res = SOCK_select( 1, readfds, writefds, exceptfds, &timeval ); + + // socket is in the exception state (only return error if caller was NOT looking for the excepted state) + if((mode != 2) && (fdsExcept.fd_count != 0)) + { + // For read mode ignore exception if we have data to read + if(!(mode == 0 && fds.fd_count != 0)) + { + return SOCK_SOCKET_ERROR; + } + } + + return res; +} + +HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::MarshalSockAddress( CLR_RT_HeapBlock& blkDst, const struct SOCK_sockaddr* addrSrc, CLR_UINT32 addrLenSrc ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + + NANOCLR_HEADER(); + + (void)addrLenSrc; + + SOCK_sockaddr_in* src = (SOCK_sockaddr_in*)addrSrc; + + CLR_RT_TypeDef_Index ipAddressTypeDef; + CLR_RT_TypeDef_Index ipEndPointTypeDef; + CLR_RT_HeapBlock* ipAddressHbObj; + CLR_RT_HeapBlock* ipEndPointHbObj; + + CLR_RT_HeapBlock ipAddress; ipAddress.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc1( ipAddress ); + + CLR_RT_HeapBlock ipEndPoint; ipEndPoint.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc2( ipEndPoint ); + + // find type definition, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef( "IPAddress", "System.Net", ipAddressTypeDef ); + + // create an instance of + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(ipAddress, ipAddressTypeDef)); + + // find type definition, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef( "IPEndPoint", "System.Net", ipEndPointTypeDef ); + + // create an instance of + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(ipEndPoint, ipEndPointTypeDef)); + + // dereference the objects in order to reach their fields + ipAddressHbObj = ipAddress.Dereference(); + ipEndPointHbObj = ipEndPoint.Dereference(); + + { + // get a reference to the managed fields and set them + + // IPAddress _address field + // CLR_INT64 fields need to be accessed by pointer + CLR_RT_HeapBlock& addressFieldRef = ipAddressHbObj[ Library_sys_net_native_System_Net_IPAddress::FIELD___address ]; + CLR_INT64* pRes = (CLR_INT64*)&addressFieldRef.NumericByRef().s8; + *pRes = src->sin_addr.S_un.S_addr; + + // IPAddress _family field + ipAddressHbObj[ Library_sys_net_native_System_Net_IPAddress::FIELD___family ].NumericByRef().s4 = src->sin_family; + + // IPEndPoint _port field + // take care of endianess swapping + ipEndPointHbObj[ Library_sys_net_native_System_Net_IPEndPoint::FIELD___port ].NumericByRef().s4 = SOCK_ntohs(src->sin_port); + + // set IPEndPoint address with IPAddress heap block object + ipEndPointHbObj[ Library_sys_net_native_System_Net_IPEndPoint::FIELD___address ].SetObjectReference( ipAddressHbObj ); + } + + _ASSERTE(blkDst.DataType() == DATATYPE_BYREF); + + // store the new IPEndPoint object to reference + NANOCLR_CHECK_HRESULT(ipEndPoint.StoreToReference( blkDst, 0 )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::MarshalSockAddress( struct SOCK_sockaddr* addrDst, CLR_UINT32& addrLenDst, const CLR_RT_HeapBlock& blkEndPointAddress ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + SOCK_sockaddr_in* dst = (SOCK_sockaddr_in*)addrDst; + + CLR_RT_HeapBlock* endPointAddress; + CLR_RT_HeapBlock* remoteEndPointAddress; + int64_t address; + int32_t port; + + endPointAddress = blkEndPointAddress.Dereference(); + FAULT_ON_NULL(endPointAddress); + + // get a pointer to the managed field object instance for m_Address + remoteEndPointAddress = endPointAddress[ Library_sys_net_native_System_Net_IPEndPoint::FIELD___address ].Dereference(); + FAULT_ON_NULL(remoteEndPointAddress); + + // get value of m_Address field (type long) + address = (CLR_INT64)remoteEndPointAddress[ Library_sys_net_native_System_Net_IPAddress::FIELD___address ].NumericByRef().s8; + + // get value of m_Port field (type int) + port = endPointAddress[ Library_sys_net_native_System_Net_IPEndPoint::FIELD___port ].NumericByRef().s4; + + // clear struct + memset(dst, 0, sizeof(SOCK_sockaddr)); + + dst->sin_family = SOCK_AF_INET; + // need to convert port number to network order + dst->sin_port = SOCK_htons(port); + + //address already in network byte order + memcpy((int8_t*)&dst->sin_addr.S_un.S_addr, (int8_t*)&address, sizeof(address)); + + addrLenDst = sizeof(address); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::SendRecvHelper( CLR_RT_StackFrame& stack, bool fSend, bool fAddress ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); + CLR_INT32 handle; + CLR_RT_HeapBlock_Array* arrData = stack.Arg1().DereferenceArray(); + CLR_UINT32 offset = stack.Arg2().NumericByRef().u4; + CLR_UINT32 count = stack.Arg3().NumericByRef().u4; + CLR_INT32 flags = stack.Arg4().NumericByRef().s4; + CLR_RT_HeapBlock hbTimeout; + + CLR_INT64* timeout; + CLR_UINT8* buf; + bool fRes = true; + CLR_INT32 totReadWrite; + CLR_INT32 ret = 0; + + FAULT_ON_NULL(socket); + FAULT_ON_NULL(arrData); + + handle = socket[ FIELD__m_Handle ].NumericByRef().s4; + + /* Because we could have been a rescheduled call due to a prior call that would have blocked, we need to see + * if our handle has been shutdown before continuing. */ + if (handle == DISPOSED_HANDLE) + { + ThrowError( stack, CLR_E_OBJECT_DISPOSED ); + NANOCLR_SET_AND_LEAVE (CLR_E_PROCESS_EXCEPTION); + } + + if(offset + count > arrData->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_INDEX_OUT_OF_RANGE); + + // Infinite Timeout + // !! need to cast to CLR_INT64 otherwise it wont setup a proper timeout infinite + hbTimeout.SetInteger( (CLR_INT64)-1 ); + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks( hbTimeout, timeout )); + + // + // Push "totReadWrite" onto the eval stack. + // + if(stack.m_customState == 1) + { + stack.PushValueI4( 0 ); + + stack.m_customState = 2; + } + + totReadWrite = stack.m_evalStack[ 1 ].NumericByRef().s4; + + buf = arrData->GetElement( offset + totReadWrite ); + count -= totReadWrite; + + while(count > 0) + { + CLR_INT32 bytes = 0; + + // first make sure we have data to read or ability to write + while(fRes) + { + ret = Helper__SelectSocket( handle, fSend ? 1 : 0 ); + + if(ret != 0) break; + + // non-blocking - allow other threads to run while we wait for handle activity + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_Socket, fRes )); + } + + // timeout expired + if(!fRes) + { + ret = SOCK_SOCKET_ERROR; + + ThrowError( stack, SOCK_ETIMEDOUT ); + + NANOCLR_SET_AND_LEAVE( CLR_E_PROCESS_EXCEPTION ); + } + + // socket is in the excepted state, so let's bail out + if(SOCK_SOCKET_ERROR == ret) + { + break; + } + + if(fAddress) + { + struct SOCK_sockaddr addr; + CLR_UINT32 addrLen = sizeof(addr); + CLR_RT_HeapBlock& blkAddr = stack.Arg6(); + + if(fSend) + { + NANOCLR_CHECK_HRESULT(MarshalSockAddress( &addr, addrLen, blkAddr )); + + bytes = SOCK_sendto( handle, (const char*)buf, count, flags, &addr, addrLen ); + } + else + { + CLR_RT_HeapBlock* pBlkAddr = blkAddr.Dereference(); + + NANOCLR_CHECK_HRESULT(MarshalSockAddress( &addr, addrLen, *pBlkAddr )); + + bytes = SOCK_recvfrom( handle, (char*)buf, count, flags, &addr, (int*)&addrLen ); + + if(bytes != SOCK_SOCKET_ERROR) + { + NANOCLR_CHECK_HRESULT(MarshalSockAddress( blkAddr, &addr, addrLen )); + } + } + } + else + { + if(fSend) + { + bytes = SOCK_send( handle, (const char*)buf, count, flags ); + } + else + { + bytes = SOCK_recv( handle, (char*)buf, count, flags ); + } + } + + // send/recv/sendto/recvfrom failed + if(bytes == SOCK_SOCKET_ERROR) + { + CLR_INT32 err = SOCK_getlasterror(); + + if(err != SOCK_EWOULDBLOCK) + { + ret = SOCK_SOCKET_ERROR; + break; + } + + continue; + } + // zero recv bytes indicates the handle has been closed. + else if(!fSend && (bytes == 0)) + { + break; + } + + buf += bytes; + totReadWrite += bytes; + count -= bytes; + + stack.m_evalStack[ 1 ].NumericByRef().s4 = totReadWrite; + + // receive returns immediately after receiving bytes. + if(!fSend && (totReadWrite > 0)) + { + break; + } + + } + + stack.PopValue(); // totReadWrite + stack.PopValue(); // Timeout + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, ret )); + + stack.SetResult_I4( totReadWrite ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::SockOptHelper( CLR_RT_StackFrame& stack, bool fGet ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); + CLR_INT32 handle; + CLR_INT32 level = stack.Arg1().NumericByRef().s4; + CLR_INT32 optname = stack.Arg2().NumericByRef().s4; + CLR_RT_HeapBlock_Array* arrOpt = stack.Arg3().DereferenceArray(); + char* optval; + CLR_INT32 optlen; + CLR_INT32 ret; + + FAULT_ON_NULL(socket); + handle = socket[ FIELD__m_Handle ].NumericByRef().s4; + + FAULT_ON_NULL(arrOpt); + + optval = (char*)arrOpt->GetFirstElement(); + optlen = arrOpt->m_numOfElements; + + if(fGet) + { + ret = SOCK_getsockopt( handle, level, optname, optval, &optlen ); + _ASSERTE( optlen <= (CLR_INT32)arrOpt->m_numOfElements ); + } + else + { + ret = SOCK_setsockopt( handle, level, optname, optval, optlen ); + } + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, ret )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::SockNameHelper( CLR_RT_StackFrame& stack, bool fPeer ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); + CLR_INT32 handle; + CLR_INT32 ret; + + struct SOCK_sockaddr addr; + CLR_INT32 addrLen = sizeof(addr); + + FAULT_ON_NULL(socket); + handle = socket[ FIELD__m_Handle ].NumericByRef().s4; + + if(fPeer) + { + ret = SOCK_getpeername( handle, &addr, &addrLen ); + } + else + { + ret = SOCK_getsockname( handle, &addr, &addrLen ); + } + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, ret )); + + NANOCLR_CHECK_HRESULT(MarshalSockAddress( stack.Arg1(), &addr, addrLen )); + + NANOCLR_NOCLEANUP(); +} + +void Library_sys_net_native_System_Net_Sockets_NativeSocket::ThrowError( CLR_RT_StackFrame& stack, CLR_INT32 errorCode ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + CLR_RT_HeapBlock& res = stack.m_owningThread->m_currentException; + + if((Library_corlib_native_System_Exception::CreateInstance( res, g_CLR_RT_WellKnownTypes.m_SocketException, CLR_E_FAIL, &stack )) == S_OK) + { + res.Dereference()[ Library_sys_net_native_System_Net_Sockets_SocketException::FIELD___errorCode ].SetInteger( errorCode ); + } +} + +HRESULT Library_sys_net_native_System_Net_Sockets_NativeSocket::ThrowOnError( CLR_RT_StackFrame& stack, CLR_INT32 res ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + if(res == SOCK_SOCKET_ERROR) + { + CLR_INT32 err = SOCK_getlasterror(); + + ThrowError( stack, err ); + + NANOCLR_SET_AND_LEAVE( CLR_E_PROCESS_EXCEPTION ); + } + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native_System_Security_Cryptography_X509Certificates_X509Certificate.cpp b/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native_System_Security_Cryptography_X509Certificates_X509Certificate.cpp new file mode 100644 index 00000000..f8800960 --- /dev/null +++ b/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native_System_Security_Cryptography_X509Certificates_X509Certificate.cpp @@ -0,0 +1,88 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "sys_net_native.h" + +HRESULT Library_sys_net_native_System_Security_Cryptography_X509Certificates_X509Certificate::ParseCertificate___STATIC__VOID__SZARRAY_U1__STRING__BYREF_STRING__BYREF_STRING__BYREF_mscorlibSystemDateTime__BYREF_mscorlibSystemDateTime( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* arrData = stack.Arg0().DereferenceArray(); + CLR_UINT8* certBytes; + CLR_RT_HeapBlock hbIssuer; + CLR_RT_HeapBlock hbSubject; + CLR_RT_ProtectFromGC gc1( hbIssuer ); + CLR_RT_ProtectFromGC gc2( hbSubject ); + X509CertData cert; + CLR_INT64* val; +// CLR_INT64 tzOffset; + SYSTEMTIME st; +// INT32 standardBias; + CLR_RT_HeapBlock* hbPwd = stack.Arg1().DereferenceString(); + LPCSTR szPwd; + + FAULT_ON_NULL_ARG(hbPwd); + + szPwd = hbPwd->StringText(); + + CLR_RT_Memory::ZeroFill( &cert, sizeof(cert) ); + + FAULT_ON_NULL(arrData); + + certBytes = arrData->GetFirstElement(); + + if(!SSL_ParseCertificate( (const char*)certBytes, arrData->m_numOfElements, szPwd, &cert )) + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( hbIssuer, cert.Issuer )); + NANOCLR_CHECK_HRESULT(hbIssuer.StoreToReference( stack.Arg2(), 0 )); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( hbSubject, cert.Subject )); + NANOCLR_CHECK_HRESULT(hbSubject.StoreToReference( stack.Arg3(), 0 )); + + st.wYear = cert.EffectiveDate.year; + st.wMonth = cert.EffectiveDate.month; + st.wDay = cert.EffectiveDate.day; + st.wHour = cert.EffectiveDate.hour; + st.wMinute = cert.EffectiveDate.minute; + st.wSecond = cert.EffectiveDate.second; + st.wMilliseconds = cert.EffectiveDate.msec; + + // standardBias = Time_GetTimeZoneOffset(); + // standardBias *= TIME_CONVERSION__ONEMINUTE; + + val = Library_corlib_native_System_DateTime::GetValuePtr( stack.Arg4() ); + *val = HAL_Time_ConvertFromSystemTime(&st); + + // tzOffset = cert.EffectiveDate.tzOffset; + + // // adjust for timezone differences + // if(standardBias != tzOffset) + // { + // *val += tzOffset - standardBias; + // } + + st.wYear = cert.ExpirationDate.year; + st.wMonth = cert.ExpirationDate.month; + st.wDay = cert.ExpirationDate.day; + st.wHour = cert.ExpirationDate.hour; + st.wMinute = cert.ExpirationDate.minute; + st.wSecond = cert.ExpirationDate.second; + st.wMilliseconds = cert.ExpirationDate.msec; + + val = Library_corlib_native_System_DateTime::GetValuePtr( stack.ArgN( 5 ) ); + *val = HAL_Time_ConvertFromSystemTime(&st); + + // tzOffset = cert.ExpirationDate.tzOffset; + + // if(standardBias != tzOffset) + // { + // *val += tzOffset - standardBias; + // } + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native_System_Security_Cryptography_X509Certificates_X509Certificate2.cpp b/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native_System_Security_Cryptography_X509Certificates_X509Certificate2.cpp new file mode 100644 index 00000000..0ed9c8e4 --- /dev/null +++ b/source/native/nf-interpreter/src/DeviceInterfaces/System.Net/sys_net_native_System_Security_Cryptography_X509Certificates_X509Certificate2.cpp @@ -0,0 +1,36 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "sys_net_native.h" + +HRESULT Library_sys_net_native_System_Security_Cryptography_X509Certificates_X509Certificate2::DecodePrivateKeyNative___STATIC__VOID__SZARRAY_U1__STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* keyData = stack.Arg0().DereferenceArray(); + CLR_UINT8* keyBuffer; + CLR_RT_HeapBlock* passwordHb = stack.Arg1().DereferenceString(); + const char* password; + + // get key buffer + keyBuffer = keyData->GetFirstElement(); + + // manage password + FAULT_ON_NULL_ARG(passwordHb); + password = passwordHb->StringText(); + + if(SSL_DecodePrivateKey( + (const unsigned char*)keyBuffer, + keyData->m_numOfElements, + (const unsigned char*)password, + hal_strlen_s(password)) < 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/HAL/Include/nanoHAL.h b/source/native/nf-interpreter/src/HAL/Include/nanoHAL.h new file mode 100644 index 00000000..d006b2cc --- /dev/null +++ b/source/native/nf-interpreter/src/HAL/Include/nanoHAL.h @@ -0,0 +1,1805 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _NANOHAL_H_ +#define _NANOHAL_H_ 1 + +#include +#include +#include +#include +#include +#include + +#if defined(PLATFORM_EMULATED_FLOATINGPOINT) +/***************************************************/ +// Keep in sync with the nanoCLR_Runtime__HeapBlock.h + +#define HAL_FLOAT_SHIFT 10 +#define HAL_FLOAT_PRECISION 1000 + +#define HAL_DOUBLE_SHIFT 16 +#define HAL_DOUBLE_PRECISION 10000 + +/************************************************/ +#else +#include +#endif + + + +#include +#include +#include +#include +#include + +//#if !defined(_WIN32) && !defined(FIQ_SAMPLING_PROFILER) && !defined(HAL_REDUCESIZE) && defined(PROFILE_BUILD) +//#define ENABLE_NATIVE_PROFILER +//#endif + +//#include "..\pal\Diagnostics\Native_Profiler.h" + +#define NATIVE_PROFILE_CLR_DEBUGGER() +#define NATIVE_PROFILE_CLR_UTF8_DECODER() +#define NATIVE_PROFILE_CLR_CORE() +#define NATIVE_PROFILE_CLR_MESSAGING() +#define NATIVE_PROFILE_CLR_SERIALIZATION() +#define NATIVE_PROFILE_CLR_NETWORK() +#define NATIVE_PROFILE_CLR_I2C() +#define NATIVE_PROFILE_CLR_DIAGNOSTICS() +#define NATIVE_PROFILE_CLR_HARDWARE() +#define NATIVE_PROFILE_CLR_GRAPHICS() +#define NATIVE_PROFILE_CLR_STARTUP() +#define NATIVE_PROFILE_CLR_HEAP_PERSISTENCE() +#define NATIVE_PROFILE_CLR_IOPORT() +#define NATIVE_PROFILE_CLR_IO() + + +#if defined(_MSC_VER) + +#define GNU_PACKED + + + + + +#elif defined(__GNUC__) + + +#define GNU_PACKED __attribute__((packed)) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +#else +!ERROR +#endif + +//--// + + + + + + + + + + + + + + +//--// + + + +//--// + + + + + + + +//--// + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +#define TRANSPORT_SHIFT 8 +#define TRANSPORT_MASK (0xFF << TRANSPORT_SHIFT) +#define PORT_NUMBER_MASK 0x00FF + +// Macro to extract the transport type from a COM_HANDLE +#define ExtractTransport(x) ((unsigned int)(x) & TRANSPORT_MASK) + +// Macro to extract well-known system event flag ids from a COM_HANDLE +#define ExtractEventFromTransport(x) (ExtractTransport(x) == USART_TRANSPORT ? SYSTEM_EVENT_FLAG_COM_IN: \ + ExtractTransport(x) == SOCKET_TRANSPORT ? SYSTEM_EVENT_FLAG_SOCKET: \ + ExtractTransport(x) == GENERIC_TRANSPORT ? SYSTEM_EVENT_FLAG_GENERIC_PORT: \ + ExtractTransport(x) == DEBUG_TRANSPORT ? SYSTEM_EVENT_FLAG_DEBUGGER_ACTIVITY: \ + ExtractTransport(x) == MESSAGING_TRANSPORT ? SYSTEM_EVENT_FLAG_MESSAGING_ACTIVITY: \ + 0) \ + +#define USART_TRANSPORT (1 << TRANSPORT_SHIFT) +//#define COM_NULL ((COM_HANDLE)(USART_TRANSPORT)) + +#define USB_TRANSPORT (2 << TRANSPORT_SHIFT) +//#define USB_CONTROLLER_SHIFT 5 +//#define USB_CONTROLLER_MASK 0xE0 +//#define USB_STREAM_MASK 0x00FF +//#define USB_STREAM_INDEX_MASK 0x001F + +#define SOCKET_TRANSPORT (3 << TRANSPORT_SHIFT) +#define COM_SOCKET_DBG ((COM_HANDLE)(SOCKET_TRANSPORT + 1)) + +#define DEBUG_TRANSPORT (4 << TRANSPORT_SHIFT) + + + + + + + +#define MESSAGING_TRANSPORT (7 << TRANSPORT_SHIFT) + +#define GENERIC_TRANSPORT (8 << TRANSPORT_SHIFT) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +// Creates a COM_HANDLE value for a platform specific port number +#define ConvertCOM_DebugHandle(x) ((COM_HANDLE)((x) + DEBUG_TRANSPORT + 1)) + +// Extracts a Socket transport port id from a SOCKET_TRASNPORT COM_HANDLE +#define ConvertCOM_SockPort(x) (((x) & PORT_NUMBER_MASK) - 1) + +typedef unsigned int FLASH_WORD; + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +typedef void (*LOGGING_CALLBACK)(const char* text); + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +// //--// + +// //--// + + + + +//--// + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +//--// + + + + + + + + + + + + + + +//--// + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +template class HAL_DblLinkedList; + +template class HAL_DblLinkedNode +{ + T* m_nextNode; + T* m_prevNode; + + friend class HAL_DblLinkedList; + +public: + void Initialize() + { + m_nextNode = NULL; + m_prevNode = NULL; + } + + T* Next() const { return m_nextNode; } + T* Prev() const { return m_prevNode; } + + void SetNext( T* next ) { m_nextNode = next; } + void SetPrev( T* prev ) { m_prevNode = prev; } + + bool IsLinked() const { return m_nextNode != NULL; } + + //--// + + void RemoveFromList() + { + T* next = m_nextNode; + T* prev = m_prevNode; + + if(prev) prev->m_nextNode = next; + if(next) next->m_prevNode = prev; + } + + void Unlink() + { + T* next = m_nextNode; + T* prev = m_prevNode; + + if(prev) prev->m_nextNode = next; + if(next) next->m_prevNode = prev; + + m_nextNode = NULL; + m_prevNode = NULL; + } +}; + +//--// + +// The use of offsetof below throwns an "invalid offset warning" because CLR_RT_StackFrame is not POD type +// C+17 is the first standard that allow this, so until we are using it we have to disable it to keep GCC happy + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Winvalid-offsetof" +#endif + +template class HAL_DblLinkedList +{ + // + // Logically, a list starts with a HAL_DblLinkedNode with only the Next() set and ends with a node with only Prev() set. + // This can be collapsed to have the two nodes overlap. + // + T* m_first; + T* m_null; + T* m_last; + + //--// + +public: + void Initialize() + { + m_first = Tail(); + m_null = NULL; + m_last = Head(); + } + + int NumOfNodes() + { + T* ptr; + T* ptrNext; + int num = 0; + + for(ptr = FirstNode(); (ptrNext = ptr->Next()) != NULL; ptr = ptrNext) + { + num++; + } + + return num; + } + + //--// + + T* FirstNode() const { return m_first ; } + T* LastNode () const { return m_last ; } + bool IsEmpty () const { return m_first == Tail(); } + + T* FirstValidNode() const { T* res = m_first; return res->Next() ? res : NULL; } + T* LastValidNode () const { T* res = m_last ; return res->Prev() ? res : NULL; } + + T* Head() const { return (T*)((size_t)&m_first - offsetof(T, m_nextNode)); } + T* Tail() const { return (T*)((size_t)&m_last - offsetof(T, m_prevNode)); } + + //--// + +private: + + void Insert( T* prev, T* next, T* node ) + { + node->m_nextNode = next; + node->m_prevNode = prev; + + next->m_prevNode = node; + prev->m_nextNode = node; + } + +public: +#if defined(_DEBUG) + bool Exists( T* searchNode ) + { + T* node = FirstValidNode(); + while( node != NULL && node != searchNode ) + { + if (node == node->Next()) + { + ASSERT(false); + } + node = node->Next(); + } + return (node == NULL? false: true); + } +#endif + + void InsertBeforeNode( T* node, T* nodeNew ) + { + if(node && nodeNew && node != nodeNew) + { + nodeNew->RemoveFromList(); + + Insert( node->Prev(), node, nodeNew ); + } + } + + void InsertAfterNode( T* node, T* nodeNew ) + { + if(node && nodeNew && node != nodeNew) + { + nodeNew->RemoveFromList(); + + Insert( node, node->Next(), nodeNew ); + } + } + + void LinkAtFront( T* node ) + { + InsertAfterNode( Head(), node ); + } + + void LinkAtBack( T* node ) + { + InsertBeforeNode( Tail(), node ); + } + + T* ExtractFirstNode() + { + T* node = FirstValidNode(); + + if(node) node->Unlink(); + + return node; + } + + T* ExtractLastNode() + { + T* node = LastValidNode(); + + if(node) node->Unlink(); + + return node; + } +}; + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +//--// + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +template class Hal_Queue_UnknownSize +{ + size_t m_writer; + size_t m_reader; + size_t m_size; + bool m_full; + T* m_data; + +public: + void Initialize( T* data, size_t size ) + { + m_writer = 0; + m_reader = 0; + m_size = size; + m_data = data; + m_full = false; + } + + size_t NumberOfElements() + { + if(m_writer < m_reader) return m_size + m_writer - m_reader; + else if(m_full) return m_size; + else return m_writer - m_reader; + } + + bool IsEmpty() + { + return (m_writer == m_reader && !m_full); + } + + bool IsFull() + { + return m_full; + } + + T* operator[](int index) + { + if(index < 0 || index >= NumberOfElements()) return NULL; + + return &m_data[(m_reader + index) % m_size]; + } + + T* Push() + { + size_t oldWriter = m_writer; + + if(m_full) return NULL; + + m_writer++; if(m_writer == m_size) m_writer = 0; + + if(m_writer == m_reader) m_full = true; + + return &m_data[oldWriter]; + } + + T* Peek() + { + if(m_writer == m_reader && !m_full) return NULL; + + return &m_data[m_reader]; + } + + T* Pop() + { + size_t oldReader = m_reader; + + if(m_reader == m_writer && !m_full) return (T*)NULL; + + m_reader++; if(m_reader == m_size) m_reader = 0; + + m_full = false; + + return &m_data[oldReader]; + } + + T* Push( size_t &nElements ) + { + size_t oldWriter = m_writer; + size_t max = 0; + + if(m_full || (nElements == 0)) + { + nElements = 0; + return NULL; + } + + if(m_writer < m_reader) max = m_reader - m_writer; + else max = m_size - m_writer; + + nElements = (max < nElements? max: nElements); + + m_writer += nElements; if(m_writer == m_size) m_writer = 0; + + if(m_writer == m_reader) m_full = true; + + return &m_data[oldWriter]; + } + + T* Pop( size_t &nElements ) + { + size_t oldReader = m_reader; + size_t max = 0; + + if(nElements == 0) return NULL; + + if((m_reader == m_writer) && !m_full) + { + nElements = 0; + // reset the reader/writer to maximize push potential + m_reader = 0; + m_writer = 0; + return NULL; + } + + if(m_writer <= m_reader) max = m_size - m_reader; + else max = m_writer - m_reader; + + nElements = (max < nElements? max: nElements); + + m_reader += nElements; if(m_reader == m_size) m_reader = 0; + + m_full = false; + + return &m_data[oldReader]; + } + + T* Storage() { return m_data; } +}; + +template class HAL_RingBuffer +{ + size_t _dataSize; + size_t _size; + size_t _capacity; + size_t _write_index; + size_t _read_index; + T * _buffer; + +public: + + void Initialize(T* data, size_t size) + { + _dataSize = sizeof(T); + + _capacity = (size * _dataSize); + _write_index = 0; + _read_index = 0; + _size = 0; + + _buffer = data; + } + + size_t Capacity() { return (_capacity / _dataSize); } + + size_t Length() { return (_size / _dataSize); } + + // Push a single element to the buffer. + size_t Push(const T data) + { + // check for buffer full + if(_size == _capacity) + { + // buffer full + return 0; + } + + T* destination = _buffer; + destination += _write_index; + + *destination = data; + _write_index += _dataSize; + + // check if we are the end of the capacity + if (_write_index == _capacity) _write_index = 0; + + // update ring buffer size + _size += _dataSize; + + return 1; + } + + // Push N elements to the buffer. + size_t Push(const T* data, size_t length) + { + size_t lengthToWrite = 0; + + // sanity check for 0 length + if (length == 0) return 0; + + // check for buffer full + if(_size == _capacity) + { + // buffer full + return 0; + } + + if( (length * _dataSize) < (_capacity - _size)) + { + lengthToWrite = (length * _dataSize); + } + else + { + lengthToWrite = (_capacity - _size); + } + + // single memcpy + if (lengthToWrite <= _capacity - _write_index) + { + memcpy(_buffer + _write_index, data, lengthToWrite); + _write_index += lengthToWrite; + + // check if we are the end of the capacity + if (_write_index == _capacity) _write_index = 0; + } + // need to memcpy in two chunks + else + { + size_t chunk1Size = _capacity - _write_index; + memcpy(_buffer + _write_index, data, chunk1Size); + + size_t chunk2Size = lengthToWrite - chunk1Size; + memcpy(_buffer, data + chunk1Size, chunk2Size); + + _write_index = chunk2Size; + } + + // update ring buffer size + _size += lengthToWrite; + + return (lengthToWrite / _dataSize); + } + + // Pop N elements from ring buffer returning them in the data argument. + size_t Pop(T* data, size_t length) + { + size_t lengthToRead = 0; + + // sanity check for 0 length + if (length == 0) return 0; + + // check for buffer empty + if(_size == 0) + { + return 0; + } + + lengthToRead = (length * _dataSize); + + // can read in a single memcpy + if (lengthToRead <= _capacity - _read_index) + { + memcpy(data, _buffer + _read_index, lengthToRead); + _read_index += lengthToRead; + + // check if we are at end of capacity + if (_read_index == _capacity) _read_index = 0; + } + // need to memcpy in two steps + else + { + size_t chunk1Size = _capacity - _read_index; + memcpy(data, _buffer + _read_index, chunk1Size); + + size_t chunk2Size = lengthToRead - chunk1Size; + memcpy(data + chunk1Size, _buffer, chunk2Size); + + _read_index = chunk2Size; + } + + // update ring buffer size + _size -= lengthToRead; + + // check for optimization to improve sequential push + // buffer has to be empty and read and write indexes coincide + if(_size == 0 && (_write_index == _read_index)) + { + // reset the read/write index + _write_index = 0; + _read_index = 0; + } + + return (lengthToRead / _dataSize); + } + + // Pop N elements from ring buffer. The elements are not actually returned, just popped from the buffer. + size_t Pop(size_t length) + { + size_t lengthToRead = 0; + + // sanity check for 0 length + if (length == 0) return 0; + + // check for buffer empty + if(_size == 0) + { + return 0; + } + + lengthToRead = (length * _dataSize); + + // can read in a single memcpy + if (lengthToRead <= _capacity - _read_index) + { + _read_index += lengthToRead; + + // check if we are at end of capacity + if (_read_index == _capacity) _read_index = 0; + } + // need to memcpy in two steps + else + { + size_t chunk1Size = _capacity - _read_index; + size_t chunk2Size = lengthToRead - chunk1Size; + _read_index = chunk2Size; + } + + // update ring buffer size + _size -= lengthToRead; + + // check for optimization to improve sequential push + // buffer has to be empty and read and write indexes coincide + if(_size == 0 && (_write_index == _read_index)) + { + // reset the read/write index + _write_index = 0; + _read_index = 0; + } + + return (lengthToRead / _dataSize); + } + + void OptimizeSequence() + { + // no elements, so there is nothing to optimize + if(_size == 0) return; + + // read index is already at index 0, so there is nothing to optimize + if(_read_index == 0) return; + + // can move data in a single memcpy + if (_read_index < _write_index) + { + // buffer looks like this + // |...xxxxx.....| + memcpy(_buffer, _buffer + _read_index, _size); + } + // need to move data in two steps + else + { + // buffer looks like this + // |xxxx......xxxxxx| + + // store size of tail + size_t tailSize = _write_index - (1 * _dataSize); + + // 1st move tail to temp buffer (need to malloc first) + T* tempBuffer = (T*)platform_malloc(tailSize); + + memcpy(tempBuffer, _buffer, tailSize); + + // store size of remaining buffer + size_t headSize = _capacity - _read_index; + + // 2nd move head to start of buffer + memcpy(_buffer, _buffer + _read_index, headSize); + + // 3rd move temp buffer after head + memcpy(_buffer + headSize, tempBuffer, tailSize); + + // free memory + platform_free(tempBuffer); + } + + // adjust indexes + _read_index = 0; + _write_index = _size; + } + + T* Reader() { return _buffer + _read_index; } +}; + +//--// + +//#include <..\Initialization\MasterConfig.h> + + + + + + +//--// + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +// hal cleanup for CLR reboot + +void nanoHAL_Initialize(); +void nanoHAL_Uninitialize(); + +void HAL_EnterBooterMode(); + +typedef void (*ON_SOFT_REBOOT_HANDLER)(void); + +void HAL_AddSoftRebootHandler(ON_SOFT_REBOOT_HANDLER handler); + +//--// + + + + + + + + + + + + + + + + + +//--// + + + +//--// + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +//--// + +extern bool g_fDoNotUninitializeDebuggerPort; + +//--// + +#include +#include +//#include + +///////////////////////////////////////////////////////////////////// +// +// Chipset +// + +//// boot +//#include +// +//// Cache driver +//#include +// +//// Cache driver +//#include +// +//// Gp I/O driver +//#include +// +//// Gp I/O driver +//#include +// + + + + + + + + + + + + + + + + + + +// +//// SPI driver +//#include +// +//// External bus interface driver +//#include +// +//// Power control unit +//#include +// +//// Clock management unit driver +//#include +// +//// DMA driver +//#include +// +//#include +// +//// Virtual Key +//#include +// + +//// Power API +//#include + + + +// +// Chipset +// +///////////////////////////////////////////////////////////////////// + +//#include + + +// platform_selector.h (from MasterConfig.h) + +#if defined(_WIN32) + +#define GLOBAL_LOCK() +#define GLOBAL_UNLOCK() + +#if defined(_DEBUG) +#define ASSERT_IRQ_MUST_BE_ON() ASSERT(!HAL_Windows_HasGlobalLock()) +#else +#define ASSERT_IRQ_MUST_BE_ON() +#endif + +#elif defined(__arm__) | defined(PLATFORM_ESP32) +// nothing to define here just to help the nanoCLR VS project to build hapilly +#else +#error Unsupported platform +#endif + +#endif // _NANOHAL_H_ diff --git a/source/native/nf-interpreter/src/HAL/Include/nanoHAL_ConfigurationManager.h b/source/native/nf-interpreter/src/HAL/Include/nanoHAL_ConfigurationManager.h new file mode 100644 index 00000000..a1c7df09 --- /dev/null +++ b/source/native/nf-interpreter/src/HAL/Include/nanoHAL_ConfigurationManager.h @@ -0,0 +1,157 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _NANOHAL_CONFIG_MANAGER_H_ +#define _NANOHAL_CONFIG_MANAGER_H_ 1 + +#include +#include +#include + + +#ifdef __cplusplus +extern "C" { +#endif + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH nanoFramework.Tools.Debugger.DeviceConfiguration.DeviceConfigurationOption (in managed code) !!! // +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +typedef enum DeviceConfigurationOption +{ + // Network configuration block + DeviceConfigurationOption_Network = 1, + + // Wireless 802.11 Network configuration block + DeviceConfigurationOption_Wireless80211Network = 2, + + // Wireless Network as AP configuration block + DeviceConfigurationOption_WirelessNetworkAP = 3, + + // X509 CA Root Certificates bundle block + DeviceConfigurationOption_X509CaRootBundle = 4, + + // All configuration blocks + DeviceConfigurationOption_All = 255, + +} DeviceConfigurationOption; + +// network interface configuration struct +// declared with a flexible array member to allow N config blocks totally independent of compilation +typedef struct HAL_CONFIGURATION_NETWORK +{ + // count of the configs elements + uint8_t Count; + + // pointer to the network interface configuration + HAL_Configuration_NetworkInterface* Configs[]; + +} HAL_CONFIGURATION_NETWORK; + +// network wireless interface configuration struct +// declared with a flexible array member to allow N config blocks totally independent of compilation +typedef struct HAL_CONFIGURATION_NETWORK_WIRELESS80211 +{ + // count of the configs elements + uint8_t Count; + + // pointer to the wireless network interface configuration + HAL_Configuration_Wireless80211* Configs[]; + +} HAL_CONFIGURATION_NETWORK_WIRELESS80211; + +// network wireless interface configuration struct +// declared with a flexible array member to allow N config blocks totally independent of compilation +typedef struct HAL_CONFIGURATION_NETWORK_WIRELESSAP +{ + // count of the configs elements + uint8_t Count; + + // pointer to the wireless network interface configuration + HAL_Configuration_WirelessAP* Configs[]; + +} HAL_CONFIGURATION_NETWORK_WIRELESSAP; + + +// certificate store struct +// declared with a flexible array member to allow N config blocks totally independent of compilation +typedef struct HAL_CONFIGURATION_X509_CERTIFICATE +{ + // count of the configs elements + uint8_t Count; + + // pointer to the certificates + HAL_Configuration_X509CaRootBundle* Certificates[]; + +} HAL_CONFIGURATION_X509_CERTIFICATE; + +// target configuration storage struct +// the memory allocation for these will have to be done as required according to the number and type of blocks found in memory +typedef struct HAL_TARGET_CONFIGURATION +{ + HAL_CONFIGURATION_NETWORK* NetworkInterfaceConfigs; + HAL_CONFIGURATION_NETWORK_WIRELESS80211* Wireless80211Configs; + HAL_CONFIGURATION_NETWORK_WIRELESSAP* WirelessAPConfigs; + HAL_CONFIGURATION_X509_CERTIFICATE* CertificateStore; + +} HAL_TARGET_CONFIGURATION; + +// Initialization of configuration manager +void ConfigurationManager_Initialize(); + +// Enumerates the configuration blocks +// This is provided as a separate function to allow it to be called when there is a need to re-enumerate the blocks +// for example when a new block is added from the debug or from the managed application +void ConfigurationManager_EnumerateConfigurationBlocks(); + +// GetConfigurationBlock() is defined in targetHAL_ConfigurationManager.cpp at target level because the target +// needs to be free to implement the storage of the configuration block as they see fit +bool ConfigurationManager_GetConfigurationBlock(void* configurationBlock, DeviceConfigurationOption configuration, uint32_t configurationIndex); + +// StoreConfigurationBlock() is defined in targetHAL_ConfigurationManager.cpp at target level because the target +// needs to be free to implement the storage of the configuration block as they see fit +bool ConfigurationManager_StoreConfigurationBlock(void* configurationBlock, DeviceConfigurationOption configuration, uint32_t configurationIndex, uint32_t blockSize, uint32_t offset); + +// UpdateConfigurationBlock() is defined in targetHAL_ConfigurationManager.cpp at target level because the target +// needs to be free to implement the storage of the configuration block as they see fit +bool ConfigurationManager_UpdateConfigurationBlock(void* configurationBlock, DeviceConfigurationOption configuration, uint32_t configurationIndex); + + +// Default initialisation for wireless config block +void InitialiseWirelessDefaultConfig(HAL_Configuration_Wireless80211 * pconfig, uint32_t configurationIndex); + +// Default initialisation for wireless AP config block +void InitialiseWirelessAPDefaultConfig(HAL_Configuration_WirelessAP * pconfig, uint32_t configurationIndex); + +// Default initialisation for Network interface config blocks +// returns FALSE if it's not possible to create a default config block +bool InitialiseNetworkDefaultConfig(HAL_Configuration_NetworkInterface * pconfig, uint32_t configurationIndex); + +// helper functions + +// function that sweeps a memory region searching for network configuration blocks +void* ConfigurationManager_FindNetworkConfigurationBlocks(uint32_t startAddress, uint32_t endAddress); + +// function that sweeps a memory region searching for wireless network configuration blocks +void* ConfigurationManager_FindNetworkWireless80211ConfigurationBlocks(uint32_t startAddress, uint32_t endAddress); + +// function that sweeps a memory region searching for X509 certificates configuration blocks +void* ConfigurationManager_FindX509CertificateConfigurationBlocks(uint32_t startAddress, uint32_t endAddress); + +// gets the HAL_Configuration_Wireless80211 configuration block that has the specified Id, if that exists +// defined as weak needs to be free to implement the storage of the configuration block as they see fit +HAL_Configuration_Wireless80211* ConfigurationManager_GetWirelessConfigurationFromId(uint32_t configurationId); + +// gets the HAL_Configuration_WirelessAP configuration block that has the specified Id, if that exists +// defined as weak needs to be free to implement the storage of the configuration block as they see fit +HAL_Configuration_WirelessAP* ConfigurationManager_GetWirelessAPConfigurationFromId(uint32_t configurationId); + +#ifdef __cplusplus +} +#endif + +// declaration of Target configuration union as external, has to be provided at target level +extern HAL_TARGET_CONFIGURATION g_TargetConfiguration; + +#endif //_NANOHAL_CONFIG_MANAGER_H_ diff --git a/source/native/nf-interpreter/src/HAL/Include/nanoHAL_Network.h b/source/native/nf-interpreter/src/HAL/Include/nanoHAL_Network.h new file mode 100644 index 00000000..45644565 --- /dev/null +++ b/source/native/nf-interpreter/src/HAL/Include/nanoHAL_Network.h @@ -0,0 +1,292 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _NANOHAL_NETWORK_H_ +#define _NANOHAL_NETWORK_H_ 1 + +#include +#include +#include + +// this is the maximum hardware address length (MAC address) +// setting it to 6 and using the same define that lwIP uses for this +#define NETIF_MAX_HWADDR_LEN 6 + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH System.Net.NetworkInformation.Wireless80211Configuration.MaxPasswordLength (in managed code) !!! // +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// this is the maximum wireless 802.11 configuration password length +#define WIRELESS82011_CONFIG_MAX_PASSWORD_LEN 64 + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH System.Net.NetworkInformation.Wireless80211Configuration.MaxSsidLength (in managed code) !!! // +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// this is the maximum wireless 802.11 configuration SSID length +#define WIRELESS82011_CONFIG_MAX_SSID_LEN 32 + +///////////////////////////////////////// +// network configuration block markers // +///////////////////////////////////////// + +// Network configuration block start marker +static const unsigned char c_MARKER_CONFIGURATION_NETWORK_V1[] = "CN1"; + +// Network configuration block start marker +static const unsigned char c_MARKER_CONFIGURATION_WIRELESS80211_V1[] = "WN1"; + +// Wireless AP configuration block start marker +static const unsigned char c_MARKER_CONFIGURATION_WIRELESS_AP_V1[] = "AP1"; + +// X509 certificate configuration block start marker +static const unsigned char c_MARKER_CONFIGURATION_X509CAROOTBUNDLE_V1[] = "XB1"; + +//////////////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH System.Net.NetworkInformation.NetworkInterfaceType (in managed code) !!! // +//////////////////////////////////////////////////////////////////////////////////////////////////// + +///////////////////////////////////////////////// +// Description: network interface type +typedef enum __nfpack NetworkInterfaceType +{ + NetworkInterfaceType_Unknown = 1, + NetworkInterfaceType_Ethernet = 6, + NetworkInterfaceType_Wireless80211 = 71, + NetworkInterfaceType_WirelessAP = 72, +}NetworkInterfaceType; + +/////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH System.Net.NetworkInformation.AddressMode (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////////// + +///////////////////////////////////////////////// +// Description: Startup network IP assigning modes +typedef enum __nfpack AddressMode +{ + AddressMode_DHCP = 0x01, + AddressMode_Static = 0x02, + + //////////////////////////////////////// + // for this option to be valid + // LWIP_AUTOIP (lwIP option) has to be defined + AddressMode_AutoIP = 0x03 + +}AddressMode; + +////////////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH System.Net.NetworkInformation.AuthenticationType (in managed code) !!! // +////////////////////////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////// +// Description: authentication used in wireless network +typedef enum __nfpack AuthenticationType +{ + AuthenticationType_None = 0x00, + AuthenticationType_EAP = 0x01, + AuthenticationType_PEAP = 0x02, + AuthenticationType_WCN = 0x03, + AuthenticationType_Open = 0x04, + AuthenticationType_Shared = 0x05, + AuthenticationType_WEP = 0x06, + AuthenticationType_WPA = 0x07, + AuthenticationType_WPA2 = 0x08, + +}AuthenticationType; + +////////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH System.Net.NetworkInformation.EncryptionType (in managed code) !!! // +////////////////////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////// +// Description: encryption used in wireless network +typedef enum __nfpack EncryptionType +{ + EncryptionType_None = 0x00, + EncryptionType_WEP = 0x01, + EncryptionType_WPA = 0x02, + EncryptionType_WPA2 = 0x03, + EncryptionType_WPA_PSK = 0x04, + EncryptionType_WPA2_PSK = 0x05, + EncryptionType_Certificate = 0x06, + +}EncryptionType; + +///////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH System.Net.NetworkInformation.RadioType (in managed code) !!! // +///////////////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////// +// Description: type of radio that the wireless network uses +typedef enum __nfpack RadioType +{ + RadioType_NotSpecified = 0x00, + RadioType_802_11a = 0x01, + RadioType_802_11b = 0x02, + RadioType_802_11g = 0x03, + RadioType_802_11n = 0x04, +}RadioType; + +typedef struct __nfpack HAL_Configuration_NetworkInterface { + + // this is the marker placeholder for this configuration block + uint8_t Marker[4]; + + // Pointer to MAC address as an array of 6 unsigned bytes. + uint8_t MacAddress[6]; + + // Network IPv4 address as 32-bit unsigned integer + uint32_t IPv4Address; + + // Network IPv4 subnet mask as 32-bit unsigned integer + uint32_t IPv4NetMask; + + // Network gateway IPv4 address as 32-bit unsigned integer + uint32_t IPv4GatewayAddress; + + // DNS server 1 IPv4 address as 32-bit unsigned integer + uint32_t IPv4DNSAddress1; + + // DNS server 2 IPv4 address as 32-bit unsigned integer + uint32_t IPv4DNSAddress2; + + // Network IPv6 address as an array of 4 32-bit unsigned integers + uint32_t IPv6Address[4]; + + // Network IPv6 subnet mask as an array of 4 32-bit unsigned integers + uint32_t IPv6NetMask[4]; + + // Network gateway IPv6 address as an array of 4 32-bit unsigned integers + uint32_t IPv6GatewayAddress[4]; + + // DNS server 1 IPv6 address as an array of 4 32-bit unsigned integers + uint32_t IPv6DNSAddress1[4]; + + // DNS server 2 IPv6 address as an array of 4 32-bit unsigned integers + uint32_t IPv6DNSAddress2[4]; + + // interface type + NetworkInterfaceType InterfaceType; + + // Specific configuration Id + // Id of the configuration block specific for this interface type + // NULL otherwise + // currently in use: + // - HAL_Configuration_Wireless80211 for NetworkInterfaceType_Wireless80211 + uint32_t SpecificConfigId; + + // Option to use DNS addresses from DHCP or static ones + uint8_t AutomaticDNS; + + // Startup network addressing mode - static, DHCP, auto + AddressMode StartupAddressMode; + +} HAL_Configuration_NetworkInterface; + +typedef enum __nfpack WirelessFlags +{ + WirelessFlags_None = 0x00, + WirelessFlags_Enable = 0x01, // Enable Station or AP ( Wifi component started & memory allocated ) + WirelessFlags_Auto = 0x02, // Wireless station automatically connects on CLR start + WirelessFlags_SmartConfig = 0x04 // Enable Smart config +} WirelessFlags; + +typedef enum __nfpack WirelessAPFlags +{ + WirelessAPFlags_None = 0x00, + WirelessAPFlags_Enable = 0x01, // Enable Wireless AP ( Wifi component started & memory allocated ) + WirelessAPFlags_Auto = 0x02, // Wireless AP automatically starts on CLR start + WirelessAPFlags_Hidden_SSID = 0x04, // Wireless AP uses hidden SSID +} WirelessAPFlags; + +typedef struct __nfpack HAL_Configuration_Wireless80211 { + + // this is the marker placeholder for this configuration block + uint8_t Marker[4]; + + // Id of the configuration + uint32_t Id; + + // Type of authentication used on the wireless network, For AP is the type of Authenication to use on network. + AuthenticationType Authentication; + + // Type of encryption used on the wireless network. + EncryptionType Encryption; + + // Type of radio used by the wireless network adapter. + RadioType Radio; + + // Network SSID - For AP if no SSID given a default value of nano_xxx where xxx is last part of MAC address + uint8_t Ssid[32]; + + // Network password + uint8_t Password[64]; + + // Wireless Flags, depends if wireless Station + uint8_t Flags; + + // Rssi, station only + +} HAL_Configuration_Wireless80211; + +typedef struct __nfpack HAL_Configuration_WirelessAP { + + // this is the marker placeholder for this configuration block + uint8_t Marker[4]; + + // Id of the configuration + uint32_t Id; + + // Type of authentication used on the wireless network, For AP is the type of Authenication to use on network. + AuthenticationType Authentication; + + // Type of encryption used on the wireless network. + EncryptionType Encryption; + + // Type of radio used by the wireless network adapter. + RadioType Radio; + + // Network SSID - For AP if no SSID given a default value of nano_xxx where xxx is last part of MAC address + uint8_t Ssid[32]; + + // Network password + uint8_t Password[64]; + + // Wireless Flags for AP + uint8_t Flags; + + // channel used for AP + uint8_t Channel; + + // Max client connections + uint8_t MaxConnections; + +} HAL_Configuration_WirelessAP; + +typedef struct __nfpack HAL_Configuration_X509CaRootBundle { + + // this is the marker placeholder for this configuration block + uint8_t Marker[4]; + + // Size of the X509 CA Root certificate bundle + uint32_t CertificateSize; + + // X509 CA Root certificate bundle + uint8_t Certificate[1]; + +} HAL_Configuration_X509CaRootBundle; + + +void nanoHAL_Network_Initialize(); +void sys_signal_sock_event(); + + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif //_NANOHAL_NETWORK_H_ diff --git a/source/native/nf-interpreter/src/HAL/Include/nanoHAL_Power.h b/source/native/nf-interpreter/src/HAL/Include/nanoHAL_Power.h new file mode 100644 index 00000000..e8e6a2bc --- /dev/null +++ b/source/native/nf-interpreter/src/HAL/Include/nanoHAL_Power.h @@ -0,0 +1,37 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _NANOHAL_POWER_H_ +#define _NANOHAL_POWER_H_ 1 + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum PowerLevel +{ + PowerLevel__Active, + PowerLevel__SelectiveOff, + PowerLevel__Sleep, + PowerLevel__DeepSleep, + PowerLevel__Off +}PowerLevel_type; + + +// this is used to store the CPU wakeup reason +// a target implementation can use it or not +// if it's used suggest to add the variable at targetHAL_Power.c +extern uint32_t WakeupReasonStore; + +bool CPU_IsSoftRebootSupported(); + +#ifdef __cplusplus +} +#endif + +#endif //_NANOHAL_POWER_H_ diff --git a/source/native/nf-interpreter/src/HAL/Include/nanoHAL_ReleaseInfo.h b/source/native/nf-interpreter/src/HAL/Include/nanoHAL_ReleaseInfo.h new file mode 100644 index 00000000..248b5c3e --- /dev/null +++ b/source/native/nf-interpreter/src/HAL/Include/nanoHAL_ReleaseInfo.h @@ -0,0 +1,90 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _NANOHAL_RELEASEINFO_H_ +#define _NANOHAL_RELEASEINFO_H_ 1 + +#include + +struct __nfpack NFVersion +{ + unsigned short usMajor; + unsigned short usMinor; + unsigned short usBuild; + unsigned short usRevision; + + // Version & NFReleaseInfo participate in a union in the debugging support, + // and therefore cannot have real constructors, though that would be better + // style otherwise. + static void Init(NFVersion& version, unsigned short major=0, unsigned short minor=0, unsigned short build=0, unsigned short revision=0) + { + version.usMajor = major; + version.usMinor = minor; + version.usBuild = build; + version.usRevision = revision; + } +}; + +struct __nfpack NFReleaseInfo +{ + NFVersion Version; + unsigned char InfoString[128]; + unsigned char TargetName[32]; + unsigned char PlatformName[32]; + + static void Init( + NFReleaseInfo& releaseInfo, + unsigned short major=0, + unsigned short minor=0, + unsigned short build=0, + unsigned short revision=0, + const char *info=(const char *)NULL, + size_t infoLen=0, + const char *target=(const char *)NULL, + size_t targetLen=0, + const char *platform=(const char *)NULL, + size_t platformLen=0 + ); +}; + +struct __nfpack OEM_MODEL_SKU +{ + unsigned char OEM; + unsigned char Model; + unsigned short SKU; +}; + +struct __nfpack OEM_SERIAL_NUMBERS +{ + unsigned char module_serial_number[32]; + unsigned char system_serial_number[16]; +}; + +struct __nfpack HalSystemInfo +{ + NFReleaseInfo m_releaseInfo; + OEM_MODEL_SKU m_OemModelInfo; + OEM_SERIAL_NUMBERS m_OemSerialNumbers; +}; + +//--// + +// GetHalSystemInfo() is defined in \src\HAL\nanoHAL_SystemInformation.cpp and is provided +// to allow convenient access to configuration and build information to the debugging +// system and to managed code. +bool GetHalSystemInfo(HalSystemInfo& systemInfo); + +// Solution-specific function; see nanoBooterEntry.cpp in your solution's nanoBooter directory for implementation. +unsigned int nanoBooter_GetReleaseInfo(NFReleaseInfo& releaseInfo); + +// target specific function, provide this to allow access to a vendor-provided +// informative string, platform, target and build-time version information. +bool Target_GetReleaseInfo(NFReleaseInfo&); + +//--// + + +#endif // _NANOHAL_RELEASEINFO_H_ + diff --git a/source/native/nf-interpreter/src/HAL/Include/nanoHAL_Time.h b/source/native/nf-interpreter/src/HAL/Include/nanoHAL_Time.h new file mode 100644 index 00000000..bb6b67ab --- /dev/null +++ b/source/native/nf-interpreter/src/HAL/Include/nanoHAL_Time.h @@ -0,0 +1,107 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _NANOHAL_TIME_H_ +#define _NANOHAL_TIME_H_ 1 + +#include +#include +#include + +/// Our time origin is 1/1/1601 00:00:00.000.000. In Gregorian Calendar Jan 1, 1601 was also a Monday. +#define BASE_YEAR 1601 +#define BASE_YEAR_LEAPYEAR_ADJUST 388 +#define DAYS_IN_NORMAL_YEAR 365 +#define BASE_YEAR_DAYOFWEEK_SHIFT 1 + +#define TIME_CONVERSION__TO_MILLISECONDS 10000 +#define TIME_CONVERSION__TO_SECONDS 10000000 +#define TIME_CONVERSION__TICKUNITS 10000 +#define TIME_CONVERSION__ONESECOND 1 +#define TIME_CONVERSION__ONEMINUTE 60 +#define TIME_CONVERSION__ONEHOUR 3600 +#define TIME_CONVERSION__ONEDAY 86400 + +#define TIMEOUT_ZERO LONGLONGCONSTANT(0x0000000000000000) +#define TIMEOUT_INFINITE LONGLONGCONSTANT(0x7FFFFFFFFFFFFFFF) + +// UNDONE: FIXME #define TIME_ZONE_OFFSET ((signed long long)Time_GetTimeZoneOffset() * 600000000) + +#define NANOHAL_TIME_CONVERSION_MICRO_TO_SECONDS 1000000 + +#define TIME_UNIX_EPOCH_AS_TICKS 116444736000000000 + +/// NOTES: Why origin is at 1/1/1601. +/// Current civil calendar is named as Gregorian calendar after Pope Gregory XIII as he made adjustments +/// in 1582 (read more at wiki http://en.wikipedia.org/wiki/Gregorian_calendar). Rules governing +/// leap years were changed from then. Also in that year month October was 21 days instead of usual 31. +/// This poses a problem on calculating date/time difference, leap years etc before 1582 using simple math. +/// For example 1500 was a leap year using old method while it is not using new. But in reality, as part of the +/// history it was leap year. Default CLR origin 1/1/01 gives wrong date time from years before 1582. For example +/// dates like 10/6/1582 does exist in history (see wiki), while CLR managed date/time will not throw an exception +/// if you are to create that date. To stay safe side 1/1/1601 is taken as origin, as was done for Windows. + + +uint64_t HAL_Time_SysTicksToTime(unsigned int sysTicks); + +/// +/// System time and date for DateTime managed class. +/// This value will be provided by the system tick or from an RTC if hardware support exists and if the board designer has enabled it in the configuration options. +/// The datePartOnly allows returning only the date part with the time fields zeroed. +/// +/// Returns current time in 100ns elapsed since 1/1/1601:00:00:00.000 UTC. +uint64_t HAL_Time_CurrentDateTime(bool datePartOnly); + +/// +/// Time according to this system. +/// +/// Returns current time in 100ns elapsed since 1/1/1601:00:00:00.000 UTC. +uint64_t HAL_Time_CurrentTime(); + +/// +/// Set UTC time of the system. This will be effective immediately. +/// +/// In 100ns since 1/1/1601:00:00:00.000 +void HAL_Time_SetUtcTime(uint64_t utcTime); + +/// +/// Retrieves time since device was booted. +/// +/// Time in 100ns. +//signed long long HAL_Time_GetMachineTime(); + +/// +/// Converts 64bit time value to SystemTime structure. 64bit time is assumed as an offset from 1/1/1601:00:00:00.000 in 100ns. +/// +/// True if conversion is successful. +bool HAL_Time_ToSystemTime(uint64_t time, SYSTEMTIME* systemTime); + +/// +/// Retrieves number of days given a month and a year. Calculates for leap years. +/// +/// S_OK if successful. +HRESULT HAL_Time_DaysInMonth(signed int year, signed int month, signed int* days); + +/// +/// Retrieves number of days since the beginning of the year given a month and a year. Calculates for leap years. +/// +/// S_OK if successful. +HRESULT HAL_Time_AccDaysInMonth(signed int year, signed int month, signed int* days); + +/// +/// Converts SYSTEMTIME structure to 64bit time, which is assumed as an offset from 1/1/1601:00:00:00.000 in 100ns. +/// +/// Time value. +uint64_t HAL_Time_ConvertFromSystemTime(const SYSTEMTIME* systemTime); + +/// APIs to convert between types +bool HAL_Time_TimeSpanToStringEx( const int64_t& ticks, char*& buf, size_t& len ); +const char* HAL_Time_CurrentDateTimeToString(); + + +uint64_t CPU_MillisecondsToTicks ( uint64_t ticks ); + +#endif //_NANOHAL_TIME_H_ diff --git a/source/native/nf-interpreter/src/HAL/Include/nanoHAL_Types.h b/source/native/nf-interpreter/src/HAL/Include/nanoHAL_Types.h new file mode 100644 index 00000000..6b181898 --- /dev/null +++ b/source/native/nf-interpreter/src/HAL/Include/nanoHAL_Types.h @@ -0,0 +1,54 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _HAL_TYPES_H_ +#define _HAL_TYPES_H_ 1 + +#include + +#include + +#if defined (__GNUC__) +#define __int64 long long +#undef NULL +#endif + +#if defined(__arm) || defined(__GNUC__) + +#undef UNICODE + +#define NULL 0 + +#endif //defined(__arm) || defined(__GNUC__) + +#define ARRAYSIZE_CONST_EXPR(x) (sizeof(x)/sizeof(x[0])) +#if (!defined(_WIN32) && !defined(WIN32)) +#define ARRAYSIZE(x) ARRAYSIZE_CONST_EXPR(x) +#endif +#define MAXSTRLEN(x) (ARRAYSIZE(x)-1) +#define ROUNDTOMULTIPLE(x,y) ((x + sizeof(y) - 1) & ~(sizeof(y)-1)) // Only works with powers of 2. +#define CONVERTFROMSIZETOELEMENTS(x,y) ((x + sizeof(y) - 1) / sizeof(y)) +#define CONVERTFROMSIZETOHEAPBLOCKS(x) CONVERTFROMSIZETOELEMENTS(x,CLR_RT_HeapBlock) + +//--// + +#if !(defined(_WIN32) || defined(WIN32)) + +typedef struct SYSTEMTIME +{ + unsigned short wYear; + unsigned short wMonth; + unsigned short wDayOfWeek; + unsigned short wDay; + unsigned short wHour; + unsigned short wMinute; + unsigned short wSecond; + unsigned short wMilliseconds; +} SYSTEMTIME; + +#endif // !(defined(_WIN32) || defined(WIN32)) + +#endif // _HAL_TYPES_H_ + diff --git a/source/native/nf-interpreter/src/HAL/Include/nanoHAL_Watchdog.h b/source/native/nf-interpreter/src/HAL/Include/nanoHAL_Watchdog.h new file mode 100644 index 00000000..a4506fd4 --- /dev/null +++ b/source/native/nf-interpreter/src/HAL/Include/nanoHAL_Watchdog.h @@ -0,0 +1,21 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _NANOHAL_WATCHDOG_H_ +#define _NANOHAL_WATCHDOG_H_ 1 + +#include + +#ifdef __cplusplus +extern "C" { +#endif + //Watchdog functions + void Watchdog_Init(); + void Watchdog_Reset(); +#ifdef __cplusplus +} +#endif + +#endif diff --git a/source/native/nf-interpreter/src/HAL/Include/nanoHAL_Windows_Storage.h b/source/native/nf-interpreter/src/HAL/Include/nanoHAL_Windows_Storage.h new file mode 100644 index 00000000..d5cd01e6 --- /dev/null +++ b/source/native/nf-interpreter/src/HAL/Include/nanoHAL_Windows_Storage.h @@ -0,0 +1,72 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// +#ifndef _NANOHAL_WINDOWS_STORAGE_H_ +#define _NANOHAL_WINDOWS_STORAGE_H_ 1 + +#include + +// FatFs define for size of file name members +// ANSI/OEM at DBCS +#define FF_LFN_BUF 255 + +// driver letters and paths +// drive letter for SD Card +#define INDEX0_DRIVE_LETTER "D:" +#define INDEX0_DRIVE_PATH INDEX0_DRIVE_LETTER"\\" +// drive letter for USB mass storage device +#define INDEX1_DRIVE_LETTER "E:" +#define INDEX1_DRIVE_PATH INDEX1_DRIVE_LETTER"\\" +// spare drive letter +#define INDEX2_DRIVE_LETTER "F:" +#define INDEX2_DRIVE_PATH INDEX2_DRIVE_LETTER"\\" +// drive letter for internal drive (SPIFFS) +#define INTERNAL_DRIVE_LETTER "I:" +#define INTERNAL_DRIVE_PATH INTERNAL_DRIVE_LETTER"\\" + +////////////////////////////////////////////////////////////////////////// +// Keep in sync with StorageEventManager.StorageEventType in managed code +// Storage events sub-categories +////////////////////////////////////////////////////////////////////////// +typedef enum StorageEventType +{ + // INVALID + StorageEventType_Invalid = 0x00, + + // removable device inserted + StorageEventType_RemovableDeviceInsertion = 0x01, + + // removable device removed + StorageEventType_RemovableDeviceRemoval = 0x02, + +}StorageEventType; + +// constants to be used throughout the code +#define SUPPORTED_DRIVES_COUNT (2) +#define DRIVE_LETTER_LENGTH sizeof(INDEX0_DRIVE_LETTER) +#define DRIVE_PATH_LENGTH sizeof(INDEX0_DRIVE_PATH) + +///////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Storage.CreationCollisionOption (in managed code) !!! // +///////////////////////////////////////////////////////////////////////////////////////// + +enum CreationCollisionOption +{ + CreationCollisionOption_GenerateUniqueName = 0, + CreationCollisionOption_ReplaceExisting, + CreationCollisionOption_FailIfExists, + CreationCollisionOption_OpenIfExists +}; + +#ifdef __cplusplus +extern "C" { +#endif + +void Target_FileSystemInit(void); + +#ifdef __cplusplus +} +#endif + +#endif // _NANOHAL_WINDOWS_STORAGE_H_ diff --git a/source/native/nf-interpreter/src/HAL/Include/nanoHAL_v2.h b/source/native/nf-interpreter/src/HAL/Include/nanoHAL_v2.h new file mode 100644 index 00000000..5e539139 --- /dev/null +++ b/source/native/nf-interpreter/src/HAL/Include/nanoHAL_v2.h @@ -0,0 +1,351 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _NANOHAL_V2_H_ +#define _NANOHAL_V2_H_ 1 + +#include +#include +#include +#include + +#include +#include +#include + +typedef enum SYSTEM_STATE +{ + SYSTEM_STATE_ISR, + SYSTEM_STATE_NO_CONTINUATIONS, + SYSTEM_STATE_TOTAL_STATES +} SYSTEM_STATE_type; + +////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Microsoft.SPOT.Hardware.SleepLevel !!! // +////////////////////////////////////////////////////////////////// +typedef enum SLEEP_LEVEL +{ + SLEEP_LEVEL__AWAKE = 0x00, + SLEEP_LEVEL__SELECTIVE_OFF = 0x10, + SLEEP_LEVEL__SLEEP = 0x20, + SLEEP_LEVEL__DEEP_SLEEP = 0x30, + SLEEP_LEVEL__OFF = 0x40, +} SLEEP_LEVEL_type; + +//These events match emulator events in Framework\Tools\Emulator\Events.cs + +#define SYSTEM_EVENT_FLAG_COM_IN 0x00000001 +#define SYSTEM_EVENT_FLAG_COM_OUT 0x00000002 +#define SYSTEM_EVENT_FLAG_STORAGE_IO 0x00000004 +#define SYSTEM_EVENT_FLAG_SYSTEM_TIMER 0x00000010 +//#define SYSTEM_EVENT_FLAG_TIMER1 0x00000020 +//#define SYSTEM_EVENT_FLAG_TIMER2 0x00000040 +//#define SYSTEM_EVENT_FLAG_BUTTON 0x00000080 +#define SYSTEM_EVENT_FLAG_GENERIC_PORT 0x00000100 +//#define SYSTEM_EVENT_FLAG_UNUSED_0x00000200 0x00000200 +//#define SYSTEM_EVENT_FLAG_UNUSED_0x00000400 0x00000400 +#define SYSTEM_EVENT_FLAG_NETWORK 0x00000800 +//#define SYSTEM_EVENT_FLAG_TONE_COMPLETE 0x00001000 +//#define SYSTEM_EVENT_FLAG_TONE_BUFFER_EMPTY 0x00002000 +#define SYSTEM_EVENT_FLAG_SOCKET 0x00004000 +#define SYSTEM_EVENT_FLAG_ONEWIRE_MASTER 0x00008000 +//#define SYSTEM_EVENT_FLAG_SPI 0x00008000 +//#define SYSTEM_EVENT_FLAG_OEM_RESERVED_1 0x00020000 +//#define SYSTEM_EVENT_FLAG_OEM_RESERVED_2 0x00040000 +//#define SYSTEM_EVENT_FLAG_UNUSED_0x00080000 0x00080000 +//#define SYSTEM_EVENT_FLAG_UNUSED_0x00100000 0x00100000 + + + + + + + +//#define SYSTEM_EVENT_FLAG_UNUSED_0x00200000 0x00200000 +//#define SYSTEM_EVENT_FLAG_UNUSED_0x00400000 0x00400000 +//#define SYSTEM_EVENT_FLAG_UNUSED_0x00800000 0x00800000 +//#define SYSTEM_EVENT_FLAG_UNUSED_0x01000000 0x01000000 +#define SYSTEM_EVENT_FLAG_SPI_MASTER 0x02000000 +#define SYSTEM_EVENT_FLAG_I2C_MASTER 0x04000000 +#define SYSTEM_EVENT_HW_INTERRUPT 0x08000000 +#define SYSTEM_EVENT_FLAG_DEBUGGER_ACTIVITY 0x20000000 +#define SYSTEM_EVENT_FLAG_MESSAGING_ACTIVITY 0x40000000 +//#define SYSTEM_EVENT_FLAG_UNUSED_0x80000000 0x80000000 +#define SYSTEM_EVENT_FLAG_ALL 0xFFFFFFFF + + +//////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH nanoFramework.Runtime.Events.EventCategory (in managed code) !!! // +//////////////////////////////////////////////////////////////////////////////////////////// + +#define EVENT_UNKNOWN 0 +#define EVENT_CUSTOM 10 +#define EVENT_GPIO 20 +#define EVENT_SERIAL 30 +#define EVENT_NETWORK 40 +#define EVENT_WIFI 50 +#define EVENT_CAN 60 +#define EVENT_STORAGE 70 + +//////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////// + + +// COM_HANDLE Defines a type representing both a port type or "transport" and a port number +// The COM_HANDLE is a multi bit field value with the following bit fields usage +// |--------+--------+--------+--------| +// |33222222|22221111|111111 | | +// |10987654|32109876|54321098|76543210| bit position +// |--------+--------+--------+--------| +// |00000000|00000000|TTTTTTTT|pppppppp| ( transport != USB_TRANSPORT ) +// |--------+--------+--------+--------| +// |00000000|00000000|TTTTTTTT|cccppppp| ( transport == USB_TRANSPORT ) +// |--------+--------+--------+--------| +// +// where: +// T => Transport type +// USART_TRANSPORT => 1 +// USB_TRANSPORT => 2 +// SOCKET_TRANSPORT => 3 +// DEBUG_TRANSPORT => 4 +// LCD_TRANSPORT => 5 +// FLASH_WRITE_TRANSPORT => 6 +// MESSAGING_TRANSPORT => 7 +// GENERIC_TRANSPORT => 8 +// p => port instance number +// Port instances in the handle are 1 based. (e.g. p == 0 is invalid except when T == 0 ) +// c -> Controller instance number ( USB_TRANSPORT only ) +// +// NULL_PORT => T==0 && p == 0 +// +// GENERIC_TRANSPORT is any custom port that isn't one of the above, they +// are implemented for the DebugPort_xxxx APIs and the port number is +// an index into a const global table of port interfaces (structure of +// function pointers) These allow custom extensions to the normal transports +// without needing to continue defining additional transport types and modifying +// switch on transport code. To keep compatibility high and code churn low, the +// previous legacy transports remain though they should be considered deprecated. +typedef int COM_HANDLE; + +typedef struct HAL_DRIVER_CONFIG_HEADER +{ + unsigned int Enable; +}HAL_DRIVER_CONFIG_HEADER; + +typedef struct HAL_SYSTEM_MEMORY_CONFIG +{ + unsigned int Base; + unsigned int Size; +}HAL_SYSTEM_MEMORY_CONFIG; + +typedef struct HAL_SYSTEM_CONFIG +{ + HAL_DRIVER_CONFIG_HEADER Header; + + //--// + + COM_HANDLE DebuggerPort; + // communication channel for debug messages in the debugger + // which may be VS, MFDEPLOY, etc... Accessed via debug_printf + // in the HAL/PAL and System.Diagnostics.Debug.Print() in managed + // applications + COM_HANDLE DebugTextPort; + + unsigned int USART_DefaultBaudRate; + // internal HAL/PAL debug/tracing channel, this is separate + // to allow tracing messages in the driver that implements + // the transport for the Debugger and DebugTextPort. This + // channel is accessed via hal_printf() in the HAL/PAL + COM_HANDLE stdio; + + HAL_SYSTEM_MEMORY_CONFIG RAM1; + HAL_SYSTEM_MEMORY_CONFIG FLASH1; + +}HAL_SYSTEM_CONFIG; + +extern HAL_SYSTEM_CONFIG HalSystemConfig; + +#ifdef __cplusplus +extern "C" { +#endif + +void nanoHAL_Initialize_C(); +void nanoHAL_Uninitialize_C(); +void HeapLocation_C(unsigned char** baseAddress, unsigned int* sizeInBytes); + +// Call to the external memory configuration and initialization function +// If a target has external memory it has to provide the implementation for it. +void Target_ExternalMemoryInit(); + +#ifdef __cplusplus +} +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +void CPU_Reset(); +void CPU_Sleep(SLEEP_LEVEL_type level, uint64_t wakeEvents); +void CPU_SetPowerMode(PowerLevel_type powerLevel); + +#ifdef __cplusplus +} +#endif + +//--// + +// +// This has to be extern "C" because we want to use platform implemented malloc +// +#ifdef __cplusplus +extern "C" { +#endif + +void* platform_malloc ( size_t size ); +void platform_free ( void* ptr ); +void* platform_realloc( void* ptr, size_t size ); + +#ifdef __cplusplus +} +#endif + +void SystemState_Set ( SYSTEM_STATE_type newState ); +void SystemState_Clear( SYSTEM_STATE_type state ); +bool SystemState_Query( SYSTEM_STATE_type state ); + +//--// + + +#ifdef __cplusplus +extern "C" { +#endif + +void SystemState_SetNoLock ( SYSTEM_STATE_type state ); +void SystemState_ClearNoLock( SYSTEM_STATE_type state ); +bool SystemState_QueryNoLock( SYSTEM_STATE_type state ); + +#ifdef __cplusplus +} +#endif + +//--// + +#define HAL_COMPLETION_IDLE_VALUE 0x0000FFFFFFFFFFFFull + +// provide platform dependent delay to CLR code +#if defined(_WIN32) +#define OS_DELAY(milliSecs); +#else +#define OS_DELAY(milliSecs) PLATFORM_DELAY(milliSecs) +#endif + +//--// +// Function macros + +#ifdef __cplusplus +extern "C" { +#endif + +void HAL_Assert ( const char* Func, int Line, const char* File ); +// HAL_AssertEx is to be defined at platform layer +void HAL_AssertEx(); + +#ifdef __cplusplus +} +#endif + +#if defined(PLATFORM_ARM) || defined(PLATFORM_ESP32) + #if !defined(BUILD_RTM) + #define ASSERT(i) { if(!(i)) HAL_AssertEx(); } + #define _SIDE_ASSERTE(i) { if(!(i)) HAL_AssertEx(); } + #endif +#else + #if defined(_DEBUG) +#if !defined _ASSERTE +#error +#endif + #define ASSERT(i) _ASSERTE(i) + #define _SIDE_ASSERTE(i) _ASSERTE(i) + #endif +#endif + +#ifndef ASSERT +#define ASSERT(i) +#endif + +#ifndef _ASSERTE +#define _ASSERTE(expr) ASSERT(expr) +#endif + +#ifndef _SIDE_ASSERTE +#define _SIDE_ASSERTE(expr) (expr) +#endif + +#if STATIC_ASSERT_SUPPORTED +#define CT_ASSERT_STRING( x ) #x +#define CT_ASSERT_UNIQUE_NAME(e,name)static_assert( (e), CT_ASSERT_STRING( name ) "@" __FILE__ CT_ASSERT_STRING(__LINE__) ); +#define CT_ASSERT(e) static_assert( (e), __FILE__ CT_ASSERT_STRING(__LINE__) ); +#else +// CT_ASSERT (compile-time assert) macro is used to test condition at compiler time and generate +// compiler error if condition is bool. +// Example: CT_ASSERT( sizeof( unsigned int ) == 2 ) would cause compilation error. +// CT_ASSERT( sizeof( unsigned int ) == 4 ) compiles without error. +// Since this declaration is just typedef - it does not create any CPU code. +// +// Reason for CT_ASSERT_UNIQUE_NAME +// The possible problem with the macro - it creates multiple identical typedefs. +// It is not a problem in global scope, but if macro is used inside of struct - it generates warnings. +// CT_ASSERT_UNIQUE_NAME is the same in essence, but it provides a way to customize the name of the type. +#define CT_ASSERT_UNIQUE_NAME(e,name) typedef char __CT_ASSERT__##name[(e)?1:-1]; +#define CT_ASSERT(e) CT_ASSERT_UNIQUE_NAME(e,nanoclr) +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#if !defined(BUILD_RTM) + +void debug_printf( const char *format, ... ); + +#else + +__inline void debug_printf( const char *format, ... ) {} + +#endif // !defined(BUILD_RTM) + +#ifdef __cplusplus +} +#endif +//--// + +#define NANOCLR_LOCKED_ACCESS_DECLARATION(type, name) type copy##name +#define NANOCLR_LOCKED_ACCESS_EXECUTE(name, expr) { GLOBAL_LOCK(); copy##name = expr; GLOBAL_UNLOCK(); } +#define NANOCLR_LOCKED_ACCESS_GET(name) copy##name + +//--// + +#ifdef __cplusplus +extern "C" { +#endif + +bool Target_HasNanoBooter(); +void HARD_Breakpoint(); +bool Target_ConfigUpdateRequiresErase(); +uint32_t GetPlatformCapabilities(); +uint32_t GetTargetCapabilities(); + +#ifdef __cplusplus +} +#endif + +// Watchdog driver +#include + +#include + +#endif // _NANOHAL_V2_H_ diff --git a/source/native/nf-interpreter/src/HAL/nanoHAL_ConfigurationManager.c b/source/native/nf-interpreter/src/HAL/nanoHAL_ConfigurationManager.c new file mode 100644 index 00000000..31250f31 --- /dev/null +++ b/source/native/nf-interpreter/src/HAL/nanoHAL_ConfigurationManager.c @@ -0,0 +1,181 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +uint32_t FindNextBlock(uint32_t startAddress, uint32_t endAddress, const unsigned char* marker) +{ + // all configuration markers are 4 bytes length + + unsigned char* cursor = (unsigned char*)startAddress; + + while(cursor < (unsigned char*)endAddress - 4) + { + if(memcmp(cursor, marker, 4 ) == 0) + { + // found one! + break; + } + + cursor++; + } + + return (uint32_t)cursor; +} + +uint32_t GetBlockCount(uint32_t startAddress, uint32_t endAddress, uint32_t blockSize, const unsigned char* marker) +{ + // all configuration markers are 4 bytes length + int blockCount = 0; + + unsigned char* cursor = (unsigned char*)startAddress; + + while(cursor < (unsigned char*)endAddress - 4) + { + if(memcmp(cursor, marker, 4 ) == 0) + { + // found one! + blockCount++; + + // bump cursor to the end of the config block size + cursor +=blockSize; + } + else + { + cursor++; + } + } + + return blockCount; +} + +__nfweak void* ConfigurationManager_FindNetworkConfigurationBlocks(uint32_t startAddress, uint32_t endAddress) +{ + uint32_t nextBlock = startAddress; + + // first pass: find out how many blocks of this type we have + uint32_t blockCount = GetBlockCount(startAddress, endAddress, sizeof(HAL_Configuration_NetworkInterface), c_MARKER_CONFIGURATION_NETWORK_V1); + + // allocate config struct + HAL_CONFIGURATION_NETWORK *networkConfigs = (HAL_CONFIGURATION_NETWORK *)platform_malloc(offsetof(HAL_CONFIGURATION_NETWORK, Configs) + blockCount * sizeof(networkConfigs->Configs[0])); + + // set collection count + networkConfigs->Count = blockCount; + + if(blockCount > 0) + { + + // second pass: get address of each config block + for(uint32_t i = 0; i < blockCount; i++) + { + nextBlock = FindNextBlock(nextBlock, endAddress, c_MARKER_CONFIGURATION_NETWORK_V1); + networkConfigs->Configs[i] = (HAL_Configuration_NetworkInterface*)nextBlock; + } + } + + return networkConfigs; +} + +__nfweak void* ConfigurationManager_FindNetworkWireless80211ConfigurationBlocks(uint32_t startAddress, uint32_t endAddress) +{ + uint32_t nextBlock = startAddress; + + // first pass: find out how many blocks of this type we have + uint32_t blockCount = GetBlockCount(startAddress, endAddress, sizeof(HAL_Configuration_Wireless80211), c_MARKER_CONFIGURATION_WIRELESS80211_V1); + + // allocate config struct + HAL_CONFIGURATION_NETWORK_WIRELESS80211 *networkWirelessConfigs = (HAL_CONFIGURATION_NETWORK_WIRELESS80211 *)platform_malloc(offsetof(HAL_CONFIGURATION_NETWORK_WIRELESS80211, Configs) + blockCount * sizeof(networkWirelessConfigs->Configs[0])); + + // set collection count + networkWirelessConfigs->Count = blockCount; + + if(blockCount > 0) + { + // second pass: get address of each config block + for(uint32_t i = 0; i < blockCount; i++) + { + nextBlock = FindNextBlock(nextBlock, endAddress, c_MARKER_CONFIGURATION_WIRELESS80211_V1); + networkWirelessConfigs->Configs[i] = (HAL_Configuration_Wireless80211*)nextBlock; + } + } + + return networkWirelessConfigs; +} + +__nfweak void* ConfigurationManager_FindX509CertificateConfigurationBlocks(uint32_t startAddress, uint32_t endAddress) +{ + uint32_t nextBlock = startAddress; + uint32_t allocationSize = 0; + + // first pass: find out how many blocks of this type we have + // because these blocks have an unknow size, need to call this without a fixed size + uint32_t blockCount = GetBlockCount(startAddress, endAddress, 1, c_MARKER_CONFIGURATION_X509CAROOTBUNDLE_V1); + + // start computing allocation size, first part is the struct initial fields + allocationSize = offsetof(HAL_CONFIGURATION_X509_CERTIFICATE, Certificates); + + // second pass: find out the size of each X509 certificate (because they can have different sizes and we need this to allocate memory for the struct) + if(blockCount > 0) + { + for(uint32_t i = 0; i < blockCount; i++) + { + nextBlock = FindNextBlock(nextBlock, endAddress, c_MARKER_CONFIGURATION_X509CAROOTBUNDLE_V1); + + // header + allocationSize += offsetof(HAL_Configuration_X509CaRootBundle, Certificate); + + // certificate + allocationSize += ((HAL_Configuration_X509CaRootBundle*)nextBlock)->CertificateSize; + } + } + + // allocate config struct + HAL_CONFIGURATION_X509_CERTIFICATE *certificateStore = (HAL_CONFIGURATION_X509_CERTIFICATE *)platform_malloc(allocationSize); + + // set collection count + certificateStore->Count = blockCount; + + if(blockCount > 0) + { + // second pass: get address of each config block + for(uint32_t i = 0; i < blockCount; i++) + { + nextBlock = FindNextBlock(nextBlock, endAddress, c_MARKER_CONFIGURATION_X509CAROOTBUNDLE_V1); + certificateStore->Certificates[i] = (HAL_Configuration_X509CaRootBundle*)nextBlock; + } + } + + return certificateStore; +} + +__nfweak HAL_Configuration_Wireless80211* ConfigurationManager_GetWirelessConfigurationFromId(uint32_t configurationId) +{ + for(int i = 0; i < g_TargetConfiguration.Wireless80211Configs->Count; i++) + { + if(g_TargetConfiguration.Wireless80211Configs->Configs[i]->Id == configurationId) + { + return g_TargetConfiguration.Wireless80211Configs->Configs[i]; + } + } + + // not found + return NULL; +} + +__nfweak HAL_Configuration_WirelessAP* ConfigurationManager_GetWirelessAPConfigurationFromId(uint32_t configurationId) +{ + for(int i = 0; i < g_TargetConfiguration.WirelessAPConfigs->Count; i++) + { + if(g_TargetConfiguration.WirelessAPConfigs->Configs[i]->Id == configurationId) + { + return g_TargetConfiguration.WirelessAPConfigs->Configs[i]; + } + } + + // not found + return NULL; +} diff --git a/source/native/nf-interpreter/src/HAL/nanoHAL_ConfigurationManager_stubs.c b/source/native/nf-interpreter/src/HAL/nanoHAL_ConfigurationManager_stubs.c new file mode 100644 index 00000000..95ee4c42 --- /dev/null +++ b/source/native/nf-interpreter/src/HAL/nanoHAL_ConfigurationManager_stubs.c @@ -0,0 +1,49 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +__nfweak void ConfigurationManager_Initialize() +{ +}; + +__nfweak void* ConfigurationManager_FindNetworkConfigurationBlocks(uint32_t startAddress, uint32_t endAddress) +{ + (void)startAddress; + (void)endAddress; + + return NULL; +} + +__nfweak void* ConfigurationManager_FindNetworkWireless80211ConfigurationBlocks(uint32_t startAddress, uint32_t endAddress) +{ + (void)startAddress; + (void)endAddress; + + return NULL; +} + +__nfweak void* ConfigurationManager_FindX509CertificateConfigurationBlocks(uint32_t startAddress, uint32_t endAddress) +{ + (void)startAddress; + (void)endAddress; + + return NULL; +} + +__nfweak HAL_Configuration_Wireless80211* ConfigurationManager_GetWirelessConfigurationFromId(uint32_t configurationId) +{ + (void)configurationId; + + return NULL; +} + +__nfweak HAL_Configuration_WirelessAP* ConfigurationManager_GetWirelessAPConfigurationFromId(uint32_t configurationId) +{ + (void)configurationId; + + return NULL; +} diff --git a/source/native/nf-interpreter/src/HAL/nanoHAL_SystemInformation.cpp b/source/native/nf-interpreter/src/HAL/nanoHAL_SystemInformation.cpp new file mode 100644 index 00000000..9abae44d --- /dev/null +++ b/source/native/nf-interpreter/src/HAL/nanoHAL_SystemInformation.cpp @@ -0,0 +1,60 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include + +bool GetHalSystemInfo(HalSystemInfo& systemInfo) +{ +#if defined(HAL_REDUCESIZE) + // No config update. + return FALSE; +#else + + // NFReleaseInfo: + systemInfo.m_releaseInfo.Version.usMajor = VERSION_MAJOR; + systemInfo.m_releaseInfo.Version.usMinor = VERSION_MINOR; + systemInfo.m_releaseInfo.Version.usBuild = VERSION_BUILD; + systemInfo.m_releaseInfo.Version.usRevision = VERSION_REVISION; + + size_t len = sizeof(systemInfo.m_releaseInfo.InfoString); + hal_strncpy_s ((char*)&systemInfo.m_releaseInfo.InfoString[0], len, OEMSYSTEMINFOSTRING, len-1 ); + + len = sizeof(systemInfo.m_releaseInfo.PlatformName); + hal_strncpy_s ((char*)&systemInfo.m_releaseInfo.PlatformName[0], len, TARGETNAMESTRING, len-1 ); + + len = sizeof(systemInfo.m_releaseInfo.TargetName); + hal_strncpy_s ((char*)&systemInfo.m_releaseInfo.TargetName[0], len, PLATFORMNAMESTRING, len-1 ); + + // we are not supporting this at this time + // OEM_MODEL_SKU: + //memcpy((void*)&(systemInfo.m_OemModelInfo), (void*)&(g_ConfigurationSector.OEM_Model_SKU), sizeof(OEM_MODEL_SKU)); + + // we are not supporting this at this time + // OEM_SERIAL_NUMBERS: + //memcpy((void*)&(systemInfo.m_OemSerialNumbers), (void*)&(g_ConfigurationSector.OemSerialNumbers), sizeof(OEM_SERIAL_NUMBERS)); + + return TRUE; +#endif +} + +bool Target_GetReleaseInfo(NFReleaseInfo& releaseInfo) +{ + NFReleaseInfo::Init( + releaseInfo, + VERSION_MAJOR, + VERSION_MINOR, + VERSION_BUILD, + VERSION_REVISION, + OEMSYSTEMINFOSTRING, + hal_strlen_s(OEMSYSTEMINFOSTRING), + TARGETNAMESTRING, + hal_strlen_s(TARGETNAMESTRING), + PLATFORMNAMESTRING, + hal_strlen_s(PLATFORMNAMESTRING) + ); + return TRUE; // alternatively, return false if you didn't initialize the releaseInfo structure. +} diff --git a/source/native/nf-interpreter/src/HAL/nanoHAL_Time.cpp b/source/native/nf-interpreter/src/HAL/nanoHAL_Time.cpp new file mode 100644 index 00000000..459b2893 --- /dev/null +++ b/source/native/nf-interpreter/src/HAL/nanoHAL_Time.cpp @@ -0,0 +1,96 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include + +const int CummulativeDaysForMonth[13] = {0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334, 365}; +const int DaysInMonth[12] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; + +#define IS_LEAP_YEAR(y) (((y % 4 == 0) && (y % 100 != 0)) || (y % 400 == 0)) +#define NUMBER_OF_LEAP_YEARS(y) ((((y - 1) / 4) - ((y - 1) / 100) + ((y - 1) / 400)) - BASE_YEAR_LEAPYEAR_ADJUST) /// Number of leap years until base year, not including the target year itself. +#define NUMBER_OF_YEARS(y) (y - BASE_YEAR) + +#define YEARS_TO_DAYS(y) ((NUMBER_OF_YEARS(y) * DAYS_IN_NORMAL_YEAR) + NUMBER_OF_LEAP_YEARS(y)) +#define MONTH_TO_DAYS(y, m) (CummulativeDaysForMonth[m - 1] + ((IS_LEAP_YEAR(y) && (m > 2)) ? 1 : 0)) +#define DAYS_IN_MONTH(y, m) (DaysInMonth[m - 1] + ((IS_LEAP_YEAR(y) && (m == 2)) ? 1 : 0)) + +#define TIMEUNIT_TO_MINUTES 600000000 +#define TIMEUNIT_TO_MILLISECONDS 10000 +#define MILLISECONDS_TO_SECONDS 1000 +#define SECONDS_TO_MINUTES 60 +#define MINUTES_TO_HOUR 60 +#define HOURS_TO_DAY 24 + +uint64_t HAL_Time_CurrentTime() +{ + return HAL_Time_SysTicksToTime( HAL_Time_CurrentSysTicks() ); +}; + +/// +/// Converts a SYSTEMTIME value to HAL time value +/// +uint64_t HAL_Time_ConvertFromSystemTime(const SYSTEMTIME* systemTime) +{ + uint64_t r = YEARS_TO_DAYS(systemTime->wYear) + MONTH_TO_DAYS(systemTime->wYear, systemTime->wMonth) + systemTime->wDay - 1; + r = (((( (r * HOURS_TO_DAY) + systemTime->wHour) * MINUTES_TO_HOUR + systemTime->wMinute) * SECONDS_TO_MINUTES + systemTime->wSecond ) * MILLISECONDS_TO_SECONDS + systemTime->wMilliseconds) * TIMEUNIT_TO_MILLISECONDS; + + return r; +} + +bool HAL_Time_ToSystemTime(uint64_t time, SYSTEMTIME* systemTime) +{ + uint32_t ytd = 0; + uint32_t mtd = 0; + + time /= TIMEUNIT_TO_MILLISECONDS; + systemTime->wMilliseconds = time % MILLISECONDS_TO_SECONDS; + time /= MILLISECONDS_TO_SECONDS; + systemTime->wSecond = time % SECONDS_TO_MINUTES; + time /= SECONDS_TO_MINUTES; + systemTime->wMinute = time % MINUTES_TO_HOUR; + time /= MINUTES_TO_HOUR; + systemTime->wHour = time % HOURS_TO_DAY; + time /= HOURS_TO_DAY; + + systemTime->wDayOfWeek = (time + BASE_YEAR_DAYOFWEEK_SHIFT) % 7; + systemTime->wYear = (unsigned short)(time / DAYS_IN_NORMAL_YEAR + BASE_YEAR); + ytd = YEARS_TO_DAYS(systemTime->wYear); + if (ytd > time) + { + systemTime->wYear--; + ytd = YEARS_TO_DAYS(systemTime->wYear); + } + + time -= ytd; + + systemTime->wMonth = (unsigned short)(time / 31 + 1); + mtd = MONTH_TO_DAYS(systemTime->wYear, systemTime->wMonth + 1); + + if (time >= mtd) + { + systemTime->wMonth++; + } + + mtd = MONTH_TO_DAYS(systemTime->wYear, systemTime->wMonth); + + systemTime->wDay = (unsigned short)(time - mtd + 1); + + return true; +} + +HRESULT HAL_Time_AccDaysInMonth(signed int year, signed int month, signed int* days) +{ + *days = MONTH_TO_DAYS(year, month); + + return S_OK; +} + +HRESULT HAL_Time_DaysInMonth(signed int year, signed int month, signed int* days) +{ + *days = DAYS_IN_MONTH(year, month); + + return S_OK; +} diff --git a/source/native/nf-interpreter/src/HAL/nanoHAL_Watchdog.c b/source/native/nf-interpreter/src/HAL/nanoHAL_Watchdog.c new file mode 100644 index 00000000..5cdebcaa --- /dev/null +++ b/source/native/nf-interpreter/src/HAL/nanoHAL_Watchdog.c @@ -0,0 +1,23 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include + +/** +* Method to initialize the watchdog. Watchdog must be initialized +* only once (when the system starts, generally in main after system and HAL initialization). +*/ +__nfweak void Watchdog_Init(){} + + +/** + * Reset the watchdog. If not done within the timout period, + * the watchdog will trigger and MCU will reset. Specific implementation + * must provide required thread-safety (e.g. whether called from thread or an + * ISR, reentrant/non-reentrant) + */ +__nfweak void Watchdog_Reset(){} + diff --git a/source/native/nf-interpreter/src/PAL/AsyncProcCall/AsyncCompletions.cpp b/source/native/nf-interpreter/src/PAL/AsyncProcCall/AsyncCompletions.cpp new file mode 100644 index 00000000..29543a29 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/AsyncProcCall/AsyncCompletions.cpp @@ -0,0 +1,239 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "stdafx.h" + +#include + +HAL_DblLinkedList g_HAL_Completion_List; + +/***************************************************************************/ + +void HAL_COMPLETION::Execute() +{ + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); + +#if defined(_DEBUG) + this->Start_RTC_Ticks = 0; +#endif + + if (this->ExecuteInISR) + { + HAL_CONTINUATION* cont = this; + + cont->Execute(); + } + else + { + this->Enqueue(); + } +} + +//--// + +void HAL_COMPLETION::InitializeList() +{ + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); + g_HAL_Completion_List.Initialize(); +} + +//--// + +void HAL_COMPLETION::DequeueAndExec() +{ + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); + + GLOBAL_LOCK(); + + HAL_COMPLETION* ptr = (HAL_COMPLETION*)g_HAL_Completion_List.FirstNode(); + + // waitforevents does not have an associated completion, therefore we need to verify + // than their is a next completion and that the current one has expired. + if (ptr->Next()) + { + // Current one expired ? + if (HAL_Time_CurrentTime() >= ptr->EventTimeTicks) + { + Events_Set(SYSTEM_EVENT_FLAG_SYSTEM_TIMER); + + ptr->Unlink(); + +#if defined(_DEBUG) + ptr->EventTimeTicks = 0; +#endif // defined(_DEBUG) + + //// let the ISR turn on interrupts, if it needs to + ptr->Execute(); + } + + // + // Set the next timer to run otherwise set the next interrupt to be 356 years since last powerup (@25kHz). + Time_SetCompare(ptr->Next() ? ptr->EventTimeTicks : HAL_COMPLETION_IDLE_VALUE); + } + + GLOBAL_UNLOCK(); +} + +//--// + +void HAL_COMPLETION::EnqueueTicks(uint64_t eventTimeTicks) +{ + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); + ASSERT(eventTimeTicks != 0); + + this->EventTimeTicks = eventTimeTicks; + +#if defined(_DEBUG) + this->Start_RTC_Ticks = HAL_Time_CurrentSysTicks(); +#endif + + GLOBAL_LOCK(); + + HAL_COMPLETION* ptr = (HAL_COMPLETION*)g_HAL_Completion_List.FirstNode(); + HAL_COMPLETION* ptrNext; + + // If not empty list the find position in Completion list based on time + // If empty just add at head. + if (!g_HAL_Completion_List.IsEmpty()) + { + do + { + ptrNext = (HAL_COMPLETION *)ptr->Next(); + + if (eventTimeTicks < ptr->EventTimeTicks) + { + break; + } + + ptr = ptrNext; + } while (ptr); + } + + g_HAL_Completion_List.InsertBeforeNode(ptr, this); + + if (this == g_HAL_Completion_List.FirstNode()) + { + Time_SetCompare(eventTimeTicks); + } + + GLOBAL_UNLOCK(); +} + +//--// + +void HAL_COMPLETION::Abort() +{ + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); + + GLOBAL_LOCK(); + + HAL_COMPLETION* firstNode = (HAL_COMPLETION*)g_HAL_Completion_List.FirstNode(); + + this->Unlink(); + +#if defined(_DEBUG) + this->Start_RTC_Ticks = 0; +#endif + + if (firstNode == this) + { + uint64_t nextTicks; + + if (g_HAL_Completion_List.IsEmpty()) + { + // + // In case there's no other request to serve, set the next interrupt to be 356 years since last powerup (@25kHz). + // + nextTicks = HAL_COMPLETION_IDLE_VALUE; + } + else + { + firstNode = (HAL_COMPLETION*)g_HAL_Completion_List.FirstNode(); + + nextTicks = firstNode->EventTimeTicks; + } + + Time_SetCompare(nextTicks); + } + + GLOBAL_UNLOCK(); +} + +//--// + + +// +// WaitForInterrupts for expireTimeInTicks time +// +// Interrupts should be disabled +// +void HAL_COMPLETION::WaitForInterrupts(uint64_t expireTimeInTicks, uint32_t sleepLevel, uint64_t wakeEvents) +{ + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); + + const int setCompare = 1; + const int resetCompare = 2; + const int nilCompare = 4; + + HAL_COMPLETION* ptr = (HAL_COMPLETION*)g_HAL_Completion_List.FirstNode(); + int state; + + // Any Completion events been Queued ? + if (ptr->Next() == NULL) + { + // No + state = setCompare | nilCompare; + } + // Is Queued event later than passed expire timeout + else if (ptr->EventTimeTicks > expireTimeInTicks) + { + // Yes + state = setCompare | resetCompare; + } + else + { + state = 0; + } + + if (state & setCompare) + { + // Set timer for expireTimeInTicks time + Time_SetCompare(expireTimeInTicks); + } + + // Wait for next interrupt ( timer etc) + CPU_Sleep((SLEEP_LEVEL_type)sleepLevel, wakeEvents); + + if (state & (resetCompare | nilCompare)) + { + // let's get the first node again + // it could have changed since CPU_Sleep re-enabled interrupts + ptr = (HAL_COMPLETION*)g_HAL_Completion_List.FirstNode(); + Time_SetCompare((state & resetCompare) ? ptr->EventTimeTicks : HAL_COMPLETION_IDLE_VALUE); + } +} + +void HAL_COMPLETION::Uninitialize() +{ + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); + + HAL_COMPLETION* ptr; + + GLOBAL_LOCK(); + + while (TRUE) + { + ptr = (HAL_COMPLETION*)g_HAL_Completion_List.ExtractFirstNode(); + + if (!ptr) + { + break; + } + + } + + GLOBAL_UNLOCK(); +} diff --git a/source/native/nf-interpreter/src/PAL/AsyncProcCall/AsyncContinuations.cpp b/source/native/nf-interpreter/src/PAL/AsyncProcCall/AsyncContinuations.cpp new file mode 100644 index 00000000..9cde8e37 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/AsyncProcCall/AsyncContinuations.cpp @@ -0,0 +1,107 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "stdafx.h" +#include + +HAL_DblLinkedList g_HAL_Continuation_List; +extern HAL_DblLinkedList g_HAL_Completion_List; + +//--// + +bool HAL_CONTINUATION::IsLinked() +{ + return ((HAL_DblLinkedNode*)this)->IsLinked(); +} + +void HAL_CONTINUATION::InitializeList() +{ + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); + g_HAL_Continuation_List.Initialize(); +} + +void HAL_CONTINUATION::Enqueue() +{ + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); + if(this->GetEntryPoint() != NULL) + { + GLOBAL_LOCK(); + + g_HAL_Continuation_List.LinkAtBack( this ); + + GLOBAL_UNLOCK(); + } +} + +void HAL_CONTINUATION::Abort() +{ + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); + GLOBAL_LOCK(); + + this->Unlink(); + + GLOBAL_UNLOCK(); +} + +bool HAL_CONTINUATION::Dequeue_And_Execute() +{ + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); + + // use this as the return value + // helpfull to make the call to release the global mutext happens + bool result; + + GLOBAL_LOCK(); + HAL_CONTINUATION* ptr = g_HAL_Continuation_List.ExtractFirstNode(); + GLOBAL_UNLOCK(); + + if(ptr == NULL ) + { + result = false; + } + else + { + //SystemState_SetNoLock( SYSTEM_STATE_NO_CONTINUATIONS ); + + HAL_CALLBACK call = ptr->Callback; + + call.Execute(); + + //SystemState_ClearNoLock( SYSTEM_STATE_NO_CONTINUATIONS ); // nestable + + result = true; + } + + return result; +} + +void HAL_CONTINUATION::InitializeCallback( HAL_CALLBACK_FPN entryPoint, void* argument ) +{ + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); + Initialize(); + + Callback.Initialize( entryPoint, argument ); +} + +void HAL_CONTINUATION::Uninitialize() +{ + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); + GLOBAL_LOCK(); + + HAL_CONTINUATION* ptr; + + while(TRUE) + { + ptr = (HAL_CONTINUATION*)g_HAL_Continuation_List.ExtractFirstNode(); + + if(!ptr) + { + break; + } + } + + GLOBAL_UNLOCK(); +} diff --git a/source/native/nf-interpreter/src/PAL/AsyncProcCall/Async_stubs.cpp b/source/native/nf-interpreter/src/PAL/AsyncProcCall/Async_stubs.cpp new file mode 100644 index 00000000..a620e97c --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/AsyncProcCall/Async_stubs.cpp @@ -0,0 +1,101 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include + +//--// + +// continuation list +__nfweak void HAL_CONTINUATION::InitializeList() +{ + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); +} + +__nfweak void HAL_CONTINUATION::Uninitialize() +{ + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); +} + +__nfweak void HAL_CONTINUATION::InitializeCallback( HAL_CALLBACK_FPN entryPoint, void* argument ) +{ + (void)entryPoint; + (void)argument; + + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); +} + +__nfweak void HAL_CONTINUATION::Enqueue() +{ + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); +} + +__nfweak void HAL_CONTINUATION::Abort () +{ + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); +} + +__nfweak bool HAL_CONTINUATION::Dequeue_And_Execute() +{ + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); + return TRUE; +} + +__nfweak bool HAL_CONTINUATION::IsLinked() +{ + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); + return false; +} + +//-// +// completion list + +__nfweak void HAL_COMPLETION::InitializeList() +{ + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); +} + +__nfweak void HAL_COMPLETION::Uninitialize() +{ + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); +} + +__nfweak void HAL_COMPLETION::EnqueueTicks( uint64_t eventTimeTicks) +{ + (void)eventTimeTicks; + + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); +} + +__nfweak void HAL_COMPLETION::EnqueueDelta( uint32_t uSecFromNow ) +{ + (void)uSecFromNow; + + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); +} + +__nfweak void HAL_COMPLETION::Abort() +{ + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); +} + +__nfweak void HAL_COMPLETION::Execute() +{ + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); +} + +__nfweak void HAL_COMPLETION::DequeueAndExec() +{ + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); +} + +__nfweak void HAL_COMPLETION::WaitForInterrupts( uint64_t expireTimeInSysTicks, uint32_t sleepLevel, uint64_t wakeEvents ) +{ + (void)expireTimeInSysTicks; + (void)sleepLevel; + (void)wakeEvents; + + NATIVE_PROFILE_PAL_ASYNC_PROC_CALL(); +} diff --git a/source/native/nf-interpreter/src/PAL/BlockStorage/nanoPAL_BlockStorage.c b/source/native/nf-interpreter/src/PAL/BlockStorage/nanoPAL_BlockStorage.c new file mode 100644 index 00000000..be3122c8 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/BlockStorage/nanoPAL_BlockStorage.c @@ -0,0 +1,890 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +BlockStorageList g_BlockStorage; + + +///////////////////////////////////////////////////// +// DeviceBlockInfo stubs + +SectorAddress DeviceBlockInfo_PhysicalToSectorAddress(DeviceBlockInfo* blockInfo, const BlockRegionInfo* pRegion, ByteAddress phyAddress) +{ + return (phyAddress - pRegion->Start) / blockInfo->BytesPerSector; +} + +bool DeviceBlockInfo_FindRegionFromAddress(DeviceBlockInfo* blockInfo, ByteAddress address, unsigned int* blockRegionIndex, unsigned int* blockRangeIndex) +{ + const BlockRegionInfo *pRegion; + + *blockRegionIndex = 0; + + for(uint32_t i = 0; i < blockInfo->NumRegions; i++) + { + pRegion = &blockInfo->Regions[i]; + + if(pRegion->Start <= address && address < (pRegion->Start + pRegion->NumBlocks * pRegion->BytesPerBlock)) + { + uint32_t endRangeAddr = pRegion->Start + pRegion->BytesPerBlock * pRegion->BlockRanges[0].StartBlock; + + for(uint32_t j =0; j < pRegion->NumBlockRanges; j++) + { + endRangeAddr += pRegion->BytesPerBlock * BlockRange_GetBlockCount(pRegion->BlockRanges[j]); + + if(address < endRangeAddr) + { + *blockRegionIndex = i; + *blockRangeIndex = j; + return true; + } + } + } + } + + return false; +} + +bool DeviceBlockInfo_FindNextUsageBlock(DeviceBlockInfo* blockInfo, unsigned int blockUsage, unsigned int* address, unsigned int* blockRegionIndex, unsigned int* blockRangeIndex) +{ + BlockRegionInfo *region; + + for(uint32_t i = *blockRegionIndex; i < blockInfo->NumRegions; i++) + { + region = &blockInfo->Regions[i]; + + for( int j = *blockRangeIndex; j < (int)region->NumBlockRanges; j++) + { + BlockRange *pRange = (BlockRange*)®ion->BlockRanges[j]; + + if ((pRange->RangeType & BlockRange_USAGE_MASK) == blockUsage || blockUsage == BlockUsage_ANY) + { + *address = BlockRegionInfo_BlockAddress(region, pRange->StartBlock); + *blockRegionIndex = i; + *blockRangeIndex = j; + + return true; + } + } + + *blockRangeIndex = 0; + } + + return false; +} + +bool DeviceBlockInfo_FindForBlockUsage(DeviceBlockInfo* blockInfo, unsigned int blockUsage, unsigned int* address, unsigned int* blockRegionIndex, unsigned int* blockRangeIndex) +{ + (void)blockInfo; + (void)blockUsage; + + address = 0; + blockRegionIndex = 0; + blockRangeIndex = 0; + + return DeviceBlockInfo_FindNextUsageBlock(blockInfo, blockUsage, address, blockRegionIndex, blockRangeIndex ); +} + + +///////////////////////////////////////////////////// +// BlockStorageStream stubs + +bool BlockStorageStream_IsXIP(BlockStorageStream *stream) +{ + (void)stream; + + return false; +} + +bool BlockStorageStream_IsReadModifyWrite(BlockStorageStream *stream) +{ + (void)stream; + + return false; +} + +bool BlockStorageStream_SetReadModifyWrite(BlockStorageStream *stream) +{ + (void)stream; + + return false; +} + +bool BlockStorageStream_Initialize(BlockStorageStream *stream, unsigned int blockUsage) +{ + return BlockStorageStream_InitializeWithBlockStorageDevice(stream, blockUsage, NULL); +} + +bool BlockStorageStream_InitializeWithBlockStorageDevice(BlockStorageStream *stream, unsigned int blockUsage, BlockStorageDevice *pDevice) +{ + DeviceBlockInfo* deviceInfo = NULL; + BlockStorageStream backupStream; + BlockStorageDevice *device = NULL; + + // backup original stream, in case this gets messed up + memcpy(&backupStream, stream, sizeof(BlockStorageStream)); + + if(pDevice != NULL) + { + device = pDevice; + + deviceInfo = BlockStorageDevice_GetDeviceInfo(pDevice); + } + else + { + for(int i = 0; i < TARGET_BLOCKSTORAGE_COUNT; i++) + { + device = g_BlockStorage.DeviceList[i]; + + deviceInfo = BlockStorageDevice_GetDeviceInfo(g_BlockStorage.DeviceList[i]); + + if(DeviceBlockInfo_FindNextUsageBlock(deviceInfo, blockUsage, &stream->BaseAddress, &stream->RegionIndex, &stream->RangeIndex)) + { + // found a block matching the request usage + break; + } + else + { + // couldn't find a block matching the request usage + // need to NULL the device info that's going to be used to fill in the stream details + deviceInfo = NULL; + } + } + } + + if(deviceInfo != NULL) + { + BlockRegionInfo* pRegion = &deviceInfo->Regions[stream->RegionIndex]; + + stream->CurrentIndex = 0; + stream->Length = BlockRange_GetBlockCount(pRegion->BlockRanges[stream->RangeIndex])* pRegion->BytesPerBlock; + stream->BlockLength = pRegion->BytesPerBlock; + stream->CurrentUsage = (pRegion->BlockRanges[stream->RangeIndex].RangeType & BlockRange_USAGE_MASK); + stream->Device = device; + + if(deviceInfo->Attribute & MediaAttribute_SupportsXIP) + { + stream->Flags |= BLOCKSTORAGESTREAM_c_BlockStorageStream__XIP; + } + else + { + stream->Flags &= ~BLOCKSTORAGESTREAM_c_BlockStorageStream__XIP; + } + + // check if block region is memory mapped + if(pRegion->Attributes & BlockRegionAttribute_MemoryMapped) + { + BlockStorageDevice_GetMemoryMappedAddress(device, stream->RegionIndex, stream->RangeIndex, &stream->MemoryMappedAddress); + + stream->Flags |= BLOCKSTORAGESTREAM_c_BlockStorageStream__MemoryMapped; + } + else + { + stream->Flags &= ~BLOCKSTORAGESTREAM_c_BlockStorageStream__MemoryMapped; + } + + // done here + return true; + } + + // couldn't find a device for the requested usage, revert stream from backup + memcpy(stream, &backupStream, sizeof(BlockStorageStream)); + + return false; +} + +bool BlockStorageStream_NextStream(BlockStorageStream* stream) +{ + if(stream->Device == NULL || BlockStorageDevice_Prev(stream->Device) == NULL) return false; + + const BlockRegionInfo* pRegion; + const DeviceBlockInfo* deviceInfo = BlockStorageDevice_GetDeviceInfo(stream->Device); + + BlockStorageStream orig; + + memcpy(&orig, stream, sizeof(orig)); + + do + { + bool fLastIndex = false; + + if(stream->RangeIndex == 0) + { + if(stream->RegionIndex == 0) + { + stream->Device = BlockStorageDevice_Prev(stream->Device); + + if(stream->Device == NULL || BlockStorageDevice_Prev(stream->Device) == NULL) + { + memcpy(stream, &orig, sizeof(orig)); + return false; + } + + deviceInfo = BlockStorageDevice_GetDeviceInfo(stream->Device); + + stream->RegionIndex = deviceInfo->NumRegions - 1; + } + else + { + stream->RegionIndex--; + } + + fLastIndex = true; + } + else + { + stream->RangeIndex--; + } + + pRegion = &deviceInfo->Regions[stream->RegionIndex]; + + if(fLastIndex) + { + stream->RangeIndex = pRegion->NumBlockRanges - 1; + } + + } while( BlockRange_GetBlockUsage(pRegion->BlockRanges[stream->RangeIndex]) != stream->Usage ); + + if(deviceInfo->Attribute & MediaAttribute_SupportsXIP) + { + stream->Flags |= BLOCKSTORAGESTREAM_c_BlockStorageStream__XIP; + } + else + { + stream->Flags &= ~BLOCKSTORAGESTREAM_c_BlockStorageStream__XIP; + } + + stream->BlockLength = pRegion->BytesPerBlock; + stream->BaseAddress = pRegion->Start + pRegion->BlockRanges[stream->RangeIndex].StartBlock * stream->BlockLength; + stream->Length = BlockRange_GetBlockCount(pRegion->BlockRanges[stream->RangeIndex]) * stream->BlockLength; + stream->CurrentIndex = 0; + + return true; +} + +bool BlockStorageStream_PrevStream(BlockStorageStream* stream) +{ + if(stream->Device == NULL || BlockStorageDevice_Prev(stream->Device) == NULL) return false; + + const BlockRegionInfo* pRegion; + const DeviceBlockInfo* deviceInfo = BlockStorageDevice_GetDeviceInfo(stream->Device); + + BlockStorageStream orig; + + memcpy(&orig, stream, sizeof(orig)); + + do + { + bool fLastIndex = false; + + if(stream->RangeIndex == 0) + { + if(stream->RegionIndex == 0) + { + stream->Device = BlockStorageDevice_Prev(stream->Device); + + if(stream->Device == NULL || BlockStorageDevice_Prev(stream->Device) == NULL) + { + memcpy(stream, &orig, sizeof(orig)); + return false; + } + + deviceInfo = BlockStorageDevice_GetDeviceInfo(stream->Device); + + stream->RegionIndex = deviceInfo->NumRegions - 1; + } + else + { + stream->RegionIndex--; + } + + fLastIndex = true; + } + else + { + stream->RangeIndex--; + } + + pRegion = &deviceInfo->Regions[stream->RegionIndex]; + + if(fLastIndex) + { + stream->RangeIndex = pRegion->NumBlockRanges - 1; + } + + } while( BlockRange_GetBlockUsage(pRegion->BlockRanges[stream->RangeIndex]) != stream->Usage ); + + if(deviceInfo->Attribute & MediaAttribute_SupportsXIP) + { + stream->Flags |= BLOCKSTORAGESTREAM_c_BlockStorageStream__XIP; + } + else + { + stream->Flags &= ~BLOCKSTORAGESTREAM_c_BlockStorageStream__XIP; + } + + stream->BlockLength = pRegion->BytesPerBlock; + stream->BaseAddress = pRegion->Start + pRegion->BlockRanges[stream->RangeIndex].StartBlock * stream->BlockLength; + stream->Length = BlockRange_GetBlockCount(pRegion->BlockRanges[stream->RangeIndex]) * stream->BlockLength; + stream->CurrentIndex = 0; + + return true; +} + +bool BlockStorageStream_Seek(BlockStorageStream *stream, unsigned int offset, SeekOrigin origin) +{ + int32_t seekIndex; + + switch (origin) + { + case BlockStorageStream_SeekBegin: + seekIndex = 0; + break; + + case BlockStorageStream_SeekCurrent: + seekIndex = stream->CurrentIndex; + break; + + case BlockStorageStream_SeekEnd: + seekIndex = stream->Length; + break; + + default: + + return false; + } + + seekIndex += offset; + + while (seekIndex >= (int32_t)stream->Length) + { + // out of region address space + return false; + } + + while (seekIndex < 0) + { + // out of region address space + return false; + } + + stream->CurrentIndex = seekIndex; + + return true; +} + +bool BlockStorageStream_Write(BlockStorageStream *stream, unsigned char *data, unsigned int length) +{ + (void)stream; + (void)data; + (void)length; + + return false; +} + +bool BlockStorageStream_Erase(BlockStorageStream *stream, unsigned int length) +{ + (void)stream; + (void)length; + + return false; +} + +bool BlockStorageStream_ReadIntoBuffer(BlockStorageStream *stream, unsigned char *buffer, unsigned int length) +{ + (void)stream; + (void)buffer; + (void)length; + + return false; +} + +bool BlockStorageStream_Read(BlockStorageStream* stream, unsigned char** buffer, unsigned int length) +{ + if(stream == NULL || stream->Device == NULL || buffer == 0) + { + return false; + } + + DeviceBlockInfo* deviceInfo = BlockStorageDevice_GetDeviceInfo(stream->Device); + unsigned char* pBuffer = *buffer; + + while(length > 0) + { + int readLen = length; + + // find the next stream if we are at the end of this one + if(stream->CurrentIndex == stream->Length) + { + // TODO FIXME + // need to check implementation of this call to get pointers to stream continuation + //if(!NextStream()) return FALSE; + } + + if((stream->CurrentIndex + readLen) > stream->Length) + { + readLen = stream->Length - stream->CurrentIndex; + } + + if(deviceInfo->Attribute & MediaAttribute_SupportsXIP) + { + // XIP assumes contiguous USAGE blocks + *buffer = (unsigned char*)(BlockStorageStream_CurrentAddress(stream)); + } + else + { + // non XIP storage... + + if(stream->Flags & BLOCKSTORAGESTREAM_c_BlockStorageStream__MemoryMapped) + { + // memory mapped region, get mapped address for read + *buffer = (unsigned char*)(BlockStorageStream_CurrentMappedAddress(stream)); + } + else + { + // non mapped access... need to call driver + if(!stream->Device->m_BSD->Read(stream->Device->m_context, BlockStorageStream_CurrentAddress(stream), readLen, pBuffer)) + { + return false; + } + } + } + + length -= readLen; + pBuffer += readLen; + stream->CurrentIndex += readLen; + } + + return true; +} + +unsigned int BlockStorageStream_CurrentAddress(BlockStorageStream *stream) +{ + return stream->BaseAddress + stream->CurrentIndex; +} + +unsigned int BlockStorageStream_CurrentMappedAddress(BlockStorageStream *stream) +{ + return stream->MemoryMappedAddress + stream->CurrentIndex; +} + +bool BlockStorageStream_IsErased(BlockStorageStream *stream, unsigned int length) +{ + (void)stream; + (void)length; + + return false; +} + +///////////////////////////////////////////////////// +// BlockStorageDevice stubs + +BlockStorageDevice* BlockStorageDevice_Next(BlockStorageDevice* device) +{ + (void)device; + + return NULL; +} + +BlockStorageDevice* BlockStorageDevice_Prev(BlockStorageDevice* device) +{ + (void)device; + + return NULL; +} + +///////////////////////////////////////////////////////// +// Description: +// Initializes a given block device for use +// +// Returns: +// true if successful; false if not +// +// Remarks: +// No other functions in this interface may be called +// until after Init returns. +// +bool BlockStorageDevice_InitializeDevice(BlockStorageDevice* device) +{ + ASSERT(device != NULL); + ASSERT(device->m_context != NULL); + + return device->m_BSD->InitializeDevice(device->m_context); +} + +///////////////////////////////////////////////////////// +// Description: +// Initializes a given block device for use +// +// Returns: +// true if successful; false if not +// +// Remarks: +// De initializes the device when no longer needed +// +bool BlockStorageDevice_UninitializeDevice(BlockStorageDevice* device) +{ + ASSERT(device != NULL); + ASSERT(device->m_context != NULL); + + return device->m_BSD->UninitializeDevice(device->m_context); +} + +///////////////////////////////////////////////////////// +// Description: +// Gets the information describing the device +// +DeviceBlockInfo* BlockStorageDevice_GetDeviceInfo(BlockStorageDevice* device) +{ + ASSERT(device != NULL); + ASSERT(device->m_context != NULL); + + return device->m_BSD->GetDeviceInfo(device->m_context); +} + +///////////////////////////////////////////////////////// +// Description: +// Reads data from a set of sectors +// +// Input: +// startAddress - Starting Sector for the read +// numBytes - Number of sectors to read +// buffer - pointer to buffer to read the data into. +// Must be large enough to hold all of the data +// being read. +// +// pSectorMetadata - pointer to an array of structured (one for each sector) +// for the extra sector information. +// +// Returns: +// true if successful; false if not +// +// Remarks: +// This function reads the number of sectors specified from the device. +// +// pSectorBuff may be NULL. This is to allow for reading just the metadata. +// +// pSectorMetadata can be set to NULL if the caller does not need the extra +// data. +// +// If the device does not support sector Metadata it should fail if the +// pSectorMetadata parameter is not NULL. +// +bool BlockStorageDevice_Read(BlockStorageDevice* device, unsigned int startAddress, unsigned int numBytes, unsigned char* buffer) +{ + ASSERT(device != NULL); + ASSERT(device->m_context != NULL); + + return device->m_BSD->Read(device->m_context, startAddress, numBytes, buffer); +} + +///////////////////////////////////////////////////////// +// Description: +// Writes data to a set of sectors +// +// Input: +// startAddress - Starting Sector for the write +// numBytes - Number of sectors to write +// buffer - pointer to data to write. +// Must be large enough to hold complete sectors +// for the number of sectors being written. +// +// pSectorMetadata - pointer to an array of structures (one for each sector) +// for the extra sector information. +// +// Returns: +// true if successful; false if not +// +// Remarks: +// This function reads the number of sectors specified from the device. +// The SectorMetadata is used for flash arrays without special controllers +// to manage wear leveling etc... (mostly for NOR and NAND). The metadata +// is used by upper layers to ensure that data is moved around on the flash +// when writing to prevent failure of the device from too many erase cycles +// on a sector. +// +// If the device does not support sector Metadata it should fail if the +// pSectorMetadata parameter is not NULL. +// +// pSectorMetadata can be set to NULL if the caller does not need the extra +// data. Implementations must not attempt to write data through a NULL pointer! +// +bool BlockStorageDevice_Write(BlockStorageDevice* device, unsigned int startAddress, unsigned int numBytes, unsigned char* buffer, bool readModifyWrite) +{ + ASSERT(device != NULL); + ASSERT(device->m_context != NULL); + + return device->m_BSD->Write(device->m_context, startAddress, numBytes, buffer, readModifyWrite); +} + +bool BlockStorageDevice_Memset(BlockStorageDevice* device, unsigned int startAddress, unsigned char buffer, unsigned int numBytes) +{ + ASSERT(device != NULL); + ASSERT(device->m_context != NULL); + + return device->m_BSD->Memset(device->m_context, startAddress, buffer, numBytes); +} + +// bool BlockStorageDevice_GetSectorMetadata(BlockStorageDevice* device, unsigned int sectorStart, SectorMetadata* pSectorMetadata); +// bool BlockStorageDevice_SetSectorMetadata(BlockStorageDevice* device, unsigned int sectorStart, SectorMetadata* pSectorMetadata); + +///////////////////////////////////////////////////////// +// Description: +// Check a block is erased or not +// +// Input: +// Address - Logical Sector Address +// +// Returns: +// true it is erased; false if not +// +// Remarks: +// check the block containing the sector address specified. +// +bool BlockStorageDevice_IsBlockErased(BlockStorageDevice* device, unsigned int blockStartAddress, unsigned int length) +{ + ASSERT(device != NULL); + ASSERT(device->m_context != NULL); + + return device->m_BSD->IsBlockErased(device->m_context, blockStartAddress, length); +} + +///////////////////////////////////////////////////////// +// Description: +// Erases a block +// +// Input: +// Address - Logical Sector Address +// +// Returns: +// true if successful; false if not +// +// Remarks: +// Erases the block containing the sector address specified. +// +bool BlockStorageDevice_EraseBlock(BlockStorageDevice* device, unsigned int address) +{ + ASSERT(device != NULL); + ASSERT(device->m_context != NULL); + + return device->m_BSD->EraseBlock(device->m_context, address); +} + +///////////////////////////////////////////////////////// +// Description: +// Changes the power state of the device +// +// Input: +// state - true= power on; false = power off +// +// Remarks: +// This function allows systems to conserve power by +// shutting down the hardware when the system is +// going into low power states. +// +void BlockStorageDevice_SetPowerState(BlockStorageDevice* device, unsigned int state) +{ + ASSERT(device != NULL); + ASSERT(device->m_context != NULL); + + device->m_BSD->SetPowerState(device->m_context, state); +} + +bool BlockStorageDevice_FindRegionFromAddress(BlockStorageDevice* device, unsigned int address, unsigned int* blockRegionIndex, unsigned int* blockRangeIndex) +{ + ASSERT(device != NULL); + + DeviceBlockInfo* deviceInfo = BlockStorageDevice_GetDeviceInfo(device); + + return DeviceBlockInfo_FindRegionFromAddress(deviceInfo, address, blockRegionIndex, blockRangeIndex); +} + +bool BlockStorageDevice_FindForBlockUsage(BlockStorageDevice* device, unsigned int blockUsage, unsigned int* address, unsigned int* blockRegionIndex, unsigned int* blockRangeIndex) +{ + ASSERT(device != NULL); + + DeviceBlockInfo* deviceInfo = BlockStorageDevice_GetDeviceInfo(device); + + return DeviceBlockInfo_FindForBlockUsage(deviceInfo, blockUsage, address, blockRegionIndex, blockRangeIndex); +} + +bool BlockStorageDevice_FindNextUsageBlock(BlockStorageDevice* device, unsigned int blockUsage, unsigned int* address, unsigned int* blockRegionIndex, unsigned int* blockRangeIndex) +{ + ASSERT(device != NULL); + + DeviceBlockInfo* deviceInfo = BlockStorageDevice_GetDeviceInfo(device); + + return DeviceBlockInfo_FindNextUsageBlock(deviceInfo, blockUsage, address, blockRegionIndex, blockRangeIndex); +} + +bool BlockStorageDevice_GetMemoryMappedAddress(BlockStorageDevice* device, unsigned int blockRegionIndex, unsigned int blockRangeIndex, unsigned int* address) +{ + ASSERT(device != NULL); + ASSERT(device->m_context != NULL); + + return device->m_BSD->GetMemoryMappedAddress(device->m_context, blockRegionIndex, blockRangeIndex, address); +} + +/////////////////////////////////////////////////// +// BlockStorageList declarations + +// initialize the storage +void BlockStorageList_Initialize() +{ + for(int i = 0; i < TARGET_BLOCKSTORAGE_COUNT; i++) + { + g_BlockStorage.DeviceList[i] = NULL; + } + + g_BlockStorage.DeviceCount = 0; +} + +// walk through list of devices and calls Init() function +bool BlockStorageList_InitializeDevices() +{ + // TODO FIXME + return true; +} + +// walk through list of devices and calls UnInit() function +bool BlockStorageList_UnInitializeDevices() +{ + // TODO FIXME + return true; +} + +bool BlockStorageList_AddDevice(BlockStorageDevice* pBSD, IBlockStorageDevice* vtable, void* config, bool init) +{ + bool success = true; + + // find next empty device slot + for(int i = 0; i < TARGET_BLOCKSTORAGE_COUNT; i++) + { + if(g_BlockStorage.DeviceList[i] == NULL) + { + // found an empty slot + + // link the driver and context + pBSD->m_BSD = vtable; + pBSD->m_context = config; + + // call initialize device, if requested + if(init) + { + success = BlockStorageDevice_InitializeDevice(pBSD); + } + + // add device to list only init was successful + if(success) + { + // add the BSD + g_BlockStorage.DeviceList[i] = pBSD; + + g_BlockStorage.DeviceCount++; + + // done here + return true; + } + } + } + + return false; +} + +bool BlockStorageList_RemoveDevice(BlockStorageDevice* pBSD, bool unInit) +{ + // find device + for(int i = 0; i < TARGET_BLOCKSTORAGE_COUNT; i++) + { + if(g_BlockStorage.DeviceList[i] == pBSD) + { + // found it + + // call uninitialize device, if requested + if(unInit) + { + BlockStorageDevice_UninitializeDevice(pBSD); + } + + // remove device + g_BlockStorage.DeviceList[i] = NULL; + + // done here + return true; + } + } + + return false; +} + +bool BlockStorageList_FindDeviceForPhysicalAddress(BlockStorageDevice** pBSD, unsigned int physicalAddress, ByteAddress* blockAddress) +{ + *pBSD = NULL; + + BlockStorageDevice* block = BlockStorageList_GetFirstDevice(); + + // this has to add to make metadataprocessor happy + if(!block) return true; + + DeviceBlockInfo* pDeviceInfo = BlockStorageDevice_GetDeviceInfo(block); + + for(uint32_t i=0; i < pDeviceInfo->NumRegions; i++) + { + BlockRegionInfo* pRegion = &pDeviceInfo->Regions[i]; + + if(pRegion->Start <= physicalAddress && physicalAddress < (pRegion->Start + pRegion->NumBlocks * pRegion->BytesPerBlock)) + { + *pBSD = block; + + // get block start address + *blockAddress = (ByteAddress)((physicalAddress - pRegion->Start) / pRegion->BytesPerBlock); + *blockAddress *= pRegion->BytesPerBlock; + *blockAddress += pRegion->Start; + + return true; + } + } + + return false; +} + +BlockStorageDevice* BlockStorageList_GetFirstDevice() +{ + for(int i = 0; i < TARGET_BLOCKSTORAGE_COUNT; i++) + { + if(g_BlockStorage.DeviceList[i] != NULL) + { + return g_BlockStorage.DeviceList[i]; + } + } + + return NULL; +} + +// returns the next device in BlockStorageList +BlockStorageDevice* BlockStorageList_GetNextDevice(BlockStorageDevice* device) +{ + for(int i = 0; i < TARGET_BLOCKSTORAGE_COUNT; i++) + { + if(g_BlockStorage.DeviceList[i] == device) + { + if((i + 1) < TARGET_BLOCKSTORAGE_COUNT){ + return g_BlockStorage.DeviceList[i + 1]; + } + } + } + return NULL; +} + +// // returns number of devices has been declared in the system +unsigned int BlockStorageList_GetNumDevices() +{ + return TARGET_BLOCKSTORAGE_COUNT; +} + +///////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/src/PAL/COM/COM_stubs.c b/source/native/nf-interpreter/src/PAL/COM/COM_stubs.c new file mode 100644 index 00000000..f1892cab --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/COM/COM_stubs.c @@ -0,0 +1,78 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include + +__nfweak bool DebuggerPort_Initialize(COM_HANDLE comPortNum) +{ + (void)comPortNum; + + NATIVE_PROFILE_PAL_COM(); + return true; +} + +__nfweak bool DebuggerPort_Uninitialize(COM_HANDLE comPortNum) +{ + (void)comPortNum; + + NATIVE_PROFILE_PAL_COM(); + return true; +} + +__nfweak int DebuggerPort_Write(COM_HANDLE comPortNum, const char* data, size_t size, int maxRetries) +{ + (void)maxRetries; + + NATIVE_PROFILE_PAL_COM(); + + // minimum implementation is calling generic port to be able to use SWO (if available) + GenericPort_Write( comPortNum, data, size ); + + return 0; +} + +__nfweak int DebuggerPort_Read(COM_HANDLE comPortNum, char* data, size_t size) +{ + (void)comPortNum; + (void)data; + (void)size; + + NATIVE_PROFILE_PAL_COM(); + return 0; +} + +__nfweak bool DebuggerPort_Flush(COM_HANDLE comPortNum) +{ + (void)comPortNum; + + NATIVE_PROFILE_PAL_COM(); + return true; +} + +__nfweak bool DebuggerPort_IsSslSupported(COM_HANDLE comPortNum) +{ + (void)comPortNum; + + NATIVE_PROFILE_PAL_COM(); + return false; +} + +__nfweak bool DebuggerPort_UpgradeToSsl(COM_HANDLE comPortNum, unsigned int flags) +{ + (void)comPortNum; + (void)flags; + + NATIVE_PROFILE_PAL_COM(); + return false; +} + +__nfweak bool DebuggerPort_IsUsingSsl(COM_HANDLE comPortNum) +{ + (void)comPortNum; + + NATIVE_PROFILE_PAL_COM(); + return false; +} diff --git a/source/native/nf-interpreter/src/PAL/COM/ComDirector.cpp b/source/native/nf-interpreter/src/PAL/COM/ComDirector.cpp new file mode 100644 index 00000000..040b4050 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/COM/ComDirector.cpp @@ -0,0 +1,64 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include + +int DebuggerPort_Write( COM_HANDLE ComPortNum, const char* Data, size_t size, int maxRetries ) +{ + NATIVE_PROFILE_PAL_COM(); + + UINT32 transport = ExtractTransport(ComPortNum); + const char* dataTmp = Data; + INT32 totWrite = 0; + int retries = maxRetries + 1; + + while(size > 0 && retries > 0 ) + { + int ret = 0; + + switch(transport) + { + case USART_TRANSPORT: + ret = USART_Write( ConvertCOM_ComPort( ComPortNum ), dataTmp, size ); + break; + case USB_TRANSPORT: + ret = USB_Write( ConvertCOM_UsbStream( ComPortNum ), dataTmp, size ); + break; + case SOCKET_TRANSPORT: + ret = SOCKETS_Write( ConvertCOM_SockPort(ComPortNum), dataTmp, size ); + break; + + case GENERIC_TRANSPORT: + return GenericPort_Write( ConvertCOM_GenericPort( ComPortNum ), dataTmp, size ); + } + + if(ret < 0) + { // error condition, bug out + break; + } + else if(ret == 0) + { // didn't send any data ( assume buffer full ) + --retries; + + // if interrupts are off and buffer is full or out of retries + // then there is nothing more to do. + if(!INTERRUPTS_ENABLED_STATE() || retries <= 0 ) + break; + + Events_WaitForEvents(0, 1); + } + else + { // succesfully transmitted at least some of the data + // update counters and loop back to try sending more + retries = maxRetries + 1; + size -= ret; + dataTmp += ret; + totWrite += ret; + } + } + + return totWrite; +} diff --git a/source/native/nf-interpreter/src/PAL/COM/GenericPort_stubs.c b/source/native/nf-interpreter/src/PAL/COM/GenericPort_stubs.c new file mode 100644 index 00000000..8de1d3bd --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/COM/GenericPort_stubs.c @@ -0,0 +1,76 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include + +__nfweak bool GenericPort_Initialize(int comPortNum) +{ + (void)comPortNum; + + NATIVE_PROFILE_PAL_COM(); + return true; +} + +__nfweak bool GenericPort_Uninitialize(int comPortNum) +{ + (void)comPortNum; + + NATIVE_PROFILE_PAL_COM(); + return true; +} + +__nfweak uint32_t GenericPort_Write(int comPortNum, const char* data, size_t size) +{ + (void)comPortNum; + (void)data; + (void)size; + + NATIVE_PROFILE_PAL_COM(); + return 0; +} + +__nfweak int GenericPort_Read(int comPortNum, char* data, size_t size) +{ + (void)comPortNum; + (void)data; + (void)size; + + NATIVE_PROFILE_PAL_COM(); + return 0; +} + +__nfweak bool GenericPort_Flush(int comPortNum) +{ + (void)comPortNum; + + NATIVE_PROFILE_PAL_COM(); + return true; +} + +__nfweak bool GenericPort_IsSslSupported(int comPortNum) +{ + (void)comPortNum; + + NATIVE_PROFILE_PAL_COM(); + return false; +} + +__nfweak bool GenericPort_UpgradeToSsl(int comPortNum, unsigned int flags) +{ + (void)comPortNum; + (void)flags; + + NATIVE_PROFILE_PAL_COM(); + return false; +} + +__nfweak bool GenericPort_IsUsingSsl(int comPortNum) +{ + (void)comPortNum; + + NATIVE_PROFILE_PAL_COM(); + return false; +} diff --git a/source/native/nf-interpreter/src/PAL/COM/sockets/Sockets_debugger.cpp b/source/native/nf-interpreter/src/PAL/COM/sockets/Sockets_debugger.cpp new file mode 100644 index 00000000..17ef409e --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/COM/sockets/Sockets_debugger.cpp @@ -0,0 +1,640 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "sockets_lwip.h" +#include + +HAL_COMPLETION Sockets_LWIP_Driver::s_DebuggerTimeoutCompletion; + +static HAL_CONTINUATION MulticastResponseContinuation; + +int g_DebuggerPort_SslCtx_Handle = -1; + +// +// Methods used by the Network Debugger +// + +bool SOCKETS_DbgInitialize( int ComPortNum ) +{ + NATIVE_PROFILE_PAL_COM(); + + return Sockets_LWIP_Driver::InitializeDbgListener( ComPortNum ); +} + +bool SOCKETS_DbgUninitialize( int ComPortNum ) +{ + NATIVE_PROFILE_PAL_COM(); + return Sockets_LWIP_Driver::UninitializeDbgListener( ComPortNum ); +} + +int32_t SOCKETS_Write( int32_t ComPortNum, const char* Data, size_t size ) +{ + NATIVE_PROFILE_PAL_COM(); + return Sockets_LWIP_Driver::Write( ComPortNum, Data, size ); +} + +int32_t SOCKETS_Read( int32_t ComPortNum, char* Data, size_t size ) +{ + NATIVE_PROFILE_PAL_COM(); + return Sockets_LWIP_Driver::Read( ComPortNum, Data, size ); +} + +bool SOCKETS_Flush( int32_t ComPortNum ) +{ + (void)ComPortNum; + + NATIVE_PROFILE_PAL_COM(); + //Events_WaitForEvents(0, 2); + return TRUE; +} + +bool SOCKETS_UpgradeToSsl( int32_t ComPortNum, const int8_t* pCACert, uint32_t caCertLen, const int8_t* pDeviceCert, uint32_t deviceCertLen, LPCSTR szTargetHost ) +{ + NATIVE_PROFILE_PAL_COM(); + return Sockets_LWIP_Driver::UpgradeToSsl( ComPortNum, pCACert, caCertLen, pDeviceCert, deviceCertLen, szTargetHost ); +} + +bool SOCKETS_IsUsingSsl( int32_t ComPortNum ) +{ + NATIVE_PROFILE_PAL_COM(); + return Sockets_LWIP_Driver::IsUsingSsl( ComPortNum ); +} + +void Sockets_LWIP_Driver::Debugger_Initialize() +{ + if(!s_initializedDbg) + { + memset(&MulticastResponseContinuation, 0, sizeof(MulticastResponseContinuation)); + memset(&s_DebuggerTimeoutCompletion, 0, sizeof(s_DebuggerTimeoutCompletion)); + + g_Sockets_LWIP_Driver.m_multicastSocket = SOCK_SOCKET_ERROR; + g_Sockets_LWIP_Driver.m_SocketDebugStream = SOCK_SOCKET_ERROR; + g_Sockets_LWIP_Driver.m_SocketDebugListener = SOCK_SOCKET_ERROR; + + g_Sockets_LWIP_Driver.m_stateDebugSocket = DbgSock_Uninitialized; + + g_Sockets_LWIP_Driver.m_usingSSL = FALSE; + + s_initializedDbg = TRUE; + } +} + + +void Sockets_LWIP_Driver::Debugger_Uninitialize() +{ + g_Sockets_LWIP_Driver.m_multicastSocket = SOCK_SOCKET_ERROR; + g_Sockets_LWIP_Driver.m_SocketDebugStream = SOCK_SOCKET_ERROR; + g_Sockets_LWIP_Driver.m_SocketDebugListener = SOCK_SOCKET_ERROR; + s_initializedDbg = FALSE; +} + +void Sockets_LWIP_Driver::Debugger_Abort() +{ + MulticastResponseContinuation.Abort(); + s_DebuggerTimeoutCompletion.Abort(); + + g_Sockets_LWIP_Driver.m_stateDebugSocket = DbgSock_Uninitialized; +} + + +bool Sockets_LWIP_Driver::InitializeDbgListener( int ComPortNum ) +{ + NATIVE_PROFILE_PAL_COM(); + SOCK_sockaddr_in sockAddr; + int nonblocking = 1; + int32_t optval = 1; + int32_t optLinger = 0; + void *dummyPtr; + SOCKET_CHECK_ENTER(); + + Debugger_Initialize(); + + if(ComPortNum != ConvertCOM_SockPort(COM_SOCKET_DBG)) return FALSE; + + if(g_Sockets_LWIP_Driver.m_SocketDebugListener != SOCK_SOCKET_ERROR) return TRUE; + + s_DebuggerTimeoutCompletion.InitializeForUserMode(OnDebuggerTimeout); + + //-- debug api socket --// + + g_Sockets_LWIP_Driver.m_SocketDebugListener = Socket( SOCK_AF_INET, SOCK_SOCK_STREAM, SOCK_IPPROTO_TCP, TRUE ); + SOCKET_CHECK_RESULT( g_Sockets_LWIP_Driver.m_SocketDebugListener ); + + memset( &sockAddr, 0, sizeof(sockAddr) ); + sockAddr.sin_family = SOCK_AF_INET; + sockAddr.sin_port = SOCK_htons(DEBUG_SOCKET_PORT); + sockAddr.sin_addr.S_un.S_addr = SOCK_htonl(SOCK_INADDR_ANY); + + SOCKET_CHECK_RESULT( SOCK_ioctl(g_Sockets_LWIP_Driver.m_SocketDebugListener, SOCK_FIONBIO, &nonblocking) ); + + SOCKET_CHECK_RESULT( HAL_SOCK_setsockopt( g_Sockets_LWIP_Driver.m_SocketDebugListener, SOCK_IPPROTO_TCP, SOCK_TCP_NODELAY, (char*)&optval, sizeof(optval) ) ); + + SOCKET_CHECK_RESULT( HAL_SOCK_setsockopt(g_Sockets_LWIP_Driver.m_SocketDebugListener, SOCK_SOL_SOCKET, SOCK_SOCKO_LINGER, (const char*)&optLinger, sizeof(int32_t)) ); + + // need this to keep the compiler happy about the cast to SOCK_sockaddr + // which is intended and perfectly safe + dummyPtr = &sockAddr; + + SOCKET_CHECK_RESULT( + SOCK_bind( + g_Sockets_LWIP_Driver.m_SocketDebugListener, + (const SOCK_sockaddr*)dummyPtr, + sizeof(sockAddr)) + ); + + SOCKET_CHECK_RESULT( SOCK_listen( g_Sockets_LWIP_Driver.m_SocketDebugListener, 1 ) ); + + g_Sockets_LWIP_Driver.m_stateDebugSocket = DbgSock_Listening; + + InitializeMulticastDiscovery(); + MulticastDiscoverySchedule(); + + SOCKET_CLEANUP(); + + if(g_Sockets_LWIP_Driver.m_SocketDebugListener != SOCK_SOCKET_ERROR) + { + SOCK_close(g_Sockets_LWIP_Driver.m_SocketDebugListener); + g_Sockets_LWIP_Driver.m_SocketDebugListener = SOCK_SOCKET_ERROR; + + debug_printf("DBGLISTENER SOCKET_ERROR: %d\r\n", HAL_SOCK_getlasterror() ); + } + + SOCKET_CHECK_EXIT_bool_CLEANUP(); +} + +bool Sockets_LWIP_Driver::UninitializeDbgListener( int ComPortNum ) +{ + NATIVE_PROFILE_PAL_COM(); + + if(ComPortNum != ConvertCOM_SockPort(COM_SOCKET_DBG)) return FALSE; + + g_Sockets_LWIP_Driver.m_stateDebugSocket = DbgSock_Uninitialized; + + CloseDebuggerSocket(); + + if(g_Sockets_LWIP_Driver.m_SocketDebugListener != SOCK_SOCKET_ERROR) + { + SOCK_close( g_Sockets_LWIP_Driver.m_SocketDebugListener ); + + g_Sockets_LWIP_Driver.m_SocketDebugListener = SOCK_SOCKET_ERROR; + } + + return TRUE; +} + +//----------------------------------------------------------------------------- +// +// Write - The Write method will write data to the debugger stream socket (if a connection is active). +// In addition if the write fails for a reason other than EWOULDBLOCK then we should shutdown +// the debugger stream socket and change to the listening state +// +//----------------------------------------------------------------------------- +int Sockets_LWIP_Driver::Write( int ComPortNum, const char* Data, size_t size ) +{ + NATIVE_PROFILE_PAL_COM(); + int32_t ret; + + if(ComPortNum != ConvertCOM_SockPort(COM_SOCKET_DBG)) return SOCK_SOCKET_ERROR; + + if((g_Sockets_LWIP_Driver.m_stateDebugSocket != DbgSock_Connected) || + (g_Sockets_LWIP_Driver.m_SocketDebugStream == SOCK_SOCKET_ERROR)) + { + return SOCK_SOCKET_ERROR; + } + + if(g_Sockets_LWIP_Driver.m_usingSSL) + { + ret = SSL_Write(g_Sockets_LWIP_Driver.m_SocketDebugStream, Data, size); + } + else + { + ret = SOCK_send( g_Sockets_LWIP_Driver.m_SocketDebugStream, Data, size, 0 ); + } + + if(ret < 0) + { + int32_t err = SOCK_getlasterror(); + + // debugger stream is no longer active, change to listening state + if(err != SOCK_EWOULDBLOCK) + { + CloseDebuggerSocket(); + } + else + { + ret = 0; + } + } + + return ret; +} + +//----------------------------------------------------------------------------- +// +// Read - the Read method performs two duties: first to read data from the debug stream; and +// second to manage the debugger connection state. The initial state is to be listening for debug +// connections, and therefore each read performs an accept to see if there is a pending connection. +// Once a connection is made the state changes to connected and the debugger stream socket +// is read for each Read call. During the Connected state an Accept is still called so that no other +// connections will be handled. If the debugger is still receiving data on the debugger stream, then +// new connections will be closed immediately. If the debugger stream socket has been closed then +// the state return to the listening state (unless there is an pending connection in which case the +// pending connection becomes the new debugger stream). +// +//----------------------------------------------------------------------------- +int Sockets_LWIP_Driver::Read( int ComPortNum, char* Data, size_t size ) +{ + NATIVE_PROFILE_PAL_COM(); + SOCK_SOCKET sock; + SOCK_sockaddr addr; + int len; + int32_t ret = 0; + SOCK_timeval timeout; + SOCK_fd_set readSet; + + if(ComPortNum != ConvertCOM_SockPort(COM_SOCKET_DBG)) return 0; + + if(g_Sockets_LWIP_Driver.m_stateDebugSocket == DbgSock_Uninitialized) return 0; + + memset(&addr, 0, sizeof(addr)); + + timeout.tv_sec = 0; + timeout.tv_usec = 0; + + readSet.fd_array[0] = g_Sockets_LWIP_Driver.m_SocketDebugListener; + readSet.fd_count = 1; + + // if we are connected, then read from the debug stream + if(g_Sockets_LWIP_Driver.m_stateDebugSocket == DbgSock_Connected) + { + if(g_Sockets_LWIP_Driver.m_usingSSL) + { + ret = SSL_Read(g_Sockets_LWIP_Driver.m_SocketDebugStream, Data, size); + } + else + { + ret = SOCK_recv(g_Sockets_LWIP_Driver.m_SocketDebugStream, Data, size, 0); + } + + // return value of zero indicates a shutdown of the socket. Also we shutdown for any error except + // ewouldblock. If either of these happens, then we go back to the listening state + if((ret == 0) || (ret == SOCK_SOCKET_ERROR && SOCK_getlasterror() != SOCK_EWOULDBLOCK)) + { + CloseDebuggerSocket(); + } + else if(ret != SOCK_SOCKET_ERROR && s_DebuggerTimeoutCompletion.IsLinked()) + { + // we either got data or the socket was closed, so kill the timeout + s_DebuggerTimeoutCompletion.Abort(); + } + } + + if(SOCK_SOCKET_ERROR != HAL_SOCK_select( SOCK_FD_SETSIZE, &readSet, NULL, NULL, &timeout)) + { + // we always perform an accept so that we handle pending connections + // if we already are connected and the debug stream socket is still active, then we immediately close + // the pending connection + sock = Accept( g_Sockets_LWIP_Driver.m_SocketDebugListener, &addr, &len, TRUE ); + + if(SOCK_SOCKET_ERROR != sock) + { + int nonblocking = 1; + bool optval = 1; + int32_t optLinger = 0; + + // if we are already in the connected state, then verify that the debugger stream socket is still active + if(DbgSock_Connected == g_Sockets_LWIP_Driver.m_stateDebugSocket) + { + // the debugger stream is still active, so shutdown the pending connection + HAL_SOCK_setsockopt( sock, SOCK_SOL_SOCKET, SOCK_SOCKO_LINGER, (const char*)&optLinger, sizeof(int32_t) ); + SOCK_close(sock); + + // set timeout since another connection is trying to use us. + if(!s_DebuggerTimeoutCompletion.IsLinked()) + { + s_DebuggerTimeoutCompletion.EnqueueDelta(5000000); // 5 seconds + } + } + else // we are in the listening state, so accept the pending connection and update the state + { + g_Sockets_LWIP_Driver.m_SocketDebugStream = sock; + SOCKET_CHECK_RESULT( SOCK_ioctl(g_Sockets_LWIP_Driver.m_SocketDebugStream, SOCK_FIONBIO, &nonblocking) ); + SOCKET_CHECK_RESULT( HAL_SOCK_setsockopt( g_Sockets_LWIP_Driver.m_SocketDebugStream, SOCK_IPPROTO_TCP, SOCK_TCP_NODELAY, (char*)&optval, sizeof(optval) ) ); + SOCKET_CHECK_RESULT( HAL_SOCK_setsockopt( g_Sockets_LWIP_Driver.m_SocketDebugStream, SOCK_SOL_SOCKET, SOCK_SOCKO_LINGER, (const char*)&optLinger, sizeof(int32_t) ) ); + + g_Sockets_LWIP_Driver.m_stateDebugSocket = DbgSock_Connected; + + SOCKET_CLEANUP() + + if(g_Sockets_LWIP_Driver.m_SocketDebugStream != SOCK_SOCKET_ERROR) + { + SOCK_close(g_Sockets_LWIP_Driver.m_SocketDebugStream); + g_Sockets_LWIP_Driver.m_SocketDebugStream = SOCK_SOCKET_ERROR; + + debug_printf("DBGSTREAM SOCKET_ERROR: %d\r\n", HAL_SOCK_getlasterror() ); + } + + SOCKET_CHECK_EXIT_NORETURN(); + } + + HAL_SOCK_EventsSet( SOCKET_EVENT_FLAG_SOCKET ); + } + } + + if(ret < 0) + { + ret = 0; + } + + return ret; +} + +void Sockets_LWIP_Driver::CloseDebuggerSocket() +{ + if(g_Sockets_LWIP_Driver.m_SocketDebugStream != SOCK_SOCKET_ERROR) + { + if(g_Sockets_LWIP_Driver.m_usingSSL) + { + SSL_CloseSocket( g_Sockets_LWIP_Driver.m_SocketDebugStream ); + } + else + { + SOCK_close( g_Sockets_LWIP_Driver.m_SocketDebugStream ); + } + + g_Sockets_LWIP_Driver.m_usingSSL = FALSE; + + g_Sockets_LWIP_Driver.m_SocketDebugStream = SOCK_SOCKET_ERROR; + + g_Sockets_LWIP_Driver.m_stateDebugSocket = DbgSock_Listening; + + s_DebuggerTimeoutCompletion.Abort(); + } +} + +void Sockets_LWIP_Driver::OnDebuggerTimeout(void* arg) +{ + (void)arg; + + CloseDebuggerSocket(); +} + +bool Sockets_LWIP_Driver::IsUsingSsl( int ComPortNum ) +{ + if(ComPortNum != ConvertCOM_SockPort(COM_SOCKET_DBG)) return FALSE; + if(g_Sockets_LWIP_Driver.m_stateDebugSocket == DbgSock_Uninitialized) return FALSE; + + if(g_Sockets_LWIP_Driver.m_stateDebugSocket == DbgSock_Connected) + { + return g_Sockets_LWIP_Driver.m_usingSSL; + } + + return FALSE; +} + +bool Sockets_LWIP_Driver::UpgradeToSsl( int ComPortNum, const int8_t* pCACert, uint32_t caCertLen, const int8_t* pDeviceCert, uint32_t deviceCertLen, const char* szTargetHost ) +{ + if(ComPortNum != ConvertCOM_SockPort(COM_SOCKET_DBG)) return 0; + if(g_Sockets_LWIP_Driver.m_stateDebugSocket == DbgSock_Uninitialized) return 0; + + if(g_Sockets_LWIP_Driver.m_stateDebugSocket == DbgSock_Connected) + { + if(g_Sockets_LWIP_Driver.m_usingSSL) return TRUE; + + // TLS only and Verify=Required --> only verify the server + if(SSL_ClientInit( 0x10, 0x04, (const char*)pDeviceCert, deviceCertLen, NULL, 0 , NULL, 0, g_DebuggerPort_SslCtx_Handle )) + { + int32_t ret; + + SSL_AddCertificateAuthority( g_DebuggerPort_SslCtx_Handle, (const char*)pCACert, caCertLen, NULL); + + do + { + ret = SSL_Connect( g_Sockets_LWIP_Driver.m_SocketDebugStream, szTargetHost, g_DebuggerPort_SslCtx_Handle ); + } + while(ret == SOCK_EWOULDBLOCK || ret == SOCK_TRY_AGAIN); + + + if(ret != 0) + { + SSL_CloseSocket(g_Sockets_LWIP_Driver.m_SocketDebugStream); + SSL_ExitContext(g_DebuggerPort_SslCtx_Handle); + } + else + { + g_Sockets_LWIP_Driver.m_usingSSL = TRUE; + } + + return ret == 0; + } + } + + return FALSE; +} + +//----------------------------------------------------------------------------- +// +// InitializeMulticastDiscovery - Initialize the NETMF discovery service for +// sockets. We use multicast sockets to create the discovery mechanism. +// +//----------------------------------------------------------------------------- +bool Sockets_LWIP_Driver::InitializeMulticastDiscovery() +{ + NATIVE_PROFILE_PAL_COM(); + SOCKET_CHECK_ENTER(); + SOCK_sockaddr_in sockAddr; + void *dummyPtr; + int nonblocking = 1; + + if(g_Sockets_LWIP_Driver.s_discoveryInitialized) return TRUE; + + MulticastResponseContinuation.InitializeCallback(MulticastDiscoveryRespond, NULL); + + // set up discovery socket to list to defined discovery port for any ip address + memset( &sockAddr, 0, sizeof(sockAddr) ); + sockAddr.sin_family = SOCK_AF_INET; + sockAddr.sin_port = SOCK_htons(SOCK_DISCOVERY_MULTICAST_PORT); + sockAddr.sin_addr.S_un.S_addr = SOCK_htonl(SOCK_INADDR_ANY); + + // UDP socket is easier in our scenario because it isn't session based + g_Sockets_LWIP_Driver.m_multicastSocket = Socket( SOCK_AF_INET, SOCK_SOCK_DGRAM, SOCK_IPPROTO_UDP, FALSE ); + SOCKET_CHECK_RESULT( g_Sockets_LWIP_Driver.m_multicastSocket ); + + // set sock option for multicast + SOCK_ip_mreq multicast; + multicast.imr_multiaddr.S_un.S_addr = SOCK_htonl(SOCK_DISCOVERY_MULTICAST_IPADDR); + multicast.imr_interface.S_un.S_addr = SOCK_htonl(SOCK_INADDR_ANY); + + SOCKET_CHECK_RESULT( SOCK_ioctl(g_Sockets_LWIP_Driver.m_multicastSocket, SOCK_FIONBIO, &nonblocking) ); + + SOCKET_CHECK_RESULT( SOCK_setsockopt( g_Sockets_LWIP_Driver.m_multicastSocket, SOCK_IPPROTO_IP, SOCK_IPO_ADD_MEMBERSHIP, (const char*)&multicast, sizeof(multicast) ) ); + + // need this to keep the compiler happy about the cast to SOCK_sockaddr + // which is intended and perfectly safe + dummyPtr = &sockAddr; + + SOCKET_CHECK_RESULT( + SOCK_bind( + g_Sockets_LWIP_Driver.m_multicastSocket, + (const SOCK_sockaddr*)&dummyPtr, + sizeof(sockAddr)) + ); + + g_Sockets_LWIP_Driver.s_discoveryInitialized = TRUE; + + + SOCKET_CLEANUP() + + if(g_Sockets_LWIP_Driver.m_multicastSocket != SOCK_SOCKET_ERROR) + { + SOCK_close(g_Sockets_LWIP_Driver.m_multicastSocket); + g_Sockets_LWIP_Driver.m_multicastSocket = SOCK_SOCKET_ERROR; + + debug_printf("MULTICAST SOCKET_ERROR: %d\r\n", HAL_SOCK_getlasterror() ); + } + + SOCKET_CHECK_EXIT_bool_CLEANUP(); +} + +// TODO. Schedule the Discovery Multicast Response + +//----------------------------------------------------------------------------- +// +// MulticastDiscoveryRespond - Respond to a NETMF multicast message. This is +// a simple discovery mechanism that uses multicast sockets over UDP. The +// client will send a message to the ip address defined by +// SOCK_DISCOVERY_MULTICAST_IPADDR +// over port +// SOCK_DISCOVERY_MULTICAST_PORT +// If the message contains the string "NETMF", then a response is sent with the +// the data structure SOCK_discoveryinfo (which includes the ip address and mac +// address of the device). +// +//----------------------------------------------------------------------------- + +void Sockets_LWIP_Driver::MulticastDiscoverySchedule() +{ + if (g_Sockets_LWIP_Driver.m_multicastSocket != SOCK_SOCKET_ERROR) + { + SOCK_fd_set privRead; + SOCK_timeval to; + + to.tv_sec = 0; + to.tv_usec = 0; + + privRead.fd_array[0] = g_Sockets_LWIP_Driver.m_multicastSocket; + privRead.fd_count = 1; + + if (1 == HAL_SOCK_select(1, &privRead, NULL, NULL, &to)) + { + if (!MulticastResponseContinuation.IsLinked()) + { + MulticastResponseContinuation.Enqueue(); + } + } + } +} + +void Sockets_LWIP_Driver::MulticastDiscoveryRespond(void* arg) +{ + (void)arg; + + NATIVE_PROFILE_PAL_COM(); + SOCK_sockaddr from; + void *dummyPtr; + + char data[64]; + int fromlen = sizeof(from); + + // intentionally call the HAL recvfrom so as not to invoke the signalnotifythread + int len = HAL_SOCK_recvfrom( g_Sockets_LWIP_Driver.m_multicastSocket, data, sizeof(data), 0, &from, &fromlen ); + + if(len > 0) + { + int32_t idx = 0; + bool fFound = FALSE; + const char* c_Signature = SOCK_DISCOVERY_MULTICAST_TOKEN; + int32_t sigLen = hal_strlen_s(c_Signature); + + // search for discovery token + while(idx <= (len-sigLen)) + { + if(0 == memcmp( &data[idx], c_Signature, sigLen)) + { + fFound = TRUE; + break; + } + idx++; + } + + if(fFound) + { + // HAL_Configuration_NetworkInterface current; + // SOCK_discoveryinfo info; + SOCK_sockaddr_in sockAddr; + SOCK_sockaddr_in sockAddrMulticast; + int32_t opt = 64; + SOCK_SOCKET sock; + int nonblocking = 1; + SOCKET_CHECK_ENTER(); + + // // Load is required here because the g_NetworkConfig contains only the static ip address (not DHCP) + // HAL_SOCK_CONFIGURATION_LoadAdapterConfiguration(0, ¤t); + + // info.ipaddr = current.ipaddr; + // info.macAddressLen = current.macAddressLen; + // memcpy( &info.macAddressBuffer[0], ¤t.macAddressBuffer[0], current.macAddressLen ); + + sock = Socket(SOCK_AF_INET, SOCK_SOCK_DGRAM, SOCK_IPPROTO_UDP, FALSE); + SOCKET_CHECK_RESULT(sock); + + memset( &sockAddr, 0, sizeof(sockAddr) ); + sockAddr.sin_family = SOCK_AF_INET; + sockAddr.sin_port = SOCK_htons(0); + // sockAddr.sin_addr.S_un.S_addr = info.ipaddr; + + memset( &sockAddrMulticast, 0, sizeof(sockAddrMulticast) ); + sockAddrMulticast.sin_family = SOCK_AF_INET; + sockAddrMulticast.sin_port = SOCK_htons(SOCK_DISCOVERY_MULTICAST_PORT); + sockAddrMulticast.sin_addr.S_un.S_addr = SOCK_htonl(SOCK_DISCOVERY_MULTICAST_IPADDR_SND); + + SOCKET_CHECK_RESULT(HAL_SOCK_ioctl(sock, SOCK_FIONBIO, &nonblocking)); + SOCKET_CHECK_RESULT(HAL_SOCK_setsockopt(sock, SOCK_IPPROTO_IP, SOCK_IPO_MULTICAST_TTL, (const char *) &opt, sizeof(opt))); + + // need this to keep the compiler happy about the cast to SOCK_sockaddr + // which is intended and perfectly safe + dummyPtr = &sockAddr; + + SOCKET_CHECK_RESULT( + HAL_SOCK_bind( + sock, + (const SOCK_sockaddr*)&dummyPtr, + sizeof(sockAddr)) + ); + + // send a multicast socket back to the caller + // SOCKET_CHECK_RESULT(SendTo(sock, (const char*)&info, sizeof(info), 0, (SOCK_sockaddr*)&sockAddrMulticast, sizeof(sockAddrMulticast))); + + SOCK_close(sock); + + SOCKET_CLEANUP(); + + if(sock != SOCK_SOCKET_ERROR) + { + SOCK_close(sock); + + debug_printf("MULTICAST RESP SOCKET_ERROR: %d\r\n", HAL_SOCK_getlasterror() ); + } + + SOCKET_CHECK_EXIT_NORETURN(); + } + } + + MulticastDiscoverySchedule(); +} + + +bool Sockets_LWIP_Driver::s_initializedDbg=FALSE; \ No newline at end of file diff --git a/source/native/nf-interpreter/src/PAL/COM/sockets/sockets_lwip.cpp b/source/native/nf-interpreter/src/PAL/COM/sockets/sockets_lwip.cpp new file mode 100644 index 00000000..028c2ec7 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/COM/sockets/sockets_lwip.cpp @@ -0,0 +1,481 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "sockets_lwip.h" + +//--// + +Sockets_LWIP_Driver g_Sockets_LWIP_Driver; + +SOCK_SOCKET SOCK_socket( int family, int type, int protocol ) +{ + NATIVE_PROFILE_PAL_COM(); + return Sockets_LWIP_Driver::Socket( family, type, protocol, FALSE ); +} +int SOCK_bind( SOCK_SOCKET socket, const struct SOCK_sockaddr* address, int addressLen ) +{ + NATIVE_PROFILE_PAL_COM(); + return HAL_SOCK_bind( socket, address, addressLen ); +} +int SOCK_connect(SOCK_SOCKET socket, const struct SOCK_sockaddr* address, int addressLen) +{ + NATIVE_PROFILE_PAL_COM(); + return Sockets_LWIP_Driver::Connect(socket, address, addressLen); +} +int SOCK_send(SOCK_SOCKET socket, const char* buf, int len, int flags) +{ + NATIVE_PROFILE_PAL_COM(); + return Sockets_LWIP_Driver::Send(socket, buf, len, flags); +} +int SOCK_recv(SOCK_SOCKET socket, char* buf, int len, int flags) +{ + NATIVE_PROFILE_PAL_COM(); + return Sockets_LWIP_Driver::Recv(socket, buf, len, flags); +} +int SOCK_close(SOCK_SOCKET socket) +{ + NATIVE_PROFILE_PAL_COM(); + return Sockets_LWIP_Driver::Close(socket); +} +int SOCK_listen( SOCK_SOCKET socket, int backlog ) +{ + NATIVE_PROFILE_PAL_COM(); + return Sockets_LWIP_Driver::Listen( socket, backlog ); +} +SOCK_SOCKET SOCK_accept( SOCK_SOCKET socket, struct SOCK_sockaddr* address, int* addressLen ) +{ + NATIVE_PROFILE_PAL_COM(); + return Sockets_LWIP_Driver::Accept( socket, address, addressLen, FALSE ); +} +int SOCK_shutdown( SOCK_SOCKET socket, int how ) +{ + NATIVE_PROFILE_PAL_COM(); + return HAL_SOCK_shutdown( socket, how ); +} +int SOCK_getaddrinfo( const char* nodename, char* servname, const struct SOCK_addrinfo* hints, struct SOCK_addrinfo** res ) +{ + NATIVE_PROFILE_PAL_COM(); + return HAL_SOCK_getaddrinfo( nodename, servname, hints, res ); +} +void SOCK_freeaddrinfo( struct SOCK_addrinfo* ai ) +{ + NATIVE_PROFILE_PAL_COM(); + HAL_SOCK_freeaddrinfo( ai ); +} +int SOCK_ioctl( SOCK_SOCKET socket, int cmd, int* data ) +{ + NATIVE_PROFILE_PAL_COM(); + return HAL_SOCK_ioctl( socket, cmd, data ); +} +int SOCK_getlasterror() +{ + NATIVE_PROFILE_PAL_COM(); + return HAL_SOCK_getlasterror(); +} +int SOCK_getsocklasterror(SOCK_SOCKET socket) +{ + NATIVE_PROFILE_PAL_COM(); + return HAL_SOCK_getsocklasterror(socket); +} +int SOCK_select( int nfds, SOCK_fd_set* readfds, SOCK_fd_set* writefds, SOCK_fd_set* except, const struct SOCK_timeval* timeout ) +{ + NATIVE_PROFILE_PAL_COM(); + return Sockets_LWIP_Driver::Select( nfds, readfds, writefds, except, timeout ); +} +int SOCK_setsockopt( SOCK_SOCKET socket, int level, int optname, const char* optval, int optlen ) +{ + NATIVE_PROFILE_PAL_COM(); + return HAL_SOCK_setsockopt( socket, level, optname, optval, optlen ); +} +int SOCK_getsockopt( SOCK_SOCKET socket, int level, int optname, char* optval, int* optlen ) +{ + NATIVE_PROFILE_PAL_COM(); + return HAL_SOCK_getsockopt( socket, level, optname, optval, optlen ); +} +int SOCK_getpeername( SOCK_SOCKET socket, struct SOCK_sockaddr* name, int* namelen ) +{ + NATIVE_PROFILE_PAL_COM(); + return HAL_SOCK_getpeername( socket, name, namelen ); +} +int SOCK_getsockname( SOCK_SOCKET socket, struct SOCK_sockaddr* name, int* namelen ) +{ + NATIVE_PROFILE_PAL_COM(); + return HAL_SOCK_getsockname( socket, name, namelen ); +} +int SOCK_recvfrom( SOCK_SOCKET s, char* buf, int len, int flags, struct SOCK_sockaddr* from, int* fromlen ) +{ + NATIVE_PROFILE_PAL_COM(); + return Sockets_LWIP_Driver::RecvFrom( s, buf, len, flags, from, fromlen ); +} +int SOCK_sendto( SOCK_SOCKET s, const char* buf, int len, int flags, const struct SOCK_sockaddr* to, int tolen ) +{ + NATIVE_PROFILE_PAL_COM(); + return Sockets_LWIP_Driver::SendTo( s, buf, len, flags, to, tolen ); +} + +bool Network_Initialize() +{ + NATIVE_PROFILE_PAL_COM(); + return Sockets_LWIP_Driver::Initialize( ); +} + +bool Network_Uninitialize() +{ + NATIVE_PROFILE_PAL_COM(); + + return Sockets_LWIP_Driver::Uninitialize( ); +} + +void SOCKETS_CloseConnections() +{ + NATIVE_PROFILE_PAL_COM(); + Sockets_LWIP_Driver::CloseConnections(FALSE); +} + +HRESULT SOCK_CONFIGURATION_LoadAdapterConfiguration(HAL_Configuration_NetworkInterface* config, uint32_t interfaceIndex) +{ + NATIVE_PROFILE_PAL_COM(); + return HAL_SOCK_CONFIGURATION_LoadAdapterConfiguration(config, interfaceIndex); +} + +HRESULT SOCK_CONFIGURATION_UpdateAdapterConfiguration(HAL_Configuration_NetworkInterface* config, uint32_t interfaceIndex, uint32_t updateFlags) +{ + NATIVE_PROFILE_PAL_COM(); + HRESULT hr = S_OK; + bool success = FALSE; + + const uint32_t c_reInitFlag = UpdateOperation_Dhcp | + UpdateOperation_DhcpRenew | + UpdateOperation_Mac; + + const uint32_t c_uninitFlag = c_reInitFlag | UpdateOperation_DhcpRelease; + + if(0 != (updateFlags & c_uninitFlag)) + { + success = SOCKETS_DbgUninitialize(COM_SOCKET_DBG); + } + + hr = HAL_SOCK_CONFIGURATION_UpdateAdapterConfiguration(config, interfaceIndex, updateFlags); + + if(!SUCCEEDED(hr)) + { + return S_FALSE; + } + + if(0 != (updateFlags & c_reInitFlag)) + { + if(success) SOCKETS_DbgInitialize(COM_SOCKET_DBG); + } + + return hr; +} + +HRESULT SOCK_CONFIGURATION_LoadConfiguration(HAL_Configuration_NetworkInterface* config, uint32_t interfaceIndex) +{ + NATIVE_PROFILE_PAL_COM(); + HRESULT hr = S_OK; + + // load current DCHP settings + hr = SOCK_CONFIGURATION_LoadAdapterConfiguration(config, interfaceIndex); + + return hr; +} + +#define SOCKET_SHUTDOWN_READ 0 +#define SOCKET_SHUTDOWN_WRITE 1 +#define SOCKET_SHUTDOWN_READ_WRITE 2 + +#define ISSET_SOCKET_FLAG(x,y) ((y) == ((y) & (x).m_flags)) +#define SET_SOCKET_FLAG(x,y) (x).m_flags |= (y) +#define CLEAR_SOCKET_FLAG(x,y) (x).m_flags &= ~(y) + +//----------------------------------------------------------------------------- +// +// CloseConnections - close all connections with the option of leaving the debugger sockets open. +// debugger sockets are left open on CLR reboot so that communication with the debugger is not +// lost. +// +//----------------------------------------------------------------------------- +void Sockets_LWIP_Driver::CloseConnections(bool fCloseDbg) +{ + NATIVE_PROFILE_PAL_COM(); + + int32_t cnt = g_Sockets_LWIP_Driver.m_cntSockets; + int32_t idx = 0; + + // round one - close all SSL sockets + for( int32_t i=cnt-1; i>=0; i-- ) + { + struct SocketRegisterMap& entry = g_Sockets_LWIP_Driver.m_socketHandles[i]; + + if(entry.m_socket != SOCK_SOCKET_ERROR && + entry.m_sslData != NULL) + { + SSL_CloseSocket(entry.m_socket); + } + } + + // round two - close all non-SSL sockets + cnt = g_Sockets_LWIP_Driver.m_cntSockets; + + for( int32_t i=0; i 0) + { + memcpy( &g_Sockets_LWIP_Driver.m_socketHandles[i], + &g_Sockets_LWIP_Driver.m_socketHandles[idx++], + sizeof(g_Sockets_LWIP_Driver.m_socketHandles[i]) ); + } + } + } +} + +//--// + +SOCK_SOCKET Sockets_LWIP_Driver::Socket( int32_t family, int32_t type, int32_t protocol, bool fDebug ) +{ + NATIVE_PROFILE_PAL_COM(); + + int ret = HAL_SOCK_socket(family, type, protocol); + + if (ret != SOCK_SOCKET_ERROR) + { + RegisterSocket(ret, (protocol != SOCK_IPPROTO_TCP), fDebug); + } + return ret; +} +int Sockets_LWIP_Driver::Connect(SOCK_SOCKET socket, const struct SOCK_sockaddr* address, int32_t addressLen) +{ + NATIVE_PROFILE_PAL_COM(); + + return HAL_SOCK_connect(socket, address, addressLen); +} +int Sockets_LWIP_Driver::Send(SOCK_SOCKET socket, const char* buf, int32_t len, int32_t flags) +{ + NATIVE_PROFILE_PAL_COM(); + + return HAL_SOCK_send(socket, buf, len, flags); +} +int Sockets_LWIP_Driver::Recv(SOCK_SOCKET socket, char* buf, int32_t len, int32_t flags) +{ + NATIVE_PROFILE_PAL_COM(); + + return HAL_SOCK_recv(socket, buf, len, flags); +} + +int Sockets_LWIP_Driver::Shutdown(SOCK_SOCKET sock, int32_t how) +{ + NATIVE_PROFILE_PAL_COM(); + + return HAL_SOCK_shutdown(sock, how); +} + +//----------------------------------------------------------------------------- +// +// Close - The close method marks a socket to be closed by the select thread. Close is handled +// in this way because (at least for one implementation) the select method can not be set for a +// closed socket. Therfore in the select thread the socket is closed. +// +//----------------------------------------------------------------------------- +int Sockets_LWIP_Driver::Close(SOCK_SOCKET sock) +{ + NATIVE_PROFILE_PAL_COM(); + UnregisterSocket(sock); + return HAL_SOCK_close(sock); +} +int Sockets_LWIP_Driver::Listen( SOCK_SOCKET socket, int32_t backlog ) +{ + NATIVE_PROFILE_PAL_COM(); + + return HAL_SOCK_listen(socket, backlog); +} +SOCK_SOCKET Sockets_LWIP_Driver::Accept( SOCK_SOCKET socket, struct SOCK_sockaddr* address, int* addressLen, bool fDebug ) +{ + NATIVE_PROFILE_PAL_COM(); + + int ret = HAL_SOCK_accept(socket, address, addressLen); + + if (ret != SOCK_SOCKET_ERROR) + { + RegisterSocket(ret, TRUE, fDebug); + } + + return ret; +} + +int Sockets_LWIP_Driver::Select( int32_t nfds, SOCK_fd_set* readfds, SOCK_fd_set* writefds, SOCK_fd_set* exceptfds, const SOCK_timeval* timeout ) +{ + NATIVE_PROFILE_PAL_COM(); + + return HAL_SOCK_select(nfds, readfds, writefds, exceptfds, timeout); +} + +int Sockets_LWIP_Driver::RecvFrom( SOCK_SOCKET s, char* buf, int32_t len, int32_t flags, struct SOCK_sockaddr* from, int* fromlen ) +{ + NATIVE_PROFILE_PAL_COM(); + + return HAL_SOCK_recvfrom(s, buf, len, flags, from, fromlen); +} + +int Sockets_LWIP_Driver::SendTo( SOCK_SOCKET s, const char* buf, int32_t len, int32_t flags, const struct SOCK_sockaddr* to, int32_t tolen ) +{ + NATIVE_PROFILE_PAL_COM(); + + return HAL_SOCK_sendto(s, buf, len, flags, to, tolen); +} + +bool Sockets_LWIP_Driver::Initialize() +{ + NATIVE_PROFILE_PAL_COM(); + SOCKET_CHECK_ENTER(); + + if(!s_initialized) + { + g_Sockets_LWIP_Driver.m_fShuttingDown = FALSE; + + g_Sockets_LWIP_Driver.m_cntSockets = 0; + + for( int32_t i=0; i= SOCKETS_MAX_COUNT) return; + + GLOBAL_LOCK_SOCKETS(lock); + + g_Sockets_LWIP_Driver.m_socketHandles[g_Sockets_LWIP_Driver.m_cntSockets].m_socket = sock; + g_Sockets_LWIP_Driver.m_socketHandles[g_Sockets_LWIP_Driver.m_cntSockets].m_flags = 0; + g_Sockets_LWIP_Driver.m_socketHandles[g_Sockets_LWIP_Driver.m_cntSockets].m_sslData = NULL; + + if(fDebug) SET_SOCKET_FLAG(g_Sockets_LWIP_Driver.m_socketHandles[g_Sockets_LWIP_Driver.m_cntSockets], SocketRegisterMap::c_DebugSocket); + + g_Sockets_LWIP_Driver.m_cntSockets++; +} + +//----------------------------------------------------------------------------- +// +// UnregisterSocket - No longer track a given socket for clean up and selection. +// This method should only be called immediately before closing down a socket. +// +//----------------------------------------------------------------------------- +void Sockets_LWIP_Driver::UnregisterSocket( SOCK_SOCKET sock ) +{ + int32_t index= -1; + + NATIVE_PROFILE_PAL_COM(); + GLOBAL_LOCK_SOCKETS(lock); + + g_Sockets_LWIP_Driver.GetSocketSslData(sock, index); + + if (index == -1) return; + + g_Sockets_LWIP_Driver.m_cntSockets--; + + if(index != g_Sockets_LWIP_Driver.m_cntSockets) + { + memcpy( &g_Sockets_LWIP_Driver.m_socketHandles[index], + &g_Sockets_LWIP_Driver.m_socketHandles[g_Sockets_LWIP_Driver.m_cntSockets], + sizeof(g_Sockets_LWIP_Driver.m_socketHandles[index]) ); + } + + g_Sockets_LWIP_Driver.m_socketHandles[g_Sockets_LWIP_Driver.m_cntSockets].m_socket = SOCK_SOCKET_ERROR; + g_Sockets_LWIP_Driver.m_socketHandles[g_Sockets_LWIP_Driver.m_cntSockets].m_flags = 0; +} + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// weak implementations of the functions (to be replaced with _strong_ implementations if and when required) // +// C++ version +// __nfweak void debug_printf( const char* format, ... ) +// { +// return; +// } + +bool Sockets_LWIP_Driver::s_initialized=FALSE; +bool Sockets_LWIP_Driver::s_wirelessInitialized=FALSE; +bool Sockets_LWIP_Driver::s_discoveryInitialized=FALSE; + + diff --git a/source/native/nf-interpreter/src/PAL/COM/sockets/sockets_lwip.h b/source/native/nf-interpreter/src/PAL/COM/sockets/sockets_lwip.h new file mode 100644 index 00000000..bb7b972c --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/COM/sockets/sockets_lwip.h @@ -0,0 +1,187 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _SOCKETS_H_ +#define _SOCKETS_H_ 1 + +//--// + +#include "nanoHAL.h" + +//--// + +#define SOCKET_CHECK_ENTER() \ + int32_t ret=0 \ + +#define SOCKET_CLEANUP() \ + goto RETURN_OK; \ + SOCKET_CHECK_RETURN: \ + +#define SOCKET_CHECK_EXIT_CLEANUP() \ + RETURN_OK: \ + ASSERT(ret != SOCK_SOCKET_ERROR); \ + return ret; \ + +#define SOCKET_CHECK_EXIT() \ + SOCKET_CLEANUP() \ + RETURN_OK: \ + ASSERT(ret != SOCK_SOCKET_ERROR); \ + return ret; \ + +#define SOCKET_CHECK_EXIT_bool() \ + SOCKET_CLEANUP() \ + RETURN_OK: \ + return ret != SOCK_SOCKET_ERROR; \ + +#define SOCKET_CHECK_EXIT_bool_CLEANUP()\ + RETURN_OK: \ + return ret != SOCK_SOCKET_ERROR; \ + +#define SOCKET_CHECK_RESULT(x) \ + if((ret = (x)) == SOCK_SOCKET_ERROR)\ + { \ + goto SOCKET_CHECK_RETURN; \ + } \ + +#define SOCKET_CHECK_bool(x) \ + if(!(x)) \ + { \ + ret = SOCK_SOCKET_ERROR; \ + goto SOCKET_CHECK_RETURN; \ + } \ + +#define SOCKET_CHECK_EXIT_NORETURN() \ + RETURN_OK: \ + +struct Sockets_LWIP_Driver +{ + static SOCK_SOCKET Socket( int32_t family, int32_t type, int32_t protocol, bool fDebug ); + static int Connect(SOCK_SOCKET socket, const struct SOCK_sockaddr* address, int32_t addressLen) ; + static int Send(SOCK_SOCKET socket, const char* buf, int32_t len, int32_t flags) ; + static int Recv(SOCK_SOCKET socket, char* buf, int32_t len, int32_t flags); + static int Close(SOCK_SOCKET socket); + static int Listen( SOCK_SOCKET socket, int32_t backlog ); + static SOCK_SOCKET Accept( SOCK_SOCKET socket, struct SOCK_sockaddr* address, int* addressLen, bool fDebug ); + static int Select( int32_t nfds, SOCK_fd_set* readfds, SOCK_fd_set* writefds, SOCK_fd_set* except, const struct SOCK_timeval* timeout ); + static int RecvFrom( SOCK_SOCKET s, char* buf, int32_t len, int32_t flags, struct SOCK_sockaddr* from, int* fromlen ); + static int SendTo( SOCK_SOCKET s, const char* buf, int32_t len, int32_t flags, const struct SOCK_sockaddr* to, int32_t tolen ); + static int Shutdown( SOCK_SOCKET s, int32_t how); + + static bool Initialize(); + static bool Uninitialize(); + static void CloseConnections(bool fCloseDbg); + + static void SaveConfig(int32_t index, HAL_Configuration_NetworkInterface *cfg); + + // Debugger methods ( socket_debugger.cpp ) + static void Debugger_Initialize(); + static void Debugger_Uninitialize(); + static void Debugger_Abort(); + + static bool InitializeDbgListener( int ComPortNum ); + static bool UninitializeDbgListener( int ComPortNum ); + static int Write( int ComPortNum, const char* Data, size_t size ); + static int Read ( int ComPortNum, char* Data, size_t size ); + static bool UpgradeToSsl( int ComPortNum, const int8_t* pCACert, uint32_t caCertLen, const int8_t* pDeviceCert, uint32_t deviceCertLen, const char* szTargetHost ); + static bool IsUsingSsl( int ComPortNum ); + + void* GetSocketSslData(SOCK_SOCKET socket) + { + int32_t tmp; + + return GetSocketSslData(socket, tmp); + } + + void* GetSocketSslData(SOCK_SOCKET socket, int32_t &sockIndex) + { + GLOBAL_LOCK_SOCKETS(x); + + for(int i=m_cntSockets-1; i>=0; i--) + { + if(socket == m_socketHandles[i].m_socket) + { + sockIndex = i; + return m_socketHandles[i].m_sslData; + } + } + + return NULL; + } + + void SetSocketSslData(SOCK_SOCKET socket, void* sslObj) + { + GLOBAL_LOCK_SOCKETS(x); + + for(int i=m_cntSockets-1; i>=0; i--) + { + if(socket == m_socketHandles[i].m_socket) + { + m_socketHandles[i].m_sslData = sslObj; + + break; + } + } + } + + // required by SSL + static void UnregisterSocket( int index ); + + + static void ClearStatusBitsForSocket(SOCK_SOCKET sock, bool fWrite); + static bool InitializeMulticastDiscovery(); + +private: + + static void RegisterSocket( SOCK_SOCKET sock, bool selectable, bool fDebug ); + + struct SocketRegisterMap + { + SOCK_SOCKET m_socket; + uint32_t m_flags; + void* m_sslData; + + static const uint32_t c_SelectableSocket = 0x0001; + static const uint32_t c_DebugSocket = 0x0002; + static const uint32_t c_CloseSocket = 0x0004; + }; + + enum DebuggerState + { + DbgSock_Uninitialized = 0, + DbgSock_Listening = 1, + DbgSock_Connected = 2, + } m_stateDebugSocket; + + bool m_usingSSL; + + static void MulticastDiscoveryRespond(void* arg); + static void MulticastDiscoverySchedule(); + + static void CloseDebuggerSocket(); + static void OnDebuggerTimeout(void* arg); + + static HAL_COMPLETION s_DebuggerTimeoutCompletion; + + SOCK_SOCKET m_SocketDebugListener; + SOCK_SOCKET m_SocketDebugStream; + SOCK_SOCKET m_multicastSocket; + + bool m_fShuttingDown; + + int32_t m_cntSockets; + struct SocketRegisterMap m_socketHandles[SOCKETS_MAX_COUNT]; + + static bool s_initialized; + static bool s_initializedDbg; + static const int32_t c_WellKnownDebugPort = DEBUG_SOCKET_PORT; + static bool s_wirelessInitialized; + static bool s_discoveryInitialized; +}; + +extern Sockets_LWIP_Driver g_Sockets_LWIP_Driver; + +#endif //_SOCKETS_H_ + diff --git a/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/mbedtls.h b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/mbedtls.h new file mode 100644 index 00000000..75f164ce --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/mbedtls.h @@ -0,0 +1,54 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef MBEDTLS_H +#define MBEDTLS_H + +#include + +#include + +#include "mbedtls/platform.h" +#include "mbedtls/net_sockets.h" +#include "mbedtls/ssl.h" +#include "mbedtls/entropy.h" +#include "mbedtls/ctr_drbg.h" +#include "mbedtls/error.h" +#include "mbedtls/certs.h" + +typedef struct mbedTLS_NFContext +{ + mbedtls_entropy_context* entropy; + mbedtls_ctr_drbg_context* ctr_drbg; + mbedtls_ssl_config* conf; + mbedtls_ssl_context* ssl; + mbedtls_net_context* server_fd; + mbedtls_x509_crt* x509_crt; + mbedtls_pk_context* pk; +}mbedTLS_NFContext; + +int net_would_block( const mbedtls_net_context *ctx ); +int mbedtls_net_recv( void *ctx, unsigned char *buf, size_t len ); +int mbedtls_net_send( void *ctx, const unsigned char *buf, size_t len ); +int mbedtls_net_recv_timeout( void *ctx, unsigned char *buf, size_t len, uint32_t timeout ); +void mbedtls_net_free( mbedtls_net_context *ctx ); + +// debug output declaration +void nf_debug( void *ctx, int level, const char *file, int line, const char *str ); + +#ifdef __cplusplus +extern "C" { +#endif + +// function returning the system date and time in Unix Epoch +time_t nf_get_unix_epoch(); + +#ifdef __cplusplus +} +#endif + +#define SOCKET_DRIVER g_Sockets_LWIP_Driver + +#endif diff --git a/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/nf_mbedtls_config.h b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/nf_mbedtls_config.h new file mode 100644 index 00000000..0b33bb1a --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/nf_mbedtls_config.h @@ -0,0 +1,192 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2006-2015, ARM Limited, All Rights Reserved +// See LICENSE file in the project root for full license information. +// + +#ifndef NF_MBEDTLS_CONFIG_H +#define NF_MBEDTLS_CONFIG_H + +#include +#include +#include + +// need to declare this as external to be picked up by mbed TLS platform_time +#ifdef __cplusplus +extern "C" { +#endif + +time_t nf_get_unix_epoch(); + +#ifdef __cplusplus +} +#endif + +/* System support */ +#define MBEDTLS_HAVE_ASM + +#define MBEDTLS_HAVE_TIME + +#define MBEDTLS_HAVE_TIME_DATE + +// need to define this as the alternative to standard time function +#define MBEDTLS_PLATFORM_TIME_MACRO nf_get_unix_epoch + +/* mbed TLS feature support */ +#define MBEDTLS_CIPHER_MODE_CBC +#define MBEDTLS_CIPHER_MODE_CFB +#define MBEDTLS_CIPHER_MODE_CTR +#define MBEDTLS_CIPHER_MODE_OFB +#define MBEDTLS_CIPHER_MODE_XTS +#define MBEDTLS_CIPHER_PADDING_PKCS7 +#define MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS +#define MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN +#define MBEDTLS_CIPHER_PADDING_ZEROS +#define MBEDTLS_REMOVE_ARC4_CIPHERSUITES + +#define MBEDTLS_ECP_DP_SECP192R1_ENABLED +#define MBEDTLS_ECP_DP_SECP224R1_ENABLED +#define MBEDTLS_ECP_DP_SECP256R1_ENABLED +#define MBEDTLS_ECP_DP_SECP384R1_ENABLED +#define MBEDTLS_ECP_DP_SECP521R1_ENABLED +#define MBEDTLS_ECP_DP_SECP192K1_ENABLED +#define MBEDTLS_ECP_DP_SECP224K1_ENABLED +#define MBEDTLS_ECP_DP_SECP256K1_ENABLED +#define MBEDTLS_ECP_DP_BP256R1_ENABLED +#define MBEDTLS_ECP_DP_BP384R1_ENABLED +#define MBEDTLS_ECP_DP_BP512R1_ENABLED +#define MBEDTLS_ECP_DP_CURVE25519_ENABLED +#define MBEDTLS_ECP_DP_CURVE448_ENABLED + +#define MBEDTLS_ECP_NIST_OPTIM +#define MBEDTLS_ECDSA_DETERMINISTIC +#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED +#define MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED +#define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED +#define MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED +#define MBEDTLS_KEY_EXCHANGE_RSA_ENABLED +#define MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED +#define MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED +#define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED +#define MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED +#define MBEDTLS_PK_PARSE_EC_EXTENDED +#define MBEDTLS_ERROR_STRERROR_DUMMY +#define MBEDTLS_GENPRIME +#define MBEDTLS_NO_PLATFORM_ENTROPY +#define MBEDTLS_PK_RSA_ALT_SUPPORT +#define MBEDTLS_PKCS1_V15 +#define MBEDTLS_PKCS1_V21 +#define MBEDTLS_SSL_ENCRYPT_THEN_MAC +#define MBEDTLS_SSL_EXTENDED_MASTER_SECRET +#define MBEDTLS_SSL_FALLBACK_SCSV +#define MBEDTLS_SSL_CBC_RECORD_SPLITTING +#define MBEDTLS_SSL_RENEGOTIATION +#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH +#define MBEDTLS_SSL_PROTO_TLS1 +#define MBEDTLS_SSL_PROTO_TLS1_1 +#define MBEDTLS_SSL_PROTO_TLS1_2 +#define MBEDTLS_SSL_PROTO_DTLS +#define MBEDTLS_SSL_ALPN +#define MBEDTLS_SSL_DTLS_ANTI_REPLAY +#define MBEDTLS_SSL_DTLS_HELLO_VERIFY +#define MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE +#define MBEDTLS_SSL_DTLS_BADMAC_LIMIT +#define MBEDTLS_SSL_SERVER_NAME_INDICATION +#define MBEDTLS_SSL_TRUNCATED_HMAC +#define MBEDTLS_X509_CHECK_KEY_USAGE +#define MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE +#define MBEDTLS_X509_RSASSA_PSS_SUPPORT + +/* mbed TLS modules */ +#define MBEDTLS_AESNI_C +#define MBEDTLS_AES_C +#define MBEDTLS_ARC4_C +#define MBEDTLS_ASN1_PARSE_C + +//#define MBEDTLS_ASN1_WRITE_C + +#define MBEDTLS_BASE64_C + +#define MBEDTLS_BIGNUM_C + +#define MBEDTLS_BLOWFISH_C + +#define MBEDTLS_CAMELLIA_C +#define MBEDTLS_CCM_C + +#define MBEDTLS_CIPHER_C + +#define MBEDTLS_CTR_DRBG_C + +#define MBEDTLS_DES_C +#define MBEDTLS_DHM_C +#define MBEDTLS_ECDH_C + +//#define MBEDTLS_ECDSA_C + +#define MBEDTLS_ECP_C + +#define MBEDTLS_ENTROPY_C + +#define MBEDTLS_ERROR_C + +#define MBEDTLS_GCM_C + +#define MBEDTLS_HKDF_C + +#define MBEDTLS_HMAC_DRBG_C + +#define MBEDTLS_MD_C + +#define MBEDTLS_MD5_C + +#define MBEDTLS_OID_C +#define MBEDTLS_PADLOCK_C + +#define MBEDTLS_PEM_PARSE_C + +#define MBEDTLS_PK_C +#define MBEDTLS_PK_PARSE_C + +#define MBEDTLS_PKCS5_C +#define MBEDTLS_PKCS12_C + +#define MBEDTLS_PLATFORM_C + +#define MBEDTLS_POLY1305_C + +#define MBEDTLS_RIPEMD160_C + +#define MBEDTLS_RSA_C +#define MBEDTLS_SHA1_C +#define MBEDTLS_SHA256_C +#define MBEDTLS_SHA512_C +#define MBEDTLS_SSL_CACHE_C +#define MBEDTLS_SSL_COOKIE_C +#define MBEDTLS_SSL_TICKET_C +#define MBEDTLS_SSL_CLI_C +#define MBEDTLS_SSL_SRV_C +#define MBEDTLS_SSL_TLS_C + +#define MBEDTLS_X509_USE_C +#define MBEDTLS_X509_CRT_PARSE_C +#define MBEDTLS_X509_CRL_PARSE_C + +#define MBEDTLS_X509_CSR_PARSE_C + +#define MBEDTLS_XTEA_C + +#define MBEDTLS_TLS_DEFAULT_ALLOW_SHA1_IN_KEY_EXCHANGE + +//////////////////////////////////////////////////////////////////////////// +// This define depends on the platform having a hardware random generator. +// Requires that a function mbedtls_hardware_poll() exits as explained in mbed TLS documentation. +// Because it's target dependent, the define PLATFORM_HAS_RNG belongs in the target_common header +#if (PLATFORM_HAS_RNG == TRUE) +#define MBEDTLS_ENTROPY_HARDWARE_ALT +#endif +////////////////////////////////////////////////////////////////////////// + +#include + +#endif // NF_MBEDTLS_CONFIG_H diff --git a/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_accept_internal.cpp b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_accept_internal.cpp new file mode 100644 index 00000000..346e7215 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_accept_internal.cpp @@ -0,0 +1,64 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "mbedtls.h" + +int ssl_accept_internal( + int sd, + int contextHandle ) +{ + mbedTLS_NFContext* context; + mbedtls_ssl_context *ssl; + int nonblock = 0; + int ret = SOCK_SOCKET_ERROR; + + // Check contextHandle range + if((contextHandle >= (int)ARRAYSIZE(g_SSL_Driver.ContextArray)) || (contextHandle < 0)) + { + goto error; + } + + context = (mbedTLS_NFContext*)g_SSL_Driver.ContextArray[contextHandle].Context; + ssl = context->ssl; + + // sanity check + if(ssl == NULL) + { + return SOCK_SOCKET_ERROR; + } + + // set socket in network context + context->server_fd->fd = sd; + + // setup internal SSL context and calls to transport layer send, receive and receive with timeout + mbedtls_ssl_set_bio( context->ssl, context->server_fd, mbedtls_net_send, mbedtls_net_recv, mbedtls_net_recv_timeout ); + + // Set non blocking socket + SOCK_ioctl(sd, SOCK_FIONBIO, &nonblock); + + // connection is set up now proceed to SSL handshake + + // perform SSL handshake + while( ( ret = mbedtls_ssl_handshake( context->ssl ) ) != 0 ) + { + if( ret != MBEDTLS_ERR_SSL_WANT_READ && ret != MBEDTLS_ERR_SSL_WANT_WRITE ) + { + // SSL handshake failed + //mbedtls_printf( " failed\n ! mbedtls_ssl_handshake returned -0x%x\n\n", -ret ); + goto error; + } + } + + nonblock = 1; + SOCK_ioctl(sd, SOCK_FIONBIO, &nonblock); + + // Save SSL context against socket + SOCKET_DRIVER.SetSocketSslData(sd, (void*)context); + +error: + + return ret; +} diff --git a/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_add_cert_auth_internal.cpp b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_add_cert_auth_internal.cpp new file mode 100644 index 00000000..24afcc71 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_add_cert_auth_internal.cpp @@ -0,0 +1,50 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "mbedtls.h" + +bool ssl_add_cert_auth_internal( + int contextHandle, + const char* certificate, + int certLength, + const char* certPassword ) +{ + (void)certPassword; + + mbedTLS_NFContext* context; + + // Check contextHandle range + if((contextHandle >= (int)ARRAYSIZE(g_SSL_Driver.ContextArray)) || (contextHandle < 0)) + { + return false; + } + + // Retrieve SSL struct from g_SSL_Driver + // sd should already have been created + context = (mbedTLS_NFContext*)g_SSL_Driver.ContextArray[contextHandle].Context; + + if (context != NULL) + { + ///////////////////////////////////////////////////////////////////////////////////////////////// + // developer notes: // + // this call parses certificates in both string and binary formats // + // when the formart is a string it has to include the terminator otherwise the parse will fail // + ///////////////////////////////////////////////////////////////////////////////////////////////// + if( mbedtls_x509_crt_parse(context->x509_crt, (const unsigned char*)certificate, certLength ) == 0) + { + // add to CA chain + mbedtls_ssl_conf_ca_chain( + context->conf, + context->x509_crt, + NULL ); + + // done + return true; + } + } + + return false; +} diff --git a/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_close_socket_internal.cpp b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_close_socket_internal.cpp new file mode 100644 index 00000000..053492e1 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_close_socket_internal.cpp @@ -0,0 +1,27 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "mbedtls.h" + +int ssl_close_socket_internal( int sd ) +{ + mbedTLS_NFContext* context= (mbedTLS_NFContext*)SOCKET_DRIVER.GetSocketSslData(sd); + + // sanity check + if(context != NULL) + { + mbedtls_ssl_context *ssl = context->ssl; + + // be nice and notify the peer that the connection is being closed + mbedtls_ssl_close_notify(ssl); + + SOCKET_DRIVER.SetSocketSslData(sd, NULL); + } + + SOCK_close( sd ); + + return 0; +} diff --git a/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_connect_internal.cpp b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_connect_internal.cpp new file mode 100644 index 00000000..56112f25 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_connect_internal.cpp @@ -0,0 +1,72 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2006-2015, ARM Limited, All Rights Reserved +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "mbedtls.h" + +int ssl_connect_internal( + int sd, + const char* szTargetHost, + int contextHandle) +{ + mbedTLS_NFContext* context; + int nonblock = 0; + + int ret = SOCK_SOCKET_ERROR; + + // Check contextHandle range + if((contextHandle >= (int)ARRAYSIZE(g_SSL_Driver.ContextArray)) || (contextHandle < 0)) + { + goto error; + } + + // Retrieve SSL struct from g_SSL_Driver + // sd should already have been created + // Now do the SSL negotiation + context = (mbedTLS_NFContext*)g_SSL_Driver.ContextArray[contextHandle].Context; + if (context == NULL) + { + return false; + } + + // set socket in network context + context->server_fd->fd = sd; + + if(szTargetHost != NULL && szTargetHost[0] != 0) + { + if( (ret = mbedtls_ssl_set_hostname( context->ssl, szTargetHost )) != 0 ) + { + // hostname_failed + goto error; + } + } + + // setup internal SSL context and calls to transport layer send, receive and receive with timeout + mbedtls_ssl_set_bio( context->ssl, context->server_fd, mbedtls_net_send, mbedtls_net_recv, mbedtls_net_recv_timeout ); + + SOCK_ioctl(sd, SOCK_FIONBIO, &nonblock); + + // perform SSL handshake + while( ( ret = mbedtls_ssl_handshake( context->ssl ) ) != 0 ) + { + if( ret != MBEDTLS_ERR_SSL_WANT_READ && ret != MBEDTLS_ERR_SSL_WANT_WRITE ) + { + // SSL handshake failed + //mbedtls_printf( " failed\n ! mbedtls_ssl_handshake returned -0x%x\n\n", -ret ); + goto error; + } + } + + nonblock = 1; + SOCK_ioctl(sd, SOCK_FIONBIO, &nonblock); + + // store SSL context in sockets driver + SOCKET_DRIVER.SetSocketSslData(sd, (void*)context); + +error: + return ret; +} diff --git a/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_decode_private_key_internal.cpp b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_decode_private_key_internal.cpp new file mode 100644 index 00000000..255aee3b --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_decode_private_key_internal.cpp @@ -0,0 +1,40 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "mbedtls.h" + +extern void SSL_GetCertDateTime_internal(DATE_TIME_INFO * dt, mbedtls_x509_time * mt ); + +int ssl_decode_private_key_internal( + const unsigned char *key, + size_t keyLength, + const unsigned char *password, + size_t passwordLength) +{ + mbedtls_pk_context pkey; + + int retCode; + + mbedtls_pk_init( &pkey ); + + ///////////////////////////////////////////////////////////////////////////////////////////////// + // developer notes: // + // this call parses certificates in both string and binary formats // + // when the formart is a string it has to include the terminator otherwise the parse will fail // + ///////////////////////////////////////////////////////////////////////////////////////////////// + retCode = mbedtls_pk_parse_key( + &pkey, + key, + keyLength, + password, + passwordLength); + + + // need to free this here + mbedtls_pk_free( &pkey ); + + return retCode; +} diff --git a/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_exit_context_internal.cpp b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_exit_context_internal.cpp new file mode 100644 index 00000000..d6c45e2a --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_exit_context_internal.cpp @@ -0,0 +1,57 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2006-2015, ARM Limited, All Rights Reserved +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "mbedtls.h" + + +bool ssl_exit_context_internal( int contextHandle ) +{ + mbedTLS_NFContext* context; + + // Check contextHandle range + if((contextHandle >= (int)ARRAYSIZE(g_SSL_Driver.ContextArray)) || (contextHandle < 0) || (g_SSL_Driver.ContextArray[contextHandle].Context == NULL)) + { + return false; + } + + context = (mbedTLS_NFContext*)g_SSL_Driver.ContextArray[contextHandle].Context; + if (context == NULL) + { + return false; + } + + mbedtls_pk_free(context->pk); + mbedtls_net_free(context->server_fd); + mbedtls_ctr_drbg_free( context->ctr_drbg ); + mbedtls_entropy_free( context->entropy ); + mbedtls_ssl_config_free( context->conf ); + mbedtls_x509_crt_free(context->x509_crt); + mbedtls_ssl_free(context->ssl); + + // zero memory to wipe any security critical info in RAM + memset(context->ssl, 0, sizeof(mbedtls_ssl_context)); + + // free memory + if(context->pk != NULL) + { + platform_free(context->pk); + } + platform_free(context->server_fd); + platform_free(context->entropy); + platform_free(context->ctr_drbg); + platform_free(context->conf); + platform_free(context->x509_crt); + platform_free(context->ssl); + platform_free(context); + + memset(&g_SSL_Driver.ContextArray[contextHandle], 0, sizeof(g_SSL_Driver.ContextArray[contextHandle])); + + g_SSL_Driver.ContextCount --; + + return true; +} diff --git a/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_generic.cpp b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_generic.cpp new file mode 100644 index 00000000..a272ebb8 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_generic.cpp @@ -0,0 +1,232 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "mbedtls.h" + +#include "lwip/sockets.h" + + +// this one lives in lwIPSocket.cpp +extern int errno; + +int sslRecv( + void *ctx, + unsigned char *buf, + size_t len) +{ + (void)buf; + (void)len; + (void)ctx; + + //int sd = (int)ctx; + + // int ret = socket->recv(buf, len); + + // if (ret == NSAPI_ERROR_WOULD_BLOCK) + // ret = MBEDTLS_ERR_SSL_WANT_READ; + // else if (ret < 0) + // mbedtls_printf("socket.recv() returned %d\n", ret); + + // return ret; + return 0; +} + +// mbedTLS requires a function with this signature, so we are wrapping the call to our debug_printf here +void nf_debug( + void *ctx, + int level, + const char *file, + int line, + const char *str ) +{ + (void)level; + (void)ctx; + (void)file; + (void)line; + + // the following line outputs the source code file name and line number + // for verbose output SWO is overhelmed and output fails at some point + //debug_printf( "%s:%04d: %s", file, line, str ); + + // this is a lightheight version with just the debug messages + debug_printf( "%s", str ); +} + +int net_would_block( const mbedtls_net_context *ctx ) +{ + /* + * Never return 'WOULD BLOCK' on a non-blocking socket + */ + int val = 0; + + if( ( fcntl( ctx->fd, F_GETFL, val) & O_NONBLOCK ) != O_NONBLOCK ) + return( 0 ); + + switch( errno ) + { + #if defined EAGAIN + case EAGAIN: + #endif + #if defined EWOULDBLOCK && EWOULDBLOCK != EAGAIN + case EWOULDBLOCK: + #endif + return( 1 ); + } + + return( 0 ); +} + +int mbedtls_net_recv( + void *ctx, + unsigned char *buf, + size_t len ) +{ + int32_t ret; + int32_t fd = ((mbedtls_net_context *) ctx)->fd; + + if( fd < 0 ) + { + return MBEDTLS_ERR_NET_INVALID_CONTEXT; + } + + ret = (int32_t) read( fd, buf, len ); + + if( ret < 0 ) + { + if(net_would_block((mbedtls_net_context *)ctx) != 0) + { + return MBEDTLS_ERR_SSL_WANT_READ; + } + + if(errno == EPIPE || errno == ECONNRESET) + { + return MBEDTLS_ERR_NET_CONN_RESET; + } + + if(errno == EINTR) + { + return MBEDTLS_ERR_SSL_WANT_READ; + } + + return MBEDTLS_ERR_NET_RECV_FAILED; + } + + return ret; +} + +int mbedtls_net_send( + void *ctx, + const unsigned char *buf, + size_t len ) +{ + int32_t ret; + int fd = ((mbedtls_net_context *) ctx)->fd; + + if( fd < 0 ) + { + return MBEDTLS_ERR_NET_INVALID_CONTEXT; + } + + ret = (int32_t) write(fd, buf, len); + + if( ret < 0 ) + { + if(net_would_block((mbedtls_net_context *)ctx) != 0) + { + return MBEDTLS_ERR_SSL_WANT_WRITE; + } + + if(errno == EPIPE || errno == ECONNRESET) + { + return MBEDTLS_ERR_NET_CONN_RESET; + } + + if(errno == EINTR) + { + return MBEDTLS_ERR_SSL_WANT_WRITE; + } + + return MBEDTLS_ERR_NET_SEND_FAILED; + } + + return ret; +} + +int mbedtls_net_recv_timeout( + void *ctx, + unsigned char *buf, + size_t len, + uint32_t timeout ) +{ + int ret; + struct timeval tv; + fd_set read_fds; + int fd = ((mbedtls_net_context *) ctx)->fd; + + if( fd < 0 ) + return( MBEDTLS_ERR_NET_INVALID_CONTEXT ); + + FD_ZERO( &read_fds ); + FD_SET( fd, &read_fds ); + + tv.tv_sec = timeout / 1000; + tv.tv_usec = ( timeout % 1000 ) * 1000; + + ret = select( fd + 1, &read_fds, NULL, NULL, timeout == 0 ? NULL : &tv ); + + /* Zero fds ready means we timed out */ + if( ret == 0 ) + return( MBEDTLS_ERR_SSL_TIMEOUT ); + + if( ret < 0 ) + { + #if ( defined(_WIN32) || defined(_WIN32_WCE) ) && !defined(EFIX64) && \ + !defined(EFI32) + if( WSAGetLastError() == WSAEINTR ) + return( MBEDTLS_ERR_SSL_WANT_READ ); + #else + if( errno == EINTR ) + return( MBEDTLS_ERR_SSL_WANT_READ ); + #endif + + return( MBEDTLS_ERR_NET_RECV_FAILED ); + } + + /* This call will not block */ + return( mbedtls_net_recv( ctx, buf, len ) ); +} + +// Gracefully closes the connection +void mbedtls_net_free( mbedtls_net_context *ctx ) +{ + if( ctx->fd == -1 ) + return; + + shutdown( ctx->fd, 2 ); + close( ctx->fd ); + + ctx->fd = -1; +} + +// get Unix Epoch time from HAL SystemTime +time_t nf_get_unix_epoch() +{ + struct tm time; + SYSTEMTIME systemTime; + + // get HAL time in SYSTEMTIME format + HAL_Time_ToSystemTime(HAL_Time_CurrentDateTime(false), &systemTime); + + // fill in the tm struct + time.tm_sec = systemTime.wSecond; + time.tm_min = systemTime.wMinute; + time.tm_hour = systemTime.wHour; + time.tm_mday = systemTime.wDay; + time.tm_mon = systemTime.wMonth - 1; + time.tm_year = systemTime.wYear - 1900; + + return mktime(&time); +} diff --git a/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_generic_init_internal.cpp b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_generic_init_internal.cpp new file mode 100644 index 00000000..47c4bdee --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_generic_init_internal.cpp @@ -0,0 +1,310 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2006-2015, ARM Limited, All Rights Reserved +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "mbedtls.h" +#include "mbedtls/debug.h" + +bool ssl_generic_init_internal( + int sslMode, + int sslVerify, + const char* certificate, + int certLength, + const uint8_t* privateKey, + int privateKeyLength, + const char* password, + int passwordLength, + int& contextHandle, + bool isServer ) +{ + (void)sslMode; + + int minVersion = MBEDTLS_SSL_MINOR_VERSION_3; + int maxVersion = MBEDTLS_SSL_MINOR_VERSION_1; + int sslContexIndex = -1; + int authMode = MBEDTLS_SSL_VERIFY_NONE; + int endpoint = 0; + int ret = 0; + + mbedtls_x509_crt* ownCertificate = NULL; + + // we only have one CA root bundle, so this is fixed to 0 + uint32_t configIndex = 0; + + /////////////////////// + mbedTLS_NFContext* context; + + for(uint32_t i=0; iserver_fd = (mbedtls_net_context*)platform_malloc(sizeof(mbedtls_net_context)); + if(context->server_fd == NULL) + { + goto error; + } + + if(isServer) + { + endpoint = MBEDTLS_SSL_IS_SERVER; + } + else + { + endpoint = MBEDTLS_SSL_IS_CLIENT; + } + + // create and init CTR_DRBG + // this needs to be freed in ssl_exit_context_internal + context->ctr_drbg = (mbedtls_ctr_drbg_context*)platform_malloc(sizeof(mbedtls_ctr_drbg_context)); + if(context->ctr_drbg == NULL) + { + goto error; + } + mbedtls_ctr_drbg_init( context->ctr_drbg ); + + // create and init SSL context + // this needs to be freed in ssl_exit_context_internal + context->ssl = (mbedtls_ssl_context*)platform_malloc(sizeof(mbedtls_ssl_context)); + if(context->ssl == NULL) + { + goto error; + } + mbedtls_ssl_init(context->ssl); + + // create and init SSL configuration + // this needs to be freed in ssl_exit_context_internal + context->conf = (mbedtls_ssl_config*)platform_malloc(sizeof(mbedtls_ssl_config)); + if(context->conf == NULL) + { + goto error; + } + + mbedtls_ssl_config_init( context->conf ); + + // create and init X509 CRT + // this needs to be freed in ssl_exit_context_internal + context->x509_crt = (mbedtls_x509_crt*)platform_malloc(sizeof(mbedtls_x509_crt)); + if(context->x509_crt == NULL) + { + goto error; + } + mbedtls_x509_crt_init( context->x509_crt ); + + // create and init entropy context + // this needs to be freed in ssl_exit_context_internal + context->entropy = (mbedtls_entropy_context*)platform_malloc(sizeof(mbedtls_entropy_context)); + if(context->entropy == NULL) + { + goto error; + } + mbedtls_entropy_init( context->entropy ); + + // TODO: review if we can add some instance-unique data to the custom argument below + if( mbedtls_ctr_drbg_seed( context->ctr_drbg, mbedtls_entropy_func, context->entropy, NULL, 0 ) != 0 ) + { + // ctr_drbg_seed_failed + goto error; + } + + if( mbedtls_ssl_config_defaults( context->conf, + endpoint, + MBEDTLS_SSL_TRANSPORT_STREAM, + MBEDTLS_SSL_PRESET_DEFAULT ) != 0 ) + { + // ssl_config_defaults_failed + goto error; + } + + // figure out the min and max protocol version to support + // sanity check for none, application has to set the supported protocols + if((SslProtocols)sslMode == SslProtocols_None) + { + goto error; + } + + // find minimum version + if(sslMode & (SslProtocols_TLSv11 | SslProtocols_TLSv1)) + { + minVersion = MBEDTLS_SSL_MINOR_VERSION_2; + } + if(sslMode & SslProtocols_TLSv1) + { + minVersion = MBEDTLS_SSL_MINOR_VERSION_1; + } + mbedtls_ssl_conf_min_version( + context->conf, MBEDTLS_SSL_MAJOR_VERSION_3, + minVersion ); + + // find maximum version + if(sslMode & (SslProtocols_TLSv12 | SslProtocols_TLSv11)) + { + maxVersion = MBEDTLS_SSL_MINOR_VERSION_2; + } + if(sslMode & SslProtocols_TLSv12) + { + maxVersion = MBEDTLS_SSL_MINOR_VERSION_3; + } + mbedtls_ssl_conf_max_version( + context->conf, MBEDTLS_SSL_MAJOR_VERSION_3, + maxVersion ); + + // configure random generator + mbedtls_ssl_conf_rng( context->conf, mbedtls_ctr_drbg_random, context->ctr_drbg ); + + // CA root certs from store, if available + if(g_TargetConfiguration.CertificateStore->Count > 0) + { + ///////////////////////////////////////////////////////////////////////////////////////////////// + // developer notes: // + // don't care about failure in processing the CA cert bundle // + // the outcome is that the CA certs won't be loaded into the trusted CA chain // + // this call parses certificates in both string and binary formats // + // when the formart is a string it has to include the terminator otherwise the parse will fail // + ///////////////////////////////////////////////////////////////////////////////////////////////// + mbedtls_x509_crt_parse( + context->x509_crt, + (const unsigned char*)g_TargetConfiguration.CertificateStore->Certificates[configIndex]->Certificate, + g_TargetConfiguration.CertificateStore->Certificates[configIndex]->CertificateSize ); + + } + + // parse "own" certificate if passed + if(certificate != NULL && certLength > 0) + { + // create and init private key context + // this needs to be freed in ssl_exit_context_internal + context->pk = (mbedtls_pk_context*)platform_malloc(sizeof(mbedtls_pk_context)); + if(context->pk == NULL) + { + goto error; + } + + mbedtls_pk_init( context->pk ); + + // is there a private key? + if(privateKey != NULL && privateKeyLength > 0) + { + + if( mbedtls_pk_parse_key( + context->pk, + privateKey, + privateKeyLength, + (const unsigned char *)password, + passwordLength) < 0) + { + // private key parse failed + goto error; + } + } + + // parse certificate + ownCertificate = (mbedtls_x509_crt*)platform_malloc(sizeof(mbedtls_x509_crt)); + if(ownCertificate == NULL) + { + goto error; + } + + mbedtls_x509_crt_init( ownCertificate ); + + if( mbedtls_x509_crt_parse( ownCertificate, (const unsigned char *) certificate, certLength ) ) + { + // failed parsing own certificate failed + goto error; + } + + if( mbedtls_ssl_conf_own_cert( context->conf, ownCertificate, context->pk ) ) + { + // configuring own certificate failed + goto error; + } + + } + else + { + // no PK, need to set it to NULL + context->pk = NULL; + } + + mbedtls_ssl_conf_ca_chain( context->conf, context->x509_crt, NULL ); + + // set certificate verification + // the current options provided by mbed TLS are only verify or don't verify + if((SslVerification)sslVerify == SslVerification_CertificateRequired) + { + authMode = MBEDTLS_SSL_VERIFY_REQUIRED; + } + mbedtls_ssl_conf_authmode( context->conf, authMode ); + + // setup debug stuff + // only required if output debug is enabled in mbedtls_config.h + #ifdef MBEDTLS_DEBUG_C + mbedtls_debug_set_threshold( MBEDTLS_DEBUG_THRESHOLD ); + mbedtls_ssl_conf_dbg( context->conf, nf_debug, stdout ); + #endif + + ret = mbedtls_ssl_setup( context->ssl, context->conf ); + if( ret != 0 ) + { + // ssl_setup_failed + goto error; + } + + ////////////////////////////////////// + + g_SSL_Driver.ContextArray[sslContexIndex].Context = context; + g_SSL_Driver.ContextCount++; + + contextHandle = sslContexIndex; + + return true; + +error: + mbedtls_pk_free(context->pk); + mbedtls_net_free(context->server_fd); + mbedtls_ctr_drbg_free( context->ctr_drbg ); + mbedtls_entropy_free( context->entropy ); + mbedtls_x509_crt_free(context->x509_crt); + mbedtls_ssl_config_free( context->conf ); + mbedtls_ssl_free(context->ssl); + + // check for any memory allocation that needs to be freed before exiting + if(context->ssl != NULL) platform_free(context->ssl); + if(context->conf != NULL) platform_free(context->conf); + if(context->entropy != NULL) platform_free(context->entropy); + if(context->ctr_drbg != NULL) platform_free(context->ctr_drbg); + if(context->server_fd != NULL) platform_free(context->server_fd); + if(context->x509_crt != NULL) platform_free(context->x509_crt); + if(context->pk != NULL) platform_free(context->pk); + + if(ownCertificate != NULL) + { + mbedtls_x509_crt_free( ownCertificate ); + platform_free(ownCertificate); + } + if(context->pk != NULL) + { + platform_free(context); + } + + return false; +} diff --git a/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_initialize_internal.cpp b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_initialize_internal.cpp new file mode 100644 index 00000000..7450d355 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_initialize_internal.cpp @@ -0,0 +1,16 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2006-2015, ARM Limited, All Rights Reserved +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "mbedtls.h" + +bool ssl_initialize_internal() +{ + memset(&g_SSL_Driver, 0, sizeof(g_SSL_Driver)); + + return true; +} diff --git a/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_parse_certificate_internal.cpp b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_parse_certificate_internal.cpp new file mode 100644 index 00000000..8169de41 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_parse_certificate_internal.cpp @@ -0,0 +1,71 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "mbedtls.h" + +void SSL_GetCertDateTime_internal( + DATE_TIME_INFO * dt, + mbedtls_x509_time * mt ) +{ + dt->year = mt->year; + dt->month = mt->mon; + dt->day = mt->day; + dt->hour = mt->hour; + dt->minute = mt->min; + dt->second = mt->sec; + + dt->dlsTime = 0; + dt->tzOffset = 0; +} + +bool ssl_parse_certificate_internal( + void * certificate, + size_t size, + void* pwd, + void* x509CertData) +{ + (void)pwd; + + int ret; + X509CertData* x509 = (X509CertData*)x509CertData; + + mbedtls_x509_crt cacert; + mbedtls_x509_crt_init(&cacert); + + ///////////////////////////////////////////////////////////////////////////////////////////////// + // developer notes: // + // this call parses certificates in both string and binary formats // + // when the formart is a string it has to include the terminator otherwise the parse will fail // + ///////////////////////////////////////////////////////////////////////////////////////////////// + ret = mbedtls_x509_crt_parse( + &cacert, + (const unsigned char *)certificate, + size); + if(ret < 0) + { + return false; + } + + mbedtls_x509_dn_gets( + x509->Issuer, + sizeof(x509->Issuer)-1, + &cacert.issuer ); + + mbedtls_x509_dn_gets( + x509->Subject, + sizeof(x509->Subject)-1, + &cacert.subject ); + + SSL_GetCertDateTime_internal( + &x509->EffectiveDate, + &cacert.valid_from ); + + SSL_GetCertDateTime_internal( + &x509->ExpirationDate, + &cacert.valid_to ); + + return true; +} diff --git a/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_pending_internal.cpp b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_pending_internal.cpp new file mode 100644 index 00000000..2fafa75d --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_pending_internal.cpp @@ -0,0 +1,22 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include "mbedtls.h" + +int ssl_pending_internal( int sd ) +{ + mbedTLS_NFContext* context= (mbedTLS_NFContext*)SOCKET_DRIVER.GetSocketSslData(sd); + mbedtls_ssl_context *ssl = context->ssl; + + // sanity check + if(ssl == NULL) + { + return SOCK_SOCKET_ERROR; + } + + return mbedtls_ssl_check_pending(ssl); +} diff --git a/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_read_internal.cpp b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_read_internal.cpp new file mode 100644 index 00000000..1d8254b1 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_read_internal.cpp @@ -0,0 +1,30 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "mbedtls.h" + +int ssl_read_internal( + int sd, + char* data, + size_t size ) +{ + mbedTLS_NFContext* context= (mbedTLS_NFContext*)SOCKET_DRIVER.GetSocketSslData(sd); + mbedtls_ssl_context *ssl = context->ssl; + + // sanity check + if(ssl == NULL) + { + return SOCK_SOCKET_ERROR; + } + + int ret = mbedtls_ssl_read(ssl, (unsigned char *)(data), size); + if ( ret < 0 ) + { + return 0; + } + + return ret; +} diff --git a/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_uninitialize_internal.cpp b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_uninitialize_internal.cpp new file mode 100644 index 00000000..fe044c2e --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/mbedTLS/ssl_uninitialize_internal.cpp @@ -0,0 +1,28 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "mbedtls.h" + +// TODO if and when implementing store certificate +// extern volatile int ssl_x509_store_ctx_idx; + +bool ssl_uninitialize_internal() +{ + bool result = true; + + for(uint32_t i = 0; i +#include "mbedtls.h" + +int ssl_write_internal( + int sd, + const char* data, + size_t req_len) +{ + int ret; + + mbedTLS_NFContext* context= (mbedTLS_NFContext*)SOCKET_DRIVER.GetSocketSslData(sd); + mbedtls_ssl_context *ssl = context->ssl; + + // sanity check + if(ssl == NULL) + { + return SOCK_SOCKET_ERROR; + } + + // Loop until all data has been sent or error + size_t req_offset = 0; + do + { + ret = mbedtls_ssl_write( ssl, (const unsigned char *)(data + req_offset), req_len - req_offset); + if (ret > 0) + { + req_offset += static_cast(ret); + } + } + while( req_offset < req_len && + (ret > 0 || + ret == MBEDTLS_ERR_SSL_WANT_WRITE || + ret == MBEDTLS_ERR_SSL_WANT_READ) ); + + if (ret < 0) + { + //mbedtls_printf("mbedtls_ssl_write() returned -0x%04X\n", -ret); + return 0; + } + + return req_len; +} diff --git a/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/ssl.cpp b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/ssl.cpp new file mode 100644 index 00000000..84bfa0bd --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/ssl.cpp @@ -0,0 +1,241 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include + +SSL_Driver g_SSL_Driver; + +// Flag to postpone init until after heap has been cleared +// in tinyhal.cpp +static bool s_InitDone = false; + +bool SSL_Initialize() +{ + NATIVE_PROFILE_PAL_COM(); + + memset(&g_SSL_Driver, 0, sizeof(g_SSL_Driver)); + + return true; +} + +bool SSL_Uninitialize() +{ + NATIVE_PROFILE_PAL_COM(); + + for(uint32_t i = 0; i +#include + +struct SSL_Driver +{ + static const int c_MaxSslContexts = SOCKETS_MAX_COUNT; + + //--// + + struct SSL_Context + { + void * Context; + }; + + SSL_Context ContextArray[c_MaxSslContexts]; + int32_t ContextCount; +}; + +extern SSL_Driver g_SSL_Driver; + +#endif // _NANO_SSL_H_ diff --git a/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/ssl_functions.h b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/ssl_functions.h new file mode 100644 index 00000000..7bf171a8 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/ssl_functions.h @@ -0,0 +1,85 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#ifndef SSL_FUNCTIONS_H +#define SSL_FUNCTIONS_H + +#include + +// Keep these in sync with SslProtocols in System.Net + +/////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH System.Net.Security.SslProtocols (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////// +enum SslProtocols +{ + SslProtocols_None = 0x00, + SslProtocols_TLSv1 = 0x10, + SslProtocols_TLSv11 = 0x20, + SslProtocols_TLSv12 = 0x40, +}; + +////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH System.Net.Security.SslVerification (in managed code) !!! // +////////////////////////////////////////////////////////////////////////////////////// +enum SslVerification +{ + SslVerification_Invalid = 0, + SslVerification_NoVerification = 1, + SslVerification_VerifyPeer = 2, + SslVerification_CertificateRequired = 4, + SslVerification_VerifyClientOnce = 8, +}; + +bool ssl_parse_certificate_internal( + void* buf, + size_t size, + void* pwd, + void* x509 ); +int ssl_decode_private_key_internal( + const unsigned char *key, + size_t keyLength, + const unsigned char *pwd, + size_t pwdLength ); +int ssl_connect_internal( + int sd, + const char* szTargetHost, + int contextHandle); +int ssl_accept_internal( + int socket, + int contextHandle ); +int ssl_read_internal( + int socket, + char* data, + size_t size ); +int ssl_write_internal( + int socket, + const char* data, + size_t size); +int ssl_close_socket_internal( int sd ); +int ssl_pending_internal( int sd ); +bool ssl_exit_context_internal( int contextHandle ); +bool ssl_generic_init_internal( + int sslMode, + int sslVerify, + const char* certificate, + int certLength, + const uint8_t* privateKey, + int privateKeyLength, + const char* password, + int passwordLength, + int& contextHandle, + bool isServer ); +bool ssl_initialize_internal(); +bool ssl_uninitialize_internal(); +bool ssl_add_cert_auth_internal( + int contextHandle, + const char* certificate, + int certLength, + const char* certPassword ); + +#endif // SSL_FUNCTIONS_H diff --git a/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/ssl_stubs.cpp b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/ssl_stubs.cpp new file mode 100644 index 00000000..1025cc34 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/ssl_stubs.cpp @@ -0,0 +1,212 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "nanoHal.h" + +//--// + +extern "C" +{ +void ssl_rand_seed(const void *seed, int length) +{ + (void)seed; + (void)length; +} +} + +__nfweak bool SSL_Initialize() +{ + NATIVE_PROFILE_PAL_COM(); + return FALSE; +} + +__nfweak bool SSL_Uninitialize() +{ + NATIVE_PROFILE_PAL_COM(); + return TRUE; +} + +__nfweak bool SSL_ServerInit( + int sslMode, + int sslVerify, + const char* certificate, + int certLength, + const uint8_t* privateKey, + int privateKeyLength, + const char* password, + int passwordLength, + int& contextHandle ) +{ + (void)sslMode; + (void)sslVerify; + (void)certificate; + (void)certLength; + (void)privateKey; + (void)privateKeyLength; + (void)password; + (void)passwordLength; + (void)contextHandle; + + NATIVE_PROFILE_PAL_COM(); + + return TRUE; +} + +__nfweak bool SSL_ClientInit( + int sslMode, + int sslVerify, + const char* certificate, + int certLength, + const uint8_t* privateKey, + int privateKeyLength, + const char* password, + int passwordLength, + int& contextHandle ) +{ + (void)sslMode; + (void)sslVerify; + (void)certificate; + (void)certLength; + (void)privateKey; + (void)privateKeyLength; + (void)password; + (void)passwordLength; + (void)contextHandle; + + NATIVE_PROFILE_PAL_COM(); + + return TRUE; +} + +__nfweak bool SSL_AddCertificateAuthority( + int contextHandle, + const char* certificate, + int certLength, + const char* certPassword ) +{ + (void)contextHandle; + (void)certificate; + (void)certLength; + (void)certPassword; + + NATIVE_PROFILE_PAL_COM(); + + return TRUE; +} + +__nfweak bool SSL_ExitContext( int contextHandle ) +{ + (void)contextHandle; + + NATIVE_PROFILE_PAL_COM(); + + return TRUE; +} + +__nfweak int SSL_Accept( + SOCK_SOCKET socket, + int contextHandle ) +{ + (void)socket; + (void)contextHandle; + + NATIVE_PROFILE_PAL_COM(); + + return 0; +} + +__nfweak int SSL_Connect( + SOCK_SOCKET socket, + const char* szTargetHost, + int contextHandle ) +{ + (void)socket; + (void)szTargetHost; + (void)contextHandle; + + NATIVE_PROFILE_PAL_COM(); + + return 0; +} + +__nfweak int SSL_Write( + SOCK_SOCKET socket, + const char* data, + size_t size ) +{ + (void)socket; + (void)data; + (void)size; + + NATIVE_PROFILE_PAL_COM(); + + return 0; +} + +__nfweak int SSL_Read( + SOCK_SOCKET socket, + char* data, + size_t size ) +{ + (void)socket; + (void)data; + (void)size; + + NATIVE_PROFILE_PAL_COM(); + + return 0; +} + +__nfweak int SSL_CloseSocket( SOCK_SOCKET socket ) +{ + (void)socket; + + NATIVE_PROFILE_PAL_COM(); + + return 0; +} + +__nfweak bool SSL_ParseCertificate( + const char* certificate, + size_t certLength, + const char* password, + X509CertData* certData ) +{ + (void)certificate; + (void)certLength; + (void)password; + (void)certData; + + NATIVE_PROFILE_PAL_COM(); + + return TRUE; +} + +__nfweak int SSL_DecodePrivateKey( + const unsigned char *key, + size_t keyLength, + const unsigned char *pwd, + size_t pwdLength ) +{ + (void)key; + (void)keyLength; + (void)pwd; + (void)pwdLength; + + NATIVE_PROFILE_PAL_COM(); + + return -1; +} + +__nfweak int SSL_DataAvailable( SOCK_SOCKET socket ) +{ + (void)socket; + + NATIVE_PROFILE_PAL_COM(); + + return 0; +} + diff --git a/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/ssl_types.h b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/ssl_types.h new file mode 100644 index 00000000..53960da5 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/COM/sockets/ssl/ssl_types.h @@ -0,0 +1,15 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef SSL_TYPES_H +#define SSL_TYPES_H + + +#define NANOCLR_SSL_STRLEN hal_strlen_s +#define TINYCLR_SSL_STRNCPY(a,b,c) hal_strncpy_s(a,c+1,b,c) +#define NANOCLR_SSL_STRNCPY(a,b) hal_strcpy_s(a,hal_strlen_s(b)+1,b) + +#endif // SSL_TYPES_H diff --git a/source/native/nf-interpreter/src/PAL/Double/nanoPAL_NativeDouble.cpp b/source/native/nf-interpreter/src/PAL/Double/nanoPAL_NativeDouble.cpp new file mode 100644 index 00000000..99d96ab1 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/Double/nanoPAL_NativeDouble.cpp @@ -0,0 +1,223 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "stdafx.h" +#include "nanoPAL_NativeDouble.h" + +#include + +#ifdef WIN32 +#include + +#define __isnand _isnan +#define __isinfd(x) (!_finite(x)) + +inline int __signbitd(double x) +{ + unsigned char *ptr = (unsigned char*) &x; + return (*(ptr + (sizeof(double) - 1)) & 0x80) != 0; +} + +#define rint(x) floor((x) + 0.5) +#define remainder(x,y) ((x) - ((y) * rint((x) / (y)))) + +#define isgreater(param0,param1) (param0 > param1) +#define isless(param0,param1) (param0 < param1) + +#elif defined(__GNUC__) + +#if !defined( isgreater ) +#define isgreater __builtin_isgreater +#endif + +#if !defined( isless ) +#define isless __builtin_isless +#endif + +#if !defined( __isnand ) +#define __isnand __builtin_isnan +#endif + +#if !defined( __isinfd ) +#define __isinfd __builtin_isinf +#endif + +#if !defined( __signbitd ) +#define __signbitd __builtin_signbit +#endif + +#endif + + + +using namespace System; +// Summary: +// Compares this instance to a specified double-precision floating-point number +// and returns an integer that indicates whether the value of this instance +// is less than, equal to, or greater than the value of the specified double-precision +// floating-point number. +// +// Parameters: +// value: +// A double-precision floating-point number to compare. +// +// Returns: +// A signed number indicating the relative values of this instance and value. +// Return Value Description +// Less than zero +// This instance is less than value. -or- +// This instance is not a number (System.Double.NaN) and value is a number. +// Zero +// This instance is equal to value. -or- +// Both this instance and value are not a number (System.Double.NaN), +// System.Double.PositiveInfinity, or System.Double.NegativeInfinity. +// Greater than zero +// This instance is greater than value. -or- +// This instance is a number and value is not a number (System.Double.NaN). +int32_t System::Double::CompareTo( double d, double val ) +{ + if (__isnand(d)) + { + // Instance is not a number + if (__isnand(val)) + { + // value is not a number + return 0; + } + else + { + //value is a number + return -1; + } + } + else + { + // Instance is a number + if (__isnand(val)) + { + // value is not a number + return 1; + } + } + + if ( __isinfd(d) && __isinfd(val) ) + { + // both are Infinity + return 0; + } + + if (isgreater(d,val)) + { + // this instance is greater than value + return 1; + } + + if (isless(d,val)) + { + // this instance is less than value + return -1; + } + + // assume values are equal as all other options have been checked. + return 0; +} + +// +// Summary: +// Returns a value indicating whether the specified number evaluates to negative +// or positive infinity +// +// Parameters: +// d: +// A double-precision floating-point number. +// +// Returns: +// true if d evaluates to System.Double.PositiveInfinity or System.Double.NegativeInfinity; +// otherwise, false. +bool System::Double::IsInfinity( double d ) +{ + if(__isnand(d)) + return false; + + /* Return 1 if __x is infinite, 0 otherwise */ + /* Used by isinf macro */ + bool retVal = __isinfd(d); + return retVal; +} + +// +// Summary: +// Returns a value indicating whether the specified number evaluates to a value +// that is not a number (System.Double.NaN). +// +// Parameters: +// d: +// A double-precision floating-point number. +// +// Returns: +// true if d evaluates to System.Double.NaN; otherwise, false. +bool System::Double::IsNaN( double d ) +{ + /* Return 1 if __x is a NaN, 0 otherwise */ + /* Used by isnan macro */ + bool retVal = __isnand(d) != 0; + return retVal; +} + +// +// Summary: +// Returns a value indicating whether the specified number evaluates to negative +// infinity. +// +// Parameters: +// d: +// A double-precision floating-point number. +// +// Returns: +// true if d evaluates to System.Double.NegativeInfinity; otherwise, false. +bool System::Double::IsNegativeInfinity( double d ) +{ + if(__isnand(d) != 0) + return false; + + /* Return signbit of __x */ + /* Used by signbit macro */ + int8_t signBit = __signbitd(d); + + /* Return 1 if __x is infinite, 0 otherwise */ + /* Used by isinf macro */ + int8_t infiniteBit = __isinfd(d) != 0; + + bool retVal = (signBit != 0) && (infiniteBit != 0); + return retVal; +} +// +// Summary: +// Returns a value indicating whether the specified number evaluates to positive +// infinity. +// +// Parameters: +// d: +// A double-precision floating-point number. +// +// Returns: +// true if d evaluates to System.Double.PositiveInfinity; otherwise, false. +bool System::Double::IsPositiveInfinity( double d ) +{ + if(__isnand(d) != 0) + return false; + + /* Return signbit of __x */ + /* Used by signbit macro */ + int8_t signBit = __signbitd(d); + + /* Return 1 if __x is infinite, 0 otherwise */ + /* Used by isinf macro */ + int8_t infiniteBit = __isinfd(d); + + bool retVal = (signBit == 0) && (infiniteBit != 0); + return retVal; +} diff --git a/source/native/nf-interpreter/src/PAL/Events/nanoPAL_Events_driver.cpp b/source/native/nf-interpreter/src/PAL/Events/nanoPAL_Events_driver.cpp new file mode 100644 index 00000000..655bebdd --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/Events/nanoPAL_Events_driver.cpp @@ -0,0 +1,60 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include + +PalEventDriver g_palEventDriver; + +bool PalEventDriver::s_initialized = FALSE; + +HRESULT PalEventDriver::Initialize() +{ + if (!g_palEventDriver.s_initialized) + { + g_palEventDriver.listenerList.Initialize(); + PalEventDriver::s_initialized = TRUE; + } + + return S_OK; +} + +HRESULT PalEventDriver::Uninitialize() +{ + if (PalEventDriver::s_initialized) + { + PalEventDriver::s_initialized = FALSE; + + /// Remove all nodes. + g_palEventDriver.listenerList.Initialize(); + } + + return S_OK; +} + +HRESULT PalEventDriver::PostEvent(uint32_t e, uint32_t param) +{ + PalEventListener *listener = g_palEventDriver.listenerList.FirstNode(); + + while(listener->Next() != NULL) + { + if (listener->m_eventMask & e) + { + listener->m_palEventListener(e, param); + } + + listener = listener->Next(); + } + + return S_OK; +} + +HRESULT PalEventDriver::EnlistListener(PalEventListener* listener) +{ + listener->Initialize(); + g_palEventDriver.listenerList.LinkAtBack(listener); + + return S_OK; +} diff --git a/source/native/nf-interpreter/src/PAL/Events/nanoPAL_Events_functions.cpp b/source/native/nf-interpreter/src/PAL/Events/nanoPAL_Events_functions.cpp new file mode 100644 index 00000000..7e0c3628 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/Events/nanoPAL_Events_functions.cpp @@ -0,0 +1,27 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include + +HRESULT PalEvent_Initialize() +{ + return g_palEventDriver.Initialize(); +} + +HRESULT PalEvent_Uninitialize() +{ + return g_palEventDriver.Uninitialize(); +} + +HRESULT PalEvent_Post(unsigned int e, unsigned int param) +{ + return g_palEventDriver.PostEvent(e, param); +} + +HRESULT PalEvent_Enlist(PalEventListener* listener) +{ + return g_palEventDriver.EnlistListener(listener); +} diff --git a/source/native/nf-interpreter/src/PAL/Include/nanoCRT.h b/source/native/nf-interpreter/src/PAL/Include/nanoCRT.h new file mode 100644 index 00000000..145cf42b --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/Include/nanoCRT.h @@ -0,0 +1,21 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _NANOCRT_DECL_H_ +#define _NANOCRT_DECL_H_ 1 + +#if defined(PLATFORM_EMULATED_FLOATINGPOINT) +int hal_snprintf_float( char* buffer, size_t len, const char* format, int32_t f ); +int hal_snprintf_double( char* buffer, size_t len, const char* format, int64_t& d ); +#else +int hal_snprintf_float( char* buffer, size_t len, const char* format, float f ); +int hal_snprintf_double( char* buffer, size_t len, const char* format, double d ); +#endif + +// Compares 2 ASCII strings case insensitive. Always defined in our code ( nanoCRT.cpp ) +int hal_stricmp( const char * dst, const char * src ); + +#endif // _NANOCRT_DECL_H_ diff --git a/source/native/nf-interpreter/src/PAL/Include/nanoPAL.h b/source/native/nf-interpreter/src/PAL/Include/nanoPAL.h new file mode 100644 index 00000000..0fe17e35 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/Include/nanoPAL.h @@ -0,0 +1,255 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _NANOPAL_H_ +#define _NANOPAL_H_ 1 + +//#include + +#include +#include +#include +#include +#include +#include +#include +#include + + + + + +#include +// +#include + + + + + + + + + + +// +//#include + +//#include (must be before events_decl.h) + + + + + + + + + + + + + + +//#include + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +//#include + +//#include + +// This function returns location of the CLR heap. +void HeapLocation(unsigned char*& BaseAddress, unsigned int& SizeInBytes); + + + + +// +//#include +// +//#include +//#include +//#include +// +//#include +// + + +// + +//#include + +// +// !!! KEEP IN SYNC WITH Microsoft.SPOT.Hardware.PowerLevel !!! +// +enum POWER_LEVEL +{ + POWER_LEVEL__HIGH_POWER = 0x10, + POWER_LEVEL__MID_POWER = 0x20, + POWER_LEVEL__LOW_POWER = 0x30, +}; + + +//#include +//#include + +//#include + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +//#include + + +//#include + +#if defined(PLATFORM_ARM) || defined(PLATFORM_ESP32) + +#define strcpy DoNotUse_*strcpy [] +#define strncpy DoNotUse_*strcpy [] +#define strlen DoNotUse_*strlen [] +#define strncmp DoNotUse_*strncmp [] + +int hal_strcpy_s ( char* strDst, size_t sizeInBytes, const char* strSrc ); +int hal_strncpy_s( char* strDst, size_t sizeInBytes, const char* strSrc, size_t count ); +size_t hal_strlen_s (const char * str); +int hal_strncmp_s( const char* str1, const char* str2, size_t num ); + +#elif defined(_WIN32) + +int hal_vprintf( const char* format, va_list arg ); +int hal_vfprintf( COM_HANDLE stream, const char* format, va_list arg ); +int hal_snprintf( char* buffer, size_t len, const char* format, ... ); +int hal_vsnprintf( char* buffer, size_t len, const char* format, va_list arg ); + +#define hal_strcpy_s(strDst, sizeInBytes, strSrc) strcpy_s(strDst, sizeInBytes, strSrc) +#define hal_strncpy_s(strDst, sizeInBytes, strSrc, count) strncpy_s(strDst, sizeInBytes, strSrc, count) +#define hal_strlen_s(str) strlen(str) +#define hal_strncmp_s(str1, str2, num) strncmp(str1, str2, num) + +#else +!ERROR +#endif + + +//#include +//#include +//#include +//#include +//#include +// +#include "TargetPAL_BlockStorage.h" + +//#include + +//#include "..\pal\Diagnostics\Native_Profiler.h" +// native profiler +#define NATIVE_PROFILE_PAL_HEAP() +#define NATIVE_PROFILE_PAL_CRT() + +#endif // _NANOPAL_H_ diff --git a/source/native/nf-interpreter/src/PAL/Include/nanoPAL_AsyncProcCalls_decl.h b/source/native/nf-interpreter/src/PAL/Include/nanoPAL_AsyncProcCalls_decl.h new file mode 100644 index 00000000..811d4f38 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/Include/nanoPAL_AsyncProcCalls_decl.h @@ -0,0 +1,134 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _NANOPAL_ASYNCPROCCALLS_DECL_H_ +#define _NANOPAL_ASYNCPROCCALLS_DECL_H_ 1 + +#include + +//--// + +#if NATIVE_PROFILE_PAL & NATIVE_PROFILE_PAL_ASYNC_PROC_CALL__flag + #define NATIVE_PROFILE_PAL_ASYNC_PROC_CALL() Native_Profiler profiler_obj +#else + #define NATIVE_PROFILE_PAL_ASYNC_PROC_CALL() +#endif + +typedef void (*HAL_CALLBACK_FPN)( void* arg ); + +struct HAL_CALLBACK +{ +public: + HAL_CALLBACK_FPN EntryPoint; + void* Argument; + +public: + void Initialize( HAL_CALLBACK_FPN EntryPoint, void* Argument ) + { + this->EntryPoint = EntryPoint; + this->Argument = Argument; + } + + void SetArgument( void* Argument ) + { + this->Argument = Argument; + } + + HAL_CALLBACK_FPN GetEntryPoint() const { return this->EntryPoint; } + void* GetArgument () const { return this->Argument ; } + + void Execute() const + { + HAL_CALLBACK_FPN EntryPoint = this->EntryPoint; + void* Argument = this->Argument; + + if(EntryPoint) + { + EntryPoint( Argument ); + } + } +}; + + +struct HAL_CONTINUATION : public HAL_DblLinkedNode +{ + +private: + HAL_CALLBACK Callback; + +public: + void InitializeCallback( HAL_CALLBACK_FPN EntryPoint, void* Argument = NULL ); + + void SetArgument( void* Argument ) + { + Callback.SetArgument( Argument ); + } + + HAL_CALLBACK_FPN GetEntryPoint() const { return Callback.GetEntryPoint(); } + void* GetArgument () const { return Callback.GetArgument (); } + + void Execute() const { Callback.Execute(); } + + bool IsLinked(); + void Enqueue(); + void Abort (); + + //--// + + static void Uninitialize(); + + static void InitializeList(); + + static bool Dequeue_And_Execute(); +}; + +//--// + +struct HAL_COMPLETION : public HAL_CONTINUATION +{ + uint64_t EventTimeTicks; + bool ExecuteInISR; + +#if defined(_DEBUG) + uint64_t Start_RTC_Ticks; +#endif + + void InitializeForISR( HAL_CALLBACK_FPN EntryPoint, void* Argument = NULL ) + { + ExecuteInISR = true; + + InitializeCallback( EntryPoint, Argument ); + } + + void InitializeForUserMode( HAL_CALLBACK_FPN EntryPoint, void* Argument = NULL ) + { + ExecuteInISR = false; + + InitializeCallback( EntryPoint, Argument ); + } + + void EnqueueTicks ( uint64_t eventTimeTicks ); + void EnqueueDelta64 ( uint64_t miliSecondsFromNow ); + void EnqueueDelta ( uint32_t miliSecondsFromNow ); + + void Abort(); + + void Execute(); + + //--// + + static void Uninitialize(); + + static void InitializeList(); + + static void DequeueAndExec(); + + static void WaitForInterrupts( uint64_t expireTimeInSysTicks, uint32_t sleepLevel, uint64_t wakeEvents ); +}; + +//--// + +#endif //_NANOPAL_ASYNCPROCCALLS_DECL_H_ diff --git a/source/native/nf-interpreter/src/PAL/Include/nanoPAL_BlockStorage.h b/source/native/nf-interpreter/src/PAL/Include/nanoPAL_BlockStorage.h new file mode 100644 index 00000000..d0a43788 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/Include/nanoPAL_BlockStorage.h @@ -0,0 +1,647 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _NANOPAL_BLOCKSTORAGE_H_ +#define _NANOPAL_BLOCKSTORAGE_H_ 1 + +#include +#include +#include +#include +#include + +///////////////////////////////////////////////////////// +// Description: +// Definitions for the Block Storage device interface +// for the nanoFramework +// +// Terminology: +// Block Storage Device - device that stores data addressable +// as a chunk as opposed to byte or unsigned short level +// +// Sector - smallest unit of storage for a Block device. Data is +// read or written as a complete sector(unless the device +// supports XIP which allows byte addresssing and reading +// directly from the processor memory bus) +// +// Block - smallest eraseable unit of the storage device. A block +// contains one or more sectors that are erased as a whole. +// All sectors within a block are always the same size. +// +// Region - Group of adjacent blocks that all contain sectors of the +// same size. +// +// Execute-In-Place (XIP) - Attribute of some storage types, NOR, ROM, +// RAM, that allows direct execution of code from the device. +// XIP capable devices are at least read-only and byte addresable +// on the CPU memory bus. +// + + +// In flash media the distinction between a block and a sector is important +// so we define the sector address to make it clear. +typedef unsigned int ByteAddress; +typedef unsigned int SectorAddress; + +////////////////////////////////////////////////////////// +// Description: +// Flags to Indicate the status of a particular block in +// flash. ALL sectors for a block *MUST* share the same +// status. +// +// Remarks: +// When the block is reserved the lower 16 bits specifies a +// USAGE_XXXX value to indicate the purpose of the block. +// +// The BlockRange information is technically dynamic in the +// sense that it is not fixed or defined in hardware. Rather, +// it is defined by the system designer. However, the BlockRange +// info does not and *MUST* not change at run-time. The only +// exceptions to this rule is in the boot loader where the +// storage device is being formated or re-laid out as part +// of an update etc... and when an FS discovers a bad block +// it should mark it as bad. WIthout this restriction +// implementing an FS is virtually impossible since the FS +// would have to deal with the possibility that the usage for +// a Block could change at any point in time. +// +typedef enum BlockUsage +{ + BlockUsage_BOOTSTRAP = 0x0010, + BlockUsage_CODE = 0x0020, + BlockUsage_CONFIG = 0x0030, + BlockUsage_FILESYSTEM = 0x0040, + + BlockUsage_DEPLOYMENT = 0x0050, + + BlockUsage_UPDATE = 0x0060, + + BlockUsage_SIMPLE_A = 0x0090, + BlockUsage_SIMPLE_B = 0x00A0, + + BlockUsage_STORAGE_A = 0x00E0, + BlockUsage_STORAGE_B = 0x00F0, + + + BlockUsage_ANY = 0x0000, + +}BlockUsage; + +// upper 4 bits of USAGE_XXXX identifies the base type of info stored in the block +// using these values it is possible to scan a device for all managed code or all +// native code without worrying about the finer details of what it's for. + +// Block contains XIP system native code +#define BlockRange_DATATYPE_NATIVECODE ((unsigned int)0x1000) +// Block contains managed code assemblies +#define BlockRange_DATATYPE_MANAGEDCODE ((unsigned int)0x2000) +// Block contains raw data +#define BlockRange_DATATYPE_RAW ((unsigned int)0x4000) + +// use to mark the block is used for special purpose +#define BlockRange_ATTRIB_PRIMARY ((unsigned int)0x10000) + + +#define BlockRange_EXECUTABLE ((unsigned int)0x80000000) +#define BlockRange_RESERVED ((unsigned int)0x40000000) +#define BlockRange_READONLY ((unsigned int)0x20000000) + +// Values for the Usage information (This helps map the new storage APIs to the needs of existing code) +#define BlockRange_ALL_MASK ((unsigned int)0xFFFFFFFF) +#define BlockRange_USAGE_MASK ((unsigned int)0x000000FF) +#define BlockRange_NON_USAGE_MASK ((unsigned int)0xFFFFFF00) + +// for secondary devices to set dirtybits +#define BlockRange_BLOCKTYPE_RESERVED (BlockRange_RESERVED) +#define BlockRange_BLOCKTYPE_DIRTYBIT ( BlockRange_RESERVED | BlockRange_DATATYPE_RAW | BlockUsage_CONFIG) +// Configuration data that contains all the unique data +#define BlockRange_BLOCKTYPE_CONFIG (BlockRange_ATTRIB_PRIMARY | BlockRange_RESERVED | BlockRange_DATATYPE_RAW | BlockUsage_CONFIG) + +// Boot loader and boot strap code +#define BlockRange_BLOCKTYPE_BOOTSTRAP (BlockRange_EXECUTABLE | BlockRange_RESERVED | BlockRange_DATATYPE_NATIVECODE | BlockUsage_BOOTSTRAP) +// CLR or other native code "application" +#define BlockRange_BLOCKTYPE_CODE (BlockRange_EXECUTABLE | BlockRange_RESERVED | BlockRange_DATATYPE_NATIVECODE | BlockUsage_CODE) +// Deployment area for MFdeploy & Visual Studio +#define BlockRange_BLOCKTYPE_DEPLOYMENT ( BlockRange_RESERVED | BlockRange_DATATYPE_MANAGEDCODE | BlockUsage_DEPLOYMENT) +// Part A of Simple Storage +#define BlockRange_BLOCKTYPE_SIMPLE_A ( BlockRange_RESERVED | BlockRange_DATATYPE_RAW | BlockUsage_SIMPLE_A) +// Part B of Simple Storage +#define BlockRange_BLOCKTYPE_SIMPLE_B ( BlockRange_RESERVED | BlockRange_DATATYPE_RAW | BlockUsage_SIMPLE_B) +// Part A of EWR Storage +#define BlockRange_BLOCKTYPE_STORAGE_A ( BlockRange_RESERVED | BlockRange_DATATYPE_RAW | BlockUsage_STORAGE_A ) +// Part B of EWR Storage +#define BlockRange_BLOCKTYPE_STORAGE_B ( BlockRange_RESERVED | BlockRange_DATATYPE_RAW | BlockUsage_STORAGE_B) +// File System +#define BlockRange_BLOCKTYPE_FILESYSTEM ( BlockRange_DATATYPE_RAW | BlockUsage_FILESYSTEM) +// Used for MFUpdate for firmware/assembly/etc updates +#define BlockRange_BLOCKTYPE_UPDATE ( BlockRange_RESERVED | BlockRange_DATATYPE_RAW | BlockUsage_UPDATE) + +//////////////////////////////////////////////////////// +// + +//typedef struct BLOCKRANGE BlockRange; + +typedef struct BlockRange +{ + unsigned int RangeType; + unsigned int StartBlock; + unsigned int EndBlock; +}BlockRange; + +#define BlockRange_GetBlockCount(block) (block.EndBlock - block.StartBlock + 1) +#define BlockRange_GetBlockUsage(block) (block.RangeType & BlockRange_USAGE_MASK) +#define BlockRange_IsDeployment(block) ((block.RangeType & BlockRange_USAGE_MASK) == BlockUsage_DEPLOYMENT) +#define BlockRange_IsConfig(block) ((block.RangeType & BlockRange_BLOCKTYPE_CONFIG) == BlockRange_BLOCKTYPE_CONFIG) + +///////////////////////////////////////////////////////// +// Description: +// This structure defines characteristics of a particular +// region of a block device. +// +// Remarks: +// There is often more than one instance of this structure for each +// block device. +// +// The BytesPerBlock value is an optimization to prevent the need +// to routinely calculate it from SectorsPerBlock * DataBytesPerSector +// + +typedef enum BlockRegionAttribute +{ + // block region is memory mapped + + BlockRegionAttribute_MemoryMapped = 0x0001, + +}BlockRegionAttribute; + +typedef struct BLOCKREGIONINFO BlockRegionInfo; + +#define BlockRegionInfo_Size(region) (region->NumBlocks * region->BytesPerBlock) +#define BlockRegionInfo_BlockAddress(region, blockIndex) (region->Start + (blockIndex * region->BytesPerBlock)) +#define BlockRegionInfo_OffsetFromBlock(region, address) ((address - region->Start) % region->BytesPerBlock) +#define BlockRegionInfo_BlockIndexFromAddress(region, address) ((address - region->Start) / region->BytesPerBlock) + +struct BLOCKREGIONINFO +{ + // attributes for the block region + BlockRegionAttribute Attributes; + + // Starting Sector address + ByteAddress Start; + + unsigned int NumBlocks; + + // total number of blocks in this region + unsigned int BytesPerBlock; // Total number of bytes per block + + unsigned int NumBlockRanges; + const BlockRange *BlockRanges; +}; + +///////////////////////////////////////////////////////// + +typedef struct DEVICEBLOCKINFO DeviceBlockInfo; + +typedef enum MediaAttribute +{ + MediaAttribute_Removable = 0x0001, + MediaAttribute_SupportsXIP = 0x0002, + MediaAttribute_WriteProtected = 0x0004, + MediaAttribute_SupportsCopyBack = 0x0008, + MediaAttribute_ErasedBitsAreZero = 0x0010, + +}MediaAttribute; + +#ifdef __cplusplus +extern "C" { +#endif + + SectorAddress DeviceBlockInfo_PhysicalToSectorAddress(DeviceBlockInfo* blockInfo, const BlockRegionInfo* pRegion, ByteAddress phyAddress); + bool DeviceBlockInfo_FindRegionFromAddress(DeviceBlockInfo* blockInfo, ByteAddress address, unsigned int* blockRegionIndex, unsigned int* blockRangeIndex); + bool DeviceBlockInfo_FindForBlockUsage(DeviceBlockInfo* blockInfo, unsigned int blockUsage, unsigned int* address, unsigned int* blockRegionIndex, unsigned int* blockRangeIndex); + bool DeviceBlockInfo_FindNextUsageBlock(DeviceBlockInfo* blockInfo, unsigned int blockUsage, unsigned int* address, unsigned int* blockRegionIndex, unsigned int* blockRangeIndex); + +#ifdef __cplusplus +} +#endif + +//typedef struct DEVICEBLOCKINFO +struct DEVICEBLOCKINFO +{ + MediaAttribute Attribute; + + // Bytes Per Sector + uint32_t BytesPerSector; + + // count of regions in the flash. + uint32_t NumRegions; + + // pointer to an array (NumRegions long) of region information + BlockRegionInfo *Regions; +}; + +///////////////////////////////////////////////////////// +// Description: +// This structure defines an interface for block devices +// +// Remarks: +// It is possible a given system might have more than one +// storage device type. This interface abstracts the +// hardware specifics from the rest of the system. +// +// All of the functions take at least one void* parameter +// that normally points to a driver specific data structure +// containing hardware specific settings to use. This +// allows a single driver to support multiple instances of +// the same type of storage device in the system. +// +// The sector read and write functions provide a parameter +// for Sector Metadata. The metadata is used for flash arrays +// without special controllers to manage wear leveling etc... +// (mostly for directly attached NOR and NAND). The metadata +// is used by upper layers for wear leveling to ensure that +// data is moved around on the flash when writing to prevent +// failure of the device from too many erase cycles on a sector. +// +// TODO: +// Define standard method of notification that media is +// removed for all removeable media. This will likely +// be a continuation so that the FS Manager can mount +// an FS and then notify the managed app of the new FS. +// + +typedef struct IBLOCKSTORAGEDEVICE IBlockStorageDevice; + +struct IBLOCKSTORAGEDEVICE +{ + ///////////////////////////////////////////////////////// + // Description: + // Initializes a given block device for use + // + // Input: + // + // Returns: + // true if successful; false if not + // + // Remarks: + // No other functions in this interface may be called + // until after Init returns. + // + bool (*InitializeDevice)(void*); + + ///////////////////////////////////////////////////////// + // Description: + // Initializes a given block device for use + // + // Returns: + // true if succesful; false if not + // + // Remarks: + // De initializes the device when no longer needed + // + bool (*UninitializeDevice)(void*); + + ///////////////////////////////////////////////////////// + // Description: + // Gets the information describing the device + // + DeviceBlockInfo* (*GetDeviceInfo)(void*); + + ///////////////////////////////////////////////////////// + // Description: + // Reads data from a set of sectors + // + // Input: + // startAddress - Starting Sector for the read + // numBytes - Number of bytes to read + // buffer - pointer to buffer to read the data into. + // Must be large enough to hold all of the data + // being read. + // + // pSectorMetadata - pointer to an array of structured (one for each sector) + // for the extra sector information. + // + // Returns: + // true if successful; false if not + // + // Remarks: + // This function reads the number of sectors specified from the device. + // + // pSectorBuff may be NULL. This is to allow for reading just the metadata. + // + // pSectorMetadata can be set to NULL if the caller does not need the extra + // data. + // + // If the device does not support sector Metadata it should fail if the + // pSectorMetadata parameter is not NULL. + // + bool (*Read)(void*, ByteAddress startAddress, unsigned int numBytes, unsigned char* buffer); + + ///////////////////////////////////////////////////////// + // Description: + // Writes data to a set of sectors + // + // Input: + // startAddress - Starting Sector for the write + // numBytes - Number of bytes to write + // buffer - pointer to data to write. + // Must be large enough to hold complete sectors + // for the number of sectors being written. + // + // pSectorMetadata - pointer to an array of structures (one for each sector) + // for the extra sector information. + // + // Returns: + // true if successful; false if not + // + // Remarks: + // This function reads the number of sectors specified from the device. + // The SectorMetadata is used for flash arrays without special controllers + // to manage wear leveling etc... (mostly for NOR and NAND). The metadata + // is used by upper layers to ensure that data is moved around on the flash + // when writing to prevent failure of the device from too many erase cycles + // on a sector. + // + // If the device does not support sector Metadata it should fail if the + // pSectorMetadata parameter is not NULL. + // + // pSectorMetadata can be set to NULL if the caller does not need the extra + // data. Implementations must not attempt to write data through a NULL pointer! + // + bool (*Write)(void*, ByteAddress startAddress, unsigned int numBytes, unsigned char* buffer, bool readModifyWrite); + + bool (*Memset)(void*, ByteAddress startAddress, unsigned char data, unsigned int numBytes); + + //bool (*GetSectorMetadata)(void*, ByteAddress startAddress, SectorMetadata* pSectorMetadata); + + //bool (*SetSectorMetadata)(void*, ByteAddress startAddress, SectorMetadata* pSectorMetadata); + + ///////////////////////////////////////////////////////// + // Description: + // Check a block is erased or not. + // + // Input: + // blockStartAddress - Logical Sector Address + // + // Returns: + // true if it is erased, otherwise false + // + // Remarks: + // Check the block containing the sector address specified. + // + bool (*IsBlockErased)(void*, ByteAddress blockStartAddress, unsigned int length); + + ///////////////////////////////////////////////////////// + // Description: + // Erases a block + // + // Input: + // address - Logical Sector Address + // + // Returns: + // true if successful; false if not + // + // Remarks: + // Erases the block containing the sector address specified. + // + bool (*EraseBlock)(void*, ByteAddress address); + + ///////////////////////////////////////////////////////// + // Description: + // Changes the power state of the device + // + // Input: + // State - true= power on; false = power off + // + // Remarks: + // This function allows systems to conserve power by + // shutting down the hardware when the system is + // going into low power states. + // + void (*SetPowerState)(void*, unsigned int state); + + ///////////////////////////////////////////////////////// + // Description: + // Gets the memory mapped address for the specified block range. + // + // Input: + // blockRegionIndex - index of the block region + // blockRangeIndex - index of the block range in the region + // address - memory mapped address for the block range + // + // Returns: + // true if the block region is memory mapped, otherwise false + // + // Remarks: + // Being memory mapped, is expected that a block region is in the same physical device. + // This implementation is useful for systems that offer the possibility to map external storage + // to flash addressess. Tipically read only. + // + bool (*GetMemoryMappedAddress)(void*, unsigned int, unsigned int, ByteAddress*); +}; + +typedef struct BLOCKSTORAGEDEVICE +{ + IBlockStorageDevice* m_BSD; + void* m_context; +}BlockStorageDevice; + +///////////////////////////////////////////////////////////////////// +#ifdef __cplusplus +extern "C" { +#endif + + BlockStorageDevice* BlockStorageDevice_Next(BlockStorageDevice* device); + BlockStorageDevice* BlockStorageDevice_Prev(BlockStorageDevice* device); + bool BlockStorageDevice_InitializeDevice(BlockStorageDevice* device); + bool BlockStorageDevice_UninitializeDevice(BlockStorageDevice* device); + DeviceBlockInfo* BlockStorageDevice_GetDeviceInfo(BlockStorageDevice* device); + bool BlockStorageDevice_Read(BlockStorageDevice* device, unsigned int startAddress, unsigned int numBytes, unsigned char* buffer); + bool BlockStorageDevice_Write(BlockStorageDevice* device, unsigned int startAddress, unsigned int numBytes, unsigned char* buffer, bool readModifyWrite); + bool BlockStorageDevice_Memset(BlockStorageDevice* device, unsigned int startAddress, unsigned char buffer, unsigned int numBytes); + // bool BlockStorageDevice_GetSectorMetadata(BlockStorageDevice* device, unsigned int sectorStart, SectorMetadata* pSectorMetadata); + // bool BlockStorageDevice_SetSectorMetadata(BlockStorageDevice* device, unsigned int sectorStart, SectorMetadata* pSectorMetadata); + bool BlockStorageDevice_IsBlockErased(BlockStorageDevice* device, unsigned int blockStartAddress, unsigned int length); + bool BlockStorageDevice_EraseBlock(BlockStorageDevice* device, unsigned int address); + void BlockStorageDevice_SetPowerState(BlockStorageDevice* device, unsigned int state); + bool BlockStorageDevice_FindRegionFromAddress(BlockStorageDevice* device, unsigned int address, unsigned int* blockRegionIndex, unsigned int* blockRangeIndex); + bool BlockStorageDevice_FindForBlockUsage(BlockStorageDevice* device, unsigned int blockUsage, unsigned int* address, unsigned int* blockRegionIndex, unsigned int* blockRangeIndex); + bool BlockStorageDevice_FindNextUsageBlock(BlockStorageDevice* device, unsigned int blockUsage, unsigned int* address, unsigned int* blockRegionIndex, unsigned int* blockRangeIndex); + bool BlockStorageDevice_GetMemoryMappedAddress(BlockStorageDevice* device, unsigned int blockRegionIndex, unsigned int blockRangeIndex, unsigned int* address); + +#ifdef __cplusplus +} +#endif + + +///////////////////////////////////////////////////// +// BlockStorageStream declarations + +typedef struct BLOCKSTORAGESTREAM BlockStorageStream; + +typedef enum SeekOrigin +{ + BlockStorageStream_SeekBegin = 0, + BlockStorageStream_SeekCurrent = 1, + BlockStorageStream_SeekEnd = 2, + +}SeekOrigin; + +#ifdef __cplusplus +extern "C" { +#endif + + bool BlockStorageStream_IsXIP(BlockStorageStream* stream); + bool BlockStorageStream_IsReadModifyWrite(BlockStorageStream* stream); + bool BlockStorageStream_SetReadModifyWrite(BlockStorageStream* stream); + + bool BlockStorageStream_Initialize(BlockStorageStream* stream, unsigned int blockUsage); + bool BlockStorageStream_InitializeWithBlockStorageDevice(BlockStorageStream* stream, unsigned int blockUsage, BlockStorageDevice* pDevice); + bool BlockStorageStream_NextStream(BlockStorageStream* stream); + bool BlockStorageStream_PrevStream(BlockStorageStream* stream); + bool BlockStorageStream_Seek(BlockStorageStream* stream, unsigned int offset, SeekOrigin origin); + bool BlockStorageStream_Write(BlockStorageStream* stream, unsigned char* data, unsigned int length); + bool BlockStorageStream_Erase(BlockStorageStream* stream, unsigned int length); + bool BlockStorageStream_ReadIntoBuffer(BlockStorageStream* stream, unsigned char* buffer, unsigned int length); + bool BlockStorageStream_Read(BlockStorageStream* stream, unsigned char** buffer, unsigned int length); + unsigned int BlockStorageStream_CurrentAddress(BlockStorageStream* stream); + unsigned int BlockStorageStream_CurrentMappedAddress(BlockStorageStream* stream); + bool BlockStorageStream_IsErased(BlockStorageStream* stream, unsigned int length); + +#ifdef __cplusplus +} +#endif + +#define BLOCKSTORAGESTREAM_STREAM_SEEK_NEXT_BLOCK ((unsigned int)0x7FFFFFFF) +#define BLOCKSTORAGESTREAM_STREAM_SEEK_PREV_BLOCK ((unsigned int)0x7FFFFFFE) + +#define BLOCKSTORAGESTREAM_c_BlockStorageStream__XIP ((unsigned int)0x00000001) +#define BLOCKSTORAGESTREAM_c_BlockStorageStream__ReadModWrite ((unsigned int)0x00000002) +#define BLOCKSTORAGESTREAM_c_BlockStorageStream__MemoryMapped ((unsigned int)0x00000004) + +struct BLOCKSTORAGESTREAM +{ + unsigned int BaseAddress; + unsigned int MemoryMappedAddress; + unsigned int CurrentIndex; + unsigned int Length; + unsigned int BlockLength; + unsigned int Usage; + unsigned int Flags; + unsigned int RegionIndex; + unsigned int RangeIndex; + unsigned int CurrentUsage; + BlockStorageDevice *Device; + +}; + +/////////////////////////////////////////////////// +// BlockStorageList declarations + +typedef struct BLOCKSTORAGELIST BlockStorageList; + +#ifdef __cplusplus +extern "C" { +#endif + + // initialize the storage + void BlockStorageList_Initialize(); + // walk through list of devices and calls Init() function + bool BlockStorageList_InitializeDevices(); + // walk through list of devices and calls UnInit() function + bool BlockStorageList_UnInitializeDevices(); + // add pBSD to the list + // If Init=true, the Init() will be called. + bool BlockStorageList_AddDevice(BlockStorageDevice* pBSD, IBlockStorageDevice* vtable, void* config, bool init); + // remove pBSD from the list + // Uninit = true, UnInit() will be called. + bool BlockStorageList_RemoveDevice(BlockStorageDevice* pBSD, bool unInit); + // Find the right Device with the corresponding phyiscal address. + bool BlockStorageList_FindDeviceForPhysicalAddress(BlockStorageDevice** pBSD, unsigned int physicalAddress, ByteAddress* blockAddress); + BlockStorageDevice* BlockStorageList_GetFirstDevice(); + BlockStorageDevice* BlockStorageList_GetNextDevice(BlockStorageDevice* device); + // returns number of devices has been declared in the system + unsigned int BlockStorageList_GetNumDevices(); + +#ifdef __cplusplus +} +#endif + +// default (and absolute minimum!!) block storage devices count is 1 (ONE) +// otherwise a target wouldn't have storage +#ifndef TARGET_BLOCKSTORAGE_COUNT +#define TARGET_BLOCKSTORAGE_COUNT 1 +#endif + +struct BLOCKSTORAGELIST +{ + // global pointer of all the storage devices + BlockStorageDevice* DeviceList[TARGET_BLOCKSTORAGE_COUNT]; + + uint32_t DeviceCount; + + // bool Initialized; +}; + +////////////////////////////////////////////////////////// +// TODO: evaluate if these typedefs below should go away +// and be replaced with others or completely ditched + + +typedef struct CPU_MEMORY_CONFIG +{ + unsigned char ChipSelect; + unsigned char ReadOnly; + unsigned int WaitStates; + unsigned int ReleaseCounts; + unsigned int BitWidth; + unsigned int BaseAddress; + unsigned int SizeInBytes; + unsigned char XREADYEnable; // 0,1 + unsigned char ByteSignalsForRead; // 0,1 + unsigned char ExternalBufferEnable; // 0,1 + +}CPU_MEMORY_CONFIG; + +typedef unsigned int GPIO_PIN; + +typedef struct GPIO_FLAG +{ + GPIO_PIN Pin; + bool ActiveState; + +}GPIO_FLAG; + +typedef struct BLOCK_CONFIG +{ + GPIO_FLAG WriteProtectionPin; + DeviceBlockInfo* BlockDeviceInformation; + +}BLOCK_CONFIG; + +typedef struct MEMORY_MAPPED_NOR_BLOCK_CONFIG +{ + BLOCK_CONFIG BlockConfig; + CPU_MEMORY_CONFIG Memory; + unsigned int ChipProtection; + unsigned int ManufacturerCode; + unsigned int DeviceCode; + +}MEMORY_MAPPED_NOR_BLOCK_CONFIG; + +#ifdef __cplusplus +extern "C" { +#endif + +////////////////////////////////////////////////////////// +// function to included in all target devices to be added +void BlockStorage_AddDevices(); + +#ifdef __cplusplus +} +#endif + +#endif // _NANOPAL_BLOCKSTORAGE_H_ diff --git a/source/native/nf-interpreter/src/PAL/Include/nanoPAL_COM.h b/source/native/nf-interpreter/src/PAL/Include/nanoPAL_COM.h new file mode 100644 index 00000000..10defc06 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/Include/nanoPAL_COM.h @@ -0,0 +1,56 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _NANOPAL_COM_H_ +#define _NANOPAL_COM_H_ 1 + +#include +#include + +#define COM_MAX_RETRIES 99 +#define NATIVE_PROFILE_PAL_COM() + + +#ifdef __cplusplus +extern "C" { +#endif + +bool GenericPort_Initialize( COM_HANDLE comPortNum ); +bool GenericPort_Uninitialize( COM_HANDLE comPortNum ); +uint32_t GenericPort_Write( int portNum, const char* data, size_t size ); +int GenericPort_Read( COM_HANDLE comPortNum, char* data, size_t size ); +bool GenericPort_Flush( COM_HANDLE comPortNum ); +bool GenericPort_IsSslSupported( COM_HANDLE comPortNum ); +bool GenericPort_UpgradeToSsl( COM_HANDLE comPortNum, unsigned int flags ); +bool GenericPort_IsUsingSsl( COM_HANDLE comPortNum ); + +#ifdef __cplusplus +} +#endif + + +#ifdef __cplusplus +int DebuggerPort_Write( COM_HANDLE comPortNum, const char* data, size_t size ); +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +bool DebuggerPort_Initialize( COM_HANDLE comPortNum ); +bool DebuggerPort_Uninitialize( COM_HANDLE comPortNum ); +int DebuggerPort_Write( COM_HANDLE comPortNum, const char* data, size_t size, int maxRetries ); +int DebuggerPort_Read( COM_HANDLE comPortNum, char* data, size_t size ); +bool DebuggerPort_Flush( COM_HANDLE comPortNum ); +bool DebuggerPort_IsSslSupported( COM_HANDLE comPortNum ); +bool DebuggerPort_UpgradeToSsl( COM_HANDLE comPortNum, unsigned int flags ); +bool DebuggerPort_IsUsingSsl( COM_HANDLE comPortNum ); + +#ifdef __cplusplus +} +#endif + +#endif // _NANOPAL_COMDECL_H_ diff --git a/source/native/nf-interpreter/src/PAL/Include/nanoPAL_Events.h b/source/native/nf-interpreter/src/PAL/Include/nanoPAL_Events.h new file mode 100644 index 00000000..6454775c --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/Include/nanoPAL_Events.h @@ -0,0 +1,101 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _NANOPAL_EVENTS_H_ +#define _NANOPAL_EVENTS_H_ 1 + +#include +#include + +typedef void (*set_Event_Callback)( void* ); + +#define EVENTS_TIMEOUT_INFINITE 0xFFFFFFFF + +#if NATIVE_PROFILE_PAL & NATIVE_PROFILE_PAL_EVENTS__flag + #define NATIVE_PROFILE_PAL_EVENTS() Native_Profiler profiler_obj +#else + #define NATIVE_PROFILE_PAL_EVENTS() +#endif + + + bool Events_Initialize(); + bool Events_Uninitialize(); + void Events_Set( uint32_t events ); + +// destructive read system event flags + uint32_t Events_Get( uint32_t eventsOfInterest ); + +// non-destructive read system event flags + uint32_t Events_MaskedRead( uint32_t eventsOfInterest ); + +// returns 0 for timeout, non-zero are events that have happened and were asked to be waiting on (non-destructive read) +// timeout limit is about 3034 milliseconds currently +// values greater than this are capped to this + +// sleep relative time into the future, or until a SystemEvent occurs, which occurs first +// timeout is a non-negative number of 1mSec ticks, or -1 (any negative value) to sleep forever until a SystemEvent occurs + +// Events_WaitForEvents(0, n), sleeps for n milliseconds independent of events +// Events_WaitForEvents(0, EVENTS_TIMEOUT_INFINITE) sleeps forever. Don't do that. +// Events_WaitForEvents(flags, EVENTS_TIMEOUT_INFINITE) waits forever for that event. + +uint32_t Events_WaitForEvents( uint32_t powerLevel, uint32_t wakeupSystemEvents, uint32_t timeoutMilliseconds ); + +__inline uint32_t Events_WaitForEvents( uint32_t wakeupSystemEvents, uint32_t timeoutMilliseconds ) +{ + return Events_WaitForEvents( SLEEP_LEVEL__SLEEP, wakeupSystemEvents, timeoutMilliseconds ); +} + + void Events_SetBoolTimer( bool* timerCompleteFlag, uint32_t millisecondsFromNow ); + void Events_SetCallback( set_Event_Callback pfn, void* arg ); + void FreeManagedEvent(uint8_t category, uint8_t subCategory, uint16_t data1, uint32_t data2); + + +#ifdef __cplusplus +extern "C" { +#endif + + void PostManagedEvent(uint8_t category, uint8_t subCategory, uint16_t data1, uint32_t data2); + +#ifdef __cplusplus +} +#endif + +//--// + +typedef void (*PALEVENTLISTENER) (uint32_t e, uint32_t param); + +struct PalEventListener : public HAL_DblLinkedNode +{ + PALEVENTLISTENER m_palEventListener; + uint32_t m_eventMask; +}; + + +HRESULT PalEvent_Initialize(); +HRESULT PalEvent_Uninitialize(); +HRESULT PalEvent_Post(uint32_t e, uint32_t param); +HRESULT PalEvent_Enlist(PalEventListener* listener); + +//--// + +struct PalEventDriver +{ +public: + + HAL_DblLinkedList listenerList; + + static HRESULT Initialize(); + static HRESULT Uninitialize(); + static HRESULT PostEvent(uint32_t e, uint32_t param); + static HRESULT EnlistListener(PalEventListener* listener); + +private: + static bool s_initialized; +}; + +extern PalEventDriver g_palEventDriver; + +#endif //_NANOPAL_EVENTS_H_ diff --git a/source/native/nf-interpreter/src/PAL/Include/nanoPAL_GPIO.h b/source/native/nf-interpreter/src/PAL/Include/nanoPAL_GPIO.h new file mode 100644 index 00000000..c7ebbc16 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/Include/nanoPAL_GPIO.h @@ -0,0 +1,25 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _NANOPAL_GPIO_H_ +#define _NANOPAL_GPIO_H_ 1 + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/// +/// Performs initialization of GPIO pins and associated drivers. +/// +void GPIO_Initialize(); +void GPIO_Uninitialize(); + +#ifdef __cplusplus +} +#endif + +#endif //_NANOPAL_GPIO_H_ diff --git a/source/native/nf-interpreter/src/PAL/Include/nanoPAL_NativeDouble.h b/source/native/nf-interpreter/src/PAL/Include/nanoPAL_NativeDouble.h new file mode 100644 index 00000000..ebb21b2c --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/Include/nanoPAL_NativeDouble.h @@ -0,0 +1,23 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _NANOPAL_DOUBLE_DECL_H_ +#define _NANOPAL_DOUBLE_DECL_H_ + +#include + +namespace System +{ + struct Double + { + static int32_t CompareTo( double d, double val ); + static bool IsInfinity( double d ); + static bool IsNaN( double d ); + static bool IsNegativeInfinity( double d ); + static bool IsPositiveInfinity( double d ); + }; +} + +#endif //_NANOPAL_DOUBLE_DECL_H_ diff --git a/source/native/nf-interpreter/src/PAL/Include/nanoPAL_Network.h b/source/native/nf-interpreter/src/PAL/Include/nanoPAL_Network.h new file mode 100644 index 00000000..a2d79034 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/Include/nanoPAL_Network.h @@ -0,0 +1,25 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _NETWORK_DECL_H_ +#define _NETWORK_DECL_H_ 1 + + +#ifdef PLATFORM_DEPENDENT__SOCKETS_MAX_COUNT +#define SOCKETS_MAX_COUNT PLATFORM_DEPENDENT__SOCKETS_MAX_COUNT +#else +#define SOCKETS_MAX_COUNT 1 // required to have at least one for array init +#endif + +#ifdef PLATFORM_DEPENDENT__SOCKETS_MAX_SEND_LENGTH +#define SOCKETS_MAX_SEND_LENGTH PLATFORM_DEPENDENT__SOCKETS_MAX_SEND_LENGTH +#endif + +#if !defined(DEBGGER_NETWORK_INTERFACE_INDEX) +#define DEBGGER_NETWORK_INTERFACE_INDEX 0 +#endif + +#endif //_NETWORK_DECL_H_ diff --git a/source/native/nf-interpreter/src/PAL/Include/nanoPAL_PerformanceCounters.h b/source/native/nf-interpreter/src/PAL/Include/nanoPAL_PerformanceCounters.h new file mode 100644 index 00000000..a068d5a8 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/Include/nanoPAL_PerformanceCounters.h @@ -0,0 +1,23 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _PERFORMANCE_COUNTERS_H_ +#define _PERFORMANCE_COUNTERS_H_ 1 + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +void PAL_PerformanceCounter_Initialize(); +void PAL_PerformanceCounter_Uninitialize(); +uint32_t PAL_PerformanceCounter(); + +#ifdef __cplusplus +} +#endif + +#endif //_PERFORMANCE_COUNTERS_H_ diff --git a/source/native/nf-interpreter/src/PAL/Include/nanoPAL_Sockets.h b/source/native/nf-interpreter/src/PAL/Include/nanoPAL_Sockets.h new file mode 100644 index 00000000..57b4deaa --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/Include/nanoPAL_Sockets.h @@ -0,0 +1,664 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _DRIVERS_SOCKETS_DECL_H_ +#define _DRIVERS_SOCKETS_DECL_H_ 1 + +#if defined(_WIN32) +#define GLOBAL_LOCK_SOCKETS(x) +#endif +//--// + + +typedef struct _DATE_TIME_INFO +{ + unsigned int year; /* year, AD */ + unsigned int month; /* 1 = January, 12 = December */ + unsigned int day; /* 1 = first of the month */ + unsigned int hour; /* 0 = midnight, 12 = noon */ + unsigned int minute; /* minutes past the hour */ + unsigned int second; /* seconds in minute */ + unsigned int msec; /* milliseconds in second */ + + /* These two fields help */ + /* interpret the absolute */ + /* time meaning of the */ + /* above values. */ + unsigned int dlsTime; /* boolean; daylight savings time is in effect */ + int tzOffset; /* signed int; difference in seconds imposed by timezone (from GMT) */ +} DATE_TIME_INFO; + +typedef struct _X509CertData +{ + char Issuer[256]; + char Subject[256]; + DATE_TIME_INFO EffectiveDate; + DATE_TIME_INFO ExpirationDate; +} X509CertData; + + +//Avoid including windows socket definitions + +#ifndef NANOCLR_SOCK_STRUCTURES +#define NANOCLR_SOCK_STRUCTURES + +#define SOCK_EINTR 10004L +#define SOCK_EBADF 10009L +#define SOCK_EACCES 10013L +#define SOCK_EFAULT 10014L +#define SOCK_EINVAL 10022L +#define SOCK_EMFILE 10024L +#define SOCK_EWOULDBLOCK 10035L /*WSAEWOULDBLOCK*/ +#define SOCK_EINPROGRESS 10036L /*WSAEINPROGRESS*/ +#define SOCK_EALREADY 10037L +#define SOCK_ENOTSOCK 10038L +#define SOCK_EDESTADDRREQ 10039L +#define SOCK_EMSGSIZE 10040L +#define SOCK_EPROTOTYPE 10041L +#define SOCK_ENOPROTOOPT 10042L +#define SOCK_EPROTONOSUPPORT 10043L +#define SOCK_ESOCKTNOSUPPORT 10044L +#define SOCK_EOPNOTSUPP 10045L +#define SOCK_EPFNOSUPPORT 10046L +#define SOCK_EAFNOSUPPORT 10047L +#define SOCK_EADDRINUSE 10048L +#define SOCK_EADDRNOTAVAIL 10049L +#define SOCK_ENETDOWN 10050L +#define SOCK_ENETUNREACH 10051L +#define SOCK_ENETRESET 10051L +#define SOCK_ECONNABORTED 10053L +#define SOCK_ECONNRESET 10054L +#define SOCK_ENOBUFS 10055L +#define SOCK_EISCONN 10056L +#define SOCK_ENOTCONN 10057L +#define SOCK_ESHUTDOWN 10058L +#define SOCK_ETOOMANYREFS 10059L +#define SOCK_ETIMEDOUT 10060L +#define SOCK_ECONNREFUSED 10061L +#define SOCK_ELOOP 10062L +#define SOCK_ENAMETOOLONG 10063L +#define SOCK_EHOSTDOWN 10064L +#define SOCK_EHOSTUNREACH 10065L +#define SOCK_ENOTEMPTY 10066L +#define SOCK_EPROCLIM 10067L +#define SOCK_EUSERS 10068L +#define SOCK_EDQUOT 10069L +#define SOCK_ESTALE 10070L +#define SOCK_EREMOTE 10071L +#define SOCK_SYSNOTREADY 10091L +#define SOCK_VERNOTSUPPORTED 10092L +#define SOCK_NOTINITIALISED 10093L +#define SOCK_EDISCON 10101L +#define SOCK_ENOMORE 10102L +#define SOCK_ECANCELLED 10103L +#define SOCK_EINVALIDPROCTABLE 10104L +#define SOCK_EINVALIDPROVIDER 10105L +#define SOCK_EPROVIDERFAILEDINIT 10106L +#define SOCK_SYSCALLFAILURE 10107L +#define SOCK_SERVICE_NOT_FOUND 10108L +#define SOCK_TYPE_NOT_FOUND 10109L +#define SOCK__E_NO_MORE 10110L +#define SOCK__E_CANCELLED 10111L +#define SOCK_EREFUSED 10112L +#define SOCK_HOST_NOT_FOUND 11001L +#define SOCK_TRY_AGAIN 11002L +#define SOCK_NO_RECOVERY 11003L +#define SOCK_NO_DATA 11004L +// +typedef unsigned char u_char; +typedef unsigned short u_short; +typedef unsigned int u_int; +typedef unsigned long u_long; +typedef unsigned __int64 u_int64; +// +// +#define SOCK_AF_UNSPEC 0 /* unspecified */ +#define SOCK_AF_INET 2 /* internetwork: UDP, TCP, etc. */ +#define SOCK_AF_INET6 28 + +typedef int SOCK_SOCKET; + +#define SOCK_INADDR_ANY 0x00000000UL +#define SOCK_INADDR_LOOPBACK 0x7F000001UL + + +#define SOCK_SOCK_STREAM 1 +#define SOCK_SOCK_DGRAM 2 +#define SOCK_SOCK_RAW 3 +#define SOCK_SOCK_RDM 4 +#define SOCK_SOCK_SEQPACKET 5 +#define SOCK_SOCK_PACK_EX 6 + +#define SOCK_TCP_NODELAY 0x0001 + +#define SOCK_IPPROTO_IP 0 +#define SOCK_IPPROTO_ICMP 1 +#define SOCK_IPPROTO_IGMP 2 +#define SOCK_IPPROTO_IPV4 4 /* IP-in-IP encapsulation */ +#define SOCK_IPPROTO_TCP 6 +#define SOCK_IPPROTO_PUP 12 +#define SOCK_IPPROTO_UDP 17 +#define SOCK_IPPROTO_IDP 22 +#define SOCK_IPPROTO_IPV6 41 +#define SOCK_IPPROTO_IPv6RoutingHeader 43 +#define SOCK_IPPROTO_IPv6FragmentHeader 44 +#define SOCK_IPPROTO_RDP 46 +#define SOCK_IPPROTO_GRE 47 +#define SOCK_IPPROTO_IPSecEncapsulatingSecurityPayload 50 +#define SOCK_IPPROTO_IPSecAuthenticationHeader 51 +#define SOCK_IPPROTO_IcmpV6 58 +#define SOCK_IPPROTO_IPv6NoNextHeader 59 +#define SOCK_IPPROTO_IPv6DestinationOptions 60 +#define SOCK_IPPROTO_ND 77 +#define SOCK_IPPROTO_OSPF 89 +#define SOCK_IPPROTO_TPACKET 127 +#define SOCK_IPPROTO_RAW 255 +#define SOCK_IPPROTO_IPX 1000 +#define SOCK_IPPROTO_SPX 1256 +#define SOCK_IPPROTO_SPXII 1257 +#define SOCK_SOL_SOCKET 0xFFFF + +/* Option flags per-socket */ +#define SOCK_SOCKO_DEBUG 0x0001 // turn on debugging info recording +#define SOCK_SOCKO_NOCHECKSUM 0x0001 +#define SOCK_SOCKO_ACCEPTCONNECTION 0x0002 // socket has had listen() +#define SOCK_SOCKO_REUSEADDRESS 0x0004 // allow local address reuse +#define SOCK_SOCKO_KEEPALIVE 0x0008 // keep connections alive +#define SOCK_SOCKO_DONTROUTE 0x0010 // just use interface addresses +#define SOCK_SOCKO_BROADCAST 0x0020 // permit sending of broadcast msgs +#define SOCK_SOCKO_USELOOPBACK 0x0040 // bypass hardware when possible +#define SOCK_SOCKO_LINGER 0x0080 // linger on close if data present +#define SOCK_SOCKO_OUTOFBANDINLINE 0x0100 // leave received OOB data in line +#define SOCK_SOCKO_DONTLINGER ~SOCK_SOCKO_LINGER +#define SOCK_SOCKO_EXCLUSIVEADDRESSUSE ~SOCK_SOCKO_REUSEADDRESS // disallow local address reuse +#define SOCK_SOCKO_SENDBUFFER 0x1001 // send buffer size +#define SOCK_SOCKO_SNDBUF SOCK_SOCKO_SENDBUFFER +#define SOCK_SOCKO_RECEIVEBUFFER 0x1002 // receive buffer size +#define SOCK_SOCKO_RCVBUF SOCK_SOCKO_RECEIVEBUFFER +#define SOCK_SOCKO_SENDLOWWATER 0x1003 // send low-water mark +#define SOCK_SOCKO_RECEIVELOWWATER 0x1004 // receive low-water mark +#define SOCK_SOCKO_SENDTIMEOUT 0x1005 // send timeout +#define SOCK_SOCKO_RECEIVETIMEOUT 0x1006 // receive timeout +#define SOCK_SOCKO_ERROR 0x1007 // get error status and clear +#define SOCK_SOCKO_UPDATE_ACCEPT_CTX 0x700B // This option updates the properties of the socket which are inherited from the listening socket. +#define SOCK_SOCKO_UPDATE_CONNECT_CTX 0x7010 // This option updates the properties of the socket after the connection is established. +#define SOCK_SOCKO_MAXCONNECTIONS 0x7FFFFFFF // Maximum queue length specifiable by listen. + +/* Option flags per-IP */ +#define SOCK_IPO_OPTIONS 0x0001 +#define SOCK_IPO_HDRINCL 0x0002 +#define SOCK_IPO_TOS 0x0003 +#define SOCK_IPO_TTL 0x0004 +#define SOCK_IPO_MULTICAST_IF 0x0009 +#define SOCK_IPO_MULTICAST_TTL 0x000A +#define SOCK_IPO_MULTICAST_LOOP 0x000B +#define SOCK_IPO_ADD_MEMBERSHIP 0x000C +#define SOCK_IPO_DROP_MEMBERSHIP 0x000D +#define SOCK_IPO_IP_DONTFRAGMENT 0x000E +#define SOCK_IPO_ADD_SOURCE_MEMBERSHIP 0x000F +#define SOCK_IPO_DROP_SOURCE_MEMBERSHIP 0x0010 +#define SOCK_IPO_BLOCK_SOURCE 0x0011 +#define SOCK_IPO_UBLOCK_SOURCE 0x0012 +#define SOCK_IPO_PACKET_INFO 0x0013 + + +#define SOCK_SOCKET_ERROR -1 +#define SOCK_WSATRY_AGAIN 11002 +#define SOCK_WSAEINVAL 10022 +#define SOCK_WSANO_RECOVERY 11003 +#define SOCK_WSAEAFNOSUPPORT 10047 +#define SOCK_WSA_NOT_ENOUGH_MEMORY -1 +#define SOCK_WSAHOST_NOT_FOUND 11001 +#define SOCK_WSATYPE_NOT_FOUND 10109 +#define SOCK_WSAESOCKTNOSUPPORT 10044 +// +#define SOCK_IOCPARM_MASK 0x7f /* parameters must be < 128 bytes */ +#define SOCK_IOC_VOID 0x20000000 /* no parameters */ +#define SOCK_IOC_OUT 0x40000000 /* copy out parameters */ +#define SOCK_IOC_IN 0x80000000 /* copy in parameters */ +#define SOCK_IOC_INOUT (SOCK_IOC_IN|SOCK_IOC_OUT) + /* 0x20000000 distinguishes new & + old ioctl's */ +#define SOCK__IO(x,y) (SOCK_IOC_VOID|((x)<<8)|(y)) + +#define SOCK__IOR(x,y,t) (SOCK_IOC_OUT|(((long)sizeof(t)&SOCK_IOCPARM_MASK)<<16)|((x)<<8)|(y)) + +#define SOCK__IOW(x,y,t) (SOCK_IOC_IN|(((long)sizeof(t)&SOCK_IOCPARM_MASK)<<16)|((x)<<8)|(y)) +// +#define SOCK_FIONREAD SOCK__IOR('f', 127, u_long) /* get # bytes to read */ +#define SOCK_FIONBIO SOCK__IOW('f', 126, u_long) /* set/clear non-blocking i/o */ +#define SOCK_FIOASYNC SOCK__IOW('f', 125, u_long) /* set/clear async i/o */ +// + +#define SOCK_FD_SETSIZE 256 +#define SOCK_MAX_ADDR_SIZE 14 + +typedef struct SOCK_fd_set { + unsigned int fd_count; + int fd_array[SOCK_FD_SETSIZE]; +}SOCK_fd_set; + +typedef struct SOCK_sockaddr { + unsigned short sa_family; /* address family */ + char sa_data[SOCK_MAX_ADDR_SIZE]; /* up to SOCK_MAX_ADDR_SIZE bytes of direct address */ +}SOCK_sockaddr; + +CT_ASSERT_UNIQUE_NAME(sizeof(SOCK_sockaddr)==(16), SOCK_SOCKADDR) + +typedef struct GNU_PACKED SOCK_in_addr{ + union GNU_PACKED { + struct GNU_PACKED { + u_char s_b1,s_b2,s_b3,s_b4; + } S_un_b; + + struct GNU_PACKED { + u_short s_w1,s_w2; + } S_un_w; + + u_long S_addr; + } S_un; +} SOCK_in_addr; + +typedef struct GNU_PACKED SOCK_sockaddr_in { + short sin_family; + u_short sin_port; + SOCK_in_addr sin_addr; + char sin_zero[8]; +} SOCK_sockaddr_in; + +CT_ASSERT_UNIQUE_NAME(sizeof(SOCK_sockaddr_in)==16, SOCK_SOCKADDR_IN) + +typedef struct SOCK_addrinfo +{ + int ai_flags; + int ai_family; + int ai_socktype; + int ai_protocol; + size_t ai_addrlen; + char* ai_canonname; + struct SOCK_sockaddr* ai_addr; + struct SOCK_addrinfo* ai_next; +}SOCK_addrinfo; + +typedef struct SOCK_ip_mreq +{ + SOCK_in_addr imr_multiaddr; /* IPv4 Class D multicast address */ + SOCK_in_addr imr_interface; /* IPv4 address of local interface */ +} SOCK_ip_mreq; + +typedef struct SOCK_discoveryinfo +{ + uint32_t ipaddr; + uint32_t macAddressLen; + char macAddressBuffer[64]; +} SOCK_discoveryinfo; + +#define SOCK_MAKE_IP_ADDR(w,x,y,z) ((uint32_t)(w) & 0xFF)<<24 | ((uint32_t)(x) & 0xff)<<16 | ((uint32_t)(y) & 0xff)<<8 | ((uint32_t)(z) & 0xff) +#define SOCK_MAKE_IP_ADDR_LITTLEEND(w,x,y,z) ((uint32_t)(z) & 0xFF)<<24 | ((uint32_t)(y) & 0xff)<<16 | ((uint32_t)(x) & 0xff)<<8 | ((uint32_t)(w) & 0xff) + +#ifndef SOCKET_READ_PEEK_OPTION +#define SOCKET_READ_PEEK_OPTION 2 +#endif + +#ifndef DEBUG_SOCKET_PORT +#define DEBUG_SOCKET_PORT 26000 +#endif + +#ifndef SOCK_DISCOVERY_MULTICAST_PORT +#define SOCK_DISCOVERY_MULTICAST_PORT 26001 +#endif + +//A multicast address is an IP address which belongs to classe D included in the range between 224.0.0.0 and 239.255.255.255 +#ifndef SOCK_DISCOVERY_MULTICAST_IPADDR +#define SOCK_DISCOVERY_MULTICAST_IPADDR SOCK_MAKE_IP_ADDR(234,102,98,44) +#endif + +#ifndef SOCK_DISCOVERY_MULTICAST_IPADDR_SND +#define SOCK_DISCOVERY_MULTICAST_IPADDR_SND SOCK_MAKE_IP_ADDR(234,102,98,45) +#endif + +#ifndef SOCK_DISCOVERY_MULTICAST_TOKEN +#define SOCK_DISCOVERY_MULTICAST_TOKEN "DOTNETMF" +#endif + +#define SOCKET_EVENT_WAIT_FOREVER 0xFFFFFFFF +#define SOCKET_EVENT_FLAG_SOCKETS_SHUTDOWN 0x00000001 +#define SOCKET_EVENT_FLAG_SOCKETS_READY 0x00000002 +#define SOCKET_EVENT_FLAG_SOCKET 0x00000004 + +/* + * Structure used in select() call, taken from the BSD file sys/time.h. + */ +typedef struct SOCK_timeval { + long tv_sec; /* seconds */ + long tv_usec; /* and microseconds */ +}SOCK_timeval; + + +#define SOCK_NETWORKCONFIGURATION_FLAGS_DHCP 0x00000001 +#define SOCK_NETWORKCONFIGURATION_FLAGS_DYNAMIC_DNS 0x00000002 + +/// Bits 19-16 of HAL_Configuration_NetworkInterface.flags: Type of HAL_Configuration_NetworkInterface +/// 0 - NetworkInterface +/// 1 - Wireless +#define SOCK_NETWORKCONFIGURATION_FLAGS_NETWORK_INTERFACE 0 +#define SOCK_NETWORKCONFIGURATION_FLAGS_WIRELESS 1 +#define SOCK_NETWORKCONFIGURATION_FLAGS_TYPE__mask 0x000F0000 +#define SOCK_NETWORKCONFIGURATION_FLAGS_TYPE__shift 16 +#define SOCK_NETWORKCONFIGURATION_FLAGS_TYPE__value(x) (((x) & SOCK_NETWORKCONFIGURATION_FLAGS_TYPE__mask) >> SOCK_NETWORKCONFIGURATION_FLAGS_TYPE__shift) +#define SOCK_NETWORKCONFIGURATION_FLAGS_TYPE__set(x) (((x) << SOCK_NETWORKCONFIGURATION_FLAGS_TYPE__shift) & SOCK_NETWORKCONFIGURATION_FLAGS_TYPE__mask) +#define SOCK_NETWORKCONFIGURATION_FLAGS_SUBINDEX__mask 0x00F00000 +#define SOCK_NETWORKCONFIGURATION_FLAGS_SUBINDEX__shift 20 +#define SOCK_NETWORKCONFIGURATION_FLAGS_SUBINDEX__value(x) (((x) & SOCK_NETWORKCONFIGURATION_FLAGS_SUBINDEX__mask) >> SOCK_NETWORKCONFIGURATION_FLAGS_SUBINDEX__shift) +#define SOCK_NETWORKCONFIGURATION_FLAGS_SUBINDEX__set(x) (((x) << SOCK_NETWORKCONFIGURATION_FLAGS_SUBINDEX__shift) & SOCK_NETWORKCONFIGURATION_FLAGS_SUBINDEX__mask) + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH System.Net.NetworkInformation.NetworkInterface.UpdateOperation (in managed code) !!! // +//////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +enum UpdateOperation +{ + UpdateOperation_Invalid = 0x00, + UpdateOperation_Dns = 0x01, + UpdateOperation_Dhcp = 0x02, + UpdateOperation_DhcpRenew = 0x04, + UpdateOperation_DhcpRelease = 0x08, + UpdateOperation_Mac = 0x10, +}; + +#define SOCK_NETWORKCONFIGURATION_INTERFACETYPE_UNKNOWN 0 +#define SOCK_NETWORKCONFIGURATION_INTERFACETYPE_ETHERNET 6 +#define SOCK_NETWORKCONFIGURATION_INTERFACETYPE_WIRELESS_80211 71 + + +//--// + +/// +/// Keep these values in sync with the manged code enumeration Wireless80211.AuthenticationType in wireless.cs +/// +// Wireless flags bits 0 - 3 +#define WIRELESS_FLAG_AUTHENTICATION_NONE 0 +#define WIRELESS_FLAG_AUTHENTICATION_EAP 1 +#define WIRELESS_FLAG_AUTHENTICATION_PEAP 2 +#define WIRELESS_FLAG_AUTHENTICATION_WCN 3 +#define WIRELESS_FLAG_AUTHENTICATION_OPEN 4 +#define WIRELESS_FLAG_AUTHENTICATION_SHARED 5 +#define WIRELESS_FLAG_AUTHENTICATION__shift 0 +#define WIRELESS_FLAG_AUTHENTICATION__mask 0x0000000F +#define WIRELESS_FLAG_AUTHENTICATION__value(x) (((x) & WIRELESS_FLAG_AUTHENTICATION__mask) >> WIRELESS_FLAG_AUTHENTICATION__shift) +#define WIRELESS_FLAG_AUTHENTICATION__set(x) (((x) << WIRELESS_FLAG_AUTHENTICATION__shift) & WIRELESS_FLAG_AUTHENTICATION__mask) + +/// +/// Keep these values in sync with the manged code enumeration Wireless80211.EncryptionType in wireless.cs +/// + +// Wireless flags bits 4 - 7 +#define WIRELESS_FLAG_ENCRYPTION_NONE 0 +#define WIRELESS_FLAG_ENCRYPTION_WEP 1 +#define WIRELESS_FLAG_ENCRYPTION_WPA 2 +#define WIRELESS_FLAG_ENCRYPTION_WPAPSK 3 +#define WIRELESS_FLAG_ENCRYPTION_Certificate 4 +#define WIRELESS_FLAG_ENCRYPTION__shift 4 +#define WIRELESS_FLAG_ENCRYPTION__mask 0x000000F0 +#define WIRELESS_FLAG_ENCRYPTION__value(x) (((x) & WIRELESS_FLAG_ENCRYPTION__mask) >> WIRELESS_FLAG_ENCRYPTION__shift) +#define WIRELESS_FLAG_ENCRYPTION__set(x) (((x) << WIRELESS_FLAG_ENCRYPTION__shift) & WIRELESS_FLAG_ENCRYPTION__mask) + +/// +/// Keep these values in sync with the manged code enumeration Wireless80211.RadioType in wireless.cs +/// + +// Wireless flags bits 8 - 11 +#define WIRELESS_FLAG_RADIO_a 1 +#define WIRELESS_FLAG_RADIO_b 2 +#define WIRELESS_FLAG_RADIO_g 4 +#define WIRELESS_FLAG_RADIO_n 8 +#define WIRELESS_FLAG_RADIO__shift 8 +#define WIRELESS_FLAG_RADIO__mask 0x00000F00 +#define WIRELESS_FLAG_RADIO__value(x) (((x) & WIRELESS_FLAG_RADIO__mask) >> WIRELESS_FLAG_RADIO__shift) +#define WIRELESS_FLAG_RADIO__set(x) (((x) << WIRELESS_FLAG_RADIO__shift) & WIRELESS_FLAG_RADIO__mask) + + +// Wireless flags bits 12 - 15 +#define WIRELESS_FLAG_DATA_ENCRYPTED 1 +#define WIRELESS_FLAG_DATA__shift 12 +#define WIRELESS_FLAG_DATA__mask 0x0000F000 +#define WIRELESS_FLAG_DATA__value(x) (((x) & WIRELESS_FLAG_DATA__mask) >> WIRELESS_FLAG_DATA__shift) +#define WIRELESS_FLAG_DATA__set(x) (((x) << WIRELESS_FLAG_DATA__shift) & WIRELESS_FLAG_DATA__mask) + + +//extern const ConfigurationSector g_ConfigurationSector; + +//--// + +#define SOCK_htons(x) ( (((x) & 0x000000FFUL) << 8) | (((x) & 0x0000FF00UL) >> 8) ) +#define SOCK_htonl(x) ( (((x) & 0x000000FFUL) << 24) | (((x) & 0x0000FF00UL) << 8) | (((x) & 0x00FF0000UL) >> 8) | (((x) & 0xFF000000UL) >> 24) ) +#define SOCK_ntohs(x) SOCK_htons(x) +#define SOCK_ntohl(x) ( (((x) & 0x000000FFUL) << 24) | (((x) & 0x0000FF00UL) << 8) | (((x) & 0x00FF0000UL) >> 8) | (((x) & 0xFF000000UL) >> 24) ) + +#define SOCK_FD_ZERO(x) memset(x, 0, sizeof(*x)) +__inline bool SOCK_FD_ISSET(int y, SOCK_fd_set* x) +{ + GLOBAL_LOCK_SOCKETS(irq); + + for(int i=0; i<(int)x->fd_count; i++) + { + if(x->fd_array[i] == y) + { + return true; + } + } + return false; +} + +__inline void SOCK_FD_SET(int y, SOCK_fd_set* x) +{ + if(SOCK_FD_ISSET(y, x)) return; + + GLOBAL_LOCK_SOCKETS(irq); + + if(x->fd_count < SOCK_FD_SETSIZE) + { + x->fd_array[x->fd_count++] = y; + } + else + { + ASSERT(false); + } +} + +__inline void SOCK_FD_CLR(int y, SOCK_fd_set* x) +{ + GLOBAL_LOCK_SOCKETS(irq); + + for(int i=0; i<(int)x->fd_count; i++) + { + if(x->fd_array[i] == y) + { + x->fd_count--; + + if(i < (int)x->fd_count) + { + x->fd_array[i] = x->fd_array[x->fd_count]; + } + x->fd_array[x->fd_count] = 0; + break; + } + } +} + +#endif //NANOCLR_SOCK_STRUCTURES + +#ifndef DEBUG_SOCKET_PORT // default debug socket port +#define DEBUG_SOCKET_PORT 26000 +#endif + + +//struct HAL_Configuration_NetworkInterface; +struct HAL_Configuration_Wireless80211; + +//--// + +bool Network_Initialize(); +bool Network_Uninitialize(); + +bool Network_Interface_Bind(int index); +int Network_Interface_Open(int index); +bool Network_Interface_Close(int index); +int Network_Interface_Disconnect(int index); +int Network_Interface_Connect(int index, const char * ssid, const char * passphase, int options); +bool Network_Interface_Start_Scan(int index); + +// Wireless AP methods +void Network_Interface_Add_Station(uint16_t index, uint8_t * macAddress); +void Network_Interface_Remove_Station(uint16_t index); +int Network_Interface_Max_Stations(); +bool Network_Interface_Get_Station(uint16_t index, uint8_t * macAddress, uint8_t * rssi, uint32_t * phyModes); +void Network_Interface_Deauth_Station(uint16_t index); + +//--// + +// Network_Interface_Connect options +#define NETWORK_CONNECT_SAVE_CONFIG 1 +#define NETWORK_CONNECT_RECONNECT 2 + +////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH System.Net.NetworkInformation.NetworkChange.NetworkEventType (in managed code) !!! // +////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +enum NetworkEventType +{ + NetworkEventType_Invalid = 0, + NetworkEventType_AvailabilityChanged = 1, + NetworkEventType_AddressChanged = 2, + NetworkEventType_APClientChanged = 3, +}; + +////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.WiFi.WiFiEventType (in managed code) !!! // +////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +enum WiFiEventType +{ + WiFiEventType_Invalid = 0, + WiFiEventType_ScanComplete = 1, +}; + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH System.Net.NetworkInformation.NetworkChange.NetworkEventFlags (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +enum NetworkEventFlags +{ + NetworkEventFlags_NetworkNOTAvailable = 0x00, + NetworkEventFlags_NetworkAvailable = 0x01, +}; + +void Network_PostEvent(unsigned int eventType, unsigned int flags, unsigned int index); + +//--// +// Debugger Methods +bool SOCKETS_DbgInitialize( int ComPortNum ); +bool SOCKETS_DbgUninitialize( int ComPortNum ); +int SOCKETS_Write( int ComPortNum, const char* Data, size_t size ); +int SOCKETS_Read( int ComPortNum, char* Data, size_t size ); +bool SOCKETS_Flush( int ComPortNum ); +bool SOCKETS_UpgradeToSsl( int ComPortNum, const uint8_t* pCACert, uint32_t caCertLen, const uint8_t* pDeviceCert, uint32_t deviceCertLen, LPCSTR szTargetHost ); +bool SOCKETS_IsUsingSsl( int32_t ComPortNum ); + + +void SOCKETS_CloseConnections(); +// RTIP +bool SOCKETS_ProcessSocketActivity(SOCK_SOCKET signalSocket); +//LWIP +void SOCKETS_CreateTcpIpProcessor(HAL_CALLBACK_FPN callback, void* arg); +void SOCKETS_RestartTcpIpProcessor(uint32_t timeFromNow_us); + +// BSD style Sockets +int SOCK_socket( int family, int type, int protocol ); +int SOCK_bind( int socket, const struct SOCK_sockaddr* address, int addressLen ); +int SOCK_connect(int socket, const struct SOCK_sockaddr* address, int addressLen ); +int SOCK_send(int socket, const char* buf, int len, int flags ); +int SOCK_recv(int socket, char* buf, int len, int flags ); +int SOCK_close(int socket); +int SOCK_listen( int socket, int backlog ); +int SOCK_accept( int socket, struct SOCK_sockaddr* address, int* addressLen ); +int SOCK_shutdown( int socket, int how ); +int SOCK_getaddrinfo( const char* nodename, char* servname, const struct SOCK_addrinfo* hints, struct SOCK_addrinfo** res ); +void SOCK_freeaddrinfo( struct SOCK_addrinfo* ai ); +int SOCK_ioctl( int socket, int cmd, int* data ); +int SOCK_getlasterror(); +int SOCK_getsocklasterror( int socket ); +int SOCK_select( int socket, SOCK_fd_set* readfds, SOCK_fd_set* writefds, SOCK_fd_set* except, const struct SOCK_timeval* timeout ); +int SOCK_setsockopt( int socket, int level, int optname, const char* optval, int optlen ); +int SOCK_getsockopt( int socket, int level, int optname, char* optval, int* optlen ); +int SOCK_getpeername( int socket, struct SOCK_sockaddr* name, int* namelen ); +int SOCK_getsockname( int socket, struct SOCK_sockaddr* name, int* namelen ); +int SOCK_recvfrom( int s, char* buf, int len, int flags, struct SOCK_sockaddr* from, int* fromlen ); +int SOCK_sendto( int s, const char* buf, int len, int flags, const struct SOCK_sockaddr* to, int tolen ); + +//network adapter settings +HRESULT SOCK_CONFIGURATION_LoadAdapterConfiguration(HAL_Configuration_NetworkInterface* config, uint32_t interfaceIndex); +HRESULT SOCK_CONFIGURATION_UpdateAdapterConfiguration(HAL_Configuration_NetworkInterface* config, uint32_t interfaceIndex, uint32_t updateFlags); +HRESULT SOCK_CONFIGURATION_LoadConfiguration(HAL_Configuration_NetworkInterface* config, uint32_t interfaceIndex); + +//--// SSL + +typedef void (*SSL_DATE_TIME_FUNC)(DATE_TIME_INFO* pdt); + +#define SSL_RESULT__WOULD_BLOCK -2 + +bool SSL_Initialize (); +bool SSL_Uninitialize(); +bool SSL_ServerInit ( int sslMode, int sslVerify, const char* certificate, int certLength, const uint8_t* privateKey, int privateKeyLength, const char* password, int passwordLength, int& sslContextHandle ); +bool SSL_ClientInit ( int sslMode, int sslVerify, const char* certificate, int certLength, const uint8_t* privateKey, int privateKeyLength, const char* password, int passwordLength, int& sslContextHandle ); +bool SSL_AddCertificateAuthority( int sslContextHandle, const char* certificate, int certLength, const char* certPassword ); +bool SSL_ExitContext( int sslContextHandle ); +int SSL_Accept ( int socket, int sslContextHandle ); +int SSL_Connect ( int socket, const char* szTargetHost, int sslContextHandle ); +int SSL_Write ( int socket, const char* Data, size_t size ); +int SSL_Read ( int socket, char* Data, size_t size ); +int SSL_CloseSocket( int socket ); +bool SSL_ParseCertificate( const char* certificate, size_t certLength, const char* password, X509CertData* certData ); +int SSL_DecodePrivateKey( const unsigned char *key, size_t keyLength, const unsigned char *password, size_t passwordLength ); +int SSL_DataAvailable( int socket ); + +//--// + + +bool HAL_SOCK_Initialize(); +bool HAL_SOCK_Uninitialize(); +void HAL_SOCK_SignalSocketThread(); +int HAL_SOCK_socket( int family, int type, int protocol ); +int HAL_SOCK_bind( int socket, const struct SOCK_sockaddr* address, int addressLen ); +int HAL_SOCK_connect(int socket, const struct SOCK_sockaddr* address, int addressLen ); +int HAL_SOCK_send(int socket, const char* buf, int len, int flags ); +int HAL_SOCK_recv(int socket, char* buf, int len, int flags ); +int HAL_SOCK_close(int socket); +int HAL_SOCK_listen( int socket, int backlog ); +int HAL_SOCK_accept( int socket, struct SOCK_sockaddr* address, int* addressLen ); +int HAL_SOCK_shutdown( int socket, int how ); +int HAL_SOCK_getaddrinfo( const char* nodename, char* servname, const struct SOCK_addrinfo* hints, struct SOCK_addrinfo** res ); +void HAL_SOCK_freeaddrinfo( struct SOCK_addrinfo* ai ); +int HAL_SOCK_ioctl( int socket, int cmd, int* data ); +int HAL_SOCK_getlasterror(); +int HAL_SOCK_getsocklasterror( int socket ); +int HAL_SOCK_select( int socket, SOCK_fd_set* readfds, SOCK_fd_set* writefds, SOCK_fd_set* except, const struct SOCK_timeval* timeout ); +int HAL_SOCK_setsockopt( int socket, int level, int optname, const char* optval, int optlen ); +int HAL_SOCK_getsockopt( int socket, int level, int optname, char* optval, int* optlen ); +int HAL_SOCK_getpeername( int socket, struct SOCK_sockaddr* name, int* namelen ); +int HAL_SOCK_getsockname( int socket, struct SOCK_sockaddr* name, int* namelen ); +int HAL_SOCK_recvfrom( int s, char* buf, int len, int flags, struct SOCK_sockaddr* from, int* fromlen ); +int HAL_SOCK_sendto( int s, const char* buf, int len, int flags, const struct SOCK_sockaddr* to, int tolen ); + +HRESULT HAL_SOCK_CONFIGURATION_LoadAdapterConfiguration(HAL_Configuration_NetworkInterface* config, uint32_t interfaceIndex); +HRESULT HAL_SOCK_CONFIGURATION_UpdateAdapterConfiguration(HAL_Configuration_NetworkInterface* config, uint32_t interfaceIndex, uint32_t updateFlags); + +void* HAL_SOCK_GlobalLockContext(); +void HAL_SOCK_EventsSet(uint32_t events); + +//--// + +#endif // _DRIVERS_SOCKETS_DECL_H_ diff --git a/source/native/nf-interpreter/src/PAL/Include/nanoPAL_Time.h b/source/native/nf-interpreter/src/PAL/Include/nanoPAL_Time.h new file mode 100644 index 00000000..597427e3 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/Include/nanoPAL_Time.h @@ -0,0 +1,28 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _NANOPAL_TIME_H_ +#define _NANOPAL_TIME_H_ 1 + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/// +/// Initializes PAL Time drivers, must be called before any of the Time_* PAL +/// methods could be used. +/// +HRESULT Time_Initialize ( ); +HRESULT Time_Uninitialize ( ); +void Time_SetCompare ( uint64_t compareValueTicks ); + +#ifdef __cplusplus +} +#endif + +#endif //_NANOPAL_TIME_H_ diff --git a/source/native/nf-interpreter/src/PAL/Lwip/lwIP_Sockets.cpp b/source/native/nf-interpreter/src/PAL/Lwip/lwIP_Sockets.cpp new file mode 100644 index 00000000..0e5c0c8b --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/Lwip/lwIP_Sockets.cpp @@ -0,0 +1,1341 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + + +#include "LWIP_sockets.h" + +extern "C" +{ +#include "lwip\init.h" +#include "lwip\tcpip.h" +#include "lwip\dns.h" +#include "lwip\netifapi.h" +#include "lwip\Netdb.h" +#include "lwip\tcp.h" +#include "lwip\Sockets.h" +#include "lwip\dhcp.h" +#include "lwip\netif.h" +} + + +int errorCode; + +//--// + +#if defined(DEBUG) +#define DEBUG_HANDLE_SOCKET_ERROR(t,a) +// assume there is something to add in later?? +#else +#define DEBUG_HANDLE_SOCKET_ERROR(t,a) +#endif + +struct netif *netif_find_interface(int num); + +// + +// declaration of function not available in standard lwIP API +extern "C" +{ +extern uint32_t lwip_socket_get_err(int s); +} +//--// + +LWIP_SOCKETS_Driver g_LWIP_SOCKETS_Driver; + +//--// +#if LWIP_NETIF_STATUS_CALLBACK == 1 +static HAL_CONTINUATION PostAddressChangedContinuation; +#endif +#if LWIP_NETIF_LINK_CALLBACK == 1 +static HAL_CONTINUATION PostAvailabilityOnContinuation; +static HAL_CONTINUATION PostAvailabilityOffContinuation; +#endif + +void LWIP_SOCKETS_Driver::PostAddressChanged(void* arg) +{ + (void)arg; + + Network_PostEvent(NetworkEventType_AddressChanged, 0, 0); +} + +void LWIP_SOCKETS_Driver::PostAvailabilityOn(void* arg) +{ + (void)arg; + + Network_PostEvent(NetworkEventType_AvailabilityChanged, NetworkEventFlags_NetworkAvailable, 0); +} + +void LWIP_SOCKETS_Driver::PostAvailabilityOff(void* arg) +{ + (void)arg; + + Network_PostEvent(NetworkEventType_AvailabilityChanged, NetworkEventFlags_NetworkNOTAvailable, 0); +} + +#if LWIP_NETIF_LINK_CALLBACK == 1 +void LWIP_SOCKETS_Driver::Link_callback(struct netif *netif) +{ + if (netif_is_link_up(netif)) + { + if (!PostAvailabilityOnContinuation.IsLinked()) + PostAvailabilityOnContinuation.Enqueue(); + } + else + { + if (!PostAvailabilityOffContinuation.IsLinked()) + PostAvailabilityOffContinuation.Enqueue(); + } + Events_Set(SYSTEM_EVENT_FLAG_SOCKET); + Events_Set(SYSTEM_EVENT_FLAG_NETWORK); +} +#endif + +#if LWIP_NETIF_STATUS_CALLBACK == 1 +void LWIP_SOCKETS_Driver::Status_callback(struct netif *netif) +{ + if (!PostAddressChangedContinuation.IsLinked()) + PostAddressChangedContinuation.Enqueue(); + +#if !defined(BUILD_RTM) + // lcd_printf("\f\n\n\n\n\n\nLink Update: %s\n", (netif_is_up(netif) ? "UP " : "DOWN")); + // lcd_printf(" IP: %d.%d.%d.%d\n", (netif->ip_addr.addr >> 0) & 0xFF, + // (netif->ip_addr.addr >> 8) & 0xFF, + // (netif->ip_addr.addr >> 16) & 0xFF, + // (netif->ip_addr.addr >> 24) & 0xFF); + // lcd_printf(" SM: %d.%d.%d.%d\n", (netif->netmask.addr >> 0) & 0xFF, + // (netif->netmask.addr >> 8) & 0xFF, + // (netif->netmask.addr >> 16) & 0xFF, + // (netif->netmask.addr >> 24) & 0xFF); + // lcd_printf(" GW: %d.%d.%d.%d\n", (netif->gw.addr >> 0) & 0xFF, + // (netif->gw.addr >> 8) & 0xFF, + // (netif->gw.addr >> 16) & 0xFF, + // (netif->gw.addr >> 24) & 0xFF); + +//FIXME debug_printf("IP Address: %d.%d.%d.%d\n", (netif->ip_addr.u_addr.ip4.addr >> 0) & 0xFF, +// (netif->ip_addr.u_addr.ip4.addr >> 8) & 0xFF, +// (netif->ip_addr.u_addr.ip4.addr >> 16) & 0xFF, +// (netif->ip_addr.u_addr.ip4.addr >> 24) & 0xFF); +#if LWIP_DNS + if (netif->flags & NETIF_FLAG_ETHARP) + { + //ip_addr_t * dns1 = dns_getserver(0); + //ip_addr_t * dns2 = dns_getserver(1); + + // lcd_printf(" dns1: %d.%d.%d.%d\n", (dns1.addr >> 0) & 0xFF, + // (dns1.addr >> 8) & 0xFF, + // (dns1.addr >> 16) & 0xFF, + // (dns1.addr >> 24) & 0xFF); + + // lcd_printf(" dns2: %d.%d.%d.%d\n", (dns2.addr >> 0) & 0xFF, + // (dns2.addr >> 8) & 0xFF, + // (dns2.addr >> 16) & 0xFF, + // (dns2.addr >> 24) & 0xFF); + } +#endif +#endif + Events_Set(SYSTEM_EVENT_FLAG_SOCKET); + Events_Set(SYSTEM_EVENT_FLAG_NETWORK); +} +#endif + +bool LWIP_SOCKETS_Driver::Initialize() +{ + NATIVE_PROFILE_PAL_NETWORK(); + + struct netif *networkInterface; + HAL_Configuration_NetworkInterface networkConfiguration; + int interfaceNumber; + +#if LWIP_NETIF_STATUS_CALLBACK == 1 + PostAddressChangedContinuation.InitializeCallback(PostAddressChanged, NULL); +#endif +#if LWIP_NETIF_LINK_CALLBACK == 1 + PostAvailabilityOnContinuation.InitializeCallback(PostAvailabilityOn, NULL); + PostAvailabilityOffContinuation.InitializeCallback(PostAvailabilityOff, NULL); +#endif + + // create m_interfaceNumber array + int interfaceCount = g_TargetConfiguration.NetworkInterfaceConfigs->Count; + g_LWIP_SOCKETS_Driver.m_interfaces = (LWIP_DRIVER_INTERFACE_DATA*)platform_malloc(interfaceCount * sizeof(LWIP_DRIVER_INTERFACE_DATA)); + + /* Initialize the target board lwIP stack */ + nanoHAL_Network_Initialize(); + + for (int i = 0; i < g_TargetConfiguration.NetworkInterfaceConfigs->Count; i++) + { + // load network interface configuration from storage + if(!ConfigurationManager_GetConfigurationBlock((void*)&networkConfiguration, DeviceConfigurationOption_Network, i)) + { + // failed to load configuration + // FIXME output error? + // move to the next, if any + continue; + } + _ASSERTE(networkConfiguration.StartupAddressMode > 0); + + /* Bind and Open the Ethernet driver */ + Network_Interface_Bind(i); + interfaceNumber = Network_Interface_Open(i); + + if (interfaceNumber == SOCK_SOCKET_ERROR) + { + DEBUG_HANDLE_SOCKET_ERROR("Network init", FALSE); +//FIXME debug_printf("SocketError: %d\n", errorCode); + continue; + } + + g_LWIP_SOCKETS_Driver.m_interfaces[i].m_interfaceNumber = interfaceNumber; + + UpdateAdapterConfiguration(i, (UpdateOperation_Dhcp | UpdateOperation_Dns), &networkConfiguration); + + networkInterface = netif_find_interface(interfaceNumber); + + if (networkInterface) + { +#if LWIP_NETIF_LINK_CALLBACK == 1 + netif_set_link_callback(networkInterface, Link_callback); + + if (netif_is_link_up(networkInterface)) + { + Link_callback(networkInterface); + } +#endif +#if LWIP_NETIF_STATUS_CALLBACK == 1 + netif_set_status_callback(networkInterface, Status_callback); + + if (netif_is_up(networkInterface)) + { + Status_callback(networkInterface); + } +#endif + + // default debugger interface + if (0 == i) + { +#if LWIP_IPV6 + //uint8_t* addr = (uint8_t*)&networkInterface->ip_addr.u_addr.ip4.addr; +#else + //uint8_t* addr = (uint8_t*)&networkInterface->ip_addr.addr; +#endif +// lcd_printf("\f\n\n\n\n\n\n\nip address: %d.%d.%d.%d\r\n", addr[0], addr[1], addr[2], addr[3]); +// FIXME debug_printf("ip address from interface info: %d.%d.%d.%d\r\n", addr[0], addr[1], addr[2], addr[3]); + } + } + } + + return TRUE; +} + +bool LWIP_SOCKETS_Driver::Uninitialize() +{ + NATIVE_PROFILE_PAL_NETWORK(); + +#if LWIP_NETIF_STATUS_CALLBACK == 1 + PostAddressChangedContinuation.Abort(); +#endif +#if LWIP_NETIF_LINK_CALLBACK == 1 + PostAvailabilityOnContinuation.Abort(); + PostAvailabilityOffContinuation.Abort(); +#endif + + for(int i=0; iCount; i++) + { + Network_Interface_Close(i); + } + +//FIXME tcpip_shutdown(); +// tcpip_shutdown is MS method added to lwip tcpip.c + + return TRUE; +} + +extern void debug_printf( const char* format, ... ); + +SOCK_SOCKET LWIP_SOCKETS_Driver::Socket(int family, int type, int protocol) +{ + NATIVE_PROFILE_PAL_NETWORK(); + + switch(protocol) + { + case SOCK_IPPROTO_TCP: + protocol = IPPROTO_TCP; + break; + case SOCK_IPPROTO_UDP: + protocol = IPPROTO_UDP; + break; + case SOCK_IPPROTO_ICMP: + protocol = IP_PROTO_ICMP; + break; + + case SOCK_IPPROTO_IGMP: + protocol = IP_PROTO_IGMP; + break; + } + + return lwip_socket(family, type, protocol); +} + +int LWIP_SOCKETS_Driver::Bind(SOCK_SOCKET socket, const SOCK_sockaddr* address, int addressLen) +{ + NATIVE_PROFILE_PAL_NETWORK(); + + sockaddr_in addr; + + SOCK_SOCKADDR_TO_SOCKADDR(address, addr, &addressLen); + + return lwip_bind(socket, (sockaddr*)&addr, addressLen); +} + +int LWIP_SOCKETS_Driver::Connect(SOCK_SOCKET socket, const SOCK_sockaddr* address, int addressLen) +{ + NATIVE_PROFILE_PAL_NETWORK(); + + sockaddr_in addr; + + SOCK_SOCKADDR_TO_SOCKADDR(address, addr, &addressLen); + + return lwip_connect(socket, (sockaddr*)&addr, addressLen); +} + +int LWIP_SOCKETS_Driver::Send(SOCK_SOCKET socket, const char* buf, int len, int flags) +{ + NATIVE_PROFILE_PAL_NETWORK(); + + return lwip_send(socket, (const void*)buf, len, flags); +} + + +int LWIP_SOCKETS_Driver::Recv(SOCK_SOCKET socket, char* buf, int len, int flags) +{ + NATIVE_PROFILE_PAL_NETWORK(); + int nativeFlag; + + switch (flags) + { + case SOCKET_READ_PEEK_OPTION: + nativeFlag = MSG_PEEK; + break; + default: + nativeFlag = flags; + break; + } + + return lwip_recv(socket,(void*)buf, len, nativeFlag); +} + +int LWIP_SOCKETS_Driver::Close(SOCK_SOCKET socket) +{ + NATIVE_PROFILE_PAL_NETWORK(); + +#ifdef PLATFORM_ESP32 + // We have to call lwip_close_r() method otherwise the socket doesn't get freed up and we run out of sockets. + // We could also call the posix closesocket() which should work for all platforms and change all other methods to + // call the posix version to be consistent.(TODO) + return lwip_close_r(socket); +#else + return lwip_close(socket); +#endif +} + +int LWIP_SOCKETS_Driver::Listen(SOCK_SOCKET socket, int backlog) +{ + NATIVE_PROFILE_PAL_NETWORK(); + + return lwip_listen(socket, backlog); +} + +SOCK_SOCKET LWIP_SOCKETS_Driver::Accept(SOCK_SOCKET socket, SOCK_sockaddr* address, int* addressLen) +{ + NATIVE_PROFILE_PAL_NETWORK(); + SOCK_SOCKET ret; + + sockaddr_in addr; + + if (address) + { + SOCK_SOCKADDR_TO_SOCKADDR(address, addr, addressLen); + } + + ret = lwip_accept(socket, address?(sockaddr*)&addr:NULL, (u32_t*)addressLen); + + if(address) + { + SOCKADDR_TO_SOCK_SOCKADDR(address, addr, addressLen); + } + + return ret; +} + +int LWIP_SOCKETS_Driver::Shutdown( SOCK_SOCKET socket, int how ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + + return lwip_shutdown (socket, how); +} + +int LWIP_SOCKETS_Driver::GetAddrInfo(const char* nodename, char* servname, const SOCK_addrinfo* hints, SOCK_addrinfo** res) +{ + #if LWIP_DNS + NATIVE_PROFILE_PAL_NETWORK(); + + SOCK_addrinfo *ai; + void *dummyPtr; + SOCK_sockaddr_in *sa = NULL; + int total_size = sizeof(SOCK_addrinfo) + sizeof(SOCK_sockaddr_in); + struct addrinfo *lwipAddrinfo = NULL; + + if(res == NULL) return SOCK_SOCKET_ERROR; + + *res = NULL; + + // if the nodename == "" then return the IP address of this device + if(nodename[0] == 0 && servname == NULL) + { + struct netif *networkInterface = netif_find_interface(g_LWIP_SOCKETS_Driver.m_interfaces[0].m_interfaceNumber); + + if(networkInterface == NULL) return -1; + + ai = (SOCK_addrinfo*)mem_malloc(total_size); + if (ai == NULL) + { + return -1; + } + memset(ai, 0, total_size); + sa = (SOCK_sockaddr_in*)((u8_t*)ai + sizeof(SOCK_addrinfo)); + + /* set up sockaddr */ + #if LWIP_IPV6 + sa->sin_addr.S_un.S_addr = networkInterface->ip_addr.u_addr.ip4.addr; + #else + sa->sin_addr.S_un.S_addr = networkInterface->ip_addr.addr; + #endif + + sa->sin_family = AF_INET; + sa->sin_port = 0; + + /* set up addrinfo */ + ai->ai_family = AF_INET; + if (hints != NULL) + { + /* copy socktype & protocol from hints if specified */ + ai->ai_socktype = hints->ai_socktype; + ai->ai_protocol = hints->ai_protocol; + } + + // need this to keep the compiler happy about the cast to SOCK_sockaddr + // which is intended and perfectly safe + dummyPtr = sa; + + ai->ai_addrlen = sizeof(SOCK_sockaddr_in); + ai->ai_addr = (SOCK_sockaddr*)dummyPtr; + + *res = ai; + + return 0; + } + + int err = lwip_getaddrinfo(nodename, servname, (addrinfo*)hints, &lwipAddrinfo); + + if(err == 0) + { + /// + /// Marshal addrinfo data + /// + struct sockaddr_in* lwip_sockaddr_in; + + ai = (SOCK_addrinfo*)mem_malloc(total_size); + if (ai == NULL) + { + lwip_freeaddrinfo(lwipAddrinfo); + return -1; + } + memset(ai, 0, total_size); + + lwip_sockaddr_in = ((struct sockaddr_in*)lwipAddrinfo->ai_addr); + + sa = (SOCK_sockaddr_in*)((u8_t*)ai + sizeof(SOCK_addrinfo)); + /* set up sockaddr */ + sa->sin_addr.S_un.S_addr = lwip_sockaddr_in->sin_addr.s_addr; + sa->sin_family = lwip_sockaddr_in->sin_family; + sa->sin_port = lwip_sockaddr_in->sin_port; + + /* set up addrinfo */ + ai->ai_family = lwipAddrinfo->ai_family; + if (hints != NULL) + { + /* copy socktype & protocol from hints if specified */ + ai->ai_socktype = hints->ai_socktype; + ai->ai_protocol = hints->ai_protocol; + } + + // need this to keep the compiler happy about the cast to SOCK_sockaddr + // which is intended and perfectly safe + dummyPtr = sa; + + ai->ai_addrlen = sizeof(SOCK_sockaddr_in); + ai->ai_addr = (SOCK_sockaddr*)dummyPtr; + + *res = ai; + + // free marshalled addrinfo + lwip_freeaddrinfo(lwipAddrinfo); + + return 0; + } + else + { + // map DNS error with socket errors + switch(err) + { + case HOST_NOT_FOUND: + errorCode = SOCK_HOST_NOT_FOUND; + break; + + default: + errorCode = SOCK_NO_RECOVERY; + } + + } + + return SOCK_SOCKET_ERROR; + + #else + return SOCK_SOCKET_ERROR; + #endif +} + +void LWIP_SOCKETS_Driver::FreeAddrInfo( SOCK_addrinfo* ai ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + + SOCK_addrinfo *next; + + while (ai != NULL) { + next = ai->ai_next; + mem_free(ai); + ai = next; + } +} + +int LWIP_SOCKETS_Driver::Ioctl( SOCK_SOCKET socket, int cmd, int* data ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + + return lwip_ioctl(socket,cmd,data); +} + +int LWIP_SOCKETS_Driver::GetLastError() +{ + NATIVE_PROFILE_PAL_NETWORK(); + + return GetNativeError(errorCode); +} + +int LWIP_SOCKETS_Driver::GetSockLastError(SOCK_SOCKET socket) +{ + NATIVE_PROFILE_PAL_NETWORK(); + + // get last error number from socket + errorCode = lwip_socket_get_err(socket); + + return GetNativeError(errorCode); +} + +static int MARSHAL_SOCK_FDSET_TO_FDSET(SOCK_fd_set *sf, fd_set *f) +{ + if(f != NULL && sf != NULL) + { + FD_ZERO(f); + + for(unsigned int i=0; i < sf->fd_count; i++) + { + FD_SET(sf->fd_array[i], f); + } + return sf->fd_count; + } + + return 0; +} + +static void MARSHAL_FDSET_TO_SOCK_FDSET(SOCK_fd_set *sf, fd_set *f) +{ + if(sf != NULL && f != NULL) + { + int cnt = sf->fd_count; + sf->fd_count = 0; + for(int i=0; ifd_array[i],f)) + { + sf->fd_array[sf->fd_count] = sf->fd_array[i]; + sf->fd_count++; + } + } + } +} + + +int LWIP_SOCKETS_Driver::Select( int nfds, SOCK_fd_set* readfds, SOCK_fd_set* writefds, SOCK_fd_set* exceptfds, const SOCK_timeval* timeout ) +{ + (void)nfds; + + NATIVE_PROFILE_PAL_NETWORK(); + int ret = 0; + + fd_set read; + fd_set write; + fd_set excpt; + + fd_set* pR = (readfds != NULL) ? &read : NULL; + fd_set* pW = (writefds != NULL) ? &write : NULL; + fd_set* pE = (exceptfds != NULL) ? &excpt : NULL; + + // If the network goes down then we should alert any pending socket actions + if(exceptfds != NULL && exceptfds->fd_count > 0) + { + struct netif *networkInterface = netif_find_interface(g_LWIP_SOCKETS_Driver.m_interfaces[0].m_interfaceNumber); + + if(networkInterface != NULL) + { + if(!netif_is_up(networkInterface)) + { + if(readfds != NULL) readfds->fd_count = 0; + if(writefds != NULL) writefds->fd_count = 0; + + errorCode = ENETDOWN; + + return exceptfds->fd_count; + } + } + } + + MARSHAL_SOCK_FDSET_TO_FDSET(readfds , pR); + MARSHAL_SOCK_FDSET_TO_FDSET(writefds , pW); + MARSHAL_SOCK_FDSET_TO_FDSET(exceptfds, pE); + + int max_sd = MEMP_NUM_NETCONN; + #if defined(PLATFORM_ESP32) + max_sd = LWIP_SOCKET_OFFSET + MEMP_NUM_NETCONN; + #endif + + // developer note: + // our declaration of SOCK_timeval is dependent of "long" type which is platform dependent + // so it's not safe to cast it to "timeval" + timeval timeoutCopy; + timeoutCopy.tv_sec = timeout->tv_sec; + timeoutCopy.tv_usec = timeout->tv_usec; + + ret = select(max_sd, pR, pW, pE, &timeoutCopy); + + MARSHAL_FDSET_TO_SOCK_FDSET(readfds , pR); + MARSHAL_FDSET_TO_SOCK_FDSET(writefds , pW); + MARSHAL_FDSET_TO_SOCK_FDSET(exceptfds, pE); + + return ret; +} + +int LWIP_SOCKETS_Driver::SetSockOpt( SOCK_SOCKET socket, int level, int optname, const char* optval, int optlen ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + int nativeLevel; + int nativeOptionName; + int nativeIntValue; + char *pNativeOptionValue = (char*)optval; + struct linger lopt = {0,0}; + + switch(level) + { + case SOCK_IPPROTO_IP: + nativeLevel = IPPROTO_IP; + nativeOptionName = GetNativeIPOption(optname); + break; + case SOCK_IPPROTO_TCP: + nativeLevel = IPPROTO_TCP; + nativeOptionName = GetNativeTcpOption(optname); + break; + case SOCK_IPPROTO_UDP: + case SOCK_IPPROTO_ICMP: + case SOCK_IPPROTO_IGMP: + case SOCK_IPPROTO_IPV4: + case SOCK_SOL_SOCKET: + nativeLevel = SOL_SOCKET; + nativeOptionName = GetNativeSockOption(optname); + + switch(optname) + { + // If linger value negative then linger off + // otherwise enabled and linger value is number of seconds + case SOCK_SOCKO_LINGER: + { + int lingerValue = *(int*)optval; + if ( lingerValue >= 0 ) + { + lopt.l_onoff = 1; + lopt.l_linger = abs(lingerValue); + } + pNativeOptionValue = (char*)&lopt; + optlen = sizeof(lopt); + } + break; + + case SOCK_SOCKO_DONTLINGER: + case SOCK_SOCKO_EXCLUSIVEADDRESSUSE: + nativeIntValue = !*(int*)optval; + pNativeOptionValue = (char*)&nativeIntValue; + break; + default: + break; + } + break; + default: + nativeLevel = 0; + nativeOptionName = 0; + break; + } + + return lwip_setsockopt(socket, nativeLevel, nativeOptionName, pNativeOptionValue, optlen); +} + +int LWIP_SOCKETS_Driver::GetSockOpt( SOCK_SOCKET socket, int level, int optname, char* optval, int* optlen ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + int nativeLevel; + int nativeOptionName; + char* pNativeOptval = optval; + int ret; + + switch(level) + { + case SOCK_IPPROTO_IP: + nativeLevel = IPPROTO_IP; + nativeOptionName = GetNativeIPOption(optname); + break; + case SOCK_IPPROTO_TCP: + nativeLevel = IPPROTO_TCP; + nativeOptionName = GetNativeTcpOption(optname); + break; + case SOCK_IPPROTO_UDP: + case SOCK_IPPROTO_ICMP: + case SOCK_IPPROTO_IGMP: + case SOCK_IPPROTO_IPV4: + case SOCK_SOL_SOCKET: + nativeLevel = SOL_SOCKET; + nativeOptionName = GetNativeSockOption(optname); + break; + default: + nativeLevel = level; + nativeOptionName = optname; + break; + } + + ret = lwip_getsockopt(socket, nativeLevel, nativeOptionName, pNativeOptval, (u32_t*)optlen); + + if(ret == 0) + { + switch(level) + { + case SOCK_SOL_SOCKET: + switch(optname) + { + case SOCK_SOCKO_EXCLUSIVEADDRESSUSE: + case SOCK_SOCKO_DONTLINGER: + *optval = !(*(int*)optval != 0); + break; + + case SOCK_SOCKO_ACCEPTCONNECTION: + case SOCK_SOCKO_BROADCAST: + case SOCK_SOCKO_KEEPALIVE: + *optval = (*(int*)optval != 0); + break; + } + break; + } + } + + return ret; +} + +int LWIP_SOCKETS_Driver::GetPeerName( SOCK_SOCKET socket, SOCK_sockaddr* name, int* namelen ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + int ret; + + sockaddr_in addr; + + SOCK_SOCKADDR_TO_SOCKADDR(name, addr, namelen); + + ret = lwip_getpeername(socket, (sockaddr*)&addr, (u32_t*)namelen); + + SOCKADDR_TO_SOCK_SOCKADDR(name, addr, namelen); + + return ret; +} + +int LWIP_SOCKETS_Driver::GetSockName( SOCK_SOCKET socket, SOCK_sockaddr* name, int* namelen ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + int ret; + + sockaddr_in addr; + + SOCK_SOCKADDR_TO_SOCKADDR(name, addr, namelen); + + ret = lwip_getsockname(socket, (sockaddr*)&addr, (u32_t*)namelen); + + SOCKADDR_TO_SOCK_SOCKADDR(name, addr, namelen); + + return ret; +} + +int LWIP_SOCKETS_Driver::RecvFrom( SOCK_SOCKET socket, char* buf, int len, int flags, SOCK_sockaddr* from, int* fromlen ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + sockaddr_in addr; + sockaddr *pFrom = NULL; + int ret; + + if(from) + { + SOCK_SOCKADDR_TO_SOCKADDR(from, addr, fromlen); + pFrom = (sockaddr*)&addr; + } + + ret = lwip_recvfrom(socket, buf, len, flags, pFrom, (u32_t*)fromlen); + + if(from && ret != SOCK_SOCKET_ERROR) + { + SOCKADDR_TO_SOCK_SOCKADDR(from, addr, fromlen); + } + + return ret; +} + +int LWIP_SOCKETS_Driver::SendTo( SOCK_SOCKET socket, const char* buf, int len, int flags, const SOCK_sockaddr* to, int tolen ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + + sockaddr_in addr; + + SOCK_SOCKADDR_TO_SOCKADDR(to, addr, &tolen); + + return lwip_sendto(socket, buf, len, flags, (sockaddr*)&addr, (u32_t)tolen); +} + +HRESULT LWIP_SOCKETS_Driver::LoadAdapterConfiguration(HAL_Configuration_NetworkInterface* config, uint32_t interfaceIndex) +{ + NATIVE_PROFILE_PAL_NETWORK(); + + if(config->StartupAddressMode == AddressMode_DHCP) + { + struct netif *networkInterface; + + if ((networkInterface = netif_find_interface(g_LWIP_SOCKETS_Driver.m_interfaces[interfaceIndex].m_interfaceNumber))) + { +#if LWIP_IPV6 + config->IPv4Address = networkInterface->ip_addr.u_addr.ip4.addr; + config->IPv4NetMask = networkInterface->netmask.u_addr.ip4.addr; + config->IPv4GatewayAddress = networkInterface->gw.u_addr.ip4.addr; + + // FIXME IPV6 + // config->IPv6Address = networkInterface->ip_addr.u_addr.ip6.addr; + // config->IPv6NetMask = networkInterface->netmask.u_addr.ip6.addr; + // config->IPv6GatewayAddress = networkInterface->gw.u_addr.ip6.addr; +#else + config->IPv4Address = networkInterface->ip_addr.addr; + config->IPv4NetMask = networkInterface->netmask.addr; + config->IPv4GatewayAddress = networkInterface->gw.addr; +#endif + +#if LWIP_DNS +#if LWIP_IPV6 +#if LWIP_VERSION_MAJOR == 2 + +#if defined(PLATFORM_ESP32) + // ESP32 return ip_addr_t instead of ip_addr_t * on statndard lwip + config->IPv4DNSAddress1 = dns_getserver(0).u_addr.ip4.addr; + config->IPv4DNSAddress2 = dns_getserver(1).u_addr.ip4.addr; +#else + config->IPv4DNSAddress1 = dns_getserver(0)->u_addr.ip4.addr; + config->IPv4DNSAddress2 = dns_getserver(1)->u_addr.ip4.addr; +#endif + // FIXME IPV6 + // config->IPv6DNSAddress1 = dns_getserver(0)->u_addr.ip6.addr; + // config->IPv6DNSAddress2 = dns_getserver(1)->u_addr.ip6.addr; +#else + config->IPv4DNSAddress1 = dns_getserver(0).u_addr.ip4.addr; + config->IPv4DNSAddress2 = dns_getserver(1).u_addr.ip4.addr; + + // FIXME IPV6 + // config->IPv6DNSAddress1 = dns_getserver(0).u_addr.ip6.addr; + // config->IPv6DNSAddress2 = dns_getserver(1).u_addr.ip6.addr; +#endif +#else +#if LWIP_VERSION_MAJOR == 2 + config->IPv4DNSAddress1 = dns_getserver(0)->addr; + config->IPv4DNSAddress2 = dns_getserver(1)->addr; +#else + config->IPv4DNSAddress1 = dns_getserver(0).addr; + config->IPv4DNSAddress2 = dns_getserver(1).addr; +#endif + +#endif +#endif + } + else + { + config->IPv4Address = 0; + config->IPv4NetMask = 0; + config->IPv4GatewayAddress = 0; + } + } + + return S_OK; +} + +struct dhcp_client_id +{ + uint8_t code; + uint8_t length; + uint8_t type; + uint8_t clientId[6]; +}; + +HRESULT LWIP_SOCKETS_Driver::UpdateAdapterConfiguration( uint32_t interfaceIndex, uint32_t updateFlags, HAL_Configuration_NetworkInterface* config ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + + bool enableDHCP = (config->StartupAddressMode == AddressMode_DHCP); + + struct netif *networkInterface = netif_find_interface(g_LWIP_SOCKETS_Driver.m_interfaces[interfaceIndex].m_interfaceNumber); + if (NULL == networkInterface) + { + return CLR_E_FAIL; + } + +#if LWIP_DNS + // when using DHCP do not use the static settings + if(0 != (updateFlags & UpdateOperation_Dns)) + { + // FIXME IPV6 + if(config->AutomaticDNS == 0) + { + // user defined DNS addresses + if(config->IPv4DNSAddress1 != 0) + { + // need to convert this first + ip_addr_t dnsServer; + ip_addr_set_ip4_u32(&dnsServer, config->IPv4DNSAddress1); + + dns_setserver(0, &dnsServer); + } + if(config->IPv4DNSAddress2 != 0) + { + // need to convert this first + ip_addr_t dnsServer; + ip_addr_set_ip4_u32(&dnsServer, config->IPv4DNSAddress2); + + dns_setserver(1, &dnsServer); + } + } + } +#endif + +#if LWIP_DHCP + if(0 != (updateFlags & UpdateOperation_Dhcp)) + { + if(enableDHCP) + { + // need to start DHCP + if(ERR_OK != dhcp_start(networkInterface)) + { + return CLR_E_FAIL; + } + } + else + { + // stop DHCP + dhcp_stop(networkInterface); + + // need to convert these first + ip_addr_t ipAddress, mask, gateway; + ip_addr_set_ip4_u32(&ipAddress, config->IPv4Address); + ip_addr_set_ip4_u32(&mask, config->IPv4NetMask); + ip_addr_set_ip4_u32(&gateway, config->IPv4GatewayAddress); + + // set interface with our static IP configs + netif_set_addr( + networkInterface, + (const ip4_addr_t*)&ipAddress, + (const ip4_addr_t*)&mask, + (const ip4_addr_t*)&gateway); + + // we should be polite and let the DHCP server that we are now using a static IP + dhcp_inform(networkInterface); + } + } + + if(enableDHCP) + { + // developer note: on legacy source there was a hack of trying to renew before release and + // also setting the release flag in managed call when the intent was to renew only + // nowadays lwIP seems to be doing what is told, so no need for these hacks anymore + // also it's NOT possible to renew & release on the same pass, so adding an extra else-if for that + // just in case it's request from the managed code + + if(0 != (updateFlags & UpdateOperation_DhcpRelease)) + { + dhcp_release(networkInterface); + } + else if(0 != (updateFlags & UpdateOperation_DhcpRenew)) + { + dhcp_renew(networkInterface); + } + else if(0 != (updateFlags & (UpdateOperation_DhcpRelease | UpdateOperation_DhcpRenew)) ) + { + return CLR_E_INVALID_PARAMETER; + } + } +#endif + + if(0 != (updateFlags & UpdateOperation_Mac)) + { + memcpy(networkInterface->hwaddr, config->MacAddress, NETIF_MAX_HWADDR_LEN); + networkInterface->hwaddr_len = NETIF_MAX_HWADDR_LEN; + + // mac address requires stack re-init + Network_Interface_Close(interfaceIndex); + g_LWIP_SOCKETS_Driver.m_interfaces[interfaceIndex].m_interfaceNumber = Network_Interface_Open(interfaceIndex); + } + + return S_OK; +} + +int LWIP_SOCKETS_Driver::GetNativeTcpOption (int optname) +{ + NATIVE_PROFILE_PAL_NETWORK(); + int nativeOptionName = 0; + + switch(optname) + { + case SOCK_TCP_NODELAY: + nativeOptionName = TCP_NODELAY; + break; + + case SOCK_SOCKO_KEEPALIVE: + nativeOptionName = TCP_KEEPALIVE; + break; + + // allow the C# user to specify LWIP options that our managed enum + // doesn't support + default: + nativeOptionName = optname; + break; + } + return nativeOptionName; +} + +int LWIP_SOCKETS_Driver::GetNativeSockOption (int optname) +{ + NATIVE_PROFILE_PAL_NETWORK(); + int nativeOptionName = 0; + + switch(optname) + { + case SOCK_SOCKO_DONTLINGER: + case SOCK_SOCKO_LINGER: + nativeOptionName = SO_LINGER; + break; + case SOCK_SOCKO_SENDTIMEOUT: + nativeOptionName = SO_SNDTIMEO; + break; + case SOCK_SOCKO_RECEIVETIMEOUT: + nativeOptionName = SO_RCVTIMEO; + break; + case SOCK_SOCKO_EXCLUSIVEADDRESSUSE: + case SOCK_SOCKO_REUSEADDRESS: + nativeOptionName = SO_REUSEADDR; + break; + case SOCK_SOCKO_KEEPALIVE: + nativeOptionName = SO_KEEPALIVE; + break; + case SOCK_SOCKO_ERROR: + nativeOptionName = SO_ERROR; + break; + case SOCK_SOCKO_BROADCAST: + nativeOptionName = SO_BROADCAST; + break; + case SOCK_SOCKO_RECEIVEBUFFER: + nativeOptionName = SO_RCVBUF; + break; + case SOCK_SOCKO_SENDBUFFER: + nativeOptionName = SO_SNDBUF; + break; + case SOCK_SOCKO_ACCEPTCONNECTION: + nativeOptionName = SO_ACCEPTCONN; + break; + case SOCK_SOCKO_USELOOPBACK: + nativeOptionName = SO_USELOOPBACK; + break; + case SOCK_SOCKO_DONTROUTE: + nativeOptionName = SO_DONTROUTE; + break; + case SOCK_SOCKO_OUTOFBANDINLINE: + nativeOptionName = SO_OOBINLINE; + break; + + case SOCK_SOCKO_DEBUG: + nativeOptionName = SO_DEBUG; + break; + + case SOCK_SOCKO_SENDLOWWATER: + nativeOptionName = SO_SNDLOWAT; + break; + + case SOCK_SOCKO_RECEIVELOWWATER: + nativeOptionName = SO_RCVLOWAT; + break; + +// case SOCK_SOCKO_MAXCONNECTIONS: //don't support + case SOCK_SOCKO_UPDATE_ACCEPT_CTX: + case SOCK_SOCKO_UPDATE_CONNECT_CTX: + nativeOptionName = 0; + break; + + // allow the C# user to specify LWIP options that our managed enum + // doesn't support + default: + nativeOptionName = optname; + break; + + } + + return nativeOptionName; +} + +int LWIP_SOCKETS_Driver::GetNativeIPOption (int optname) +{ + NATIVE_PROFILE_PAL_NETWORK(); + int nativeOptionName = 0; + + switch(optname) + { + case SOCK_IPO_TTL: + nativeOptionName = IP_TTL; + break; + case SOCK_IPO_TOS: + nativeOptionName = IP_TOS; + break; +#if LWIP_IGMP + case SOCK_IPO_MULTICAST_IF: + nativeOptionName = IP_MULTICAST_IF; + break; + case SOCK_IPO_MULTICAST_TTL: + nativeOptionName = IP_MULTICAST_TTL; + break; + case SOCK_IPO_MULTICAST_LOOP: + nativeOptionName = IP_MULTICAST_LOOP; + break; + case SOCK_IPO_ADD_MEMBERSHIP: + nativeOptionName = IP_ADD_MEMBERSHIP; + break; + case SOCK_IPO_DROP_MEMBERSHIP: + nativeOptionName = IP_DROP_MEMBERSHIP; + break; +#else + case SOCK_IPO_MULTICAST_IF: + case SOCK_IPO_MULTICAST_TTL: + case SOCK_IPO_MULTICAST_LOOP: + case SOCK_IPO_ADD_MEMBERSHIP: + case SOCK_IPO_DROP_MEMBERSHIP: +#endif + case SOCK_IPO_ADD_SOURCE_MEMBERSHIP: + case SOCK_IPO_DROP_SOURCE_MEMBERSHIP: + case SOCK_IPO_OPTIONS: + case SOCK_IPO_HDRINCL: + case SOCK_IPO_IP_DONTFRAGMENT: + case SOCK_IPO_BLOCK_SOURCE: + case SOCK_IPO_UBLOCK_SOURCE: + case SOCK_IPO_PACKET_INFO: + nativeOptionName = 0; + break; + + // allow the C# user to specify LWIP options that our managed enum + // doesn't support + default: + nativeOptionName = optname; + break; + } + + return nativeOptionName; +} + +int LWIP_SOCKETS_Driver::GetNativeError ( int error ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + int ret; + + switch(error) + { + case EINTR: + ret = SOCK_EINTR; + break; + + case EACCES: + ret = SOCK_EACCES; + break; + + case EFAULT: + ret = SOCK_EFAULT; + break; + + case EINVAL: + ret = SOCK_EINVAL; + break; + + case EMFILE: + ret = SOCK_EMFILE; + break; + + case EAGAIN: + case EBUSY: + /* case EWOULDBLOCK: same as EINPROGRESS */ + case EINPROGRESS: + ret = SOCK_EWOULDBLOCK; + break; + + case EALREADY: + ret = SOCK_EALREADY; + break; + + case ENOTSOCK: + ret = SOCK_ENOTSOCK; + break; + + case EDESTADDRREQ: + ret = SOCK_EDESTADDRREQ; + break; + + case EMSGSIZE: + ret = SOCK_EMSGSIZE; + break; + + case EPROTOTYPE: + ret = SOCK_EPROTOTYPE; + break; + + case ENOPROTOOPT: + ret = SOCK_ENOPROTOOPT; + break; + + case EPROTONOSUPPORT: + ret = SOCK_EPROTONOSUPPORT; + break; +// TODO nanoframework check why missing + // case ESOCKTNOSUPPORT: + // ret = SOCK_ESOCKTNOSUPPORT; + // break; + + case EPFNOSUPPORT: + ret = SOCK_EPFNOSUPPORT; + break; + + case EAFNOSUPPORT: + ret = SOCK_EAFNOSUPPORT; + break; + + case EADDRINUSE: + ret = SOCK_EADDRINUSE; + break; + + case EADDRNOTAVAIL: + ret = SOCK_EADDRNOTAVAIL; + break; + + case ENETDOWN: + ret = SOCK_ENETDOWN; + break; + + case ENETUNREACH: + ret = SOCK_ENETUNREACH; + break; + + case ENETRESET: + ret = SOCK_ENETRESET; + break; + + case ECONNABORTED: + ret = SOCK_ECONNABORTED; + break; + + case ECONNRESET: + ret = SOCK_ECONNRESET; + break; + + case ENOBUFS: + case ENOMEM: + ret = SOCK_ENOBUFS; + break; + + case EISCONN: + ret = SOCK_EISCONN; + break; + + case ENOTCONN: + ret = SOCK_EISCONN; + break; + +#if !defined(__GNUC__) // same as ENOTSOCK for GCC + case ESHUTDOWN: + ret = SOCK_ESHUTDOWN; + break; +#endif + + case ETIMEDOUT: + ret = SOCK_ETIMEDOUT; + break; + + case ECONNREFUSED: + ret = SOCK_ECONNREFUSED; + break; + + case EHOSTDOWN: + ret = SOCK_EHOSTDOWN; + break; + + case EHOSTUNREACH: + ret = SOCK_EHOSTUNREACH; + break; + + case ENODATA: + ret = SOCK_NO_DATA; + break; + + default: + ret = error; + break; + } + + return (ret); +} + +/** + * Find a network interface by searching for its number + * Similar to LWIP's netif_find(char *name) + */ +struct netif *netif_find_interface(int num) +{ + struct netif *networkInterface; + + for (networkInterface = netif_list; networkInterface != NULL; networkInterface = networkInterface->next) + { + if (num == networkInterface->num) + { + return networkInterface; + } + } + return NULL; +} diff --git a/source/native/nf-interpreter/src/PAL/Lwip/lwIP_Sockets.h b/source/native/nf-interpreter/src/PAL/Lwip/lwIP_Sockets.h new file mode 100644 index 00000000..18bc841c --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/Lwip/lwIP_Sockets.h @@ -0,0 +1,126 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _LWIP_SOCKETS_H_ +#define _LWIP_SOCKETS_H_ + +#include +#include + +#define NATIVE_PROFILE_PAL_NETWORK() + +////////////////////////////////////////////////////////////////////////////// +// SOCKET driver +// + +struct LWIP_DRIVER_INTERFACE_DATA +{ + int m_interfaceNumber; +}; + +#define SOCK_SOCKADDR_TO_SOCKADDR(ssa, sa, addrLen) \ + sa.sin_len = (u8_t)sizeof(sa); \ + sa.sin_family = (u8_t)((SOCK_sockaddr_in*)ssa)->sin_family; \ + sa.sin_port = ((SOCK_sockaddr_in*)ssa)->sin_port; \ + sa.sin_addr.s_addr = ((SOCK_sockaddr_in*)ssa)->sin_addr.S_un.S_addr; \ + memcpy(sa.sin_zero, ((SOCK_sockaddr_in*)ssa)->sin_zero, sizeof(sa.sin_zero)); \ + *addrLen = sizeof(sa) + +#define SOCKADDR_TO_SOCK_SOCKADDR(ssa, sa, addrLen) \ + ((SOCK_sockaddr_in*)ssa)->sin_port = sa.sin_port; \ + ((SOCK_sockaddr_in*)ssa)->sin_addr.S_un.S_addr = sa.sin_addr.s_addr; \ + ((SOCK_sockaddr_in*)ssa)->sin_family = sa.sin_family; \ + memcpy(((SOCK_sockaddr_in*)ssa)->sin_zero, sa.sin_zero, sizeof(((SOCK_sockaddr_in*)ssa)->sin_zero)); \ + *addrLen = sizeof(SOCK_sockaddr_in) + + +struct LWIP_SOCKETS_Driver +{ + static bool Initialize(); + + static bool Uninitialize(); + + static SOCK_SOCKET Socket( int family, int type, int protocol ); + + static int Bind( SOCK_SOCKET socket, const SOCK_sockaddr* address, int addressLen ); + + static int Connect(SOCK_SOCKET socket, const SOCK_sockaddr* address, int addressLen); + + static int Send(SOCK_SOCKET socket, const char* buf, int len, int flags); + + static int Recv(SOCK_SOCKET socket, char* buf, int len, int flags); + + static int Close(SOCK_SOCKET socket); + + static int Listen(SOCK_SOCKET socket, int backlog ); + + static SOCK_SOCKET Accept(SOCK_SOCKET socket, SOCK_sockaddr* address, int* addressLen ); + + + static int Shutdown(SOCK_SOCKET socket, int how ); + + static int GetAddrInfo(const char* nodename, + char* servname, + const SOCK_addrinfo* hints, + SOCK_addrinfo** res ); + + static void FreeAddrInfo(SOCK_addrinfo* ai ); + + static int Ioctl(SOCK_SOCKET socket, int cmd, int* data ); + + static int GetLastError(); + + static int GetSockLastError(SOCK_SOCKET socket); + + static int GetNativeTcpOption (int optname); + + static int GetNativeSockOption (int optname); + + static int GetNativeError( int error ); + + static int GetNativeIPOption (int optname); + + static int Select(int nfds, SOCK_fd_set* readfds, SOCK_fd_set* writefds, SOCK_fd_set* exceptfds, const SOCK_timeval* timeout ); + + static int SetSockOpt(SOCK_SOCKET socket, int level, int optname, const char* optval, int optlen ); + + static int GetSockOpt(SOCK_SOCKET socket, int level, int optname, char* optval, int* optlen ); + + static int GetPeerName(SOCK_SOCKET socket, SOCK_sockaddr* name, int* namelen ); + + static int GetSockName(SOCK_SOCKET socket, SOCK_sockaddr* name, int* namelen ); + + static int RecvFrom(SOCK_SOCKET s, char* buf, int len, int flags, SOCK_sockaddr* from, int* fromlen ); + + static int SendTo(SOCK_SOCKET s, const char* buf, int len, int flags, const SOCK_sockaddr* to, int tolen ); + + static HRESULT LoadAdapterConfiguration(HAL_Configuration_NetworkInterface* config, uint32_t interfaceIndex); + + static HRESULT UpdateAdapterConfiguration( uint32_t interfaceIndex, uint32_t updateFlags, HAL_Configuration_NetworkInterface* config ); + + static HRESULT LoadWirelessConfiguration( uint32_t interfaceIndex, HAL_Configuration_Wireless80211* wirelessConfig ); + + +private: + static void Status_callback(struct netif *netif); + + static void Link_callback(struct netif *netif); + + static void PostAddressChanged(void* arg); + + static void PostAvailabilityOn(void* arg); + + static void PostAvailabilityOff(void* arg); + + LWIP_DRIVER_INTERFACE_DATA* m_interfaces; +}; + +// +// SOCKET driver +///////////////////////////////////////////////////////////////////////////////////////////////// + +#endif // _LWIP_SOCKETS_H_ 1 + diff --git a/source/native/nf-interpreter/src/PAL/Lwip/lwIP_Sockets_functions.cpp b/source/native/nf-interpreter/src/PAL/Lwip/lwIP_Sockets_functions.cpp new file mode 100644 index 00000000..e1e73178 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/Lwip/lwIP_Sockets_functions.cpp @@ -0,0 +1,152 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "LWIP_Sockets.h" + + +bool HAL_SOCK_Initialize() +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::Initialize(); +} + +bool HAL_SOCK_Uninitialize() +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::Uninitialize(); +} + +SOCK_SOCKET HAL_SOCK_socket( int family, int type, int protocol ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::Socket( family, type, protocol ); +} +int HAL_SOCK_bind( SOCK_SOCKET socket, const struct SOCK_sockaddr* address, int addressLen ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::Bind( socket, address, addressLen ); +} +int HAL_SOCK_connect(SOCK_SOCKET socket, const struct SOCK_sockaddr* address, int addressLen) +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::Connect(socket, address, addressLen); +} +int HAL_SOCK_send(SOCK_SOCKET socket, const char* buf, int len, int flags) +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::Send(socket, buf, len, flags); +} +int HAL_SOCK_recv(SOCK_SOCKET socket, char* buf, int len, int flags) +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::Recv(socket, buf, len, flags); +} +int HAL_SOCK_close(SOCK_SOCKET socket) +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::Close(socket); +} +int HAL_SOCK_listen( SOCK_SOCKET socket, int backlog ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::Listen( socket, backlog ); +} +SOCK_SOCKET HAL_SOCK_accept( SOCK_SOCKET socket, struct SOCK_sockaddr* address, int* addressLen ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::Accept( socket, address, addressLen ); +} +int HAL_SOCK_shutdown( SOCK_SOCKET socket, int how ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::Shutdown( socket, how ); +} +int HAL_SOCK_getaddrinfo( const char* nodename, char* servname, const struct SOCK_addrinfo* hints, struct SOCK_addrinfo** res ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::GetAddrInfo( nodename, servname, hints, res ); +} +void HAL_SOCK_freeaddrinfo( struct SOCK_addrinfo* ai ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + LWIP_SOCKETS_Driver::FreeAddrInfo( ai ); +} +int HAL_SOCK_ioctl( SOCK_SOCKET socket, int cmd, int* data ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::Ioctl( socket, cmd, data ); +} +int HAL_SOCK_getlasterror() +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::GetLastError(); +} +int HAL_SOCK_getsocklasterror(SOCK_SOCKET socket) +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::GetSockLastError(socket); +} +int HAL_SOCK_select( int nfds, SOCK_fd_set* readfds, SOCK_fd_set* writefds, SOCK_fd_set* except, const struct SOCK_timeval* timeout ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::Select( nfds, readfds, writefds, except, timeout ); +} +int HAL_SOCK_setsockopt( SOCK_SOCKET socket, int level, int optname, const char* optval, int optlen ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::SetSockOpt( socket, level, optname, optval, optlen ); +} +int HAL_SOCK_getsockopt( SOCK_SOCKET socket, int level, int optname, char* optval, int* optlen ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::GetSockOpt( socket, level, optname, optval, optlen ); +} +int HAL_SOCK_getpeername( SOCK_SOCKET socket, struct SOCK_sockaddr* name, int* namelen ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::GetPeerName( socket, name, namelen ); +} +int HAL_SOCK_getsockname( SOCK_SOCKET socket, struct SOCK_sockaddr* name, int* namelen ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::GetSockName( socket, name, namelen ); +} +int HAL_SOCK_recvfrom( SOCK_SOCKET s, char* buf, int len, int flags, struct SOCK_sockaddr* from, int* fromlen ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::RecvFrom( s, buf, len, flags, from, fromlen ); +} +int HAL_SOCK_sendto( SOCK_SOCKET s, const char* buf, int len, int flags, const struct SOCK_sockaddr* to, int tolen ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::SendTo( s, buf, len, flags, to, tolen ); +} + +HRESULT HAL_SOCK_CONFIGURATION_LoadAdapterConfiguration(HAL_Configuration_NetworkInterface* config, uint32_t interfaceIndex) +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::LoadAdapterConfiguration(config, interfaceIndex); +} + +HRESULT HAL_SOCK_CONFIGURATION_UpdateAdapterConfiguration(HAL_Configuration_NetworkInterface* config, uint32_t interfaceIndex, uint32_t updateFlags) +{ + NATIVE_PROFILE_PAL_NETWORK(); + return LWIP_SOCKETS_Driver::UpdateAdapterConfiguration(interfaceIndex, updateFlags, config); +} + +void HAL_SOCK_EventsSet( uint32_t events ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + ASSERT( (events == SOCKET_EVENT_FLAG_SOCKET) || (events == SOCKET_EVENT_FLAG_SOCKETS_READY)); + + Events_Set( SYSTEM_EVENT_FLAG_SOCKET ); +} + +void * HAL_SOCK_GlobalLockContext() +{ + NATIVE_PROFILE_PAL_NETWORK(); + return NULL; +} diff --git a/source/native/nf-interpreter/src/PAL/Profiler/nanoPAL_PerformanceCounters_stubs.cpp b/source/native/nf-interpreter/src/PAL/Profiler/nanoPAL_PerformanceCounters_stubs.cpp new file mode 100644 index 00000000..ca72a4bb --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/Profiler/nanoPAL_PerformanceCounters_stubs.cpp @@ -0,0 +1,20 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include + +__nfweak void PAL_PerformanceCounter_Initialize() +{ +} + +__nfweak void PAL_PerformanceCounter_Uninitialize() +{ +} + +__nfweak uint32_t PAL_PerformanceCounter() +{ + return 0; +} diff --git a/source/native/nf-interpreter/src/PAL/nanoPAL_Network_stubs.cpp b/source/native/nf-interpreter/src/PAL/nanoPAL_Network_stubs.cpp new file mode 100644 index 00000000..a079c544 --- /dev/null +++ b/source/native/nf-interpreter/src/PAL/nanoPAL_Network_stubs.cpp @@ -0,0 +1,21 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +__nfweak bool Network_Initialize() +{ + return true; +}; + +__nfweak bool Network_Uninitialize() +{ + return true; +}; + +__nfweak void SOCKETS_CloseConnections() +{ + NATIVE_PROFILE_PAL_COM(); +} diff --git a/source/native/nf-interpreter/src/System.Devices.Dac/sys_dev_dac_native.cpp b/source/native/nf-interpreter/src/System.Devices.Dac/sys_dev_dac_native.cpp new file mode 100644 index 00000000..fdc74d60 --- /dev/null +++ b/source/native/nf-interpreter/src/System.Devices.Dac/sys_dev_dac_native.cpp @@ -0,0 +1,53 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#include "sys_dev_dac_native.h" + + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_sys_dev_dac_native_System_Devices_Dac_DacChannel::NativeWriteValue___VOID__U2, + Library_sys_dev_dac_native_System_Devices_Dac_DacChannel::NativeDispose___VOID__BOOLEAN, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_sys_dev_dac_native_System_Devices_Dac_DacController::NativeOpenChannel___VOID__I4, + Library_sys_dev_dac_native_System_Devices_Dac_DacController::NativeGetChannelCount___I4, + Library_sys_dev_dac_native_System_Devices_Dac_DacController::NativeGetResolutionInBits___I4, + Library_sys_dev_dac_native_System_Devices_Dac_DacController::NativeInit___VOID, + NULL, + NULL, + Library_sys_dev_dac_native_System_Devices_Dac_DacController::GetDeviceSelector___STATIC__STRING, + NULL, + NULL, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Devices_Dac = +{ + "System.Devices.Dac", + 0x9B932004, + method_lookup, + { 100, 0, 0, 5 } +}; diff --git a/source/native/nf-interpreter/src/System.Devices.Dac/sys_dev_dac_native.h b/source/native/nf-interpreter/src/System.Devices.Dac/sys_dev_dac_native.h new file mode 100644 index 00000000..15b13a4a --- /dev/null +++ b/source/native/nf-interpreter/src/System.Devices.Dac/sys_dev_dac_native.h @@ -0,0 +1,55 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _SYS_DEV_DAC_NATIVE_H_ +#define _SYS_DEV_DAC_NATIVE_H_ + +#include +#include +#include + +struct Library_sys_dev_dac_native_System_Devices_Dac_DacChannel +{ + static const int FIELD___syncLock = 1; + static const int FIELD___channelNumber = 2; + static const int FIELD___dacController = 3; + static const int FIELD___disposed = 4; + + NANOCLR_NATIVE_DECLARE(NativeWriteValue___VOID__U2); + NANOCLR_NATIVE_DECLARE(NativeDispose___VOID__BOOLEAN); + + //--// + +}; + +struct Library_sys_dev_dac_native_System_Devices_Dac_DacController +{ + static const int FIELD___syncLock = 1; + static const int FIELD___controllerId = 2; + static const int FIELD__s_deviceCollection = 3; + + NANOCLR_NATIVE_DECLARE(NativeOpenChannel___VOID__I4); + NANOCLR_NATIVE_DECLARE(NativeGetChannelCount___I4); + NANOCLR_NATIVE_DECLARE(NativeGetResolutionInBits___I4); + NANOCLR_NATIVE_DECLARE(NativeInit___VOID); + NANOCLR_NATIVE_DECLARE(GetDeviceSelector___STATIC__STRING); + + //--// + +}; + +struct Library_sys_dev_dac_native_System_Devices_Dac_DacControllerManager +{ + static const int FIELD_STATIC___syncLock = 0; + static const int FIELD_STATIC__s_controllersCollection = 1; + + + //--// + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_System_Devices_Dac; + +#endif //_SYS_DEV_DAC_NATIVE_H_ diff --git a/source/native/nf-interpreter/src/Windows.Devices.Adc/win_dev_adc_native.cpp b/source/native/nf-interpreter/src/Windows.Devices.Adc/win_dev_adc_native.cpp new file mode 100644 index 00000000..e0258993 --- /dev/null +++ b/source/native/nf-interpreter/src/Windows.Devices.Adc/win_dev_adc_native.cpp @@ -0,0 +1,65 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#include "win_dev_adc_native.h" + + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_adc_native_Windows_Devices_Adc_AdcChannel::NativeReadValue___I4, + Library_win_dev_adc_native_Windows_Devices_Adc_AdcChannel::NativeDisposeChannel___VOID, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeOpenChannel___VOID__I4, + Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeGetChannelCount___I4, + Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeGetMaxValue___I4, + Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeGetMinValue___I4, + Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeIsChannelModeSupported___BOOLEAN__I4, + Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeGetResolutionInBits___I4, + Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeInit___VOID, + NULL, + NULL, + Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::GetDeviceSelector___STATIC__STRING, + NULL, + NULL, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Adc = +{ + "Windows.Devices.Adc", + 0xDEDF1136, + method_lookup, + { 100, 1, 3, 2 } +}; diff --git a/source/native/nf-interpreter/src/Windows.Devices.Adc/win_dev_adc_native.h b/source/native/nf-interpreter/src/Windows.Devices.Adc/win_dev_adc_native.h new file mode 100644 index 00000000..9911ef50 --- /dev/null +++ b/source/native/nf-interpreter/src/Windows.Devices.Adc/win_dev_adc_native.h @@ -0,0 +1,68 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIN_DEV_ADC_NATIVE_H_ +#define _WIN_DEV_ADC_NATIVE_H_ + +#include +#include +#include + +/////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.Adc.AdcChannelMode (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////// +enum AdcChannelMode +{ + SingleEnded = 0, + Differential +}; + +struct Library_win_dev_adc_native_Windows_Devices_Adc_AdcChannel +{ + static const int FIELD___syncLock = 1; + static const int FIELD___channelNumber = 2; + static const int FIELD___adcController = 3; + static const int FIELD___disposed = 4; + + NANOCLR_NATIVE_DECLARE(NativeReadValue___I4); + NANOCLR_NATIVE_DECLARE(NativeDisposeChannel___VOID); + + //--// + +}; + +struct Library_win_dev_adc_native_Windows_Devices_Adc_AdcController +{ + static const int FIELD___syncLock = 1; + static const int FIELD___controllerId = 2; + static const int FIELD___channelMode = 3; + static const int FIELD__s_deviceCollection = 4; + + NANOCLR_NATIVE_DECLARE(NativeOpenChannel___VOID__I4); + NANOCLR_NATIVE_DECLARE(NativeGetChannelCount___I4); + NANOCLR_NATIVE_DECLARE(NativeGetMaxValue___I4); + NANOCLR_NATIVE_DECLARE(NativeGetMinValue___I4); + NANOCLR_NATIVE_DECLARE(NativeIsChannelModeSupported___BOOLEAN__I4); + NANOCLR_NATIVE_DECLARE(NativeGetResolutionInBits___I4); + NANOCLR_NATIVE_DECLARE(NativeInit___VOID); + NANOCLR_NATIVE_DECLARE(GetDeviceSelector___STATIC__STRING); + + //--// + +}; + +struct Library_win_dev_adc_native_Windows_Devices_Adc_AdcControllerManager +{ + static const int FIELD_STATIC___syncLock = 0; + static const int FIELD_STATIC__s_controllersCollection = 1; + + + //--// + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Adc; + +#endif //_WIN_DEV_ADC_NATIVE_H_ diff --git a/source/native/nf-interpreter/src/Windows.Devices.Gpio/win_dev_gpio_native.cpp b/source/native/nf-interpreter/src/Windows.Devices.Gpio/win_dev_gpio_native.cpp new file mode 100644 index 00000000..4228fdd0 --- /dev/null +++ b/source/native/nf-interpreter/src/Windows.Devices.Gpio/win_dev_gpio_native.cpp @@ -0,0 +1,103 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#include "win_dev_gpio_native.h" + + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter::NativeInit___VOID, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter::NativeRead___U8__BOOLEAN, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter::NativeStart___VOID, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter::NativeStop___VOID, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter::NativeDispose___VOID, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioController::get_PinCount___I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::Read___WindowsDevicesGpioGpioPinValue, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::Toggle___VOID, + NULL, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::DisposeNative___VOID, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeIsDriveModeSupported___BOOLEAN__WindowsDevicesGpioGpioPinDriveMode, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeSetDriveMode___VOID__WindowsDevicesGpioGpioPinDriveMode, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeInit___BOOLEAN__I4, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeSetDebounceTimeout___VOID, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::WriteNative___VOID__WindowsDevicesGpioGpioPinValue, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeSetAlternateFunction___VOID__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Gpio = +{ + "Windows.Devices.Gpio", + 0x2432E7EB, + method_lookup, + { 100, 1, 2, 0 } +}; diff --git a/source/native/nf-interpreter/src/Windows.Devices.Gpio/win_dev_gpio_native.h b/source/native/nf-interpreter/src/Windows.Devices.Gpio/win_dev_gpio_native.h new file mode 100644 index 00000000..84220227 --- /dev/null +++ b/source/native/nf-interpreter/src/Windows.Devices.Gpio/win_dev_gpio_native.h @@ -0,0 +1,155 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIN_DEV_GPIO_NATIVE_H_ +#define _WIN_DEV_GPIO_NATIVE_H_ + +#include +#include +#include +#include + +/////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.Gpio.GpioPinDriveMode (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////// + +enum GpioPinDriveMode +{ + GpioPinDriveMode_Input = 0, + GpioPinDriveMode_InputPullDown, + GpioPinDriveMode_InputPullUp, + GpioPinDriveMode_Output, + GpioPinDriveMode_OutputOpenDrain, + GpioPinDriveMode_OutputOpenDrainPullUp, + GpioPinDriveMode_OutputOpenSource, + GpioPinDriveMode_OutputOpenSourcePullDown +}; + +/////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.Gpio.GpioPinValue (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////// + +enum GpioPinValue +{ + GpioPinValue_Low = 0, + GpioPinValue_High, +}; + +/////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.Gpio.GpioChangePolarity (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////// + +enum GpioChangePolarity +{ + Both = 0, + Falling, + Rising +}; + + +/////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////// + +struct Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCount +{ + static const int FIELD__Count = 1; + static const int FIELD__RelativeTime = 2; + + + //--// + +}; + +struct Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter +{ + static const int FIELD___pinNumber = 1; + static const int FIELD___inputMode = 2; + static const int FIELD___polarity = 3; + static const int FIELD___CountActive = 4; + static const int FIELD___readTime = 5; + static const int FIELD___syncLock = 6; + static const int FIELD___disposedValue = 7; + + NANOCLR_NATIVE_DECLARE(NativeInit___VOID); + NANOCLR_NATIVE_DECLARE(NativeRead___U8__BOOLEAN); + NANOCLR_NATIVE_DECLARE(NativeStart___VOID); + NANOCLR_NATIVE_DECLARE(NativeStop___VOID); + NANOCLR_NATIVE_DECLARE(NativeDispose___VOID); + + //--// + +}; + + +struct Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioController +{ + static const int FIELD_STATIC___syncLock = 0; + static const int FIELD_STATIC__s_instance = 1; + + NANOCLR_NATIVE_DECLARE(get_PinCount___I4); + + //--// + +}; + +struct Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin +{ + static const int FIELD_STATIC__s_eventListener = 2; + + static const int FIELD___syncLock = 1; + static const int FIELD___pinNumber = 2; + static const int FIELD___driveMode = 3; + static const int FIELD___debounceTimeout = 4; + static const int FIELD___callbacks = 5; + static const int FIELD___lastOutputValue = 6; + static const int FIELD___lastInputValue = 7; + static const int FIELD___disposedValue = 8; + + NANOCLR_NATIVE_DECLARE(Read___WindowsDevicesGpioGpioPinValue); + NANOCLR_NATIVE_DECLARE(Toggle___VOID); + NANOCLR_NATIVE_DECLARE(DisposeNative___VOID); + NANOCLR_NATIVE_DECLARE(NativeIsDriveModeSupported___BOOLEAN__WindowsDevicesGpioGpioPinDriveMode); + NANOCLR_NATIVE_DECLARE(NativeSetDriveMode___VOID__WindowsDevicesGpioGpioPinDriveMode); + NANOCLR_NATIVE_DECLARE(NativeInit___BOOLEAN__I4); + NANOCLR_NATIVE_DECLARE(NativeSetDebounceTimeout___VOID); + NANOCLR_NATIVE_DECLARE(WriteNative___VOID__WindowsDevicesGpioGpioPinValue); + NANOCLR_NATIVE_DECLARE(NativeSetAlternateFunction___VOID__I4); + + //--// + +}; + +struct Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPinEvent +{ + static const int FIELD__PinNumber = 3; + static const int FIELD__Edge = 4; + + + //--// + +}; + +struct Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPinEventListener +{ + static const int FIELD___pinMap = 1; + + + //--// + +}; + +struct Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPinValueChangedEventArgs +{ + static const int FIELD___edge = 1; + + + //--// + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Gpio; + +#endif //_WIN_DEV_GPIO_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/src/Windows.Devices.I2c/win_dev_i2c_native.cpp b/source/native/nf-interpreter/src/Windows.Devices.I2c/win_dev_i2c_native.cpp new file mode 100644 index 00000000..1dc2ad14 --- /dev/null +++ b/source/native/nf-interpreter/src/Windows.Devices.I2c/win_dev_i2c_native.cpp @@ -0,0 +1,66 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_i2c_native.h" + + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_i2c_native_Windows_Devices_I2c_I2cController::NativeInit___VOID, + NULL, + NULL, + Library_win_dev_i2c_native_Windows_Devices_I2c_I2cController::GetDeviceSelector___STATIC__STRING, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::NativeInit___VOID, + Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::NativeDispose___VOID__BOOLEAN, + Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::NativeTransmit___WindowsDevicesI2cI2cTransferResult__SZARRAY_U1__SZARRAY_U1, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_I2c = +{ + "Windows.Devices.I2c", + 0x8D1C8F95, + method_lookup, + { 100, 2, 0, 1 } +}; diff --git a/source/native/nf-interpreter/src/Windows.Devices.I2c/win_dev_i2c_native.h b/source/native/nf-interpreter/src/Windows.Devices.I2c/win_dev_i2c_native.h new file mode 100644 index 00000000..eca7cb98 --- /dev/null +++ b/source/native/nf-interpreter/src/Windows.Devices.I2c/win_dev_i2c_native.h @@ -0,0 +1,107 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIN_DEV_I2C_NATIVE_H_ +#define _WIN_DEV_I2C_NATIVE_H_ + +#include +#include +#include + +/////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.I2c.I2cSharingMode (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////// +enum I2cSharingMode +{ + Exclusive = 0, + Shared +}; + +/////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.I2c.I2cTransferStatus (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////// + enum I2cTransferStatus +{ + I2cTransferStatus_FullTransfer = 0, + I2cTransferStatus_ClockStretchTimeout, + I2cTransferStatus_PartialTransfer, + I2cTransferStatus_SlaveAddressNotAcknowledged, + I2cTransferStatus_UnknownError +}; + +/////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.I2c.I2cBusSpeed (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////// +enum I2cBusSpeed +{ + I2cBusSpeed_StandardMode = 0, + I2cBusSpeed_FastMode +}; + +/////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////// + +struct Library_win_dev_i2c_native_Windows_Devices_I2c_I2cConnectionSettings +{ + static const int FIELD___slaveAddress = 1; + static const int FIELD___busSpeed = 2; + static const int FIELD___sharingMode = 3; + + + //--// + +}; + +struct Library_win_dev_i2c_native_Windows_Devices_I2c_I2cController +{ + static const int FIELD___syncLock = 1; + static const int FIELD___controllerId = 2; + static const int FIELD__s_deviceCollection = 3; + + NANOCLR_NATIVE_DECLARE(NativeInit___VOID); + NANOCLR_NATIVE_DECLARE(GetDeviceSelector___STATIC__STRING); + + //--// + +}; + +struct Library_win_dev_i2c_native_Windows_Devices_I2c_I2cControllerManager +{ + static const int FIELD_STATIC___syncLock = 0; + static const int FIELD_STATIC__s_controllersCollection = 1; + + + //--// + +}; + +struct Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice +{ + static const int FIELD___syncLock = 1; + static const int FIELD___deviceId = 2; + static const int FIELD___connectionSettings = 3; + static const int FIELD___disposed = 4; + + NANOCLR_NATIVE_DECLARE(NativeInit___VOID); + NANOCLR_NATIVE_DECLARE(NativeDispose___VOID__BOOLEAN); + NANOCLR_NATIVE_DECLARE(NativeTransmit___WindowsDevicesI2cI2cTransferResult__SZARRAY_U1__SZARRAY_U1); + + //--// + +}; + +struct Library_win_dev_i2c_native_Windows_Devices_I2c_I2cTransferResult +{ + static const int FIELD___bytesTransferred = 1; + static const int FIELD___status = 2; + + + //--// + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_I2c; + +#endif //_WIN_DEV_I2C_NATIVE_H_ diff --git a/source/native/nf-interpreter/src/Windows.Devices.Pwm/win_dev_pwm_native.cpp b/source/native/nf-interpreter/src/Windows.Devices.Pwm/win_dev_pwm_native.cpp new file mode 100644 index 00000000..f9e80727 --- /dev/null +++ b/source/native/nf-interpreter/src/Windows.Devices.Pwm/win_dev_pwm_native.cpp @@ -0,0 +1,65 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_pwm_native.h" + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_MaxFrequency___R8, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_MinFrequency___R8, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_PinCount___I4, + NULL, + NULL, + NULL, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::NativeSetDesiredFrequency___U4__U4, + NULL, + NULL, + NULL, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::GetDeviceSelector___STATIC__STRING, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeInit___VOID, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeSetActiveDutyCyclePercentage___VOID__U4, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeSetPolarity___VOID__U1, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeStart___VOID, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeStop___VOID, + Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::DisposeNative___VOID, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Pwm = +{ + "Windows.Devices.Pwm", + 0x84D8B10C, + method_lookup, + { 100, 1, 3, 2 } +}; diff --git a/source/native/nf-interpreter/src/Windows.Devices.Pwm/win_dev_pwm_native.h b/source/native/nf-interpreter/src/Windows.Devices.Pwm/win_dev_pwm_native.h new file mode 100644 index 00000000..a58cd007 --- /dev/null +++ b/source/native/nf-interpreter/src/Windows.Devices.Pwm/win_dev_pwm_native.h @@ -0,0 +1,64 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIN_DEV_PWM_NATIVE_H_ +#define _WIN_DEV_PWM_NATIVE_H_ + +#include +#include +#include + +struct Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController +{ + static const int FIELD___controllerId = 1; + static const int FIELD___actualFrequency = 2; + static const int FIELD___pwmTimer = 3; + + NANOCLR_NATIVE_DECLARE(get_MaxFrequency___R8); + NANOCLR_NATIVE_DECLARE(get_MinFrequency___R8); + NANOCLR_NATIVE_DECLARE(get_PinCount___I4); + NANOCLR_NATIVE_DECLARE(NativeSetDesiredFrequency___U4__U4); + NANOCLR_NATIVE_DECLARE(GetDeviceSelector___STATIC__STRING); + + //--// + +}; + +struct Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmControllerManager +{ + static const int FIELD_STATIC___syncLock = 0; + static const int FIELD_STATIC__s_controllersCollection = 1; + + + //--// + +}; + +struct Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin +{ + static const int FIELD___syncLock = 1; + static const int FIELD___pwmController = 2; + static const int FIELD___polarity = 3; + static const int FIELD___dutyCyclePercentage = 4; + static const int FIELD___dutyCycle = 5; + static const int FIELD___pinNumber = 6; + static const int FIELD___pwmTimer = 7; + static const int FIELD___isStarted = 8; + static const int FIELD___disposed = 9; + + NANOCLR_NATIVE_DECLARE(NativeInit___VOID); + NANOCLR_NATIVE_DECLARE(NativeSetActiveDutyCyclePercentage___VOID__U4); + NANOCLR_NATIVE_DECLARE(NativeSetPolarity___VOID__U1); + NANOCLR_NATIVE_DECLARE(NativeStart___VOID); + NANOCLR_NATIVE_DECLARE(NativeStop___VOID); + NANOCLR_NATIVE_DECLARE(DisposeNative___VOID); + + //--// + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Pwm; + +#endif //_WIN_DEV_PWM_NATIVE_H_ diff --git a/source/native/nf-interpreter/src/Windows.Devices.SerialCommunication/win_dev_serial_native.cpp b/source/native/nf-interpreter/src/Windows.Devices.SerialCommunication/win_dev_serial_native.cpp new file mode 100644 index 00000000..0a524fda --- /dev/null +++ b/source/native/nf-interpreter/src/Windows.Devices.SerialCommunication/win_dev_serial_native.cpp @@ -0,0 +1,87 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#include "win_dev_serial_native.h" + + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::get_BytesToRead___U4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::NativeDispose___VOID, + Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::NativeInit___VOID, + Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::NativeConfig___VOID, + Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::NativeWrite___VOID__SZARRAY_U1, + Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::NativeStore___U4, + Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::NativeRead___U4__SZARRAY_U1__I4__I4, + Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::NativeSetWatchChar___VOID, + NULL, + Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::GetDeviceSelector___STATIC__STRING, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_SerialCommunication = +{ + "Windows.Devices.SerialCommunication", + 0x8E46E2E2, + method_lookup, + { 100, 1, 1, 0 } +}; diff --git a/source/native/nf-interpreter/src/Windows.Devices.SerialCommunication/win_dev_serial_native.h b/source/native/nf-interpreter/src/Windows.Devices.SerialCommunication/win_dev_serial_native.h new file mode 100644 index 00000000..a3b099fd --- /dev/null +++ b/source/native/nf-interpreter/src/Windows.Devices.SerialCommunication/win_dev_serial_native.h @@ -0,0 +1,184 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIN_DEV_SERIAL_NATIVE_H_ +#define _WIN_DEV_SERIAL_NATIVE_H_ + +#include +#include +#include +#include + +///////////////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.SerialCommunication.SerialHandshake (in managed code) !!! // +///////////////////////////////////////////////////////////////////////////////////////////////////// +enum SerialHandshake +{ + SerialHandshake_None = 0, + SerialHandshake_RequestToSend, + SerialHandshake_RequestToSendXOnXOff, + SerialHandshake_XOnXOff +}; + +////////////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.SerialCommunication.SerialParity (in managed code) !!! // +////////////////////////////////////////////////////////////////////////////////////////////////// +enum SerialParity +{ + SerialParity_None = 0, + SerialParity_Even, + SerialParity_Mark, + SerialParity_Odd, + SerialParity_Space +}; + +//////////////////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.SerialCommunication.SerialStopBitCount (in managed code) !!! // +//////////////////////////////////////////////////////////////////////////////////////////////////////// +enum SerialStopBitCount +{ + SerialStopBitCount_One = 0, + SerialStopBitCount_OnePointFive, + SerialStopBitCount_Two +}; + +///////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Storage.Streams.InputStreamOptions (in managed code) !!! // +///////////////////////////////////////////////////////////////////////////////////////////// + +enum InputStreamOptions +{ + InputStreamOptions_None = 0, + InputStreamOptions_Partial, + InputStreamOptions_ReadAhead +}; + +//////////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.SerialCommunication.SerialData (in managed code) !!! // +//////////////////////////////////////////////////////////////////////////////////////////////// +enum SerialData +{ + SerialData_Chars = 0, + SerialData_WatchChar, +}; + +/////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////// + +struct Library_win_dev_serial_native_Windows_Devices_SerialCommunication_ErrorReceivedEventArgs +{ + static const int FIELD___error = 1; + + + //--// + +}; + +struct Library_win_dev_serial_native_Windows_Devices_SerialCommunication_PinChangedEventArgs +{ + static const int FIELD___pinChange = 1; + + + //--// + +}; + +struct Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDataEvent +{ + static const int FIELD__SerialDeviceIndex = 3; + static const int FIELD__Event = 4; + + + //--// + +}; + +struct Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDataReceivedEventArgs +{ + static const int FIELD___data = 1; + + + //--// + +}; + +struct Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice +{ + static const int FIELD_STATIC__s_eventListener = 0; + + static const int FIELD___disposed = 1; + static const int FIELD___syncLock = 2; + static const int FIELD___opened = 3; + static const int FIELD___deviceId = 4; + static const int FIELD___portIndex = 5; + static const int FIELD___outputStream = 6; + static const int FIELD___inputStream = 7; + static const int FIELD___readTimeout = 8; + static const int FIELD___writeTimeout = 9; + static const int FIELD___baudRate = 10; + static const int FIELD___dataBits = 11; + static const int FIELD___handshake = 12; + static const int FIELD___parity = 13; + static const int FIELD___stopBits = 14; + static const int FIELD___bytesReceived = 15; + static const int FIELD___watchChar = 16; + static const int FIELD___callbacksDataReceivedEvent = 17; + + NANOCLR_NATIVE_DECLARE(get_BytesToRead___U4); + NANOCLR_NATIVE_DECLARE(NativeDispose___VOID); + NANOCLR_NATIVE_DECLARE(NativeInit___VOID); + NANOCLR_NATIVE_DECLARE(NativeConfig___VOID); + NANOCLR_NATIVE_DECLARE(NativeWrite___VOID__SZARRAY_U1); + NANOCLR_NATIVE_DECLARE(NativeStore___U4); + NANOCLR_NATIVE_DECLARE(NativeRead___U4__SZARRAY_U1__I4__I4); + NANOCLR_NATIVE_DECLARE(NativeSetWatchChar___VOID); + NANOCLR_NATIVE_DECLARE(GetDeviceSelector___STATIC__STRING); + + //--// + +}; + +struct Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDeviceController +{ + static const int FIELD_STATIC___syncLock = 1; + static const int FIELD_STATIC__s_instance = 2; + static const int FIELD_STATIC__s_deviceCollection = 3; + + + //--// + +}; + +struct Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDeviceEventListener +{ + static const int FIELD___serialDevicesMap = 1; + + + //--// + +}; + +struct Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDeviceInputStream +{ + static const int FIELD___serialDevice = 1; + + + //--// + +}; + +struct Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDeviceOutputStream +{ + static const int FIELD___serialDevice = 1; + static const int FIELD___unstoredBufferLength = 2; + + + //--// + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_SerialCommunication; + +#endif //_WIN_DEV_SERIAL_NATIVE_H_ diff --git a/source/native/nf-interpreter/src/Windows.Devices.Spi/win_dev_spi_native.cpp b/source/native/nf-interpreter/src/Windows.Devices.Spi/win_dev_spi_native.cpp new file mode 100644 index 00000000..995bf22c --- /dev/null +++ b/source/native/nf-interpreter/src/Windows.Devices.Spi/win_dev_spi_native.cpp @@ -0,0 +1,79 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#include "win_dev_spi_native.h" + + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo::get_MaxClockFrequency___I4, + Library_win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo::get_MinClockFrequency___I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_spi_native_Windows_Devices_Spi_SpiController::GetDeviceSelector___STATIC__STRING, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::DisposeNative___VOID, + Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer___VOID__SZARRAY_U1__SZARRAY_U1__BOOLEAN, + Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer___VOID__SZARRAY_U2__SZARRAY_U2__BOOLEAN, + Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeInit___VOID, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Spi = +{ + "Windows.Devices.Spi", + 0xEA555AF2, + method_lookup, + { 100, 1, 4, 0 } +}; diff --git a/source/native/nf-interpreter/src/Windows.Devices.Spi/win_dev_spi_native.h b/source/native/nf-interpreter/src/Windows.Devices.Spi/win_dev_spi_native.h new file mode 100644 index 00000000..1655de3d --- /dev/null +++ b/source/native/nf-interpreter/src/Windows.Devices.Spi/win_dev_spi_native.h @@ -0,0 +1,108 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#ifndef _WIN_DEV_SPI_NATIVE_H_ +#define _WIN_DEV_SPI_NATIVE_H_ + + +#include +#include +#include + + +/////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.Spi.SpiMode (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////// + +enum DataBitOrder +{ + DataBitOrder_MSB = 0, + DataBitOrder_LSB +}; + +/////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.Spi.SpiMode (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////// + +enum SpiModes +{ + SpiModes_Mode0 = 0, + SpiModes_Mode1, + SpiModes_Mode2, + SpiModes_Mode3 +}; + +/////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////// + +struct Library_win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo +{ + static const int FIELD___chipSelectLineCount = 1; + + NANOCLR_NATIVE_DECLARE(get_MaxClockFrequency___I4); + NANOCLR_NATIVE_DECLARE(get_MinClockFrequency___I4); + + //--// + +}; + +struct Library_win_dev_spi_native_Windows_Devices_Spi_SpiConnectionSettings +{ + static const int FIELD___csLine = 1; + static const int FIELD___clockFrequency = 2; + static const int FIELD___databitLength = 3; + static const int FIELD___spiMode = 4; + static const int FIELD___spiSharingMode = 5; + static const int FIELD___bitOrder = 6; + + + //--// + +}; + +struct Library_win_dev_spi_native_Windows_Devices_Spi_SpiController +{ + static const int FIELD___syncLock = 1; + static const int FIELD___controllerId = 2; + static const int FIELD__s_deviceCollection = 3; + + NANOCLR_NATIVE_DECLARE(GetDeviceSelector___STATIC__STRING); + + //--// + +}; + +struct Library_win_dev_spi_native_Windows_Devices_Spi_SpiControllerManager +{ + static const int FIELD_STATIC__s_syncLock = 0; + static const int FIELD_STATIC__s_controllersCollection = 1; + + + //--// + +}; + +struct Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice +{ + static const int FIELD___syncLock = 1; + static const int FIELD___spiBus = 2; + static const int FIELD___deviceId = 3; + static const int FIELD___connectionSettings = 4; + static const int FIELD___disposedValue = 5; + + NANOCLR_NATIVE_DECLARE(DisposeNative___VOID); + NANOCLR_NATIVE_DECLARE(NativeTransfer___VOID__SZARRAY_U1__SZARRAY_U1__BOOLEAN); + NANOCLR_NATIVE_DECLARE(NativeTransfer___VOID__SZARRAY_U2__SZARRAY_U2__BOOLEAN); + NANOCLR_NATIVE_DECLARE(NativeInit___VOID); + + //--// + + static HRESULT NativeTransfer(CLR_RT_StackFrame& stack, bool bufferIs16bits); +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Spi; + +#endif //_WIN_DEV_SPI_NATIVE_H_ diff --git a/source/native/nf-interpreter/src/Windows.Devices.Wifi/win_dev_wifi_native.cpp b/source/native/nf-interpreter/src/Windows.Devices.Wifi/win_dev_wifi_native.cpp new file mode 100644 index 00000000..7967b885 --- /dev/null +++ b/source/native/nf-interpreter/src/Windows.Devices.Wifi/win_dev_wifi_native.cpp @@ -0,0 +1,63 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_wifi_native.h" + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiAdapter::DisposeNative___VOID, + Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiAdapter::NativeInit___VOID, + Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiAdapter::NativeConnect___WindowsDevicesWiFiWiFiConnectionStatus__STRING__STRING__WindowsDevicesWiFiWiFiReconnectionKind, + Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiAdapter::NativeDisconnect___VOID, + Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiAdapter::NativeScanAsync___VOID, + Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiAdapter::GetNativeScanReport___SZARRAY_U1, + NULL, + Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiAdapter::NativeFindWirelessAdapters___STATIC__SZARRAY_U1, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Wifi = +{ + "Windows.Devices.Wifi", + 0x5AC050C9, + method_lookup, + { 100, 0, 6, 0 } +}; diff --git a/source/native/nf-interpreter/src/Windows.Devices.Wifi/win_dev_wifi_native.h b/source/native/nf-interpreter/src/Windows.Devices.Wifi/win_dev_wifi_native.h new file mode 100644 index 00000000..6100027f --- /dev/null +++ b/source/native/nf-interpreter/src/Windows.Devices.Wifi/win_dev_wifi_native.h @@ -0,0 +1,87 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#ifndef _WIN_DEV_WIFI_NATIVE_H_ +#define _WIN_DEV_WIFI_NATIVE_H_ + +#include +#include +#include + +struct Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiAdapter +{ + static const int FIELD_STATIC__s_eventListener = 0; + + static const int FIELD___networkInterface = 1; + static const int FIELD___syncLock = 2; + static const int FIELD__AvailableNetworksChanged = 3; + static const int FIELD___disposedValue = 4; + + NANOCLR_NATIVE_DECLARE(DisposeNative___VOID); + NANOCLR_NATIVE_DECLARE(NativeInit___VOID); + NANOCLR_NATIVE_DECLARE(NativeConnect___WindowsDevicesWiFiWiFiConnectionStatus__STRING__STRING__WindowsDevicesWiFiWiFiReconnectionKind); + NANOCLR_NATIVE_DECLARE(NativeDisconnect___VOID); + NANOCLR_NATIVE_DECLARE(NativeScanAsync___VOID); + NANOCLR_NATIVE_DECLARE(GetNativeScanReport___SZARRAY_U1); + NANOCLR_NATIVE_DECLARE(NativeFindWirelessAdapters___STATIC__SZARRAY_U1); + + //--// + + static HRESULT GetNetInterfaceIndex(CLR_RT_StackFrame& stack, int * pNetIndex); +}; + +struct Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiAvailableNetwork +{ + static const int FIELD___bsid = 1; + static const int FIELD___ssid = 2; + static const int FIELD___rssi = 3; + static const int FIELD___networkKind = 4; + + + //--// + +}; + +struct Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiConnectionResult +{ + static const int FIELD___ConnectionStatus = 1; + + + //--// + +}; + +struct Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiEvent +{ + static const int FIELD__EventType = 3; + static const int FIELD__Time = 4; + + + //--// + +}; + +struct Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiEventListener +{ + static const int FIELD__wifiAdapters = 1; + + + //--// + +}; + +struct Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiNetworkReport +{ + static const int FIELD___wifiNetworks = 1; + + + //--// + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Wifi; + +#endif //_WIN_DEV_WIFI_NATIVE_H_ diff --git a/source/native/nf-interpreter/src/Windows.Networking.Sockets/win_net_sockets_native.cpp b/source/native/nf-interpreter/src/Windows.Networking.Sockets/win_net_sockets_native.cpp new file mode 100644 index 00000000..cc85cebb --- /dev/null +++ b/source/native/nf-interpreter/src/Windows.Networking.Sockets/win_net_sockets_native.cpp @@ -0,0 +1,119 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "win_net_sockets_native.h" + + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::socket___STATIC__I4__I4__I4__I4, + Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::bind___STATIC__VOID__OBJECT__SZARRAY_U1, + Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::connect___STATIC__VOID__OBJECT__SZARRAY_U1__BOOLEAN, + Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::send___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4, + Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::recv___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4, + Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::close___STATIC__I4__OBJECT, + Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::listen___STATIC__VOID__OBJECT__I4, + Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::accept___STATIC__I4__OBJECT, + Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::getaddrinfo___STATIC__VOID__STRING__BYREF_STRING__BYREF_SZARRAY_SZARRAY_U1, + Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::shutdown___STATIC__VOID__OBJECT__I4__BYREF_I4, + Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::sendto___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4__SZARRAY_U1, + Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::recvfrom___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4__BYREF_SZARRAY_U1, + Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::getpeername___STATIC__VOID__OBJECT__BYREF_SZARRAY_U1, + Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::getsockname___STATIC__VOID__OBJECT__BYREF_SZARRAY_U1, + Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::getsockopt___STATIC__VOID__OBJECT__I4__I4__SZARRAY_U1, + Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::setsockopt___STATIC__VOID__OBJECT__I4__I4__SZARRAY_U1, + Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::poll___STATIC__BOOLEAN__OBJECT__I4__I4, + Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::ioctl___STATIC__VOID__OBJECT__U4__BYREF_U4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Networking_Sockets = +{ + "Windows.Networking.Sockets", + 0x03D7E1A6, + method_lookup, + { 1, 0, 0, 0 } +}; diff --git a/source/native/nf-interpreter/src/Windows.Networking.Sockets/win_net_sockets_native.h b/source/native/nf-interpreter/src/Windows.Networking.Sockets/win_net_sockets_native.h new file mode 100644 index 00000000..9b2d9775 --- /dev/null +++ b/source/native/nf-interpreter/src/Windows.Networking.Sockets/win_net_sockets_native.h @@ -0,0 +1,126 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +//--------------------------------------------------------------------------- + +#ifndef _WIN_NET_SOCKETS_NATIVE_H_ +#define _WIN_NET_SOCKETS_NATIVE_H_ + +#include +#include +#include + + +struct Library_win_net_sockets_native_Windows_Networking_EndpointPair +{ + static const int FIELD__localHostName = 1; + static const int FIELD__localServiceName = 2; + static const int FIELD__remoteHostName = 3; + static const int FIELD__remoteServiceName = 4; + + + //--// + +}; + +struct Library_win_net_sockets_native_Windows_Networking_HostName +{ + static const int FIELD__canonicalName = 1; + static const int FIELD__displayName = 2; + static const int FIELD__rawName = 3; + static const int FIELD__hostNameType = 4; + + + //--// + +}; + +struct Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative +{ + NANOCLR_NATIVE_DECLARE(socket___STATIC__I4__I4__I4__I4); + NANOCLR_NATIVE_DECLARE(bind___STATIC__VOID__OBJECT__SZARRAY_U1); + NANOCLR_NATIVE_DECLARE(connect___STATIC__VOID__OBJECT__SZARRAY_U1__BOOLEAN); + NANOCLR_NATIVE_DECLARE(send___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4); + NANOCLR_NATIVE_DECLARE(recv___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4); + NANOCLR_NATIVE_DECLARE(close___STATIC__I4__OBJECT); + NANOCLR_NATIVE_DECLARE(listen___STATIC__VOID__OBJECT__I4); + NANOCLR_NATIVE_DECLARE(accept___STATIC__I4__OBJECT); + NANOCLR_NATIVE_DECLARE(getaddrinfo___STATIC__VOID__STRING__BYREF_STRING__BYREF_SZARRAY_SZARRAY_U1); + NANOCLR_NATIVE_DECLARE(shutdown___STATIC__VOID__OBJECT__I4__BYREF_I4); + NANOCLR_NATIVE_DECLARE(sendto___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4__SZARRAY_U1); + NANOCLR_NATIVE_DECLARE(recvfrom___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4__BYREF_SZARRAY_U1); + NANOCLR_NATIVE_DECLARE(getpeername___STATIC__VOID__OBJECT__BYREF_SZARRAY_U1); + NANOCLR_NATIVE_DECLARE(getsockname___STATIC__VOID__OBJECT__BYREF_SZARRAY_U1); + NANOCLR_NATIVE_DECLARE(getsockopt___STATIC__VOID__OBJECT__I4__I4__SZARRAY_U1); + NANOCLR_NATIVE_DECLARE(setsockopt___STATIC__VOID__OBJECT__I4__I4__SZARRAY_U1); + NANOCLR_NATIVE_DECLARE(poll___STATIC__BOOLEAN__OBJECT__I4__I4); + NANOCLR_NATIVE_DECLARE(ioctl___STATIC__VOID__OBJECT__U4__BYREF_U4); + + //--// + static HRESULT MarshalSockAddress( struct SOCK_sockaddr* addrDst, CLR_UINT32& addrLenDst, const CLR_RT_HeapBlock& blkSrc ); + static HRESULT MarshalSockAddress( CLR_RT_HeapBlock& blkDst, const struct SOCK_sockaddr* addrSrc, CLR_UINT32 addrLenSrc ); + static HRESULT SendRecvHelper( CLR_RT_StackFrame& stack, bool fSend, bool fAddress ); + static HRESULT SockOptHelper( CLR_RT_StackFrame& stack, bool fGet ); + static HRESULT SockNameHelper( CLR_RT_StackFrame& stack, bool fPeer ); + static HRESULT BindConnectHelper( CLR_RT_StackFrame& stack, bool fBind ); + static HRESULT ThrowOnError( CLR_RT_StackFrame& stack, CLR_INT32 err ); + static void ThrowError( CLR_RT_StackFrame& stack, CLR_INT32 errorCode ); + + static CLR_INT32 Helper__SelectSocket( CLR_INT32 socket, CLR_INT32 mode ); + + /* WARNING!!! + * The value of this constant is the offset for the m_Handle field in the System.Net.Sockets.Socket class. + * It is defined here to avoid a circular reference issue. + */ + static const int FIELD__m_Handle = 1; + + static const int DISPOSED_HANDLE = -1; +}; + +struct Library_win_net_sockets_native_Windows_Networking_Sockets_StreamSocket +{ + static const int FIELD__control = 1; + static const int FIELD__socketHandle = 2; + + + //--// + +}; + +struct Library_win_net_sockets_native_Windows_Networking_Sockets_StreamSocketControl +{ + static const int FIELD__keepAlive = 1; + static const int FIELD__minProtectionLevel = 2; + static const int FIELD__noDelay = 3; + static const int FIELD__outboundBufferSizeInBytes = 4; + static const int FIELD__outboundUnicastHopLimit = 5; + static const int FIELD__qualityOfService = 6; + static const int FIELD__serializeConnectionAttempts = 7; + + + //--// + +}; + +struct Library_win_net_sockets_native_Windows_Networking_Sockets_StreamSocketInformation +{ + static const int FIELD__localAddress = 1; + static const int FIELD__localPort = 2; + static const int FIELD__protectionLevel = 3; + static const int FIELD__remoteAddress = 4; + static const int FIELD__remoteHostName = 5; + static const int FIELD__remotePort = 6; + static const int FIELD__remoteServiceName = 7; + + + //--// + +}; + + + //--// + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Networking_Sockets; + +#endif //_WIN_NET_SOCKETS_NATIVE_H_ diff --git a/source/native/nf-interpreter/src/Windows.Storage/win_storage_native.cpp b/source/native/nf-interpreter/src/Windows.Storage/win_storage_native.cpp new file mode 100644 index 00000000..96e3df5c --- /dev/null +++ b/source/native/nf-interpreter/src/Windows.Storage/win_storage_native.cpp @@ -0,0 +1,111 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_storage_native.h" + + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_storage_native_Windows_Storage_Devices_SDCard::MountMMCNative___STATIC__VOID__BOOLEAN, + Library_win_storage_native_Windows_Storage_Devices_SDCard::MountSpiNative___STATIC__VOID__I4__I4, + Library_win_storage_native_Windows_Storage_Devices_SDCard::UnmountNative___STATIC__VOID, + NULL, + NULL, + NULL, + NULL, + Library_win_storage_native_Windows_Storage_FileIO::WriteBytes___STATIC__VOID__WindowsStorageIStorageFile__SZARRAY_U1, + Library_win_storage_native_Windows_Storage_FileIO::WriteText___STATIC__VOID__WindowsStorageIStorageFile__STRING, + Library_win_storage_native_Windows_Storage_FileIO::ReadBufferNative___STATIC__VOID__WindowsStorageIStorageFile__BYREF_SZARRAY_U1, + Library_win_storage_native_Windows_Storage_FileIO::ReadTextNative___STATIC__VOID__WindowsStorageIStorageFile__BYREF_STRING, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_storage_native_Windows_Storage_StorageFile::DeleteFileNative___VOID, + Library_win_storage_native_Windows_Storage_StorageFile::RenameFileNative___VOID__STRING, + NULL, + NULL, + Library_win_storage_native_Windows_Storage_StorageFile::GetFileFromPathNative___STATIC__WindowsStorageStorageFile__STRING__STRING, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_storage_native_Windows_Storage_StorageFolder::GetRemovableStorageFoldersNative___SZARRAY_WindowsStorageStorageFolder, + Library_win_storage_native_Windows_Storage_StorageFolder::GetInternalStorageFoldersNative___SZARRAY_WindowsStorageStorageFolder, + Library_win_storage_native_Windows_Storage_StorageFolder::GetStorageFoldersNative___SZARRAY_WindowsStorageStorageFolder, + Library_win_storage_native_Windows_Storage_StorageFolder::GetStorageFilesNative___SZARRAY_WindowsStorageStorageFile__U4__U4, + Library_win_storage_native_Windows_Storage_StorageFolder::CreateFileNative___WindowsStorageStorageFile__STRING__U4, + Library_win_storage_native_Windows_Storage_StorageFolder::CreateFolderNative___WindowsStorageStorageFolder__STRING__U4, + Library_win_storage_native_Windows_Storage_StorageFolder::DeleteFolderNative___VOID, + Library_win_storage_native_Windows_Storage_StorageFolder::RenameFolderNative___VOID__STRING, + Library_win_storage_native_Windows_Storage_StorageFolder::GetFolderNative___WindowsStorageStorageFolder__STRING, + NULL, + NULL, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Storage = +{ + "Windows.Storage", + 0x8D8C8026, + method_lookup, + { 100, 0, 1, 0 } +}; diff --git a/source/native/nf-interpreter/src/Windows.Storage/win_storage_native.h b/source/native/nf-interpreter/src/Windows.Storage/win_storage_native.h new file mode 100644 index 00000000..d6cf2f74 --- /dev/null +++ b/source/native/nf-interpreter/src/Windows.Storage/win_storage_native.h @@ -0,0 +1,114 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#ifndef _WIN_STORAGE_NATIVE_H_ +#define _WIN_STORAGE_NATIVE_H_ + +#include +#include + +struct Library_win_storage_native_Windows_Storage_RemovableDeviceEventArgs +{ + static const int FIELD___path = 1; + static const int FIELD___event = 2; + + + //--// + +}; + +struct Library_win_storage_native_Windows_Storage_StorageEventManager +{ + static const int FIELD_STATIC__RemovableDeviceInserted = 0; + static const int FIELD_STATIC__RemovableDeviceRemoved = 1; + + + //--// + +}; + +struct Library_win_storage_native_Windows_Storage_StorageEventManager__StorageEvent +{ + static const int FIELD__EventType = 3; + static const int FIELD__DriveIndex = 4; + static const int FIELD__Time = 5; + + + //--// + +}; + +struct Library_win_storage_native_Windows_Storage_Devices_SDCard +{ + static const int FIELD_STATIC___mounted = 2; + + NANOCLR_NATIVE_DECLARE(MountMMCNative___STATIC__VOID__BOOLEAN); + NANOCLR_NATIVE_DECLARE(MountSpiNative___STATIC__VOID__I4__I4); + NANOCLR_NATIVE_DECLARE(UnmountNative___STATIC__VOID); + + //--// + +}; + +struct Library_win_storage_native_Windows_Storage_FileIO +{ + NANOCLR_NATIVE_DECLARE(WriteBytes___STATIC__VOID__WindowsStorageIStorageFile__SZARRAY_U1); + NANOCLR_NATIVE_DECLARE(WriteText___STATIC__VOID__WindowsStorageIStorageFile__STRING); + NANOCLR_NATIVE_DECLARE(ReadBufferNative___STATIC__VOID__WindowsStorageIStorageFile__BYREF_SZARRAY_U1); + NANOCLR_NATIVE_DECLARE(ReadTextNative___STATIC__VOID__WindowsStorageIStorageFile__BYREF_STRING); + + //--// + +}; + +struct Library_win_storage_native_Windows_Storage_StorageFile +{ + static const int FIELD___dateCreated = 1; + static const int FIELD___name = 2; + static const int FIELD___path = 3; + + NANOCLR_NATIVE_DECLARE(DeleteFileNative___VOID); + NANOCLR_NATIVE_DECLARE(RenameFileNative___VOID__STRING); + NANOCLR_NATIVE_DECLARE(GetFileFromPathNative___STATIC__WindowsStorageStorageFile__STRING__STRING); + + //--// + +}; + +struct Library_win_storage_native_Windows_Storage_StorageFolder +{ + static const int FIELD___knownFolderId = 1; + static const int FIELD___dateCreated = 2; + static const int FIELD___name = 3; + static const int FIELD___path = 4; + + NANOCLR_NATIVE_DECLARE(GetRemovableStorageFoldersNative___SZARRAY_WindowsStorageStorageFolder); + NANOCLR_NATIVE_DECLARE(GetInternalStorageFoldersNative___SZARRAY_WindowsStorageStorageFolder); + NANOCLR_NATIVE_DECLARE(GetStorageFoldersNative___SZARRAY_WindowsStorageStorageFolder); + NANOCLR_NATIVE_DECLARE(GetStorageFilesNative___SZARRAY_WindowsStorageStorageFile__U4__U4); + NANOCLR_NATIVE_DECLARE(CreateFileNative___WindowsStorageStorageFile__STRING__U4); + NANOCLR_NATIVE_DECLARE(CreateFolderNative___WindowsStorageStorageFolder__STRING__U4); + NANOCLR_NATIVE_DECLARE(DeleteFolderNative___VOID); + NANOCLR_NATIVE_DECLARE(RenameFolderNative___VOID__STRING); + NANOCLR_NATIVE_DECLARE(GetFolderNative___WindowsStorageStorageFolder__STRING); + + //--// + +}; + +struct Library_win_storage_native_Windows_Storage_StorageProvider +{ + static const int FIELD___displayName = 1; + static const int FIELD___id = 2; + + + //--// + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Storage; + +#endif //_WIN_STORAGE_NATIVE_H_ diff --git a/source/native/nf-interpreter/src/nanoFramework.Devices.Can/nf_devices_can_native.cpp b/source/native/nf-interpreter/src/nanoFramework.Devices.Can/nf_devices_can_native.cpp new file mode 100644 index 00000000..c0a668af --- /dev/null +++ b/source/native/nf-interpreter/src/nanoFramework.Devices.Can/nf_devices_can_native.cpp @@ -0,0 +1,70 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "nf_devices_can_native.h" + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController::WriteMessage___VOID__nanoFrameworkDevicesCanCanMessage, + NULL, + NULL, + NULL, + NULL, + Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController::GetMessage___nanoFrameworkDevicesCanCanMessage, + Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController::DisposeNative___VOID, + Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController::NativeInit___VOID, + Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController::NativeUpdateCallbacks___VOID, + NULL, + NULL, + Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController::GetDeviceSelector___STATIC__STRING, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Devices_Can = +{ + "nanoFramework.Devices.Can", + 0xC90BF0BB, + method_lookup, + { 100, 0, 4, 0 } +}; diff --git a/source/native/nf-interpreter/src/nanoFramework.Devices.Can/nf_devices_can_native.h b/source/native/nf-interpreter/src/nanoFramework.Devices.Can/nf_devices_can_native.h new file mode 100644 index 00000000..02416df9 --- /dev/null +++ b/source/native/nf-interpreter/src/nanoFramework.Devices.Can/nf_devices_can_native.h @@ -0,0 +1,124 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#ifndef _NF_DEVICES_CAN_NATIVE_H_ +#define _NF_DEVICES_CAN_NATIVE_H_ + +#include +#include + +//////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH nanoFramework.Devices.Can.CanEvent (in managed code) !!! // +//////////////////////////////////////////////////////////////////////////////////// + +enum CanEvent +{ + CanEvent_MessageReceived = 0, + CanEvent_ErrorOccurred, +}; + +//////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH nanoFramework.Devices.Can.CanMessageIdType (in managed code) !!! // +//////////////////////////////////////////////////////////////////////////////////////////// + +enum CanMessageIdType +{ + CanMessageIdType_SID = 0, + CanMessageIdType_EID, +}; + +/////////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH nanoFramework.Devices.Can.CanMessageFrameType (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////////////// + +enum CanMessageFrameType +{ + CanMessageFrameType_Data = 0, + CanMessageFrameType_RemoteRequest, +}; + +/////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////// + +struct Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController +{ + static const int FIELD_STATIC__s_eventListener = 0; + + static const int FIELD___disposed = 1; + static const int FIELD___callbacks = 2; + static const int FIELD___syncLock = 3; + static const int FIELD___controllerId = 4; + static const int FIELD___settings = 5; + static const int FIELD___message = 6; + static const int FIELD__ControllerId = 7; + + NANOCLR_NATIVE_DECLARE(WriteMessage___VOID__nanoFrameworkDevicesCanCanMessage); + NANOCLR_NATIVE_DECLARE(GetMessage___nanoFrameworkDevicesCanCanMessage); + NANOCLR_NATIVE_DECLARE(DisposeNative___VOID); + NANOCLR_NATIVE_DECLARE(NativeInit___VOID); + NANOCLR_NATIVE_DECLARE(NativeUpdateCallbacks___VOID); + NANOCLR_NATIVE_DECLARE(GetDeviceSelector___STATIC__STRING); + + //--// + +}; + +struct Library_nf_devices_can_native_nanoFramework_Devices_Can_CanControllerEventListener +{ + static const int FIELD___canControllersMap = 1; + + + //--// + +}; + +struct Library_nf_devices_can_native_nanoFramework_Devices_Can_CanControllerManager +{ + static const int FIELD_STATIC___syncLock = 1; + static const int FIELD_STATIC__s_controllersCollection = 2; + + + //--// + +}; + +struct Library_nf_devices_can_native_nanoFramework_Devices_Can_CanMessage +{ + static const int FIELD___id = 1; + static const int FIELD___identifierType = 2; + static const int FIELD___frameType = 3; + static const int FIELD___message = 4; + + + //--// + +}; + +struct Library_nf_devices_can_native_nanoFramework_Devices_Can_CanMessageEvent +{ + static const int FIELD__ControllerIndex = 3; + static const int FIELD__Event = 4; + + + //--// + +}; + +struct Library_nf_devices_can_native_nanoFramework_Devices_Can_CanSettings +{ + static const int FIELD___baudRatePrescaler = 1; + static const int FIELD___phaseSegment1 = 2; + static const int FIELD___phaseSegment2 = 3; + static const int FIELD___syncJumpWidth = 4; + + + //--// + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Devices_Can; + +#endif //_NF_DEVICES_CAN_NATIVE_H_ diff --git a/source/native/nf-interpreter/src/nanoFramework.Devices.OneWire/nf_devices_onewire_native.cpp b/source/native/nf-interpreter/src/nanoFramework.Devices.OneWire/nf_devices_onewire_native.cpp new file mode 100644 index 00000000..88998b46 --- /dev/null +++ b/source/native/nf-interpreter/src/nanoFramework.Devices.OneWire/nf_devices_onewire_native.cpp @@ -0,0 +1,29 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "nf_devices_onewire_native.h" + +static const CLR_RT_MethodHandler method_lookup[] = +{ + Library_nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController::TouchReset___BOOLEAN, + Library_nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController::TouchBit___BOOLEAN__BOOLEAN, + Library_nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController::TouchByte___U1__U1, + Library_nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController::WriteByte___U1__U1, + Library_nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController::ReadByte___U1, + Library_nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController::FindFirstDevice___BOOLEAN__BOOLEAN__BOOLEAN, + Library_nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController::FindNextDevice___BOOLEAN__BOOLEAN__BOOLEAN, + NULL, + NULL, + NULL, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Devices_OneWire = +{ + "nanoFramework.Devices.OneWire", + 0xC7BEAEBC, + method_lookup, + { 100, 0, 3, 3 } +}; diff --git a/source/native/nf-interpreter/src/nanoFramework.Devices.OneWire/nf_devices_onewire_native.h b/source/native/nf-interpreter/src/nanoFramework.Devices.OneWire/nf_devices_onewire_native.h new file mode 100644 index 00000000..176f4681 --- /dev/null +++ b/source/native/nf-interpreter/src/nanoFramework.Devices.OneWire/nf_devices_onewire_native.h @@ -0,0 +1,32 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _NF_DEVICES_ONEWIRE_NATIVE_H_ +#define _NF_DEVICES_ONEWIRE_NATIVE_H_ + +#include +#include +#include + +struct Library_nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController +{ + static const int FIELD___syncLock = 1; + static const int FIELD___serialNumber = 2; + + NANOCLR_NATIVE_DECLARE(TouchReset___BOOLEAN); + NANOCLR_NATIVE_DECLARE(TouchBit___BOOLEAN__BOOLEAN); + NANOCLR_NATIVE_DECLARE(TouchByte___U1__U1); + NANOCLR_NATIVE_DECLARE(WriteByte___U1__U1); + NANOCLR_NATIVE_DECLARE(ReadByte___U1); + NANOCLR_NATIVE_DECLARE(FindFirstDevice___BOOLEAN__BOOLEAN__BOOLEAN); + NANOCLR_NATIVE_DECLARE(FindNextDevice___BOOLEAN__BOOLEAN__BOOLEAN); + + //--// + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Devices_OneWire; + +#endif //_NF_DEVICES_ONEWIRE_NATIVE_H_ diff --git a/source/native/nf-interpreter/src/nanoFramework.ResourceManager/nf_system_resourcemanager.cpp b/source/native/nf-interpreter/src/nanoFramework.ResourceManager/nf_system_resourcemanager.cpp new file mode 100644 index 00000000..142ed51a --- /dev/null +++ b/source/native/nf-interpreter/src/nanoFramework.ResourceManager/nf_system_resourcemanager.cpp @@ -0,0 +1,40 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "nf_system_resourcemanager.h" + + +static const CLR_RT_MethodHandler method_lookup[] = +{ + Library_nf_system_resourcemanager_System_Resources_ResourceManager::GetObjectInternal___OBJECT__I2, + Library_nf_system_resourcemanager_System_Resources_ResourceManager::GetObjectInternal___OBJECT__I2__I4__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_nf_system_resourcemanager_System_Resources_ResourceManager::FindResource___STATIC__I4__STRING__mscorlibSystemReflectionAssembly, + Library_nf_system_resourcemanager_System_Resources_ResourceManager::GetObject___STATIC__OBJECT__SystemResourcesResourceManager__mscorlibSystemEnum, + Library_nf_system_resourcemanager_nanoFramework_Runtime_Native_ResourceUtility::GetObject___STATIC__OBJECT__SystemResourcesResourceManager__mscorlibSystemEnum, + Library_nf_system_resourcemanager_nanoFramework_Runtime_Native_ResourceUtility::GetObject___STATIC__OBJECT__SystemResourcesResourceManager__mscorlibSystemEnum__I4__I4, + NULL, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_ResourceManager = +{ + "nanoFramework.ResourceManager", + 0xCDF9E76C, + method_lookup, + //////////////////////////////////////////////////////////////////////////////////// + // check if the version bellow matches the one in AssemblyNativeVersion attribute // + //////////////////////////////////////////////////////////////////////////////////// + { 100, 0, 0, 0 } +}; diff --git a/source/native/nf-interpreter/src/nanoFramework.ResourceManager/nf_system_resourcemanager.h b/source/native/nf-interpreter/src/nanoFramework.ResourceManager/nf_system_resourcemanager.h new file mode 100644 index 00000000..0ceee94d --- /dev/null +++ b/source/native/nf-interpreter/src/nanoFramework.ResourceManager/nf_system_resourcemanager.h @@ -0,0 +1,47 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _NF_SYSTEM_RESOURCEMANAGER_H_ +#define _NF_SYSTEM_RESOURCEMANAGER_H_ + +#include +#include +#include + +struct Library_nf_system_resourcemanager_System_Resources_ResourceManager +{ + static const int FIELD___resourceFileId = 1; + static const int FIELD___assembly = 2; + static const int FIELD___baseAssembly = 3; + static const int FIELD___baseName = 4; + static const int FIELD___cultureName = 5; + static const int FIELD___rmFallback = 6; + + NANOCLR_NATIVE_DECLARE(GetObjectInternal___OBJECT__I2); + NANOCLR_NATIVE_DECLARE(GetObjectInternal___OBJECT__I2__I4__I4); + NANOCLR_NATIVE_DECLARE(FindResource___STATIC__I4__STRING__mscorlibSystemReflectionAssembly); + NANOCLR_NATIVE_DECLARE(GetObject___STATIC__OBJECT__SystemResourcesResourceManager__mscorlibSystemEnum); + + //--// + + NANOCLR_NATIVE_DECLARE(GetObject___STATIC__OBJECT__SystemResourcesResourceManager__mscorlibSystemEnum__I4__I4); + +}; + +struct Library_nf_system_resourcemanager_nanoFramework_Runtime_Native_ResourceUtility +{ + NANOCLR_NATIVE_DECLARE(GetObject___STATIC__OBJECT__SystemResourcesResourceManager__mscorlibSystemEnum); + NANOCLR_NATIVE_DECLARE(GetObject___STATIC__OBJECT__SystemResourcesResourceManager__mscorlibSystemEnum__I4__I4); + + //--// + +}; + + + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_ResourceManager; + +#endif //_NF_SYSTEM_RESOURCEMANAGER_H_ diff --git a/source/native/nf-interpreter/src/nanoFramework.ResourceManager/nf_system_resourcemanager_System_Resources_ResourceManager.cpp b/source/native/nf-interpreter/src/nanoFramework.ResourceManager/nf_system_resourcemanager_System_Resources_ResourceManager.cpp new file mode 100644 index 00000000..be7e5d15 --- /dev/null +++ b/source/native/nf-interpreter/src/nanoFramework.ResourceManager/nf_system_resourcemanager_System_Resources_ResourceManager.cpp @@ -0,0 +1,218 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "nf_system_resourcemanager.h" + + +HRESULT Library_nf_system_resourcemanager_System_Resources_ResourceManager::GetObjectInternal___OBJECT__I2( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_Assembly_Instance assm; + CLR_UINT32 size; + const CLR_RECORD_RESOURCE* resource; + CLR_RT_Assembly* pAssm; + const CLR_UINT8* buf; + CLR_RT_HeapBlock* pThis = stack.This(); + CLR_RT_HeapBlock* pArgs = &(stack.Arg1()); + CLR_UINT32 resourceFileId = pThis[ FIELD___resourceFileId ].NumericByRefConst().s4; + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + + // + // Set up for restart on out of memory. + // + if(stack.m_customState == 0) + { + stack.m_customState = 1; + stack.m_flags |= CLR_RT_StackFrame::c_CompactAndRestartOnOutOfMemory; + } + + NANOCLR_CHECK_HRESULT(Library_corlib_native_System_Reflection_Assembly::GetTypeDescriptor( *pThis[ FIELD___assembly ].Dereference(), assm )); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_TypeSystem.LocateResource( assm, resourceFileId, pArgs[ 0 ].NumericByRefConst().s2, resource, size )); + + if(resource != NULL) //otherwise NULL is returned + { + pAssm = assm.m_assm; + buf = pAssm->GetResourceData( resource->offset ); + + switch(resource->kind) + { + case CLR_RECORD_RESOURCE::RESOURCE_String: + { + NANOCLR_SET_AND_LEAVE(CLR_RT_HeapBlock_String::CreateInstance( top, (const char*)buf, pAssm )); + } + break; + + case CLR_RECORD_RESOURCE::RESOURCE_Binary: + { + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( top, size, g_CLR_RT_WellKnownTypes.m_UInt8 )); + + memcpy( top.DereferenceArray()->GetFirstElement(), buf, size ); + } + break; + + default: + _ASSERTE(false); + break; + } + } + + NANOCLR_NOCLEANUP(); +} + + +HRESULT Library_nf_system_resourcemanager_System_Resources_ResourceManager::GetObjectInternal___OBJECT__I2__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_Assembly_Instance assm; + CLR_UINT32 size; + const CLR_RECORD_RESOURCE* resource; + CLR_RT_Assembly* pAssm; + const CLR_UINT8* buf; + CLR_RT_HeapBlock* pThis = stack.This(); + CLR_RT_HeapBlock* pArgs = &(stack.Arg1()); + CLR_UINT32 resourceFileId = pThis[ FIELD___resourceFileId ].NumericByRefConst().s4; + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + CLR_UINT32 offset = pArgs[ 1 ].NumericByRef().s4; + CLR_UINT32 length = pArgs[ 2 ].NumericByRef().s4; + + // + // Set up for restart on out of memory. + // + if(stack.m_customState == 0) + { + stack.m_customState = 1; + stack.m_flags |= CLR_RT_StackFrame::c_CompactAndRestartOnOutOfMemory; + } + + NANOCLR_CHECK_HRESULT(Library_corlib_native_System_Reflection_Assembly::GetTypeDescriptor( *pThis[FIELD___assembly].Dereference(), assm )); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_TypeSystem.LocateResource( assm, resourceFileId, pArgs[ 0 ].NumericByRefConst().s2, resource, size )); + + + if(resource != NULL) //otherwise NULL is returned + { + pAssm = assm.m_assm; + buf = pAssm->GetResourceData( resource->offset ); + + switch(resource->kind) + { + // + // Chunked access is only possible for binary resources + // + case CLR_RECORD_RESOURCE::RESOURCE_String: + case CLR_RECORD_RESOURCE::RESOURCE_Bitmap: + case CLR_RECORD_RESOURCE::RESOURCE_Font: + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + } + break; + case CLR_RECORD_RESOURCE::RESOURCE_Binary: + { + // throw out-of-range when offset is too large... + if(offset >= size) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INDEX_OUT_OF_RANGE); + } + // ... but trim length if necessary + else + { + if(offset + length >= size) + { + length = size - offset; + } + } + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( top, length, g_CLR_RT_WellKnownTypes.m_UInt8 )); + + memcpy( top.DereferenceArray()->GetFirstElement() , buf + offset, length ); + } + break; + + default: + _ASSERTE(false); + break; + } + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_system_resourcemanager_System_Resources_ResourceManager::FindResource___STATIC__I4__STRING__mscorlibSystemReflectionAssembly( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_Assembly_Instance assm; + CLR_INT32 resourceFileId; + CLR_RT_HeapBlock* pArgs = &stack.Arg0(); + + const char* szText = pArgs[ 0 ].RecoverString(); FAULT_ON_NULL(szText); + + NANOCLR_CHECK_HRESULT(Library_corlib_native_System_Reflection_Assembly::GetTypeDescriptor( *pArgs[ 1 ].Dereference(), assm )); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_TypeSystem.LocateResourceFile( assm, szText, resourceFileId )); + + stack.SetResult_I4( resourceFileId ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_system_resourcemanager_System_Resources_ResourceManager::GetObject___STATIC__OBJECT__SystemResourcesResourceManager__mscorlibSystemEnum( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock& blkResourceManager = stack.Arg0(); + CLR_RT_HeapBlock& blkEnumObj = stack.Arg1(); + CLR_RT_HeapBlock* blkVT = blkEnumObj.Dereference(); + CLR_RT_HeapBlock* blkEnum = blkVT + 1; + CLR_RT_MethodDef_Instance md; + + if(stack.m_customState == 0) + { + stack.m_customState = 1; + + FAULT_ON_NULL(blkVT); + + if(blkEnum->DataType() != DATATYPE_I2 && blkEnum->DataType() != DATATYPE_U2) NANOCLR_SET_AND_LEAVE( CLR_E_INVALID_PARAMETER ); + + //call back into ResourceManager.GetObjectFromId(short id); + + _SIDE_ASSERTE(md.InitializeFromIndex( g_CLR_RT_WellKnownMethods.m_ResourceManager_GetObjectFromId )); + + NANOCLR_CHECK_HRESULT( stack.MakeCall( md, &blkResourceManager, blkEnum, 1 )); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_system_resourcemanager_System_Resources_ResourceManager::GetObject___STATIC__OBJECT__SystemResourcesResourceManager__mscorlibSystemEnum__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock& blkResourceManager = stack.Arg0(); + CLR_RT_MethodDef_Instance md; + + if(stack.m_customState == 0) + { + stack.m_customState = 1; + + //call back into ResourceManager.GetObjectFromId(short id, int offset, int length); + + _SIDE_ASSERTE(md.InitializeFromIndex( g_CLR_RT_WellKnownMethods.m_ResourceManager_GetObjectChunkFromId )); + + NANOCLR_CHECK_HRESULT( stack.MakeCall( md, &blkResourceManager, &stack.Arg1(), 3 )); + } + + NANOCLR_NOCLEANUP(); +} + diff --git a/source/native/nf-interpreter/src/nanoFramework.ResourceManager/nf_system_resourcemanager_nanoFramework_Runtime_Native_ResourceUtility.cpp b/source/native/nf-interpreter/src/nanoFramework.ResourceManager/nf_system_resourcemanager_nanoFramework_Runtime_Native_ResourceUtility.cpp new file mode 100644 index 00000000..274f98b6 --- /dev/null +++ b/source/native/nf-interpreter/src/nanoFramework.ResourceManager/nf_system_resourcemanager_nanoFramework_Runtime_Native_ResourceUtility.cpp @@ -0,0 +1,20 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "nf_system_resourcemanager.h" + + +HRESULT Library_nf_system_resourcemanager_nanoFramework_Runtime_Native_ResourceUtility::GetObject___STATIC__OBJECT__SystemResourcesResourceManager__mscorlibSystemEnum( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + return Library_nf_system_resourcemanager_System_Resources_ResourceManager::GetObject___STATIC__OBJECT__SystemResourcesResourceManager__mscorlibSystemEnum( stack ); +} + +HRESULT Library_nf_system_resourcemanager_nanoFramework_Runtime_Native_ResourceUtility::GetObject___STATIC__OBJECT__SystemResourcesResourceManager__mscorlibSystemEnum__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + return Library_nf_system_resourcemanager_System_Resources_ResourceManager::GetObject___STATIC__OBJECT__SystemResourcesResourceManager__mscorlibSystemEnum__I4__I4( stack ); +} diff --git a/source/native/nf-interpreter/src/nanoFramework.Runtime.Events/nf_rt_events_native.cpp b/source/native/nf-interpreter/src/nanoFramework.Runtime.Events/nf_rt_events_native.cpp new file mode 100644 index 00000000..a1dbaf84 --- /dev/null +++ b/source/native/nf-interpreter/src/nanoFramework.Runtime.Events/nf_rt_events_native.cpp @@ -0,0 +1,75 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#include "nf_rt_events_native.h" + + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher::EnableInterrupt___VOID, + Library_nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher::DisableInterrupt___VOID, + Library_nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher::Dispose___VOID__BOOLEAN, + NULL, + NULL, + Library_nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher::_ctor___VOID__STRING__U8, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_nf_rt_events_native_nanoFramework_Runtime_Events_EventSink::EventConfig___VOID, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_nf_rt_events_native_nanoFramework_Runtime_Events_WeakDelegate::Combine___STATIC__mscorlibSystemDelegate__mscorlibSystemDelegate__mscorlibSystemDelegate, + Library_nf_rt_events_native_nanoFramework_Runtime_Events_WeakDelegate::Remove___STATIC__mscorlibSystemDelegate__mscorlibSystemDelegate__mscorlibSystemDelegate, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Runtime_Events = +{ + "nanoFramework.Runtime.Events", + 0x7B4AC2F2, + method_lookup, + { 100, 0, 7, 0 } +}; diff --git a/source/native/nf-interpreter/src/nanoFramework.Runtime.Events/nf_rt_events_native.h b/source/native/nf-interpreter/src/nanoFramework.Runtime.Events/nf_rt_events_native.h new file mode 100644 index 00000000..30a1049f --- /dev/null +++ b/source/native/nf-interpreter/src/nanoFramework.Runtime.Events/nf_rt_events_native.h @@ -0,0 +1,131 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#ifndef _NF_RT_EVENTS_NATIVE_H_ +#define _NF_RT_EVENTS_NATIVE_H_ + + +#include +#include +#include + + +struct Library_nf_rt_events_native_nanoFramework_Runtime_Events_CustomEvent +{ + static const int FIELD_STATIC__CustomEventPosted = 0; + + + //--// + +}; + +struct Library_nf_rt_events_native_nanoFramework_Runtime_Events_BaseEvent +{ + static const int FIELD__Source = 1; + static const int FIELD__Message = 2; + + + //--// + +}; + +struct Library_nf_rt_events_native_nanoFramework_Runtime_Events_CustomEvent__CustomEventInternal +{ + static const int FIELD__Data1 = 3; + static const int FIELD__Data2 = 4; + static const int FIELD__Time = 5; + + + //--// + +}; + +struct Library_nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher +{ + static const int FIELD__threadSpawn = 1; + static const int FIELD__callbacks = 2; + static const int FIELD__disposed = 3; + static const int FIELD___NativeEventDispatcher = 4; + + NANOCLR_NATIVE_DECLARE(EnableInterrupt___VOID); + NANOCLR_NATIVE_DECLARE(DisableInterrupt___VOID); + NANOCLR_NATIVE_DECLARE(Dispose___VOID__BOOLEAN); + NANOCLR_NATIVE_DECLARE(_ctor___VOID__STRING__U8); + + //--// + static CLR_RT_ObjectToEvent_Source* GetEventDispReference( CLR_RT_StackFrame& stack ); + static HRESULT GetEventDispatcher ( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock_NativeEventDispatcher*& event ); + static CLR_RT_HeapBlock_NativeEventDispatcher* GetEventDispatcher ( CLR_RT_StackFrame& stack ); +}; + +struct Library_nf_rt_events_native_nanoFramework_Runtime_Events_EventSink +{ + static const int FIELD_STATIC__s_eventSink = 1; + static const int FIELD_STATIC__s_eventInfoTable = 2; + + NANOCLR_NATIVE_DECLARE(EventConfig___VOID); + + //--// + +}; + +struct Library_nf_rt_events_native_nanoFramework_Runtime_Events_EventSink__EventInfo +{ + static const int FIELD__EventListener = 1; + static const int FIELD__EventFilter = 2; + static const int FIELD__EventProcessor = 3; + static const int FIELD__Category = 4; + + + //--// + +}; + +struct Library_nf_rt_events_native_nanoFramework_Runtime_Events_EventArgs +{ + static const int FIELD_STATIC__Empty = 3; + + + //--// + +}; + +struct Library_nf_rt_events_native_nanoFramework_Runtime_Events_CustomEventArgs +{ + static const int FIELD___data1 = 1; + static const int FIELD___data2 = 2; + + + //--// + +}; + +struct Library_nf_rt_events_native_nanoFramework_Runtime_Events_GenericEvent +{ + static const int FIELD__Category = 3; + static const int FIELD__Data = 4; + static const int FIELD__Time = 5; + + + //--// + +}; + +struct Library_nf_rt_events_native_nanoFramework_Runtime_Events_WeakDelegate +{ + NANOCLR_NATIVE_DECLARE(Combine___STATIC__mscorlibSystemDelegate__mscorlibSystemDelegate__mscorlibSystemDelegate); + NANOCLR_NATIVE_DECLARE(Remove___STATIC__mscorlibSystemDelegate__mscorlibSystemDelegate__mscorlibSystemDelegate); + + //--// + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Runtime_Events_EventSink_DriverProcs; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Runtime_Events; + +#endif //_NF_RT_EVENTS_NATIVE_H_ diff --git a/source/native/nf-interpreter/src/nanoFramework.Runtime.Events/nf_rt_events_native_nanoFramework_Runtime_Events_EventSink.cpp b/source/native/nf-interpreter/src/nanoFramework.Runtime.Events/nf_rt_events_native_nanoFramework_Runtime_Events_EventSink.cpp new file mode 100644 index 00000000..05593f92 --- /dev/null +++ b/source/native/nf-interpreter/src/nanoFramework.Runtime.Events/nf_rt_events_native_nanoFramework_Runtime_Events_EventSink.cpp @@ -0,0 +1,69 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "nf_rt_events_native.h" + +static CLR_RT_HeapBlock_NativeEventDispatcher *g_Context = NULL; + +void PostManagedEvent(uint8_t category, uint8_t subCategory, uint16_t data1, uint32_t data2) +{ + if(g_Context != NULL) + { + uint32_t d = ((uint32_t)data1 << 16) | (category << 8) | subCategory; + + SaveNativeEventToHALQueue( g_Context, d, data2 ); + } +} + +static HRESULT InitializeEventSink( CLR_RT_HeapBlock_NativeEventDispatcher *pContext, uint64_t userData ) +{ + (void)userData; + + g_Context = pContext; + + return S_OK; +} + +static HRESULT EnableDisableEventSink( CLR_RT_HeapBlock_NativeEventDispatcher *pContext, bool fEnable ) +{ + (void)pContext; + (void)fEnable; + + return S_OK; +} + +static HRESULT CleanupEventSink( CLR_RT_HeapBlock_NativeEventDispatcher *pContext ) +{ + (void)pContext; + + g_Context = NULL; + + CleanupNativeEventsFromHALQueue( pContext ); + + return S_OK; +} + +HRESULT Library_nf_rt_events_native_nanoFramework_Runtime_Events_EventSink::EventConfig___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + return S_OK; +} + +static const CLR_RT_DriverInterruptMethods g_CLR_AssemblyNative_nanoFramework_Runtime_Events_EventSink = +{ + InitializeEventSink, + EnableDisableEventSink, + CleanupEventSink +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Runtime_Events_EventSink_DriverProcs = +{ + "EventSink", + DRIVER_INTERRUPT_METHODS_CHECKSUM, + &g_CLR_AssemblyNative_nanoFramework_Runtime_Events_EventSink, + { 1, 0, 0, 0 } +}; diff --git a/source/native/nf-interpreter/src/nanoFramework.Runtime.Events/nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher.cpp b/source/native/nf-interpreter/src/nanoFramework.Runtime.Events/nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher.cpp new file mode 100644 index 00000000..9dd7d315 --- /dev/null +++ b/source/native/nf-interpreter/src/nanoFramework.Runtime.Events/nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher.cpp @@ -0,0 +1,183 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#include "nf_rt_events_native.h" + + +HRESULT Library_nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher::EnableInterrupt___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_NativeEventDispatcher *pNativeDisp = NULL; + + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + if(pThis[ FIELD__disposed ].NumericByRef().s1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + NANOCLR_CHECK_HRESULT(GetEventDispatcher( stack, pNativeDisp )); + + // Calls driver to enable interrupts. Consider that there could be no driver + // associated to this object so check that the driver methods are set + if(pNativeDisp->driverMethods == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + } + + NANOCLR_CHECK_HRESULT(pNativeDisp->driverMethods->enableProcessor( pNativeDisp, true )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher::DisableInterrupt___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_NativeEventDispatcher *pNativeDisp = NULL; + + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + if(pThis[ FIELD__disposed ].NumericByRef().s1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + NANOCLR_CHECK_HRESULT(GetEventDispatcher( stack, pNativeDisp )); + + // Calls driver to enable interrupts. Consider that there could be no driver + // associated to this object so check that the driver methods are set + // we will be tolerant in this case and not throw any exception + if(pNativeDisp->driverMethods != NULL) + { + NANOCLR_CHECK_HRESULT(pNativeDisp->driverMethods->enableProcessor( pNativeDisp, false )); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher::Dispose___VOID__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_NativeEventDispatcher *pNativeDisp = NULL; + + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + NANOCLR_CHECK_HRESULT(GetEventDispatcher( stack, pNativeDisp )); + + // Cleanup the HAL queue from the instance of associated CLR_RT_HeapBlock_NativeEventDispatcher + pNativeDisp->RemoveFromHALQueue(); + + // Calls driver to enable interrupts. Consider that there could be no driver + // associated to this object so check that the driver methods are set + // we will be tolerant in this case and not throw any exception + if(pNativeDisp->driverMethods != NULL) + { + NANOCLR_CHECK_HRESULT(pNativeDisp->driverMethods->cleanupProcessor( pNativeDisp )); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher::_ctor___VOID__STRING__U8( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_DriverInterruptMethods* pDriverMethods; + const CLR_RT_NativeAssemblyData* pNativeDriverData; + CLR_RT_HeapBlock_NativeEventDispatcher* pNativeDisp = NULL; + + const char * driverName; + uint64_t driverData; + + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Retrieve paramenters; + if (stack.Arg1().DataType() != DATATYPE_OBJECT) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + driverName = stack.Arg1().RecoverString(); FAULT_ON_NULL(driverName); + driverData = stack.Arg2().NumericByRef().u8; + + // Throw NULL exception if string is empty. + if(hal_strlen_s( driverName ) == 0) + { + NANOCLR_CHECK_HRESULT(CLR_E_ARGUMENT_NULL); + } + + // Retrives pointers to driver implemented functions. + pNativeDriverData = GetAssemblyNativeData( driverName ); + + // Validates check sum and presence of the structure. + if(pNativeDriverData == NULL || pNativeDriverData->m_checkSum != DRIVER_INTERRUPT_METHODS_CHECKSUM) + { + NANOCLR_CHECK_HRESULT(CLR_E_DRIVER_NOT_REGISTERED); + } + + // Get pointer to CLR_RT_DriverInterruptMethods + pDriverMethods = (CLR_RT_DriverInterruptMethods *)pNativeDriverData->m_pNativeMethods; + + // Check that all methods are present: + if( pDriverMethods->initProcessor == NULL || + pDriverMethods->enableProcessor == NULL || + pDriverMethods->cleanupProcessor == NULL) + { + NANOCLR_CHECK_HRESULT(CLR_E_DRIVER_NOT_REGISTERED); + } + + // So we found driver by name and now we create instance of CLR_RT_HeapBlock_NativeEventDispatcher + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_NativeEventDispatcher::CreateInstance( *pThis, pThis[ FIELD___NativeEventDispatcher ] )); + + // Initialize the driver with and provide the instance of CLR_RT_HeapBlock_NativeEventDispatcher + NANOCLR_CHECK_HRESULT(GetEventDispatcher( stack, pNativeDisp )); + + // Now call the driver. First save pointer to driver data. + pNativeDisp->driverMethods = pDriverMethods; + + NANOCLR_CHECK_HRESULT(pDriverMethods->initProcessor( pNativeDisp, driverData )); + + NANOCLR_NOCLEANUP(); +} + +//--// + +CLR_RT_ObjectToEvent_Source* Library_nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher::GetEventDispReference( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_HARDWARE(); + + CLR_RT_HeapBlock* pThis = stack.This(); + + return CLR_RT_ObjectToEvent_Source::ExtractInstance( pThis[ FIELD___NativeEventDispatcher ] ); +} + +HRESULT Library_nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher::GetEventDispatcher( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock_NativeEventDispatcher*& event ) +{ + NATIVE_PROFILE_CLR_HARDWARE(); + + NANOCLR_HEADER(); + + event = GetEventDispatcher( stack ); + if(event == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + NANOCLR_NOCLEANUP(); +} + +CLR_RT_HeapBlock_NativeEventDispatcher* Library_nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher::GetEventDispatcher( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_HARDWARE(); + + CLR_RT_ObjectToEvent_Source* src = GetEventDispReference( stack ); + + return (src == NULL) ? NULL : (CLR_RT_HeapBlock_NativeEventDispatcher*)src->m_eventPtr; +} diff --git a/source/native/nf-interpreter/src/nanoFramework.Runtime.Events/nf_rt_events_native_nanoFramework_Runtime_Events_WeakDelegate.cpp b/source/native/nf-interpreter/src/nanoFramework.Runtime.Events/nf_rt_events_native_nanoFramework_Runtime_Events_WeakDelegate.cpp new file mode 100644 index 00000000..14c5f1a6 --- /dev/null +++ b/source/native/nf-interpreter/src/nanoFramework.Runtime.Events/nf_rt_events_native_nanoFramework_Runtime_Events_WeakDelegate.cpp @@ -0,0 +1,31 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#include "nf_rt_events_native.h" + + +HRESULT Library_nf_rt_events_native_nanoFramework_Runtime_Events_WeakDelegate::Combine___STATIC__mscorlibSystemDelegate__mscorlibSystemDelegate__mscorlibSystemDelegate( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(CLR_RT_HeapBlock_Delegate_List::Combine( stack.PushValue(), stack.Arg0(), stack.Arg1(), true )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_rt_events_native_nanoFramework_Runtime_Events_WeakDelegate::Remove___STATIC__mscorlibSystemDelegate__mscorlibSystemDelegate__mscorlibSystemDelegate( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(CLR_RT_HeapBlock_Delegate_List::Remove( stack.PushValue(), stack.Arg0(), stack.Arg1() )); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/nanoFramework.Runtime.Native/nf_rt_native.cpp b/source/native/nf-interpreter/src/nanoFramework.Runtime.Native/nf_rt_native.cpp new file mode 100644 index 00000000..6cba76c1 --- /dev/null +++ b/source/native/nf-interpreter/src/nanoFramework.Runtime.Native/nf_rt_native.cpp @@ -0,0 +1,49 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "nf_rt_native.h" + + +static const CLR_RT_MethodHandler method_lookup[] = +{ + Library_nf_rt_native_nanoFramework_Runtime_Native_SystemInfo::GetSystemVersion___STATIC__VOID__BYREF_I4__BYREF_I4__BYREF_I4__BYREF_I4, + NULL, + Library_nf_rt_native_nanoFramework_Runtime_Native_SystemInfo::get_OEMString___STATIC__STRING, + Library_nf_rt_native_nanoFramework_Runtime_Native_SystemInfo::get_OEM___STATIC__U1, + Library_nf_rt_native_nanoFramework_Runtime_Native_SystemInfo::get_Model___STATIC__U1, + Library_nf_rt_native_nanoFramework_Runtime_Native_SystemInfo::get_SKU___STATIC__U2, + Library_nf_rt_native_nanoFramework_Runtime_Native_SystemInfo::get_TargetName___STATIC__STRING, + Library_nf_rt_native_nanoFramework_Runtime_Native_SystemInfo::get_Platform___STATIC__STRING, + NULL, + Library_nf_rt_native_nanoFramework_Runtime_Native_SystemInfo::GetNativeFloatingPointSupport___STATIC__U1, + NULL, + Library_nf_rt_native_nanoFramework_Runtime_Native_Debug::GC___STATIC__U4__BOOLEAN, + Library_nf_rt_native_nanoFramework_Runtime_Native_Debug::EnableGCMessages___STATIC__VOID__BOOLEAN, + NULL, + NULL, + NULL, + Library_nf_rt_native_nanoFramework_Runtime_Native_ExecutionConstraint::Install___STATIC__VOID__I4__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_nf_rt_native_nanoFramework_Runtime_Native_Power::NativeReboot___STATIC__VOID, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_nf_rt_native_nanoFramework_Runtime_Native_Rtc::Native_RTC_SetSystemTime___STATIC__BOOLEAN__I4__U1__U1__U1__U1__U1__U1, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Runtime_Native = +{ + "nanoFramework.Runtime.Native", + 0x035EC7E8, + method_lookup, + { 100, 0, 6, 0 } +}; diff --git a/source/native/nf-interpreter/src/nanoFramework.Runtime.Native/nf_rt_native.h b/source/native/nf-interpreter/src/nanoFramework.Runtime.Native/nf_rt_native.h new file mode 100644 index 00000000..2912874b --- /dev/null +++ b/source/native/nf-interpreter/src/nanoFramework.Runtime.Native/nf_rt_native.h @@ -0,0 +1,76 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _NF_RT_NATIVE_H_ +#define _NF_RT_NATIVE_H_ + +#include +#include + + +////////////////////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH nanoFramework.Runtime.Native.SystemInfo.FloatingPoint (in managed code) !!! // +////////////////////////////////////////////////////////////////////////////////////////////////////////// + +enum FloatingPoint +{ + FloatingPoint_None = 0, + FloatingPoint_SinglePrecisionSoftware = 1, + FloatingPoint_SinglePrecisionHardware = 2, + FloatingPoint_DoublePrecisionSoftware = 3, + FloatingPoint_DoublePrecisionHardware = 4, +}; + +struct Library_nf_rt_native_nanoFramework_Runtime_Native_SystemInfo +{ + NANOCLR_NATIVE_DECLARE(GetSystemVersion___STATIC__VOID__BYREF_I4__BYREF_I4__BYREF_I4__BYREF_I4); + NANOCLR_NATIVE_DECLARE(get_OEMString___STATIC__STRING); + NANOCLR_NATIVE_DECLARE(get_OEM___STATIC__U1); + NANOCLR_NATIVE_DECLARE(get_Model___STATIC__U1); + NANOCLR_NATIVE_DECLARE(get_SKU___STATIC__U2); + NANOCLR_NATIVE_DECLARE(get_TargetName___STATIC__STRING); + NANOCLR_NATIVE_DECLARE(get_Platform___STATIC__STRING); + NANOCLR_NATIVE_DECLARE(GetNativeFloatingPointSupport___STATIC__U1); + + //--// + +}; +struct Library_nf_rt_native_nanoFramework_Runtime_Native_Debug +{ + NANOCLR_NATIVE_DECLARE(GC___STATIC__U4__BOOLEAN); + NANOCLR_NATIVE_DECLARE(EnableGCMessages___STATIC__VOID__BOOLEAN); + + //--// + +}; +struct Library_nf_rt_native_nanoFramework_Runtime_Native_ExecutionConstraint +{ + NANOCLR_NATIVE_DECLARE(Install___STATIC__VOID__I4__I4); + + //--// + +}; + +struct Library_nf_rt_native_nanoFramework_Runtime_Native_Power +{ + static const int FIELD_STATIC__OnRebootEvent = 0; + + NANOCLR_NATIVE_DECLARE(NativeReboot___STATIC__VOID); + + //--// + +}; +struct Library_nf_rt_native_nanoFramework_Runtime_Native_Rtc +{ + NANOCLR_NATIVE_DECLARE(Native_RTC_SetSystemTime___STATIC__BOOLEAN__I4__U1__U1__U1__U1__U1__U1); + + //--// + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Runtime_Native; + +#endif //_NF_RT_NATIVE_H_ diff --git a/source/native/nf-interpreter/src/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Hardware_SystemInfo.cpp b/source/native/nf-interpreter/src/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Hardware_SystemInfo.cpp new file mode 100644 index 00000000..52033233 --- /dev/null +++ b/source/native/nf-interpreter/src/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Hardware_SystemInfo.cpp @@ -0,0 +1,163 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#include "nf_rt_native.h" +#include "nanoHAL_ReleaseInfo.h" + + +HRESULT Library_nf_rt_native_nanoFramework_Runtime_Native_SystemInfo::GetSystemVersion___STATIC__VOID__BYREF_I4__BYREF_I4__BYREF_I4__BYREF_I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock hbMajor; + CLR_RT_HeapBlock hbMinor; + CLR_RT_HeapBlock hbBuild; + CLR_RT_HeapBlock hbRevision; + + NFReleaseInfo releaseInfo; + + Target_GetReleaseInfo( releaseInfo ); + + hbMajor.SetInteger( releaseInfo.Version.usMajor ); + NANOCLR_CHECK_HRESULT(hbMajor.StoreToReference( stack.Arg0(), 0 )); + + hbMinor.SetInteger( releaseInfo.Version.usMinor ); + NANOCLR_CHECK_HRESULT(hbMinor.StoreToReference( stack.Arg1(), 0 )); + + hbBuild.SetInteger( releaseInfo.Version.usBuild ); + NANOCLR_CHECK_HRESULT(hbBuild.StoreToReference( stack.Arg2(), 0 )); + + hbRevision.SetInteger( releaseInfo.Version.usRevision ); + NANOCLR_CHECK_HRESULT(hbRevision.StoreToReference( stack.Arg3(), 0 )); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_rt_native_nanoFramework_Runtime_Native_SystemInfo::get_OEMString___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + + NANOCLR_HEADER(); + { + NFReleaseInfo releaseInfo; + + Target_GetReleaseInfo( releaseInfo ); + + NANOCLR_SET_AND_LEAVE(stack.SetResult_String( (char*)releaseInfo.InfoString )); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_rt_native_nanoFramework_Runtime_Native_SystemInfo::get_OEM___STATIC__U1( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + + NANOCLR_HEADER(); + + // we are not supporting this right now + //stack.SetResult( OEM_Model_SKU.OEM, DATATYPE_U1 ); + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + //NANOCLR_NOCLEANUP_NOLABEL(); + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_rt_native_nanoFramework_Runtime_Native_SystemInfo::get_Model___STATIC__U1( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + + NANOCLR_HEADER(); + + // we are not supporting this right now + // stack.SetResult( OEM_Model_SKU.Model, DATATYPE_U1 ); + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + //NANOCLR_NOCLEANUP_NOLABEL(); + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_rt_native_nanoFramework_Runtime_Native_SystemInfo::get_SKU___STATIC__U2( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + + NANOCLR_HEADER(); + + // we are not supporting this right now + // stack.SetResult( OEM_Model_SKU.SKU, DATATYPE_U2 ); + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + //NANOCLR_NOCLEANUP_NOLABEL(); + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_rt_native_nanoFramework_Runtime_Native_SystemInfo::get_TargetName___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + + NANOCLR_HEADER(); + + NFReleaseInfo releaseInfo; + + Target_GetReleaseInfo( releaseInfo ); + + NANOCLR_SET_AND_LEAVE(stack.SetResult_String( (char*)releaseInfo.TargetName )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_rt_native_nanoFramework_Runtime_Native_SystemInfo::get_Platform___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + + NANOCLR_HEADER(); + + + NFReleaseInfo releaseInfo; + + Target_GetReleaseInfo( releaseInfo ); + + NANOCLR_SET_AND_LEAVE(stack.SetResult_String( (char*)releaseInfo.PlatformName )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_rt_native_nanoFramework_Runtime_Native_SystemInfo::GetNativeFloatingPointSupport___STATIC__U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + FloatingPoint floatingPointOption = FloatingPoint_None; + + #if !defined(NANOCLR_EMULATED_FLOATINGPOINT) + + #if (USE_FPU_IS_TRUE == TRUE) + + #if (DP_FLOATINGPOINT == TRUE) + floatingPointOption = FloatingPoint_DoublePrecisionHardware; + #else + floatingPointOption = FloatingPoint_SinglePrecisionHardware; + #endif + + #else + + #if (DP_FLOATINGPOINT == TRUE) + floatingPointOption = FloatingPoint_DoublePrecisionSoftware; + #else + floatingPointOption = FloatingPoint_SinglePrecisionSoftware; + #endif + + #endif // (USE_FPU_IS_TRUE == TRUE) + + #endif // defined(NANOCLR_EMULATED_FLOATINGPOINT) + + stack.SetResult_U1((int8_t)floatingPointOption); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/src/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Native_Debug.cpp b/source/native/nf-interpreter/src/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Native_Debug.cpp new file mode 100644 index 00000000..c75fa041 --- /dev/null +++ b/source/native/nf-interpreter/src/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Native_Debug.cpp @@ -0,0 +1,53 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#include "nf_rt_native.h" + + + +HRESULT Library_nf_rt_native_nanoFramework_Runtime_Native_Debug::GC___STATIC__U4__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + + NANOCLR_HEADER(); + +#if defined(NANOCLR_GC_VERBOSE) + if(s_CLR_RT_fTrace_GC >= c_CLR_RT_Trace_Info) + { + CLR_Debug::Printf( " Memory: Debug.GC.\r\n" ); + } +#endif + + stack.SetResult_I4( g_CLR_RT_ExecutionEngine.PerformGarbageCollection() ); + + if(stack.Arg0().NumericByRefConst().u1) + { + // + // Decrement the number of GC, otherwise the outer loop may request another compaction. + // + g_CLR_RT_GarbageCollector.m_numberOfGarbageCollections--; + + g_CLR_RT_ExecutionEngine.PerformHeapCompaction(); + } + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nf_rt_native_nanoFramework_Runtime_Native_Debug::EnableGCMessages___STATIC__VOID__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + + NANOCLR_HEADER(); + + #if defined(NANOCLR_TRACE_MEMORY_STATS) + s_CLR_RT_fTrace_MemoryStats = stack.Arg0().NumericByRefConst().u1 != 0 ? c_CLR_RT_Trace_Info : c_CLR_RT_Trace_None; + #else + (void)stack; + #endif + + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/src/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Native_ExecutionConstraint.cpp b/source/native/nf-interpreter/src/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Native_ExecutionConstraint.cpp new file mode 100644 index 00000000..326b32bb --- /dev/null +++ b/source/native/nf-interpreter/src/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Native_ExecutionConstraint.cpp @@ -0,0 +1,70 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#include "nf_rt_native.h" + + +HRESULT Library_nf_rt_native_nanoFramework_Runtime_Native_ExecutionConstraint::Install___STATIC__VOID__I4__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + + NANOCLR_HEADER(); + + CLR_RT_StackFrame* caller; + CLR_RT_SubThread* sth; + CLR_INT32 timeout; + CLR_INT32 pri; + + caller = stack.Caller(); FAULT_ON_NULL(caller); // We need to set the constraint on the caller, not on us... + timeout = stack.Arg0().NumericByRef().s4; + pri = stack.Arg1().NumericByRef().s4; + + // + // Find the owned subthread or create a new one. + // + sth = (CLR_RT_SubThread*)caller->m_owningSubThread->Next(); + if(sth->Next()) + { + if(sth->m_owningStackFrame != caller) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + } + else + { + CLR_RT_SubThread* sthNew; + + NANOCLR_CHECK_HRESULT(CLR_RT_SubThread::CreateInstance( stack.m_owningThread, caller, 0, sthNew )); + + sth = sthNew; + } + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.InitTimeout( sth->m_timeConstraint, timeout )); + + // + // Compensate for time spent inside system calls. + // + if(sth->m_timeConstraint != TIMEOUT_INFINITE) + { + sth->m_timeConstraint -= CLR_RT_ExecutionEngine::s_compensation.Adjust( 0 ); + + CLR_RT_ExecutionEngine::InvalidateTimerCache(); + } + + // + // Only threads with priority above zero can raise their priority. + // + if(pri > 0 && caller->m_owningSubThread->m_priority < 0) + { + pri = caller->m_owningSubThread->m_priority; + } + + sth->m_priority = pri; + sth->m_status &= CLR_RT_SubThread::STATUS_Triggered; + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Native_Power.cpp b/source/native/nf-interpreter/src/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Native_Power.cpp new file mode 100644 index 00000000..2d49398c --- /dev/null +++ b/source/native/nf-interpreter/src/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Native_Power.cpp @@ -0,0 +1,18 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#include "nf_rt_native.h" + +HRESULT Library_nf_rt_native_nanoFramework_Runtime_Native_Power::NativeReboot___STATIC__VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + { + g_CLR_RT_ExecutionEngine.Reboot(true); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/src/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Native_Rtc_stubs.cpp b/source/native/nf-interpreter/src/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Native_Rtc_stubs.cpp new file mode 100644 index 00000000..ec344dcd --- /dev/null +++ b/source/native/nf-interpreter/src/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Native_Rtc_stubs.cpp @@ -0,0 +1,23 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#include "nf_rt_native.h" +#include + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// these functions are declared as 'weak' so they can be replaced by the actual ones when they exist on the target platform +// they should be located at targets\NNNN\YYYY\nanoCLR\nanoFramework.Runtime.Native +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + + +__nfweak HRESULT Library_nf_rt_native_nanoFramework_Runtime_Native_Rtc::Native_RTC_SetSystemTime___STATIC__BOOLEAN__I4__U1__U1__U1__U1__U1__U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/nanoFramework.System.Collections/nf_system_collections.cpp b/source/native/nf-interpreter/src/nanoFramework.System.Collections/nf_system_collections.cpp new file mode 100644 index 00000000..2b59644b --- /dev/null +++ b/source/native/nf-interpreter/src/nanoFramework.System.Collections/nf_system_collections.cpp @@ -0,0 +1,100 @@ +#include "nf_system_collections.h" + + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_nf_system_collections_System_Collections_Queue::Clear___VOID, + Library_nf_system_collections_System_Collections_Queue::CopyTo___VOID__mscorlibSystemArray__I4, + Library_nf_system_collections_System_Collections_Queue::Enqueue___VOID__OBJECT, + NULL, + Library_nf_system_collections_System_Collections_Queue::Dequeue___OBJECT, + Library_nf_system_collections_System_Collections_Queue::Peek___OBJECT, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_nf_system_collections_System_Collections_Stack::Clear___VOID, + NULL, + NULL, + NULL, + NULL, + Library_nf_system_collections_System_Collections_Stack::Peek___OBJECT, + Library_nf_system_collections_System_Collections_Stack::Pop___OBJECT, + Library_nf_system_collections_System_Collections_Stack::Push___VOID__OBJECT, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_System_Collections = +{ + "nanoFramework.System.Collections", + 0xC7167094, + method_lookup, + //////////////////////////////////////////////////////////////////////////////////// + // check if the version bellow matches the one in AssemblyNativeVersion attribute // + //////////////////////////////////////////////////////////////////////////////////// + { 100, 0, 0, 0 } +}; diff --git a/source/native/nf-interpreter/src/nanoFramework.System.Collections/nf_system_collections.h b/source/native/nf-interpreter/src/nanoFramework.System.Collections/nf_system_collections.h new file mode 100644 index 00000000..ae439b85 --- /dev/null +++ b/source/native/nf-interpreter/src/nanoFramework.System.Collections/nf_system_collections.h @@ -0,0 +1,113 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _NF_SYSTEM_COLLECTIONS_H_ +#define _NF_SYSTEM_COLLECTIONS_H_ + +#include +#include + +struct Library_nf_system_collections_System_Collections_Hashtable +{ + static const int FIELD___buckets = 1; + static const int FIELD___numberOfBuckets = 2; + static const int FIELD___count = 3; + static const int FIELD___loadFactor = 4; + static const int FIELD___maxLoadFactor = 5; + static const int FIELD___growthFactor = 6; + + + //--// + +}; + +struct Library_nf_system_collections_System_Collections_Hashtable__Entry +{ + static const int FIELD__key = 1; + static const int FIELD__value = 2; + static const int FIELD__next = 3; + + + //--// + +}; + +struct Library_nf_system_collections_System_Collections_Hashtable__HashtableEnumerator +{ + static const int FIELD__ht = 1; + static const int FIELD__temp = 2; + static const int FIELD__index = 3; + static const int FIELD__returnType = 4; + + + //--// + +}; + +struct Library_nf_system_collections_System_Collections_Hashtable__KeyCollection +{ + static const int FIELD__ht = 1; + + + //--// + +}; + +struct Library_nf_system_collections_System_Collections_DictionaryEntry +{ + static const int FIELD__Key = 1; + static const int FIELD__Value = 2; + + + //--// + +}; + +struct Library_nf_system_collections_System_Collections_Queue +{ + static const int FIELD___array = 1; + static const int FIELD___head = 2; + static const int FIELD___tail = 3; + static const int FIELD___size = 4; + + NANOCLR_NATIVE_DECLARE(Clear___VOID); + NANOCLR_NATIVE_DECLARE(CopyTo___VOID__mscorlibSystemArray__I4); + NANOCLR_NATIVE_DECLARE(Enqueue___VOID__OBJECT); + NANOCLR_NATIVE_DECLARE(Dequeue___OBJECT); + NANOCLR_NATIVE_DECLARE(Peek___OBJECT); + + //--// + +}; + +struct Library_nf_system_collections_System_Collections_Stack +{ + static const int FIELD___array = 1; + static const int FIELD___size = 2; + + NANOCLR_NATIVE_DECLARE(Clear___VOID); + NANOCLR_NATIVE_DECLARE(Peek___OBJECT); + NANOCLR_NATIVE_DECLARE(Pop___OBJECT); + NANOCLR_NATIVE_DECLARE(Push___VOID__OBJECT); + + //--// + +}; + +struct Library_nf_system_collections_System_Collections_Hashtable__ValueCollection +{ + static const int FIELD__ht = 1; + + + //--// + +}; + + + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_System_Collections; + +#endif //_NF_SYSTEM_COLLECTIONS_H_ diff --git a/source/native/nf-interpreter/src/nanoFramework.System.Collections/nf_system_collections_System_Collections_Queue.cpp b/source/native/nf-interpreter/src/nanoFramework.System.Collections/nf_system_collections_System_Collections_Queue.cpp new file mode 100644 index 00000000..806c19e8 --- /dev/null +++ b/source/native/nf-interpreter/src/nanoFramework.System.Collections/nf_system_collections_System_Collections_Queue.cpp @@ -0,0 +1,80 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "nf_system_collections.h" + + +HRESULT Library_nf_system_collections_System_Collections_Queue::CopyTo___VOID__mscorlibSystemArray__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Queue* pThis; + CLR_RT_HeapBlock_Array* array; + CLR_INT32 index; + + pThis = (CLR_RT_HeapBlock_Queue*)stack.This(); FAULT_ON_NULL(pThis); + array = stack.Arg1().DereferenceArray(); FAULT_ON_NULL_ARG(array); + index = stack.Arg2().NumericByRef().s4; + + NANOCLR_SET_AND_LEAVE(pThis->CopyTo( array, index )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_system_collections_System_Collections_Queue::Clear___VOID( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Queue* pThis = (CLR_RT_HeapBlock_Queue*)stack.This(); FAULT_ON_NULL(pThis); + + NANOCLR_SET_AND_LEAVE(pThis->Clear()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_system_collections_System_Collections_Queue::Enqueue___VOID__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Queue* pThis = (CLR_RT_HeapBlock_Queue*)stack.This(); FAULT_ON_NULL(pThis); + + NANOCLR_SET_AND_LEAVE(pThis->Enqueue( stack.Arg1().Dereference() )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_system_collections_System_Collections_Queue::Dequeue___OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Queue* pThis = (CLR_RT_HeapBlock_Queue*)stack.This(); FAULT_ON_NULL(pThis); + CLR_RT_HeapBlock* value; + + NANOCLR_CHECK_HRESULT(pThis->Dequeue( value )); + + stack.SetResult_Object( value ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_system_collections_System_Collections_Queue::Peek___OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Queue* pThis = (CLR_RT_HeapBlock_Queue*)stack.This(); FAULT_ON_NULL(pThis); + CLR_RT_HeapBlock* value; + + NANOCLR_CHECK_HRESULT(pThis->Peek( value )); + + stack.SetResult_Object( value ); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/src/nanoFramework.System.Collections/nf_system_collections_System_Collections_Stack.cpp b/source/native/nf-interpreter/src/nanoFramework.System.Collections/nf_system_collections_System_Collections_Stack.cpp new file mode 100644 index 00000000..d5449c24 --- /dev/null +++ b/source/native/nf-interpreter/src/nanoFramework.System.Collections/nf_system_collections_System_Collections_Stack.cpp @@ -0,0 +1,63 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "nf_system_collections.h" + + +HRESULT Library_nf_system_collections_System_Collections_Stack::Clear___VOID( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Stack* pThis = (CLR_RT_HeapBlock_Stack*)stack.This(); FAULT_ON_NULL(pThis); + + NANOCLR_SET_AND_LEAVE(pThis->Clear()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_system_collections_System_Collections_Stack::Peek___OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Stack* pThis = (CLR_RT_HeapBlock_Stack*)stack.This(); FAULT_ON_NULL(pThis); + CLR_RT_HeapBlock* value; + + NANOCLR_CHECK_HRESULT(pThis->Peek( value )); + + stack.SetResult_Object( value ); + + NANOCLR_NOCLEANUP(); + +} + +HRESULT Library_nf_system_collections_System_Collections_Stack::Pop___OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Stack* pThis = (CLR_RT_HeapBlock_Stack*)stack.This(); FAULT_ON_NULL(pThis); + CLR_RT_HeapBlock* value; + + NANOCLR_CHECK_HRESULT(pThis->Pop( value )); + + stack.SetResult_Object( value ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_system_collections_System_Collections_Stack::Push___VOID__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Stack* pThis = (CLR_RT_HeapBlock_Stack*)stack.This(); FAULT_ON_NULL(pThis); + + NANOCLR_SET_AND_LEAVE(pThis->Push( stack.Arg1().Dereference() )); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/startocd.bat b/source/native/nf-interpreter/startocd.bat new file mode 100644 index 00000000..9ac719d0 --- /dev/null +++ b/source/native/nf-interpreter/startocd.bat @@ -0,0 +1,48 @@ +REM Starts OpenOCD - designed to be called from GDB, itself started from Visual Studio launch.vs.json +REM If already running it will fail and exit, leaving the existing one to handle GDB requests +REM Template allows for multiple target interfaces and boards - add new ones as required +REM DAV 26FEB19 +setlocal +set cmd=C:/Esp32_Tools/openocd-esp32/bin/openocd.exe -s C:/Esp32_Tools/openocd-esp32/share/openocd/scripts + +if %1.==. goto ESP32_JLINK +call :%1 +if %errorlevel% equ 1 goto :lblerror +goto end + +REM Start OpenOCD +:start +start %cmd% %iface% +goto :eof + +:end +endlocal +exit + +:lblerror +mshta javascript:alert("Error: Unknown label %1");close(); +goto end + +REM Add additional interface/board combinations here, and add the label to the launch.vs.json file + +:ESP32_JLINK +set iface=-f interface/jlink.cfg -f target/esp32.cfg -c "adapter_khz 3000" +goto start + +:ESP32_OLIMEX +set iface=-f interface/ftdi/olimex-arm-usb-ocd-h.cfg -f target/esp32.cfg -c "adapter_khz 3000" +goto start + +:ESP32_WROVER +set iface=-f interface/ftdi/esp32_devkitj_v1.cfg -f board/esp32-wrover.cfg +goto start + +:STM32_STLINK +REM Note: I tried using the Eclipse OpenOCD without much success here, then switched to the ESP32 version, and it works right out of the box! +REM set cmd=C:/nanoFramework_Tools/Tools/openocd/bin/openocd.exe -s C:/nanoFramework_Tools/Tools/openocd/bin/scripts +set iface=-f interface/stlink-v2-1.cfg -f board/stm32f7discovery.cfg +goto start + + + + diff --git a/source/native/nf-interpreter/targets-community/.github/ISSUE_TEMPLATE.md b/source/native/nf-interpreter/targets-community/.github/ISSUE_TEMPLATE.md new file mode 100644 index 00000000..e1cd4a8d --- /dev/null +++ b/source/native/nf-interpreter/targets-community/.github/ISSUE_TEMPLATE.md @@ -0,0 +1,2 @@ +Please DO NOT open issues in this repository. +We are now using the Home repository for centralized issue management. diff --git a/source/native/nf-interpreter/targets-community/.github/PULL_REQUEST_TEMPLATE.md b/source/native/nf-interpreter/targets-community/.github/PULL_REQUEST_TEMPLATE.md new file mode 100644 index 00000000..35f30cf8 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/.github/PULL_REQUEST_TEMPLATE.md @@ -0,0 +1,4 @@ + +- Fixes/Closes/Resolves nanoFramework/Home#NNNN + + diff --git a/source/native/nf-interpreter/targets-community/.gitignore b/source/native/nf-interpreter/targets-community/.gitignore new file mode 100644 index 00000000..87747b24 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/.gitignore @@ -0,0 +1,60 @@ +# ignore all ZIP files +*.zip +/zips/ + +# ignore build folder +/build/ +/build/.gitkeep + +# ignore cmake-variants file (will change frequently per user/board setup, use should derive content from cmake-variants.TEMPLATE.json) +cmake-variants.json + +# ignore any content inside the Interop assemblies folder +InteropAssemblies/* + +# Visual Studio Code +# ignore C/C++ launch file (will change frequently per user/board setup, use should derive content from launch.TEMPLATE.json) +.vscode/launch.json +.vscode/.cmaketools.json +.vscode/settings.json +.vscode/tasks.json +.vscode/extensions.json +.vscode/c_cpp_properties.json +.vscode/cmake-kits.json +.vscode/ipch + +# ignore CMake modules for Interop assemblies +CMake/Modules/FindINTEROP*.cmake + +# Visual Studio +## Ignore Visual Studio temporary files, build results, and +## files generated by popular Visual Studio add-ons. +## +## Get latest from https://github.com/github/gitignore/blob/master/VisualStudio.gitignore + +# User-specific files +*.suo +*.user + +# Build results +[Dd]ebug/ +[Rr]elease/ +[Rr]eleases/ +[Bb]in/ +[Oo]bj/ + +# Visual Studio cache/options directory contents but not the example launch.vs.json +!.vs/ +.vs/* +!.vs/launch.vs.SAMPLE.json +!.vs/tasks.vs.SAMPLE.json + +# Visual C++ cache files +*.VC.db + +# NuGet Packages +*.nupkg +# The packages folder can be ignored because of Package Restore +**/packages/* +# except build/, which is used as an MSBuild target. +!**/packages/build/ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/CMakeLists.txt new file mode 100644 index 00000000..235396be --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/CMakeLists.txt @@ -0,0 +1,228 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +cmake_minimum_required(VERSION 3.0) +ENABLE_LANGUAGE(ASM) + +# add header files with common OS definitions and board definitions specific for each image +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/target_common.h" @ONLY) + +set(NANOBOOTER_PROJECT_NAME "nanoBooter") +set(NANOCLR_PROJECT_NAME "nanoCLR") + +find_package(BuildUtils REQUIRED) +find_package(CHIBIOS REQUIRED) +find_package(ChibiOSnfOverlay REQUIRED) +find_package(WireProtocol REQUIRED) + +# packages for nanoFramework libraries +####################################### +# mandatory +find_package(NF_CoreCLR REQUIRED) + +####################################### +# optional + +# ChibiOS contrib repo +if(CHIBIOS_CONTRIB_REQUIRED) + find_package(ChibiOS-Contrib REQUIRED) +endif() + +# nF feature: debugger +if(NF_FEATURE_DEBUGGER) + find_package(NF_Debugger REQUIRED) + find_package(NF_Diagnostics REQUIRED) +endif() + +# nF feature: networking +if(USE_NETWORKING_OPTION) + find_package(CHIBIOS_LWIP REQUIRED) +endif() + +# nF feature: filesystem +if(USE_FILESYSTEM_OPTION) + find_package(CHIBIOS_FATFS REQUIRED) +endif() + +####################################### + +add_subdirectory("common") +add_subdirectory("nanoBooter") +add_subdirectory("nanoCLR") + +####################### +# nanoBooter executable + +add_executable( + # executables for project, project sources + ${NANOBOOTER_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + "${CMAKE_CURRENT_SOURCE_DIR}/target_BlockStorage.c" + + # need to add configuration manager to allow get/store configuration blocks + "${PROJECT_SOURCE_DIR}/src/HAL/nanoHAL_ConfigurationManager_stubs.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOBOOTER_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOBOOTER_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOBOOTER_SOURCES} + + ${CHIBIOS_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} +) + +####################### +# nanoCLR executable + +add_executable( + # executables for project, project sources + ${NANOCLR_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOCLR_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOCLR_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOCLR_SOURCES} + + ${CHIBIOS_SOURCES} + ${CHIBIOS_CONTRIB_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} + + # sources for nanoFramework libraries + ${NF_CoreCLR_SOURCES} + ${NF_Debugger_SOURCES} + ${NF_Diagnostics_SOURCES} + + # sources for nanoFramework APIs + ${TARGET_NANO_APIS_SOURCES} +) + +# add dependency from ChibiOS (this is required to make sure the ChibiOS repo is downloaded before the build starts) +add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf ChibiOS) +add_dependencies(${NANOCLR_PROJECT_NAME}.elf ChibiOS) + +# include common directories +include_directories( + ${CMAKE_CURRENT_BINARY_DIR} + ${CMAKE_CURRENT_SOURCE_DIR} + ${CMAKE_CURRENT_SOURCE_DIR}/common + ${PROJECT_SOURCE_DIR}/src/CLR/Core + ${PROJECT_SOURCE_DIR}/src/CLR/Include + ${PROJECT_SOURCE_DIR}/src/HAL/Include + ${PROJECT_SOURCE_DIR}/src/PAL/Include + + ${WireProtocol_INCLUDE_DIRS} + ${CHIBIOS_INCLUDE_DIRS} + ${ChibiOSnfOverlay_INCLUDE_DIRS} + ${CHIBIOS_CONTRIB_INCLUDE_DIRS} + + ${TARGET_CMSIS_COMMON_INCLUDE_DIRS} + ${TARGET_CHIBIOS_COMMON_INCLUDE_DIRS} +) + +# include directories for nanoBooter +target_include_directories(${NANOBOOTER_PROJECT_NAME}.elf PUBLIC + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter" + ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter + + ${TARGET_CMSIS_NANOBOOTER_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOBOOTER_INCLUDE_DIRS} +) + +# include directories for nanoCLR +target_include_directories(${NANOCLR_PROJECT_NAME}.elf PUBLIC + ${CMAKE_CURRENT_BINARY_DIR}/nanoCLR + ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR + + ${TARGET_CMSIS_NANOCLR_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOCLR_INCLUDE_DIRS} + + # directories for nanoFramework libraries + ${NF_CoreCLR_INCLUDE_DIRS} + ${NF_Debugger_INCLUDE_DIRS} + ${NF_Diagnostics_INCLUDE_DIRS} + + # includes for nanoFramework APIs + ${TARGET_NANO_APIS_INCLUDES} + + # includes for ChibiOS LwIP + ${CHIBIOS_LWIP_INCLUDE_DIRS} +) + +# set compiler options +nf_set_compiler_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_options(${NANOCLR_PROJECT_NAME}.elf) + +# set compiler definitions +nf_set_compiler_definitions(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_definitions(${NANOCLR_PROJECT_NAME}.elf) + +# set linker files +if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F405xG_booter-DEBUG.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/STM32F405xG_CLR-DEBUG.ld) +else() + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F405xG_booter.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/STM32F405xG_CLR.ld) +endif() + +# set linker options +nf_set_linker_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_linker_options(${NANOCLR_PROJECT_NAME}.elf) + +# add other linker flags +########################################################### +# the sizes of CRT heap and ChibiOS stacks are defined here +############################################################################ +# CRT heap is assigned to RAM4 region @ CCM SRAM so we are OK to use it all +############################################################################ +set_property(TARGET ${NANOBOOTER_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x400,--defsym=__crt_heap_size__=0x10000") +set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x10000") + +# generate output files +nf_generate_build_output_files(${NANOBOOTER_PROJECT_NAME}.elf) +nf_generate_build_output_files(${NANOCLR_PROJECT_NAME}.elf) + +# if HEX2DFU tool is available pack the binaries into a DFU package +if(HEX2DFU_TOOL_AVAILABLE) + + #################################################################################################### + ## when changing the linker file make sure to update the new addresses for the image files bellow ## + ## DO NOT use the leading 0x notation, just the address in plain hexadecimal formating ## + #################################################################################################### + if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + NF_GENERATE_DFU_PACKAGE( + ${PROJECT_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin 08000000 + ${PROJECT_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin 08008000 + ${PROJECT_SOURCE_DIR}/build/nanobooter-nanoclr.dfu + ) + else() + NF_GENERATE_DFU_PACKAGE( + ${PROJECT_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin 08000000 + ${PROJECT_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin 08004000 + ${PROJECT_SOURCE_DIR}/build/nanobooter-nanoclr.dfu + ) + endif() + +endif() diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/README.md b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/README.md new file mode 100644 index 00000000..56397fa0 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/README.md @@ -0,0 +1,56 @@ +![GHI FEZ CERB40](https://github.com/nanoframework/nf-Community-Targets/blob/master/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/resources/cerb40.jpg) + +----- + +## Board introduction ## + +The board here used is a GHI Fez Cerb40 based upon an STM32F405RGT6 supporting a 1MB Flash and up to 192KB RAM in a LQFP64 package. On this board the LSE is soldered in case you have a board without the LSE please make sure you have it configured correctly in both the mcuconf.h files for nanoBooter as well as nanoCLR. + +The available pins have been set as can be read in the board.h file and it is there where you can set the pin usage for your required use. Visiting the official site [here](http://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f4-series/stm32f405-415/stm32f405rg.html) and per datasheet looking at Table 9. Alternate function mapping you will find possible alternative uses of the various pins. In its initial release the following pin configuration and usage has been verified. Looking at the board from the above (MCU visible) and with the USB connector at the top we have pin 1 on the left hand side. + +| PCB Pin | MCU | Usage | Comment | Date | +|:-|---|---|---|---| +| 01 | VCC | 3.3V | | | +| 02 | GND | | | | +| 03 | PA8 | | | | +| 04 | PA13 | | | | +| 05 | PA7 | SPI1 MISO | | | +| 06 | PA6 | SPI1 MOSI | | | +| 07 | PC10 | | | | +| 08 | PA14 | | | | +| 09 | PC11 | | | | +| 10 | PB4 | | | | +| 11 | PB9 | I2C1 SDA | Confirmed and working | 2018-02-07 | +| 12 | PB3 | | | | +| 13 | PD2 | | | | +| 14 | PC12 | | | | +| 15 | VBAT | | | | +| 16 | PB8 | I2C1 SCL | Confirmed and working | 2018-02-07 | +| 17 | LODR | | | | +| 18 | PB7 | UART1 RX | Confirmed and working | 2018-02-09 | +| 19 | PB6 | UART1 TX | Confirmed and working | 2018-02-09 | +| 20 | PB5 | GPIO, PWM | GPIO confirmed, PWM not done yet | 2018-02-07 | +| 21 | Reset | | Confirmed | 2018-02-07 | +| 22 | PC0 | A0 | | | +| 23 | PC1 | A1 | | | +| 24 | PC2 | A2 | | | +| 25 | PC3 | A3 | | | +| 26 | PA0 | UART2 CTS | | | +| 27 | PA1 | UART2 RTS | | | +| 28 | PA2 | UART2 TX | Confirmed and working | 2018-02-08 | +| 29 | PA3 | UART2 RX | Confirmed and working | 2018-02-09 | +| 30 | PA4 | | | | +| 31 | PA5 | SPI1 SCK | | | +| 32 | PB10 | I2C2 SCL | Confirmed and working | 2018-02-07 | +| 33 | PB11 | I2C2 SDA | Confirmed and working | 2018-02-07 | +| 34 | PB14 | | | | +| 35 | PB15 | | | | +| 36 | PC6 | | | | +| 37 | PC7 | | | | +| 38 | PC8 | | | | +| 39 | PC9 | | | | +| 40 | USB | | | | + +For more information on the board specifics you can have a look at the [GHI Electronics Cerb40 page](http://old.ghielectronics.com/catalog/product/353) + +**NOTE: this configuration was successfully tested in a GHI_FEZ_CERB40_NF board using the Serial over USB connection on USB port 1 that creates a virtual COM port.** diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/board.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/board.c new file mode 100644 index 00000000..fc29a0c0 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/board.c @@ -0,0 +1,265 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) + gpio_setup_t PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_setup_t PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) + gpio_setup_t PKData; +#endif +} gpio_config_t; + +/** + * @brief STM32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +#endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB1(STM32_GPIO_EN_MASK); + rccEnableAHB1(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG + gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI + gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ + gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK + gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + * else. + */ +void __early_init(void) { + + stm32_gpio_init(); + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/board.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/board.h new file mode 100644 index 00000000..0369e951 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/board.h @@ -0,0 +1,1612 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#ifndef BOARD_H +#define BOARD_H + +/* + * Setup for GHI Fez CERB40 board. + */ + +/* + * Board identifier. + */ +#define BOARD_GHI_FEZ_CERB40_NF +#define BOARD_NAME "GHI Fez Cerb40 board" + +#define BOARD_OTG_NOVBUSSENS + +/* + * Board oscillators-related settings. + * NOTE: LSE fitted. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768U +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 12000000U +#endif + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U + +/* + * MCU type as defined in the ST header. + */ +#define STM32F405xx + +/* + * IO pins assignments. + */ +#define GPIOA_UART2_CTS 0U +#define GPIOA_UART2_RTS 1U +#define GPIOA_UART2_TX 2U +#define GPIOA_UART2_RX 3U +#define GPIOA_LRCK 4U +#define GPIOA_SPC 5U +#define GPIOA_SDO 6U +#define GPIOA_SDI 7U +#define GPIOA_PIN8 8U +#define GPIOA_VBUS_FS 9U +#define GPIOA_OTG_FS_ID 10U +#define GPIOA_OTG_FS_DM 11U +#define GPIOA_OTG_FS_DP 12U +#define GPIOA_SWDIO 13U +#define GPIOA_SWCLK 14U +#define GPIOA_PIN15 15U + +#define GPIOB_PIN0 0U +#define GPIOB_PIN1 1U +#define GPIOB_PIN2 2U +#define GPIOB_SWO 3U +#define GPIOB_PIN4 4U +#define GPIOB_PIN5 5U +#define GPIOB_UART1_TX 6U +#define GPIOB_UART1_RX 7U +#define GPIOB_I2C1_SCL 8U +#define GPIOB_I2C1_SDA 9U +#define GPIOB_I2C2_SCL 10U +#define GPIOB_I2C2_SDA 11U +#define GPIOB_PIN12 12U +#define GPIOB_PIN13 13U +#define GPIOB_PIN14 14U +#define GPIOB_PIN15 15U + +#define GPIOC_ADC2_IN10 0U +#define GPIOC_ADC2_IN11 1U +#define GPIOC_ADC3_IN12 2U +#define GPIOC_ADC3_IN13 3U +#define GPIOC_PIN4 4U +#define GPIOC_PIN5 5U +#define GPIOC_PIN6 6U +#define GPIOC_PIN7 7U +#define GPIOC_PIN8 8U +#define GPIOC_PIN9 9U +#define GPIOC_PIN10 10U +#define GPIOC_PIN11 11U +#define GPIOC_PIN12 12U +#define GPIOC_PIN13 13U +#define GPIOC_PIN14 14U +#define GPIOC_PIN15 15U + +#define GPIOD_PIN0 0U +#define GPIOD_PIN1 1U +#define GPIOD_PIN2 2U +#define GPIOD_PIN3 3U +#define GPIOD_RESET 4U +#define GPIOD_OVER_CURRENT 5U +#define GPIOD_PIN6 6U +#define GPIOD_PIN7 7U +#define GPIOD_PIN8 8U +#define GPIOD_PIN9 9U +#define GPIOD_PIN10 10U +#define GPIOD_PIN11 11U +#define GPIOD_LED4 12U +#define GPIOD_LED3 13U +#define GPIOD_LED5 14U +#define GPIOD_LED6 15U + +#define GPIOE_INT1 0U +#define GPIOE_INT2 1U +#define GPIOE_PIN2 2U +#define GPIOE_CS_SPI 3U +#define GPIOE_PIN4 4U +#define GPIOE_PIN5 5U +#define GPIOE_PIN6 6U +#define GPIOE_PIN7 7U +#define GPIOE_PIN8 8U +#define GPIOE_PIN9 9U +#define GPIOE_PIN10 10U +#define GPIOE_PIN11 11U +#define GPIOE_PIN12 12U +#define GPIOE_PIN13 13U +#define GPIOE_PIN14 14U +#define GPIOE_PIN15 15U + +#define GPIOF_PIN0 0U +#define GPIOF_PIN1 1U +#define GPIOF_PIN2 2U +#define GPIOF_PIN3 3U +#define GPIOF_PIN4 4U +#define GPIOF_PIN5 5U +#define GPIOF_PIN6 6U +#define GPIOF_PIN7 7U +#define GPIOF_PIN8 8U +#define GPIOF_PIN9 9U +#define GPIOF_PIN10 10U +#define GPIOF_PIN11 11U +#define GPIOF_PIN12 12U +#define GPIOF_PIN13 13U +#define GPIOF_PIN14 14U +#define GPIOF_PIN15 15U + +#define GPIOG_PIN0 0U +#define GPIOG_PIN1 1U +#define GPIOG_PIN2 2U +#define GPIOG_PIN3 3U +#define GPIOG_PIN4 4U +#define GPIOG_PIN5 5U +#define GPIOG_PIN6 6U +#define GPIOG_PIN7 7U +#define GPIOG_PIN8 8U +#define GPIOG_PIN9 9U +#define GPIOG_PIN10 10U +#define GPIOG_PIN11 11U +#define GPIOG_PIN12 12U +#define GPIOG_PIN13 13U +#define GPIOG_PIN14 14U +#define GPIOG_PIN15 15U + +#define GPIOH_OSC_IN 0U +#define GPIOH_OSC_OUT 1U +#define GPIOH_PIN2 2U +#define GPIOH_PIN3 3U +#define GPIOH_PIN4 4U +#define GPIOH_PIN5 5U +#define GPIOH_PIN6 6U +#define GPIOH_PIN7 7U +#define GPIOH_PIN8 8U +#define GPIOH_PIN9 9U +#define GPIOH_PIN10 10U +#define GPIOH_PIN11 11U +#define GPIOH_PIN12 12U +#define GPIOH_PIN13 13U +#define GPIOH_PIN14 14U +#define GPIOH_PIN15 15U + +#define GPIOI_PIN0 0U +#define GPIOI_PIN1 1U +#define GPIOI_PIN2 2U +#define GPIOI_PIN3 3U +#define GPIOI_PIN4 4U +#define GPIOI_PIN5 5U +#define GPIOI_PIN6 6U +#define GPIOI_PIN7 7U +#define GPIOI_PIN8 8U +#define GPIOI_PIN9 9U +#define GPIOI_PIN10 10U +#define GPIOI_PIN11 11U +#define GPIOI_PIN12 12U +#define GPIOI_PIN13 13U +#define GPIOI_PIN14 14U +#define GPIOI_PIN15 15U + +#define GPIOJ_PIN0 0U +#define GPIOJ_PIN1 1U +#define GPIOJ_PIN2 2U +#define GPIOJ_PIN3 3U +#define GPIOJ_PIN4 4U +#define GPIOJ_PIN5 5U +#define GPIOJ_PIN6 6U +#define GPIOJ_PIN7 7U +#define GPIOJ_PIN8 8U +#define GPIOJ_PIN9 9U +#define GPIOJ_PIN10 10U +#define GPIOJ_PIN11 11U +#define GPIOJ_PIN12 12U +#define GPIOJ_PIN13 13U +#define GPIOJ_PIN14 14U +#define GPIOJ_PIN15 15U + +#define GPIOK_PIN0 0U +#define GPIOK_PIN1 1U +#define GPIOK_PIN2 2U +#define GPIOK_PIN3 3U +#define GPIOK_PIN4 4U +#define GPIOK_PIN5 5U +#define GPIOK_PIN6 6U +#define GPIOK_PIN7 7U +#define GPIOK_PIN8 8U +#define GPIOK_PIN9 9U +#define GPIOK_PIN10 10U +#define GPIOK_PIN11 11U +#define GPIOK_PIN12 12U +#define GPIOK_PIN13 13U +#define GPIOK_PIN14 14U +#define GPIOK_PIN15 15U + +/* + * IO lines assignments. + */ +#define LINE_BUTTON PAL_LINE(GPIOA, 0U) +#define LINE_LRCK PAL_LINE(GPIOA, 4U) +#define LINE_SPC PAL_LINE(GPIOA, 5U) +#define LINE_SDO PAL_LINE(GPIOA, 6U) +#define LINE_SDI PAL_LINE(GPIOA, 7U) +#define LINE_VBUS_FS PAL_LINE(GPIOA, 9U) +#define LINE_OTG_FS_ID PAL_LINE(GPIOA, 10U) +#define LINE_OTG_FS_DM PAL_LINE(GPIOA, 11U) +#define LINE_OTG_FS_DP PAL_LINE(GPIOA, 12U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) + +#define LINE_SWO PAL_LINE(GPIOB, 3U) +#define LINE_SCL PAL_LINE(GPIOB, 6U) +#define LINE_SDA PAL_LINE(GPIOB, 9U) +#define LINE_CLK_IN PAL_LINE(GPIOB, 10U) + +#define LINE_OTG_FS_POWER_ON PAL_LINE(GPIOC, 0U) +#define LINE_PDM_OUT PAL_LINE(GPIOC, 3U) +#define LINE_MCLK PAL_LINE(GPIOC, 7U) +#define LINE_SCLK PAL_LINE(GPIOC, 10U) +#define LINE_SDIN PAL_LINE(GPIOC, 12U) + +#define LINE_RESET PAL_LINE(GPIOD, 4U) +#define LINE_OVER_CURRENT PAL_LINE(GPIOD, 5U) +#define LINE_LED4 PAL_LINE(GPIOD, 12U) +#define LINE_LED3 PAL_LINE(GPIOD, 13U) +#define LINE_LED5 PAL_LINE(GPIOD, 14U) +#define LINE_LED6 PAL_LINE(GPIOD, 15U) + +#define LINE_INT1 PAL_LINE(GPIOE, 0U) +#define LINE_INT2 PAL_LINE(GPIOE, 1U) +#define LINE_CS_SPI PAL_LINE(GPIOE, 3U) + + + +#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) +#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) + + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * GPIOA setup: + * + * PA0 - BUTTON (input floating). + * PA1 - PIN1 (input pullup). + * PA2 - PIN2 (input pullup). + * PA3 - PIN3 (input pullup). + * PA4 - LRCK (alternate 6). + * PA5 - SPC (alternate 5). + * PA6 - SDO (alternate 5). + * PA7 - SDI (alternate 5). + * PA8 - PIN8 (input pullup). + * PA9 - VBUS_FS (input floating). + * PA10 - OTG_FS_ID (alternate 10). + * PA11 - OTG_FS_DM (alternate 10). + * PA12 - OTG_FS_DP (alternate 10). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - PIN15 (input pullup). + */ +#define VAL_GPIOA_MODER (PIN_MODE_ALTERNATE(GPIOA_UART2_CTS) | \ + PIN_MODE_ALTERNATE(GPIOA_UART2_RTS) | \ + PIN_MODE_ALTERNATE(GPIOA_UART2_TX) | \ + PIN_MODE_ALTERNATE(GPIOA_UART2_RX) | \ + PIN_MODE_ALTERNATE(GPIOA_LRCK) | \ + PIN_MODE_ALTERNATE(GPIOA_SPC) | \ + PIN_MODE_ALTERNATE(GPIOA_SDO) | \ + PIN_MODE_ALTERNATE(GPIOA_SDI) | \ + PIN_MODE_INPUT(GPIOA_PIN8) | \ + PIN_MODE_INPUT(GPIOA_VBUS_FS) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_INPUT(GPIOA_PIN15)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_UART2_CTS) | \ + PIN_OTYPE_PUSHPULL(GPIOA_UART2_RTS) | \ + PIN_OTYPE_PUSHPULL(GPIOA_UART2_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOA_UART2_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LRCK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SPC) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SDO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SDI) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOA_VBUS_FS) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_ID) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_MEDIUM(GPIOA_UART2_CTS) | \ + PIN_OSPEED_MEDIUM(GPIOA_UART2_RTS) | \ + PIN_OSPEED_MEDIUM(GPIOA_UART2_TX) | \ + PIN_OSPEED_MEDIUM(GPIOA_UART2_RX) | \ + PIN_OSPEED_HIGH(GPIOA_LRCK) | \ + PIN_OSPEED_MEDIUM(GPIOA_SPC) | \ + PIN_OSPEED_MEDIUM(GPIOA_SDO) | \ + PIN_OSPEED_MEDIUM(GPIOA_SDI) | \ + PIN_OSPEED_HIGH(GPIOA_PIN8) | \ + PIN_OSPEED_HIGH(GPIOA_VBUS_FS) | \ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_ID) | \ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ + PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ + PIN_OSPEED_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_UART2_CTS) | \ + PIN_PUPDR_FLOATING(GPIOA_UART2_RTS) | \ + PIN_PUPDR_FLOATING(GPIOA_UART2_TX) | \ + PIN_PUPDR_FLOATING(GPIOA_UART2_RX) | \ + PIN_PUPDR_FLOATING(GPIOA_LRCK) | \ + PIN_PUPDR_FLOATING(GPIOA_SPC) | \ + PIN_PUPDR_FLOATING(GPIOA_SDO) | \ + PIN_PUPDR_FLOATING(GPIOA_SDI) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOA_VBUS_FS) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_ID) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \ + PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \ + PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN15)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_UART2_CTS) | \ + PIN_ODR_HIGH(GPIOA_UART2_RTS) | \ + PIN_ODR_HIGH(GPIOA_UART2_TX) | \ + PIN_ODR_HIGH(GPIOA_UART2_RX) | \ + PIN_ODR_HIGH(GPIOA_LRCK) | \ + PIN_ODR_HIGH(GPIOA_SPC) | \ + PIN_ODR_HIGH(GPIOA_SDO) | \ + PIN_ODR_HIGH(GPIOA_SDI) | \ + PIN_ODR_HIGH(GPIOA_PIN8) | \ + PIN_ODR_HIGH(GPIOA_VBUS_FS) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_ID) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_UART2_CTS, 7U) | \ + PIN_AFIO_AF(GPIOA_UART2_RTS, 7U) | \ + PIN_AFIO_AF(GPIOA_UART2_TX, 7U) | \ + PIN_AFIO_AF(GPIOA_UART2_RX, 7U) | \ + PIN_AFIO_AF(GPIOA_LRCK, 0U) | \ + PIN_AFIO_AF(GPIOA_SPC, 5U) | \ + PIN_AFIO_AF(GPIOA_SDO, 5U) | \ + PIN_AFIO_AF(GPIOA_SDI, 5U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOA_VBUS_FS, 0U) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10U) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10U) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10U) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN15, 0U)) + +/* + * GPIOB setup: + * + * PB0 - PIN0 (input pullup). + * PB1 - PIN1 (input pullup). + * PB2 - PIN2 (input pullup). + * PB3 - SWO (alternate 0). + * PB4 - PIN4 (input pullup). + * PB5 - PIN5 (input pullup). + * PB6 - SCL (alternate 4). + * PB7 - PIN7 (input pullup). + * PB8 - PIN8 (input pullup). + * PB9 - SDA (alternate 4). + * PB10 - CLK_IN (input pullup). + * PB11 - PIN11 (input pullup). + * PB12 - PIN12 (input pullup). + * PB13 - PIN13 (input pullup). + * PB14 - PIN14 (input pullup). + * PB15 - PIN15 (input pullup). + */ +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \ + PIN_MODE_INPUT(GPIOB_PIN1) | \ + PIN_MODE_INPUT(GPIOB_PIN2) | \ + PIN_MODE_ALTERNATE(GPIOB_SWO) | \ + PIN_MODE_INPUT(GPIOB_PIN4) | \ + PIN_MODE_OUTPUT(GPIOB_PIN5) | \ + PIN_MODE_ALTERNATE(GPIOB_UART1_TX) | \ + PIN_MODE_ALTERNATE(GPIOB_UART1_RX) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C2_SCL) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C2_SDA) | \ + PIN_MODE_INPUT(GPIOB_PIN12) | \ + PIN_MODE_INPUT(GPIOB_PIN13) | \ + PIN_MODE_INPUT(GPIOB_PIN14) | \ + PIN_MODE_INPUT(GPIOB_PIN15)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_UART1_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOB_UART1_RX) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C2_SCL) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C2_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_PIN0) | \ + PIN_OSPEED_HIGH(GPIOB_PIN1) | \ + PIN_OSPEED_HIGH(GPIOB_PIN2) | \ + PIN_OSPEED_HIGH(GPIOB_SWO) | \ + PIN_OSPEED_HIGH(GPIOB_PIN4) | \ + PIN_OSPEED_HIGH(GPIOB_PIN5) | \ + PIN_OSPEED_MEDIUM(GPIOB_UART1_TX) | \ + PIN_OSPEED_MEDIUM(GPIOB_UART1_RX) | \ + PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ + PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ + PIN_OSPEED_HIGH(GPIOB_I2C2_SCL) | \ + PIN_OSPEED_HIGH(GPIOB_I2C2_SDA) | \ + PIN_OSPEED_HIGH(GPIOB_PIN12) | \ + PIN_OSPEED_HIGH(GPIOB_PIN13) | \ + PIN_OSPEED_HIGH(GPIOB_PIN14) | \ + PIN_OSPEED_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOB_SWO) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOB_UART1_TX) | \ + PIN_PUPDR_FLOATING(GPIOB_UART1_RX) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C2_SCL) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C2_SDA) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN15)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ + PIN_ODR_HIGH(GPIOB_PIN1) | \ + PIN_ODR_HIGH(GPIOB_PIN2) | \ + PIN_ODR_HIGH(GPIOB_SWO) | \ + PIN_ODR_HIGH(GPIOB_PIN4) | \ + PIN_ODR_LOW(GPIOB_PIN5) | \ + PIN_ODR_HIGH(GPIOB_UART1_TX) | \ + PIN_ODR_HIGH(GPIOB_UART1_RX) | \ + PIN_ODR_HIGH(GPIOB_I2C1_SCL) | \ + PIN_ODR_HIGH(GPIOB_I2C1_SDA) | \ + PIN_ODR_HIGH(GPIOB_I2C2_SCL) | \ + PIN_ODR_HIGH(GPIOB_I2C2_SDA) | \ + PIN_ODR_HIGH(GPIOB_PIN12) | \ + PIN_ODR_HIGH(GPIOB_PIN13) | \ + PIN_ODR_HIGH(GPIOB_PIN14) | \ + PIN_ODR_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOB_SWO, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOB_UART1_TX, 7U) | \ + PIN_AFIO_AF(GPIOB_UART1_RX, 7U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4U) | \ + PIN_AFIO_AF(GPIOB_I2C1_SDA, 4U) | \ + PIN_AFIO_AF(GPIOB_I2C2_SCL, 4U) | \ + PIN_AFIO_AF(GPIOB_I2C2_SDA, 4U) | \ + PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN15, 0U)) + +/* + * GPIOC setup: + * + * PC0 - GPIOC_ADC2_IN10 (analog input). + * PC1 - GPIOC_ADC2_IN11 (analog input). + * PC2 - GPIOC_ADC3_IN12 (analog input). + * PC3 - GPIOC_ADC1_IN13 (analog input). + * PC4 - PIN4 (input pullup). + * PC5 - PIN5 (input pullup). + * PC6 - PIN6 (input pullup). + * PC7 - MCLK (alternate 6). + * PC8 - PIN8 (input pullup). + * PC9 - PIN9 (input pullup). + * PC10 - SCLK (alternate 6). + * PC11 - PIN11 (input pullup). + * PC12 - SDIN (alternate 6). + * PC13 - PIN13 (input pullup). + * PC14 - PIN14 (input pullup). + * PC15 - PIN15 (input pullup). + */ +#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_ADC2_IN10) |\ + PIN_MODE_ANALOG(GPIOC_ADC2_IN11) | \ + PIN_MODE_ANALOG(GPIOC_ADC3_IN12) | \ + PIN_MODE_ANALOG(GPIOC_ADC3_IN13) | \ + PIN_MODE_INPUT(GPIOC_PIN4) | \ + PIN_MODE_INPUT(GPIOC_PIN5) | \ + PIN_MODE_INPUT(GPIOC_PIN6) | \ + PIN_MODE_INPUT(GPIOC_PIN7) | \ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_INPUT(GPIOC_PIN9) | \ + PIN_MODE_INPUT(GPIOC_PIN10) | \ + PIN_MODE_INPUT(GPIOC_PIN11) | \ + PIN_MODE_INPUT(GPIOC_PIN12) | \ + PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_PIN14) | \ + PIN_MODE_INPUT(GPIOC_PIN15)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ADC2_IN10) |\ + PIN_OTYPE_PUSHPULL(GPIOC_ADC2_IN11) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ADC3_IN12) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ADC3_IN13) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ADC2_IN10) |\ + PIN_OSPEED_HIGH(GPIOC_ADC2_IN11) | \ + PIN_OSPEED_HIGH(GPIOC_ADC3_IN12) | \ + PIN_OSPEED_HIGH(GPIOC_ADC3_IN13) | \ + PIN_OSPEED_HIGH(GPIOC_PIN4) | \ + PIN_OSPEED_HIGH(GPIOC_PIN5) | \ + PIN_OSPEED_HIGH(GPIOC_PIN6) | \ + PIN_OSPEED_HIGH(GPIOC_PIN7) | \ + PIN_OSPEED_HIGH(GPIOC_PIN8) | \ + PIN_OSPEED_HIGH(GPIOC_PIN9) | \ + PIN_OSPEED_HIGH(GPIOC_PIN10) | \ + PIN_OSPEED_HIGH(GPIOC_PIN11) | \ + PIN_OSPEED_HIGH(GPIOC_PIN12) | \ + PIN_OSPEED_HIGH(GPIOC_PIN13) | \ + PIN_OSPEED_HIGH(GPIOC_PIN14) | \ + PIN_OSPEED_HIGH(GPIOC_PIN15)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_ADC2_IN10) |\ + PIN_PUPDR_FLOATING(GPIOC_ADC2_IN11) | \ + PIN_PUPDR_FLOATING(GPIOC_ADC3_IN12) | \ + PIN_PUPDR_FLOATING(GPIOC_ADC3_IN13) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN15)) +#define VAL_GPIOC_ODR (PIN_ODR_LOW(GPIOC_ADC2_IN10) | \ + PIN_ODR_LOW(GPIOC_ADC2_IN11) | \ + PIN_ODR_LOW(GPIOC_ADC3_IN12) | \ + PIN_ODR_LOW(GPIOC_ADC3_IN13) | \ + PIN_ODR_HIGH(GPIOC_PIN4) | \ + PIN_ODR_HIGH(GPIOC_PIN5) | \ + PIN_ODR_HIGH(GPIOC_PIN6) | \ + PIN_ODR_HIGH(GPIOC_PIN7) | \ + PIN_ODR_HIGH(GPIOC_PIN8) | \ + PIN_ODR_HIGH(GPIOC_PIN9) | \ + PIN_ODR_HIGH(GPIOC_PIN10) | \ + PIN_ODR_HIGH(GPIOC_PIN11) | \ + PIN_ODR_HIGH(GPIOC_PIN12) | \ + PIN_ODR_HIGH(GPIOC_PIN13) | \ + PIN_ODR_HIGH(GPIOC_PIN14) | \ + PIN_ODR_HIGH(GPIOC_PIN15)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ADC2_IN10, 0U) |\ + PIN_AFIO_AF(GPIOC_ADC2_IN11, 0U) | \ + PIN_AFIO_AF(GPIOC_ADC3_IN12, 0U) | \ + PIN_AFIO_AF(GPIOC_ADC3_IN13, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN7, 0U)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN15, 0U)) + +/* + * GPIOD setup: + * + * PD0 - PIN0 (input pullup). + * PD1 - PIN1 (input pullup). + * PD2 - PIN2 (input pullup). + * PD3 - PIN3 (input pullup). + * PD4 - RESET (output pushpull maximum). + * PD5 - OVER_CURRENT (input floating). + * PD6 - PIN6 (input pullup). + * PD7 - PIN7 (input pullup). + * PD8 - PIN8 (input pullup). + * PD9 - PIN9 (input pullup). + * PD10 - PIN10 (input pullup). + * PD11 - PIN11 (input pullup). + * PD12 - LED4 (output pushpull maximum). + * PD13 - LED3 (output pushpull maximum). + * PD14 - LED5 (output pushpull maximum). + * PD15 - LED6 (output pushpull maximum). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ + PIN_MODE_INPUT(GPIOD_PIN1) | \ + PIN_MODE_INPUT(GPIOD_PIN2) | \ + PIN_MODE_INPUT(GPIOD_PIN3) | \ + PIN_MODE_INPUT(GPIOD_RESET) | \ + PIN_MODE_INPUT(GPIOD_OVER_CURRENT) | \ + PIN_MODE_INPUT(GPIOD_PIN6) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_INPUT(GPIOD_PIN8) | \ + PIN_MODE_INPUT(GPIOD_PIN9) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_PIN11) | \ + PIN_MODE_INPUT(GPIOD_LED4) | \ + PIN_MODE_INPUT(GPIOD_LED3) | \ + PIN_MODE_INPUT(GPIOD_LED5) | \ + PIN_MODE_INPUT(GPIOD_LED6)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_RESET) | \ + PIN_OTYPE_PUSHPULL(GPIOD_OVER_CURRENT) |\ + PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED5) | \ + PIN_OTYPE_PUSHPULL(GPIOD_LED6)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ + PIN_OSPEED_HIGH(GPIOD_PIN1) | \ + PIN_OSPEED_HIGH(GPIOD_PIN2) | \ + PIN_OSPEED_HIGH(GPIOD_PIN3) | \ + PIN_OSPEED_HIGH(GPIOD_RESET) | \ + PIN_OSPEED_HIGH(GPIOD_OVER_CURRENT) | \ + PIN_OSPEED_HIGH(GPIOD_PIN6) | \ + PIN_OSPEED_HIGH(GPIOD_PIN7) | \ + PIN_OSPEED_HIGH(GPIOD_PIN8) | \ + PIN_OSPEED_HIGH(GPIOD_PIN9) | \ + PIN_OSPEED_HIGH(GPIOD_PIN10) | \ + PIN_OSPEED_HIGH(GPIOD_PIN11) | \ + PIN_OSPEED_HIGH(GPIOD_LED4) | \ + PIN_OSPEED_HIGH(GPIOD_LED3) | \ + PIN_OSPEED_HIGH(GPIOD_LED5) | \ + PIN_OSPEED_HIGH(GPIOD_LED6)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOD_RESET) | \ + PIN_PUPDR_PULLUP(GPIOD_OVER_CURRENT) |\ + PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOD_LED4) | \ + PIN_PUPDR_PULLUP(GPIOD_LED3) | \ + PIN_PUPDR_PULLUP(GPIOD_LED5) | \ + PIN_PUPDR_PULLUP(GPIOD_LED6)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ + PIN_ODR_HIGH(GPIOD_PIN1) | \ + PIN_ODR_HIGH(GPIOD_PIN2) | \ + PIN_ODR_HIGH(GPIOD_PIN3) | \ + PIN_ODR_HIGH(GPIOD_RESET) | \ + PIN_ODR_HIGH(GPIOD_OVER_CURRENT) | \ + PIN_ODR_HIGH(GPIOD_PIN6) | \ + PIN_ODR_HIGH(GPIOD_PIN7) | \ + PIN_ODR_HIGH(GPIOD_PIN8) | \ + PIN_ODR_HIGH(GPIOD_PIN9) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_PIN11) | \ + PIN_ODR_HIGH(GPIOD_LED4) | \ + PIN_ODR_HIGH(GPIOD_LED3) | \ + PIN_ODR_HIGH(GPIOD_LED5) | \ + PIN_ODR_HIGH(GPIOD_LED6)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOD_RESET, 0U) | \ + PIN_AFIO_AF(GPIOD_OVER_CURRENT, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOD_LED4, 0U) | \ + PIN_AFIO_AF(GPIOD_LED3, 0U) | \ + PIN_AFIO_AF(GPIOD_LED5, 0U) | \ + PIN_AFIO_AF(GPIOD_LED6, 0U)) + +/* + * GPIOE setup: + * + * PE0 - INT1 (input floating). + * PE1 - INT2 (input floating). + * PE2 - PIN2 (input floating). + * PE3 - CS_SPI (output pushpull maximum). + * PE4 - PIN4 (input floating). + * PE5 - PIN5 (input floating). + * PE6 - PIN6 (input floating). + * PE7 - PIN7 (input floating). + * PE8 - PIN8 (input floating). + * PE9 - PIN9 (input floating). + * PE10 - PIN10 (input floating). + * PE11 - PIN11 (input floating). + * PE12 - PIN12 (input floating). + * PE13 - PIN13 (input floating). + * PE14 - PIN14 (input floating). + * PE15 - PIN15 (input floating). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_INT1) | \ + PIN_MODE_INPUT(GPIOE_INT2) | \ + PIN_MODE_INPUT(GPIOE_PIN2) | \ + PIN_MODE_INPUT(GPIOE_CS_SPI) | \ + PIN_MODE_INPUT(GPIOE_PIN4) | \ + PIN_MODE_INPUT(GPIOE_PIN5) | \ + PIN_MODE_INPUT(GPIOE_PIN6) | \ + PIN_MODE_INPUT(GPIOE_PIN7) | \ + PIN_MODE_INPUT(GPIOE_PIN8) | \ + PIN_MODE_INPUT(GPIOE_PIN9) | \ + PIN_MODE_INPUT(GPIOE_PIN10) | \ + PIN_MODE_INPUT(GPIOE_PIN11) | \ + PIN_MODE_INPUT(GPIOE_PIN12) | \ + PIN_MODE_INPUT(GPIOE_PIN13) | \ + PIN_MODE_INPUT(GPIOE_PIN14) | \ + PIN_MODE_INPUT(GPIOE_PIN15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_INT1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_INT2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_CS_SPI) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_INT1) | \ + PIN_OSPEED_HIGH(GPIOE_INT2) | \ + PIN_OSPEED_HIGH(GPIOE_PIN2) | \ + PIN_OSPEED_HIGH(GPIOE_CS_SPI) | \ + PIN_OSPEED_HIGH(GPIOE_PIN4) | \ + PIN_OSPEED_HIGH(GPIOE_PIN5) | \ + PIN_OSPEED_HIGH(GPIOE_PIN6) | \ + PIN_OSPEED_HIGH(GPIOE_PIN7) | \ + PIN_OSPEED_HIGH(GPIOE_PIN8) | \ + PIN_OSPEED_HIGH(GPIOE_PIN9) | \ + PIN_OSPEED_HIGH(GPIOE_PIN10) | \ + PIN_OSPEED_HIGH(GPIOE_PIN11) | \ + PIN_OSPEED_HIGH(GPIOE_PIN12) | \ + PIN_OSPEED_HIGH(GPIOE_PIN13) | \ + PIN_OSPEED_HIGH(GPIOE_PIN14) | \ + PIN_OSPEED_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_INT1) | \ + PIN_PUPDR_FLOATING(GPIOE_INT2) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOE_CS_SPI) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOE_PIN15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_INT1) | \ + PIN_ODR_HIGH(GPIOE_INT2) | \ + PIN_ODR_HIGH(GPIOE_PIN2) | \ + PIN_ODR_HIGH(GPIOE_CS_SPI) | \ + PIN_ODR_HIGH(GPIOE_PIN4) | \ + PIN_ODR_HIGH(GPIOE_PIN5) | \ + PIN_ODR_HIGH(GPIOE_PIN6) | \ + PIN_ODR_HIGH(GPIOE_PIN7) | \ + PIN_ODR_HIGH(GPIOE_PIN8) | \ + PIN_ODR_HIGH(GPIOE_PIN9) | \ + PIN_ODR_HIGH(GPIOE_PIN10) | \ + PIN_ODR_HIGH(GPIOE_PIN11) | \ + PIN_ODR_HIGH(GPIOE_PIN12) | \ + PIN_ODR_HIGH(GPIOE_PIN13) | \ + PIN_ODR_HIGH(GPIOE_PIN14) | \ + PIN_ODR_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_INT1, 0U) | \ + PIN_AFIO_AF(GPIOE_INT2, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOE_CS_SPI, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN7, 0U)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN15, 0U)) + +/* + * GPIOF setup: + * + * PF0 - PIN0 (input floating). + * PF1 - PIN1 (input floating). + * PF2 - PIN2 (input floating). + * PF3 - PIN3 (input floating). + * PF4 - PIN4 (input floating). + * PF5 - PIN5 (input floating). + * PF6 - PIN6 (input floating). + * PF7 - PIN7 (input floating). + * PF8 - PIN8 (input floating). + * PF9 - PIN9 (input floating). + * PF10 - PIN10 (input floating). + * PF11 - PIN11 (input floating). + * PF12 - PIN12 (input floating). + * PF13 - PIN13 (input floating). + * PF14 - PIN14 (input floating). + * PF15 - PIN15 (input floating). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ + PIN_MODE_INPUT(GPIOF_PIN1) | \ + PIN_MODE_INPUT(GPIOF_PIN2) | \ + PIN_MODE_INPUT(GPIOF_PIN3) | \ + PIN_MODE_INPUT(GPIOF_PIN4) | \ + PIN_MODE_INPUT(GPIOF_PIN5) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_INPUT(GPIOF_PIN7) | \ + PIN_MODE_INPUT(GPIOF_PIN8) | \ + PIN_MODE_INPUT(GPIOF_PIN9) | \ + PIN_MODE_INPUT(GPIOF_PIN10) | \ + PIN_MODE_INPUT(GPIOF_PIN11) | \ + PIN_MODE_INPUT(GPIOF_PIN12) | \ + PIN_MODE_INPUT(GPIOF_PIN13) | \ + PIN_MODE_INPUT(GPIOF_PIN14) | \ + PIN_MODE_INPUT(GPIOF_PIN15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \ + PIN_OSPEED_HIGH(GPIOF_PIN1) | \ + PIN_OSPEED_HIGH(GPIOF_PIN2) | \ + PIN_OSPEED_HIGH(GPIOF_PIN3) | \ + PIN_OSPEED_HIGH(GPIOF_PIN4) | \ + PIN_OSPEED_HIGH(GPIOF_PIN5) | \ + PIN_OSPEED_HIGH(GPIOF_PIN6) | \ + PIN_OSPEED_HIGH(GPIOF_PIN7) | \ + PIN_OSPEED_HIGH(GPIOF_PIN8) | \ + PIN_OSPEED_HIGH(GPIOF_PIN9) | \ + PIN_OSPEED_HIGH(GPIOF_PIN10) | \ + PIN_OSPEED_HIGH(GPIOF_PIN11) | \ + PIN_OSPEED_HIGH(GPIOF_PIN12) | \ + PIN_OSPEED_HIGH(GPIOF_PIN13) | \ + PIN_OSPEED_HIGH(GPIOF_PIN14) | \ + PIN_OSPEED_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOF_PIN15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ + PIN_ODR_HIGH(GPIOF_PIN1) | \ + PIN_ODR_HIGH(GPIOF_PIN2) | \ + PIN_ODR_HIGH(GPIOF_PIN3) | \ + PIN_ODR_HIGH(GPIOF_PIN4) | \ + PIN_ODR_HIGH(GPIOF_PIN5) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_PIN7) | \ + PIN_ODR_HIGH(GPIOF_PIN8) | \ + PIN_ODR_HIGH(GPIOF_PIN9) | \ + PIN_ODR_HIGH(GPIOF_PIN10) | \ + PIN_ODR_HIGH(GPIOF_PIN11) | \ + PIN_ODR_HIGH(GPIOF_PIN12) | \ + PIN_ODR_HIGH(GPIOF_PIN13) | \ + PIN_ODR_HIGH(GPIOF_PIN14) | \ + PIN_ODR_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN7, 0U)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN15, 0U)) + +/* + * GPIOG setup: + * + * PG0 - PIN0 (input floating). + * PG1 - PIN1 (input floating). + * PG2 - PIN2 (input floating). + * PG3 - PIN3 (input floating). + * PG4 - PIN4 (input floating). + * PG5 - PIN5 (input floating). + * PG6 - PIN6 (input floating). + * PG7 - PIN7 (input floating). + * PG8 - PIN8 (input floating). + * PG9 - PIN9 (input floating). + * PG10 - PIN10 (input floating). + * PG11 - PIN11 (input floating). + * PG12 - PIN12 (input floating). + * PG13 - PIN13 (input floating). + * PG14 - PIN14 (input floating). + * PG15 - PIN15 (input floating). + */ +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \ + PIN_MODE_INPUT(GPIOG_PIN1) | \ + PIN_MODE_INPUT(GPIOG_PIN2) | \ + PIN_MODE_INPUT(GPIOG_PIN3) | \ + PIN_MODE_INPUT(GPIOG_PIN4) | \ + PIN_MODE_INPUT(GPIOG_PIN5) | \ + PIN_MODE_INPUT(GPIOG_PIN6) | \ + PIN_MODE_INPUT(GPIOG_PIN7) | \ + PIN_MODE_INPUT(GPIOG_PIN8) | \ + PIN_MODE_INPUT(GPIOG_PIN9) | \ + PIN_MODE_INPUT(GPIOG_PIN10) | \ + PIN_MODE_INPUT(GPIOG_PIN11) | \ + PIN_MODE_INPUT(GPIOG_PIN12) | \ + PIN_MODE_INPUT(GPIOG_PIN13) | \ + PIN_MODE_INPUT(GPIOG_PIN14) | \ + PIN_MODE_INPUT(GPIOG_PIN15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_PIN0) | \ + PIN_OSPEED_HIGH(GPIOG_PIN1) | \ + PIN_OSPEED_HIGH(GPIOG_PIN2) | \ + PIN_OSPEED_HIGH(GPIOG_PIN3) | \ + PIN_OSPEED_HIGH(GPIOG_PIN4) | \ + PIN_OSPEED_HIGH(GPIOG_PIN5) | \ + PIN_OSPEED_HIGH(GPIOG_PIN6) | \ + PIN_OSPEED_HIGH(GPIOG_PIN7) | \ + PIN_OSPEED_HIGH(GPIOG_PIN8) | \ + PIN_OSPEED_HIGH(GPIOG_PIN9) | \ + PIN_OSPEED_HIGH(GPIOG_PIN10) | \ + PIN_OSPEED_HIGH(GPIOG_PIN11) | \ + PIN_OSPEED_HIGH(GPIOG_PIN12) | \ + PIN_OSPEED_HIGH(GPIOG_PIN13) | \ + PIN_OSPEED_HIGH(GPIOG_PIN14) | \ + PIN_OSPEED_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOG_PIN15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ + PIN_ODR_HIGH(GPIOG_PIN1) | \ + PIN_ODR_HIGH(GPIOG_PIN2) | \ + PIN_ODR_HIGH(GPIOG_PIN3) | \ + PIN_ODR_HIGH(GPIOG_PIN4) | \ + PIN_ODR_HIGH(GPIOG_PIN5) | \ + PIN_ODR_HIGH(GPIOG_PIN6) | \ + PIN_ODR_HIGH(GPIOG_PIN7) | \ + PIN_ODR_HIGH(GPIOG_PIN8) | \ + PIN_ODR_HIGH(GPIOG_PIN9) | \ + PIN_ODR_HIGH(GPIOG_PIN10) | \ + PIN_ODR_HIGH(GPIOG_PIN11) | \ + PIN_ODR_HIGH(GPIOG_PIN12) | \ + PIN_ODR_HIGH(GPIOG_PIN13) | \ + PIN_ODR_HIGH(GPIOG_PIN14) | \ + PIN_ODR_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN7, 0U)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN15, 0U)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - PIN2 (input floating). + * PH3 - PIN3 (input floating). + * PH4 - PIN4 (input floating). + * PH5 - PIN5 (input floating). + * PH6 - PIN6 (input floating). + * PH7 - PIN7 (input floating). + * PH8 - PIN8 (input floating). + * PH9 - PIN9 (input floating). + * PH10 - PIN10 (input floating). + * PH11 - PIN11 (input floating). + * PH12 - PIN12 (input floating). + * PH13 - PIN13 (input floating). + * PH14 - PIN14 (input floating). + * PH15 - PIN15 (input floating). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOH_PIN2) | \ + PIN_MODE_INPUT(GPIOH_PIN3) | \ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_INPUT(GPIOH_PIN5) | \ + PIN_MODE_INPUT(GPIOH_PIN6) | \ + PIN_MODE_INPUT(GPIOH_PIN7) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ + PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ + PIN_OSPEED_HIGH(GPIOH_PIN2) | \ + PIN_OSPEED_HIGH(GPIOH_PIN3) | \ + PIN_OSPEED_HIGH(GPIOH_PIN4) | \ + PIN_OSPEED_HIGH(GPIOH_PIN5) | \ + PIN_OSPEED_HIGH(GPIOH_PIN6) | \ + PIN_OSPEED_HIGH(GPIOH_PIN7) | \ + PIN_OSPEED_HIGH(GPIOH_PIN8) | \ + PIN_OSPEED_HIGH(GPIOH_PIN9) | \ + PIN_OSPEED_HIGH(GPIOH_PIN10) | \ + PIN_OSPEED_HIGH(GPIOH_PIN11) | \ + PIN_OSPEED_HIGH(GPIOH_PIN12) | \ + PIN_OSPEED_HIGH(GPIOH_PIN13) | \ + PIN_OSPEED_HIGH(GPIOH_PIN14) | \ + PIN_OSPEED_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0U)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0U)) + +/* + * GPIOI setup: + * + * PI0 - PIN0 (input floating). + * PI1 - PIN1 (input floating). + * PI2 - PIN2 (input floating). + * PI3 - PIN3 (input floating). + * PI4 - PIN4 (input floating). + * PI5 - PIN5 (input floating). + * PI6 - PIN6 (input floating). + * PI7 - PIN7 (input floating). + * PI8 - PIN8 (input floating). + * PI9 - PIN9 (input floating). + * PI10 - PIN10 (input floating). + * PI11 - PIN11 (input floating). + * PI12 - PIN12 (input floating). + * PI13 - PIN13 (input floating). + * PI14 - PIN14 (input floating). + * PI15 - PIN15 (input floating). + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ + PIN_MODE_INPUT(GPIOI_PIN1) | \ + PIN_MODE_INPUT(GPIOI_PIN2) | \ + PIN_MODE_INPUT(GPIOI_PIN3) | \ + PIN_MODE_INPUT(GPIOI_PIN4) | \ + PIN_MODE_INPUT(GPIOI_PIN5) | \ + PIN_MODE_INPUT(GPIOI_PIN6) | \ + PIN_MODE_INPUT(GPIOI_PIN7) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_INPUT(GPIOI_PIN9) | \ + PIN_MODE_INPUT(GPIOI_PIN10) | \ + PIN_MODE_INPUT(GPIOI_PIN11) | \ + PIN_MODE_INPUT(GPIOI_PIN12) | \ + PIN_MODE_INPUT(GPIOI_PIN13) | \ + PIN_MODE_INPUT(GPIOI_PIN14) | \ + PIN_MODE_INPUT(GPIOI_PIN15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_HIGH(GPIOI_PIN0) | \ + PIN_OSPEED_HIGH(GPIOI_PIN1) | \ + PIN_OSPEED_HIGH(GPIOI_PIN2) | \ + PIN_OSPEED_HIGH(GPIOI_PIN3) | \ + PIN_OSPEED_HIGH(GPIOI_PIN4) | \ + PIN_OSPEED_HIGH(GPIOI_PIN5) | \ + PIN_OSPEED_HIGH(GPIOI_PIN6) | \ + PIN_OSPEED_HIGH(GPIOI_PIN7) | \ + PIN_OSPEED_HIGH(GPIOI_PIN8) | \ + PIN_OSPEED_HIGH(GPIOI_PIN9) | \ + PIN_OSPEED_HIGH(GPIOI_PIN10) | \ + PIN_OSPEED_HIGH(GPIOI_PIN11) | \ + PIN_OSPEED_HIGH(GPIOI_PIN12) | \ + PIN_OSPEED_HIGH(GPIOI_PIN13) | \ + PIN_OSPEED_HIGH(GPIOI_PIN14) | \ + PIN_OSPEED_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOI_PIN15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ + PIN_ODR_HIGH(GPIOI_PIN1) | \ + PIN_ODR_HIGH(GPIOI_PIN2) | \ + PIN_ODR_HIGH(GPIOI_PIN3) | \ + PIN_ODR_HIGH(GPIOI_PIN4) | \ + PIN_ODR_HIGH(GPIOI_PIN5) | \ + PIN_ODR_HIGH(GPIOI_PIN6) | \ + PIN_ODR_HIGH(GPIOI_PIN7) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_PIN9) | \ + PIN_ODR_HIGH(GPIOI_PIN10) | \ + PIN_ODR_HIGH(GPIOI_PIN11) | \ + PIN_ODR_HIGH(GPIOI_PIN12) | \ + PIN_ODR_HIGH(GPIOI_PIN13) | \ + PIN_ODR_HIGH(GPIOI_PIN14) | \ + PIN_ODR_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN7, 0U)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN15, 0U)) + +/* + * GPIOJ setup: + * + * PJ0 - PIN0 (input floating). + * PJ1 - PIN1 (input floating). + * PJ2 - PIN2 (input floating). + * PJ3 - PIN3 (input floating). + * PJ4 - PIN4 (input floating). + * PJ5 - PIN5 (input floating). + * PJ6 - PIN6 (input floating). + * PJ7 - PIN7 (input floating). + * PJ8 - PIN8 (input floating). + * PJ9 - PIN9 (input floating). + * PJ10 - PIN10 (input floating). + * PJ11 - PIN11 (input floating). + * PJ12 - PIN12 (input floating). + * PJ13 - PIN13 (input floating). + * PJ14 - PIN14 (input floating). + * PJ15 - PIN15 (input floating). + */ +#define VAL_GPIOJ_MODER (PIN_MODE_INPUT(GPIOJ_PIN0) | \ + PIN_MODE_INPUT(GPIOJ_PIN1) | \ + PIN_MODE_INPUT(GPIOJ_PIN2) | \ + PIN_MODE_INPUT(GPIOJ_PIN3) | \ + PIN_MODE_INPUT(GPIOJ_PIN4) | \ + PIN_MODE_INPUT(GPIOJ_PIN5) | \ + PIN_MODE_INPUT(GPIOJ_PIN6) | \ + PIN_MODE_INPUT(GPIOJ_PIN7) | \ + PIN_MODE_INPUT(GPIOJ_PIN8) | \ + PIN_MODE_INPUT(GPIOJ_PIN9) | \ + PIN_MODE_INPUT(GPIOJ_PIN10) | \ + PIN_MODE_INPUT(GPIOJ_PIN11) | \ + PIN_MODE_INPUT(GPIOJ_PIN12) | \ + PIN_MODE_INPUT(GPIOJ_PIN13) | \ + PIN_MODE_INPUT(GPIOJ_PIN14) | \ + PIN_MODE_INPUT(GPIOJ_PIN15)) +#define VAL_GPIOJ_OTYPER (PIN_OTYPE_PUSHPULL(GPIOJ_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN15)) +#define VAL_GPIOJ_OSPEEDR (PIN_OSPEED_HIGH(GPIOJ_PIN0) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN1) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN2) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN3) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN4) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN5) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN6) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN7) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN8) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN9) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN10) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN11) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN12) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN13) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN14) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN15)) +#define VAL_GPIOJ_PUPDR (PIN_PUPDR_FLOATING(GPIOJ_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN15)) +#define VAL_GPIOJ_ODR (PIN_ODR_HIGH(GPIOJ_PIN0) | \ + PIN_ODR_HIGH(GPIOJ_PIN1) | \ + PIN_ODR_HIGH(GPIOJ_PIN2) | \ + PIN_ODR_HIGH(GPIOJ_PIN3) | \ + PIN_ODR_HIGH(GPIOJ_PIN4) | \ + PIN_ODR_HIGH(GPIOJ_PIN5) | \ + PIN_ODR_HIGH(GPIOJ_PIN6) | \ + PIN_ODR_HIGH(GPIOJ_PIN7) | \ + PIN_ODR_HIGH(GPIOJ_PIN8) | \ + PIN_ODR_HIGH(GPIOJ_PIN9) | \ + PIN_ODR_HIGH(GPIOJ_PIN10) | \ + PIN_ODR_HIGH(GPIOJ_PIN11) | \ + PIN_ODR_HIGH(GPIOJ_PIN12) | \ + PIN_ODR_HIGH(GPIOJ_PIN13) | \ + PIN_ODR_HIGH(GPIOJ_PIN14) | \ + PIN_ODR_HIGH(GPIOJ_PIN15)) +#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(GPIOJ_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN7, 0U)) +#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(GPIOJ_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN15, 0U)) + +/* + * GPIOK setup: + * + * PK0 - PIN0 (input floating). + * PK1 - PIN1 (input floating). + * PK2 - PIN2 (input floating). + * PK3 - PIN3 (input floating). + * PK4 - PIN4 (input floating). + * PK5 - PIN5 (input floating). + * PK6 - PIN6 (input floating). + * PK7 - PIN7 (input floating). + * PK8 - PIN8 (input floating). + * PK9 - PIN9 (input floating). + * PK10 - PIN10 (input floating). + * PK11 - PIN11 (input floating). + * PK12 - PIN12 (input floating). + * PK13 - PIN13 (input floating). + * PK14 - PIN14 (input floating). + * PK15 - PIN15 (input floating). + */ +#define VAL_GPIOK_MODER (PIN_MODE_INPUT(GPIOK_PIN0) | \ + PIN_MODE_INPUT(GPIOK_PIN1) | \ + PIN_MODE_INPUT(GPIOK_PIN2) | \ + PIN_MODE_INPUT(GPIOK_PIN3) | \ + PIN_MODE_INPUT(GPIOK_PIN4) | \ + PIN_MODE_INPUT(GPIOK_PIN5) | \ + PIN_MODE_INPUT(GPIOK_PIN6) | \ + PIN_MODE_INPUT(GPIOK_PIN7) | \ + PIN_MODE_INPUT(GPIOK_PIN8) | \ + PIN_MODE_INPUT(GPIOK_PIN9) | \ + PIN_MODE_INPUT(GPIOK_PIN10) | \ + PIN_MODE_INPUT(GPIOK_PIN11) | \ + PIN_MODE_INPUT(GPIOK_PIN12) | \ + PIN_MODE_INPUT(GPIOK_PIN13) | \ + PIN_MODE_INPUT(GPIOK_PIN14) | \ + PIN_MODE_INPUT(GPIOK_PIN15)) +#define VAL_GPIOK_OTYPER (PIN_OTYPE_PUSHPULL(GPIOK_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN15)) +#define VAL_GPIOK_OSPEEDR (PIN_OSPEED_HIGH(GPIOK_PIN0) | \ + PIN_OSPEED_HIGH(GPIOK_PIN1) | \ + PIN_OSPEED_HIGH(GPIOK_PIN2) | \ + PIN_OSPEED_HIGH(GPIOK_PIN3) | \ + PIN_OSPEED_HIGH(GPIOK_PIN4) | \ + PIN_OSPEED_HIGH(GPIOK_PIN5) | \ + PIN_OSPEED_HIGH(GPIOK_PIN6) | \ + PIN_OSPEED_HIGH(GPIOK_PIN7) | \ + PIN_OSPEED_HIGH(GPIOK_PIN8) | \ + PIN_OSPEED_HIGH(GPIOK_PIN9) | \ + PIN_OSPEED_HIGH(GPIOK_PIN10) | \ + PIN_OSPEED_HIGH(GPIOK_PIN11) | \ + PIN_OSPEED_HIGH(GPIOK_PIN12) | \ + PIN_OSPEED_HIGH(GPIOK_PIN13) | \ + PIN_OSPEED_HIGH(GPIOK_PIN14) | \ + PIN_OSPEED_HIGH(GPIOK_PIN15)) +#define VAL_GPIOK_PUPDR (PIN_PUPDR_FLOATING(GPIOK_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN15)) +#define VAL_GPIOK_ODR (PIN_ODR_HIGH(GPIOK_PIN0) | \ + PIN_ODR_HIGH(GPIOK_PIN1) | \ + PIN_ODR_HIGH(GPIOK_PIN2) | \ + PIN_ODR_HIGH(GPIOK_PIN3) | \ + PIN_ODR_HIGH(GPIOK_PIN4) | \ + PIN_ODR_HIGH(GPIOK_PIN5) | \ + PIN_ODR_HIGH(GPIOK_PIN6) | \ + PIN_ODR_HIGH(GPIOK_PIN7) | \ + PIN_ODR_HIGH(GPIOK_PIN8) | \ + PIN_ODR_HIGH(GPIOK_PIN9) | \ + PIN_ODR_HIGH(GPIOK_PIN10) | \ + PIN_ODR_HIGH(GPIOK_PIN11) | \ + PIN_ODR_HIGH(GPIOK_PIN12) | \ + PIN_ODR_HIGH(GPIOK_PIN13) | \ + PIN_ODR_HIGH(GPIOK_PIN14) | \ + PIN_ODR_HIGH(GPIOK_PIN15)) +#define VAL_GPIOK_AFRL (PIN_AFIO_AF(GPIOK_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN7, 0U)) +#define VAL_GPIOK_AFRH (PIN_AFIO_AF(GPIOK_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN15, 0U)) + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/common/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/common/CMakeLists.txt new file mode 100644 index 00000000..aa7f1d54 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/common/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/usbcfg.c") +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c") + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/common/Device_BlockStorage-DEBUG.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 00000000..c0759ead --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,94 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 1 }, // 08000000 nanoBooter + { BlockRange_BLOCKTYPE_CODE , 2, 3 } // 08008000 nanoCLR +}; + +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 08010000 nanoCLR +}; + +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 }, // 08020000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 1, 6 } // 08040000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08010000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 7, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00100000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/common/Device_BlockStorage.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/common/Device_BlockStorage.c new file mode 100644 index 00000000..b05efe0e --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/common/Device_BlockStorage.c @@ -0,0 +1,94 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 0 }, // 08000000 nanoBooter + { BlockRange_BLOCKTYPE_CODE , 1, 3 } // 08004000 nanoCLR +}; + +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 08010000 nanoCLR +}; + +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 }, // 08020000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 1, 6 } // 08040000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08010000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 7, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00100000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/common/usbcfg.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/common/usbcfg.c new file mode 100644 index 00000000..a048c76f --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/common/usbcfg.c @@ -0,0 +1,435 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "hal.h" + +/* Virtual serial port over USB.*/ +SerialUSBDriver SDU1; + +/* + * Endpoints to be used for USBD1. + */ +#define USBD1_DATA_REQUEST_EP 1 +#define USBD1_DATA_AVAILABLE_EP 1 +#define USBD1_INTERRUPT_REQUEST_EP 2 + +// address for device unique ID +// valid for STM32F4 series +#define DEVICE_ID1 (0x1FFF7A10) +#define DEVICE_ID2 (0x1FFF7A14) +#define DEVICE_ID3 (0x1FFF7A18) + +// // size of string serial is 36 = 2 + 5x2 + 26 from silicon unique ID precedeed of string "NANO_" and descriptor codes +// #define USB_SIZ_STRING_SERIAL 36 + +//////////////////////////////////////////////// +// vendor +#define USB_STRING_VENDOR L"STMicroelectronics" +//////////////////////////////////////////////// + +// structure for USB Vendor with Unicode string +typedef struct usb_string_vendor +{ + uint8_t bLength; + uint8_t bDescriptorType; + wchar_t bPropertyData[sizeof(USB_STRING_VENDOR)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec) + +}usb_string_vendor; + + +///////////////////////////////////////////////////////////////////////// +// device description +#define USB_STRING_DEVICE_DESCRIPTION L"nanoFramework Virtual COM Port" +///////////////////////////////////////////////////////////////////////// + +// structure for USB device descriptor with Unicode string +typedef struct usb_string_device_description +{ + uint8_t bLength; + uint8_t bDescriptorType; + wchar_t bPropertyData[sizeof(USB_STRING_DEVICE_DESCRIPTION)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec) + +}usb_string_device_description; + + +///////////////////////////////////////////////////////////////////////// +// device serial number +// this will produce a string with NANO_ prefix followed +// by the hexadecimal representation of the silicon unique ID of the CPU +#define USB_STRING_SERIAL_NUMBER L"NANO_xxxxxxxxxxx" +///////////////////////////////////////////////////////////////////////// +#define INDEX_OF_WCHAR_FOR_UNIQUE_ID 5 + +// structure for USB serial number descriptor with Unicode string +typedef struct usb_string_serial_number +{ + uint8_t bLength; + uint8_t bDescriptorType; + wchar_t bPropertyData[sizeof(USB_STRING_SERIAL_NUMBER)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec) + +}usb_string_serial_number; + + +/* + * USB Device Descriptor. + */ +static const uint8_t vcom_device_descriptor_data[18] = { + USB_DESC_DEVICE (0x0200, /* bcdUSB (2.0). */ + 0x02, /* bDeviceClass (CDC). */ + 0x00, /* bDeviceSubClass. */ + 0x00, /* bDeviceProtocol. */ + 0x40, /* bMaxPacketSize. */ + 0x0483, /* idVendor (ST). */ + 0x5740, /* idProduct. */ + 0x0200, /* bcdDevice. */ + 1, /* iManufacturer. */ + 2, /* iProduct. */ + 3, /* iSerialNumber. */ + 1) /* bNumConfigurations. */ +}; + +/* + * Device Descriptor wrapper. + */ +static const USBDescriptor vcom_device_descriptor = { + sizeof vcom_device_descriptor_data, + vcom_device_descriptor_data +}; + +/* Configuration Descriptor tree for a CDC.*/ +static const uint8_t vcom_configuration_descriptor_data[67] = { + /* Configuration Descriptor.*/ + USB_DESC_CONFIGURATION(67, /* wTotalLength. */ + 0x02, /* bNumInterfaces. */ + 0x01, /* bConfigurationValue. */ + 0, /* iConfiguration. */ + 0xC0, /* bmAttributes (self powered). */ + 50), /* bMaxPower (100mA). */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x01, /* bNumEndpoints. */ + 0x02, /* bInterfaceClass (Communications + Interface Class, CDC section + 4.2). */ + 0x02, /* bInterfaceSubClass (Abstract + Control Model, CDC section 4.3). */ + 0x01, /* bInterfaceProtocol (AT commands, + CDC section 4.4). */ + 0), /* iInterface. */ + /* Header Functional Descriptor (CDC section 5.2.3).*/ + USB_DESC_BYTE (5), /* bLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header + Functional Descriptor. */ + USB_DESC_BCD (0x0110), /* bcdCDC. */ + /* Call Management Functional Descriptor. */ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */ + USB_DESC_BYTE (0x01), /* bDataInterface. */ + /* ACM Functional Descriptor.*/ + USB_DESC_BYTE (4), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract + Control Management Descriptor). */ + USB_DESC_BYTE (0x02), /* bmCapabilities. */ + /* Union Functional Descriptor.*/ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bMasterInterface (Communication + Class Interface). */ + USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class + Interface). */ + /* Endpoint 2 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_INTERRUPT_REQUEST_EP|0x80, + 0x03, /* bmAttributes (Interrupt). */ + 0x0008, /* wMaxPacketSize. */ + 0xFF), /* bInterval. */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x02, /* bNumEndpoints. */ + 0x0A, /* bInterfaceClass (Data Class + Interface, CDC section 4.5). */ + 0x00, /* bInterfaceSubClass (CDC section + 4.6). */ + 0x00, /* bInterfaceProtocol (CDC section + 4.7). */ + 0x00), /* iInterface. */ + /* Endpoint 3 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_AVAILABLE_EP, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00), /* bInterval. */ + /* Endpoint 1 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00) /* bInterval. */ +}; + +/* + * Configuration Descriptor wrapper. + */ +static const USBDescriptor vcom_configuration_descriptor = { + sizeof vcom_configuration_descriptor_data, + vcom_configuration_descriptor_data +}; + +/* + * U.S. English language identifier. + */ +static const uint8_t vcom_string0[] = { + USB_DESC_BYTE(4), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */ +}; + + +// Vendor string +static const usb_string_vendor usb_vendor = { + sizeof(usb_vendor), + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), + USB_STRING_VENDOR +}; + + +// Device Description string +static const usb_string_device_description usb_device_description = { + sizeof(usb_device_description), + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), + USB_STRING_DEVICE_DESCRIPTION +}; + + +// Serial Number string. +static usb_string_serial_number usb_serial_number = { + sizeof(usb_serial_number), + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), + USB_STRING_SERIAL_NUMBER +}; + + +/* + * Strings wrappers array. + */ +static const USBDescriptor vcom_strings[] = { + {sizeof vcom_string0, vcom_string0}, + {sizeof usb_vendor, (uint8_t*)(&usb_vendor)}, + {sizeof usb_device_description, (uint8_t*)(&usb_device_description)}, + {sizeof usb_serial_number, (uint8_t*)(&usb_serial_number)}, +}; + + +// Convert Hex 32Bits value into char +// value: value to convert +// pbuf: pointer to the buffer +// len: buffer length +void IntToUnicode(uint32_t value , uint8_t *pbuf, uint8_t len) +{ + uint8_t idx = 0; + + for( idx = 0; idx < len; idx ++) + { + if( ((value >> 28)) < 0xA ) + { + pbuf[ 2* idx] = (value >> 28) + '0'; + } + else + { + pbuf[2* idx] = (value >> 28) + 'A' - 10; + } + + value = value << 4; + + pbuf[ 2* idx + 1] = 0; + } +} + +// Create the serial number string descriptor +void Get_SerialNum(uint8_t* pbuf) +{ + uint32_t deviceserial0, deviceserial1, deviceserial2; + + deviceserial0 = *(uint32_t*)DEVICE_ID1; + deviceserial1 = *(uint32_t*)DEVICE_ID2; + deviceserial2 = *(uint32_t*)DEVICE_ID3; + + deviceserial0 += deviceserial2; + + if (deviceserial0 != 0) + { + IntToUnicode(deviceserial0, pbuf, 8); + pbuf += 16; + IntToUnicode(deviceserial1, pbuf, 4); + } +} + +/* + * Handles the GET_DESCRIPTOR callback. All required descriptors must be + * handled here. + */ +static const USBDescriptor *get_descriptor(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang) { + + (void)usbp; + (void)lang; + + switch (dtype) { + case USB_DESCRIPTOR_DEVICE: + return &vcom_device_descriptor; + case USB_DESCRIPTOR_CONFIGURATION: + return &vcom_configuration_descriptor; + case USB_DESCRIPTOR_STRING: + if (dindex < 4) + { + if(dindex == 3) + { + // request is for serial number + // get it from the silicon unique ID + Get_SerialNum((uint8_t*)&usb_serial_number.bPropertyData[INDEX_OF_WCHAR_FOR_UNIQUE_ID]); + } + + return &vcom_strings[dindex]; + } + } + return NULL; +} + +/** + * @brief IN EP1 state. + */ +static USBInEndpointState ep1instate; + +/** + * @brief OUT EP1 state. + */ +static USBOutEndpointState ep1outstate; + +/** + * @brief EP1 initialization structure (both IN and OUT). + */ +static const USBEndpointConfig ep1config = { + USB_EP_MODE_TYPE_BULK, + NULL, + sduDataTransmitted, + sduDataReceived, + 0x0040, + 0x0040, + &ep1instate, + &ep1outstate, + 2, + NULL +}; + +/** + * @brief IN EP2 state. + */ +static USBInEndpointState ep2instate; + +/** + * @brief EP2 initialization structure (IN only). + */ +static const USBEndpointConfig ep2config = { + USB_EP_MODE_TYPE_INTR, + NULL, + sduInterruptTransmitted, + NULL, + 0x0010, + 0x0000, + &ep2instate, + NULL, + 1, + NULL +}; + +/* + * Handles the USB driver global events. + */ +static void usb_event(USBDriver *usbp, usbevent_t event) { + extern SerialUSBDriver SDU1; + + switch (event) { + case USB_EVENT_ADDRESS: + return; + case USB_EVENT_CONFIGURED: + chSysLockFromISR(); + + /* Enables the endpoints specified into the configuration. + Note, this callback is invoked from an ISR so I-Class functions + must be used.*/ + usbInitEndpointI(usbp, USBD1_DATA_REQUEST_EP, &ep1config); + usbInitEndpointI(usbp, USBD1_INTERRUPT_REQUEST_EP, &ep2config); + + /* Resetting the state of the CDC subsystem.*/ + sduConfigureHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_RESET: + /* Falls into.*/ + case USB_EVENT_UNCONFIGURED: + /* Falls into.*/ + case USB_EVENT_SUSPEND: + chSysLockFromISR(); + + /* Disconnection event on suspend.*/ + sduSuspendHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_WAKEUP: + chSysLockFromISR(); + + /* Disconnection event on suspend.*/ + sduWakeupHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_STALLED: + return; + } + return; +} + +/* + * Handles the USB driver global events. + */ +static void sof_handler(USBDriver *usbp) { + + (void)usbp; + + osalSysLockFromISR(); + sduSOFHookI(&SDU1); + osalSysUnlockFromISR(); +} + +/* + * USB driver configuration. + */ +const USBConfig usbcfg = { + usb_event, + get_descriptor, + sduRequestsHook, + sof_handler +}; + +/* + * Serial over USB driver configuration. + */ +const SerialUSBConfig serusbcfg = { + &USBD1, + USBD1_DATA_REQUEST_EP, + USBD1_DATA_AVAILABLE_EP, + USBD1_INTERRUPT_REQUEST_EP +}; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/common/usbcfg.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/common/usbcfg.h new file mode 100644 index 00000000..167e1df8 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/common/usbcfg.h @@ -0,0 +1,17 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef USBCFG_H +#define USBCFG_H + +extern const USBConfig usbcfg; +extern SerialUSBConfig serusbcfg; +extern SerialUSBDriver SDU1; + +#endif /* USBCFG_H */ + +/** @} */ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/managed_helpers/GHI_FEZ_CERB40_NF.Adc.cs b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/managed_helpers/GHI_FEZ_CERB40_NF.Adc.cs new file mode 100644 index 00000000..f73100be --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/managed_helpers/GHI_FEZ_CERB40_NF.Adc.cs @@ -0,0 +1,48 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +namespace nanoFramework.Targets.Community.GHI_FEZ_CERB40_NF +{ + /// + /// Enumeration of ADC channels available in the community board GHI_FEZ_CERB40_NF + /// + public static class AdcChannels + { + /// + /// Channel 0, exposed on PC0, connected to PC0 (ADC2 - IN10) + /// + public const int Channel_0 = 0; + + /// + /// Channel 1, exposed on PA1, connected to PA1 (ADC2 - IN11) + /// + public const int Channel_1 = 1; + + /// + /// Channel 2, exposed on PA4, connected to PA4 (ADC3 - IN12) + /// + public const int Channel_2 = 2; + + /// + /// Channel 3, exposed on PC3, connected to PC3 (ADC3 - IN13) + /// + public const int Channel_3 = 3; + + /// + /// Channel 4, internal temperature sensor, connected to ADC1 + /// + public const int Channel_TemperatureSensor = 4; + + /// + /// Channel 5, internal voltage reference, connected to ADC1 + /// + public const int Channel_VrefIn = 5; + + /// + /// Channel 6, connected to VBatt pin, ADC1 + /// + public const int Channel_Vbatt = 6; + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/managed_helpers/GHI_FEZ_CERB40_NF.Gpio.cs b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/managed_helpers/GHI_FEZ_CERB40_NF.Gpio.cs new file mode 100644 index 00000000..d10d066e --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/managed_helpers/GHI_FEZ_CERB40_NF.Gpio.cs @@ -0,0 +1,55 @@ +using System; + +namespace nanoFramework.Targets.Community.GHI_FEZ_CERB40_NF +{ + public static class Gpio + { + /// + /// + /// + public const int PA0 = 0; + public const int PA1 = 1; + public const int PA2 = 2; + public const int PA3 = 3; + public const int PA4 = 4; + public const int PA5 = 5; + public const int PA6 = 6; + public const int PA7 = 7; + public const int PA8 = 8; + public const int PA9 = 9; + public const int PA10 = 10; + public const int PA11 = 11; + public const int PA12 = 12; + public const int PA13 = 13; + public const int PA14 = 14; + public const int PA15 = 15; + + /// + /// + /// + public const int PB0 = 16; + public const int PB1 = 17; + public const int PB2 = 18; + public const int PB3 = 19; + public const int PB4 = 20; + public const int PB5 = 21; + public const int PB6 = 22; + public const int PB7 = 23; + public const int PB8 = 24; + public const int PB9 = 25; + public const int PB10 = 26; + public const int PB11 = 27; + public const int PB12 = 28; + public const int PB13 = 29; + public const int PB14 = 30; + public const int PB15 = 31; + + /// + /// + /// + public const int PC0 = 32; + public const int PC1 = 33; + public const int PC2 = 34; + public const int PC3 = 35; + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/managed_helpers/README.md b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/managed_helpers/README.md new file mode 100644 index 00000000..a749a3ce --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/managed_helpers/README.md @@ -0,0 +1,6 @@ +## Managed code helpers + +This folder contains helper classes to make developers life easier when coding for this target board. + +* [Adc](GHI_FEZ_CERB40_NF.Adc.cs) +* [Gpio](GHI_FEZ_CERB40_NF.Gpio.cs) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/CMakeLists.txt new file mode 100644 index 00000000..291f47e1 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/CMakeLists.txt @@ -0,0 +1,9 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# # append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/STM32F405xG_booter-DEBUG.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/STM32F405xG_booter-DEBUG.ld new file mode 100644 index 00000000..740054ed --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/STM32F405xG_booter-DEBUG.ld @@ -0,0 +1,80 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F405xG memory setup. + * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash : org = 0x08000000, len = 32k /* space reserved for nanoBooter (1st two sectors 0x08000000 to 0x08008000)*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */ + ram1 : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Stacks rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/STM32F405xG_booter.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/STM32F405xG_booter.ld new file mode 100644 index 00000000..f79d8294 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/STM32F405xG_booter.ld @@ -0,0 +1,80 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F405xG memory setup. + * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash : org = 0x08000000, len = 16k /* space reserved for nanoBooter (1st two sectors 0x08000000 to 0x08004000)*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */ + ram1 : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Stacks rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/chconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/chconf.h new file mode 100644 index 00000000..335e3fa4 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/chconf.h @@ -0,0 +1,616 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 1000 // this is 1 millisecond + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#define CH_CFG_INTERVALS_SIZE 32 + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_TIME_TYPES_SIZE 32 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES FALSE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS FALSE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT FALSE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES FALSE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_OBJ_FIFOS TRUE + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#define CH_CFG_USE_FACTORY FALSE + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 + +/** + * @brief Enables the registry of generic objects. + */ +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE + +/** + * @brief Enables factory for generic buffers. + */ +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE + +/** + * @brief Enables factory for semaphores. + */ +#define CH_CFG_FACTORY_SEMAPHORES TRUE + +/** + * @brief Enables factory for mailboxes. + */ +#define CH_CFG_FACTORY_MAILBOXES TRUE + +/** + * @brief Enables factory for objects FIFOs. + */ +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/halconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/halconf.h new file mode 100644 index 00000000..b970c22f --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/halconf.h @@ -0,0 +1,513 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/halconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/halconf_nf.h new file mode 100644 index 00000000..809a6cfa --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/halconf_nf.h @@ -0,0 +1,15 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +#endif // _HALCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/main.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/main.c new file mode 100644 index 00000000..521b0f7e --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/main.c @@ -0,0 +1,76 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); + +// Application entry point. +int main(void) { + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init SWO as soon as possible to make it available to output ASAP + #if (SWO_OUTPUT == TRUE) + SwoInit(); + #endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + osDelay(20); // Let init stabilize + + // check for valid CLR image + if(CheckValidCLRImage((uint32_t)&__nanoImage_end__)) + { + // there seems to be a valid CLR image + // launch nanoCLR + LaunchCLR((uint32_t)&__nanoImage_end__); + } + + + // Initializes a serial-over-USB CDC driver. + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + // Activates the USB driver and then the USB bus pull-up on D+. + // Note, a delay is inserted in order to not have to disconnect the cable after a reset. + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1500); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // Normal main() thread + while (true) { + palSetPad(GPIOB, GPIOB_PIN5); + osDelay(500); + palClearPad(GPIOB, GPIOB_PIN5); + osDelay(500); + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/mcuconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/mcuconf.h new file mode 100644 index 00000000..5ed72f99 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/mcuconf.h @@ -0,0 +1,336 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF +#define STM32F405_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED FALSE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 6 +#define STM32_PLLN_VALUE 168 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV8 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSE +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_PLLI2S +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 250 +#define STM32_SDC_READ_TIMEOUT_MS 25 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/mcuconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/mcuconf_nf.h new file mode 100644 index 00000000..574b9636 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/mcuconf_nf.h @@ -0,0 +1,10 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/target_board.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/target_board.h.in new file mode 100644 index 00000000..19531d9c --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoBooter/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOBOOTER_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/CMakeLists.txt new file mode 100644 index 00000000..e5496b7e --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/STM32F405xG_CLR-DEBUG.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/STM32F405xG_CLR-DEBUG.ld new file mode 100644 index 00000000..d3630a67 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/STM32F405xG_CLR-DEBUG.ld @@ -0,0 +1,76 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F405xG memory setup. + * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash : org = 0x08008000, len = 1M - 32k - 768k /* flash size less the space reserved for nanoBooter and application deployment*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x08040000, len = 768k /* space reserved for application deployment */ + ramvt : org = 0x20000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */ + ram1 : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram4); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +INCLUDE rules.ld \ No newline at end of file diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/STM32F405xG_CLR.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/STM32F405xG_CLR.ld new file mode 100644 index 00000000..a9114720 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/STM32F405xG_CLR.ld @@ -0,0 +1,76 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F405xG memory setup. + * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash : org = 0x08004000, len = 1M - 16k - 768k /* flash size less the space reserved for nanoBooter and application deployment*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x08040000, len = 768k /* space reserved for application deployment */ + ramvt : org = 0x20000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */ + ram1 : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram4); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +INCLUDE rules.ld \ No newline at end of file diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/chconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/chconf.h new file mode 100644 index 00000000..390ce3a6 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/chconf.h @@ -0,0 +1,616 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 10000 + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#define CH_CFG_INTERVALS_SIZE 32 + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_TIME_TYPES_SIZE 32 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_OBJ_FIFOS TRUE + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#define CH_CFG_USE_FACTORY FALSE + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 + +/** + * @brief Enables the registry of generic objects. + */ +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE + +/** + * @brief Enables factory for generic buffers. + */ +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE + +/** + * @brief Enables factory for semaphores. + */ +#define CH_CFG_FACTORY_SEMAPHORES TRUE + +/** + * @brief Enables factory for mailboxes. + */ +#define CH_CFG_FACTORY_MAILBOXES TRUE + +/** + * @brief Enables factory for objects FIFOs. + */ +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/halconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/halconf.h new file mode 100644 index 00000000..a1e2b875 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/halconf.h @@ -0,0 +1,525 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +// #define HAL_USE_ADC TRUE +// #endif + +/** + * @brief Enables the CAN subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +// #define HAL_USE_CAN FALSE +// #endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +// /** +// * @brief Enables the DAC subsystem. +// */ +// #if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +// #define HAL_USE_DAC FALSE +// #endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +// this option is set at target_platform.h (from config file) +//#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +//#define HAL_USE_I2C TRUE +//#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +// #define HAL_USE_MAC TRUE +// #endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +// #define HAL_USE_PWM TRUE +// #endif + +/** + * @brief Enables the RTC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +// #define HAL_USE_RTC TRUE +// #endif + +/** + * @brief Enables the SDC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +// #define HAL_USE_SDC FALSE +// #endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + + +/** + * @brief Enables the SPI subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +// #define HAL_USE_SPI FALSE +// #endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +// #define HAL_USE_UART FALSE +// #endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +// #define HAL_USE_WDG FALSE +// #endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS TRUE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/halconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/halconf_nf.h new file mode 100644 index 00000000..6e46ee50 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/halconf_nf.h @@ -0,0 +1,20 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +// enables STM32 Can driver +#if !defined(HAL_USE_STM32_CAN) +#define HAL_USE_STM32_CAN FALSE +#endif + +#endif // _HALCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/main.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/main.c new file mode 100644 index 00000000..b6e22be3 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/main.c @@ -0,0 +1,74 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include "usbcfg.h" +#include +#include +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); +// declare CLRStartup thread here +osThreadDef(CLRStartupThread, osPriorityNormal, 4096, "CLRStartupThread"); + +// Application entry point. +int main(void) { + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init SWO as soon as possible to make it available to output ASAP + #if (SWO_OUTPUT == TRUE) + SwoInit(); + #endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // start watchdog + Watchdog_Init(); + + // Initializes a serial-over-USB CDC driver. + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + // Activates the USB driver and then the USB bus pull-up on D+. + // Note, a delay is inserted in order to not have to disconnect the cable after a reset + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1500); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // CLR settings to launch CLR thread + CLR_SETTINGS clrSettings; + (void)memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.EnterDebuggerLoopAfterExit = true; + + // create the CLR Startup thread + osThreadCreate(osThread(CLRStartupThread), &clrSettings); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + while (true) { + osDelay(100); + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/mcuconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/mcuconf.h new file mode 100644 index 00000000..7365203d --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/mcuconf.h @@ -0,0 +1,336 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF +#define STM32F405_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED FALSE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 6 +#define STM32_PLLN_VALUE 168 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV8 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSE +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 TRUE +#define STM32_ADC_USE_ADC3 TRUE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 TRUE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 TRUE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 TRUE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 TRUE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 250 +#define STM32_SDC_READ_TIMEOUT_MS 25 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 TRUE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 TRUE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG TRUE + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/mcuconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/mcuconf_nf.h new file mode 100644 index 00000000..574b9636 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/mcuconf_nf.h @@ -0,0 +1,10 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/nanoHAL.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/nanoHAL.cpp new file mode 100644 index 00000000..076a50fc --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/nanoHAL.cpp @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +void HAL_EnterBooterMode() +{ +} + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/target_board.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/target_board.h.in new file mode 100644 index 00000000..b980bc05 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/nanoCLR/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOCLR_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/resources/cerb40-top.PNG b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/resources/cerb40-top.PNG new file mode 100644 index 00000000..e0f346c7 Binary files /dev/null and b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/resources/cerb40-top.PNG differ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/resources/cerb40.jpg b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/resources/cerb40.jpg new file mode 100644 index 00000000..9bfd7367 Binary files /dev/null and b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/resources/cerb40.jpg differ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_BlockStorage.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_BlockStorage.c new file mode 100644 index 00000000..9e7c7f55 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_BlockStorage.c @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice STM32Flash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &STM32Flash_BlockStorageInterface, &Device_BlockStorageConfig, false); +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_BlockStorage.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_BlockStorage.h new file mode 100644 index 00000000..aa50b1b7 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_common.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_common.c new file mode 100644 index 00000000..c70f5865 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_common.c @@ -0,0 +1,31 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include "target_common.h" +#include + +HAL_SYSTEM_CONFIG HalSystemConfig = +{ + { true }, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, //ConvertCOM_DebugHandle(1), + 0, //ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + { RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size }, + { FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size } +}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; + +// this target uses DFU for updates +uint32_t GetTargetCapabilities() +{ + return TargetCapabilities_DfuUpdate; +}; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_common.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_common.h.in new file mode 100644 index 00000000..89d68da4 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_common.h.in @@ -0,0 +1,37 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x20000000) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x00020000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x08000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00100000) + +///////////////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////// +#define TARGETNAMESTRING "@CHIBIOS_BOARD@" +#define PLATFORMNAMESTRING "STM32F4" +/////////////////////////////////////////////// + +#endif /* _TARGET_COMMON_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_system_devices_dac_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_system_devices_dac_config.cpp new file mode 100644 index 00000000..88a70347 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_system_devices_dac_config.cpp @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_DAC_PORT_PIN_CHANNEL DacPortPinConfig[] = { + + // DAC1, channel 1, GPIO port A, pin 4 + {1, 1, GPIOA, 4}, + +}; + +const int DacChannelCount = ARRAYSIZE(DacPortPinConfig); diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_windows_devices_adc_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_windows_devices_adc_config.cpp new file mode 100644 index 00000000..cd9ed56a --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_windows_devices_adc_config.cpp @@ -0,0 +1,25 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_adc_native_target.h" + + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // ADC2 + {2, GPIOC, 0, ADC_CHANNEL_IN10}, + {2, GPIOC, 1, ADC_CHANNEL_IN11}, + + // ADC3 + {3, GPIOC, 2, ADC_CHANNEL_IN12}, + {3, GPIOC, 3, ADC_CHANNEL_IN13}, + + // these are the internal sources, available only at ADC1 + {1, NULL, 0, ADC_CHANNEL_SENSOR}, + {1, NULL, 0, ADC_CHANNEL_VREFINT}, + {1, NULL, 0, ADC_CHANNEL_VBAT}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_windows_devices_i2c_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_windows_devices_i2c_config.cpp new file mode 100644 index 00000000..534f821a --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_windows_devices_i2c_config.cpp @@ -0,0 +1,30 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_i2c_native_target.h" + +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for SCL pin is: GPIOB +// port for SDA pin is: GPIOB +// SCL pin: is GPIOB_8 +// SDA pin: is GPIOB_9 +// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, GPIOB, GPIOB, 8, 9, 4) + +////////// +// I2C2 // +////////// + +// pin configuration for I2C2 +// port for SCL pin is: GPIOB +// port for SDA pin is: GPIOB +// SCL pin: is GPIOB_10 +// SDA pin: is GPIOB_11 +// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(2, GPIOB, GPIOB, 10, 11, 4) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_windows_devices_serialcommunication_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_windows_devices_serialcommunication_config.cpp new file mode 100644 index 00000000..fe9517a6 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_windows_devices_serialcommunication_config.cpp @@ -0,0 +1,66 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_windows_devices_serialcommunication_config.h" +#include "win_dev_serial_native_target.h" + +/////////// +// UART1 // +/////////// + +// pin configuration for UART1 +// port: GPIOB +// TX pin: is GPIOB_6 +// RX pin: is GPIOB_7 +// GPIO alternate pin function is 7 (see "Table 9. Alternate function mapping" in STM32F405xx/STM32F407xx datasheet) +UART_CONFIG_PINS(1, GPIOB, GPIOB, 6, 7, 7) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart1_TxBuffer[UART1_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart1_RxBuffer[UART1_RX_SIZE]; + +// initialization for UART1 +UART_INIT(1, UART1_TX_SIZE, UART1_RX_SIZE) + +// un-initialization for UART1 +UART_UNINIT(1) + +/////////// +// UART2 // +/////////// + +// pin configuration for UART2 +// port: GPIOA +// TX pin: is GPIOA_2 +// RX pin: is GPIOA_3 +// GPIO alternate pin function is 7 (see "Table 9. Alternate function mapping" in STM32F405xx/STM32F407xx datasheet) +UART_CONFIG_PINS(2, GPIOA, GPIOA, 2, 3, 7) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart2_TxBuffer[UART2_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart2_RxBuffer[UART2_RX_SIZE]; + +// initialization for UART2 +UART_INIT(2, UART2_TX_SIZE, UART2_RX_SIZE) + +// un-initialization for UART2 +UART_UNINIT(2) + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_windows_devices_serialcommunication_config.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_windows_devices_serialcommunication_config.h new file mode 100644 index 00000000..dc1de238 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_windows_devices_serialcommunication_config.h @@ -0,0 +1,32 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +/////////// +// UART1 // +/////////// + +// enable USART1 +#define NF_SERIAL_COMM_STM32_UART_USE_USART1 TRUE + +// buffers size +// tx buffer size: 256 bytes +#define UART1_TX_SIZE 256 +// rx buffer size: 256 bytes +#define UART1_RX_SIZE 256 + + +/////////// +// UART2 // +/////////// + +// enable USART2 +#define NF_SERIAL_COMM_STM32_UART_USE_USART2 TRUE + +// buffers size +// tx buffer size: 1024 bytes +#define UART2_TX_SIZE 1024 +// rx buffer size: 1024 bytes +#define UART2_RX_SIZE 1024 diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_windows_devices_spi_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_windows_devices_spi_config.cpp new file mode 100644 index 00000000..ef2d3a10 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF/target_windows_devices_spi_config.cpp @@ -0,0 +1,10 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_spi_native.h" + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/CMakeLists.txt new file mode 100644 index 00000000..513bffbe --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/CMakeLists.txt @@ -0,0 +1,212 @@ +# +# Copyright (c) 2018 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +cmake_minimum_required(VERSION 3.0) +ENABLE_LANGUAGE(ASM) + +# add header files with common OS definitions and board definitions specific for each image +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/target_common.h" @ONLY) + +set(NANOBOOTER_PROJECT_NAME "nanoBooter") +set(NANOCLR_PROJECT_NAME "nanoCLR") + +find_package(BuildUtils REQUIRED) +find_package(CHIBIOS REQUIRED) +find_package(ChibiOSnfOverlay REQUIRED) +find_package(WireProtocol REQUIRED) + +# packages for nanoFramework libraries +####################################### +# mandatory +find_package(NF_CoreCLR REQUIRED) + +####################################### +# optional + +# ChibiOS contrib repo +if(CHIBIOS_CONTRIB_REQUIRED) + find_package(ChibiOS-Contrib REQUIRED) +endif() + +# nF feature: debugger +if(NF_FEATURE_DEBUGGER) + find_package(NF_Debugger REQUIRED) + find_package(NF_Diagnostics REQUIRED) +endif() + +# nF feature: networking +if(USE_NETWORKING_OPTION) + find_package(CHIBIOS_LWIP REQUIRED) +endif() + +# nF feature: filesystem +if(USE_FILESYSTEM_OPTION) + find_package(CHIBIOS_FATFS REQUIRED) +endif() + +####################################### + +add_subdirectory("common") +add_subdirectory("nanoBooter") +add_subdirectory("nanoCLR") + +####################### +# nanoBooter executable + +add_executable( + # executables for project, project sources + ${NANOBOOTER_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + "${CMAKE_CURRENT_SOURCE_DIR}/target_BlockStorage.c" + + # need to add configuration manager to allow get/store configuration blocks + "${PROJECT_SOURCE_DIR}/src/HAL/nanoHAL_ConfigurationManager_stubs.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOBOOTER_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOBOOTER_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOBOOTER_SOURCES} + + ${CHIBIOS_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} +) + +####################### +# nanoCLR executable + +add_executable( + # executables for project, project sources + ${NANOCLR_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOCLR_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOCLR_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOCLR_SOURCES} + + ${CHIBIOS_SOURCES} + ${CHIBIOS_CONTRIB_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} + + # sources for nanoFramework libraries + ${NF_CoreCLR_SOURCES} + ${NF_Debugger_SOURCES} + ${NF_Diagnostics_SOURCES} + + # sources for nanoFramework APIs + ${TARGET_NANO_APIS_SOURCES} +) + +# add dependency from ChibiOS (this is required to make sure the ChibiOS repo is downloaded before the build starts) +add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf ChibiOS) +add_dependencies(${NANOCLR_PROJECT_NAME}.elf ChibiOS) + +# include common directories +include_directories( + ${CMAKE_CURRENT_BINARY_DIR} + ${CMAKE_CURRENT_SOURCE_DIR} + ${CMAKE_CURRENT_SOURCE_DIR}/common + ${PROJECT_SOURCE_DIR}/src/CLR/Core + ${PROJECT_SOURCE_DIR}/src/CLR/Include + ${PROJECT_SOURCE_DIR}/src/HAL/Include + ${PROJECT_SOURCE_DIR}/src/PAL/Include + + ${WireProtocol_INCLUDE_DIRS} + ${CHIBIOS_INCLUDE_DIRS} + ${ChibiOSnfOverlay_INCLUDE_DIRS} + ${CHIBIOS_CONTRIB_INCLUDE_DIRS} + + ${TARGET_CMSIS_COMMON_INCLUDE_DIRS} + ${TARGET_CHIBIOS_COMMON_INCLUDE_DIRS} +) + +# include directories for nanoBooter +target_include_directories(${NANOBOOTER_PROJECT_NAME}.elf PUBLIC + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter" + ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter + + ${TARGET_CMSIS_NANOBOOTER_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOBOOTER_INCLUDE_DIRS} +) + +# include directories for nanoCLR +target_include_directories(${NANOCLR_PROJECT_NAME}.elf PUBLIC + ${CMAKE_CURRENT_BINARY_DIR}/nanoCLR + ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR + + ${TARGET_CMSIS_NANOCLR_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOCLR_INCLUDE_DIRS} + + # directories for nanoFramework libraries + ${NF_CoreCLR_INCLUDE_DIRS} + ${NF_Debugger_INCLUDE_DIRS} + ${NF_Diagnostics_INCLUDE_DIRS} + + # includes for nanoFramework APIs + ${TARGET_NANO_APIS_INCLUDES} + + # includes for ChibiOS LwIP + ${CHIBIOS_LWIP_INCLUDE_DIRS} +) + +# set compiler options +nf_set_compiler_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_options(${NANOCLR_PROJECT_NAME}.elf) + +# set compiler definitions +nf_set_compiler_definitions(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_definitions(${NANOCLR_PROJECT_NAME}.elf) + +# set linker file +nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F411xE_booter.ld) +nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/STM32F411xE_CLR.ld) + +# set linker options +nf_set_linker_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_linker_options(${NANOCLR_PROJECT_NAME}.elf) + +# add other linker flags +########################################################### +# the sizes of CRT heap and ChibiOS stacks are defined here +set_property(TARGET ${NANOBOOTER_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x400,--defsym=__crt_heap_size__=0x1000") +set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x2800") + +# generate output files +nf_generate_build_output_files(${NANOBOOTER_PROJECT_NAME}.elf) +nf_generate_build_output_files(${NANOCLR_PROJECT_NAME}.elf) + +# if HEX2DFU tool is available pack the binaries into a DFU package +if(HEX2DFU_TOOL_AVAILABLE) + + #################################################################################################### + ## when changing the linker file make sure to update the new addresses for the image files bellow ## + ## DO NOT use the leading 0x notation, just the address in plain hexadecimal formating ## + #################################################################################################### + NF_GENERATE_DFU_PACKAGE( + ${PROJECT_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin 08000000 + ${PROJECT_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin 08008000 + ${PROJECT_SOURCE_DIR}/build/nanoframework-4-electron.dfu + ) + +endif() diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/README.md b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/README.md new file mode 100644 index 00000000..b3735442 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/README.md @@ -0,0 +1,17 @@ + + +## Electron community board ## + +The board used in this community contribution is a STM32F411CEU6 based board from IngenuityMicro called Electron. The board has only 12 pins of which 3 are already used for 3.3V, 5V and GND, leaving use of only 9 pins. + +These pins can be used for: + +- 1 x TX/RX +- 4 x PWM +- 4 X ADC +- 1 x I2C +- 1 x SPI + +In addition, the board has two on-board LEDs connected to PA1 and PA8 and are tested for use as GPIO, PWM. + +Further information can be found on http://www.ingenuitymicro.com/products/electron/ where firmware, board layout and schema can be found. diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/board.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/board.c new file mode 100644 index 00000000..6f55c3bf --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/board.c @@ -0,0 +1,265 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) + gpio_setup_t PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_setup_t PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) + gpio_setup_t PKData; +#endif +} gpio_config_t; + +/** + * @brief STM32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +#endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB1(STM32_GPIO_EN_MASK); + rccEnableAHB1(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG + gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI + gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ + gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK + gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + * else. + */ +void __early_init(void) { + + stm32_gpio_init(); + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/board.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/board.h new file mode 100644 index 00000000..5d7f0d7c --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/board.h @@ -0,0 +1,1607 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This is the a board made by IngenuityMicro based upon MCU from ST + * the STM32F411CEU6. The board is equipped with both LSE and HSE. + * Details can be found on + * + * http://www.ingenuitymicro.com/products/electron/ + * + * for various firmware, board layout and schematic. + */ + +#ifndef BOARD_H +#define BOARD_H + +/* + * Setup for the IngenuityMicro Electron board based upon an STM32F411CEU6. + */ + +/* + * Board identifier. + */ +#define BOARD_I2M_ELECTRON_NF +#define BOARD_NAME "IngenuityMicro Electron" + +/* + * USB OTG Force + */ +#define BOARD_OTG_NOVBUSSENS + +/* + * Completely wacko definition of a flash sector here + */ +#define FLASH_SECTOR_11 ((uint32_t)11U) + +/* + * Board oscillators-related settings. + * NOTE: LSE is fitted and is of course 32768. + * NOTE: HSE is fitted and set to a 12 MHz one. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768U +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 12000000U +#endif + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U + +/* + * MCU type as defined in the ST header. + */ +#define STM32F411xE + +/* + * IO pins assignments. + */ +#define GPIOA_PIN0 0U +#define GPIOA_LED_GREEN 1U +#define GPIOA_PIN2 2U +#define GPIOA_PIN3 3U +#define GPIOA_ADC1_4 4U +#define GPIOA_ADC1_5 5U +#define GPIOA_PIN6 6U +#define GPIOA_PIN7 7U +#define GPIOA_LED_BLUE 8U +#define GPIOA_PIN9 9U +#define GPIOA_PIN10 10U +#define GPIOA_OTG_FS_DM 11U +#define GPIOA_OTG_FS_DP 12U +#define GPIOA_PIN13 13U +#define GPIOA_PIN14 14U +#define GPIOA_PIN15 15U + +#define GPIOB_PIN0 0U +#define GPIOB_PIN1 1U +#define GPIOB_PIN2 2U +#define GPIOB_SPI1_CLK 3U +#define GPIOB_SPI1_MISO 4U +#define GPIOB_SPI1_MOSI 5U +#define GPIOB_I2C1_SCL 6U +#define GPIOB_I2C1_SDA 7U +#define GPIOB_PIN8 8U +#define GPIOB_PIN9 9U +#define GPIOB_PIN10 10U +#define GPIOB_PIN11 11U +#define GPIOB_PIN12 12U +#define GPIOB_PIN13 13U +#define GPIOB_PIN14 14U +#define GPIOB_PIN15 15U + +#define GPIOC_PIN0 0U +#define GPIOC_PIN1 1U +#define GPIOC_PIN2 2U +#define GPIOC_PIN3 3U +#define GPIOC_PIN4 4U +#define GPIOC_PIN5 5U +#define GPIOC_PIN6 6U +#define GPIOC_PIN7 7U +#define GPIOC_PIN8 8U +#define GPIOC_PIN9 9U +#define GPIOC_PIN10 10U +#define GPIOC_PIN11 11U +#define GPIOC_PIN12 12U +#define GPIOC_PIN13 13U +#define GPIOC_PIN14 14U +#define GPIOC_PIN15 15U + +#define GPIOD_PIN0 0U +#define GPIOD_PIN1 1U +#define GPIOD_PIN2 2U +#define GPIOD_PIN3 3U +#define GPIOD_PIN4 4U +#define GPIOD_PIN5 5U +#define GPIOD_PIN6 6U +#define GPIOD_PIN7 7U +#define GPIOD_PIN8 8U +#define GPIOD_PIN9 9U +#define GPIOD_PIN10 10U +#define GPIOD_PIN11 11U +#define GPIOD_PIN12 12U +#define GPIOD_PIN13 13U +#define GPIOD_PIN14 14U +#define GPIOD_PIN15 15U + +#define GPIOE_PIN0 0U +#define GPIOE_PIN1 1U +#define GPIOE_PIN2 2U +#define GPIOE_PIN3 3U +#define GPIOE_PIN4 4U +#define GPIOE_PIN5 5U +#define GPIOE_PIN6 6U +#define GPIOE_PIN7 7U +#define GPIOE_PIN8 8U +#define GPIOE_PIN9 9U +#define GPIOE_PIN10 10U +#define GPIOE_PIN11 11U +#define GPIOE_PIN12 12U +#define GPIOE_PIN13 13U +#define GPIOE_PIN14 14U +#define GPIOE_PIN15 15U + +#define GPIOF_PIN0 0U +#define GPIOF_PIN1 1U +#define GPIOF_PIN2 2U +#define GPIOF_PIN3 3U +#define GPIOF_PIN4 4U +#define GPIOF_PIN5 5U +#define GPIOF_PIN6 6U +#define GPIOF_PIN7 7U +#define GPIOF_PIN8 8U +#define GPIOF_PIN9 9U +#define GPIOF_PIN10 10U +#define GPIOF_PIN11 11U +#define GPIOF_PIN12 12U +#define GPIOF_PIN13 13U +#define GPIOF_PIN14 14U +#define GPIOF_PIN15 15U + +#define GPIOG_PIN0 0U +#define GPIOG_PIN1 1U +#define GPIOG_PIN2 2U +#define GPIOG_PIN3 3U +#define GPIOG_PIN4 4U +#define GPIOG_PIN5 5U +#define GPIOG_PIN6 6U +#define GPIOG_PIN7 7U +#define GPIOG_PIN8 8U +#define GPIOG_PIN9 9U +#define GPIOG_PIN10 10U +#define GPIOG_PIN11 11U +#define GPIOG_PIN12 12U +#define GPIOG_PIN13 13U +#define GPIOG_PIN14 14U +#define GPIOG_PIN15 15U + +#define GPIOH_OSC_IN 0U +#define GPIOH_OSC_OUT 1U +#define GPIOH_PIN2 2U +#define GPIOH_PIN3 3U +#define GPIOH_PIN4 4U +#define GPIOH_PIN5 5U +#define GPIOH_PIN6 6U +#define GPIOH_PIN7 7U +#define GPIOH_PIN8 8U +#define GPIOH_PIN9 9U +#define GPIOH_PIN10 10U +#define GPIOH_PIN11 11U +#define GPIOH_PIN12 12U +#define GPIOH_PIN13 13U +#define GPIOH_PIN14 14U +#define GPIOH_PIN15 15U + +#define GPIOI_PIN0 0U +#define GPIOI_PIN1 1U +#define GPIOI_PIN2 2U +#define GPIOI_PIN3 3U +#define GPIOI_PIN4 4U +#define GPIOI_PIN5 5U +#define GPIOI_PIN6 6U +#define GPIOI_PIN7 7U +#define GPIOI_PIN8 8U +#define GPIOI_PIN9 9U +#define GPIOI_PIN10 10U +#define GPIOI_PIN11 11U +#define GPIOI_PIN12 12U +#define GPIOI_PIN13 13U +#define GPIOI_PIN14 14U +#define GPIOI_PIN15 15U + +#define GPIOJ_PIN0 0U +#define GPIOJ_PIN1 1U +#define GPIOJ_PIN2 2U +#define GPIOJ_PIN3 3U +#define GPIOJ_PIN4 4U +#define GPIOJ_PIN5 5U +#define GPIOJ_PIN6 6U +#define GPIOJ_PIN7 7U +#define GPIOJ_PIN8 8U +#define GPIOJ_PIN9 9U +#define GPIOJ_PIN10 10U +#define GPIOJ_PIN11 11U +#define GPIOJ_PIN12 12U +#define GPIOJ_PIN13 13U +#define GPIOJ_PIN14 14U +#define GPIOJ_PIN15 15U + +#define GPIOK_PIN0 0U +#define GPIOK_PIN1 1U +#define GPIOK_PIN2 2U +#define GPIOK_PIN3 3U +#define GPIOK_PIN4 4U +#define GPIOK_PIN5 5U +#define GPIOK_PIN6 6U +#define GPIOK_PIN7 7U +#define GPIOK_PIN8 8U +#define GPIOK_PIN9 9U +#define GPIOK_PIN10 10U +#define GPIOK_PIN11 11U +#define GPIOK_PIN12 12U +#define GPIOK_PIN13 13U +#define GPIOK_PIN14 14U +#define GPIOK_PIN15 15U + +/* + * IO lines assignments. + */ +#define LINE_LED_GREEN PAL_LINE(GPIOA, 1U) +#define LINE_PIN2 PAL_LINE(GPIOA, 2U) +#define LINE_PIN3 PAL_LINE(GPIOA, 3U) +#define LINE_PIN4 PAL_LINE(GPIOA, 4U) +#define LINE_LED_BLUE PAL_LINE(GPIOA, 8U) +#define LINE_OTG_FS_DM PAL_LINE(GPIOA, 11U) +#define LINE_OTG_FS_DP PAL_LINE(GPIOA, 12U) + +#define LINE_SPI1_CLK PAL_LINE(GPIOB, 3U) +#define LINE_SPI1_MISO PAL_LINE(GPIOB, 4U) +#define LINE_SPI1_MOSI PAL_LINE(GPIOB, 5U) +#define LINE_I2C1_SCL PAL_LINE(GPIOB, 6U) +#define LINE_I2C1_SDA PAL_LINE(GPIOB, 7U) + +#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) +#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) + +#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) +#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) + + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * GPIOA setup: + * + * PA0 - PIN0 (input pullup). + * PA1 - LED_GREEN (output pushpull high). + * PA2 - USART_TX (alternate 7). + * PA3 - USART_RX (alternate 7). + * PA4 - ADC1_4 (input analog). + * PA5 - ADC1_5 (input analog). + * PA6 - PIN6 (input pullup). + * PA7 - PIN7 (input pullup). + * PA8 - LED_BLUE (output pushpull high). + * PA9 - PIN9 (input pullup). + * PA10 - PIN10 (input pullup). + * PA11 - OTG_FS_DM (alternate 10). + * PA12 - OTG_FS_DP (alternate 10). + * PA13 - PIN13 (input pullup). + * PA14 - PIN14 (input pullup). + * PA15 - PIN15 (input pullup). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_PIN0) | \ + PIN_MODE_OUTPUT(GPIOA_LED_GREEN) | \ + PIN_MODE_ALTERNATE(GPIOA_PIN2) | \ + PIN_MODE_ALTERNATE(GPIOA_PIN3) | \ + PIN_MODE_ANALOG(GPIOA_ADC1_4) | \ + PIN_MODE_ANALOG(GPIOA_ADC1_5) | \ + PIN_MODE_INPUT(GPIOA_PIN6) | \ + PIN_MODE_INPUT(GPIOA_PIN7) | \ + PIN_MODE_OUTPUT(GPIOA_LED_BLUE) | \ + PIN_MODE_INPUT(GPIOA_PIN9) | \ + PIN_MODE_INPUT(GPIOA_PIN10) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ + PIN_MODE_INPUT(GPIOA_PIN13) | \ + PIN_MODE_INPUT(GPIOA_PIN14) | \ + PIN_MODE_INPUT(GPIOA_PIN15)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LED_GREEN) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ADC1_4) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ADC1_5) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LED_BLUE) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_PIN0) | \ + PIN_OSPEED_MEDIUM(GPIOA_LED_GREEN) | \ + PIN_OSPEED_HIGH(GPIOA_PIN2) | \ + PIN_OSPEED_HIGH(GPIOA_PIN3) | \ + PIN_OSPEED_HIGH(GPIOA_ADC1_4) | \ + PIN_OSPEED_HIGH(GPIOA_ADC1_5) | \ + PIN_OSPEED_HIGH(GPIOA_PIN6) | \ + PIN_OSPEED_HIGH(GPIOA_PIN7) | \ + PIN_OSPEED_MEDIUM(GPIOA_LED_BLUE) | \ + PIN_OSPEED_HIGH(GPIOA_PIN9) | \ + PIN_OSPEED_HIGH(GPIOA_PIN10) | \ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_OSPEED_HIGH(GPIOA_PIN13) | \ + PIN_OSPEED_HIGH(GPIOA_PIN14) | \ + PIN_OSPEED_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOA_LED_GREEN) | \ + PIN_PUPDR_FLOATING(GPIOA_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOA_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOA_ADC1_4) | \ + PIN_PUPDR_FLOATING(GPIOA_ADC1_5) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOA_LED_BLUE) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN15)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \ + PIN_ODR_LOW(GPIOA_LED_GREEN) | \ + PIN_ODR_LOW(GPIOA_PIN2) | \ + PIN_ODR_LOW(GPIOA_PIN3) | \ + PIN_ODR_LOW(GPIOA_ADC1_4) | \ + PIN_ODR_LOW(GPIOA_ADC1_5) | \ + PIN_ODR_HIGH(GPIOA_PIN6) | \ + PIN_ODR_HIGH(GPIOA_PIN7) | \ + PIN_ODR_LOW(GPIOA_LED_BLUE) | \ + PIN_ODR_HIGH(GPIOA_PIN9) | \ + PIN_ODR_HIGH(GPIOA_PIN10) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_ODR_HIGH(GPIOA_PIN13) | \ + PIN_ODR_HIGH(GPIOA_PIN14) | \ + PIN_ODR_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOA_LED_GREEN, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN2, 7U) | \ + PIN_AFIO_AF(GPIOA_PIN3, 7U) | \ + PIN_AFIO_AF(GPIOA_ADC1_4, 0U) | \ + PIN_AFIO_AF(GPIOA_ADC1_5, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN7, 0U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_LED_BLUE, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10U) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10U) | \ + PIN_AFIO_AF(GPIOA_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN15, 0U)) + +/* + * GPIOB setup: + * + * PB0 - PIN0 (input pullup). + * PB1 - PIN1 (input pullup). + * PB2 - PIN2 (input pullup). + * PB3 - SPI1_CLK (alternate 5). + * PB4 - SPI1_MISO (alternate 5). + * PB5 - SPI1_MOSI (alternate 5). + * PB6 - I2C1_SCL (alternate 4). + * PB7 - I2C1_SDA (alternate 4). + * PB8 - PIN8 (input pullup). + * PB9 - PIN9 (input pullup). + * PB10 - PIN10 (input pullup). + * PB11 - PIN11 (input pullup). + * PB12 - PIN12 (input pullup). + * PB13 - PIN13 (input pullup). + * PB14 - PIN14 (input pullup). + * PB15 - PIN15 (input pullup). + */ +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \ + PIN_MODE_INPUT(GPIOB_PIN1) | \ + PIN_MODE_INPUT(GPIOB_PIN2) | \ + PIN_MODE_ALTERNATE(GPIOB_SPI1_CLK) | \ + PIN_MODE_ALTERNATE(GPIOB_SPI1_MISO) | \ + PIN_MODE_ALTERNATE(GPIOB_SPI1_MOSI) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ + PIN_MODE_INPUT(GPIOB_PIN8) | \ + PIN_MODE_INPUT(GPIOB_PIN9) | \ + PIN_MODE_INPUT(GPIOB_PIN10) | \ + PIN_MODE_INPUT(GPIOB_PIN11) | \ + PIN_MODE_INPUT(GPIOB_PIN12) | \ + PIN_MODE_INPUT(GPIOB_PIN13) | \ + PIN_MODE_INPUT(GPIOB_PIN14) | \ + PIN_MODE_INPUT(GPIOB_PIN15)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SPI1_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SPI1_MISO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SPI1_MOSI) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_PIN0) | \ + PIN_OSPEED_HIGH(GPIOB_PIN1) | \ + PIN_OSPEED_HIGH(GPIOB_PIN2) | \ + PIN_OSPEED_HIGH(GPIOB_SPI1_CLK) | \ + PIN_OSPEED_HIGH(GPIOB_SPI1_MISO) | \ + PIN_OSPEED_HIGH(GPIOB_SPI1_MOSI) | \ + PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ + PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ + PIN_OSPEED_HIGH(GPIOB_PIN8) | \ + PIN_OSPEED_HIGH(GPIOB_PIN9) | \ + PIN_OSPEED_HIGH(GPIOB_PIN10) | \ + PIN_OSPEED_HIGH(GPIOB_PIN11) | \ + PIN_OSPEED_HIGH(GPIOB_PIN12) | \ + PIN_OSPEED_HIGH(GPIOB_PIN13) | \ + PIN_OSPEED_HIGH(GPIOB_PIN14) | \ + PIN_OSPEED_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOB_SPI1_CLK) | \ + PIN_PUPDR_FLOATING(GPIOB_SPI1_MISO) | \ + PIN_PUPDR_FLOATING(GPIOB_SPI1_MOSI) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN15)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ + PIN_ODR_HIGH(GPIOB_PIN1) | \ + PIN_ODR_HIGH(GPIOB_PIN2) | \ + PIN_ODR_LOW(GPIOB_SPI1_CLK) | \ + PIN_ODR_LOW(GPIOB_SPI1_MISO) | \ + PIN_ODR_LOW(GPIOB_SPI1_MOSI) | \ + PIN_ODR_LOW(GPIOB_I2C1_SCL) | \ + PIN_ODR_LOW(GPIOB_I2C1_SDA) | \ + PIN_ODR_HIGH(GPIOB_PIN8) | \ + PIN_ODR_HIGH(GPIOB_PIN9) | \ + PIN_ODR_HIGH(GPIOB_PIN10) | \ + PIN_ODR_HIGH(GPIOB_PIN11) | \ + PIN_ODR_HIGH(GPIOB_PIN12) | \ + PIN_ODR_HIGH(GPIOB_PIN13) | \ + PIN_ODR_HIGH(GPIOB_PIN14) | \ + PIN_ODR_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOB_SPI1_CLK, 5U) | \ + PIN_AFIO_AF(GPIOB_SPI1_MISO, 5U) | \ + PIN_AFIO_AF(GPIOB_SPI1_MOSI, 5U) | \ + PIN_AFIO_AF(GPIOB_I2C1_SCL, 4U) | \ + PIN_AFIO_AF(GPIOB_I2C1_SDA, 4U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN15, 0U)) + +/* + * GPIOC setup: + * + * PC0 - PIN0 (input pullup). + * PC1 - PIN1 (input pullup). + * PC2 - PIN2 (input pullup). + * PC3 - PIN3 (input pullup). + * PC4 - PIN4 (input pullup). + * PC5 - PIN5 (input pullup). + * PC6 - PIN6 (input pullup). + * PC7 - PIN7 (input pullup). + * PC8 - PIN8 (input pullup). + * PC9 - PIN9 (input pullup). + * PC10 - PIN10 (input pullup). + * PC11 - PIN11 (input pullup). + * PC12 - PIN12 (input pullup). + * PC13 - PIN13 (input pullup). + * PC14 - PIN14 (input pullup). + * PC15 - PIN15 (input pullup). + */ +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ + PIN_MODE_INPUT(GPIOC_PIN1) | \ + PIN_MODE_INPUT(GPIOC_PIN2) | \ + PIN_MODE_INPUT(GPIOC_PIN3) | \ + PIN_MODE_INPUT(GPIOC_PIN4) | \ + PIN_MODE_INPUT(GPIOC_PIN5) | \ + PIN_MODE_INPUT(GPIOC_PIN6) | \ + PIN_MODE_INPUT(GPIOC_PIN7) | \ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_INPUT(GPIOC_PIN9) | \ + PIN_MODE_INPUT(GPIOC_PIN10) | \ + PIN_MODE_INPUT(GPIOC_PIN11) | \ + PIN_MODE_INPUT(GPIOC_PIN12) | \ + PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_PIN14) | \ + PIN_MODE_INPUT(GPIOC_PIN15)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN15)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ + PIN_OSPEED_HIGH(GPIOC_PIN1) | \ + PIN_OSPEED_HIGH(GPIOC_PIN2) | \ + PIN_OSPEED_HIGH(GPIOC_PIN3) | \ + PIN_OSPEED_HIGH(GPIOC_PIN4) | \ + PIN_OSPEED_HIGH(GPIOC_PIN5) | \ + PIN_OSPEED_HIGH(GPIOC_PIN6) | \ + PIN_OSPEED_HIGH(GPIOC_PIN7) | \ + PIN_OSPEED_HIGH(GPIOC_PIN8) | \ + PIN_OSPEED_HIGH(GPIOC_PIN9) | \ + PIN_OSPEED_HIGH(GPIOC_PIN10) | \ + PIN_OSPEED_HIGH(GPIOC_PIN11) | \ + PIN_OSPEED_HIGH(GPIOC_PIN12) | \ + PIN_OSPEED_HIGH(GPIOC_PIN13) | \ + PIN_OSPEED_HIGH(GPIOC_PIN14) | \ + PIN_OSPEED_HIGH(GPIOC_PIN15)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN15)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ + PIN_ODR_HIGH(GPIOC_PIN1) | \ + PIN_ODR_HIGH(GPIOC_PIN2) | \ + PIN_ODR_HIGH(GPIOC_PIN3) | \ + PIN_ODR_HIGH(GPIOC_PIN4) | \ + PIN_ODR_HIGH(GPIOC_PIN5) | \ + PIN_ODR_HIGH(GPIOC_PIN6) | \ + PIN_ODR_HIGH(GPIOC_PIN7) | \ + PIN_ODR_HIGH(GPIOC_PIN8) | \ + PIN_ODR_HIGH(GPIOC_PIN9) | \ + PIN_ODR_HIGH(GPIOC_PIN10) | \ + PIN_ODR_HIGH(GPIOC_PIN11) | \ + PIN_ODR_HIGH(GPIOC_PIN12) | \ + PIN_ODR_HIGH(GPIOC_PIN13) | \ + PIN_ODR_HIGH(GPIOC_PIN14) | \ + PIN_ODR_HIGH(GPIOC_PIN15)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN7, 0U)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN15, 0U)) + +/* + * GPIOD setup: + * + * PD0 - PIN0 (input pullup). + * PD1 - PIN1 (input pullup). + * PD2 - PIN2 (input pullup). + * PD3 - PIN3 (input pullup). + * PD4 - PIN4 (input pullup). + * PD5 - PIN5 (input pullup). + * PD6 - PIN6 (input pullup). + * PD7 - PIN7 (input pullup). + * PD8 - PIN8 (input pullup). + * PD9 - PIN9 (input pullup). + * PD10 - PIN10 (input pullup). + * PD11 - PIN11 (input pullup). + * PD12 - PIN12 (input pullup). + * PD13 - PIN13 (input pullup). + * PD14 - PIN14 (input pullup). + * PD15 - PIN15 (input pullup). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ + PIN_MODE_INPUT(GPIOD_PIN1) | \ + PIN_MODE_INPUT(GPIOD_PIN2) | \ + PIN_MODE_INPUT(GPIOD_PIN3) | \ + PIN_MODE_INPUT(GPIOD_PIN4) | \ + PIN_MODE_INPUT(GPIOD_PIN5) | \ + PIN_MODE_INPUT(GPIOD_PIN6) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_INPUT(GPIOD_PIN8) | \ + PIN_MODE_INPUT(GPIOD_PIN9) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_PIN11) | \ + PIN_MODE_INPUT(GPIOD_PIN12) | \ + PIN_MODE_INPUT(GPIOD_PIN13) | \ + PIN_MODE_INPUT(GPIOD_PIN14) | \ + PIN_MODE_INPUT(GPIOD_PIN15)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ + PIN_OSPEED_HIGH(GPIOD_PIN1) | \ + PIN_OSPEED_HIGH(GPIOD_PIN2) | \ + PIN_OSPEED_HIGH(GPIOD_PIN3) | \ + PIN_OSPEED_HIGH(GPIOD_PIN4) | \ + PIN_OSPEED_HIGH(GPIOD_PIN5) | \ + PIN_OSPEED_HIGH(GPIOD_PIN6) | \ + PIN_OSPEED_HIGH(GPIOD_PIN7) | \ + PIN_OSPEED_HIGH(GPIOD_PIN8) | \ + PIN_OSPEED_HIGH(GPIOD_PIN9) | \ + PIN_OSPEED_HIGH(GPIOD_PIN10) | \ + PIN_OSPEED_HIGH(GPIOD_PIN11) | \ + PIN_OSPEED_HIGH(GPIOD_PIN12) | \ + PIN_OSPEED_HIGH(GPIOD_PIN13) | \ + PIN_OSPEED_HIGH(GPIOD_PIN14) | \ + PIN_OSPEED_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN15)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ + PIN_ODR_HIGH(GPIOD_PIN1) | \ + PIN_ODR_HIGH(GPIOD_PIN2) | \ + PIN_ODR_HIGH(GPIOD_PIN3) | \ + PIN_ODR_HIGH(GPIOD_PIN4) | \ + PIN_ODR_HIGH(GPIOD_PIN5) | \ + PIN_ODR_HIGH(GPIOD_PIN6) | \ + PIN_ODR_HIGH(GPIOD_PIN7) | \ + PIN_ODR_HIGH(GPIOD_PIN8) | \ + PIN_ODR_HIGH(GPIOD_PIN9) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_PIN11) | \ + PIN_ODR_HIGH(GPIOD_PIN12) | \ + PIN_ODR_HIGH(GPIOD_PIN13) | \ + PIN_ODR_HIGH(GPIOD_PIN14) | \ + PIN_ODR_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN15, 0U)) + +/* + * GPIOE setup: + * + * PE0 - PIN0 (input pullup). + * PE1 - PIN1 (input pullup). + * PE2 - PIN2 (input pullup). + * PE3 - PIN3 (input pullup). + * PE4 - PIN4 (input pullup). + * PE5 - PIN5 (input pullup). + * PE6 - PIN6 (input pullup). + * PE7 - PIN7 (input pullup). + * PE8 - PIN8 (input pullup). + * PE9 - PIN9 (input pullup). + * PE10 - PIN10 (input pullup). + * PE11 - PIN11 (input pullup). + * PE12 - PIN12 (input pullup). + * PE13 - PIN13 (input pullup). + * PE14 - PIN14 (input pullup). + * PE15 - PIN15 (input pullup). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ + PIN_MODE_INPUT(GPIOE_PIN1) | \ + PIN_MODE_INPUT(GPIOE_PIN2) | \ + PIN_MODE_INPUT(GPIOE_PIN3) | \ + PIN_MODE_INPUT(GPIOE_PIN4) | \ + PIN_MODE_INPUT(GPIOE_PIN5) | \ + PIN_MODE_INPUT(GPIOE_PIN6) | \ + PIN_MODE_INPUT(GPIOE_PIN7) | \ + PIN_MODE_INPUT(GPIOE_PIN8) | \ + PIN_MODE_INPUT(GPIOE_PIN9) | \ + PIN_MODE_INPUT(GPIOE_PIN10) | \ + PIN_MODE_INPUT(GPIOE_PIN11) | \ + PIN_MODE_INPUT(GPIOE_PIN12) | \ + PIN_MODE_INPUT(GPIOE_PIN13) | \ + PIN_MODE_INPUT(GPIOE_PIN14) | \ + PIN_MODE_INPUT(GPIOE_PIN15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ + PIN_OSPEED_HIGH(GPIOE_PIN1) | \ + PIN_OSPEED_HIGH(GPIOE_PIN2) | \ + PIN_OSPEED_HIGH(GPIOE_PIN3) | \ + PIN_OSPEED_HIGH(GPIOE_PIN4) | \ + PIN_OSPEED_HIGH(GPIOE_PIN5) | \ + PIN_OSPEED_HIGH(GPIOE_PIN6) | \ + PIN_OSPEED_HIGH(GPIOE_PIN7) | \ + PIN_OSPEED_HIGH(GPIOE_PIN8) | \ + PIN_OSPEED_HIGH(GPIOE_PIN9) | \ + PIN_OSPEED_HIGH(GPIOE_PIN10) | \ + PIN_OSPEED_HIGH(GPIOE_PIN11) | \ + PIN_OSPEED_HIGH(GPIOE_PIN12) | \ + PIN_OSPEED_HIGH(GPIOE_PIN13) | \ + PIN_OSPEED_HIGH(GPIOE_PIN14) | \ + PIN_OSPEED_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ + PIN_ODR_HIGH(GPIOE_PIN1) | \ + PIN_ODR_HIGH(GPIOE_PIN2) | \ + PIN_ODR_HIGH(GPIOE_PIN3) | \ + PIN_ODR_HIGH(GPIOE_PIN4) | \ + PIN_ODR_HIGH(GPIOE_PIN5) | \ + PIN_ODR_HIGH(GPIOE_PIN6) | \ + PIN_ODR_HIGH(GPIOE_PIN7) | \ + PIN_ODR_HIGH(GPIOE_PIN8) | \ + PIN_ODR_HIGH(GPIOE_PIN9) | \ + PIN_ODR_HIGH(GPIOE_PIN10) | \ + PIN_ODR_HIGH(GPIOE_PIN11) | \ + PIN_ODR_HIGH(GPIOE_PIN12) | \ + PIN_ODR_HIGH(GPIOE_PIN13) | \ + PIN_ODR_HIGH(GPIOE_PIN14) | \ + PIN_ODR_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN7, 0U)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN15, 0U)) + +/* + * GPIOF setup: + * + * PF0 - PIN0 (input pullup). + * PF1 - PIN1 (input pullup). + * PF2 - PIN2 (input pullup). + * PF3 - PIN3 (input pullup). + * PF4 - PIN4 (input pullup). + * PF5 - PIN5 (input pullup). + * PF6 - PIN6 (input pullup). + * PF7 - PIN7 (input pullup). + * PF8 - PIN8 (input pullup). + * PF9 - PIN9 (input pullup). + * PF10 - PIN10 (input pullup). + * PF11 - PIN11 (input pullup). + * PF12 - PIN12 (input pullup). + * PF13 - PIN13 (input pullup). + * PF14 - PIN14 (input pullup). + * PF15 - PIN15 (input pullup). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ + PIN_MODE_INPUT(GPIOF_PIN1) | \ + PIN_MODE_INPUT(GPIOF_PIN2) | \ + PIN_MODE_INPUT(GPIOF_PIN3) | \ + PIN_MODE_INPUT(GPIOF_PIN4) | \ + PIN_MODE_INPUT(GPIOF_PIN5) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_INPUT(GPIOF_PIN7) | \ + PIN_MODE_INPUT(GPIOF_PIN8) | \ + PIN_MODE_INPUT(GPIOF_PIN9) | \ + PIN_MODE_INPUT(GPIOF_PIN10) | \ + PIN_MODE_INPUT(GPIOF_PIN11) | \ + PIN_MODE_INPUT(GPIOF_PIN12) | \ + PIN_MODE_INPUT(GPIOF_PIN13) | \ + PIN_MODE_INPUT(GPIOF_PIN14) | \ + PIN_MODE_INPUT(GPIOF_PIN15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \ + PIN_OSPEED_HIGH(GPIOF_PIN1) | \ + PIN_OSPEED_HIGH(GPIOF_PIN2) | \ + PIN_OSPEED_HIGH(GPIOF_PIN3) | \ + PIN_OSPEED_HIGH(GPIOF_PIN4) | \ + PIN_OSPEED_HIGH(GPIOF_PIN5) | \ + PIN_OSPEED_HIGH(GPIOF_PIN6) | \ + PIN_OSPEED_HIGH(GPIOF_PIN7) | \ + PIN_OSPEED_HIGH(GPIOF_PIN8) | \ + PIN_OSPEED_HIGH(GPIOF_PIN9) | \ + PIN_OSPEED_HIGH(GPIOF_PIN10) | \ + PIN_OSPEED_HIGH(GPIOF_PIN11) | \ + PIN_OSPEED_HIGH(GPIOF_PIN12) | \ + PIN_OSPEED_HIGH(GPIOF_PIN13) | \ + PIN_OSPEED_HIGH(GPIOF_PIN14) | \ + PIN_OSPEED_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ + PIN_ODR_HIGH(GPIOF_PIN1) | \ + PIN_ODR_HIGH(GPIOF_PIN2) | \ + PIN_ODR_HIGH(GPIOF_PIN3) | \ + PIN_ODR_HIGH(GPIOF_PIN4) | \ + PIN_ODR_HIGH(GPIOF_PIN5) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_PIN7) | \ + PIN_ODR_HIGH(GPIOF_PIN8) | \ + PIN_ODR_HIGH(GPIOF_PIN9) | \ + PIN_ODR_HIGH(GPIOF_PIN10) | \ + PIN_ODR_HIGH(GPIOF_PIN11) | \ + PIN_ODR_HIGH(GPIOF_PIN12) | \ + PIN_ODR_HIGH(GPIOF_PIN13) | \ + PIN_ODR_HIGH(GPIOF_PIN14) | \ + PIN_ODR_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN7, 0U)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN15, 0U)) + +/* + * GPIOG setup: + * + * PG0 - PIN0 (input pullup). + * PG1 - PIN1 (input pullup). + * PG2 - PIN2 (input pullup). + * PG3 - PIN3 (input pullup). + * PG4 - PIN4 (input pullup). + * PG5 - PIN5 (input pullup). + * PG6 - PIN6 (input pullup). + * PG7 - PIN7 (input pullup). + * PG8 - PIN8 (input pullup). + * PG9 - PIN9 (input pullup). + * PG10 - PIN10 (input pullup). + * PG11 - PIN11 (input pullup). + * PG12 - PIN12 (input pullup). + * PG13 - PIN13 (input pullup). + * PG14 - PIN14 (input pullup). + * PG15 - PIN15 (input pullup). + */ +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \ + PIN_MODE_INPUT(GPIOG_PIN1) | \ + PIN_MODE_INPUT(GPIOG_PIN2) | \ + PIN_MODE_INPUT(GPIOG_PIN3) | \ + PIN_MODE_INPUT(GPIOG_PIN4) | \ + PIN_MODE_INPUT(GPIOG_PIN5) | \ + PIN_MODE_INPUT(GPIOG_PIN6) | \ + PIN_MODE_INPUT(GPIOG_PIN7) | \ + PIN_MODE_INPUT(GPIOG_PIN8) | \ + PIN_MODE_INPUT(GPIOG_PIN9) | \ + PIN_MODE_INPUT(GPIOG_PIN10) | \ + PIN_MODE_INPUT(GPIOG_PIN11) | \ + PIN_MODE_INPUT(GPIOG_PIN12) | \ + PIN_MODE_INPUT(GPIOG_PIN13) | \ + PIN_MODE_INPUT(GPIOG_PIN14) | \ + PIN_MODE_INPUT(GPIOG_PIN15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_PIN0) | \ + PIN_OSPEED_HIGH(GPIOG_PIN1) | \ + PIN_OSPEED_HIGH(GPIOG_PIN2) | \ + PIN_OSPEED_HIGH(GPIOG_PIN3) | \ + PIN_OSPEED_HIGH(GPIOG_PIN4) | \ + PIN_OSPEED_HIGH(GPIOG_PIN5) | \ + PIN_OSPEED_HIGH(GPIOG_PIN6) | \ + PIN_OSPEED_HIGH(GPIOG_PIN7) | \ + PIN_OSPEED_HIGH(GPIOG_PIN8) | \ + PIN_OSPEED_HIGH(GPIOG_PIN9) | \ + PIN_OSPEED_HIGH(GPIOG_PIN10) | \ + PIN_OSPEED_HIGH(GPIOG_PIN11) | \ + PIN_OSPEED_HIGH(GPIOG_PIN12) | \ + PIN_OSPEED_HIGH(GPIOG_PIN13) | \ + PIN_OSPEED_HIGH(GPIOG_PIN14) | \ + PIN_OSPEED_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ + PIN_ODR_HIGH(GPIOG_PIN1) | \ + PIN_ODR_HIGH(GPIOG_PIN2) | \ + PIN_ODR_HIGH(GPIOG_PIN3) | \ + PIN_ODR_HIGH(GPIOG_PIN4) | \ + PIN_ODR_HIGH(GPIOG_PIN5) | \ + PIN_ODR_HIGH(GPIOG_PIN6) | \ + PIN_ODR_HIGH(GPIOG_PIN7) | \ + PIN_ODR_HIGH(GPIOG_PIN8) | \ + PIN_ODR_HIGH(GPIOG_PIN9) | \ + PIN_ODR_HIGH(GPIOG_PIN10) | \ + PIN_ODR_HIGH(GPIOG_PIN11) | \ + PIN_ODR_HIGH(GPIOG_PIN12) | \ + PIN_ODR_HIGH(GPIOG_PIN13) | \ + PIN_ODR_HIGH(GPIOG_PIN14) | \ + PIN_ODR_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN7, 0U)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN15, 0U)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - PIN2 (input pullup). + * PH3 - PIN3 (input pullup). + * PH4 - PIN4 (input pullup). + * PH5 - PIN5 (input pullup). + * PH6 - PIN6 (input pullup). + * PH7 - PIN7 (input pullup). + * PH8 - PIN8 (input pullup). + * PH9 - PIN9 (input pullup). + * PH10 - PIN10 (input pullup). + * PH11 - PIN11 (input pullup). + * PH12 - PIN12 (input pullup). + * PH13 - PIN13 (input pullup). + * PH14 - PIN14 (input pullup). + * PH15 - PIN15 (input pullup). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOH_PIN2) | \ + PIN_MODE_INPUT(GPIOH_PIN3) | \ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_INPUT(GPIOH_PIN5) | \ + PIN_MODE_INPUT(GPIOH_PIN6) | \ + PIN_MODE_INPUT(GPIOH_PIN7) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ + PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ + PIN_OSPEED_HIGH(GPIOH_PIN2) | \ + PIN_OSPEED_HIGH(GPIOH_PIN3) | \ + PIN_OSPEED_HIGH(GPIOH_PIN4) | \ + PIN_OSPEED_HIGH(GPIOH_PIN5) | \ + PIN_OSPEED_HIGH(GPIOH_PIN6) | \ + PIN_OSPEED_HIGH(GPIOH_PIN7) | \ + PIN_OSPEED_HIGH(GPIOH_PIN8) | \ + PIN_OSPEED_HIGH(GPIOH_PIN9) | \ + PIN_OSPEED_HIGH(GPIOH_PIN10) | \ + PIN_OSPEED_HIGH(GPIOH_PIN11) | \ + PIN_OSPEED_HIGH(GPIOH_PIN12) | \ + PIN_OSPEED_HIGH(GPIOH_PIN13) | \ + PIN_OSPEED_HIGH(GPIOH_PIN14) | \ + PIN_OSPEED_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0U)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0U)) + +/* + * GPIOI setup: + * + * PI0 - PIN0 (input pullup). + * PI1 - PIN1 (input pullup). + * PI2 - PIN2 (input pullup). + * PI3 - PIN3 (input pullup). + * PI4 - PIN4 (input pullup). + * PI5 - PIN5 (input pullup). + * PI6 - PIN6 (input pullup). + * PI7 - PIN7 (input pullup). + * PI8 - PIN8 (input pullup). + * PI9 - PIN9 (input pullup). + * PI10 - PIN10 (input pullup). + * PI11 - PIN11 (input pullup). + * PI12 - PIN12 (input pullup). + * PI13 - PIN13 (input pullup). + * PI14 - PIN14 (input pullup). + * PI15 - PIN15 (input pullup). + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ + PIN_MODE_INPUT(GPIOI_PIN1) | \ + PIN_MODE_INPUT(GPIOI_PIN2) | \ + PIN_MODE_INPUT(GPIOI_PIN3) | \ + PIN_MODE_INPUT(GPIOI_PIN4) | \ + PIN_MODE_INPUT(GPIOI_PIN5) | \ + PIN_MODE_INPUT(GPIOI_PIN6) | \ + PIN_MODE_INPUT(GPIOI_PIN7) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_INPUT(GPIOI_PIN9) | \ + PIN_MODE_INPUT(GPIOI_PIN10) | \ + PIN_MODE_INPUT(GPIOI_PIN11) | \ + PIN_MODE_INPUT(GPIOI_PIN12) | \ + PIN_MODE_INPUT(GPIOI_PIN13) | \ + PIN_MODE_INPUT(GPIOI_PIN14) | \ + PIN_MODE_INPUT(GPIOI_PIN15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_HIGH(GPIOI_PIN0) | \ + PIN_OSPEED_HIGH(GPIOI_PIN1) | \ + PIN_OSPEED_HIGH(GPIOI_PIN2) | \ + PIN_OSPEED_HIGH(GPIOI_PIN3) | \ + PIN_OSPEED_HIGH(GPIOI_PIN4) | \ + PIN_OSPEED_HIGH(GPIOI_PIN5) | \ + PIN_OSPEED_HIGH(GPIOI_PIN6) | \ + PIN_OSPEED_HIGH(GPIOI_PIN7) | \ + PIN_OSPEED_HIGH(GPIOI_PIN8) | \ + PIN_OSPEED_HIGH(GPIOI_PIN9) | \ + PIN_OSPEED_HIGH(GPIOI_PIN10) | \ + PIN_OSPEED_HIGH(GPIOI_PIN11) | \ + PIN_OSPEED_HIGH(GPIOI_PIN12) | \ + PIN_OSPEED_HIGH(GPIOI_PIN13) | \ + PIN_OSPEED_HIGH(GPIOI_PIN14) | \ + PIN_OSPEED_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ + PIN_ODR_HIGH(GPIOI_PIN1) | \ + PIN_ODR_HIGH(GPIOI_PIN2) | \ + PIN_ODR_HIGH(GPIOI_PIN3) | \ + PIN_ODR_HIGH(GPIOI_PIN4) | \ + PIN_ODR_HIGH(GPIOI_PIN5) | \ + PIN_ODR_HIGH(GPIOI_PIN6) | \ + PIN_ODR_HIGH(GPIOI_PIN7) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_PIN9) | \ + PIN_ODR_HIGH(GPIOI_PIN10) | \ + PIN_ODR_HIGH(GPIOI_PIN11) | \ + PIN_ODR_HIGH(GPIOI_PIN12) | \ + PIN_ODR_HIGH(GPIOI_PIN13) | \ + PIN_ODR_HIGH(GPIOI_PIN14) | \ + PIN_ODR_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN7, 0U)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN15, 0U)) + +/* + * GPIOJ setup: + * + * PJ0 - PIN0 (input floating). + * PJ1 - PIN1 (input floating). + * PJ2 - PIN2 (input floating). + * PJ3 - PIN3 (input floating). + * PJ4 - PIN4 (input floating). + * PJ5 - PIN5 (input floating). + * PJ6 - PIN6 (input floating). + * PJ7 - PIN7 (input floating). + * PJ8 - PIN8 (input floating). + * PJ9 - PIN9 (input floating). + * PJ10 - PIN10 (input floating). + * PJ11 - PIN11 (input floating). + * PJ12 - PIN12 (input floating). + * PJ13 - PIN13 (input floating). + * PJ14 - PIN14 (input floating). + * PJ15 - PIN15 (input floating). + */ +#define VAL_GPIOJ_MODER (PIN_MODE_INPUT(GPIOJ_PIN0) | \ + PIN_MODE_INPUT(GPIOJ_PIN1) | \ + PIN_MODE_INPUT(GPIOJ_PIN2) | \ + PIN_MODE_INPUT(GPIOJ_PIN3) | \ + PIN_MODE_INPUT(GPIOJ_PIN4) | \ + PIN_MODE_INPUT(GPIOJ_PIN5) | \ + PIN_MODE_INPUT(GPIOJ_PIN6) | \ + PIN_MODE_INPUT(GPIOJ_PIN7) | \ + PIN_MODE_INPUT(GPIOJ_PIN8) | \ + PIN_MODE_INPUT(GPIOJ_PIN9) | \ + PIN_MODE_INPUT(GPIOJ_PIN10) | \ + PIN_MODE_INPUT(GPIOJ_PIN11) | \ + PIN_MODE_INPUT(GPIOJ_PIN12) | \ + PIN_MODE_INPUT(GPIOJ_PIN13) | \ + PIN_MODE_INPUT(GPIOJ_PIN14) | \ + PIN_MODE_INPUT(GPIOJ_PIN15)) +#define VAL_GPIOJ_OTYPER (PIN_OTYPE_PUSHPULL(GPIOJ_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN15)) +#define VAL_GPIOJ_OSPEEDR (PIN_OSPEED_HIGH(GPIOJ_PIN0) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN1) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN2) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN3) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN4) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN5) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN6) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN7) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN8) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN9) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN10) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN11) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN12) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN13) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN14) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN15)) +#define VAL_GPIOJ_PUPDR (PIN_PUPDR_FLOATING(GPIOJ_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN15)) +#define VAL_GPIOJ_ODR (PIN_ODR_HIGH(GPIOJ_PIN0) | \ + PIN_ODR_HIGH(GPIOJ_PIN1) | \ + PIN_ODR_HIGH(GPIOJ_PIN2) | \ + PIN_ODR_HIGH(GPIOJ_PIN3) | \ + PIN_ODR_HIGH(GPIOJ_PIN4) | \ + PIN_ODR_HIGH(GPIOJ_PIN5) | \ + PIN_ODR_HIGH(GPIOJ_PIN6) | \ + PIN_ODR_HIGH(GPIOJ_PIN7) | \ + PIN_ODR_HIGH(GPIOJ_PIN8) | \ + PIN_ODR_HIGH(GPIOJ_PIN9) | \ + PIN_ODR_HIGH(GPIOJ_PIN10) | \ + PIN_ODR_HIGH(GPIOJ_PIN11) | \ + PIN_ODR_HIGH(GPIOJ_PIN12) | \ + PIN_ODR_HIGH(GPIOJ_PIN13) | \ + PIN_ODR_HIGH(GPIOJ_PIN14) | \ + PIN_ODR_HIGH(GPIOJ_PIN15)) +#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(GPIOJ_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN7, 0U)) +#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(GPIOJ_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN15, 0U)) + +/* + * GPIOK setup: + * + * PK0 - PIN0 (input floating). + * PK1 - PIN1 (input floating). + * PK2 - PIN2 (input floating). + * PK3 - PIN3 (input floating). + * PK4 - PIN4 (input floating). + * PK5 - PIN5 (input floating). + * PK6 - PIN6 (input floating). + * PK7 - PIN7 (input floating). + * PK8 - PIN8 (input floating). + * PK9 - PIN9 (input floating). + * PK10 - PIN10 (input floating). + * PK11 - PIN11 (input floating). + * PK12 - PIN12 (input floating). + * PK13 - PIN13 (input floating). + * PK14 - PIN14 (input floating). + * PK15 - PIN15 (input floating). + */ +#define VAL_GPIOK_MODER (PIN_MODE_INPUT(GPIOK_PIN0) | \ + PIN_MODE_INPUT(GPIOK_PIN1) | \ + PIN_MODE_INPUT(GPIOK_PIN2) | \ + PIN_MODE_INPUT(GPIOK_PIN3) | \ + PIN_MODE_INPUT(GPIOK_PIN4) | \ + PIN_MODE_INPUT(GPIOK_PIN5) | \ + PIN_MODE_INPUT(GPIOK_PIN6) | \ + PIN_MODE_INPUT(GPIOK_PIN7) | \ + PIN_MODE_INPUT(GPIOK_PIN8) | \ + PIN_MODE_INPUT(GPIOK_PIN9) | \ + PIN_MODE_INPUT(GPIOK_PIN10) | \ + PIN_MODE_INPUT(GPIOK_PIN11) | \ + PIN_MODE_INPUT(GPIOK_PIN12) | \ + PIN_MODE_INPUT(GPIOK_PIN13) | \ + PIN_MODE_INPUT(GPIOK_PIN14) | \ + PIN_MODE_INPUT(GPIOK_PIN15)) +#define VAL_GPIOK_OTYPER (PIN_OTYPE_PUSHPULL(GPIOK_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN15)) +#define VAL_GPIOK_OSPEEDR (PIN_OSPEED_HIGH(GPIOK_PIN0) | \ + PIN_OSPEED_HIGH(GPIOK_PIN1) | \ + PIN_OSPEED_HIGH(GPIOK_PIN2) | \ + PIN_OSPEED_HIGH(GPIOK_PIN3) | \ + PIN_OSPEED_HIGH(GPIOK_PIN4) | \ + PIN_OSPEED_HIGH(GPIOK_PIN5) | \ + PIN_OSPEED_HIGH(GPIOK_PIN6) | \ + PIN_OSPEED_HIGH(GPIOK_PIN7) | \ + PIN_OSPEED_HIGH(GPIOK_PIN8) | \ + PIN_OSPEED_HIGH(GPIOK_PIN9) | \ + PIN_OSPEED_HIGH(GPIOK_PIN10) | \ + PIN_OSPEED_HIGH(GPIOK_PIN11) | \ + PIN_OSPEED_HIGH(GPIOK_PIN12) | \ + PIN_OSPEED_HIGH(GPIOK_PIN13) | \ + PIN_OSPEED_HIGH(GPIOK_PIN14) | \ + PIN_OSPEED_HIGH(GPIOK_PIN15)) +#define VAL_GPIOK_PUPDR (PIN_PUPDR_FLOATING(GPIOK_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN15)) +#define VAL_GPIOK_ODR (PIN_ODR_HIGH(GPIOK_PIN0) | \ + PIN_ODR_HIGH(GPIOK_PIN1) | \ + PIN_ODR_HIGH(GPIOK_PIN2) | \ + PIN_ODR_HIGH(GPIOK_PIN3) | \ + PIN_ODR_HIGH(GPIOK_PIN4) | \ + PIN_ODR_HIGH(GPIOK_PIN5) | \ + PIN_ODR_HIGH(GPIOK_PIN6) | \ + PIN_ODR_HIGH(GPIOK_PIN7) | \ + PIN_ODR_HIGH(GPIOK_PIN8) | \ + PIN_ODR_HIGH(GPIOK_PIN9) | \ + PIN_ODR_HIGH(GPIOK_PIN10) | \ + PIN_ODR_HIGH(GPIOK_PIN11) | \ + PIN_ODR_HIGH(GPIOK_PIN12) | \ + PIN_ODR_HIGH(GPIOK_PIN13) | \ + PIN_ODR_HIGH(GPIOK_PIN14) | \ + PIN_ODR_HIGH(GPIOK_PIN15)) +#define VAL_GPIOK_AFRL (PIN_AFIO_AF(GPIOK_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN7, 0U)) +#define VAL_GPIOK_AFRH (PIN_AFIO_AF(GPIOK_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN15, 0U)) + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/common/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/common/CMakeLists.txt new file mode 100644 index 00000000..db80e7ce --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/common/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/usbcfg.c") +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage.c") + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/common/Device_BlockStorage.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/common/Device_BlockStorage.c new file mode 100644 index 00000000..b4ccd595 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/common/Device_BlockStorage.c @@ -0,0 +1,94 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 1 }, // 08000000 nanoBooter + { BlockRange_BLOCKTYPE_CODE , 2, 3 } // 08008000 nanoCLR +}; + +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 08010000 nanoCLR +}; + +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 1 }, // 08020000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 2, 5 } // 08040000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08010000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 6, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00080000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/common/usbcfg.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/common/usbcfg.c new file mode 100644 index 00000000..a048c76f --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/common/usbcfg.c @@ -0,0 +1,435 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "hal.h" + +/* Virtual serial port over USB.*/ +SerialUSBDriver SDU1; + +/* + * Endpoints to be used for USBD1. + */ +#define USBD1_DATA_REQUEST_EP 1 +#define USBD1_DATA_AVAILABLE_EP 1 +#define USBD1_INTERRUPT_REQUEST_EP 2 + +// address for device unique ID +// valid for STM32F4 series +#define DEVICE_ID1 (0x1FFF7A10) +#define DEVICE_ID2 (0x1FFF7A14) +#define DEVICE_ID3 (0x1FFF7A18) + +// // size of string serial is 36 = 2 + 5x2 + 26 from silicon unique ID precedeed of string "NANO_" and descriptor codes +// #define USB_SIZ_STRING_SERIAL 36 + +//////////////////////////////////////////////// +// vendor +#define USB_STRING_VENDOR L"STMicroelectronics" +//////////////////////////////////////////////// + +// structure for USB Vendor with Unicode string +typedef struct usb_string_vendor +{ + uint8_t bLength; + uint8_t bDescriptorType; + wchar_t bPropertyData[sizeof(USB_STRING_VENDOR)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec) + +}usb_string_vendor; + + +///////////////////////////////////////////////////////////////////////// +// device description +#define USB_STRING_DEVICE_DESCRIPTION L"nanoFramework Virtual COM Port" +///////////////////////////////////////////////////////////////////////// + +// structure for USB device descriptor with Unicode string +typedef struct usb_string_device_description +{ + uint8_t bLength; + uint8_t bDescriptorType; + wchar_t bPropertyData[sizeof(USB_STRING_DEVICE_DESCRIPTION)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec) + +}usb_string_device_description; + + +///////////////////////////////////////////////////////////////////////// +// device serial number +// this will produce a string with NANO_ prefix followed +// by the hexadecimal representation of the silicon unique ID of the CPU +#define USB_STRING_SERIAL_NUMBER L"NANO_xxxxxxxxxxx" +///////////////////////////////////////////////////////////////////////// +#define INDEX_OF_WCHAR_FOR_UNIQUE_ID 5 + +// structure for USB serial number descriptor with Unicode string +typedef struct usb_string_serial_number +{ + uint8_t bLength; + uint8_t bDescriptorType; + wchar_t bPropertyData[sizeof(USB_STRING_SERIAL_NUMBER)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec) + +}usb_string_serial_number; + + +/* + * USB Device Descriptor. + */ +static const uint8_t vcom_device_descriptor_data[18] = { + USB_DESC_DEVICE (0x0200, /* bcdUSB (2.0). */ + 0x02, /* bDeviceClass (CDC). */ + 0x00, /* bDeviceSubClass. */ + 0x00, /* bDeviceProtocol. */ + 0x40, /* bMaxPacketSize. */ + 0x0483, /* idVendor (ST). */ + 0x5740, /* idProduct. */ + 0x0200, /* bcdDevice. */ + 1, /* iManufacturer. */ + 2, /* iProduct. */ + 3, /* iSerialNumber. */ + 1) /* bNumConfigurations. */ +}; + +/* + * Device Descriptor wrapper. + */ +static const USBDescriptor vcom_device_descriptor = { + sizeof vcom_device_descriptor_data, + vcom_device_descriptor_data +}; + +/* Configuration Descriptor tree for a CDC.*/ +static const uint8_t vcom_configuration_descriptor_data[67] = { + /* Configuration Descriptor.*/ + USB_DESC_CONFIGURATION(67, /* wTotalLength. */ + 0x02, /* bNumInterfaces. */ + 0x01, /* bConfigurationValue. */ + 0, /* iConfiguration. */ + 0xC0, /* bmAttributes (self powered). */ + 50), /* bMaxPower (100mA). */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x01, /* bNumEndpoints. */ + 0x02, /* bInterfaceClass (Communications + Interface Class, CDC section + 4.2). */ + 0x02, /* bInterfaceSubClass (Abstract + Control Model, CDC section 4.3). */ + 0x01, /* bInterfaceProtocol (AT commands, + CDC section 4.4). */ + 0), /* iInterface. */ + /* Header Functional Descriptor (CDC section 5.2.3).*/ + USB_DESC_BYTE (5), /* bLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header + Functional Descriptor. */ + USB_DESC_BCD (0x0110), /* bcdCDC. */ + /* Call Management Functional Descriptor. */ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */ + USB_DESC_BYTE (0x01), /* bDataInterface. */ + /* ACM Functional Descriptor.*/ + USB_DESC_BYTE (4), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract + Control Management Descriptor). */ + USB_DESC_BYTE (0x02), /* bmCapabilities. */ + /* Union Functional Descriptor.*/ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bMasterInterface (Communication + Class Interface). */ + USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class + Interface). */ + /* Endpoint 2 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_INTERRUPT_REQUEST_EP|0x80, + 0x03, /* bmAttributes (Interrupt). */ + 0x0008, /* wMaxPacketSize. */ + 0xFF), /* bInterval. */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x02, /* bNumEndpoints. */ + 0x0A, /* bInterfaceClass (Data Class + Interface, CDC section 4.5). */ + 0x00, /* bInterfaceSubClass (CDC section + 4.6). */ + 0x00, /* bInterfaceProtocol (CDC section + 4.7). */ + 0x00), /* iInterface. */ + /* Endpoint 3 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_AVAILABLE_EP, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00), /* bInterval. */ + /* Endpoint 1 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00) /* bInterval. */ +}; + +/* + * Configuration Descriptor wrapper. + */ +static const USBDescriptor vcom_configuration_descriptor = { + sizeof vcom_configuration_descriptor_data, + vcom_configuration_descriptor_data +}; + +/* + * U.S. English language identifier. + */ +static const uint8_t vcom_string0[] = { + USB_DESC_BYTE(4), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */ +}; + + +// Vendor string +static const usb_string_vendor usb_vendor = { + sizeof(usb_vendor), + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), + USB_STRING_VENDOR +}; + + +// Device Description string +static const usb_string_device_description usb_device_description = { + sizeof(usb_device_description), + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), + USB_STRING_DEVICE_DESCRIPTION +}; + + +// Serial Number string. +static usb_string_serial_number usb_serial_number = { + sizeof(usb_serial_number), + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), + USB_STRING_SERIAL_NUMBER +}; + + +/* + * Strings wrappers array. + */ +static const USBDescriptor vcom_strings[] = { + {sizeof vcom_string0, vcom_string0}, + {sizeof usb_vendor, (uint8_t*)(&usb_vendor)}, + {sizeof usb_device_description, (uint8_t*)(&usb_device_description)}, + {sizeof usb_serial_number, (uint8_t*)(&usb_serial_number)}, +}; + + +// Convert Hex 32Bits value into char +// value: value to convert +// pbuf: pointer to the buffer +// len: buffer length +void IntToUnicode(uint32_t value , uint8_t *pbuf, uint8_t len) +{ + uint8_t idx = 0; + + for( idx = 0; idx < len; idx ++) + { + if( ((value >> 28)) < 0xA ) + { + pbuf[ 2* idx] = (value >> 28) + '0'; + } + else + { + pbuf[2* idx] = (value >> 28) + 'A' - 10; + } + + value = value << 4; + + pbuf[ 2* idx + 1] = 0; + } +} + +// Create the serial number string descriptor +void Get_SerialNum(uint8_t* pbuf) +{ + uint32_t deviceserial0, deviceserial1, deviceserial2; + + deviceserial0 = *(uint32_t*)DEVICE_ID1; + deviceserial1 = *(uint32_t*)DEVICE_ID2; + deviceserial2 = *(uint32_t*)DEVICE_ID3; + + deviceserial0 += deviceserial2; + + if (deviceserial0 != 0) + { + IntToUnicode(deviceserial0, pbuf, 8); + pbuf += 16; + IntToUnicode(deviceserial1, pbuf, 4); + } +} + +/* + * Handles the GET_DESCRIPTOR callback. All required descriptors must be + * handled here. + */ +static const USBDescriptor *get_descriptor(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang) { + + (void)usbp; + (void)lang; + + switch (dtype) { + case USB_DESCRIPTOR_DEVICE: + return &vcom_device_descriptor; + case USB_DESCRIPTOR_CONFIGURATION: + return &vcom_configuration_descriptor; + case USB_DESCRIPTOR_STRING: + if (dindex < 4) + { + if(dindex == 3) + { + // request is for serial number + // get it from the silicon unique ID + Get_SerialNum((uint8_t*)&usb_serial_number.bPropertyData[INDEX_OF_WCHAR_FOR_UNIQUE_ID]); + } + + return &vcom_strings[dindex]; + } + } + return NULL; +} + +/** + * @brief IN EP1 state. + */ +static USBInEndpointState ep1instate; + +/** + * @brief OUT EP1 state. + */ +static USBOutEndpointState ep1outstate; + +/** + * @brief EP1 initialization structure (both IN and OUT). + */ +static const USBEndpointConfig ep1config = { + USB_EP_MODE_TYPE_BULK, + NULL, + sduDataTransmitted, + sduDataReceived, + 0x0040, + 0x0040, + &ep1instate, + &ep1outstate, + 2, + NULL +}; + +/** + * @brief IN EP2 state. + */ +static USBInEndpointState ep2instate; + +/** + * @brief EP2 initialization structure (IN only). + */ +static const USBEndpointConfig ep2config = { + USB_EP_MODE_TYPE_INTR, + NULL, + sduInterruptTransmitted, + NULL, + 0x0010, + 0x0000, + &ep2instate, + NULL, + 1, + NULL +}; + +/* + * Handles the USB driver global events. + */ +static void usb_event(USBDriver *usbp, usbevent_t event) { + extern SerialUSBDriver SDU1; + + switch (event) { + case USB_EVENT_ADDRESS: + return; + case USB_EVENT_CONFIGURED: + chSysLockFromISR(); + + /* Enables the endpoints specified into the configuration. + Note, this callback is invoked from an ISR so I-Class functions + must be used.*/ + usbInitEndpointI(usbp, USBD1_DATA_REQUEST_EP, &ep1config); + usbInitEndpointI(usbp, USBD1_INTERRUPT_REQUEST_EP, &ep2config); + + /* Resetting the state of the CDC subsystem.*/ + sduConfigureHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_RESET: + /* Falls into.*/ + case USB_EVENT_UNCONFIGURED: + /* Falls into.*/ + case USB_EVENT_SUSPEND: + chSysLockFromISR(); + + /* Disconnection event on suspend.*/ + sduSuspendHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_WAKEUP: + chSysLockFromISR(); + + /* Disconnection event on suspend.*/ + sduWakeupHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_STALLED: + return; + } + return; +} + +/* + * Handles the USB driver global events. + */ +static void sof_handler(USBDriver *usbp) { + + (void)usbp; + + osalSysLockFromISR(); + sduSOFHookI(&SDU1); + osalSysUnlockFromISR(); +} + +/* + * USB driver configuration. + */ +const USBConfig usbcfg = { + usb_event, + get_descriptor, + sduRequestsHook, + sof_handler +}; + +/* + * Serial over USB driver configuration. + */ +const SerialUSBConfig serusbcfg = { + &USBD1, + USBD1_DATA_REQUEST_EP, + USBD1_DATA_AVAILABLE_EP, + USBD1_INTERRUPT_REQUEST_EP +}; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/common/usbcfg.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/common/usbcfg.h new file mode 100644 index 00000000..167e1df8 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/common/usbcfg.h @@ -0,0 +1,17 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef USBCFG_H +#define USBCFG_H + +extern const USBConfig usbcfg; +extern SerialUSBConfig serusbcfg; +extern SerialUSBDriver SDU1; + +#endif /* USBCFG_H */ + +/** @} */ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/managed_helpers/I2M_ELECTRON_NF.Adc.cs b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/managed_helpers/I2M_ELECTRON_NF.Adc.cs new file mode 100644 index 00000000..94e54b13 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/managed_helpers/I2M_ELECTRON_NF.Adc.cs @@ -0,0 +1,38 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +namespace nanoFramework.Targets.Community.I2M_ELECTRON_NF +{ + /// + /// Enumeration of ADC channels available in the community board I2M_ELECTRON_NF + /// + public static class AdcChannels + { + /// + /// Channel 0, exposed on PA4, connected to PA4 (ADC1 - IN4) + /// + public const int Channel_0 = 0; + + /// + /// Channel 1, exposed on PA5, connected to PA5 (ADC1 - IN5) + /// + public const int Channel_1 = 1; + + /// + /// Channel 2, internal temperature sensor, connected to ADC1 + /// + public const int Channel_TemperatureSensor = 2; + + /// + /// Channel 3, internal voltage reference, connected to ADC1 + /// + public const int Channel_VrefIn = 3; + + /// + /// Channel 4, connected to VBatt pin, ADC1 + /// + public const int Channel_Vbatt = 4; + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/managed_helpers/I2M_ELECTRON_NF.Gpio.cs b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/managed_helpers/I2M_ELECTRON_NF.Gpio.cs new file mode 100644 index 00000000..8f4ec298 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/managed_helpers/I2M_ELECTRON_NF.Gpio.cs @@ -0,0 +1,57 @@ +using System; + +namespace nanoFramework.Targets.Community.I2M_ELECTRON_NF +{ + public static class Gpio + { + /// + /// Output pin connected to the on-board Green LED + /// + public const int GreenLed = PA1; + + /// + /// Output pin connected to the on-board Blue LED + /// + public const int BlueLed = PA8; + + /// + /// + /// + public const int PA0 = 0; + public const int PA1 = 1; + public const int PA2 = 2; + public const int PA3 = 3; + public const int PA4 = 4; + public const int PA5 = 5; + public const int PA6 = 6; + public const int PA7 = 7; + public const int PA8 = 8; + public const int PA9 = 9; + public const int PA10 = 10; + public const int PA11 = 11; + public const int PA12 = 12; + public const int PA13 = 13; + public const int PA14 = 14; + public const int PA15 = 15; + + /// + /// + /// + public const int PB0 = 16; + public const int PB1 = 17; + public const int PB2 = 18; + public const int PB3 = 19; + public const int PB4 = 20; + public const int PB5 = 21; + public const int PB6 = 22; + public const int PB7 = 23; + public const int PB8 = 24; + public const int PB9 = 25; + public const int PB10 = 26; + public const int PB11 = 27; + public const int PB12 = 28; + public const int PB13 = 29; + public const int PB14 = 30; + public const int PB15 = 31; + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/managed_helpers/README.md b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/managed_helpers/README.md new file mode 100644 index 00000000..0820b7ed --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/managed_helpers/README.md @@ -0,0 +1,6 @@ +## Managed code helpers + +This folder contains helper classes to make developers life easier when coding for this target board. + +* [Adc](I2M_ELECTRON_NF.Adc.cs) +* [Gpio](I2M_ELECTRON_NF.Gpio.cs) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/CMakeLists.txt new file mode 100644 index 00000000..291f47e1 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/CMakeLists.txt @@ -0,0 +1,9 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# # append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/STM32F411xE_booter.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/STM32F411xE_booter.ld new file mode 100644 index 00000000..ef8cbbab --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/STM32F411xE_booter.ld @@ -0,0 +1,80 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F411xE memory setup. + * + */ +MEMORY +{ + flash : org = 0x08000000, len = 32k /* space reserved for nanoBooter (1st two sectors 0x08000000 to 0x08008000)*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 128k /* SRAM1 */ + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Stacks rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/chconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/chconf.h new file mode 100644 index 00000000..335e3fa4 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/chconf.h @@ -0,0 +1,616 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 1000 // this is 1 millisecond + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#define CH_CFG_INTERVALS_SIZE 32 + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_TIME_TYPES_SIZE 32 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES FALSE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS FALSE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT FALSE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES FALSE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_OBJ_FIFOS TRUE + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#define CH_CFG_USE_FACTORY FALSE + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 + +/** + * @brief Enables the registry of generic objects. + */ +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE + +/** + * @brief Enables factory for generic buffers. + */ +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE + +/** + * @brief Enables factory for semaphores. + */ +#define CH_CFG_FACTORY_SEMAPHORES TRUE + +/** + * @brief Enables factory for mailboxes. + */ +#define CH_CFG_FACTORY_MAILBOXES TRUE + +/** + * @brief Enables factory for objects FIFOs. + */ +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/halconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/halconf.h new file mode 100644 index 00000000..b970c22f --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/halconf.h @@ -0,0 +1,513 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/halconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/halconf_nf.h new file mode 100644 index 00000000..e35b7bec --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/halconf_nf.h @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +#if !defined(HAL_USE_STM32_RNG) +#define HAL_USE_STM32_RNG FALSE +#endif + +#endif // _HALCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/main.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/main.c new file mode 100644 index 00000000..b7890058 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/main.c @@ -0,0 +1,75 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); + +// Application entry point. +int main(void) { + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init SWO as soon as possible to make it available to output ASAP + #if (SWO_OUTPUT == TRUE) + SwoInit(); + #endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + osDelay(20); // Let init stabilize + + // check for valid CLR image + if(CheckValidCLRImage((uint32_t)&__nanoImage_end__)) + { + // there seems to be a valid CLR image + // launch nanoCLR + LaunchCLR((uint32_t)&__nanoImage_end__); + } + + // Initializes a serial-over-USB CDC driver. + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + // Activates the USB driver and then the USB bus pull-up on D+. + // Note, a delay is inserted in order to not have to disconnect the cable after a reset. + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1500); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // Normal main() thread + while (true) { + palSetPad(GPIOA, GPIOA_LED_GREEN); + osDelay(500); + palClearPad(GPIOA, GPIOA_LED_GREEN); + osDelay(500); + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/mcuconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/mcuconf.h new file mode 100644 index 00000000..318fae15 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/mcuconf.h @@ -0,0 +1,338 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF +#define STM32F411_MCUCONF + +/* + * HAL driver system settings. + */ + +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED FALSE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 12 +#define STM32_PLLN_VALUE 192 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 4 + +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSE +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 250 +#define STM32_SDC_READ_TIMEOUT_MS 25 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/mcuconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/mcuconf_nf.h new file mode 100644 index 00000000..574b9636 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/mcuconf_nf.h @@ -0,0 +1,10 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/target_board.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/target_board.h.in new file mode 100644 index 00000000..19531d9c --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoBooter/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOBOOTER_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/CMakeLists.txt new file mode 100644 index 00000000..e5496b7e --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/STM32F411xE_CLR.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/STM32F411xE_CLR.ld new file mode 100644 index 00000000..f1f0afc1 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/STM32F411xE_CLR.ld @@ -0,0 +1,76 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F411xE memory setup. + * Note: Only use of ram0. + */ +MEMORY +{ + flash : org = 0x08008000, len = 512k - 32k - 256k /* flash size less the space reserved for nanoBooter and application deployment*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x08040000, len = 256k /* space reserved for application deployment */ + ramvt : org = 0x20000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 128k /* SRAM1 */ + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/chconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/chconf.h new file mode 100644 index 00000000..390ce3a6 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/chconf.h @@ -0,0 +1,616 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 10000 + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#define CH_CFG_INTERVALS_SIZE 32 + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_TIME_TYPES_SIZE 32 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_OBJ_FIFOS TRUE + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#define CH_CFG_USE_FACTORY FALSE + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 + +/** + * @brief Enables the registry of generic objects. + */ +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE + +/** + * @brief Enables factory for generic buffers. + */ +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE + +/** + * @brief Enables factory for semaphores. + */ +#define CH_CFG_FACTORY_SEMAPHORES TRUE + +/** + * @brief Enables factory for mailboxes. + */ +#define CH_CFG_FACTORY_MAILBOXES TRUE + +/** + * @brief Enables factory for objects FIFOs. + */ +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/halconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/halconf.h new file mode 100644 index 00000000..85b9b4e6 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/halconf.h @@ -0,0 +1,532 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +// #define HAL_USE_ADC TRUE +// #endif + +/** + * @brief Enables the CAN subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +// #define HAL_USE_CAN FALSE +// #endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +// /** +// * @brief Enables the DAC subsystem. +// */ +// #if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +// #define HAL_USE_DAC FALSE +// #endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +// this option is set at target_platform.h (from config file) +//#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +//#define HAL_USE_I2C TRUE +//#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +// #define HAL_USE_MAC TRUE +// #endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +// #define HAL_USE_PWM TRUE +// #endif + +/** + * @brief Enables the RTC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +// #define HAL_USE_RTC TRUE +// #endif + +/** + * @brief Enables the SDC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +// #define HAL_USE_SDC FALSE +// #endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + + +/** + * @brief Enables the SPI subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +// #define HAL_USE_SPI FALSE +// #endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +// #define HAL_USE_UART FALSE +// #endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +// #define HAL_USE_WDG FALSE +// #endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS TRUE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/halconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/halconf_nf.h new file mode 100644 index 00000000..e35b7bec --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/halconf_nf.h @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +#if !defined(HAL_USE_STM32_RNG) +#define HAL_USE_STM32_RNG FALSE +#endif + +#endif // _HALCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/main.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/main.c new file mode 100644 index 00000000..83f74065 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/main.c @@ -0,0 +1,79 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include "usbcfg.h" +#include +#include +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); +// declare CLRStartup thread here +osThreadDef(CLRStartupThread, osPriorityNormal, 4096, "CLRStartupThread"); + +// Application entry point. +int main(void) { + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init SWO as soon as possible to make it available to output ASAP + #if (SWO_OUTPUT == TRUE) + SwoInit(); + #endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // Start Watchdog + Watchdog_Init(); + + // Initializes a serial-over-USB CDC driver. + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + // Activates the USB driver and then the USB bus pull-up on D+. + // Note, a delay is inserted in order to not have to disconnect the cable after a reset + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1500); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // CLR settings to launch CLR thread + CLR_SETTINGS clrSettings; + (void)memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.EnterDebuggerLoopAfterExit = true; + + // create the CLR Startup thread + osThreadCreate(osThread(CLRStartupThread), &clrSettings); + + // EXT driver needs to be started from main + #if (HAL_USE_EXT == TRUE) + extStart(&EXTD1, &extInterruptsConfiguration); + #endif + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + while (true) { + osDelay(100); + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/mcuconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/mcuconf.h new file mode 100644 index 00000000..af4fd4d7 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/mcuconf.h @@ -0,0 +1,338 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF +#define STM32F411_MCUCONF + +/* + * HAL driver system settings. + */ + +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED FALSE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 12 +#define STM32_PLLN_VALUE 192 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 4 + +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSE +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 TRUE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 TRUE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 TRUE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 250 +#define STM32_SDC_READ_TIMEOUT_MS 25 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 TRUE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG TRUE + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/mcuconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/mcuconf_nf.h new file mode 100644 index 00000000..574b9636 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/mcuconf_nf.h @@ -0,0 +1,10 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/nanoHAL.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/nanoHAL.cpp new file mode 100644 index 00000000..076a50fc --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/nanoHAL.cpp @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +void HAL_EnterBooterMode() +{ +} + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/target_board.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/target_board.h.in new file mode 100644 index 00000000..b980bc05 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/nanoCLR/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOCLR_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/resources/IngenuityMicro_Logo.svg b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/resources/IngenuityMicro_Logo.svg new file mode 100644 index 00000000..4ffae142 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/resources/IngenuityMicro_Logo.svg @@ -0,0 +1,128 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + I + + + 2 + + + M + + + IngenuityMicro + + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/resources/electron.pdf b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/resources/electron.pdf new file mode 100644 index 00000000..8792a0e7 Binary files /dev/null and b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/resources/electron.pdf differ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/resources/electronpins.png b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/resources/electronpins.png new file mode 100644 index 00000000..1d7d4e99 Binary files /dev/null and b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/resources/electronpins.png differ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_BlockStorage.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_BlockStorage.c new file mode 100644 index 00000000..9e7c7f55 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_BlockStorage.c @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice STM32Flash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &STM32Flash_BlockStorageInterface, &Device_BlockStorageConfig, false); +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_BlockStorage.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_BlockStorage.h new file mode 100644 index 00000000..aa50b1b7 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_common.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_common.c new file mode 100644 index 00000000..c70f5865 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_common.c @@ -0,0 +1,31 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include "target_common.h" +#include + +HAL_SYSTEM_CONFIG HalSystemConfig = +{ + { true }, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, //ConvertCOM_DebugHandle(1), + 0, //ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + { RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size }, + { FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size } +}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; + +// this target uses DFU for updates +uint32_t GetTargetCapabilities() +{ + return TargetCapabilities_DfuUpdate; +}; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_common.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_common.h.in new file mode 100644 index 00000000..419f9f35 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_common.h.in @@ -0,0 +1,37 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x20000000) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x00020000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x08000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00080000) + +///////////////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////// +#define TARGETNAMESTRING "@CHIBIOS_BOARD@" +#define PLATFORMNAMESTRING "STM32F4" +/////////////////////////////////////////////// + +#endif /* _TARGET_COMMON_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_system_devices_dac_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_system_devices_dac_config.cpp new file mode 100644 index 00000000..88a70347 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_system_devices_dac_config.cpp @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_DAC_PORT_PIN_CHANNEL DacPortPinConfig[] = { + + // DAC1, channel 1, GPIO port A, pin 4 + {1, 1, GPIOA, 4}, + +}; + +const int DacChannelCount = ARRAYSIZE(DacPortPinConfig); diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_windows_devices_adc_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_windows_devices_adc_config.cpp new file mode 100644 index 00000000..5d78d470 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_windows_devices_adc_config.cpp @@ -0,0 +1,21 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_adc_native_target.h" + + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // ADC1 + {1, GPIOA, 4, ADC_CHANNEL_IN4}, + {1, GPIOA, 5, ADC_CHANNEL_IN5}, + + // these are the internal sources, available only at ADC1 + {1, NULL, 0, ADC_CHANNEL_SENSOR}, + {1, NULL, 0, ADC_CHANNEL_VREFINT}, + {1, NULL, 0, ADC_CHANNEL_VBAT}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_windows_devices_i2c_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_windows_devices_i2c_config.cpp new file mode 100644 index 00000000..2a60a22f --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_windows_devices_i2c_config.cpp @@ -0,0 +1,18 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_i2c_native_target.h" + +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for SCL pin is: GPIOB +// port for SDA pin is: GPIOB +// SCL pin: is GPIOB_8 +// SDA pin: is GPIOB_9 +// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, GPIOB, GPIOB, 8, 9, 4) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_windows_devices_serialcommunication_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_windows_devices_serialcommunication_config.cpp new file mode 100644 index 00000000..cbd0a365 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_windows_devices_serialcommunication_config.cpp @@ -0,0 +1,36 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_windows_devices_serialcommunication_config.h" +#include "win_dev_serial_native_target.h" + +/////////// +// UART2 // +/////////// + +// pin configuration for UART2 +// port: GPIOA +// TX pin: is GPIOA_2 +// RX pin: is GPIOA_3 +// GPIO alternate pin function is 7 (see "Table 9. Alternate function mapping" in STM32F411xC and STM32F411xE datasheet) +UART_CONFIG_PINS(2, GPIOA, GPIOA, 2, 3, 7) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart2_TxBuffer[UART2_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart2_RxBuffer[UART2_RX_SIZE]; + +// initialization for UART2 +UART_INIT(2, UART2_TX_SIZE, UART2_RX_SIZE) + +// un-initialization for UART2 +UART_UNINIT(2) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_windows_devices_serialcommunication_config.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_windows_devices_serialcommunication_config.h new file mode 100644 index 00000000..68578e71 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_windows_devices_serialcommunication_config.h @@ -0,0 +1,18 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +/////////// +// UART2 // +/////////// + +// enable USART2 +#define NF_SERIAL_COMM_STM32_UART_USE_USART2 TRUE + +// buffers size +// tx buffer size: 1024 bytes +#define UART2_TX_SIZE 1024 +// rx buffer size: 1024 bytes +#define UART2_RX_SIZE 1024 diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_windows_devices_spi_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_windows_devices_spi_config.cpp new file mode 100644 index 00000000..ef2d3a10 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_ELECTRON_NF/target_windows_devices_spi_config.cpp @@ -0,0 +1,10 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_spi_native.h" + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/CMakeLists.txt new file mode 100644 index 00000000..52a69f81 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/CMakeLists.txt @@ -0,0 +1,225 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +cmake_minimum_required(VERSION 3.0) +ENABLE_LANGUAGE(ASM) + +# add header files with common OS definitions and board definitions specific for each image +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/target_common.h" @ONLY) + +set(NANOBOOTER_PROJECT_NAME "nanoBooter") +set(NANOCLR_PROJECT_NAME "nanoCLR") + +find_package(BuildUtils REQUIRED) +find_package(CHIBIOS REQUIRED) +find_package(ChibiOSnfOverlay REQUIRED) +find_package(WireProtocol REQUIRED) + +# packages for nanoFramework libraries +####################################### +# mandatory +find_package(NF_CoreCLR REQUIRED) + +####################################### +# optional + +# ChibiOS contrib repo +if(CHIBIOS_CONTRIB_REQUIRED) + find_package(ChibiOS-Contrib REQUIRED) +endif() + +# nF feature: debugger +if(NF_FEATURE_DEBUGGER) + find_package(NF_Debugger REQUIRED) + find_package(NF_Diagnostics REQUIRED) +endif() + +# nF feature: networking +if(USE_NETWORKING_OPTION) + find_package(CHIBIOS_LWIP REQUIRED) +endif() + +# nF feature: filesystem +if(USE_FILESYSTEM_OPTION) + find_package(CHIBIOS_FATFS REQUIRED) +endif() + +####################################### + +add_subdirectory("common") +add_subdirectory("nanoBooter") +add_subdirectory("nanoCLR") + +####################### +# nanoBooter executable + +add_executable( + # executables for project, project sources + ${NANOBOOTER_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + "${CMAKE_CURRENT_SOURCE_DIR}/target_BlockStorage.c" + + # need to add configuration manager to allow get/store configuration blocks + "${PROJECT_SOURCE_DIR}/src/HAL/nanoHAL_ConfigurationManager_stubs.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOBOOTER_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOBOOTER_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOBOOTER_SOURCES} + + ${CHIBIOS_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} +) + +####################### +# nanoCLR executable + +add_executable( + # executables for project, project sources + ${NANOCLR_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOCLR_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOCLR_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOCLR_SOURCES} + + ${CHIBIOS_SOURCES} + ${CHIBIOS_CONTRIB_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} + + # sources for nanoFramework libraries + ${NF_CoreCLR_SOURCES} + ${NF_Debugger_SOURCES} + ${NF_Diagnostics_SOURCES} + + # sources for nanoFramework APIs + ${TARGET_NANO_APIS_SOURCES} +) + +# add dependency from ChibiOS (this is required to make sure the ChibiOS repo is downloaded before the build starts) +add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf ChibiOS) +add_dependencies(${NANOCLR_PROJECT_NAME}.elf ChibiOS) + +# include common directories +include_directories( + ${CMAKE_CURRENT_BINARY_DIR} + ${CMAKE_CURRENT_SOURCE_DIR} + ${CMAKE_CURRENT_SOURCE_DIR}/common + ${PROJECT_SOURCE_DIR}/src/CLR/Core + ${PROJECT_SOURCE_DIR}/src/CLR/Include + ${PROJECT_SOURCE_DIR}/src/HAL/Include + ${PROJECT_SOURCE_DIR}/src/PAL/Include + + ${WireProtocol_INCLUDE_DIRS} + ${CHIBIOS_INCLUDE_DIRS} + ${ChibiOSnfOverlay_INCLUDE_DIRS} + ${CHIBIOS_CONTRIB_INCLUDE_DIRS} + + ${TARGET_CMSIS_COMMON_INCLUDE_DIRS} + ${TARGET_CHIBIOS_COMMON_INCLUDE_DIRS} +) + +# include directories for nanoBooter +target_include_directories(${NANOBOOTER_PROJECT_NAME}.elf PUBLIC + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter" + ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter + + ${TARGET_CMSIS_NANOBOOTER_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOBOOTER_INCLUDE_DIRS} +) + +# include directories for nanoCLR +target_include_directories(${NANOCLR_PROJECT_NAME}.elf PUBLIC + ${CMAKE_CURRENT_BINARY_DIR}/nanoCLR + ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR + + ${TARGET_CMSIS_NANOCLR_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOCLR_INCLUDE_DIRS} + + # directories for nanoFramework libraries + ${NF_CoreCLR_INCLUDE_DIRS} + ${NF_Debugger_INCLUDE_DIRS} + ${NF_Diagnostics_INCLUDE_DIRS} + + # includes for nanoFramework APIs + ${TARGET_NANO_APIS_INCLUDES} + + # includes for ChibiOS LwIP + ${CHIBIOS_LWIP_INCLUDE_DIRS} +) + +# set compiler options +nf_set_compiler_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_options(${NANOCLR_PROJECT_NAME}.elf) + +# set compiler definitions +nf_set_compiler_definitions(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_definitions(${NANOCLR_PROJECT_NAME}.elf) + +# set linker files +if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F411xE_booter-DEBUG.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/STM32F411xE_CLR-DEBUG.ld) +else() + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F411xE_booter.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/STM32F411xE_CLR.ld) +endif() + +# set linker options +nf_set_linker_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_linker_options(${NANOCLR_PROJECT_NAME}.elf) + +# add other linker flags +########################################################### +# the sizes of CRT heap and ChibiOS stacks are defined here +set_property(TARGET ${NANOBOOTER_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x400,--defsym=__crt_heap_size__=0x1000") +set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x2800") + +# generate output files +nf_generate_build_output_files(${NANOBOOTER_PROJECT_NAME}.elf) +nf_generate_build_output_files(${NANOCLR_PROJECT_NAME}.elf) + +# if HEX2DFU tool is available pack the binaries into a DFU package +if(HEX2DFU_TOOL_AVAILABLE) + + #################################################################################################### + ## when changing the linker file make sure to update the new addresses for the image files bellow ## + ## DO NOT use the leading 0x notation, just the address in plain hexadecimal formating ## + #################################################################################################### + if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + NF_GENERATE_DFU_PACKAGE( + ${PROJECT_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin 08000000 + ${PROJECT_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin 08008000 + ${PROJECT_SOURCE_DIR}/build/nanoframework-4-oxygen.dfu + ) + else() + NF_GENERATE_DFU_PACKAGE( + ${PROJECT_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin 08000000 + ${PROJECT_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin 08004000 + ${PROJECT_SOURCE_DIR}/build/nanoframework-4-oxygen.dfu + ) + endif() + +endif() diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/README.md b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/README.md new file mode 100644 index 00000000..e1c16b7f --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/README.md @@ -0,0 +1,9 @@ +## Oxygen community board ## + +The board used in this community contribution is a STM32F411CEU6 based board from IngenuityMicro called Oxygen. The board has 20 pins for your use. The pins on the opposite side of the USB connector can be used for several add-on boards for f.e. BLE, WiFi (ESP8266). + +The pins can be used for several purposes, GPIO, PWM, I2C, SPI, SERIAL, etc. + +Further details how the pin out is supposed to work can be found in the resources folder, of course since we know now what MCU pins go to what PCB pins we can change the board.h depending on what you want to achieve with the board. + +For more information you nay want to have a look at https://github.com/piwi1263/Molecules diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/board.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/board.c new file mode 100644 index 00000000..5e13690c --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/board.c @@ -0,0 +1,265 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) + gpio_setup_t PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_setup_t PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) + gpio_setup_t PKData; +#endif +} gpio_config_t; + +/** + * @brief STM32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +#endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB1(STM32_GPIO_EN_MASK); + rccEnableAHB1(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG + gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI + gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ + gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK + gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + * else. + */ +void __early_init(void) { + + stm32_gpio_init(); + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/board.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/board.h new file mode 100644 index 00000000..92f959c7 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/board.h @@ -0,0 +1,1633 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This is the a board made by IngenuityMicro based upon MCU from ST + * the STM32F411CEU6. The board is equipped with both LSE and HSE. + */ + +#ifndef BOARD_H +#define BOARD_H + +/* + * Setup for IngenuityMicro Oxygen board based upon an STM32F411CEU6.. + */ + +/* + * Board identifier. + */ +#define BOARD_I2M_OXYGEN_NF +#define BOARD_NAME "IngenuityMicro Oxygen board based upon STM32F411CEU6 for nanoFramework" + +/* + * USB OTG Force + */ +#define BOARD_OTG_NOVBUSSENS + +/* + * Completely wacko definition of a flash sector here + */ +#define FLASH_SECTOR_11 ((uint32_t)11U) + +/* + * Board oscillators-related settings. + * NOTE: LSE is fitted and is of course 32768. + * NOTE: HSE is fitted and set to a 12 MHz one. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768U +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 12000000U +#endif + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U + +/* + * MCU type as defined in the ST header. + */ +#define STM32F411xE + +/* + * IO pins assignments. + */ +#define GPIOA_ADC1_IN0 0U +#define GPIOA_USART2_CTS 0U +#define GPIOA_ADC1_IN1 1U +#define GPIOA_USART2_RTS 1U +#define GPIOA_USART2_TX 2U +#define GPIOA_USART2_RX 3U +#define GPIOA_ADC1_IN4 4U +#define GPIOA_SPI1_SCLK 5U +#define GPIOA_SPI1_MISO 6U +#define GPIOA_SPI1_MOSI 7U +#define GPIOA_PIN8 8U +#define GPIOA_USART1_TX 9U +#define GPIOA_USART1_RX 10U +#define GPIOA_OTG_FS_DM 11U +#define GPIOA_OTG_FS_DP 12U +#define GPIOA_USER_LED 13U +#define GPIOA_PIN14 14U +#define GPIOA_PIN15 15U + +#define GPIOB_PIN0 0U +#define GPIOB_PIN1 1U +#define GPIOB_PIN2 2U +#define GPIOB_PIN3 3U +#define GPIOB_PIN4 4U +#define GPIOB_PIN5 5U +#define GPIOB_PIN6 6U +#define GPIOB_PIN7 7U +#define GPIOB_I2C1_SCL 8U +#define GPIOB_I2C1_SDA 9U +#define GPIOB_PIN10 10U +#define GPIOB_PIN11 11U +#define GPIOB_PIN12 12U +#define GPIOB_SPI2_SCLK 13U +#define GPIOB_SPI2_MISO 14U +#define GPIOB_SPI2_MOSI 15U + +#define GPIOC_PIN0 0U +#define GPIOC_PIN1 1U +#define GPIOC_PIN2 2U +#define GPIOC_PIN3 3U +#define GPIOC_PIN4 4U +#define GPIOC_PIN5 5U +#define GPIOC_USART6_TX 6U +#define GPIOC_USART6_RX 7U +#define GPIOC_PIN8 8U +#define GPIOC_PIN9 9U +#define GPIOC_PIN10 10U +#define GPIOC_PIN11 11U +#define GPIOC_PIN12 12U +#define GPIOC_PIN13 13U +#define GPIOC_OSC32_IN 14U +#define GPIOC_OSC32_OUT 15U + +#define GPIOD_PIN0 0U +#define GPIOD_PIN1 1U +#define GPIOD_PIN2 2U +#define GPIOD_PIN3 3U +#define GPIOD_PIN4 4U +#define GPIOD_PIN5 5U +#define GPIOD_PIN6 6U +#define GPIOD_PIN7 7U +#define GPIOD_PIN8 8U +#define GPIOD_PIN9 9U +#define GPIOD_PIN10 10U +#define GPIOD_PIN11 11U +#define GPIOD_PIN12 12U +#define GPIOD_PIN13 13U +#define GPIOD_PIN14 14U +#define GPIOD_PIN15 15U + +#define GPIOE_PIN0 0U +#define GPIOE_PIN1 1U +#define GPIOE_PIN2 2U +#define GPIOE_PIN3 3U +#define GPIOE_PIN4 4U +#define GPIOE_PIN5 5U +#define GPIOE_PIN6 6U +#define GPIOE_PIN7 7U +#define GPIOE_PIN8 8U +#define GPIOE_PIN9 9U +#define GPIOE_PIN10 10U +#define GPIOE_PIN11 11U +#define GPIOE_PIN12 12U +#define GPIOE_PIN13 13U +#define GPIOE_PIN14 14U +#define GPIOE_PIN15 15U + +#define GPIOF_PIN0 0U +#define GPIOF_PIN1 1U +#define GPIOF_PIN2 2U +#define GPIOF_PIN3 3U +#define GPIOF_PIN4 4U +#define GPIOF_PIN5 5U +#define GPIOF_PIN6 6U +#define GPIOF_PIN7 7U +#define GPIOF_PIN8 8U +#define GPIOF_PIN9 9U +#define GPIOF_PIN10 10U +#define GPIOF_PIN11 11U +#define GPIOF_PIN12 12U +#define GPIOF_PIN13 13U +#define GPIOF_PIN14 14U +#define GPIOF_PIN15 15U + +#define GPIOG_PIN0 0U +#define GPIOG_PIN1 1U +#define GPIOG_PIN2 2U +#define GPIOG_PIN3 3U +#define GPIOG_PIN4 4U +#define GPIOG_PIN5 5U +#define GPIOG_PIN6 6U +#define GPIOG_PIN7 7U +#define GPIOG_PIN8 8U +#define GPIOG_PIN9 9U +#define GPIOG_PIN10 10U +#define GPIOG_PIN11 11U +#define GPIOG_PIN12 12U +#define GPIOG_PIN13 13U +#define GPIOG_PIN14 14U +#define GPIOG_PIN15 15U + +#define GPIOH_OSC_IN 0U +#define GPIOH_OSC_OUT 1U +#define GPIOH_PIN2 2U +#define GPIOH_PIN3 3U +#define GPIOH_PIN4 4U +#define GPIOH_PIN5 5U +#define GPIOH_PIN6 6U +#define GPIOH_PIN7 7U +#define GPIOH_PIN8 8U +#define GPIOH_PIN9 9U +#define GPIOH_PIN10 10U +#define GPIOH_PIN11 11U +#define GPIOH_PIN12 12U +#define GPIOH_PIN13 13U +#define GPIOH_PIN14 14U +#define GPIOH_PIN15 15U + +#define GPIOI_PIN0 0U +#define GPIOI_PIN1 1U +#define GPIOI_PIN2 2U +#define GPIOI_PIN3 3U +#define GPIOI_PIN4 4U +#define GPIOI_PIN5 5U +#define GPIOI_PIN6 6U +#define GPIOI_PIN7 7U +#define GPIOI_PIN8 8U +#define GPIOI_PIN9 9U +#define GPIOI_PIN10 10U +#define GPIOI_PIN11 11U +#define GPIOI_PIN12 12U +#define GPIOI_PIN13 13U +#define GPIOI_PIN14 14U +#define GPIOI_PIN15 15U + +#define GPIOJ_PIN0 0U +#define GPIOJ_PIN1 1U +#define GPIOJ_PIN2 2U +#define GPIOJ_PIN3 3U +#define GPIOJ_PIN4 4U +#define GPIOJ_PIN5 5U +#define GPIOJ_PIN6 6U +#define GPIOJ_PIN7 7U +#define GPIOJ_PIN8 8U +#define GPIOJ_PIN9 9U +#define GPIOJ_PIN10 10U +#define GPIOJ_PIN11 11U +#define GPIOJ_PIN12 12U +#define GPIOJ_PIN13 13U +#define GPIOJ_PIN14 14U +#define GPIOJ_PIN15 15U + +#define GPIOK_PIN0 0U +#define GPIOK_PIN1 1U +#define GPIOK_PIN2 2U +#define GPIOK_PIN3 3U +#define GPIOK_PIN4 4U +#define GPIOK_PIN5 5U +#define GPIOK_PIN6 6U +#define GPIOK_PIN7 7U +#define GPIOK_PIN8 8U +#define GPIOK_PIN9 9U +#define GPIOK_PIN10 10U +#define GPIOK_PIN11 11U +#define GPIOK_PIN12 12U +#define GPIOK_PIN13 13U +#define GPIOK_PIN14 14U +#define GPIOK_PIN15 15U + +/* + * IO lines assignments. + */ +#define LINE_ARD_A0 PAL_LINE(GPIOA, 0U) +#define LINE_ADC1_IN0 PAL_LINE(GPIOA, 0U) +#define LINE_ARD_A1 PAL_LINE(GPIOA, 1U) +#define LINE_ADC1_IN1 PAL_LINE(GPIOA, 1U) +#define LINE_ARD_D1 PAL_LINE(GPIOA, 2U) +#define LINE_USART2_TX PAL_LINE(GPIOA, 2U) +#define LINE_ARD_D0 PAL_LINE(GPIOA, 3U) +#define LINE_USART2_RX PAL_LINE(GPIOA, 3U) +#define LINE_ARD_A2 PAL_LINE(GPIOA, 4U) +#define LINE_ADC1_IN4 PAL_LINE(GPIOA, 4U) +#define LINE_LED_GREEN PAL_LINE(GPIOA, 5U) +#define LINE_ARD_D13 PAL_LINE(GPIOA, 5U) +#define LINE_ARD_D12 PAL_LINE(GPIOA, 6U) +#define LINE_ARD_D11 PAL_LINE(GPIOA, 7U) +#define LINE_ARD_D7 PAL_LINE(GPIOA, 8U) +#define LINE_ARD_D8 PAL_LINE(GPIOA, 9U) +#define LINE_ARD_D2 PAL_LINE(GPIOA, 10U) +#define LINE_OTG_FS_DM PAL_LINE(GPIOA, 11U) +#define LINE_OTG_FS_DP PAL_LINE(GPIOA, 12U) +#define LINE_USER_LED PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) + +#define LINE_ARD_A3 PAL_LINE(GPIOB, 0U) +#define LINE_ADC1_IN8 PAL_LINE(GPIOB, 0U) +#define LINE_SWO PAL_LINE(GPIOB, 3U) +#define LINE_ARD_D3 PAL_LINE(GPIOB, 3U) +#define LINE_ARD_D5 PAL_LINE(GPIOB, 4U) +#define LINE_ARD_D4 PAL_LINE(GPIOB, 5U) +#define LINE_ARD_D10 PAL_LINE(GPIOB, 6U) +#define LINE_ARD_D15 PAL_LINE(GPIOB, 8U) +#define LINE_ARD_D14 PAL_LINE(GPIOB, 9U) +#define LINE_ARD_D6 PAL_LINE(GPIOB, 10U) + +#define LINE_ARD_A5 PAL_LINE(GPIOC, 0U) +#define LINE_ADC1_IN10 PAL_LINE(GPIOC, 0U) +#define LINE_ARD_A4 PAL_LINE(GPIOC, 1U) +#define LINE_ADC1_IN11 PAL_LINE(GPIOC, 1U) +#define LINE_ARD_D9 PAL_LINE(GPIOC, 7U) +#define LINE_BUTTON PAL_LINE(GPIOC, 13U) +#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) +#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) + + + + + +#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) +#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) + + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * GPIOA setup: + * + * PA0 - ADC1_IN0 (input pullup). + * PA1 - ADC1_IN1 (input pullup). + * PA2 - USART2_TX (alternate 7). + * PA3 - USART2_RX (alternate 7). + * PA4 - ADC1_IN4 (input pullup). + * PA5 - SPI1_SCLK (alternate 5). + * PA6 - SPI1_MISO (alternate 5). + * PA7 - SPI1_MOSI (alternate 5). + * PA8 - PIN8 (input pullup). + * PA9 - USART1_TX (alternate 7). + * PA10 - USART1_RX (alternate 7). + * PA11 - OTG_FS_DM (alternate 10). + * PA12 - OTG_FS_DP (alternate 10). + * PA13 - USER_LED (output pushpull high). + * PA14 - PIN14 (alternate 0). + * PA15 - PIN15 (input pullup). + */ +#define VAL_GPIOA_MODER (PIN_MODE_ANALOG(GPIOA_ADC1_IN0) | \ + PIN_MODE_ANALOG(GPIOA_ADC1_IN1) | \ + PIN_MODE_ALTERNATE(GPIOA_USART2_TX) | \ + PIN_MODE_ALTERNATE(GPIOA_USART2_RX) | \ + PIN_MODE_ANALOG(GPIOA_ADC1_IN4) | \ + PIN_MODE_ALTERNATE(GPIOA_SPI1_SCLK) | \ + PIN_MODE_ALTERNATE(GPIOA_SPI1_MISO) | \ + PIN_MODE_ALTERNATE(GPIOA_SPI1_MOSI) | \ + PIN_MODE_INPUT(GPIOA_PIN8) | \ + PIN_MODE_ALTERNATE(GPIOA_USART1_TX) | \ + PIN_MODE_ALTERNATE(GPIOA_USART1_RX) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ + PIN_MODE_OUTPUT(GPIOA_USER_LED) | \ + PIN_MODE_INPUT(GPIOA_PIN14) | \ + PIN_MODE_INPUT(GPIOA_PIN15)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ADC1_IN0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ADC1_IN1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USART2_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USART2_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ADC1_IN4) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SPI1_SCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MISO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SPI1_MOSI) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USART1_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USART1_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USER_LED) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ADC1_IN0) | \ + PIN_OSPEED_HIGH(GPIOA_ADC1_IN1) | \ + PIN_OSPEED_HIGH(GPIOA_USART2_TX) | \ + PIN_OSPEED_HIGH(GPIOA_USART2_RX) | \ + PIN_OSPEED_HIGH(GPIOA_ADC1_IN4) | \ + PIN_OSPEED_HIGH(GPIOA_SPI1_SCLK) | \ + PIN_OSPEED_HIGH(GPIOA_SPI1_MISO) | \ + PIN_OSPEED_HIGH(GPIOA_SPI1_MOSI) | \ + PIN_OSPEED_HIGH(GPIOA_PIN8) | \ + PIN_OSPEED_HIGH(GPIOA_USART1_TX) | \ + PIN_OSPEED_HIGH(GPIOA_USART1_RX) | \ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_OSPEED_HIGH(GPIOA_USER_LED) | \ + PIN_OSPEED_HIGH(GPIOA_PIN14) | \ + PIN_OSPEED_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_ADC1_IN0) | \ + PIN_PUPDR_FLOATING(GPIOA_ADC1_IN1) | \ + PIN_PUPDR_FLOATING(GPIOA_USART2_TX) | \ + PIN_PUPDR_FLOATING(GPIOA_USART2_RX) | \ + PIN_PUPDR_FLOATING(GPIOA_ADC1_IN4) | \ + PIN_PUPDR_FLOATING(GPIOA_SPI1_SCLK) | \ + PIN_PUPDR_FLOATING(GPIOA_SPI1_MISO) | \ + PIN_PUPDR_FLOATING(GPIOA_SPI1_MOSI) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOA_USART1_TX) | \ + PIN_PUPDR_FLOATING(GPIOA_USART1_RX) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \ + PIN_PUPDR_FLOATING(GPIOA_USER_LED) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN15)) +#define VAL_GPIOA_ODR (PIN_ODR_LOW(GPIOA_ADC1_IN0) | \ + PIN_ODR_LOW(GPIOA_ADC1_IN1) | \ + PIN_ODR_LOW(GPIOA_USART2_TX) | \ + PIN_ODR_LOW(GPIOA_USART2_RX) | \ + PIN_ODR_LOW(GPIOA_ADC1_IN4) | \ + PIN_ODR_LOW(GPIOA_SPI1_SCLK) | \ + PIN_ODR_LOW(GPIOA_SPI1_MISO) | \ + PIN_ODR_LOW(GPIOA_SPI1_MOSI) | \ + PIN_ODR_HIGH(GPIOA_PIN8) | \ + PIN_ODR_LOW(GPIOA_USART1_TX) | \ + PIN_ODR_LOW(GPIOA_USART1_RX) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_ODR_LOW(GPIOA_USER_LED) | \ + PIN_ODR_HIGH(GPIOA_PIN14) | \ + PIN_ODR_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ADC1_IN0, 0U) | \ + PIN_AFIO_AF(GPIOA_ADC1_IN1, 0U) | \ + PIN_AFIO_AF(GPIOA_USART2_TX, 7U) | \ + PIN_AFIO_AF(GPIOA_USART2_RX, 7U) | \ + PIN_AFIO_AF(GPIOA_ADC1_IN4, 0U) | \ + PIN_AFIO_AF(GPIOA_SPI1_SCLK, 5U) | \ + PIN_AFIO_AF(GPIOA_SPI1_MISO, 5U) | \ + PIN_AFIO_AF(GPIOA_SPI1_MOSI, 5U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOA_USART1_TX, 7U) | \ + PIN_AFIO_AF(GPIOA_USART1_RX, 7U) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10U) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10U) | \ + PIN_AFIO_AF(GPIOA_USER_LED, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN15, 0U)) + +/* + * GPIOB setup: + * + * PB0 - PIN0 (input pullup). + * PB1 - PIN1 (input pullup). + * PB2 - PIN2 (input pullup). + * PB3 - PIN3 (input pullup). + * PB4 - PIN4 (input pullup). + * PB5 - PIN5 (input pullup). + * PB6 - PIN6 (input pullup). + * PB7 - PIN7 (input pullup). + * PB8 - I2C1_SCL (alternate 4). + * PB9 - I2C1_SDA (alternate 4). + * PB10 - ARD_D6 (input pullup). + * PB11 - PIN11 (input pullup). + * PB12 - PIN12 (input pullup). + * PB13 - SPI2_SCLK (alternate 5). + * PB14 - SPI2_MISO (alternate 5). + * PB15 - SPI2_MOSI (alternate 5). + */ +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \ + PIN_MODE_INPUT(GPIOB_PIN1) | \ + PIN_MODE_INPUT(GPIOB_PIN2) | \ + PIN_MODE_INPUT(GPIOB_PIN3) | \ + PIN_MODE_INPUT(GPIOB_PIN4) | \ + PIN_MODE_INPUT(GPIOB_PIN5) | \ + PIN_MODE_INPUT(GPIOB_PIN6) | \ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ + PIN_MODE_INPUT(GPIOB_PIN10) | \ + PIN_MODE_INPUT(GPIOB_PIN11) | \ + PIN_MODE_INPUT(GPIOB_PIN12) | \ + PIN_MODE_ALTERNATE(GPIOB_SPI2_SCLK) | \ + PIN_MODE_ALTERNATE(GPIOB_SPI2_MISO) | \ + PIN_MODE_ALTERNATE(GPIOB_SPI2_MOSI)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SPI2_SCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SPI2_MISO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SPI2_MOSI)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_PIN0) | \ + PIN_OSPEED_HIGH(GPIOB_PIN1) | \ + PIN_OSPEED_HIGH(GPIOB_PIN2) | \ + PIN_OSPEED_HIGH(GPIOB_PIN3) | \ + PIN_OSPEED_HIGH(GPIOB_PIN4) | \ + PIN_OSPEED_HIGH(GPIOB_PIN5) | \ + PIN_OSPEED_HIGH(GPIOB_PIN6) | \ + PIN_OSPEED_HIGH(GPIOB_PIN7) | \ + PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ + PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ + PIN_OSPEED_HIGH(GPIOB_PIN10) | \ + PIN_OSPEED_HIGH(GPIOB_PIN11) | \ + PIN_OSPEED_HIGH(GPIOB_PIN12) | \ + PIN_OSPEED_HIGH(GPIOB_SPI2_SCLK) | \ + PIN_OSPEED_HIGH(GPIOB_SPI2_MISO) | \ + PIN_OSPEED_HIGH(GPIOB_SPI2_MOSI)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOB_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOB_SPI2_SCLK) | \ + PIN_PUPDR_FLOATING(GPIOB_SPI2_MISO) | \ + PIN_PUPDR_FLOATING(GPIOB_SPI2_MOSI)) +#define VAL_GPIOB_ODR (PIN_ODR_LOW(GPIOB_PIN0) | \ + PIN_ODR_LOW(GPIOB_PIN1) | \ + PIN_ODR_LOW(GPIOB_PIN2) | \ + PIN_ODR_LOW(GPIOB_PIN3) | \ + PIN_ODR_LOW(GPIOB_PIN4) | \ + PIN_ODR_LOW(GPIOB_PIN5) | \ + PIN_ODR_LOW(GPIOB_PIN6) | \ + PIN_ODR_LOW(GPIOB_PIN7) | \ + PIN_ODR_LOW(GPIOB_I2C1_SCL) | \ + PIN_ODR_LOW(GPIOB_I2C1_SDA) | \ + PIN_ODR_LOW(GPIOB_PIN10) | \ + PIN_ODR_LOW(GPIOB_PIN11) | \ + PIN_ODR_LOW(GPIOB_PIN12) | \ + PIN_ODR_LOW(GPIOB_SPI2_SCLK) | \ + PIN_ODR_LOW(GPIOB_SPI2_MISO) | \ + PIN_ODR_LOW(GPIOB_SPI2_MOSI)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN7, 0U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4U) | \ + PIN_AFIO_AF(GPIOB_I2C1_SDA, 4U) | \ + PIN_AFIO_AF(GPIOB_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOB_SPI2_SCLK, 5U) | \ + PIN_AFIO_AF(GPIOB_SPI2_MISO, 5U) | \ + PIN_AFIO_AF(GPIOB_SPI2_MOSI, 5U)) + +/* + * GPIOC setup: + * + * PC0 - ARD_A5 ADC1_IN10 (input pullup). + * PC1 - ARD_A4 ADC1_IN11 (input pullup). + * PC2 - PIN2 (input pullup). + * PC3 - PIN3 (input pullup). + * PC4 - PIN4 (input pullup). + * PC5 - PIN5 (input pullup). + * PC6 - PIN6 = TX6 (Alternate8 floating). + * PC7 - PIN7 = RX6 (Alternate8 floating). + * PC8 - PIN8 (input pullup). + * PC9 - PIN9 (input pullup). + * PC10 - PIN10 (input pullup). + * PC11 - PIN11 (input pullup). + * PC12 - PIN12 (input pullup). + * PC13 - BUTTON (input floating). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ + PIN_MODE_INPUT(GPIOC_PIN1) | \ + PIN_MODE_INPUT(GPIOC_PIN2) | \ + PIN_MODE_INPUT(GPIOC_PIN3) | \ + PIN_MODE_INPUT(GPIOC_PIN4) | \ + PIN_MODE_INPUT(GPIOC_PIN5) | \ + PIN_MODE_ALTERNATE(GPIOC_USART6_TX) | \ + PIN_MODE_ALTERNATE(GPIOC_USART6_RX) | \ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_INPUT(GPIOC_PIN9) | \ + PIN_MODE_INPUT(GPIOC_PIN10) | \ + PIN_MODE_INPUT(GPIOC_PIN11) | \ + PIN_MODE_INPUT(GPIOC_PIN12) | \ + PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_USART6_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOC_USART6_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_PIN0) | \ + PIN_OSPEED_HIGH(GPIOC_PIN1) | \ + PIN_OSPEED_HIGH(GPIOC_PIN2) | \ + PIN_OSPEED_HIGH(GPIOC_PIN3) | \ + PIN_OSPEED_HIGH(GPIOC_PIN4) | \ + PIN_OSPEED_HIGH(GPIOC_PIN5) | \ + PIN_OSPEED_MEDIUM(GPIOC_USART6_TX) | \ + PIN_OSPEED_MEDIUM(GPIOC_USART6_RX) | \ + PIN_OSPEED_HIGH(GPIOC_PIN8) | \ + PIN_OSPEED_HIGH(GPIOC_PIN9) | \ + PIN_OSPEED_HIGH(GPIOC_PIN10) | \ + PIN_OSPEED_HIGH(GPIOC_PIN11) | \ + PIN_OSPEED_HIGH(GPIOC_PIN12) | \ + PIN_OSPEED_HIGH(GPIOC_PIN13) | \ + PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \ + PIN_OSPEED_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOC_USART6_TX) | \ + PIN_PUPDR_FLOATING(GPIOC_USART6_RX) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOC_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ + PIN_ODR_HIGH(GPIOC_PIN1) | \ + PIN_ODR_HIGH(GPIOC_PIN2) | \ + PIN_ODR_HIGH(GPIOC_PIN3) | \ + PIN_ODR_HIGH(GPIOC_PIN4) | \ + PIN_ODR_HIGH(GPIOC_PIN5) | \ + PIN_ODR_HIGH(GPIOC_USART6_TX) | \ + PIN_ODR_HIGH(GPIOC_USART6_RX) | \ + PIN_ODR_HIGH(GPIOC_PIN8) | \ + PIN_ODR_HIGH(GPIOC_PIN9) | \ + PIN_ODR_HIGH(GPIOC_PIN10) | \ + PIN_ODR_HIGH(GPIOC_PIN11) | \ + PIN_ODR_HIGH(GPIOC_PIN12) | \ + PIN_ODR_HIGH(GPIOC_PIN13) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOC_USART6_TX, 8U) | \ + PIN_AFIO_AF(GPIOC_USART6_RX, 8U)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) + +/* + * GPIOD setup: + * + * PD0 - PIN0 (input pullup). + * PD1 - PIN1 (input pullup). + * PD2 - PIN2 (input pullup). + * PD3 - PIN3 (input pullup). + * PD4 - PIN4 (input pullup). + * PD5 - PIN5 (input pullup). + * PD6 - PIN6 (input pullup). + * PD7 - PIN7 (input pullup). + * PD8 - PIN8 (input pullup). + * PD9 - PIN9 (input pullup). + * PD10 - PIN10 (input pullup). + * PD11 - PIN11 (input pullup). + * PD12 - PIN12 (input pullup). + * PD13 - PIN13 (input pullup). + * PD14 - PIN14 (input pullup). + * PD15 - PIN15 (input pullup). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ + PIN_MODE_INPUT(GPIOD_PIN1) | \ + PIN_MODE_INPUT(GPIOD_PIN2) | \ + PIN_MODE_INPUT(GPIOD_PIN3) | \ + PIN_MODE_INPUT(GPIOD_PIN4) | \ + PIN_MODE_INPUT(GPIOD_PIN5) | \ + PIN_MODE_INPUT(GPIOD_PIN6) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_INPUT(GPIOD_PIN8) | \ + PIN_MODE_INPUT(GPIOD_PIN9) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_PIN11) | \ + PIN_MODE_INPUT(GPIOD_PIN12) | \ + PIN_MODE_INPUT(GPIOD_PIN13) | \ + PIN_MODE_INPUT(GPIOD_PIN14) | \ + PIN_MODE_INPUT(GPIOD_PIN15)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ + PIN_OSPEED_HIGH(GPIOD_PIN1) | \ + PIN_OSPEED_HIGH(GPIOD_PIN2) | \ + PIN_OSPEED_HIGH(GPIOD_PIN3) | \ + PIN_OSPEED_HIGH(GPIOD_PIN4) | \ + PIN_OSPEED_HIGH(GPIOD_PIN5) | \ + PIN_OSPEED_HIGH(GPIOD_PIN6) | \ + PIN_OSPEED_HIGH(GPIOD_PIN7) | \ + PIN_OSPEED_HIGH(GPIOD_PIN8) | \ + PIN_OSPEED_HIGH(GPIOD_PIN9) | \ + PIN_OSPEED_HIGH(GPIOD_PIN10) | \ + PIN_OSPEED_HIGH(GPIOD_PIN11) | \ + PIN_OSPEED_HIGH(GPIOD_PIN12) | \ + PIN_OSPEED_HIGH(GPIOD_PIN13) | \ + PIN_OSPEED_HIGH(GPIOD_PIN14) | \ + PIN_OSPEED_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN15)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ + PIN_ODR_HIGH(GPIOD_PIN1) | \ + PIN_ODR_HIGH(GPIOD_PIN2) | \ + PIN_ODR_HIGH(GPIOD_PIN3) | \ + PIN_ODR_HIGH(GPIOD_PIN4) | \ + PIN_ODR_HIGH(GPIOD_PIN5) | \ + PIN_ODR_HIGH(GPIOD_PIN6) | \ + PIN_ODR_HIGH(GPIOD_PIN7) | \ + PIN_ODR_HIGH(GPIOD_PIN8) | \ + PIN_ODR_HIGH(GPIOD_PIN9) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_PIN11) | \ + PIN_ODR_HIGH(GPIOD_PIN12) | \ + PIN_ODR_HIGH(GPIOD_PIN13) | \ + PIN_ODR_HIGH(GPIOD_PIN14) | \ + PIN_ODR_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN15, 0U)) + +/* + * GPIOE setup: + * + * PE0 - PIN0 (input pullup). + * PE1 - PIN1 (input pullup). + * PE2 - PIN2 (input pullup). + * PE3 - PIN3 (input pullup). + * PE4 - PIN4 (input pullup). + * PE5 - PIN5 (input pullup). + * PE6 - PIN6 (input pullup). + * PE7 - PIN7 (input pullup). + * PE8 - PIN8 (input pullup). + * PE9 - PIN9 (input pullup). + * PE10 - PIN10 (input pullup). + * PE11 - PIN11 (input pullup). + * PE12 - PIN12 (input pullup). + * PE13 - PIN13 (input pullup). + * PE14 - PIN14 (input pullup). + * PE15 - PIN15 (input pullup). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ + PIN_MODE_INPUT(GPIOE_PIN1) | \ + PIN_MODE_INPUT(GPIOE_PIN2) | \ + PIN_MODE_INPUT(GPIOE_PIN3) | \ + PIN_MODE_INPUT(GPIOE_PIN4) | \ + PIN_MODE_INPUT(GPIOE_PIN5) | \ + PIN_MODE_INPUT(GPIOE_PIN6) | \ + PIN_MODE_INPUT(GPIOE_PIN7) | \ + PIN_MODE_INPUT(GPIOE_PIN8) | \ + PIN_MODE_INPUT(GPIOE_PIN9) | \ + PIN_MODE_INPUT(GPIOE_PIN10) | \ + PIN_MODE_INPUT(GPIOE_PIN11) | \ + PIN_MODE_INPUT(GPIOE_PIN12) | \ + PIN_MODE_INPUT(GPIOE_PIN13) | \ + PIN_MODE_INPUT(GPIOE_PIN14) | \ + PIN_MODE_INPUT(GPIOE_PIN15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ + PIN_OSPEED_HIGH(GPIOE_PIN1) | \ + PIN_OSPEED_HIGH(GPIOE_PIN2) | \ + PIN_OSPEED_HIGH(GPIOE_PIN3) | \ + PIN_OSPEED_HIGH(GPIOE_PIN4) | \ + PIN_OSPEED_HIGH(GPIOE_PIN5) | \ + PIN_OSPEED_HIGH(GPIOE_PIN6) | \ + PIN_OSPEED_HIGH(GPIOE_PIN7) | \ + PIN_OSPEED_HIGH(GPIOE_PIN8) | \ + PIN_OSPEED_HIGH(GPIOE_PIN9) | \ + PIN_OSPEED_HIGH(GPIOE_PIN10) | \ + PIN_OSPEED_HIGH(GPIOE_PIN11) | \ + PIN_OSPEED_HIGH(GPIOE_PIN12) | \ + PIN_OSPEED_HIGH(GPIOE_PIN13) | \ + PIN_OSPEED_HIGH(GPIOE_PIN14) | \ + PIN_OSPEED_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ + PIN_ODR_HIGH(GPIOE_PIN1) | \ + PIN_ODR_HIGH(GPIOE_PIN2) | \ + PIN_ODR_HIGH(GPIOE_PIN3) | \ + PIN_ODR_HIGH(GPIOE_PIN4) | \ + PIN_ODR_HIGH(GPIOE_PIN5) | \ + PIN_ODR_HIGH(GPIOE_PIN6) | \ + PIN_ODR_HIGH(GPIOE_PIN7) | \ + PIN_ODR_HIGH(GPIOE_PIN8) | \ + PIN_ODR_HIGH(GPIOE_PIN9) | \ + PIN_ODR_HIGH(GPIOE_PIN10) | \ + PIN_ODR_HIGH(GPIOE_PIN11) | \ + PIN_ODR_HIGH(GPIOE_PIN12) | \ + PIN_ODR_HIGH(GPIOE_PIN13) | \ + PIN_ODR_HIGH(GPIOE_PIN14) | \ + PIN_ODR_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN7, 0U)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN15, 0U)) + +/* + * GPIOF setup: + * + * PF0 - PIN0 (input pullup). + * PF1 - PIN1 (input pullup). + * PF2 - PIN2 (input pullup). + * PF3 - PIN3 (input pullup). + * PF4 - PIN4 (input pullup). + * PF5 - PIN5 (input pullup). + * PF6 - PIN6 (input pullup). + * PF7 - PIN7 (input pullup). + * PF8 - PIN8 (input pullup). + * PF9 - PIN9 (input pullup). + * PF10 - PIN10 (input pullup). + * PF11 - PIN11 (input pullup). + * PF12 - PIN12 (input pullup). + * PF13 - PIN13 (input pullup). + * PF14 - PIN14 (input pullup). + * PF15 - PIN15 (input pullup). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ + PIN_MODE_INPUT(GPIOF_PIN1) | \ + PIN_MODE_INPUT(GPIOF_PIN2) | \ + PIN_MODE_INPUT(GPIOF_PIN3) | \ + PIN_MODE_INPUT(GPIOF_PIN4) | \ + PIN_MODE_INPUT(GPIOF_PIN5) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_INPUT(GPIOF_PIN7) | \ + PIN_MODE_INPUT(GPIOF_PIN8) | \ + PIN_MODE_INPUT(GPIOF_PIN9) | \ + PIN_MODE_INPUT(GPIOF_PIN10) | \ + PIN_MODE_INPUT(GPIOF_PIN11) | \ + PIN_MODE_INPUT(GPIOF_PIN12) | \ + PIN_MODE_INPUT(GPIOF_PIN13) | \ + PIN_MODE_INPUT(GPIOF_PIN14) | \ + PIN_MODE_INPUT(GPIOF_PIN15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \ + PIN_OSPEED_HIGH(GPIOF_PIN1) | \ + PIN_OSPEED_HIGH(GPIOF_PIN2) | \ + PIN_OSPEED_HIGH(GPIOF_PIN3) | \ + PIN_OSPEED_HIGH(GPIOF_PIN4) | \ + PIN_OSPEED_HIGH(GPIOF_PIN5) | \ + PIN_OSPEED_HIGH(GPIOF_PIN6) | \ + PIN_OSPEED_HIGH(GPIOF_PIN7) | \ + PIN_OSPEED_HIGH(GPIOF_PIN8) | \ + PIN_OSPEED_HIGH(GPIOF_PIN9) | \ + PIN_OSPEED_HIGH(GPIOF_PIN10) | \ + PIN_OSPEED_HIGH(GPIOF_PIN11) | \ + PIN_OSPEED_HIGH(GPIOF_PIN12) | \ + PIN_OSPEED_HIGH(GPIOF_PIN13) | \ + PIN_OSPEED_HIGH(GPIOF_PIN14) | \ + PIN_OSPEED_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ + PIN_ODR_HIGH(GPIOF_PIN1) | \ + PIN_ODR_HIGH(GPIOF_PIN2) | \ + PIN_ODR_HIGH(GPIOF_PIN3) | \ + PIN_ODR_HIGH(GPIOF_PIN4) | \ + PIN_ODR_HIGH(GPIOF_PIN5) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_PIN7) | \ + PIN_ODR_HIGH(GPIOF_PIN8) | \ + PIN_ODR_HIGH(GPIOF_PIN9) | \ + PIN_ODR_HIGH(GPIOF_PIN10) | \ + PIN_ODR_HIGH(GPIOF_PIN11) | \ + PIN_ODR_HIGH(GPIOF_PIN12) | \ + PIN_ODR_HIGH(GPIOF_PIN13) | \ + PIN_ODR_HIGH(GPIOF_PIN14) | \ + PIN_ODR_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN7, 0U)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN15, 0U)) + +/* + * GPIOG setup: + * + * PG0 - PIN0 (input pullup). + * PG1 - PIN1 (input pullup). + * PG2 - PIN2 (input pullup). + * PG3 - PIN3 (input pullup). + * PG4 - PIN4 (input pullup). + * PG5 - PIN5 (input pullup). + * PG6 - PIN6 (input pullup). + * PG7 - PIN7 (input pullup). + * PG8 - PIN8 (input pullup). + * PG9 - PIN9 (input pullup). + * PG10 - PIN10 (input pullup). + * PG11 - PIN11 (input pullup). + * PG12 - PIN12 (input pullup). + * PG13 - PIN13 (input pullup). + * PG14 - PIN14 (input pullup). + * PG15 - PIN15 (input pullup). + */ +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \ + PIN_MODE_INPUT(GPIOG_PIN1) | \ + PIN_MODE_INPUT(GPIOG_PIN2) | \ + PIN_MODE_INPUT(GPIOG_PIN3) | \ + PIN_MODE_INPUT(GPIOG_PIN4) | \ + PIN_MODE_INPUT(GPIOG_PIN5) | \ + PIN_MODE_INPUT(GPIOG_PIN6) | \ + PIN_MODE_INPUT(GPIOG_PIN7) | \ + PIN_MODE_INPUT(GPIOG_PIN8) | \ + PIN_MODE_INPUT(GPIOG_PIN9) | \ + PIN_MODE_INPUT(GPIOG_PIN10) | \ + PIN_MODE_INPUT(GPIOG_PIN11) | \ + PIN_MODE_INPUT(GPIOG_PIN12) | \ + PIN_MODE_INPUT(GPIOG_PIN13) | \ + PIN_MODE_INPUT(GPIOG_PIN14) | \ + PIN_MODE_INPUT(GPIOG_PIN15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_PIN0) | \ + PIN_OSPEED_HIGH(GPIOG_PIN1) | \ + PIN_OSPEED_HIGH(GPIOG_PIN2) | \ + PIN_OSPEED_HIGH(GPIOG_PIN3) | \ + PIN_OSPEED_HIGH(GPIOG_PIN4) | \ + PIN_OSPEED_HIGH(GPIOG_PIN5) | \ + PIN_OSPEED_HIGH(GPIOG_PIN6) | \ + PIN_OSPEED_HIGH(GPIOG_PIN7) | \ + PIN_OSPEED_HIGH(GPIOG_PIN8) | \ + PIN_OSPEED_HIGH(GPIOG_PIN9) | \ + PIN_OSPEED_HIGH(GPIOG_PIN10) | \ + PIN_OSPEED_HIGH(GPIOG_PIN11) | \ + PIN_OSPEED_HIGH(GPIOG_PIN12) | \ + PIN_OSPEED_HIGH(GPIOG_PIN13) | \ + PIN_OSPEED_HIGH(GPIOG_PIN14) | \ + PIN_OSPEED_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ + PIN_ODR_HIGH(GPIOG_PIN1) | \ + PIN_ODR_HIGH(GPIOG_PIN2) | \ + PIN_ODR_HIGH(GPIOG_PIN3) | \ + PIN_ODR_HIGH(GPIOG_PIN4) | \ + PIN_ODR_HIGH(GPIOG_PIN5) | \ + PIN_ODR_HIGH(GPIOG_PIN6) | \ + PIN_ODR_HIGH(GPIOG_PIN7) | \ + PIN_ODR_HIGH(GPIOG_PIN8) | \ + PIN_ODR_HIGH(GPIOG_PIN9) | \ + PIN_ODR_HIGH(GPIOG_PIN10) | \ + PIN_ODR_HIGH(GPIOG_PIN11) | \ + PIN_ODR_HIGH(GPIOG_PIN12) | \ + PIN_ODR_HIGH(GPIOG_PIN13) | \ + PIN_ODR_HIGH(GPIOG_PIN14) | \ + PIN_ODR_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN7, 0U)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN15, 0U)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - PIN2 (input pullup). + * PH3 - PIN3 (input pullup). + * PH4 - PIN4 (input pullup). + * PH5 - PIN5 (input pullup). + * PH6 - PIN6 (input pullup). + * PH7 - PIN7 (input pullup). + * PH8 - PIN8 (input pullup). + * PH9 - PIN9 (input pullup). + * PH10 - PIN10 (input pullup). + * PH11 - PIN11 (input pullup). + * PH12 - PIN12 (input pullup). + * PH13 - PIN13 (input pullup). + * PH14 - PIN14 (input pullup). + * PH15 - PIN15 (input pullup). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOH_PIN2) | \ + PIN_MODE_INPUT(GPIOH_PIN3) | \ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_INPUT(GPIOH_PIN5) | \ + PIN_MODE_INPUT(GPIOH_PIN6) | \ + PIN_MODE_INPUT(GPIOH_PIN7) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ + PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ + PIN_OSPEED_HIGH(GPIOH_PIN2) | \ + PIN_OSPEED_HIGH(GPIOH_PIN3) | \ + PIN_OSPEED_HIGH(GPIOH_PIN4) | \ + PIN_OSPEED_HIGH(GPIOH_PIN5) | \ + PIN_OSPEED_HIGH(GPIOH_PIN6) | \ + PIN_OSPEED_HIGH(GPIOH_PIN7) | \ + PIN_OSPEED_HIGH(GPIOH_PIN8) | \ + PIN_OSPEED_HIGH(GPIOH_PIN9) | \ + PIN_OSPEED_HIGH(GPIOH_PIN10) | \ + PIN_OSPEED_HIGH(GPIOH_PIN11) | \ + PIN_OSPEED_HIGH(GPIOH_PIN12) | \ + PIN_OSPEED_HIGH(GPIOH_PIN13) | \ + PIN_OSPEED_HIGH(GPIOH_PIN14) | \ + PIN_OSPEED_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0U)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0U)) + +/* + * GPIOI setup: + * + * PI0 - PIN0 (input pullup). + * PI1 - PIN1 (input pullup). + * PI2 - PIN2 (input pullup). + * PI3 - PIN3 (input pullup). + * PI4 - PIN4 (input pullup). + * PI5 - PIN5 (input pullup). + * PI6 - PIN6 (input pullup). + * PI7 - PIN7 (input pullup). + * PI8 - PIN8 (input pullup). + * PI9 - PIN9 (input pullup). + * PI10 - PIN10 (input pullup). + * PI11 - PIN11 (input pullup). + * PI12 - PIN12 (input pullup). + * PI13 - PIN13 (input pullup). + * PI14 - PIN14 (input pullup). + * PI15 - PIN15 (input pullup). + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ + PIN_MODE_INPUT(GPIOI_PIN1) | \ + PIN_MODE_INPUT(GPIOI_PIN2) | \ + PIN_MODE_INPUT(GPIOI_PIN3) | \ + PIN_MODE_INPUT(GPIOI_PIN4) | \ + PIN_MODE_INPUT(GPIOI_PIN5) | \ + PIN_MODE_INPUT(GPIOI_PIN6) | \ + PIN_MODE_INPUT(GPIOI_PIN7) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_INPUT(GPIOI_PIN9) | \ + PIN_MODE_INPUT(GPIOI_PIN10) | \ + PIN_MODE_INPUT(GPIOI_PIN11) | \ + PIN_MODE_INPUT(GPIOI_PIN12) | \ + PIN_MODE_INPUT(GPIOI_PIN13) | \ + PIN_MODE_INPUT(GPIOI_PIN14) | \ + PIN_MODE_INPUT(GPIOI_PIN15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_HIGH(GPIOI_PIN0) | \ + PIN_OSPEED_HIGH(GPIOI_PIN1) | \ + PIN_OSPEED_HIGH(GPIOI_PIN2) | \ + PIN_OSPEED_HIGH(GPIOI_PIN3) | \ + PIN_OSPEED_HIGH(GPIOI_PIN4) | \ + PIN_OSPEED_HIGH(GPIOI_PIN5) | \ + PIN_OSPEED_HIGH(GPIOI_PIN6) | \ + PIN_OSPEED_HIGH(GPIOI_PIN7) | \ + PIN_OSPEED_HIGH(GPIOI_PIN8) | \ + PIN_OSPEED_HIGH(GPIOI_PIN9) | \ + PIN_OSPEED_HIGH(GPIOI_PIN10) | \ + PIN_OSPEED_HIGH(GPIOI_PIN11) | \ + PIN_OSPEED_HIGH(GPIOI_PIN12) | \ + PIN_OSPEED_HIGH(GPIOI_PIN13) | \ + PIN_OSPEED_HIGH(GPIOI_PIN14) | \ + PIN_OSPEED_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ + PIN_ODR_HIGH(GPIOI_PIN1) | \ + PIN_ODR_HIGH(GPIOI_PIN2) | \ + PIN_ODR_HIGH(GPIOI_PIN3) | \ + PIN_ODR_HIGH(GPIOI_PIN4) | \ + PIN_ODR_HIGH(GPIOI_PIN5) | \ + PIN_ODR_HIGH(GPIOI_PIN6) | \ + PIN_ODR_HIGH(GPIOI_PIN7) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_PIN9) | \ + PIN_ODR_HIGH(GPIOI_PIN10) | \ + PIN_ODR_HIGH(GPIOI_PIN11) | \ + PIN_ODR_HIGH(GPIOI_PIN12) | \ + PIN_ODR_HIGH(GPIOI_PIN13) | \ + PIN_ODR_HIGH(GPIOI_PIN14) | \ + PIN_ODR_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN7, 0U)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN15, 0U)) + +/* + * GPIOJ setup: + * + * PJ0 - PIN0 (input floating). + * PJ1 - PIN1 (input floating). + * PJ2 - PIN2 (input floating). + * PJ3 - PIN3 (input floating). + * PJ4 - PIN4 (input floating). + * PJ5 - PIN5 (input floating). + * PJ6 - PIN6 (input floating). + * PJ7 - PIN7 (input floating). + * PJ8 - PIN8 (input floating). + * PJ9 - PIN9 (input floating). + * PJ10 - PIN10 (input floating). + * PJ11 - PIN11 (input floating). + * PJ12 - PIN12 (input floating). + * PJ13 - PIN13 (input floating). + * PJ14 - PIN14 (input floating). + * PJ15 - PIN15 (input floating). + */ +#define VAL_GPIOJ_MODER (PIN_MODE_INPUT(GPIOJ_PIN0) | \ + PIN_MODE_INPUT(GPIOJ_PIN1) | \ + PIN_MODE_INPUT(GPIOJ_PIN2) | \ + PIN_MODE_INPUT(GPIOJ_PIN3) | \ + PIN_MODE_INPUT(GPIOJ_PIN4) | \ + PIN_MODE_INPUT(GPIOJ_PIN5) | \ + PIN_MODE_INPUT(GPIOJ_PIN6) | \ + PIN_MODE_INPUT(GPIOJ_PIN7) | \ + PIN_MODE_INPUT(GPIOJ_PIN8) | \ + PIN_MODE_INPUT(GPIOJ_PIN9) | \ + PIN_MODE_INPUT(GPIOJ_PIN10) | \ + PIN_MODE_INPUT(GPIOJ_PIN11) | \ + PIN_MODE_INPUT(GPIOJ_PIN12) | \ + PIN_MODE_INPUT(GPIOJ_PIN13) | \ + PIN_MODE_INPUT(GPIOJ_PIN14) | \ + PIN_MODE_INPUT(GPIOJ_PIN15)) +#define VAL_GPIOJ_OTYPER (PIN_OTYPE_PUSHPULL(GPIOJ_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN15)) +#define VAL_GPIOJ_OSPEEDR (PIN_OSPEED_HIGH(GPIOJ_PIN0) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN1) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN2) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN3) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN4) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN5) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN6) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN7) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN8) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN9) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN10) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN11) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN12) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN13) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN14) | \ + PIN_OSPEED_HIGH(GPIOJ_PIN15)) +#define VAL_GPIOJ_PUPDR (PIN_PUPDR_FLOATING(GPIOJ_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN15)) +#define VAL_GPIOJ_ODR (PIN_ODR_HIGH(GPIOJ_PIN0) | \ + PIN_ODR_HIGH(GPIOJ_PIN1) | \ + PIN_ODR_HIGH(GPIOJ_PIN2) | \ + PIN_ODR_HIGH(GPIOJ_PIN3) | \ + PIN_ODR_HIGH(GPIOJ_PIN4) | \ + PIN_ODR_HIGH(GPIOJ_PIN5) | \ + PIN_ODR_HIGH(GPIOJ_PIN6) | \ + PIN_ODR_HIGH(GPIOJ_PIN7) | \ + PIN_ODR_HIGH(GPIOJ_PIN8) | \ + PIN_ODR_HIGH(GPIOJ_PIN9) | \ + PIN_ODR_HIGH(GPIOJ_PIN10) | \ + PIN_ODR_HIGH(GPIOJ_PIN11) | \ + PIN_ODR_HIGH(GPIOJ_PIN12) | \ + PIN_ODR_HIGH(GPIOJ_PIN13) | \ + PIN_ODR_HIGH(GPIOJ_PIN14) | \ + PIN_ODR_HIGH(GPIOJ_PIN15)) +#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(GPIOJ_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN7, 0U)) +#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(GPIOJ_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN15, 0U)) + +/* + * GPIOK setup: + * + * PK0 - PIN0 (input floating). + * PK1 - PIN1 (input floating). + * PK2 - PIN2 (input floating). + * PK3 - PIN3 (input floating). + * PK4 - PIN4 (input floating). + * PK5 - PIN5 (input floating). + * PK6 - PIN6 (input floating). + * PK7 - PIN7 (input floating). + * PK8 - PIN8 (input floating). + * PK9 - PIN9 (input floating). + * PK10 - PIN10 (input floating). + * PK11 - PIN11 (input floating). + * PK12 - PIN12 (input floating). + * PK13 - PIN13 (input floating). + * PK14 - PIN14 (input floating). + * PK15 - PIN15 (input floating). + */ +#define VAL_GPIOK_MODER (PIN_MODE_INPUT(GPIOK_PIN0) | \ + PIN_MODE_INPUT(GPIOK_PIN1) | \ + PIN_MODE_INPUT(GPIOK_PIN2) | \ + PIN_MODE_INPUT(GPIOK_PIN3) | \ + PIN_MODE_INPUT(GPIOK_PIN4) | \ + PIN_MODE_INPUT(GPIOK_PIN5) | \ + PIN_MODE_INPUT(GPIOK_PIN6) | \ + PIN_MODE_INPUT(GPIOK_PIN7) | \ + PIN_MODE_INPUT(GPIOK_PIN8) | \ + PIN_MODE_INPUT(GPIOK_PIN9) | \ + PIN_MODE_INPUT(GPIOK_PIN10) | \ + PIN_MODE_INPUT(GPIOK_PIN11) | \ + PIN_MODE_INPUT(GPIOK_PIN12) | \ + PIN_MODE_INPUT(GPIOK_PIN13) | \ + PIN_MODE_INPUT(GPIOK_PIN14) | \ + PIN_MODE_INPUT(GPIOK_PIN15)) +#define VAL_GPIOK_OTYPER (PIN_OTYPE_PUSHPULL(GPIOK_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN15)) +#define VAL_GPIOK_OSPEEDR (PIN_OSPEED_HIGH(GPIOK_PIN0) | \ + PIN_OSPEED_HIGH(GPIOK_PIN1) | \ + PIN_OSPEED_HIGH(GPIOK_PIN2) | \ + PIN_OSPEED_HIGH(GPIOK_PIN3) | \ + PIN_OSPEED_HIGH(GPIOK_PIN4) | \ + PIN_OSPEED_HIGH(GPIOK_PIN5) | \ + PIN_OSPEED_HIGH(GPIOK_PIN6) | \ + PIN_OSPEED_HIGH(GPIOK_PIN7) | \ + PIN_OSPEED_HIGH(GPIOK_PIN8) | \ + PIN_OSPEED_HIGH(GPIOK_PIN9) | \ + PIN_OSPEED_HIGH(GPIOK_PIN10) | \ + PIN_OSPEED_HIGH(GPIOK_PIN11) | \ + PIN_OSPEED_HIGH(GPIOK_PIN12) | \ + PIN_OSPEED_HIGH(GPIOK_PIN13) | \ + PIN_OSPEED_HIGH(GPIOK_PIN14) | \ + PIN_OSPEED_HIGH(GPIOK_PIN15)) +#define VAL_GPIOK_PUPDR (PIN_PUPDR_FLOATING(GPIOK_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN15)) +#define VAL_GPIOK_ODR (PIN_ODR_HIGH(GPIOK_PIN0) | \ + PIN_ODR_HIGH(GPIOK_PIN1) | \ + PIN_ODR_HIGH(GPIOK_PIN2) | \ + PIN_ODR_HIGH(GPIOK_PIN3) | \ + PIN_ODR_HIGH(GPIOK_PIN4) | \ + PIN_ODR_HIGH(GPIOK_PIN5) | \ + PIN_ODR_HIGH(GPIOK_PIN6) | \ + PIN_ODR_HIGH(GPIOK_PIN7) | \ + PIN_ODR_HIGH(GPIOK_PIN8) | \ + PIN_ODR_HIGH(GPIOK_PIN9) | \ + PIN_ODR_HIGH(GPIOK_PIN10) | \ + PIN_ODR_HIGH(GPIOK_PIN11) | \ + PIN_ODR_HIGH(GPIOK_PIN12) | \ + PIN_ODR_HIGH(GPIOK_PIN13) | \ + PIN_ODR_HIGH(GPIOK_PIN14) | \ + PIN_ODR_HIGH(GPIOK_PIN15)) +#define VAL_GPIOK_AFRL (PIN_AFIO_AF(GPIOK_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN7, 0U)) +#define VAL_GPIOK_AFRH (PIN_AFIO_AF(GPIOK_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN15, 0U)) + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/common/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/common/CMakeLists.txt new file mode 100644 index 00000000..aa7f1d54 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/common/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/usbcfg.c") +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c") + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/common/Device_BlockStorage-DEBUG.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 00000000..0e822535 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,97 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +//16kB block +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 1 }, // 08000000 nanoBooter + { BlockRange_BLOCKTYPE_CODE , 2, 3 } // 08008000 nanoCLR +}; + +//64kB block +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 08010000 nanoCLR +}; + +//384kB block +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 1 }, // 08020000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 2, 5 } // 08040000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08010000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 6, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00080000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/common/Device_BlockStorage.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/common/Device_BlockStorage.c new file mode 100644 index 00000000..6e381213 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/common/Device_BlockStorage.c @@ -0,0 +1,97 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +//16kB block +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 0 }, // 08000000 nanoBooter + { BlockRange_BLOCKTYPE_CODE , 1, 3 } // 08004000 nanoCLR +}; + +//64kB block +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 08010000 nanoCLR +}; + +//384kB block +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 1 }, // 08020000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 2, 5 } // 08040000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08010000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 6, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00080000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/common/usbcfg.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/common/usbcfg.c new file mode 100644 index 00000000..a048c76f --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/common/usbcfg.c @@ -0,0 +1,435 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "hal.h" + +/* Virtual serial port over USB.*/ +SerialUSBDriver SDU1; + +/* + * Endpoints to be used for USBD1. + */ +#define USBD1_DATA_REQUEST_EP 1 +#define USBD1_DATA_AVAILABLE_EP 1 +#define USBD1_INTERRUPT_REQUEST_EP 2 + +// address for device unique ID +// valid for STM32F4 series +#define DEVICE_ID1 (0x1FFF7A10) +#define DEVICE_ID2 (0x1FFF7A14) +#define DEVICE_ID3 (0x1FFF7A18) + +// // size of string serial is 36 = 2 + 5x2 + 26 from silicon unique ID precedeed of string "NANO_" and descriptor codes +// #define USB_SIZ_STRING_SERIAL 36 + +//////////////////////////////////////////////// +// vendor +#define USB_STRING_VENDOR L"STMicroelectronics" +//////////////////////////////////////////////// + +// structure for USB Vendor with Unicode string +typedef struct usb_string_vendor +{ + uint8_t bLength; + uint8_t bDescriptorType; + wchar_t bPropertyData[sizeof(USB_STRING_VENDOR)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec) + +}usb_string_vendor; + + +///////////////////////////////////////////////////////////////////////// +// device description +#define USB_STRING_DEVICE_DESCRIPTION L"nanoFramework Virtual COM Port" +///////////////////////////////////////////////////////////////////////// + +// structure for USB device descriptor with Unicode string +typedef struct usb_string_device_description +{ + uint8_t bLength; + uint8_t bDescriptorType; + wchar_t bPropertyData[sizeof(USB_STRING_DEVICE_DESCRIPTION)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec) + +}usb_string_device_description; + + +///////////////////////////////////////////////////////////////////////// +// device serial number +// this will produce a string with NANO_ prefix followed +// by the hexadecimal representation of the silicon unique ID of the CPU +#define USB_STRING_SERIAL_NUMBER L"NANO_xxxxxxxxxxx" +///////////////////////////////////////////////////////////////////////// +#define INDEX_OF_WCHAR_FOR_UNIQUE_ID 5 + +// structure for USB serial number descriptor with Unicode string +typedef struct usb_string_serial_number +{ + uint8_t bLength; + uint8_t bDescriptorType; + wchar_t bPropertyData[sizeof(USB_STRING_SERIAL_NUMBER)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec) + +}usb_string_serial_number; + + +/* + * USB Device Descriptor. + */ +static const uint8_t vcom_device_descriptor_data[18] = { + USB_DESC_DEVICE (0x0200, /* bcdUSB (2.0). */ + 0x02, /* bDeviceClass (CDC). */ + 0x00, /* bDeviceSubClass. */ + 0x00, /* bDeviceProtocol. */ + 0x40, /* bMaxPacketSize. */ + 0x0483, /* idVendor (ST). */ + 0x5740, /* idProduct. */ + 0x0200, /* bcdDevice. */ + 1, /* iManufacturer. */ + 2, /* iProduct. */ + 3, /* iSerialNumber. */ + 1) /* bNumConfigurations. */ +}; + +/* + * Device Descriptor wrapper. + */ +static const USBDescriptor vcom_device_descriptor = { + sizeof vcom_device_descriptor_data, + vcom_device_descriptor_data +}; + +/* Configuration Descriptor tree for a CDC.*/ +static const uint8_t vcom_configuration_descriptor_data[67] = { + /* Configuration Descriptor.*/ + USB_DESC_CONFIGURATION(67, /* wTotalLength. */ + 0x02, /* bNumInterfaces. */ + 0x01, /* bConfigurationValue. */ + 0, /* iConfiguration. */ + 0xC0, /* bmAttributes (self powered). */ + 50), /* bMaxPower (100mA). */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x01, /* bNumEndpoints. */ + 0x02, /* bInterfaceClass (Communications + Interface Class, CDC section + 4.2). */ + 0x02, /* bInterfaceSubClass (Abstract + Control Model, CDC section 4.3). */ + 0x01, /* bInterfaceProtocol (AT commands, + CDC section 4.4). */ + 0), /* iInterface. */ + /* Header Functional Descriptor (CDC section 5.2.3).*/ + USB_DESC_BYTE (5), /* bLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header + Functional Descriptor. */ + USB_DESC_BCD (0x0110), /* bcdCDC. */ + /* Call Management Functional Descriptor. */ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */ + USB_DESC_BYTE (0x01), /* bDataInterface. */ + /* ACM Functional Descriptor.*/ + USB_DESC_BYTE (4), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract + Control Management Descriptor). */ + USB_DESC_BYTE (0x02), /* bmCapabilities. */ + /* Union Functional Descriptor.*/ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bMasterInterface (Communication + Class Interface). */ + USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class + Interface). */ + /* Endpoint 2 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_INTERRUPT_REQUEST_EP|0x80, + 0x03, /* bmAttributes (Interrupt). */ + 0x0008, /* wMaxPacketSize. */ + 0xFF), /* bInterval. */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x02, /* bNumEndpoints. */ + 0x0A, /* bInterfaceClass (Data Class + Interface, CDC section 4.5). */ + 0x00, /* bInterfaceSubClass (CDC section + 4.6). */ + 0x00, /* bInterfaceProtocol (CDC section + 4.7). */ + 0x00), /* iInterface. */ + /* Endpoint 3 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_AVAILABLE_EP, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00), /* bInterval. */ + /* Endpoint 1 Descriptor.*/ + USB_DESC_ENDPOINT (USBD1_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00) /* bInterval. */ +}; + +/* + * Configuration Descriptor wrapper. + */ +static const USBDescriptor vcom_configuration_descriptor = { + sizeof vcom_configuration_descriptor_data, + vcom_configuration_descriptor_data +}; + +/* + * U.S. English language identifier. + */ +static const uint8_t vcom_string0[] = { + USB_DESC_BYTE(4), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */ +}; + + +// Vendor string +static const usb_string_vendor usb_vendor = { + sizeof(usb_vendor), + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), + USB_STRING_VENDOR +}; + + +// Device Description string +static const usb_string_device_description usb_device_description = { + sizeof(usb_device_description), + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), + USB_STRING_DEVICE_DESCRIPTION +}; + + +// Serial Number string. +static usb_string_serial_number usb_serial_number = { + sizeof(usb_serial_number), + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), + USB_STRING_SERIAL_NUMBER +}; + + +/* + * Strings wrappers array. + */ +static const USBDescriptor vcom_strings[] = { + {sizeof vcom_string0, vcom_string0}, + {sizeof usb_vendor, (uint8_t*)(&usb_vendor)}, + {sizeof usb_device_description, (uint8_t*)(&usb_device_description)}, + {sizeof usb_serial_number, (uint8_t*)(&usb_serial_number)}, +}; + + +// Convert Hex 32Bits value into char +// value: value to convert +// pbuf: pointer to the buffer +// len: buffer length +void IntToUnicode(uint32_t value , uint8_t *pbuf, uint8_t len) +{ + uint8_t idx = 0; + + for( idx = 0; idx < len; idx ++) + { + if( ((value >> 28)) < 0xA ) + { + pbuf[ 2* idx] = (value >> 28) + '0'; + } + else + { + pbuf[2* idx] = (value >> 28) + 'A' - 10; + } + + value = value << 4; + + pbuf[ 2* idx + 1] = 0; + } +} + +// Create the serial number string descriptor +void Get_SerialNum(uint8_t* pbuf) +{ + uint32_t deviceserial0, deviceserial1, deviceserial2; + + deviceserial0 = *(uint32_t*)DEVICE_ID1; + deviceserial1 = *(uint32_t*)DEVICE_ID2; + deviceserial2 = *(uint32_t*)DEVICE_ID3; + + deviceserial0 += deviceserial2; + + if (deviceserial0 != 0) + { + IntToUnicode(deviceserial0, pbuf, 8); + pbuf += 16; + IntToUnicode(deviceserial1, pbuf, 4); + } +} + +/* + * Handles the GET_DESCRIPTOR callback. All required descriptors must be + * handled here. + */ +static const USBDescriptor *get_descriptor(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang) { + + (void)usbp; + (void)lang; + + switch (dtype) { + case USB_DESCRIPTOR_DEVICE: + return &vcom_device_descriptor; + case USB_DESCRIPTOR_CONFIGURATION: + return &vcom_configuration_descriptor; + case USB_DESCRIPTOR_STRING: + if (dindex < 4) + { + if(dindex == 3) + { + // request is for serial number + // get it from the silicon unique ID + Get_SerialNum((uint8_t*)&usb_serial_number.bPropertyData[INDEX_OF_WCHAR_FOR_UNIQUE_ID]); + } + + return &vcom_strings[dindex]; + } + } + return NULL; +} + +/** + * @brief IN EP1 state. + */ +static USBInEndpointState ep1instate; + +/** + * @brief OUT EP1 state. + */ +static USBOutEndpointState ep1outstate; + +/** + * @brief EP1 initialization structure (both IN and OUT). + */ +static const USBEndpointConfig ep1config = { + USB_EP_MODE_TYPE_BULK, + NULL, + sduDataTransmitted, + sduDataReceived, + 0x0040, + 0x0040, + &ep1instate, + &ep1outstate, + 2, + NULL +}; + +/** + * @brief IN EP2 state. + */ +static USBInEndpointState ep2instate; + +/** + * @brief EP2 initialization structure (IN only). + */ +static const USBEndpointConfig ep2config = { + USB_EP_MODE_TYPE_INTR, + NULL, + sduInterruptTransmitted, + NULL, + 0x0010, + 0x0000, + &ep2instate, + NULL, + 1, + NULL +}; + +/* + * Handles the USB driver global events. + */ +static void usb_event(USBDriver *usbp, usbevent_t event) { + extern SerialUSBDriver SDU1; + + switch (event) { + case USB_EVENT_ADDRESS: + return; + case USB_EVENT_CONFIGURED: + chSysLockFromISR(); + + /* Enables the endpoints specified into the configuration. + Note, this callback is invoked from an ISR so I-Class functions + must be used.*/ + usbInitEndpointI(usbp, USBD1_DATA_REQUEST_EP, &ep1config); + usbInitEndpointI(usbp, USBD1_INTERRUPT_REQUEST_EP, &ep2config); + + /* Resetting the state of the CDC subsystem.*/ + sduConfigureHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_RESET: + /* Falls into.*/ + case USB_EVENT_UNCONFIGURED: + /* Falls into.*/ + case USB_EVENT_SUSPEND: + chSysLockFromISR(); + + /* Disconnection event on suspend.*/ + sduSuspendHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_WAKEUP: + chSysLockFromISR(); + + /* Disconnection event on suspend.*/ + sduWakeupHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_STALLED: + return; + } + return; +} + +/* + * Handles the USB driver global events. + */ +static void sof_handler(USBDriver *usbp) { + + (void)usbp; + + osalSysLockFromISR(); + sduSOFHookI(&SDU1); + osalSysUnlockFromISR(); +} + +/* + * USB driver configuration. + */ +const USBConfig usbcfg = { + usb_event, + get_descriptor, + sduRequestsHook, + sof_handler +}; + +/* + * Serial over USB driver configuration. + */ +const SerialUSBConfig serusbcfg = { + &USBD1, + USBD1_DATA_REQUEST_EP, + USBD1_DATA_AVAILABLE_EP, + USBD1_INTERRUPT_REQUEST_EP +}; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/common/usbcfg.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/common/usbcfg.h new file mode 100644 index 00000000..167e1df8 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/common/usbcfg.h @@ -0,0 +1,17 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef USBCFG_H +#define USBCFG_H + +extern const USBConfig usbcfg; +extern SerialUSBConfig serusbcfg; +extern SerialUSBDriver SDU1; + +#endif /* USBCFG_H */ + +/** @} */ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/managed_helpers/I2M_OXYGEN_NF.Adc.cs b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/managed_helpers/I2M_OXYGEN_NF.Adc.cs new file mode 100644 index 00000000..16f88c5a --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/managed_helpers/I2M_OXYGEN_NF.Adc.cs @@ -0,0 +1,43 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +namespace nanoFramework.Targets.Community.I2M_OXYGEN_NF +{ + /// + /// Enumeration of ADC channels available in the community board I2M_OXYGEN_NF + /// + public static class AdcChannels + { + /// + /// Channel 0, exposed on PA0, connected to PA0 (ADC1 - IN0) + /// + public const int Channel_0 = 0; + + /// + /// Channel 1, exposed on PA1, connected to PA1 (ADC1 - IN1) + /// + public const int Channel_1 = 1; + + /// + /// Channel 2, exposed on PA4, connected to PA4 (ADC1 - IN4) + /// + public const int Channel_2 = 2; + + /// + /// Channel 3, internal temperature sensor, connected to ADC1 + /// + public const int Channel_TemperatureSensor = 3; + + /// + /// Channel 4, internal voltage reference, connected to ADC1 + /// + public const int Channel_VrefIn = 4; + + /// + /// Channel 5, connected to VBatt pin, ADC1 + /// + public const int Channel_Vbatt = 5; + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/managed_helpers/I2M_OXYGEN_NF.Gpio.cs b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/managed_helpers/I2M_OXYGEN_NF.Gpio.cs new file mode 100644 index 00000000..204b455d --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/managed_helpers/I2M_OXYGEN_NF.Gpio.cs @@ -0,0 +1,63 @@ +using System; + +namespace nanoFramework.Targets.Community.I2M_OXYGEN_NF +{ + public static class Gpio + { + /// + /// Output pin connected to the on-board user LED + /// + public const int UserLed = PA13; + + /// + /// Output pin used for controlling the power to the Rf sub-assembly + /// + public const int RfPower = PB3; + + /// + /// + /// + public const int PA0 = 0; + public const int PA1 = 1; + public const int PA2 = 2; + public const int PA3 = 3; + public const int PA4 = 4; + public const int PA5 = 5; + public const int PA6 = 6; + public const int PA7 = 7; + public const int PA8 = 8; + public const int PA9 = 9; + public const int PA10 = 10; + public const int PA11 = 11; + public const int PA12 = 12; + public const int PA13 = 13; + public const int PA14 = 14; + public const int PA15 = 15; + + /// + /// + /// + public const int PB0 = 16; + public const int PB1 = 17; + public const int PB2 = 18; + public const int PB3 = 19; + public const int PB4 = 20; + public const int PB5 = 21; + public const int PB6 = 22; + public const int PB7 = 23; + public const int PB8 = 24; + public const int PB9 = 25; + public const int PB10 = 26; + public const int PB11 = 27; + public const int PB12 = 28; + public const int PB13 = 29; + public const int PB14 = 30; + public const int PB15 = 31; + + /// + /// + /// + public const int PC0 = 32; + public const int PC1 = 33; + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/managed_helpers/README.md b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/managed_helpers/README.md new file mode 100644 index 00000000..551569ac --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/managed_helpers/README.md @@ -0,0 +1,6 @@ +## Managed code helpers + +This folder contains helper classes to make developers life easier when coding for this target board. + +* [Adc](I2M_OXYGEN_NF.Adc.cs) +* [Gpio](I2M_OXYGEN_NF.Gpio.cs) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/CMakeLists.txt new file mode 100644 index 00000000..291f47e1 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/CMakeLists.txt @@ -0,0 +1,9 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# # append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/STM32F411xE_booter-DEBUG.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/STM32F411xE_booter-DEBUG.ld new file mode 100644 index 00000000..704cbf78 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/STM32F411xE_booter-DEBUG.ld @@ -0,0 +1,80 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F411xE memory setup. + * + */ +MEMORY +{ + flash : org = 0x08000000, len = 32k /* space reserved for nanoBooter (1st two sectors 0x08000000 to 0x08007FFF)*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 128k /* SRAM1 */ + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Stacks rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/STM32F411xE_booter.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/STM32F411xE_booter.ld new file mode 100644 index 00000000..93940298 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/STM32F411xE_booter.ld @@ -0,0 +1,80 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F411xE memory setup. + * + */ +MEMORY +{ + flash : org = 0x08000000, len = 16k /* space reserved for nanoBooter (1st two sectors 0x08000000 to 0x08003FFF)*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 128k /* SRAM1 */ + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Stacks rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/chconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/chconf.h new file mode 100644 index 00000000..335e3fa4 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/chconf.h @@ -0,0 +1,616 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 1000 // this is 1 millisecond + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#define CH_CFG_INTERVALS_SIZE 32 + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_TIME_TYPES_SIZE 32 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES FALSE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS FALSE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT FALSE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES FALSE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_OBJ_FIFOS TRUE + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#define CH_CFG_USE_FACTORY FALSE + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 + +/** + * @brief Enables the registry of generic objects. + */ +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE + +/** + * @brief Enables factory for generic buffers. + */ +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE + +/** + * @brief Enables factory for semaphores. + */ +#define CH_CFG_FACTORY_SEMAPHORES TRUE + +/** + * @brief Enables factory for mailboxes. + */ +#define CH_CFG_FACTORY_MAILBOXES TRUE + +/** + * @brief Enables factory for objects FIFOs. + */ +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/halconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/halconf.h new file mode 100644 index 00000000..b970c22f --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/halconf.h @@ -0,0 +1,513 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/halconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/halconf_nf.h new file mode 100644 index 00000000..e35b7bec --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/halconf_nf.h @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +#if !defined(HAL_USE_STM32_RNG) +#define HAL_USE_STM32_RNG FALSE +#endif + +#endif // _HALCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/main.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/main.c new file mode 100644 index 00000000..404ff970 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/main.c @@ -0,0 +1,75 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); + +// Application entry point. +int main(void) { + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init SWO as soon as possible to make it available to output ASAP + #if (SWO_OUTPUT == TRUE) + SwoInit(); + #endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + osDelay(20); // Let init stabilize + + // check for valid CLR image + if(CheckValidCLRImage((uint32_t)&__nanoImage_end__)) + { + // there seems to be a valid CLR image + // launch nanoCLR + LaunchCLR((uint32_t)&__nanoImage_end__); + } + + // Initializes a serial-over-USB CDC driver. + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + // Activates the USB driver and then the USB bus pull-up on D+. + // Note, a delay is inserted in order to not have to disconnect the cable after a reset. + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1500); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // Normal main() thread + while (true) { + palSetPad(GPIOA, GPIOA_USER_LED); + osDelay(500); + palClearPad(GPIOA, GPIOA_USER_LED); + osDelay(500); + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/mcuconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/mcuconf.h new file mode 100644 index 00000000..7138056a --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/mcuconf.h @@ -0,0 +1,338 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF +#define STM32F411_MCUCONF + +/* + * HAL driver system settings. + */ + +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED FALSE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 12 +#define STM32_PLLN_VALUE 192 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 4 + +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSE +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 250 +#define STM32_SDC_READ_TIMEOUT_MS 25 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 TRUE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/mcuconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/mcuconf_nf.h new file mode 100644 index 00000000..574b9636 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/mcuconf_nf.h @@ -0,0 +1,10 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/target_board.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/target_board.h.in new file mode 100644 index 00000000..19531d9c --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoBooter/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOBOOTER_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/CMakeLists.txt new file mode 100644 index 00000000..e5496b7e --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/STM32F411xE_CLR-DEBUG.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/STM32F411xE_CLR-DEBUG.ld new file mode 100644 index 00000000..f1f0afc1 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/STM32F411xE_CLR-DEBUG.ld @@ -0,0 +1,76 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F411xE memory setup. + * Note: Only use of ram0. + */ +MEMORY +{ + flash : org = 0x08008000, len = 512k - 32k - 256k /* flash size less the space reserved for nanoBooter and application deployment*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x08040000, len = 256k /* space reserved for application deployment */ + ramvt : org = 0x20000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 128k /* SRAM1 */ + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/STM32F411xE_CLR.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/STM32F411xE_CLR.ld new file mode 100644 index 00000000..41fe4314 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/STM32F411xE_CLR.ld @@ -0,0 +1,76 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F411xE memory setup. + * Note: Only use of ram0. + */ +MEMORY +{ + flash : org = 0x08004000, len = 512k - 16k - 256k /* flash size less the space reserved for nanoBooter and application deployment*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x08040000, len = 256k /* space reserved for application deployment */ + ramvt : org = 0x20000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 128k /* SRAM1 */ + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/chconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/chconf.h new file mode 100644 index 00000000..3ce5c5aa --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/chconf.h @@ -0,0 +1,621 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 10000 + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#define CH_CFG_INTERVALS_SIZE 32 + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_TIME_TYPES_SIZE 32 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_OBJ_FIFOS TRUE + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#define CH_CFG_USE_FACTORY FALSE + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 + +/** + * @brief Enables the registry of generic objects. + */ +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE + +/** + * @brief Enables factory for generic buffers. + */ +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE + +/** + * @brief Enables factory for semaphores. + */ +#define CH_CFG_FACTORY_SEMAPHORES TRUE + +/** + * @brief Enables factory for mailboxes. + */ +#define CH_CFG_FACTORY_MAILBOXES TRUE + +/** + * @brief Enables factory for objects FIFOs. + */ +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +/////////////////////////////////////////////////////////////////////////////// +// address of vector table for nanoCLR +#define CORTEX_VTOR_INIT 0x08008000U +/////////////////////////////////////////////////////////////////////////////// + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/halconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/halconf.h new file mode 100644 index 00000000..a1e2b875 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/halconf.h @@ -0,0 +1,525 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +// #define HAL_USE_ADC TRUE +// #endif + +/** + * @brief Enables the CAN subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +// #define HAL_USE_CAN FALSE +// #endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +// /** +// * @brief Enables the DAC subsystem. +// */ +// #if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +// #define HAL_USE_DAC FALSE +// #endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +// this option is set at target_platform.h (from config file) +//#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +//#define HAL_USE_I2C TRUE +//#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +// #define HAL_USE_MAC TRUE +// #endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +// #define HAL_USE_PWM TRUE +// #endif + +/** + * @brief Enables the RTC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +// #define HAL_USE_RTC TRUE +// #endif + +/** + * @brief Enables the SDC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +// #define HAL_USE_SDC FALSE +// #endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + + +/** + * @brief Enables the SPI subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +// #define HAL_USE_SPI FALSE +// #endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +// #define HAL_USE_UART FALSE +// #endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +// #define HAL_USE_WDG FALSE +// #endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS TRUE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/halconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/halconf_nf.h new file mode 100644 index 00000000..e35b7bec --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/halconf_nf.h @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +#if !defined(HAL_USE_STM32_RNG) +#define HAL_USE_STM32_RNG FALSE +#endif + +#endif // _HALCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/main.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/main.c new file mode 100644 index 00000000..83f74065 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/main.c @@ -0,0 +1,79 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include "usbcfg.h" +#include +#include +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); +// declare CLRStartup thread here +osThreadDef(CLRStartupThread, osPriorityNormal, 4096, "CLRStartupThread"); + +// Application entry point. +int main(void) { + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init SWO as soon as possible to make it available to output ASAP + #if (SWO_OUTPUT == TRUE) + SwoInit(); + #endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // Start Watchdog + Watchdog_Init(); + + // Initializes a serial-over-USB CDC driver. + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + // Activates the USB driver and then the USB bus pull-up on D+. + // Note, a delay is inserted in order to not have to disconnect the cable after a reset + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1500); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // CLR settings to launch CLR thread + CLR_SETTINGS clrSettings; + (void)memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.EnterDebuggerLoopAfterExit = true; + + // create the CLR Startup thread + osThreadCreate(osThread(CLRStartupThread), &clrSettings); + + // EXT driver needs to be started from main + #if (HAL_USE_EXT == TRUE) + extStart(&EXTD1, &extInterruptsConfiguration); + #endif + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + while (true) { + osDelay(100); + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/mcuconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/mcuconf.h new file mode 100644 index 00000000..8416bc6e --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/mcuconf.h @@ -0,0 +1,338 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF +#define STM32F411_MCUCONF + +/* + * HAL driver system settings. + */ + + #define STM32_NO_INIT FALSE + #define STM32_HSI_ENABLED FALSE + #define STM32_LSI_ENABLED TRUE + #define STM32_HSE_ENABLED TRUE + #define STM32_LSE_ENABLED TRUE + #define STM32_CLOCK48_REQUIRED TRUE + #define STM32_SW STM32_SW_PLL + #define STM32_PLLSRC STM32_PLLSRC_HSE + #define STM32_PLLM_VALUE 12 + #define STM32_PLLN_VALUE 192 + #define STM32_PLLP_VALUE 2 + #define STM32_PLLQ_VALUE 4 + + #define STM32_HPRE STM32_HPRE_DIV1 + #define STM32_PPRE1 STM32_PPRE1_DIV4 + #define STM32_PPRE2 STM32_PPRE2_DIV2 + #define STM32_RTCSEL STM32_RTCSEL_LSE + #define STM32_RTCPRE_VALUE 8 + #define STM32_MCO1SEL STM32_MCO1SEL_HSE + #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 + #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK + #define STM32_MCO2PRE STM32_MCO2PRE_DIV5 + #define STM32_I2SSRC STM32_I2SSRC_CKIN + #define STM32_PLLI2SN_VALUE 192 + #define STM32_PLLI2SR_VALUE 5 + #define STM32_PVD_ENABLE FALSE + #define STM32_PLS STM32_PLS_LEV0 + #define STM32_BKPRAM_ENABLE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 TRUE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 TRUE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 TRUE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 250 +#define STM32_SDC_READ_TIMEOUT_MS 25 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 TRUE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 TRUE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG TRUE + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/mcuconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/mcuconf_nf.h new file mode 100644 index 00000000..574b9636 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/mcuconf_nf.h @@ -0,0 +1,10 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/nanoHAL.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/nanoHAL.cpp new file mode 100644 index 00000000..076a50fc --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/nanoHAL.cpp @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +void HAL_EnterBooterMode() +{ +} + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/target_board.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/target_board.h.in new file mode 100644 index 00000000..b980bc05 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/nanoCLR/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOCLR_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/resources/oxygen-pcb.jpeg b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/resources/oxygen-pcb.jpeg new file mode 100644 index 00000000..2cf5fbd6 Binary files /dev/null and b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/resources/oxygen-pcb.jpeg differ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/resources/oxygen.jpeg b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/resources/oxygen.jpeg new file mode 100644 index 00000000..71395c9f Binary files /dev/null and b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/resources/oxygen.jpeg differ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_BlockStorage.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_BlockStorage.c new file mode 100644 index 00000000..9e7c7f55 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_BlockStorage.c @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice STM32Flash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &STM32Flash_BlockStorageInterface, &Device_BlockStorageConfig, false); +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_BlockStorage.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_BlockStorage.h new file mode 100644 index 00000000..aa50b1b7 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_common.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_common.c new file mode 100644 index 00000000..c70f5865 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_common.c @@ -0,0 +1,31 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include "target_common.h" +#include + +HAL_SYSTEM_CONFIG HalSystemConfig = +{ + { true }, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, //ConvertCOM_DebugHandle(1), + 0, //ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + { RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size }, + { FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size } +}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; + +// this target uses DFU for updates +uint32_t GetTargetCapabilities() +{ + return TargetCapabilities_DfuUpdate; +}; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_common.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_common.h.in new file mode 100644 index 00000000..419f9f35 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_common.h.in @@ -0,0 +1,37 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x20000000) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x00020000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x08000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00080000) + +///////////////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////// +#define TARGETNAMESTRING "@CHIBIOS_BOARD@" +#define PLATFORMNAMESTRING "STM32F4" +/////////////////////////////////////////////// + +#endif /* _TARGET_COMMON_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_system_devices_dac_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_system_devices_dac_config.cpp new file mode 100644 index 00000000..88a70347 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_system_devices_dac_config.cpp @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_DAC_PORT_PIN_CHANNEL DacPortPinConfig[] = { + + // DAC1, channel 1, GPIO port A, pin 4 + {1, 1, GPIOA, 4}, + +}; + +const int DacChannelCount = ARRAYSIZE(DacPortPinConfig); diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_windows_devices_adc_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_windows_devices_adc_config.cpp new file mode 100644 index 00000000..9fd10764 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_windows_devices_adc_config.cpp @@ -0,0 +1,22 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_adc_native_target.h" + + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // ADC1 + {1, GPIOA, 0, ADC_CHANNEL_IN0}, + {1, GPIOA, 1, ADC_CHANNEL_IN1}, + {1, GPIOA, 4, ADC_CHANNEL_IN4}, + + // these are the internal sources, available only at ADC1 + {1, NULL, 0, ADC_CHANNEL_SENSOR}, + {1, NULL, 0, ADC_CHANNEL_VREFINT}, + {1, NULL, 0, ADC_CHANNEL_VBAT}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_windows_devices_i2c_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_windows_devices_i2c_config.cpp new file mode 100644 index 00000000..2a60a22f --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_windows_devices_i2c_config.cpp @@ -0,0 +1,18 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_i2c_native_target.h" + +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for SCL pin is: GPIOB +// port for SDA pin is: GPIOB +// SCL pin: is GPIOB_8 +// SDA pin: is GPIOB_9 +// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, GPIOB, GPIOB, 8, 9, 4) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_windows_devices_serialcommunication_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_windows_devices_serialcommunication_config.cpp new file mode 100644 index 00000000..ef8c9b10 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_windows_devices_serialcommunication_config.cpp @@ -0,0 +1,66 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_windows_devices_serialcommunication_config.h" +#include "win_dev_serial_native_target.h" + +/////////// +// UART1 // +/////////// + +// pin configuration for UART1 +// port: GPIOA +// TX pin: is GPIOA_9 +// RX pin: is GPIOA_10 +// GPIO alternate pin function is 7 (see "Table 9. Alternate function mapping" in STM32F411xC and STM32F411xE datasheet) +UART_CONFIG_PINS(1, GPIOA, GPIOA, 9, 10, 7) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart1_TxBuffer[UART1_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart1_RxBuffer[UART1_RX_SIZE]; + +// initialization for UART1 +UART_INIT(1, UART1_TX_SIZE, UART1_RX_SIZE) + +// un-initialization for UART1 +UART_UNINIT(1) + + +/////////// +// UART2 // +/////////// + +// pin configuration for UART2 +// port: GPIOA +// TX pin: is GPIOA_2 +// RX pin: is GPIOA_3 +// GPIO alternate pin function is 7 (see "Table 9. Alternate function mapping" in STM32F411xC and STM32F411xE datasheet) +UART_CONFIG_PINS(2, GPIOA, GPIOA, 2, 3, 7) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart2_TxBuffer[UART2_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart2_RxBuffer[UART2_RX_SIZE]; + +// initialization for UART2 +UART_INIT(2, UART2_TX_SIZE, UART2_RX_SIZE) + +// un-initialization for UART2 +UART_UNINIT(2) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_windows_devices_serialcommunication_config.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_windows_devices_serialcommunication_config.h new file mode 100644 index 00000000..dc1de238 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_windows_devices_serialcommunication_config.h @@ -0,0 +1,32 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +/////////// +// UART1 // +/////////// + +// enable USART1 +#define NF_SERIAL_COMM_STM32_UART_USE_USART1 TRUE + +// buffers size +// tx buffer size: 256 bytes +#define UART1_TX_SIZE 256 +// rx buffer size: 256 bytes +#define UART1_RX_SIZE 256 + + +/////////// +// UART2 // +/////////// + +// enable USART2 +#define NF_SERIAL_COMM_STM32_UART_USE_USART2 TRUE + +// buffers size +// tx buffer size: 1024 bytes +#define UART2_TX_SIZE 1024 +// rx buffer size: 1024 bytes +#define UART2_RX_SIZE 1024 diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_windows_devices_spi_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_windows_devices_spi_config.cpp new file mode 100644 index 00000000..ef2d3a10 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/I2M_OXYGEN_NF/target_windows_devices_spi_config.cpp @@ -0,0 +1,10 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_spi_native.h" + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/CMakeLists.txt new file mode 100644 index 00000000..e49d468a --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/CMakeLists.txt @@ -0,0 +1,213 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +cmake_minimum_required(VERSION 3.0) +ENABLE_LANGUAGE(ASM) + +# add header files with common OS definitions and board definitions specific for each image +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/target_common.h" @ONLY) + +set(NANOBOOTER_PROJECT_NAME "nanoBooter") +set(NANOCLR_PROJECT_NAME "nanoCLR") + +find_package(BuildUtils REQUIRED) +find_package(CHIBIOS REQUIRED) +find_package(ChibiOSnfOverlay REQUIRED) +find_package(WireProtocol REQUIRED) + +# packages for nanoFramework libraries +####################################### +# mandatory +find_package(NF_CoreCLR REQUIRED) + +####################################### +# optional + +# ChibiOS contrib repo +if(CHIBIOS_CONTRIB_REQUIRED) + find_package(ChibiOS-Contrib REQUIRED) +endif() + +# nF feature: debugger +if(NF_FEATURE_DEBUGGER) + find_package(NF_Debugger REQUIRED) + find_package(NF_Diagnostics REQUIRED) +endif() + +# nF feature: networking +if(USE_NETWORKING_OPTION) + find_package(CHIBIOS_LWIP REQUIRED) + find_package(NF_NETWORKING REQUIRED) +endif() + +# nF feature: filesystem +if(USE_FILESYSTEM_OPTION) + find_package(CHIBIOS_FATFS REQUIRED) +endif() + +####################################### + +add_subdirectory("common") +add_subdirectory("nanoBooter") +add_subdirectory("nanoCLR") + +####################### +# nanoBooter executable + +add_executable( + # executables for project, project sources + ${NANOBOOTER_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + "${CMAKE_CURRENT_SOURCE_DIR}/target_BlockStorage.c" + + # need to add configuration manager to allow get/store configuration blocks + "${PROJECT_SOURCE_DIR}/src/HAL/nanoHAL_ConfigurationManager_stubs.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOBOOTER_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOBOOTER_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOBOOTER_SOURCES} + + ${CHIBIOS_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} +) + +####################### +# nanoCLR executable + +add_executable( + # executables for project, project sources + ${NANOCLR_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + + # need to add configuration manager to allow get/store configuration blocks + "${PROJECT_SOURCE_DIR}/src/HAL/nanoHAL_ConfigurationManager_stubs.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOCLR_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOCLR_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOCLR_SOURCES} + + ${CHIBIOS_SOURCES} + ${CHIBIOS_CONTRIB_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} + + # sources for nanoFramework libraries + ${NF_CoreCLR_SOURCES} + ${NF_Debugger_SOURCES} + ${NF_Diagnostics_SOURCES} + + # sources for nanoFramework Network LWIP and Sockets + "${CHIBIOS_LWIP_SOURCES}" + ${NF_Networking_SOURCES} + + # sources for nanoFramework APIs + ${TARGET_NANO_APIS_SOURCES} +) + +# add dependency from ChibiOS (this is required to make sure the ChibiOS repo is downloaded before the build starts) +add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf ChibiOS) +add_dependencies(${NANOCLR_PROJECT_NAME}.elf ChibiOS) + +# include common directories +include_directories( + ${CMAKE_CURRENT_BINARY_DIR} + ${CMAKE_CURRENT_SOURCE_DIR} + ${CMAKE_CURRENT_SOURCE_DIR}/common + ${PROJECT_SOURCE_DIR}/src/CLR/Core + ${PROJECT_SOURCE_DIR}/src/CLR/Include + ${PROJECT_SOURCE_DIR}/src/HAL/Include + ${PROJECT_SOURCE_DIR}/src/PAL/Include + + ${WireProtocol_INCLUDE_DIRS} + ${CHIBIOS_INCLUDE_DIRS} + ${ChibiOSnfOverlay_INCLUDE_DIRS} + ${CHIBIOS_CONTRIB_INCLUDE_DIRS} + + ${TARGET_CMSIS_COMMON_INCLUDE_DIRS} + ${TARGET_CHIBIOS_COMMON_INCLUDE_DIRS} +) + +# include directories for nanoBooter +target_include_directories(${NANOBOOTER_PROJECT_NAME}.elf PUBLIC + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter" + ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter + + ${TARGET_CMSIS_NANOBOOTER_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOBOOTER_INCLUDE_DIRS} +) + +# include directories for nanoCLR +target_include_directories(${NANOCLR_PROJECT_NAME}.elf PUBLIC + ${CMAKE_CURRENT_BINARY_DIR}/nanoCLR + ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR + + ${TARGET_CMSIS_NANOCLR_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOCLR_INCLUDE_DIRS} + + # directories for nanoFramework libraries + ${NF_CoreCLR_INCLUDE_DIRS} + ${NF_Debugger_INCLUDE_DIRS} + ${NF_Diagnostics_INCLUDE_DIRS} + + # includes for nanoFramework APIs + ${TARGET_NANO_APIS_INCLUDES} + + # includes for ChibiOS LwIP + ${CHIBIOS_LWIP_INCLUDE_DIRS} + + # incudes for Networking + ${NF_Networking_INCLUDE_DIRS} +) + +# set compiler options +nf_set_compiler_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_options(${NANOCLR_PROJECT_NAME}.elf) + +# set compiler definitions +nf_set_compiler_definitions(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_definitions(${NANOCLR_PROJECT_NAME}.elf) + +# set linker files +if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F412xG_booter-DEBUG.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/STM32F412xG_CLR-DEBUG.ld) +else() + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F412xG_booter.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/STM32F412xG_CLR.ld) +endif() + +# set linker options +nf_set_linker_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_linker_options(${NANOCLR_PROJECT_NAME}.elf) + +# add other linker flags +########################################################### +# the sizes of CRT heap and ChibiOS stacks are defined here +set_property(TARGET ${NANOBOOTER_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x400,--defsym=__crt_heap_size__=0x1000") +set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x2800") + +# generate output files +nf_generate_build_output_files(${NANOBOOTER_PROJECT_NAME}.elf) +nf_generate_build_output_files(${NANOCLR_PROJECT_NAME}.elf) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/README.md b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/README.md new file mode 100644 index 00000000..e1c771eb --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/README.md @@ -0,0 +1,25 @@ +## ST of the shelve board ## + +The board used in this community contribution is the NUCLEO144_F412ZG board from ST. The board can be purchased from various sources and should be about 20 euros. Further information on the Nucleo144 boards can be found in the user manuals UM1727 or UM1974 on the ST side (www.st.com). + +Some basic information abstracted from ST: + +• STM32F412ZGT6 100MHz Cortex-M4F core microcontroller with 1MB Flash memory, 256KB SRAM +• Adaptive real-time accelerator (ART Accelerator™) allowing 0-wait state execution from Flash memory +• Full access to all GPIO with ST Zio connector (Arduino Uno v3 connectivity support) +• ST morpho extension pin headers for access to all GPIO +• ST-LINK/V2-1 debugger/programmer with SWD connector +• Up to 17 serial communication interfaces: USART, IrDA, I²C, SPI, LIN, CAN, USB, I²S, SDIO +• Flexible board power supply +• USB OTG or FS Device with micro-AB connector +• True random number generator +• CRC calculation unit +• RTC with subsecond accuracy and hardware calendar +• 96-bit unique ID +• 3 x LEDs: Power LED, USB communication, User LED +• User and Reset pushbuttons +• 32.768 KHz crystal oscillator + +Since the board has two MicroUSB connectors so you can use one for flashing the nanoFramework firmware and use for debugging purposes on the ST Link side and the other for a connection that can be used against VS to be recognized as a nanoFramework device to run your C# managed application. + + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/board.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/board.c new file mode 100644 index 00000000..aece76d4 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/board.c @@ -0,0 +1,266 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) + gpio_setup_t PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_setup_t PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) + gpio_setup_t PKData; +#endif +} gpio_config_t; + +/** + * @brief STM32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +#endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB1(STM32_GPIO_EN_MASK); + rccEnableAHB1(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG + gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI + gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ + gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK + gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + * else. + */ +void __early_init(void) { + + stm32_gpio_init(); + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { + +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/board.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/board.h new file mode 100644 index 00000000..d8297458 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/board.h @@ -0,0 +1,1846 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#ifndef BOARD_H +#define BOARD_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* + * Setup for STMicroelectronics STM32 Nucleo144-F412ZG board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_NUCLEO144_F412ZG_NF +#define BOARD_NAME "STMicroelectronics STM32 Nucleo144-F412ZG" + +/* + * Board oscillators-related settings. + * NOTE: LSE is fitted. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768U +#endif + +#define STM32_LSEDRV (3U << 3U) + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 8000000U +#endif + +#define STM32_HSE_BYPASS + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U + +/* + * MCU type as defined in the ST header. + */ +#define STM32F412Zx + +/* + * IO pins assignments. + */ +#define GPIOA_ZIO_D32 0U +#define GPIOA_TIM2_CH1 0U +#define GPIOA_PIN1 1U +#define GPIOA_ZIO_A8 2U +#define GPIOA_ADC1_IN2 2U +#define GPIOA_ARD_A0 3U +#define GPIOA_ADC1_IN3 3U +#define GPIOA_ZIO_D24 4U +#define GPIOA_SPI3_NSS 4U +#define GPIOA_ARD_D13 5U +#define GPIOA_SPI1_SCK 5U +#define GPIOA_ARD_D12 6U +#define GPIOA_SPI1_MISO 6U +#define GPIOA_ARD_D11 7U +#define GPIOA_SPI1_MOSI 7U +#define GPIOA_ZIO_D71 7U +#define GPIOA_USB_SOF 8U +#define GPIOA_USB_VBUS 9U +#define GPIOA_USB_ID 10U +#define GPIOA_USB_DM 11U +#define GPIOA_USB_DP 12U +#define GPIOA_SWDIO 13U +#define GPIOA_SWCLK 14U +#define GPIOA_ZIO_D20 15U +#define GPIOA_I2S3_WS 15U + +#define GPIOB_ZIO_D33 0U +#define GPIOB_TIM3_CH3 0U +#define GPIOB_LED1 0U +#define GPIOB_ZIO_A6 1U +#define GPIOB_ADC1_IN9 1U +#define GPIOB_ZIO_D27 2U +#define GPIOB_QUADSPI_CLK 2U +#define GPIOB_ZIO_D23 3U +#define GPIOB_I2S3_CK 3U +#define GPIOB_ZIO_D25 4U +#define GPIOB_SPI3_MISO 4U +#define GPIOB_ZIO_D22 5U +#define GPIOB_I2S3_SD 5U +#define GPIOB_ZIO_D26 6U +#define GPIOB_QUADSPI_BK1_NCS 6U +#define GPIOB_LED2 7U +#define GPIOB_ARD_D15 8U +#define GPIOB_I2C1_SCL 8U +#define GPIOB_ARD_D14 9U +#define GPIOB_I2C1_SDA 9U +#define GPIOB_ZIO_D36 10U +#define GPIOB_TIM2_CH3 10U +#define GPIOB_ZIO_D35 11U +#define GPIOB_TIM2_CH4 11U +#define GPIOB_ZIO_D19 12U +#define GPIOB_I2S2_WS 12U +#define GPIOB_ZIO_D18 13U +#define GPIOB_I2S2_CK 13U +#define GPIOB_LED3 14U +#define GPIOB_ZIO_D17 15U +#define GPIOB_I2S2_SD 15U + +#define GPIOC_ARD_A1 0U +#define GPIOC_ADC1_IN10 0U +#define GPIOC_ARD_A3 1U +#define GPIOC_ADC1_IN11 1U +#define GPIOC_ZIO_A7 2U +#define GPIOC_ADC1_IN12 2U +#define GPIOC_ARD_A2 3U +#define GPIOC_ADC1_IN13 3U +#define GPIOC_ARD_A4 4U +#define GPIOC_ADC1_IN14 4U +#define GPIOC_ARD_A5 5U +#define GPIOC_ADC1_IN15 5U +#define GPIOC_ZIO_D16 6U +#define GPIOC_I2S2_MCK 6U +#define GPIOC_ZIO_D21 7U +#define GPIOC_I2S3_MCK 7U +#define GPIOC_ZIO_D43 8U +#define GPIOC_SDMMC_D0 8U +#define GPIOC_ZIO_D44 9U +#define GPIOC_SDMMC_D1 9U +#define GPIOC_ZIO_D45 10U +#define GPIOC_SDMMC_D2 10U +#define GPIOC_ZIO_D46 11U +#define GPIOC_SDMMC_D3 11U +#define GPIOC_ZIO_D47 12U +#define GPIOC_SDMMC_CK 12U +#define GPIOC_BUTTON 13U +#define GPIOC_OSC32_IN 14U +#define GPIOC_OSC32_OUT 15U + +#define GPIOD_ZIO_D67 0U +#define GPIOD_CAN1_RX 0U +#define GPIOD_ZIO_D66 1U +#define GPIOD_CAN1_TX 1U +#define GPIOD_ZIO_D48 2U +#define GPIOD_SDMMC_CMD 2U +#define GPIOD_ZIO_D55 3U +#define GPIOD_USART2_CTS 3U +#define GPIOD_ZIO_D54 4U +#define GPIOD_USART2_RTS 4U +#define GPIOD_ZIO_D53 5U +#define GPIOD_USART2_TX 5U +#define GPIOD_ZIO_D52 6U +#define GPIOD_USART2_RX 6U +#define GPIOD_ZIO_D51 7U +#define GPIOD_USART2_SCLK 7U +#define GPIOD_USART3_RX 8U +#define GPIOD_STLK_RX 8U +#define GPIOD_USART3_TX 9U +#define GPIOD_STLK_TX 9U +#define GPIOD_PIN10 10U +#define GPIOD_ZIO_D30 11U +#define GPIOD_QUADSPI_BK1_IO0 11U +#define GPIOD_ZIO_D29 12U +#define GPIOD_QUADSPI_BK1_IO1 12U +#define GPIOD_ZIO_D28 13U +#define GPIOD_QUADSPI_BK1_IO3 13U +#define GPIOD_ARD_D10 14U +#define GPIOD_SPI1_NSS 14U +#define GPIOD_ARD_D9 15U +#define GPIOD_TIM4_CH4 15U + +#define GPIOE_ZIO_D34 0U +#define GPIOE_TIM4_ETR 0U +#define GPIOE_PIN1 1U +#define GPIOE_ZIO_D31 2U +#define GPIOE_ZIO_D56 2U +#define GPIOE_QUADSPI_BK1_IO2 2U +#define GPIOE_ZIO_D60 3U +#define GPIOE_SAI1_SD_B 3U +#define GPIOE_ZIO_D57 4U +#define GPIOE_SAI1_FS_A 4U +#define GPIOE_ZIO_D58 5U +#define GPIOE_SAI1_SCK_A 5U +#define GPIOE_ZIO_D59 6U +#define GPIOE_SAI1_SD_A 6U +#define GPIOE_ZIO_D41 7U +#define GPIOE_TIM1_ETR 7U +#define GPIOE_ZIO_D42 8U +#define GPIOE_TIM1_CH1N 8U +#define GPIOE_ARD_D6 9U +#define GPIOE_TIM1_CH1 9U +#define GPIOE_ZIO_D40 10U +#define GPIOE_TIM1_CH2N 10U +#define GPIOE_ARD_D5 11U +#define GPIOE_TIM1_CH2 11U +#define GPIOE_ZIO_D39 12U +#define GPIOE_TIM1_CH3N 12U +#define GPIOE_ARD_D3 13U +#define GPIOE_TIM1_CH3 13U +#define GPIOE_ZIO_D38 14U +#define GPIOE_ZIO_D37 15U +#define GPIOE_TIM1_BKIN1 15U + +#define GPIOF_ZIO_D68 0U +#define GPIOF_I2C2_SDA 0U +#define GPIOF_ZIO_D69 1U +#define GPIOF_I2C2_SCL 1U +#define GPIOF_ZIO_D70 2U +#define GPIOF_I2C2_SMBA 2U +#define GPIOF_PIN3 3U +#define GPIOF_PIN4 4U +#define GPIOF_PIN5 5U +#define GPIOF_PIN6 6U +#define GPIOF_ZIO_D62 7U +#define GPIOF_SAI1_MCLK_B 7U +#define GPIOF_ZIO_D61 8U +#define GPIOF_SAI1_SCK_B 8U +#define GPIOF_ZIO_D63 9U +#define GPIOF_SAI1_FS_B 9U +#define GPIOF_PIN10 10U +#define GPIOF_PIN11 11U +#define GPIOF_ARD_D8 12U +#define GPIOF_ARD_D7 13U +#define GPIOF_ARD_D4 14U +#define GPIOF_ARD_D2 15U + +#define GPIOG_ZIO_D65 0U +#define GPIOG_ZIO_D64 1U +#define GPIOG_ZIO_D49 2U +#define GPIOG_ZIO_D50 3U +#define GPIOG_PIN4 4U +#define GPIOG_PIN5 5U +#define GPIOG_USB_GPIO_OUT 6U +#define GPIOG_USB_GPIO_IN 7U +#define GPIOG_PIN8 8U +#define GPIOG_ARD_D0 9U +#define GPIOG_USART6_RX 9U +#define GPIOG_PIN10 10U +#define GPIOG_PIN11 11U +#define GPIOG_PIN12 12U +#define GPIOG_PIN13 13U +#define GPIOG_ARD_D1 14U +#define GPIOG_USART6_TX 14U +#define GPIOG_PIN15 15U + +#define GPIOH_OSC_IN 0U +#define GPIOH_OSC_OUT 1U +#define GPIOH_PIN2 2U +#define GPIOH_PIN3 3U +#define GPIOH_PIN4 4U +#define GPIOH_PIN5 5U +#define GPIOH_PIN6 6U +#define GPIOH_PIN7 7U +#define GPIOH_PIN8 8U +#define GPIOH_PIN9 9U +#define GPIOH_PIN10 10U +#define GPIOH_PIN11 11U +#define GPIOH_PIN12 12U +#define GPIOH_PIN13 13U +#define GPIOH_PIN14 14U +#define GPIOH_PIN15 15U + +#define GPIOI_PIN0 0U +#define GPIOI_PIN1 1U +#define GPIOI_PIN2 2U +#define GPIOI_PIN3 3U +#define GPIOI_PIN4 4U +#define GPIOI_PIN5 5U +#define GPIOI_PIN6 6U +#define GPIOI_PIN7 7U +#define GPIOI_PIN8 8U +#define GPIOI_PIN9 9U +#define GPIOI_PIN10 10U +#define GPIOI_PIN11 11U +#define GPIOI_PIN12 12U +#define GPIOI_PIN13 13U +#define GPIOI_PIN14 14U +#define GPIOI_PIN15 15U + +#define GPIOJ_PIN0 0U +#define GPIOJ_PIN1 1U +#define GPIOJ_PIN2 2U +#define GPIOJ_PIN3 3U +#define GPIOJ_PIN4 4U +#define GPIOJ_PIN5 5U +#define GPIOJ_PIN6 6U +#define GPIOJ_PIN7 7U +#define GPIOJ_PIN8 8U +#define GPIOJ_PIN9 9U +#define GPIOJ_PIN10 10U +#define GPIOJ_PIN11 11U +#define GPIOJ_PIN12 12U +#define GPIOJ_PIN13 13U +#define GPIOJ_PIN14 14U +#define GPIOJ_PIN15 15U + +#define GPIOK_PIN0 0U +#define GPIOK_PIN1 1U +#define GPIOK_PIN2 2U +#define GPIOK_PIN3 3U +#define GPIOK_PIN4 4U +#define GPIOK_PIN5 5U +#define GPIOK_PIN6 6U +#define GPIOK_PIN7 7U +#define GPIOK_PIN8 8U +#define GPIOK_PIN9 9U +#define GPIOK_PIN10 10U +#define GPIOK_PIN11 11U +#define GPIOK_PIN12 12U +#define GPIOK_PIN13 13U +#define GPIOK_PIN14 14U +#define GPIOK_PIN15 15U + +/* + * IO lines assignments. + */ +#define LINE_ZIO_D32 PAL_LINE(GPIOA, 0U) +#define LINE_TIM2_CH1 PAL_LINE(GPIOA, 0U) +#define LINE_ZIO_A8 PAL_LINE(GPIOA, 2U) +#define LINE_ADC1_IN2 PAL_LINE(GPIOA, 2U) +#define LINE_ARD_A0 PAL_LINE(GPIOA, 3U) +#define LINE_ADC1_IN3 PAL_LINE(GPIOA, 3U) +#define LINE_ZIO_D24 PAL_LINE(GPIOA, 4U) +#define LINE_SPI3_NSS PAL_LINE(GPIOA, 4U) +#define LINE_ARD_D13 PAL_LINE(GPIOA, 5U) +#define LINE_SPI1_SCK PAL_LINE(GPIOA, 5U) +#define LINE_ARD_D12 PAL_LINE(GPIOA, 6U) +#define LINE_SPI1_MISO PAL_LINE(GPIOA, 6U) +#define LINE_ARD_D11 PAL_LINE(GPIOA, 7U) +#define LINE_SPI1_MOSI PAL_LINE(GPIOA, 7U) +#define LINE_ZIO_D71 PAL_LINE(GPIOA, 7U) +#define LINE_USB_SOF PAL_LINE(GPIOA, 8U) +#define LINE_USB_VBUS PAL_LINE(GPIOA, 9U) +#define LINE_USB_ID PAL_LINE(GPIOA, 10U) +#define LINE_USB_DM PAL_LINE(GPIOA, 11U) +#define LINE_USB_DP PAL_LINE(GPIOA, 12U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) +#define LINE_ZIO_D20 PAL_LINE(GPIOA, 15U) +#define LINE_I2S3_WS PAL_LINE(GPIOA, 15U) +#define LINE_ZIO_D33 PAL_LINE(GPIOB, 0U) +#define LINE_TIM3_CH3 PAL_LINE(GPIOB, 0U) +#define LINE_LED1 PAL_LINE(GPIOB, 0U) +#define LINE_ZIO_A6 PAL_LINE(GPIOB, 1U) +#define LINE_ADC1_IN9 PAL_LINE(GPIOB, 1U) +#define LINE_ZIO_D27 PAL_LINE(GPIOB, 2U) +#define LINE_QUADSPI_CLK PAL_LINE(GPIOB, 2U) +#define LINE_ZIO_D23 PAL_LINE(GPIOB, 3U) +#define LINE_I2S3_CK PAL_LINE(GPIOB, 3U) +#define LINE_ZIO_D25 PAL_LINE(GPIOB, 4U) +#define LINE_SPI3_MISO PAL_LINE(GPIOB, 4U) +#define LINE_ZIO_D22 PAL_LINE(GPIOB, 5U) +#define LINE_I2S3_SD PAL_LINE(GPIOB, 5U) +#define LINE_ZIO_D26 PAL_LINE(GPIOB, 6U) +#define LINE_QUADSPI_BK1_NCS PAL_LINE(GPIOB, 6U) +#define LINE_LED2 PAL_LINE(GPIOB, 7U) +#define LINE_ARD_D15 PAL_LINE(GPIOB, 8U) +#define LINE_I2C1_SCL PAL_LINE(GPIOB, 8U) +#define LINE_ARD_D14 PAL_LINE(GPIOB, 9U) +#define LINE_I2C1_SDA PAL_LINE(GPIOB, 9U) +#define LINE_ZIO_D36 PAL_LINE(GPIOB, 10U) +#define LINE_TIM2_CH3 PAL_LINE(GPIOB, 10U) +#define LINE_ZIO_D35 PAL_LINE(GPIOB, 11U) +#define LINE_TIM2_CH4 PAL_LINE(GPIOB, 11U) +#define LINE_ZIO_D19 PAL_LINE(GPIOB, 12U) +#define LINE_I2S2_WS PAL_LINE(GPIOB, 12U) +#define LINE_ZIO_D18 PAL_LINE(GPIOB, 13U) +#define LINE_I2S2_CK PAL_LINE(GPIOB, 13U) +#define LINE_LED3 PAL_LINE(GPIOB, 14U) +#define LINE_ZIO_D17 PAL_LINE(GPIOB, 15U) +#define LINE_I2S2_SD PAL_LINE(GPIOB, 15U) +#define LINE_ARD_A1 PAL_LINE(GPIOC, 0U) +#define LINE_ADC1_IN10 PAL_LINE(GPIOC, 0U) +#define LINE_ARD_A3 PAL_LINE(GPIOC, 1U) +#define LINE_ADC1_IN11 PAL_LINE(GPIOC, 1U) +#define LINE_ZIO_A7 PAL_LINE(GPIOC, 2U) +#define LINE_ADC1_IN12 PAL_LINE(GPIOC, 2U) +#define LINE_ARD_A2 PAL_LINE(GPIOC, 3U) +#define LINE_ADC1_IN13 PAL_LINE(GPIOC, 3U) +#define LINE_ARD_A4 PAL_LINE(GPIOC, 4U) +#define LINE_ADC1_IN14 PAL_LINE(GPIOC, 4U) +#define LINE_ARD_A5 PAL_LINE(GPIOC, 5U) +#define LINE_ADC1_IN15 PAL_LINE(GPIOC, 5U) +#define LINE_ZIO_D16 PAL_LINE(GPIOC, 6U) +#define LINE_I2S2_MCK PAL_LINE(GPIOC, 6U) +#define LINE_ZIO_D21 PAL_LINE(GPIOC, 7U) +#define LINE_I2S3_MCK PAL_LINE(GPIOC, 7U) +#define LINE_ZIO_D43 PAL_LINE(GPIOC, 8U) +#define LINE_SDMMC_D0 PAL_LINE(GPIOC, 8U) +#define LINE_ZIO_D44 PAL_LINE(GPIOC, 9U) +#define LINE_SDMMC_D1 PAL_LINE(GPIOC, 9U) +#define LINE_ZIO_D45 PAL_LINE(GPIOC, 10U) +#define LINE_SDMMC_D2 PAL_LINE(GPIOC, 10U) +#define LINE_ZIO_D46 PAL_LINE(GPIOC, 11U) +#define LINE_SDMMC_D3 PAL_LINE(GPIOC, 11U) +#define LINE_ZIO_D47 PAL_LINE(GPIOC, 12U) +#define LINE_SDMMC_CK PAL_LINE(GPIOC, 12U) +#define LINE_BUTTON PAL_LINE(GPIOC, 13U) +#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) +#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) +#define LINE_ZIO_D67 PAL_LINE(GPIOD, 0U) +#define LINE_CAN1_RX PAL_LINE(GPIOD, 0U) +#define LINE_ZIO_D66 PAL_LINE(GPIOD, 1U) +#define LINE_CAN1_TX PAL_LINE(GPIOD, 1U) +#define LINE_ZIO_D48 PAL_LINE(GPIOD, 2U) +#define LINE_SDMMC_CMD PAL_LINE(GPIOD, 2U) +#define LINE_ZIO_D55 PAL_LINE(GPIOD, 3U) +#define LINE_USART2_CTS PAL_LINE(GPIOD, 3U) +#define LINE_ZIO_D54 PAL_LINE(GPIOD, 4U) +#define LINE_USART2_RTS PAL_LINE(GPIOD, 4U) +#define LINE_ZIO_D53 PAL_LINE(GPIOD, 5U) +#define LINE_USART2_TX PAL_LINE(GPIOD, 5U) +#define LINE_ZIO_D52 PAL_LINE(GPIOD, 6U) +#define LINE_USART2_RX PAL_LINE(GPIOD, 6U) +#define LINE_ZIO_D51 PAL_LINE(GPIOD, 7U) +#define LINE_USART2_SCLK PAL_LINE(GPIOD, 7U) +#define LINE_USART3_RX PAL_LINE(GPIOD, 8U) +#define LINE_STLK_RX PAL_LINE(GPIOD, 8U) +#define LINE_USART3_TX PAL_LINE(GPIOD, 9U) +#define LINE_STLK_TX PAL_LINE(GPIOD, 9U) +#define LINE_ZIO_D30 PAL_LINE(GPIOD, 11U) +#define LINE_QUADSPI_BK1_IO0 PAL_LINE(GPIOD, 11U) +#define LINE_ZIO_D29 PAL_LINE(GPIOD, 12U) +#define LINE_QUADSPI_BK1_IO1 PAL_LINE(GPIOD, 12U) +#define LINE_ZIO_D28 PAL_LINE(GPIOD, 13U) +#define LINE_QUADSPI_BK1_IO3 PAL_LINE(GPIOD, 13U) +#define LINE_ARD_D10 PAL_LINE(GPIOD, 14U) +#define LINE_SPI1_NSS PAL_LINE(GPIOD, 14U) +#define LINE_ARD_D9 PAL_LINE(GPIOD, 15U) +#define LINE_TIM4_CH4 PAL_LINE(GPIOD, 15U) +#define LINE_ZIO_D34 PAL_LINE(GPIOE, 0U) +#define LINE_TIM4_ETR PAL_LINE(GPIOE, 0U) +#define LINE_ZIO_D31 PAL_LINE(GPIOE, 2U) +#define LINE_ZIO_D56 PAL_LINE(GPIOE, 2U) +#define LINE_QUADSPI_BK1_IO2 PAL_LINE(GPIOE, 2U) +#define LINE_ZIO_D60 PAL_LINE(GPIOE, 3U) +#define LINE_SAI1_SD_B PAL_LINE(GPIOE, 3U) +#define LINE_ZIO_D57 PAL_LINE(GPIOE, 4U) +#define LINE_SAI1_FS_A PAL_LINE(GPIOE, 4U) +#define LINE_ZIO_D58 PAL_LINE(GPIOE, 5U) +#define LINE_SAI1_SCK_A PAL_LINE(GPIOE, 5U) +#define LINE_ZIO_D59 PAL_LINE(GPIOE, 6U) +#define LINE_SAI1_SD_A PAL_LINE(GPIOE, 6U) +#define LINE_ZIO_D41 PAL_LINE(GPIOE, 7U) +#define LINE_TIM1_ETR PAL_LINE(GPIOE, 7U) +#define LINE_ZIO_D42 PAL_LINE(GPIOE, 8U) +#define LINE_TIM1_CH1N PAL_LINE(GPIOE, 8U) +#define LINE_ARD_D6 PAL_LINE(GPIOE, 9U) +#define LINE_TIM1_CH1 PAL_LINE(GPIOE, 9U) +#define LINE_ZIO_D40 PAL_LINE(GPIOE, 10U) +#define LINE_TIM1_CH2N PAL_LINE(GPIOE, 10U) +#define LINE_ARD_D5 PAL_LINE(GPIOE, 11U) +#define LINE_TIM1_CH2 PAL_LINE(GPIOE, 11U) +#define LINE_ZIO_D39 PAL_LINE(GPIOE, 12U) +#define LINE_TIM1_CH3N PAL_LINE(GPIOE, 12U) +#define LINE_ARD_D3 PAL_LINE(GPIOE, 13U) +#define LINE_TIM1_CH3 PAL_LINE(GPIOE, 13U) +#define LINE_ZIO_D38 PAL_LINE(GPIOE, 14U) +#define LINE_ZIO_D37 PAL_LINE(GPIOE, 15U) +#define LINE_TIM1_BKIN1 PAL_LINE(GPIOE, 15U) +#define LINE_ZIO_D68 PAL_LINE(GPIOF, 0U) +#define LINE_I2C2_SDA PAL_LINE(GPIOF, 0U) +#define LINE_ZIO_D69 PAL_LINE(GPIOF, 1U) +#define LINE_I2C2_SCL PAL_LINE(GPIOF, 1U) +#define LINE_ZIO_D70 PAL_LINE(GPIOF, 2U) +#define LINE_I2C2_SMBA PAL_LINE(GPIOF, 2U) +#define LINE_ZIO_D62 PAL_LINE(GPIOF, 7U) +#define LINE_SAI1_MCLK_B PAL_LINE(GPIOF, 7U) +#define LINE_ZIO_D61 PAL_LINE(GPIOF, 8U) +#define LINE_SAI1_SCK_B PAL_LINE(GPIOF, 8U) +#define LINE_ZIO_D63 PAL_LINE(GPIOF, 9U) +#define LINE_SAI1_FS_B PAL_LINE(GPIOF, 9U) +#define LINE_ARD_D8 PAL_LINE(GPIOF, 12U) +#define LINE_ARD_D7 PAL_LINE(GPIOF, 13U) +#define LINE_ARD_D4 PAL_LINE(GPIOF, 14U) +#define LINE_ARD_D2 PAL_LINE(GPIOF, 15U) +#define LINE_ZIO_D65 PAL_LINE(GPIOG, 0U) +#define LINE_ZIO_D64 PAL_LINE(GPIOG, 1U) +#define LINE_ZIO_D49 PAL_LINE(GPIOG, 2U) +#define LINE_ZIO_D50 PAL_LINE(GPIOG, 3U) +#define LINE_USB_GPIO_OUT PAL_LINE(GPIOG, 6U) +#define LINE_USB_GPIO_IN PAL_LINE(GPIOG, 7U) +#define LINE_ARD_D0 PAL_LINE(GPIOG, 9U) +#define LINE_USART6_RX PAL_LINE(GPIOG, 9U) +#define LINE_ARD_D1 PAL_LINE(GPIOG, 14U) +#define LINE_USART6_TX PAL_LINE(GPIOG, 14U) +#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) +#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * GPIOA setup: + * + * PA0 - ZIO_D32 TIM2_CH1 (input pullup). + * PA1 - PIN1 (input pullup). + * PA2 - ZIO_A8 ADC1_IN2 (input pullup). + * PA3 - ARD_A0 ADC1_IN3 (input pullup). + * PA4 - ZIO_D24 SPI3_NSS (input pullup). + * PA5 - ARD_D13 SPI1_SCK (input pullup). + * PA6 - ARD_D12 SPI1_MISO (input pullup). + * PA7 - ARD_D11 SPI1_MOSI ZIO_D71 (input pullup). + * PA8 - USB_SOF (alternate 10). + * PA9 - USB_VBUS (analog). + * PA10 - USB_ID (alternate 10). + * PA11 - USB_DM (alternate 10). + * PA12 - USB_DP (alternate 10). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - ZIO_D20 I2S3_WS (alternate 6). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_ZIO_D32) | \ + PIN_MODE_INPUT(GPIOA_PIN1) | \ + PIN_MODE_INPUT(GPIOA_ZIO_A8) | \ + PIN_MODE_INPUT(GPIOA_ARD_A0) | \ + PIN_MODE_INPUT(GPIOA_ZIO_D24) | \ + PIN_MODE_INPUT(GPIOA_ARD_D13) | \ + PIN_MODE_INPUT(GPIOA_ARD_D12) | \ + PIN_MODE_INPUT(GPIOA_ARD_D11) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_SOF) | \ + PIN_MODE_ANALOG(GPIOA_USB_VBUS) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_ID) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_DP) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_ALTERNATE(GPIOA_ZIO_D20)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ZIO_D32) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ZIO_A8) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ZIO_D24) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D13) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D12) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D11) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_SOF) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_VBUS) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_ID) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ZIO_D20)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ZIO_D32) | \ + PIN_OSPEED_VERYLOW(GPIOA_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOA_ZIO_A8) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \ + PIN_OSPEED_HIGH(GPIOA_ZIO_D24) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D13) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D12) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D11) | \ + PIN_OSPEED_HIGH(GPIOA_USB_SOF) | \ + PIN_OSPEED_HIGH(GPIOA_USB_VBUS) | \ + PIN_OSPEED_HIGH(GPIOA_USB_ID) | \ + PIN_OSPEED_HIGH(GPIOA_USB_DM) | \ + PIN_OSPEED_HIGH(GPIOA_USB_DP) | \ + PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ + PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ + PIN_OSPEED_HIGH(GPIOA_ZIO_D20)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_ZIO_D32) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOA_ZIO_A8) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_A0) | \ + PIN_PUPDR_PULLUP(GPIOA_ZIO_D24) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D13) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D12) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D11) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_SOF) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_VBUS) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_ID) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_DM) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_DP) | \ + PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \ + PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \ + PIN_PUPDR_FLOATING(GPIOA_ZIO_D20)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_ZIO_D32) | \ + PIN_ODR_HIGH(GPIOA_PIN1) | \ + PIN_ODR_HIGH(GPIOA_ZIO_A8) | \ + PIN_ODR_HIGH(GPIOA_ARD_A0) | \ + PIN_ODR_HIGH(GPIOA_ZIO_D24) | \ + PIN_ODR_HIGH(GPIOA_ARD_D13) | \ + PIN_ODR_HIGH(GPIOA_ARD_D12) | \ + PIN_ODR_HIGH(GPIOA_ARD_D11) | \ + PIN_ODR_HIGH(GPIOA_USB_SOF) | \ + PIN_ODR_HIGH(GPIOA_USB_VBUS) | \ + PIN_ODR_HIGH(GPIOA_USB_ID) | \ + PIN_ODR_HIGH(GPIOA_USB_DM) | \ + PIN_ODR_HIGH(GPIOA_USB_DP) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_ZIO_D20)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ZIO_D32, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOA_ZIO_A8, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \ + PIN_AFIO_AF(GPIOA_ZIO_D24, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D13, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D12, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D11, 0U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_SOF, 10U) | \ + PIN_AFIO_AF(GPIOA_USB_VBUS, 0U) | \ + PIN_AFIO_AF(GPIOA_USB_ID, 10U) | \ + PIN_AFIO_AF(GPIOA_USB_DM, 10U) | \ + PIN_AFIO_AF(GPIOA_USB_DP, 10U) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ + PIN_AFIO_AF(GPIOA_ZIO_D20, 6U)) + +/* + * GPIOB setup: + * + * PB0 - ZIO_D33 TIM3_CH3 LED1 (output pushpull maximum). + * PB1 - ZIO_A6 ADC1_IN9 (input pullup). + * PB2 - ZIO_D27 QUADSPI_CLK (input pullup). + * PB3 - ZIO_D23 I2S3_CK (input pullup). + * PB4 - ZIO_D25 SPI3_MISO (input pullup). + * PB5 - ZIO_D22 I2S3_SD (input pullup). + * PB6 - ZIO_D26 QUADSPI_BK1_NCS (input pullup). + * PB7 - LED2 (output pushpull maximum). + * PB8 - ARD_D15 I2C1_SCL (input pullup). + * PB9 - ARD_D14 I2C1_SDA (input pullup). + * PB10 - ZIO_D36 TIM2_CH3 (input pullup). + * PB11 - ZIO_D35 TIM2_CH4 (input pullup). + * PB12 - ZIO_D19 I2S2_WS (input pullup). + * PB13 - ZIO_D18 I2S2_CK (input pullup). + * PB14 - LED3 (output pushpull maximum). + * PB15 - ZIO_D17 I2S2_SD (input pullup). + */ +#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_ZIO_D33) | \ + PIN_MODE_INPUT(GPIOB_ZIO_A6) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D27) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D23) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D25) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D22) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D26) | \ + PIN_MODE_OUTPUT(GPIOB_LED2) | \ + PIN_MODE_ALTERNATE(GPIOB_ARD_D15) | \ + PIN_MODE_ALTERNATE(GPIOB_ARD_D14) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D36) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D35) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D19) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D18) | \ + PIN_MODE_OUTPUT(GPIOB_LED3) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D17)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D33) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_A6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D27) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D23) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D25) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D22) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D26) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LED2) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_ARD_D15) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_ARD_D14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D36) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D35) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D19) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D18) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LED3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D17)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ZIO_D33) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_A6) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D27) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D23) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D25) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D22) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D26) | \ + PIN_OSPEED_HIGH(GPIOB_LED2) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D15) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D14) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D36) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D35) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D19) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D18) | \ + PIN_OSPEED_HIGH(GPIOB_LED3) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D17)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_ZIO_D33) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_A6) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D27) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D23) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D25) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D22) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D26) | \ + PIN_PUPDR_FLOATING(GPIOB_LED2) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D15) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D14) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D36) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D35) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D19) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D18) | \ + PIN_PUPDR_FLOATING(GPIOB_LED3) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D17)) +#define VAL_GPIOB_ODR (PIN_ODR_LOW(GPIOB_ZIO_D33) | \ + PIN_ODR_HIGH(GPIOB_ZIO_A6) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D27) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D23) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D25) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D22) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D26) | \ + PIN_ODR_LOW(GPIOB_LED2) | \ + PIN_ODR_LOW(GPIOB_ARD_D15) | \ + PIN_ODR_LOW(GPIOB_ARD_D14) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D36) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D35) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D19) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D18) | \ + PIN_ODR_LOW(GPIOB_LED3) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D17)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ZIO_D33, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_A6, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D27, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D23, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D25, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D22, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D26, 0U) | \ + PIN_AFIO_AF(GPIOB_LED2, 0U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_ARD_D15, 4U) | \ + PIN_AFIO_AF(GPIOB_ARD_D14, 4U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D36, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D35, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D19, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D18, 0U) | \ + PIN_AFIO_AF(GPIOB_LED3, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D17, 0U)) + +/* + * GPIOC setup: + * + * PC0 - ARD_A1 ADC1_IN10 (input pullup). + * PC1 - ARD_A3 ADC1_IN11 (input pullup). + * PC2 - ZIO_A7 ADC1_IN12 (input pullup). + * PC3 - ARD_A2 ADC1_IN13 (input pullup). + * PC4 - ARD_A4 ADC1_IN14 (input pullup). + * PC5 - ARD_A5 ADC1_IN15 (input pullup). + * PC6 - ZIO_D16 I2S2_MCK (input pullup). + * PC7 - ZIO_D21 I2S3_MCK (input pullup). + * PC8 - ZIO_D43 SDMMC_D0 (input pullup). + * PC9 - ZIO_D44 SDMMC_D1 (input pullup). + * PC10 - ZIO_D45 SDMMC_D2 (input pullup). + * PC11 - ZIO_D46 SDMMC_D3 (input pullup). + * PC12 - ZIO_D47 SDMMC_CK (input pullup). + * PC13 - BUTTON (input floating). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_ARD_A1) | \ + PIN_MODE_INPUT(GPIOC_ARD_A3) | \ + PIN_MODE_INPUT(GPIOC_ZIO_A7) | \ + PIN_MODE_INPUT(GPIOC_ARD_A2) | \ + PIN_MODE_INPUT(GPIOC_ARD_A4) | \ + PIN_MODE_INPUT(GPIOC_ARD_A5) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D16) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D21) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D43) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D44) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D45) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D46) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D47) | \ + PIN_MODE_INPUT(GPIOC_BUTTON) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ARD_A1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_A3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_A7) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_A2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_A4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_A5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D16) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D21) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D43) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D44) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D45) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D46) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D47) | \ + PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ARD_A1) | \ + PIN_OSPEED_VERYLOW(GPIOC_ARD_A3) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_A7) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_A2) | \ + PIN_OSPEED_VERYLOW(GPIOC_ARD_A4) | \ + PIN_OSPEED_VERYLOW(GPIOC_ARD_A5) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D16) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D21) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D43) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D44) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D45) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D46) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D47) | \ + PIN_OSPEED_HIGH(GPIOC_BUTTON) | \ + PIN_OSPEED_VERYLOW(GPIOC_OSC32_IN) | \ + PIN_OSPEED_VERYLOW(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_ARD_A1) | \ + PIN_PUPDR_PULLUP(GPIOC_ARD_A3) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_A7) | \ + PIN_PUPDR_PULLUP(GPIOC_ARD_A2) | \ + PIN_PUPDR_PULLUP(GPIOC_ARD_A4) | \ + PIN_PUPDR_PULLUP(GPIOC_ARD_A5) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D16) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D21) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D43) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D44) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D45) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D46) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D47) | \ + PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_ARD_A1) | \ + PIN_ODR_HIGH(GPIOC_ARD_A3) | \ + PIN_ODR_HIGH(GPIOC_ZIO_A7) | \ + PIN_ODR_HIGH(GPIOC_ARD_A2) | \ + PIN_ODR_HIGH(GPIOC_ARD_A4) | \ + PIN_ODR_HIGH(GPIOC_ARD_A5) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D16) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D21) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D43) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D44) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D45) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D46) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D47) | \ + PIN_ODR_HIGH(GPIOC_BUTTON) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ARD_A1, 0U) | \ + PIN_AFIO_AF(GPIOC_ARD_A3, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_A7, 0U) | \ + PIN_AFIO_AF(GPIOC_ARD_A2, 0U) | \ + PIN_AFIO_AF(GPIOC_ARD_A4, 0U) | \ + PIN_AFIO_AF(GPIOC_ARD_A5, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D16, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D21, 0U)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_ZIO_D43, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D44, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D45, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D46, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D47, 0U) | \ + PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) + +/* + * GPIOD setup: + * + * PD0 - ZIO_D67 CAN1_RX (input pullup). + * PD1 - ZIO_D66 CAN1_TX (input pullup). + * PD2 - ZIO_D48 SDMMC_CMD (input pullup). + * PD3 - ZIO_D55 USART2_CTS (input pullup). + * PD4 - ZIO_D54 USART2_RTS (input pullup). + * PD5 - ZIO_D53 USART2_TX (input pullup). + * PD6 - ZIO_D52 USART2_RX (input pullup). + * PD7 - ZIO_D51 USART2_SCLK (input pullup). + * PD8 - USART3_RX STLK_RX (alternate 7). + * PD9 - USART3_TX STLK_TX (alternate 7). + * PD10 - PIN10 (input pullup). + * PD11 - ZIO_D30 QUADSPI_BK1_IO0 (input pullup). + * PD12 - ZIO_D29 QUADSPI_BK1_IO1 (input pullup). + * PD13 - ZIO_D28 QUADSPI_BK1_IO3 (input pullup). + * PD14 - ARD_D10 SPI1_NSS (input pullup). + * PD15 - ARD_D9 TIM4_CH4 (input pullup). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_ZIO_D67) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D66) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D48) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D55) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D54) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D53) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D52) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D51) | \ + PIN_MODE_ALTERNATE(GPIOD_USART3_RX) | \ + PIN_MODE_ALTERNATE(GPIOD_USART3_TX) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D30) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D29) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D28) | \ + PIN_MODE_INPUT(GPIOD_ARD_D10) | \ + PIN_MODE_INPUT(GPIOD_ARD_D9)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D67) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D66) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D48) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D55) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D54) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D53) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D52) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D51) | \ + PIN_OTYPE_PUSHPULL(GPIOD_USART3_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_USART3_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D30) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D29) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D28) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ARD_D10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ARD_D9)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_ZIO_D67) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D66) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D48) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D55) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D54) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D53) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D52) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D51) | \ + PIN_OSPEED_HIGH(GPIOD_USART3_RX) | \ + PIN_OSPEED_HIGH(GPIOD_USART3_TX) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN10) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D30) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D29) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D28) | \ + PIN_OSPEED_HIGH(GPIOD_ARD_D10) | \ + PIN_OSPEED_HIGH(GPIOD_ARD_D9)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_ZIO_D67) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D66) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D48) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D55) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D54) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D53) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D52) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D51) | \ + PIN_PUPDR_FLOATING(GPIOD_USART3_RX) | \ + PIN_PUPDR_FLOATING(GPIOD_USART3_TX) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D30) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D29) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D28) | \ + PIN_PUPDR_PULLUP(GPIOD_ARD_D10) | \ + PIN_PUPDR_PULLUP(GPIOD_ARD_D9)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_ZIO_D67) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D66) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D48) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D55) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D54) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D53) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D52) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D51) | \ + PIN_ODR_HIGH(GPIOD_USART3_RX) | \ + PIN_ODR_HIGH(GPIOD_USART3_TX) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D30) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D29) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D28) | \ + PIN_ODR_HIGH(GPIOD_ARD_D10) | \ + PIN_ODR_HIGH(GPIOD_ARD_D9)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_ZIO_D67, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D66, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D48, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D55, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D54, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D53, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D52, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D51, 0U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_USART3_RX, 7U) | \ + PIN_AFIO_AF(GPIOD_USART3_TX, 7U) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D30, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D29, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D28, 0U) | \ + PIN_AFIO_AF(GPIOD_ARD_D10, 0U) | \ + PIN_AFIO_AF(GPIOD_ARD_D9, 0U)) + +/* + * GPIOE setup: + * + * PE0 - ZIO_D34 TIM4_ETR (input pullup). + * PE1 - PIN1 (input pullup). + * PE2 - ZIO_D31 ZIO_D56 QUADSPI_BK1_IO2(input pullup). + * PE3 - ZIO_D60 SAI1_SD_B (input pullup). + * PE4 - ZIO_D57 SAI1_FS_A (input pullup). + * PE5 - ZIO_D58 SAI1_SCK_A (input pullup). + * PE6 - ZIO_D59 SAI1_SD_A (input pullup). + * PE7 - ZIO_D41 TIM1_ETR (input pullup). + * PE8 - ZIO_D42 TIM1_CH1N (input pullup). + * PE9 - ARD_D6 TIM1_CH1 (input pullup). + * PE10 - ZIO_D40 TIM1_CH2N (input pullup). + * PE11 - ARD_D5 TIM1_CH2 (input pullup). + * PE12 - ZIO_D39 TIM1_CH3N (input pullup). + * PE13 - ARD_D3 TIM1_CH3 (input pullup). + * PE14 - ZIO_D38 (input pullup). + * PE15 - ZIO_D37 TIM1_BKIN1 (input pullup). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_ZIO_D34) | \ + PIN_MODE_INPUT(GPIOE_PIN1) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D31) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D60) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D57) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D58) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D59) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D41) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D42) | \ + PIN_MODE_INPUT(GPIOE_ARD_D6) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D40) | \ + PIN_MODE_INPUT(GPIOE_ARD_D5) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D39) | \ + PIN_MODE_INPUT(GPIOE_ARD_D3) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D38) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D37)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D34) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D31) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D60) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D57) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D58) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D59) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D41) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D42) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ARD_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D40) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ARD_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D39) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ARD_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D38) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D37)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_ZIO_D34) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN1) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D31) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D60) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D57) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D58) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D59) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D41) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D42) | \ + PIN_OSPEED_HIGH(GPIOE_ARD_D6) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D40) | \ + PIN_OSPEED_HIGH(GPIOE_ARD_D5) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D39) | \ + PIN_OSPEED_HIGH(GPIOE_ARD_D3) | \ + PIN_OSPEED_VERYLOW(GPIOE_ZIO_D38) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D37)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_ZIO_D34) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D31) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D60) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D57) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D58) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D59) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D41) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D42) | \ + PIN_PUPDR_PULLUP(GPIOE_ARD_D6) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D40) | \ + PIN_PUPDR_PULLUP(GPIOE_ARD_D5) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D39) | \ + PIN_PUPDR_PULLUP(GPIOE_ARD_D3) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D38) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D37)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_ZIO_D34) | \ + PIN_ODR_HIGH(GPIOE_PIN1) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D31) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D60) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D57) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D58) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D59) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D41) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D42) | \ + PIN_ODR_HIGH(GPIOE_ARD_D6) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D40) | \ + PIN_ODR_HIGH(GPIOE_ARD_D5) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D39) | \ + PIN_ODR_HIGH(GPIOE_ARD_D3) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D38) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D37)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_ZIO_D34, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D31, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D60, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D57, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D58, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D59, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D41, 0U)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_ZIO_D42, 0U) | \ + PIN_AFIO_AF(GPIOE_ARD_D6, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D40, 0U) | \ + PIN_AFIO_AF(GPIOE_ARD_D5, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D39, 0U) | \ + PIN_AFIO_AF(GPIOE_ARD_D3, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D38, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D37, 0U)) + +/* + * GPIOF setup: + * + * PF0 - ZIO_D68 I2C2_SDA (input pullup). + * PF1 - ZIO_D69 I2C2_SCL (input pullup). + * PF2 - ZIO_D70 I2C2_SMBA (input pullup). + * PF3 - PIN3 (input pullup). + * PF4 - PIN4 (input pullup). + * PF5 - PIN5 (input pullup). + * PF6 - PIN6 (input pullup). + * PF7 - ZIO_D62 SAI1_MCLK_B (input pullup). + * PF8 - ZIO_D61 SAI1_SCK_B (input pullup). + * PF9 - ZIO_D63 SAI1_FS_B (input pullup). + * PF10 - PIN10 (input pullup). + * PF11 - PIN11 (input pullup). + * PF12 - ARD_D8 (input pullup). + * PF13 - ARD_D7 (input pullup). + * PF14 - ARD_D4 (input pullup). + * PF15 - ARD_D2 (input pullup). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_ZIO_D68) | \ + PIN_MODE_INPUT(GPIOF_ZIO_D69) | \ + PIN_MODE_INPUT(GPIOF_ZIO_D70) | \ + PIN_MODE_INPUT(GPIOF_PIN3) | \ + PIN_MODE_INPUT(GPIOF_PIN4) | \ + PIN_MODE_INPUT(GPIOF_PIN5) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_INPUT(GPIOF_ZIO_D62) | \ + PIN_MODE_INPUT(GPIOF_ZIO_D61) | \ + PIN_MODE_INPUT(GPIOF_ZIO_D63) | \ + PIN_MODE_INPUT(GPIOF_PIN10) | \ + PIN_MODE_INPUT(GPIOF_PIN11) | \ + PIN_MODE_INPUT(GPIOF_ARD_D8) | \ + PIN_MODE_INPUT(GPIOF_ARD_D7) | \ + PIN_MODE_INPUT(GPIOF_ARD_D4) | \ + PIN_MODE_INPUT(GPIOF_ARD_D2)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D68) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D69) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D70) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D62) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D61) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D63) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D2)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_ZIO_D68) | \ + PIN_OSPEED_HIGH(GPIOF_ZIO_D69) | \ + PIN_OSPEED_HIGH(GPIOF_ZIO_D70) | \ + PIN_OSPEED_HIGH(GPIOF_PIN3) | \ + PIN_OSPEED_HIGH(GPIOF_PIN4) | \ + PIN_OSPEED_HIGH(GPIOF_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN6) | \ + PIN_OSPEED_HIGH(GPIOF_ZIO_D62) | \ + PIN_OSPEED_HIGH(GPIOF_ZIO_D61) | \ + PIN_OSPEED_HIGH(GPIOF_ZIO_D63) | \ + PIN_OSPEED_HIGH(GPIOF_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOF_ARD_D8) | \ + PIN_OSPEED_VERYLOW(GPIOF_ARD_D7) | \ + PIN_OSPEED_VERYLOW(GPIOF_ARD_D4) | \ + PIN_OSPEED_VERYLOW(GPIOF_ARD_D2)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_ZIO_D68) | \ + PIN_PUPDR_PULLUP(GPIOF_ZIO_D69) | \ + PIN_PUPDR_PULLUP(GPIOF_ZIO_D70) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOF_ZIO_D62) | \ + PIN_PUPDR_PULLUP(GPIOF_ZIO_D61) | \ + PIN_PUPDR_PULLUP(GPIOF_ZIO_D63) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D8) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D7) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D4) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D2)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_ZIO_D68) | \ + PIN_ODR_HIGH(GPIOF_ZIO_D69) | \ + PIN_ODR_HIGH(GPIOF_ZIO_D70) | \ + PIN_ODR_HIGH(GPIOF_PIN3) | \ + PIN_ODR_HIGH(GPIOF_PIN4) | \ + PIN_ODR_HIGH(GPIOF_PIN5) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_ZIO_D62) | \ + PIN_ODR_HIGH(GPIOF_ZIO_D61) | \ + PIN_ODR_HIGH(GPIOF_ZIO_D63) | \ + PIN_ODR_HIGH(GPIOF_PIN10) | \ + PIN_ODR_HIGH(GPIOF_PIN11) | \ + PIN_ODR_HIGH(GPIOF_ARD_D8) | \ + PIN_ODR_HIGH(GPIOF_ARD_D7) | \ + PIN_ODR_HIGH(GPIOF_ARD_D4) | \ + PIN_ODR_HIGH(GPIOF_ARD_D2)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_ZIO_D68, 0U) | \ + PIN_AFIO_AF(GPIOF_ZIO_D69, 0U) | \ + PIN_AFIO_AF(GPIOF_ZIO_D70, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOF_ZIO_D62, 0U)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_ZIO_D61, 0U) | \ + PIN_AFIO_AF(GPIOF_ZIO_D63, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_D8, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_D7, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_D4, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_D2, 0U)) + +/* + * GPIOG setup: + * + * PG0 - ZIO_D65 (input pullup). + * PG1 - ZIO_D64 (input pullup). + * PG2 - ZIO_D49 (input pullup). + * PG3 - ZIO_D50 (input pullup). + * PG4 - PIN4 (input pullup). + * PG5 - PIN5 (input pullup). + * PG6 - USB_GPIO_OUT (output pushpull maximum). + * PG7 - USB_GPIO_IN (input pullup). + * PG8 - PIN8 (input pullup). + * PG9 - ARD_D0 USART6_RX (input pullup). + * PG10 - PIN10 (input pullup). + * PG11 - PIN11 (input pullup). + * PG12 - PIN12 (input pullup). + * PG13 - PIN13 (input pullup). + * PG14 - ARD_D1 USART6_TX (input pullup). + * PG15 - PIN15 (input pullup). + */ +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_ZIO_D65) | \ + PIN_MODE_INPUT(GPIOG_ZIO_D64) | \ + PIN_MODE_INPUT(GPIOG_ZIO_D49) | \ + PIN_MODE_INPUT(GPIOG_ZIO_D50) | \ + PIN_MODE_INPUT(GPIOG_PIN4) | \ + PIN_MODE_INPUT(GPIOG_PIN5) | \ + PIN_MODE_OUTPUT(GPIOG_USB_GPIO_OUT) | \ + PIN_MODE_INPUT(GPIOG_USB_GPIO_IN) | \ + PIN_MODE_INPUT(GPIOG_PIN8) | \ + PIN_MODE_INPUT(GPIOG_ARD_D0) | \ + PIN_MODE_INPUT(GPIOG_PIN10) | \ + PIN_MODE_INPUT(GPIOG_PIN11) | \ + PIN_MODE_INPUT(GPIOG_PIN12) | \ + PIN_MODE_INPUT(GPIOG_PIN13) | \ + PIN_MODE_INPUT(GPIOG_ARD_D1) | \ + PIN_MODE_INPUT(GPIOG_PIN15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D65) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D64) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D49) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D50) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOG_USB_GPIO_OUT) |\ + PIN_OTYPE_PUSHPULL(GPIOG_USB_GPIO_IN) |\ + PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ARD_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ARD_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_ZIO_D65) | \ + PIN_OSPEED_VERYLOW(GPIOG_ZIO_D64) | \ + PIN_OSPEED_VERYLOW(GPIOG_ZIO_D49) | \ + PIN_OSPEED_VERYLOW(GPIOG_ZIO_D50) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN5) | \ + PIN_OSPEED_HIGH(GPIOG_USB_GPIO_OUT) | \ + PIN_OSPEED_HIGH(GPIOG_USB_GPIO_IN) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN8) | \ + PIN_OSPEED_HIGH(GPIOG_ARD_D0) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN13) | \ + PIN_OSPEED_HIGH(GPIOG_ARD_D1) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_ZIO_D65) | \ + PIN_PUPDR_PULLUP(GPIOG_ZIO_D64) | \ + PIN_PUPDR_PULLUP(GPIOG_ZIO_D49) | \ + PIN_PUPDR_PULLUP(GPIOG_ZIO_D50) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOG_USB_GPIO_OUT) | \ + PIN_PUPDR_PULLUP(GPIOG_USB_GPIO_IN) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOG_ARD_D0) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOG_ARD_D1) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_ZIO_D65) | \ + PIN_ODR_HIGH(GPIOG_ZIO_D64) | \ + PIN_ODR_HIGH(GPIOG_ZIO_D49) | \ + PIN_ODR_HIGH(GPIOG_ZIO_D50) | \ + PIN_ODR_HIGH(GPIOG_PIN4) | \ + PIN_ODR_HIGH(GPIOG_PIN5) | \ + PIN_ODR_HIGH(GPIOG_USB_GPIO_OUT) | \ + PIN_ODR_HIGH(GPIOG_USB_GPIO_IN) | \ + PIN_ODR_HIGH(GPIOG_PIN8) | \ + PIN_ODR_HIGH(GPIOG_ARD_D0) | \ + PIN_ODR_HIGH(GPIOG_PIN10) | \ + PIN_ODR_HIGH(GPIOG_PIN11) | \ + PIN_ODR_HIGH(GPIOG_PIN12) | \ + PIN_ODR_HIGH(GPIOG_PIN13) | \ + PIN_ODR_HIGH(GPIOG_ARD_D1) | \ + PIN_ODR_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_ZIO_D65, 0U) | \ + PIN_AFIO_AF(GPIOG_ZIO_D64, 0U) | \ + PIN_AFIO_AF(GPIOG_ZIO_D49, 0U) | \ + PIN_AFIO_AF(GPIOG_ZIO_D50, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOG_USB_GPIO_OUT, 0U) | \ + PIN_AFIO_AF(GPIOG_USB_GPIO_IN, 0U)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOG_ARD_D0, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOG_ARD_D1, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN15, 0U)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - PIN2 (input pullup). + * PH3 - PIN3 (input pullup). + * PH4 - PIN4 (input pullup). + * PH5 - PIN5 (input pullup). + * PH6 - PIN6 (input pullup). + * PH7 - PIN7 (input pullup). + * PH8 - PIN8 (input pullup). + * PH9 - PIN9 (input pullup). + * PH10 - PIN10 (input pullup). + * PH11 - PIN11 (input pullup). + * PH12 - PIN12 (input pullup). + * PH13 - PIN13 (input pullup). + * PH14 - PIN14 (input pullup). + * PH15 - PIN15 (input pullup). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOH_PIN2) | \ + PIN_MODE_INPUT(GPIOH_PIN3) | \ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_INPUT(GPIOH_PIN5) | \ + PIN_MODE_INPUT(GPIOH_PIN6) | \ + PIN_MODE_INPUT(GPIOH_PIN7) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ + PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0U)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0U)) + +/* + * GPIOI setup: + * + * PI0 - PIN0 (input pullup). + * PI1 - PIN1 (input pullup). + * PI2 - PIN2 (input pullup). + * PI3 - PIN3 (input pullup). + * PI4 - PIN4 (input pullup). + * PI5 - PIN5 (input pullup). + * PI6 - PIN6 (input pullup). + * PI7 - PIN7 (input pullup). + * PI8 - PIN8 (input pullup). + * PI9 - PIN9 (input pullup). + * PI10 - PIN10 (input pullup). + * PI11 - PIN11 (input pullup). + * PI12 - PIN12 (input pullup). + * PI13 - PIN13 (input pullup). + * PI14 - PIN14 (input pullup). + * PI15 - PIN15 (input pullup). + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ + PIN_MODE_INPUT(GPIOI_PIN1) | \ + PIN_MODE_INPUT(GPIOI_PIN2) | \ + PIN_MODE_INPUT(GPIOI_PIN3) | \ + PIN_MODE_INPUT(GPIOI_PIN4) | \ + PIN_MODE_INPUT(GPIOI_PIN5) | \ + PIN_MODE_INPUT(GPIOI_PIN6) | \ + PIN_MODE_INPUT(GPIOI_PIN7) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_INPUT(GPIOI_PIN9) | \ + PIN_MODE_INPUT(GPIOI_PIN10) | \ + PIN_MODE_INPUT(GPIOI_PIN11) | \ + PIN_MODE_INPUT(GPIOI_PIN12) | \ + PIN_MODE_INPUT(GPIOI_PIN13) | \ + PIN_MODE_INPUT(GPIOI_PIN14) | \ + PIN_MODE_INPUT(GPIOI_PIN15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOI_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ + PIN_ODR_HIGH(GPIOI_PIN1) | \ + PIN_ODR_HIGH(GPIOI_PIN2) | \ + PIN_ODR_HIGH(GPIOI_PIN3) | \ + PIN_ODR_HIGH(GPIOI_PIN4) | \ + PIN_ODR_HIGH(GPIOI_PIN5) | \ + PIN_ODR_HIGH(GPIOI_PIN6) | \ + PIN_ODR_HIGH(GPIOI_PIN7) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_PIN9) | \ + PIN_ODR_HIGH(GPIOI_PIN10) | \ + PIN_ODR_HIGH(GPIOI_PIN11) | \ + PIN_ODR_HIGH(GPIOI_PIN12) | \ + PIN_ODR_HIGH(GPIOI_PIN13) | \ + PIN_ODR_HIGH(GPIOI_PIN14) | \ + PIN_ODR_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN7, 0U)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN15, 0U)) + +/* + * GPIOJ setup: + * + * PJ0 - PIN0 (input pullup). + * PJ1 - PIN1 (input pullup). + * PJ2 - PIN2 (input pullup). + * PJ3 - PIN3 (input pullup). + * PJ4 - PIN4 (input pullup). + * PJ5 - PIN5 (input pullup). + * PJ6 - PIN6 (input pullup). + * PJ7 - PIN7 (input pullup). + * PJ8 - PIN8 (input pullup). + * PJ9 - PIN9 (input pullup). + * PJ10 - PIN10 (input pullup). + * PJ11 - PIN11 (input pullup). + * PJ12 - PIN12 (input pullup). + * PJ13 - PIN13 (input pullup). + * PJ14 - PIN14 (input pullup). + * PJ15 - PIN15 (input pullup). + */ +#define VAL_GPIOJ_MODER (PIN_MODE_INPUT(GPIOJ_PIN0) | \ + PIN_MODE_INPUT(GPIOJ_PIN1) | \ + PIN_MODE_INPUT(GPIOJ_PIN2) | \ + PIN_MODE_INPUT(GPIOJ_PIN3) | \ + PIN_MODE_INPUT(GPIOJ_PIN4) | \ + PIN_MODE_INPUT(GPIOJ_PIN5) | \ + PIN_MODE_INPUT(GPIOJ_PIN6) | \ + PIN_MODE_INPUT(GPIOJ_PIN7) | \ + PIN_MODE_INPUT(GPIOJ_PIN8) | \ + PIN_MODE_INPUT(GPIOJ_PIN9) | \ + PIN_MODE_INPUT(GPIOJ_PIN10) | \ + PIN_MODE_INPUT(GPIOJ_PIN11) | \ + PIN_MODE_INPUT(GPIOJ_PIN12) | \ + PIN_MODE_INPUT(GPIOJ_PIN13) | \ + PIN_MODE_INPUT(GPIOJ_PIN14) | \ + PIN_MODE_INPUT(GPIOJ_PIN15)) +#define VAL_GPIOJ_OTYPER (PIN_OTYPE_PUSHPULL(GPIOJ_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN15)) +#define VAL_GPIOJ_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOJ_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN15)) +#define VAL_GPIOJ_PUPDR (PIN_PUPDR_PULLUP(GPIOJ_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN15)) +#define VAL_GPIOJ_ODR (PIN_ODR_HIGH(GPIOJ_PIN0) | \ + PIN_ODR_HIGH(GPIOJ_PIN1) | \ + PIN_ODR_HIGH(GPIOJ_PIN2) | \ + PIN_ODR_HIGH(GPIOJ_PIN3) | \ + PIN_ODR_HIGH(GPIOJ_PIN4) | \ + PIN_ODR_HIGH(GPIOJ_PIN5) | \ + PIN_ODR_HIGH(GPIOJ_PIN6) | \ + PIN_ODR_HIGH(GPIOJ_PIN7) | \ + PIN_ODR_HIGH(GPIOJ_PIN8) | \ + PIN_ODR_HIGH(GPIOJ_PIN9) | \ + PIN_ODR_HIGH(GPIOJ_PIN10) | \ + PIN_ODR_HIGH(GPIOJ_PIN11) | \ + PIN_ODR_HIGH(GPIOJ_PIN12) | \ + PIN_ODR_HIGH(GPIOJ_PIN13) | \ + PIN_ODR_HIGH(GPIOJ_PIN14) | \ + PIN_ODR_HIGH(GPIOJ_PIN15)) +#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(GPIOJ_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN7, 0U)) +#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(GPIOJ_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN15, 0U)) + +/* + * GPIOK setup: + * + * PK0 - PIN0 (input pullup). + * PK1 - PIN1 (input pullup). + * PK2 - PIN2 (input pullup). + * PK3 - PIN3 (input pullup). + * PK4 - PIN4 (input pullup). + * PK5 - PIN5 (input pullup). + * PK6 - PIN6 (input pullup). + * PK7 - PIN7 (input pullup). + * PK8 - PIN8 (input pullup). + * PK9 - PIN9 (input pullup). + * PK10 - PIN10 (input pullup). + * PK11 - PIN11 (input pullup). + * PK12 - PIN12 (input pullup). + * PK13 - PIN13 (input pullup). + * PK14 - PIN14 (input pullup). + * PK15 - PIN15 (input pullup). + */ +#define VAL_GPIOK_MODER (PIN_MODE_INPUT(GPIOK_PIN0) | \ + PIN_MODE_INPUT(GPIOK_PIN1) | \ + PIN_MODE_INPUT(GPIOK_PIN2) | \ + PIN_MODE_INPUT(GPIOK_PIN3) | \ + PIN_MODE_INPUT(GPIOK_PIN4) | \ + PIN_MODE_INPUT(GPIOK_PIN5) | \ + PIN_MODE_INPUT(GPIOK_PIN6) | \ + PIN_MODE_INPUT(GPIOK_PIN7) | \ + PIN_MODE_INPUT(GPIOK_PIN8) | \ + PIN_MODE_INPUT(GPIOK_PIN9) | \ + PIN_MODE_INPUT(GPIOK_PIN10) | \ + PIN_MODE_INPUT(GPIOK_PIN11) | \ + PIN_MODE_INPUT(GPIOK_PIN12) | \ + PIN_MODE_INPUT(GPIOK_PIN13) | \ + PIN_MODE_INPUT(GPIOK_PIN14) | \ + PIN_MODE_INPUT(GPIOK_PIN15)) +#define VAL_GPIOK_OTYPER (PIN_OTYPE_PUSHPULL(GPIOK_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN15)) +#define VAL_GPIOK_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOK_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN15)) +#define VAL_GPIOK_PUPDR (PIN_PUPDR_PULLUP(GPIOK_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN15)) +#define VAL_GPIOK_ODR (PIN_ODR_HIGH(GPIOK_PIN0) | \ + PIN_ODR_HIGH(GPIOK_PIN1) | \ + PIN_ODR_HIGH(GPIOK_PIN2) | \ + PIN_ODR_HIGH(GPIOK_PIN3) | \ + PIN_ODR_HIGH(GPIOK_PIN4) | \ + PIN_ODR_HIGH(GPIOK_PIN5) | \ + PIN_ODR_HIGH(GPIOK_PIN6) | \ + PIN_ODR_HIGH(GPIOK_PIN7) | \ + PIN_ODR_HIGH(GPIOK_PIN8) | \ + PIN_ODR_HIGH(GPIOK_PIN9) | \ + PIN_ODR_HIGH(GPIOK_PIN10) | \ + PIN_ODR_HIGH(GPIOK_PIN11) | \ + PIN_ODR_HIGH(GPIOK_PIN12) | \ + PIN_ODR_HIGH(GPIOK_PIN13) | \ + PIN_ODR_HIGH(GPIOK_PIN14) | \ + PIN_ODR_HIGH(GPIOK_PIN15)) +#define VAL_GPIOK_AFRL (PIN_AFIO_AF(GPIOK_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN7, 0U)) +#define VAL_GPIOK_AFRH (PIN_AFIO_AF(GPIOK_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN15, 0U)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/common/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/common/CMakeLists.txt new file mode 100644 index 00000000..aa7f1d54 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/common/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/usbcfg.c") +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c") + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/common/Device_BlockStorage-DEBUG.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 00000000..f1b9ab35 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,96 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 32kB blocks +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 0 }, // 0x08000000 nanoBooter + { BlockRange_BLOCKTYPE_CODE , 1, 3 } // 0x08008000 nanoCLR +}; + +//128kB block +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 0x08020000 nanoCLR +}; + +// 256kB blocks +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 2 } // 0x08040000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x8000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 1, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08040000, // start address for block region + 3, // total number of blocks in this region + 0x40000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00100000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/common/Device_BlockStorage.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/common/Device_BlockStorage.c new file mode 100644 index 00000000..e8f18706 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/common/Device_BlockStorage.c @@ -0,0 +1,96 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 32kB blocks +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 0 }, // 0x08000000 nanoBooter + { BlockRange_BLOCKTYPE_CODE , 1, 3 } // 0x08008000 nanoCLR +}; + +//128kB block +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 0x08020000 nanoCLR +}; + +// 256kB blocks +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 2 } // 0x08040000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x8000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 1, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08040000, // start address for block region + 3, // total number of blocks in this region + 0x40000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00100000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/common/usbcfg.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/common/usbcfg.c new file mode 100644 index 00000000..11e6d6bd --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/common/usbcfg.c @@ -0,0 +1,454 @@ +// +// Copyright (c) 2017..2018 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "hal.h" + +/* Virtual serial port over USB.*/ +SerialUSBDriver SDU1; + +/* + * Endpoints to be used for USBD2. + */ +#define USBD2_DATA_REQUEST_EP 1 +#define USBD2_DATA_AVAILABLE_EP 1 +#define USBD2_INTERRUPT_REQUEST_EP 2 + +// address for device unique ID +// valid for STM32F4 series +#define DEVICE_ID1 (0x1FFF7A10) +#define DEVICE_ID2 (0x1FFF7A14) +#define DEVICE_ID3 (0x1FFF7A18) + +// // size of string serial is 36 = 2 + 5x2 + 26 from silicon unique ID precedeed of string "NANO_" and descriptor codes +// #define USB_SIZ_STRING_SERIAL 36 + +//////////////////////////////////////////////// +// vendor +#define USB_STRING_VENDOR L"STMicroelectronics" +//////////////////////////////////////////////// + +// structure for USB Vendor with Unicode string +typedef struct usb_string_vendor +{ + uint8_t bLength; + uint8_t bDescriptorType; + wchar_t bPropertyData[sizeof(USB_STRING_VENDOR)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec) + +}usb_string_vendor; + + +///////////////////////////////////////////////////////////////////////// +// device description +#define USB_STRING_DEVICE_DESCRIPTION L"nanoFramework Virtual COM Port" +///////////////////////////////////////////////////////////////////////// + +// structure for USB device descriptor with Unicode string +typedef struct usb_string_device_description +{ + uint8_t bLength; + uint8_t bDescriptorType; + wchar_t bPropertyData[sizeof(USB_STRING_DEVICE_DESCRIPTION)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec) + +}usb_string_device_description; + + +///////////////////////////////////////////////////////////////////////// +// device serial number +// this will produce a string with NANO_ prefix followed +// by the hexadecimal representation of the silicon unique ID of the CPU +#define USB_STRING_SERIAL_NUMBER L"NANO_xxxxxxxxxxx" +///////////////////////////////////////////////////////////////////////// +#define INDEX_OF_WCHAR_FOR_UNIQUE_ID 5 + +// structure for USB serial number descriptor with Unicode string +typedef struct usb_string_serial_number +{ + uint8_t bLength; + uint8_t bDescriptorType; + wchar_t bPropertyData[sizeof(USB_STRING_SERIAL_NUMBER)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec) + +}usb_string_serial_number; + + +/* + * USB Device Descriptor. + */ +static const uint8_t vcom_device_descriptor_data[] = { + USB_DESC_DEVICE (0x0200, /* bcdUSB (2.0). */ + 0x02, /* bDeviceClass (CDC). */ + 0x00, /* bDeviceSubClass. */ + 0x00, /* bDeviceProtocol. */ + 0x40, /* bMaxPacketSize. */ + 0x0483, /* idVendor (ST). */ + 0x5740, /* idProduct. */ + 0x0200, /* bcdDevice. */ + 1, /* iManufacturer. */ + 2, /* iProduct. */ + 3, /* iSerialNumber. */ + 1) /* bNumConfigurations. */ +}; + +/* + * Device Descriptor wrapper. + */ +static const USBDescriptor vcom_device_descriptor = { + sizeof vcom_device_descriptor_data, + vcom_device_descriptor_data +}; + +/* Configuration Descriptor tree for a CDC.*/ +static const uint8_t vcom_configuration_descriptor_data[] = { + /* Configuration Descriptor.*/ + USB_DESC_CONFIGURATION(0x0043, /* wTotalLength. */ + 0x02, /* bNumInterfaces. */ + 0x01, /* bConfigurationValue. */ + 0, /* iConfiguration. */ + 0xC0, /* bmAttributes (self powered). */ + 50), /* bMaxPower (100mA). */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x01, /* bNumEndpoints. */ + 0x02, /* bInterfaceClass (Communications + Interface Class, CDC section + 4.2). */ + 0x02, /* bInterfaceSubClass (Abstract + Control Model, CDC section 4.3). */ + 0x01, /* bInterfaceProtocol (AT commands, + CDC section 4.4). */ + 0), /* iInterface. */ + /* Header Functional Descriptor (CDC section 5.2.3).*/ + USB_DESC_BYTE (5), /* bLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header + Functional Descriptor. */ + USB_DESC_BCD (0x0110), /* bcdCDC. */ + /* Call Management Functional Descriptor. */ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */ + USB_DESC_BYTE (0x01), /* bDataInterface. */ + /* ACM Functional Descriptor.*/ + USB_DESC_BYTE (4), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract + Control Management Descriptor). */ + USB_DESC_BYTE (0x02), /* bmCapabilities. */ + /* Union Functional Descriptor.*/ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bMasterInterface (Communication + Class Interface). */ + USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class + Interface). */ + /* Endpoint 2 Descriptor.*/ + USB_DESC_ENDPOINT (USBD2_INTERRUPT_REQUEST_EP|0x80, + 0x03, /* bmAttributes (Interrupt). */ + 0x0008, /* wMaxPacketSize. */ + 0xFF), /* bInterval. */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x02, /* bNumEndpoints. */ + 0x0A, /* bInterfaceClass (Data Class + Interface, CDC section 4.5). */ + 0x00, /* bInterfaceSubClass (CDC section + 4.6). */ + 0x00, /* bInterfaceProtocol (CDC section + 4.7). */ + 0x00), /* iInterface. */ + /* Endpoint 3 Descriptor.*/ + USB_DESC_ENDPOINT (USBD2_DATA_AVAILABLE_EP, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00), /* bInterval. */ + /* Endpoint 1 Descriptor.*/ + USB_DESC_ENDPOINT (USBD2_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00) /* bInterval. */ +}; + +/* + * Configuration Descriptor wrapper. + */ +static const USBDescriptor vcom_configuration_descriptor = { + sizeof vcom_configuration_descriptor_data, + vcom_configuration_descriptor_data +}; + +/* + * U.S. English language identifier. + */ +static const uint8_t vcom_string0[] = { + USB_DESC_BYTE(4), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */ +}; + + +// Vendor string +static const usb_string_vendor usb_vendor = { + sizeof(usb_vendor), + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), + USB_STRING_VENDOR +}; + + +// Device Description string +static const usb_string_device_description usb_device_description = { + sizeof(usb_device_description), + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), + USB_STRING_DEVICE_DESCRIPTION +}; + + +// Serial Number string. +static usb_string_serial_number usb_serial_number = { + sizeof(usb_serial_number), + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), + USB_STRING_SERIAL_NUMBER +}; + + +/* + * Strings wrappers array. + */ +static const USBDescriptor vcom_strings[] = { + {sizeof vcom_string0, vcom_string0}, + {sizeof usb_vendor, (uint8_t*)(&usb_vendor)}, + {sizeof usb_device_description, (uint8_t*)(&usb_device_description)}, + {sizeof usb_serial_number, (uint8_t*)(&usb_serial_number)}, +}; + + +// Convert Hex 32Bits value into char +// value: value to convert +// pbuf: pointer to the buffer +// len: buffer length +void IntToUnicode(uint32_t value , uint8_t *pbuf, uint8_t len) +{ + uint8_t idx = 0; + + for( idx = 0; idx < len; idx ++) + { + if( ((value >> 28)) < 0xA ) + { + pbuf[ 2* idx] = (value >> 28) + '0'; + } + else + { + pbuf[2* idx] = (value >> 28) + 'A' - 10; + } + + value = value << 4; + + pbuf[ 2* idx + 1] = 0; + } +} + +// Create the serial number string descriptor +void Get_SerialNum(uint8_t* pbuf) +{ + uint32_t deviceserial0, deviceserial1, deviceserial2; + + deviceserial0 = *(uint32_t*)DEVICE_ID1; + deviceserial1 = *(uint32_t*)DEVICE_ID2; + deviceserial2 = *(uint32_t*)DEVICE_ID3; + + deviceserial0 += deviceserial2; + + if (deviceserial0 != 0) + { + IntToUnicode(deviceserial0, pbuf, 8); + pbuf += 16; + IntToUnicode(deviceserial1, pbuf, 4); + } +} + +/* + * Handles the GET_DESCRIPTOR callback. All required descriptors must be + * handled here. + */ +static const USBDescriptor *get_descriptor(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang) { + + (void)usbp; + (void)lang; + + switch (dtype) { + case USB_DESCRIPTOR_DEVICE: + return &vcom_device_descriptor; + case USB_DESCRIPTOR_CONFIGURATION: + return &vcom_configuration_descriptor; + case USB_DESCRIPTOR_STRING: + if (dindex < 4) + { + if(dindex == 3) + { + // request is for serial number + // get it from the silicon unique ID + Get_SerialNum((uint8_t*)&usb_serial_number.bPropertyData[INDEX_OF_WCHAR_FOR_UNIQUE_ID]); + } + + return &vcom_strings[dindex]; + } + } + return NULL; +} + +/** + * @brief IN EP1 state. + */ +static USBInEndpointState ep1instate; + +/** + * @brief OUT EP1 state. + */ +static USBOutEndpointState ep1outstate; + +/** + * @brief EP1 initialization structure (both IN and OUT). + */ +static const USBEndpointConfig ep1config = { + USB_EP_MODE_TYPE_BULK, + NULL, + sduDataTransmitted, + sduDataReceived, + 0x0040, + 0x0040, + &ep1instate, + &ep1outstate, + 2, + NULL +}; + +/** + * @brief IN EP2 state. + */ +static USBInEndpointState ep2instate; + +/** + * @brief EP2 initialization structure (IN only). + */ +static const USBEndpointConfig ep2config = { + USB_EP_MODE_TYPE_INTR, + NULL, + sduInterruptTransmitted, + NULL, + 0x0010, + 0x0000, + &ep2instate, + NULL, + 1, + NULL +}; + +/* + * Handles the USB driver global events. + */ +static void usb_event(USBDriver *usbp, usbevent_t event) { + extern SerialUSBDriver SDU1; + + switch (event) { + case USB_EVENT_ADDRESS: + return; + case USB_EVENT_CONFIGURED: + chSysLockFromISR(); + + if (usbp->state == USB_ACTIVE) { + /* Enables the endpoints specified into the configuration. + Note, this callback is invoked from an ISR so I-Class functions + must be used.*/ + usbInitEndpointI(usbp, USBD2_DATA_REQUEST_EP, &ep1config); + usbInitEndpointI(usbp, USBD2_INTERRUPT_REQUEST_EP, &ep2config); + + /* Resetting the state of the CDC subsystem.*/ + sduConfigureHookI(&SDU1); + } + else if (usbp->state == USB_SELECTED) { + usbDisableEndpointsI(usbp); + } + + chSysUnlockFromISR(); + return; + case USB_EVENT_RESET: + /* Falls into.*/ + case USB_EVENT_UNCONFIGURED: + /* Falls into.*/ + case USB_EVENT_SUSPEND: + chSysLockFromISR(); + + /* Disconnection event on suspend.*/ + sduSuspendHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_WAKEUP: + chSysLockFromISR(); + + /* Disconnection event on suspend.*/ + sduWakeupHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_STALLED: + return; + } + return; +} + +/* + * Handling messages not implemented in the default handler nor in the + * SerialUSB handler. + */ +static bool requests_hook(USBDriver *usbp) { + + if (((usbp->setup[0] & USB_RTYPE_RECIPIENT_MASK) == USB_RTYPE_RECIPIENT_INTERFACE) && + (usbp->setup[1] == USB_REQ_SET_INTERFACE)) { + usbSetupTransfer(usbp, NULL, 0, NULL); + return true; + } + return sduRequestsHook(usbp); +} + +/* + * Handles the USB driver global events. + */ +static void sof_handler(USBDriver *usbp) { + + (void)usbp; + + osalSysLockFromISR(); + sduSOFHookI(&SDU1); + osalSysUnlockFromISR(); +} + +/* + * USB driver configuration. + */ +const USBConfig usbcfg = { + usb_event, + get_descriptor, + requests_hook, + sof_handler +}; + +/* + * Serial over USB driver configuration. + */ +const SerialUSBConfig serusbcfg = { + &USBD1, + USBD2_DATA_REQUEST_EP, + USBD2_DATA_AVAILABLE_EP, + USBD2_INTERRUPT_REQUEST_EP +}; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/common/usbcfg.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/common/usbcfg.h new file mode 100644 index 00000000..72960028 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/common/usbcfg.h @@ -0,0 +1,16 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef USBCFG_H +#define USBCFG_H + +extern const USBConfig usbcfg; +extern SerialUSBConfig serusbcfg; +extern SerialUSBDriver SDU1; + +#endif /* USBCFG_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/managed_helpers/README.md b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/managed_helpers/README.md new file mode 100644 index 00000000..e0453b7b --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/managed_helpers/README.md @@ -0,0 +1,7 @@ +## Managed code helpers + +This folder contains helper classes to make developers life easier when coding for this target board. + +* [Adc](ST_NUCLEO144_F412ZG_NF.Adc.cs) +* [Gpio](ST_NUCLEO144_F412ZG_NF.Gpio.cs) +* [LEDs](ST_NUCLEO144_F412ZG_NF.LEDs.cs) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/managed_helpers/ST_NUCLEO144_F412ZG_NF.Adc.cs b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/managed_helpers/ST_NUCLEO144_F412ZG_NF.Adc.cs new file mode 100644 index 00000000..594d5203 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/managed_helpers/ST_NUCLEO144_F412ZG_NF.Adc.cs @@ -0,0 +1,58 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +namespace nanoFramework.Targets.ST_NUCLEO144_F412ZG_NF +{ + /// + /// Enumeration of ADC channels available on board ST_NUCLEO144_F412ZG_NF + /// + public static class AdcChannels + { + /// + /// Channel 0, exposed on CN9 Pin 1, connected to PA3 (ADC1 - IN3) + /// + public const int Channel_0 = 0; + + /// + /// Channel 1, exposed on CN9 Pin 3, connected to PC0 (ADC1 - IN10) + /// + public const int Channel_1 = 1; + + /// + /// Channel 2, exposed on CN9 Pin 5, connected to PC3 (ADC1 - IN13) + /// + public const int Channel_2 = 2; + + /// + /// Channel 3, exposed on CN9 Pin 7, connected to PC1 (ADC1 - IN11) + /// + public const int Channel_3 = 3; + + /// + /// Channel 4, exposed on CN9 Pin 9, connected to PC4 (ADC1 - IN14) + /// + public const int Channel_4 = 4; + + /// + /// Channel 5, exposed on CN9 Pin 11, connected to PC5 (ADC1 - IN15) + /// + public const int Channel_5 = 5; + + /// + /// Channel 6, internal temperature sensor, connected to ADC1 + /// + public const int Channel_TemperatureSensor = 6; + + /// + /// Channel 7, internal voltage reference, connected to ADC1 + /// + public const int Channel_VrefIn = 7; + + /// + /// Channel 8, connected to VBatt pin, ADC1 + /// + public const int Channel_Vbatt = 8; + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/managed_helpers/ST_NUCLEO144_F412ZG_NF.Gpio.cs b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/managed_helpers/ST_NUCLEO144_F412ZG_NF.Gpio.cs new file mode 100644 index 00000000..aa09ba34 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/managed_helpers/ST_NUCLEO144_F412ZG_NF.Gpio.cs @@ -0,0 +1,72 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +using System; + +namespace nanoFramework.Targets.Community.ST_NUCLEO144_F412ZG_NF +{ + public static class Gpio + { + /// + /// + /// + public const int PA0 = 0; + public const int PA1 = 1; + public const int PA2 = 2; + public const int PA3 = 3; + public const int PA4 = 4; + public const int PA5 = 5; + public const int PA6 = 6; + public const int PA7 = 7; + public const int PA8 = 8; + public const int PA9 = 9; + public const int PA10 = 10; + public const int PA11 = 11; + public const int PA12 = 12; + public const int PA13 = 13; + public const int PA14 = 14; + public const int PA15 = 15; + + /// + /// + /// + public const int PB0 = 16; + public const int PB1 = 17; + public const int PB2 = 18; + public const int PB3 = 19; + public const int PB4 = 20; + public const int PB5 = 21; + public const int PB6 = 22; + public const int PB7 = 23; + public const int PB8 = 24; + public const int PB9 = 25; + public const int PB10 = 26; + public const int PB11 = 27; + public const int PB12 = 28; + public const int PB13 = 29; + public const int PB14 = 30; + public const int PB15 = 31; + + /// + /// + /// + public const int PC0 = 32; + public const int PC1 = 33; + public const int PC2 = 34; + public const int PC3 = 35; + public const int PC4 = 36; + public const int PC5 = 37; + public const int PC6 = 38; + public const int PC7 = 39; + public const int PC8 = 40; + public const int PC9 = 41; + public const int PC10 = 42; + public const int PC11 = 43; + public const int PC12 = 44; + public const int PC13 = 45; + public const int PC14 = 46; + public const int PC15 = 47; + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/managed_helpers/ST_NUCLEO144_F412ZG_NF.LEDs.cs b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/managed_helpers/ST_NUCLEO144_F412ZG_NF.LEDs.cs new file mode 100644 index 00000000..ef9cb0dc --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/managed_helpers/ST_NUCLEO144_F412ZG_NF.LEDs.cs @@ -0,0 +1,25 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +namespace nanoFramework.Targets.Community.ST_NUCLEO144_F412ZG_NF +{ + public enum OnBoardLeds + { + /// + /// Output pin connected to the on-board green user LED + /// + GreenLed = Gpio.PB0, + + /// + /// Output pin connected to the on-board blue user LED + /// + BlueLed = Gpio.PB7, + + /// + /// Output pin connected to the on-board red user LED + /// + RedLed = Gpio.PB14 + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/CMakeLists.txt new file mode 100644 index 00000000..f0e921f7 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# # append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") + +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/STM32F412xG_booter-DEBUG.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/STM32F412xG_booter-DEBUG.ld new file mode 100644 index 00000000..f9ee71b8 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/STM32F412xG_booter-DEBUG.ld @@ -0,0 +1,80 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F412xG memory setup. + * + */ +MEMORY +{ + flash : org = 0x08000000, len = 32k /* space reserved for nanoBooter (1st two sectors 0x08000000 to 0x08007FFF)*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 256k /* SRAM1 */ + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Stacks rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/STM32F412xG_booter.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/STM32F412xG_booter.ld new file mode 100644 index 00000000..f71d39bd --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/STM32F412xG_booter.ld @@ -0,0 +1,80 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F412xG memory setup. + * + */ +MEMORY +{ + flash : org = 0x08000000, len = 32k /* space reserved for nanoBooter (1st sector 0x08000000 to 0x08007FFF)*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 256k /* SRAM1 */ + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Stacks rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/chconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/chconf.h new file mode 100644 index 00000000..90665754 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/chconf.h @@ -0,0 +1,618 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 2000 // this is 2 milliseconds + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#define CH_CFG_INTERVALS_SIZE 32 + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_TIME_TYPES_SIZE 32 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES FALSE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS FALSE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT FALSE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES FALSE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_OBJ_FIFOS TRUE + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#define CH_CFG_USE_FACTORY FALSE + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 + +/** + * @brief Enables the registry of generic objects. + */ +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE + +/** + * @brief Enables factory for generic buffers. + */ +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE + +/** + * @brief Enables factory for semaphores. + */ +#define CH_CFG_FACTORY_SEMAPHORES TRUE + +/** + * @brief Enables factory for mailboxes. + */ +#define CH_CFG_FACTORY_MAILBOXES TRUE + +/** + * @brief Enables factory for objects FIFOs. + */ +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#define CORTEX_VTOR_INIT 0x00200000U + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/halconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/halconf.h new file mode 100644 index 00000000..fee2feb7 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/halconf.h @@ -0,0 +1,513 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/halconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/halconf_nf.h new file mode 100644 index 00000000..809a6cfa --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/halconf_nf.h @@ -0,0 +1,15 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +#endif // _HALCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/main.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/main.c new file mode 100644 index 00000000..11c74236 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/main.c @@ -0,0 +1,87 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); + +// Application entry point. +int main(void) { + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init SWO as soon as possible to make it available to output ASAP + #if (SWO_OUTPUT == TRUE) + SwoInit(); + #endif + + // the following IF is not mandatory, it's just providing a way for a user to 'force' + // the board to remain in nanoBooter and not launching nanoCLR + + // if the USER button (blue one) is pressed, skip the check for a valid CLR image and remain in booter + // the user button in this board has a pull-up resistor so the check has to be inverted + if (!palReadPad(GPIOC, GPIOC_BUTTON)) + { + // check for valid CLR image + // we are checking for a valid image right after the configuration block + if(CheckValidCLRImage((uint32_t)&__nanoImage_end__)) + { + // there seems to be a valid CLR image + // launch nanoCLR + LaunchCLR((uint32_t)&__nanoImage_end__); + } + } + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // Initializes a serial-over-USB CDC driver. + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + // Activates the USB driver and then the USB bus pull-up on D+. + // Note, a delay is inserted in order to not have to disconnect the cable after a reset. + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1500); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // Normal main() thread + while (true) { + palSetPad(GPIOB, GPIOB_LED1); + palSetPad(GPIOB, GPIOB_LED2); + palSetPad(GPIOB, GPIOB_LED3); + osDelay(250); + palClearPad(GPIOB, GPIOB_LED1); + palClearPad(GPIOB, GPIOB_LED2); + palClearPad(GPIOB, GPIOB_LED3); + osDelay(250); + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/mcuconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/mcuconf.h new file mode 100644 index 00000000..bf26e0f7 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/mcuconf.h @@ -0,0 +1,343 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 4 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSE +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_PLLI2SSRC STM32_PLLI2SSRC_PLLSRC +#define STM32_I2SCKIN_VALUE 0 +#define STM32_PLLI2SM_VALUE 8 +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 4 +#define STM32_PLLI2SQ_VALUE 4 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_USE_I2C4 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C4_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C4_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 250 +#define STM32_SDC_READ_TIMEOUT_MS 25 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/mcuconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/mcuconf_nf.h new file mode 100644 index 00000000..5ff03534 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/mcuconf_nf.h @@ -0,0 +1,9 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/target_board.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/target_board.h.in new file mode 100644 index 00000000..19531d9c --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoBooter/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOBOOTER_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/CMakeLists.txt new file mode 100644 index 00000000..e5496b7e --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/STM32F412xG_CLR-DEBUG.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/STM32F412xG_CLR-DEBUG.ld new file mode 100644 index 00000000..36c75241 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/STM32F412xG_CLR-DEBUG.ld @@ -0,0 +1,76 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F412xG memory setup. + * Note: Only use of ram0. + */ +MEMORY +{ + flash : org = 0x08008000, len = 1M - 32k - 768k /* flash size less the space reserved for nanoBooter and application deployment*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x08040000, len = 768k /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 256k /* SRAM1 */ + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/STM32F412xG_CLR.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/STM32F412xG_CLR.ld new file mode 100644 index 00000000..265d2745 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/STM32F412xG_CLR.ld @@ -0,0 +1,76 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F411xE memory setup. + * Note: Only use of ram0. + */ +MEMORY +{ + flash : org = 0x08008000, len = 1M - 32k - 768k /* flash size less the space reserved for nanoBooter and application deployment*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x08040000, len = 768k /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 256k /* SRAM1 */ + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/chconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/chconf.h new file mode 100644 index 00000000..4e161afa --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/chconf.h @@ -0,0 +1,621 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 1000 // this is 1 millisecond + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#define CH_CFG_INTERVALS_SIZE 32 + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_TIME_TYPES_SIZE 32 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_OBJ_FIFOS TRUE + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#define CH_CFG_USE_FACTORY FALSE + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 + +/** + * @brief Enables the registry of generic objects. + */ +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE + +/** + * @brief Enables factory for generic buffers. + */ +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE + +/** + * @brief Enables factory for semaphores. + */ +#define CH_CFG_FACTORY_SEMAPHORES TRUE + +/** + * @brief Enables factory for mailboxes. + */ +#define CH_CFG_FACTORY_MAILBOXES TRUE + +/** + * @brief Enables factory for objects FIFOs. + */ +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +/////////////////////////////////////////////////////////////////////////////// +// address of vector table for nanoCLR +#define CORTEX_VTOR_INIT 0x08008000U +/////////////////////////////////////////////////////////////////////////////// + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/halconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/halconf.h new file mode 100644 index 00000000..ba392052 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/halconf.h @@ -0,0 +1,524 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +// #define HAL_USE_ADC FALSE +// #endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +// /** +// * @brief Enables the DAC subsystem. +// */ +// #if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +// #define HAL_USE_DAC FALSE +// #endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +// this option is set at target_platform.h (from config file) +//#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +//#define HAL_USE_I2C TRUE +//#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +// #define HAL_USE_MAC TRUE +// #endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +// #define HAL_USE_PWM FALSE +// #endif + +/** + * @brief Enables the RTC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +// #define HAL_USE_RTC TRUE +// #endif + +/** + * @brief Enables the SDC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +// #define HAL_USE_SDC FALSE +// #endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +// #define HAL_USE_SPI FALSE +// #endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +// #define HAL_USE_UART FALSE +// #endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ + +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +// #define HAL_USE_WDG FALSE +// #endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/halconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/halconf_nf.h new file mode 100644 index 00000000..5ac68c7c --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/halconf_nf.h @@ -0,0 +1,14 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +#endif // _HALCONF_NF_H_ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/main.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/main.c new file mode 100644 index 00000000..d1126c73 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/main.c @@ -0,0 +1,71 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include "usbcfg.h" +#include +#include +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); +// declare CLRStartup thread here +osThreadDef(CLRStartupThread, osPriorityNormal, 4096, "CLRStartupThread"); + +// Application entry point. +int main(void) { + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init SWO as soon as possible to make it available to output ASAP + #if (SWO_OUTPUT == TRUE) + SwoInit(); + #endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // Initializes a serial-over-USB CDC driver. + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + // Activates the USB driver and then the USB bus pull-up on D+. + // Note, a delay is inserted in order to not have to disconnect the cable after a reset + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1500); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // CLR settings to launch CLR thread + CLR_SETTINGS clrSettings; + (void)memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.EnterDebuggerLoopAfterExit = true; + + // create the CLR Startup thread + osThreadCreate(osThread(CLRStartupThread), &clrSettings); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + while (true) { + osDelay(100); + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/mcuconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/mcuconf.h new file mode 100644 index 00000000..b80b4e23 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/mcuconf.h @@ -0,0 +1,349 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ + + #define STM32_NO_INIT FALSE + #define STM32_HSI_ENABLED TRUE + #define STM32_LSI_ENABLED TRUE + #define STM32_HSE_ENABLED TRUE + #define STM32_LSE_ENABLED TRUE + #define STM32_CLOCK48_REQUIRED TRUE + #define STM32_SW STM32_SW_PLL + #define STM32_PLLSRC STM32_PLLSRC_HSE + #define STM32_PLLM_VALUE 8 + #define STM32_PLLN_VALUE 336 + #define STM32_PLLP_VALUE 4 + #define STM32_PLLQ_VALUE 7 + #define STM32_HPRE STM32_HPRE_DIV1 + #define STM32_PPRE1 STM32_PPRE1_DIV4 + #define STM32_PPRE2 STM32_PPRE2_DIV2 + #define STM32_RTCSEL STM32_RTCSEL_LSE + #define STM32_RTCPRE_VALUE 8 + #define STM32_MCO1SEL STM32_MCO1SEL_HSE + #define STM32_MCO1PRE STM32_MCO1PRE_DIV1 + #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK + #define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_PLLI2SSRC STM32_PLLI2SSRC_PLLSRC +#define STM32_I2SCKIN_VALUE 0 +#define STM32_PLLI2SM_VALUE 8 +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 4 +#define STM32_PLLI2SQ_VALUE 4 + #define STM32_PVD_ENABLE FALSE + #define STM32_PLS STM32_PLS_LEV0 + #define STM32_BKPRAM_ENABLE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 TRUE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 TRUE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 TRUE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 TRUE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 TRUE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 250 +#define STM32_SDC_READ_TIMEOUT_MS 25 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_USE_SPI4 TRUE +#define STM32_SPI_USE_SPI5 TRUE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI5_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG TRUE + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/mcuconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/mcuconf_nf.h new file mode 100644 index 00000000..5ff03534 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/mcuconf_nf.h @@ -0,0 +1,9 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/nanoHAL.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/nanoHAL.cpp new file mode 100644 index 00000000..076a50fc --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/nanoHAL.cpp @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +void HAL_EnterBooterMode() +{ +} + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/target_board.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/target_board.h.in new file mode 100644 index 00000000..b980bc05 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/nanoCLR/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOCLR_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_BlockStorage.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_BlockStorage.c new file mode 100644 index 00000000..9e7c7f55 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_BlockStorage.c @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice STM32Flash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &STM32Flash_BlockStorageInterface, &Device_BlockStorageConfig, false); +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_BlockStorage.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_BlockStorage.h new file mode 100644 index 00000000..aa50b1b7 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_common.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_common.c new file mode 100644 index 00000000..c633da5b --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_common.c @@ -0,0 +1,24 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include "target_common.h" + +HAL_SYSTEM_CONFIG HalSystemConfig = +{ + { true }, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, //ConvertCOM_DebugHandle(1), + 0, //ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + { RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size }, + { FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size } +}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_common.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_common.h.in new file mode 100644 index 00000000..a247c865 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_common.h.in @@ -0,0 +1,37 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x200000C0) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x00040000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x08000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00100000) + +///////////////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////// +#define TARGETNAMESTRING "@CHIBIOS_BOARD@" +#define PLATFORMNAMESTRING "STM32F4" +/////////////////////////////////////////////// + +#endif /* _TARGET_COMMON_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_system_devices_dac_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_system_devices_dac_config.cpp new file mode 100644 index 00000000..88a70347 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_system_devices_dac_config.cpp @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_DAC_PORT_PIN_CHANNEL DacPortPinConfig[] = { + + // DAC1, channel 1, GPIO port A, pin 4 + {1, 1, GPIOA, 4}, + +}; + +const int DacChannelCount = ARRAYSIZE(DacPortPinConfig); diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_windows_devices_adc_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_windows_devices_adc_config.cpp new file mode 100644 index 00000000..0a92a44a --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_windows_devices_adc_config.cpp @@ -0,0 +1,24 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_adc_native_target.h" + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // ADC1 + {1, GPIOA, 3, ADC_CHANNEL_IN3}, + {1, GPIOC, 0, ADC_CHANNEL_IN10}, + {1, GPIOC, 3, ADC_CHANNEL_IN13}, + {1, GPIOC, 1, ADC_CHANNEL_IN11}, + {1, GPIOC, 4, ADC_CHANNEL_IN14}, + {1, GPIOC, 5, ADC_CHANNEL_IN15}, + + // these are the internal sources, available only at ADC1 + {1, NULL, 0, ADC_CHANNEL_SENSOR}, + {1, NULL, 0, ADC_CHANNEL_VREFINT}, + {1, NULL, 0, ADC_CHANNEL_VBAT}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_windows_devices_i2c_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_windows_devices_i2c_config.cpp new file mode 100644 index 00000000..534f821a --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_windows_devices_i2c_config.cpp @@ -0,0 +1,30 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_i2c_native_target.h" + +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for SCL pin is: GPIOB +// port for SDA pin is: GPIOB +// SCL pin: is GPIOB_8 +// SDA pin: is GPIOB_9 +// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, GPIOB, GPIOB, 8, 9, 4) + +////////// +// I2C2 // +////////// + +// pin configuration for I2C2 +// port for SCL pin is: GPIOB +// port for SDA pin is: GPIOB +// SCL pin: is GPIOB_10 +// SDA pin: is GPIOB_11 +// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(2, GPIOB, GPIOB, 10, 11, 4) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_windows_devices_serialcommunication_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_windows_devices_serialcommunication_config.cpp new file mode 100644 index 00000000..945efe88 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_windows_devices_serialcommunication_config.cpp @@ -0,0 +1,37 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_windows_devices_serialcommunication_config.h" +#include "win_dev_serial_native_target.h" + +/////////// +// UART2 // +/////////// + +// pin configuration for UART2 +// port for TX pin is: GPIOD +// port for RX pin is: GPIOD +// TX pin: is GPIOD_5 +// RX pin: is GPIOD_6 +// GPIO alternate pin function is 7 (see "Table 10. STM32F412xE/G alternate function mapping" in datasheet) +UART_CONFIG_PINS(2, GPIOD, GPIOD, 5, 6, 7) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart2_TxBuffer[UART2_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart2_RxBuffer[UART2_RX_SIZE]; + +// initialization for UART2 +UART_INIT(2, UART2_TX_SIZE, UART2_RX_SIZE) + +// un-initialization for UART2 +UART_UNINIT(2) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_windows_devices_serialcommunication_config.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_windows_devices_serialcommunication_config.h new file mode 100644 index 00000000..8320132b --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_windows_devices_serialcommunication_config.h @@ -0,0 +1,18 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +/////////// +// UART2 // +/////////// + +// enable USART2 +#define NF_SERIAL_COMM_STM32_UART_USE_USART2 TRUE + +// buffers size +// tx buffer size: 256 bytes +#define UART2_TX_SIZE 256 +// rx buffer size: 256 bytes +#define UART2_RX_SIZE 256 diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_windows_devices_spi_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_windows_devices_spi_config.cpp new file mode 100644 index 00000000..ef2d3a10 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF/target_windows_devices_spi_config.cpp @@ -0,0 +1,10 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_spi_native.h" + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/CMakeLists.txt new file mode 100644 index 00000000..4d858847 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/CMakeLists.txt @@ -0,0 +1,245 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +cmake_minimum_required(VERSION 3.0) +ENABLE_LANGUAGE(ASM) + +# add header files with common OS definitions and board definitions specific for each image +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/target_common.h" @ONLY) + +set(NANOBOOTER_PROJECT_NAME "nanoBooter") +set(NANOCLR_PROJECT_NAME "nanoCLR") + +find_package(BuildUtils REQUIRED) +find_package(CHIBIOS REQUIRED) +find_package(ChibiOSnfOverlay REQUIRED) +find_package(WireProtocol REQUIRED) + +# packages for nanoFramework libraries +####################################### +# mandatory +find_package(NF_CoreCLR REQUIRED) + +####################################### +# optional + +# ChibiOS contrib repo +if(CHIBIOS_CONTRIB_REQUIRED) + find_package(ChibiOS-Contrib REQUIRED) +endif() + +# nF feature: debugger +if(NF_FEATURE_DEBUGGER) + find_package(NF_Debugger REQUIRED) + find_package(NF_Diagnostics REQUIRED) +endif() + +# nF feature: networking +if(USE_NETWORKING_OPTION) + find_package(CHIBIOS_LWIP REQUIRED) + find_package(NF_NETWORKING REQUIRED) +endif() + +# nF feature: filesystem +if(USE_FILESYSTEM_OPTION) + find_package(CHIBIOS_FATFS REQUIRED) +endif() + +# security provider is mbedTLS +if(USE_SECURITY_MBEDTLS_OPTION) + find_package(mbedTLS REQUIRED) +endif() + +####################################### + +add_subdirectory("common") +add_subdirectory("nanoBooter") +add_subdirectory("nanoCLR") + +####################### +# nanoBooter executable + +add_executable( + # executables for project, project sources + ${NANOBOOTER_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + "${CMAKE_CURRENT_SOURCE_DIR}/target_BlockStorage.c" + + # need to add configuration manager to allow get/store configuration blocks + "${PROJECT_SOURCE_DIR}/src/HAL/nanoHAL_ConfigurationManager.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOBOOTER_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOBOOTER_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOBOOTER_SOURCES} + + ${CHIBIOS_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} +) + +####################### +# nanoCLR executable + +add_executable( + # executables for project, project sources + ${NANOCLR_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOCLR_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOCLR_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOCLR_SOURCES} + + ${CHIBIOS_SOURCES} + ${CHIBIOS_CONTRIB_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} + + # sources for nanoFramework libraries + ${NF_CoreCLR_SOURCES} + ${NF_Debugger_SOURCES} + ${NF_Diagnostics_SOURCES} + + # sources for ChibiOS FatFS + ${CHIBIOS_FATFS_SOURCES} + + # sources for nanoFramework Network LWIP, Sockets and TLS + "${CHIBIOS_LWIP_SOURCES}" + ${NF_Networking_SOURCES} + "${mbedTLS_SOURCES}" + + # sources for nanoFramework APIs + ${TARGET_NANO_APIS_SOURCES} +) + +# add dependency from ChibiOS (this is required to make sure the ChibiOS repo is downloaded before the build starts) +add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf ChibiOS) +add_dependencies(${NANOCLR_PROJECT_NAME}.elf ChibiOS) + +# add dependencies from CHIBIOS_NETWORK_COMPONENTS (this is required to make sure that ChibiOS network components are unzip at the proper locations before the build starts) +# only required if networking in ON +if(USE_NETWORKING_OPTION) + add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf CHIBIOS_NETWORK_COMPONENTS) + add_dependencies(${NANOCLR_PROJECT_NAME}.elf CHIBIOS_NETWORK_COMPONENTS) + + # add dependency for security provider mbedTLS + if(USE_SECURITY_MBEDTLS_OPTION) + add_dependencies(${NANOCLR_PROJECT_NAME}.elf mbedTLS) + endif() +endif() + +# include common directories +include_directories( + ${CMAKE_CURRENT_BINARY_DIR} + ${CMAKE_CURRENT_SOURCE_DIR} + ${CMAKE_CURRENT_SOURCE_DIR}/common + ${PROJECT_SOURCE_DIR}/src/CLR/Core + ${PROJECT_SOURCE_DIR}/src/CLR/Include + ${PROJECT_SOURCE_DIR}/src/HAL/Include + ${PROJECT_SOURCE_DIR}/src/PAL/Include + + ${WireProtocol_INCLUDE_DIRS} + ${CHIBIOS_INCLUDE_DIRS} + ${ChibiOSnfOverlay_INCLUDE_DIRS} + ${CHIBIOS_CONTRIB_INCLUDE_DIRS} + + ${TARGET_CMSIS_COMMON_INCLUDE_DIRS} + ${TARGET_CHIBIOS_COMMON_INCLUDE_DIRS} +) + +# include directories for nanoBooter +target_include_directories(${NANOBOOTER_PROJECT_NAME}.elf PUBLIC + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter" + ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter + + ${TARGET_CMSIS_NANOBOOTER_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOBOOTER_INCLUDE_DIRS} + + # includes for ChibiOS LwIP + ${CHIBIOS_LWIP_INCLUDE_DIRS} +) + +# include directories for nanoCLR +target_include_directories(${NANOCLR_PROJECT_NAME}.elf PUBLIC + ${CMAKE_CURRENT_BINARY_DIR}/nanoCLR + ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR + + ${TARGET_CMSIS_NANOCLR_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOCLR_INCLUDE_DIRS} + + # directories for nanoFramework libraries + ${NF_CoreCLR_INCLUDE_DIRS} + ${NF_Debugger_INCLUDE_DIRS} + ${NF_Diagnostics_INCLUDE_DIRS} + + # includes for nanoFramework APIs + ${TARGET_NANO_APIS_INCLUDES} + + # includes for ChibiOS FatFS + ${CHIBIOS_FATFS_INCLUDE_DIRS} + + # includes for ChibiOS LwIP + ${CHIBIOS_LWIP_INCLUDE_DIRS} + + # incudes for Networking and TLS + ${NF_Networking_INCLUDE_DIRS} + ${mbedTLS_INCLUDE_DIRS} +) + +# set compiler options +nf_set_compiler_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_options(${NANOCLR_PROJECT_NAME}.elf) + +# mbed TLS requires a config file +if(USE_SECURITY_MBEDTLS_OPTION) + # this seems to be only option to properly set a compiler define through the command line that needs to be a string literal + SET(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -DMBEDTLS_CONFIG_FILE=\"<${PROJECT_SOURCE_DIR}/src/PAL/COM/sockets/ssl/mbedTLS/nf_mbedtls_config.h>\"") + SET(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -DMBEDTLS_CONFIG_FILE=\"<${PROJECT_SOURCE_DIR}/src/PAL/COM/sockets/ssl/mbedTLS/nf_mbedtls_config.h>\"") +endif() + +# set compiler definitions +nf_set_compiler_definitions(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_definitions(${NANOCLR_PROJECT_NAME}.elf) + +# set linker files +if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F439xI_booter-DEBUG.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/STM32F439xI_CLR-DEBUG.ld) +else() + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F439xI_booter.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/STM32F439xI_CLR.ld) +endif() + +# set linker options +nf_set_linker_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_linker_options(${NANOCLR_PROJECT_NAME}.elf) + +# add other linker flags +########################################################### +# the sizes of CRT heap and ChibiOS stacks are defined here +set_property(TARGET ${NANOBOOTER_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x400,--defsym=__crt_heap_size__=0x10000") +set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x10000") + +# generate output files +nf_generate_build_output_files(${NANOBOOTER_PROJECT_NAME}.elf) +nf_generate_build_output_files(${NANOCLR_PROJECT_NAME}.elf) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/README.md b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/README.md new file mode 100644 index 00000000..34a6b2ce --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/README.md @@ -0,0 +1,31 @@ +## STM NUCLEO144 F439ZI board + +![STM NUCLEO144 F439ZI board](nucleo144-f439zi.jpg) + +The board used in this community contribution is the NUCLEO144 F439ZI board from STM. The board can be purchased from various sources and should be about 23 euros. Further information on this board and links for the user and programming manuals can be found at the product page in ST [website](http://www.st.com/en/evaluation-tools/nucleo-f439zi.html). + +Some basic information abstracted from ST: +- STM32 microcontroller in LQFP144 package +- External SMPS to generate Vcore logic supply (only available on '-P' suffixed boards) +- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) +- USB OTG or full-speed device (depending on STM32 support) +- 3 user LEDs +- User and reset push-buttons +- 32.768 kHz crystal oscillator +- Board connectors: + - USB with Micro-AB + - SWD + - Ethernet RJ45 (depending on STM32 support) + - ST Zio connector including Arduino™ Uno V3 + - ST morpho +- Flexible power-supply options: ST-LINK USB VBUS or external sources +- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration capability: mass storage, virtual COM port and debug port + +### Flashing and debugging + +This board has two micro USB connectors. One is exposing the embedded ST-Link interface that is used for flashing the nanoFramework firmware and for performing debugging on the nanoCLR code. The second is used to connect the device with Visual Studio allowing to deploy and debug your C# managed applications. + +## Floating point + +The current build is set to add support for single-precision floating point. +Meaning that `System.Math` API supports only the `float` overloads. The `double` ones will throw a `NotImplementedException`. diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/board.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/board.c new file mode 100644 index 00000000..90f2ece9 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/board.c @@ -0,0 +1,266 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) + gpio_setup_t PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_setup_t PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) + gpio_setup_t PKData; +#endif +} gpio_config_t; + +/** + * @brief STM32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +#endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB1(STM32_GPIO_EN_MASK); + rccEnableAHB1(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG + gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI + gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ + gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK + gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + * else. + */ +void __early_init(void) { + + stm32_gpio_init(); + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + + return !palReadLine(LINE_SD_DETECT); +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { + +} \ No newline at end of file diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/board.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/board.h new file mode 100644 index 00000000..1b558faf --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/board.h @@ -0,0 +1,1837 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef BOARD_H +#define BOARD_H + +/* + * Setup for STMicroelectronics STM32 Nucleo144-F439ZI board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_NUCLEO144_F439ZI +#define BOARD_NAME "STMicroelectronics STM32 Nucleo144-F439ZI" + +/* + * Ethernet PHY type. + */ +#define BOARD_PHY_ID MII_LAN8742A_ID +#define BOARD_PHY_RMII + +/* + * Board oscillators-related settings. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768U +#endif + +#define STM32_LSEDRV (3U << 3U) + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 8000000U +#endif + +#define STM32_HSE_BYPASS + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U + +/* + * MCU type as defined in the ST header. + */ +#define STM32F439xx + +/* + * IO pins assignments. + */ +#define GPIOA_ZIO_D32 0U +#define GPIOA_TIM2_CH1 0U +#define GPIOA_RMII_REF_CLK 1U +#define GPIOA_RMII_MDIO 2U +#define GPIOA_ARD_A0 3U +#define GPIOA_ADC123_IN3 3U +#define GPIOA_ZIO_D24 4U +#define GPIOA_SPI3_NSS 4U +#define GPIOA_ARD_D13 5U +#define GPIOA_SPI1_SCK 5U +#define GPIOA_ARD_D12 6U +#define GPIOA_SPI1_MISO 6U +#define GPIOA_ARD_D11 7U +#define GPIOA_SPI1_MOSI 7U +#define GPIOA_ZIO_D71 7U +#define GPIOA_RMII_RX_DV 7U +#define GPIOA_USB_SOF 8U +#define GPIOA_USB_VBUS 9U +#define GPIOA_USB_ID 10U +#define GPIOA_USB_DM 11U +#define GPIOA_USB_DP 12U +#define GPIOA_SWDIO 13U +#define GPIOA_SWCLK 14U +#define GPIOA_ZIO_D20 15U +#define GPIOA_I2S3_WS 15U + +#define GPIOB_ZIO_D33 0U +#define GPIOB_TIM3_CH3 0U +#define GPIOB_LED1 0U +#define GPIOB_ZIO_A6 1U +#define GPIOB_ADC12_IN9 1U +#define GPIOB_ZIO_D27 2U +#define GPIOB_ZIO_D23 3U +#define GPIOB_I2S3_CK 3U +#define GPIOB_SWO 3U +#define GPIOB_ZIO_D25 4U +#define GPIOB_SPI3_MISO 4U +#define GPIOB_ZIO_D22 5U +#define GPIOB_I2S3_SD 5U +#define GPIOB_ZIO_D26 6U +#define GPIOB_LED2 7U +#define GPIOB_ARD_D15 8U +#define GPIOB_I2C1_SCL 8U +#define GPIOB_ARD_D14 9U +#define GPIOB_I2C1_SDA 9U +#define GPIOB_ZIO_D36 10U +#define GPIOB_TIM2_CH3 10U +#define GPIOB_ZIO_D35 11U +#define GPIOB_TIM2_CH4 11U +#define GPIOB_ZIO_D19 12U +#define GPIOB_I2S2_WS 12U +#define GPIOB_ZIO_D18 13U +#define GPIOB_I2S2_CK 13U +#define GPIOB_RMII_TXD1 13U +#define GPIOB_LED3 14U +#define GPIOB_ZIO_D17 15U +#define GPIOB_I2S2_SD 15U + +#define GPIOC_ARD_A1 0U +#define GPIOC_ADC123_IN10 0U +#define GPIOC_RMII_MDC 1U +#define GPIOC_ZIO_A7 2U +#define GPIOC_ADC123_IN12 2U +#define GPIOC_ARD_A2 3U +#define GPIOC_ADC123_IN13 3U +#define GPIOC_RMII_RXD0 4U +#define GPIOC_RMII_RXD1 5U +#define GPIOC_ZIO_D16 6U +#define GPIOC_I2S2_MCK 6U +#define GPIOC_ZIO_D21 7U +#define GPIOC_I2S3_MCK 7U +#define GPIOC_ZIO_D43 8U +#define GPIOC_SDMMC_D0 8U +#define GPIOC_ZIO_D44 9U +#define GPIOC_SDMMC_D1 9U +#define GPIOC_ZIO_D45 10U +#define GPIOC_SDMMC_D2 10U +#define GPIOC_ZIO_D46 11U +#define GPIOC_SDMMC_D3 11U +#define GPIOC_ZIO_D47 12U +#define GPIOC_SDMMC_CK 12U +#define GPIOC_BUTTON 13U +#define GPIOC_OSC32_IN 14U +#define GPIOC_OSC32_OUT 15U + +#define GPIOD_ZIO_D67 0U +#define GPIOD_CAN1_RX 0U +#define GPIOD_ZIO_D66 1U +#define GPIOD_CAN1_TX 1U +#define GPIOD_ZIO_D48 2U +#define GPIOD_SDMMC_CMD 2U +#define GPIOD_ZIO_D55 3U +#define GPIOD_USART2_CTS 3U +#define GPIOD_ZIO_D54 4U +#define GPIOD_USART2_RTS 4U +#define GPIOD_ZIO_D53 5U +#define GPIOD_USART2_TX 5U +#define GPIOD_ZIO_D52 6U +#define GPIOD_USART2_RX 6U +#define GPIOD_ZIO_D51 7U +#define GPIOD_USART2_SCLK 7U +#define GPIOD_USART3_TX 8U +#define GPIOD_STLK_TX 8U +#define GPIOD_USART3_RX 9U +#define GPIOD_STLK_RX 9U +#define GPIOD_PIN10 10U +#define GPIOD_ZIO_D30 11U +#define GPIOD_ZIO_D29 12U +#define GPIOD_ZIO_D28 13U +#define GPIOD_ARD_D10 14U +#define GPIOD_SPI1_NSS 14U +#define GPIOD_ARD_D9 15U +#define GPIOD_TIM4_CH4 15U + +#define GPIOE_ZIO_D34 0U +#define GPIOE_TIM4_ETR 0U +#define GPIOE_PIN1 1U +#define GPIOE_ZIO_D31 2U +#define GPIOE_ZIO_D56 2U +#define GPIOE_SAI1_MCLK_A 2U +#define GPIOE_ZIO_D60 3U +#define GPIOE_SAI1_SD_B 3U +#define GPIOE_ZIO_D57 4U +#define GPIOE_SAI1_FS_A 4U +#define GPIOE_ZIO_D58 5U +#define GPIOE_SAI1_SCK_A 5U +#define GPIOE_ZIO_D59 6U +#define GPIOE_SAI1_SD_A 6U +#define GPIOE_ZIO_D41 7U +#define GPIOE_TIM1_ETR 7U +#define GPIOE_ZIO_D42 8U +#define GPIOE_TIM1_CH1N 8U +#define GPIOE_ARD_D6 9U +#define GPIOE_TIM1_CH1 9U +#define GPIOE_ZIO_D40 10U +#define GPIOE_TIM1_CH2N 10U +#define GPIOE_ARD_D5 11U +#define GPIOE_TIM1_CH2 11U +#define GPIOE_ZIO_D39 12U +#define GPIOE_TIM1_CH3N 12U +#define GPIOE_ARD_D3 13U +#define GPIOE_TIM1_CH3 13U +#define GPIOE_ZIO_D38 14U +#define GPIOE_ZIO_D37 15U +#define GPIOE_TIM1_BKIN1 15U + +#define GPIOF_ZIO_D68 0U +#define GPIOF_I2C2_SDA 0U +#define GPIOF_ZIO_D69 1U +#define GPIOF_I2C2_SCL 1U +#define GPIOF_ZIO_D70 2U +#define GPIOF_I2C2_SMBA 2U +#define GPIOF_ARD_A3 3U +#define GPIOF_ADC3_IN9 3U +#define GPIOF_ZIO_A8 4U +#define GPIOF_ADC3_IN14 4U +#define GPIOF_ARD_A4 5U +#define GPIOF_ADC3_IN15 5U +#define GPIOF_PIN6 6U +#define GPIOF_ZIO_D62 7U +#define GPIOF_SAI1_MCLK_B 7U +#define GPIOF_SPI5_SCK 7U +#define GPIOF_ZIO_D61 8U +#define GPIOF_SAI1_SCK_B 8U +#define GPIOF_SPI5_MISO 8U +#define GPIOF_ZIO_D63 9U +#define GPIOF_SAI1_FS_B 9U +#define GPIOF_SPI5_MOSI 9U +#define GPIOF_ARD_A5 10U +#define GPIOF_ADC3_IN8 10U +#define GPIOF_PIN11 11U +#define GPIOF_ARD_D8 12U +#define GPIOF_ARD_D7 13U +#define GPIOF_ARD_D4 14U +#define GPIOF_ARD_D2 15U + +#define GPIOG_ZIO_D65 0U +#define GPIOG_ZIO_D64 1U +#define GPIOG_ZIO_D49 2U +#define GPIOG_ZIO_D50 3U +#define GPIOG_PIN4 4U +#define GPIOG_PIN5 5U +#define GPIOG_USB_GPIO_OUT 6U +#define GPIOG_USB_GPIO_IN 7U +#define GPIOG_PIN8 8U +#define GPIOG_ARD_D0 9U +#define GPIOG_USART6_RX 9U +#define GPIOG_PIN10 10U +#define GPIOG_RMII_TX_EN 11U +#define GPIOG_PIN12 12U +#define GPIOG_RMII_TXD0 13U +#define GPIOG_ARD_D1 14U +#define GPIOG_USART6_TX 14U +#define GPIOG_PIN15 15U + +#define GPIOH_OSC_IN 0U +#define GPIOH_OSC_OUT 1U +#define GPIOH_PIN2 2U +#define GPIOH_PIN3 3U +#define GPIOH_PIN4 4U +#define GPIOH_PIN5 5U +#define GPIOH_PIN6 6U +#define GPIOH_PIN7 7U +#define GPIOH_PIN8 8U +#define GPIOH_PIN9 9U +#define GPIOH_PIN10 10U +#define GPIOH_PIN11 11U +#define GPIOH_PIN12 12U +#define GPIOH_PIN13 13U +#define GPIOH_PIN14 14U +#define GPIOH_PIN15 15U + +#define GPIOI_PIN0 0U +#define GPIOI_PIN1 1U +#define GPIOI_PIN2 2U +#define GPIOI_PIN3 3U +#define GPIOI_PIN4 4U +#define GPIOI_PIN5 5U +#define GPIOI_PIN6 6U +#define GPIOI_PIN7 7U +#define GPIOI_PIN8 8U +#define GPIOI_PIN9 9U +#define GPIOI_PIN10 10U +#define GPIOI_PIN11 11U +#define GPIOI_PIN12 12U +#define GPIOI_PIN13 13U +#define GPIOI_PIN14 14U +#define GPIOI_PIN15 15U + +#define GPIOJ_PIN0 0U +#define GPIOJ_PIN1 1U +#define GPIOJ_PIN2 2U +#define GPIOJ_PIN3 3U +#define GPIOJ_PIN4 4U +#define GPIOJ_PIN5 5U +#define GPIOJ_PIN6 6U +#define GPIOJ_PIN7 7U +#define GPIOJ_PIN8 8U +#define GPIOJ_PIN9 9U +#define GPIOJ_PIN10 10U +#define GPIOJ_PIN11 11U +#define GPIOJ_PIN12 12U +#define GPIOJ_PIN13 13U +#define GPIOJ_PIN14 14U +#define GPIOJ_PIN15 15U + +#define GPIOK_PIN0 0U +#define GPIOK_PIN1 1U +#define GPIOK_PIN2 2U +#define GPIOK_PIN3 3U +#define GPIOK_PIN4 4U +#define GPIOK_PIN5 5U +#define GPIOK_PIN6 6U +#define GPIOK_PIN7 7U +#define GPIOK_PIN8 8U +#define GPIOK_PIN9 9U +#define GPIOK_PIN10 10U +#define GPIOK_PIN11 11U +#define GPIOK_PIN12 12U +#define GPIOK_PIN13 13U +#define GPIOK_PIN14 14U +#define GPIOK_PIN15 15U + +/* + * IO lines assignments. + */ +#define LINE_ZIO_D32 PAL_LINE(GPIOA, 0U) +#define LINE_TIM2_CH1 PAL_LINE(GPIOA, 0U) +#define LINE_RMII_REF_CLK PAL_LINE(GPIOA, 1U) +#define LINE_RMII_MDIO PAL_LINE(GPIOA, 2U) +#define LINE_ARD_A0 PAL_LINE(GPIOA, 3U) +#define LINE_ADC123_IN3 PAL_LINE(GPIOA, 3U) +#define LINE_ZIO_D24 PAL_LINE(GPIOA, 4U) +#define LINE_SPI3_NSS PAL_LINE(GPIOA, 4U) +#define LINE_ARD_D13 PAL_LINE(GPIOA, 5U) +#define LINE_SPI1_SCK PAL_LINE(GPIOA, 5U) +#define LINE_ARD_D12 PAL_LINE(GPIOA, 6U) +#define LINE_SPI1_MISO PAL_LINE(GPIOA, 6U) +#define LINE_ARD_D11 PAL_LINE(GPIOA, 7U) +#define LINE_SPI1_MOSI PAL_LINE(GPIOA, 7U) +#define LINE_ZIO_D71 PAL_LINE(GPIOA, 7U) +#define LINE_RMII_RX_DV PAL_LINE(GPIOA, 7U) +#define LINE_USB_SOF PAL_LINE(GPIOA, 8U) +#define LINE_USB_VBUS PAL_LINE(GPIOA, 9U) +#define LINE_USB_ID PAL_LINE(GPIOA, 10U) +#define LINE_USB_DM PAL_LINE(GPIOA, 11U) +#define LINE_USB_DP PAL_LINE(GPIOA, 12U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) +#define LINE_ZIO_D20 PAL_LINE(GPIOA, 15U) +#define LINE_I2S3_WS PAL_LINE(GPIOA, 15U) +#define LINE_ZIO_D33 PAL_LINE(GPIOB, 0U) +#define LINE_TIM3_CH3 PAL_LINE(GPIOB, 0U) +#define LINE_LED1 PAL_LINE(GPIOB, 0U) +#define LINE_ZIO_A6 PAL_LINE(GPIOB, 1U) +#define LINE_ADC12_IN9 PAL_LINE(GPIOB, 1U) +#define LINE_ZIO_D27 PAL_LINE(GPIOB, 2U) +#define LINE_ZIO_D23 PAL_LINE(GPIOB, 3U) +#define LINE_I2S3_CK PAL_LINE(GPIOB, 3U) +#define LINE_ZIO_D25 PAL_LINE(GPIOB, 4U) +#define LINE_SPI3_MISO PAL_LINE(GPIOB, 4U) +#define LINE_ZIO_D22 PAL_LINE(GPIOB, 5U) +#define LINE_I2S3_SD PAL_LINE(GPIOB, 5U) +#define LINE_ZIO_D26 PAL_LINE(GPIOB, 6U) +#define LINE_LED2 PAL_LINE(GPIOB, 7U) +#define LINE_ARD_D15 PAL_LINE(GPIOB, 8U) +#define LINE_I2C1_SCL PAL_LINE(GPIOB, 8U) +#define LINE_ARD_D14 PAL_LINE(GPIOB, 9U) +#define LINE_I2C1_SDA PAL_LINE(GPIOB, 9U) +#define LINE_ZIO_D36 PAL_LINE(GPIOB, 10U) +#define LINE_TIM2_CH3 PAL_LINE(GPIOB, 10U) +#define LINE_ZIO_D35 PAL_LINE(GPIOB, 11U) +#define LINE_TIM2_CH4 PAL_LINE(GPIOB, 11U) +#define LINE_ZIO_D19 PAL_LINE(GPIOB, 12U) +#define LINE_I2S2_WS PAL_LINE(GPIOB, 12U) +#define LINE_ZIO_D18 PAL_LINE(GPIOB, 13U) +#define LINE_I2S2_CK PAL_LINE(GPIOB, 13U) +#define LINE_RMII_TXD1 PAL_LINE(GPIOB, 13U) +#define LINE_LED3 PAL_LINE(GPIOB, 14U) +#define LINE_ZIO_D17 PAL_LINE(GPIOB, 15U) +#define LINE_I2S2_SD PAL_LINE(GPIOB, 15U) +#define LINE_ARD_A1 PAL_LINE(GPIOC, 0U) +#define LINE_ADC123_IN10 PAL_LINE(GPIOC, 0U) +#define LINE_RMII_MDC PAL_LINE(GPIOC, 1U) +#define LINE_ZIO_A7 PAL_LINE(GPIOC, 2U) +#define LINE_ADC123_IN12 PAL_LINE(GPIOC, 2U) +#define LINE_ARD_A2 PAL_LINE(GPIOC, 3U) +#define LINE_ADC123_IN13 PAL_LINE(GPIOC, 3U) +#define LINE_RMII_RXD0 PAL_LINE(GPIOC, 4U) +#define LINE_RMII_RXD1 PAL_LINE(GPIOC, 5U) +#define LINE_ZIO_D16 PAL_LINE(GPIOC, 6U) +#define LINE_I2S2_MCK PAL_LINE(GPIOC, 6U) +#define LINE_ZIO_D21 PAL_LINE(GPIOC, 7U) +#define LINE_I2S3_MCK PAL_LINE(GPIOC, 7U) +#define LINE_ZIO_D43 PAL_LINE(GPIOC, 8U) +#define LINE_SDMMC_D0 PAL_LINE(GPIOC, 8U) +#define LINE_ZIO_D44 PAL_LINE(GPIOC, 9U) +#define LINE_SDMMC_D1 PAL_LINE(GPIOC, 9U) +#define LINE_ZIO_D45 PAL_LINE(GPIOC, 10U) +#define LINE_SDMMC_D2 PAL_LINE(GPIOC, 10U) +#define LINE_ZIO_D46 PAL_LINE(GPIOC, 11U) +#define LINE_SDMMC_D3 PAL_LINE(GPIOC, 11U) +#define LINE_ZIO_D47 PAL_LINE(GPIOC, 12U) +#define LINE_SDMMC_CK PAL_LINE(GPIOC, 12U) +#define LINE_BUTTON PAL_LINE(GPIOC, 13U) +#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) +#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) +#define LINE_ZIO_D67 PAL_LINE(GPIOD, 0U) +#define LINE_CAN1_RX PAL_LINE(GPIOD, 0U) +#define LINE_ZIO_D66 PAL_LINE(GPIOD, 1U) +#define LINE_CAN1_TX PAL_LINE(GPIOD, 1U) +#define LINE_ZIO_D48 PAL_LINE(GPIOD, 2U) +#define LINE_SDMMC_CMD PAL_LINE(GPIOD, 2U) +#define LINE_ZIO_D55 PAL_LINE(GPIOD, 3U) +#define LINE_USART2_CTS PAL_LINE(GPIOD, 3U) +#define LINE_ZIO_D54 PAL_LINE(GPIOD, 4U) +#define LINE_USART2_RTS PAL_LINE(GPIOD, 4U) +#define LINE_ZIO_D53 PAL_LINE(GPIOD, 5U) +#define LINE_USART2_TX PAL_LINE(GPIOD, 5U) +#define LINE_ZIO_D52 PAL_LINE(GPIOD, 6U) +#define LINE_USART2_RX PAL_LINE(GPIOD, 6U) +#define LINE_ZIO_D51 PAL_LINE(GPIOD, 7U) +#define LINE_USART2_SCLK PAL_LINE(GPIOD, 7U) +#define LINE_USART3_TX PAL_LINE(GPIOD, 8U) +#define LINE_STLK_TX PAL_LINE(GPIOD, 8U) +#define LINE_USART3_RX PAL_LINE(GPIOD, 9U) +#define LINE_STLK_RX PAL_LINE(GPIOD, 9U) +#define LINE_ZIO_D30 PAL_LINE(GPIOD, 11U) +#define LINE_ZIO_D29 PAL_LINE(GPIOD, 12U) +#define LINE_ZIO_D28 PAL_LINE(GPIOD, 13U) +#define LINE_ARD_D10 PAL_LINE(GPIOD, 14U) +#define LINE_SPI1_NSS PAL_LINE(GPIOD, 14U) +#define LINE_ARD_D9 PAL_LINE(GPIOD, 15U) +#define LINE_TIM4_CH4 PAL_LINE(GPIOD, 15U) +#define LINE_ZIO_D34 PAL_LINE(GPIOE, 0U) +#define LINE_TIM4_ETR PAL_LINE(GPIOE, 0U) +#define LINE_ZIO_D31 PAL_LINE(GPIOE, 2U) +#define LINE_ZIO_D56 PAL_LINE(GPIOE, 2U) +#define LINE_SAI1_MCLK_A PAL_LINE(GPIOE, 2U) +#define LINE_ZIO_D60 PAL_LINE(GPIOE, 3U) +#define LINE_SAI1_SD_B PAL_LINE(GPIOE, 3U) +#define LINE_ZIO_D57 PAL_LINE(GPIOE, 4U) +#define LINE_SAI1_FS_A PAL_LINE(GPIOE, 4U) +#define LINE_ZIO_D58 PAL_LINE(GPIOE, 5U) +#define LINE_SAI1_SCK_A PAL_LINE(GPIOE, 5U) +#define LINE_ZIO_D59 PAL_LINE(GPIOE, 6U) +#define LINE_SAI1_SD_A PAL_LINE(GPIOE, 6U) +#define LINE_ZIO_D41 PAL_LINE(GPIOE, 7U) +#define LINE_TIM1_ETR PAL_LINE(GPIOE, 7U) +#define LINE_ZIO_D42 PAL_LINE(GPIOE, 8U) +#define LINE_TIM1_CH1N PAL_LINE(GPIOE, 8U) +#define LINE_ARD_D6 PAL_LINE(GPIOE, 9U) +#define LINE_TIM1_CH1 PAL_LINE(GPIOE, 9U) +#define LINE_ZIO_D40 PAL_LINE(GPIOE, 10U) +#define LINE_TIM1_CH2N PAL_LINE(GPIOE, 10U) +#define LINE_ARD_D5 PAL_LINE(GPIOE, 11U) +#define LINE_TIM1_CH2 PAL_LINE(GPIOE, 11U) +#define LINE_ZIO_D39 PAL_LINE(GPIOE, 12U) +#define LINE_TIM1_CH3N PAL_LINE(GPIOE, 12U) +#define LINE_ARD_D3 PAL_LINE(GPIOE, 13U) +#define LINE_TIM1_CH3 PAL_LINE(GPIOE, 13U) +#define LINE_ZIO_D38 PAL_LINE(GPIOE, 14U) +#define LINE_ZIO_D37 PAL_LINE(GPIOE, 15U) +#define LINE_TIM1_BKIN1 PAL_LINE(GPIOE, 15U) +#define LINE_ZIO_D68 PAL_LINE(GPIOF, 0U) +#define LINE_I2C2_SDA PAL_LINE(GPIOF, 0U) +#define LINE_ZIO_D69 PAL_LINE(GPIOF, 1U) +#define LINE_I2C2_SCL PAL_LINE(GPIOF, 1U) +#define LINE_ZIO_D70 PAL_LINE(GPIOF, 2U) +#define LINE_I2C2_SMBA PAL_LINE(GPIOF, 2U) +#define LINE_ARD_A3 PAL_LINE(GPIOF, 3U) +#define LINE_ADC3_IN9 PAL_LINE(GPIOF, 3U) +#define LINE_ZIO_A8 PAL_LINE(GPIOF, 4U) +#define LINE_ADC3_IN14 PAL_LINE(GPIOF, 4U) +#define LINE_ARD_A4 PAL_LINE(GPIOF, 5U) +#define LINE_ADC3_IN15 PAL_LINE(GPIOF, 5U) +#define LINE_ZIO_D62 PAL_LINE(GPIOF, 7U) +#define LINE_SAI1_MCLK_B PAL_LINE(GPIOF, 7U) +#define LINE_ZIO_D61 PAL_LINE(GPIOF, 8U) +#define LINE_SAI1_SCK_B PAL_LINE(GPIOF, 8U) +#define LINE_ZIO_D63 PAL_LINE(GPIOF, 9U) +#define LINE_SAI1_FS_B PAL_LINE(GPIOF, 9U) +#define LINE_ARD_A5 PAL_LINE(GPIOF, 10U) +#define LINE_ADC3_IN8 PAL_LINE(GPIOF, 10U) +#define LINE_ARD_D8 PAL_LINE(GPIOF, 12U) +#define LINE_ARD_D7 PAL_LINE(GPIOF, 13U) +#define LINE_ARD_D4 PAL_LINE(GPIOF, 14U) +#define LINE_ARD_D2 PAL_LINE(GPIOF, 15U) +#define LINE_ZIO_D65 PAL_LINE(GPIOG, 0U) +#define LINE_ZIO_D64 PAL_LINE(GPIOG, 1U) +#define LINE_ZIO_D49 PAL_LINE(GPIOG, 2U) +#define LINE_ZIO_D50 PAL_LINE(GPIOG, 3U) +#define LINE_USB_GPIO_OUT PAL_LINE(GPIOG, 6U) +#define LINE_USB_GPIO_IN PAL_LINE(GPIOG, 7U) +#define LINE_ARD_D0 PAL_LINE(GPIOG, 9U) +#define LINE_USART6_RX PAL_LINE(GPIOG, 9U) +#define LINE_RMII_TX_EN PAL_LINE(GPIOG, 11U) +#define LINE_RMII_TXD0 PAL_LINE(GPIOG, 13U) +#define LINE_ARD_D1 PAL_LINE(GPIOG, 14U) +#define LINE_USART6_TX PAL_LINE(GPIOG, 14U) +#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) +#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * GPIOA setup: + * + * PA0 - ZIO_D32 TIM2_CH1 (input pullup). + * PA1 - RMII_REF_CLK (alternate 11). + * PA2 - RMII_MDIO (alternate 11). + * PA3 - ARD_A0 ADC123_IN3 (input pullup). + * PA4 - ZIO_D24 SPI3_NSS (input pullup). + * PA5 - ARD_D13 SPI1_SCK (input pullup). + * PA6 - ARD_D12 SPI1_MISO (input pullup). + * PA7 - ARD_D11 SPI1_MOSI ZIO_D71 RMII_RX_DV(alternate 11). + * PA8 - USB_SOF (alternate 10). + * PA9 - USB_VBUS (analog). + * PA10 - USB_ID (alternate 10). + * PA11 - USB_DM (alternate 10). + * PA12 - USB_DP (alternate 10). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - ZIO_D20 I2S3_WS (input pullup). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_ZIO_D32) | \ + PIN_MODE_ALTERNATE(GPIOA_RMII_REF_CLK) |\ + PIN_MODE_ALTERNATE(GPIOA_RMII_MDIO) | \ + PIN_MODE_INPUT(GPIOA_ARD_A0) | \ + PIN_MODE_INPUT(GPIOA_ZIO_D24) | \ + PIN_MODE_INPUT(GPIOA_ARD_D13) | \ + PIN_MODE_INPUT(GPIOA_ARD_D12) | \ + PIN_MODE_ALTERNATE(GPIOA_ARD_D11) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_SOF) | \ + PIN_MODE_ANALOG(GPIOA_USB_VBUS) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_ID) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_DP) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_INPUT(GPIOA_ZIO_D20)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ZIO_D32) | \ + PIN_OTYPE_PUSHPULL(GPIOA_RMII_REF_CLK) |\ + PIN_OTYPE_PUSHPULL(GPIOA_RMII_MDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ZIO_D24) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D13) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D12) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D11) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_SOF) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_VBUS) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_ID) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ZIO_D20)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ZIO_D32) | \ + PIN_OSPEED_HIGH(GPIOA_RMII_REF_CLK) | \ + PIN_OSPEED_HIGH(GPIOA_RMII_MDIO) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \ + PIN_OSPEED_HIGH(GPIOA_ZIO_D24) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D13) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D12) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D11) | \ + PIN_OSPEED_HIGH(GPIOA_USB_SOF) | \ + PIN_OSPEED_HIGH(GPIOA_USB_VBUS) | \ + PIN_OSPEED_HIGH(GPIOA_USB_ID) | \ + PIN_OSPEED_HIGH(GPIOA_USB_DM) | \ + PIN_OSPEED_HIGH(GPIOA_USB_DP) | \ + PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ + PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ + PIN_OSPEED_HIGH(GPIOA_ZIO_D20)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_ZIO_D32) | \ + PIN_PUPDR_FLOATING(GPIOA_RMII_REF_CLK) |\ + PIN_PUPDR_PULLUP(GPIOA_RMII_MDIO) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_A0) | \ + PIN_PUPDR_PULLUP(GPIOA_ZIO_D24) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D13) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D12) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D11) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_SOF) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_VBUS) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_ID) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_DM) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_DP) | \ + PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \ + PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \ + PIN_PUPDR_PULLUP(GPIOA_ZIO_D20)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_ZIO_D32) | \ + PIN_ODR_HIGH(GPIOA_RMII_REF_CLK) | \ + PIN_ODR_HIGH(GPIOA_RMII_MDIO) | \ + PIN_ODR_HIGH(GPIOA_ARD_A0) | \ + PIN_ODR_HIGH(GPIOA_ZIO_D24) | \ + PIN_ODR_HIGH(GPIOA_ARD_D13) | \ + PIN_ODR_HIGH(GPIOA_ARD_D12) | \ + PIN_ODR_HIGH(GPIOA_ARD_D11) | \ + PIN_ODR_HIGH(GPIOA_USB_SOF) | \ + PIN_ODR_HIGH(GPIOA_USB_VBUS) | \ + PIN_ODR_HIGH(GPIOA_USB_ID) | \ + PIN_ODR_HIGH(GPIOA_USB_DM) | \ + PIN_ODR_HIGH(GPIOA_USB_DP) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_ZIO_D20)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ZIO_D32, 0U) | \ + PIN_AFIO_AF(GPIOA_RMII_REF_CLK, 11U) | \ + PIN_AFIO_AF(GPIOA_RMII_MDIO, 11U) | \ + PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \ + PIN_AFIO_AF(GPIOA_ZIO_D24, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D13, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D12, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D11, 11U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_SOF, 10U) | \ + PIN_AFIO_AF(GPIOA_USB_VBUS, 0U) | \ + PIN_AFIO_AF(GPIOA_USB_ID, 10U) | \ + PIN_AFIO_AF(GPIOA_USB_DM, 10U) | \ + PIN_AFIO_AF(GPIOA_USB_DP, 10U) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ + PIN_AFIO_AF(GPIOA_ZIO_D20, 0U)) + +/* + * GPIOB setup: + * + * PB0 - ZIO_D33 TIM3_CH3 LED1 (output pushpull maximum). + * PB1 - ZIO_A6 ADC12_IN9 (input pullup). + * PB2 - ZIO_D27 (input pullup). + * PB3 - ZIO_D23 I2S3_CK SWO (alternate). + * PB4 - ZIO_D25 SPI3_MISO (input pullup). + * PB5 - ZIO_D22 I2S3_SD (input pullup). + * PB6 - ZIO_D26 (input pullup). + * PB7 - LED2 (output pushpull maximum). + * PB8 - ARD_D15 I2C1_SCL (input pullup). + * PB9 - ARD_D14 I2C1_SDA (input pullup). + * PB10 - ZIO_D36 TIM2_CH3 (input pullup). + * PB11 - ZIO_D35 TIM2_CH4 (input pullup). + * PB12 - ZIO_D19 I2S2_WS (input pullup). + * PB13 - ZIO_D18 I2S2_CK RMII_TXD1 (alternate 11). + * PB14 - LED3 (output pushpull maximum). + * PB15 - ZIO_D17 I2S2_SD (input pullup). + */ +#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_ZIO_D33) | \ + PIN_MODE_INPUT(GPIOB_ZIO_A6) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D27) | \ + PIN_MODE_ALTERNATE(GPIOB_SWO) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D25) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D22) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D26) | \ + PIN_MODE_OUTPUT(GPIOB_LED2) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D36) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D35) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D19) | \ + PIN_MODE_ALTERNATE(GPIOB_ZIO_D18) | \ + PIN_MODE_OUTPUT(GPIOB_LED3) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D17)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D33) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_A6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D27) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D25) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D22) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D26) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LED2) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D36) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D35) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D19) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D18) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LED3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D17)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ZIO_D33) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_A6) | \ + PIN_OSPEED_VERYLOW(GPIOB_ZIO_D27) | \ + PIN_OSPEED_HIGH(GPIOB_SWO) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D25) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D22) | \ + PIN_OSPEED_VERYLOW(GPIOB_ZIO_D26) | \ + PIN_OSPEED_HIGH(GPIOB_LED2) | \ + PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ + PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D36) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D35) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D19) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D18) | \ + PIN_OSPEED_HIGH(GPIOB_LED3) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D17)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_ZIO_D33) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_A6) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D27) | \ + PIN_PUPDR_FLOATING(GPIOB_SWO) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D25) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D22) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D26) | \ + PIN_PUPDR_FLOATING(GPIOB_LED2) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D36) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D35) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D19) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D18) | \ + PIN_PUPDR_FLOATING(GPIOB_LED3) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D17)) +#define VAL_GPIOB_ODR (PIN_ODR_LOW(GPIOB_ZIO_D33) | \ + PIN_ODR_HIGH(GPIOB_ZIO_A6) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D27) | \ + PIN_ODR_HIGH(GPIOB_SWO) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D25) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D22) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D26) | \ + PIN_ODR_LOW(GPIOB_LED2) | \ + PIN_ODR_LOW(GPIOB_I2C1_SCL) | \ + PIN_ODR_LOW(GPIOB_I2C1_SDA) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D36) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D35) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D19) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D18) | \ + PIN_ODR_LOW(GPIOB_LED3) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D17)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ZIO_D33, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_A6, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D27, 0U) | \ + PIN_AFIO_AF(GPIOB_SWO, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D25, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D22, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D26, 0U) | \ + PIN_AFIO_AF(GPIOB_LED2, 0U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4U) | \ + PIN_AFIO_AF(GPIOB_I2C1_SDA, 4U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D36, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D35, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D19, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D18, 11U) | \ + PIN_AFIO_AF(GPIOB_LED3, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D17, 0U)) + +/* + * GPIOC setup: + * + * PC0 - ARD_A1 ADC123_IN10 (input pullup). + * PC1 - RMII_MDC (alternate 11). + * PC2 - ZIO_A7 ADC123_IN12 (input pullup). + * PC3 - ARD_A2 ADC123_IN13 (input pullup). + * PC4 - RMII_RXD0 (alternate 11). + * PC5 - RMII_RXD1 (alternate 11). + * PC6 - ZIO_D16 I2S2_MCK (input pullup). + * PC7 - ZIO_D21 I2S3_MCK (input pullup). + * PC8 - ZIO_D43 SDMMC_D0 (input pullup). + * PC9 - ZIO_D44 SDMMC_D1 (input pullup). + * PC10 - ZIO_D45 SDMMC_D2 (input pullup). + * PC11 - ZIO_D46 SDMMC_D3 (input pullup). + * PC12 - ZIO_D47 SDMMC_CK (input pullup). + * PC13 - BUTTON (input floating). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_ARD_A1) | \ + PIN_MODE_ALTERNATE(GPIOC_RMII_MDC) | \ + PIN_MODE_INPUT(GPIOC_ZIO_A7) | \ + PIN_MODE_INPUT(GPIOC_ARD_A2) | \ + PIN_MODE_ALTERNATE(GPIOC_RMII_RXD0) | \ + PIN_MODE_ALTERNATE(GPIOC_RMII_RXD1) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D16) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D21) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D43) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D44) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D45) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D46) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D47) | \ + PIN_MODE_INPUT(GPIOC_BUTTON) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ARD_A1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_RMII_MDC) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_A7) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_A2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D16) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D21) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D43) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D44) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D45) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D46) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D47) | \ + PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ARD_A1) | \ + PIN_OSPEED_HIGH(GPIOC_RMII_MDC) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_A7) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_A2) | \ + PIN_OSPEED_HIGH(GPIOC_RMII_RXD0) | \ + PIN_OSPEED_HIGH(GPIOC_RMII_RXD1) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D16) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D21) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D43) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D44) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D45) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D46) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D47) | \ + PIN_OSPEED_HIGH(GPIOC_BUTTON) | \ + PIN_OSPEED_VERYLOW(GPIOC_OSC32_IN) | \ + PIN_OSPEED_VERYLOW(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_ARD_A1) | \ + PIN_PUPDR_FLOATING(GPIOC_RMII_MDC) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_A7) | \ + PIN_PUPDR_PULLUP(GPIOC_ARD_A2) | \ + PIN_PUPDR_FLOATING(GPIOC_RMII_RXD0) | \ + PIN_PUPDR_FLOATING(GPIOC_RMII_RXD1) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D16) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D21) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D43) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D44) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D45) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D46) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D47) | \ + PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_ARD_A1) | \ + PIN_ODR_HIGH(GPIOC_RMII_MDC) | \ + PIN_ODR_HIGH(GPIOC_ZIO_A7) | \ + PIN_ODR_HIGH(GPIOC_ARD_A2) | \ + PIN_ODR_HIGH(GPIOC_RMII_RXD0) | \ + PIN_ODR_HIGH(GPIOC_RMII_RXD1) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D16) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D21) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D43) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D44) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D45) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D46) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D47) | \ + PIN_ODR_HIGH(GPIOC_BUTTON) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ARD_A1, 0U) | \ + PIN_AFIO_AF(GPIOC_RMII_MDC, 11U) | \ + PIN_AFIO_AF(GPIOC_ZIO_A7, 0U) | \ + PIN_AFIO_AF(GPIOC_ARD_A2, 0U) | \ + PIN_AFIO_AF(GPIOC_RMII_RXD0, 11U) | \ + PIN_AFIO_AF(GPIOC_RMII_RXD1, 11U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D16, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D21, 0U)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_ZIO_D43, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D44, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D45, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D46, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D47, 0U) | \ + PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) + +/* + * GPIOD setup: + * + * PD0 - ZIO_D67 CAN1_RX (input pullup). + * PD1 - ZIO_D66 CAN1_TX (input pullup). + * PD2 - ZIO_D48 SDMMC_CMD (input pullup). + * PD3 - ZIO_D55 USART2_CTS (input pullup). + * PD4 - ZIO_D54 USART2_RTS (input pullup). + * PD5 - ZIO_D53 USART2_TX (input pullup). + * PD6 - ZIO_D52 USART2_RX (input pullup). + * PD7 - ZIO_D51 USART2_SCLK (input pullup). + * PD8 - USART3_TX STLK_TX (alternate 7). + * PD9 - USART3_RX STLK_RX (alternate 7). + * PD10 - PIN10 (input pullup). + * PD11 - ZIO_D30 (input pullup). + * PD12 - ZIO_D29 (input pullup). + * PD13 - ZIO_D28 (input pullup). + * PD14 - ARD_D10 SPI1_NSS (input pullup). + * PD15 - ARD_D9 TIM4_CH4 (input pullup). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_ZIO_D67) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D66) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D48) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D55) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D54) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D53) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D52) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D51) | \ + PIN_MODE_ALTERNATE(GPIOD_USART3_TX) | \ + PIN_MODE_ALTERNATE(GPIOD_USART3_RX) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D30) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D29) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D28) | \ + PIN_MODE_INPUT(GPIOD_ARD_D10) | \ + PIN_MODE_INPUT(GPIOD_ARD_D9)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D67) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D66) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D48) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D55) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D54) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D53) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D52) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D51) | \ + PIN_OTYPE_PUSHPULL(GPIOD_USART3_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_USART3_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D30) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D29) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D28) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ARD_D10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ARD_D9)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_ZIO_D67) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D66) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D48) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D55) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D54) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D53) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D52) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D51) | \ + PIN_OSPEED_HIGH(GPIOD_USART3_TX) | \ + PIN_OSPEED_HIGH(GPIOD_USART3_RX) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOD_ZIO_D30) | \ + PIN_OSPEED_VERYLOW(GPIOD_ZIO_D29) | \ + PIN_OSPEED_VERYLOW(GPIOD_ZIO_D28) | \ + PIN_OSPEED_HIGH(GPIOD_ARD_D10) | \ + PIN_OSPEED_HIGH(GPIOD_ARD_D9)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_ZIO_D67) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D66) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D48) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D55) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D54) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D53) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D52) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D51) | \ + PIN_PUPDR_FLOATING(GPIOD_USART3_TX) | \ + PIN_PUPDR_FLOATING(GPIOD_USART3_RX) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D30) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D29) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D28) | \ + PIN_PUPDR_PULLUP(GPIOD_ARD_D10) | \ + PIN_PUPDR_PULLUP(GPIOD_ARD_D9)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_ZIO_D67) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D66) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D48) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D55) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D54) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D53) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D52) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D51) | \ + PIN_ODR_HIGH(GPIOD_USART3_TX) | \ + PIN_ODR_HIGH(GPIOD_USART3_RX) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D30) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D29) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D28) | \ + PIN_ODR_HIGH(GPIOD_ARD_D10) | \ + PIN_ODR_HIGH(GPIOD_ARD_D9)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_ZIO_D67, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D66, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D48, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D55, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D54, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D53, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D52, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D51, 0U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_USART3_TX, 7U) | \ + PIN_AFIO_AF(GPIOD_USART3_RX, 7U) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D30, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D29, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D28, 0U) | \ + PIN_AFIO_AF(GPIOD_ARD_D10, 0U) | \ + PIN_AFIO_AF(GPIOD_ARD_D9, 0U)) + +/* + * GPIOE setup: + * + * PE0 - ZIO_D34 TIM4_ETR (input pullup). + * PE1 - PIN1 (input pullup). + * PE2 - ZIO_D31 ZIO_D56 SAI1_MCLK_A(input pullup). + * PE3 - ZIO_D60 SAI1_SD_B (input pullup). + * PE4 - ZIO_D57 SAI1_FS_A (input pullup). + * PE5 - ZIO_D58 SAI1_SCK_A (input pullup). + * PE6 - ZIO_D59 SAI1_SD_A (input pullup). + * PE7 - ZIO_D41 TIM1_ETR (input pullup). + * PE8 - ZIO_D42 TIM1_CH1N (input pullup). + * PE9 - ARD_D6 TIM1_CH1 (input pullup). + * PE10 - ZIO_D40 TIM1_CH2N (input pullup). + * PE11 - ARD_D5 TIM1_CH2 (input pullup). + * PE12 - ZIO_D39 TIM1_CH3N (input pullup). + * PE13 - ARD_D3 TIM1_CH3 (input pullup). + * PE14 - ZIO_D38 (input pullup). + * PE15 - ZIO_D37 TIM1_BKIN1 (input pullup). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_ZIO_D34) | \ + PIN_MODE_INPUT(GPIOE_PIN1) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D31) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D60) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D57) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D58) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D59) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D41) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D42) | \ + PIN_MODE_INPUT(GPIOE_ARD_D6) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D40) | \ + PIN_MODE_INPUT(GPIOE_ARD_D5) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D39) | \ + PIN_MODE_INPUT(GPIOE_ARD_D3) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D38) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D37)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D34) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D31) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D60) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D57) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D58) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D59) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D41) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D42) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ARD_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D40) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ARD_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D39) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ARD_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D38) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D37)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_ZIO_D34) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN1) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D31) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D60) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D57) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D58) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D59) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D41) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D42) | \ + PIN_OSPEED_HIGH(GPIOE_ARD_D6) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D40) | \ + PIN_OSPEED_HIGH(GPIOE_ARD_D5) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D39) | \ + PIN_OSPEED_HIGH(GPIOE_ARD_D3) | \ + PIN_OSPEED_VERYLOW(GPIOE_ZIO_D38) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D37)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_ZIO_D34) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D31) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D60) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D57) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D58) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D59) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D41) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D42) | \ + PIN_PUPDR_PULLUP(GPIOE_ARD_D6) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D40) | \ + PIN_PUPDR_PULLUP(GPIOE_ARD_D5) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D39) | \ + PIN_PUPDR_PULLUP(GPIOE_ARD_D3) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D38) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D37)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_ZIO_D34) | \ + PIN_ODR_HIGH(GPIOE_PIN1) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D31) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D60) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D57) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D58) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D59) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D41) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D42) | \ + PIN_ODR_HIGH(GPIOE_ARD_D6) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D40) | \ + PIN_ODR_HIGH(GPIOE_ARD_D5) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D39) | \ + PIN_ODR_HIGH(GPIOE_ARD_D3) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D38) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D37)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_ZIO_D34, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D31, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D60, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D57, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D58, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D59, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D41, 0U)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_ZIO_D42, 0U) | \ + PIN_AFIO_AF(GPIOE_ARD_D6, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D40, 0U) | \ + PIN_AFIO_AF(GPIOE_ARD_D5, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D39, 0U) | \ + PIN_AFIO_AF(GPIOE_ARD_D3, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D38, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D37, 0U)) + +/* + * GPIOF setup: + * + * PF0 - ZIO_D68 I2C2_SDA (input pullup). + * PF1 - ZIO_D69 I2C2_SCL (input pullup). + * PF2 - ZIO_D70 I2C2_SMBA (input pullup). + * PF3 - ARD_A3 ADC3_IN9 (input pullup). + * PF4 - ZIO_A8 ADC3_IN14 (input pullup). + * PF5 - ARD_A4 ADC3_IN15 (input pullup). + * PF6 - PIN6 (input pullup). + * PF7 - SPI5_SCK (Alternate 5). + * PF8 - SPI5_MISO (Alternate 5). + * PF9 - SPI5_MOSI (Alternate 5). + * PF10 - ARD_A5 ADC3_IN8 (input pullup). + * PF11 - PIN11 (input pullup). + * PF12 - ARD_D8 (input pullup). + * PF13 - ARD_D7 (input pullup). + * PF14 - ARD_D4 (input pullup). + * PF15 - ARD_D2 (input pullup). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_ZIO_D68) | \ + PIN_MODE_INPUT(GPIOF_ZIO_D69) | \ + PIN_MODE_INPUT(GPIOF_ZIO_D70) | \ + PIN_MODE_INPUT(GPIOF_ARD_A3) | \ + PIN_MODE_INPUT(GPIOF_ZIO_A8) | \ + PIN_MODE_INPUT(GPIOF_ARD_A4) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_ALTERNATE(GPIOF_SPI5_SCK) | \ + PIN_MODE_ALTERNATE(GPIOF_SPI5_MISO) | \ + PIN_MODE_ALTERNATE(GPIOF_SPI5_MOSI) | \ + PIN_MODE_INPUT(GPIOF_ARD_A5) | \ + PIN_MODE_INPUT(GPIOF_PIN11) | \ + PIN_MODE_INPUT(GPIOF_ARD_D8) | \ + PIN_MODE_INPUT(GPIOF_ARD_D7) | \ + PIN_MODE_INPUT(GPIOF_ARD_D4) | \ + PIN_MODE_INPUT(GPIOF_ARD_D2)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D68) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D69) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D70) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_A3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ZIO_A8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_A4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_SPI5_SCK) | \ + PIN_OTYPE_PUSHPULL(GPIOF_SPI5_MISO) | \ + PIN_OTYPE_PUSHPULL(GPIOF_SPI5_MOSI) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_A5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D2)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_ZIO_D68) | \ + PIN_OSPEED_HIGH(GPIOF_ZIO_D69) | \ + PIN_OSPEED_HIGH(GPIOF_ZIO_D70) | \ + PIN_OSPEED_HIGH(GPIOF_ARD_A3) | \ + PIN_OSPEED_HIGH(GPIOF_ZIO_A8) | \ + PIN_OSPEED_HIGH(GPIOF_ARD_A4) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN6) | \ + PIN_OSPEED_HIGH(GPIOF_SPI5_SCK) | \ + PIN_OSPEED_HIGH(GPIOF_SPI5_MISO) | \ + PIN_OSPEED_HIGH(GPIOF_SPI5_MOSI) | \ + PIN_OSPEED_HIGH(GPIOF_ARD_A5) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOF_ARD_D8) | \ + PIN_OSPEED_VERYLOW(GPIOF_ARD_D7) | \ + PIN_OSPEED_VERYLOW(GPIOF_ARD_D4) | \ + PIN_OSPEED_VERYLOW(GPIOF_ARD_D2)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_ZIO_D68) | \ + PIN_PUPDR_PULLUP(GPIOF_ZIO_D69) | \ + PIN_PUPDR_PULLUP(GPIOF_ZIO_D70) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_A3) | \ + PIN_PUPDR_PULLUP(GPIOF_ZIO_A8) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_A4) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOF_SPI5_SCK) | \ + PIN_PUPDR_FLOATING(GPIOF_SPI5_MISO) | \ + PIN_PUPDR_FLOATING(GPIOF_SPI5_MOSI) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_A5) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D8) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D7) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D4) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D2)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_ZIO_D68) | \ + PIN_ODR_HIGH(GPIOF_ZIO_D69) | \ + PIN_ODR_HIGH(GPIOF_ZIO_D70) | \ + PIN_ODR_HIGH(GPIOF_ARD_A3) | \ + PIN_ODR_HIGH(GPIOF_ZIO_A8) | \ + PIN_ODR_HIGH(GPIOF_ARD_A4) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_SPI5_SCK) | \ + PIN_ODR_HIGH(GPIOF_SPI5_MISO) | \ + PIN_ODR_HIGH(GPIOF_SPI5_MOSI) | \ + PIN_ODR_HIGH(GPIOF_ARD_A5) | \ + PIN_ODR_HIGH(GPIOF_PIN11) | \ + PIN_ODR_HIGH(GPIOF_ARD_D8) | \ + PIN_ODR_HIGH(GPIOF_ARD_D7) | \ + PIN_ODR_HIGH(GPIOF_ARD_D4) | \ + PIN_ODR_HIGH(GPIOF_ARD_D2)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_ZIO_D68, 0U) | \ + PIN_AFIO_AF(GPIOF_ZIO_D69, 0U) | \ + PIN_AFIO_AF(GPIOF_ZIO_D70, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_A3, 0U) | \ + PIN_AFIO_AF(GPIOF_ZIO_A8, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_A4, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOF_SPI5_SCK, 5U)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_SPI5_MISO, 5U) | \ + PIN_AFIO_AF(GPIOF_SPI5_MOSI, 5U) | \ + PIN_AFIO_AF(GPIOF_ARD_A5, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_D8, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_D7, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_D4, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_D2, 0U)) + +/* + * GPIOG setup: + * + * PG0 - ZIO_D65 (input pullup). + * PG1 - ZIO_D64 (input pullup). + * PG2 - ZIO_D49 (input pullup). + * PG3 - ZIO_D50 (input pullup). + * PG4 - PIN4 (input pullup). + * PG5 - PIN5 (input pullup). + * PG6 - USB_GPIO_OUT (input pullup). + * PG7 - USB_GPIO_IN (input pullup). + * PG8 - PIN8 (input pullup). + * PG9 - ARD_D0 USART6_RX (input pullup). + * PG10 - PIN10 (input pullup). + * PG11 - RMII_TX_EN (alternate 11). + * PG12 - PIN12 (input pullup). + * PG13 - RMII_TXD0 (alternate 11). + * PG14 - ARD_D1 USART6_TX (input pullup). + * PG15 - PIN15 (input pullup). + */ +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_ZIO_D65) | \ + PIN_MODE_INPUT(GPIOG_ZIO_D64) | \ + PIN_MODE_INPUT(GPIOG_ZIO_D49) | \ + PIN_MODE_INPUT(GPIOG_ZIO_D50) | \ + PIN_MODE_INPUT(GPIOG_PIN4) | \ + PIN_MODE_INPUT(GPIOG_PIN5) | \ + PIN_MODE_INPUT(GPIOG_USB_GPIO_OUT) | \ + PIN_MODE_INPUT(GPIOG_USB_GPIO_IN) | \ + PIN_MODE_INPUT(GPIOG_PIN8) | \ + PIN_MODE_ALTERNATE(GPIOG_USART6_RX) | \ + PIN_MODE_INPUT(GPIOG_PIN10) | \ + PIN_MODE_ALTERNATE(GPIOG_RMII_TX_EN) | \ + PIN_MODE_INPUT(GPIOG_PIN12) | \ + PIN_MODE_ALTERNATE(GPIOG_RMII_TXD0) | \ + PIN_MODE_ALTERNATE(GPIOG_USART6_TX) | \ + PIN_MODE_INPUT(GPIOG_PIN15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D65) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D64) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D49) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D50) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOG_USB_GPIO_OUT) |\ + PIN_OTYPE_PUSHPULL(GPIOG_USB_GPIO_IN) |\ + PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOG_USART6_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_RMII_TX_EN) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOG_RMII_TXD0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_USART6_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOG_ZIO_D65) | \ + PIN_OSPEED_VERYLOW(GPIOG_ZIO_D64) | \ + PIN_OSPEED_VERYLOW(GPIOG_ZIO_D49) | \ + PIN_OSPEED_VERYLOW(GPIOG_ZIO_D50) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN5) | \ + PIN_OSPEED_HIGH(GPIOG_USB_GPIO_OUT) | \ + PIN_OSPEED_HIGH(GPIOG_USB_GPIO_IN) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN8) | \ + PIN_OSPEED_HIGH(GPIOG_USART6_RX) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN10) | \ + PIN_OSPEED_HIGH(GPIOG_RMII_TX_EN) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN12) | \ + PIN_OSPEED_HIGH(GPIOG_RMII_TXD0) | \ + PIN_OSPEED_HIGH(GPIOG_USART6_TX) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_ZIO_D65) | \ + PIN_PUPDR_PULLUP(GPIOG_ZIO_D64) | \ + PIN_PUPDR_PULLUP(GPIOG_ZIO_D49) | \ + PIN_PUPDR_PULLUP(GPIOG_ZIO_D50) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOG_USB_GPIO_OUT) | \ + PIN_PUPDR_PULLUP(GPIOG_USB_GPIO_IN) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOG_USART6_RX) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOG_RMII_TX_EN) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOG_RMII_TXD0) | \ + PIN_PUPDR_FLOATING(GPIOG_USART6_TX) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_ZIO_D65) | \ + PIN_ODR_HIGH(GPIOG_ZIO_D64) | \ + PIN_ODR_HIGH(GPIOG_ZIO_D49) | \ + PIN_ODR_HIGH(GPIOG_ZIO_D50) | \ + PIN_ODR_HIGH(GPIOG_PIN4) | \ + PIN_ODR_HIGH(GPIOG_PIN5) | \ + PIN_ODR_HIGH(GPIOG_USB_GPIO_OUT) | \ + PIN_ODR_HIGH(GPIOG_USB_GPIO_IN) | \ + PIN_ODR_HIGH(GPIOG_PIN8) | \ + PIN_ODR_HIGH(GPIOG_USART6_RX) | \ + PIN_ODR_HIGH(GPIOG_PIN10) | \ + PIN_ODR_HIGH(GPIOG_RMII_TX_EN) | \ + PIN_ODR_HIGH(GPIOG_PIN12) | \ + PIN_ODR_HIGH(GPIOG_RMII_TXD0) | \ + PIN_ODR_HIGH(GPIOG_USART6_TX) | \ + PIN_ODR_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_ZIO_D65, 0U) | \ + PIN_AFIO_AF(GPIOG_ZIO_D64, 0U) | \ + PIN_AFIO_AF(GPIOG_ZIO_D49, 0U) | \ + PIN_AFIO_AF(GPIOG_ZIO_D50, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOG_USB_GPIO_OUT, 0U) | \ + PIN_AFIO_AF(GPIOG_USB_GPIO_IN, 0U)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOG_USART6_RX, 8U) | \ + PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOG_RMII_TX_EN, 11U) | \ + PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOG_RMII_TXD0, 11U) | \ + PIN_AFIO_AF(GPIOG_USART6_TX, 8U) | \ + PIN_AFIO_AF(GPIOG_PIN15, 0U)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - PIN2 (input pullup). + * PH3 - PIN3 (input pullup). + * PH4 - PIN4 (input pullup). + * PH5 - PIN5 (input pullup). + * PH6 - PIN6 (input pullup). + * PH7 - PIN7 (input pullup). + * PH8 - PIN8 (input pullup). + * PH9 - PIN9 (input pullup). + * PH10 - PIN10 (input pullup). + * PH11 - PIN11 (input pullup). + * PH12 - PIN12 (input pullup). + * PH13 - PIN13 (input pullup). + * PH14 - PIN14 (input pullup). + * PH15 - PIN15 (input pullup). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOH_PIN2) | \ + PIN_MODE_INPUT(GPIOH_PIN3) | \ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_INPUT(GPIOH_PIN5) | \ + PIN_MODE_INPUT(GPIOH_PIN6) | \ + PIN_MODE_INPUT(GPIOH_PIN7) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ + PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0U)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0U)) + +/* + * GPIOI setup: + * + * PI0 - PIN0 (input pullup). + * PI1 - PIN1 (input pullup). + * PI2 - PIN2 (input pullup). + * PI3 - PIN3 (input pullup). + * PI4 - PIN4 (input pullup). + * PI5 - PIN5 (input pullup). + * PI6 - PIN6 (input pullup). + * PI7 - PIN7 (input pullup). + * PI8 - PIN8 (input pullup). + * PI9 - PIN9 (input pullup). + * PI10 - PIN10 (input pullup). + * PI11 - PIN11 (input pullup). + * PI12 - PIN12 (input pullup). + * PI13 - PIN13 (input pullup). + * PI14 - PIN14 (input pullup). + * PI15 - PIN15 (input pullup). + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ + PIN_MODE_INPUT(GPIOI_PIN1) | \ + PIN_MODE_INPUT(GPIOI_PIN2) | \ + PIN_MODE_INPUT(GPIOI_PIN3) | \ + PIN_MODE_INPUT(GPIOI_PIN4) | \ + PIN_MODE_INPUT(GPIOI_PIN5) | \ + PIN_MODE_INPUT(GPIOI_PIN6) | \ + PIN_MODE_INPUT(GPIOI_PIN7) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_INPUT(GPIOI_PIN9) | \ + PIN_MODE_INPUT(GPIOI_PIN10) | \ + PIN_MODE_INPUT(GPIOI_PIN11) | \ + PIN_MODE_INPUT(GPIOI_PIN12) | \ + PIN_MODE_INPUT(GPIOI_PIN13) | \ + PIN_MODE_INPUT(GPIOI_PIN14) | \ + PIN_MODE_INPUT(GPIOI_PIN15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOI_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ + PIN_ODR_HIGH(GPIOI_PIN1) | \ + PIN_ODR_HIGH(GPIOI_PIN2) | \ + PIN_ODR_HIGH(GPIOI_PIN3) | \ + PIN_ODR_HIGH(GPIOI_PIN4) | \ + PIN_ODR_HIGH(GPIOI_PIN5) | \ + PIN_ODR_HIGH(GPIOI_PIN6) | \ + PIN_ODR_HIGH(GPIOI_PIN7) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_PIN9) | \ + PIN_ODR_HIGH(GPIOI_PIN10) | \ + PIN_ODR_HIGH(GPIOI_PIN11) | \ + PIN_ODR_HIGH(GPIOI_PIN12) | \ + PIN_ODR_HIGH(GPIOI_PIN13) | \ + PIN_ODR_HIGH(GPIOI_PIN14) | \ + PIN_ODR_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN7, 0U)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN15, 0U)) + +/* + * GPIOJ setup: + * + * PJ0 - PIN0 (input pullup). + * PJ1 - PIN1 (input pullup). + * PJ2 - PIN2 (input pullup). + * PJ3 - PIN3 (input pullup). + * PJ4 - PIN4 (input pullup). + * PJ5 - PIN5 (input pullup). + * PJ6 - PIN6 (input pullup). + * PJ7 - PIN7 (input pullup). + * PJ8 - PIN8 (input pullup). + * PJ9 - PIN9 (input pullup). + * PJ10 - PIN10 (input pullup). + * PJ11 - PIN11 (input pullup). + * PJ12 - PIN12 (input pullup). + * PJ13 - PIN13 (input pullup). + * PJ14 - PIN14 (input pullup). + * PJ15 - PIN15 (input pullup). + */ +#define VAL_GPIOJ_MODER (PIN_MODE_INPUT(GPIOJ_PIN0) | \ + PIN_MODE_INPUT(GPIOJ_PIN1) | \ + PIN_MODE_INPUT(GPIOJ_PIN2) | \ + PIN_MODE_INPUT(GPIOJ_PIN3) | \ + PIN_MODE_INPUT(GPIOJ_PIN4) | \ + PIN_MODE_INPUT(GPIOJ_PIN5) | \ + PIN_MODE_INPUT(GPIOJ_PIN6) | \ + PIN_MODE_INPUT(GPIOJ_PIN7) | \ + PIN_MODE_INPUT(GPIOJ_PIN8) | \ + PIN_MODE_INPUT(GPIOJ_PIN9) | \ + PIN_MODE_INPUT(GPIOJ_PIN10) | \ + PIN_MODE_INPUT(GPIOJ_PIN11) | \ + PIN_MODE_INPUT(GPIOJ_PIN12) | \ + PIN_MODE_INPUT(GPIOJ_PIN13) | \ + PIN_MODE_INPUT(GPIOJ_PIN14) | \ + PIN_MODE_INPUT(GPIOJ_PIN15)) +#define VAL_GPIOJ_OTYPER (PIN_OTYPE_PUSHPULL(GPIOJ_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN15)) +#define VAL_GPIOJ_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOJ_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN15)) +#define VAL_GPIOJ_PUPDR (PIN_PUPDR_PULLUP(GPIOJ_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN15)) +#define VAL_GPIOJ_ODR (PIN_ODR_HIGH(GPIOJ_PIN0) | \ + PIN_ODR_HIGH(GPIOJ_PIN1) | \ + PIN_ODR_HIGH(GPIOJ_PIN2) | \ + PIN_ODR_HIGH(GPIOJ_PIN3) | \ + PIN_ODR_HIGH(GPIOJ_PIN4) | \ + PIN_ODR_HIGH(GPIOJ_PIN5) | \ + PIN_ODR_HIGH(GPIOJ_PIN6) | \ + PIN_ODR_HIGH(GPIOJ_PIN7) | \ + PIN_ODR_HIGH(GPIOJ_PIN8) | \ + PIN_ODR_HIGH(GPIOJ_PIN9) | \ + PIN_ODR_HIGH(GPIOJ_PIN10) | \ + PIN_ODR_HIGH(GPIOJ_PIN11) | \ + PIN_ODR_HIGH(GPIOJ_PIN12) | \ + PIN_ODR_HIGH(GPIOJ_PIN13) | \ + PIN_ODR_HIGH(GPIOJ_PIN14) | \ + PIN_ODR_HIGH(GPIOJ_PIN15)) +#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(GPIOJ_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN7, 0U)) +#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(GPIOJ_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN15, 0U)) + +/* + * GPIOK setup: + * + * PK0 - PIN0 (input pullup). + * PK1 - PIN1 (input pullup). + * PK2 - PIN2 (input pullup). + * PK3 - PIN3 (input pullup). + * PK4 - PIN4 (input pullup). + * PK5 - PIN5 (input pullup). + * PK6 - PIN6 (input pullup). + * PK7 - PIN7 (input pullup). + * PK8 - PIN8 (input pullup). + * PK9 - PIN9 (input pullup). + * PK10 - PIN10 (input pullup). + * PK11 - PIN11 (input pullup). + * PK12 - PIN12 (input pullup). + * PK13 - PIN13 (input pullup). + * PK14 - PIN14 (input pullup). + * PK15 - PIN15 (input pullup). + */ +#define VAL_GPIOK_MODER (PIN_MODE_INPUT(GPIOK_PIN0) | \ + PIN_MODE_INPUT(GPIOK_PIN1) | \ + PIN_MODE_INPUT(GPIOK_PIN2) | \ + PIN_MODE_INPUT(GPIOK_PIN3) | \ + PIN_MODE_INPUT(GPIOK_PIN4) | \ + PIN_MODE_INPUT(GPIOK_PIN5) | \ + PIN_MODE_INPUT(GPIOK_PIN6) | \ + PIN_MODE_INPUT(GPIOK_PIN7) | \ + PIN_MODE_INPUT(GPIOK_PIN8) | \ + PIN_MODE_INPUT(GPIOK_PIN9) | \ + PIN_MODE_INPUT(GPIOK_PIN10) | \ + PIN_MODE_INPUT(GPIOK_PIN11) | \ + PIN_MODE_INPUT(GPIOK_PIN12) | \ + PIN_MODE_INPUT(GPIOK_PIN13) | \ + PIN_MODE_INPUT(GPIOK_PIN14) | \ + PIN_MODE_INPUT(GPIOK_PIN15)) +#define VAL_GPIOK_OTYPER (PIN_OTYPE_PUSHPULL(GPIOK_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN15)) +#define VAL_GPIOK_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOK_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN15)) +#define VAL_GPIOK_PUPDR (PIN_PUPDR_PULLUP(GPIOK_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN15)) +#define VAL_GPIOK_ODR (PIN_ODR_HIGH(GPIOK_PIN0) | \ + PIN_ODR_HIGH(GPIOK_PIN1) | \ + PIN_ODR_HIGH(GPIOK_PIN2) | \ + PIN_ODR_HIGH(GPIOK_PIN3) | \ + PIN_ODR_HIGH(GPIOK_PIN4) | \ + PIN_ODR_HIGH(GPIOK_PIN5) | \ + PIN_ODR_HIGH(GPIOK_PIN6) | \ + PIN_ODR_HIGH(GPIOK_PIN7) | \ + PIN_ODR_HIGH(GPIOK_PIN8) | \ + PIN_ODR_HIGH(GPIOK_PIN9) | \ + PIN_ODR_HIGH(GPIOK_PIN10) | \ + PIN_ODR_HIGH(GPIOK_PIN11) | \ + PIN_ODR_HIGH(GPIOK_PIN12) | \ + PIN_ODR_HIGH(GPIOK_PIN13) | \ + PIN_ODR_HIGH(GPIOK_PIN14) | \ + PIN_ODR_HIGH(GPIOK_PIN15)) +#define VAL_GPIOK_AFRL (PIN_AFIO_AF(GPIOK_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN7, 0U)) +#define VAL_GPIOK_AFRH (PIN_AFIO_AF(GPIOK_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN15, 0U)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/common/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/common/CMakeLists.txt new file mode 100644 index 00000000..27f8f458 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/common/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c") +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_ConfigurationManager.cpp") + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/common/Device_BlockStorage-DEBUG.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 00000000..7651a37e --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,135 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 16kB blocks +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 1 }, // 0x08000000 nanoBooter + { BlockRange_BLOCKTYPE_CONFIG , 2, 3 } // 0x08008000 nanoConfig +}; + +// 64kB blocks +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 0x08010000 nanoCLR +}; + +// 128kB blocks +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 3 }, // 0x08020000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 4, 6 }, // 0x080A0000 deployment +}; + +// 16kB blocks +const BlockRange BlockRange4[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 3 } // 0x08100000 deployment +}; + +// 64kB blocks +const BlockRange BlockRange5[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 0 } // 0x08110000 deployment +}; + +// 128kB blocks +const BlockRange BlockRange6[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 6 } // 0x08120000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + 0x08010000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + 0x08020000, // start address for block region + 7, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + + { + 0x08100000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange4), + BlockRange4, + }, + + { + 0x08110000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange5), + BlockRange5, + }, + + { + 0x08120000, // start address for block region + 7, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange6), + BlockRange6, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/common/Device_BlockStorage.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/common/Device_BlockStorage.c new file mode 100644 index 00000000..46f13500 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/common/Device_BlockStorage.c @@ -0,0 +1,142 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 16kB blocks +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 1 }, // 0x08000000 nanoBooter + { BlockRange_BLOCKTYPE_CONFIG , 2, 3 } // 0x08008000 nanoConfig +}; + +// 64kB blocks +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 0x08010000 nanoCLR +}; + +// 128kB blocks +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 3 }, // 0x08020000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 4, 6 }, // 0x080A0000 deployment +}; + +// 16kB blocks +const BlockRange BlockRange4[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 3 } // 0x08100000 deployment +}; + +// 64kB blocks +const BlockRange BlockRange5[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 0 } // 0x08110000 deployment +}; + +// 128kB blocks +const BlockRange BlockRange6[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 6 } // 0x08120000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08010000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 7, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + + { + (0), // no attributes for this region + 0x08100000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange4), + BlockRange4, + }, + + { + (0), // no attributes for this region + 0x08110000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange5), + BlockRange5, + }, + + { + (0), // no attributes for this region + 0x08120000, // start address for block region + 7, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange6), + BlockRange6, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/common/serialcfg.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/common/serialcfg.h new file mode 100644 index 00000000..803da07a --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/common/serialcfg.h @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef SERIALCFG_H +#define SERIALCFG_H + +// define which serial driver the Wire Protocol will be using +#define SERIAL_DRIVER SD3 + +#endif /* SERIALCFG_H */ + +/** @} */ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/common/targetHAL_ConfigurationManager.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/common/targetHAL_ConfigurationManager.cpp new file mode 100644 index 00000000..178f6aa7 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/common/targetHAL_ConfigurationManager.cpp @@ -0,0 +1,35 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include + +// Default initialisation for Network interface config blocks +// strong implementation replacing ChibiOS 'weak' one +bool InitialiseNetworkDefaultConfig(HAL_Configuration_NetworkInterface * pconfig, uint32_t configurationIndex) +{ + (void)configurationIndex; + + // make sure the config block marker is set + memcpy(pconfig->Marker, c_MARKER_CONFIGURATION_NETWORK_V1, sizeof(c_MARKER_CONFIGURATION_NETWORK_V1)); + + pconfig->InterfaceType = NetworkInterfaceType_Ethernet; + pconfig->StartupAddressMode = AddressMode_DHCP; + pconfig->AutomaticDNS = 1; + pconfig->SpecificConfigId = 0; + + // set MAC address with ST provided MAC for development boards + // 00:80:E1:01:35:D1 + pconfig->MacAddress[0] = 0x00; + pconfig->MacAddress[1] = 0x80; + pconfig->MacAddress[2] = 0xE1; + pconfig->MacAddress[3] = 0x01; + pconfig->MacAddress[4] = 0x35; + pconfig->MacAddress[5] = 0xD1; + + return true; +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/ffconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/ffconf.h new file mode 100644 index 00000000..7ffb3957 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/ffconf.h @@ -0,0 +1,272 @@ +/* CHIBIOS FIX */ +#include "ch.h" + +/*---------------------------------------------------------------------------/ +/ FatFs - Configuration file +/---------------------------------------------------------------------------*/ + +#define FFCONF_DEF 87030 /* Revision ID */ + +/*---------------------------------------------------------------------------/ +/ Function Configurations +/---------------------------------------------------------------------------*/ + +#define FF_FS_READONLY 0 +/* This option switches read-only configuration. (0:Read/Write or 1:Read-only) +/ Read-only configuration removes writing API functions, f_write(), f_sync(), +/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree() +/ and optional writing functions as well. */ + + +#define FF_FS_MINIMIZE 0 +/* This option defines minimization level to remove some basic API functions. +/ +/ 0: All basic functions are enabled. +/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename() +/ are removed. +/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1. +/ 3: f_lseek() function is removed in addition to 2. */ + + +#define FF_USE_STRFUNC 0 +/* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf(). +/ +/ 0: Disable string functions. +/ 1: Enable without LF-CRLF conversion. +/ 2: Enable with LF-CRLF conversion. */ + + +#define FF_USE_FIND 0 +/* This option switches filtered directory read functions, f_findfirst() and +/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */ + + +#define FF_USE_MKFS 0 +/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */ + + +#define FF_USE_FASTSEEK 0 +/* This option switches fast seek function. (0:Disable or 1:Enable) */ + + +#define FF_USE_EXPAND 0 +/* This option switches f_expand function. (0:Disable or 1:Enable) */ + + +#define FF_USE_CHMOD 0 +/* This option switches attribute manipulation functions, f_chmod() and f_utime(). +/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */ + + +#define FF_USE_LABEL 0 +/* This option switches volume label functions, f_getlabel() and f_setlabel(). +/ (0:Disable or 1:Enable) */ + + +#define FF_USE_FORWARD 0 +/* This option switches f_forward() function. (0:Disable or 1:Enable) */ + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/---------------------------------------------------------------------------*/ + +#define FF_CODE_PAGE 850 +/* This option specifies the OEM code page to be used on the target system. +/ Incorrect code page setting can cause a file open failure. +/ +/ 437 - U.S. +/ 720 - Arabic +/ 737 - Greek +/ 771 - KBL +/ 775 - Baltic +/ 850 - Latin 1 +/ 852 - Latin 2 +/ 855 - Cyrillic +/ 857 - Turkish +/ 860 - Portuguese +/ 861 - Icelandic +/ 862 - Hebrew +/ 863 - Canadian French +/ 864 - Arabic +/ 865 - Nordic +/ 866 - Russian +/ 869 - Greek 2 +/ 932 - Japanese (DBCS) +/ 936 - Simplified Chinese (DBCS) +/ 949 - Korean (DBCS) +/ 950 - Traditional Chinese (DBCS) +/ 0 - Include all code pages above and configured by f_setcp() +*/ + + +#define FF_USE_LFN 3 +#define FF_MAX_LFN 255 +/* The FF_USE_LFN switches the support for LFN (long file name). +/ +/ 0: Disable LFN. FF_MAX_LFN has no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ To enable the LFN, Unicode handling functions (option/unicode.c) must be added +/ to the project. The working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and +/ additional 608 bytes at exFAT enabled. FF_MAX_LFN can be in range from 12 to 255. +/ It should be set 255 to support full featured LFN operations. +/ When use stack for the working buffer, take care on stack overflow. When use heap +/ memory for the working buffer, memory management functions, ff_memalloc() and +/ ff_memfree(), must be added to the project. */ + + +#define FF_LFN_UNICODE 0 +/* This option switches character encoding on the API, 0:ANSI/OEM or 1:UTF-16, +/ when LFN is enabled. Also behavior of string I/O functions will be affected by +/ this option. When LFN is not enabled, this option has no effect. +*/ + + +#define FF_STRF_ENCODE 3 +/* When FF_LFN_UNICODE = 1 with LFN enabled, string I/O functions, f_gets(), +/ f_putc(), f_puts and f_printf() convert the character encoding in it. +/ This option selects assumption of character encoding ON THE FILE to be +/ read/written via those functions. +/ +/ 0: ANSI/OEM +/ 1: UTF-16LE +/ 2: UTF-16BE +/ 3: UTF-8 +*/ + + +#define FF_FS_RPATH 0 +/* This option configures support for relative path. +/ +/ 0: Disable relative path and remove related functions. +/ 1: Enable relative path. f_chdir() and f_chdrive() are available. +/ 2: f_getcwd() function is available in addition to 1. +*/ + + +/*---------------------------------------------------------------------------/ +/ Drive/Volume Configurations +/---------------------------------------------------------------------------*/ + +#define FF_VOLUMES 1 +/* Number of volumes (logical drives) to be used. (1-10) */ + + +#define FF_STR_VOLUME_ID 0 +#define FF_VOLUME_STRS "RAM","NAND","CF","SD","SD2","USB","USB2","USB3" +/* FF_STR_VOLUME_ID switches string support for volume ID. +/ When FF_STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive +/ number in the path name. FF_VOLUME_STRS defines the drive ID strings for each +/ logical drives. Number of items must be equal to FF_VOLUMES. Valid characters for +/ the drive ID strings are: A-Z and 0-9. */ + + +#define FF_MULTI_PARTITION 0 +/* This option switches support for multiple volumes on the physical drive. +/ By default (0), each logical drive number is bound to the same physical drive +/ number and only an FAT volume found on the physical drive will be mounted. +/ When this function is enabled (1), each logical drive number can be bound to +/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk() +/ funciton will be available. */ + + +#define FF_MIN_SS 512 +#define FF_MAX_SS 512 +/* This set of options configures the range of sector size to be supported. (512, +/ 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and +/ harddisk. But a larger value may be required for on-board flash memory and some +/ type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured +/ for variable sector size mode and disk_ioctl() function needs to implement +/ GET_SECTOR_SIZE command. */ + + +#define FF_USE_TRIM 0 +/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable) +/ To enable Trim function, also CTRL_TRIM command should be implemented to the +/ disk_ioctl() function. */ + + +#define FF_FS_NOFSINFO 0 +/* If you need to know correct free space on the FAT32 volume, set bit 0 of this +/ option, and f_getfree() function at first time after volume mount will force +/ a full FAT scan. Bit 1 controls the use of last allocated cluster number. +/ +/ bit0=0: Use free cluster count in the FSINFO if available. +/ bit0=1: Do not trust free cluster count in the FSINFO. +/ bit1=0: Use last allocated cluster number in the FSINFO if available. +/ bit1=1: Do not trust last allocated cluster number in the FSINFO. +*/ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/---------------------------------------------------------------------------*/ + +#define FF_FS_TINY 0 +/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny) +/ At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes. +/ Instead of private sector buffer eliminated from the file object, common sector +/ buffer in the filesystem object (FATFS) is used for the file data transfer. */ + + +#define FF_FS_EXFAT 0 +/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable) +/ When enable exFAT, also LFN needs to be enabled. +/ Note that enabling exFAT discards ANSI C (C89) compatibility. */ + + +#define FF_FS_NORTC 1 +#define FF_NORTC_MON 8 +#define FF_NORTC_MDAY 1 +#define FF_NORTC_YEAR 2018 +/* The option FF_FS_NORTC switches timestamp functiton. If the system does not have +/ any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable +/ the timestamp function. All objects modified by FatFs will have a fixed timestamp +/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time. +/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be +/ added to the project to read current time form real-time clock. FF_NORTC_MON, +/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect. +/ These options have no effect at read-only configuration (FF_FS_READONLY = 1). */ + + +#define FF_FS_LOCK 0 +/* The option FF_FS_LOCK switches file lock function to control duplicated file open +/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY +/ is 1. +/ +/ 0: Disable file lock function. To avoid volume corruption, application program +/ should avoid illegal open, remove and rename to the open objects. +/ >0: Enable file lock function. The value defines how many files/sub-directories +/ can be opened simultaneously under file lock control. Note that the file +/ lock control is independent of re-entrancy. */ + + +#define FF_FS_REENTRANT 0 +#define FF_FS_TIMEOUT TIME_MS2I(1000) +#define FF_SYNC_t semaphore_t* +/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs +/ module itself. Note that regardless of this option, file access to different +/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs() +/ and f_fdisk() function, are always not re-entrant. Only file/directory access +/ to the same volume is under control of this function. +/ +/ 0: Disable re-entrancy. FF_FS_TIMEOUT and FF_SYNC_t have no effect. +/ 1: Enable re-entrancy. Also user provided synchronization handlers, +/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj() +/ function, must be added to the project. Samples are available in +/ option/syscall.c. +/ +/ The FF_FS_TIMEOUT defines timeout period in unit of time tick. +/ The FF_SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*, +/ SemaphoreHandle_t and etc. A header file for O/S definitions needs to be +/ included somewhere in the scope of ff.h. */ + +/* #include // O/S definitions */ + + + +/*--- End of configuration options ---*/ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/lwipopts.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/lwipopts.h new file mode 100644 index 00000000..3e12c25e --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/lwipopts.h @@ -0,0 +1,2167 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2001-2004 Swedish Institute of Computer Science, All Rights Reserved +// See LICENSE file in the project root for full license information. +// +/** + * @file + * + * lwIP Options Configuration + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIPOPT_H__ +#define __LWIPOPT_H__ + + +#define _REENT_ONLY +#define set_errno(err) +#include +#include +#include + +/* + ----------------------------------------------- + ---------- Platform specific locking ---------- + ----------------------------------------------- +*/ + +/** + * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain + * critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#ifndef SYS_LIGHTWEIGHT_PROT +#define SYS_LIGHTWEIGHT_PROT 1 +#endif + +/** + * NO_SYS==1: Provides VERY minimal functionality. Otherwise, + * use lwIP facilities. + */ +#ifndef NO_SYS +#define NO_SYS 0 +#endif + +/** + * NO_SYS_NO_TIMERS==1: Drop support for sys_timeout when NO_SYS==1 + * Mainly for compatibility to old versions. + */ +#ifndef NO_SYS_NO_TIMERS +#define NO_SYS_NO_TIMERS 0 +#endif + +// empty on purpose +#define LWIP_TCPIP_THREAD_ALIVE() + +/** + * MEMCPY: override this if you have a faster implementation at hand than the + * one included in your C library + */ +#ifndef MEMCPY +#define MEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/** + * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a + * call to memcpy() if the length is known at compile time and is small. + */ +#ifndef SMEMCPY +#define SMEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/* + ------------------------------------ + ---------- Memory options ---------- + ------------------------------------ +*/ +/** + * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library + * instead of the lwip internal allocator. Can save code size if you + * already use it. + */ +#ifndef MEM_LIBC_MALLOC +#define MEM_LIBC_MALLOC 1 +#endif + +/** +* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator. +* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution +* speed and usage from interrupts! +*/ +#ifndef MEMP_MEM_MALLOC +#define MEMP_MEM_MALLOC 1 +#endif + +/** + * MEM_ALIGNMENT: should be set to the alignment of the CPU + * 4 byte alignment -> #define MEM_ALIGNMENT 4 + * 2 byte alignment -> #define MEM_ALIGNMENT 2 + */ +#ifndef MEM_ALIGNMENT +#define MEM_ALIGNMENT 4 +#endif + +/** + * MEM_SIZE: the size of the heap memory. If the application will send + * a lot of data that needs to be copied, this should be set high. + */ +#ifndef MEM_SIZE +#define MEM_SIZE (16 * 1024) +#endif + +/** + * MEMP_SEPARATE_POOLS: if defined to 1, each pool is placed in its own array. + * This can be used to individually change the location of each pool. + * Default is one big array for all pools + */ +#ifndef MEMP_SEPARATE_POOLS +#define MEMP_SEPARATE_POOLS 0 +#endif + +/** + * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable + * amount of bytes before and after each memp element in every pool and fills + * it with a prominent default value. + * MEMP_OVERFLOW_CHECK == 0 no checking + * MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed + * MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time + * memp_malloc() or memp_free() is called (useful but slow!) + */ +#ifndef MEMP_OVERFLOW_CHECK +#define MEMP_OVERFLOW_CHECK 0 +#endif + +/** + * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make + * sure that there are no cycles in the linked lists. + */ +#ifndef MEMP_SANITY_CHECK +#define MEMP_SANITY_CHECK 0 +#endif + +/** + * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set + * of memory pools of various sizes. When mem_malloc is called, an element of + * the smallest pool that can provide the length needed is returned. + * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled. + */ +#ifndef MEM_USE_POOLS +#define MEM_USE_POOLS 0 +#endif + +/** + * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next + * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more + * reliable. */ +#ifndef MEM_USE_POOLS_TRY_BIGGER_POOL +#define MEM_USE_POOLS_TRY_BIGGER_POOL 0 +#endif + +/** + * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h + * that defines additional pools beyond the "standard" ones required + * by lwIP. If you set this to 1, you must have lwippools.h in your + * inlude path somewhere. + */ +#ifndef MEMP_USE_CUSTOM_POOLS +#define MEMP_USE_CUSTOM_POOLS 0 +#endif + +/** + * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from + * interrupt context (or another context that doesn't allow waiting for a + * semaphore). + * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT, + * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs + * with each loop so that mem_free can run. + * + * ATTENTION: As you can see from the above description, this leads to dis-/ + * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc + * can need longer. + * + * If you don't want that, at least for NO_SYS=0, you can still use the following + * functions to enqueue a deallocation call which then runs in the tcpip_thread + * context: + * - pbuf_free_callback(p); + * - mem_free_callback(m); + */ +#ifndef LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT +#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0 +#endif + +/* + --------------------------------------- + ---------- IPv6 options --------------- + --------------------------------------- +*/ +/** + * LWIP_IPV6==1: Enable IPv6 + */ +#define LWIP_IPV6 0 + +/* + ------------------------------------------------ + ---------- Internal Memory Pool Sizes ---------- + ------------------------------------------------ +*/ +/** + * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF). + * If the application sends a lot of data out of ROM (or other static memory), + * this should be set high. + */ +#ifndef MEMP_NUM_PBUF +#define MEMP_NUM_PBUF 16 +#endif + +/** + * MEMP_NUM_RAW_PCB: Number of raw connection PCBs + * (requires the LWIP_RAW option) + */ +#ifndef MEMP_NUM_RAW_PCB +#define MEMP_NUM_RAW_PCB 4 +#endif + +/** + * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + * per active UDP "connection". + * (requires the LWIP_UDP option) + */ +#ifndef MEMP_NUM_UDP_PCB +#define MEMP_NUM_UDP_PCB 4 +#endif + +/** + * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB +#define MEMP_NUM_TCP_PCB 5 +#endif + +/** + * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB_LISTEN +#define MEMP_NUM_TCP_PCB_LISTEN 8 +#endif + +/** + * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_SEG +#define MEMP_NUM_TCP_SEG 16 +#endif + +/** + * MEMP_NUM_REASSDATA: the number of IP packets simultaneously queued for + * reassembly (whole packets, not fragments!) + */ +#ifndef MEMP_NUM_REASSDATA +#define MEMP_NUM_REASSDATA 5 +#endif + +/** + * MEMP_NUM_FRAG_PBUF: the number of IP fragments simultaneously sent + * (fragments, not whole packets!). + * This is only used with IP_FRAG_USES_STATIC_BUF==0 and + * LWIP_NETIF_TX_SINGLE_PBUF==0 and only has to be > 1 with DMA-enabled MACs + * where the packet is not yet sent when netif->output returns. + */ +#ifndef MEMP_NUM_FRAG_PBUF +#define MEMP_NUM_FRAG_PBUF 15 +#endif + +/** + * MEMP_NUM_ARP_QUEUE: the number of simulateously queued outgoing + * packets (pbufs) that are waiting for an ARP request (to resolve + * their destination address) to finish. + * (requires the ARP_QUEUEING option) + */ +#ifndef MEMP_NUM_ARP_QUEUE +#define MEMP_NUM_ARP_QUEUE 15 +#endif + +/** + * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces + * can be members et the same time (one per netif - allsystems group -, plus one + * per netif membership). + * (requires the LWIP_IGMP option) + */ +#ifndef MEMP_NUM_IGMP_GROUP +#define MEMP_NUM_IGMP_GROUP 8 +#endif + +/** + * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts. + * (requires NO_SYS==0) + * The default number of timeouts is calculated here for all enabled modules. + * The formula expects settings to be either '0' or '1'. + */ +#ifndef MEMP_NUM_SYS_TIMEOUT +#define MEMP_NUM_SYS_TIMEOUT (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + PPP_SUPPORT + (LWIP_IPV6 ? (1 + LWIP_IPV6_REASS + LWIP_IPV6_MLD) : 0)) +#endif + +/** + * MEMP_NUM_NETBUF: the number of struct netbufs. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETBUF +#define MEMP_NUM_NETBUF 2 +#endif + +/** + * MEMP_NUM_NETCONN: the number of struct netconns. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETCONN +#define MEMP_NUM_NETCONN 4 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used + * for callback/timeout API communication. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_API +#define MEMP_NUM_TCPIP_MSG_API 8 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used + * for incoming packets. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_INPKT +#define MEMP_NUM_TCPIP_MSG_INPKT 8 +#endif + +/** + * MEMP_NUM_SNMP_NODE: the number of leafs in the SNMP tree. + */ +#ifndef MEMP_NUM_SNMP_NODE +#define MEMP_NUM_SNMP_NODE 50 +#endif + +/** + * MEMP_NUM_SNMP_ROOTNODE: the number of branches in the SNMP tree. + * Every branch has one leaf (MEMP_NUM_SNMP_NODE) at least! + */ +#ifndef MEMP_NUM_SNMP_ROOTNODE +#define MEMP_NUM_SNMP_ROOTNODE 30 +#endif + +/** + * MEMP_NUM_SNMP_VARBIND: the number of concurrent requests (does not have to + * be changed normally) - 2 of these are used per request (1 for input, + * 1 for output) + */ +#ifndef MEMP_NUM_SNMP_VARBIND +#define MEMP_NUM_SNMP_VARBIND 2 +#endif + +/** + * MEMP_NUM_SNMP_VALUE: the number of OID or values concurrently used + * (does not have to be changed normally) - 3 of these are used per request + * (1 for the value read and 2 for OIDs - input and output) + */ +#ifndef MEMP_NUM_SNMP_VALUE +#define MEMP_NUM_SNMP_VALUE 3 +#endif + +/** + * MEMP_NUM_NETDB: the number of concurrently running lwip_addrinfo() calls + * (before freeing the corresponding memory using lwip_freeaddrinfo()). + */ +#ifndef MEMP_NUM_NETDB +#define MEMP_NUM_NETDB 1 +#endif + +/** + * MEMP_NUM_LOCALHOSTLIST: the number of host entries in the local host list + * if DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1. + */ +#ifndef MEMP_NUM_LOCALHOSTLIST +#define MEMP_NUM_LOCALHOSTLIST 1 +#endif + +/** + * MEMP_NUM_PPPOE_INTERFACES: the number of concurrently active PPPoE + * interfaces (only used with PPPOE_SUPPORT==1) + */ +#ifndef MEMP_NUM_PPPOE_INTERFACES +#define MEMP_NUM_PPPOE_INTERFACES 1 +#endif + +/** + * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. + */ +#ifndef PBUF_POOL_SIZE +#define PBUF_POOL_SIZE 16 +#endif + +/* + --------------------------------- + ---------- ARP options ---------- + --------------------------------- +*/ +/** + * LWIP_ARP==1: Enable ARP functionality. + */ +#ifndef LWIP_ARP +#define LWIP_ARP 1 +#endif + +/** + * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached. + */ +#ifndef ARP_TABLE_SIZE +#define ARP_TABLE_SIZE 10 +#endif + +/** + * ARP_QUEUEING==1: Multiple outgoing packets are queued during hardware address + * resolution. By default, only the most recent packet is queued per IP address. + * This is sufficient for most protocols and mainly reduces TCP connection + * startup time. Set this to 1 if you know your application sends more than one + * packet in a row to an IP address that is not in the ARP cache. + */ +#ifndef ARP_QUEUEING +#define ARP_QUEUEING 0 +#endif + +/** + * ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be + * updated with the source MAC and IP addresses supplied in the packet. + * You may want to disable this if you do not trust LAN peers to have the + * correct addresses, or as a limited approach to attempt to handle + * spoofing. If disabled, lwIP will need to make a new ARP request if + * the peer is not already in the ARP table, adding a little latency. + * The peer *is* in the ARP table if it requested our address before. + * Also notice that this slows down input processing of every IP packet! + */ +#ifndef ETHARP_TRUST_IP_MAC +#define ETHARP_TRUST_IP_MAC 0 +#endif + +/** + * ETHARP_SUPPORT_VLAN==1: support receiving ethernet packets with VLAN header. + * Additionally, you can define ETHARP_VLAN_CHECK to an u16_t VLAN ID to check. + * If ETHARP_VLAN_CHECK is defined, only VLAN-traffic for this VLAN is accepted. + * If ETHARP_VLAN_CHECK is not defined, all traffic is accepted. + * Alternatively, define a function/define ETHARP_VLAN_CHECK_FN(eth_hdr, vlan) + * that returns 1 to accept a packet or 0 to drop a packet. + */ +#ifndef ETHARP_SUPPORT_VLAN +#define ETHARP_SUPPORT_VLAN 0 +#endif + +/** LWIP_ETHERNET==1: enable ethernet support for PPPoE even though ARP + * might be disabled + */ +#ifndef LWIP_ETHERNET +#define LWIP_ETHERNET (LWIP_ARP || PPPOE_SUPPORT) +#endif + +/** ETH_PAD_SIZE: number of bytes added before the ethernet header to ensure + * alignment of payload after that header. Since the header is 14 bytes long, + * without this padding e.g. addresses in the IP header will not be aligned + * on a 32-bit boundary, so setting this to 2 can speed up 32-bit-platforms. + */ +#ifndef ETH_PAD_SIZE +#define ETH_PAD_SIZE 0 +#endif + +/** ETHARP_SUPPORT_STATIC_ENTRIES==1: enable code to support static ARP table + * entries (using etharp_add_static_entry/etharp_remove_static_entry). + */ +#ifndef ETHARP_SUPPORT_STATIC_ENTRIES +#define ETHARP_SUPPORT_STATIC_ENTRIES 0 +#endif + +/* + -------------------------------- + ---------- IP options ---------- + -------------------------------- +*/ +/** + * IP_FORWARD==1: Enables the ability to forward IP packets across network + * interfaces. If you are going to run lwIP on a device with only one network + * interface, define this to 0. + */ +#ifndef IP_FORWARD +#define IP_FORWARD 0 +#endif + +/** + * IP_OPTIONS_ALLOWED: Defines the behavior for IP options. + * IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped. + * IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed). + */ +#ifndef IP_OPTIONS_ALLOWED +#define IP_OPTIONS_ALLOWED 1 +#endif + +/** + * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that + * this option does not affect outgoing packet sizes, which can be controlled + * via IP_FRAG. + */ +#ifndef IP_REASSEMBLY +#define IP_REASSEMBLY 1 +#endif + +/** + * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note + * that this option does not affect incoming packet sizes, which can be + * controlled via IP_REASSEMBLY. + */ +#ifndef IP_FRAG +#define IP_FRAG 1 +#endif + +/** + * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally) + * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived + * in this time, the whole packet is discarded. + */ +#ifndef IP_REASS_MAXAGE +#define IP_REASS_MAXAGE 3 +#endif + +/** + * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled. + * Since the received pbufs are enqueued, be sure to configure + * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive + * packets even if the maximum amount of fragments is enqueued for reassembly! + */ +#ifndef IP_REASS_MAX_PBUFS +#define IP_REASS_MAX_PBUFS 10 +#endif + +/** + * IP_FRAG_USES_STATIC_BUF==1: Use a static MTU-sized buffer for IP + * fragmentation. Otherwise pbufs are allocated and reference the original + * packet data to be fragmented (or with LWIP_NETIF_TX_SINGLE_PBUF==1, + * new PBUF_RAM pbufs are used for fragments). + * ATTENTION: IP_FRAG_USES_STATIC_BUF==1 may not be used for DMA-enabled MACs! + */ +#ifndef IP_FRAG_USES_STATIC_BUF +#define IP_FRAG_USES_STATIC_BUF 0 +#endif + +/** + * IP_FRAG_MAX_MTU: Assumed max MTU on any interface for IP frag buffer + * (requires IP_FRAG_USES_STATIC_BUF==1) + */ +#if IP_FRAG_USES_STATIC_BUF && !defined(IP_FRAG_MAX_MTU) +#define IP_FRAG_MAX_MTU 1500 +#endif + +/** + * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers. + */ +#ifndef IP_DEFAULT_TTL +#define IP_DEFAULT_TTL 255 +#endif + +/** + * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast + * filter per pcb on udp and raw send operations. To enable broadcast filter + * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1. + */ +#ifndef IP_SOF_BROADCAST +#define IP_SOF_BROADCAST 0 +#endif + +/** + * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast + * filter on recv operations. + */ +#ifndef IP_SOF_BROADCAST_RECV +#define IP_SOF_BROADCAST_RECV 0 +#endif + +/** + * IP_FORWARD_ALLOW_TX_ON_RX_NETIF==1: allow ip_forward() to send packets back + * out on the netif where it was received. This should only be used for + * wireless networks. + * ATTENTION: When this is 1, make sure your netif driver correctly marks incoming + * link-layer-broadcast/multicast packets as such using the corresponding pbuf flags! + */ +#ifndef IP_FORWARD_ALLOW_TX_ON_RX_NETIF +#define IP_FORWARD_ALLOW_TX_ON_RX_NETIF 0 +#endif + +/** + * LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS==1: randomize the local port for the first + * local TCP/UDP pcb (default==0). This can prevent creating predictable port + * numbers after booting a device. + */ +#ifndef LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS +#define LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS 1 +#endif + +#define LWIP_RAND rand + +/* + ---------------------------------- + ---------- ICMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_ICMP==1: Enable ICMP module inside the IP stack. + * Be careful, disable that make your product non-compliant to RFC1122 + */ +#ifndef LWIP_ICMP +#define LWIP_ICMP 1 +#endif + +/** + * ICMP_TTL: Default value for Time-To-Live used by ICMP packets. + */ +#ifndef ICMP_TTL +#define ICMP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only) + */ +#ifndef LWIP_BROADCAST_PING +#define LWIP_BROADCAST_PING 0 +#endif + +/** + * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only) + */ +#ifndef LWIP_MULTICAST_PING +#define LWIP_MULTICAST_PING 0 +#endif + +/* + --------------------------------- + ---------- RAW options ---------- + --------------------------------- +*/ +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef LWIP_RAW +#define LWIP_RAW 1 +#endif + +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef RAW_TTL +#define RAW_TTL (IP_DEFAULT_TTL) +#endif + +/* + ---------------------------------- + ---------- DHCP options ---------- + ---------------------------------- +*/ +/** + * LWIP_DHCP==1: Enable DHCP module. + */ +#ifndef LWIP_DHCP +#define LWIP_DHCP 1 +#endif + +/** + * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address. + */ +#ifndef DHCP_DOES_ARP_CHECK +#define DHCP_DOES_ARP_CHECK ((LWIP_DHCP) && (LWIP_ARP)) +#endif + +#define LWIP_DHCP_CHECK_LINK_UP 1 + +/* + ------------------------------------ + ---------- AUTOIP options ---------- + ------------------------------------ +*/ +/** + * LWIP_AUTOIP==1: Enable AUTOIP module. + */ +#ifndef LWIP_AUTOIP +#define LWIP_AUTOIP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on + * the same interface at the same time. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP +#define LWIP_DHCP_AUTOIP_COOP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes + * that should be sent before falling back on AUTOIP. This can be set + * as low as 1 to get an AutoIP address very quickly, but you should + * be prepared to handle a changing IP address when DHCP overrides + * AutoIP. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP_TRIES +#define LWIP_DHCP_AUTOIP_COOP_TRIES 9 +#endif + +/* + ---------------------------------- + ---------- SNMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_SNMP==1: Turn on SNMP module. UDP must be available for SNMP + * transport. + */ +#ifndef LWIP_SNMP +#define LWIP_SNMP 0 +#endif + +/** + * SNMP_CONCURRENT_REQUESTS: Number of concurrent requests the module will + * allow. At least one request buffer is required. + * Does not have to be changed unless external MIBs answer request asynchronously + */ +#ifndef SNMP_CONCURRENT_REQUESTS +#define SNMP_CONCURRENT_REQUESTS 1 +#endif + +/** + * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap + * destination is required + */ +#ifndef SNMP_TRAP_DESTINATIONS +#define SNMP_TRAP_DESTINATIONS 1 +#endif + +/** + * SNMP_PRIVATE_MIB: + * When using a private MIB, you have to create a file 'private_mib.h' that contains + * a 'struct mib_array_node mib_private' which contains your MIB. + */ +#ifndef SNMP_PRIVATE_MIB +#define SNMP_PRIVATE_MIB 0 +#endif + +/** + * Only allow SNMP write actions that are 'safe' (e.g. disabeling netifs is not + * a safe action and disabled when SNMP_SAFE_REQUESTS = 1). + * Unsafe requests are disabled by default! + */ +#ifndef SNMP_SAFE_REQUESTS +#define SNMP_SAFE_REQUESTS 1 +#endif + +/** + * The maximum length of strings used. This affects the size of + * MEMP_SNMP_VALUE elements. + */ +#ifndef SNMP_MAX_OCTET_STRING_LEN +#define SNMP_MAX_OCTET_STRING_LEN 127 +#endif + +/** + * The maximum depth of the SNMP tree. + * With private MIBs enabled, this depends on your MIB! + * This affects the size of MEMP_SNMP_VALUE elements. + */ +#ifndef SNMP_MAX_TREE_DEPTH +#define SNMP_MAX_TREE_DEPTH 15 +#endif + +/** + * The size of the MEMP_SNMP_VALUE elements, normally calculated from + * SNMP_MAX_OCTET_STRING_LEN and SNMP_MAX_TREE_DEPTH. + */ +#ifndef SNMP_MAX_VALUE_SIZE +#define SNMP_MAX_VALUE_SIZE LWIP_MAX((SNMP_MAX_OCTET_STRING_LEN)+1, sizeof(s32_t)*(SNMP_MAX_TREE_DEPTH)) +#endif + +/* + ---------------------------------- + ---------- IGMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_IGMP==1: Turn on IGMP module. + */ +#ifndef LWIP_IGMP +#define LWIP_IGMP 0 +#endif + +/* + ---------------------------------- + ---------- DNS options ----------- + ---------------------------------- +*/ +/** + * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS + * transport. + */ +#ifndef LWIP_DNS +#define LWIP_DNS 1 +#endif + +/** DNS maximum number of entries to maintain locally. */ +#ifndef DNS_TABLE_SIZE +#define DNS_TABLE_SIZE 4 +#endif + +/** DNS maximum host name length supported in the name table. */ +#ifndef DNS_MAX_NAME_LENGTH +#define DNS_MAX_NAME_LENGTH 256 +#endif + +/** The maximum of DNS servers */ +#ifndef DNS_MAX_SERVERS +#define DNS_MAX_SERVERS 2 +#endif + +/** DNS do a name checking between the query and the response. */ +#ifndef DNS_DOES_NAME_CHECK +#define DNS_DOES_NAME_CHECK 1 +#endif + +/** DNS message max. size. Default value is RFC compliant. */ +#ifndef DNS_MSG_SIZE +#define DNS_MSG_SIZE 512 +#endif + +/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled, + * you have to define + * #define DNS_LOCAL_HOSTLIST_INIT {{"host1", 0x123}, {"host2", 0x234}} + * (an array of structs name/address, where address is an u32_t in network + * byte order). + * + * Instead, you can also use an external function: + * #define DNS_LOOKUP_LOCAL_EXTERN(x) extern u32_t my_lookup_function(const char *name) + * that returns the IP address or INADDR_NONE if not found. + */ +#ifndef DNS_LOCAL_HOSTLIST +#define DNS_LOCAL_HOSTLIST 0 +#endif /* DNS_LOCAL_HOSTLIST */ + +/** If this is turned on, the local host-list can be dynamically changed + * at runtime. */ +#ifndef DNS_LOCAL_HOSTLIST_IS_DYNAMIC +#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC 0 +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + +/* + --------------------------------- + ---------- UDP options ---------- + --------------------------------- +*/ +/** + * LWIP_UDP==1: Turn on UDP. + */ +#ifndef LWIP_UDP +#define LWIP_UDP 1 +#endif + +/** + * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP) + */ +#ifndef LWIP_UDPLITE +#define LWIP_UDPLITE 0 +#endif + +/** + * UDP_TTL: Default Time-To-Live value. + */ +#ifndef UDP_TTL +#define UDP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * LWIP_NETBUF_RECVINFO==1: append destination addr and port to every netbuf. + */ +#ifndef LWIP_NETBUF_RECVINFO +#define LWIP_NETBUF_RECVINFO 0 +#endif + +/* + --------------------------------- + ---------- TCP options ---------- + --------------------------------- +*/ +/** + * LWIP_TCP==1: Turn on TCP. + */ +#ifndef LWIP_TCP +#define LWIP_TCP 1 +#endif + +/** + * TCP_TTL: Default Time-To-Live value. + */ +#ifndef TCP_TTL +#define TCP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * TCP_WND: The size of a TCP window. This must be at least + * (2 * TCP_MSS) for things to work well + */ +#ifndef TCP_WND +#define TCP_WND (4 * TCP_MSS) +#endif + +/** + * TCP_MAXRTX: Maximum number of retransmissions of data segments. + */ +#ifndef TCP_MAXRTX +#define TCP_MAXRTX 12 +#endif + +/** + * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments. + */ +#ifndef TCP_SYNMAXRTX +#define TCP_SYNMAXRTX 6 +#endif + +/** + * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order. + * Define to 0 if your device is low on memory. + */ +#ifndef TCP_QUEUE_OOSEQ +#define TCP_QUEUE_OOSEQ (LWIP_TCP) +#endif + +/** + * TCP_MSS: TCP Maximum segment size. (default is 536, a conservative default, + * you might want to increase this.) + * For the receive side, this MSS is advertised to the remote side + * when opening a connection. For the transmit size, this MSS sets + * an upper limit on the MSS advertised by the remote host. + */ +#ifndef TCP_MSS +#define TCP_MSS 1480 +#endif + +/** + * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really + * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which + * reflects the available reassembly buffer size at the remote host) and the + * largest size permitted by the IP layer" (RFC 1122) + * Setting this to 1 enables code that checks TCP_MSS against the MTU of the + * netif used for a connection and limits the MSS if it would be too big otherwise. + */ +#ifndef TCP_CALCULATE_EFF_SEND_MSS +#define TCP_CALCULATE_EFF_SEND_MSS 1 +#endif + + +/** + * TCP_SND_BUF: TCP sender buffer space (bytes). + * To achieve good performance, this should be at least 2 * TCP_MSS. + */ +#ifndef TCP_SND_BUF +#define TCP_SND_BUF (2 * TCP_MSS) +#endif + +/** + * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least + * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. + */ +#ifndef TCP_SND_QUEUELEN +#define TCP_SND_QUEUELEN ((4 * (TCP_SND_BUF) + (TCP_MSS - 1))/(TCP_MSS)) +#endif + +/** + * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than + * TCP_SND_BUF. It is the amount of space which must be available in the + * TCP snd_buf for select to return writable (combined with TCP_SNDQUEUELOWAT). + */ +#ifndef TCP_SNDLOWAT +#define TCP_SNDLOWAT LWIP_MIN(LWIP_MAX(((TCP_SND_BUF)/2), (2 * TCP_MSS) + 1), (TCP_SND_BUF) - 1) +#endif + +/** + * TCP_SNDQUEUELOWAT: TCP writable bufs (pbuf count). This must be less + * than TCP_SND_QUEUELEN. If the number of pbufs queued on a pcb drops below + * this number, select returns writable (combined with TCP_SNDLOWAT). + */ +#ifndef TCP_SNDQUEUELOWAT +#define TCP_SNDQUEUELOWAT LWIP_MAX(((TCP_SND_QUEUELEN)/2), 5) +#endif + +/** + * TCP_OOSEQ_MAX_BYTES: The maximum number of bytes queued on ooseq per pcb. + * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==0. + */ +#ifndef TCP_OOSEQ_MAX_BYTES +#define TCP_OOSEQ_MAX_BYTES 0 +#endif + +/** + * TCP_OOSEQ_MAX_PBUFS: The maximum number of pbufs queued on ooseq per pcb. + * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==0. + */ +#ifndef TCP_OOSEQ_MAX_PBUFS +#define TCP_OOSEQ_MAX_PBUFS 0 +#endif + +/** + * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb. + */ +#ifndef TCP_LISTEN_BACKLOG +#define TCP_LISTEN_BACKLOG 1 +#endif + +/** + * The maximum allowed backlog for TCP listen netconns. + * This backlog is used unless another is explicitly specified. + * 0xff is the maximum (u8_t). + */ +#ifndef TCP_DEFAULT_LISTEN_BACKLOG +#define TCP_DEFAULT_LISTEN_BACKLOG 0xff +#endif + +/** + * TCP_OVERSIZE: The maximum number of bytes that tcp_write may + * allocate ahead of time in an attempt to create shorter pbuf chains + * for transmission. The meaningful range is 0 to TCP_MSS. Some + * suggested values are: + * + * 0: Disable oversized allocation. Each tcp_write() allocates a new + pbuf (old behaviour). + * 1: Allocate size-aligned pbufs with minimal excess. Use this if your + * scatter-gather DMA requires aligned fragments. + * 128: Limit the pbuf/memory overhead to 20%. + * TCP_MSS: Try to create unfragmented TCP packets. + * TCP_MSS/4: Try to create 4 fragments or less per TCP packet. + */ +#ifndef TCP_OVERSIZE +#define TCP_OVERSIZE TCP_MSS +#endif + +/** + * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option. + */ +#ifndef LWIP_TCP_TIMESTAMPS +#define LWIP_TCP_TIMESTAMPS 0 +#endif + +/** + * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an + * explicit window update + */ +#ifndef TCP_WND_UPDATE_THRESHOLD +#define TCP_WND_UPDATE_THRESHOLD (TCP_WND / 4) +#endif + +/** + * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1. + * LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all + * events (accept, sent, etc) that happen in the system. + * LWIP_CALLBACK_API==1: The PCB callback function is called directly + * for the event. This is the default. + */ +#if !defined(LWIP_EVENT_API) && !defined(LWIP_CALLBACK_API) +#define LWIP_EVENT_API 0 +#define LWIP_CALLBACK_API 1 +#endif + + +/* + ---------------------------------- + ---------- Pbuf options ---------- + ---------------------------------- +*/ +/** + * PBUF_LINK_HLEN: the number of bytes that should be allocated for a + * link level header. The default is 14, the standard value for + * Ethernet. + */ +#ifndef PBUF_LINK_HLEN +#define PBUF_LINK_HLEN (14 + ETH_PAD_SIZE) +#endif + +/** + * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is + * designed to accomodate single full size TCP frame in one pbuf, including + * TCP_MSS, IP header, and link header. + */ +#ifndef PBUF_POOL_BUFSIZE +#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_HLEN) +#endif + +/* + ------------------------------------------------ + ---------- Network Interfaces options ---------- + ------------------------------------------------ +*/ +/** + * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname + * field. + */ +#ifndef LWIP_NETIF_HOSTNAME +#define LWIP_NETIF_HOSTNAME 1 +#endif + +/** + * LWIP_NETIF_API==1: Support netif api (in netifapi.c) + */ +#ifndef LWIP_NETIF_API +#define LWIP_NETIF_API 0 +#endif + +/** + * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface + * changes its up/down status (i.e., due to DHCP IP acquistion) + */ +#ifndef LWIP_NETIF_STATUS_CALLBACK +#define LWIP_NETIF_STATUS_CALLBACK 1 +#endif + +/** + * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface + * whenever the link changes (i.e., link down) + */ +#ifndef LWIP_NETIF_LINK_CALLBACK +#define LWIP_NETIF_LINK_CALLBACK 1 +#endif + +/** + * LWIP_NETIF_REMOVE_CALLBACK==1: Support a callback function that is called + * when a netif has been removed + */ +#ifndef LWIP_NETIF_REMOVE_CALLBACK +#define LWIP_NETIF_REMOVE_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table + * indices) in struct netif. TCP and UDP can make use of this to prevent + * scanning the ARP table for every sent packet. While this is faster for big + * ARP tables or many concurrent connections, it might be counterproductive + * if you have a tiny ARP table or if there never are concurrent connections. + */ +#ifndef LWIP_NETIF_HWADDRHINT +#define LWIP_NETIF_HWADDRHINT 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP + * address equal to the netif IP address, looping them back up the stack. + */ +#ifndef LWIP_NETIF_LOOPBACK +#define LWIP_NETIF_LOOPBACK 0 +#endif + +/** + * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback + * sending for each netif (0 = disabled) + */ +#ifndef LWIP_LOOPBACK_MAX_PBUFS +#define LWIP_LOOPBACK_MAX_PBUFS 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in + * the system, as netifs must change how they behave depending on this setting + * for the LWIP_NETIF_LOOPBACK option to work. + * Setting this is needed to avoid reentering non-reentrant functions like + * tcp_input(). + * LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a + * multithreaded environment like tcpip.c. In this case, netif->input() + * is called directly. + * LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup. + * The packets are put on a list and netif_poll() must be called in + * the main application loop. + */ +#ifndef LWIP_NETIF_LOOPBACK_MULTITHREADING +#define LWIP_NETIF_LOOPBACK_MULTITHREADING (!NO_SYS) +#endif + +/** + * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data + * to be sent into one single pbuf. This is for compatibility with DMA-enabled + * MACs that do not support scatter-gather. + * Beware that this might involve CPU-memcpy before transmitting that would not + * be needed without this flag! Use this only if you need to! + * + * @todo: TCP and IP-frag do not work with this, yet: + */ +#ifndef LWIP_NETIF_TX_SINGLE_PBUF +#define LWIP_NETIF_TX_SINGLE_PBUF 0 +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + +/* + ------------------------------------ + ---------- LOOPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1) and loopif.c + */ +#ifndef LWIP_HAVE_LOOPIF +#define LWIP_HAVE_LOOPIF 0 +#endif + +/* + ------------------------------------ + ---------- SLIPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_SLIPIF==1: Support slip interface and slipif.c + */ +#ifndef LWIP_HAVE_SLIPIF +#define LWIP_HAVE_SLIPIF 0 +#endif + +/* + ------------------------------------ + ---------- Thread options ---------- + ------------------------------------ +*/ +/** + * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread. + */ +#ifndef TCPIP_THREAD_NAME +#define TCPIP_THREAD_NAME "tcpip_thread" +#endif + +/** + * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_STACKSIZE +#define TCPIP_THREAD_STACKSIZE 1024 +#endif + +/** + * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_PRIO +#define TCPIP_THREAD_PRIO (NORMALPRIO) +#endif + +/** + * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when tcpip_init is called. + */ +#ifndef TCPIP_MBOX_SIZE +#define TCPIP_MBOX_SIZE MEMP_NUM_PBUF +#endif + +/** + * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread. + */ +#ifndef SLIPIF_THREAD_NAME +#define SLIPIF_THREAD_NAME "slipif_loop" +#endif + +/** + * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_STACKSIZE +#define SLIPIF_THREAD_STACKSIZE 1024 +#endif + +/** + * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_PRIO +#define SLIPIF_THREAD_PRIO (NORMALPRIO) +#endif + +/** + * PPP_THREAD_NAME: The name assigned to the pppInputThread. + */ +#ifndef PPP_THREAD_NAME +#define PPP_THREAD_NAME "pppInputThread" +#endif + +/** + * PPP_THREAD_STACKSIZE: The stack size used by the pppInputThread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_STACKSIZE +#define PPP_THREAD_STACKSIZE 1024 +#endif + +/** + * PPP_THREAD_PRIO: The priority assigned to the pppInputThread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_PRIO +#define PPP_THREAD_PRIO (NORMALPRIO) +#endif + +/** + * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread. + */ +#ifndef DEFAULT_THREAD_NAME +#define DEFAULT_THREAD_NAME "lwIP" +#endif + +/** + * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_STACKSIZE +#define DEFAULT_THREAD_STACKSIZE 1024 +#endif + +/** + * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_PRIO +#define DEFAULT_THREAD_PRIO (NORMALPRIO) +#endif + +/** + * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_RAW_RECVMBOX_SIZE +#define DEFAULT_RAW_RECVMBOX_SIZE 4 +#endif + +/** + * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_UDP_RECVMBOX_SIZE +#define DEFAULT_UDP_RECVMBOX_SIZE 4 +#endif + +/** + * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_TCP_RECVMBOX_SIZE +#define DEFAULT_TCP_RECVMBOX_SIZE 40 +#endif + +/** + * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections. + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when the acceptmbox is created. + */ +#ifndef DEFAULT_ACCEPTMBOX_SIZE +#define DEFAULT_ACCEPTMBOX_SIZE 4 +#endif + +/* + ---------------------------------------------- + ---------- Sequential layer options ---------- + ---------------------------------------------- +*/ +/** + * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!) + * Don't use it if you're not an active lwIP project member + */ +#ifndef LWIP_TCPIP_CORE_LOCKING +#define LWIP_TCPIP_CORE_LOCKING 0 +#endif + +/** + * LWIP_TCPIP_CORE_LOCKING_INPUT: (EXPERIMENTAL!) + * Don't use it if you're not an active lwIP project member + */ +#ifndef LWIP_TCPIP_CORE_LOCKING_INPUT +#define LWIP_TCPIP_CORE_LOCKING_INPUT 0 +#endif + +/** + * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c) + */ +#ifndef LWIP_NETCONN +#define LWIP_NETCONN 1 +#endif + +/** LWIP_TCPIP_TIMEOUT==1: Enable tcpip_timeout/tcpip_untimeout tod create + * timers running in tcpip_thread from another thread. + */ +#ifndef LWIP_TCPIP_TIMEOUT +#define LWIP_TCPIP_TIMEOUT 1 +#endif + +/* + ------------------------------------ + ---------- Socket options ---------- + ------------------------------------ +*/ +/** + * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) + */ +#ifndef LWIP_SOCKET +#define LWIP_SOCKET 1 +#endif + +/** + * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names. + * (only used if you use sockets.c) + */ +#ifndef LWIP_COMPAT_SOCKETS +#define LWIP_COMPAT_SOCKETS 1 +#endif + +/** + * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names. + * Disable this option if you use a POSIX operating system that uses the same + * names (read, write & close). (only used if you use sockets.c) + */ +#ifndef LWIP_POSIX_SOCKETS_IO_NAMES +#define LWIP_POSIX_SOCKETS_IO_NAMES 1 +#endif + +/** + * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT + * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set + * in seconds. (does not require sockets.c, and will affect tcp.c) + */ +#ifndef LWIP_TCP_KEEPALIVE +#define LWIP_TCP_KEEPALIVE 0 +#endif + +/** + * LWIP_SO_SNDTIMEO==1: Enable send timeout for sockets/netconns and + * SO_SNDTIMEO processing. + */ +#ifndef LWIP_SO_SNDTIMEO +#define LWIP_SO_SNDTIMEO 1 +#endif + +/** + * LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and + * SO_RCVTIMEO processing. + */ +#ifndef LWIP_SO_RCVTIMEO +#define LWIP_SO_RCVTIMEO 1 +#endif + +/** + * LWIP_SO_LINGER==1: Enable linger option for sockets/netconns + */ +#define LWIP_SO_LINGER 1 + +/** + * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing. + */ +#ifndef LWIP_SO_RCVBUF +#define LWIP_SO_RCVBUF 1 +#endif + +/** + * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize. + */ +#ifndef RECV_BUFSIZE_DEFAULT +#define RECV_BUFSIZE_DEFAULT INT_MAX +#endif + +/** + * SO_REUSE==1: Enable SO_REUSEADDR option. + */ +#ifndef SO_REUSE +#define SO_REUSE 1 +#endif + +/** + * SO_REUSE_RXTOALL==1: Pass a copy of incoming broadcast/multicast packets + * to all local matches if SO_REUSEADDR is turned on. + * WARNING: Adds a memcpy for every packet if passing to more than one pcb! + */ +#ifndef SO_REUSE_RXTOALL +#define SO_REUSE_RXTOALL 1 +#endif + +/* + ---------------------------------------- + ---------- Statistics options ---------- + ---------------------------------------- +*/ +/** + * LWIP_STATS==1: Enable statistics collection in lwip_stats. + */ +#ifndef LWIP_STATS +#define LWIP_STATS 0 +#endif + +#if LWIP_STATS + +/** + * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions. + */ +#ifndef LWIP_STATS_DISPLAY +#define LWIP_STATS_DISPLAY 0 +#endif + +/** + * LINK_STATS==1: Enable link stats. + */ +#ifndef LINK_STATS +#define LINK_STATS 1 +#endif + +/** + * ETHARP_STATS==1: Enable etharp stats. + */ +#ifndef ETHARP_STATS +#define ETHARP_STATS (LWIP_ARP) +#endif + +/** + * IP_STATS==1: Enable IP stats. + */ +#ifndef IP_STATS +#define IP_STATS 1 +#endif + +/** + * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is + * on if using either frag or reass. + */ +#ifndef IPFRAG_STATS +#define IPFRAG_STATS (IP_REASSEMBLY || IP_FRAG) +#endif + +/** + * ICMP_STATS==1: Enable ICMP stats. + */ +#ifndef ICMP_STATS +#define ICMP_STATS 1 +#endif + +/** + * IGMP_STATS==1: Enable IGMP stats. + */ +#ifndef IGMP_STATS +#define IGMP_STATS (LWIP_IGMP) +#endif + +/** + * UDP_STATS==1: Enable UDP stats. Default is on if + * UDP enabled, otherwise off. + */ +#ifndef UDP_STATS +#define UDP_STATS (LWIP_UDP) +#endif + +/** + * TCP_STATS==1: Enable TCP stats. Default is on if TCP + * enabled, otherwise off. + */ +#ifndef TCP_STATS +#define TCP_STATS (LWIP_TCP) +#endif + +/** + * MEM_STATS==1: Enable mem.c stats. + */ +#ifndef MEM_STATS +#define MEM_STATS ((MEM_LIBC_MALLOC == 0) && (MEM_USE_POOLS == 0)) +#endif + +/** + * MEMP_STATS==1: Enable memp.c pool stats. + */ +#ifndef MEMP_STATS +#define MEMP_STATS (MEMP_MEM_MALLOC == 0) +#endif + +/** + * SYS_STATS==1: Enable system stats (sem and mbox counts, etc). + */ +#ifndef SYS_STATS +#define SYS_STATS (NO_SYS == 0) +#endif + +#else + +#define LINK_STATS 0 +#define IP_STATS 0 +#define IPFRAG_STATS 0 +#define ICMP_STATS 0 +#define IGMP_STATS 0 +#define UDP_STATS 0 +#define TCP_STATS 0 +#define MEM_STATS 0 +#define MEMP_STATS 0 +#define SYS_STATS 0 +#define LWIP_STATS_DISPLAY 0 + +#endif /* LWIP_STATS */ + +/* + --------------------------------- + ---------- PPP options ---------- + --------------------------------- +*/ +/** + * PPP_SUPPORT==1: Enable PPP. + */ +#ifndef PPP_SUPPORT +#define PPP_SUPPORT 0 +#endif + +/** + * PPPOE_SUPPORT==1: Enable PPP Over Ethernet + */ +#ifndef PPPOE_SUPPORT +#define PPPOE_SUPPORT 0 +#endif + +/** + * PPPOS_SUPPORT==1: Enable PPP Over Serial + */ +#ifndef PPPOS_SUPPORT +#define PPPOS_SUPPORT PPP_SUPPORT +#endif + +#if PPP_SUPPORT + +/** + * NUM_PPP: Max PPP sessions. + */ +#ifndef NUM_PPP +#define NUM_PPP 1 +#endif + +/** + * PAP_SUPPORT==1: Support PAP. + */ +#ifndef PAP_SUPPORT +#define PAP_SUPPORT 0 +#endif + +/** + * CHAP_SUPPORT==1: Support CHAP. + */ +#ifndef CHAP_SUPPORT +#define CHAP_SUPPORT 0 +#endif + +/** + * MSCHAP_SUPPORT==1: Support MSCHAP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef MSCHAP_SUPPORT +#define MSCHAP_SUPPORT 0 +#endif + +/** + * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CBCP_SUPPORT +#define CBCP_SUPPORT 0 +#endif + +/** + * CCP_SUPPORT==1: Support CCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CCP_SUPPORT +#define CCP_SUPPORT 0 +#endif + +/** + * VJ_SUPPORT==1: Support VJ header compression. + */ +#ifndef VJ_SUPPORT +#define VJ_SUPPORT 0 +#endif + +/** + * MD5_SUPPORT==1: Support MD5 (see also CHAP). + */ +#ifndef MD5_SUPPORT +#define MD5_SUPPORT 0 +#endif + +/* + * Timeouts + */ +#ifndef FSM_DEFTIMEOUT +#define FSM_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef FSM_DEFMAXTERMREQS +#define FSM_DEFMAXTERMREQS 2 /* Maximum Terminate-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXCONFREQS +#define FSM_DEFMAXCONFREQS 10 /* Maximum Configure-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXNAKLOOPS +#define FSM_DEFMAXNAKLOOPS 5 /* Maximum number of nak loops */ +#endif + +#ifndef UPAP_DEFTIMEOUT +#define UPAP_DEFTIMEOUT 6 /* Timeout (seconds) for retransmitting req */ +#endif + +#ifndef UPAP_DEFREQTIME +#define UPAP_DEFREQTIME 30 /* Time to wait for auth-req from peer */ +#endif + +#ifndef CHAP_DEFTIMEOUT +#define CHAP_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef CHAP_DEFTRANSMITS +#define CHAP_DEFTRANSMITS 10 /* max # times to send challenge */ +#endif + +/* Interval in seconds between keepalive echo requests, 0 to disable. */ +#ifndef LCP_ECHOINTERVAL +#define LCP_ECHOINTERVAL 0 +#endif + +/* Number of unanswered echo requests before failure. */ +#ifndef LCP_MAXECHOFAILS +#define LCP_MAXECHOFAILS 3 +#endif + +/* Max Xmit idle time (in jiffies) before resend flag char. */ +#ifndef PPP_MAXIDLEFLAG +#define PPP_MAXIDLEFLAG 100 +#endif + +/* + * Packet sizes + * + * Note - lcp shouldn't be allowed to negotiate stuff outside these + * limits. See lcp.h in the pppd directory. + * (XXX - these constants should simply be shared by lcp.c instead + * of living in lcp.h) + */ +#define PPP_MTU 1500 /* Default MTU (size of Info field) */ +#ifndef PPP_MAXMTU +/* #define PPP_MAXMTU 65535 - (PPP_HDRLEN + PPP_FCSLEN) */ +#define PPP_MAXMTU 1500 /* Largest MTU we allow */ +#endif +#define PPP_MINMTU 64 +#define PPP_MRU 1500 /* default MRU = max length of info field */ +#define PPP_MAXMRU 1500 /* Largest MRU we allow */ +#ifndef PPP_DEFMRU +#define PPP_DEFMRU 296 /* Try for this */ +#endif +#define PPP_MINMRU 128 /* No MRUs below this */ + +#ifndef MAXNAMELEN +#define MAXNAMELEN 256 /* max length of hostname or name for auth */ +#endif +#ifndef MAXSECRETLEN +#define MAXSECRETLEN 256 /* max length of password or secret */ +#endif + +#endif /* PPP_SUPPORT */ + +/* + -------------------------------------- + ---------- Checksum options ---------- + -------------------------------------- +*/ +/** + * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets. + */ +#ifndef CHECKSUM_GEN_IP +#define CHECKSUM_GEN_IP 1 +#endif + +/** + * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets. + */ +#ifndef CHECKSUM_GEN_UDP +#define CHECKSUM_GEN_UDP 1 +#endif + +/** + * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets. + */ +#ifndef CHECKSUM_GEN_TCP +#define CHECKSUM_GEN_TCP 1 +#endif + +/** + * CHECKSUM_GEN_ICMP==1: Generate checksums in software for outgoing ICMP packets. + */ +#ifndef CHECKSUM_GEN_ICMP +#define CHECKSUM_GEN_ICMP 1 +#endif + +/** + * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets. + */ +#ifndef CHECKSUM_CHECK_IP +#define CHECKSUM_CHECK_IP 1 +#endif + +/** + * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets. + */ +#ifndef CHECKSUM_CHECK_UDP +#define CHECKSUM_CHECK_UDP 1 +#endif + +/** + * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets. + */ +#ifndef CHECKSUM_CHECK_TCP +#define CHECKSUM_CHECK_TCP 1 +#endif + +/** + * LWIP_CHECKSUM_ON_COPY==1: Calculate checksum when copying data from + * application buffers to pbufs. + */ +#ifndef LWIP_CHECKSUM_ON_COPY +#define LWIP_CHECKSUM_ON_COPY 0 +#endif + +/* + --------------------------------------- + ---------- Hook options --------------- + --------------------------------------- +*/ + +/* Hooks are undefined by default, define them to a function if you need them. */ + +/** + * LWIP_HOOK_IP4_INPUT(pbuf, input_netif): + * - called from ip_input() (IPv4) + * - pbuf: received struct pbuf passed to ip_input() + * - input_netif: struct netif on which the packet has been received + * Return values: + * - 0: Hook has not consumed the packet, packet is processed as normal + * - != 0: Hook has consumed the packet. + * If the hook consumed the packet, 'pbuf' is in the responsibility of the hook + * (i.e. free it when done). + */ + +/** + * LWIP_HOOK_IP4_ROUTE(dest): + * - called from ip_route() (IPv4) + * - dest: destination IPv4 address + * Returns the destination netif or NULL if no destination netif is found. In + * that case, ip_route() continues as normal. + */ + +/* + --------------------------------------- + ---------- Debugging options ---------- + --------------------------------------- +*/ +/** + * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is + * compared against this value. If it is smaller, then debugging + * messages are written. + */ +#ifndef LWIP_DBG_MIN_LEVEL +#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_ALL +#endif + +/** + * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable + * debug messages of certain types. + */ +#ifndef LWIP_DBG_TYPES_ON +#define LWIP_DBG_TYPES_ON LWIP_DBG_OFF +#endif + +/** + * ETHARP_DEBUG: Enable debugging in etharp.c. + */ +#ifndef ETHARP_DEBUG +#define ETHARP_DEBUG LWIP_DBG_OFF +#endif + +/** + * NETIF_DEBUG: Enable debugging in netif.c. + */ +#ifndef NETIF_DEBUG +#define NETIF_DEBUG LWIP_DBG_OFF +#endif + +/** + * PBUF_DEBUG: Enable debugging in pbuf.c. + */ +#ifndef PBUF_DEBUG +#define PBUF_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_LIB_DEBUG: Enable debugging in api_lib.c. + */ +#ifndef API_LIB_DEBUG +#define API_LIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_MSG_DEBUG: Enable debugging in api_msg.c. + */ +#ifndef API_MSG_DEBUG +#define API_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SOCKETS_DEBUG: Enable debugging in sockets.c. + */ +#ifndef SOCKETS_DEBUG +#define SOCKETS_DEBUG LWIP_DBG_OFF +#endif + +/** + * ICMP_DEBUG: Enable debugging in icmp.c. + */ +#ifndef ICMP_DEBUG +#define ICMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IGMP_DEBUG: Enable debugging in igmp.c. + */ +#ifndef IGMP_DEBUG +#define IGMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * INET_DEBUG: Enable debugging in inet.c. + */ +#ifndef INET_DEBUG +#define INET_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_DEBUG: Enable debugging for IP. + */ +#ifndef IP_DEBUG +#define IP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass. + */ +#ifndef IP_REASS_DEBUG +#define IP_REASS_DEBUG LWIP_DBG_OFF +#endif + +/** + * RAW_DEBUG: Enable debugging in raw.c. + */ +#ifndef RAW_DEBUG +#define RAW_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEM_DEBUG: Enable debugging in mem.c. + */ +#ifndef MEM_DEBUG +#define MEM_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEMP_DEBUG: Enable debugging in memp.c. + */ +#ifndef MEMP_DEBUG +#define MEMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SYS_DEBUG: Enable debugging in sys.c. + */ +#ifndef SYS_DEBUG +#define SYS_DEBUG LWIP_DBG_OFF +#endif + +/** + * TIMERS_DEBUG: Enable debugging in timers.c. + */ +#ifndef TIMERS_DEBUG +#define TIMERS_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_DEBUG: Enable debugging for TCP. + */ +#ifndef TCP_DEBUG +#define TCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug. + */ +#ifndef TCP_INPUT_DEBUG +#define TCP_INPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit. + */ +#ifndef TCP_FR_DEBUG +#define TCP_FR_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit + * timeout. + */ +#ifndef TCP_RTO_DEBUG +#define TCP_RTO_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_CWND_DEBUG: Enable debugging for TCP congestion window. + */ +#ifndef TCP_CWND_DEBUG +#define TCP_CWND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating. + */ +#ifndef TCP_WND_DEBUG +#define TCP_WND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions. + */ +#ifndef TCP_OUTPUT_DEBUG +#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RST_DEBUG: Enable debugging for TCP with the RST message. + */ +#ifndef TCP_RST_DEBUG +#define TCP_RST_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths. + */ +#ifndef TCP_QLEN_DEBUG +#define TCP_QLEN_DEBUG LWIP_DBG_OFF +#endif + +/** + * UDP_DEBUG: Enable debugging in UDP. + */ +#ifndef UDP_DEBUG +#define UDP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCPIP_DEBUG: Enable debugging in tcpip.c. + */ +#ifndef TCPIP_DEBUG +#define TCPIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * PPP_DEBUG: Enable debugging for PPP. + */ +#ifndef PPP_DEBUG +#define PPP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SLIP_DEBUG: Enable debugging in slipif.c. + */ +#ifndef SLIP_DEBUG +#define SLIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * DHCP_DEBUG: Enable debugging in dhcp.c. + */ +#ifndef DHCP_DEBUG +#define DHCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * AUTOIP_DEBUG: Enable debugging in autoip.c. + */ +#ifndef AUTOIP_DEBUG +#define AUTOIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MSG_DEBUG: Enable debugging for SNMP messages. + */ +#ifndef SNMP_MSG_DEBUG +#define SNMP_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs. + */ +#ifndef SNMP_MIB_DEBUG +#define SNMP_MIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * DNS_DEBUG: Enable debugging for DNS. + */ +#ifndef DNS_DEBUG +#define DNS_DEBUG LWIP_DBG_OFF +#endif + +// in order to enable the lwIP debug output the bellow has to be uncomment and +// the options above changed to LWIP_DBG_ON for the features that are to output debug information +//#define LWIP_DEBUG 1 + +// enable full duplex comms on multiple threads +// this requires adding an extra field in ChibiOS thread_t (see comment on platform_sys_arch.c) +//#define LWIP_NETCONN_FULLDUPLEX 1 + +#endif /* __LWIPOPT_H__ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/managed_helpers/Adc.cs b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/managed_helpers/Adc.cs new file mode 100644 index 00000000..8fe3c75b --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/managed_helpers/Adc.cs @@ -0,0 +1,73 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +namespace nanoFramework.Targets.ST_NUCLEO144_F439ZI +{ + /// + /// Enumeration of ADC channels available on ST_NUCLEO144_F439ZI + /// + public static class AdcChannels + { + /// + /// Channel 0, exposed as A0, connected to pin 1 on CN9 = PA3 (ADC1 - IN3) + /// + public const int Channel_0 = 0; + + /// + /// Channel 1, exposed as A1, connected to pin 3 on CN9 = PC0 (ADC1 - IN10) + /// + public const int Channel_1 = 1; + + /// + /// Channel 2, exposed as A2, connected to pin 5 on CN9 = PC3 (ADC1 - IN13) + /// + public const int Channel_2 = 2; + + /// + /// Channel 3, exposed as A3, connected to pin 7 on CN9 = PF3 (ADC3 - IN9) + /// + public const int Channel_3 = 3; + + /// + /// Channel 4, exposed as A4, connected to pin 9 on CN9 = PF5 (ADC3 - IN15) + /// + public const int Channel_4 = 4; + + /// + /// Channel 5, exposed on A5, connected to pin 11 on CN9 = PF10 (ADC3 - IN8) + /// + public const int Channel_5 = 5; + + /// + /// Channel 6, exposed on PB1, connected to CN10 Pin 7 (ADC2 - IN9) + /// + public const int Channel_6 = 6; + + /// + /// Channel 7, exposed on PC2, connected to CN10 Pin 9 (ADC2 - IN12) + /// + public const int Channel_7 = 7; + + /// + /// Channel 8, exposed on PF4, connected to CN10 Pin 11 (ADC3 - IN14) + /// + public const int Channel_8 = 8; + + /// + /// Channel 9, internal temperature sensor, connected to ADC1 + /// + public const int Channel_TemperatureSensor = 9; + + /// + /// Channel 10, internal voltage reference, connected to ADC1 + /// + public const int Channel_VrefIn = 10; + + /// + /// Channel 11, connected to VBatt pin, ADC1 + /// + public const int Channel_Vbatt = 11; + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/managed_helpers/README.md b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/managed_helpers/README.md new file mode 100644 index 00000000..e73c9643 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/managed_helpers/README.md @@ -0,0 +1,5 @@ +## Managed code helpers + +This folder contains helper classes to make developers life easier when coding for this target board. + +* [Adc](Adc.cs) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/mbedtls_config.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/mbedtls_config.h new file mode 100644 index 00000000..9877ca77 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/mbedtls_config.h @@ -0,0 +1,53 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2006-2015, ARM Limited, All Rights Reserved +// See LICENSE file in the project root for full license information. +// + +#ifndef MBEDTLS_CONFIG_H +#define MBEDTLS_CONFIG_H + +/* For test certificates */ +// #define MBEDTLS_CERTS_C +// #define MBEDTLS_PEM_PARSE_C + +// #define SSL_DEBUG_BUF MBEDTLS_SSL_DEBUG_BUF +// #define SSL_DEBUG_CRT MBEDTLS_SSL_DEBUG_CRT +// #define SSL_DEBUG_ECP MBEDTLS_SSL_DEBUG_ECP +// #define SSL_DEBUG_MPI MBEDTLS_SSL_DEBUG_MPI +// #define SSL_DEBUG_MSG MBEDTLS_SSL_DEBUG_MSG +// #define SSL_DEBUG_RET MBEDTLS_SSL_DEBUG_RET + +// #define MBEDTLS_SSL_ALL_ALERT_MESSAGES +// #define MBEDTLS_SSL_DEBUG_ALL +// #define MBEDTLS_VERSION_FEATURES +// #define MBEDTLS_CERTS_C +// #define MBEDTLS_ERROR_C +// #define MBEDTLS_VERSION_C + +// uncomment the defines below to enable static memory allocation feature +#if 0 +#define MBEDTLS_MEMORY_BUFFER_ALLOC_C +#define MBEDTLS_PLATFORM_MEMORY +#endif + +#ifdef USE_LCD +#include "lcd_log.h" +#define MBEDTLS_PLATFORM_PRINTF_MACRO LCD_UsrLog +#endif + +// uncomment the defines bellow to generate debug output +// set below the threshold level for debug messages +// check mbed TLS mbedtls/debug.h header for details. +// Debug levels: +// 0 No debug +// 1 Error +// 2 State change +// 3 Informational +// 4 Verbose + +// #define MBEDTLS_DEBUG_C +// #define MBEDTLS_SSL_ALL_ALERT_MESSAGES +// #define MBEDTLS_DEBUG_THRESHOLD 2 + +#endif // MBEDTLS_CONFIG_H diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/CMakeLists.txt new file mode 100644 index 00000000..f0e921f7 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# # append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") + +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/STM32F439xI_booter-DEBUG.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/STM32F439xI_booter-DEBUG.ld new file mode 100644 index 00000000..455ac681 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/STM32F439xI_booter-DEBUG.ld @@ -0,0 +1,97 @@ +/* +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * ST32F439xI memory setup. + * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash : org = 0x08000000, len = 32k /* space reserved for nanoBooter (1st two sectors 0x08000000 to 0x08008000)*/ + config : org = 0x08008000, len = 32k /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */ + ram1 : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20020000, len = 64k /* SRAM3 */ + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram4); + +/* Stacks rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* RAM region to be used for eth segment.*/ +REGION_ALIAS("ETH_RAM", ram0); + +SECTIONS +{ + /* Special section for Ethernet DMA non cache-able areas.*/ + .eth (NOLOAD) : ALIGN(4) + { + __eth_base__ = .; + *(.eth) + *(.eth.*) + *(.bss.__eth_*) + . = ALIGN(4); + __eth_end__ = .; + } > ETH_RAM +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/STM32F439xI_booter.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/STM32F439xI_booter.ld new file mode 100644 index 00000000..d76bca04 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/STM32F439xI_booter.ld @@ -0,0 +1,97 @@ +/* +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * ST32F439xI memory setup. + * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash : org = 0x08000000, len = 32k /* space reserved for nanoBooter (1st two sectors 0x08000000 to 0x08007FFF)*/ + config : org = 0x08008000, len = 32k /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */ + ram1 : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20020000, len = 64k /* SRAM3 */ + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram4); + +/* Stacks rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* RAM region to be used for eth segment.*/ +REGION_ALIAS("ETH_RAM", ram0); + +SECTIONS +{ + /* Special section for Ethernet DMA non cache-able areas.*/ + .eth (NOLOAD) : ALIGN(4) + { + __eth_base__ = .; + *(.eth) + *(.eth.*) + *(.bss.__eth_*) + . = ALIGN(4); + __eth_end__ = .; + } > ETH_RAM +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/chconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/chconf.h new file mode 100644 index 00000000..ef98a914 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/chconf.h @@ -0,0 +1,616 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 1000 // this is 1 millisecond + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#define CH_CFG_INTERVALS_SIZE 32 + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_TIME_TYPES_SIZE 32 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES FALSE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS FALSE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT FALSE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES FALSE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_OBJ_FIFOS TRUE + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#define CH_CFG_USE_FACTORY FALSE + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 + +/** + * @brief Enables the registry of generic objects. + */ +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE + +/** + * @brief Enables factory for generic buffers. + */ +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE + +/** + * @brief Enables factory for semaphores. + */ +#define CH_CFG_FACTORY_SEMAPHORES TRUE + +/** + * @brief Enables factory for mailboxes. + */ +#define CH_CFG_FACTORY_MAILBOXES TRUE + +/** + * @brief Enables factory for objects FIFOs. + */ +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/halconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/halconf.h new file mode 100644 index 00000000..32253663 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/halconf.h @@ -0,0 +1,519 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 64 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/halconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/halconf_nf.h new file mode 100644 index 00000000..c710062b --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/halconf_nf.h @@ -0,0 +1,20 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// Enables the ChibiOS community overlay. +#if !defined(HAL_USE_COMMUNITY) +#define HAL_USE_COMMUNITY TRUE +#endif + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +#endif // _HALCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/main.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/main.c new file mode 100644 index 00000000..01d95f38 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/main.c @@ -0,0 +1,81 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); + +// Application entry point. +int main(void) { + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init SWO as soon as possible to make it available to output ASAP + #if (SWO_OUTPUT == TRUE) + SwoInit(); + #endif + + // the following IF is not mandatory, it's just providing a way for a user to 'force' + // the board to remain in nanoBooter and not launching nanoCLR + + // if the USER button (blue one) is pressed, skip the check for a valid CLR image and remain in booter + // the user button in this board has a pull-up resistor so the check has to be inverted + if (!palReadLine(LINE_BUTTON)) + { + // check for valid CLR image + // we are checking for a valid image right after the configuration block + if(CheckValidCLRImage((uint32_t)&__nanoConfig_end__)) + { + // there seems to be a valid CLR image + // launch nanoCLR + LaunchCLR((uint32_t)&__nanoConfig_end__); + } + } + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // starts the serial driver + sdStart(&SERIAL_DRIVER, NULL); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // initialize configuration manager + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it here to have access to network configuration blocks + ConfigurationManager_Initialize(); + + // Normal main() thread + while (true) { + palToggleLine(LINE_LED1); + palToggleLine(LINE_LED2); + palToggleLine(LINE_LED3); + osDelay(500); + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/mcuconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/mcuconf.h new file mode 100644 index 00000000..6a6ca336 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/mcuconf.h @@ -0,0 +1,355 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF +#define STM32F439_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PLLM_VALUE 16 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV8 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 250 +#define STM32_SDC_READ_TIMEOUT_MS 25 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 TRUE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 +#define STM32_SERIAL_UART7_PRIORITY 12 +#define STM32_SERIAL_UART8_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 FALSE +#define STM32_SPI_USE_SPI5 FALSE +#define STM32_SPI_USE_SPI6 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI5_DMA_PRIORITY 1 +#define STM32_SPI_SPI6_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/mcuconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/mcuconf_nf.h new file mode 100644 index 00000000..5ff03534 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/mcuconf_nf.h @@ -0,0 +1,9 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/target_board.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/target_board.h.in new file mode 100644 index 00000000..19531d9c --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoBooter/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOBOOTER_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/CMakeLists.txt new file mode 100644 index 00000000..e5496b7e --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/STM32F439xI_CLR-DEBUG.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/STM32F439xI_CLR-DEBUG.ld new file mode 100644 index 00000000..f364f36c --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/STM32F439xI_CLR-DEBUG.ld @@ -0,0 +1,102 @@ +/* +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * ST32F439xI memory setup. + * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash : org = 0x08010000, len = 2M - 32k - 32k - 1408k /* flash size less the space reserved for nanoBooter and application deployment*/ + config : org = 0x08008000, len = 32k /* space reserved for configuration block */ + deployment : org = 0x080A0000, len = 1408k /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */ + ram1 : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20020000, len = 64k /* SRAM3 */ + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram4); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +INCLUDE rules_stacks.ld + +/* RAM region to be used for eth segment.*/ +REGION_ALIAS("ETH_RAM", ram0); + +SECTIONS +{ + /* Special section for Ethernet DMA non cache-able areas.*/ + .eth (NOLOAD) : ALIGN(4) + { + __eth_base__ = .; + *(.eth) + *(.eth.*) + *(.bss.__eth_*) + . = ALIGN(4); + __eth_end__ = .; + } > ETH_RAM +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld + +/* nanoCLR rules inclusion.*/ +INCLUDE rules_clr.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/STM32F439xI_CLR.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/STM32F439xI_CLR.ld new file mode 100644 index 00000000..f364f36c --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/STM32F439xI_CLR.ld @@ -0,0 +1,102 @@ +/* +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * ST32F439xI memory setup. + * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash : org = 0x08010000, len = 2M - 32k - 32k - 1408k /* flash size less the space reserved for nanoBooter and application deployment*/ + config : org = 0x08008000, len = 32k /* space reserved for configuration block */ + deployment : org = 0x080A0000, len = 1408k /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */ + ram1 : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20020000, len = 64k /* SRAM3 */ + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram4); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +INCLUDE rules_stacks.ld + +/* RAM region to be used for eth segment.*/ +REGION_ALIAS("ETH_RAM", ram0); + +SECTIONS +{ + /* Special section for Ethernet DMA non cache-able areas.*/ + .eth (NOLOAD) : ALIGN(4) + { + __eth_base__ = .; + *(.eth) + *(.eth.*) + *(.bss.__eth_*) + . = ALIGN(4); + __eth_end__ = .; + } > ETH_RAM +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld + +/* nanoCLR rules inclusion.*/ +INCLUDE rules_clr.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/chconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/chconf.h new file mode 100644 index 00000000..ef39575e --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/chconf.h @@ -0,0 +1,616 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 1000 // this is 1 millisecond + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#define CH_CFG_INTERVALS_SIZE 32 + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_TIME_TYPES_SIZE 32 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_OBJ_FIFOS TRUE + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#define CH_CFG_USE_FACTORY FALSE + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 + +/** + * @brief Enables the registry of generic objects. + */ +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE + +/** + * @brief Enables factory for generic buffers. + */ +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE + +/** + * @brief Enables factory for semaphores. + */ +#define CH_CFG_FACTORY_SEMAPHORES TRUE + +/** + * @brief Enables factory for mailboxes. + */ +#define CH_CFG_FACTORY_MAILBOXES TRUE + +/** + * @brief Enables factory for objects FIFOs. + */ +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/halconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/halconf.h new file mode 100644 index 00000000..aa4d7607 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/halconf.h @@ -0,0 +1,541 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +// #define HAL_USE_ADC FALSE +// #endif + +/** + * @brief Enables the CAN subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +// #define HAL_USE_CAN FALSE +// #endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +// /** +// * @brief Enables the DAC subsystem. +// */ +// #if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +// #define HAL_USE_DAC FALSE +// #endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +// this option is set at target_platform.h (from config file) +//#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +//#define HAL_USE_I2C TRUE +//#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +// #define HAL_USE_MAC TRUE +// #endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +// #define HAL_USE_PWM FALSE +// #endif + +/** + * @brief Enables the RTC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +// #define HAL_USE_RTC TRUE +// #endif + +/** + * @brief Enables the SDC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +// #define HAL_USE_SDC FALSE +// #endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + + +/** + * @brief Enables the SPI subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +// #define HAL_USE_SPI FALSE +// #endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +// #define HAL_USE_UART FALSE +// #endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ + +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +// #define HAL_USE_WDG FALSE +// #endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS TRUE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 64 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/halconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/halconf_nf.h new file mode 100644 index 00000000..7b316d22 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/halconf_nf.h @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ 1 + +// Enables the ChibiOS community overlay. +#if !defined(HAL_USE_COMMUNITY) +#define HAL_USE_COMMUNITY TRUE +#endif + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +#endif // _HALCONF_NF_H_ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/main.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/main.c new file mode 100644 index 00000000..3d00c498 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/main.c @@ -0,0 +1,67 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); +// declare CLRStartup thread here +osThreadDef(CLRStartupThread, osPriorityNormal, 4096, "CLRStartupThread"); + +// Application entry point. +int main(void) { + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init SWO as soon as possible to make it available to output ASAP + #if (SWO_OUTPUT == TRUE) + SwoInit(); + #endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // start watchdog + Watchdog_Init(); + + // starts the serial driver + sdStart(&SERIAL_DRIVER, NULL); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // CLR settings to launch CLR thread + CLR_SETTINGS clrSettings; + (void)memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.EnterDebuggerLoopAfterExit = true; + + // create the CLR Startup thread + osThreadCreate(osThread(CLRStartupThread), &clrSettings); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + while (true) { + osDelay(100); + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/mcuconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/mcuconf.h new file mode 100644 index 00000000..2bc22f18 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/mcuconf.h @@ -0,0 +1,355 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF +#define STM32F439_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSI +#define STM32_PLLM_VALUE 16 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV8 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 2 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 TRUE +#define STM32_ADC_USE_ADC3 TRUE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 TRUE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 TRUE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 TRUE +#define STM32_PWM_USE_TIM8 TRUE +#define STM32_PWM_USE_TIM9 TRUE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 250 +#define STM32_SDC_READ_TIMEOUT_MS 25 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 TRUE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 +#define STM32_SERIAL_UART7_PRIORITY 12 +#define STM32_SERIAL_UART8_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_USE_SPI4 TRUE +#define STM32_SPI_USE_SPI5 TRUE +#define STM32_SPI_USE_SPI6 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI5_DMA_PRIORITY 1 +#define STM32_SPI_SPI6_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 TRUE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 TRUE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG TRUE + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/mcuconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/mcuconf_nf.h new file mode 100644 index 00000000..5ff03534 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/mcuconf_nf.h @@ -0,0 +1,9 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/nanoHAL.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/nanoHAL.cpp new file mode 100644 index 00000000..076a50fc --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/nanoHAL.cpp @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +void HAL_EnterBooterMode() +{ +} + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/target_board.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/target_board.h.in new file mode 100644 index 00000000..5b4698cf --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nanoCLR/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOCLR_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nucleo144-f439zi.jpg b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nucleo144-f439zi.jpg new file mode 100644 index 00000000..9af10bd8 Binary files /dev/null and b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/nucleo144-f439zi.jpg differ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_BlockStorage.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_BlockStorage.c new file mode 100644 index 00000000..9e7c7f55 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_BlockStorage.c @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice STM32Flash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &STM32Flash_BlockStorageInterface, &Device_BlockStorageConfig, false); +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_BlockStorage.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_BlockStorage.h new file mode 100644 index 00000000..aa50b1b7 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_common.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_common.c new file mode 100644 index 00000000..c633da5b --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_common.c @@ -0,0 +1,24 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include "target_common.h" + +HAL_SYSTEM_CONFIG HalSystemConfig = +{ + { true }, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, //ConvertCOM_DebugHandle(1), + 0, //ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + { RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size }, + { FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size } +}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_common.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_common.h.in new file mode 100644 index 00000000..cc944913 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_common.h.in @@ -0,0 +1,37 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x20000000) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x00040000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x08000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00200000) + +///////////////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////// +#define TARGETNAMESTRING "@CHIBIOS_BOARD@" +#define PLATFORMNAMESTRING "STM32F4" +/////////////////////////////////////////////// + +#endif /* _TARGET_COMMON_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_lwip_sntp_opts.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_lwip_sntp_opts.h new file mode 100644 index 00000000..c115cd67 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_lwip_sntp_opts.h @@ -0,0 +1,18 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#define SNTP_SERVER_DEFAULT_ADDRESS "0.pool.ntp.org" + +// update delay (default 1 hour) +// (value in milliseconds) +#define SNTP_UPDATE_DELAY 3600000 + +// better have a startup delay because we can have DHCP enabled (default 30 seconds) +// value in milliseconds +#define SNTP_STARTUP_DELAY 30000 + +// retry timeout (15 minutes) +// value in milliseconds +#define SNTP_RETRY_TIMEOUT 900000 diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_system_devices_dac_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_system_devices_dac_config.cpp new file mode 100644 index 00000000..88a70347 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_system_devices_dac_config.cpp @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_DAC_PORT_PIN_CHANNEL DacPortPinConfig[] = { + + // DAC1, channel 1, GPIO port A, pin 4 + {1, 1, GPIOA, 4}, + +}; + +const int DacChannelCount = ARRAYSIZE(DacPortPinConfig); diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_windows_devices_adc_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_windows_devices_adc_config.cpp new file mode 100644 index 00000000..7d5ccdeb --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_windows_devices_adc_config.cpp @@ -0,0 +1,32 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_adc_native_target.h" + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // ADC1 + {1, GPIOA, 3, ADC_CHANNEL_IN3}, + {1, GPIOC, 0, ADC_CHANNEL_IN10}, + {1, GPIOC, 3, ADC_CHANNEL_IN13}, + + // ADC3 + {3, GPIOF, 3, ADC_CHANNEL_IN9}, + {3, GPIOF, 5, ADC_CHANNEL_IN15}, + {3, GPIOF, 10, ADC_CHANNEL_IN8}, + + // ADC2/ADC3 + // Fill up with rest of set ADC pins + {2, GPIOB, 1, ADC_CHANNEL_IN9}, + {2, GPIOC, 2, ADC_CHANNEL_IN12}, + {3, GPIOF, 4, ADC_CHANNEL_IN14}, + + // these are the internal sources, available only at ADC1 + {1, NULL, 0, ADC_CHANNEL_SENSOR}, + {1, NULL, 0, ADC_CHANNEL_VREFINT}, + {1, NULL, 0, ADC_CHANNEL_VBAT}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_windows_devices_i2c_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_windows_devices_i2c_config.cpp new file mode 100644 index 00000000..70d9d9a8 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_windows_devices_i2c_config.cpp @@ -0,0 +1,31 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_i2c_native_target.h" + +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for SCL pin is: GPIOB +// port for SDA pin is: GPIOB +// SCL pin: is GPIOB_8 +// SDA pin: is GPIOB_9 +// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, GPIOB, GPIOB, 8, 9, 4) + +////////// +// I2C2 // +////////// + +// pin configuration for I2C2 +// port for SCL pin is: GPIOF +// port for SDA pin is: GPIOF +// SCL pin: is GPIOF_0 +// SDA pin: is GPIOF_1 +// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(2, GPIOF, GPIOF, 0, 1, 4) + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_windows_devices_serialcommunication_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_windows_devices_serialcommunication_config.cpp new file mode 100644 index 00000000..219210fa --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_windows_devices_serialcommunication_config.cpp @@ -0,0 +1,68 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_windows_devices_serialcommunication_config.h" +#include "win_dev_serial_native_target.h" + +/////////// +// UART1 // +/////////// + +// pin configuration for UART1 +// port for TX pin is: GPIOA +// port for RX pin is: GPIOA +// TX pin: is GPIOA_9 +// RX pin: is GPIOA_10 +// GPIO alternate pin function is 7 (see "Table 12. STM32F427xx and STM32F429xx alternate function mapping" in STM32F427xx and STM32F429xx datasheet) +UART_CONFIG_PINS(1, GPIOA, GPIOA, 9, 10, 7) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart1_TxBuffer[UART1_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart1_RxBuffer[UART1_RX_SIZE]; + +// initialization for UART1 +UART_INIT(1, UART1_TX_SIZE, UART1_RX_SIZE) + +// un-initialization for UART1 +UART_UNINIT(1) + +/////////// +// UART6 // +/////////// + +// pin configuration for UART6 +// port for TX pin is: GPIOG +// port for RX pin is: GPIOG +// TX pin: is GPIOG_14 +// RX pin: is GPIOG_9 +// GPIO alternate pin function is 8 (see "Table 12. STM32F427xx and STM32F429xx alternate function mapping" in STM32F427xx and STM32F429xx datasheet) +UART_CONFIG_PINS(6, GPIOG, GPIOG, 14, 9, 8) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart6_TxBuffer[UART6_TX_SIZE]; + +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart6_RxBuffer[UART6_RX_SIZE]; + +// initialization for UART6 +UART_INIT(6, UART6_TX_SIZE, UART6_RX_SIZE) + +// un-initialization for UART6 +UART_UNINIT(6) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_windows_devices_serialcommunication_config.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_windows_devices_serialcommunication_config.h new file mode 100644 index 00000000..66671f10 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_windows_devices_serialcommunication_config.h @@ -0,0 +1,31 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////// +// UART1 // +/////////// + +// enable USART1 +#define NF_SERIAL_COMM_STM32_UART_USE_USART1 TRUE + +// buffers size +// tx buffer size: 256 bytes +#define UART1_TX_SIZE 256 +// rx buffer size: 256 bytes +#define UART1_RX_SIZE 256 + + +/////////// +// UART6 // +/////////// + +// enable USART6 +#define NF_SERIAL_COMM_STM32_UART_USE_USART6 TRUE + +// buffers size +// tx buffer size: 256 bytes +#define UART6_TX_SIZE 256 +// rx buffer size: 256 bytes +#define UART6_RX_SIZE 256 diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_windows_devices_spi_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_windows_devices_spi_config.cpp new file mode 100644 index 00000000..f08c5650 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI/target_windows_devices_spi_config.cpp @@ -0,0 +1,10 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_spi_native_target.h" + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/CMakeLists.txt new file mode 100644 index 00000000..eaaf8443 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/CMakeLists.txt @@ -0,0 +1,239 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +cmake_minimum_required(VERSION 3.0) +ENABLE_LANGUAGE(ASM) + +# add header files with common OS definitions and board definitions specific for each image +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/target_common.h" @ONLY) + +set(NANOBOOTER_PROJECT_NAME "nanoBooter") +set(NANOCLR_PROJECT_NAME "nanoCLR") + +find_package(BuildUtils REQUIRED) +find_package(CHIBIOS REQUIRED) +find_package(ChibiOSnfOverlay REQUIRED) +find_package(WireProtocol REQUIRED) + +# packages for nanoFramework libraries +####################################### +# mandatory +find_package(NF_CoreCLR REQUIRED) + +####################################### +# optional + +# ChibiOS contrib repo +if(CHIBIOS_CONTRIB_REQUIRED) + find_package(ChibiOS-Contrib REQUIRED) +endif() + +# nF feature: debugger +if(NF_FEATURE_DEBUGGER) + find_package(NF_Debugger REQUIRED) + find_package(NF_Diagnostics REQUIRED) +endif() + +# nF feature: networking +if(USE_NETWORKING_OPTION) + find_package(CHIBIOS_LWIP REQUIRED) + find_package(NF_NETWORKING REQUIRED) +endif() + +# nF feature: filesystem +if(USE_FILESYSTEM_OPTION) + find_package(CHIBIOS_FATFS REQUIRED) +endif() + +# security provider is mbedTLS +if(USE_SECURITY_MBEDTLS_OPTION) + find_package(mbedTLS REQUIRED) +endif() + +####################################### + +add_subdirectory("common") +add_subdirectory("nanoBooter") +add_subdirectory("nanoCLR") + +####################### +# nanoBooter executable + +add_executable( + # executables for project, project sources + ${NANOBOOTER_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + "${CMAKE_CURRENT_SOURCE_DIR}/target_BlockStorage.c" + + # need to add configuration manager to allow get/store configuration blocks + "${PROJECT_SOURCE_DIR}/src/HAL/nanoHAL_ConfigurationManager.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOBOOTER_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOBOOTER_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOBOOTER_SOURCES} + + ${CHIBIOS_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} +) + +####################### +# nanoCLR executable + +add_executable( + # executables for project, project sources + ${NANOCLR_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOCLR_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOCLR_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOCLR_SOURCES} + + ${CHIBIOS_SOURCES} + ${CHIBIOS_CONTRIB_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} + + # sources for nanoFramework libraries + ${NF_CoreCLR_SOURCES} + ${NF_Debugger_SOURCES} + ${NF_Diagnostics_SOURCES} + + # sources for nanoFramework Network LWIP, Sockets and TLS + "${CHIBIOS_LWIP_SOURCES}" + ${NF_Networking_SOURCES} + "${mbedTLS_SOURCES}" + + # sources for nanoFramework APIs + ${TARGET_NANO_APIS_SOURCES} +) + +# add dependency from ChibiOS (this is required to make sure the ChibiOS repo is downloaded before the build starts) +add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf ChibiOS) +add_dependencies(${NANOCLR_PROJECT_NAME}.elf ChibiOS) + +# add dependencies from CHIBIOS_NETWORK_COMPONENTS (this is required to make sure that ChibiOS network components are unzip at the proper locations before the build starts) +# only required if networking in ON +if(USE_NETWORKING_OPTION) + add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf CHIBIOS_NETWORK_COMPONENTS) + add_dependencies(${NANOCLR_PROJECT_NAME}.elf CHIBIOS_NETWORK_COMPONENTS) + + # add dependency for security provider mbedTLS + if(USE_SECURITY_MBEDTLS_OPTION) + add_dependencies(${NANOCLR_PROJECT_NAME}.elf mbedTLS) + endif() +endif() + +# include common directories +include_directories( + ${CMAKE_CURRENT_BINARY_DIR} + ${CMAKE_CURRENT_SOURCE_DIR} + ${CMAKE_CURRENT_SOURCE_DIR}/common + ${PROJECT_SOURCE_DIR}/src/CLR/Core + ${PROJECT_SOURCE_DIR}/src/CLR/Include + ${PROJECT_SOURCE_DIR}/src/HAL/Include + ${PROJECT_SOURCE_DIR}/src/PAL/Include + + ${WireProtocol_INCLUDE_DIRS} + ${CHIBIOS_INCLUDE_DIRS} + ${ChibiOSnfOverlay_INCLUDE_DIRS} + ${CHIBIOS_CONTRIB_INCLUDE_DIRS} + + ${TARGET_CMSIS_COMMON_INCLUDE_DIRS} + ${TARGET_CHIBIOS_COMMON_INCLUDE_DIRS} +) + +# include directories for nanoBooter +target_include_directories(${NANOBOOTER_PROJECT_NAME}.elf PUBLIC + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter" + ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter + + ${TARGET_CMSIS_NANOBOOTER_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOBOOTER_INCLUDE_DIRS} + + # includes for ChibiOS LwIP + ${CHIBIOS_LWIP_INCLUDE_DIRS} +) + +# include directories for nanoCLR +target_include_directories(${NANOCLR_PROJECT_NAME}.elf PUBLIC + ${CMAKE_CURRENT_BINARY_DIR}/nanoCLR + ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR + + ${TARGET_CMSIS_NANOCLR_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOCLR_INCLUDE_DIRS} + + # directories for nanoFramework libraries + ${NF_CoreCLR_INCLUDE_DIRS} + ${NF_Debugger_INCLUDE_DIRS} + ${NF_Diagnostics_INCLUDE_DIRS} + + # includes for nanoFramework APIs + ${TARGET_NANO_APIS_INCLUDES} + + # includes for ChibiOS LwIP + ${CHIBIOS_LWIP_INCLUDE_DIRS} + + # incudes for Networking and TLS + ${NF_Networking_INCLUDE_DIRS} + ${mbedTLS_INCLUDE_DIRS} +) + +# set compiler options +nf_set_compiler_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_options(${NANOCLR_PROJECT_NAME}.elf) + +# mbed TLS requires a config file +if(USE_SECURITY_MBEDTLS_OPTION) + # this seems to be only option to properly set a compiler define through the command line that needs to be a string literal + SET(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -DMBEDTLS_CONFIG_FILE=\"<${PROJECT_SOURCE_DIR}/src/PAL/COM/sockets/ssl/mbedTLS/nf_mbedtls_config.h>\"") + SET(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -DMBEDTLS_CONFIG_FILE=\"<${PROJECT_SOURCE_DIR}/src/PAL/COM/sockets/ssl/mbedTLS/nf_mbedtls_config.h>\"") +endif() + +# set compiler definitions +nf_set_compiler_definitions(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_definitions(${NANOCLR_PROJECT_NAME}.elf) + +# set linker files +if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F746xG_booter-DEBUG.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/STM32F746xG_CLR-DEBUG.ld) +else() + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F746xG_booter.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/STM32F746xG_CLR.ld) +endif() + +# set linker options +nf_set_linker_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_linker_options(${NANOCLR_PROJECT_NAME}.elf) + +# add other linker flags +########################################################### +# the sizes of CRT heap and ChibiOS stacks are defined here +set_property(TARGET ${NANOBOOTER_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x400,--defsym=__crt_heap_size__=0x1000") +set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x21000") + +# generate output files +nf_generate_build_output_files(${NANOBOOTER_PROJECT_NAME}.elf) +nf_generate_build_output_files(${NANOCLR_PROJECT_NAME}.elf) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/README.md b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/README.md new file mode 100644 index 00000000..04fa8212 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/README.md @@ -0,0 +1,31 @@ +## STM NUCLEO144 F746ZG board + +![STM NUCLEO144 F746ZG board](nucleo144-f746zg.jpg) + +The board used in this community contribution is the NUCLEO144 F746ZG board from STM. The board can be purchased from various sources and should be about 23 euros. Further information on this board and links for the user and programming manuals can be found at the product page in ST [website](http://www.st.com/en/evaluation-tools/nucleo-f746zg.html). + +Some basic information abstracted from ST: +- STM32 microcontroller in LQFP144 package +- External SMPS to generate Vcore logic supply (only available on '-P' suffixed boards) +- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) +- USB OTG or full-speed device (depending on STM32 support) +- 3 user LEDs +-2 user and reset push-buttons +- 32.768 kHz crystal oscillator +- Board connectors: + - USB with Micro-AB + - SWD + - Ethernet RJ45 (depending on STM32 support) + - ST Zio connector including Arduino™ Uno V3 + - ST morpho +- Flexible power-supply options: ST-LINK USB VBUS or external sources +- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration capability: mass storage, virtual COM port and debug port + +### Flashing and debugging + +This board has two micro USB connectors. One is exposing the embedded ST-Link interface that is used for flashing the nanoFramework firmware and for performing debugging on the nanoCLR code. The second is used to connect the device with Visual Studio allowing to deploy and debug your C# managed applications. + +## Floating point + +The current build is set to add support for single-precision floating point. +Meaning that `System.Math` API supports only the `float` overloads. The `double` ones will throw a `NotImplementedException`. diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/board.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/board.c new file mode 100644 index 00000000..90f2ece9 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/board.c @@ -0,0 +1,266 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) + gpio_setup_t PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_setup_t PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) + gpio_setup_t PKData; +#endif +} gpio_config_t; + +/** + * @brief STM32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +#endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB1(STM32_GPIO_EN_MASK); + rccEnableAHB1(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG + gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI + gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ + gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK + gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + * else. + */ +void __early_init(void) { + + stm32_gpio_init(); + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + + return !palReadLine(LINE_SD_DETECT); +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { + +} \ No newline at end of file diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/board.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/board.h new file mode 100644 index 00000000..6f8dd55f --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/board.h @@ -0,0 +1,1833 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef BOARD_H +#define BOARD_H + +/* + * Setup for STMicroelectronics STM32 Nucleo144-F746ZG board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_NUCLEO144_F746ZG +#define BOARD_NAME "STMicroelectronics STM32 Nucleo144-F746ZG" + +/* + * Ethernet PHY type. + */ +#define BOARD_PHY_ID MII_LAN8742A_ID +#define BOARD_PHY_RMII + +/* + * Board oscillators-related settings. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768U +#endif + +#define STM32_LSEDRV (3U << 3U) + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 8000000U +#endif + +#define STM32_HSE_BYPASS + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U + +/* + * MCU type as defined in the ST header. + */ +#define STM32F746xx + +/* + * IO pins assignments. + */ +#define GPIOA_ZIO_D32 0U +#define GPIOA_TIM2_CH1 0U +#define GPIOA_RMII_REF_CLK 1U +#define GPIOA_RMII_MDIO 2U +#define GPIOA_ARD_A0 3U +#define GPIOA_ADC123_IN3 3U +#define GPIOA_ZIO_D24 4U +#define GPIOA_SPI3_NSS 4U +#define GPIOA_ARD_D13 5U +#define GPIOA_SPI1_SCK 5U +#define GPIOA_ARD_D12 6U +#define GPIOA_SPI1_MISO 6U +#define GPIOA_RMII_CRS_DV 7U +#define GPIOA_SPI1_MOSI 7U +#define GPIOA_ZIO_D71 7U +#define GPIOA_RMII_RX_DV 7U +#define GPIOA_USB_SOF 8U +#define GPIOA_USB_VBUS 9U +#define GPIOA_USB_ID 10U +#define GPIOA_USB_DM 11U +#define GPIOA_USB_DP 12U +#define GPIOA_SWDIO 13U +#define GPIOA_SWCLK 14U +#define GPIOA_ZIO_D20 15U +#define GPIOA_I2S3_WS 15U + +#define GPIOB_ZIO_D33 0U +#define GPIOB_TIM3_CH3 0U +#define GPIOB_LED1 0U +#define GPIOB_ZIO_A6 1U +#define GPIOB_ADC12_IN9 1U +#define GPIOB_ZIO_D27 2U +#define GPIOB_QSPI_CLK 2U +#define GPIOB_ZIO_D23 3U +#define GPIOB_I2S3_CK 3U +#define GPIOB_ZIO_D25 4U +#define GPIOB_SPI3_MISO 4U +#define GPIOB_ZIO_D22 5U +#define GPIOB_I2S3_SD 5U +#define GPIOB_ZIO_D26 6U +#define GPIOB_QSPI_BK1_NCS 6U +#define GPIOB_LED2 7U +#define GPIOB_ARD_D15 8U +#define GPIOB_I2C1_SCL 8U +#define GPIOB_ARD_D14 9U +#define GPIOB_I2C1_SDA 9U +#define GPIOB_ZIO_D36 10U +#define GPIOB_TIM2_CH3 10U +#define GPIOB_ZIO_D35 11U +#define GPIOB_TIM2_CH4 11U +#define GPIOB_ZIO_D19 12U +#define GPIOB_I2S2_WS 12U +#define GPIOB_ZIO_D18 13U +#define GPIOB_I2S2_CK 13U +#define GPIOB_RMII_TXD1 13U +#define GPIOB_LED3 14U +#define GPIOB_ZIO_D17 15U +#define GPIOB_I2S2_SD 15U + +#define GPIOC_ARD_A1 0U +#define GPIOC_ADC123_IN10 0U +#define GPIOC_RMII_MDC 1U +#define GPIOC_ZIO_A7 2U +#define GPIOC_ADC123_IN12 2U +#define GPIOC_ARD_A2 3U +#define GPIOC_ADC123_IN13 3U +#define GPIOC_RMII_RXD0 4U +#define GPIOC_RMII_RXD1 5U +#define GPIOC_ZIO_D16 6U +#define GPIOC_I2S2_MCK 6U +#define GPIOC_ZIO_D21 7U +#define GPIOC_I2S3_MCK 7U +#define GPIOC_ZIO_D43 8U +#define GPIOC_SDMMC_D0 8U +#define GPIOC_ZIO_D44 9U +#define GPIOC_SDMMC_D1 9U +#define GPIOC_ZIO_D45 10U +#define GPIOC_SDMMC_D2 10U +#define GPIOC_ZIO_D46 11U +#define GPIOC_SDMMC_D3 11U +#define GPIOC_ZIO_D47 12U +#define GPIOC_SDMMC_CK 12U +#define GPIOC_BUTTON 13U +#define GPIOC_OSC32_IN 14U +#define GPIOC_OSC32_OUT 15U + +#define GPIOD_ZIO_D67 0U +#define GPIOD_CAN1_RX 0U +#define GPIOD_ZIO_D66 1U +#define GPIOD_CAN1_TX 1U +#define GPIOD_ZIO_D48 2U +#define GPIOD_SDMMC_CMD 2U +#define GPIOD_ZIO_D55 3U +#define GPIOD_USART2_CTS 3U +#define GPIOD_ZIO_D54 4U +#define GPIOD_USART2_RTS 4U +#define GPIOD_ZIO_D53 5U +#define GPIOD_USART2_TX 5U +#define GPIOD_ZIO_D52 6U +#define GPIOD_USART2_RX 6U +#define GPIOD_ZIO_D51 7U +#define GPIOD_USART2_SCLK 7U +#define GPIOD_USART3_RX 8U +#define GPIOD_STLK_RX 8U +#define GPIOD_USART3_TX 9U +#define GPIOD_STLK_TX 9U +#define GPIOD_PIN10 10U +#define GPIOD_ZIO_D30 11U +#define GPIOD_QSPI_BK1_IO0 11U +#define GPIOD_ZIO_D29 12U +#define GPIOD_QSPI_BK1_IO1 12U +#define GPIOD_ZIO_D28 13U +#define GPIOD_QSPI_BK1_IO3 13U +#define GPIOD_ARD_D10 14U +#define GPIOD_SPI1_NSS 14U +#define GPIOD_ARD_D9 15U +#define GPIOD_TIM4_CH4 15U + +#define GPIOE_ZIO_D34 0U +#define GPIOE_TIM4_ETR 0U +#define GPIOE_PIN1 1U +#define GPIOE_ZIO_D31 2U +#define GPIOE_ZIO_D56 2U +#define GPIOE_SAI1_MCLK_A 2U +#define GPIOE_ZIO_D60 3U +#define GPIOE_SAI1_SD_B 3U +#define GPIOE_ZIO_D57 4U +#define GPIOE_SAI1_FS_A 4U +#define GPIOE_ZIO_D58 5U +#define GPIOE_SAI1_SCK_A 5U +#define GPIOE_ZIO_D59 6U +#define GPIOE_SAI1_SD_A 6U +#define GPIOE_ZIO_D41 7U +#define GPIOE_TIM1_ETR 7U +#define GPIOE_ZIO_D42 8U +#define GPIOE_TIM1_CH1N 8U +#define GPIOE_ARD_D6 9U +#define GPIOE_TIM1_CH1 9U +#define GPIOE_ZIO_D40 10U +#define GPIOE_TIM1_CH2N 10U +#define GPIOE_ARD_D5 11U +#define GPIOE_TIM1_CH2 11U +#define GPIOE_ZIO_D39 12U +#define GPIOE_TIM1_CH3N 12U +#define GPIOE_ARD_D3 13U +#define GPIOE_TIM1_CH3 13U +#define GPIOE_ZIO_D38 14U +#define GPIOE_ZIO_D37 15U +#define GPIOE_TIM1_BKIN1 15U + +#define GPIOF_ZIO_D68 0U +#define GPIOF_I2C2_SDA 0U +#define GPIOF_ZIO_D69 1U +#define GPIOF_I2C2_SCL 1U +#define GPIOF_ZIO_D70 2U +#define GPIOF_I2C2_SMBA 2U +#define GPIOF_ARD_A3 3U +#define GPIOF_ADC3_IN9 3U +#define GPIOF_ZIO_A8 4U +#define GPIOF_ADC3_IN14 4U +#define GPIOF_ARD_A4 5U +#define GPIOF_ADC3_IN15 5U +#define GPIOF_PIN6 6U +#define GPIOF_ZIO_D62 7U +#define GPIOF_SPI5_SCK 7U +#define GPIOF_SPI5_MISO 8U +#define GPIOF_SAI1_SCK_B 8U +#define GPIOF_SPI5_MOSI 9U +#define GPIOF_SAI1_FS_B 9U +#define GPIOF_ARD_A5 10U +#define GPIOF_ADC3_IN8 10U +#define GPIOF_PIN11 11U +#define GPIOF_ARD_D8 12U +#define GPIOF_ARD_D7 13U +#define GPIOF_ARD_D4 14U +#define GPIOF_ARD_D2 15U + +#define GPIOG_ZIO_D65 0U +#define GPIOG_ZIO_D64 1U +#define GPIOG_ZIO_D49 2U +#define GPIOG_ZIO_D50 3U +#define GPIOG_PIN4 4U +#define GPIOG_PIN5 5U +#define GPIOG_USB_GPIO_OUT 6U +#define GPIOG_USB_GPIO_IN 7U +#define GPIOG_PIN8 8U +#define GPIOG_ARD_D0 9U +#define GPIOG_USART6_RX 9U +#define GPIOG_PIN10 10U +#define GPIOG_RMII_TX_EN 11U +#define GPIOG_PIN12 12U +#define GPIOG_RMII_TXD0 13U +#define GPIOG_ARD_D1 14U +#define GPIOG_USART6_TX 14U +#define GPIOG_PIN15 15U + +#define GPIOH_OSC_IN 0U +#define GPIOH_OSC_OUT 1U +#define GPIOH_PIN2 2U +#define GPIOH_PIN3 3U +#define GPIOH_PIN4 4U +#define GPIOH_PIN5 5U +#define GPIOH_PIN6 6U +#define GPIOH_PIN7 7U +#define GPIOH_PIN8 8U +#define GPIOH_PIN9 9U +#define GPIOH_PIN10 10U +#define GPIOH_PIN11 11U +#define GPIOH_PIN12 12U +#define GPIOH_PIN13 13U +#define GPIOH_PIN14 14U +#define GPIOH_PIN15 15U + +#define GPIOI_PIN0 0U +#define GPIOI_PIN1 1U +#define GPIOI_PIN2 2U +#define GPIOI_PIN3 3U +#define GPIOI_PIN4 4U +#define GPIOI_PIN5 5U +#define GPIOI_PIN6 6U +#define GPIOI_PIN7 7U +#define GPIOI_PIN8 8U +#define GPIOI_PIN9 9U +#define GPIOI_PIN10 10U +#define GPIOI_PIN11 11U +#define GPIOI_PIN12 12U +#define GPIOI_PIN13 13U +#define GPIOI_PIN14 14U +#define GPIOI_PIN15 15U + +#define GPIOJ_PIN0 0U +#define GPIOJ_PIN1 1U +#define GPIOJ_PIN2 2U +#define GPIOJ_PIN3 3U +#define GPIOJ_PIN4 4U +#define GPIOJ_PIN5 5U +#define GPIOJ_PIN6 6U +#define GPIOJ_PIN7 7U +#define GPIOJ_PIN8 8U +#define GPIOJ_PIN9 9U +#define GPIOJ_PIN10 10U +#define GPIOJ_PIN11 11U +#define GPIOJ_PIN12 12U +#define GPIOJ_PIN13 13U +#define GPIOJ_PIN14 14U +#define GPIOJ_PIN15 15U + +#define GPIOK_PIN0 0U +#define GPIOK_PIN1 1U +#define GPIOK_PIN2 2U +#define GPIOK_PIN3 3U +#define GPIOK_PIN4 4U +#define GPIOK_PIN5 5U +#define GPIOK_PIN6 6U +#define GPIOK_PIN7 7U +#define GPIOK_PIN8 8U +#define GPIOK_PIN9 9U +#define GPIOK_PIN10 10U +#define GPIOK_PIN11 11U +#define GPIOK_PIN12 12U +#define GPIOK_PIN13 13U +#define GPIOK_PIN14 14U +#define GPIOK_PIN15 15U + +/* + * IO lines assignments. + */ +#define LINE_ZIO_D32 PAL_LINE(GPIOA, 0U) +#define LINE_TIM2_CH1 PAL_LINE(GPIOA, 0U) +#define LINE_RMII_REF_CLK PAL_LINE(GPIOA, 1U) +#define LINE_RMII_MDIO PAL_LINE(GPIOA, 2U) +#define LINE_ARD_A0 PAL_LINE(GPIOA, 3U) +#define LINE_ADC123_IN3 PAL_LINE(GPIOA, 3U) +#define LINE_ZIO_D24 PAL_LINE(GPIOA, 4U) +#define LINE_SPI3_NSS PAL_LINE(GPIOA, 4U) +#define LINE_ARD_D13 PAL_LINE(GPIOA, 5U) +#define LINE_SPI1_SCK PAL_LINE(GPIOA, 5U) +#define LINE_ARD_D12 PAL_LINE(GPIOA, 6U) +#define LINE_SPI1_MISO PAL_LINE(GPIOA, 6U) +#define LINE_RMII_CRS_DV PAL_LINE(GPIOA, 7U) +#define LINE_SPI1_MOSI PAL_LINE(GPIOA, 7U) +#define LINE_ZIO_D71 PAL_LINE(GPIOA, 7U) +#define LINE_USB_SOF PAL_LINE(GPIOA, 8U) +#define LINE_USB_VBUS PAL_LINE(GPIOA, 9U) +#define LINE_USB_ID PAL_LINE(GPIOA, 10U) +#define LINE_USB_DM PAL_LINE(GPIOA, 11U) +#define LINE_USB_DP PAL_LINE(GPIOA, 12U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) +#define LINE_ZIO_D20 PAL_LINE(GPIOA, 15U) +#define LINE_I2S3_WS PAL_LINE(GPIOA, 15U) + +#define LINE_ZIO_D33 PAL_LINE(GPIOB, 0U) +#define LINE_TIM3_CH3 PAL_LINE(GPIOB, 0U) +#define LINE_LED1 PAL_LINE(GPIOB, 0U) +#define LINE_ZIO_A6 PAL_LINE(GPIOB, 1U) +#define LINE_ADC12_IN9 PAL_LINE(GPIOB, 1U) +#define LINE_ZIO_D27 PAL_LINE(GPIOB, 2U) +#define LINE_QSPI_CLK PAL_LINE(GPIOB, 2U) +#define LINE_ZIO_D23 PAL_LINE(GPIOB, 3U) +#define LINE_I2S3_CK PAL_LINE(GPIOB, 3U) +#define LINE_ZIO_D25 PAL_LINE(GPIOB, 4U) +#define LINE_SPI3_MISO PAL_LINE(GPIOB, 4U) +#define LINE_ZIO_D22 PAL_LINE(GPIOB, 5U) +#define LINE_I2S3_SD PAL_LINE(GPIOB, 5U) +#define LINE_ZIO_D26 PAL_LINE(GPIOB, 6U) +#define LINE_QSPI_BK1_NCS PAL_LINE(GPIOB, 6U) +#define LINE_LED2 PAL_LINE(GPIOB, 7U) +#define LINE_ARD_D15 PAL_LINE(GPIOB, 8U) +#define LINE_I2C1_SCL PAL_LINE(GPIOB, 8U) +#define LINE_ARD_D14 PAL_LINE(GPIOB, 9U) +#define LINE_I2C1_SDA PAL_LINE(GPIOB, 9U) +#define LINE_ZIO_D36 PAL_LINE(GPIOB, 10U) +#define LINE_TIM2_CH3 PAL_LINE(GPIOB, 10U) +#define LINE_ZIO_D35 PAL_LINE(GPIOB, 11U) +#define LINE_TIM2_CH4 PAL_LINE(GPIOB, 11U) +#define LINE_ZIO_D19 PAL_LINE(GPIOB, 12U) +#define LINE_I2S2_WS PAL_LINE(GPIOB, 12U) +#define LINE_ZIO_D18 PAL_LINE(GPIOB, 13U) +#define LINE_I2S2_CK PAL_LINE(GPIOB, 13U) +#define LINE_RMII_TXD1 PAL_LINE(GPIOB, 13U) +#define LINE_LED3 PAL_LINE(GPIOB, 14U) +#define LINE_ZIO_D17 PAL_LINE(GPIOB, 15U) +#define LINE_I2S2_SD PAL_LINE(GPIOB, 15U) + +#define LINE_ARD_A1 PAL_LINE(GPIOC, 0U) +#define LINE_ADC123_IN10 PAL_LINE(GPIOC, 0U) +#define LINE_RMII_MDC PAL_LINE(GPIOC, 1U) +#define LINE_ZIO_A7 PAL_LINE(GPIOC, 2U) +#define LINE_ADC123_IN12 PAL_LINE(GPIOC, 2U) +#define LINE_ARD_A2 PAL_LINE(GPIOC, 3U) +#define LINE_ADC123_IN13 PAL_LINE(GPIOC, 3U) +#define LINE_RMII_RXD0 PAL_LINE(GPIOC, 4U) +#define LINE_RMII_RXD1 PAL_LINE(GPIOC, 5U) +#define LINE_ZIO_D16 PAL_LINE(GPIOC, 6U) +#define LINE_I2S2_MCK PAL_LINE(GPIOC, 6U) +#define LINE_ZIO_D21 PAL_LINE(GPIOC, 7U) +#define LINE_I2S3_MCK PAL_LINE(GPIOC, 7U) +#define LINE_ZIO_D43 PAL_LINE(GPIOC, 8U) +#define LINE_SDMMC_D0 PAL_LINE(GPIOC, 8U) +#define LINE_ZIO_D44 PAL_LINE(GPIOC, 9U) +#define LINE_SDMMC_D1 PAL_LINE(GPIOC, 9U) +#define LINE_ZIO_D45 PAL_LINE(GPIOC, 10U) +#define LINE_SDMMC_D2 PAL_LINE(GPIOC, 10U) +#define LINE_ZIO_D46 PAL_LINE(GPIOC, 11U) +#define LINE_SDMMC_D3 PAL_LINE(GPIOC, 11U) +#define LINE_ZIO_D47 PAL_LINE(GPIOC, 12U) +#define LINE_SDMMC_CK PAL_LINE(GPIOC, 12U) +#define LINE_BUTTON PAL_LINE(GPIOC, 13U) +#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) +#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) + +#define LINE_ZIO_D67 PAL_LINE(GPIOD, 0U) +#define LINE_CAN1_RX PAL_LINE(GPIOD, 0U) +#define LINE_ZIO_D66 PAL_LINE(GPIOD, 1U) +#define LINE_CAN1_TX PAL_LINE(GPIOD, 1U) +#define LINE_ZIO_D48 PAL_LINE(GPIOD, 2U) +#define LINE_SDMMC_CMD PAL_LINE(GPIOD, 2U) +#define LINE_ZIO_D55 PAL_LINE(GPIOD, 3U) +#define LINE_USART2_CTS PAL_LINE(GPIOD, 3U) +#define LINE_ZIO_D54 PAL_LINE(GPIOD, 4U) +#define LINE_USART2_RTS PAL_LINE(GPIOD, 4U) +#define LINE_ZIO_D53 PAL_LINE(GPIOD, 5U) +#define LINE_USART2_TX PAL_LINE(GPIOD, 5U) +#define LINE_ZIO_D52 PAL_LINE(GPIOD, 6U) +#define LINE_USART2_RX PAL_LINE(GPIOD, 6U) +#define LINE_ZIO_D51 PAL_LINE(GPIOD, 7U) +#define LINE_USART2_SCLK PAL_LINE(GPIOD, 7U) +#define LINE_USART3_RX PAL_LINE(GPIOD, 8U) +#define LINE_STLK_RX PAL_LINE(GPIOD, 8U) +#define LINE_USART3_TX PAL_LINE(GPIOD, 9U) +#define LINE_STLK_TX PAL_LINE(GPIOD, 9U) +#define LINE_ZIO_D30 PAL_LINE(GPIOD, 11U) +#define LINE_QSPI_BK1_IO0 PAL_LINE(GPIOD, 11U) +#define LINE_ZIO_D29 PAL_LINE(GPIOD, 12U) +#define LINE_QSPI_BK1_IO1 PAL_LINE(GPIOD, 12U) +#define LINE_ZIO_D28 PAL_LINE(GPIOD, 13U) +#define LINE_QSPI_BK1_IO3 PAL_LINE(GPIOD, 13U) +#define LINE_ARD_D10 PAL_LINE(GPIOD, 14U) +#define LINE_SPI1_NSS PAL_LINE(GPIOD, 14U) +#define LINE_ARD_D9 PAL_LINE(GPIOD, 15U) +#define LINE_TIM4_CH4 PAL_LINE(GPIOD, 15U) + +#define LINE_ZIO_D34 PAL_LINE(GPIOE, 0U) +#define LINE_TIM4_ETR PAL_LINE(GPIOE, 0U) +#define LINE_ZIO_D31 PAL_LINE(GPIOE, 2U) +#define LINE_ZIO_D56 PAL_LINE(GPIOE, 2U) +#define LINE_SAI1_MCLK_A PAL_LINE(GPIOE, 2U) +#define LINE_ZIO_D60 PAL_LINE(GPIOE, 3U) +#define LINE_SAI1_SD_B PAL_LINE(GPIOE, 3U) +#define LINE_ZIO_D57 PAL_LINE(GPIOE, 4U) +#define LINE_SAI1_FS_A PAL_LINE(GPIOE, 4U) +#define LINE_ZIO_D58 PAL_LINE(GPIOE, 5U) +#define LINE_SAI1_SCK_A PAL_LINE(GPIOE, 5U) +#define LINE_ZIO_D59 PAL_LINE(GPIOE, 6U) +#define LINE_SAI1_SD_A PAL_LINE(GPIOE, 6U) +#define LINE_ZIO_D41 PAL_LINE(GPIOE, 7U) +#define LINE_TIM1_ETR PAL_LINE(GPIOE, 7U) +#define LINE_ZIO_D42 PAL_LINE(GPIOE, 8U) +#define LINE_TIM1_CH1N PAL_LINE(GPIOE, 8U) +#define LINE_ARD_D6 PAL_LINE(GPIOE, 9U) +#define LINE_TIM1_CH1 PAL_LINE(GPIOE, 9U) +#define LINE_ZIO_D40 PAL_LINE(GPIOE, 10U) +#define LINE_TIM1_CH2N PAL_LINE(GPIOE, 10U) +#define LINE_ARD_D5 PAL_LINE(GPIOE, 11U) +#define LINE_TIM1_CH2 PAL_LINE(GPIOE, 11U) +#define LINE_ZIO_D39 PAL_LINE(GPIOE, 12U) +#define LINE_TIM1_CH3N PAL_LINE(GPIOE, 12U) +#define LINE_ARD_D3 PAL_LINE(GPIOE, 13U) +#define LINE_TIM1_CH3 PAL_LINE(GPIOE, 13U) +#define LINE_ZIO_D38 PAL_LINE(GPIOE, 14U) +#define LINE_ZIO_D37 PAL_LINE(GPIOE, 15U) +#define LINE_TIM1_BKIN1 PAL_LINE(GPIOE, 15U) + +#define LINE_ZIO_D68 PAL_LINE(GPIOF, 0U) +#define LINE_I2C2_SDA PAL_LINE(GPIOF, 0U) +#define LINE_ZIO_D69 PAL_LINE(GPIOF, 1U) +#define LINE_I2C2_SCL PAL_LINE(GPIOF, 1U) +#define LINE_ZIO_D70 PAL_LINE(GPIOF, 2U) +#define LINE_I2C2_SMBA PAL_LINE(GPIOF, 2U) +#define LINE_ARD_A3 PAL_LINE(GPIOF, 3U) +#define LINE_ADC3_IN9 PAL_LINE(GPIOF, 3U) +#define LINE_ZIO_A8 PAL_LINE(GPIOF, 4U) +#define LINE_ADC3_IN14 PAL_LINE(GPIOF, 4U) +#define LINE_ARD_A4 PAL_LINE(GPIOF, 5U) +#define LINE_ADC3_IN15 PAL_LINE(GPIOF, 5U) +#define LINE_ZIO_D62 PAL_LINE(GPIOF, 7U) +#define LINE_SAI1_MCLK_B PAL_LINE(GPIOF, 7U) +#define LINE_ZIO_D61 PAL_LINE(GPIOF, 8U) +#define LINE_SAI1_SCK_B PAL_LINE(GPIOF, 8U) +#define LINE_ZIO_D63 PAL_LINE(GPIOF, 9U) +#define LINE_SAI1_FS_B PAL_LINE(GPIOF, 9U) +#define LINE_ARD_A5 PAL_LINE(GPIOF, 10U) +#define LINE_ADC3_IN8 PAL_LINE(GPIOF, 10U) +#define LINE_ARD_D8 PAL_LINE(GPIOF, 12U) +#define LINE_ARD_D7 PAL_LINE(GPIOF, 13U) +#define LINE_ARD_D4 PAL_LINE(GPIOF, 14U) +#define LINE_ARD_D2 PAL_LINE(GPIOF, 15U) + +#define LINE_ZIO_D65 PAL_LINE(GPIOG, 0U) +#define LINE_ZIO_D64 PAL_LINE(GPIOG, 1U) +#define LINE_ZIO_D49 PAL_LINE(GPIOG, 2U) +#define LINE_ZIO_D50 PAL_LINE(GPIOG, 3U) +#define LINE_USB_GPIO_OUT PAL_LINE(GPIOG, 6U) +#define LINE_USB_GPIO_IN PAL_LINE(GPIOG, 7U) +#define LINE_ARD_D0 PAL_LINE(GPIOG, 9U) +#define LINE_USART6_RX PAL_LINE(GPIOG, 9U) +#define LINE_RMII_TX_EN PAL_LINE(GPIOG, 11U) +#define LINE_RMII_TXD0 PAL_LINE(GPIOG, 13U) +#define LINE_ARD_D1 PAL_LINE(GPIOG, 14U) +#define LINE_USART6_TX PAL_LINE(GPIOG, 14U) + +#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) +#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) + + + + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * GPIOA setup: + * + * PA0 - ZIO_D32 TIM2_CH1 (input pullup). + * PA1 - RMII_REF_CLK (alternate 11). + * PA2 - RMII_MDIO (alternate 11). + * PA3 - ARD_A0 ADC123_IN3 (input pullup). + * PA4 - ZIO_D24 SPI3_NSS (input pullup). + * PA5 - ARD_D13 (input pullup). + * PA6 - ARD_D12 (input pullup). + * PA7 - RMII_CRS_DV (alternate 11). + * PA8 - USB_SOF (alternate 10). + * PA9 - USB_VBUS (analog). + * PA10 - USB_ID (alternate 10). + * PA11 - USB_DM (alternate 10). + * PA12 - USB_DP (alternate 10). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - ZIO_D20 I2S3_WS (input pullup). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_ZIO_D32) | \ + PIN_MODE_ALTERNATE(GPIOA_RMII_REF_CLK) |\ + PIN_MODE_ALTERNATE(GPIOA_RMII_MDIO) | \ + PIN_MODE_INPUT(GPIOA_ARD_A0) | \ + PIN_MODE_INPUT(GPIOA_ZIO_D24) | \ + PIN_MODE_INPUT(GPIOA_ARD_D13) | \ + PIN_MODE_INPUT(GPIOA_ARD_D12) | \ + PIN_MODE_ALTERNATE(GPIOA_RMII_CRS_DV) |\ + PIN_MODE_ALTERNATE(GPIOA_USB_SOF) | \ + PIN_MODE_ANALOG(GPIOA_USB_VBUS) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_ID) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_USB_DP) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_INPUT(GPIOA_ZIO_D20)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ZIO_D32) | \ + PIN_OTYPE_PUSHPULL(GPIOA_RMII_REF_CLK) |\ + PIN_OTYPE_PUSHPULL(GPIOA_RMII_MDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ZIO_D24) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D13) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D12) | \ + PIN_OTYPE_PUSHPULL(GPIOA_RMII_CRS_DV) |\ + PIN_OTYPE_PUSHPULL(GPIOA_USB_SOF) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_VBUS) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_ID) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USB_DP) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ZIO_D20)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ZIO_D32) | \ + PIN_OSPEED_HIGH(GPIOA_RMII_REF_CLK) | \ + PIN_OSPEED_HIGH(GPIOA_RMII_MDIO) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \ + PIN_OSPEED_HIGH(GPIOA_ZIO_D24) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D13) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D12) | \ + PIN_OSPEED_VERYLOW(GPIOA_RMII_CRS_DV) |\ + PIN_OSPEED_HIGH(GPIOA_USB_SOF) | \ + PIN_OSPEED_HIGH(GPIOA_USB_VBUS) | \ + PIN_OSPEED_HIGH(GPIOA_USB_ID) | \ + PIN_OSPEED_HIGH(GPIOA_USB_DM) | \ + PIN_OSPEED_HIGH(GPIOA_USB_DP) | \ + PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ + PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ + PIN_OSPEED_HIGH(GPIOA_ZIO_D20)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_ZIO_D32) | \ + PIN_PUPDR_FLOATING(GPIOA_RMII_REF_CLK) |\ + PIN_PUPDR_PULLUP(GPIOA_RMII_MDIO) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_A0) | \ + PIN_PUPDR_PULLUP(GPIOA_ZIO_D24) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D13) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D12) | \ + PIN_PUPDR_FLOATING(GPIOA_RMII_CRS_DV) |\ + PIN_PUPDR_FLOATING(GPIOA_USB_SOF) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_VBUS) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_ID) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_DM) | \ + PIN_PUPDR_FLOATING(GPIOA_USB_DP) | \ + PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \ + PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \ + PIN_PUPDR_PULLUP(GPIOA_ZIO_D20)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_ZIO_D32) | \ + PIN_ODR_HIGH(GPIOA_RMII_REF_CLK) | \ + PIN_ODR_HIGH(GPIOA_RMII_MDIO) | \ + PIN_ODR_HIGH(GPIOA_ARD_A0) | \ + PIN_ODR_HIGH(GPIOA_ZIO_D24) | \ + PIN_ODR_HIGH(GPIOA_ARD_D13) | \ + PIN_ODR_HIGH(GPIOA_ARD_D12) | \ + PIN_ODR_HIGH(GPIOA_RMII_CRS_DV) | \ + PIN_ODR_HIGH(GPIOA_USB_SOF) | \ + PIN_ODR_HIGH(GPIOA_USB_VBUS) | \ + PIN_ODR_HIGH(GPIOA_USB_ID) | \ + PIN_ODR_HIGH(GPIOA_USB_DM) | \ + PIN_ODR_HIGH(GPIOA_USB_DP) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_ZIO_D20)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ZIO_D32, 0U) | \ + PIN_AFIO_AF(GPIOA_RMII_REF_CLK, 11U) | \ + PIN_AFIO_AF(GPIOA_RMII_MDIO, 11U) | \ + PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \ + PIN_AFIO_AF(GPIOA_ZIO_D24, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D13, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D12, 0U) | \ + PIN_AFIO_AF(GPIOA_RMII_CRS_DV, 11U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_USB_SOF, 10U) | \ + PIN_AFIO_AF(GPIOA_USB_VBUS, 0U) | \ + PIN_AFIO_AF(GPIOA_USB_ID, 10U) | \ + PIN_AFIO_AF(GPIOA_USB_DM, 10U) | \ + PIN_AFIO_AF(GPIOA_USB_DP, 10U) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ + PIN_AFIO_AF(GPIOA_ZIO_D20, 0U)) + +/* + * GPIOB setup: + * + * PB0 - ZIO_D33 TIM3_CH3 LED1 (output pushpull maximum). + * PB1 - ZIO_A6 ADC12_IN9 (input pullup). + * PB2 - ZIO_D27 QSPI_CLK (input pullup). + * PB3 - ZIO_D23 I2S3_CK (input pullup). + * PB4 - ZIO_D25 SPI3_MISO (input pullup). + * PB5 - ZIO_D22 I2S3_SD (input pullup). + * PB6 - ZIO_D26 QSPI_BK1_NCS (input pullup). + * PB7 - LED2 (output pushpull maximum). + * PB8 - ARD_D15 I2C1_SCL (input pullup). + * PB9 - ARD_D14 I2C1_SDA (input pullup). + * PB10 - ZIO_D36 TIM2_CH3 (input pullup). + * PB11 - ZIO_D35 TIM2_CH4 (input pullup). + * PB12 - ZIO_D19 I2S2_WS (input pullup). + * PB13 - ZIO_D18 I2S2_CK RMII_TXD1 (alternate 11). + * PB14 - LED3 (output pushpull maximum). + * PB15 - ZIO_D17 I2S2_SD (input pullup). + */ +#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_ZIO_D33) | \ + PIN_MODE_INPUT(GPIOB_ZIO_A6) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D27) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D23) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D25) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D22) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D26) | \ + PIN_MODE_OUTPUT(GPIOB_LED2) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D36) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D35) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D19) | \ + PIN_MODE_ALTERNATE(GPIOB_RMII_TXD1) | \ + PIN_MODE_OUTPUT(GPIOB_LED3) | \ + PIN_MODE_INPUT(GPIOB_ZIO_D17)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D33) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_A6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D27) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D23) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D25) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D22) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D26) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LED2) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D36) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D35) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D19) | \ + PIN_OTYPE_PUSHPULL(GPIOB_RMII_TXD1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_LED3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ZIO_D17)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ZIO_D33) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_A6) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D27) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D23) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D25) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D22) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D26) | \ + PIN_OSPEED_HIGH(GPIOB_LED2) | \ + PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ + PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D36) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D35) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D19) | \ + PIN_OSPEED_HIGH(GPIOB_RMII_TXD1) | \ + PIN_OSPEED_HIGH(GPIOB_LED3) | \ + PIN_OSPEED_HIGH(GPIOB_ZIO_D17)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_ZIO_D33) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_A6) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D27) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D23) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D25) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D22) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D26) | \ + PIN_PUPDR_FLOATING(GPIOB_LED2) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D36) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D35) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D19) | \ + PIN_PUPDR_FLOATING(GPIOB_RMII_TXD1) | \ + PIN_PUPDR_FLOATING(GPIOB_LED3) | \ + PIN_PUPDR_PULLUP(GPIOB_ZIO_D17)) +#define VAL_GPIOB_ODR (PIN_ODR_LOW(GPIOB_ZIO_D33) | \ + PIN_ODR_HIGH(GPIOB_ZIO_A6) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D27) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D23) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D25) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D22) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D26) | \ + PIN_ODR_LOW(GPIOB_LED2) | \ + PIN_ODR_LOW(GPIOB_I2C1_SCL) | \ + PIN_ODR_LOW(GPIOB_I2C1_SDA) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D36) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D35) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D19) | \ + PIN_ODR_HIGH(GPIOB_RMII_TXD1) | \ + PIN_ODR_LOW(GPIOB_LED3) | \ + PIN_ODR_HIGH(GPIOB_ZIO_D17)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ZIO_D33, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_A6, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D27, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D23, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D25, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D22, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D26, 0U) | \ + PIN_AFIO_AF(GPIOB_LED2, 0U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4U) | \ + PIN_AFIO_AF(GPIOB_I2C1_SDA, 4U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D36, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D35, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D19, 0U) | \ + PIN_AFIO_AF(GPIOB_RMII_TXD1, 11U) | \ + PIN_AFIO_AF(GPIOB_LED3, 0U) | \ + PIN_AFIO_AF(GPIOB_ZIO_D17, 0U)) + +/* + * GPIOC setup: + * + * PC0 - ARD_A1 ADC123_IN10 (input pullup). + * PC1 - RMII_MDC (alternate 11). + * PC2 - ZIO_A7 ADC123_IN12 (input pullup). + * PC3 - ARD_A2 ADC123_IN13 (input pullup). + * PC4 - RMII_RXD0 (alternate 11). + * PC5 - RMII_RXD1 (alternate 11). + * PC6 - ZIO_D16 I2S2_MCK (input pullup). + * PC7 - ZIO_D21 I2S3_MCK (input pullup). + * PC8 - ZIO_D43 SDMMC_D0 (input pullup). + * PC9 - ZIO_D44 SDMMC_D1 (input pullup). + * PC10 - ZIO_D45 SDMMC_D2 (input pullup). + * PC11 - ZIO_D46 SDMMC_D3 (input pullup). + * PC12 - ZIO_D47 SDMMC_CK (input pullup). + * PC13 - BUTTON (input floating). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_ARD_A1) | \ + PIN_MODE_ALTERNATE(GPIOC_RMII_MDC) | \ + PIN_MODE_INPUT(GPIOC_ZIO_A7) | \ + PIN_MODE_INPUT(GPIOC_ARD_A2) | \ + PIN_MODE_ALTERNATE(GPIOC_RMII_RXD0) | \ + PIN_MODE_ALTERNATE(GPIOC_RMII_RXD1) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D16) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D21) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D43) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D44) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D45) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D46) | \ + PIN_MODE_INPUT(GPIOC_ZIO_D47) | \ + PIN_MODE_INPUT(GPIOC_BUTTON) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ARD_A1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_RMII_MDC) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_A7) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_A2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D16) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D21) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D43) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D44) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D45) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D46) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ZIO_D47) | \ + PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ARD_A1) | \ + PIN_OSPEED_HIGH(GPIOC_RMII_MDC) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_A7) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_A2) | \ + PIN_OSPEED_HIGH(GPIOC_RMII_RXD0) | \ + PIN_OSPEED_HIGH(GPIOC_RMII_RXD1) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D16) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D21) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D43) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D44) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D45) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D46) | \ + PIN_OSPEED_HIGH(GPIOC_ZIO_D47) | \ + PIN_OSPEED_HIGH(GPIOC_BUTTON) | \ + PIN_OSPEED_VERYLOW(GPIOC_OSC32_IN) | \ + PIN_OSPEED_VERYLOW(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_ARD_A1) | \ + PIN_PUPDR_FLOATING(GPIOC_RMII_MDC) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_A7) | \ + PIN_PUPDR_PULLUP(GPIOC_ARD_A2) | \ + PIN_PUPDR_FLOATING(GPIOC_RMII_RXD0) | \ + PIN_PUPDR_FLOATING(GPIOC_RMII_RXD1) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D16) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D21) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D43) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D44) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D45) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D46) | \ + PIN_PUPDR_PULLUP(GPIOC_ZIO_D47) | \ + PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_ARD_A1) | \ + PIN_ODR_HIGH(GPIOC_RMII_MDC) | \ + PIN_ODR_HIGH(GPIOC_ZIO_A7) | \ + PIN_ODR_HIGH(GPIOC_ARD_A2) | \ + PIN_ODR_HIGH(GPIOC_RMII_RXD0) | \ + PIN_ODR_HIGH(GPIOC_RMII_RXD1) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D16) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D21) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D43) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D44) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D45) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D46) | \ + PIN_ODR_HIGH(GPIOC_ZIO_D47) | \ + PIN_ODR_HIGH(GPIOC_BUTTON) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ARD_A1, 0U) | \ + PIN_AFIO_AF(GPIOC_RMII_MDC, 11U) | \ + PIN_AFIO_AF(GPIOC_ZIO_A7, 0U) | \ + PIN_AFIO_AF(GPIOC_ARD_A2, 0U) | \ + PIN_AFIO_AF(GPIOC_RMII_RXD0, 11U) | \ + PIN_AFIO_AF(GPIOC_RMII_RXD1, 11U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D16, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D21, 0U)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_ZIO_D43, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D44, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D45, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D46, 0U) | \ + PIN_AFIO_AF(GPIOC_ZIO_D47, 0U) | \ + PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) + +/* + * GPIOD setup: + * + * PD0 - ZIO_D67 CAN1_RX (input pullup). + * PD1 - ZIO_D66 CAN1_TX (input pullup). + * PD2 - ZIO_D48 SDMMC_CMD (input pullup). + * PD3 - ZIO_D55 USART2_CTS (input pullup). + * PD4 - ZIO_D54 USART2_RTS (input pullup). + * PD5 - ZIO_D53 USART2_TX (input pullup). + * PD6 - ZIO_D52 USART2_RX (input pullup). + * PD7 - ZIO_D51 USART2_SCLK (input pullup). + * PD8 - USART3_RX STLK_RX (alternate 7). + * PD9 - USART3_TX STLK_TX (alternate 7). + * PD10 - PIN10 (input pullup). + * PD11 - ZIO_D30 QSPI_BK1_IO0 (input pullup). + * PD12 - ZIO_D29 QSPI_BK1_IO1 (input pullup). + * PD13 - ZIO_D28 QSPI_BK1_IO3 (input pullup). + * PD14 - ARD_D10 SPI1_NSS (input pullup). + * PD15 - ARD_D9 TIM4_CH4 (input pullup). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_ZIO_D67) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D66) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D48) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D55) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D54) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D53) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D52) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D51) | \ + PIN_MODE_ALTERNATE(GPIOD_USART3_RX) | \ + PIN_MODE_ALTERNATE(GPIOD_USART3_TX) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D30) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D29) | \ + PIN_MODE_INPUT(GPIOD_ZIO_D28) | \ + PIN_MODE_INPUT(GPIOD_ARD_D10) | \ + PIN_MODE_INPUT(GPIOD_ARD_D9)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D67) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D66) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D48) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D55) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D54) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D53) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D52) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D51) | \ + PIN_OTYPE_PUSHPULL(GPIOD_USART3_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_USART3_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D30) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D29) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ZIO_D28) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ARD_D10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_ARD_D9)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_ZIO_D67) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D66) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D48) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D55) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D54) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D53) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D52) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D51) | \ + PIN_OSPEED_HIGH(GPIOD_USART3_RX) | \ + PIN_OSPEED_HIGH(GPIOD_USART3_TX) | \ + PIN_OSPEED_VERYLOW(GPIOD_PIN10) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D30) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D29) | \ + PIN_OSPEED_HIGH(GPIOD_ZIO_D28) | \ + PIN_OSPEED_HIGH(GPIOD_ARD_D10) | \ + PIN_OSPEED_HIGH(GPIOD_ARD_D9)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_ZIO_D67) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D66) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D48) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D55) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D54) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D53) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D52) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D51) | \ + PIN_PUPDR_FLOATING(GPIOD_USART3_RX) | \ + PIN_PUPDR_FLOATING(GPIOD_USART3_TX) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D30) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D29) | \ + PIN_PUPDR_PULLUP(GPIOD_ZIO_D28) | \ + PIN_PUPDR_PULLUP(GPIOD_ARD_D10) | \ + PIN_PUPDR_PULLUP(GPIOD_ARD_D9)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_ZIO_D67) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D66) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D48) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D55) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D54) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D53) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D52) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D51) | \ + PIN_ODR_HIGH(GPIOD_USART3_RX) | \ + PIN_ODR_HIGH(GPIOD_USART3_TX) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D30) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D29) | \ + PIN_ODR_HIGH(GPIOD_ZIO_D28) | \ + PIN_ODR_HIGH(GPIOD_ARD_D10) | \ + PIN_ODR_HIGH(GPIOD_ARD_D9)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_ZIO_D67, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D66, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D48, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D55, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D54, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D53, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D52, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D51, 0U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_USART3_RX, 7U) | \ + PIN_AFIO_AF(GPIOD_USART3_TX, 7U) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D30, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D29, 0U) | \ + PIN_AFIO_AF(GPIOD_ZIO_D28, 0U) | \ + PIN_AFIO_AF(GPIOD_ARD_D10, 0U) | \ + PIN_AFIO_AF(GPIOD_ARD_D9, 0U)) + +/* + * GPIOE setup: + * + * PE0 - ZIO_D34 TIM4_ETR (input pullup). + * PE1 - PIN1 (input pullup). + * PE2 - ZIO_D31 ZIO_D56 SAI1_MCLK_A(input pullup). + * PE3 - ZIO_D60 SAI1_SD_B (input pullup). + * PE4 - ZIO_D57 SAI1_FS_A (input pullup). + * PE5 - ZIO_D58 SAI1_SCK_A (input pullup). + * PE6 - ZIO_D59 SAI1_SD_A (input pullup). + * PE7 - ZIO_D41 TIM1_ETR (input pullup). + * PE8 - ZIO_D42 TIM1_CH1N (input pullup). + * PE9 - ARD_D6 TIM1_CH1 (input pullup). + * PE10 - ZIO_D40 TIM1_CH2N (input pullup). + * PE11 - ARD_D5 TIM1_CH2 (input pullup). + * PE12 - ZIO_D39 TIM1_CH3N (input pullup). + * PE13 - ARD_D3 TIM1_CH3 (input pullup). + * PE14 - ZIO_D38 (input pullup). + * PE15 - ZIO_D37 TIM1_BKIN1 (input pullup). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_ZIO_D34) | \ + PIN_MODE_INPUT(GPIOE_PIN1) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D31) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D60) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D57) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D58) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D59) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D41) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D42) | \ + PIN_MODE_INPUT(GPIOE_ARD_D6) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D40) | \ + PIN_MODE_INPUT(GPIOE_ARD_D5) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D39) | \ + PIN_MODE_INPUT(GPIOE_ARD_D3) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D38) | \ + PIN_MODE_INPUT(GPIOE_ZIO_D37)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D34) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D31) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D60) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D57) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D58) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D59) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D41) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D42) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ARD_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D40) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ARD_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D39) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ARD_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D38) | \ + PIN_OTYPE_PUSHPULL(GPIOE_ZIO_D37)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_ZIO_D34) | \ + PIN_OSPEED_VERYLOW(GPIOE_PIN1) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D31) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D60) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D57) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D58) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D59) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D41) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D42) | \ + PIN_OSPEED_HIGH(GPIOE_ARD_D6) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D40) | \ + PIN_OSPEED_HIGH(GPIOE_ARD_D5) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D39) | \ + PIN_OSPEED_HIGH(GPIOE_ARD_D3) | \ + PIN_OSPEED_VERYLOW(GPIOE_ZIO_D38) | \ + PIN_OSPEED_HIGH(GPIOE_ZIO_D37)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_ZIO_D34) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D31) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D60) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D57) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D58) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D59) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D41) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D42) | \ + PIN_PUPDR_PULLUP(GPIOE_ARD_D6) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D40) | \ + PIN_PUPDR_PULLUP(GPIOE_ARD_D5) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D39) | \ + PIN_PUPDR_PULLUP(GPIOE_ARD_D3) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D38) | \ + PIN_PUPDR_PULLUP(GPIOE_ZIO_D37)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_ZIO_D34) | \ + PIN_ODR_HIGH(GPIOE_PIN1) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D31) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D60) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D57) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D58) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D59) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D41) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D42) | \ + PIN_ODR_HIGH(GPIOE_ARD_D6) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D40) | \ + PIN_ODR_HIGH(GPIOE_ARD_D5) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D39) | \ + PIN_ODR_HIGH(GPIOE_ARD_D3) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D38) | \ + PIN_ODR_HIGH(GPIOE_ZIO_D37)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_ZIO_D34, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D31, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D60, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D57, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D58, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D59, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D41, 0U)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_ZIO_D42, 0U) | \ + PIN_AFIO_AF(GPIOE_ARD_D6, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D40, 0U) | \ + PIN_AFIO_AF(GPIOE_ARD_D5, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D39, 0U) | \ + PIN_AFIO_AF(GPIOE_ARD_D3, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D38, 0U) | \ + PIN_AFIO_AF(GPIOE_ZIO_D37, 0U)) + +/* + * GPIOF setup: + * + * PF0 - ZIO_D68 I2C2_SDA (input pullup). + * PF1 - ZIO_D69 I2C2_SCL (input pullup). + * PF2 - ZIO_D70 I2C2_SMBA (input pullup). + * PF3 - ARD_A3 ADC3_IN9 (input pullup). + * PF4 - ZIO_A8 ADC3_IN14 (input pullup). + * PF5 - ARD_A4 ADC3_IN15 (input pullup). + * PF6 - PIN6 (input pullup). + * PF7 - SPI5_SCK (Alternate 5). + * PF8 - SPI5_MISO (Alternate 5). + * PF9 - SPI5_MOSI (Alternate 5). + * PF10 - ARD_A5 ADC3_IN8 (input pullup). + * PF11 - PIN11 (input pullup). + * PF12 - ARD_D8 (input pullup). + * PF13 - ARD_D7 (input pullup). + * PF14 - ARD_D4 (input pullup). + * PF15 - ARD_D2 (input pullup). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_ZIO_D68) | \ + PIN_MODE_INPUT(GPIOF_ZIO_D69) | \ + PIN_MODE_INPUT(GPIOF_ZIO_D70) | \ + PIN_MODE_INPUT(GPIOF_ARD_A3) | \ + PIN_MODE_INPUT(GPIOF_ZIO_A8) | \ + PIN_MODE_INPUT(GPIOF_ARD_A4) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_ALTERNATE(GPIOF_SPI5_SCK) | \ + PIN_MODE_ALTERNATE(GPIOF_SPI5_MISO) | \ + PIN_MODE_ALTERNATE(GPIOF_SPI5_MOSI) | \ + PIN_MODE_INPUT(GPIOF_ARD_A5) | \ + PIN_MODE_INPUT(GPIOF_PIN11) | \ + PIN_MODE_INPUT(GPIOF_ARD_D8) | \ + PIN_MODE_INPUT(GPIOF_ARD_D7) | \ + PIN_MODE_INPUT(GPIOF_ARD_D4) | \ + PIN_MODE_INPUT(GPIOF_ARD_D2)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D68) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D69) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ZIO_D70) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_A3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ZIO_A8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_A4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_SPI5_SCK) | \ + PIN_OTYPE_PUSHPULL(GPIOF_SPI5_MISO) | \ + PIN_OTYPE_PUSHPULL(GPIOF_SPI5_MOSI) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_A5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D2)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_ZIO_D68) | \ + PIN_OSPEED_HIGH(GPIOF_ZIO_D69) | \ + PIN_OSPEED_HIGH(GPIOF_ZIO_D70) | \ + PIN_OSPEED_HIGH(GPIOF_ARD_A3) | \ + PIN_OSPEED_HIGH(GPIOF_ZIO_A8) | \ + PIN_OSPEED_HIGH(GPIOF_ARD_A4) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN6) | \ + PIN_OSPEED_HIGH(GPIOF_SPI5_SCK) | \ + PIN_OSPEED_HIGH(GPIOF_SPI5_MISO) | \ + PIN_OSPEED_HIGH(GPIOF_SPI5_MOSI) | \ + PIN_OSPEED_HIGH(GPIOF_ARD_A5) | \ + PIN_OSPEED_VERYLOW(GPIOF_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOF_ARD_D8) | \ + PIN_OSPEED_VERYLOW(GPIOF_ARD_D7) | \ + PIN_OSPEED_VERYLOW(GPIOF_ARD_D4) | \ + PIN_OSPEED_VERYLOW(GPIOF_ARD_D2)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_ZIO_D68) | \ + PIN_PUPDR_PULLUP(GPIOF_ZIO_D69) | \ + PIN_PUPDR_PULLUP(GPIOF_ZIO_D70) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_A3) | \ + PIN_PUPDR_PULLUP(GPIOF_ZIO_A8) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_A4) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOF_SPI5_SCK) | \ + PIN_PUPDR_FLOATING(GPIOF_SPI5_MISO) | \ + PIN_PUPDR_FLOATING(GPIOF_SPI5_MOSI) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_A5) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D8) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D7) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D4) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D2)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_ZIO_D68) | \ + PIN_ODR_HIGH(GPIOF_ZIO_D69) | \ + PIN_ODR_HIGH(GPIOF_ZIO_D70) | \ + PIN_ODR_HIGH(GPIOF_ARD_A3) | \ + PIN_ODR_HIGH(GPIOF_ZIO_A8) | \ + PIN_ODR_HIGH(GPIOF_ARD_A4) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_SPI5_SCK) | \ + PIN_ODR_HIGH(GPIOF_SPI5_MISO) | \ + PIN_ODR_HIGH(GPIOF_SPI5_MOSI) | \ + PIN_ODR_HIGH(GPIOF_ARD_A5) | \ + PIN_ODR_HIGH(GPIOF_PIN11) | \ + PIN_ODR_HIGH(GPIOF_ARD_D8) | \ + PIN_ODR_HIGH(GPIOF_ARD_D7) | \ + PIN_ODR_HIGH(GPIOF_ARD_D4) | \ + PIN_ODR_HIGH(GPIOF_ARD_D2)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_ZIO_D68, 0U) | \ + PIN_AFIO_AF(GPIOF_ZIO_D69, 0U) | \ + PIN_AFIO_AF(GPIOF_ZIO_D70, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_A3, 0U) | \ + PIN_AFIO_AF(GPIOF_ZIO_A8, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_A4, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOF_SPI5_SCK, 5U)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_SPI5_MISO, 5U) | \ + PIN_AFIO_AF(GPIOF_SPI5_MOSI, 5U) | \ + PIN_AFIO_AF(GPIOF_ARD_A5, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_D8, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_D7, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_D4, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_D2, 0U)) + +/* + * GPIOG setup: + * + * PG0 - ZIO_D65 (input pullup). + * PG1 - ZIO_D64 (input pullup). + * PG2 - ZIO_D49 (input pullup). + * PG3 - ZIO_D50 (input pullup). + * PG4 - PIN4 (input pullup). + * PG5 - PIN5 (input pullup). + * PG6 - USB_GPIO_OUT (input pullup). + * PG7 - USB_GPIO_IN (input pullup). + * PG8 - PIN8 (input pullup). + * PG9 - ARD_D0 USART6_RX (input pullup). + * PG10 - PIN10 (input pullup). + * PG11 - RMII_TX_EN (alternate 11). + * PG12 - PIN12 (input pullup). + * PG13 - RMII_TXD0 (alternate 11). + * PG14 - ARD_D1 USART6_TX (input pullup). + * PG15 - PIN15 (input pullup). + */ +#define VAL_GPIOG_MODER (PIN_MODE_OUTPUT(GPIOG_ZIO_D65) | \ + PIN_MODE_OUTPUT(GPIOG_ZIO_D64) | \ + PIN_MODE_INPUT(GPIOG_ZIO_D49) | \ + PIN_MODE_INPUT(GPIOG_ZIO_D50) | \ + PIN_MODE_INPUT(GPIOG_PIN4) | \ + PIN_MODE_INPUT(GPIOG_PIN5) | \ + PIN_MODE_INPUT(GPIOG_USB_GPIO_OUT) | \ + PIN_MODE_INPUT(GPIOG_USB_GPIO_IN) | \ + PIN_MODE_INPUT(GPIOG_PIN8) | \ + PIN_MODE_INPUT(GPIOG_ARD_D0) | \ + PIN_MODE_INPUT(GPIOG_PIN10) | \ + PIN_MODE_ALTERNATE(GPIOG_RMII_TX_EN) | \ + PIN_MODE_INPUT(GPIOG_PIN12) | \ + PIN_MODE_ALTERNATE(GPIOG_RMII_TXD0) | \ + PIN_MODE_INPUT(GPIOG_ARD_D1) | \ + PIN_MODE_INPUT(GPIOG_PIN15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D65) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D64) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D49) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ZIO_D50) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOG_USB_GPIO_OUT) |\ + PIN_OTYPE_PUSHPULL(GPIOG_USB_GPIO_IN) |\ + PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ARD_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_RMII_TX_EN) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOG_RMII_TXD0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_ARD_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_ZIO_D65) | \ + PIN_OSPEED_HIGH(GPIOG_ZIO_D64) | \ + PIN_OSPEED_VERYLOW(GPIOG_ZIO_D49) | \ + PIN_OSPEED_VERYLOW(GPIOG_ZIO_D50) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN5) | \ + PIN_OSPEED_HIGH(GPIOG_USB_GPIO_OUT) | \ + PIN_OSPEED_HIGH(GPIOG_USB_GPIO_IN) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN8) | \ + PIN_OSPEED_HIGH(GPIOG_ARD_D0) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN10) | \ + PIN_OSPEED_HIGH(GPIOG_RMII_TX_EN) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN12) | \ + PIN_OSPEED_HIGH(GPIOG_RMII_TXD0) | \ + PIN_OSPEED_HIGH(GPIOG_ARD_D1) | \ + PIN_OSPEED_VERYLOW(GPIOG_PIN15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_ZIO_D65) | \ + PIN_PUPDR_PULLUP(GPIOG_ZIO_D64) | \ + PIN_PUPDR_PULLUP(GPIOG_ZIO_D49) | \ + PIN_PUPDR_PULLUP(GPIOG_ZIO_D50) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOG_USB_GPIO_OUT) | \ + PIN_PUPDR_PULLUP(GPIOG_USB_GPIO_IN) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOG_ARD_D0) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOG_RMII_TX_EN) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOG_RMII_TXD0) | \ + PIN_PUPDR_PULLUP(GPIOG_ARD_D1) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_ZIO_D65) | \ + PIN_ODR_HIGH(GPIOG_ZIO_D64) | \ + PIN_ODR_HIGH(GPIOG_ZIO_D49) | \ + PIN_ODR_HIGH(GPIOG_ZIO_D50) | \ + PIN_ODR_HIGH(GPIOG_PIN4) | \ + PIN_ODR_HIGH(GPIOG_PIN5) | \ + PIN_ODR_HIGH(GPIOG_USB_GPIO_OUT) | \ + PIN_ODR_HIGH(GPIOG_USB_GPIO_IN) | \ + PIN_ODR_HIGH(GPIOG_PIN8) | \ + PIN_ODR_HIGH(GPIOG_ARD_D0) | \ + PIN_ODR_HIGH(GPIOG_PIN10) | \ + PIN_ODR_HIGH(GPIOG_RMII_TX_EN) | \ + PIN_ODR_HIGH(GPIOG_PIN12) | \ + PIN_ODR_HIGH(GPIOG_RMII_TXD0) | \ + PIN_ODR_HIGH(GPIOG_ARD_D1) | \ + PIN_ODR_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_ZIO_D65, 0U) | \ + PIN_AFIO_AF(GPIOG_ZIO_D64, 0U) | \ + PIN_AFIO_AF(GPIOG_ZIO_D49, 0U) | \ + PIN_AFIO_AF(GPIOG_ZIO_D50, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOG_USB_GPIO_OUT, 0U) | \ + PIN_AFIO_AF(GPIOG_USB_GPIO_IN, 0U)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOG_ARD_D0, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOG_RMII_TX_EN, 11U) | \ + PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOG_RMII_TXD0, 11U) | \ + PIN_AFIO_AF(GPIOG_ARD_D1, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN15, 0U)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - PIN2 (input pullup). + * PH3 - PIN3 (input pullup). + * PH4 - PIN4 (input pullup). + * PH5 - PIN5 (input pullup). + * PH6 - PIN6 (input pullup). + * PH7 - PIN7 (input pullup). + * PH8 - PIN8 (input pullup). + * PH9 - PIN9 (input pullup). + * PH10 - PIN10 (input pullup). + * PH11 - PIN11 (input pullup). + * PH12 - PIN12 (input pullup). + * PH13 - PIN13 (input pullup). + * PH14 - PIN14 (input pullup). + * PH15 - PIN15 (input pullup). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOH_PIN2) | \ + PIN_MODE_INPUT(GPIOH_PIN3) | \ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_INPUT(GPIOH_PIN5) | \ + PIN_MODE_INPUT(GPIOH_PIN6) | \ + PIN_MODE_INPUT(GPIOH_PIN7) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ + PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0U)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0U)) + +/* + * GPIOI setup: + * + * PI0 - PIN0 (input pullup). + * PI1 - PIN1 (input pullup). + * PI2 - PIN2 (input pullup). + * PI3 - PIN3 (input pullup). + * PI4 - PIN4 (input pullup). + * PI5 - PIN5 (input pullup). + * PI6 - PIN6 (input pullup). + * PI7 - PIN7 (input pullup). + * PI8 - PIN8 (input pullup). + * PI9 - PIN9 (input pullup). + * PI10 - PIN10 (input pullup). + * PI11 - PIN11 (input pullup). + * PI12 - PIN12 (input pullup). + * PI13 - PIN13 (input pullup). + * PI14 - PIN14 (input pullup). + * PI15 - PIN15 (input pullup). + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ + PIN_MODE_INPUT(GPIOI_PIN1) | \ + PIN_MODE_INPUT(GPIOI_PIN2) | \ + PIN_MODE_INPUT(GPIOI_PIN3) | \ + PIN_MODE_INPUT(GPIOI_PIN4) | \ + PIN_MODE_INPUT(GPIOI_PIN5) | \ + PIN_MODE_INPUT(GPIOI_PIN6) | \ + PIN_MODE_INPUT(GPIOI_PIN7) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_INPUT(GPIOI_PIN9) | \ + PIN_MODE_INPUT(GPIOI_PIN10) | \ + PIN_MODE_INPUT(GPIOI_PIN11) | \ + PIN_MODE_INPUT(GPIOI_PIN12) | \ + PIN_MODE_INPUT(GPIOI_PIN13) | \ + PIN_MODE_INPUT(GPIOI_PIN14) | \ + PIN_MODE_INPUT(GPIOI_PIN15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOI_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOI_PIN15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ + PIN_ODR_HIGH(GPIOI_PIN1) | \ + PIN_ODR_HIGH(GPIOI_PIN2) | \ + PIN_ODR_HIGH(GPIOI_PIN3) | \ + PIN_ODR_HIGH(GPIOI_PIN4) | \ + PIN_ODR_HIGH(GPIOI_PIN5) | \ + PIN_ODR_HIGH(GPIOI_PIN6) | \ + PIN_ODR_HIGH(GPIOI_PIN7) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_PIN9) | \ + PIN_ODR_HIGH(GPIOI_PIN10) | \ + PIN_ODR_HIGH(GPIOI_PIN11) | \ + PIN_ODR_HIGH(GPIOI_PIN12) | \ + PIN_ODR_HIGH(GPIOI_PIN13) | \ + PIN_ODR_HIGH(GPIOI_PIN14) | \ + PIN_ODR_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN7, 0U)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN15, 0U)) + +/* + * GPIOJ setup: + * + * PJ0 - PIN0 (input pullup). + * PJ1 - PIN1 (input pullup). + * PJ2 - PIN2 (input pullup). + * PJ3 - PIN3 (input pullup). + * PJ4 - PIN4 (input pullup). + * PJ5 - PIN5 (input pullup). + * PJ6 - PIN6 (input pullup). + * PJ7 - PIN7 (input pullup). + * PJ8 - PIN8 (input pullup). + * PJ9 - PIN9 (input pullup). + * PJ10 - PIN10 (input pullup). + * PJ11 - PIN11 (input pullup). + * PJ12 - PIN12 (input pullup). + * PJ13 - PIN13 (input pullup). + * PJ14 - PIN14 (input pullup). + * PJ15 - PIN15 (input pullup). + */ +#define VAL_GPIOJ_MODER (PIN_MODE_INPUT(GPIOJ_PIN0) | \ + PIN_MODE_INPUT(GPIOJ_PIN1) | \ + PIN_MODE_INPUT(GPIOJ_PIN2) | \ + PIN_MODE_INPUT(GPIOJ_PIN3) | \ + PIN_MODE_INPUT(GPIOJ_PIN4) | \ + PIN_MODE_INPUT(GPIOJ_PIN5) | \ + PIN_MODE_INPUT(GPIOJ_PIN6) | \ + PIN_MODE_INPUT(GPIOJ_PIN7) | \ + PIN_MODE_INPUT(GPIOJ_PIN8) | \ + PIN_MODE_INPUT(GPIOJ_PIN9) | \ + PIN_MODE_INPUT(GPIOJ_PIN10) | \ + PIN_MODE_INPUT(GPIOJ_PIN11) | \ + PIN_MODE_INPUT(GPIOJ_PIN12) | \ + PIN_MODE_INPUT(GPIOJ_PIN13) | \ + PIN_MODE_INPUT(GPIOJ_PIN14) | \ + PIN_MODE_INPUT(GPIOJ_PIN15)) +#define VAL_GPIOJ_OTYPER (PIN_OTYPE_PUSHPULL(GPIOJ_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN15)) +#define VAL_GPIOJ_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOJ_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN15)) +#define VAL_GPIOJ_PUPDR (PIN_PUPDR_PULLUP(GPIOJ_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOJ_PIN15)) +#define VAL_GPIOJ_ODR (PIN_ODR_HIGH(GPIOJ_PIN0) | \ + PIN_ODR_HIGH(GPIOJ_PIN1) | \ + PIN_ODR_HIGH(GPIOJ_PIN2) | \ + PIN_ODR_HIGH(GPIOJ_PIN3) | \ + PIN_ODR_HIGH(GPIOJ_PIN4) | \ + PIN_ODR_HIGH(GPIOJ_PIN5) | \ + PIN_ODR_HIGH(GPIOJ_PIN6) | \ + PIN_ODR_HIGH(GPIOJ_PIN7) | \ + PIN_ODR_HIGH(GPIOJ_PIN8) | \ + PIN_ODR_HIGH(GPIOJ_PIN9) | \ + PIN_ODR_HIGH(GPIOJ_PIN10) | \ + PIN_ODR_HIGH(GPIOJ_PIN11) | \ + PIN_ODR_HIGH(GPIOJ_PIN12) | \ + PIN_ODR_HIGH(GPIOJ_PIN13) | \ + PIN_ODR_HIGH(GPIOJ_PIN14) | \ + PIN_ODR_HIGH(GPIOJ_PIN15)) +#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(GPIOJ_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN7, 0U)) +#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(GPIOJ_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN15, 0U)) + +/* + * GPIOK setup: + * + * PK0 - PIN0 (input pullup). + * PK1 - PIN1 (input pullup). + * PK2 - PIN2 (input pullup). + * PK3 - PIN3 (input pullup). + * PK4 - PIN4 (input pullup). + * PK5 - PIN5 (input pullup). + * PK6 - PIN6 (input pullup). + * PK7 - PIN7 (input pullup). + * PK8 - PIN8 (input pullup). + * PK9 - PIN9 (input pullup). + * PK10 - PIN10 (input pullup). + * PK11 - PIN11 (input pullup). + * PK12 - PIN12 (input pullup). + * PK13 - PIN13 (input pullup). + * PK14 - PIN14 (input pullup). + * PK15 - PIN15 (input pullup). + */ +#define VAL_GPIOK_MODER (PIN_MODE_INPUT(GPIOK_PIN0) | \ + PIN_MODE_INPUT(GPIOK_PIN1) | \ + PIN_MODE_INPUT(GPIOK_PIN2) | \ + PIN_MODE_INPUT(GPIOK_PIN3) | \ + PIN_MODE_INPUT(GPIOK_PIN4) | \ + PIN_MODE_INPUT(GPIOK_PIN5) | \ + PIN_MODE_INPUT(GPIOK_PIN6) | \ + PIN_MODE_INPUT(GPIOK_PIN7) | \ + PIN_MODE_INPUT(GPIOK_PIN8) | \ + PIN_MODE_INPUT(GPIOK_PIN9) | \ + PIN_MODE_INPUT(GPIOK_PIN10) | \ + PIN_MODE_INPUT(GPIOK_PIN11) | \ + PIN_MODE_INPUT(GPIOK_PIN12) | \ + PIN_MODE_INPUT(GPIOK_PIN13) | \ + PIN_MODE_INPUT(GPIOK_PIN14) | \ + PIN_MODE_INPUT(GPIOK_PIN15)) +#define VAL_GPIOK_OTYPER (PIN_OTYPE_PUSHPULL(GPIOK_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN15)) +#define VAL_GPIOK_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOK_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN15)) +#define VAL_GPIOK_PUPDR (PIN_PUPDR_PULLUP(GPIOK_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOK_PIN15)) +#define VAL_GPIOK_ODR (PIN_ODR_HIGH(GPIOK_PIN0) | \ + PIN_ODR_HIGH(GPIOK_PIN1) | \ + PIN_ODR_HIGH(GPIOK_PIN2) | \ + PIN_ODR_HIGH(GPIOK_PIN3) | \ + PIN_ODR_HIGH(GPIOK_PIN4) | \ + PIN_ODR_HIGH(GPIOK_PIN5) | \ + PIN_ODR_HIGH(GPIOK_PIN6) | \ + PIN_ODR_HIGH(GPIOK_PIN7) | \ + PIN_ODR_HIGH(GPIOK_PIN8) | \ + PIN_ODR_HIGH(GPIOK_PIN9) | \ + PIN_ODR_HIGH(GPIOK_PIN10) | \ + PIN_ODR_HIGH(GPIOK_PIN11) | \ + PIN_ODR_HIGH(GPIOK_PIN12) | \ + PIN_ODR_HIGH(GPIOK_PIN13) | \ + PIN_ODR_HIGH(GPIOK_PIN14) | \ + PIN_ODR_HIGH(GPIOK_PIN15)) +#define VAL_GPIOK_AFRL (PIN_AFIO_AF(GPIOK_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN7, 0U)) +#define VAL_GPIOK_AFRH (PIN_AFIO_AF(GPIOK_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN15, 0U)) + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/common/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/common/CMakeLists.txt new file mode 100644 index 00000000..7c21ff9b --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/common/CMakeLists.txt @@ -0,0 +1,13 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c") +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_ConfigurationManager.cpp") + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") + +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/common/Device_BlockStorage-DEBUG.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 00000000..b70530cd --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,106 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 32kB blocks +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 0 }, // 0x08000000 nanoBooter + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + { BlockRange_BLOCKTYPE_CONFIG , 1, 1 }, // 0x08008000 configuration block + /////////////////////////////////////////////////////////////////////////////////////// + + { BlockRange_BLOCKTYPE_CODE , 2, 3 } // 0x08010000 nanoCLR +}; + +//128kB block +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 0x08020000 nanoCLR +}; + +// 256kB blocks +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE, 0, 1 }, // 0x08040000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 2, 2 } // 0x080C0000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x8000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 1, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08040000, // start address for block region + 3, // total number of blocks in this region + 0x40000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00100000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/common/Device_BlockStorage.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/common/Device_BlockStorage.c new file mode 100644 index 00000000..eae99f09 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/common/Device_BlockStorage.c @@ -0,0 +1,106 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 32kB blocks +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 0 }, // 0x08000000 nanoBooter + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + { BlockRange_BLOCKTYPE_CONFIG , 1, 1 }, // 0x08008000 configuration block + /////////////////////////////////////////////////////////////////////////////////////// + + { BlockRange_BLOCKTYPE_CODE , 2, 3 } // 0x08010000 nanoCLR +}; + +//128kB block +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 0x08020000 nanoCLR +}; + +// 256kB blocks +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE, 0, 0 }, // 0x08040000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 1, 2 } // 0x08080000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x8000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 1, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08040000, // start address for block region + 3, // total number of blocks in this region + 0x40000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00100000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/common/serialcfg.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/common/serialcfg.h new file mode 100644 index 00000000..803da07a --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/common/serialcfg.h @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef SERIALCFG_H +#define SERIALCFG_H + +// define which serial driver the Wire Protocol will be using +#define SERIAL_DRIVER SD3 + +#endif /* SERIALCFG_H */ + +/** @} */ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/common/targetHAL_ConfigurationManager.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/common/targetHAL_ConfigurationManager.cpp new file mode 100644 index 00000000..178f6aa7 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/common/targetHAL_ConfigurationManager.cpp @@ -0,0 +1,35 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include + +// Default initialisation for Network interface config blocks +// strong implementation replacing ChibiOS 'weak' one +bool InitialiseNetworkDefaultConfig(HAL_Configuration_NetworkInterface * pconfig, uint32_t configurationIndex) +{ + (void)configurationIndex; + + // make sure the config block marker is set + memcpy(pconfig->Marker, c_MARKER_CONFIGURATION_NETWORK_V1, sizeof(c_MARKER_CONFIGURATION_NETWORK_V1)); + + pconfig->InterfaceType = NetworkInterfaceType_Ethernet; + pconfig->StartupAddressMode = AddressMode_DHCP; + pconfig->AutomaticDNS = 1; + pconfig->SpecificConfigId = 0; + + // set MAC address with ST provided MAC for development boards + // 00:80:E1:01:35:D1 + pconfig->MacAddress[0] = 0x00; + pconfig->MacAddress[1] = 0x80; + pconfig->MacAddress[2] = 0xE1; + pconfig->MacAddress[3] = 0x01; + pconfig->MacAddress[4] = 0x35; + pconfig->MacAddress[5] = 0xD1; + + return true; +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/lwipopts.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/lwipopts.h new file mode 100644 index 00000000..3e12c25e --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/lwipopts.h @@ -0,0 +1,2167 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2001-2004 Swedish Institute of Computer Science, All Rights Reserved +// See LICENSE file in the project root for full license information. +// +/** + * @file + * + * lwIP Options Configuration + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIPOPT_H__ +#define __LWIPOPT_H__ + + +#define _REENT_ONLY +#define set_errno(err) +#include +#include +#include + +/* + ----------------------------------------------- + ---------- Platform specific locking ---------- + ----------------------------------------------- +*/ + +/** + * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain + * critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#ifndef SYS_LIGHTWEIGHT_PROT +#define SYS_LIGHTWEIGHT_PROT 1 +#endif + +/** + * NO_SYS==1: Provides VERY minimal functionality. Otherwise, + * use lwIP facilities. + */ +#ifndef NO_SYS +#define NO_SYS 0 +#endif + +/** + * NO_SYS_NO_TIMERS==1: Drop support for sys_timeout when NO_SYS==1 + * Mainly for compatibility to old versions. + */ +#ifndef NO_SYS_NO_TIMERS +#define NO_SYS_NO_TIMERS 0 +#endif + +// empty on purpose +#define LWIP_TCPIP_THREAD_ALIVE() + +/** + * MEMCPY: override this if you have a faster implementation at hand than the + * one included in your C library + */ +#ifndef MEMCPY +#define MEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/** + * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a + * call to memcpy() if the length is known at compile time and is small. + */ +#ifndef SMEMCPY +#define SMEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/* + ------------------------------------ + ---------- Memory options ---------- + ------------------------------------ +*/ +/** + * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library + * instead of the lwip internal allocator. Can save code size if you + * already use it. + */ +#ifndef MEM_LIBC_MALLOC +#define MEM_LIBC_MALLOC 1 +#endif + +/** +* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator. +* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution +* speed and usage from interrupts! +*/ +#ifndef MEMP_MEM_MALLOC +#define MEMP_MEM_MALLOC 1 +#endif + +/** + * MEM_ALIGNMENT: should be set to the alignment of the CPU + * 4 byte alignment -> #define MEM_ALIGNMENT 4 + * 2 byte alignment -> #define MEM_ALIGNMENT 2 + */ +#ifndef MEM_ALIGNMENT +#define MEM_ALIGNMENT 4 +#endif + +/** + * MEM_SIZE: the size of the heap memory. If the application will send + * a lot of data that needs to be copied, this should be set high. + */ +#ifndef MEM_SIZE +#define MEM_SIZE (16 * 1024) +#endif + +/** + * MEMP_SEPARATE_POOLS: if defined to 1, each pool is placed in its own array. + * This can be used to individually change the location of each pool. + * Default is one big array for all pools + */ +#ifndef MEMP_SEPARATE_POOLS +#define MEMP_SEPARATE_POOLS 0 +#endif + +/** + * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable + * amount of bytes before and after each memp element in every pool and fills + * it with a prominent default value. + * MEMP_OVERFLOW_CHECK == 0 no checking + * MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed + * MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time + * memp_malloc() or memp_free() is called (useful but slow!) + */ +#ifndef MEMP_OVERFLOW_CHECK +#define MEMP_OVERFLOW_CHECK 0 +#endif + +/** + * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make + * sure that there are no cycles in the linked lists. + */ +#ifndef MEMP_SANITY_CHECK +#define MEMP_SANITY_CHECK 0 +#endif + +/** + * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set + * of memory pools of various sizes. When mem_malloc is called, an element of + * the smallest pool that can provide the length needed is returned. + * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled. + */ +#ifndef MEM_USE_POOLS +#define MEM_USE_POOLS 0 +#endif + +/** + * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next + * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more + * reliable. */ +#ifndef MEM_USE_POOLS_TRY_BIGGER_POOL +#define MEM_USE_POOLS_TRY_BIGGER_POOL 0 +#endif + +/** + * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h + * that defines additional pools beyond the "standard" ones required + * by lwIP. If you set this to 1, you must have lwippools.h in your + * inlude path somewhere. + */ +#ifndef MEMP_USE_CUSTOM_POOLS +#define MEMP_USE_CUSTOM_POOLS 0 +#endif + +/** + * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from + * interrupt context (or another context that doesn't allow waiting for a + * semaphore). + * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT, + * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs + * with each loop so that mem_free can run. + * + * ATTENTION: As you can see from the above description, this leads to dis-/ + * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc + * can need longer. + * + * If you don't want that, at least for NO_SYS=0, you can still use the following + * functions to enqueue a deallocation call which then runs in the tcpip_thread + * context: + * - pbuf_free_callback(p); + * - mem_free_callback(m); + */ +#ifndef LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT +#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0 +#endif + +/* + --------------------------------------- + ---------- IPv6 options --------------- + --------------------------------------- +*/ +/** + * LWIP_IPV6==1: Enable IPv6 + */ +#define LWIP_IPV6 0 + +/* + ------------------------------------------------ + ---------- Internal Memory Pool Sizes ---------- + ------------------------------------------------ +*/ +/** + * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF). + * If the application sends a lot of data out of ROM (or other static memory), + * this should be set high. + */ +#ifndef MEMP_NUM_PBUF +#define MEMP_NUM_PBUF 16 +#endif + +/** + * MEMP_NUM_RAW_PCB: Number of raw connection PCBs + * (requires the LWIP_RAW option) + */ +#ifndef MEMP_NUM_RAW_PCB +#define MEMP_NUM_RAW_PCB 4 +#endif + +/** + * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + * per active UDP "connection". + * (requires the LWIP_UDP option) + */ +#ifndef MEMP_NUM_UDP_PCB +#define MEMP_NUM_UDP_PCB 4 +#endif + +/** + * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB +#define MEMP_NUM_TCP_PCB 5 +#endif + +/** + * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB_LISTEN +#define MEMP_NUM_TCP_PCB_LISTEN 8 +#endif + +/** + * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_SEG +#define MEMP_NUM_TCP_SEG 16 +#endif + +/** + * MEMP_NUM_REASSDATA: the number of IP packets simultaneously queued for + * reassembly (whole packets, not fragments!) + */ +#ifndef MEMP_NUM_REASSDATA +#define MEMP_NUM_REASSDATA 5 +#endif + +/** + * MEMP_NUM_FRAG_PBUF: the number of IP fragments simultaneously sent + * (fragments, not whole packets!). + * This is only used with IP_FRAG_USES_STATIC_BUF==0 and + * LWIP_NETIF_TX_SINGLE_PBUF==0 and only has to be > 1 with DMA-enabled MACs + * where the packet is not yet sent when netif->output returns. + */ +#ifndef MEMP_NUM_FRAG_PBUF +#define MEMP_NUM_FRAG_PBUF 15 +#endif + +/** + * MEMP_NUM_ARP_QUEUE: the number of simulateously queued outgoing + * packets (pbufs) that are waiting for an ARP request (to resolve + * their destination address) to finish. + * (requires the ARP_QUEUEING option) + */ +#ifndef MEMP_NUM_ARP_QUEUE +#define MEMP_NUM_ARP_QUEUE 15 +#endif + +/** + * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces + * can be members et the same time (one per netif - allsystems group -, plus one + * per netif membership). + * (requires the LWIP_IGMP option) + */ +#ifndef MEMP_NUM_IGMP_GROUP +#define MEMP_NUM_IGMP_GROUP 8 +#endif + +/** + * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts. + * (requires NO_SYS==0) + * The default number of timeouts is calculated here for all enabled modules. + * The formula expects settings to be either '0' or '1'. + */ +#ifndef MEMP_NUM_SYS_TIMEOUT +#define MEMP_NUM_SYS_TIMEOUT (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + PPP_SUPPORT + (LWIP_IPV6 ? (1 + LWIP_IPV6_REASS + LWIP_IPV6_MLD) : 0)) +#endif + +/** + * MEMP_NUM_NETBUF: the number of struct netbufs. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETBUF +#define MEMP_NUM_NETBUF 2 +#endif + +/** + * MEMP_NUM_NETCONN: the number of struct netconns. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETCONN +#define MEMP_NUM_NETCONN 4 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used + * for callback/timeout API communication. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_API +#define MEMP_NUM_TCPIP_MSG_API 8 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used + * for incoming packets. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_INPKT +#define MEMP_NUM_TCPIP_MSG_INPKT 8 +#endif + +/** + * MEMP_NUM_SNMP_NODE: the number of leafs in the SNMP tree. + */ +#ifndef MEMP_NUM_SNMP_NODE +#define MEMP_NUM_SNMP_NODE 50 +#endif + +/** + * MEMP_NUM_SNMP_ROOTNODE: the number of branches in the SNMP tree. + * Every branch has one leaf (MEMP_NUM_SNMP_NODE) at least! + */ +#ifndef MEMP_NUM_SNMP_ROOTNODE +#define MEMP_NUM_SNMP_ROOTNODE 30 +#endif + +/** + * MEMP_NUM_SNMP_VARBIND: the number of concurrent requests (does not have to + * be changed normally) - 2 of these are used per request (1 for input, + * 1 for output) + */ +#ifndef MEMP_NUM_SNMP_VARBIND +#define MEMP_NUM_SNMP_VARBIND 2 +#endif + +/** + * MEMP_NUM_SNMP_VALUE: the number of OID or values concurrently used + * (does not have to be changed normally) - 3 of these are used per request + * (1 for the value read and 2 for OIDs - input and output) + */ +#ifndef MEMP_NUM_SNMP_VALUE +#define MEMP_NUM_SNMP_VALUE 3 +#endif + +/** + * MEMP_NUM_NETDB: the number of concurrently running lwip_addrinfo() calls + * (before freeing the corresponding memory using lwip_freeaddrinfo()). + */ +#ifndef MEMP_NUM_NETDB +#define MEMP_NUM_NETDB 1 +#endif + +/** + * MEMP_NUM_LOCALHOSTLIST: the number of host entries in the local host list + * if DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1. + */ +#ifndef MEMP_NUM_LOCALHOSTLIST +#define MEMP_NUM_LOCALHOSTLIST 1 +#endif + +/** + * MEMP_NUM_PPPOE_INTERFACES: the number of concurrently active PPPoE + * interfaces (only used with PPPOE_SUPPORT==1) + */ +#ifndef MEMP_NUM_PPPOE_INTERFACES +#define MEMP_NUM_PPPOE_INTERFACES 1 +#endif + +/** + * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. + */ +#ifndef PBUF_POOL_SIZE +#define PBUF_POOL_SIZE 16 +#endif + +/* + --------------------------------- + ---------- ARP options ---------- + --------------------------------- +*/ +/** + * LWIP_ARP==1: Enable ARP functionality. + */ +#ifndef LWIP_ARP +#define LWIP_ARP 1 +#endif + +/** + * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached. + */ +#ifndef ARP_TABLE_SIZE +#define ARP_TABLE_SIZE 10 +#endif + +/** + * ARP_QUEUEING==1: Multiple outgoing packets are queued during hardware address + * resolution. By default, only the most recent packet is queued per IP address. + * This is sufficient for most protocols and mainly reduces TCP connection + * startup time. Set this to 1 if you know your application sends more than one + * packet in a row to an IP address that is not in the ARP cache. + */ +#ifndef ARP_QUEUEING +#define ARP_QUEUEING 0 +#endif + +/** + * ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be + * updated with the source MAC and IP addresses supplied in the packet. + * You may want to disable this if you do not trust LAN peers to have the + * correct addresses, or as a limited approach to attempt to handle + * spoofing. If disabled, lwIP will need to make a new ARP request if + * the peer is not already in the ARP table, adding a little latency. + * The peer *is* in the ARP table if it requested our address before. + * Also notice that this slows down input processing of every IP packet! + */ +#ifndef ETHARP_TRUST_IP_MAC +#define ETHARP_TRUST_IP_MAC 0 +#endif + +/** + * ETHARP_SUPPORT_VLAN==1: support receiving ethernet packets with VLAN header. + * Additionally, you can define ETHARP_VLAN_CHECK to an u16_t VLAN ID to check. + * If ETHARP_VLAN_CHECK is defined, only VLAN-traffic for this VLAN is accepted. + * If ETHARP_VLAN_CHECK is not defined, all traffic is accepted. + * Alternatively, define a function/define ETHARP_VLAN_CHECK_FN(eth_hdr, vlan) + * that returns 1 to accept a packet or 0 to drop a packet. + */ +#ifndef ETHARP_SUPPORT_VLAN +#define ETHARP_SUPPORT_VLAN 0 +#endif + +/** LWIP_ETHERNET==1: enable ethernet support for PPPoE even though ARP + * might be disabled + */ +#ifndef LWIP_ETHERNET +#define LWIP_ETHERNET (LWIP_ARP || PPPOE_SUPPORT) +#endif + +/** ETH_PAD_SIZE: number of bytes added before the ethernet header to ensure + * alignment of payload after that header. Since the header is 14 bytes long, + * without this padding e.g. addresses in the IP header will not be aligned + * on a 32-bit boundary, so setting this to 2 can speed up 32-bit-platforms. + */ +#ifndef ETH_PAD_SIZE +#define ETH_PAD_SIZE 0 +#endif + +/** ETHARP_SUPPORT_STATIC_ENTRIES==1: enable code to support static ARP table + * entries (using etharp_add_static_entry/etharp_remove_static_entry). + */ +#ifndef ETHARP_SUPPORT_STATIC_ENTRIES +#define ETHARP_SUPPORT_STATIC_ENTRIES 0 +#endif + +/* + -------------------------------- + ---------- IP options ---------- + -------------------------------- +*/ +/** + * IP_FORWARD==1: Enables the ability to forward IP packets across network + * interfaces. If you are going to run lwIP on a device with only one network + * interface, define this to 0. + */ +#ifndef IP_FORWARD +#define IP_FORWARD 0 +#endif + +/** + * IP_OPTIONS_ALLOWED: Defines the behavior for IP options. + * IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped. + * IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed). + */ +#ifndef IP_OPTIONS_ALLOWED +#define IP_OPTIONS_ALLOWED 1 +#endif + +/** + * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that + * this option does not affect outgoing packet sizes, which can be controlled + * via IP_FRAG. + */ +#ifndef IP_REASSEMBLY +#define IP_REASSEMBLY 1 +#endif + +/** + * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note + * that this option does not affect incoming packet sizes, which can be + * controlled via IP_REASSEMBLY. + */ +#ifndef IP_FRAG +#define IP_FRAG 1 +#endif + +/** + * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally) + * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived + * in this time, the whole packet is discarded. + */ +#ifndef IP_REASS_MAXAGE +#define IP_REASS_MAXAGE 3 +#endif + +/** + * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled. + * Since the received pbufs are enqueued, be sure to configure + * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive + * packets even if the maximum amount of fragments is enqueued for reassembly! + */ +#ifndef IP_REASS_MAX_PBUFS +#define IP_REASS_MAX_PBUFS 10 +#endif + +/** + * IP_FRAG_USES_STATIC_BUF==1: Use a static MTU-sized buffer for IP + * fragmentation. Otherwise pbufs are allocated and reference the original + * packet data to be fragmented (or with LWIP_NETIF_TX_SINGLE_PBUF==1, + * new PBUF_RAM pbufs are used for fragments). + * ATTENTION: IP_FRAG_USES_STATIC_BUF==1 may not be used for DMA-enabled MACs! + */ +#ifndef IP_FRAG_USES_STATIC_BUF +#define IP_FRAG_USES_STATIC_BUF 0 +#endif + +/** + * IP_FRAG_MAX_MTU: Assumed max MTU on any interface for IP frag buffer + * (requires IP_FRAG_USES_STATIC_BUF==1) + */ +#if IP_FRAG_USES_STATIC_BUF && !defined(IP_FRAG_MAX_MTU) +#define IP_FRAG_MAX_MTU 1500 +#endif + +/** + * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers. + */ +#ifndef IP_DEFAULT_TTL +#define IP_DEFAULT_TTL 255 +#endif + +/** + * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast + * filter per pcb on udp and raw send operations. To enable broadcast filter + * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1. + */ +#ifndef IP_SOF_BROADCAST +#define IP_SOF_BROADCAST 0 +#endif + +/** + * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast + * filter on recv operations. + */ +#ifndef IP_SOF_BROADCAST_RECV +#define IP_SOF_BROADCAST_RECV 0 +#endif + +/** + * IP_FORWARD_ALLOW_TX_ON_RX_NETIF==1: allow ip_forward() to send packets back + * out on the netif where it was received. This should only be used for + * wireless networks. + * ATTENTION: When this is 1, make sure your netif driver correctly marks incoming + * link-layer-broadcast/multicast packets as such using the corresponding pbuf flags! + */ +#ifndef IP_FORWARD_ALLOW_TX_ON_RX_NETIF +#define IP_FORWARD_ALLOW_TX_ON_RX_NETIF 0 +#endif + +/** + * LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS==1: randomize the local port for the first + * local TCP/UDP pcb (default==0). This can prevent creating predictable port + * numbers after booting a device. + */ +#ifndef LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS +#define LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS 1 +#endif + +#define LWIP_RAND rand + +/* + ---------------------------------- + ---------- ICMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_ICMP==1: Enable ICMP module inside the IP stack. + * Be careful, disable that make your product non-compliant to RFC1122 + */ +#ifndef LWIP_ICMP +#define LWIP_ICMP 1 +#endif + +/** + * ICMP_TTL: Default value for Time-To-Live used by ICMP packets. + */ +#ifndef ICMP_TTL +#define ICMP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only) + */ +#ifndef LWIP_BROADCAST_PING +#define LWIP_BROADCAST_PING 0 +#endif + +/** + * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only) + */ +#ifndef LWIP_MULTICAST_PING +#define LWIP_MULTICAST_PING 0 +#endif + +/* + --------------------------------- + ---------- RAW options ---------- + --------------------------------- +*/ +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef LWIP_RAW +#define LWIP_RAW 1 +#endif + +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef RAW_TTL +#define RAW_TTL (IP_DEFAULT_TTL) +#endif + +/* + ---------------------------------- + ---------- DHCP options ---------- + ---------------------------------- +*/ +/** + * LWIP_DHCP==1: Enable DHCP module. + */ +#ifndef LWIP_DHCP +#define LWIP_DHCP 1 +#endif + +/** + * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address. + */ +#ifndef DHCP_DOES_ARP_CHECK +#define DHCP_DOES_ARP_CHECK ((LWIP_DHCP) && (LWIP_ARP)) +#endif + +#define LWIP_DHCP_CHECK_LINK_UP 1 + +/* + ------------------------------------ + ---------- AUTOIP options ---------- + ------------------------------------ +*/ +/** + * LWIP_AUTOIP==1: Enable AUTOIP module. + */ +#ifndef LWIP_AUTOIP +#define LWIP_AUTOIP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on + * the same interface at the same time. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP +#define LWIP_DHCP_AUTOIP_COOP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes + * that should be sent before falling back on AUTOIP. This can be set + * as low as 1 to get an AutoIP address very quickly, but you should + * be prepared to handle a changing IP address when DHCP overrides + * AutoIP. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP_TRIES +#define LWIP_DHCP_AUTOIP_COOP_TRIES 9 +#endif + +/* + ---------------------------------- + ---------- SNMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_SNMP==1: Turn on SNMP module. UDP must be available for SNMP + * transport. + */ +#ifndef LWIP_SNMP +#define LWIP_SNMP 0 +#endif + +/** + * SNMP_CONCURRENT_REQUESTS: Number of concurrent requests the module will + * allow. At least one request buffer is required. + * Does not have to be changed unless external MIBs answer request asynchronously + */ +#ifndef SNMP_CONCURRENT_REQUESTS +#define SNMP_CONCURRENT_REQUESTS 1 +#endif + +/** + * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap + * destination is required + */ +#ifndef SNMP_TRAP_DESTINATIONS +#define SNMP_TRAP_DESTINATIONS 1 +#endif + +/** + * SNMP_PRIVATE_MIB: + * When using a private MIB, you have to create a file 'private_mib.h' that contains + * a 'struct mib_array_node mib_private' which contains your MIB. + */ +#ifndef SNMP_PRIVATE_MIB +#define SNMP_PRIVATE_MIB 0 +#endif + +/** + * Only allow SNMP write actions that are 'safe' (e.g. disabeling netifs is not + * a safe action and disabled when SNMP_SAFE_REQUESTS = 1). + * Unsafe requests are disabled by default! + */ +#ifndef SNMP_SAFE_REQUESTS +#define SNMP_SAFE_REQUESTS 1 +#endif + +/** + * The maximum length of strings used. This affects the size of + * MEMP_SNMP_VALUE elements. + */ +#ifndef SNMP_MAX_OCTET_STRING_LEN +#define SNMP_MAX_OCTET_STRING_LEN 127 +#endif + +/** + * The maximum depth of the SNMP tree. + * With private MIBs enabled, this depends on your MIB! + * This affects the size of MEMP_SNMP_VALUE elements. + */ +#ifndef SNMP_MAX_TREE_DEPTH +#define SNMP_MAX_TREE_DEPTH 15 +#endif + +/** + * The size of the MEMP_SNMP_VALUE elements, normally calculated from + * SNMP_MAX_OCTET_STRING_LEN and SNMP_MAX_TREE_DEPTH. + */ +#ifndef SNMP_MAX_VALUE_SIZE +#define SNMP_MAX_VALUE_SIZE LWIP_MAX((SNMP_MAX_OCTET_STRING_LEN)+1, sizeof(s32_t)*(SNMP_MAX_TREE_DEPTH)) +#endif + +/* + ---------------------------------- + ---------- IGMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_IGMP==1: Turn on IGMP module. + */ +#ifndef LWIP_IGMP +#define LWIP_IGMP 0 +#endif + +/* + ---------------------------------- + ---------- DNS options ----------- + ---------------------------------- +*/ +/** + * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS + * transport. + */ +#ifndef LWIP_DNS +#define LWIP_DNS 1 +#endif + +/** DNS maximum number of entries to maintain locally. */ +#ifndef DNS_TABLE_SIZE +#define DNS_TABLE_SIZE 4 +#endif + +/** DNS maximum host name length supported in the name table. */ +#ifndef DNS_MAX_NAME_LENGTH +#define DNS_MAX_NAME_LENGTH 256 +#endif + +/** The maximum of DNS servers */ +#ifndef DNS_MAX_SERVERS +#define DNS_MAX_SERVERS 2 +#endif + +/** DNS do a name checking between the query and the response. */ +#ifndef DNS_DOES_NAME_CHECK +#define DNS_DOES_NAME_CHECK 1 +#endif + +/** DNS message max. size. Default value is RFC compliant. */ +#ifndef DNS_MSG_SIZE +#define DNS_MSG_SIZE 512 +#endif + +/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled, + * you have to define + * #define DNS_LOCAL_HOSTLIST_INIT {{"host1", 0x123}, {"host2", 0x234}} + * (an array of structs name/address, where address is an u32_t in network + * byte order). + * + * Instead, you can also use an external function: + * #define DNS_LOOKUP_LOCAL_EXTERN(x) extern u32_t my_lookup_function(const char *name) + * that returns the IP address or INADDR_NONE if not found. + */ +#ifndef DNS_LOCAL_HOSTLIST +#define DNS_LOCAL_HOSTLIST 0 +#endif /* DNS_LOCAL_HOSTLIST */ + +/** If this is turned on, the local host-list can be dynamically changed + * at runtime. */ +#ifndef DNS_LOCAL_HOSTLIST_IS_DYNAMIC +#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC 0 +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + +/* + --------------------------------- + ---------- UDP options ---------- + --------------------------------- +*/ +/** + * LWIP_UDP==1: Turn on UDP. + */ +#ifndef LWIP_UDP +#define LWIP_UDP 1 +#endif + +/** + * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP) + */ +#ifndef LWIP_UDPLITE +#define LWIP_UDPLITE 0 +#endif + +/** + * UDP_TTL: Default Time-To-Live value. + */ +#ifndef UDP_TTL +#define UDP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * LWIP_NETBUF_RECVINFO==1: append destination addr and port to every netbuf. + */ +#ifndef LWIP_NETBUF_RECVINFO +#define LWIP_NETBUF_RECVINFO 0 +#endif + +/* + --------------------------------- + ---------- TCP options ---------- + --------------------------------- +*/ +/** + * LWIP_TCP==1: Turn on TCP. + */ +#ifndef LWIP_TCP +#define LWIP_TCP 1 +#endif + +/** + * TCP_TTL: Default Time-To-Live value. + */ +#ifndef TCP_TTL +#define TCP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * TCP_WND: The size of a TCP window. This must be at least + * (2 * TCP_MSS) for things to work well + */ +#ifndef TCP_WND +#define TCP_WND (4 * TCP_MSS) +#endif + +/** + * TCP_MAXRTX: Maximum number of retransmissions of data segments. + */ +#ifndef TCP_MAXRTX +#define TCP_MAXRTX 12 +#endif + +/** + * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments. + */ +#ifndef TCP_SYNMAXRTX +#define TCP_SYNMAXRTX 6 +#endif + +/** + * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order. + * Define to 0 if your device is low on memory. + */ +#ifndef TCP_QUEUE_OOSEQ +#define TCP_QUEUE_OOSEQ (LWIP_TCP) +#endif + +/** + * TCP_MSS: TCP Maximum segment size. (default is 536, a conservative default, + * you might want to increase this.) + * For the receive side, this MSS is advertised to the remote side + * when opening a connection. For the transmit size, this MSS sets + * an upper limit on the MSS advertised by the remote host. + */ +#ifndef TCP_MSS +#define TCP_MSS 1480 +#endif + +/** + * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really + * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which + * reflects the available reassembly buffer size at the remote host) and the + * largest size permitted by the IP layer" (RFC 1122) + * Setting this to 1 enables code that checks TCP_MSS against the MTU of the + * netif used for a connection and limits the MSS if it would be too big otherwise. + */ +#ifndef TCP_CALCULATE_EFF_SEND_MSS +#define TCP_CALCULATE_EFF_SEND_MSS 1 +#endif + + +/** + * TCP_SND_BUF: TCP sender buffer space (bytes). + * To achieve good performance, this should be at least 2 * TCP_MSS. + */ +#ifndef TCP_SND_BUF +#define TCP_SND_BUF (2 * TCP_MSS) +#endif + +/** + * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least + * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. + */ +#ifndef TCP_SND_QUEUELEN +#define TCP_SND_QUEUELEN ((4 * (TCP_SND_BUF) + (TCP_MSS - 1))/(TCP_MSS)) +#endif + +/** + * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than + * TCP_SND_BUF. It is the amount of space which must be available in the + * TCP snd_buf for select to return writable (combined with TCP_SNDQUEUELOWAT). + */ +#ifndef TCP_SNDLOWAT +#define TCP_SNDLOWAT LWIP_MIN(LWIP_MAX(((TCP_SND_BUF)/2), (2 * TCP_MSS) + 1), (TCP_SND_BUF) - 1) +#endif + +/** + * TCP_SNDQUEUELOWAT: TCP writable bufs (pbuf count). This must be less + * than TCP_SND_QUEUELEN. If the number of pbufs queued on a pcb drops below + * this number, select returns writable (combined with TCP_SNDLOWAT). + */ +#ifndef TCP_SNDQUEUELOWAT +#define TCP_SNDQUEUELOWAT LWIP_MAX(((TCP_SND_QUEUELEN)/2), 5) +#endif + +/** + * TCP_OOSEQ_MAX_BYTES: The maximum number of bytes queued on ooseq per pcb. + * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==0. + */ +#ifndef TCP_OOSEQ_MAX_BYTES +#define TCP_OOSEQ_MAX_BYTES 0 +#endif + +/** + * TCP_OOSEQ_MAX_PBUFS: The maximum number of pbufs queued on ooseq per pcb. + * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==0. + */ +#ifndef TCP_OOSEQ_MAX_PBUFS +#define TCP_OOSEQ_MAX_PBUFS 0 +#endif + +/** + * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb. + */ +#ifndef TCP_LISTEN_BACKLOG +#define TCP_LISTEN_BACKLOG 1 +#endif + +/** + * The maximum allowed backlog for TCP listen netconns. + * This backlog is used unless another is explicitly specified. + * 0xff is the maximum (u8_t). + */ +#ifndef TCP_DEFAULT_LISTEN_BACKLOG +#define TCP_DEFAULT_LISTEN_BACKLOG 0xff +#endif + +/** + * TCP_OVERSIZE: The maximum number of bytes that tcp_write may + * allocate ahead of time in an attempt to create shorter pbuf chains + * for transmission. The meaningful range is 0 to TCP_MSS. Some + * suggested values are: + * + * 0: Disable oversized allocation. Each tcp_write() allocates a new + pbuf (old behaviour). + * 1: Allocate size-aligned pbufs with minimal excess. Use this if your + * scatter-gather DMA requires aligned fragments. + * 128: Limit the pbuf/memory overhead to 20%. + * TCP_MSS: Try to create unfragmented TCP packets. + * TCP_MSS/4: Try to create 4 fragments or less per TCP packet. + */ +#ifndef TCP_OVERSIZE +#define TCP_OVERSIZE TCP_MSS +#endif + +/** + * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option. + */ +#ifndef LWIP_TCP_TIMESTAMPS +#define LWIP_TCP_TIMESTAMPS 0 +#endif + +/** + * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an + * explicit window update + */ +#ifndef TCP_WND_UPDATE_THRESHOLD +#define TCP_WND_UPDATE_THRESHOLD (TCP_WND / 4) +#endif + +/** + * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1. + * LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all + * events (accept, sent, etc) that happen in the system. + * LWIP_CALLBACK_API==1: The PCB callback function is called directly + * for the event. This is the default. + */ +#if !defined(LWIP_EVENT_API) && !defined(LWIP_CALLBACK_API) +#define LWIP_EVENT_API 0 +#define LWIP_CALLBACK_API 1 +#endif + + +/* + ---------------------------------- + ---------- Pbuf options ---------- + ---------------------------------- +*/ +/** + * PBUF_LINK_HLEN: the number of bytes that should be allocated for a + * link level header. The default is 14, the standard value for + * Ethernet. + */ +#ifndef PBUF_LINK_HLEN +#define PBUF_LINK_HLEN (14 + ETH_PAD_SIZE) +#endif + +/** + * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is + * designed to accomodate single full size TCP frame in one pbuf, including + * TCP_MSS, IP header, and link header. + */ +#ifndef PBUF_POOL_BUFSIZE +#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_HLEN) +#endif + +/* + ------------------------------------------------ + ---------- Network Interfaces options ---------- + ------------------------------------------------ +*/ +/** + * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname + * field. + */ +#ifndef LWIP_NETIF_HOSTNAME +#define LWIP_NETIF_HOSTNAME 1 +#endif + +/** + * LWIP_NETIF_API==1: Support netif api (in netifapi.c) + */ +#ifndef LWIP_NETIF_API +#define LWIP_NETIF_API 0 +#endif + +/** + * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface + * changes its up/down status (i.e., due to DHCP IP acquistion) + */ +#ifndef LWIP_NETIF_STATUS_CALLBACK +#define LWIP_NETIF_STATUS_CALLBACK 1 +#endif + +/** + * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface + * whenever the link changes (i.e., link down) + */ +#ifndef LWIP_NETIF_LINK_CALLBACK +#define LWIP_NETIF_LINK_CALLBACK 1 +#endif + +/** + * LWIP_NETIF_REMOVE_CALLBACK==1: Support a callback function that is called + * when a netif has been removed + */ +#ifndef LWIP_NETIF_REMOVE_CALLBACK +#define LWIP_NETIF_REMOVE_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table + * indices) in struct netif. TCP and UDP can make use of this to prevent + * scanning the ARP table for every sent packet. While this is faster for big + * ARP tables or many concurrent connections, it might be counterproductive + * if you have a tiny ARP table or if there never are concurrent connections. + */ +#ifndef LWIP_NETIF_HWADDRHINT +#define LWIP_NETIF_HWADDRHINT 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP + * address equal to the netif IP address, looping them back up the stack. + */ +#ifndef LWIP_NETIF_LOOPBACK +#define LWIP_NETIF_LOOPBACK 0 +#endif + +/** + * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback + * sending for each netif (0 = disabled) + */ +#ifndef LWIP_LOOPBACK_MAX_PBUFS +#define LWIP_LOOPBACK_MAX_PBUFS 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in + * the system, as netifs must change how they behave depending on this setting + * for the LWIP_NETIF_LOOPBACK option to work. + * Setting this is needed to avoid reentering non-reentrant functions like + * tcp_input(). + * LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a + * multithreaded environment like tcpip.c. In this case, netif->input() + * is called directly. + * LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup. + * The packets are put on a list and netif_poll() must be called in + * the main application loop. + */ +#ifndef LWIP_NETIF_LOOPBACK_MULTITHREADING +#define LWIP_NETIF_LOOPBACK_MULTITHREADING (!NO_SYS) +#endif + +/** + * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data + * to be sent into one single pbuf. This is for compatibility with DMA-enabled + * MACs that do not support scatter-gather. + * Beware that this might involve CPU-memcpy before transmitting that would not + * be needed without this flag! Use this only if you need to! + * + * @todo: TCP and IP-frag do not work with this, yet: + */ +#ifndef LWIP_NETIF_TX_SINGLE_PBUF +#define LWIP_NETIF_TX_SINGLE_PBUF 0 +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + +/* + ------------------------------------ + ---------- LOOPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1) and loopif.c + */ +#ifndef LWIP_HAVE_LOOPIF +#define LWIP_HAVE_LOOPIF 0 +#endif + +/* + ------------------------------------ + ---------- SLIPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_SLIPIF==1: Support slip interface and slipif.c + */ +#ifndef LWIP_HAVE_SLIPIF +#define LWIP_HAVE_SLIPIF 0 +#endif + +/* + ------------------------------------ + ---------- Thread options ---------- + ------------------------------------ +*/ +/** + * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread. + */ +#ifndef TCPIP_THREAD_NAME +#define TCPIP_THREAD_NAME "tcpip_thread" +#endif + +/** + * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_STACKSIZE +#define TCPIP_THREAD_STACKSIZE 1024 +#endif + +/** + * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_PRIO +#define TCPIP_THREAD_PRIO (NORMALPRIO) +#endif + +/** + * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when tcpip_init is called. + */ +#ifndef TCPIP_MBOX_SIZE +#define TCPIP_MBOX_SIZE MEMP_NUM_PBUF +#endif + +/** + * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread. + */ +#ifndef SLIPIF_THREAD_NAME +#define SLIPIF_THREAD_NAME "slipif_loop" +#endif + +/** + * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_STACKSIZE +#define SLIPIF_THREAD_STACKSIZE 1024 +#endif + +/** + * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_PRIO +#define SLIPIF_THREAD_PRIO (NORMALPRIO) +#endif + +/** + * PPP_THREAD_NAME: The name assigned to the pppInputThread. + */ +#ifndef PPP_THREAD_NAME +#define PPP_THREAD_NAME "pppInputThread" +#endif + +/** + * PPP_THREAD_STACKSIZE: The stack size used by the pppInputThread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_STACKSIZE +#define PPP_THREAD_STACKSIZE 1024 +#endif + +/** + * PPP_THREAD_PRIO: The priority assigned to the pppInputThread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_PRIO +#define PPP_THREAD_PRIO (NORMALPRIO) +#endif + +/** + * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread. + */ +#ifndef DEFAULT_THREAD_NAME +#define DEFAULT_THREAD_NAME "lwIP" +#endif + +/** + * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_STACKSIZE +#define DEFAULT_THREAD_STACKSIZE 1024 +#endif + +/** + * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_PRIO +#define DEFAULT_THREAD_PRIO (NORMALPRIO) +#endif + +/** + * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_RAW_RECVMBOX_SIZE +#define DEFAULT_RAW_RECVMBOX_SIZE 4 +#endif + +/** + * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_UDP_RECVMBOX_SIZE +#define DEFAULT_UDP_RECVMBOX_SIZE 4 +#endif + +/** + * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_TCP_RECVMBOX_SIZE +#define DEFAULT_TCP_RECVMBOX_SIZE 40 +#endif + +/** + * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections. + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when the acceptmbox is created. + */ +#ifndef DEFAULT_ACCEPTMBOX_SIZE +#define DEFAULT_ACCEPTMBOX_SIZE 4 +#endif + +/* + ---------------------------------------------- + ---------- Sequential layer options ---------- + ---------------------------------------------- +*/ +/** + * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!) + * Don't use it if you're not an active lwIP project member + */ +#ifndef LWIP_TCPIP_CORE_LOCKING +#define LWIP_TCPIP_CORE_LOCKING 0 +#endif + +/** + * LWIP_TCPIP_CORE_LOCKING_INPUT: (EXPERIMENTAL!) + * Don't use it if you're not an active lwIP project member + */ +#ifndef LWIP_TCPIP_CORE_LOCKING_INPUT +#define LWIP_TCPIP_CORE_LOCKING_INPUT 0 +#endif + +/** + * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c) + */ +#ifndef LWIP_NETCONN +#define LWIP_NETCONN 1 +#endif + +/** LWIP_TCPIP_TIMEOUT==1: Enable tcpip_timeout/tcpip_untimeout tod create + * timers running in tcpip_thread from another thread. + */ +#ifndef LWIP_TCPIP_TIMEOUT +#define LWIP_TCPIP_TIMEOUT 1 +#endif + +/* + ------------------------------------ + ---------- Socket options ---------- + ------------------------------------ +*/ +/** + * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) + */ +#ifndef LWIP_SOCKET +#define LWIP_SOCKET 1 +#endif + +/** + * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names. + * (only used if you use sockets.c) + */ +#ifndef LWIP_COMPAT_SOCKETS +#define LWIP_COMPAT_SOCKETS 1 +#endif + +/** + * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names. + * Disable this option if you use a POSIX operating system that uses the same + * names (read, write & close). (only used if you use sockets.c) + */ +#ifndef LWIP_POSIX_SOCKETS_IO_NAMES +#define LWIP_POSIX_SOCKETS_IO_NAMES 1 +#endif + +/** + * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT + * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set + * in seconds. (does not require sockets.c, and will affect tcp.c) + */ +#ifndef LWIP_TCP_KEEPALIVE +#define LWIP_TCP_KEEPALIVE 0 +#endif + +/** + * LWIP_SO_SNDTIMEO==1: Enable send timeout for sockets/netconns and + * SO_SNDTIMEO processing. + */ +#ifndef LWIP_SO_SNDTIMEO +#define LWIP_SO_SNDTIMEO 1 +#endif + +/** + * LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and + * SO_RCVTIMEO processing. + */ +#ifndef LWIP_SO_RCVTIMEO +#define LWIP_SO_RCVTIMEO 1 +#endif + +/** + * LWIP_SO_LINGER==1: Enable linger option for sockets/netconns + */ +#define LWIP_SO_LINGER 1 + +/** + * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing. + */ +#ifndef LWIP_SO_RCVBUF +#define LWIP_SO_RCVBUF 1 +#endif + +/** + * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize. + */ +#ifndef RECV_BUFSIZE_DEFAULT +#define RECV_BUFSIZE_DEFAULT INT_MAX +#endif + +/** + * SO_REUSE==1: Enable SO_REUSEADDR option. + */ +#ifndef SO_REUSE +#define SO_REUSE 1 +#endif + +/** + * SO_REUSE_RXTOALL==1: Pass a copy of incoming broadcast/multicast packets + * to all local matches if SO_REUSEADDR is turned on. + * WARNING: Adds a memcpy for every packet if passing to more than one pcb! + */ +#ifndef SO_REUSE_RXTOALL +#define SO_REUSE_RXTOALL 1 +#endif + +/* + ---------------------------------------- + ---------- Statistics options ---------- + ---------------------------------------- +*/ +/** + * LWIP_STATS==1: Enable statistics collection in lwip_stats. + */ +#ifndef LWIP_STATS +#define LWIP_STATS 0 +#endif + +#if LWIP_STATS + +/** + * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions. + */ +#ifndef LWIP_STATS_DISPLAY +#define LWIP_STATS_DISPLAY 0 +#endif + +/** + * LINK_STATS==1: Enable link stats. + */ +#ifndef LINK_STATS +#define LINK_STATS 1 +#endif + +/** + * ETHARP_STATS==1: Enable etharp stats. + */ +#ifndef ETHARP_STATS +#define ETHARP_STATS (LWIP_ARP) +#endif + +/** + * IP_STATS==1: Enable IP stats. + */ +#ifndef IP_STATS +#define IP_STATS 1 +#endif + +/** + * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is + * on if using either frag or reass. + */ +#ifndef IPFRAG_STATS +#define IPFRAG_STATS (IP_REASSEMBLY || IP_FRAG) +#endif + +/** + * ICMP_STATS==1: Enable ICMP stats. + */ +#ifndef ICMP_STATS +#define ICMP_STATS 1 +#endif + +/** + * IGMP_STATS==1: Enable IGMP stats. + */ +#ifndef IGMP_STATS +#define IGMP_STATS (LWIP_IGMP) +#endif + +/** + * UDP_STATS==1: Enable UDP stats. Default is on if + * UDP enabled, otherwise off. + */ +#ifndef UDP_STATS +#define UDP_STATS (LWIP_UDP) +#endif + +/** + * TCP_STATS==1: Enable TCP stats. Default is on if TCP + * enabled, otherwise off. + */ +#ifndef TCP_STATS +#define TCP_STATS (LWIP_TCP) +#endif + +/** + * MEM_STATS==1: Enable mem.c stats. + */ +#ifndef MEM_STATS +#define MEM_STATS ((MEM_LIBC_MALLOC == 0) && (MEM_USE_POOLS == 0)) +#endif + +/** + * MEMP_STATS==1: Enable memp.c pool stats. + */ +#ifndef MEMP_STATS +#define MEMP_STATS (MEMP_MEM_MALLOC == 0) +#endif + +/** + * SYS_STATS==1: Enable system stats (sem and mbox counts, etc). + */ +#ifndef SYS_STATS +#define SYS_STATS (NO_SYS == 0) +#endif + +#else + +#define LINK_STATS 0 +#define IP_STATS 0 +#define IPFRAG_STATS 0 +#define ICMP_STATS 0 +#define IGMP_STATS 0 +#define UDP_STATS 0 +#define TCP_STATS 0 +#define MEM_STATS 0 +#define MEMP_STATS 0 +#define SYS_STATS 0 +#define LWIP_STATS_DISPLAY 0 + +#endif /* LWIP_STATS */ + +/* + --------------------------------- + ---------- PPP options ---------- + --------------------------------- +*/ +/** + * PPP_SUPPORT==1: Enable PPP. + */ +#ifndef PPP_SUPPORT +#define PPP_SUPPORT 0 +#endif + +/** + * PPPOE_SUPPORT==1: Enable PPP Over Ethernet + */ +#ifndef PPPOE_SUPPORT +#define PPPOE_SUPPORT 0 +#endif + +/** + * PPPOS_SUPPORT==1: Enable PPP Over Serial + */ +#ifndef PPPOS_SUPPORT +#define PPPOS_SUPPORT PPP_SUPPORT +#endif + +#if PPP_SUPPORT + +/** + * NUM_PPP: Max PPP sessions. + */ +#ifndef NUM_PPP +#define NUM_PPP 1 +#endif + +/** + * PAP_SUPPORT==1: Support PAP. + */ +#ifndef PAP_SUPPORT +#define PAP_SUPPORT 0 +#endif + +/** + * CHAP_SUPPORT==1: Support CHAP. + */ +#ifndef CHAP_SUPPORT +#define CHAP_SUPPORT 0 +#endif + +/** + * MSCHAP_SUPPORT==1: Support MSCHAP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef MSCHAP_SUPPORT +#define MSCHAP_SUPPORT 0 +#endif + +/** + * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CBCP_SUPPORT +#define CBCP_SUPPORT 0 +#endif + +/** + * CCP_SUPPORT==1: Support CCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CCP_SUPPORT +#define CCP_SUPPORT 0 +#endif + +/** + * VJ_SUPPORT==1: Support VJ header compression. + */ +#ifndef VJ_SUPPORT +#define VJ_SUPPORT 0 +#endif + +/** + * MD5_SUPPORT==1: Support MD5 (see also CHAP). + */ +#ifndef MD5_SUPPORT +#define MD5_SUPPORT 0 +#endif + +/* + * Timeouts + */ +#ifndef FSM_DEFTIMEOUT +#define FSM_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef FSM_DEFMAXTERMREQS +#define FSM_DEFMAXTERMREQS 2 /* Maximum Terminate-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXCONFREQS +#define FSM_DEFMAXCONFREQS 10 /* Maximum Configure-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXNAKLOOPS +#define FSM_DEFMAXNAKLOOPS 5 /* Maximum number of nak loops */ +#endif + +#ifndef UPAP_DEFTIMEOUT +#define UPAP_DEFTIMEOUT 6 /* Timeout (seconds) for retransmitting req */ +#endif + +#ifndef UPAP_DEFREQTIME +#define UPAP_DEFREQTIME 30 /* Time to wait for auth-req from peer */ +#endif + +#ifndef CHAP_DEFTIMEOUT +#define CHAP_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef CHAP_DEFTRANSMITS +#define CHAP_DEFTRANSMITS 10 /* max # times to send challenge */ +#endif + +/* Interval in seconds between keepalive echo requests, 0 to disable. */ +#ifndef LCP_ECHOINTERVAL +#define LCP_ECHOINTERVAL 0 +#endif + +/* Number of unanswered echo requests before failure. */ +#ifndef LCP_MAXECHOFAILS +#define LCP_MAXECHOFAILS 3 +#endif + +/* Max Xmit idle time (in jiffies) before resend flag char. */ +#ifndef PPP_MAXIDLEFLAG +#define PPP_MAXIDLEFLAG 100 +#endif + +/* + * Packet sizes + * + * Note - lcp shouldn't be allowed to negotiate stuff outside these + * limits. See lcp.h in the pppd directory. + * (XXX - these constants should simply be shared by lcp.c instead + * of living in lcp.h) + */ +#define PPP_MTU 1500 /* Default MTU (size of Info field) */ +#ifndef PPP_MAXMTU +/* #define PPP_MAXMTU 65535 - (PPP_HDRLEN + PPP_FCSLEN) */ +#define PPP_MAXMTU 1500 /* Largest MTU we allow */ +#endif +#define PPP_MINMTU 64 +#define PPP_MRU 1500 /* default MRU = max length of info field */ +#define PPP_MAXMRU 1500 /* Largest MRU we allow */ +#ifndef PPP_DEFMRU +#define PPP_DEFMRU 296 /* Try for this */ +#endif +#define PPP_MINMRU 128 /* No MRUs below this */ + +#ifndef MAXNAMELEN +#define MAXNAMELEN 256 /* max length of hostname or name for auth */ +#endif +#ifndef MAXSECRETLEN +#define MAXSECRETLEN 256 /* max length of password or secret */ +#endif + +#endif /* PPP_SUPPORT */ + +/* + -------------------------------------- + ---------- Checksum options ---------- + -------------------------------------- +*/ +/** + * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets. + */ +#ifndef CHECKSUM_GEN_IP +#define CHECKSUM_GEN_IP 1 +#endif + +/** + * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets. + */ +#ifndef CHECKSUM_GEN_UDP +#define CHECKSUM_GEN_UDP 1 +#endif + +/** + * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets. + */ +#ifndef CHECKSUM_GEN_TCP +#define CHECKSUM_GEN_TCP 1 +#endif + +/** + * CHECKSUM_GEN_ICMP==1: Generate checksums in software for outgoing ICMP packets. + */ +#ifndef CHECKSUM_GEN_ICMP +#define CHECKSUM_GEN_ICMP 1 +#endif + +/** + * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets. + */ +#ifndef CHECKSUM_CHECK_IP +#define CHECKSUM_CHECK_IP 1 +#endif + +/** + * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets. + */ +#ifndef CHECKSUM_CHECK_UDP +#define CHECKSUM_CHECK_UDP 1 +#endif + +/** + * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets. + */ +#ifndef CHECKSUM_CHECK_TCP +#define CHECKSUM_CHECK_TCP 1 +#endif + +/** + * LWIP_CHECKSUM_ON_COPY==1: Calculate checksum when copying data from + * application buffers to pbufs. + */ +#ifndef LWIP_CHECKSUM_ON_COPY +#define LWIP_CHECKSUM_ON_COPY 0 +#endif + +/* + --------------------------------------- + ---------- Hook options --------------- + --------------------------------------- +*/ + +/* Hooks are undefined by default, define them to a function if you need them. */ + +/** + * LWIP_HOOK_IP4_INPUT(pbuf, input_netif): + * - called from ip_input() (IPv4) + * - pbuf: received struct pbuf passed to ip_input() + * - input_netif: struct netif on which the packet has been received + * Return values: + * - 0: Hook has not consumed the packet, packet is processed as normal + * - != 0: Hook has consumed the packet. + * If the hook consumed the packet, 'pbuf' is in the responsibility of the hook + * (i.e. free it when done). + */ + +/** + * LWIP_HOOK_IP4_ROUTE(dest): + * - called from ip_route() (IPv4) + * - dest: destination IPv4 address + * Returns the destination netif or NULL if no destination netif is found. In + * that case, ip_route() continues as normal. + */ + +/* + --------------------------------------- + ---------- Debugging options ---------- + --------------------------------------- +*/ +/** + * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is + * compared against this value. If it is smaller, then debugging + * messages are written. + */ +#ifndef LWIP_DBG_MIN_LEVEL +#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_ALL +#endif + +/** + * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable + * debug messages of certain types. + */ +#ifndef LWIP_DBG_TYPES_ON +#define LWIP_DBG_TYPES_ON LWIP_DBG_OFF +#endif + +/** + * ETHARP_DEBUG: Enable debugging in etharp.c. + */ +#ifndef ETHARP_DEBUG +#define ETHARP_DEBUG LWIP_DBG_OFF +#endif + +/** + * NETIF_DEBUG: Enable debugging in netif.c. + */ +#ifndef NETIF_DEBUG +#define NETIF_DEBUG LWIP_DBG_OFF +#endif + +/** + * PBUF_DEBUG: Enable debugging in pbuf.c. + */ +#ifndef PBUF_DEBUG +#define PBUF_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_LIB_DEBUG: Enable debugging in api_lib.c. + */ +#ifndef API_LIB_DEBUG +#define API_LIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_MSG_DEBUG: Enable debugging in api_msg.c. + */ +#ifndef API_MSG_DEBUG +#define API_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SOCKETS_DEBUG: Enable debugging in sockets.c. + */ +#ifndef SOCKETS_DEBUG +#define SOCKETS_DEBUG LWIP_DBG_OFF +#endif + +/** + * ICMP_DEBUG: Enable debugging in icmp.c. + */ +#ifndef ICMP_DEBUG +#define ICMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IGMP_DEBUG: Enable debugging in igmp.c. + */ +#ifndef IGMP_DEBUG +#define IGMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * INET_DEBUG: Enable debugging in inet.c. + */ +#ifndef INET_DEBUG +#define INET_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_DEBUG: Enable debugging for IP. + */ +#ifndef IP_DEBUG +#define IP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass. + */ +#ifndef IP_REASS_DEBUG +#define IP_REASS_DEBUG LWIP_DBG_OFF +#endif + +/** + * RAW_DEBUG: Enable debugging in raw.c. + */ +#ifndef RAW_DEBUG +#define RAW_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEM_DEBUG: Enable debugging in mem.c. + */ +#ifndef MEM_DEBUG +#define MEM_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEMP_DEBUG: Enable debugging in memp.c. + */ +#ifndef MEMP_DEBUG +#define MEMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SYS_DEBUG: Enable debugging in sys.c. + */ +#ifndef SYS_DEBUG +#define SYS_DEBUG LWIP_DBG_OFF +#endif + +/** + * TIMERS_DEBUG: Enable debugging in timers.c. + */ +#ifndef TIMERS_DEBUG +#define TIMERS_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_DEBUG: Enable debugging for TCP. + */ +#ifndef TCP_DEBUG +#define TCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug. + */ +#ifndef TCP_INPUT_DEBUG +#define TCP_INPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit. + */ +#ifndef TCP_FR_DEBUG +#define TCP_FR_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit + * timeout. + */ +#ifndef TCP_RTO_DEBUG +#define TCP_RTO_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_CWND_DEBUG: Enable debugging for TCP congestion window. + */ +#ifndef TCP_CWND_DEBUG +#define TCP_CWND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating. + */ +#ifndef TCP_WND_DEBUG +#define TCP_WND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions. + */ +#ifndef TCP_OUTPUT_DEBUG +#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RST_DEBUG: Enable debugging for TCP with the RST message. + */ +#ifndef TCP_RST_DEBUG +#define TCP_RST_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths. + */ +#ifndef TCP_QLEN_DEBUG +#define TCP_QLEN_DEBUG LWIP_DBG_OFF +#endif + +/** + * UDP_DEBUG: Enable debugging in UDP. + */ +#ifndef UDP_DEBUG +#define UDP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCPIP_DEBUG: Enable debugging in tcpip.c. + */ +#ifndef TCPIP_DEBUG +#define TCPIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * PPP_DEBUG: Enable debugging for PPP. + */ +#ifndef PPP_DEBUG +#define PPP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SLIP_DEBUG: Enable debugging in slipif.c. + */ +#ifndef SLIP_DEBUG +#define SLIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * DHCP_DEBUG: Enable debugging in dhcp.c. + */ +#ifndef DHCP_DEBUG +#define DHCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * AUTOIP_DEBUG: Enable debugging in autoip.c. + */ +#ifndef AUTOIP_DEBUG +#define AUTOIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MSG_DEBUG: Enable debugging for SNMP messages. + */ +#ifndef SNMP_MSG_DEBUG +#define SNMP_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs. + */ +#ifndef SNMP_MIB_DEBUG +#define SNMP_MIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * DNS_DEBUG: Enable debugging for DNS. + */ +#ifndef DNS_DEBUG +#define DNS_DEBUG LWIP_DBG_OFF +#endif + +// in order to enable the lwIP debug output the bellow has to be uncomment and +// the options above changed to LWIP_DBG_ON for the features that are to output debug information +//#define LWIP_DEBUG 1 + +// enable full duplex comms on multiple threads +// this requires adding an extra field in ChibiOS thread_t (see comment on platform_sys_arch.c) +//#define LWIP_NETCONN_FULLDUPLEX 1 + +#endif /* __LWIPOPT_H__ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/managed_helpers/README.md b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/managed_helpers/README.md new file mode 100644 index 00000000..d745be69 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/managed_helpers/README.md @@ -0,0 +1,5 @@ +## Managed code helpers + +This folder contains helper classes to make developers life easier when coding for this target board. + +* [Adc](ST_NUCLEO144_F746ZG.Adc.cs) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/managed_helpers/ST_NUCLEO144_F746ZG.Adc.cs b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/managed_helpers/ST_NUCLEO144_F746ZG.Adc.cs new file mode 100644 index 00000000..ca285084 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/managed_helpers/ST_NUCLEO144_F746ZG.Adc.cs @@ -0,0 +1,73 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +namespace nanoFramework.Targets.ST_NUCLEO144_F746ZG +{ + /// + /// Enumeration of ADC channels available on ST_NUCLEO144_F746ZG + /// + public static class AdcChannels + { + /// + /// Channel 0, exposed as A0, connected to pin 1 on CN9 = PA3 (ADC1 - IN3) + /// + public const int Channel_0 = 0; + + /// + /// Channel 1, exposed as A1, connected to pin 3 on CN9 = PC0 (ADC1 - IN10) + /// + public const int Channel_1 = 1; + + /// + /// Channel 2, exposed as A2, connected to pin 5 on CN9 = PC3 (ADC1 - IN13) + /// + public const int Channel_2 = 2; + + /// + /// Channel 3, exposed as A3, connected to pin 7 on CN9 = PF3 (ADC3 - IN9) + /// + public const int Channel_3 = 3; + + /// + /// Channel 4, exposed as A4, connected to pin 9 on CN9 = PF5 (ADC3 - IN15) + /// + public const int Channel_4 = 4; + + /// + /// Channel 5, exposed on A5, connected to pin 11 on CN9 = PF10 (ADC3 - IN8) + /// + public const int Channel_5 = 5; + + /// + /// Channel 6, exposed on PB1, connected to CN10 Pin 7 (ADC2 - IN9) + /// + public const int Channel_6 = 6; + + /// + /// Channel 7, exposed on PC2, connected to CN10 Pin 9 (ADC2 - IN12) + /// + public const int Channel_7 = 7; + + /// + /// Channel 8, exposed on PF4, connected to CN10 Pin 11 (ADC3 - IN14) + /// + public const int Channel_8 = 8; + + /// + /// Channel 9, internal temperature sensor, connected to ADC1 + /// + public const int Channel_TemperatureSensor = 9; + + /// + /// Channel 10, internal voltage reference, connected to ADC1 + /// + public const int Channel_VrefIn = 10; + + /// + /// Channel 11, connected to VBatt pin, ADC1 + /// + public const int Channel_Vbatt = 11; + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/mbedtls_config.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/mbedtls_config.h new file mode 100644 index 00000000..9877ca77 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/mbedtls_config.h @@ -0,0 +1,53 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2006-2015, ARM Limited, All Rights Reserved +// See LICENSE file in the project root for full license information. +// + +#ifndef MBEDTLS_CONFIG_H +#define MBEDTLS_CONFIG_H + +/* For test certificates */ +// #define MBEDTLS_CERTS_C +// #define MBEDTLS_PEM_PARSE_C + +// #define SSL_DEBUG_BUF MBEDTLS_SSL_DEBUG_BUF +// #define SSL_DEBUG_CRT MBEDTLS_SSL_DEBUG_CRT +// #define SSL_DEBUG_ECP MBEDTLS_SSL_DEBUG_ECP +// #define SSL_DEBUG_MPI MBEDTLS_SSL_DEBUG_MPI +// #define SSL_DEBUG_MSG MBEDTLS_SSL_DEBUG_MSG +// #define SSL_DEBUG_RET MBEDTLS_SSL_DEBUG_RET + +// #define MBEDTLS_SSL_ALL_ALERT_MESSAGES +// #define MBEDTLS_SSL_DEBUG_ALL +// #define MBEDTLS_VERSION_FEATURES +// #define MBEDTLS_CERTS_C +// #define MBEDTLS_ERROR_C +// #define MBEDTLS_VERSION_C + +// uncomment the defines below to enable static memory allocation feature +#if 0 +#define MBEDTLS_MEMORY_BUFFER_ALLOC_C +#define MBEDTLS_PLATFORM_MEMORY +#endif + +#ifdef USE_LCD +#include "lcd_log.h" +#define MBEDTLS_PLATFORM_PRINTF_MACRO LCD_UsrLog +#endif + +// uncomment the defines bellow to generate debug output +// set below the threshold level for debug messages +// check mbed TLS mbedtls/debug.h header for details. +// Debug levels: +// 0 No debug +// 1 Error +// 2 State change +// 3 Informational +// 4 Verbose + +// #define MBEDTLS_DEBUG_C +// #define MBEDTLS_SSL_ALL_ALERT_MESSAGES +// #define MBEDTLS_DEBUG_THRESHOLD 2 + +#endif // MBEDTLS_CONFIG_H diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/CMakeLists.txt new file mode 100644 index 00000000..f0e921f7 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# # append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") + +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/STM32F746xG_booter-DEBUG.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/STM32F746xG_booter-DEBUG.ld new file mode 100644 index 00000000..b1b4c994 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/STM32F746xG_booter-DEBUG.ld @@ -0,0 +1,122 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F746xG generic setup. + * + * RAM0 - Data, Heap. + * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. + * + * Notes: + * BSS is placed in DTCM RAM in order to simplify DMA buffers management. + */ +MEMORY +{ + flash : org = 0x08000000, len = 32k /* space reserved for nanoBooter (1st sector 0x08000000 to 0x08008000)*/ + flash_itcm : org = 0x00200000, len = 1M + config : org = 0x08008000, len = 32k /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */ + ram1 : org = 0x20010000, len = 240k /* SRAM1 */ + ram2 : org = 0x2004C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20000000, len = 64k /* DTCM-RAM */ + ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash_itcm); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash_itcm); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash_itcm); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash_itcm); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram3); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram3); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram3); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + + +/* rules inclusion.*/ +INCLUDE rules_stacks.ld + +/*===========================================================================*/ +/* Custom sections for STM32F7xx. */ +/*===========================================================================*/ + +/* RAM region to be used for nocache segment.*/ +REGION_ALIAS("NOCACHE_RAM", ram3); + +/* RAM region to be used for eth segment.*/ +REGION_ALIAS("ETH_RAM", ram3); + +SECTIONS +{ + /* Special section for non cache-able areas.*/ + .nocache (NOLOAD) : ALIGN(4) + { + __nocache_base__ = .; + *(.nocache) + *(.nocache.*) + *(.bss.__nocache_*) + . = ALIGN(4); + __nocache_end__ = .; + } > NOCACHE_RAM + + /* Special section for Ethernet DMA non cache-able areas.*/ + .eth (NOLOAD) : ALIGN(4) + { + __eth_base__ = .; + *(.eth) + *(.eth.*) + *(.bss.__eth_*) + . = ALIGN(4); + __eth_end__ = .; + } > ETH_RAM +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld \ No newline at end of file diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/STM32F746xG_booter.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/STM32F746xG_booter.ld new file mode 100644 index 00000000..b1b4c994 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/STM32F746xG_booter.ld @@ -0,0 +1,122 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F746xG generic setup. + * + * RAM0 - Data, Heap. + * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. + * + * Notes: + * BSS is placed in DTCM RAM in order to simplify DMA buffers management. + */ +MEMORY +{ + flash : org = 0x08000000, len = 32k /* space reserved for nanoBooter (1st sector 0x08000000 to 0x08008000)*/ + flash_itcm : org = 0x00200000, len = 1M + config : org = 0x08008000, len = 32k /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */ + ram1 : org = 0x20010000, len = 240k /* SRAM1 */ + ram2 : org = 0x2004C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20000000, len = 64k /* DTCM-RAM */ + ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash_itcm); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash_itcm); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash_itcm); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash_itcm); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram3); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram3); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram3); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + + +/* rules inclusion.*/ +INCLUDE rules_stacks.ld + +/*===========================================================================*/ +/* Custom sections for STM32F7xx. */ +/*===========================================================================*/ + +/* RAM region to be used for nocache segment.*/ +REGION_ALIAS("NOCACHE_RAM", ram3); + +/* RAM region to be used for eth segment.*/ +REGION_ALIAS("ETH_RAM", ram3); + +SECTIONS +{ + /* Special section for non cache-able areas.*/ + .nocache (NOLOAD) : ALIGN(4) + { + __nocache_base__ = .; + *(.nocache) + *(.nocache.*) + *(.bss.__nocache_*) + . = ALIGN(4); + __nocache_end__ = .; + } > NOCACHE_RAM + + /* Special section for Ethernet DMA non cache-able areas.*/ + .eth (NOLOAD) : ALIGN(4) + { + __eth_base__ = .; + *(.eth) + *(.eth.*) + *(.bss.__eth_*) + . = ALIGN(4); + __eth_end__ = .; + } > ETH_RAM +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld \ No newline at end of file diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/chconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/chconf.h new file mode 100644 index 00000000..de13f63d --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/chconf.h @@ -0,0 +1,707 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM FALSE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES FALSE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS FALSE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT FALSE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES FALSE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY FALSE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + // this field is required in case lwIP options has LWIP_NETCONN_SEM_PER_THREAD + // void* localStorage; + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#define CORTEX_VTOR_INIT 0x00200000U + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/halconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/halconf.h new file mode 100644 index 00000000..1a2f5c78 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/halconf.h @@ -0,0 +1,524 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +#if !defined(FATFS_HAL_DEVICE) || defined(__DOXYGEN__) +//this board requires SDCD2 not SDCD1 +#define FATFS_HAL_DEVICE SDCD2 +#endif + +//#define STM32_SDC_SDMMC_50MHZ TRUE + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 64 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +// header for nanoFramework overlay +#include "halconf_nf.h" +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/halconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/halconf_nf.h new file mode 100644 index 00000000..809a6cfa --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/halconf_nf.h @@ -0,0 +1,15 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +#endif // _HALCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/main.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/main.c new file mode 100644 index 00000000..ed61f944 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/main.c @@ -0,0 +1,84 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); + +// Application entry point. +int main(void) { + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init SWO as soon as possible to make it available to output ASAP + #if (SWO_OUTPUT == TRUE) + SwoInit(); + #endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + osDelay(20); // Let init stabilize + + // the following IF is not mandatory, it's just providing a way for a user to 'force' + // the board to remain in nanoBooter and not launching nanoCLR + + // if the USER button (blue one) is pressed, skip the check for a valid CLR image and remain in booter + // the user button in this board has a pull-up resistor so the check has to be inverted + if (!palReadLine(LINE_BUTTON)) + { + // check for valid CLR image + // we are checking for a valid image right after the configuration block + if(CheckValidCLRImage((uint32_t)&__nanoConfig_end__)) + { + // there seems to be a valid CLR image + // launch nanoCLR + LaunchCLR((uint32_t)&__nanoConfig_end__); + } + } + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // starts the serial driver + sdStart(&SERIAL_DRIVER, NULL); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // initialize configuration manager + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it here to have access to network configuration blocks + ConfigurationManager_Initialize(); + + // Normal main() thread + while (true) { + palToggleLine(LINE_LED1); + osDelay(500); + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/mcuconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/mcuconf.h new file mode 100644 index 00000000..9ea6775e --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/mcuconf.h @@ -0,0 +1,381 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F7xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F7xx_MCUCONF +#define STM32F746_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 4 +#define STM32_PLLN_VALUE 216 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 25 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 +#define STM32_I2SSRC STM32_I2SSRC_OFF +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SP_VALUE 2 +#define STM32_PLLI2SQ_VALUE 2 +#define STM32_PLLI2SR_VALUE 2 +#define STM32_PLLSAIN_VALUE 192 +#define STM32_PLLSAIP_VALUE 2 +#define STM32_PLLSAIQ_VALUE 2 +#define STM32_PLLSAIR_VALUE 2 +#define STM32_PLLSAIDIVQ_VALUE 2 +#define STM32_PLLSAIDIVR_VALUE 2 +#define STM32_SAI1SEL STM32_SAI1SEL_OFF +#define STM32_SAI2SEL STM32_SAI2SEL_OFF +#define STM32_LCDTFT_REQUIRED FALSE +#define STM32_USART1SEL STM32_USART1SEL_PCLK2 +#define STM32_USART2SEL STM32_USART2SEL_PCLK1 +#define STM32_USART3SEL STM32_USART3SEL_PCLK1 +#define STM32_UART4SEL STM32_UART4SEL_PCLK1 +#define STM32_UART5SEL STM32_UART5SEL_PCLK1 +#define STM32_USART6SEL STM32_USART6SEL_PCLK2 +#define STM32_UART7SEL STM32_UART7SEL_PCLK1 +#define STM32_UART8SEL STM32_UART8SEL_PCLK1 +#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 +#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1 +#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1 +#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1 +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 +#define STM32_CECSEL STM32_CECSEL_HSIDIV488 +#define STM32_CK48MSEL STM32_CK48MSEL_PLL +#define STM32_SDMMCSEL STM32_SDMMCSEL_SYSCLK +#define STM32_SRAM2_NOCACHE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_USE_CAN3 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 +#define STM32_CAN_CAN3_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_USE_I2C4 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C4_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C4_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 FALSE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000 +#define STM32_SDC_SDMMC_READ_TIMEOUT 1000 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 TRUE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 +#define STM32_SERIAL_UART7_PRIORITY 12 +#define STM32_SERIAL_UART8_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 FALSE +#define STM32_SPI_USE_SPI5 FALSE +#define STM32_SPI_USE_SPI6 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI5_DMA_PRIORITY 1 +#define STM32_SPI_SPI6_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USE_UART7 FALSE +#define STM32_UART_USE_UART8 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_UART7_DMA_PRIORITY 0 +#define STM32_UART_UART8_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +#endif /* MCUCONF_H */ \ No newline at end of file diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/mcuconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/mcuconf_nf.h new file mode 100644 index 00000000..5ff03534 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/mcuconf_nf.h @@ -0,0 +1,9 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/target_board.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/target_board.h.in new file mode 100644 index 00000000..19531d9c --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoBooter/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOBOOTER_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/CMakeLists.txt new file mode 100644 index 00000000..e5496b7e --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/STM32F746xG_CLR-DEBUG.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/STM32F746xG_CLR-DEBUG.ld new file mode 100644 index 00000000..3b10b360 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/STM32F746xG_CLR-DEBUG.ld @@ -0,0 +1,127 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F746xG generic setup. + * + * RAM0 - Data, Heap. + * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. + * + * Notes: + * BSS is placed in DTCM RAM in order to simplify DMA buffers management. + */ +MEMORY +{ + flash : org = 0x08010000, len = 1M - 32k - 32k - 256k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + flash_itcm : org = 0x00210000, len = 1M - 32k - 32k - 256k + config : org = 0x08008000, len = 32k /* space reserved for configuration block */ + deployment : org = 0x080C0000, len = 256k /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */ + ram1 : org = 0x20010000, len = 240k /* SRAM1 */ + ram2 : org = 0x2004C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20000000, len = 64k /* DTCM-RAM */ + ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash_itcm); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash_itcm); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash_itcm); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash_itcm); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram3); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram3); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram3); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +/* rules inclusion.*/ +INCLUDE rules_stacks.ld + +/*===========================================================================*/ +/* Custom sections for STM32F7xx. */ +/*===========================================================================*/ + +/* RAM region to be used for nocache segment.*/ +REGION_ALIAS("NOCACHE_RAM", ram3); + +/* RAM region to be used for eth segment.*/ +REGION_ALIAS("ETH_RAM", ram3); + +SECTIONS +{ + /* Special section for non cache-able areas.*/ + .nocache (NOLOAD) : ALIGN(4) + { + __nocache_base__ = .; + *(.nocache) + *(.nocache.*) + *(.bss.__nocache_*) + . = ALIGN(4); + __nocache_end__ = .; + } > NOCACHE_RAM + + /* Special section for Ethernet DMA non cache-able areas.*/ + .eth (NOLOAD) : ALIGN(4) + { + __eth_base__ = .; + *(.eth) + *(.eth.*) + *(.bss.__eth_*) + . = ALIGN(4); + __eth_end__ = .; + } > ETH_RAM +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld + +/* nanoCLR rules inclusion.*/ +INCLUDE rules_clr.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/STM32F746xG_CLR.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/STM32F746xG_CLR.ld new file mode 100644 index 00000000..dbaaf06f --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/STM32F746xG_CLR.ld @@ -0,0 +1,127 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F746xG generic setup. + * + * RAM0 - Data, Heap. + * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. + * + * Notes: + * BSS is placed in DTCM RAM in order to simplify DMA buffers management. + */ +MEMORY +{ + flash : org = 0x08010000, len = 1M - 32k - 32k - 512k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + flash_itcm : org = 0x00210000, len = 1M - 32k - 32k - 512k + config : org = 0x08008000, len = 32k /* space reserved for configuration block */ + deployment : org = 0x08080000, len = 512k /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */ + ram1 : org = 0x20010000, len = 240k /* SRAM1 */ + ram2 : org = 0x2004C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20000000, len = 64k /* DTCM-RAM */ + ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash_itcm); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash_itcm); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash_itcm); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash_itcm); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram3); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram3); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram3); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +/* rules inclusion.*/ +INCLUDE rules_stacks.ld + +/*===========================================================================*/ +/* Custom sections for STM32F7xx. */ +/*===========================================================================*/ + +/* RAM region to be used for nocache segment.*/ +REGION_ALIAS("NOCACHE_RAM", ram3); + +/* RAM region to be used for eth segment.*/ +REGION_ALIAS("ETH_RAM", ram3); + +SECTIONS +{ + /* Special section for non cache-able areas.*/ + .nocache (NOLOAD) : ALIGN(4) + { + __nocache_base__ = .; + *(.nocache) + *(.nocache.*) + *(.bss.__nocache_*) + . = ALIGN(4); + __nocache_end__ = .; + } > NOCACHE_RAM + + /* Special section for Ethernet DMA non cache-able areas.*/ + .eth (NOLOAD) : ALIGN(4) + { + __eth_base__ = .; + *(.eth) + *(.eth.*) + *(.bss.__eth_*) + . = ALIGN(4); + __eth_end__ = .; + } > ETH_RAM +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld + +/* nanoCLR rules inclusion.*/ +INCLUDE rules_clr.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/chconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/chconf.h new file mode 100644 index 00000000..214cbcd6 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/chconf.h @@ -0,0 +1,705 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM FALSE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY FALSE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + // this field is required in case lwIP options has LWIP_NETCONN_SEM_PER_THREAD + // void* localStorage; + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/halconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/halconf.h new file mode 100644 index 00000000..32abfdc5 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/halconf.h @@ -0,0 +1,535 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +#if !defined(FATFS_HAL_DEVICE) || defined(__DOXYGEN__) +//this board requires SDCD2 not SDCD1 +#define FATFS_HAL_DEVICE SDCD2 +#endif + +//#define STM32_SDC_SDMMC_50MHZ TRUE + +/** + * @brief Enables the ADC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +// #define HAL_USE_ADC FALSE +// #endif + +/** + * @brief Enables the CAN subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +// #define HAL_USE_CAN FALSE +// #endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +// /** +// * @brief Enables the DAC subsystem. +// */ +// #if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +// #define HAL_USE_DAC FALSE +// #endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +// this option is set at target_platform.h (from config file) +//#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +//#define HAL_USE_I2C TRUE +//#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +// #define HAL_USE_MAC TRUE +// #endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +// #define HAL_USE_PWM FALSE +// #endif + +/** + * @brief Enables the RTC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +// #define HAL_USE_RTC TRUE +// #endif + +/** + * @brief Enables the SDC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +// #define HAL_USE_SDC TRUE +// #endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +// #define HAL_USE_SPI FALSE +// #endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +// #define HAL_USE_UART FALSE +// #endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +// #define HAL_USE_WDG FALSE +// #endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS TRUE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 64 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +// header for nanoFramework overlay +#include "halconf_nf.h" +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/halconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/halconf_nf.h new file mode 100644 index 00000000..c40fe9b1 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/halconf_nf.h @@ -0,0 +1,14 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ 1 + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +#endif // _HALCONF_NF_H_ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/main.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/main.c new file mode 100644 index 00000000..d244b913 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/main.c @@ -0,0 +1,67 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); +// declare CLRStartup thread here +osThreadDef(CLRStartupThread, osPriorityNormal, 4096, "CLRStartupThread"); + +// Application entry point. +int main(void) { + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init SWO as soon as possible to make it available to output ASAP + #if (SWO_OUTPUT == TRUE) + SwoInit(); + #endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // start watchdog + Watchdog_Init(); + + // starts the serial driver + sdStart(&SERIAL_DRIVER, NULL); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // CLR settings to launch CLR thread + CLR_SETTINGS clrSettings; + (void)memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.EnterDebuggerLoopAfterExit = true; + + // create the CLR Startup thread + osThreadCreate(osThread(CLRStartupThread), &clrSettings); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + while (true) { + osDelay(100); + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/mcuconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/mcuconf.h new file mode 100644 index 00000000..eeede4ff --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/mcuconf.h @@ -0,0 +1,384 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F7xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F7xx_MCUCONF +#define STM32F746_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 4 +#define STM32_PLLN_VALUE 216 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 25 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 +#define STM32_I2SSRC STM32_I2SSRC_OFF +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SP_VALUE 2 +#define STM32_PLLI2SQ_VALUE 2 +#define STM32_PLLI2SR_VALUE 2 +#define STM32_PLLSAIN_VALUE 192 +#define STM32_PLLSAIP_VALUE 2 +#define STM32_PLLSAIQ_VALUE 2 +#define STM32_PLLSAIR_VALUE 2 +#define STM32_PLLSAIDIVQ_VALUE 2 +#define STM32_PLLSAIDIVR_VALUE 2 +#define STM32_SAI1SEL STM32_SAI1SEL_OFF +#define STM32_SAI2SEL STM32_SAI2SEL_OFF +#define STM32_LCDTFT_REQUIRED FALSE +#define STM32_USART1SEL STM32_USART1SEL_PCLK2 +#define STM32_USART2SEL STM32_USART2SEL_PCLK1 +#define STM32_USART3SEL STM32_USART3SEL_PCLK1 +#define STM32_UART4SEL STM32_UART4SEL_PCLK1 +#define STM32_UART5SEL STM32_UART5SEL_PCLK1 +#define STM32_USART6SEL STM32_USART6SEL_PCLK2 +#define STM32_UART7SEL STM32_UART7SEL_PCLK1 +#define STM32_UART8SEL STM32_UART8SEL_PCLK1 +#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 +#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1 +#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1 +#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1 +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 +#define STM32_CECSEL STM32_CECSEL_HSIDIV488 +#define STM32_CK48MSEL STM32_CK48MSEL_PLL +#define STM32_SDMMCSEL STM32_SDMMCSEL_SYSCLK +#define STM32_SRAM2_NOCACHE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 TRUE +#define STM32_ADC_USE_ADC3 TRUE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_USE_CAN3 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 +#define STM32_CAN_CAN3_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 TRUE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 TRUE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_USE_I2C4 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C4_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C4_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 TRUE +#define STM32_PWM_USE_TIM8 TRUE +#define STM32_PWM_USE_TIM9 TRUE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 FALSE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000 +#define STM32_SDC_SDMMC_READ_TIMEOUT 1000 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 TRUE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 +#define STM32_SERIAL_UART7_PRIORITY 12 +#define STM32_SERIAL_UART8_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_USE_SPI4 TRUE +#define STM32_SPI_USE_SPI5 TRUE +#define STM32_SPI_USE_SPI6 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI5_DMA_PRIORITY 1 +#define STM32_SPI_SPI6_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 TRUE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 TRUE +#define STM32_UART_USE_UART7 FALSE +#define STM32_UART_USE_UART8 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_UART7_DMA_PRIORITY 0 +#define STM32_UART_UART8_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG TRUE + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/mcuconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/mcuconf_nf.h new file mode 100644 index 00000000..5ff03534 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/mcuconf_nf.h @@ -0,0 +1,9 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/nanoHAL.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/nanoHAL.cpp new file mode 100644 index 00000000..076a50fc --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/nanoHAL.cpp @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +void HAL_EnterBooterMode() +{ +} + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/target_board.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/target_board.h.in new file mode 100644 index 00000000..b980bc05 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nanoCLR/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOCLR_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nucleo144-f746zg.jpg b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nucleo144-f746zg.jpg new file mode 100644 index 00000000..b59f8467 Binary files /dev/null and b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/nucleo144-f746zg.jpg differ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_BlockStorage.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_BlockStorage.c new file mode 100644 index 00000000..9e7c7f55 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_BlockStorage.c @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice STM32Flash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &STM32Flash_BlockStorageInterface, &Device_BlockStorageConfig, false); +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_BlockStorage.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_BlockStorage.h new file mode 100644 index 00000000..aa50b1b7 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_common.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_common.c new file mode 100644 index 00000000..c633da5b --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_common.c @@ -0,0 +1,24 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include "target_common.h" + +HAL_SYSTEM_CONFIG HalSystemConfig = +{ + { true }, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, //ConvertCOM_DebugHandle(1), + 0, //ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + { RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size }, + { FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size } +}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_common.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_common.h.in new file mode 100644 index 00000000..3eddd436 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_common.h.in @@ -0,0 +1,41 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x200000C0) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x00040000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x08000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00100000) + +///////////////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////// +#define TARGETNAMESTRING "@CHIBIOS_BOARD@" +#define PLATFORMNAMESTRING "STM32F7" +/////////////////////////////////////////////// + +///////////////////////////////////// +#define PLATFORM_HAS_RNG TRUE +///////////////////////////////////// + +#endif /* _TARGET_COMMON_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_lwip_sntp_opts.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_lwip_sntp_opts.h new file mode 100644 index 00000000..ed534601 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_lwip_sntp_opts.h @@ -0,0 +1,18 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#define SNTP_SERVER_DEFAULT_ADDRESS "0.pool.ntp.org" + +// update delay (default 1 hour) +// (value in milliseconds) +#define SNTP_UPDATE_DELAY 3600000 + +// better have a startup delay because we can have DHCP enabled (default 30 seconds) +// value in milliseconds +#define SNTP_STARTUP_DELAY 5000 + +// retry timeout (2 minutes) +// value in milliseconds +#define SNTP_RETRY_TIMEOUT 2*6000 diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_nf_devices_onewire_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_nf_devices_onewire_config.cpp new file mode 100644 index 00000000..09f1420e --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_nf_devices_onewire_config.cpp @@ -0,0 +1,29 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_nf_devices_onewire_config.h" +#include + +/////////// +// UART4 // +/////////// + +// pin configuration for UART4 +// port for TX pin is: GPIOC +// TX pin: is GPIOC_10 +// GPIO alternate pin function is 8 +UART_CONFIG_PINS(4, GPIOC, 10, 8) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart4_TxBuffer[UART4_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart4_RxBuffer[UART4_RX_SIZE]; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_nf_devices_onewire_config.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_nf_devices_onewire_config.h new file mode 100644 index 00000000..76f90a10 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_nf_devices_onewire_config.h @@ -0,0 +1,17 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////// +// UART4 // +/////////// + +// enable USART4 +#define NF_ONEWIRE_STM32_UART_USE_USART4 TRUE + +// buffers size +// tx buffer size: 32 bytes +#define UART4_TX_SIZE 32 +// rx buffer size: 32 bytes +#define UART4_RX_SIZE 32 \ No newline at end of file diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_system_devices_dac_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_system_devices_dac_config.cpp new file mode 100644 index 00000000..88a70347 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_system_devices_dac_config.cpp @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_DAC_PORT_PIN_CHANNEL DacPortPinConfig[] = { + + // DAC1, channel 1, GPIO port A, pin 4 + {1, 1, GPIOA, 4}, + +}; + +const int DacChannelCount = ARRAYSIZE(DacPortPinConfig); diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_windows_devices_adc_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_windows_devices_adc_config.cpp new file mode 100644 index 00000000..7d5ccdeb --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_windows_devices_adc_config.cpp @@ -0,0 +1,32 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_adc_native_target.h" + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // ADC1 + {1, GPIOA, 3, ADC_CHANNEL_IN3}, + {1, GPIOC, 0, ADC_CHANNEL_IN10}, + {1, GPIOC, 3, ADC_CHANNEL_IN13}, + + // ADC3 + {3, GPIOF, 3, ADC_CHANNEL_IN9}, + {3, GPIOF, 5, ADC_CHANNEL_IN15}, + {3, GPIOF, 10, ADC_CHANNEL_IN8}, + + // ADC2/ADC3 + // Fill up with rest of set ADC pins + {2, GPIOB, 1, ADC_CHANNEL_IN9}, + {2, GPIOC, 2, ADC_CHANNEL_IN12}, + {3, GPIOF, 4, ADC_CHANNEL_IN14}, + + // these are the internal sources, available only at ADC1 + {1, NULL, 0, ADC_CHANNEL_SENSOR}, + {1, NULL, 0, ADC_CHANNEL_VREFINT}, + {1, NULL, 0, ADC_CHANNEL_VBAT}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_windows_devices_i2c_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_windows_devices_i2c_config.cpp new file mode 100644 index 00000000..16256ec8 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_windows_devices_i2c_config.cpp @@ -0,0 +1,30 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_i2c_native_target.h" + +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for SCL pin is: GPIOB +// port for SDA pin is: GPIOB +// SCL pin: is GPIOB_8 +// SDA pin: is GPIOB_9 +// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, GPIOB, GPIOB, 8, 9, 4) + +////////// +// I2C2 // +////////// + +// pin configuration for I2C2 +// port for SCL pin is: GPIOF +// port for SDA pin is: GPIOF +// SCL pin: is GPIOB_0 +// SDA pin: is GPIOB_1 +// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(2, GPIOF, GPIOF, 0, 1, 4) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_windows_devices_serialcommunication_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_windows_devices_serialcommunication_config.cpp new file mode 100644 index 00000000..92f732ec --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_windows_devices_serialcommunication_config.cpp @@ -0,0 +1,69 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_windows_devices_serialcommunication_config.h" +#include "win_dev_serial_native_target.h" + +/////////// +// UART2 // +/////////// + +// pin configuration for UART2 +// port for TX pin is: GPIOD +// port for RX pin is: GPIOD +// TX pin: is GPIOD_5 +// RX pin: is GPIOD_6 +// GPIO alternate pin function is 7 (see "Table 12. STM32F427xx and STM32F429xx alternate function mapping" in STM32F427xx and STM32F429xx datasheet) +UART_CONFIG_PINS(2, GPIOD, GPIOD, 5, 6, 7) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart2_TxBuffer[UART2_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart2_RxBuffer[UART2_RX_SIZE]; + +// initialization for UART2 +UART_INIT(2, UART2_TX_SIZE, UART2_RX_SIZE) + +// un-initialization for UART2 +UART_UNINIT(2) + + +/////////// +// UART6 // +/////////// + +// pin configuration for UART6 +// port for TX pin is: GPIOC +// port for RX pin is: GPIOC +// TX pin: is GPIOC_6 +// RX pin: is GPIOC_7 +// GPIO alternate pin function is 8 (see "Table 12. STM32F427xx and STM32F429xx alternate function mapping" in STM32F427xx and STM32F429xx datasheet) +UART_CONFIG_PINS(6, GPIOC, GPIOC, 6, 7, 8) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart6_TxBuffer[UART6_TX_SIZE]; + +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart6_RxBuffer[UART6_RX_SIZE]; + +// initialization for UART6 +UART_INIT(6, UART6_TX_SIZE, UART6_RX_SIZE) + +// un-initialization for UART6 +UART_UNINIT(6) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_windows_devices_serialcommunication_config.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_windows_devices_serialcommunication_config.h new file mode 100644 index 00000000..2c4f7c69 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_windows_devices_serialcommunication_config.h @@ -0,0 +1,31 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////// +// UART2 // +/////////// + +// enable USART2 +#define NF_SERIAL_COMM_STM32_UART_USE_USART2 TRUE + +// buffers size +// tx buffer size: 256 bytes +#define UART2_TX_SIZE 256 +// rx buffer size: 256 bytes +#define UART2_RX_SIZE 256 + + +/////////// +// UART6 // +/////////// + +// enable USART6 +#define NF_SERIAL_COMM_STM32_UART_USE_USART6 TRUE + +// buffers size +// tx buffer size: 256 bytes +#define UART6_TX_SIZE 256 +// rx buffer size: 256 bytes +#define UART6_RX_SIZE 256 diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_windows_devices_spi_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_windows_devices_spi_config.cpp new file mode 100644 index 00000000..f08c5650 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG/target_windows_devices_spi_config.cpp @@ -0,0 +1,10 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_spi_native_target.h" + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/CMakeLists.txt new file mode 100644 index 00000000..8b8ab9b2 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/CMakeLists.txt @@ -0,0 +1,202 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +cmake_minimum_required(VERSION 3.0) +ENABLE_LANGUAGE(ASM) + +# add header files with common OS definitions and board definitions specific for each image +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/target_common.h" @ONLY) + +set(NANOBOOTER_PROJECT_NAME "nanoBooter") +set(NANOCLR_PROJECT_NAME "nanoCLR") + +find_package(BuildUtils REQUIRED) +find_package(CHIBIOS REQUIRED) +find_package(ChibiOSnfOverlay REQUIRED) +find_package(WireProtocol REQUIRED) + +# packages for nanoFramework libraries +####################################### +# mandatory +find_package(NF_CoreCLR REQUIRED) + +####################################### +# optional + +# ChibiOS contrib repo +if(CHIBIOS_CONTRIB_REQUIRED) + find_package(ChibiOS-Contrib REQUIRED) +endif() + +# nF feature: debugger +if(NF_FEATURE_DEBUGGER) + find_package(NF_Debugger REQUIRED) + find_package(NF_Diagnostics REQUIRED) +endif() + +# nF feature: networking +if(USE_NETWORKING_OPTION) + find_package(CHIBIOS_LWIP REQUIRED) +endif() + +# nF feature: filesystem +if(USE_FILESYSTEM_OPTION) + find_package(CHIBIOS_FATFS REQUIRED) +endif() + +####################################### + +add_subdirectory("common") +add_subdirectory("nanoBooter") +add_subdirectory("nanoCLR") + +####################### +# nanoBooter executable + +add_executable( + # executables for project, project sources + ${NANOBOOTER_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + "${CMAKE_CURRENT_SOURCE_DIR}/target_BlockStorage.c" + + # need to add configuration manager to allow get/store configuration blocks + "${PROJECT_SOURCE_DIR}/src/HAL/nanoHAL_ConfigurationManager_stubs.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOBOOTER_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOBOOTER_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOBOOTER_SOURCES} + + ${CHIBIOS_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} +) + +####################### +# nanoCLR executable + +add_executable( + # executables for project, project sources + ${NANOCLR_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOCLR_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOCLR_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOCLR_SOURCES} + + ${CHIBIOS_SOURCES} + ${CHIBIOS_CONTRIB_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} + + # sources for nanoFramework libraries + ${NF_CoreCLR_SOURCES} + ${NF_Debugger_SOURCES} + ${NF_Diagnostics_SOURCES} + + # sources for nanoFramework APIs + ${TARGET_NANO_APIS_SOURCES} +) + +# add dependency from ChibiOS (this is required to make sure the ChibiOS repo is downloaded before the build starts) +add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf ChibiOS) +add_dependencies(${NANOCLR_PROJECT_NAME}.elf ChibiOS) + +# include common directories +include_directories( + ${CMAKE_CURRENT_BINARY_DIR} + ${CMAKE_CURRENT_SOURCE_DIR} + ${CMAKE_CURRENT_SOURCE_DIR}/common + ${PROJECT_SOURCE_DIR}/src/CLR/Core + ${PROJECT_SOURCE_DIR}/src/CLR/Include + ${PROJECT_SOURCE_DIR}/src/HAL/Include + ${PROJECT_SOURCE_DIR}/src/PAL/Include + + ${WireProtocol_INCLUDE_DIRS} + ${CHIBIOS_INCLUDE_DIRS} + ${ChibiOSnfOverlay_INCLUDE_DIRS} + ${CHIBIOS_CONTRIB_INCLUDE_DIRS} + + ${TARGET_CMSIS_COMMON_INCLUDE_DIRS} + ${TARGET_CHIBIOS_COMMON_INCLUDE_DIRS} +) + +# include directories for nanoBooter +target_include_directories(${NANOBOOTER_PROJECT_NAME}.elf PUBLIC + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter" + ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter + + ${TARGET_CMSIS_NANOBOOTER_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOBOOTER_INCLUDE_DIRS} +) + +# include directories for nanoCLR +target_include_directories(${NANOCLR_PROJECT_NAME}.elf PUBLIC + ${CMAKE_CURRENT_BINARY_DIR}/nanoCLR + ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR + + ${TARGET_CMSIS_NANOCLR_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOCLR_INCLUDE_DIRS} + + # directories for nanoFramework libraries + ${NF_CoreCLR_INCLUDE_DIRS} + ${NF_Debugger_INCLUDE_DIRS} + ${NF_Diagnostics_INCLUDE_DIRS} + + # includes for nanoFramework APIs + ${TARGET_NANO_APIS_INCLUDES} + + # includes for ChibiOS LwIP + ${CHIBIOS_LWIP_INCLUDE_DIRS} +) + +# set compiler options +nf_set_compiler_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_options(${NANOCLR_PROJECT_NAME}.elf) + +# set compiler definitions +nf_set_compiler_definitions(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_definitions(${NANOCLR_PROJECT_NAME}.elf) + +# set linker files +if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F401xE_booter-DEBUG.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/STM32F401xE_CLR-DEBUG.ld) +else() + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F401xE_booter.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/STM32F401xE_CLR.ld) +endif() + +# set linker options +nf_set_linker_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_linker_options(${NANOCLR_PROJECT_NAME}.elf) + +# add other linker flags +########################################################### +# the sizes of CRT heap and ChibiOS stacks are defined here +set_property(TARGET ${NANOBOOTER_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x400,--defsym=__crt_heap_size__=0x1000") +set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x2800") + +# generate output files +nf_generate_build_output_files(${NANOBOOTER_PROJECT_NAME}.elf) +nf_generate_build_output_files(${NANOCLR_PROJECT_NAME}.elf) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/README.md b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/README.md new file mode 100644 index 00000000..28532220 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/README.md @@ -0,0 +1,47 @@ +## ST of the shelve board ## + +The board used in this community contribution is the NUCLEO64_F401RE board from ST. The board can be purchased from various sources and should be about 20 euros. Further information on the Nucleo64 boards can be found in the user manual UM1724 on the ST side (www.st.com). The board used here is of revision c as can be found on the board's lower backside sticker. The board MB1136 C-02 is configured to use ST-LINK MCO as clock input for HSE so we have an HSE of 8 MHz. Plus X2 is mounted so we do have an LSE as well. This is reflected in the mcuconf.h in both nanoBooter and nanoCLR paths. If it is chosen to activate LSE as this is a for more accurate clock for RTC, the board.h file needs to be adjusted accordingly to use 32768 frequency for LSE. + +I prepared a custom made a 4-wire jumper to USB cable by cutting off one end (Type A part) and figuring out the required D+, D-, 5V and GND. These need to be connected as follows: + +USB V5 -> Can be ignored +USB GND -> GND on CN7 +USB D- -> PA11 on CN10 (outer row 7th pin from top) +USB D+ -> PA12 on CN10 (outer row 6th pin from top) + +Once these are connected and nanoFramework is flashed using the STM32 ST-LINK Utility the device should be visible in the Printf via SWO viewer function in the ST-LINK utility. Please set the frequency to match to what has been set in mcuconf.h (for the STM32F401RE it is 84MHz) and the Stimulus port to 0 and than hit start. If the board doesn't show then a reset (Black button on board) should do it. + +We can now fire up Visual Studio and view the Device explorer window the board should be visible there as well. Select the board (if not done already) and hit the device capabilities button. The board specifics can than be seen in the output window. + +Now you can start your adventure in the nanoFramework world and use one of the samples and adjust to the board specific features. Try to make a sample of yourself and publish it on f.e. www.hackster.io to show your achievement. + +For your convenience I've listed below the features and on what pins they can be found to help you out for an easy start. + +Arduino header pins: +==================== +D0 = COM2 RX +D1 = COM2 TX + +D2 - D9 can be used for an intermix of GPIO and PWM + +D14 = I2C1 SDA +D15 = I2C1 SCL + +A0 - A5 for Analog signal, please be aware the MCU has only one 12-bit ADC. + + +Connector CN7: +============== +1 = SPI3 SCK +2 = SPI3 MISO +3 = SPI3 MOSI + + +Connector CN10: +=============== +26 = SPI2 MOSI +28 = SPI2 MISO +30 = SPI2 SCK + + +**NOTE: This configuration was successfully tested on a NUCLEO64_F401RE board.** diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/board.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/board.c new file mode 100644 index 00000000..aece76d4 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/board.c @@ -0,0 +1,266 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) + gpio_setup_t PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_setup_t PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) + gpio_setup_t PKData; +#endif +} gpio_config_t; + +/** + * @brief STM32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +#endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB1(STM32_GPIO_EN_MASK); + rccEnableAHB1(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG + gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI + gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ + gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK + gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + * else. + */ +void __early_init(void) { + + stm32_gpio_init(); + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { + +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/board.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/board.h new file mode 100644 index 00000000..0ba7df63 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/board.h @@ -0,0 +1,1390 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#ifndef BOARD_H +#define BOARD_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* + * Setup for STMicroelectronics STM32 Nucleo64-F401RE board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_NUCLEO64_F401RE +#define BOARD_NAME "STMicroelectronics STM32 Nucleo64-F401RE" + +/* + * USB OTG Force + */ +#define BOARD_OTG_NOVBUSSENS + +/* + * Completely wacko definition of a flash sector here + */ +#define FLASH_SECTOR_11 ((uint32_t)11U) + +/* + * Board oscillators-related settings. + * NOTE: LSE not fitted. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768U +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 8000000U +#endif + +#define STM32_HSE_BYPASS + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U + +/* + * MCU type as defined in the ST header. + */ +#define STM32F401xE + +/* + * IO pins assignments. + */ +#define GPIOA_ARD_A0 0U +#define GPIOA_ADC1_IN0 0U +#define GPIOA_ARD_A1 1U +#define GPIOA_ADC1_IN1 1U +#define GPIOA_ARD_D1 2U +#define GPIOA_USART2_TX 2U +#define GPIOA_ARD_D0 3U +#define GPIOA_USART2_RX 3U +#define GPIOA_ARD_A2 4U +#define GPIOA_ADC1_IN4 4U +#define GPIOA_LED_GREEN 5U +#define GPIOA_ARD_D13 5U +#define GPIOA_ARD_D12 6U +#define GPIOA_ARD_D11 7U +#define GPIOA_ARD_D7 8U +#define GPIOA_ARD_D8 9U +#define GPIOA_ARD_D2 10U +#define GPIOA_OTG_FS_DM 11U +#define GPIOA_OTG_FS_DP 12U +#define GPIOA_SWDIO 13U +#define GPIOA_SWCLK 14U +#define GPIOA_PIN15 15U + +#define GPIOB_ARD_A3 0U +#define GPIOB_ADC1_IN8 0U +#define GPIOB_PIN1 1U +#define GPIOB_PIN2 2U +#define GPIOB_SWO 3U +#define GPIOB_ARD_D3 3U +#define GPIOB_ARD_D5 4U +#define GPIOB_ARD_D4 5U +#define GPIOB_ARD_D10 6U +#define GPIOB_PIN7 7U +#define GPIOB_ARD_D15 8U +#define GPIOB_ARD_D14 9U +#define GPIOB_ARD_D6 10U +#define GPIOB_PIN11 11U +#define GPIOB_PIN12 12U +#define GPIOB_SPI2_SCK 13U +#define GPIOB_SPI2_MISO 14U +#define GPIOB_SPI2_MOSI 15U + +#define GPIOC_ARD_A5 0U +#define GPIOC_ADC1_IN10 0U +#define GPIOC_ARD_A4 1U +#define GPIOC_ADC1_IN11 1U +#define GPIOC_PIN2 2U +#define GPIOC_PIN3 3U +#define GPIOC_PIN4 4U +#define GPIOC_PIN5 5U +#define GPIOC_PIN6 6U +#define GPIOC_ARD_D9 7U +#define GPIOC_PIN8 8U +#define GPIOC_PIN9 9U +#define GPIOC_SPI3_SCK 10U +#define GPIOC_SPI3_MISO 11U +#define GPIOC_SPI3_MOSI 12U +#define GPIOC_BUTTON 13U +#define GPIOC_OSC32_IN 14U +#define GPIOC_OSC32_OUT 15U + +#define GPIOD_PIN0 0U +#define GPIOD_PIN1 1U +#define GPIOD_PIN2 2U +#define GPIOD_PIN3 3U +#define GPIOD_PIN4 4U +#define GPIOD_PIN5 5U +#define GPIOD_PIN6 6U +#define GPIOD_PIN7 7U +#define GPIOD_PIN8 8U +#define GPIOD_PIN9 9U +#define GPIOD_PIN10 10U +#define GPIOD_PIN11 11U +#define GPIOD_PIN12 12U +#define GPIOD_PIN13 13U +#define GPIOD_PIN14 14U +#define GPIOD_PIN15 15U + +#define GPIOE_PIN0 0U +#define GPIOE_PIN1 1U +#define GPIOE_PIN2 2U +#define GPIOE_PIN3 3U +#define GPIOE_PIN4 4U +#define GPIOE_PIN5 5U +#define GPIOE_PIN6 6U +#define GPIOE_PIN7 7U +#define GPIOE_PIN8 8U +#define GPIOE_PIN9 9U +#define GPIOE_PIN10 10U +#define GPIOE_PIN11 11U +#define GPIOE_PIN12 12U +#define GPIOE_PIN13 13U +#define GPIOE_PIN14 14U +#define GPIOE_PIN15 15U + +#define GPIOF_PIN0 0U +#define GPIOF_PIN1 1U +#define GPIOF_PIN2 2U +#define GPIOF_PIN3 3U +#define GPIOF_PIN4 4U +#define GPIOF_PIN5 5U +#define GPIOF_PIN6 6U +#define GPIOF_PIN7 7U +#define GPIOF_PIN8 8U +#define GPIOF_PIN9 9U +#define GPIOF_PIN10 10U +#define GPIOF_PIN11 11U +#define GPIOF_PIN12 12U +#define GPIOF_PIN13 13U +#define GPIOF_PIN14 14U +#define GPIOF_PIN15 15U + +#define GPIOG_PIN0 0U +#define GPIOG_PIN1 1U +#define GPIOG_PIN2 2U +#define GPIOG_PIN3 3U +#define GPIOG_PIN4 4U +#define GPIOG_PIN5 5U +#define GPIOG_PIN6 6U +#define GPIOG_PIN7 7U +#define GPIOG_PIN8 8U +#define GPIOG_PIN9 9U +#define GPIOG_PIN10 10U +#define GPIOG_PIN11 11U +#define GPIOG_PIN12 12U +#define GPIOG_PIN13 13U +#define GPIOG_PIN14 14U +#define GPIOG_PIN15 15U + +#define GPIOH_OSC_IN 0U +#define GPIOH_OSC_OUT 1U +#define GPIOH_PIN2 2U +#define GPIOH_PIN3 3U +#define GPIOH_PIN4 4U +#define GPIOH_PIN5 5U +#define GPIOH_PIN6 6U +#define GPIOH_PIN7 7U +#define GPIOH_PIN8 8U +#define GPIOH_PIN9 9U +#define GPIOH_PIN10 10U +#define GPIOH_PIN11 11U +#define GPIOH_PIN12 12U +#define GPIOH_PIN13 13U +#define GPIOH_PIN14 14U +#define GPIOH_PIN15 15U + +#define GPIOI_PIN0 0U +#define GPIOI_PIN1 1U +#define GPIOI_PIN2 2U +#define GPIOI_PIN3 3U +#define GPIOI_PIN4 4U +#define GPIOI_PIN5 5U +#define GPIOI_PIN6 6U +#define GPIOI_PIN7 7U +#define GPIOI_PIN8 8U +#define GPIOI_PIN9 9U +#define GPIOI_PIN10 10U +#define GPIOI_PIN11 11U +#define GPIOI_PIN12 12U +#define GPIOI_PIN13 13U +#define GPIOI_PIN14 14U +#define GPIOI_PIN15 15U + +/* + * IO lines assignments. + */ +#define LINE_ARD_A0 PAL_LINE(GPIOA, 0U) +#define LINE_ADC1_IN0 PAL_LINE(GPIOA, 0U) +#define LINE_ARD_A1 PAL_LINE(GPIOA, 1U) +#define LINE_ADC1_IN1 PAL_LINE(GPIOA, 1U) +#define LINE_ARD_D1 PAL_LINE(GPIOA, 2U) +#define LINE_USART2_TX PAL_LINE(GPIOA, 2U) +#define LINE_ARD_D0 PAL_LINE(GPIOA, 3U) +#define LINE_USART2_RX PAL_LINE(GPIOA, 3U) +#define LINE_ARD_A2 PAL_LINE(GPIOA, 4U) +#define LINE_ADC1_IN4 PAL_LINE(GPIOA, 4U) +#define LINE_LED_GREEN PAL_LINE(GPIOA, 5U) +#define LINE_ARD_D13 PAL_LINE(GPIOA, 5U) +#define LINE_ARD_D12 PAL_LINE(GPIOA, 6U) +#define LINE_ARD_D11 PAL_LINE(GPIOA, 7U) +#define LINE_ARD_D7 PAL_LINE(GPIOA, 8U) +#define LINE_ARD_D8 PAL_LINE(GPIOA, 9U) +#define LINE_ARD_D2 PAL_LINE(GPIOA, 10U) +#define LINE_OTG_FS_DM PAL_LINE(GPIOA, 11U) +#define LINE_OTG_FS_DP PAL_LINE(GPIOA, 12U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) +#define LINE_ARD_A3 PAL_LINE(GPIOB, 0U) +#define LINE_ADC1_IN8 PAL_LINE(GPIOB, 0U) +#define LINE_SWO PAL_LINE(GPIOB, 3U) +#define LINE_ARD_D3 PAL_LINE(GPIOB, 3U) +#define LINE_ARD_D5 PAL_LINE(GPIOB, 4U) +#define LINE_ARD_D4 PAL_LINE(GPIOB, 5U) +#define LINE_ARD_D10 PAL_LINE(GPIOB, 6U) +#define LINE_ARD_D15 PAL_LINE(GPIOB, 8U) +#define LINE_ARD_D14 PAL_LINE(GPIOB, 9U) +#define LINE_ARD_D6 PAL_LINE(GPIOB, 10U) +#define LINE_ARD_A5 PAL_LINE(GPIOC, 0U) +#define LINE_ADC1_IN10 PAL_LINE(GPIOC, 0U) +#define LINE_ARD_A4 PAL_LINE(GPIOC, 1U) +#define LINE_ADC1_IN11 PAL_LINE(GPIOC, 1U) +#define LINE_ARD_D9 PAL_LINE(GPIOC, 7U) +#define LINE_BUTTON PAL_LINE(GPIOC, 13U) +#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) +#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) +#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) +#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * GPIOA setup: + * + * PA0 - ARD_A0 ADC1_IN0 (input pullup). + * PA1 - ARD_A1 ADC1_IN1 (input pullup). + * PA2 - ARD_D1 USART2_TX (alternate 7). + * PA3 - ARD_D0 USART2_RX (alternate 7). + * PA4 - ARD_A2 ADC1_IN4 (input pullup). + * PA5 - LED_GREEN ARD_D13 (output pushpull high). + * PA6 - ARD_D12 (input pullup). + * PA7 - ARD_D11 (input pullup). + * PA8 - ARD_D7 (input pullup). + * PA9 - ARD_D8 (input pullup). + * PA10 - ARD_D2 (input pullup). + * PA11 - OTG_FS_DM (alternate 10). + * PA12 - OTG_FS_DP (alternate 10). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - PIN15 (input pullup). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_ARD_A0) | \ + PIN_MODE_INPUT(GPIOA_ARD_A1) | \ + PIN_MODE_ALTERNATE(GPIOA_ARD_D1) | \ + PIN_MODE_ALTERNATE(GPIOA_ARD_D0) | \ + PIN_MODE_INPUT(GPIOA_ARD_A2) | \ + PIN_MODE_OUTPUT(GPIOA_LED_GREEN) | \ + PIN_MODE_INPUT(GPIOA_ARD_D12) | \ + PIN_MODE_INPUT(GPIOA_ARD_D11) | \ + PIN_MODE_INPUT(GPIOA_ARD_D7) | \ + PIN_MODE_INPUT(GPIOA_ARD_D8) | \ + PIN_MODE_INPUT(GPIOA_ARD_D2) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_INPUT(GPIOA_PIN15)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_A1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_A2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LED_GREEN) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D12) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D11) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D8) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_A1) | \ + PIN_OSPEED_MEDIUM(GPIOA_ARD_D1) | \ + PIN_OSPEED_MEDIUM(GPIOA_ARD_D0) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_A2) | \ + PIN_OSPEED_MEDIUM(GPIOA_LED_GREEN) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D12) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D11) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D7) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D8) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D2) | \ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ + PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ + PIN_OSPEED_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_ARD_A0) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_A1) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D1) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D0) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_A2) | \ + PIN_PUPDR_FLOATING(GPIOA_LED_GREEN) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D12) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D11) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D7) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D8) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D2) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \ + PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ + PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN15)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_ARD_A0) | \ + PIN_ODR_HIGH(GPIOA_ARD_A1) | \ + PIN_ODR_HIGH(GPIOA_ARD_D1) | \ + PIN_ODR_HIGH(GPIOA_ARD_D0) | \ + PIN_ODR_HIGH(GPIOA_ARD_A2) | \ + PIN_ODR_LOW(GPIOA_LED_GREEN) | \ + PIN_ODR_HIGH(GPIOA_ARD_D12) | \ + PIN_ODR_HIGH(GPIOA_ARD_D11) | \ + PIN_ODR_HIGH(GPIOA_ARD_D7) | \ + PIN_ODR_HIGH(GPIOA_ARD_D8) | \ + PIN_ODR_HIGH(GPIOA_ARD_D2) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_A1, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D1, 7U) | \ + PIN_AFIO_AF(GPIOA_ARD_D0, 7U) | \ + PIN_AFIO_AF(GPIOA_ARD_A2, 0U) | \ + PIN_AFIO_AF(GPIOA_LED_GREEN, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D12, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D11, 0U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_ARD_D7, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D8, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D2, 0U) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10U) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10U) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN15, 0U)) + +/* + * GPIOB setup: + * + * PB0 - ARD_A3 ADC1_IN8 (input pullup). + * PB1 - PIN1 (input pullup). + * PB2 - PIN2 (input pullup). + * PB3 - SWO ARD_D3 (alternate 0). + * PB4 - ARD_D5 (input pullup). + * PB5 - ARD_D4 (input pullup). + * PB6 - ARD_D10 (input pullup). + * PB7 - PIN7 (input pullup). + * PB8 - ARD_D15 (alternate 4). + * PB9 - ARD_D14 (alternate 4). + * PB10 - ARD_D6 (input pullup). + * PB11 - PIN11 (input pullup). + * PB12 - PIN12 (input pullup). + * PB13 - SPI2_SCK (alternate 5). + * PB14 - SPI2_MISO (alternate 5). + * PB15 - SPI2_MOSI (alternate 5). + */ +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_ARD_A3) | \ + PIN_MODE_INPUT(GPIOB_PIN1) | \ + PIN_MODE_INPUT(GPIOB_PIN2) | \ + PIN_MODE_ALTERNATE(GPIOB_SWO) | \ + PIN_MODE_INPUT(GPIOB_ARD_D5) | \ + PIN_MODE_INPUT(GPIOB_ARD_D4) | \ + PIN_MODE_INPUT(GPIOB_ARD_D10) | \ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_ALTERNATE(GPIOB_ARD_D15) | \ + PIN_MODE_ALTERNATE(GPIOB_ARD_D14) | \ + PIN_MODE_INPUT(GPIOB_ARD_D6) | \ + PIN_MODE_INPUT(GPIOB_PIN11) | \ + PIN_MODE_INPUT(GPIOB_PIN12) | \ + PIN_MODE_ALTERNATE(GPIOB_SPI2_SCK) | \ + PIN_MODE_ALTERNATE(GPIOB_SPI2_MISO) | \ + PIN_MODE_ALTERNATE(GPIOB_SPI2_MOSI)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ARD_A3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D10) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_ARD_D15) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_ARD_D14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SPI2_SCK) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SPI2_MISO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SPI2_MOSI)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ARD_A3) | \ + PIN_OSPEED_HIGH(GPIOB_PIN1) | \ + PIN_OSPEED_HIGH(GPIOB_PIN2) | \ + PIN_OSPEED_HIGH(GPIOB_SWO) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D5) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D4) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D10) | \ + PIN_OSPEED_HIGH(GPIOB_PIN7) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D15) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D14) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D6) | \ + PIN_OSPEED_HIGH(GPIOB_PIN11) | \ + PIN_OSPEED_HIGH(GPIOB_PIN12) | \ + PIN_OSPEED_HIGH(GPIOB_SPI2_SCK) | \ + PIN_OSPEED_HIGH(GPIOB_SPI2_MISO) | \ + PIN_OSPEED_HIGH(GPIOB_SPI2_MOSI)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_ARD_A3) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOB_SWO) | \ + PIN_PUPDR_PULLUP(GPIOB_ARD_D5) | \ + PIN_PUPDR_PULLUP(GPIOB_ARD_D4) | \ + PIN_PUPDR_PULLUP(GPIOB_ARD_D10) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D15) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D14) | \ + PIN_PUPDR_PULLUP(GPIOB_ARD_D6) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOB_SPI2_SCK) | \ + PIN_PUPDR_FLOATING(GPIOB_SPI2_MISO) | \ + PIN_PUPDR_FLOATING(GPIOB_SPI2_MOSI)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_ARD_A3) | \ + PIN_ODR_HIGH(GPIOB_PIN1) | \ + PIN_ODR_HIGH(GPIOB_PIN2) | \ + PIN_ODR_HIGH(GPIOB_SWO) | \ + PIN_ODR_HIGH(GPIOB_ARD_D5) | \ + PIN_ODR_HIGH(GPIOB_ARD_D4) | \ + PIN_ODR_HIGH(GPIOB_ARD_D10) | \ + PIN_ODR_HIGH(GPIOB_PIN7) | \ + PIN_ODR_LOW(GPIOB_ARD_D15) | \ + PIN_ODR_LOW(GPIOB_ARD_D14) | \ + PIN_ODR_HIGH(GPIOB_ARD_D6) | \ + PIN_ODR_HIGH(GPIOB_PIN11) | \ + PIN_ODR_HIGH(GPIOB_PIN12) | \ + PIN_ODR_LOW(GPIOB_SPI2_SCK) | \ + PIN_ODR_LOW(GPIOB_SPI2_MISO) | \ + PIN_ODR_LOW(GPIOB_SPI2_MOSI)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ARD_A3, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOB_SWO, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D5, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D4, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D10, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN7, 0U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_ARD_D15, 4U) | \ + PIN_AFIO_AF(GPIOB_ARD_D14, 4U) | \ + PIN_AFIO_AF(GPIOB_ARD_D6, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOB_SPI2_SCK, 5U) | \ + PIN_AFIO_AF(GPIOB_SPI2_MISO, 5U) | \ + PIN_AFIO_AF(GPIOB_SPI2_MOSI, 5U)) + +/* + * GPIOC setup: + * + * PC0 - ARD_A5 ADC1_IN10 (input pullup). + * PC1 - ARD_A4 ADC1_IN11 (input pullup). + * PC2 - PIN2 (input pullup). + * PC3 - PIN3 (input pullup). + * PC4 - PIN4 (input pullup). + * PC5 - PIN5 (input pullup). + * PC6 - PIN6 (input pullup). + * PC7 - ARD_D9 (input pullup). + * PC8 - PIN8 (input pullup). + * PC9 - PIN9 (input pullup). + * PC10 - SPI3_SCK (alternative 5). + * PC11 - SPI3_MISO (alternative 5). + * PC12 - SPI3_MOSI (alternative 5). + * PC13 - BUTTON (input floating). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_ARD_A5) | \ + PIN_MODE_INPUT(GPIOC_ARD_A4) | \ + PIN_MODE_INPUT(GPIOC_PIN2) | \ + PIN_MODE_INPUT(GPIOC_PIN3) | \ + PIN_MODE_INPUT(GPIOC_PIN4) | \ + PIN_MODE_INPUT(GPIOC_PIN5) | \ + PIN_MODE_INPUT(GPIOC_PIN6) | \ + PIN_MODE_INPUT(GPIOC_ARD_D9) | \ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_INPUT(GPIOC_PIN9) | \ + PIN_MODE_ALTERNATE(GPIOC_SPI3_SCK) | \ + PIN_MODE_ALTERNATE(GPIOC_SPI3_MISO) | \ + PIN_MODE_ALTERNATE(GPIOC_SPI3_MOSI) | \ + PIN_MODE_INPUT(GPIOC_BUTTON) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ARD_A5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_A4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_D9) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SPI3_SCK) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SPI3_MISO) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SPI3_MOSI) | \ + PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ARD_A5) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_A4) | \ + PIN_OSPEED_HIGH(GPIOC_PIN2) | \ + PIN_OSPEED_HIGH(GPIOC_PIN3) | \ + PIN_OSPEED_HIGH(GPIOC_PIN4) | \ + PIN_OSPEED_HIGH(GPIOC_PIN5) | \ + PIN_OSPEED_HIGH(GPIOC_PIN6) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_D9) | \ + PIN_OSPEED_HIGH(GPIOC_PIN8) | \ + PIN_OSPEED_HIGH(GPIOC_PIN9) | \ + PIN_OSPEED_HIGH(GPIOC_SPI3_SCK) | \ + PIN_OSPEED_HIGH(GPIOC_SPI3_MISO) | \ + PIN_OSPEED_HIGH(GPIOC_SPI3_MOSI) | \ + PIN_OSPEED_HIGH(GPIOC_BUTTON) | \ + PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \ + PIN_OSPEED_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_ARD_A5) | \ + PIN_PUPDR_PULLUP(GPIOC_ARD_A4) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOC_ARD_D9) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOC_SPI3_SCK) | \ + PIN_PUPDR_FLOATING(GPIOC_SPI3_MISO) | \ + PIN_PUPDR_FLOATING(GPIOC_SPI3_MOSI) | \ + PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_ARD_A5) | \ + PIN_ODR_HIGH(GPIOC_ARD_A4) | \ + PIN_ODR_HIGH(GPIOC_PIN2) | \ + PIN_ODR_HIGH(GPIOC_PIN3) | \ + PIN_ODR_HIGH(GPIOC_PIN4) | \ + PIN_ODR_HIGH(GPIOC_PIN5) | \ + PIN_ODR_HIGH(GPIOC_PIN6) | \ + PIN_ODR_HIGH(GPIOC_ARD_D9) | \ + PIN_ODR_HIGH(GPIOC_PIN8) | \ + PIN_ODR_HIGH(GPIOC_PIN9) | \ + PIN_ODR_LOW(GPIOC_SPI3_SCK) | \ + PIN_ODR_LOW(GPIOC_SPI3_MISO) | \ + PIN_ODR_LOW(GPIOC_SPI3_MOSI) | \ + PIN_ODR_HIGH(GPIOC_BUTTON) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ARD_A5, 0U) | \ + PIN_AFIO_AF(GPIOC_ARD_A4, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOC_ARD_D9, 0U)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOC_SPI3_SCK, 5U) | \ + PIN_AFIO_AF(GPIOC_SPI3_MISO, 5U) | \ + PIN_AFIO_AF(GPIOC_SPI3_MOSI, 5U) | \ + PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) + +/* + * GPIOD setup: + * + * PD0 - PIN0 (input pullup). + * PD1 - PIN1 (input pullup). + * PD2 - PIN2 (input pullup). + * PD3 - PIN3 (input pullup). + * PD4 - PIN4 (input pullup). + * PD5 - PIN5 (input pullup). + * PD6 - PIN6 (input pullup). + * PD7 - PIN7 (input pullup). + * PD8 - PIN8 (input pullup). + * PD9 - PIN9 (input pullup). + * PD10 - PIN10 (input pullup). + * PD11 - PIN11 (input pullup). + * PD12 - PIN12 (input pullup). + * PD13 - PIN13 (input pullup). + * PD14 - PIN14 (input pullup). + * PD15 - PIN15 (input pullup). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ + PIN_MODE_INPUT(GPIOD_PIN1) | \ + PIN_MODE_INPUT(GPIOD_PIN2) | \ + PIN_MODE_INPUT(GPIOD_PIN3) | \ + PIN_MODE_INPUT(GPIOD_PIN4) | \ + PIN_MODE_INPUT(GPIOD_PIN5) | \ + PIN_MODE_INPUT(GPIOD_PIN6) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_INPUT(GPIOD_PIN8) | \ + PIN_MODE_INPUT(GPIOD_PIN9) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_PIN11) | \ + PIN_MODE_INPUT(GPIOD_PIN12) | \ + PIN_MODE_INPUT(GPIOD_PIN13) | \ + PIN_MODE_INPUT(GPIOD_PIN14) | \ + PIN_MODE_INPUT(GPIOD_PIN15)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ + PIN_OSPEED_HIGH(GPIOD_PIN1) | \ + PIN_OSPEED_HIGH(GPIOD_PIN2) | \ + PIN_OSPEED_HIGH(GPIOD_PIN3) | \ + PIN_OSPEED_HIGH(GPIOD_PIN4) | \ + PIN_OSPEED_HIGH(GPIOD_PIN5) | \ + PIN_OSPEED_HIGH(GPIOD_PIN6) | \ + PIN_OSPEED_HIGH(GPIOD_PIN7) | \ + PIN_OSPEED_HIGH(GPIOD_PIN8) | \ + PIN_OSPEED_HIGH(GPIOD_PIN9) | \ + PIN_OSPEED_HIGH(GPIOD_PIN10) | \ + PIN_OSPEED_HIGH(GPIOD_PIN11) | \ + PIN_OSPEED_HIGH(GPIOD_PIN12) | \ + PIN_OSPEED_HIGH(GPIOD_PIN13) | \ + PIN_OSPEED_HIGH(GPIOD_PIN14) | \ + PIN_OSPEED_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN15)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ + PIN_ODR_HIGH(GPIOD_PIN1) | \ + PIN_ODR_HIGH(GPIOD_PIN2) | \ + PIN_ODR_HIGH(GPIOD_PIN3) | \ + PIN_ODR_HIGH(GPIOD_PIN4) | \ + PIN_ODR_HIGH(GPIOD_PIN5) | \ + PIN_ODR_HIGH(GPIOD_PIN6) | \ + PIN_ODR_HIGH(GPIOD_PIN7) | \ + PIN_ODR_HIGH(GPIOD_PIN8) | \ + PIN_ODR_HIGH(GPIOD_PIN9) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_PIN11) | \ + PIN_ODR_HIGH(GPIOD_PIN12) | \ + PIN_ODR_HIGH(GPIOD_PIN13) | \ + PIN_ODR_HIGH(GPIOD_PIN14) | \ + PIN_ODR_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN15, 0U)) + +/* + * GPIOE setup: + * + * PE0 - PIN0 (input pullup). + * PE1 - PIN1 (input pullup). + * PE2 - PIN2 (input pullup). + * PE3 - PIN3 (input pullup). + * PE4 - PIN4 (input pullup). + * PE5 - PIN5 (input pullup). + * PE6 - PIN6 (input pullup). + * PE7 - PIN7 (input pullup). + * PE8 - PIN8 (input pullup). + * PE9 - PIN9 (input pullup). + * PE10 - PIN10 (input pullup). + * PE11 - PIN11 (input pullup). + * PE12 - PIN12 (input pullup). + * PE13 - PIN13 (input pullup). + * PE14 - PIN14 (input pullup). + * PE15 - PIN15 (input pullup). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ + PIN_MODE_INPUT(GPIOE_PIN1) | \ + PIN_MODE_INPUT(GPIOE_PIN2) | \ + PIN_MODE_INPUT(GPIOE_PIN3) | \ + PIN_MODE_INPUT(GPIOE_PIN4) | \ + PIN_MODE_INPUT(GPIOE_PIN5) | \ + PIN_MODE_INPUT(GPIOE_PIN6) | \ + PIN_MODE_INPUT(GPIOE_PIN7) | \ + PIN_MODE_INPUT(GPIOE_PIN8) | \ + PIN_MODE_INPUT(GPIOE_PIN9) | \ + PIN_MODE_INPUT(GPIOE_PIN10) | \ + PIN_MODE_INPUT(GPIOE_PIN11) | \ + PIN_MODE_INPUT(GPIOE_PIN12) | \ + PIN_MODE_INPUT(GPIOE_PIN13) | \ + PIN_MODE_INPUT(GPIOE_PIN14) | \ + PIN_MODE_INPUT(GPIOE_PIN15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ + PIN_OSPEED_HIGH(GPIOE_PIN1) | \ + PIN_OSPEED_HIGH(GPIOE_PIN2) | \ + PIN_OSPEED_HIGH(GPIOE_PIN3) | \ + PIN_OSPEED_HIGH(GPIOE_PIN4) | \ + PIN_OSPEED_HIGH(GPIOE_PIN5) | \ + PIN_OSPEED_HIGH(GPIOE_PIN6) | \ + PIN_OSPEED_HIGH(GPIOE_PIN7) | \ + PIN_OSPEED_HIGH(GPIOE_PIN8) | \ + PIN_OSPEED_HIGH(GPIOE_PIN9) | \ + PIN_OSPEED_HIGH(GPIOE_PIN10) | \ + PIN_OSPEED_HIGH(GPIOE_PIN11) | \ + PIN_OSPEED_HIGH(GPIOE_PIN12) | \ + PIN_OSPEED_HIGH(GPIOE_PIN13) | \ + PIN_OSPEED_HIGH(GPIOE_PIN14) | \ + PIN_OSPEED_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ + PIN_ODR_HIGH(GPIOE_PIN1) | \ + PIN_ODR_HIGH(GPIOE_PIN2) | \ + PIN_ODR_HIGH(GPIOE_PIN3) | \ + PIN_ODR_HIGH(GPIOE_PIN4) | \ + PIN_ODR_HIGH(GPIOE_PIN5) | \ + PIN_ODR_HIGH(GPIOE_PIN6) | \ + PIN_ODR_HIGH(GPIOE_PIN7) | \ + PIN_ODR_HIGH(GPIOE_PIN8) | \ + PIN_ODR_HIGH(GPIOE_PIN9) | \ + PIN_ODR_HIGH(GPIOE_PIN10) | \ + PIN_ODR_HIGH(GPIOE_PIN11) | \ + PIN_ODR_HIGH(GPIOE_PIN12) | \ + PIN_ODR_HIGH(GPIOE_PIN13) | \ + PIN_ODR_HIGH(GPIOE_PIN14) | \ + PIN_ODR_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN7, 0U)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN15, 0U)) + +/* + * GPIOF setup: + * + * PF0 - PIN0 (input pullup). + * PF1 - PIN1 (input pullup). + * PF2 - PIN2 (input pullup). + * PF3 - PIN3 (input pullup). + * PF4 - PIN4 (input pullup). + * PF5 - PIN5 (input pullup). + * PF6 - PIN6 (input pullup). + * PF7 - PIN7 (input pullup). + * PF8 - PIN8 (input pullup). + * PF9 - PIN9 (input pullup). + * PF10 - PIN10 (input pullup). + * PF11 - PIN11 (input pullup). + * PF12 - PIN12 (input pullup). + * PF13 - PIN13 (input pullup). + * PF14 - PIN14 (input pullup). + * PF15 - PIN15 (input pullup). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ + PIN_MODE_INPUT(GPIOF_PIN1) | \ + PIN_MODE_INPUT(GPIOF_PIN2) | \ + PIN_MODE_INPUT(GPIOF_PIN3) | \ + PIN_MODE_INPUT(GPIOF_PIN4) | \ + PIN_MODE_INPUT(GPIOF_PIN5) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_INPUT(GPIOF_PIN7) | \ + PIN_MODE_INPUT(GPIOF_PIN8) | \ + PIN_MODE_INPUT(GPIOF_PIN9) | \ + PIN_MODE_INPUT(GPIOF_PIN10) | \ + PIN_MODE_INPUT(GPIOF_PIN11) | \ + PIN_MODE_INPUT(GPIOF_PIN12) | \ + PIN_MODE_INPUT(GPIOF_PIN13) | \ + PIN_MODE_INPUT(GPIOF_PIN14) | \ + PIN_MODE_INPUT(GPIOF_PIN15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \ + PIN_OSPEED_HIGH(GPIOF_PIN1) | \ + PIN_OSPEED_HIGH(GPIOF_PIN2) | \ + PIN_OSPEED_HIGH(GPIOF_PIN3) | \ + PIN_OSPEED_HIGH(GPIOF_PIN4) | \ + PIN_OSPEED_HIGH(GPIOF_PIN5) | \ + PIN_OSPEED_HIGH(GPIOF_PIN6) | \ + PIN_OSPEED_HIGH(GPIOF_PIN7) | \ + PIN_OSPEED_HIGH(GPIOF_PIN8) | \ + PIN_OSPEED_HIGH(GPIOF_PIN9) | \ + PIN_OSPEED_HIGH(GPIOF_PIN10) | \ + PIN_OSPEED_HIGH(GPIOF_PIN11) | \ + PIN_OSPEED_HIGH(GPIOF_PIN12) | \ + PIN_OSPEED_HIGH(GPIOF_PIN13) | \ + PIN_OSPEED_HIGH(GPIOF_PIN14) | \ + PIN_OSPEED_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ + PIN_ODR_HIGH(GPIOF_PIN1) | \ + PIN_ODR_HIGH(GPIOF_PIN2) | \ + PIN_ODR_HIGH(GPIOF_PIN3) | \ + PIN_ODR_HIGH(GPIOF_PIN4) | \ + PIN_ODR_HIGH(GPIOF_PIN5) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_PIN7) | \ + PIN_ODR_HIGH(GPIOF_PIN8) | \ + PIN_ODR_HIGH(GPIOF_PIN9) | \ + PIN_ODR_HIGH(GPIOF_PIN10) | \ + PIN_ODR_HIGH(GPIOF_PIN11) | \ + PIN_ODR_HIGH(GPIOF_PIN12) | \ + PIN_ODR_HIGH(GPIOF_PIN13) | \ + PIN_ODR_HIGH(GPIOF_PIN14) | \ + PIN_ODR_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN7, 0U)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN15, 0U)) + +/* + * GPIOG setup: + * + * PG0 - PIN0 (input pullup). + * PG1 - PIN1 (input pullup). + * PG2 - PIN2 (input pullup). + * PG3 - PIN3 (input pullup). + * PG4 - PIN4 (input pullup). + * PG5 - PIN5 (input pullup). + * PG6 - PIN6 (input pullup). + * PG7 - PIN7 (input pullup). + * PG8 - PIN8 (input pullup). + * PG9 - PIN9 (input pullup). + * PG10 - PIN10 (input pullup). + * PG11 - PIN11 (input pullup). + * PG12 - PIN12 (input pullup). + * PG13 - PIN13 (input pullup). + * PG14 - PIN14 (input pullup). + * PG15 - PIN15 (input pullup). + */ +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \ + PIN_MODE_INPUT(GPIOG_PIN1) | \ + PIN_MODE_INPUT(GPIOG_PIN2) | \ + PIN_MODE_INPUT(GPIOG_PIN3) | \ + PIN_MODE_INPUT(GPIOG_PIN4) | \ + PIN_MODE_INPUT(GPIOG_PIN5) | \ + PIN_MODE_INPUT(GPIOG_PIN6) | \ + PIN_MODE_INPUT(GPIOG_PIN7) | \ + PIN_MODE_INPUT(GPIOG_PIN8) | \ + PIN_MODE_INPUT(GPIOG_PIN9) | \ + PIN_MODE_INPUT(GPIOG_PIN10) | \ + PIN_MODE_INPUT(GPIOG_PIN11) | \ + PIN_MODE_INPUT(GPIOG_PIN12) | \ + PIN_MODE_INPUT(GPIOG_PIN13) | \ + PIN_MODE_INPUT(GPIOG_PIN14) | \ + PIN_MODE_INPUT(GPIOG_PIN15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_PIN0) | \ + PIN_OSPEED_HIGH(GPIOG_PIN1) | \ + PIN_OSPEED_HIGH(GPIOG_PIN2) | \ + PIN_OSPEED_HIGH(GPIOG_PIN3) | \ + PIN_OSPEED_HIGH(GPIOG_PIN4) | \ + PIN_OSPEED_HIGH(GPIOG_PIN5) | \ + PIN_OSPEED_HIGH(GPIOG_PIN6) | \ + PIN_OSPEED_HIGH(GPIOG_PIN7) | \ + PIN_OSPEED_HIGH(GPIOG_PIN8) | \ + PIN_OSPEED_HIGH(GPIOG_PIN9) | \ + PIN_OSPEED_HIGH(GPIOG_PIN10) | \ + PIN_OSPEED_HIGH(GPIOG_PIN11) | \ + PIN_OSPEED_HIGH(GPIOG_PIN12) | \ + PIN_OSPEED_HIGH(GPIOG_PIN13) | \ + PIN_OSPEED_HIGH(GPIOG_PIN14) | \ + PIN_OSPEED_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ + PIN_ODR_HIGH(GPIOG_PIN1) | \ + PIN_ODR_HIGH(GPIOG_PIN2) | \ + PIN_ODR_HIGH(GPIOG_PIN3) | \ + PIN_ODR_HIGH(GPIOG_PIN4) | \ + PIN_ODR_HIGH(GPIOG_PIN5) | \ + PIN_ODR_HIGH(GPIOG_PIN6) | \ + PIN_ODR_HIGH(GPIOG_PIN7) | \ + PIN_ODR_HIGH(GPIOG_PIN8) | \ + PIN_ODR_HIGH(GPIOG_PIN9) | \ + PIN_ODR_HIGH(GPIOG_PIN10) | \ + PIN_ODR_HIGH(GPIOG_PIN11) | \ + PIN_ODR_HIGH(GPIOG_PIN12) | \ + PIN_ODR_HIGH(GPIOG_PIN13) | \ + PIN_ODR_HIGH(GPIOG_PIN14) | \ + PIN_ODR_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN7, 0U)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN15, 0U)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - PIN2 (input pullup). + * PH3 - PIN3 (input pullup). + * PH4 - PIN4 (input pullup). + * PH5 - PIN5 (input pullup). + * PH6 - PIN6 (input pullup). + * PH7 - PIN7 (input pullup). + * PH8 - PIN8 (input pullup). + * PH9 - PIN9 (input pullup). + * PH10 - PIN10 (input pullup). + * PH11 - PIN11 (input pullup). + * PH12 - PIN12 (input pullup). + * PH13 - PIN13 (input pullup). + * PH14 - PIN14 (input pullup). + * PH15 - PIN15 (input pullup). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOH_PIN2) | \ + PIN_MODE_INPUT(GPIOH_PIN3) | \ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_INPUT(GPIOH_PIN5) | \ + PIN_MODE_INPUT(GPIOH_PIN6) | \ + PIN_MODE_INPUT(GPIOH_PIN7) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ + PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ + PIN_OSPEED_HIGH(GPIOH_PIN2) | \ + PIN_OSPEED_HIGH(GPIOH_PIN3) | \ + PIN_OSPEED_HIGH(GPIOH_PIN4) | \ + PIN_OSPEED_HIGH(GPIOH_PIN5) | \ + PIN_OSPEED_HIGH(GPIOH_PIN6) | \ + PIN_OSPEED_HIGH(GPIOH_PIN7) | \ + PIN_OSPEED_HIGH(GPIOH_PIN8) | \ + PIN_OSPEED_HIGH(GPIOH_PIN9) | \ + PIN_OSPEED_HIGH(GPIOH_PIN10) | \ + PIN_OSPEED_HIGH(GPIOH_PIN11) | \ + PIN_OSPEED_HIGH(GPIOH_PIN12) | \ + PIN_OSPEED_HIGH(GPIOH_PIN13) | \ + PIN_OSPEED_HIGH(GPIOH_PIN14) | \ + PIN_OSPEED_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0U)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0U)) + +/* + * GPIOI setup: + * + * PI0 - PIN0 (input pullup). + * PI1 - PIN1 (input pullup). + * PI2 - PIN2 (input pullup). + * PI3 - PIN3 (input pullup). + * PI4 - PIN4 (input pullup). + * PI5 - PIN5 (input pullup). + * PI6 - PIN6 (input pullup). + * PI7 - PIN7 (input pullup). + * PI8 - PIN8 (input pullup). + * PI9 - PIN9 (input pullup). + * PI10 - PIN10 (input pullup). + * PI11 - PIN11 (input pullup). + * PI12 - PIN12 (input pullup). + * PI13 - PIN13 (input pullup). + * PI14 - PIN14 (input pullup). + * PI15 - PIN15 (input pullup). + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ + PIN_MODE_INPUT(GPIOI_PIN1) | \ + PIN_MODE_INPUT(GPIOI_PIN2) | \ + PIN_MODE_INPUT(GPIOI_PIN3) | \ + PIN_MODE_INPUT(GPIOI_PIN4) | \ + PIN_MODE_INPUT(GPIOI_PIN5) | \ + PIN_MODE_INPUT(GPIOI_PIN6) | \ + PIN_MODE_INPUT(GPIOI_PIN7) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_INPUT(GPIOI_PIN9) | \ + PIN_MODE_INPUT(GPIOI_PIN10) | \ + PIN_MODE_INPUT(GPIOI_PIN11) | \ + PIN_MODE_INPUT(GPIOI_PIN12) | \ + PIN_MODE_INPUT(GPIOI_PIN13) | \ + PIN_MODE_INPUT(GPIOI_PIN14) | \ + PIN_MODE_INPUT(GPIOI_PIN15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_HIGH(GPIOI_PIN0) | \ + PIN_OSPEED_HIGH(GPIOI_PIN1) | \ + PIN_OSPEED_HIGH(GPIOI_PIN2) | \ + PIN_OSPEED_HIGH(GPIOI_PIN3) | \ + PIN_OSPEED_HIGH(GPIOI_PIN4) | \ + PIN_OSPEED_HIGH(GPIOI_PIN5) | \ + PIN_OSPEED_HIGH(GPIOI_PIN6) | \ + PIN_OSPEED_HIGH(GPIOI_PIN7) | \ + PIN_OSPEED_HIGH(GPIOI_PIN8) | \ + PIN_OSPEED_HIGH(GPIOI_PIN9) | \ + PIN_OSPEED_HIGH(GPIOI_PIN10) | \ + PIN_OSPEED_HIGH(GPIOI_PIN11) | \ + PIN_OSPEED_HIGH(GPIOI_PIN12) | \ + PIN_OSPEED_HIGH(GPIOI_PIN13) | \ + PIN_OSPEED_HIGH(GPIOI_PIN14) | \ + PIN_OSPEED_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ + PIN_ODR_HIGH(GPIOI_PIN1) | \ + PIN_ODR_HIGH(GPIOI_PIN2) | \ + PIN_ODR_HIGH(GPIOI_PIN3) | \ + PIN_ODR_HIGH(GPIOI_PIN4) | \ + PIN_ODR_HIGH(GPIOI_PIN5) | \ + PIN_ODR_HIGH(GPIOI_PIN6) | \ + PIN_ODR_HIGH(GPIOI_PIN7) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_PIN9) | \ + PIN_ODR_HIGH(GPIOI_PIN10) | \ + PIN_ODR_HIGH(GPIOI_PIN11) | \ + PIN_ODR_HIGH(GPIOI_PIN12) | \ + PIN_ODR_HIGH(GPIOI_PIN13) | \ + PIN_ODR_HIGH(GPIOI_PIN14) | \ + PIN_ODR_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN7, 0U)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN15, 0U)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/common/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/common/CMakeLists.txt new file mode 100644 index 00000000..42be0d5f --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/common/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c") + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/common/Device_BlockStorage-DEBUG.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 00000000..0e822535 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,97 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +//16kB block +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 1 }, // 08000000 nanoBooter + { BlockRange_BLOCKTYPE_CODE , 2, 3 } // 08008000 nanoCLR +}; + +//64kB block +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 08010000 nanoCLR +}; + +//384kB block +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 1 }, // 08020000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 2, 5 } // 08040000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08010000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 6, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00080000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/common/Device_BlockStorage.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/common/Device_BlockStorage.c new file mode 100644 index 00000000..6e381213 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/common/Device_BlockStorage.c @@ -0,0 +1,97 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +//16kB block +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 0 }, // 08000000 nanoBooter + { BlockRange_BLOCKTYPE_CODE , 1, 3 } // 08004000 nanoCLR +}; + +//64kB block +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 08010000 nanoCLR +}; + +//384kB block +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 1 }, // 08020000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 2, 5 } // 08040000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08010000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 6, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00080000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/common/serialcfg.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/common/serialcfg.h new file mode 100644 index 00000000..bb32facc --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/common/serialcfg.h @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef SERIALCFG_H +#define SERIALCFG_H + +// define which serial driver the Wire Protocol will be using +#define SERIAL_DRIVER SD2 + +#endif /* SERIALCFG_H */ + +/** @} */ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/managed_helpers/README.md b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/managed_helpers/README.md new file mode 100644 index 00000000..604b1bc1 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/managed_helpers/README.md @@ -0,0 +1,5 @@ +## Managed code helpers + +This folder contains helper classes to make developers life easier when coding for this target board. + +* [Adc](ST_NUCLEO64_F401RE.Adc.cs) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/managed_helpers/ST_NUCLEO64_F401RE.Adc.cs b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/managed_helpers/ST_NUCLEO64_F401RE.Adc.cs new file mode 100644 index 00000000..1ef0c990 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/managed_helpers/ST_NUCLEO64_F401RE.Adc.cs @@ -0,0 +1,58 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +namespace nanoFramework.Targets.ST_NUCLEO64_F401RE +{ + /// + /// Enumeration of ADC channels available on ST_NUCLEO64_F401RE + /// + public static class AdcChannels + { + /// + /// Channel 0, exposed as A0, connected to pin 1 on CN8 = PA0 (ADC1 - IN0) + /// + public const int Channel_0 = 0; + + /// + /// Channel 1, exposed as A1, connected to pin 2 on CN8 = PA1 (ADC1 - IN1) + /// + public const int Channel_1 = 1; + + /// + /// Channel 2, exposed as A2, connected to pin 3 on CN8 = PA4 (ADC1 - IN4) + /// + public const int Channel_2 = 2; + + /// + /// Channel 3, exposed as A3, connected to pin 4 on CN8 = PB0 (ADC1 - IN8) + /// + public const int Channel_3 = 3; + + /// + /// Channel 4, exposed as A4, connected to pin 5 on CN8 = PC1 (ADC1 - IN11) + /// + public const int Channel_4 = 4; + + /// + /// Channel 5, exposed on A5, connected to pin 6 on CN8 = PC0 (ADC1 - IN10) + /// + public const int Channel_5 = 5; + + /// + /// Channel 6, internal temperature sensor, connected to ADC1 + /// + public const int Channel_TemperatureSensor = 6; + + /// + /// Channel 7, internal voltage reference, connected to ADC1 + /// + public const int Channel_VrefIn = 7; + + /// + /// Channel 8, connected to VBatt pin, ADC1 + /// + public const int Channel_Vbatt = 8; + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/CMakeLists.txt new file mode 100644 index 00000000..291f47e1 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/CMakeLists.txt @@ -0,0 +1,9 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# # append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/STM32F401xE_booter-DEBUG.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/STM32F401xE_booter-DEBUG.ld new file mode 100644 index 00000000..d5010ba4 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/STM32F401xE_booter-DEBUG.ld @@ -0,0 +1,80 @@ +/* +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F401xE memory setup. + * + */ +MEMORY +{ + flash : org = 0x08000000, len = 32k /* space reserved for nanoBooter (1st two sectors 0x08000000 to 0x08007FFF)*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 96k /* SRAM1 */ + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Stacks rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/STM32F401xE_booter.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/STM32F401xE_booter.ld new file mode 100644 index 00000000..80074fed --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/STM32F401xE_booter.ld @@ -0,0 +1,80 @@ +/* +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F401xE memory setup. + * + */ +MEMORY +{ + flash : org = 0x08000000, len = 16k /* space reserved for nanoBooter (1st two sectors 0x08000000 to 0x08003FFF)*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 96k /* SRAM1 */ + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Stacks rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/chconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/chconf.h new file mode 100644 index 00000000..335e3fa4 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/chconf.h @@ -0,0 +1,616 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 1000 // this is 1 millisecond + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#define CH_CFG_INTERVALS_SIZE 32 + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_TIME_TYPES_SIZE 32 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES FALSE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS FALSE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT FALSE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES FALSE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_OBJ_FIFOS TRUE + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#define CH_CFG_USE_FACTORY FALSE + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 + +/** + * @brief Enables the registry of generic objects. + */ +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE + +/** + * @brief Enables factory for generic buffers. + */ +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE + +/** + * @brief Enables factory for semaphores. + */ +#define CH_CFG_FACTORY_SEMAPHORES TRUE + +/** + * @brief Enables factory for mailboxes. + */ +#define CH_CFG_FACTORY_MAILBOXES TRUE + +/** + * @brief Enables factory for objects FIFOs. + */ +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/halconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/halconf.h new file mode 100644 index 00000000..bb163e41 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/halconf.h @@ -0,0 +1,513 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/halconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/halconf_nf.h new file mode 100644 index 00000000..e35b7bec --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/halconf_nf.h @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +#if !defined(HAL_USE_STM32_RNG) +#define HAL_USE_STM32_RNG FALSE +#endif + +#endif // _HALCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/main.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/main.c new file mode 100644 index 00000000..78a16f43 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/main.c @@ -0,0 +1,73 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); + +// Application entry point. +int main(void) { + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init SWO as soon as possible to make it available to output ASAP + #if (SWO_OUTPUT == TRUE) + SwoInit(); + #endif + + // the following IF is not mandatory, it's just providing a way for a user to 'force' + // the board to remain in nanoBooter and not launching nanoCLR + + // if the USER button (blue one) is pressed, skip the check for a valid CLR image and remain in booter + if (palReadPad(GPIOC, GPIOC_BUTTON)) + { + // check for valid CLR image + if(CheckValidCLRImage((uint32_t)&__nanoImage_end__)) + { + // there seems to be a valid CLR image + // launch nanoCLR + LaunchCLR((uint32_t)&__nanoImage_end__); + } + } + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // starts the serial driver + sdStart(&SERIAL_DRIVER, NULL); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // Normal main() thread + while (true) { + palSetPad(GPIOA, GPIOA_LED_GREEN); + osDelay(500); + palClearPad(GPIOA, GPIOA_LED_GREEN); + osDelay(500); + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/mcuconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/mcuconf.h new file mode 100644 index 00000000..1566db9f --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/mcuconf.h @@ -0,0 +1,338 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF +#define STM32F401_MCUCONF + +/* + * HAL driver system settings. + */ + +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 4 +#define STM32_PLLQ_VALUE 7 + +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSE +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 250 +#define STM32_SDC_READ_TIMEOUT_MS 25 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/mcuconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/mcuconf_nf.h new file mode 100644 index 00000000..574b9636 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/mcuconf_nf.h @@ -0,0 +1,10 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/target_board.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/target_board.h.in new file mode 100644 index 00000000..19531d9c --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoBooter/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOBOOTER_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/CMakeLists.txt new file mode 100644 index 00000000..e5496b7e --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/STM32F401xE_CLR-DEBUG.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/STM32F401xE_CLR-DEBUG.ld new file mode 100644 index 00000000..2223b481 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/STM32F401xE_CLR-DEBUG.ld @@ -0,0 +1,76 @@ +/* +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F401xE memory setup. + * Note: Only use of ram0. + */ +MEMORY +{ + flash : org = 0x08008000, len = 512k - 32k - 256k /* flash size less the space reserved for nanoBooter and application deployment*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x08040000, len = 256k /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 96k /* SRAM1 */ + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/STM32F401xE_CLR.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/STM32F401xE_CLR.ld new file mode 100644 index 00000000..c93b2d95 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/STM32F401xE_CLR.ld @@ -0,0 +1,76 @@ +/* +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F401xE memory setup. + * Note: Only use of ram0. + */ +MEMORY +{ + flash : org = 0x08004000, len = 512k - 16k - 256k /* flash size less the space reserved for nanoBooter and application deployment*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x08040000, len = 256k /* space reserved for application deployment */ + ramvt : org = 0x20000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 96k /* SRAM1 */ + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/chconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/chconf.h new file mode 100644 index 00000000..3ce5c5aa --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/chconf.h @@ -0,0 +1,621 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 10000 + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#define CH_CFG_INTERVALS_SIZE 32 + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_TIME_TYPES_SIZE 32 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_OBJ_FIFOS TRUE + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#define CH_CFG_USE_FACTORY FALSE + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 + +/** + * @brief Enables the registry of generic objects. + */ +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE + +/** + * @brief Enables factory for generic buffers. + */ +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE + +/** + * @brief Enables factory for semaphores. + */ +#define CH_CFG_FACTORY_SEMAPHORES TRUE + +/** + * @brief Enables factory for mailboxes. + */ +#define CH_CFG_FACTORY_MAILBOXES TRUE + +/** + * @brief Enables factory for objects FIFOs. + */ +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +/////////////////////////////////////////////////////////////////////////////// +// address of vector table for nanoCLR +#define CORTEX_VTOR_INIT 0x08008000U +/////////////////////////////////////////////////////////////////////////////// + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/halconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/halconf.h new file mode 100644 index 00000000..cdf9edad --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/halconf.h @@ -0,0 +1,525 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +// #define HAL_USE_ADC TRUE +// #endif + +/** + * @brief Enables the CAN subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +// #define HAL_USE_CAN FALSE +// #endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +// /** +// * @brief Enables the DAC subsystem. +// */ +// #if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +// #define HAL_USE_DAC FALSE +// #endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +// this option is set at target_platform.h (from config file) +//#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +//#define HAL_USE_I2C TRUE +//#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +// #define HAL_USE_MAC TRUE +// #endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +// #define HAL_USE_PWM TRUE +// #endif + +/** + * @brief Enables the RTC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +// #define HAL_USE_RTC TRUE +// #endif + +/** + * @brief Enables the SDC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +// #define HAL_USE_SDC FALSE +// #endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + + +/** + * @brief Enables the SPI subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +// #define HAL_USE_SPI FALSE +// #endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +// #define HAL_USE_UART FALSE +// #endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +// #define HAL_USE_WDG FALSE +// #endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS TRUE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 64 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/halconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/halconf_nf.h new file mode 100644 index 00000000..c9800ae9 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/halconf_nf.h @@ -0,0 +1,24 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +// Disables the FSMC subsystem. +#if !defined(HAL_USE_FSMC) +#define HAL_USE_FSMC FALSE +#endif + +// STM32F401xx Does not support TRNG +#if !defined(HAL_USE_STM32_RNG) +#define HAL_USE_STM32_RNG FALSE +#endif + +#endif // _HALCONF_NF_H_ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/main.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/main.c new file mode 100644 index 00000000..ca082290 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/main.c @@ -0,0 +1,67 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); +// declare CLRStartup thread here +osThreadDef(CLRStartupThread, osPriorityNormal, 4096, "CLRStartupThread"); + +// Application entry point. +int main(void) { + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init SWO as soon as possible to make it available to output ASAP + #if (SWO_OUTPUT == TRUE) + SwoInit(); + #endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // start watchdog + Watchdog_Init(); + + // starts the serial driver + sdStart(&SERIAL_DRIVER, NULL); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // CLR settings to launch CLR thread + CLR_SETTINGS clrSettings; + (void)memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.EnterDebuggerLoopAfterExit = true; + + // create the CLR Startup thread + osThreadCreate(osThread(CLRStartupThread), &clrSettings); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + while (true) { + osDelay(100); + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/mcuconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/mcuconf.h new file mode 100644 index 00000000..3a2d2f88 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/mcuconf.h @@ -0,0 +1,336 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF +#define STM32F401_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 4 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSE +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 TRUE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 TRUE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 TRUE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 250 +#define STM32_SDC_READ_TIMEOUT_MS 25 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 TRUE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 TRUE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG TRUE + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/mcuconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/mcuconf_nf.h new file mode 100644 index 00000000..574b9636 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/mcuconf_nf.h @@ -0,0 +1,10 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/nanoHAL.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/nanoHAL.cpp new file mode 100644 index 00000000..076a50fc --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/nanoHAL.cpp @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +void HAL_EnterBooterMode() +{ +} + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/target_board.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/target_board.h.in new file mode 100644 index 00000000..b980bc05 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/nanoCLR/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOCLR_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_BlockStorage.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_BlockStorage.c new file mode 100644 index 00000000..9e7c7f55 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_BlockStorage.c @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice STM32Flash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &STM32Flash_BlockStorageInterface, &Device_BlockStorageConfig, false); +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_BlockStorage.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_BlockStorage.h new file mode 100644 index 00000000..aa50b1b7 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_common.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_common.c new file mode 100644 index 00000000..c633da5b --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_common.c @@ -0,0 +1,24 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include "target_common.h" + +HAL_SYSTEM_CONFIG HalSystemConfig = +{ + { true }, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, //ConvertCOM_DebugHandle(1), + 0, //ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + { RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size }, + { FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size } +}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_common.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_common.h.in new file mode 100644 index 00000000..99c1458e --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_common.h.in @@ -0,0 +1,37 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x20000000) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x00018000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x08000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00080000) + +///////////////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////// +#define TARGETNAMESTRING "@CHIBIOS_BOARD@" +#define PLATFORMNAMESTRING "STM32F4" +/////////////////////////////////////////////// + +#endif /* _TARGET_COMMON_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_nf_devices_onewire_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_nf_devices_onewire_config.cpp new file mode 100644 index 00000000..3f13d18c --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_nf_devices_onewire_config.cpp @@ -0,0 +1,30 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_nf_devices_onewire_config.h" +#include + +/////////// +// UART1 // +/////////// + +// pin configuration for UART1 +// port for TX pin is: GPIOA_9 +// port for RX pin is: GPIOB_7 +// GPIO alternate pin function is 7 (see "Table 9. Alternate function mapping" in STM32F401RE datasheet) +UART_CONFIG_PINS(1, GPIOA, 9, 7) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart1_TxBuffer[UART1_TX_SIZE]; + +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart1_RxBuffer[UART1_RX_SIZE]; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_nf_devices_onewire_config.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_nf_devices_onewire_config.h new file mode 100644 index 00000000..1c16444d --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_nf_devices_onewire_config.h @@ -0,0 +1,17 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////// +// UART1 // +/////////// + +// enable USART1 +#define NF_ONEWIRE_STM32_UART_USE_USART1 TRUE + +// buffers size +// tx buffer size: 32 bytes +#define UART1_TX_SIZE 32 +// rx buffer size: 32 bytes +#define UART1_RX_SIZE 32 diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_system_devices_dac_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_system_devices_dac_config.cpp new file mode 100644 index 00000000..88a70347 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_system_devices_dac_config.cpp @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_DAC_PORT_PIN_CHANNEL DacPortPinConfig[] = { + + // DAC1, channel 1, GPIO port A, pin 4 + {1, 1, GPIOA, 4}, + +}; + +const int DacChannelCount = ARRAYSIZE(DacPortPinConfig); diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_windows_devices_adc_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_windows_devices_adc_config.cpp new file mode 100644 index 00000000..0e68d91b --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_windows_devices_adc_config.cpp @@ -0,0 +1,25 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_adc_native_target.h" + + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // ADC1 + {1, GPIOA, 0, ADC_CHANNEL_IN0}, + {1, GPIOA, 1, ADC_CHANNEL_IN1}, + {1, GPIOA, 4, ADC_CHANNEL_IN4}, + {1, GPIOB, 0, ADC_CHANNEL_IN8}, + {1, GPIOC, 1, ADC_CHANNEL_IN11}, + {1, GPIOC, 0, ADC_CHANNEL_IN10}, + + // these are the internal sources, available only at ADC1 + {1, NULL, 0, ADC_CHANNEL_SENSOR}, + {1, NULL, 0, ADC_CHANNEL_VREFINT}, + {1, NULL, 0, ADC_CHANNEL_VBAT}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_windows_devices_i2c_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_windows_devices_i2c_config.cpp new file mode 100644 index 00000000..2a60a22f --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_windows_devices_i2c_config.cpp @@ -0,0 +1,18 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_i2c_native_target.h" + +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for SCL pin is: GPIOB +// port for SDA pin is: GPIOB +// SCL pin: is GPIOB_8 +// SDA pin: is GPIOB_9 +// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, GPIOB, GPIOB, 8, 9, 4) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_windows_devices_serialcommunication_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_windows_devices_serialcommunication_config.cpp new file mode 100644 index 00000000..d117a945 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_windows_devices_serialcommunication_config.cpp @@ -0,0 +1,36 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_windows_devices_serialcommunication_config.h" +#include "win_dev_serial_native_target.h" + +/////////// +// UART6 // +/////////// + +// pin configuration for UART6 +// port: GPIOA +// TX pin: is GPIOA_11 +// RX pin: is GPIOA_12 +// GPIO alternate pin function is 8 (see "Table 9. Alternate function mapping" in STM32F401xC and STM32F401xE datasheet) +UART_CONFIG_PINS(6, GPIOA, GPIOA, 11, 12, 8) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart6_TxBuffer[UART6_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart6_RxBuffer[UART6_RX_SIZE]; + +// initialization for UART6 +UART_INIT(6, UART6_TX_SIZE, UART6_RX_SIZE) + +// un-initialization for UART6 +UART_UNINIT(6) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_windows_devices_serialcommunication_config.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_windows_devices_serialcommunication_config.h new file mode 100644 index 00000000..d554e12c --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_windows_devices_serialcommunication_config.h @@ -0,0 +1,18 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +/////////// +// UART6 // +/////////// + +// enable USART6 +#define NF_SERIAL_COMM_STM32_UART_USE_USART6 TRUE + +// buffers size +// tx buffer size: 256 bytes +#define UART6_TX_SIZE 256 +// rx buffer size: 256 bytes +#define UART6_RX_SIZE 256 diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_windows_devices_spi_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_windows_devices_spi_config.cpp new file mode 100644 index 00000000..ef2d3a10 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF/target_windows_devices_spi_config.cpp @@ -0,0 +1,10 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_spi_native.h" + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/CMakeLists.txt new file mode 100644 index 00000000..6668c291 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/CMakeLists.txt @@ -0,0 +1,202 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +cmake_minimum_required(VERSION 3.0) +ENABLE_LANGUAGE(ASM) + +# add header files with common OS definitions and board definitions specific for each image +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/target_common.h" @ONLY) + +set(NANOBOOTER_PROJECT_NAME "nanoBooter") +set(NANOCLR_PROJECT_NAME "nanoCLR") + +find_package(BuildUtils REQUIRED) +find_package(CHIBIOS REQUIRED) +find_package(ChibiOSnfOverlay REQUIRED) +find_package(WireProtocol REQUIRED) + +# packages for nanoFramework libraries +####################################### +# mandatory +find_package(NF_CoreCLR REQUIRED) + +####################################### +# optional + +# ChibiOS contrib repo +if(CHIBIOS_CONTRIB_REQUIRED) + find_package(ChibiOS-Contrib REQUIRED) +endif() + +# nF feature: debugger +if(NF_FEATURE_DEBUGGER) + find_package(NF_Debugger REQUIRED) + find_package(NF_Diagnostics REQUIRED) +endif() + +# nF feature: networking +if(USE_NETWORKING_OPTION) + find_package(CHIBIOS_LWIP REQUIRED) +endif() + +# nF feature: filesystem +if(USE_FILESYSTEM_OPTION) + find_package(CHIBIOS_FATFS REQUIRED) +endif() + +####################################### + +add_subdirectory("common") +add_subdirectory("nanoBooter") +add_subdirectory("nanoCLR") + +####################### +# nanoBooter executable + +add_executable( + # executables for project, project sources + ${NANOBOOTER_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + "${CMAKE_CURRENT_SOURCE_DIR}/target_BlockStorage.c" + + # need to add configuration manager to allow get/store configuration blocks + "${PROJECT_SOURCE_DIR}/src/HAL/nanoHAL_ConfigurationManager_stubs.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOBOOTER_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOBOOTER_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOBOOTER_SOURCES} + + ${CHIBIOS_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} +) + +####################### +# nanoCLR executable + +add_executable( + # executables for project, project sources + ${NANOCLR_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOCLR_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOCLR_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOCLR_SOURCES} + + ${CHIBIOS_SOURCES} + ${CHIBIOS_CONTRIB_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} + + # sources for nanoFramework libraries + ${NF_CoreCLR_SOURCES} + ${NF_Debugger_SOURCES} + ${NF_Diagnostics_SOURCES} + + # sources for nanoFramework APIs + ${TARGET_NANO_APIS_SOURCES} +) + +# add dependency from ChibiOS (this is required to make sure the ChibiOS repo is downloaded before the build starts) +add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf ChibiOS) +add_dependencies(${NANOCLR_PROJECT_NAME}.elf ChibiOS) + +# include common directories +include_directories( + ${CMAKE_CURRENT_BINARY_DIR} + ${CMAKE_CURRENT_SOURCE_DIR} + ${CMAKE_CURRENT_SOURCE_DIR}/common + ${PROJECT_SOURCE_DIR}/src/CLR/Core + ${PROJECT_SOURCE_DIR}/src/CLR/Include + ${PROJECT_SOURCE_DIR}/src/HAL/Include + ${PROJECT_SOURCE_DIR}/src/PAL/Include + + ${WireProtocol_INCLUDE_DIRS} + ${CHIBIOS_INCLUDE_DIRS} + ${ChibiOSnfOverlay_INCLUDE_DIRS} + ${CHIBIOS_CONTRIB_INCLUDE_DIRS} + + ${TARGET_CMSIS_COMMON_INCLUDE_DIRS} + ${TARGET_CHIBIOS_COMMON_INCLUDE_DIRS} +) + +# include directories for nanoBooter +target_include_directories(${NANOBOOTER_PROJECT_NAME}.elf PUBLIC + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter" + ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter + + ${TARGET_CMSIS_NANOBOOTER_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOBOOTER_INCLUDE_DIRS} +) + +# include directories for nanoCLR +target_include_directories(${NANOCLR_PROJECT_NAME}.elf PUBLIC + ${CMAKE_CURRENT_BINARY_DIR}/nanoCLR + ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR + + ${TARGET_CMSIS_NANOCLR_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOCLR_INCLUDE_DIRS} + + # directories for nanoFramework libraries + ${NF_CoreCLR_INCLUDE_DIRS} + ${NF_Debugger_INCLUDE_DIRS} + ${NF_Diagnostics_INCLUDE_DIRS} + + # includes for nanoFramework APIs + ${TARGET_NANO_APIS_INCLUDES} + + # includes for ChibiOS LwIP + ${CHIBIOS_LWIP_INCLUDE_DIRS} +) + +# set compiler options +nf_set_compiler_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_options(${NANOCLR_PROJECT_NAME}.elf) + +# set compiler definitions +nf_set_compiler_definitions(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_definitions(${NANOCLR_PROJECT_NAME}.elf) + +# set linker files +if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F411xE_booter-DEBUG.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/STM32F411xE_CLR-DEBUG.ld) +else() + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F411xE_booter.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/STM32F411xE_CLR.ld) +endif() + +# set linker options +nf_set_linker_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_linker_options(${NANOCLR_PROJECT_NAME}.elf) + +# add other linker flags +########################################################### +# the sizes of CRT heap and ChibiOS stacks are defined here +set_property(TARGET ${NANOBOOTER_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x400,--defsym=__crt_heap_size__=0x1000") +set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x2800") + +# generate output files +nf_generate_build_output_files(${NANOBOOTER_PROJECT_NAME}.elf) +nf_generate_build_output_files(${NANOCLR_PROJECT_NAME}.elf) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/README.md b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/README.md new file mode 100644 index 00000000..cf99709d --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/README.md @@ -0,0 +1,45 @@ +## ST of the shelve board ## + +The board used in this community contribution is the NUCLEO64_F411RE board from ST. The board can be purchased from various sources and should be about 20 euros. Further information on the Nucleo64 boards can be found in the user manual UM1724 on the ST side (www.st.com). The board used here is of revision c as can be found on the board's lower backside sticker. The board MB1136 C-02 is configured to use ST-LINK MCO as clock input for HSE so we have an HSE of 8 MHz. Plus X2 is mounted we do have an LSE as well. This is reflected in the mcuconf.h in both nanoBooter and nanoCLR paths. If it is chosen to activate LSE as this is a for more accurate clock for RTC the board.h file needs to be adjusted accordingly to use 32768 frequency for LSE. + +I prepared a custom made a 4-wire jumper to USB cable by cutting off one end (Type A part) and figuring out the required D+, D-, 5V and GND. These need to be connected as follows: + +USB V5 -> Can be ignored +USB GND -> GND on CN7 +USB D- -> PA11 on CN10 (outer row 7th pin from top) +USB D+ -> PA12 on CN10 (outer row 6th pin from top) + +Once these are connected and nanoFramework is flashed using the STM32 ST-LINK Utility the device should be visible in the Printf via SWO viewer function in the ST-LINK utility. Please set the frequency to match to what has been set in mcuconf.h (mostly 96000000) and the Stimulus port to 0 and than hit start. If the board doesn't show then a reset (Black button on board) should do it. + +We can now fire up Visual Studio and view the Device explorer window the board should be visible there as well. Select the board (if not done already) and hit the device capabilities button. The board specifics can than be seen in the output window. + +Now you can start your adventure in the nanoFramework world and use one of the samples and adjust to the board specific features. Try to make a sample of yourself and publish it on f.e. www.hackster.io to show your achievement. + +For your convenience I've listed below the features and on what pins they can be found to help you out for an easy start. + +Arduino header pins: +==================== +D0 = COM2 RX +D1 = COM2 TX + +D2 - D9 can be used for an intermix of GPIO and PWM + +D14 = I2C1 SDA +D15 = I2C1 SCL + + +Connector CN7: +============== +1 = SPI3 SCK +2 = SPI3 MISO +3 = SPI3 MOSI + + +Connector CN10: +=============== +26 = SPI2 MOSI +28 = SPI2 MISO +30 = SPI2 SCK + + +**NOTE: This configuration was successfully tested on a NUCLEO64_F411RE board.** diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/board.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/board.c new file mode 100644 index 00000000..aece76d4 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/board.c @@ -0,0 +1,266 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) + gpio_setup_t PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_setup_t PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) + gpio_setup_t PKData; +#endif +} gpio_config_t; + +/** + * @brief STM32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +#endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB1(STM32_GPIO_EN_MASK); + rccEnableAHB1(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG + gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI + gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ + gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK + gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + * else. + */ +void __early_init(void) { + + stm32_gpio_init(); + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { + +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/board.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/board.h new file mode 100644 index 00000000..4f85a0e5 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/board.h @@ -0,0 +1,1375 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#ifndef BOARD_H +#define BOARD_H + +/* + * Setup for STMicroelectronics STM32 Nucleo64-F411RE board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_NUCLEO64_F411RE_NF +#define BOARD_NAME "STMicroelectronics STM32 Nucleo64-F411RE for nanoFramework" + +/* + * USB OTG Force + */ +#define BOARD_OTG_NOVBUSSENS + +/* + * Completely wacko definition of a flash sector here + */ +#define FLASH_SECTOR_11 ((uint32_t)11U) + +/* + * Board oscillators-related settings. + * NOTE: LSE not fitted. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768U +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 8000000U +#endif + +//#define STM32_HSE_BYPASS + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U + +/* + * MCU type as defined in the ST header. + */ +#define STM32F411xE + +/* + * IO pins assignments. + */ +#define GPIOA_ARD_A0 0U +#define GPIOA_ADC1_IN0 0U +#define GPIOA_ARD_A1 1U +#define GPIOA_ADC1_IN1 1U +#define GPIOA_ARD_D1 2U +#define GPIOA_USART2_TX 2U +#define GPIOA_ARD_D0 3U +#define GPIOA_USART2_RX 3U +#define GPIOA_ARD_A2 4U +#define GPIOA_ADC1_IN4 4U +#define GPIOA_LED_GREEN 5U +#define GPIOA_ARD_D13 5U +#define GPIOA_ARD_D12 6U +#define GPIOA_ARD_D11 7U +#define GPIOA_ARD_D7 8U +#define GPIOA_ARD_D8 9U +#define GPIOA_ARD_D2 10U +#define GPIOA_OTG_FS_DM 11U +#define GPIOA_OTG_FS_DP 12U +#define GPIOA_SWDIO 13U +#define GPIOA_SWCLK 14U +#define GPIOA_PIN15 15U + +#define GPIOB_ARD_A3 0U +#define GPIOB_ADC1_IN8 0U +#define GPIOB_PIN1 1U +#define GPIOB_PIN2 2U +#define GPIOB_SWO 3U +#define GPIOB_ARD_D3 3U +#define GPIOB_ARD_D5 4U +#define GPIOB_ARD_D4 5U +#define GPIOB_ARD_D10 6U +#define GPIOB_PIN7 7U +#define GPIOB_ARD_D15 8U +#define GPIOB_ARD_D14 9U +#define GPIOB_ARD_D6 10U +#define GPIOB_PIN11 11U +#define GPIOB_PIN12 12U +#define GPIOB_SPI2_SCK 13U +#define GPIOB_SPI2_MISO 14U +#define GPIOB_SPI2_MOSI 15U + +#define GPIOC_ARD_A5 0U +#define GPIOC_ADC1_IN10 0U +#define GPIOC_ARD_A4 1U +#define GPIOC_ADC1_IN11 1U +#define GPIOC_PIN2 2U +#define GPIOC_PIN3 3U +#define GPIOC_PIN4 4U +#define GPIOC_PIN5 5U +#define GPIOC_PIN6 6U +#define GPIOC_ARD_D9 7U +#define GPIOC_PIN8 8U +#define GPIOC_PIN9 9U +#define GPIOC_SPI3_SCK 10U +#define GPIOC_SPI3_MISO 11U +#define GPIOC_SPI3_MOSI 12U +#define GPIOC_BUTTON 13U +#define GPIOC_OSC32_IN 14U +#define GPIOC_OSC32_OUT 15U + +#define GPIOD_PIN0 0U +#define GPIOD_PIN1 1U +#define GPIOD_PIN2 2U +#define GPIOD_PIN3 3U +#define GPIOD_PIN4 4U +#define GPIOD_PIN5 5U +#define GPIOD_PIN6 6U +#define GPIOD_PIN7 7U +#define GPIOD_PIN8 8U +#define GPIOD_PIN9 9U +#define GPIOD_PIN10 10U +#define GPIOD_PIN11 11U +#define GPIOD_PIN12 12U +#define GPIOD_PIN13 13U +#define GPIOD_PIN14 14U +#define GPIOD_PIN15 15U + +#define GPIOE_PIN0 0U +#define GPIOE_PIN1 1U +#define GPIOE_PIN2 2U +#define GPIOE_PIN3 3U +#define GPIOE_PIN4 4U +#define GPIOE_PIN5 5U +#define GPIOE_PIN6 6U +#define GPIOE_PIN7 7U +#define GPIOE_PIN8 8U +#define GPIOE_PIN9 9U +#define GPIOE_PIN10 10U +#define GPIOE_PIN11 11U +#define GPIOE_PIN12 12U +#define GPIOE_PIN13 13U +#define GPIOE_PIN14 14U +#define GPIOE_PIN15 15U + +#define GPIOF_PIN0 0U +#define GPIOF_PIN1 1U +#define GPIOF_PIN2 2U +#define GPIOF_PIN3 3U +#define GPIOF_PIN4 4U +#define GPIOF_PIN5 5U +#define GPIOF_PIN6 6U +#define GPIOF_PIN7 7U +#define GPIOF_PIN8 8U +#define GPIOF_PIN9 9U +#define GPIOF_PIN10 10U +#define GPIOF_PIN11 11U +#define GPIOF_PIN12 12U +#define GPIOF_PIN13 13U +#define GPIOF_PIN14 14U +#define GPIOF_PIN15 15U + +#define GPIOG_PIN0 0U +#define GPIOG_PIN1 1U +#define GPIOG_PIN2 2U +#define GPIOG_PIN3 3U +#define GPIOG_PIN4 4U +#define GPIOG_PIN5 5U +#define GPIOG_PIN6 6U +#define GPIOG_PIN7 7U +#define GPIOG_PIN8 8U +#define GPIOG_PIN9 9U +#define GPIOG_PIN10 10U +#define GPIOG_PIN11 11U +#define GPIOG_PIN12 12U +#define GPIOG_PIN13 13U +#define GPIOG_PIN14 14U +#define GPIOG_PIN15 15U + +#define GPIOH_OSC_IN 0U +#define GPIOH_OSC_OUT 1U +#define GPIOH_PIN2 2U +#define GPIOH_PIN3 3U +#define GPIOH_PIN4 4U +#define GPIOH_PIN5 5U +#define GPIOH_PIN6 6U +#define GPIOH_PIN7 7U +#define GPIOH_PIN8 8U +#define GPIOH_PIN9 9U +#define GPIOH_PIN10 10U +#define GPIOH_PIN11 11U +#define GPIOH_PIN12 12U +#define GPIOH_PIN13 13U +#define GPIOH_PIN14 14U +#define GPIOH_PIN15 15U + +#define GPIOI_PIN0 0U +#define GPIOI_PIN1 1U +#define GPIOI_PIN2 2U +#define GPIOI_PIN3 3U +#define GPIOI_PIN4 4U +#define GPIOI_PIN5 5U +#define GPIOI_PIN6 6U +#define GPIOI_PIN7 7U +#define GPIOI_PIN8 8U +#define GPIOI_PIN9 9U +#define GPIOI_PIN10 10U +#define GPIOI_PIN11 11U +#define GPIOI_PIN12 12U +#define GPIOI_PIN13 13U +#define GPIOI_PIN14 14U +#define GPIOI_PIN15 15U + +/* + * IO lines assignments. + */ +#define LINE_ARD_A0 PAL_LINE(GPIOA, 0U) +#define LINE_ADC1_IN0 PAL_LINE(GPIOA, 0U) +#define LINE_ARD_A1 PAL_LINE(GPIOA, 1U) +#define LINE_ADC1_IN1 PAL_LINE(GPIOA, 1U) +#define LINE_ARD_D1 PAL_LINE(GPIOA, 2U) +#define LINE_USART2_TX PAL_LINE(GPIOA, 2U) +#define LINE_ARD_D0 PAL_LINE(GPIOA, 3U) +#define LINE_USART2_RX PAL_LINE(GPIOA, 3U) +#define LINE_ARD_A2 PAL_LINE(GPIOA, 4U) +#define LINE_ADC1_IN4 PAL_LINE(GPIOA, 4U) +#define LINE_LED_GREEN PAL_LINE(GPIOA, 5U) +#define LINE_ARD_D13 PAL_LINE(GPIOA, 5U) +#define LINE_ARD_D12 PAL_LINE(GPIOA, 6U) +#define LINE_ARD_D11 PAL_LINE(GPIOA, 7U) +#define LINE_ARD_D7 PAL_LINE(GPIOA, 8U) +#define LINE_ARD_D8 PAL_LINE(GPIOA, 9U) +#define LINE_ARD_D2 PAL_LINE(GPIOA, 10U) +#define LINE_OTG_FS_DM PAL_LINE(GPIOA, 11U) +#define LINE_OTG_FS_DP PAL_LINE(GPIOA, 12U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) + +#define LINE_ARD_A3 PAL_LINE(GPIOB, 0U) +#define LINE_ADC1_IN8 PAL_LINE(GPIOB, 0U) +#define LINE_SWO PAL_LINE(GPIOB, 3U) +#define LINE_ARD_D3 PAL_LINE(GPIOB, 3U) +#define LINE_ARD_D5 PAL_LINE(GPIOB, 4U) +#define LINE_ARD_D4 PAL_LINE(GPIOB, 5U) +#define LINE_ARD_D10 PAL_LINE(GPIOB, 6U) +#define LINE_ARD_D15 PAL_LINE(GPIOB, 8U) +#define LINE_ARD_D14 PAL_LINE(GPIOB, 9U) +#define LINE_ARD_D6 PAL_LINE(GPIOB, 10U) + +#define LINE_ARD_A5 PAL_LINE(GPIOC, 0U) +#define LINE_ADC1_IN10 PAL_LINE(GPIOC, 0U) +#define LINE_ARD_A4 PAL_LINE(GPIOC, 1U) +#define LINE_ADC1_IN11 PAL_LINE(GPIOC, 1U) +#define LINE_ARD_D9 PAL_LINE(GPIOC, 7U) +#define LINE_BUTTON PAL_LINE(GPIOC, 13U) +#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) +#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) + + + + + +#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) +#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) + + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * GPIOA setup: + * + * PA0 - ARD_A0 ADC1_IN0 (input pullup). + * PA1 - ARD_A1 ADC1_IN1 (input pullup). + * PA2 - ARD_D1 USART2_TX (alternate 7). + * PA3 - ARD_D0 USART2_RX (alternate 7). + * PA4 - ARD_A2 ADC1_IN4 (input pullup). + * PA5 - LED_GREEN ARD_D13 (output pushpull high). + * PA6 - ARD_D12 (input pullup). + * PA7 - ARD_D11 (input pullup). + * PA8 - ARD_D7 (input pullup). + * PA9 - ARD_D8 (input pullup). + * PA10 - ARD_D2 (input pullup). + * PA11 - OTG_FS_DM (alternate 10). + * PA12 - OTG_FS_DP (alternate 10). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - PIN15 (input pullup). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_ARD_A0) | \ + PIN_MODE_INPUT(GPIOA_ARD_A1) | \ + PIN_MODE_ALTERNATE(GPIOA_ARD_D1) | \ + PIN_MODE_ALTERNATE(GPIOA_ARD_D0) | \ + PIN_MODE_INPUT(GPIOA_ARD_A2) | \ + PIN_MODE_OUTPUT(GPIOA_LED_GREEN) | \ + PIN_MODE_INPUT(GPIOA_ARD_D12) | \ + PIN_MODE_INPUT(GPIOA_ARD_D11) | \ + PIN_MODE_INPUT(GPIOA_ARD_D7) | \ + PIN_MODE_INPUT(GPIOA_ARD_D8) | \ + PIN_MODE_INPUT(GPIOA_ARD_D2) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_INPUT(GPIOA_PIN15)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_A1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_A2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_LED_GREEN) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D12) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D11) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D8) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN15)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_A1) | \ + PIN_OSPEED_MEDIUM(GPIOA_ARD_D1) | \ + PIN_OSPEED_MEDIUM(GPIOA_ARD_D0) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_A2) | \ + PIN_OSPEED_MEDIUM(GPIOA_LED_GREEN) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D12) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D11) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D7) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D8) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D2) | \ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ + PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ + PIN_OSPEED_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_ARD_A0) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_A1) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D1) | \ + PIN_PUPDR_FLOATING(GPIOA_ARD_D0) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_A2) | \ + PIN_PUPDR_FLOATING(GPIOA_LED_GREEN) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D12) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D11) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D7) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D8) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D2) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \ + PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \ + PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN15)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_ARD_A0) | \ + PIN_ODR_HIGH(GPIOA_ARD_A1) | \ + PIN_ODR_HIGH(GPIOA_ARD_D1) | \ + PIN_ODR_HIGH(GPIOA_ARD_D0) | \ + PIN_ODR_HIGH(GPIOA_ARD_A2) | \ + PIN_ODR_LOW(GPIOA_LED_GREEN) | \ + PIN_ODR_HIGH(GPIOA_ARD_D12) | \ + PIN_ODR_HIGH(GPIOA_ARD_D11) | \ + PIN_ODR_HIGH(GPIOA_ARD_D7) | \ + PIN_ODR_HIGH(GPIOA_ARD_D8) | \ + PIN_ODR_HIGH(GPIOA_ARD_D2) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_PIN15)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_A1, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D1, 7U) | \ + PIN_AFIO_AF(GPIOA_ARD_D0, 7U) | \ + PIN_AFIO_AF(GPIOA_ARD_A2, 0U) | \ + PIN_AFIO_AF(GPIOA_LED_GREEN, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D12, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D11, 0U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_ARD_D7, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D8, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D2, 0U) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10U) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10U) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ + PIN_AFIO_AF(GPIOA_PIN15, 0U)) + +/* + * GPIOB setup: + * + * PB0 - ARD_A3 ADC1_IN8 (input pullup). + * PB1 - PIN1 (input pullup). + * PB2 - PIN2 (input pullup). + * PB3 - SWO ARD_D3 (alternate 0). + * PB4 - ARD_D5 (input pullup). + * PB5 - ARD_D4 (input pullup). + * PB6 - ARD_D10 (input pullup). + * PB7 - PIN7 (input pullup). + * PB8 - ARD_D15 (alternate 4). + * PB9 - ARD_D14 (alternate 4). + * PB10 - ARD_D6 (input pullup). + * PB11 - PIN11 (input pullup). + * PB12 - PIN12 (input pullup). + * PB13 - SPI2_SCK (alternate 5). + * PB14 - SPI2_MISO (alternate 5). + * PB15 - SPI2_MOSI (alternate 5). + */ +#define VAL_GPIOB_MODER (PIN_MODE_ANALOG(GPIOB_ARD_A3) | \ + PIN_MODE_INPUT(GPIOB_PIN1) | \ + PIN_MODE_INPUT(GPIOB_PIN2) | \ + PIN_MODE_ALTERNATE(GPIOB_SWO) | \ + PIN_MODE_INPUT(GPIOB_ARD_D5) | \ + PIN_MODE_INPUT(GPIOB_ARD_D4) | \ + PIN_MODE_INPUT(GPIOB_ARD_D10) | \ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_ALTERNATE(GPIOB_ARD_D15) | \ + PIN_MODE_ALTERNATE(GPIOB_ARD_D14) | \ + PIN_MODE_INPUT(GPIOB_ARD_D6) | \ + PIN_MODE_INPUT(GPIOB_PIN11) | \ + PIN_MODE_INPUT(GPIOB_PIN12) | \ + PIN_MODE_ALTERNATE(GPIOB_SPI2_SCK) | \ + PIN_MODE_ALTERNATE(GPIOB_SPI2_MISO) | \ + PIN_MODE_ALTERNATE(GPIOB_SPI2_MOSI)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ARD_A3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D10) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_ARD_D15) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_ARD_D14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SPI2_SCK) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SPI2_MISO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SPI2_MOSI)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ARD_A3) | \ + PIN_OSPEED_HIGH(GPIOB_PIN1) | \ + PIN_OSPEED_HIGH(GPIOB_PIN2) | \ + PIN_OSPEED_HIGH(GPIOB_SWO) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D5) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D4) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D10) | \ + PIN_OSPEED_HIGH(GPIOB_PIN7) | \ + PIN_OSPEED_MEDIUM(GPIOB_ARD_D15) | \ + PIN_OSPEED_MEDIUM(GPIOB_ARD_D14) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D6) | \ + PIN_OSPEED_HIGH(GPIOB_PIN11) | \ + PIN_OSPEED_HIGH(GPIOB_PIN12) | \ + PIN_OSPEED_HIGH(GPIOB_SPI2_SCK) | \ + PIN_OSPEED_HIGH(GPIOB_SPI2_MISO) | \ + PIN_OSPEED_HIGH(GPIOB_SPI2_MOSI)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_ARD_A3) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOB_SWO) | \ + PIN_PUPDR_PULLUP(GPIOB_ARD_D5) | \ + PIN_PUPDR_PULLUP(GPIOB_ARD_D4) | \ + PIN_PUPDR_PULLUP(GPIOB_ARD_D10) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D15) | \ + PIN_PUPDR_FLOATING(GPIOB_ARD_D14) | \ + PIN_PUPDR_PULLUP(GPIOB_ARD_D6) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOB_SPI2_SCK) | \ + PIN_PUPDR_FLOATING(GPIOB_SPI2_MISO) | \ + PIN_PUPDR_FLOATING(GPIOB_SPI2_MOSI)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_ARD_A3) | \ + PIN_ODR_HIGH(GPIOB_PIN1) | \ + PIN_ODR_HIGH(GPIOB_PIN2) | \ + PIN_ODR_HIGH(GPIOB_SWO) | \ + PIN_ODR_HIGH(GPIOB_ARD_D5) | \ + PIN_ODR_HIGH(GPIOB_ARD_D4) | \ + PIN_ODR_HIGH(GPIOB_ARD_D10) | \ + PIN_ODR_HIGH(GPIOB_PIN7) | \ + PIN_ODR_HIGH(GPIOB_ARD_D15) | \ + PIN_ODR_HIGH(GPIOB_ARD_D14) | \ + PIN_ODR_HIGH(GPIOB_ARD_D6) | \ + PIN_ODR_HIGH(GPIOB_PIN11) | \ + PIN_ODR_HIGH(GPIOB_PIN12) | \ + PIN_ODR_LOW(GPIOB_SPI2_SCK) | \ + PIN_ODR_LOW(GPIOB_SPI2_MISO) | \ + PIN_ODR_LOW(GPIOB_SPI2_MOSI)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ARD_A3, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOB_SWO, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D5, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D4, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D10, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN7, 0U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_ARD_D15, 4U) | \ + PIN_AFIO_AF(GPIOB_ARD_D14, 4U) | \ + PIN_AFIO_AF(GPIOB_ARD_D6, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOB_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOB_SPI2_SCK, 5U) | \ + PIN_AFIO_AF(GPIOB_SPI2_MISO, 5U) | \ + PIN_AFIO_AF(GPIOB_SPI2_MOSI, 5U)) + +/* + * GPIOC setup: + * + * PC0 - ARD_A5 ADC1_IN10 (input pullup). + * PC1 - ARD_A4 ADC1_IN11 (input pullup). + * PC2 - PIN2 (input pullup). + * PC3 - PIN3 (input pullup). + * PC4 - PIN4 (input pullup). + * PC5 - PIN5 (input pullup). + * PC6 - PIN6 (input pullup). + * PC7 - ARD_D9 (input pullup). + * PC8 - PIN8 (input pullup). + * PC9 - PIN9 (input pullup). + * PC10 - SPI3_SCK (alternate 5). + * PC11 - SPI3_MISO (alternate 5). + * PC12 - SPI3_MOSI (alternate 5). + * PC13 - BUTTON (input floating). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_ARD_A5) | \ + PIN_MODE_ANALOG(GPIOC_ARD_A4) | \ + PIN_MODE_INPUT(GPIOC_PIN2) | \ + PIN_MODE_INPUT(GPIOC_PIN3) | \ + PIN_MODE_INPUT(GPIOC_PIN4) | \ + PIN_MODE_INPUT(GPIOC_PIN5) | \ + PIN_MODE_INPUT(GPIOC_PIN6) | \ + PIN_MODE_INPUT(GPIOC_ARD_D9) | \ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_INPUT(GPIOC_PIN9) | \ + PIN_MODE_ALTERNATE(GPIOC_SPI3_SCK) | \ + PIN_MODE_ALTERNATE(GPIOC_SPI3_MISO) | \ + PIN_MODE_ALTERNATE(GPIOC_SPI3_MOSI) | \ + PIN_MODE_INPUT(GPIOC_BUTTON) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ARD_A5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_A4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_D9) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SPI3_SCK) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SPI3_MISO) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SPI3_MOSI) | \ + PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ARD_A5) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_A4) | \ + PIN_OSPEED_HIGH(GPIOC_PIN2) | \ + PIN_OSPEED_HIGH(GPIOC_PIN3) | \ + PIN_OSPEED_HIGH(GPIOC_PIN4) | \ + PIN_OSPEED_HIGH(GPIOC_PIN5) | \ + PIN_OSPEED_HIGH(GPIOC_PIN6) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_D9) | \ + PIN_OSPEED_HIGH(GPIOC_PIN8) | \ + PIN_OSPEED_HIGH(GPIOC_PIN9) | \ + PIN_OSPEED_HIGH(GPIOC_SPI3_SCK) | \ + PIN_OSPEED_HIGH(GPIOC_SPI3_MISO) | \ + PIN_OSPEED_HIGH(GPIOC_SPI3_MOSI) | \ + PIN_OSPEED_HIGH(GPIOC_BUTTON) | \ + PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \ + PIN_OSPEED_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_ARD_A5) | \ + PIN_PUPDR_PULLUP(GPIOC_ARD_A4) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOC_ARD_D9) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOC_SPI3_SCK) | \ + PIN_PUPDR_FLOATING(GPIOC_SPI3_MISO) | \ + PIN_PUPDR_FLOATING(GPIOC_SPI3_MOSI) | \ + PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_ARD_A5) | \ + PIN_ODR_HIGH(GPIOC_ARD_A4) | \ + PIN_ODR_HIGH(GPIOC_PIN2) | \ + PIN_ODR_HIGH(GPIOC_PIN3) | \ + PIN_ODR_HIGH(GPIOC_PIN4) | \ + PIN_ODR_HIGH(GPIOC_PIN5) | \ + PIN_ODR_HIGH(GPIOC_PIN6) | \ + PIN_ODR_HIGH(GPIOC_ARD_D9) | \ + PIN_ODR_HIGH(GPIOC_PIN8) | \ + PIN_ODR_HIGH(GPIOC_PIN9) | \ + PIN_ODR_LOW(GPIOC_SPI3_SCK) | \ + PIN_ODR_LOW(GPIOC_SPI3_MISO) | \ + PIN_ODR_LOW(GPIOC_SPI3_MOSI) | \ + PIN_ODR_HIGH(GPIOC_BUTTON) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ARD_A5, 0U) | \ + PIN_AFIO_AF(GPIOC_ARD_A4, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOC_ARD_D9, 0U)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOC_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOC_SPI3_SCK, 5U) | \ + PIN_AFIO_AF(GPIOC_SPI3_MISO, 5U) | \ + PIN_AFIO_AF(GPIOC_SPI3_MOSI, 5U) | \ + PIN_AFIO_AF(GPIOC_BUTTON, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) + +/* + * GPIOD setup: + * + * PD0 - PIN0 (input pullup). + * PD1 - PIN1 (input pullup). + * PD2 - PIN2 (input pullup). + * PD3 - PIN3 (input pullup). + * PD4 - PIN4 (input pullup). + * PD5 - PIN5 (input pullup). + * PD6 - PIN6 (input pullup). + * PD7 - PIN7 (input pullup). + * PD8 - PIN8 (input pullup). + * PD9 - PIN9 (input pullup). + * PD10 - PIN10 (input pullup). + * PD11 - PIN11 (input pullup). + * PD12 - PIN12 (input pullup). + * PD13 - PIN13 (input pullup). + * PD14 - PIN14 (input pullup). + * PD15 - PIN15 (input pullup). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ + PIN_MODE_INPUT(GPIOD_PIN1) | \ + PIN_MODE_INPUT(GPIOD_PIN2) | \ + PIN_MODE_INPUT(GPIOD_PIN3) | \ + PIN_MODE_INPUT(GPIOD_PIN4) | \ + PIN_MODE_INPUT(GPIOD_PIN5) | \ + PIN_MODE_INPUT(GPIOD_PIN6) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_INPUT(GPIOD_PIN8) | \ + PIN_MODE_INPUT(GPIOD_PIN9) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_PIN11) | \ + PIN_MODE_INPUT(GPIOD_PIN12) | \ + PIN_MODE_INPUT(GPIOD_PIN13) | \ + PIN_MODE_INPUT(GPIOD_PIN14) | \ + PIN_MODE_INPUT(GPIOD_PIN15)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_PIN0) | \ + PIN_OSPEED_HIGH(GPIOD_PIN1) | \ + PIN_OSPEED_HIGH(GPIOD_PIN2) | \ + PIN_OSPEED_HIGH(GPIOD_PIN3) | \ + PIN_OSPEED_HIGH(GPIOD_PIN4) | \ + PIN_OSPEED_HIGH(GPIOD_PIN5) | \ + PIN_OSPEED_HIGH(GPIOD_PIN6) | \ + PIN_OSPEED_HIGH(GPIOD_PIN7) | \ + PIN_OSPEED_HIGH(GPIOD_PIN8) | \ + PIN_OSPEED_HIGH(GPIOD_PIN9) | \ + PIN_OSPEED_HIGH(GPIOD_PIN10) | \ + PIN_OSPEED_HIGH(GPIOD_PIN11) | \ + PIN_OSPEED_HIGH(GPIOD_PIN12) | \ + PIN_OSPEED_HIGH(GPIOD_PIN13) | \ + PIN_OSPEED_HIGH(GPIOD_PIN14) | \ + PIN_OSPEED_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN15)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ + PIN_ODR_HIGH(GPIOD_PIN1) | \ + PIN_ODR_HIGH(GPIOD_PIN2) | \ + PIN_ODR_HIGH(GPIOD_PIN3) | \ + PIN_ODR_HIGH(GPIOD_PIN4) | \ + PIN_ODR_HIGH(GPIOD_PIN5) | \ + PIN_ODR_HIGH(GPIOD_PIN6) | \ + PIN_ODR_HIGH(GPIOD_PIN7) | \ + PIN_ODR_HIGH(GPIOD_PIN8) | \ + PIN_ODR_HIGH(GPIOD_PIN9) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_PIN11) | \ + PIN_ODR_HIGH(GPIOD_PIN12) | \ + PIN_ODR_HIGH(GPIOD_PIN13) | \ + PIN_ODR_HIGH(GPIOD_PIN14) | \ + PIN_ODR_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOD_PIN15, 0U)) + +/* + * GPIOE setup: + * + * PE0 - PIN0 (input pullup). + * PE1 - PIN1 (input pullup). + * PE2 - PIN2 (input pullup). + * PE3 - PIN3 (input pullup). + * PE4 - PIN4 (input pullup). + * PE5 - PIN5 (input pullup). + * PE6 - PIN6 (input pullup). + * PE7 - PIN7 (input pullup). + * PE8 - PIN8 (input pullup). + * PE9 - PIN9 (input pullup). + * PE10 - PIN10 (input pullup). + * PE11 - PIN11 (input pullup). + * PE12 - PIN12 (input pullup). + * PE13 - PIN13 (input pullup). + * PE14 - PIN14 (input pullup). + * PE15 - PIN15 (input pullup). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ + PIN_MODE_INPUT(GPIOE_PIN1) | \ + PIN_MODE_INPUT(GPIOE_PIN2) | \ + PIN_MODE_INPUT(GPIOE_PIN3) | \ + PIN_MODE_INPUT(GPIOE_PIN4) | \ + PIN_MODE_INPUT(GPIOE_PIN5) | \ + PIN_MODE_INPUT(GPIOE_PIN6) | \ + PIN_MODE_INPUT(GPIOE_PIN7) | \ + PIN_MODE_INPUT(GPIOE_PIN8) | \ + PIN_MODE_INPUT(GPIOE_PIN9) | \ + PIN_MODE_INPUT(GPIOE_PIN10) | \ + PIN_MODE_INPUT(GPIOE_PIN11) | \ + PIN_MODE_INPUT(GPIOE_PIN12) | \ + PIN_MODE_INPUT(GPIOE_PIN13) | \ + PIN_MODE_INPUT(GPIOE_PIN14) | \ + PIN_MODE_INPUT(GPIOE_PIN15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_PIN0) | \ + PIN_OSPEED_HIGH(GPIOE_PIN1) | \ + PIN_OSPEED_HIGH(GPIOE_PIN2) | \ + PIN_OSPEED_HIGH(GPIOE_PIN3) | \ + PIN_OSPEED_HIGH(GPIOE_PIN4) | \ + PIN_OSPEED_HIGH(GPIOE_PIN5) | \ + PIN_OSPEED_HIGH(GPIOE_PIN6) | \ + PIN_OSPEED_HIGH(GPIOE_PIN7) | \ + PIN_OSPEED_HIGH(GPIOE_PIN8) | \ + PIN_OSPEED_HIGH(GPIOE_PIN9) | \ + PIN_OSPEED_HIGH(GPIOE_PIN10) | \ + PIN_OSPEED_HIGH(GPIOE_PIN11) | \ + PIN_OSPEED_HIGH(GPIOE_PIN12) | \ + PIN_OSPEED_HIGH(GPIOE_PIN13) | \ + PIN_OSPEED_HIGH(GPIOE_PIN14) | \ + PIN_OSPEED_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ + PIN_ODR_HIGH(GPIOE_PIN1) | \ + PIN_ODR_HIGH(GPIOE_PIN2) | \ + PIN_ODR_HIGH(GPIOE_PIN3) | \ + PIN_ODR_HIGH(GPIOE_PIN4) | \ + PIN_ODR_HIGH(GPIOE_PIN5) | \ + PIN_ODR_HIGH(GPIOE_PIN6) | \ + PIN_ODR_HIGH(GPIOE_PIN7) | \ + PIN_ODR_HIGH(GPIOE_PIN8) | \ + PIN_ODR_HIGH(GPIOE_PIN9) | \ + PIN_ODR_HIGH(GPIOE_PIN10) | \ + PIN_ODR_HIGH(GPIOE_PIN11) | \ + PIN_ODR_HIGH(GPIOE_PIN12) | \ + PIN_ODR_HIGH(GPIOE_PIN13) | \ + PIN_ODR_HIGH(GPIOE_PIN14) | \ + PIN_ODR_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN7, 0U)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOE_PIN15, 0U)) + +/* + * GPIOF setup: + * + * PF0 - PIN0 (input pullup). + * PF1 - PIN1 (input pullup). + * PF2 - PIN2 (input pullup). + * PF3 - PIN3 (input pullup). + * PF4 - PIN4 (input pullup). + * PF5 - PIN5 (input pullup). + * PF6 - PIN6 (input pullup). + * PF7 - PIN7 (input pullup). + * PF8 - PIN8 (input pullup). + * PF9 - PIN9 (input pullup). + * PF10 - PIN10 (input pullup). + * PF11 - PIN11 (input pullup). + * PF12 - PIN12 (input pullup). + * PF13 - PIN13 (input pullup). + * PF14 - PIN14 (input pullup). + * PF15 - PIN15 (input pullup). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ + PIN_MODE_INPUT(GPIOF_PIN1) | \ + PIN_MODE_INPUT(GPIOF_PIN2) | \ + PIN_MODE_INPUT(GPIOF_PIN3) | \ + PIN_MODE_INPUT(GPIOF_PIN4) | \ + PIN_MODE_INPUT(GPIOF_PIN5) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_INPUT(GPIOF_PIN7) | \ + PIN_MODE_INPUT(GPIOF_PIN8) | \ + PIN_MODE_INPUT(GPIOF_PIN9) | \ + PIN_MODE_INPUT(GPIOF_PIN10) | \ + PIN_MODE_INPUT(GPIOF_PIN11) | \ + PIN_MODE_INPUT(GPIOF_PIN12) | \ + PIN_MODE_INPUT(GPIOF_PIN13) | \ + PIN_MODE_INPUT(GPIOF_PIN14) | \ + PIN_MODE_INPUT(GPIOF_PIN15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_PIN0) | \ + PIN_OSPEED_HIGH(GPIOF_PIN1) | \ + PIN_OSPEED_HIGH(GPIOF_PIN2) | \ + PIN_OSPEED_HIGH(GPIOF_PIN3) | \ + PIN_OSPEED_HIGH(GPIOF_PIN4) | \ + PIN_OSPEED_HIGH(GPIOF_PIN5) | \ + PIN_OSPEED_HIGH(GPIOF_PIN6) | \ + PIN_OSPEED_HIGH(GPIOF_PIN7) | \ + PIN_OSPEED_HIGH(GPIOF_PIN8) | \ + PIN_OSPEED_HIGH(GPIOF_PIN9) | \ + PIN_OSPEED_HIGH(GPIOF_PIN10) | \ + PIN_OSPEED_HIGH(GPIOF_PIN11) | \ + PIN_OSPEED_HIGH(GPIOF_PIN12) | \ + PIN_OSPEED_HIGH(GPIOF_PIN13) | \ + PIN_OSPEED_HIGH(GPIOF_PIN14) | \ + PIN_OSPEED_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ + PIN_ODR_HIGH(GPIOF_PIN1) | \ + PIN_ODR_HIGH(GPIOF_PIN2) | \ + PIN_ODR_HIGH(GPIOF_PIN3) | \ + PIN_ODR_HIGH(GPIOF_PIN4) | \ + PIN_ODR_HIGH(GPIOF_PIN5) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_PIN7) | \ + PIN_ODR_HIGH(GPIOF_PIN8) | \ + PIN_ODR_HIGH(GPIOF_PIN9) | \ + PIN_ODR_HIGH(GPIOF_PIN10) | \ + PIN_ODR_HIGH(GPIOF_PIN11) | \ + PIN_ODR_HIGH(GPIOF_PIN12) | \ + PIN_ODR_HIGH(GPIOF_PIN13) | \ + PIN_ODR_HIGH(GPIOF_PIN14) | \ + PIN_ODR_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN7, 0U)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOF_PIN15, 0U)) + +/* + * GPIOG setup: + * + * PG0 - PIN0 (input pullup). + * PG1 - PIN1 (input pullup). + * PG2 - PIN2 (input pullup). + * PG3 - PIN3 (input pullup). + * PG4 - PIN4 (input pullup). + * PG5 - PIN5 (input pullup). + * PG6 - PIN6 (input pullup). + * PG7 - PIN7 (input pullup). + * PG8 - PIN8 (input pullup). + * PG9 - PIN9 (input pullup). + * PG10 - PIN10 (input pullup). + * PG11 - PIN11 (input pullup). + * PG12 - PIN12 (input pullup). + * PG13 - PIN13 (input pullup). + * PG14 - PIN14 (input pullup). + * PG15 - PIN15 (input pullup). + */ +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \ + PIN_MODE_INPUT(GPIOG_PIN1) | \ + PIN_MODE_INPUT(GPIOG_PIN2) | \ + PIN_MODE_INPUT(GPIOG_PIN3) | \ + PIN_MODE_INPUT(GPIOG_PIN4) | \ + PIN_MODE_INPUT(GPIOG_PIN5) | \ + PIN_MODE_INPUT(GPIOG_PIN6) | \ + PIN_MODE_INPUT(GPIOG_PIN7) | \ + PIN_MODE_INPUT(GPIOG_PIN8) | \ + PIN_MODE_INPUT(GPIOG_PIN9) | \ + PIN_MODE_INPUT(GPIOG_PIN10) | \ + PIN_MODE_INPUT(GPIOG_PIN11) | \ + PIN_MODE_INPUT(GPIOG_PIN12) | \ + PIN_MODE_INPUT(GPIOG_PIN13) | \ + PIN_MODE_INPUT(GPIOG_PIN14) | \ + PIN_MODE_INPUT(GPIOG_PIN15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOG_PIN15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_PIN0) | \ + PIN_OSPEED_HIGH(GPIOG_PIN1) | \ + PIN_OSPEED_HIGH(GPIOG_PIN2) | \ + PIN_OSPEED_HIGH(GPIOG_PIN3) | \ + PIN_OSPEED_HIGH(GPIOG_PIN4) | \ + PIN_OSPEED_HIGH(GPIOG_PIN5) | \ + PIN_OSPEED_HIGH(GPIOG_PIN6) | \ + PIN_OSPEED_HIGH(GPIOG_PIN7) | \ + PIN_OSPEED_HIGH(GPIOG_PIN8) | \ + PIN_OSPEED_HIGH(GPIOG_PIN9) | \ + PIN_OSPEED_HIGH(GPIOG_PIN10) | \ + PIN_OSPEED_HIGH(GPIOG_PIN11) | \ + PIN_OSPEED_HIGH(GPIOG_PIN12) | \ + PIN_OSPEED_HIGH(GPIOG_PIN13) | \ + PIN_OSPEED_HIGH(GPIOG_PIN14) | \ + PIN_OSPEED_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLUP(GPIOG_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOG_PIN15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \ + PIN_ODR_HIGH(GPIOG_PIN1) | \ + PIN_ODR_HIGH(GPIOG_PIN2) | \ + PIN_ODR_HIGH(GPIOG_PIN3) | \ + PIN_ODR_HIGH(GPIOG_PIN4) | \ + PIN_ODR_HIGH(GPIOG_PIN5) | \ + PIN_ODR_HIGH(GPIOG_PIN6) | \ + PIN_ODR_HIGH(GPIOG_PIN7) | \ + PIN_ODR_HIGH(GPIOG_PIN8) | \ + PIN_ODR_HIGH(GPIOG_PIN9) | \ + PIN_ODR_HIGH(GPIOG_PIN10) | \ + PIN_ODR_HIGH(GPIOG_PIN11) | \ + PIN_ODR_HIGH(GPIOG_PIN12) | \ + PIN_ODR_HIGH(GPIOG_PIN13) | \ + PIN_ODR_HIGH(GPIOG_PIN14) | \ + PIN_ODR_HIGH(GPIOG_PIN15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN7, 0U)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOG_PIN15, 0U)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - PIN2 (input pullup). + * PH3 - PIN3 (input pullup). + * PH4 - PIN4 (input pullup). + * PH5 - PIN5 (input pullup). + * PH6 - PIN6 (input pullup). + * PH7 - PIN7 (input pullup). + * PH8 - PIN8 (input pullup). + * PH9 - PIN9 (input pullup). + * PH10 - PIN10 (input pullup). + * PH11 - PIN11 (input pullup). + * PH12 - PIN12 (input pullup). + * PH13 - PIN13 (input pullup). + * PH14 - PIN14 (input pullup). + * PH15 - PIN15 (input pullup). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOH_PIN2) | \ + PIN_MODE_INPUT(GPIOH_PIN3) | \ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_INPUT(GPIOH_PIN5) | \ + PIN_MODE_INPUT(GPIOH_PIN6) | \ + PIN_MODE_INPUT(GPIOH_PIN7) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ + PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ + PIN_OSPEED_HIGH(GPIOH_PIN2) | \ + PIN_OSPEED_HIGH(GPIOH_PIN3) | \ + PIN_OSPEED_HIGH(GPIOH_PIN4) | \ + PIN_OSPEED_HIGH(GPIOH_PIN5) | \ + PIN_OSPEED_HIGH(GPIOH_PIN6) | \ + PIN_OSPEED_HIGH(GPIOH_PIN7) | \ + PIN_OSPEED_HIGH(GPIOH_PIN8) | \ + PIN_OSPEED_HIGH(GPIOH_PIN9) | \ + PIN_OSPEED_HIGH(GPIOH_PIN10) | \ + PIN_OSPEED_HIGH(GPIOH_PIN11) | \ + PIN_OSPEED_HIGH(GPIOH_PIN12) | \ + PIN_OSPEED_HIGH(GPIOH_PIN13) | \ + PIN_OSPEED_HIGH(GPIOH_PIN14) | \ + PIN_OSPEED_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0U)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0U)) + +/* + * GPIOI setup: + * + * PI0 - PIN0 (input pullup). + * PI1 - PIN1 (input pullup). + * PI2 - PIN2 (input pullup). + * PI3 - PIN3 (input pullup). + * PI4 - PIN4 (input pullup). + * PI5 - PIN5 (input pullup). + * PI6 - PIN6 (input pullup). + * PI7 - PIN7 (input pullup). + * PI8 - PIN8 (input pullup). + * PI9 - PIN9 (input pullup). + * PI10 - PIN10 (input pullup). + * PI11 - PIN11 (input pullup). + * PI12 - PIN12 (input pullup). + * PI13 - PIN13 (input pullup). + * PI14 - PIN14 (input pullup). + * PI15 - PIN15 (input pullup). + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \ + PIN_MODE_INPUT(GPIOI_PIN1) | \ + PIN_MODE_INPUT(GPIOI_PIN2) | \ + PIN_MODE_INPUT(GPIOI_PIN3) | \ + PIN_MODE_INPUT(GPIOI_PIN4) | \ + PIN_MODE_INPUT(GPIOI_PIN5) | \ + PIN_MODE_INPUT(GPIOI_PIN6) | \ + PIN_MODE_INPUT(GPIOI_PIN7) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_INPUT(GPIOI_PIN9) | \ + PIN_MODE_INPUT(GPIOI_PIN10) | \ + PIN_MODE_INPUT(GPIOI_PIN11) | \ + PIN_MODE_INPUT(GPIOI_PIN12) | \ + PIN_MODE_INPUT(GPIOI_PIN13) | \ + PIN_MODE_INPUT(GPIOI_PIN14) | \ + PIN_MODE_INPUT(GPIOI_PIN15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_HIGH(GPIOI_PIN0) | \ + PIN_OSPEED_HIGH(GPIOI_PIN1) | \ + PIN_OSPEED_HIGH(GPIOI_PIN2) | \ + PIN_OSPEED_HIGH(GPIOI_PIN3) | \ + PIN_OSPEED_HIGH(GPIOI_PIN4) | \ + PIN_OSPEED_HIGH(GPIOI_PIN5) | \ + PIN_OSPEED_HIGH(GPIOI_PIN6) | \ + PIN_OSPEED_HIGH(GPIOI_PIN7) | \ + PIN_OSPEED_HIGH(GPIOI_PIN8) | \ + PIN_OSPEED_HIGH(GPIOI_PIN9) | \ + PIN_OSPEED_HIGH(GPIOI_PIN10) | \ + PIN_OSPEED_HIGH(GPIOI_PIN11) | \ + PIN_OSPEED_HIGH(GPIOI_PIN12) | \ + PIN_OSPEED_HIGH(GPIOI_PIN13) | \ + PIN_OSPEED_HIGH(GPIOI_PIN14) | \ + PIN_OSPEED_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLUP(GPIOI_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \ + PIN_ODR_HIGH(GPIOI_PIN1) | \ + PIN_ODR_HIGH(GPIOI_PIN2) | \ + PIN_ODR_HIGH(GPIOI_PIN3) | \ + PIN_ODR_HIGH(GPIOI_PIN4) | \ + PIN_ODR_HIGH(GPIOI_PIN5) | \ + PIN_ODR_HIGH(GPIOI_PIN6) | \ + PIN_ODR_HIGH(GPIOI_PIN7) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_PIN9) | \ + PIN_ODR_HIGH(GPIOI_PIN10) | \ + PIN_ODR_HIGH(GPIOI_PIN11) | \ + PIN_ODR_HIGH(GPIOI_PIN12) | \ + PIN_ODR_HIGH(GPIOI_PIN13) | \ + PIN_ODR_HIGH(GPIOI_PIN14) | \ + PIN_ODR_HIGH(GPIOI_PIN15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN7, 0U)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOI_PIN15, 0U)) + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/common/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/common/CMakeLists.txt new file mode 100644 index 00000000..42be0d5f --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/common/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c") + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/common/Device_BlockStorage-DEBUG.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 00000000..0e822535 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,97 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +//16kB block +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 1 }, // 08000000 nanoBooter + { BlockRange_BLOCKTYPE_CODE , 2, 3 } // 08008000 nanoCLR +}; + +//64kB block +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 08010000 nanoCLR +}; + +//384kB block +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 1 }, // 08020000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 2, 5 } // 08040000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08010000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 6, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00080000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/common/Device_BlockStorage.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/common/Device_BlockStorage.c new file mode 100644 index 00000000..6e381213 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/common/Device_BlockStorage.c @@ -0,0 +1,97 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +//16kB block +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 0 }, // 08000000 nanoBooter + { BlockRange_BLOCKTYPE_CODE , 1, 3 } // 08004000 nanoCLR +}; + +//64kB block +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 08010000 nanoCLR +}; + +//384kB block +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 1 }, // 08020000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 2, 5 } // 08040000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08010000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 6, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00080000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/common/serialcfg.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/common/serialcfg.h new file mode 100644 index 00000000..bb32facc --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/common/serialcfg.h @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef SERIALCFG_H +#define SERIALCFG_H + +// define which serial driver the Wire Protocol will be using +#define SERIAL_DRIVER SD2 + +#endif /* SERIALCFG_H */ + +/** @} */ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/managed_helpers/README.md b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/managed_helpers/README.md new file mode 100644 index 00000000..57c6e269 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/managed_helpers/README.md @@ -0,0 +1,5 @@ +## Managed code helpers + +This folder contains helper classes to make developers life easier when coding for this target board. + +* [Adc](ST_NUCLEO64_F411RE_NF.Adc.cs) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/managed_helpers/ST_NUCLEO64_F411RE_NF.Adc.cs b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/managed_helpers/ST_NUCLEO64_F411RE_NF.Adc.cs new file mode 100644 index 00000000..f01b85ff --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/managed_helpers/ST_NUCLEO64_F411RE_NF.Adc.cs @@ -0,0 +1,58 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +namespace nanoFramework.Targets.ST_NUCLEO64_F411RE_NF +{ + /// + /// Enumeration of ADC channels available on ST_NUCLEO64_F411RE_NF + /// + public static class AdcChannels + { + /// + /// Channel 0, exposed as A0, connected to pin 1 on CN8 = PA0 (ADC1 - IN0) + /// + public const int Channel_0 = 0; + + /// + /// Channel 1, exposed as A1, connected to pin 2 on CN8 = PA1 (ADC1 - IN1) + /// + public const int Channel_1 = 1; + + /// + /// Channel 2, exposed as A2, connected to pin 3 on CN8 = PA4 (ADC1 - IN4) + /// + public const int Channel_2 = 2; + + /// + /// Channel 3, exposed as A3, connected to pin 4 on CN8 = PB0 (ADC1 - IN8) + /// + public const int Channel_3 = 3; + + /// + /// Channel 4, exposed as A4, connected to pin 5 on CN8 = PC1 (ADC1 - IN11) + /// + public const int Channel_4 = 4; + + /// + /// Channel 5, exposed on A5, connected to pin 6 on CN8 = PC0 (ADC1 - IN10) + /// + public const int Channel_5 = 5; + + /// + /// Channel 6, internal temperature sensor, connected to ADC1 + /// + public const int Channel_TemperatureSensor = 6; + + /// + /// Channel 7, internal voltage reference, connected to ADC1 + /// + public const int Channel_VrefIn = 7; + + /// + /// Channel 8, connected to VBatt pin, ADC1 + /// + public const int Channel_Vbatt = 8; + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/CMakeLists.txt new file mode 100644 index 00000000..291f47e1 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/CMakeLists.txt @@ -0,0 +1,9 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# # append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/STM32F411xE_booter-DEBUG.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/STM32F411xE_booter-DEBUG.ld new file mode 100644 index 00000000..5c5bde44 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/STM32F411xE_booter-DEBUG.ld @@ -0,0 +1,80 @@ +/* +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F411xE memory setup. + * + */ +MEMORY +{ + flash : org = 0x08000000, len = 32k /* space reserved for nanoBooter (1st two sectors 0x08000000 to 0x08008000)*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 128k /* SRAM1 */ + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Stacks rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/STM32F411xE_booter.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/STM32F411xE_booter.ld new file mode 100644 index 00000000..33f45204 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/STM32F411xE_booter.ld @@ -0,0 +1,80 @@ +/* +// +// Copyright (c) 2017..2019 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F411xE memory setup. + * + */ +MEMORY +{ + flash : org = 0x08000000, len = 16k /* space reserved for nanoBooter (1st two sectors 0x08000000 to 0x08004000)*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 128k /* SRAM1 */ + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Stacks rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/chconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/chconf.h new file mode 100644 index 00000000..335e3fa4 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/chconf.h @@ -0,0 +1,616 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 1000 // this is 1 millisecond + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#define CH_CFG_INTERVALS_SIZE 32 + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_TIME_TYPES_SIZE 32 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES FALSE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS FALSE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT FALSE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES FALSE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_OBJ_FIFOS TRUE + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#define CH_CFG_USE_FACTORY FALSE + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 + +/** + * @brief Enables the registry of generic objects. + */ +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE + +/** + * @brief Enables factory for generic buffers. + */ +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE + +/** + * @brief Enables factory for semaphores. + */ +#define CH_CFG_FACTORY_SEMAPHORES TRUE + +/** + * @brief Enables factory for mailboxes. + */ +#define CH_CFG_FACTORY_MAILBOXES TRUE + +/** + * @brief Enables factory for objects FIFOs. + */ +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/halconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/halconf.h new file mode 100644 index 00000000..bb163e41 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/halconf.h @@ -0,0 +1,513 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/halconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/halconf_nf.h new file mode 100644 index 00000000..e35b7bec --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/halconf_nf.h @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +#if !defined(HAL_USE_STM32_RNG) +#define HAL_USE_STM32_RNG FALSE +#endif + +#endif // _HALCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/main.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/main.c new file mode 100644 index 00000000..2df0f094 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/main.c @@ -0,0 +1,73 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); + +// Application entry point. +int main(void) { + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init SWO as soon as possible to make it available to output ASAP + #if (SWO_OUTPUT == TRUE) + SwoInit(); + #endif + + // the following IF is not mandatory, it's just providing a way for a user to 'force' + // the board to remain in nanoBooter and not launching nanoCLR + + // if the USER button (blue one) is pressed, skip the check for a valid CLR image and remain in booter + if (palReadPad(GPIOC, GPIOC_BUTTON)) + { + // check for valid CLR image + if(CheckValidCLRImage((uint32_t)&__nanoImage_end__)) + { + // there seems to be a valid CLR image + // launch nanoCLR + LaunchCLR((uint32_t)&__nanoImage_end__); + } + } + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // starts the serial driver + sdStart(&SERIAL_DRIVER, NULL); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // Normal main() thread + while (true) { + palSetPad(GPIOA, GPIOA_LED_GREEN); + osDelay(500); + palClearPad(GPIOA, GPIOA_LED_GREEN); + osDelay(500); + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/mcuconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/mcuconf.h new file mode 100644 index 00000000..692d8d1e --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/mcuconf.h @@ -0,0 +1,337 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF +#define STM32F411_MCUCONF +/* + * HAL driver system settings. + */ + +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 192 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 4 + +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSE +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 250 +#define STM32_SDC_READ_TIMEOUT_MS 25 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/mcuconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/mcuconf_nf.h new file mode 100644 index 00000000..574b9636 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/mcuconf_nf.h @@ -0,0 +1,10 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/target_board.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/target_board.h.in new file mode 100644 index 00000000..19531d9c --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoBooter/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOBOOTER_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/CMakeLists.txt new file mode 100644 index 00000000..e5496b7e --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/STM32F411xE_CLR-DEBUG.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/STM32F411xE_CLR-DEBUG.ld new file mode 100644 index 00000000..674ee9b4 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/STM32F411xE_CLR-DEBUG.ld @@ -0,0 +1,76 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F411xE memory setup. + * Note: Only use of ram0. + */ +MEMORY +{ + flash : org = 0x08008000, len = 512k - 32k - 256k /* flash size less the space reserved for nanoBooter and application deployment*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x08040000, len = 256k /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 128k /* SRAM1 */ + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/STM32F411xE_CLR.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/STM32F411xE_CLR.ld new file mode 100644 index 00000000..6b1d2747 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/STM32F411xE_CLR.ld @@ -0,0 +1,76 @@ +/* +// +// Copyright (c) 2017..2019 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F411xE memory setup. + * Note: Only use of ram0. + */ +MEMORY +{ + flash : org = 0x08004000, len = 512k - 16k - 256k /* flash size less the space reserved for nanoBooter and application deployment*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x08040000, len = 256k /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 128k /* SRAM1 */ + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/chconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/chconf.h new file mode 100644 index 00000000..3ce5c5aa --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/chconf.h @@ -0,0 +1,621 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 10000 + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#define CH_CFG_INTERVALS_SIZE 32 + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_TIME_TYPES_SIZE 32 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_OBJ_FIFOS TRUE + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#define CH_CFG_USE_FACTORY FALSE + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 + +/** + * @brief Enables the registry of generic objects. + */ +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE + +/** + * @brief Enables factory for generic buffers. + */ +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE + +/** + * @brief Enables factory for semaphores. + */ +#define CH_CFG_FACTORY_SEMAPHORES TRUE + +/** + * @brief Enables factory for mailboxes. + */ +#define CH_CFG_FACTORY_MAILBOXES TRUE + +/** + * @brief Enables factory for objects FIFOs. + */ +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +/////////////////////////////////////////////////////////////////////////////// +// address of vector table for nanoCLR +#define CORTEX_VTOR_INIT 0x08008000U +/////////////////////////////////////////////////////////////////////////////// + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/halconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/halconf.h new file mode 100644 index 00000000..43e74c29 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/halconf.h @@ -0,0 +1,525 @@ +// +// Copyright (c) 2017..2019 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +// #define HAL_USE_ADC TRUE +// #endif + +/** + * @brief Enables the CAN subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +// #define HAL_USE_CAN FALSE +// #endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +// /** +// * @brief Enables the DAC subsystem. +// */ +// #if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +// #define HAL_USE_DAC FALSE +// #endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +// this option is set at target_platform.h (from config file) +//#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +//#define HAL_USE_I2C TRUE +//#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +// #define HAL_USE_MAC TRUE +// #endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +// #define HAL_USE_PWM TRUE +// #endif + +/** + * @brief Enables the RTC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +// #define HAL_USE_RTC TRUE +// #endif + +/** + * @brief Enables the SDC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +// #define HAL_USE_SDC FALSE +// #endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + + +/** + * @brief Enables the SPI subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +// #define HAL_USE_SPI FALSE +// #endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +// #define HAL_USE_UART FALSE +// #endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +// #define HAL_USE_WDG FALSE +// #endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS TRUE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 64 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/halconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/halconf_nf.h new file mode 100644 index 00000000..2cf04ece --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/halconf_nf.h @@ -0,0 +1,24 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +// Disables the FSMC subsystem. +#if !defined(HAL_USE_FSMC) +#define HAL_USE_FSMC FALSE +#endif + +// STM32F411xx Does not support TRNG +#if !defined(HAL_USE_STM32_RNG) +#define HAL_USE_STM32_RNG FALSE +#endif + +#endif // _HALCONF_NF_H_ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/main.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/main.c new file mode 100644 index 00000000..58ebf66f --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/main.c @@ -0,0 +1,67 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); +// declare CLRStartup thread here +osThreadDef(CLRStartupThread, osPriorityNormal, 4096, "CLRStartupThread"); + +// Application entry point. +int main(void) { + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init SWO as soon as possible to make it available to output ASAP + #if (SWO_OUTPUT == TRUE) + SwoInit(); + #endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // start watchdog + Watchdog_Init(); + + // starts the serial driver + sdStart(&SERIAL_DRIVER, NULL); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // CLR settings to launch CLR thread + CLR_SETTINGS clrSettings; + (void)memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.EnterDebuggerLoopAfterExit = true; + + // create the CLR Startup thread + osThreadCreate(osThread(CLRStartupThread), &clrSettings); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + while (true) { + osDelay(100); + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/mcuconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/mcuconf.h new file mode 100644 index 00000000..1b4c6b57 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/mcuconf.h @@ -0,0 +1,336 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF +#define STM32F411_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 192 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 4 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSE +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 TRUE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 TRUE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 TRUE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 250 +#define STM32_SDC_READ_TIMEOUT_MS 25 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 TRUE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 TRUE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG TRUE + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/mcuconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/mcuconf_nf.h new file mode 100644 index 00000000..574b9636 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/mcuconf_nf.h @@ -0,0 +1,10 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/nanoHAL.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/nanoHAL.cpp new file mode 100644 index 00000000..076a50fc --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/nanoHAL.cpp @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +void HAL_EnterBooterMode() +{ +} + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/target_board.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/target_board.h.in new file mode 100644 index 00000000..b980bc05 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/nanoCLR/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOCLR_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_BlockStorage.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_BlockStorage.c new file mode 100644 index 00000000..9e7c7f55 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_BlockStorage.c @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice STM32Flash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &STM32Flash_BlockStorageInterface, &Device_BlockStorageConfig, false); +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_BlockStorage.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_BlockStorage.h new file mode 100644 index 00000000..aa50b1b7 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_common.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_common.c new file mode 100644 index 00000000..c633da5b --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_common.c @@ -0,0 +1,24 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include "target_common.h" + +HAL_SYSTEM_CONFIG HalSystemConfig = +{ + { true }, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, //ConvertCOM_DebugHandle(1), + 0, //ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + { RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size }, + { FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size } +}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_common.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_common.h.in new file mode 100644 index 00000000..419f9f35 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_common.h.in @@ -0,0 +1,37 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x20000000) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x00020000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x08000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00080000) + +///////////////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////// +#define TARGETNAMESTRING "@CHIBIOS_BOARD@" +#define PLATFORMNAMESTRING "STM32F4" +/////////////////////////////////////////////// + +#endif /* _TARGET_COMMON_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_system_devices_dac_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_system_devices_dac_config.cpp new file mode 100644 index 00000000..88a70347 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_system_devices_dac_config.cpp @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_DAC_PORT_PIN_CHANNEL DacPortPinConfig[] = { + + // DAC1, channel 1, GPIO port A, pin 4 + {1, 1, GPIOA, 4}, + +}; + +const int DacChannelCount = ARRAYSIZE(DacPortPinConfig); diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_windows_devices_adc_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_windows_devices_adc_config.cpp new file mode 100644 index 00000000..8fddb9a0 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_windows_devices_adc_config.cpp @@ -0,0 +1,24 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_adc_native_target.h" + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // ADC1 + {1, GPIOA, 0, ADC_CHANNEL_IN0}, + {1, GPIOA, 1, ADC_CHANNEL_IN1}, + {1, GPIOA, 4, ADC_CHANNEL_IN4}, + {1, GPIOB, 0, ADC_CHANNEL_IN8}, + {1, GPIOC, 1, ADC_CHANNEL_IN11}, + {1, GPIOC, 0, ADC_CHANNEL_IN10}, + + // these are the internal sources, available only at ADC1 + {1, NULL, 0, ADC_CHANNEL_SENSOR}, + {1, NULL, 0, ADC_CHANNEL_VREFINT}, + {1, NULL, 0, ADC_CHANNEL_VBAT}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_windows_devices_i2c_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_windows_devices_i2c_config.cpp new file mode 100644 index 00000000..2a60a22f --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_windows_devices_i2c_config.cpp @@ -0,0 +1,18 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_i2c_native_target.h" + +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for SCL pin is: GPIOB +// port for SDA pin is: GPIOB +// SCL pin: is GPIOB_8 +// SDA pin: is GPIOB_9 +// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, GPIOB, GPIOB, 8, 9, 4) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_windows_devices_serialcommunication_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_windows_devices_serialcommunication_config.cpp new file mode 100644 index 00000000..fbfef7b4 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_windows_devices_serialcommunication_config.cpp @@ -0,0 +1,36 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_windows_devices_serialcommunication_config.h" +#include "win_dev_serial_native_target.h" + +/////////// +// UART6 // +/////////// + +// pin configuration for UART6 +// port: GPIOA +// TX pin: is GPIOA_11 +// RX pin: is GPIOA_12 +// GPIO alternate pin function is 7 (see "Table 9. Alternate function mapping" in STM32F411xC and STM32F411xE datasheet) +UART_CONFIG_PINS(6, GPIOA, GPIOA, 11, 12, 8) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart6_TxBuffer[UART6_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart6_RxBuffer[UART6_RX_SIZE]; + +// initialization for UART6 +UART_INIT(6, UART6_TX_SIZE, UART6_RX_SIZE) + +// un-initialization for UART6 +UART_UNINIT(6) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_windows_devices_serialcommunication_config.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_windows_devices_serialcommunication_config.h new file mode 100644 index 00000000..408eb86b --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_windows_devices_serialcommunication_config.h @@ -0,0 +1,18 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +/////////// +// UART6 // +/////////// + +// enable USART6 +#define NF_SERIAL_COMM_STM32_UART_USE_USART6 TRUE + +// buffers size +// tx buffer size: 1024 bytes +#define UART6_TX_SIZE 1024 +// rx buffer size: 1024 bytes +#define UART6_RX_SIZE 1024 diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_windows_devices_spi_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_windows_devices_spi_config.cpp new file mode 100644 index 00000000..f08c5650 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF/target_windows_devices_spi_config.cpp @@ -0,0 +1,10 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_spi_native_target.h" + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/CMakeLists.txt new file mode 100644 index 00000000..0f13c959 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/CMakeLists.txt @@ -0,0 +1,205 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +cmake_minimum_required(VERSION 3.0) +ENABLE_LANGUAGE(ASM) + +# add header files with common OS definitions and board definitions specific for each image +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/target_common.h" @ONLY) + +set(NANOBOOTER_PROJECT_NAME "nanoBooter") +set(NANOCLR_PROJECT_NAME "nanoCLR") + +find_package(BuildUtils REQUIRED) +find_package(CHIBIOS REQUIRED) +find_package(ChibiOSnfOverlay REQUIRED) +find_package(WireProtocol REQUIRED) + +# packages for nanoFramework libraries +####################################### +# mandatory +find_package(NF_CoreCLR REQUIRED) + +####################################### +# optional + +# ChibiOS contrib repo +if(CHIBIOS_CONTRIB_REQUIRED) + find_package(ChibiOS-Contrib REQUIRED) +endif() + +# nF feature: debugger +if(NF_FEATURE_DEBUGGER) + find_package(NF_Debugger REQUIRED) + find_package(NF_Diagnostics REQUIRED) +endif() + +# nF feature: networking +if(USE_NETWORKING_OPTION) + find_package(CHIBIOS_LWIP REQUIRED) +endif() + +# nF feature: filesystem +if(USE_FILESYSTEM_OPTION) + find_package(CHIBIOS_FATFS REQUIRED) +endif() + +####################################### + +add_subdirectory("common") +add_subdirectory("nanoBooter") +add_subdirectory("nanoCLR") + +####################### +# nanoBooter executable + +add_executable( + # executables for project, project sources + ${NANOBOOTER_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + "${CMAKE_CURRENT_SOURCE_DIR}/target_BlockStorage.c" + + # need to add configuration manager to allow get/store configuration blocks + "${PROJECT_SOURCE_DIR}/src/HAL/nanoHAL_ConfigurationManager_stubs.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOBOOTER_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOBOOTER_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOBOOTER_SOURCES} + + ${CHIBIOS_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} +) + +####################### +# nanoCLR executable + +add_executable( + # executables for project, project sources + ${NANOCLR_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOCLR_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOCLR_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOCLR_SOURCES} + + ${CHIBIOS_SOURCES} + ${CHIBIOS_CONTRIB_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} + + # sources for nanoFramework libraries + ${NF_CoreCLR_SOURCES} + ${NF_Debugger_SOURCES} + ${NF_Diagnostics_SOURCES} + + # sources for nanoFramework APIs + ${TARGET_NANO_APIS_SOURCES} +) + +# add dependency from ChibiOS (this is required to make sure the ChibiOS repo is downloaded before the build starts) +add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf ChibiOS) +add_dependencies(${NANOCLR_PROJECT_NAME}.elf ChibiOS) + +# include common directories +include_directories( + ${CMAKE_CURRENT_BINARY_DIR} + ${CMAKE_CURRENT_SOURCE_DIR} + ${CMAKE_CURRENT_SOURCE_DIR}/common + ${PROJECT_SOURCE_DIR}/src/CLR/Core + ${PROJECT_SOURCE_DIR}/src/CLR/Include + ${PROJECT_SOURCE_DIR}/src/HAL/Include + ${PROJECT_SOURCE_DIR}/src/PAL/Include + + ${WireProtocol_INCLUDE_DIRS} + ${CHIBIOS_INCLUDE_DIRS} + ${ChibiOSnfOverlay_INCLUDE_DIRS} + ${CHIBIOS_CONTRIB_INCLUDE_DIRS} + + ${TARGET_CMSIS_COMMON_INCLUDE_DIRS} + ${TARGET_CHIBIOS_COMMON_INCLUDE_DIRS} +) + +# include directories for nanoBooter +target_include_directories(${NANOBOOTER_PROJECT_NAME}.elf PUBLIC + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter" + ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter + + ${TARGET_CMSIS_NANOBOOTER_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOBOOTER_INCLUDE_DIRS} +) + +# include directories for nanoCLR +target_include_directories(${NANOCLR_PROJECT_NAME}.elf PUBLIC + ${CMAKE_CURRENT_BINARY_DIR}/nanoCLR + ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR + + ${TARGET_CMSIS_NANOCLR_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOCLR_INCLUDE_DIRS} + + # directories for nanoFramework libraries + ${NF_CoreCLR_INCLUDE_DIRS} + ${NF_Debugger_INCLUDE_DIRS} + ${NF_Diagnostics_INCLUDE_DIRS} + + # includes for nanoFramework APIs + ${TARGET_NANO_APIS_INCLUDES} + + # includes for ChibiOS LwIP + ${CHIBIOS_LWIP_INCLUDE_DIRS} +) + +# set compiler options +nf_set_compiler_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_options(${NANOCLR_PROJECT_NAME}.elf) + +# set compiler definitions +nf_set_compiler_definitions(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_definitions(${NANOCLR_PROJECT_NAME}.elf) + +# set linker files +if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F407xG_booter-DEBUG.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/STM32F407xG_CLR-DEBUG.ld) +else() + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F407xG_booter.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/STM32F407xG_CLR.ld) +endif() + +# set linker options +nf_set_linker_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_linker_options(${NANOCLR_PROJECT_NAME}.elf) + +# add other linker flags +########################################################### +# the sizes of CRT heap and ChibiOS stacks are defined here +############################################################################ +# CRT heap is assigned to RAM4 region @ CCM SRAM so we are OK to use it all +############################################################################ +set_property(TARGET ${NANOBOOTER_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x400,--defsym=__crt_heap_size__=0x10000") +set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x10000") + +# generate output files +nf_generate_build_output_files(${NANOBOOTER_PROJECT_NAME}.elf) +nf_generate_build_output_files(${NANOCLR_PROJECT_NAME}.elf) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/README.md b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/README.md new file mode 100644 index 00000000..f0799610 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/README.md @@ -0,0 +1,57 @@ +## STM STM32F4DISCOVERY board + +![STM STM32F4DISCOVERY board](stm32f4_discovery.jpg) + +The board used in this community contribution is the STM32F4DISCOVERY board from STM. The board can be purchased from various sources and should be about 20 euros. Further information on this board and links for the user and programming manuals can be found at the product page in ST [website](https://www.st.com/en/evaluation-tools/stm32f4discovery.html). + +Some basic information abstracted from ST: + +- STM32F407VGT6 microcontroller featuring 32-bit ARM®Cortex®-M4 with FPU core, 1-Mbyte Flash memory, 192-kbyte RAM in an LQFP100 package +- On-board ST-LINK/V2 on STM32F4DISCOVERY (old reference) or ST-LINK/V2-A on STM32F407G-DISC1 (new order code) +- USB ST-LINK with re-enumeration capability and three different interfaces: + - Debug port + - Virtual Com port (with new order code only) + - Mass storage (with new order code only) +- Board power supply: through USB bus or from an external 5 V supply voltage +- External application power supply: 3 V and 5 V +- LIS302DL or LIS3DSH ST MEMS 3-axis accelerometer +- MP45DT02 ST-MEMS audio sensor omni-directional digital microphone +- CS43L22 audio DAC with integrated class D speaker driver +- Eight LEDs: + - LD1 (red/green) for USB communication + - LD2 (red) for 3.3 V power on + - Four user LEDs, LD3 (orange), LD4 (green), LD5 (red) and LD6 (blue) + - 2 USB OTG LEDs LD7 (green) VBUS and LD8 (red) over-current +- Two push-buttons (user and reset) +- USB OTG FS with micro-AB connector +- Extension header for all LQFP100 I/Os for quick connection to prototyping board and easy probing + +### Flashing and debugging + +This board has one mini USB connector exposing the embedded ST-Link interface that is used for flashing the nanoFramework firmware and for performing debugging on the nanoCLR code. +The second USB connector (a micro USB one) is used to connect the device with Visual Studio allowing to deploy and debug your C# managed applications. + +## ADC configurations + +The following ADC channels (and respective GPIO pins) are available to the managed API, in the respective index: + +- PC1, ADC1 IN11 +- PC2 ADC1 IN12 +- PA6 ADC2 IN6 +- PA7 ADC2 IN7 +- PB0 ADC2 IN8 +- Temp Sensor ADC1 +- VrefInt ADC1 +- Vbatt ADC1 + +## I2C configurations + +I2C buses available: +- I2C1 + - SCL pin: GPIOB_8 + - SDA pin: GPIOB_9 + +## Floating point + +The current build is set to add support for single-precision floating point. +Meaning that `System.Math` API supports only the `float` overloads. The `double` ones will throw a `NotImplementedException`. diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/common/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/common/CMakeLists.txt new file mode 100644 index 00000000..aa7f1d54 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/common/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/usbcfg.c") +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c") + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/common/Device_BlockStorage-DEBUG.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 00000000..52e006a1 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,97 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +//16kB block +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 1 }, // 0x08000000 nanoBooter + { BlockRange_BLOCKTYPE_CODE , 2, 3 } // 0x08008000 nanoCLR +}; + +//64kB block +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 0x08010000 nanoCLR +}; + +//128kB block +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 }, // 0x08020000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 1, 6 } // 0x08040000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08010000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 7, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00100000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/common/Device_BlockStorage.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/common/Device_BlockStorage.c new file mode 100644 index 00000000..5989a2ce --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/common/Device_BlockStorage.c @@ -0,0 +1,97 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +//16kB block +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 0 }, // 0x08000000 nanoBooter + { BlockRange_BLOCKTYPE_CODE , 1, 3 } // 0x08004000 nanoCLR +}; + +//64kB block +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 0x08010000 nanoCLR +}; + +//128kB block +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 }, // 0x08020000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 1, 6 } // 0x08040000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08010000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 7, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00100000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/common/usbcfg.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/common/usbcfg.c new file mode 100644 index 00000000..225d046a --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/common/usbcfg.c @@ -0,0 +1,454 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "hal.h" + +/* Virtual serial port over USB.*/ +SerialUSBDriver SDU1; + +/* + * Endpoints to be used for USBD2. + */ +#define USBD2_DATA_REQUEST_EP 1 +#define USBD2_DATA_AVAILABLE_EP 1 +#define USBD2_INTERRUPT_REQUEST_EP 2 + +// address for device unique ID +// valid for STM32F4 series +#define DEVICE_ID1 (0x1FFF7A10) +#define DEVICE_ID2 (0x1FFF7A14) +#define DEVICE_ID3 (0x1FFF7A18) + +// // size of string serial is 36 = 2 + 5x2 + 26 from silicon unique ID precedeed of string "NANO_" and descriptor codes +// #define USB_SIZ_STRING_SERIAL 36 + +//////////////////////////////////////////////// +// vendor +#define USB_STRING_VENDOR L"STMicroelectronics" +//////////////////////////////////////////////// + +// structure for USB Vendor with Unicode string +typedef struct usb_string_vendor +{ + uint8_t bLength; + uint8_t bDescriptorType; + wchar_t bPropertyData[sizeof(USB_STRING_VENDOR)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec) + +}usb_string_vendor; + + +///////////////////////////////////////////////////////////////////////// +// device description +#define USB_STRING_DEVICE_DESCRIPTION L"nanoFramework Virtual COM Port" +///////////////////////////////////////////////////////////////////////// + +// structure for USB device descriptor with Unicode string +typedef struct usb_string_device_description +{ + uint8_t bLength; + uint8_t bDescriptorType; + wchar_t bPropertyData[sizeof(USB_STRING_DEVICE_DESCRIPTION)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec) + +}usb_string_device_description; + + +///////////////////////////////////////////////////////////////////////// +// device serial number +// this will produce a string with NANO_ prefix followed +// by the hexadecimal representation of the silicon unique ID of the CPU +#define USB_STRING_SERIAL_NUMBER L"NANO_xxxxxxxxxxx" +///////////////////////////////////////////////////////////////////////// +#define INDEX_OF_WCHAR_FOR_UNIQUE_ID 5 + +// structure for USB serial number descriptor with Unicode string +typedef struct usb_string_serial_number +{ + uint8_t bLength; + uint8_t bDescriptorType; + wchar_t bPropertyData[sizeof(USB_STRING_SERIAL_NUMBER)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec) + +}usb_string_serial_number; + + +/* + * USB Device Descriptor. + */ +static const uint8_t vcom_device_descriptor_data[18] = { + USB_DESC_DEVICE (0x0200, /* bcdUSB (2.0). */ + 0x02, /* bDeviceClass (CDC). */ + 0x00, /* bDeviceSubClass. */ + 0x00, /* bDeviceProtocol. */ + 0x40, /* bMaxPacketSize. */ + 0x0483, /* idVendor (ST). */ + 0x5740, /* idProduct. */ + 0x0200, /* bcdDevice. */ + 1, /* iManufacturer. */ + 2, /* iProduct. */ + 3, /* iSerialNumber. */ + 1) /* bNumConfigurations. */ +}; + +/* + * Device Descriptor wrapper. + */ +static const USBDescriptor vcom_device_descriptor = { + sizeof vcom_device_descriptor_data, + vcom_device_descriptor_data +}; + +/* Configuration Descriptor tree for a CDC.*/ +static const uint8_t vcom_configuration_descriptor_data[67] = { + /* Configuration Descriptor.*/ + USB_DESC_CONFIGURATION(67, /* wTotalLength. */ + 0x02, /* bNumInterfaces. */ + 0x01, /* bConfigurationValue. */ + 0, /* iConfiguration. */ + 0xC0, /* bmAttributes (self powered). */ + 50), /* bMaxPower (100mA). */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x01, /* bNumEndpoints. */ + 0x02, /* bInterfaceClass (Communications + Interface Class, CDC section + 4.2). */ + 0x02, /* bInterfaceSubClass (Abstract + Control Model, CDC section 4.3). */ + 0x01, /* bInterfaceProtocol (AT commands, + CDC section 4.4). */ + 0), /* iInterface. */ + /* Header Functional Descriptor (CDC section 5.2.3).*/ + USB_DESC_BYTE (5), /* bLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header + Functional Descriptor. */ + USB_DESC_BCD (0x0110), /* bcdCDC. */ + /* Call Management Functional Descriptor. */ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */ + USB_DESC_BYTE (0x01), /* bDataInterface. */ + /* ACM Functional Descriptor.*/ + USB_DESC_BYTE (4), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract + Control Management Descriptor). */ + USB_DESC_BYTE (0x02), /* bmCapabilities. */ + /* Union Functional Descriptor.*/ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bMasterInterface (Communication + Class Interface). */ + USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class + Interface). */ + /* Endpoint 2 Descriptor.*/ + USB_DESC_ENDPOINT (USBD2_INTERRUPT_REQUEST_EP|0x80, + 0x03, /* bmAttributes (Interrupt). */ + 0x0008, /* wMaxPacketSize. */ + 0xFF), /* bInterval. */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x02, /* bNumEndpoints. */ + 0x0A, /* bInterfaceClass (Data Class + Interface, CDC section 4.5). */ + 0x00, /* bInterfaceSubClass (CDC section + 4.6). */ + 0x00, /* bInterfaceProtocol (CDC section + 4.7). */ + 0x00), /* iInterface. */ + /* Endpoint 3 Descriptor.*/ + USB_DESC_ENDPOINT (USBD2_DATA_AVAILABLE_EP, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00), /* bInterval. */ + /* Endpoint 1 Descriptor.*/ + USB_DESC_ENDPOINT (USBD2_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00) /* bInterval. */ +}; + +/* + * Configuration Descriptor wrapper. + */ +static const USBDescriptor vcom_configuration_descriptor = { + sizeof vcom_configuration_descriptor_data, + vcom_configuration_descriptor_data +}; + +/* + * U.S. English language identifier. + */ +static const uint8_t vcom_string0[] = { + USB_DESC_BYTE(4), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */ +}; + + +// Vendor string +static const usb_string_vendor usb_vendor = { + sizeof(usb_vendor), + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), + USB_STRING_VENDOR +}; + + +// Device Description string +static const usb_string_device_description usb_device_description = { + sizeof(usb_device_description), + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), + USB_STRING_DEVICE_DESCRIPTION +}; + + +// Serial Number string. +static usb_string_serial_number usb_serial_number = { + sizeof(usb_serial_number), + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), + USB_STRING_SERIAL_NUMBER +}; + + +/* + * Strings wrappers array. + */ +static const USBDescriptor vcom_strings[] = { + {sizeof vcom_string0, vcom_string0}, + {sizeof usb_vendor, (uint8_t*)(&usb_vendor)}, + {sizeof usb_device_description, (uint8_t*)(&usb_device_description)}, + {sizeof usb_serial_number, (uint8_t*)(&usb_serial_number)}, +}; + + +// Convert Hex 32Bits value into char +// value: value to convert +// pbuf: pointer to the buffer +// len: buffer length +void IntToUnicode(uint32_t value , uint8_t *pbuf, uint8_t len) +{ + uint8_t idx = 0; + + for( idx = 0; idx < len; idx ++) + { + if( ((value >> 28)) < 0xA ) + { + pbuf[ 2* idx] = (value >> 28) + '0'; + } + else + { + pbuf[2* idx] = (value >> 28) + 'A' - 10; + } + + value = value << 4; + + pbuf[ 2* idx + 1] = 0; + } +} + +// Create the serial number string descriptor +void Get_SerialNum(uint8_t* pbuf) +{ + uint32_t deviceserial0, deviceserial1, deviceserial2; + + deviceserial0 = *(uint32_t*)DEVICE_ID1; + deviceserial1 = *(uint32_t*)DEVICE_ID2; + deviceserial2 = *(uint32_t*)DEVICE_ID3; + + deviceserial0 += deviceserial2; + + if (deviceserial0 != 0) + { + IntToUnicode(deviceserial0, pbuf, 8); + pbuf += 16; + IntToUnicode(deviceserial1, pbuf, 4); + } +} + +/* + * Handles the GET_DESCRIPTOR callback. All required descriptors must be + * handled here. + */ +static const USBDescriptor *get_descriptor(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang) { + + (void)usbp; + (void)lang; + + switch (dtype) { + case USB_DESCRIPTOR_DEVICE: + return &vcom_device_descriptor; + case USB_DESCRIPTOR_CONFIGURATION: + return &vcom_configuration_descriptor; + case USB_DESCRIPTOR_STRING: + if (dindex < 4) + { + if(dindex == 3) + { + // request is for serial number + // get it from the silicon unique ID + Get_SerialNum((uint8_t*)&usb_serial_number.bPropertyData[INDEX_OF_WCHAR_FOR_UNIQUE_ID]); + } + + return &vcom_strings[dindex]; + } + } + return NULL; +} + +/** + * @brief IN EP1 state. + */ +static USBInEndpointState ep1instate; + +/** + * @brief OUT EP1 state. + */ +static USBOutEndpointState ep1outstate; + +/** + * @brief EP1 initialization structure (both IN and OUT). + */ +static const USBEndpointConfig ep1config = { + USB_EP_MODE_TYPE_BULK, + NULL, + sduDataTransmitted, + sduDataReceived, + 0x0040, + 0x0040, + &ep1instate, + &ep1outstate, + 2, + NULL +}; + +/** + * @brief IN EP2 state. + */ +static USBInEndpointState ep2instate; + +/** + * @brief EP2 initialization structure (IN only). + */ +static const USBEndpointConfig ep2config = { + USB_EP_MODE_TYPE_INTR, + NULL, + sduInterruptTransmitted, + NULL, + 0x0010, + 0x0000, + &ep2instate, + NULL, + 1, + NULL +}; + +/* + * Handles the USB driver global events. + */ +static void usb_event(USBDriver *usbp, usbevent_t event) { + extern SerialUSBDriver SDU1; + + switch (event) { + case USB_EVENT_ADDRESS: + return; + case USB_EVENT_CONFIGURED: + chSysLockFromISR(); + + if (usbp->state == USB_ACTIVE) { + /* Enables the endpoints specified into the configuration. + Note, this callback is invoked from an ISR so I-Class functions + must be used.*/ + usbInitEndpointI(usbp, USBD2_DATA_REQUEST_EP, &ep1config); + usbInitEndpointI(usbp, USBD2_INTERRUPT_REQUEST_EP, &ep2config); + + /* Resetting the state of the CDC subsystem.*/ + sduConfigureHookI(&SDU1); + } + else if (usbp->state == USB_SELECTED) { + usbDisableEndpointsI(usbp); + } + + chSysUnlockFromISR(); + return; + case USB_EVENT_RESET: + /* Falls into.*/ + case USB_EVENT_UNCONFIGURED: + /* Falls into.*/ + case USB_EVENT_SUSPEND: + chSysLockFromISR(); + + /* Disconnection event on suspend.*/ + sduSuspendHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_WAKEUP: + chSysLockFromISR(); + + /* Disconnection event on suspend.*/ + sduWakeupHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_STALLED: + return; + } + return; +} + +/* + * Handling messages not implemented in the default handler nor in the + * SerialUSB handler. + */ +static bool requests_hook(USBDriver *usbp) { + + if (((usbp->setup[0] & USB_RTYPE_RECIPIENT_MASK) == USB_RTYPE_RECIPIENT_INTERFACE) && + (usbp->setup[1] == USB_REQ_SET_INTERFACE)) { + usbSetupTransfer(usbp, NULL, 0, NULL); + return true; + } + return sduRequestsHook(usbp); +} + +/* + * Handles the USB driver global events. + */ +static void sof_handler(USBDriver *usbp) { + + (void)usbp; + + osalSysLockFromISR(); + sduSOFHookI(&SDU1); + osalSysUnlockFromISR(); +} + +/* + * USB driver configuration. + */ +const USBConfig usbcfg = { + usb_event, + get_descriptor, + requests_hook, + sof_handler +}; + +/* + * Serial over USB driver configuration. + */ +const SerialUSBConfig serusbcfg = { + &USBD1, + USBD2_DATA_REQUEST_EP, + USBD2_DATA_AVAILABLE_EP, + USBD2_INTERRUPT_REQUEST_EP +}; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/common/usbcfg.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/common/usbcfg.h new file mode 100644 index 00000000..167e1df8 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/common/usbcfg.h @@ -0,0 +1,17 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef USBCFG_H +#define USBCFG_H + +extern const USBConfig usbcfg; +extern SerialUSBConfig serusbcfg; +extern SerialUSBDriver SDU1; + +#endif /* USBCFG_H */ + +/** @} */ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/managed_helpers/README.md b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/managed_helpers/README.md new file mode 100644 index 00000000..780b69ad --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/managed_helpers/README.md @@ -0,0 +1,5 @@ +## Managed code helpers + +This folder contains helper classes to make developers life easier when coding for this target board. + +* [Adc](ST_STM32F4_DISCOVERY.Adc.cs) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/managed_helpers/ST_STM32F4_DISCOVERY.Adc.cs b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/managed_helpers/ST_STM32F4_DISCOVERY.Adc.cs new file mode 100644 index 00000000..a2395660 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/managed_helpers/ST_STM32F4_DISCOVERY.Adc.cs @@ -0,0 +1,53 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +namespace nanoFramework.Targets.ST_STM32F4_DISCOVERY +{ + /// + /// Enumeration of ADC channels available on ST_STM32F4_DISCOVERY + /// + public static class AdcChannels + { + /// + /// Channel 0, connected to PC1 (ADC1 - IN11) + /// + public const int Channel_0 = 0; + + /// + /// Channel 1, connected to PC2 (ADC1 - IN12) + /// + public const int Channel_1 = 1; + + /// + /// Channel 2, connected to PA6 (ADC2 - IN6) + /// + public const int Channel_2 = 2; + + /// + /// Channel 3, connected to PA7 (ADC2 - IN7) + /// + public const int Channel_3 = 3; + + /// + /// Channel 4, connected to PB0 (ADC2 - IN8) + /// + public const int Channel_4 = 4; + + /// + /// Channel 5, internal temperature sensor, connected to ADC1 + /// + public const int Channel_TemperatureSensor = 5; + + /// + /// Channel 6, internal voltage reference, connected to ADC1 + /// + public const int Channel_VrefIn = 6; + + /// + /// Channel 7, connected to VBatt pin, ADC1 + /// + public const int Channel_Vbatt = 7; + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/CMakeLists.txt new file mode 100644 index 00000000..291f47e1 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/CMakeLists.txt @@ -0,0 +1,9 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# # append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/STM32F407xG_booter-DEBUG.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/STM32F407xG_booter-DEBUG.ld new file mode 100644 index 00000000..60fd44dd --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/STM32F407xG_booter-DEBUG.ld @@ -0,0 +1,80 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F407xG memory setup. + * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash : org = 0x08000000, len = 32k /* space reserved for nanoBooter (1st two sectors 0x08000000 to 0x08008000)*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */ + ram1 : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Stacks rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/STM32F407xG_booter.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/STM32F407xG_booter.ld new file mode 100644 index 00000000..eeaf96d0 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/STM32F407xG_booter.ld @@ -0,0 +1,80 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F407xG memory setup. + * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash : org = 0x08000000, len = 16k /* space reserved for nanoBooter (1st two sectors 0x08000000 to 0x08008000)*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */ + ram1 : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Stacks rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/chconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/chconf.h new file mode 100644 index 00000000..335e3fa4 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/chconf.h @@ -0,0 +1,616 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 1000 // this is 1 millisecond + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#define CH_CFG_INTERVALS_SIZE 32 + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_TIME_TYPES_SIZE 32 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES FALSE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS FALSE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT FALSE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES FALSE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_OBJ_FIFOS TRUE + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#define CH_CFG_USE_FACTORY FALSE + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 + +/** + * @brief Enables the registry of generic objects. + */ +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE + +/** + * @brief Enables factory for generic buffers. + */ +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE + +/** + * @brief Enables factory for semaphores. + */ +#define CH_CFG_FACTORY_SEMAPHORES TRUE + +/** + * @brief Enables factory for mailboxes. + */ +#define CH_CFG_FACTORY_MAILBOXES TRUE + +/** + * @brief Enables factory for objects FIFOs. + */ +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/halconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/halconf.h new file mode 100644 index 00000000..b970c22f --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/halconf.h @@ -0,0 +1,513 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/halconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/halconf_nf.h new file mode 100644 index 00000000..809a6cfa --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/halconf_nf.h @@ -0,0 +1,15 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +#endif // _HALCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/main.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/main.c new file mode 100644 index 00000000..c9085139 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/main.c @@ -0,0 +1,84 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); + +// Application entry point. +int main(void) { + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init SWO as soon as possible to make it available to output ASAP + #if (SWO_OUTPUT == TRUE) + SwoInit(); + #endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + osDelay(20); // Let init stabilize + + // the following IF is not mandatory, it's just providing a way for a user to 'force' + // the board to remain in nanoBooter and not launching nanoCLR + + // if the USER button (blue one) is pressed, skip the check for a valid CLR image and remain in booter + // the user button in this board has a pull-up resistor so the check has to be inverted + if (!palReadPad(GPIOA, GPIOA_BUTTON)) + { + // check for valid CLR image + // this target DOES NOT have configuration block, so we need to use the __nanoImage_end__ address here + if(CheckValidCLRImage((uint32_t)&__nanoImage_end__)) + { + // there seems to be a valid CLR image + // launch nanoCLR + LaunchCLR((uint32_t)&__nanoImage_end__); + } + } + + // Initializes a serial-over-USB CDC driver. + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + // Activates the USB driver and then the USB bus pull-up on D+. + // Note, a delay is inserted in order to not have to disconnect the cable after a reset. + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1500); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // Normal main() thread + while (true) { + palSetPad(GPIOD, GPIOD_LED3); + osDelay(500); + palClearPad(GPIOD, GPIOD_LED3); + osDelay(500); + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/mcuconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/mcuconf.h new file mode 100644 index 00000000..67f610b1 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/mcuconf.h @@ -0,0 +1,336 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF +#define STM32F407_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 4 +#define STM32_PLLN_VALUE 168 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV8 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 250 +#define STM32_SDC_READ_TIMEOUT_MS 25 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/mcuconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/mcuconf_nf.h new file mode 100644 index 00000000..574b9636 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/mcuconf_nf.h @@ -0,0 +1,10 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/target_board.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/target_board.h.in new file mode 100644 index 00000000..19531d9c --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoBooter/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOBOOTER_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/CMakeLists.txt b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/CMakeLists.txt new file mode 100644 index 00000000..e5496b7e --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/STM32F407xG_CLR-DEBUG.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/STM32F407xG_CLR-DEBUG.ld new file mode 100644 index 00000000..0e092d71 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/STM32F407xG_CLR-DEBUG.ld @@ -0,0 +1,76 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F407xG memory setup. + * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash : org = 0x08008000, len = 1M - 32k - 768k /* flash size less the space reserved for nanoBooter and application deployment*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x08040000, len = 768k /* space reserved for application deployment */ + ramvt : org = 0x20000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */ + ram1 : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram4); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +INCLUDE rules.ld \ No newline at end of file diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/STM32F407xG_CLR.ld b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/STM32F407xG_CLR.ld new file mode 100644 index 00000000..599abc4f --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/STM32F407xG_CLR.ld @@ -0,0 +1,76 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F407xG memory setup. + * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash : org = 0x08004000, len = 1M - 16k - 768k /* flash size less the space reserved for nanoBooter and application deployment*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x08040000, len = 768k /* space reserved for application deployment */ + ramvt : org = 0x20000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */ + ram1 : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram4); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +INCLUDE rules.ld \ No newline at end of file diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/chconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/chconf.h new file mode 100644 index 00000000..390ce3a6 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/chconf.h @@ -0,0 +1,616 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 10000 + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#define CH_CFG_INTERVALS_SIZE 32 + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_TIME_TYPES_SIZE 32 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_OBJ_FIFOS TRUE + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#define CH_CFG_USE_FACTORY FALSE + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 + +/** + * @brief Enables the registry of generic objects. + */ +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE + +/** + * @brief Enables factory for generic buffers. + */ +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE + +/** + * @brief Enables factory for semaphores. + */ +#define CH_CFG_FACTORY_SEMAPHORES TRUE + +/** + * @brief Enables factory for mailboxes. + */ +#define CH_CFG_FACTORY_MAILBOXES TRUE + +/** + * @brief Enables factory for objects FIFOs. + */ +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/halconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/halconf.h new file mode 100644 index 00000000..a1e2b875 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/halconf.h @@ -0,0 +1,525 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +// #define HAL_USE_ADC TRUE +// #endif + +/** + * @brief Enables the CAN subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +// #define HAL_USE_CAN FALSE +// #endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +// /** +// * @brief Enables the DAC subsystem. +// */ +// #if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +// #define HAL_USE_DAC FALSE +// #endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +// this option is set at target_platform.h (from config file) +//#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +//#define HAL_USE_I2C TRUE +//#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +// #define HAL_USE_MAC TRUE +// #endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +// #define HAL_USE_PWM TRUE +// #endif + +/** + * @brief Enables the RTC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +// #define HAL_USE_RTC TRUE +// #endif + +/** + * @brief Enables the SDC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +// #define HAL_USE_SDC FALSE +// #endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + + +/** + * @brief Enables the SPI subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +// #define HAL_USE_SPI FALSE +// #endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +// #define HAL_USE_UART FALSE +// #endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +// #define HAL_USE_WDG FALSE +// #endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS TRUE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/halconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/halconf_nf.h new file mode 100644 index 00000000..215ec4a8 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/halconf_nf.h @@ -0,0 +1,20 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +// enables STM32 Can driver +#if !defined(HAL_USE_STM32_CAN) +#define HAL_USE_STM32_CAN TRUE +#endif + +#endif // _HALCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/main.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/main.c new file mode 100644 index 00000000..a1738761 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/main.c @@ -0,0 +1,74 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include "usbcfg.h" +#include +#include +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); +// declare CLRStartup thread here +osThreadDef(CLRStartupThread, osPriorityNormal, 4096, "CLRStartupThread"); + +// Application entry point. +int main(void) { + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init SWO as soon as possible to make it available to output ASAP + #if (SWO_OUTPUT == TRUE) + SwoInit(); + #endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // start watchdog + Watchdog_Init(); + + // Initializes a serial-over-USB CDC driver. + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + // Activates the USB driver and then the USB bus pull-up on D+. + // Note, a delay is inserted in order to not have to disconnect the cable after a reset + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1500); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // CLR settings to launch CLR thread + CLR_SETTINGS clrSettings; + (void)memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.EnterDebuggerLoopAfterExit = true; + + // create the CLR Startup thread + osThreadCreate(osThread(CLRStartupThread), &clrSettings); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + while (true) { + osDelay(100); + } +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/mcuconf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/mcuconf.h new file mode 100644 index 00000000..10039241 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/mcuconf.h @@ -0,0 +1,336 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF +#define STM32F407_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 4 +#define STM32_PLLN_VALUE 168 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV8 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_USE_CAN2 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 TRUE +#define STM32_DAC_USE_DAC1_CH2 TRUE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 TRUE +#define STM32_PWM_USE_TIM8 TRUE +#define STM32_PWM_USE_TIM9 TRUE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 250 +#define STM32_SDC_READ_TIMEOUT_MS 25 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 TRUE +#define STM32_UART_USE_UART4 TRUE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG TRUE + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/mcuconf_nf.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/mcuconf_nf.h new file mode 100644 index 00000000..574b9636 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/mcuconf_nf.h @@ -0,0 +1,10 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/nanoHAL.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/nanoHAL.cpp new file mode 100644 index 00000000..076a50fc --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/nanoHAL.cpp @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +void HAL_EnterBooterMode() +{ +} + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/target_board.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/target_board.h.in new file mode 100644 index 00000000..b980bc05 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/nanoCLR/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOCLR_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/stm32f4_discovery.jpg b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/stm32f4_discovery.jpg new file mode 100644 index 00000000..a5d3ace0 Binary files /dev/null and b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/stm32f4_discovery.jpg differ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_BlockStorage.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_BlockStorage.c new file mode 100644 index 00000000..9e7c7f55 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_BlockStorage.c @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice STM32Flash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &STM32Flash_BlockStorageInterface, &Device_BlockStorageConfig, false); +} diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_BlockStorage.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_BlockStorage.h new file mode 100644 index 00000000..aa50b1b7 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_common.c b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_common.c new file mode 100644 index 00000000..c633da5b --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_common.c @@ -0,0 +1,24 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include "target_common.h" + +HAL_SYSTEM_CONFIG HalSystemConfig = +{ + { true }, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, //ConvertCOM_DebugHandle(1), + 0, //ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + { RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size }, + { FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size } +}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_common.h.in b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_common.h.in new file mode 100644 index 00000000..fd07d285 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_common.h.in @@ -0,0 +1,37 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x200000C0) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x00020000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x08000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00100000) + +///////////////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////// +#define TARGETNAMESTRING "@CHIBIOS_BOARD@" +#define PLATFORMNAMESTRING "STM32F4" +/////////////////////////////////////////////// + +#endif /* _TARGET_COMMON_H_ */ diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_nf_devices_can_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_nf_devices_can_config.cpp new file mode 100644 index 00000000..7dbe7ff1 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_nf_devices_can_config.cpp @@ -0,0 +1,44 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_nf_devices_can_config.h" +#include + +/////////// +// CAN1 // +/////////// + +// pin configuration for CAN1 +// port for TX pin is: GPIOB +// TX pin: is GPIOB_09 +// port for RX pin is: GPIOB +// RX pin: is GPIOB_08 +// GPIO alternate pin function is 9 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in STM32F405xx/STM32F407xx datasheet) +CAN_CONFIG_PINS(1, GPIOB, GPIOB, 9, 8, 9) + +// buffer +CANRxFrame Can1_MsgBuffer[CAN1_RX_BUFFER_SIZE]; + +// initialization for CAN1 +CAN_INIT(1, CAN1_RX_BUFFER_SIZE) + +/////////// +// CAN2 // +/////////// + +// pin configuration for CAN2 +// port for TX pin is: GPIOB +// TX pin: is GPIOB_06 +// port for RX pin is: GPIOB +// RX pin: is GPIOB_05 +// GPIO alternate pin function is 9 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in STM32F405xx/STM32F407xx datasheet) +CAN_CONFIG_PINS(2, GPIOB, GPIOB, 6, 5, 9) + +// buffer +CANRxFrame Can2_MsgBuffer[CAN2_RX_BUFFER_SIZE]; + +// initialization for CAN1 +CAN_INIT(2, CAN2_RX_BUFFER_SIZE) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_nf_devices_can_config.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_nf_devices_can_config.h new file mode 100644 index 00000000..adc8ace3 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_nf_devices_can_config.h @@ -0,0 +1,25 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +////////// +// CAN1 // +////////// + +// enable CAN1 +#define NF_CAN_STM32_CAN_USE_CAN1 TRUE + +// buffers size +#define CAN1_RX_BUFFER_SIZE 16 + +////////// +// CAN2 // +////////// + +// enable CAN2 +#define NF_CAN_STM32_CAN_USE_CAN2 TRUE + +// buffers size +#define CAN2_RX_BUFFER_SIZE 16 diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_nf_devices_onewire_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_nf_devices_onewire_config.cpp new file mode 100644 index 00000000..f56a636f --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_nf_devices_onewire_config.cpp @@ -0,0 +1,29 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_nf_devices_onewire_config.h" +#include + +/////////// +// UART4 // +/////////// + +// pin configuration for UART4 +// port for TX pin is: GPIOC +// TX pin: is GPIOC_10 +// GPIO alternate pin function is 8 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in STM32F405xx/STM32F407xx datasheet) +UART_CONFIG_PINS(4, GPIOC, 10, 8) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart4_TxBuffer[UART4_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart4_RxBuffer[UART4_RX_SIZE]; diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_nf_devices_onewire_config.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_nf_devices_onewire_config.h new file mode 100644 index 00000000..76f90a10 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_nf_devices_onewire_config.h @@ -0,0 +1,17 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////// +// UART4 // +/////////// + +// enable USART4 +#define NF_ONEWIRE_STM32_UART_USE_USART4 TRUE + +// buffers size +// tx buffer size: 32 bytes +#define UART4_TX_SIZE 32 +// rx buffer size: 32 bytes +#define UART4_RX_SIZE 32 \ No newline at end of file diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_system_devices_dac_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_system_devices_dac_config.cpp new file mode 100644 index 00000000..e3a0eee9 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_system_devices_dac_config.cpp @@ -0,0 +1,17 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_DAC_PORT_PIN_CHANNEL DacPortPinConfig[] = { + + // DAC1, channel 1, GPIO port A, pin 4 + {1, 1, GPIOA, 4}, + + // DAC1, channel 2, GPIO port A, pin 5 + {1, 2, GPIOA, 5}, +}; + +const int DacChannelCount = ARRAYSIZE(DacPortPinConfig); diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_windows_devices_adc_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_windows_devices_adc_config.cpp new file mode 100644 index 00000000..a4bea18d --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_windows_devices_adc_config.cpp @@ -0,0 +1,25 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_adc_native_target.h" + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // ADC1 + {1, GPIOC, 1, ADC_CHANNEL_IN11}, + {1, GPIOC, 2, ADC_CHANNEL_IN12}, + + // ADC2 + {2, GPIOA, 6, ADC_CHANNEL_IN6}, + {2, GPIOA, 7, ADC_CHANNEL_IN7}, + {2, GPIOB, 0, ADC_CHANNEL_IN8}, + + // these are the internal sources, available only at ADC1 + {1, NULL, 0, ADC_CHANNEL_SENSOR}, + {1, NULL, 0, ADC_CHANNEL_VREFINT}, + {1, NULL, 0, ADC_CHANNEL_VBAT}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_windows_devices_i2c_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_windows_devices_i2c_config.cpp new file mode 100644 index 00000000..2a60a22f --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_windows_devices_i2c_config.cpp @@ -0,0 +1,18 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_i2c_native_target.h" + +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for SCL pin is: GPIOB +// port for SDA pin is: GPIOB +// SCL pin: is GPIOB_8 +// SDA pin: is GPIOB_9 +// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, GPIOB, GPIOB, 8, 9, 4) diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_windows_devices_serialcommunication_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_windows_devices_serialcommunication_config.cpp new file mode 100644 index 00000000..309c05fb --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_windows_devices_serialcommunication_config.cpp @@ -0,0 +1,69 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_windows_devices_serialcommunication_config.h" +#include + +/////////// +// UART2 // +/////////// + +// pin configuration for UART2 +// port for TX pin is: GPIOA +// port for RX pin is: GPIOA +// TX pin: is GPIOA_2 +// RX pin: is GPIOA_3 +// GPIO alternate pin function is 7 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in STM32F405xx/STM32F407xx datasheet) +UART_CONFIG_PINS(2, GPIOA, GPIOA, 2, 3, 7) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart2_TxBuffer[UART2_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart2_RxBuffer[UART2_RX_SIZE]; + +// initialization for UART2 +UART_INIT(2, UART2_TX_SIZE, UART2_RX_SIZE) + +// un-initialization for UART2 +UART_UNINIT(2) + + +/////////// +// UART3 // +/////////// + +// pin configuration for UART3 +// port for TX pin is: GPIOD +// port for RX pin is: GPIOD +// TX pin: is GPIOD_8 +// RX pin: is GPIOD_9 +// GPIO alternate pin function is 7 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in STM32F405xx/STM32F407xx datasheet) +UART_CONFIG_PINS(3, GPIOD, GPIOD, 8, 9, 7) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart3_TxBuffer[UART3_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart3_RxBuffer[UART3_RX_SIZE]; + +// initialization for UART3 +UART_INIT(3, UART3_TX_SIZE, UART3_RX_SIZE) + +// un-initialization for UART3 +UART_UNINIT(3) + diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_windows_devices_serialcommunication_config.h b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_windows_devices_serialcommunication_config.h new file mode 100644 index 00000000..d0dad6c0 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_windows_devices_serialcommunication_config.h @@ -0,0 +1,31 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////// +// UART2 // +/////////// + +// enable USART2 +#define NF_SERIAL_COMM_STM32_UART_USE_USART2 TRUE + +// buffers size +// tx buffer size: 256 bytes +#define UART2_TX_SIZE 256 +// rx buffer size: 256 bytes +#define UART2_RX_SIZE 256 + + +/////////// +// UART3 // +/////////// + +// enable USART3 +#define NF_SERIAL_COMM_STM32_UART_USE_USART3 TRUE + +// buffers size +// tx buffer size: 256 bytes +#define UART3_TX_SIZE 256 +// rx buffer size: 256 bytes +#define UART3_RX_SIZE 256 diff --git a/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_windows_devices_spi_config.cpp b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_windows_devices_spi_config.cpp new file mode 100644 index 00000000..ef2d3a10 --- /dev/null +++ b/source/native/nf-interpreter/targets-community/CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY/target_windows_devices_spi_config.cpp @@ -0,0 +1,10 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_spi_native.h" + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets-community/LICENSE b/source/native/nf-interpreter/targets-community/LICENSE new file mode 100644 index 00000000..8dada3ed --- /dev/null +++ b/source/native/nf-interpreter/targets-community/LICENSE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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We also recommend that a + file or class name and description of purpose be included on the + same "printed page" as the copyright notice for easier + identification within third-party archives. + + Copyright {yyyy} {name of copyright owner} + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. diff --git a/source/native/nf-interpreter/targets-community/README.md b/source/native/nf-interpreter/targets-community/README.md new file mode 100644 index 00000000..86125a6b --- /dev/null +++ b/source/native/nf-interpreter/targets-community/README.md @@ -0,0 +1,62 @@ +[![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0) [![Discord](https://img.shields.io/discord/478725473862549535.svg)](https://discord.gg/gCyBu8T) [![Build Status](https://dev.azure.com/nanoframework/Community-Targets/_apis/build/status/nanoframework.nf-Community-Targets)](https://dev.azure.com/nanoframework/Community-Targets/_build/latest?definitionId=4) + +![nanoFramework logo](https://github.com/nanoframework/Home/blob/master/resources/logo/nanoFramework-repo-logo.png) + +----- + +### Welcome to the **nanoFramework** community targets repository! + +This repository contains target boards for the **nanoFramework**, provided and maintained by community members. + +The provided boards are **NOT** supported by the **nanoFramework** team and any issues must be communicated with the contributor that _owns_ it. + +## Available community boards + +| Target name | Firmware Images | MCU | Frequency | FLASH | RAM | +|:-:|:-:|:-:|:-:|:-:|:-:| +| [GHI FEZ CERB40-I](CMSIS-OS/ChibiOS/GHI_FEZ_CERB40_NF) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/GHI_FEZ_CERB40_NF/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/GHI_FEZ_CERB40_NF/_latestVersion) | STM32F405RG | 168 MHz | 1024 KB | 192 KB | +| [IngenuityMicro Electron](CMSIS-OS/ChibiOS/I2M_ELECTRON_NF) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/I2M_ELECTRON_NF/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/I2M_ELECTRON_NF/_latestVersion) | STM32F411CE | 100 MHz | 512 KB | 128 KB | +| [IngenuityMicro Oxygen](CMSIS-OS/ChibiOS/I2M_OXYGEN_NF) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/I2M_OXYGEN_NF/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/I2M_OXYGEN_NF/_latestVersion) | STM32F411CE | 100 MHz | 512 KB | 128 KB | +| [ST Nucleo64 F401RE](CMSIS-OS/ChibiOS/ST_NUCLEO64_F401RE_NF) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/ST_NUCLEO64_F401RE_NF/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/ST_NUCLEO64_F401RE_NF/_latestVersion) | STM32F401RE | 84 MHz | 512 KB | 96 KB | +| [ST Nucleo64 F411RE](CMSIS-OS/ChibiOS/ST_NUCLEO64_F411RE_NF) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/ST_NUCLEO64_F411RE_NF/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/ST_NUCLEO64_F411RE_NF/_latestVersion) | STM32F411RE | 100 MHz | 512 KB | 128 KB | +| [ST Nucleo144 F412ZG](CMSIS-OS/ChibiOS/ST_NUCLEO144_F412ZG_NF) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/ST_NUCLEO144_F412ZG_NF/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/ST_NUCLEO144_F412ZG_NF/_latestVersion) | STM32F412ZG | 100 MHz | 1024 KB | 256 KB | +| [ST Nucleo144 F746ZG](CMSIS-OS/ChibiOS/ST_NUCLEO144_F746ZG) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/ST_NUCLEO144_F746ZG/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/ST_NUCLEO144_F746ZG/_latestVersion) | STM32F746ZG | 216 MHz | 1024 KB | 320 KB | +| [ST STM32F4DISCO](CMSIS-OS/ChibiOS/ST_STM32F4_DISCOVERY) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/ST_STM32F4_DISCOVERY/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/ST_STM32F4_DISCOVERY/_latestVersion) | STM32F407VGT6 | 168 MHz | 1024 KB | 192 KB | +| [ST Nucleo144 F439ZI](CMSIS-OS/ChibiOS/ST_NUCLEO144_F439ZI) | [ ![Download](https://api.bintray.com/packages/nfbot/nanoframework-images-community-targets/ST_NUCLEO144_F439ZI/images/download.svg) ](https://bintray.com/nfbot/nanoframework-images-community-targets/ST_NUCLEO144_F439ZI/_latestVersion) | STM32F439ZI | 180 MHz | 2048 KB | 256 KB | + +The above firmware builds include support for the class libraries and features marked below. + +| Target | Gpio | Spi | I2c | Pwm | Adc | Serial | OneWire | CAN | Events | SWO | Networking | Large Heap | +|:-:|:-:|:-:|:-:|:-:|:-:|:-:|:-:|:-:|:-:|:-:|:-:|:-:| +| GHI FEZ CERB40-I | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: |:heavy_check_mark: | | | :heavy_check_mark: | | | | +| IngenuityMicro Electron | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | | | | | +| IngenuityMicro Oxygen | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | :heavy_check_mark: | | | | +| ST Nucleo64 F401RE | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: | | | +| ST Nucleo64 F411RE | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | :heavy_check_mark: | :heavy_check_mark: | | | +| ST Nucleo144 F412ZG | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | :heavy_check_mark: | :heavy_check_mark: | | | +| ST Nucleo144 F746ZG | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | +| ST STM32F4DISCO | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | +| ST Nucleo144 F439ZI | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | | :heavy_check_mark: | :heavy_check_mark: | :heavy_check_mark: | | + +## Feedback and documentation + +For documentation, providing feedback, issues and finding out how to contribute please refer to the [Home repo](https://github.com/nanoframework/Home). + +When you need to discuss something specific about a community target start by doing so in the _support:community-targets_ channel in our Discord community or reach out directly to the target _owner_. + +Join our Discord community [here](https://discord.gg/gCyBu8T). + +## Credits + +The list of contributors to this project can be found at [CONTRIBUTORS](https://github.com/nanoframework/Home/blob/master/CONTRIBUTORS.md). + +The individual targets are _owned_ by the contributor and credit is due to the creator of the community board. + +## License + +The community target contributions are licensed under the [Apache 2.0 license](http://www.apache.org/licenses/LICENSE-2.0). + +## Code of Conduct + +This project has adopted the code of conduct defined by the [Contributor Covenant](http://contributor-covenant.org/) +to clarify expected behavior in our community. diff --git a/source/native/nf-interpreter/targets-community/azure-pipelines-templates/clone-nf-interpreter-repo.yml b/source/native/nf-interpreter/targets-community/azure-pipelines-templates/clone-nf-interpreter-repo.yml new file mode 100644 index 00000000..411246ef --- /dev/null +++ b/source/native/nf-interpreter/targets-community/azure-pipelines-templates/clone-nf-interpreter-repo.yml @@ -0,0 +1,20 @@ +# Copyright (c) 2018 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. + +steps: + # clone nf-interpreter repo to launch the build + - task: PowerShell@2 + inputs: + targetType: 'inline' + script: git clone https://github.com/nanoframework/nf-interpreter.git -b develop nf-interpreter --depth 1 -q + errorActionPreference: 'stop' + displayName: Clone nf-interpreter repo + + # Copy target files to nf-interpreter folder + - task: CopyFiles@2 + inputs: + sourceFolder: $(Build.SourcesDirectory)\CMSIS-OS + targetFolder: $(Build.SourcesDirectory)\nf-interpreter\targets-community\CMSIS-OS + cleanTargetFolder: false + overWrite: true + displayName: Copy community target to nf-interpreter diff --git a/source/native/nf-interpreter/targets-community/azure-pipelines-templates/set-build-version.yml b/source/native/nf-interpreter/targets-community/azure-pipelines-templates/set-build-version.yml new file mode 100644 index 00000000..c964eace --- /dev/null +++ b/source/native/nf-interpreter/targets-community/azure-pipelines-templates/set-build-version.yml @@ -0,0 +1,24 @@ +# Copyright (c) 2018 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. + +steps: + # compute build version + - task: PowerShell@2 + inputs: + targetType: 'inline' + script: | + $counter = $env:REVISION + $version = [int]$counter + + $buildSimpleVersion = "1.1." + $version.ToString() + $buildFullVersion = $buildSimpleVersion + ".0" + + Write-Host ">>$buildFullVersion<<" + + # need to hijack NBGV variable that is expected in the build CMake command and others that follow + Write-Host "$("##vso[task.setvariable variable=NBGV_Version]")$buildFullVersion" + Write-Host "$("##vso[task.setvariable variable=NBGV_SimpleVersion]")$buildSimpleVersion" + Write-Host "$("##vso[task.setvariable variable=NBGV_PrereleaseVersion]").0" + + condition: succeeded() + displayName: compute the build version diff --git a/source/native/nf-interpreter/targets-community/azure-pipelines.yml b/source/native/nf-interpreter/targets-community/azure-pipelines.yml new file mode 100644 index 00000000..b9ce8bad --- /dev/null +++ b/source/native/nf-interpreter/targets-community/azure-pipelines.yml @@ -0,0 +1,552 @@ +# Copyright (c) 2018 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. + +trigger: + branches: + include: + - master + paths: + exclude: + - /*.md + - .gitignore + +pr: + branches: + include: + - master + autoCancel: true + +schedules: +- cron: "50 23 * * *" + branches: + include: + - master + always: true + displayName: Daily build at 23:50 + +# add nf-tools repo to resources (for Azure Pipelines templates) +# add nf-interpreter repo to resources (for Azure Pipelines templates) +resources: + repositories: + - repository: templates + type: github + name: nanoframework/nf-tools + endpoint: nanoframework + - repository: templatesBuild + type: github + name: nanoframework/nf-interpreter + ref: refs/heads/develop + endpoint: nanoframework + +variables: + GNU_GCC_TOOLCHAIN_PATH: $(Agent.TempDirectory)\GNU_Tools_ARM_Embedded + +jobs: + +############################## +- job: Check_Build_Options + pool: + vmImage: 'VS2017-Win2016' + + steps: + - checkout: self + fetchDepth: 1 + + - powershell: | + + # get commit date, if this is NOT a PR + if($env:Build_SourceBranch -like "refs/pull*") + { + # this is a PR: always build + echo "##vso[task.setvariable variable=GO;isOutput=true]true" + } + else + { + # clone nf-interpreter + git clone https://github.com/nanoframework/nf-interpreter.git -b develop nf-interpreter --depth 1 -q + cd "nf-interpreter" > $null + + $commitDate = git show -s --format=%cd --date=short + $commitDate = [DateTime]$commitDate + + if($commitDate -eq [System.DateTime]::UtcNow.Date) + { + # last commit from nf-interpreter is from today, build images + echo "##vso[task.setvariable variable=GO;isOutput=true]true" + } + else + { + # last commit from nf-interpreter is older than today, skip build + + "**********************************************************************" | Write-Host + "* Last commit from nf-interpreter is older than today, skiping build *" | Write-Host + "**********************************************************************" | Write-Host + + echo "##vso[task.setvariable variable=GO;isOutput=true]false" + } + } + + name: BuildOptions + displayName: Evaluate build options + +############################## +- job: Get_Commit_Message + condition: eq( dependencies.Check_Build_Options.outputs['BuildOptions.GO'], true ) + pool: + vmImage: 'VS2017-Win2016' + + dependsOn: + - Check_Build_Options + + steps: + - checkout: self + fetchDepth: 1 + + # get commint message + - powershell: | + + if($env:Build_SourceBranch -like "refs/pull*") + { + # PR build, get PR message + + # need to get PR number from branch as the Azure Pipeline var can't be trusted + if($env:Build_SourceBranch -match '(?<=(pull\/))\w*(?=(\/))') + { + $prNumber = $matches[0] + + $prUrl = "https://api.github.com/repos/$env:Build_Repository_Name/pulls/$prNumber" + + $commit = Invoke-RestMethod -Uri $prUrl -ContentType "application/json" -Method GET + + $commitMessage = $commit.body + } + } + else + { + # not a PR, get subject and commit message for commit + $commitMessage = git log --format='%B' -1 + } + + # need to flatten message by removing new lines + $commitMessage = $commitMessage -replace "`r`n", " " + + # set variable to foward to jobs + echo "##vso[task.setvariable variable=COMMIT_MESSAGE;isOutput=true]$commitMessage" + name: getCommitMessage + displayName: grab commit message + +############################## +- job: Build_GHI_FEZ_CERB40_NF + condition: and( or( contains(dependencies.Get_Commit_Message.outputs['getCommitMessage.COMMIT_MESSAGE'], '***GHI_FEZ_CERB40_NF***'), contains(dependencies.Get_Commit_Message.outputs['getCommitMessage.COMMIT_MESSAGE'], '***ALL***'), eq(variables['BUILD_ALL'], 'true') ), eq( dependencies.Check_Build_Options.outputs['BuildOptions.GO'], true ) ) + + dependsOn: + - Get_Commit_Message + - Check_Build_Options + + pool: + vmImage: 'VS2017-Win2016' + + variables: + BoardName: GHI_FEZ_CERB40_NF + BuildOptions: -DTARGET_SERIES=STM32F4xx -DNF_FEATURE_DEBUGGER=ON -DNF_FEATURE_RTC=ON -DAPI_Windows.Devices.Gpio=ON -DAPI_Windows.Devices.Spi=ON -DAPI_Windows.Devices.I2c=ON -DAPI_Windows.Devices.Pwm=ON -DAPI_Windows.Devices.SerialCommunication=ON -DAPI_Windows.Devices.Adc=ON + # creates a counter and assigns it to the revision variable + REVISION: $[counter('GHI_FEZ_CERB40_NF_versioncounter', 3)] + GccArm_Version: + NeedsDFU: true + + steps: + - checkout: self + fetchDepth: 1 + + - template: azure-pipelines-templates/set-build-version.yml + + - template: azure-pipelines-templates/clone-nf-interpreter-repo.yml + + - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml@templatesBuild + + - template: azure-pipelines-templates/download-install-ninja.yml@templatesBuild + + - template: azure-pipelines-templates/download-hexdfu.yml@templatesBuild + + - template: azure-pipelines-templates/build-chibios-stm32.yml@templatesBuild + parameters: + buildDirectory: $(Build.SourcesDirectory)\nf-interpreter\build + + - template: azure-pipelines-templates/pack-publish-artifacts.yml@templatesBuild + parameters: + buildDirectory: $(Build.SourcesDirectory)\nf-interpreter\build + + - template: azure-pipelines-templates/publish-bintray.yml@templatesBuild + +############################## +- job: Build_I2M_ELECTRON_NF + condition: and( or( contains(dependencies.Get_Commit_Message.outputs['getCommitMessage.COMMIT_MESSAGE'], '***I2M_ELECTRON_NF***'), contains(dependencies.Get_Commit_Message.outputs['getCommitMessage.COMMIT_MESSAGE'], '***ALL***'), eq(variables['BUILD_ALL'], 'true') ), eq( dependencies.Check_Build_Options.outputs['BuildOptions.GO'], true ) ) + + dependsOn: + - Get_Commit_Message + - Check_Build_Options + + pool: + vmImage: 'VS2017-Win2016' + + variables: + BoardName: I2M_ELECTRON_NF + BuildOptions: -DTARGET_SERIES=STM32F4xx -DNF_FEATURE_DEBUGGER=ON -DUSE_RNG=OFF -DNF_FEATURE_RTC=ON -DAPI_Windows.Devices.Gpio=ON -DAPI_Windows.Devices.Spi=ON -DAPI_Windows.Devices.I2c=ON -DAPI_Windows.Devices.Pwm=ON -DAPI_Windows.Devices.SerialCommunication=ON -DAPI_Windows.Devices.Adc=ON + # creates a counter and assigns it to the revision variable + REVISION: $[counter('I2M_ELECTRON_NF_versioncounter', 3)] + GccArm_Version: + NeedsDFU: true + + steps: + - checkout: self + fetchDepth: 1 + + - template: azure-pipelines-templates/set-build-version.yml + + - template: azure-pipelines-templates/clone-nf-interpreter-repo.yml + + - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml@templatesBuild + + - template: azure-pipelines-templates/download-install-ninja.yml@templatesBuild + + - template: azure-pipelines-templates/download-hexdfu.yml@templatesBuild + + - template: azure-pipelines-templates/build-chibios-stm32.yml@templatesBuild + parameters: + buildDirectory: $(Build.SourcesDirectory)\nf-interpreter\build + + - template: azure-pipelines-templates/pack-publish-artifacts.yml@templatesBuild + parameters: + buildDirectory: $(Build.SourcesDirectory)\nf-interpreter\build + + - template: azure-pipelines-templates/publish-bintray.yml@templatesBuild + +############################## +- job: Build_I2M_OXYGEN_NF + condition: and( or( contains(dependencies.Get_Commit_Message.outputs['getCommitMessage.COMMIT_MESSAGE'], '***I2M_OXYGEN_NF***'), contains(dependencies.Get_Commit_Message.outputs['getCommitMessage.COMMIT_MESSAGE'], '***ALL***'), eq(variables['BUILD_ALL'], 'true') ), eq( dependencies.Check_Build_Options.outputs['BuildOptions.GO'], true ) ) + + dependsOn: + - Get_Commit_Message + - Check_Build_Options + + pool: + vmImage: 'VS2017-Win2016' + + variables: + BoardName: I2M_OXYGEN_NF + BuildOptions: -DTARGET_SERIES=STM32F4xx -DNF_FEATURE_DEBUGGER=ON -DUSE_RNG=OFF -DNF_FEATURE_RTC=ON -DAPI_Windows.Devices.Gpio=ON -DAPI_Windows.Devices.Spi=ON -DAPI_Windows.Devices.I2c=ON -DAPI_Windows.Devices.Pwm=ON -DAPI_Windows.Devices.SerialCommunication=ON -DAPI_Windows.Devices.Adc=ON + # creates a counter and assigns it to the revision variable + REVISION: $[counter('I2M_OXYGEN_NF_versioncounter', 3)] + GccArm_Version: + NeedsDFU: true + + steps: + - checkout: self + fetchDepth: 1 + + - template: azure-pipelines-templates/set-build-version.yml + + - template: azure-pipelines-templates/clone-nf-interpreter-repo.yml + + - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml@templatesBuild + + - template: azure-pipelines-templates/download-install-ninja.yml@templatesBuild + + - template: azure-pipelines-templates/download-hexdfu.yml@templatesBuild + + - template: azure-pipelines-templates/build-chibios-stm32.yml@templatesBuild + parameters: + buildDirectory: $(Build.SourcesDirectory)\nf-interpreter\build + + - template: azure-pipelines-templates/pack-publish-artifacts.yml@templatesBuild + parameters: + buildDirectory: $(Build.SourcesDirectory)\nf-interpreter\build + + - template: azure-pipelines-templates/publish-bintray.yml@templatesBuild + +############################## +- job: Build_ST_NUCLEO64_F401RE_NF + condition: and( or( contains(dependencies.Get_Commit_Message.outputs['getCommitMessage.COMMIT_MESSAGE'], '***ST_NUCLEO64_F401RE_NF***'), contains(dependencies.Get_Commit_Message.outputs['getCommitMessage.COMMIT_MESSAGE'], '***ALL***'), eq(variables['BUILD_ALL'], 'true') ), eq( dependencies.Check_Build_Options.outputs['BuildOptions.GO'], true ) ) + + dependsOn: + - Get_Commit_Message + - Check_Build_Options + + pool: + vmImage: 'VS2017-Win2016' + + variables: + BoardName: ST_NUCLEO64_F401RE_NF + BuildOptions: -DTARGET_SERIES=STM32F4xx -DNF_FEATURE_DEBUGGER=ON -DUSE_RNG=OFF -DSWO_OUTPUT=ON -DNF_FEATURE_RTC=ON -DAPI_Windows.Devices.Gpio=ON -DAPI_Windows.Devices.Spi=ON -DAPI_Windows.Devices.I2c=ON -DAPI_Windows.Devices.Pwm=ON -DAPI_Windows.Devices.SerialCommunication=ON -DAPI_Windows.Devices.Adc=ON -DAPI_nanoFramework.Devices.OneWire=ON + # creates a counter and assigns it to the revision variable + REVISION: $[counter('ST_NUCLEO64_F401RE_NF_versioncounter', 3)] + GccArm_Version: + NeedsDFU: false + + steps: + - checkout: self + fetchDepth: 1 + + - template: azure-pipelines-templates/set-build-version.yml + + - template: azure-pipelines-templates/clone-nf-interpreter-repo.yml + + - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml@templatesBuild + + - template: azure-pipelines-templates/download-install-ninja.yml@templatesBuild + + - template: azure-pipelines-templates/download-hexdfu.yml@templatesBuild + + - template: azure-pipelines-templates/build-chibios-stm32.yml@templatesBuild + parameters: + buildDirectory: $(Build.SourcesDirectory)\nf-interpreter\build + + - template: azure-pipelines-templates/pack-publish-artifacts.yml@templatesBuild + parameters: + buildDirectory: $(Build.SourcesDirectory)\nf-interpreter\build + + - template: azure-pipelines-templates/publish-bintray.yml@templatesBuild + +############################## +- job: Build_ST_NUCLEO64_F411RE_NF + condition: and( or( contains(dependencies.Get_Commit_Message.outputs['getCommitMessage.COMMIT_MESSAGE'], '***ST_NUCLEO64_F411RE_NF***'), contains(dependencies.Get_Commit_Message.outputs['getCommitMessage.COMMIT_MESSAGE'], '***ALL***'), eq(variables['BUILD_ALL'], 'true') ), eq( dependencies.Check_Build_Options.outputs['BuildOptions.GO'], true ) ) + + dependsOn: + - Get_Commit_Message + - Check_Build_Options + + pool: + vmImage: 'VS2017-Win2016' + + variables: + BoardName: ST_NUCLEO64_F411RE_NF + BuildOptions: -DTARGET_SERIES=STM32F4xx -DNF_FEATURE_DEBUGGER=ON -DUSE_RNG=OFF -DSWO_OUTPUT=ON -DNF_FEATURE_RTC=ON -DAPI_Windows.Devices.Gpio=ON -DAPI_Windows.Devices.Spi=ON -DAPI_Windows.Devices.I2c=ON -DAPI_Windows.Devices.Pwm=ON -DAPI_Windows.Devices.SerialCommunication=ON -DAPI_Windows.Devices.Adc=ON + # creates a counter and assigns it to the revision variable + REVISION: $[counter('ST_NUCLEO64_F411RE_NF_versioncounter', 3)] + GccArm_Version: + NeedsDFU: false + + steps: + - checkout: self + fetchDepth: 1 + + - template: azure-pipelines-templates/set-build-version.yml + + - template: azure-pipelines-templates/clone-nf-interpreter-repo.yml + + - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml@templatesBuild + + - template: azure-pipelines-templates/download-install-ninja.yml@templatesBuild + + - template: azure-pipelines-templates/download-hexdfu.yml@templatesBuild + + - template: azure-pipelines-templates/build-chibios-stm32.yml@templatesBuild + parameters: + buildDirectory: $(Build.SourcesDirectory)\nf-interpreter\build + + - template: azure-pipelines-templates/pack-publish-artifacts.yml@templatesBuild + parameters: + buildDirectory: $(Build.SourcesDirectory)\nf-interpreter\build + + - template: azure-pipelines-templates/publish-bintray.yml@templatesBuild + +############################## +- job: Build_ST_NUCLEO144_F412ZG_NF + condition: and( or( contains(dependencies.Get_Commit_Message.outputs['getCommitMessage.COMMIT_MESSAGE'], '***ST_NUCLEO144_F412ZG_NF***'), contains(dependencies.Get_Commit_Message.outputs['getCommitMessage.COMMIT_MESSAGE'], '***ALL***'), eq(variables['BUILD_ALL'], 'true') ), eq( dependencies.Check_Build_Options.outputs['BuildOptions.GO'], true ) ) + + dependsOn: + - Get_Commit_Message + - Check_Build_Options + + pool: + vmImage: 'VS2017-Win2016' + + variables: + BoardName: ST_NUCLEO144_F412ZG_NF + BuildOptions: -DTARGET_SERIES=STM32F4xx -DNF_FEATURE_DEBUGGER=ON -DSWO_OUTPUT=ON -DNF_FEATURE_RTC=ON -DAPI_Windows.Devices.Gpio=ON -DAPI_Windows.Devices.Spi=ON -DAPI_Windows.Devices.I2c=ON -DAPI_Windows.Devices.Pwm=ON -DAPI_Windows.Devices.SerialCommunication=OFF -DAPI_Windows.Devices.Adc=ON + # creates a counter and assigns it to the revision variable + REVISION: $[counter('ST_NUCLEO144_F412ZG_NF_versioncounter', 3)] + GccArm_Version: + NeedsDFU: false + + steps: + - checkout: self + fetchDepth: 1 + + - template: azure-pipelines-templates/set-build-version.yml + + - template: azure-pipelines-templates/clone-nf-interpreter-repo.yml + + - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml@templatesBuild + + - template: azure-pipelines-templates/download-install-ninja.yml@templatesBuild + + - template: azure-pipelines-templates/download-hexdfu.yml@templatesBuild + + - template: azure-pipelines-templates/build-chibios-stm32.yml@templatesBuild + parameters: + buildDirectory: $(Build.SourcesDirectory)\nf-interpreter\build + + - template: azure-pipelines-templates/pack-publish-artifacts.yml@templatesBuild + parameters: + buildDirectory: $(Build.SourcesDirectory)\nf-interpreter\build + + - template: azure-pipelines-templates/publish-bintray.yml@templatesBuild + +############################## +- job: Build_ST_NUCLEO144_F746ZG + condition: and( or( contains(dependencies.Get_Commit_Message.outputs['getCommitMessage.COMMIT_MESSAGE'], '***ST_NUCLEO144_F746ZG***'), contains(dependencies.Get_Commit_Message.outputs['getCommitMessage.COMMIT_MESSAGE'], '***ALL***'), eq(variables['BUILD_ALL'], 'true') ), eq( dependencies.Check_Build_Options.outputs['BuildOptions.GO'], true ) ) + + dependsOn: + - Get_Commit_Message + - Check_Build_Options + + pool: + vmImage: 'VS2017-Win2016' + + variables: + BoardName: ST_NUCLEO144_F746ZG + BuildOptions: -DTARGET_SERIES=STM32F7xx -DRTOS=CHIBIOS -DNF_FEATURE_DEBUGGER=ON -DSWO_OUTPUT=ON -DNF_FEATURE_RTC=ON -DNF_FEATURE_HAS_CONFIG_BLOCK=ON -DAPI_System.Math=ON -DAPI_Hardware.Stm32=ON -DAPI_Windows.Devices.Gpio=ON -DAPI_Windows.Devices.Spi=ON -DAPI_Windows.Devices.I2c=ON -DAPI_Windows.Devices.Pwm=ON -DAPI_Windows.Devices.SerialCommunication=ON -DAPI_Windows.Devices.Adc=ON -DAPI_System.Net=ON -DNF_SECURITY_MBEDTLS=ON -DAPI_nanoFramework.Devices.OneWire=ON + # creates a counter and assigns it to the revision variable + REVISION: $[counter('ST_NUCLEO144_F746ZG_versioncounter', 3)] + GccArm_Version: + NeedsDFU: false + + steps: + - checkout: self + fetchDepth: 1 + + - template: azure-pipelines-templates/set-build-version.yml + + - template: azure-pipelines-templates/clone-nf-interpreter-repo.yml + + - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml@templatesBuild + + - template: azure-pipelines-templates/download-install-ninja.yml@templatesBuild + + - template: azure-pipelines-templates/download-hexdfu.yml@templatesBuild + + - template: azure-pipelines-templates/build-chibios-stm32.yml@templatesBuild + parameters: + buildDirectory: $(Build.SourcesDirectory)\nf-interpreter\build + + - template: azure-pipelines-templates/pack-publish-artifacts.yml@templatesBuild + parameters: + buildDirectory: $(Build.SourcesDirectory)\nf-interpreter\build + + - template: azure-pipelines-templates/publish-bintray.yml@templatesBuild + +############################## +- job: Build_ST_STM32F4_DISCOVERY + condition: and( or( contains(dependencies.Get_Commit_Message.outputs['getCommitMessage.COMMIT_MESSAGE'], '***ST_STM32F4_DISCOVERY***'), contains(dependencies.Get_Commit_Message.outputs['getCommitMessage.COMMIT_MESSAGE'], '***ALL***'), eq(variables['BUILD_ALL'], 'true') ), eq( dependencies.Check_Build_Options.outputs['BuildOptions.GO'], true ) ) + + dependsOn: + - Get_Commit_Message + - Check_Build_Options + + pool: + vmImage: 'VS2017-Win2016' + + variables: + BoardName: ST_STM32F4_DISCOVERY + BuildOptions: -DTARGET_SERIES=STM32F4xx -DRTOS=CHIBIOS -DSUPPORT_ANY_BASE_CONVERSION=ON -DNF_FEATURE_DEBUGGER=ON -DSWO_OUTPUT=ON -DNF_FEATURE_RTC=ON -DAPI_System.Math=ON -DAPI_Hardware.Stm32=ON -DAPI_Windows.Devices.Gpio=ON -DAPI_Windows.Devices.Spi=ON -DAPI_Windows.Devices.I2c=ON -DAPI_Windows.Devices.Pwm=ON -DAPI_Windows.Devices.SerialCommunication=ON -DAPI_Windows.Devices.Adc=ON -DAPI_nanoFramework.Devices.OneWire=ON -DAPI_nanoFramework.Devices.Can=ON + # creates a counter and assigns it to the revision variable + REVISION: $[counter('ST_STM32F4_DISCOVERY_versioncounter', 3)] + GccArm_Version: + NeedsDFU: false + + steps: + - checkout: self + fetchDepth: 1 + + - template: azure-pipelines-templates/set-build-version.yml + + - template: azure-pipelines-templates/clone-nf-interpreter-repo.yml + + - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml@templatesBuild + + - template: azure-pipelines-templates/download-install-ninja.yml@templatesBuild + + - template: azure-pipelines-templates/download-hexdfu.yml@templatesBuild + + - template: azure-pipelines-templates/build-chibios-stm32.yml@templatesBuild + parameters: + buildDirectory: $(Build.SourcesDirectory)\nf-interpreter\build + + - template: azure-pipelines-templates/pack-publish-artifacts.yml@templatesBuild + parameters: + buildDirectory: $(Build.SourcesDirectory)\nf-interpreter\build + + - template: azure-pipelines-templates/publish-bintray.yml@templatesBuild + +############################## +- job: Build_ST_NUCLEO144_F439ZI + condition: and( or( contains(dependencies.Get_Commit_Message.outputs['getCommitMessage.COMMIT_MESSAGE'], '***ST_NUCLEO144_F439ZI***'), contains(dependencies.Get_Commit_Message.outputs['getCommitMessage.COMMIT_MESSAGE'], '***ALL***'), eq(variables['BUILD_ALL'], 'true') ), eq( dependencies.Check_Build_Options.outputs['BuildOptions.GO'], true ) ) + + dependsOn: + - Get_Commit_Message + - Check_Build_Options + + pool: + vmImage: 'VS2017-Win2016' + + variables: + BoardName: ST_NUCLEO144_F439ZI + BuildOptions: -DTARGET_SERIES=STM32F4xx -DRTOS=CHIBIOS -DNF_FEATURE_DEBUGGER=ON -DSWO_OUTPUT=ON -DNF_FEATURE_RTC=ON -DNF_FEATURE_HAS_CONFIG_BLOCK=ON -DAPI_System.Math=ON -DAPI_Hardware.Stm32=ON -DAPI_Windows.Devices.Gpio=ON -DAPI_Windows.Devices.Spi=ON -DAPI_Windows.Devices.I2c=ON -DAPI_Windows.Devices.Pwm=ON -DAPI_Windows.Devices.SerialCommunication=ON -DAPI_Windows.Devices.Adc=ON -DAPI_System.Net=ON -DNF_SECURITY_MBEDTLS=ON + # creates a counter and assigns it to the revision variable + REVISION: $[counter('ST_NUCLEO144_F439ZI_versioncounter', 3)] + GccArm_Version: + NeedsDFU: false + + steps: + - checkout: self + fetchDepth: 1 + + - template: azure-pipelines-templates/set-build-version.yml + + - template: azure-pipelines-templates/clone-nf-interpreter-repo.yml + + - template: azure-pipelines-templates/download-install-arm-gcc-toolchain.yml@templatesBuild + + - template: azure-pipelines-templates/download-install-ninja.yml@templatesBuild + + - template: azure-pipelines-templates/download-hexdfu.yml@templatesBuild + + - template: azure-pipelines-templates/build-chibios-stm32.yml@templatesBuild + parameters: + buildDirectory: $(Build.SourcesDirectory)\nf-interpreter\build + + - template: azure-pipelines-templates/pack-publish-artifacts.yml@templatesBuild + parameters: + buildDirectory: $(Build.SourcesDirectory)\nf-interpreter\build + + - template: azure-pipelines-templates/publish-bintray.yml@templatesBuild + +################################## +# report build failure to Discord +- job: Report_Build_Failure + dependsOn: + - Build_GHI_FEZ_CERB40_NF + - Build_I2M_ELECTRON_NF + - Build_I2M_OXYGEN_NF + - Build_ST_NUCLEO64_F401RE_NF + - Build_ST_NUCLEO64_F411RE_NF + - Build_ST_NUCLEO144_F412ZG_NF + - Build_ST_NUCLEO144_F746ZG + - Build_ST_STM32F4_DISCOVERY + condition: or( failed('Build_GHI_FEZ_CERB40_NF'), failed('Build_I2M_ELECTRON_NF'), failed('Build_I2M_OXYGEN_NF'), failed('Build_ST_NUCLEO64_F401RE_NF'), failed('Build_ST_NUCLEO64_F411RE_NF'), failed('Build_ST_NUCLEO144_F412ZG_NF'), failed('Build_ST_NUCLEO144_F746ZG'), failed('Build_ST_STM32F4_DISCOVERY')) + + pool: + vmImage: 'VS2017-Win2016' + + steps: + - checkout: self + fetchDepth: 1 + + # step from template @ nf-tools repo + - template: azure-pipelines-templates/discord-webhook.yml@templates + parameters: + status: 'failure' + webhookUrl: '$(DiscordWebhook)' + message: '' + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/CMakeLists.txt new file mode 100644 index 00000000..a362ead4 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/CMakeLists.txt @@ -0,0 +1,493 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +include(STM32_CubePackage) + +######################################################## +# check availability of hex2dfu tool if specified +if(NOT "${TOOL_HEX2DFU_PREFIX}" STREQUAL "") + if(NOT EXISTS ${TOOL_HEX2DFU_PREFIX}/hex2dfu.exe) + message(STATUS "") + message(STATUS "Couldn't find the hex2dfu tool at the specified path: ${TOOL_HEX2DFU_PREFIX}/hex2dfu.exe") + message(STATUS "Make sure that the CMake option TOOL_HEX2DFU_PREFIX has the correct path.") + message(STATUS "If you don't have this tool download it from https://github.com/nanoframework/nf-tools/releases") + message(STATUS "") + message(FATAL_ERROR "hex2dfu tool not found") + else() + set(HEX2DFU_TOOL_AVAILABLE TRUE CACHE INTERNAL "hex2dfu tool available") + endif() +endif() + +# check if CHIBIOS_SOURCE was specified or if it's empty (default is empty) +set(NO_CHIBIOS_SOURCE TRUE) +if(CHIBIOS_SOURCE) + if(NOT "${CHIBIOS_SOURCE}" STREQUAL "") + set(NO_CHIBIOS_SOURCE FALSE) + endif() +endif() + +# check if CHIBIOS-Contrib_SOURCE was specified or if it's empty (default is empty) +set(NO_CHIBIOS_CONTRIB_SOURCE TRUE) +if(CHIBIOS_CONTRIB_SOURCE) + if(NOT "${CHIBIOS_CONTRIB_SOURCE}" STREQUAL "") + set(NO_CHIBIOS_CONTRIB_SOURCE FALSE) + endif() +endif() + +if(NO_CHIBIOS_SOURCE) + # no CHIBIOS source specified, download it from it's repo + + # check for Git (needed here for advanced warning to user if it's not installed) + find_package(Git) + + # check if Git was found, if not report to user and abort + if(NOT GIT_EXECUTABLE) + message(FATAL_ERROR "error: could not find Git, make sure you have it installed.") + endif() + + # ChibiOS version + set(CHIBIOS_GIT_TAG "stable_19.1.x") + message(STATUS "RTOS is: CHIBIOS (latest available code from ${CHIBIOS_GIT_TAG})") + + # need to setup a separate CMake project to download the code from the GitHub repository + # otherwise it won't be available before the actual build step + configure_file("${PROJECT_SOURCE_DIR}/CMake/ChibiOS.CMakeLists.cmake.in" + "${CMAKE_BINARY_DIR}/ChibiOS_Download/CMakeLists.txt") + + # setup CMake project for ChibiOS download + execute_process(COMMAND ${CMAKE_COMMAND} -G "${CMAKE_GENERATOR}" . + RESULT_VARIABLE result + WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/ChibiOS_Download") + + # run build on ChibiOS download CMake project to perform the download + execute_process(COMMAND ${CMAKE_COMMAND} --build . + RESULT_VARIABLE result + WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/ChibiOS_Download") + + # add ChibiOS as external project + ExternalProject_Add( + ChibiOS + PREFIX ChibiOS + SOURCE_DIR ${CMAKE_BINARY_DIR}/ChibiOS_Source + GIT_REPOSITORY https://github.com/nanoframework/chibios + GIT_TAG ${CHIBIOS_GIT_TAG} # target specified branch + GIT_SHALLOW 1 # download only the tip of the branch, not the complete history + TIMEOUT 10 + LOG_DOWNLOAD 1 + + # Disable all other steps + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND "" + ) + + # get source dir for ChibiOS CMake project + ExternalProject_Get_Property(ChibiOS SOURCE_DIR) + +else() + # ChibiOS source was specified + + # sanity check is source path exists + if(EXISTS "${CHIBIOS_SOURCE}/") + message(STATUS "RTOS is: ChibiOS (source from: ${CHIBIOS_SOURCE})") + + # check if we already have the sources, no need to copy again + if(NOT EXISTS "${CMAKE_BINARY_DIR}/ChibiOS_Source") + file(COPY "${CHIBIOS_SOURCE}/" DESTINATION "${CMAKE_BINARY_DIR}/ChibiOS_Source") + else() + message(STATUS "Using local cache of ChibiOS source from ${CHIBIOS_SOURCE}") + endif() + + set(CHIBIOS_INCLUDE_DIR ${CMAKE_BINARY_DIR}/ChibiOS_Source/include) + else() + message(FATAL_ERROR "Couldn't find ChibiOS source at ${CHIBIOS_SOURCE}/") + endif() + + # add ChibiOS as external project + ExternalProject_Add( + ChibiOS + PREFIX ChibiOS + SOURCE_DIR ${CMAKE_BINARY_DIR}/ChibiOS_Source + + # Disable all other steps + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND "" + ) + + # get source dir for ChibiOS CMake project + ExternalProject_Get_Property(ChibiOS SOURCE_DIR) + +endif() + +if(CHIBIOS_CONTRIB_REQUIRED) + if(NO_CHIBIOS_CONTRIB_SOURCE) + # no CHIBIOS_CONTRIB source specified, download it from it's repo + + # check for Git (needed here for advanced warning to user if it's not installed) + find_package(Git) + + # check if Git was found, if not report to user and abort + if(NOT GIT_EXECUTABLE) + message(FATAL_ERROR "error: could not find Git, make sure you have it installed.") + endif() + + message(STATUS "ChibiOS-Contrib source from GitHub repo") + + # need to setup a separate CMake project to download the code from the GitHub repository + # otherwise it won't be available before the actual build step + configure_file("${PROJECT_SOURCE_DIR}/CMake/ChibiOS-Contrib.CMakeLists.cmake.in" + "${CMAKE_BINARY_DIR}/ChibiOS-Contrib_Download/CMakeLists.txt") + + # setup CMake project for ChibiOS-Contrib download + execute_process(COMMAND ${CMAKE_COMMAND} -G "${CMAKE_GENERATOR}" . + RESULT_VARIABLE result + WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/ChibiOS-Contrib_Download") + + # run build on ChibiOS-Contrib download CMake project to perform the download + execute_process(COMMAND ${CMAKE_COMMAND} --build . + RESULT_VARIABLE result + WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/ChibiOS-Contrib_Download") + + # add ChibiOS-Contrib as external project + # need to specify nanoframework as the active branch + ExternalProject_Add( + ChibiOS-Contrib + PREFIX ChibiOS-Contrib + SOURCE_DIR ${CMAKE_BINARY_DIR}/ChibiOS-Contrib_Source + GIT_REPOSITORY https://github.com/nanoframework/ChibiOS-Contrib + GIT_TAG nanoframework # target specified branch + GIT_SHALLOW 1 # download only the tip of the branch, not the complete history + TIMEOUT 10 + LOG_DOWNLOAD 1 + # Disable all other steps + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND "" + ) + + # get source dir for ChibiOS-Contrib CMake project + ExternalProject_Get_Property(ChibiOS-Contrib SOURCE_DIR) + + else() + # ChibiOS-Contrib source was specified + + # sanity check is source path exists + if(EXISTS "${CHIBIOS_CONTRIB_SOURCE}/") + message(STATUS "ChibiOS-Contrib source from: ${CHIBIOS_CONTRIB_SOURCE}") + + # check if we already have the sources, no need to copy again + if(NOT EXISTS "${CMAKE_BINARY_DIR}/ChibiOS-Contrib_Source") + file(COPY "${CHIBIOS_CONTRIB_SOURCE}/" DESTINATION "${CMAKE_BINARY_DIR}/ChibiOS-Contrib_Source") + else() + message(STATUS "Using local cache of ChibiOS-Contrib source from ${CHIBIOS_CONTRIB_SOURCE}") + endif() + + set(CHIBIOS_INCLUDE_DIR ${CMAKE_BINARY_DIR}/ChibiOS_Source/include) + else() + message(FATAL_ERROR "Couldn't find ChibiOS-Contrib source at ${CHIBIOS_CONTRIB_SOURCE}/") + endif() + + # add ChibiOS-Contrib as external project + ExternalProject_Add( + ChibiOS-Contrib + PREFIX ChibiOS-Contrib + SOURCE_DIR ${CMAKE_BINARY_DIR}/ChibiOS-Contrib_Source + # Disable all other steps + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND "" + ) + + # get source dir for ChibiOS-Contrib CMake project + ExternalProject_Get_Property(ChibiOS-Contrib SOURCE_DIR) + + endif() +endif() + +# if mbed TLS is enabled add it to the build +if(NF_SECURITY_MBEDTLS) + + # check if MBEDTLS_SOURCE was specified or if it's empty (default is empty) + set(NO_MBEDTLS_SOURCE TRUE) + + if(MBEDTLS_SOURCE) + if(NOT "${MBEDTLS_SOURCE}" STREQUAL "") + set(NO_MBEDTLS_SOURCE FALSE) + endif() + endif() + + # set options for mbed TLS + option(ENABLE_TESTING "no testing when building mbed TLS." OFF) + + if(NO_MBEDTLS_SOURCE) + # no mbed TLS source specified, download it from it's repo + + # check for Git (needed here for advanced warning to user if it's not installed) + find_package(Git) + + # check if Git was found, if not report to user and abort + if(NOT GIT_EXECUTABLE) + message(FATAL_ERROR "error: could not find Git, make sure you have it installed.") + endif() + + # set tag for currently supported version + set(MBEDTLS_GIT_TAG "mbedtls-2.16.3") + + # need to setup a separate CMake project to download the code from the GitHub repository + # otherwise it won't be available before the actual build step + configure_file("${PROJECT_SOURCE_DIR}/CMake/mbedTLS.CMakeLists.cmake.in" + "${CMAKE_BINARY_DIR}/mbedTLS_Download/CMakeLists.txt") + + # setup CMake project for mbedTLS download + execute_process(COMMAND ${CMAKE_COMMAND} -G "${CMAKE_GENERATOR}" . + RESULT_VARIABLE result + WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/mbedTLS_Download") + + # run build on mbedTLS download CMake project to perform the download + execute_process(COMMAND ${CMAKE_COMMAND} --build . + RESULT_VARIABLE result + WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/mbedTLS_Download") + + # add mbedTLS as external project + ExternalProject_Add( + mbedTLS + PREFIX mbedTLS + SOURCE_DIR ${CMAKE_BINARY_DIR}/mbedTLS_Source + GIT_REPOSITORY https://github.com/nanoframework/mbedtls + GIT_TAG ${MBEDTLS_GIT_TAG} # target specified branch + GIT_SHALLOW 1 # download only the tip of the branch, not the complete history + TIMEOUT 10 + LOG_DOWNLOAD 1 + + # Disable all other steps + CONFIGURE_COMMAND "" + BUILD_COMMAND "" + INSTALL_COMMAND "" + ) + + else() + # mbedTLS source was specified + + # sanity check is source path exists + if(EXISTS "${MBEDTLS_SOURCE}/") + + # check if we already have the sources, no need to copy again + if(NOT EXISTS "${CMAKE_BINARY_DIR}/mbedTLS_Source") + message(STATUS "mbedTLS source from: ${MBEDTLS_SOURCE}") + file(COPY "${MBEDTLS_SOURCE}/" DESTINATION "${CMAKE_BINARY_DIR}/mbedTLS_Source") + else() + message(STATUS "Using local cache of mbedTLS source from ${MBEDTLS_SOURCE}") + endif() + + set(MBEDTLS_INCLUDE_DIR ${CMAKE_BINARY_DIR}/mbedTLS_Source/include) + else() + message(FATAL_ERROR "Couldn't find mbedTLS source at ${MBEDTLS_SOURCE}/") + endif() + + # add mbedTLS as external project + ExternalProject_Add( + mbedTLS + PREFIX mbedTLS + SOURCE_DIR ${CMAKE_BINARY_DIR}/mbedTLS_Source + + # Disable all other steps + CONFIGURE_COMMAND "" + BUILD_COMMAND "" + INSTALL_COMMAND "" + ) + + endif() + + set(mbedTLS_INCLUDE_DIRS "${CMAKE_SOURCE_DIR}/3rdparty/humblelogging/include") + set(mbedTLS_LIBRARIES "${CMAKE_SHARED_LIBRARY_PREFIX}mbedTLS${CMAKE_SHARED_LIBRARY_SUFFIX}") + include_directories(${mbedTLS_INCLUDE_DIRS}) + +endif() + +# set target base location +# this has to be set before the class library modules are pulled in +if(EXISTS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/${CHIBIOS_BOARD}) + # set target base location + set(TARGET_BASE_LOCATION "${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/${CHIBIOS_BOARD}") +else() + # try to find board in the Community targets folder + if(EXISTS ${PROJECT_SOURCE_DIR}/targets-community/CMSIS-OS/ChibiOS/${CHIBIOS_BOARD}) + # set target base location + set(TARGET_BASE_LOCATION "${PROJECT_SOURCE_DIR}/targets-community/CMSIS-OS/ChibiOS/${CHIBIOS_BOARD}") + else() + # board NOT found in targets folder + # can't continue + message(FATAL_ERROR "\n\nSorry but support for ${CHIBIOS_BOARD} target is not available...\n\nYou can wait for that to be added or you might want to contribute and start working on a PR for that.\n\n") + endif() +endif() + +# set CMSIS RTOS include directory +include_directories( ${CMSIS_RTOS_INCLUDE_DIR}) + +# need to find board definition files (board.c and board.h) + +# assume no community board... until proven otherwise +set(CHIBIOS_COMMUNITY_TARGET FALSE CACHE INTERNAL "Community target flag") + +# start search in nanoFramework ChibiOS 'overlay' folder +if(EXISTS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/boards/${CHIBIOS_BOARD}) + # board found + # if it's on nF overlay board.c and board.h exist there for sure + set(CHIBIOS_BOARD_DEFINITIONS_LOCATION "Board definition files taken from nanoFramework overlay" CACHE INTERNAL "Location of board definition files") +else() + # board NOT found in ChibiOS 'overlay' + + # try to find it in the target boards + if(EXISTS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/${CHIBIOS_BOARD}) + # board found + # check if the board definition files are available at the target folder + if( EXISTS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/${CHIBIOS_BOARD}/board.c AND + EXISTS ${PROJECT_SOURCE_DIR}/targets/CMSIS-OS/ChibiOS/${CHIBIOS_BOARD}/board.h) + # definition files found + set(CHIBIOS_BOARD_DEFINITIONS_LOCATION "Board definition files taken from target folder" CACHE INTERNAL "Location of board definition files") + + else() + # board.c and board.h are NOT in the target folder, try to find them in the official distribution + + if(EXISTS ${PROJECT_BINARY_DIR}/ChibiOS_Source/os/hal/boards/${CHIBIOS_BOARD}) + # board found + # if it's on the ChibiOS official distribution board.c and board.h exist here for sure + set(CHIBIOS_BOARD_DEFINITIONS_LOCATION "Board definition files taken from official ChibiOS distribution" CACHE INTERNAL "Location of board definition files") + + else() + # board NOT found in official distribution + # quit now as there is no were else to search for these + message(FATAL_ERROR "\n\nSorry but couldn't find definition files for ${CHIBIOS_BOARD} in the available list of ChibiOS supported boards...\n\n") + + endif() + endif() + + else() + # try to find board in the Community targets folder + if(EXISTS ${PROJECT_SOURCE_DIR}/targets-community/CMSIS-OS/ChibiOS/${CHIBIOS_BOARD}) + # set flag for this being a community board + set(CHIBIOS_COMMUNITY_TARGET TRUE CACHE INTERNAL "Community target flag") + else() + # board NOT found in official distribution + # quit now as there is no were else to search for these + message(FATAL_ERROR "\n\nSorry but couldn't find definition files for ${CHIBIOS_BOARD} in the available list of ChibiOS supported boards...\n\n") + endif() + + endif() + +endif() + +# (default is OFF so STM Cube package is NOT included) +option(STM32_CUBE_PACKAGE_REQUIRED "option to include STM Cube pcakge in the build") +if(STM32_CUBE_PACKAGE_REQUIRED) + ProcessSTM32CubePackage() +endif() + +# if support for SPIFFS is enabled add it to the build +if(NF_FEATURE_USE_SPIFFS) + + # check if SPIFFS_SOURCE was specified or if it's empty (default is empty) + set(NO_SPIFFS_SOURCE TRUE) + + if(SPIFFS_SOURCE) + if(NOT "${SPIFFS_SOURCE}" STREQUAL "") + set(NO_SPIFFS_SOURCE FALSE) + endif() + endif() + + if(NO_SPIFFS_SOURCE) + # no SPIFFS source specified, download it from it's repo + + # check for Git (needed here for advanced warning to user if it's not installed) + find_package(Git) + + # check if Git was found, if not report to user and abort + if(NOT GIT_EXECUTABLE) + message(FATAL_ERROR "error: could not find Git, make sure you have it installed.") + endif() + + # need to setup a separate CMake project to download the code from the GitHub repository + # otherwise it won't be available before the actual build step + configure_file("${PROJECT_SOURCE_DIR}/CMake/SPIFFS.CMakeLists.cmake.in" + "${CMAKE_BINARY_DIR}/SPIFFS_Download/CMakeLists.txt") + + # setup CMake project for SPIFFS download + execute_process(COMMAND ${CMAKE_COMMAND} -G "${CMAKE_GENERATOR}" . + RESULT_VARIABLE result + WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/SPIFFS_Download") + + # run build on SPIFFS download CMake project to perform the download + execute_process(COMMAND ${CMAKE_COMMAND} --build . + RESULT_VARIABLE result + WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/SPIFFS_Download") + + # add SPIFFS as external project + ExternalProject_Add( + SPIFFS + PREFIX SPIFFS + SOURCE_DIR ${CMAKE_BINARY_DIR}/SPIFFS_Source + GIT_REPOSITORY https://github.com/nanoframework/spiffs + GIT_TAG "nf-build" # target nanoFramework modified branch + GIT_SHALLOW 1 # download only the tip of the branch, not the complete history + TIMEOUT 10 + LOG_DOWNLOAD 1 + + # Disable all other steps + CONFIGURE_COMMAND "" + BUILD_COMMAND "" + INSTALL_COMMAND "" + ) + + else() + # SPIFFS source was specified + + # sanity check is source path exists + if(EXISTS "${SPIFFS_SOURCE}/") + + # check if we already have the sources, no need to copy again + if(NOT EXISTS "${CMAKE_BINARY_DIR}/SPIFFS_Source") + message(STATUS "SPIFFS source from: ${SPIFFS_SOURCE}") + file(COPY "${SPIFFS_SOURCE}/" DESTINATION "${CMAKE_BINARY_DIR}/SPIFFS_Source") + else() + message(STATUS "Using local cache of SPIFFS source from ${SPIFFS_SOURCE}") + endif() + + set(SPIFFS_INCLUDE_DIR ${CMAKE_BINARY_DIR}/SPIFFS_Source/include) + else() + message(FATAL_ERROR "Couldn't find SPIFFS source at ${SPIFFS_SOURCE}/") + endif() + + # add SPIFFS as external project + ExternalProject_Add( + SPIFFS + PREFIX SPIFFS + SOURCE_DIR ${CMAKE_BINARY_DIR}/SPIFFS_Source + + # Disable all other steps + CONFIGURE_COMMAND "" + BUILD_COMMAND "" + INSTALL_COMMAND "" + ) + + endif() + + # get source dir for SPIFFS CMake project + ExternalProject_Get_Property(SPIFFS SOURCE_DIR) + + set(SPIFFS_LIBRARIES "${CMAKE_SHARED_LIBRARY_PREFIX}SPIFFS${CMAKE_SHARED_LIBRARY_SUFFIX}") + include_directories(${SPIFFS_INCLUDE_DIRS}) + + add_subdirectory(spiffs) + +endif() + +# add target ChibiOS dirs +add_subdirectory(Include) +add_subdirectory(common) +add_subdirectory(nanoBooter) +add_subdirectory(nanoCLR) + +# board folder will be added in main CMakeList diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/CLR_Startup_Thread.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/CLR_Startup_Thread.h new file mode 100644 index 00000000..3c394ef4 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/CLR_Startup_Thread.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _CLRSTARTUPTHREAD_ +#define _CLRSTARTUPTHREAD_ + +// declaration of RTOS thread +void CLRStartupThread(void const * argument); + +#endif //_CLRSTARTUPTHREAD_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/CMakeLists.txt new file mode 100644 index 00000000..011c8fad --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/CMakeLists.txt @@ -0,0 +1,19 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append include directory for target ChibiOS +list(APPEND TARGET_CHIBIOS_COMMON_INCLUDE_DIRS "${CMAKE_CURRENT_SOURCE_DIR}") + +# make var global +set(TARGET_CHIBIOS_COMMON_INCLUDE_DIRS ${TARGET_CHIBIOS_COMMON_INCLUDE_DIRS} CACHE INTERNAL "make global") + +# add header with target platform definitions +if(CHIBIOS_COMMUNITY_TARGET) + configure_file("${CMAKE_SOURCE_DIR}/CMake/ChibiOS_target_os.h.in" + "${CMAKE_BINARY_DIR}/targets-community/CMSIS-OS/ChibiOS/${CHIBIOS_BOARD}/target_os.h" @ONLY) +else() + configure_file("${CMAKE_SOURCE_DIR}/CMake/ChibiOS_target_os.h.in" + "${CMAKE_BINARY_DIR}/targets/CMSIS-OS/ChibiOS/${CHIBIOS_BOARD}/target_os.h" @ONLY) +endif() diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/LaunchCLR.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/LaunchCLR.h new file mode 100644 index 00000000..15e319ef --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/LaunchCLR.h @@ -0,0 +1,13 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _LAUNCHCLR_H_ +#define _LAUNCHCLR_H_ + +void LaunchCLR(uint32_t address); +bool CheckValidCLRImage(uint32_t address); + +#endif //_LAUNCHCLR_H_ + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/TargetPAL_BlockStorage.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/TargetPAL_BlockStorage.h new file mode 100644 index 00000000..805c2e32 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/TargetPAL_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_PAL_BLOCKSTORAGE_H_ +#define _TARGET_PAL_BLOCKSTORAGE_H_ 1 + +#include + +#endif // _TARGET_PAL_BLOCKSTORAGE_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/Target_BlockStorage_STM32FlashDriver.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/Target_BlockStorage_STM32FlashDriver.h new file mode 100644 index 00000000..421ebc4d --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/Target_BlockStorage_STM32FlashDriver.h @@ -0,0 +1,30 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_STM32FLASH_DRIVER_H_ +#define _TARGET_STM32FLASH_DRIVER_H_ 1 + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +bool STM32FlashDriver_InitializeDevice(void*); +bool STM32FlashDriver_UninitializeDevice(void*); +DeviceBlockInfo* STM32FlashDriver_GetDeviceInfo(void*); +bool STM32FlashDriver_Read(void*, ByteAddress startAddress, unsigned int numBytes, unsigned char* buffer); +bool STM32FlashDriver_Write(void*, ByteAddress startAddress, unsigned int numBytes, unsigned char* buffer, bool readModifyWrite); +bool STM32FlashDriver_IsBlockErased(void*, ByteAddress blockAddress, unsigned int length); +bool STM32FlashDriver_EraseBlock(void*, ByteAddress address); + +#ifdef __cplusplus +} +#endif + +#endif //_TARGET_STM32FLASH_DRIVER_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/Target_Windows_Storage.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/Target_Windows_Storage.h new file mode 100644 index 00000000..57bd9b3f --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/Target_Windows_Storage.h @@ -0,0 +1,28 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_WINDOWS_STORAGE_H_ +#define _TARGET_WINDOWS_STORAGE_H_ 1 + +#define SDCARD_POLLING_INTERVAL (10) +#define SDCARD_POLLING_DELAY (500) + + +#define USB_MSD_POLLING_INTERVAL (1000) +#define USB_MSD_POLLING_DELAY (1000) + +#ifdef __cplusplus +extern "C" { +#endif + + // declaration of storage working threads + void SdCardWorkingThread(void const * argument); + void UsbMsdWorkingThread(void const * argument); + +#ifdef __cplusplus +} +#endif + +#endif //_TARGET_WINDOWS_STORAGE_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/WireProtocol_ReceiverThread.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/WireProtocol_ReceiverThread.h new file mode 100644 index 00000000..c6b75c3e --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/WireProtocol_ReceiverThread.h @@ -0,0 +1,13 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIREPROTOCOL_RECEIVERTHREAD_H_ +#define _WIREPROTOCOL_RECEIVERTHREAD_H_ + +// declaration of RTOS thread +void ReceiverThread(void const * argument); + +#endif //_WIREPROTOCOL_RECEIVERTHREAD_H_ + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/platform_target_capabilities.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/platform_target_capabilities.h new file mode 100644 index 00000000..eb7f38d8 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/platform_target_capabilities.h @@ -0,0 +1,34 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _PLATFORM_TARGET_CAPABILITIES_H_ +#define _PLATFORM_TARGET_CAPABILITIES_H_ 1 + +/////////////////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH nanoFramework.Tools.Debugger.Stm32.TargetCapabilities (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////////////////////// + +#ifdef __cplusplus +extern "C" { +#endif + +// this platform doesn't have any declared capabilities + +// the targets of this platform can declate these capabilities +typedef enum TargetCapabilities +{ + // JTAG update + TargetCapabilities_JtagUpdate = 0x00000000, + + // DFU update + TargetCapabilities_DfuUpdate = 0x00040000, + +}TargetCapabilities; + +#ifdef __cplusplus +} +#endif + +#endif //_PLATFORM_TARGET_CAPABILITIES_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/targetHAL.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/targetHAL.h new file mode 100644 index 00000000..fe2ab9b4 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/targetHAL.h @@ -0,0 +1,76 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_HAL_H_ +#define _TARGET_HAL_H_ + +#include +#include +#include +#include + +#define GLOBAL_LOCK() chSysLock(); +#define GLOBAL_UNLOCK(); chSysUnlock(); +// platform dependent delay +#define PLATFORM_DELAY(milliSecs) osDelay(milliSecs); + +// Definitions for Sockets/Network +#define GLOBAL_LOCK_SOCKETS(x) + +#define PLATFORM_DEPENDENT__SOCKETS_MAX_COUNT 16 + +#define LPCSTR const char* + +// these macros are to be used at entry/exit of native interrupt handlers +#define NATIVE_INTERRUPT_START SystemState_SetNoLock( SYSTEM_STATE_ISR ); \ + SystemState_SetNoLock( SYSTEM_STATE_NO_CONTINUATIONS ); +#define NATIVE_INTERRUPT_END SystemState_ClearNoLock( SYSTEM_STATE_NO_CONTINUATIONS ); \ + SystemState_ClearNoLock( SYSTEM_STATE_ISR ); + +#if !defined(BUILD_RTM) + +#define HARD_BREAKPOINT() HARD_Breakpoint() + +// #if defined(_DEBUG) +// #define DEBUG_HARD_BREAKPOINT() HARD_Breakpoint() +// #else +// #define DEBUG_HARD_BREAKPOINT() +// #endif + +// #else + +// #define HARD_BREAKPOINT() +// #define DEBUG_HARD_BREAKPOINT() + +#endif // !defined(BUILD_RTM) + + +///////////////////////////////////////////////////////////////////////////////////////////////////// +// DEBUGGER HELPER // +// The line below is meant to be used as helper on checking that the execution engine is running. // +// This can be inferred by checking if Events_WaitForEvents loop is running. // +// The implementation should is to be provided by each target at target_common.h.in // +//////////////////////////////////////////////////////////////////////////////////////////////////// +#if defined(BUILD_RTM) + #define EVENTS_HEART_BEAT +#else + #ifndef EVENTS_HEART_BEAT + #define EVENTS_HEART_BEAT __NOP() + #endif // EVENTS_HEART_BEAT +#endif + +#define NANOCLR_STOP() CPU_Reset(); + +extern int HeapBegin; +extern int HeapEnd; + +extern uint32_t __nanoImage_start__; +extern uint32_t __nanoImage_end__; +extern uint32_t __nanoConfig_start__; +extern uint32_t __nanoConfig_end__; +extern uint32_t __deployment_start__; +extern uint32_t __deployment_end__; + +#endif //_TARGET_HAL_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/targetHAL_Power.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/targetHAL_Power.h new file mode 100644 index 00000000..96d00fee --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/targetHAL_Power.h @@ -0,0 +1,18 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_HAL_POWER_H_ +#define _TARGET_HAL_POWER_H_ 1 + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef __cplusplus +} +#endif + +#endif //_TARGET_HAL_POWER_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/targetHAL_Time.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/targetHAL_Time.h new file mode 100644 index 00000000..88083178 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/targetHAL_Time.h @@ -0,0 +1,13 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_HAL_TIME_H_ +#define _TARGET_HAL_TIME_H_ 1 + +#include + +#define HAL_Time_CurrentSysTicks osKernelSysTick + +#endif //_TARGET_HAL_TIME_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/targetHAL_Watchdog.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/targetHAL_Watchdog.h new file mode 100644 index 00000000..c0748717 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/targetHAL_Watchdog.h @@ -0,0 +1,23 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// +#include +#include + +#ifndef _TARGETHAL_WATCHDOG_H_ +#define _TARGETHAL_WATCHDOG_H_ 1 + +#if (HAL_USE_WDG) + #if (STM32_LSI_ENABLED == FALSE) + #error "LSI clock must be enabled for independent watchdog (IWDG) to work" + #endif + + // if the timeout isn't set at target level, set a default value (10 seconds) + #if !defined(IWATCHDOG_TIMEOUT_MILLIS) + #define IWATCHDOG_TIMEOUT_MILLIS 10000 + #endif + +#endif + +#endif diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/targetPAL.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/targetPAL.h new file mode 100644 index 00000000..b8edb901 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/targetPAL.h @@ -0,0 +1,22 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_H_ +#define _TARGETPAL_H_ + +#include + + +#if defined(STM32L0XX) || defined(STM32F0XX) || defined(STM32F4XX) || defined(STM32F7XX) || defined(STM32H7XX) + +// Contains available GPIO ports for the current board +extern stm32_gpio_t* gpioPort[]; + +//Gets the GPIO according to a pin number +#define GPIO_PORT(pin) (gpioPort[pin/16]) + +#endif + +#endif // _TARGETPAL_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/targetPAL_Time.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/targetPAL_Time.h new file mode 100644 index 00000000..3d857fd3 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/targetPAL_Time.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_PAL_TIME_H_ +#define _TARGET_PAL_TIME_H_ 1 + +#include + + +#endif //_TARGET_PAL_TIME_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/vectors.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/vectors.h new file mode 100644 index 00000000..bdf3a46a --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Include/vectors.h @@ -0,0 +1,57 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +// Interrupt vectors for Cortex-Mx devices. + +#ifndef VECTORS_H +#define VECTORS_H + +#include "cmparams.h" + +#if !defined(_FROM_ASM_) +/** + * @brief Type of an IRQ vector. + */ +typedef void (*irq_vector_t)(void); + +// Type of a structure representing the 16 system vectors of Cortex-M. +// The remaining interrupt vectors are not included. +typedef struct { + uint32_t *init_stack; + irq_vector_t reset_handler; + irq_vector_t nmi_handler; + irq_vector_t hardfault_handler; + irq_vector_t memmanage_handler; + irq_vector_t busfault_handler; + irq_vector_t usagefault_handler; + irq_vector_t vector1c; + irq_vector_t vector20; + irq_vector_t vector24; + irq_vector_t vector28; + irq_vector_t svc_handler; + irq_vector_t debugmonitor_handler; + irq_vector_t vector34; + irq_vector_t pendsv_handler; + irq_vector_t systick_handler; + irq_vector_t vectors[CORTEX_NUM_VECTORS]; +} vectors_t; +#endif /* !defined(_FROM_ASM_) */ + +#if !defined(_FROM_ASM_) +extern vectors_t _vectors; +#endif + +#endif // VECTORS_H diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Lwip/nf_lwipthread.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Lwip/nf_lwipthread.c new file mode 100644 index 00000000..b9c58339 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Lwip/nf_lwipthread.c @@ -0,0 +1,477 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + * **** This file incorporates work covered by the following copyright and **** + * **** permission notice: **** + * + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/** + * @file lwipthread.c + * @brief LWIP wrapper thread code. + * @addtogroup LWIP_THREAD + * @{ + */ + +#include "hal.h" +#include "evtimer.h" + +#include "nf_lwipthread.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if LWIP_DHCP +#include +#endif + +#if LWIP_AUTOIP +#include +#endif + +#define PERIODIC_TIMER_ID 1 +#define FRAME_RECEIVED_ID 2 + +/* + * Suspension point for initialization procedure. + */ +thread_reference_t lwip_trp = NULL; + +/* + * Stack area for the LWIP-MAC thread. + */ +static THD_WORKING_AREA(wa_lwip_thread, LWIP_THREAD_STACK_SIZE); + +/* + * Initialization. + */ +static void low_level_init(struct netif *netif) { + /* set MAC hardware address length */ + netif->hwaddr_len = ETHARP_HWADDR_LEN; + + /* maximum transfer unit */ + netif->mtu = LWIP_NETIF_MTU; + + /* device capabilities */ + /* don't set NETIF_FLAG_ETHARP if this device is not an Ethernet one */ + netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP; + + /* Do whatever else is needed to initialize interface. */ +} + +/* + * This function does the actual transmission of the packet. The packet is + * contained in the pbuf that is passed to the function. This pbuf + * might be chained. + * + * @param netif the lwip network interface structure for this ethernetif + * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type) + * @return ERR_OK if the packet could be sent + * an err_t value if the packet couldn't be sent + * + * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to + * strange results. You might consider waiting for space in the DMA queue + * to become available since the stack doesn't retry to send a packet + * dropped because of memory failure (except for the TCP timers). + */ +static err_t low_level_output(struct netif *netif, struct pbuf *p) { + struct pbuf *q; + MACTransmitDescriptor td; + + (void)netif; + if (macWaitTransmitDescriptor(ÐD1, &td, TIME_MS2I(LWIP_SEND_TIMEOUT)) != MSG_OK) + return ERR_TIMEOUT; + +#if ETH_PAD_SIZE + pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ +#endif + + /* Iterates through the pbuf chain. */ + for(q = p; q != NULL; q = q->next) + macWriteTransmitDescriptor(&td, (uint8_t *)q->payload, (size_t)q->len); + macReleaseTransmitDescriptor(&td); + + MIB2_STATS_NETIF_ADD(netif, ifoutoctets, p->tot_len); + if (((u8_t*)p->payload)[0] & 1) { + /* broadcast or multicast packet*/ + MIB2_STATS_NETIF_INC(netif, ifoutnucastpkts); + } + else { + /* unicast packet */ + MIB2_STATS_NETIF_INC(netif, ifoutucastpkts); + } + /* increase ifoutdiscards or ifouterrors on error */ + +#if ETH_PAD_SIZE + pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ +#endif + + LINK_STATS_INC(link.xmit); + + return ERR_OK; +} + +/* + * Receives a frame. + * Allocates a pbuf and transfers the bytes of the incoming + * packet from the interface into the pbuf. + * + * @param netif the lwip network interface structure for this ethernetif + * @return a pbuf filled with the received packet (including MAC header) + * NULL on memory error + */ +static bool low_level_input(struct netif *netif, struct pbuf **pbuf) { + MACReceiveDescriptor rd; + struct pbuf *q; + u16_t len; + + (void)netif; + + osalDbgAssert(pbuf != NULL, "invalid null pointer"); + + if (macWaitReceiveDescriptor(ÐD1, &rd, TIME_IMMEDIATE) != MSG_OK) + return false; + + len = (u16_t)rd.size; + +#if ETH_PAD_SIZE + len += ETH_PAD_SIZE; /* allow room for Ethernet padding */ +#endif + + /* We allocate a pbuf chain of pbufs from the pool. */ + *pbuf = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); + + if (*pbuf != NULL) { +#if ETH_PAD_SIZE + pbuf_header(pbuf, -ETH_PAD_SIZE); /* drop the padding word */ +#endif + + /* Iterates through the pbuf chain. */ + for(q = *pbuf; q != NULL; q = q->next) + macReadReceiveDescriptor(&rd, (uint8_t *)q->payload, (size_t)q->len); + macReleaseReceiveDescriptor(&rd); + + MIB2_STATS_NETIF_ADD(netif, ifinoctets, *pbuf->tot_len); + + if (*(uint8_t *)((*pbuf)->payload) & 1) { + /* broadcast or multicast packet*/ + MIB2_STATS_NETIF_INC(netif, ifinnucastpkts); + } + else { + /* unicast packet*/ + MIB2_STATS_NETIF_INC(netif, ifinucastpkts); + } + +#if ETH_PAD_SIZE + pbuf_header(pbuf, ETH_PAD_SIZE); /* reclaim the padding word */ +#endif + + LINK_STATS_INC(link.recv); + } + else { + macReleaseReceiveDescriptor(&rd); // Drop packet + LINK_STATS_INC(link.memerr); + LINK_STATS_INC(link.drop); + MIB2_STATS_NETIF_INC(netif, ifindiscards); + } + + return true; +} + +/* + * Called at the beginning of the program to set up the + * network interface. It calls the function low_level_init() to do the + * actual setup of the hardware. + * + * This function should be passed as a parameter to netifapi_netif_add(). + * + * @param netif the lwip network interface structure for this ethernetif + * @return ERR_OK if the loopif is initialised + * ERR_MEM if private data couldn't be allocated + * any other err_t on error + */ +static err_t ethernetif_init(struct netif *netif) { + osalDbgAssert((netif != NULL), "netif != NULL"); + + /* + * Initialize the snmp variables and counters inside the struct netif. + * The last argument should be replaced with your link speed, in units + * of bits per second. + */ + MIB2_INIT_NETIF(netif, snmp_ifType_ethernet_csmacd, LWIP_LINK_SPEED); + + netif->state = NULL; + netif->name[0] = LWIP_IFNAME0; + netif->name[1] = LWIP_IFNAME1; + /* We directly use etharp_output() here to save a function call. + * You can instead declare your own function an call etharp_output() + * from it if you have to do some checks before sending (e.g. if link + * is available...) */ + netif->output = etharp_output; + netif->linkoutput = low_level_output; + + /* initialize the hardware */ + low_level_init(netif); + + return ERR_OK; +} + +static struct netif thisif = { 0 }; + +struct netif * nf_getNetif() { + return &thisif; +} + +/** + * @brief LWIP handling thread. + * + * @param[in] p pointer to a @p lwipthread_opts structure or @p NULL + * @return The function does not return. + */ +static THD_FUNCTION(lwip_thread, p) { + event_timer_t evt; + event_listener_t el0, el1; + ip_addr_t ip, gateway, netmask; + static const MACConfig mac_config = {thisif.hwaddr}; + net_addr_mode_t addressMode; + err_t result; + + chRegSetThreadName(LWIP_THREAD_NAME); + + /* Initializes the thing.*/ + tcpip_init(NULL, NULL); + + /* TCP/IP parameters, runtime or compile time.*/ + if (p) { + struct lwipthread_opts *opts = p; + unsigned i; + + for (i = 0; i < 6; i++) + { + thisif.hwaddr[i] = opts->macaddress[i]; + } +#if LWIP_IPV6 + // FIXME IPV6 + //ip.u_addr = opts->address; + //gateway.u_addr = opts->gateway; + //netmask.u_addr = opts->netmask; +#else + ip.addr = opts->address; + gateway.addr = opts->gateway; + netmask.addr = opts->netmask; +#endif + addressMode = opts->addrMode; +#if LWIP_NETIF_HOSTNAME + thisif.hostname = opts->ourHostName; +#endif + } + else { + thisif.hwaddr[0] = LWIP_ETHADDR_0; + thisif.hwaddr[1] = LWIP_ETHADDR_1; + thisif.hwaddr[2] = LWIP_ETHADDR_2; + thisif.hwaddr[3] = LWIP_ETHADDR_3; + thisif.hwaddr[4] = LWIP_ETHADDR_4; + thisif.hwaddr[5] = LWIP_ETHADDR_5; +#if LWIP_IPV6 + // FIXME IPV6 + // LWIP_IPADDR(&ip); + // LWIP_GATEWAY(&gateway); + // LWIP_NETMASK(&netmask); +#else + LWIP_IPADDR(&ip); + LWIP_GATEWAY(&gateway); + LWIP_NETMASK(&netmask); +#endif + addressMode = NET_ADDRESS_STATIC; +#if LWIP_NETIF_HOSTNAME + thisif.hostname = NULL; +#endif + } + +#if LWIP_NETIF_HOSTNAME + if (thisif.hostname == NULL) + thisif.hostname = LWIP_NETIF_HOSTNAME_STRING; +#endif + + macStart(ÐD1, &mac_config); + +#if LWIP_NETCONN_SEM_PER_THREAD + sys_arch_netconn_sem_alloc(); +#endif + + /* Add interface. */ + result = netifapi_netif_add(&thisif, &ip, &netmask, &gateway, NULL, ethernetif_init, tcpip_input); + if (result != ERR_OK) + { + chThdSleepMilliseconds(1000); // Give some time to print any other diagnostics. + osalSysHalt("netif_add error"); // Not sure what else we can do if an error occurs here. + }; + + netif_set_default(&thisif); + + switch (addressMode) + { +#if LWIP_AUTOIP + case NET_ADDRESS_AUTO: + autoip_start(&thisif); + break; +#endif + + default: + netif_set_up(&thisif); + break; + } + + /* Setup event sources.*/ + evtObjectInit(&evt, LWIP_LINK_POLL_INTERVAL); + evtStart(&evt); + chEvtRegisterMask(&evt.et_es, &el0, PERIODIC_TIMER_ID); + chEvtRegisterMask(macGetReceiveEventSource(ÐD1), &el1, FRAME_RECEIVED_ID); + chEvtAddEvents(PERIODIC_TIMER_ID | FRAME_RECEIVED_ID); + + /* Resumes the caller and goes to the final priority.*/ + chThdResume(&lwip_trp, MSG_OK); + chThdSetPriority(LWIP_THREAD_PRIORITY); + + // setup SNTP + #if SNTP_SERVER_DNS + sntp_setoperatingmode(SNTP_OPMODE_POLL); + sntp_setservername(0, SNTP_SERVER_DEFAULT_ADDRESS); + sntp_init(); + #endif + + while (true) { + eventmask_t mask = chEvtWaitAny(ALL_EVENTS); + if (mask & PERIODIC_TIMER_ID) { + bool current_link_status = macPollLinkStatus(ÐD1); + if (current_link_status != netif_is_link_up(&thisif)) { + if (current_link_status) { + tcpip_callback_with_block((tcpip_callback_fn) netif_set_link_up, + &thisif, 0); +#if LWIP_DHCP + if (addressMode == NET_ADDRESS_DHCP) + { + dhcp_start(&thisif); + } + + // start SNTP request + #if SNTP_SERVER_DNS + sntp_init(); + #endif +#endif + + } + else { + tcpip_callback_with_block((tcpip_callback_fn) netif_set_link_down, + &thisif, 0); +#if LWIP_DHCP + if (addressMode == NET_ADDRESS_DHCP) + dhcp_stop(&thisif); +#endif + // no connection, stop SNTP + #if SNTP_SERVER_DNS + sntp_stop(); + #endif + } + } + } + + if (mask & FRAME_RECEIVED_ID) { + struct pbuf *p; + while (low_level_input(&thisif, &p)) { + if (p != NULL) { + struct eth_hdr *ethhdr = p->payload; + switch (htons(ethhdr->type)) { + /* IP or ARP packet? */ + case ETHTYPE_IP: + case ETHTYPE_ARP: + /* full packet send to tcpip_thread to process */ + if (thisif.input(p, &thisif) == ERR_OK) + break; + LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n")); + /* Falls through */ + default: + pbuf_free(p); + } + } + } + } + } + +#if LWIP_NETCONN_SEM_PER_THREAD + sys_arch_netconn_sem_free(); +#endif +} + +/** + * @brief Initializes the lwIP subsystem. + * @note The function exits after the initialization is finished. + * + * @param[in] opts pointer to the configuration structure, if @p NULL + * then the static configuration is used. + */ +void lwipInit(const lwipthread_opts_t *opts) { + /* Creating the lwIP thread (it changes priority internally).*/ + chThdCreateStatic(wa_lwip_thread, sizeof (wa_lwip_thread), + chThdGetPriorityX() - 1, lwip_thread, (void *)opts); + + /* Waiting for the lwIP thread complete initialization. Note, + this thread reaches the thread reference object first because + the relative priorities.*/ + chSysLock(); + chThdSuspendS(&lwip_trp); + chSysUnlock(); +} + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Lwip/nf_lwipthread.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Lwip/nf_lwipthread.h new file mode 100644 index 00000000..9b6c2cc9 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Lwip/nf_lwipthread.h @@ -0,0 +1,247 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file lwipthread.h + * @brief LWIP wrapper thread macros and structures. + * @addtogroup LWIP_THREAD + * @{ + */ + +#ifndef LWIPTHREAD_H +#define LWIPTHREAD_H + +#include + +/** + * @brief lwIP default network interface maximum transmission unit (MTU). + */ +#if !defined(LWIP_NETIF_MTU) || defined(__DOXYGEN__) +#define LWIP_NETIF_MTU 1500 +#endif + +/** + * @brief Default network interface hostname. + */ +#if !defined(LWIP_NETIF_HOSTNAME_STRING) || defined(__DOXYGEN__) +#define LWIP_NETIF_HOSTNAME_STRING "lwip" +#endif + +/** + * @brief Default network interface hostname. + */ +#if !defined(LWIP_THREAD_NAME) || defined(__DOXYGEN__) +#define LWIP_THREAD_NAME "lwipthread" +#endif + +/** + * @brief lwIP thread priority. + */ +#ifndef LWIP_THREAD_PRIORITY +#define LWIP_THREAD_PRIORITY NORMALPRIO +#endif + +/** + * @brief lwIP thread stack size. + */ +#if !defined(LWIP_THREAD_STACK_SIZE) || defined(__DOXYGEN__) +#define LWIP_THREAD_STACK_SIZE 672 +#endif + +/** + * @brief Link poll interval. + */ +#if !defined(LWIP_LINK_POLL_INTERVAL) || defined(__DOXYGEN__) +#define LWIP_LINK_POLL_INTERVAL TIME_S2I(5) +#endif + +/** + * @brief IP Address. + */ +#if !defined(LWIP_IPADDR) || defined(__DOXYGEN__) +#define LWIP_IPADDR(p) IP4_ADDR(p, 192, 168, 1, 10) +#endif + +/** + * @brief IP Gateway. + */ +#if !defined(LWIP_GATEWAY) || defined(__DOXYGEN__) +#define LWIP_GATEWAY(p) IP4_ADDR(p, 192, 168, 1, 1) +#endif + +/** + * @brief IP netmask. + */ +#if !defined(LWIP_NETMASK) || defined(__DOXYGEN__) +#define LWIP_NETMASK(p) IP4_ADDR(p, 255, 255, 255, 0) +#endif + +/** + * @brief Transmission timeout. + */ +#if !defined(LWIP_SEND_TIMEOUT) || defined(__DOXYGEN__) +#define LWIP_SEND_TIMEOUT 50 +#endif + +/** + * @brief Link speed. + */ +#if !defined(LWIP_LINK_SPEED) || defined(__DOXYGEN__) +#define LWIP_LINK_SPEED 100000000 +#endif + +/** + * @brief MAC Address byte 0. + */ +#if !defined(LWIP_ETHADDR_0) || defined(__DOXYGEN__) +#define LWIP_ETHADDR_0 0xC2 +#endif + +/** + * @brief MAC Address byte 1. + */ +#if !defined(LWIP_ETHADDR_1) || defined(__DOXYGEN__) +#define LWIP_ETHADDR_1 0xAF +#endif + +/** + * @brief MAC Address byte 2. + */ +#if !defined(LWIP_ETHADDR_2) || defined(__DOXYGEN__) +#define LWIP_ETHADDR_2 0x51 +#endif + +/** + * @brief MAC Address byte 3. + */ +#if !defined(LWIP_ETHADDR_3) || defined(__DOXYGEN__) +#define LWIP_ETHADDR_3 0x03 +#endif + +/** + * @brief MAC Address byte 4. + */ +#if !defined(LWIP_ETHADDR_4) || defined(__DOXYGEN__) +#define LWIP_ETHADDR_4 0xCF +#endif + +/** + * @brief MAC Address byte 5. + */ +#if !defined(LWIP_ETHADDR_5) || defined(__DOXYGEN__) +#define LWIP_ETHADDR_5 0x46 +#endif + +/** + * @brief Interface name byte 0. + */ +#if !defined(LWIP_IFNAME0) || defined(__DOXYGEN__) +#define LWIP_IFNAME0 'm' +#endif + +/** + * @brief Interface name byte 1. + */ +#if !defined(LWIP_IFNAME1) || defined(__DOXYGEN__) +#define LWIP_IFNAME1 's' +#endif + +/** + * @brief Utility macro to define an IPv4 address. + * + * @note Within the networking subsystem, IPv4 network addresses are + * stored with LS byte of network address in MS byte of unsigned int. + */ +#if BYTE_ORDER == LITTLE_ENDIAN +#define IP4_ADDR_VALUE(a,b,c,d) \ + (((u32_t)((d) & 0xff) << 24) | \ + ((u32_t)((c) & 0xff) << 16) | \ + ((u32_t)((b) & 0xff) << 8) | \ + (u32_t)((a) & 0xff)) +#else +#define IP4_ADDR_VALUE(a,b,c,d) \ + (((u32_t)((a) & 0xff) << 24) | \ + ((u32_t)((b) & 0xff) << 16) | \ + ((u32_t)((c) & 0xff) << 8) | \ + (u32_t)((d) & 0xff)) +#endif + +/** + * @brief Startup network assigning modes. + */ +typedef enum { +#if LWIP_DHCP || defined(__DOXYGEN__) + /** + * @brief Assign a DHCP given address. + */ + NET_ADDRESS_DHCP = 1, +#endif + /** + * @brief Assign a statically IPv4 address. + */ + NET_ADDRESS_STATIC = 2, +#if LWIP_AUTOIP || defined(__DOXYGEN__) + /** + * @brief Assign an IPv4 link-Local address. + */ + NET_ADDRESS_AUTO = 3 +#endif +} net_addr_mode_t; + +/** + * @brief Runtime TCP/IP settings. + */ +typedef struct lwipthread_opts { + /** + * @brief Pointer to MAC address as an array of 6 unsigned bytes. + */ + uint8_t *macaddress; + /** + * @brief Network address as 32-bit unsigned integer. + */ + uint32_t address; + /** + * @brief Network subnet mask as 32-bit unsigned integer. + */ + uint32_t netmask; + /** + * @brief Network gateway as 32-bit unsigned integer. + */ + uint32_t gateway; + /** + * @brief Startup network addressing mode - static, DHCP, auto. + */ + net_addr_mode_t addrMode; + /** + * @brief Host name. If NULL, a default string is used. + * @note Not checked for validity. In particular, spaces not allowed. + */ +#if LWIP_NETIF_HOSTNAME || defined(__DOXYGEN__) + const char *ourHostName; +#endif +} lwipthread_opts_t; + +#ifdef __cplusplus +extern "C" { +#endif + void lwipInit(const lwipthread_opts_t *opts); +#ifdef __cplusplus +} +#endif + +#endif /* LWIPTHREAD_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Lwip/platform_sys_arch.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Lwip/platform_sys_arch.c new file mode 100644 index 00000000..d73760a8 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/Lwip/platform_sys_arch.c @@ -0,0 +1,186 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2001-2004 Swedish Institute of Computer Science. All rights reserved. +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +// from the original source code file +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// 3. The name of the author may not be used to endorse or promote products +// derived from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED +// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT +// SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +// OF SUCH DAMAGE. +// +// This file is part of the lwIP TCP/IP stack. +// +// Author: Adam Dunkels + +// see http://lwip.wikia.com/wiki/Porting_for_an_OS for instructions + +#include +#include +#include + +#include "lwip/opt.h" +#include "lwip/mem.h" +#include "lwip/sys.h" +#include "lwip/stats.h" + +#include "arch/cc.h" +#include "arch/sys_arch.h" + +// Creates an empty mailbox. +// Developer notes +// Because ChibiOS CMSIS wrapper requires static allocation of message queues we can't use the +// standard CMSIS define like osMessageQDef(QUEUE, size, void *); +// the workaround is to use a ChibiOS mailbox and allocate memory for the mailbox and the buffer +err_t sys_mbox_new(sys_mbox_t *mbox, int size) +{ + *mbox = platform_malloc(sizeof(mailbox_t) + sizeof(msg_t) * size); + if (*mbox == NULL) + { + return ERR_MEM; + } + + // init the mailbox + chMBObjectInit((mailbox_t*)*mbox, (void *)(((uint8_t *)*mbox) + sizeof(mailbox_t)), size); + +#if SYS_STATS + ++lwip_stats.sys.mbox.used; + if (lwip_stats.sys.mbox.max < lwip_stats.sys.mbox.used) { + lwip_stats.sys.mbox.max = lwip_stats.sys.mbox.used; + } +#endif /* SYS_STATS */ + if (*mbox == NULL) + { + return ERR_MEM; + } + + return ERR_OK; +} + +// Deallocates a mailbox. +// Because this mailbox was created from heap (see sys_mbox_new above) need to free it here +void sys_mbox_free(sys_mbox_t *mbox) +{ + msg_t msgp; + + // check for messages waiting + // If there are messages still present in the + // mailbox when the mailbox is deallocated, it is an indication of a + // programming error in lwIP and the developer should be notified. + if(chMBFetchI((mailbox_t*)*mbox, &msgp) != MSG_TIMEOUT) + { + #if SYS_STATS + lwip_stats.sys.mbox.err++; + #endif /* SYS_STATS */ + + // breaks execution to ensure developer is aware that this function needs a strong implementation at platform level + __asm volatile("BKPT #0\n"); + } + + // ...free memory from mailbox + platform_free(*mbox); +} + +u32_t sys_now(void) +{ + #if OSAL_ST_FREQUENCY == 1000 + return (u32_t)chVTGetSystemTimeX(); + #elif (OSAL_ST_FREQUENCY / 1000) >= 1 && (OSAL_ST_FREQUENCY % 1000) == 0 + return ((u32_t)chVTGetSystemTimeX() - 1) / (OSAL_ST_FREQUENCY / 1000) + 1; + #elif (1000 / OSAL_ST_FREQUENCY) >= 1 && (1000 % OSAL_ST_FREQUENCY) == 0 + return ((u32_t)chVTGetSystemTimeX() - 1) * (1000 / OSAL_ST_FREQUENCY) + 1; + #else + return (u32_t)(((u64_t)(chVTGetSystemTimeX() - 1) * 1000) / OSAL_ST_FREQUENCY) + 1; + #endif +} + +// need to implement this calling the CMSIS implementation because ChibiOS declares this +// TODO can be removed if we ever stop using ChibiOS lwIP source +void sys_sem_signal_S(sys_sem_t* sem) +{ + sys_sem_signal(sem); +} + +#if LWIP_NETCONN_SEM_PER_THREAD + +////////////////////////////////////////////////////////////////////////////////////////////////////// +// required for LWIP_NETCONN_SEM_PER_THREAD +// need to implement this with ChibiOS API because CMSIS RTOS doesn't have an API to deal with this +// +// For this to work ChibiOS thread struct has to be extended at target level. +// This is accomplished by adding the following line at the target 'chconf.h' file +// void* localStorage; + +sys_sem_t* sys_arch_netconn_sem_get(void) +{ + thread_t* currentThread = chThdGetSelfX(); + LWIP_ASSERT("thread != NULL", currentThread != NULL); +volatile char* tName = (char*)currentThread->name; +(void)tName; + return currentThread->localStorage; +} + +void sys_arch_netconn_sem_alloc(void) +{ + void* storage; + + thread_t* currentThread = chThdGetSelfX(); + LWIP_ASSERT("thread != NULL", currentThread != NULL); + + storage = currentThread->localStorage; + if(storage == NULL) + { + // semaphore doesn't exist + sys_sem_t* semaphore = NULL; + err_t err; + + err = sys_sem_new(semaphore, 0); + LWIP_ASSERT("err == ERR_OK", err == ERR_OK); + LWIP_ASSERT("semaphore invalid", sys_sem_valid(semaphore)); + + // store it in thread struc + currentThread->localStorage = semaphore; + } +} + +void sys_arch_netconn_sem_free(void) +{ + void* storage; + + thread_t* currentThread = chThdGetSelfX(); + LWIP_ASSERT("thread != NULL", currentThread != NULL); + + storage = currentThread->localStorage; + if(storage == NULL) + { + // there is a semaphore + sys_sem_t* semaphore = storage; + + // free memory allocation + sys_sem_free(semaphore); + + // clear pointer in thread struct + currentThread->localStorage = NULL; + } +} + +#endif // LWIP_NETCONN_SEM_PER_THREAD diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/CMakeLists.txt new file mode 100644 index 00000000..8e04d314 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/CMakeLists.txt @@ -0,0 +1,237 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +cmake_minimum_required(VERSION 3.0) +ENABLE_LANGUAGE(ASM) + +# add header files with common OS definitions and board definitions specific for each image +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/target_common.h" @ONLY) + +set(NANOBOOTER_PROJECT_NAME "nanoBooter") +set(NANOCLR_PROJECT_NAME "nanoCLR") + +find_package(BuildUtils REQUIRED) +find_package(CHIBIOS REQUIRED) +find_package(ChibiOSnfOverlay REQUIRED) +find_package(WireProtocol REQUIRED) + +# packages for nanoFramework libraries +####################################### +# mandatory +find_package(NF_CoreCLR REQUIRED) + +####################################### +# optional + +# ChibiOS contrib repo +if(CHIBIOS_CONTRIB_REQUIRED) + find_package(ChibiOS-Contrib REQUIRED) +endif() + +# nF feature: debugger +if(NF_FEATURE_DEBUGGER) + find_package(NF_Debugger REQUIRED) + find_package(NF_Diagnostics REQUIRED) +endif() + +# nF feature: networking +if(USE_NETWORKING_OPTION) + find_package(CHIBIOS_LWIP REQUIRED) +endif() + +# nF feature: filesystem +if(USE_FILESYSTEM_OPTION) + find_package(CHIBIOS_FATFS REQUIRED) +endif() + +####################################### + +add_subdirectory("common") +add_subdirectory("nanoBooter") +add_subdirectory("nanoCLR") + +####################### +# nanoBooter executable + +add_executable( + # executables for project, project sources + ${NANOBOOTER_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + "${CMAKE_CURRENT_SOURCE_DIR}/target_BlockStorage.c" + + # need to add configuration manager to allow get/store configuration blocks + "${PROJECT_SOURCE_DIR}/src/HAL/nanoHAL_ConfigurationManager_stubs.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOBOOTER_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOBOOTER_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOBOOTER_SOURCES} + + ${CHIBIOS_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} +) + +####################### +# nanoCLR executable + +add_executable( + # executables for project, project sources + ${NANOCLR_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOCLR_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOCLR_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOCLR_SOURCES} + + ${CHIBIOS_SOURCES} + ${CHIBIOS_CONTRIB_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} + + # sources for nanoFramework libraries + ${NF_CoreCLR_SOURCES} + ${NF_Debugger_SOURCES} + ${NF_Diagnostics_SOURCES} + + # sources for nanoFramework APIs + ${TARGET_NANO_APIS_SOURCES} +) + +# add dependency from ChibiOS (this is required to make sure the ChibiOS repo is downloaded before the build starts) +add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf ChibiOS) +add_dependencies(${NANOCLR_PROJECT_NAME}.elf ChibiOS) + +# add dependencies from CHIBIOS_FILESYSTEM_COMPONENTS (this is required to make sure that ChibiOS filesystem components are unzip at the proper locations before the build starts) +# only required if filesystem is ON +if(USE_FILESYSTEM_OPTION) + add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf CHIBIOS_FILESYSTEM_COMPONENTS) + add_dependencies(${NANOCLR_PROJECT_NAME}.elf CHIBIOS_FILESYSTEM_COMPONENTS) +endif() + +# include common directories +include_directories( + ${CMAKE_CURRENT_BINARY_DIR} + ${CMAKE_CURRENT_SOURCE_DIR} + ${CMAKE_CURRENT_SOURCE_DIR}/common + ${PROJECT_SOURCE_DIR}/src/CLR/Core + ${PROJECT_SOURCE_DIR}/src/CLR/Include + ${PROJECT_SOURCE_DIR}/src/HAL/Include + ${PROJECT_SOURCE_DIR}/src/PAL/Include + + ${WireProtocol_INCLUDE_DIRS} + ${CHIBIOS_INCLUDE_DIRS} + ${ChibiOSnfOverlay_INCLUDE_DIRS} + ${CHIBIOS_CONTRIB_INCLUDE_DIRS} + + ${TARGET_CMSIS_COMMON_INCLUDE_DIRS} + ${TARGET_CHIBIOS_COMMON_INCLUDE_DIRS} +) + +# include directories for nanoBooter +target_include_directories(${NANOBOOTER_PROJECT_NAME}.elf PUBLIC + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter" + ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter + + ${TARGET_CMSIS_NANOBOOTER_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOBOOTER_INCLUDE_DIRS} +) + +# include directories for nanoCLR +target_include_directories(${NANOCLR_PROJECT_NAME}.elf PUBLIC + ${CMAKE_CURRENT_BINARY_DIR}/nanoCLR + ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR + + ${TARGET_CMSIS_NANOCLR_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOCLR_INCLUDE_DIRS} + + # directories for nanoFramework libraries + ${NF_CoreCLR_INCLUDE_DIRS} + ${NF_Debugger_INCLUDE_DIRS} + ${NF_Diagnostics_INCLUDE_DIRS} + + # includes for nanoFramework APIs + ${TARGET_NANO_APIS_INCLUDES} + + # includes for ChibiOS LwIP + ${CHIBIOS_LWIP_INCLUDE_DIRS} +) + +# set compiler options +nf_set_compiler_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_options(${NANOCLR_PROJECT_NAME}.elf) + +# set compiler definitions +nf_set_compiler_definitions(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_definitions(${NANOCLR_PROJECT_NAME}.elf) + +# set linker files +if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/mbn_quail_booter-DEBUG.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/mbn_quail_CLR-DEBUG.ld) +else() + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/mbn_quail_booter.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/mbn_quail_CLR.ld) +endif() + +# set linker options +nf_set_linker_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_linker_options(${NANOCLR_PROJECT_NAME}.elf) + +# add other linker flags +########################################################### +# the sizes of CRT heap and ChibiOS stacks are defined here +############################################################################ +# CRT heap is assigned to RAM4 region @ CCM SRAM so we are OK to use it all +############################################################################ +set_property(TARGET ${NANOBOOTER_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x400,--defsym=__crt_heap_size__=0x10000") +set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x10000") + +# generate output files +nf_generate_build_output_files(${NANOBOOTER_PROJECT_NAME}.elf) +nf_generate_build_output_files(${NANOCLR_PROJECT_NAME}.elf) + +# if HEX2DFU tool is available pack the binaries into a DFU package +if(HEX2DFU_TOOL_AVAILABLE) + + #################################################################################################### + ## when changing the linker file make sure to update the new addresses for the image files below ## + ## DO NOT use the leading 0x notation, just the address in plain hexadecimal formating ## + #################################################################################################### + + if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + NF_GENERATE_DFU_PACKAGE( + ${PROJECT_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin 08000000 + ${PROJECT_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin 08008000 + ${PROJECT_SOURCE_DIR}/build/nanobooter-nanoclr.dfu + ) + else() + NF_GENERATE_DFU_PACKAGE( + ${PROJECT_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin 08000000 + ${PROJECT_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin 08004000 + ${PROJECT_SOURCE_DIR}/build/nanobooter-nanoclr.dfu + ) + endif() + + +endif() diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/README.md b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/README.md new file mode 100644 index 00000000..7f328793 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/README.md @@ -0,0 +1,34 @@ +## Configuration of Chibios, HAL and MCU ## + +For a successful build the following changes are required: + +In _halconf.g_ (in both nanoBooter and nanoCLR folders), when compared with a default file: +- HAL_USE_SERIAL to TRUE +- HAL_USE_SERIAL_USB to TRUE +- HAL_USE_USB to TRUE +- SERIAL_DEFAULT_BITRATE to 921600 + +In _mcuconf.h_ (in both nanoBooter and nanoCLR folders), when compared with a default file: +- STM32_SERIAL_USE_USART2 to TRUE +- STM32_USB_USE_OTG1 to TRUE + +In _chconf.h_ (_**only**_ for nanoCLR folder), when compared with a default file: +- set the CORTEX_VTOR_INIT with the appropriate address of the vector table for nanoCLR + + +## Definitions for each image ## + +Any defines specific to an image (nanoBooter or nanoCLR) that are to be made available throughout the code should be added to the _target_board.h.in_. There is one in [nanoBooter](nanoBooter/target_board.h.in) and another in [nanoCLR](nanoCLR/target_board.h.in) directories, allowing different defines for each one. +Defines that are common to a target board should be added to the [_target_common.h.in_](target_common.h.in). +The content of these files is parsed by CMake. It can include CMake variables. Check the documentation of CMake config files [here](https://cmake.org/cmake/help/v3.7/command/configure_file.html?highlight=configure_file). + + + + +**NOTE: this configuration was successfully tested in a ST_STM32F4_DISCOVERY board using the Serial over USB connection on USB port 1 that creates a virtual COM port.** + + +## Floating point + +The current build is set to add support for single-precision floating point. +Meaning that `System.Math` API supports only the `float` overloads. The `double` ones will throw a `NotImplementedException`. diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/board.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/board.c new file mode 100644 index 00000000..8b90ece5 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/board.c @@ -0,0 +1,266 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +// #if STM32_HAS_GPIOF || defined(__DOXYGEN__) +// gpio_setup_t PFData; +// #endif +// #if STM32_HAS_GPIOG || defined(__DOXYGEN__) +// gpio_setup_t PGData; +// #endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +// #if STM32_HAS_GPIOI || defined(__DOXYGEN__) +// gpio_setup_t PIData; +// #endif +// #if STM32_HAS_GPIOJ || defined(__DOXYGEN__) +// gpio_setup_t PJData; +// #endif +// #if STM32_HAS_GPIOK || defined(__DOXYGEN__) +// gpio_setup_t PKData; +// #endif +} gpio_config_t; + +/** + * @brief STM32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +// #if STM32_HAS_GPIOF +// {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, +// VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +// #endif +// #if STM32_HAS_GPIOG +// {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, +// VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +// #endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +// #if STM32_HAS_GPIOI +// {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, +// VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +// #endif +// #if STM32_HAS_GPIOJ +// {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, +// VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +// #endif +// #if STM32_HAS_GPIOK +// {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, +// VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +// #endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB1(STM32_GPIO_EN_MASK); + rccEnableAHB1(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +// #if STM32_HAS_GPIOF +// gpio_init(GPIOF, &gpio_default_config.PFData); +// #endif +// #if STM32_HAS_GPIOG +// gpio_init(GPIOG, &gpio_default_config.PGData); +// #endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +// #if STM32_HAS_GPIOI +// gpio_init(GPIOI, &gpio_default_config.PIData); +// #endif +// #if STM32_HAS_GPIOJ +// gpio_init(GPIOJ, &gpio_default_config.PJData); +// #endif +// #if STM32_HAS_GPIOK +// gpio_init(GPIOK, &gpio_default_config.PKData); +// #endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + * else. + */ +void __early_init(void) { + + stm32_gpio_init(); + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + + return !palReadLine(LINE_SD_DETECT); +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { + +} \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/board.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/board.h new file mode 100644 index 00000000..11a4490d --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/board.h @@ -0,0 +1,976 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef BOARD_H +#define BOARD_H + +/* + * Board identifier. + */ +#define BOARD_MBN_QUAIL +#define BOARD_NAME "Mikrobus.Net QUAIL" + +#define BOARD_OTG_NOVBUSSENS + +/* + * Board oscillators-related settings. + * NOTE: LSE not fitted. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768U +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 12000000U +#endif + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U + +/* + * MCU type as defined in the ST header. + */ +#define STM32F427xx + +/* + * IO pins assignments. + */ +#define GPIOA_PA0 0U +#define GPIOA_INT1 1U +#define GPIOA_RST1 2U +#define GPIOA_CS1 3U +#define GPIOA_AN2 4U +#define GPIOA_AN4 5U +#define GPIOA_AN1 6U +#define GPIOA_AN3 7U +#define GPIOA_FLASH_HOLD 8U +#define GPIOA_TX4 9U +#define GPIOA_RX4 10U +#define GPIOA_OTG_FS_DM 11U +#define GPIOA_OTG_FS_DP 12U +#define GPIOA_FLASH_CS 13U +#define GPIOA_INT4 14U +#define GPIOA_GPIO1 15U + +#define GPIOB_GPIO2 0U +#define GPIOB_PB1 1U +#define GPIOB_BOOT1 2U +#define GPIOB_SPI1_CLK 3U +#define GPIOB_SPI1_MISO 4U +#define GPIOB_SPI1_MOSI 5U +#define GPIOB_I2C1_SCL 6U +#define GPIOB_I2C1_SDA 7U +#define GPIOB_PB8 8U +#define GPIOB_INT2 9U +#define GPIOB_GPIO3 10U +#define GPIOB_GPIO4 11U +#define GPIOB_GPIO5 12U +#define GPIOB_GPIO6 13U +#define GPIOB_OTG_HS_DM 14U +#define GPIOB_OTG_HS_DP 15U + +#define GPIOC_ID0 0U +#define GPIOC_ID1 1U +#define GPIOC_ID2 2U +#define GPIOC_LED3 3U +#define GPIOC_GPIO7 4U +#define GPIOC_GPIO8 5U +#define GPIOC_TX3 6U +#define GPIOC_RX3 7U +#define GPIOC_INT3 8U +#define GPIOC_FLASH_WP 9U +#define GPIOC_SPI3_CLK 10U +#define GPIOC_SPI3_MISO 11U +#define GPIOC_SPI3_MOSI 12U +#define GPIOC_GPIO9 13U +#define GPIOC_OSC32_IN 14U +#define GPIOC_OSC32_OUT 15U + +#define GPIOD_RST4 0U +#define GPIOD_CS4 1U +#define GPIOD_GPIO10 2U +#define GPIOD_GPIO11 3U +#define GPIOD_GPIO12 4U +#define GPIOD_TX2 5U +#define GPIOD_RX2 6U +#define GPIOD_GPIO13 7U +#define GPIOD_TX1 8U +#define GPIOD_RX1 9U +#define GPIOD_GPIO14 10U +#define GPIOD_CS3 11U +#define GPIOD_RST3 12U +#define GPIOD_PWM3 13U +#define GPIOD_PWM4 14U +#define GPIOD_PWM2 15U + +#define GPIOE_CS2 0U +#define GPIOE_RST2 1U +#define GPIOE_GPIO15 2U +#define GPIOE_GPIO16 3U +#define GPIOE_GPIO17 4U +#define GPIOE_GPIO18 5U +#define GPIOE_GPIO19 6U +#define GPIOE_GPIO20 7U +#define GPIOE_GPIO21 8U +#define GPIOE_PWM1 9U +#define GPIOE_LED2 10U +#define GPIOE_GPIO22 11U +#define GPIOE_USB_DETECT 12U +#define GPIOE_GPIO23 13U +#define GPIOE_GPIO24 14U +#define GPIOE_LED1 15U + +#define GPIOH_OSC_IN 0U +#define GPIOH_OSC_OUT 1U +#define GPIOH_PIN2 2U +#define GPIOH_PIN3 3U +#define GPIOH_PIN4 4U +#define GPIOH_PIN5 5U +#define GPIOH_PIN6 6U +#define GPIOH_PIN7 7U +#define GPIOH_PIN8 8U +#define GPIOH_PIN9 9U +#define GPIOH_PIN10 10U +#define GPIOH_PIN11 11U +#define GPIOH_PIN12 12U +#define GPIOH_PIN13 13U +#define GPIOH_PIN14 14U +#define GPIOH_PIN15 15U + +/* + * IO lines assignments. + */ + + + // Christophe : what are those "lines" used for ? + +#define LINE_INT1 PAL_LINE(GPIOA, 1U) +#define LINE_RST1 PAL_LINE(GPIOA, 2U) +#define LINE_CS1 PAL_LINE(GPIOA, 3U) +#define LINE_AN2 PAL_LINE(GPIOA, 4U) +#define LINE_AN4 PAL_LINE(GPIOA, 5U) +#define LINE_AN1 PAL_LINE(GPIOA, 6U) +#define LINE_AN3 PAL_LINE(GPIOA, 7U) +#define LINE_FLASH_HOLD PAL_LINE(GPIOA, 8U) +#define LINE_TX4 PAL_LINE(GPIOA, 9U) +#define LINE_RX4 PAL_LINE(GPIOA, 10U) +#define LINE_OTG_FS_DM PAL_LINE(GPIOA, 11U) +#define LINE_OTG_FS_DP PAL_LINE(GPIOA, 12U) +#define LINE_FLASH_CS PAL_LINE(GPIOA, 13U) +#define LINE_INT4 PAL_LINE(GPIOA, 14U) +#define LINE_GPIO1 PAL_LINE(GPIOA, 15U) + +#define LINE_GPIO2 PAL_LINE(GPIOB, 0U) +#define LINE_PB1 PAL_LINE(GPIOB, 1U) +#define LINE_BOOT1 PAL_LINE(GPIOB, 2U) +#define LINE_SPI1_CLK PAL_LINE(GPIOB, 3U) +#define LINE_SPI1_MISO PAL_LINE(GPIOB, 4U) +#define LINE_SPI1_MOSI PAL_LINE(GPIOB, 5U) +#define LINE_I2C1_SCL PAL_LINE(GPIOB, 6U) +#define LINE_I2C1_SDA PAL_LINE(GPIOB, 7U) +#define LINE_PB8 PAL_LINE(GPIOB, 8U) +#define LINE_INT2 PAL_LINE(GPIOB, 9U) +#define LINE_GPIO3 PAL_LINE(GPIOB, 10U) +#define LINE_GPIO4 PAL_LINE(GPIOB, 11U) +#define LINE_GPIO5 PAL_LINE(GPIOB, 12U) +#define LINE_GPIO6 PAL_LINE(GPIOB, 13U) +#define LINE_OTG_HS_DM PAL_LINE(GPIOB, 14U) +#define LINE_OTG_HS_DP PAL_LINE(GPIOB, 15U) + +#define LINE_ID0 PAL_LINE(GPIOC, 0U) +#define LINE_ID1 PAL_LINE(GPIOC, 1U) +#define LINE_ID2 PAL_LINE(GPIOC, 2U) +#define LINE_LED3 PAL_LINE(GPIOC, 3U) +#define LINE_GPIO7 PAL_LINE(GPIOC, 4U) +#define LINE_GPIO8 PAL_LINE(GPIOC, 5U) +#define LINE_TX3 PAL_LINE(GPIOC, 6U) +#define LINE_RX3 PAL_LINE(GPIOC, 7U) +#define LINE_INT3 PAL_LINE(GPIOC, 8U) +#define LINE_FLASH_WP PAL_LINE(GPIOC, 9U) +#define LINE_SPI3_CLK PAL_LINE(GPIOC, 10U) +#define LINE_SPI3_MISO PAL_LINE(GPIOC, 11U) +#define LINE_SPI3_MOSI PAL_LINE(GPIOC, 12U) +#define LINE_GPIO9 PAL_LINE(GPIOC, 13U) +#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) +#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) + +#define LINE_RST4 PAL_LINE(GPIOD, 0U) +#define LINE_CS4 PAL_LINE(GPIOD, 1U) +#define LINE_CS5 PAL_LINE(GPIOD, 2U) +#define LINE_GPIO11 PAL_LINE(GPIOD, 3U) +#define LINE_GPIO12 PAL_LINE(GPIOD, 4U) +#define LINE_CS6 PAL_LINE(GPIOD, 5U) +#define LINE_RX2 PAL_LINE(GPIOD, 6U) +#define LINE_CS7 PAL_LINE(GPIOD, 7U) +#define LINE_TX1 PAL_LINE(GPIOD, 8U) +#define LINE_RX1 PAL_LINE(GPIOD, 9U) +#define LINE_GPIO14 PAL_LINE(GPIOD, 10U) +#define LINE_CS3 PAL_LINE(GPIOD, 11U) +#define LINE_RST3 PAL_LINE(GPIOD, 12U) +#define LINE_PWM3 PAL_LINE(GPIOD, 13U) +#define LINE_PWM4 PAL_LINE(GPIOD, 14U) +#define LINE_PWM2 PAL_LINE(GPIOD, 15U) + +#define LINE_CS2 PAL_LINE(GPIOE, 0U) +#define LINE_RST2 PAL_LINE(GPIOE, 1U) +#define LINE_GPIO15 PAL_LINE(GPIOE, 2U) +#define LINE_GPIO16 PAL_LINE(GPIOE, 3U) +#define LINE_GPIO17 PAL_LINE(GPIOE, 4U) +#define LINE_GPIO18 PAL_LINE(GPIOE, 5U) +#define LINE_GPIO19 PAL_LINE(GPIOE, 6U) +#define LINE_GPIO20 PAL_LINE(GPIOE, 7U) +#define LINE_GPIO21 PAL_LINE(GPIOE, 8U) +#define LINE_PWM1 PAL_LINE(GPIOE, 9U) +#define LINE_LED2 PAL_LINE(GPIOE, 10U) +#define LINE_GPIO22 PAL_LINE(GPIOE, 11U) +#define LINE_USB_DETECT PAL_LINE(GPIOE, 12U) +#define LINE_GPIO23 PAL_LINE(GPIOE, 13U) +#define LINE_GPIO24 PAL_LINE(GPIOE, 14U) +#define LINE_LED1 PAL_LINE(GPIOE, 15U) + +#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) +#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) + + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * GPIOA setup: + * + * PA0 - N/A + * PA1 - INT1 (input floating). + * PA2 - RST1 (input floating). + * PA3 - CS1 (alternate 14). + * PA4 - AN2 (alternate 14). + * PA5 - AN5 (input pullup). + * PA6 - AN1 (alternate 14). + * PA7 - AN3 (input pullup). + * PA8 - FLASH_HOLD (alternate 4). + * PA9 - TX4 (alternate 7). + * PA10 - RX4 (alternate 7). + * PA11 - OTG_FS_DM (alternate 14). + * PA12 - OTG_FS_DP (alternate 14). + * PA13 - FLASH_CS (alternate 0). + * PA14 - INT4 (alternate 0). + * PA15 - GPIO1 (input floating). + */ +#define VAL_GPIOA_MODER (PIN_MODE_ALTERNATE(GPIOA_PA0) | \ + PIN_MODE_INPUT(GPIOA_INT1) | \ + PIN_MODE_INPUT(GPIOA_RST1) | \ + PIN_MODE_OUTPUT(GPIOA_CS1) | \ + PIN_MODE_ANALOG(GPIOA_AN2) | \ + PIN_MODE_ANALOG(GPIOA_AN4) | \ + PIN_MODE_ANALOG(GPIOA_AN1) | \ + PIN_MODE_ANALOG(GPIOA_AN3) | \ + PIN_MODE_OUTPUT(GPIOA_FLASH_HOLD) | \ + PIN_MODE_ALTERNATE(GPIOA_TX4) | \ + PIN_MODE_ALTERNATE(GPIOA_RX4) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ + PIN_MODE_OUTPUT(GPIOA_FLASH_CS) | \ + PIN_MODE_INPUT(GPIOA_INT4) | \ + PIN_MODE_INPUT(GPIOA_GPIO1)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PA0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_INT1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_RST1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_CS1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_AN2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_AN4) | \ + PIN_OTYPE_PUSHPULL(GPIOA_AN1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_AN3) | \ + PIN_OTYPE_PUSHPULL(GPIOA_FLASH_HOLD) | \ + PIN_OTYPE_PUSHPULL(GPIOA_TX4) | \ + PIN_OTYPE_PUSHPULL(GPIOA_RX4) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \ + PIN_OTYPE_PUSHPULL(GPIOA_FLASH_CS) | \ + PIN_OTYPE_PUSHPULL(GPIOA_INT4) | \ + PIN_OTYPE_PUSHPULL(GPIOA_GPIO1)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_PA0) | \ + PIN_OSPEED_HIGH(GPIOA_INT1) | \ + PIN_OSPEED_HIGH(GPIOA_RST1) | \ + PIN_OSPEED_HIGH(GPIOA_CS1) | \ + PIN_OSPEED_HIGH(GPIOA_AN2) | \ + PIN_OSPEED_HIGH(GPIOA_AN4) | \ + PIN_OSPEED_HIGH(GPIOA_AN1) | \ + PIN_OSPEED_HIGH(GPIOA_AN3) | \ + PIN_OSPEED_HIGH(GPIOA_FLASH_HOLD) | \ + PIN_OSPEED_HIGH(GPIOA_TX4) | \ + PIN_OSPEED_HIGH(GPIOA_RX4) | \ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_OSPEED_HIGH(GPIOA_FLASH_CS) | \ + PIN_OSPEED_HIGH(GPIOA_INT4) | \ + PIN_OSPEED_HIGH(GPIOA_GPIO1)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_PA0) | \ + PIN_PUPDR_FLOATING(GPIOA_INT1) | \ + PIN_PUPDR_FLOATING(GPIOA_RST1) | \ + PIN_PUPDR_FLOATING(GPIOA_CS1) | \ + PIN_PUPDR_FLOATING(GPIOA_AN2) | \ + PIN_PUPDR_FLOATING(GPIOA_AN4) | \ + PIN_PUPDR_FLOATING(GPIOA_AN1) | \ + PIN_PUPDR_FLOATING(GPIOA_AN3) | \ + PIN_PUPDR_FLOATING(GPIOA_FLASH_HOLD) | \ + PIN_PUPDR_FLOATING(GPIOA_TX4) | \ + PIN_PUPDR_FLOATING(GPIOA_RX4) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \ + PIN_PUPDR_FLOATING(GPIOA_FLASH_CS) | \ + PIN_PUPDR_FLOATING(GPIOA_INT4) | \ + PIN_PUPDR_FLOATING(GPIOA_GPIO1)) +#define VAL_GPIOA_ODR (PIN_ODR_LOW(GPIOA_PA0) | \ + PIN_ODR_LOW(GPIOA_INT1) | \ + PIN_ODR_LOW(GPIOA_RST1) | \ + PIN_ODR_LOW(GPIOA_CS1) | \ + PIN_ODR_LOW(GPIOA_AN2) | \ + PIN_ODR_LOW(GPIOA_AN4) | \ + PIN_ODR_LOW(GPIOA_AN1) | \ + PIN_ODR_LOW(GPIOA_AN3) | \ + PIN_ODR_HIGH(GPIOA_FLASH_HOLD) | \ + PIN_ODR_LOW(GPIOA_TX4) | \ + PIN_ODR_LOW(GPIOA_RX4) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_ODR_HIGH(GPIOA_FLASH_CS) | \ + PIN_ODR_LOW(GPIOA_INT4) | \ + PIN_ODR_LOW(GPIOA_GPIO1)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PA0, 0U) | \ + PIN_AFIO_AF(GPIOA_INT1, 0U) | \ + PIN_AFIO_AF(GPIOA_RST1, 0U) | \ + PIN_AFIO_AF(GPIOA_CS1, 0U) | \ + PIN_AFIO_AF(GPIOA_AN2, 0U) | \ + PIN_AFIO_AF(GPIOA_AN4, 0U) | \ + PIN_AFIO_AF(GPIOA_AN1, 0U) | \ + PIN_AFIO_AF(GPIOA_AN3, 0U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_FLASH_HOLD, 0U) | \ + PIN_AFIO_AF(GPIOA_TX4, 7U) | \ + PIN_AFIO_AF(GPIOA_RX4, 7U) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10U) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10U) | \ + PIN_AFIO_AF(GPIOA_FLASH_CS, 0U) | \ + PIN_AFIO_AF(GPIOA_INT4, 0U) | \ + PIN_AFIO_AF(GPIOA_GPIO1, 0U)) + +/* + * GPIOB setup: + * + * PB0 - GPIO2 (alternate 14). + * PB1 - PB1 (alternate 14). + * PB2 - BOOT1 (input pullup). + * PB3 - SPI1_CLK (alternate 0). + * PB4 - SPI1_MISO (input pullup). + * PB5 - SPI1_MOSI (alternate 12). + * PB6 - I2C1_SCL (alternate 12). + * PB7 - PIN7 (input pullup). + * PB8 - PB8 (alternate 14). + * PB9 - INT2 (alternate 14). + * PB10 - GPIO3 (alternate 14). + * PB11 - GPIO4 (alternate 14). + * PB12 - GPIO5 (alternate 12). + * PB13 - GPIO6 (input pulldown). + * PB14 - OTG_HS_DM (alternate 12). + * PB15 - OTG_HS_DP (alternate 12). + */ +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_GPIO2) | \ + PIN_MODE_ALTERNATE(GPIOB_PB1) | \ + PIN_MODE_ALTERNATE(GPIOB_BOOT1) | \ + PIN_MODE_ALTERNATE(GPIOB_SPI1_CLK) | \ + PIN_MODE_ALTERNATE(GPIOB_SPI1_MISO) | \ + PIN_MODE_ALTERNATE(GPIOB_SPI1_MOSI) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ + PIN_MODE_INPUT(GPIOB_PB8) | \ + PIN_MODE_INPUT(GPIOB_INT2) | \ + PIN_MODE_INPUT(GPIOB_GPIO3) | \ + PIN_MODE_INPUT(GPIOB_GPIO4) | \ + PIN_MODE_INPUT(GPIOB_GPIO5) | \ + PIN_MODE_INPUT(GPIOB_GPIO6) | \ + PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DM) | \ + PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_GPIO2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PB1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SPI1_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SPI1_MISO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SPI1_MOSI) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PB8) | \ + PIN_OTYPE_PUSHPULL(GPIOB_INT2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_GPIO3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_GPIO4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_GPIO5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_GPIO6) |\ + PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_GPIO2) | \ + PIN_OSPEED_HIGH(GPIOB_PB1) | \ + PIN_OSPEED_HIGH(GPIOB_BOOT1) | \ + PIN_OSPEED_HIGH(GPIOB_SPI1_CLK) | \ + PIN_OSPEED_HIGH(GPIOB_SPI1_MISO) | \ + PIN_OSPEED_HIGH(GPIOB_SPI1_MOSI) | \ + PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ + PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ + PIN_OSPEED_HIGH(GPIOB_PB8) | \ + PIN_OSPEED_HIGH(GPIOB_INT2) | \ + PIN_OSPEED_HIGH(GPIOB_GPIO3) | \ + PIN_OSPEED_HIGH(GPIOB_GPIO4) | \ + PIN_OSPEED_HIGH(GPIOB_GPIO5) | \ + PIN_OSPEED_HIGH(GPIOB_GPIO6) |\ + PIN_OSPEED_HIGH(GPIOB_OTG_HS_DM) | \ + PIN_OSPEED_HIGH(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_GPIO2) | \ + PIN_PUPDR_FLOATING(GPIOB_PB1) | \ + PIN_PUPDR_FLOATING(GPIOB_BOOT1) | \ + PIN_PUPDR_FLOATING(GPIOB_SPI1_CLK) | \ + PIN_PUPDR_FLOATING(GPIOB_SPI1_MISO) | \ + PIN_PUPDR_FLOATING(GPIOB_SPI1_MOSI) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \ + PIN_PUPDR_FLOATING(GPIOB_PB8) | \ + PIN_PUPDR_FLOATING(GPIOB_INT2) | \ + PIN_PUPDR_FLOATING(GPIOB_GPIO3) | \ + PIN_PUPDR_FLOATING(GPIOB_GPIO4) | \ + PIN_PUPDR_FLOATING(GPIOB_GPIO5) | \ + PIN_PUPDR_FLOATING(GPIOB_GPIO6) |\ + PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DM) | \ + PIN_PUPDR_FLOATING(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_ODR (PIN_ODR_LOW(GPIOB_GPIO2) | \ + PIN_ODR_LOW(GPIOB_PB1) | \ + PIN_ODR_HIGH(GPIOB_BOOT1) | \ + PIN_ODR_LOW(GPIOB_SPI1_CLK) | \ + PIN_ODR_LOW(GPIOB_SPI1_MISO) | \ + PIN_ODR_LOW(GPIOB_SPI1_MOSI) | \ + PIN_ODR_LOW(GPIOB_I2C1_SCL) | \ + PIN_ODR_LOW(GPIOB_I2C1_SDA) | \ + PIN_ODR_LOW(GPIOB_PB8) | \ + PIN_ODR_LOW(GPIOB_INT2) | \ + PIN_ODR_LOW(GPIOB_GPIO3) | \ + PIN_ODR_LOW(GPIOB_GPIO4) | \ + PIN_ODR_LOW(GPIOB_GPIO5) | \ + PIN_ODR_LOW(GPIOB_GPIO6) | \ + PIN_ODR_LOW(GPIOB_OTG_HS_DM) | \ + PIN_ODR_LOW(GPIOB_OTG_HS_DP)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_GPIO2, 0U) | \ + PIN_AFIO_AF(GPIOB_PB1, 0U) | \ + PIN_AFIO_AF(GPIOB_BOOT1, 0U) | \ + PIN_AFIO_AF(GPIOB_SPI1_CLK, 5U) | \ + PIN_AFIO_AF(GPIOB_SPI1_MISO, 5U) | \ + PIN_AFIO_AF(GPIOB_SPI1_MOSI, 5U) | \ + PIN_AFIO_AF(GPIOB_I2C1_SCL, 4U) | \ + PIN_AFIO_AF(GPIOB_I2C1_SDA, 4U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PB8, 0U) | \ + PIN_AFIO_AF(GPIOB_INT2, 0U) | \ + PIN_AFIO_AF(GPIOB_GPIO3, 0U) | \ + PIN_AFIO_AF(GPIOB_GPIO4, 0U) | \ + PIN_AFIO_AF(GPIOB_GPIO5, 0U) | \ + PIN_AFIO_AF(GPIOB_GPIO6, 0U) | \ + PIN_AFIO_AF(GPIOB_OTG_HS_DM, 12U) | \ + PIN_AFIO_AF(GPIOB_OTG_HS_DP, 12U)) + +/* + * GPIOC setup: + * + * PC0 - ID1 (alternate 12). + * PC1 - ID1 (output pushpull maximum). + * PC2 - ID2 (output pushpull maximum). + * PC3 - PIN3 (input pullup). + * PC4 - GPIO7 (output pushpull maximum). + * PC5 - GPIO8 (input floating). + * PC6 - TX3 (alternate 14). + * PC7 - RX3 (alternate 14). + * PC8 - PIN8 (input pullup). + * PC9 - FLASH_WP (alternate 4). + * PC10 - SPI3_CLK (alternate 14). + * PC11 - PIN11 (input pullup). + * PC12 - PIN12 (input pullup). + * PC13 - PIN13 (input pullup). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_ID0) | \ + PIN_MODE_INPUT(GPIOC_ID1) | \ + PIN_MODE_INPUT(GPIOC_ID2) | \ + PIN_MODE_OUTPUT(GPIOC_LED3) | \ + PIN_MODE_INPUT(GPIOC_GPIO7) | \ + PIN_MODE_INPUT(GPIOC_GPIO8) | \ + PIN_MODE_ALTERNATE(GPIOC_TX3) | \ + PIN_MODE_ALTERNATE(GPIOC_RX3) | \ + PIN_MODE_INPUT(GPIOC_INT3) | \ + PIN_MODE_OUTPUT(GPIOC_FLASH_WP) | \ + PIN_MODE_ALTERNATE(GPIOC_SPI3_CLK) | \ + PIN_MODE_ALTERNATE(GPIOC_SPI3_MISO) | \ + PIN_MODE_ALTERNATE(GPIOC_SPI3_MOSI) | \ + PIN_MODE_INPUT(GPIOC_GPIO9) | \ + PIN_MODE_ALTERNATE(GPIOC_OSC32_IN) | \ + PIN_MODE_ALTERNATE(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ID0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ID1) |\ + PIN_OTYPE_PUSHPULL(GPIOC_ID2) |\ + PIN_OTYPE_PUSHPULL(GPIOC_LED3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_GPIO7) | \ + PIN_OTYPE_PUSHPULL(GPIOC_GPIO8) | \ + PIN_OTYPE_PUSHPULL(GPIOC_TX3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_RX3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_INT3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_FLASH_WP) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SPI3_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SPI3_MISO) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SPI3_MOSI) | \ + PIN_OTYPE_PUSHPULL(GPIOC_GPIO9) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ID0) | \ + PIN_OSPEED_HIGH(GPIOC_ID1) | \ + PIN_OSPEED_HIGH(GPIOC_ID2) | \ + PIN_OSPEED_HIGH(GPIOC_LED3) | \ + PIN_OSPEED_HIGH(GPIOC_GPIO7) | \ + PIN_OSPEED_HIGH(GPIOC_GPIO8) | \ + PIN_OSPEED_HIGH(GPIOC_TX3) | \ + PIN_OSPEED_HIGH(GPIOC_RX3) | \ + PIN_OSPEED_HIGH(GPIOC_INT3) | \ + PIN_OSPEED_HIGH(GPIOC_FLASH_WP) | \ + PIN_OSPEED_HIGH(GPIOC_SPI3_CLK) | \ + PIN_OSPEED_HIGH(GPIOC_SPI3_MISO) | \ + PIN_OSPEED_HIGH(GPIOC_SPI3_MOSI) | \ + PIN_OSPEED_HIGH(GPIOC_GPIO9) | \ + PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \ + PIN_OSPEED_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_ID0) | \ + PIN_PUPDR_FLOATING(GPIOC_ID1) |\ + PIN_PUPDR_FLOATING(GPIOC_ID2) |\ + PIN_PUPDR_FLOATING(GPIOC_LED3) | \ + PIN_PUPDR_FLOATING(GPIOC_GPIO7) | \ + PIN_PUPDR_FLOATING(GPIOC_GPIO8) | \ + PIN_PUPDR_FLOATING(GPIOC_TX3) | \ + PIN_PUPDR_FLOATING(GPIOC_RX3) | \ + PIN_PUPDR_FLOATING(GPIOC_INT3) | \ + PIN_PUPDR_FLOATING(GPIOC_FLASH_WP) | \ + PIN_PUPDR_FLOATING(GPIOC_SPI3_CLK) | \ + PIN_PUPDR_FLOATING(GPIOC_SPI3_MISO) | \ + PIN_PUPDR_FLOATING(GPIOC_SPI3_MOSI) | \ + PIN_PUPDR_FLOATING(GPIOC_GPIO9) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_LOW(GPIOC_ID0) | \ + PIN_ODR_LOW(GPIOC_ID1) | \ + PIN_ODR_LOW(GPIOC_ID2) | \ + PIN_ODR_LOW(GPIOC_LED3) | \ + PIN_ODR_LOW(GPIOC_GPIO7) | \ + PIN_ODR_LOW(GPIOC_GPIO8) | \ + PIN_ODR_LOW(GPIOC_TX3) | \ + PIN_ODR_LOW(GPIOC_RX3) | \ + PIN_ODR_LOW(GPIOC_INT3) | \ + PIN_ODR_HIGH(GPIOC_FLASH_WP) | \ + PIN_ODR_LOW(GPIOC_SPI3_CLK) | \ + PIN_ODR_LOW(GPIOC_SPI3_MISO) | \ + PIN_ODR_LOW(GPIOC_SPI3_MOSI) | \ + PIN_ODR_LOW(GPIOC_GPIO9) | \ + PIN_ODR_LOW(GPIOC_OSC32_IN) | \ + PIN_ODR_LOW(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ID0, 0U) | \ + PIN_AFIO_AF(GPIOC_ID1, 0U) | \ + PIN_AFIO_AF(GPIOC_ID2, 0U) | \ + PIN_AFIO_AF(GPIOC_LED3, 0U) | \ + PIN_AFIO_AF(GPIOC_GPIO7, 0U) | \ + PIN_AFIO_AF(GPIOC_GPIO8, 0U) | \ + PIN_AFIO_AF(GPIOC_TX3, 8U) | \ + PIN_AFIO_AF(GPIOC_RX3, 8U)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_INT3, 0U) | \ + PIN_AFIO_AF(GPIOC_FLASH_WP, 0U) | \ + PIN_AFIO_AF(GPIOC_SPI3_CLK, 6U) | \ + PIN_AFIO_AF(GPIOC_SPI3_MISO, 6U) | \ + PIN_AFIO_AF(GPIOC_SPI3_MOSI, 6U) | \ + PIN_AFIO_AF(GPIOC_GPIO9, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) + +/* + * GPIOD setup: + * + * PD0 - RST4 (alternate 12). + * PD1 - CS4 (alternate 12). + * PD2 - PIN2 (input pullup). + * PD3 - GPIO11 (alternate 14). + * PD4 - GPIO12 (input pullup). + * PD5 - PIN5 (input pullup). + * PD6 - RX2 (alternate 14). + * PD7 - PIN7 (input pullup). + * PD8 - TX1 (alternate 12). + * PD9 - RX1 (alternate 12). + * PD10 - GPIO14 (alternate 12). + * PD11 - CS3 (input floating). + * PD12 - RST3 (output pushpull maximum). + * PD13 - PWM3 (output pushpull maximum). + * PD14 - PWM4 (alternate 12). + * PD15 - FMC_D1 (alternate 12). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_RST4) | \ + PIN_MODE_OUTPUT(GPIOD_CS4) | \ + PIN_MODE_INPUT(GPIOD_GPIO10) | \ + PIN_MODE_INPUT(GPIOD_GPIO11) | \ + PIN_MODE_INPUT(GPIOD_GPIO12) | \ + PIN_MODE_ALTERNATE(GPIOD_TX2) | \ + PIN_MODE_ALTERNATE(GPIOD_RX2) | \ + PIN_MODE_INPUT(GPIOD_GPIO13) | \ + PIN_MODE_ALTERNATE(GPIOD_TX1) | \ + PIN_MODE_ALTERNATE(GPIOD_RX1) | \ + PIN_MODE_INPUT(GPIOD_GPIO14) | \ + PIN_MODE_OUTPUT(GPIOD_CS3) | \ + PIN_MODE_INPUT(GPIOD_RST3) | \ + PIN_MODE_ALTERNATE(GPIOD_PWM3) | \ + PIN_MODE_ALTERNATE(GPIOD_PWM4) | \ + PIN_MODE_ALTERNATE(GPIOD_PWM2)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_RST4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_CS4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_GPIO10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_GPIO11) | \ + PIN_OTYPE_PUSHPULL(GPIOD_GPIO12) | \ + PIN_OTYPE_PUSHPULL(GPIOD_TX2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_RX2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_GPIO13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_TX1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_RX1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_GPIO14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_CS3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_RST3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PWM3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PWM4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PWM2)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_RST4) | \ + PIN_OSPEED_HIGH(GPIOD_CS4) | \ + PIN_OSPEED_HIGH(GPIOD_GPIO10) | \ + PIN_OSPEED_HIGH(GPIOD_GPIO11) | \ + PIN_OSPEED_HIGH(GPIOD_GPIO12) | \ + PIN_OSPEED_HIGH(GPIOD_TX2) | \ + PIN_OSPEED_HIGH(GPIOD_RX2) | \ + PIN_OSPEED_HIGH(GPIOD_GPIO13) | \ + PIN_OSPEED_HIGH(GPIOD_TX1) | \ + PIN_OSPEED_HIGH(GPIOD_RX1) | \ + PIN_OSPEED_HIGH(GPIOD_GPIO14) | \ + PIN_OSPEED_HIGH(GPIOD_CS3) | \ + PIN_OSPEED_HIGH(GPIOD_RST3) | \ + PIN_OSPEED_HIGH(GPIOD_PWM3) | \ + PIN_OSPEED_HIGH(GPIOD_PWM4) | \ + PIN_OSPEED_HIGH(GPIOD_PWM2)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_RST4) | \ + PIN_PUPDR_FLOATING(GPIOD_CS4) | \ + PIN_PUPDR_FLOATING(GPIOD_GPIO10) | \ + PIN_PUPDR_FLOATING(GPIOD_GPIO11) | \ + PIN_PUPDR_FLOATING(GPIOD_GPIO12) | \ + PIN_PUPDR_FLOATING(GPIOD_TX2) | \ + PIN_PUPDR_FLOATING(GPIOD_RX2) | \ + PIN_PUPDR_FLOATING(GPIOD_GPIO13) | \ + PIN_PUPDR_FLOATING(GPIOD_TX1) | \ + PIN_PUPDR_FLOATING(GPIOD_RX1) | \ + PIN_PUPDR_FLOATING(GPIOD_GPIO14) | \ + PIN_PUPDR_FLOATING(GPIOD_CS3) | \ + PIN_PUPDR_FLOATING(GPIOD_RST3) | \ + PIN_PUPDR_FLOATING(GPIOD_PWM3) | \ + PIN_PUPDR_FLOATING(GPIOD_PWM4) | \ + PIN_PUPDR_FLOATING(GPIOD_PWM2)) +#define VAL_GPIOD_ODR (PIN_ODR_LOW(GPIOD_RST4) | \ + PIN_ODR_LOW(GPIOD_CS4) | \ + PIN_ODR_LOW(GPIOD_GPIO10) | \ + PIN_ODR_LOW(GPIOD_GPIO11) | \ + PIN_ODR_LOW(GPIOD_GPIO12) | \ + PIN_ODR_LOW(GPIOD_TX2) | \ + PIN_ODR_LOW(GPIOD_RX2) | \ + PIN_ODR_LOW(GPIOD_GPIO13) | \ + PIN_ODR_LOW(GPIOD_TX1) | \ + PIN_ODR_LOW(GPIOD_RX1) | \ + PIN_ODR_LOW(GPIOD_GPIO14) | \ + PIN_ODR_LOW(GPIOD_CS3) | \ + PIN_ODR_LOW(GPIOD_RST3) | \ + PIN_ODR_LOW(GPIOD_PWM3) | \ + PIN_ODR_LOW(GPIOD_PWM4) | \ + PIN_ODR_LOW(GPIOD_PWM2)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_RST4, 0U) | \ + PIN_AFIO_AF(GPIOD_CS4, 0U) | \ + PIN_AFIO_AF(GPIOD_GPIO10, 0U) | \ + PIN_AFIO_AF(GPIOD_GPIO11, 0U) | \ + PIN_AFIO_AF(GPIOD_GPIO12, 0U) | \ + PIN_AFIO_AF(GPIOD_TX2, 7U) | \ + PIN_AFIO_AF(GPIOD_RX2, 7U) | \ + PIN_AFIO_AF(GPIOD_GPIO13, 0U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_TX1, 7U) | \ + PIN_AFIO_AF(GPIOD_RX1, 7U) | \ + PIN_AFIO_AF(GPIOD_GPIO14, 0U) | \ + PIN_AFIO_AF(GPIOD_CS3, 0U) | \ + PIN_AFIO_AF(GPIOD_RST3, 0U) | \ + PIN_AFIO_AF(GPIOD_PWM3, 2U) | \ + PIN_AFIO_AF(GPIOD_PWM4, 2U) | \ + PIN_AFIO_AF(GPIOD_PWM2, 2U)) + +/* + * GPIOE setup: + * + * PE0 - CS2 (alternate 12). + * PE1 - RST2 (alternate 12). + * PE2 - PIN2 (input pullup). + * PE3 - PIN3 (input pullup). + * PE4 - SPI1_MISO (input pullup). + * PE5 - PIN5 (input pullup). + * PE6 - PIN6 (input pullup). + * PE7 - GPIO20 (alternate 12). + * PE8 - GPIO21 (alternate 12). + * PE9 - PWM1 (alternate 12). + * PE10 - FMC_D7 (alternate 12). + * PE11 - GPIO22 (alternate 12). + * PE12 - USB_DETECT (alternate 12). + * PE13 - GPIO23 (alternate 12). + * PE14 - GPIO24 (alternate 12). + * PE15 - FMC_D12 (alternate 12). + */ +#define VAL_GPIOE_MODER (PIN_MODE_OUTPUT(GPIOE_CS2) | \ + PIN_MODE_INPUT(GPIOE_RST2) | \ + PIN_MODE_INPUT(GPIOE_GPIO15) | \ + PIN_MODE_INPUT(GPIOE_GPIO16) | \ + PIN_MODE_INPUT(GPIOE_GPIO17) | \ + PIN_MODE_INPUT(GPIOE_GPIO18) | \ + PIN_MODE_INPUT(GPIOE_GPIO19) | \ + PIN_MODE_INPUT(GPIOE_GPIO20) | \ + PIN_MODE_INPUT(GPIOE_GPIO21) | \ + PIN_MODE_ALTERNATE(GPIOE_PWM1) | \ + PIN_MODE_OUTPUT(GPIOE_LED2) | \ + PIN_MODE_INPUT(GPIOE_GPIO22) | \ + PIN_MODE_ALTERNATE(GPIOE_USB_DETECT) | \ + PIN_MODE_INPUT(GPIOE_GPIO23) | \ + PIN_MODE_INPUT(GPIOE_GPIO24) | \ + PIN_MODE_OUTPUT(GPIOE_LED1)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_CS2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_RST2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_GPIO15) | \ + PIN_OTYPE_PUSHPULL(GPIOE_GPIO16) | \ + PIN_OTYPE_PUSHPULL(GPIOE_GPIO17) | \ + PIN_OTYPE_PUSHPULL(GPIOE_GPIO18) | \ + PIN_OTYPE_PUSHPULL(GPIOE_GPIO19) | \ + PIN_OTYPE_PUSHPULL(GPIOE_GPIO20) | \ + PIN_OTYPE_PUSHPULL(GPIOE_GPIO21) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PWM1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_LED2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_GPIO22) | \ + PIN_OTYPE_PUSHPULL(GPIOE_USB_DETECT) | \ + PIN_OTYPE_PUSHPULL(GPIOE_GPIO23) | \ + PIN_OTYPE_PUSHPULL(GPIOE_GPIO24) | \ + PIN_OTYPE_PUSHPULL(GPIOE_LED1)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_CS2) | \ + PIN_OSPEED_HIGH(GPIOE_RST2) | \ + PIN_OSPEED_HIGH(GPIOE_GPIO15) | \ + PIN_OSPEED_HIGH(GPIOE_GPIO16) | \ + PIN_OSPEED_HIGH(GPIOE_GPIO17) | \ + PIN_OSPEED_HIGH(GPIOE_GPIO18) | \ + PIN_OSPEED_HIGH(GPIOE_GPIO19) | \ + PIN_OSPEED_HIGH(GPIOE_GPIO20) | \ + PIN_OSPEED_HIGH(GPIOE_GPIO21) | \ + PIN_OSPEED_HIGH(GPIOE_PWM1) | \ + PIN_OSPEED_HIGH(GPIOE_LED2) | \ + PIN_OSPEED_HIGH(GPIOE_GPIO22) | \ + PIN_OSPEED_HIGH(GPIOE_USB_DETECT) | \ + PIN_OSPEED_HIGH(GPIOE_GPIO23) | \ + PIN_OSPEED_HIGH(GPIOE_GPIO24) | \ + PIN_OSPEED_HIGH(GPIOE_LED1)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_CS2) | \ + PIN_PUPDR_FLOATING(GPIOE_RST2) | \ + PIN_PUPDR_FLOATING(GPIOE_GPIO15) | \ + PIN_PUPDR_FLOATING(GPIOE_GPIO16) | \ + PIN_PUPDR_FLOATING(GPIOE_GPIO17) | \ + PIN_PUPDR_FLOATING(GPIOE_GPIO18) | \ + PIN_PUPDR_FLOATING(GPIOE_GPIO19) | \ + PIN_PUPDR_FLOATING(GPIOE_GPIO20) | \ + PIN_PUPDR_FLOATING(GPIOE_GPIO21) | \ + PIN_PUPDR_FLOATING(GPIOE_PWM1) | \ + PIN_PUPDR_FLOATING(GPIOE_LED2) | \ + PIN_PUPDR_FLOATING(GPIOE_GPIO22) | \ + PIN_PUPDR_FLOATING(GPIOE_USB_DETECT) | \ + PIN_PUPDR_FLOATING(GPIOE_GPIO23) | \ + PIN_PUPDR_FLOATING(GPIOE_GPIO24) | \ + PIN_PUPDR_FLOATING(GPIOE_LED1)) +#define VAL_GPIOE_ODR (PIN_ODR_LOW(GPIOE_CS2) | \ + PIN_ODR_LOW(GPIOE_RST2) | \ + PIN_ODR_LOW(GPIOE_GPIO15) | \ + PIN_ODR_LOW(GPIOE_GPIO16) | \ + PIN_ODR_LOW(GPIOE_GPIO17) | \ + PIN_ODR_LOW(GPIOE_GPIO18) | \ + PIN_ODR_LOW(GPIOE_GPIO19) | \ + PIN_ODR_LOW(GPIOE_GPIO20) | \ + PIN_ODR_LOW(GPIOE_GPIO21) | \ + PIN_ODR_LOW(GPIOE_PWM1) | \ + PIN_ODR_LOW(GPIOE_LED2) | \ + PIN_ODR_LOW(GPIOE_GPIO22) | \ + PIN_ODR_LOW(GPIOE_USB_DETECT) | \ + PIN_ODR_LOW(GPIOE_GPIO23) | \ + PIN_ODR_LOW(GPIOE_GPIO24) | \ + PIN_ODR_LOW(GPIOE_LED1)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_CS2, 0U) | \ + PIN_AFIO_AF(GPIOE_RST2, 0U) | \ + PIN_AFIO_AF(GPIOE_GPIO15, 0U) | \ + PIN_AFIO_AF(GPIOE_GPIO16, 0U) | \ + PIN_AFIO_AF(GPIOE_GPIO17, 0U) | \ + PIN_AFIO_AF(GPIOE_GPIO18, 0U) | \ + PIN_AFIO_AF(GPIOE_GPIO19, 0U) | \ + PIN_AFIO_AF(GPIOE_GPIO20, 0U)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_GPIO21, 0U) | \ + PIN_AFIO_AF(GPIOE_PWM1, 1U) | \ + PIN_AFIO_AF(GPIOE_LED2, 0U) | \ + PIN_AFIO_AF(GPIOE_GPIO22, 0U) | \ + PIN_AFIO_AF(GPIOE_USB_DETECT, 0U) | \ + PIN_AFIO_AF(GPIOE_GPIO23, 0U) | \ + PIN_AFIO_AF(GPIOE_GPIO24, 0U) | \ + PIN_AFIO_AF(GPIOE_LED1, 0U)) + + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - PIN2 (input pullup). + * PH3 - PIN3 (input pullup). + * PH4 - SPI1_MISO (input pullup). + * PH5 - PIN5 (input pullup). + * PH6 - PIN6 (input pullup). + * PH7 - PIN7 (input pullup). + * PH8 - PIN8 (input pullup). + * PH9 - PIN9 (input pullup). + * PH10 - PIN10 (input pullup). + * PH11 - PIN11 (input pullup). + * PH12 - PIN12 (input pullup). + * PH13 - PIN13 (input pullup). + * PH14 - PIN14 (input pullup). + * PH15 - PIN15 (input pullup). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOH_PIN2) | \ + PIN_MODE_INPUT(GPIOH_PIN3) | \ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_INPUT(GPIOH_PIN5) | \ + PIN_MODE_INPUT(GPIOH_PIN6) | \ + PIN_MODE_INPUT(GPIOH_PIN7) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ + PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0U)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0U)) + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/common/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/common/CMakeLists.txt new file mode 100644 index 00000000..aa7f1d54 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/common/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/usbcfg.c") +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c") + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/common/Device_BlockStorage-DEBUG.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 00000000..a970be77 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,142 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +//16kB block +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 1 }, // 0x08000000 nanoBooter + { BlockRange_BLOCKTYPE_CODE , 2, 3 } // 0x08008000 nanoCLR +}; + +//64kB block +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 0x08010000 nanoCLR +}; + +//128kB block +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 3 }, // 0x08020000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 4, 6 }, // 0x080A0000 deployment +}; + +//16kB block +const BlockRange BlockRange4[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 3 } // 0x08100000 deployment +}; + +//64kB block +const BlockRange BlockRange5[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 0 } // 0x08110000 deployment +}; + +//128kB block +const BlockRange BlockRange6[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 6 } // 0x08120000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08010000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 7, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + + { + (0), // no attributes for this region + 0x08100000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange4), + BlockRange4, + }, + + { + (0), // no attributes for this region + 0x08110000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange5), + BlockRange5, + }, + + { + (0), // no attributes for this region + 0x08120000, // start address for block region + 7, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange6), + BlockRange6, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), // STM32 flash memory is XIP + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/common/Device_BlockStorage.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/common/Device_BlockStorage.c new file mode 100644 index 00000000..23428263 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/common/Device_BlockStorage.c @@ -0,0 +1,142 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +//16kB block +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 0 }, // 0x08000000 nanoBooter + { BlockRange_BLOCKTYPE_CODE , 1, 3 } // 0x08004000 nanoCLR +}; + +//64kB block +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 0x08010000 nanoCLR +}; + +//128kB block +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 }, // 0x08020000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 1, 6 }, // 0x08040000 deployment +}; + +//16kB block +const BlockRange BlockRange4[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 3 } // 0x08100000 deployment +}; + +//64kB block +const BlockRange BlockRange5[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 0 } // 0x08110000 deployment +}; + +//128kB block +const BlockRange BlockRange6[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 6 } // 0x08120000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08010000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 7, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + + { + (0), // no attributes for this region + 0x08100000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange4), + BlockRange4, + }, + + { + (0), // no attributes for this region + 0x08110000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange5), + BlockRange5, + }, + + { + (0), // no attributes for this region + 0x08120000, // start address for block region + 7, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange6), + BlockRange6, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), // STM32 flash memory is XIP + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/common/usbcfg.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/common/usbcfg.c new file mode 100644 index 00000000..7545d9e3 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/common/usbcfg.c @@ -0,0 +1,454 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "hal.h" + +/* Virtual serial port over USB.*/ +SerialUSBDriver SDU1; + +/* + * Endpoints to be used for USBD2. + */ +#define USBD2_DATA_REQUEST_EP 1 +#define USBD2_DATA_AVAILABLE_EP 1 +#define USBD2_INTERRUPT_REQUEST_EP 2 + +// address for device unique ID +// valid for STM32F4 series +#define DEVICE_ID1 (0x1FFF7A10) +#define DEVICE_ID2 (0x1FFF7A14) +#define DEVICE_ID3 (0x1FFF7A18) + +// // size of string serial is 36 = 2 + 5x2 + 26 from silicon unique ID precedeed of string "NANO_" and descriptor codes +// #define USB_SIZ_STRING_SERIAL 36 + +//////////////////////////////////////////////// +// vendor +#define USB_STRING_VENDOR L"Mikrobus.Net" +//////////////////////////////////////////////// + +// structure for USB Vendor with Unicode string +typedef struct usb_string_vendor +{ + uint8_t bLength; + uint8_t bDescriptorType; + wchar_t bPropertyData[sizeof(USB_STRING_VENDOR)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec) + +}usb_string_vendor; + + +///////////////////////////////////////////////////////////////////////// +// device description +#define USB_STRING_DEVICE_DESCRIPTION L"Quail Virtual COM Port" +///////////////////////////////////////////////////////////////////////// + +// structure for USB device descriptor with Unicode string +typedef struct usb_string_device_description +{ + uint8_t bLength; + uint8_t bDescriptorType; + wchar_t bPropertyData[sizeof(USB_STRING_DEVICE_DESCRIPTION)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec) + +}usb_string_device_description; + + +///////////////////////////////////////////////////////////////////////// +// device serial number +// this will produce a string with NANO_ prefix followed +// by the hexadecimal representation of the silicon unique ID of the CPU +#define USB_STRING_SERIAL_NUMBER L"NANO_xxxxxxxxxxx" +///////////////////////////////////////////////////////////////////////// +#define INDEX_OF_WCHAR_FOR_UNIQUE_ID 5 + +// structure for USB serial number descriptor with Unicode string +typedef struct usb_string_serial_number +{ + uint8_t bLength; + uint8_t bDescriptorType; + wchar_t bPropertyData[sizeof(USB_STRING_SERIAL_NUMBER)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec) + +}usb_string_serial_number; + + +/* + * USB Device Descriptor. + */ +static const uint8_t vcom_device_descriptor_data[] = { + USB_DESC_DEVICE (0x0200, /* bcdUSB (2.0). */ + 0x02, /* bDeviceClass (CDC). */ + 0x00, /* bDeviceSubClass. */ + 0x00, /* bDeviceProtocol. */ + 0x40, /* bMaxPacketSize. */ + 0x0483, /* idVendor (ST). */ + 0x5740, /* idProduct. */ + 0x0200, /* bcdDevice. */ + 1, /* iManufacturer. */ + 2, /* iProduct. */ + 3, /* iSerialNumber. */ + 1) /* bNumConfigurations. */ +}; + +/* + * Device Descriptor wrapper. + */ +static const USBDescriptor vcom_device_descriptor = { + sizeof vcom_device_descriptor_data, + vcom_device_descriptor_data +}; + +/* Configuration Descriptor tree for a CDC.*/ +static const uint8_t vcom_configuration_descriptor_data[] = { + /* Configuration Descriptor.*/ + USB_DESC_CONFIGURATION(0x0043, /* wTotalLength. */ + 0x02, /* bNumInterfaces. */ + 0x01, /* bConfigurationValue. */ + 0, /* iConfiguration. */ + 0xC0, /* bmAttributes (self powered). */ + 50), /* bMaxPower (100mA). */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x01, /* bNumEndpoints. */ + 0x02, /* bInterfaceClass (Communications + Interface Class, CDC section + 4.2). */ + 0x02, /* bInterfaceSubClass (Abstract + Control Model, CDC section 4.3). */ + 0x01, /* bInterfaceProtocol (AT commands, + CDC section 4.4). */ + 0), /* iInterface. */ + /* Header Functional Descriptor (CDC section 5.2.3).*/ + USB_DESC_BYTE (5), /* bLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header + Functional Descriptor. */ + USB_DESC_BCD (0x0110), /* bcdCDC. */ + /* Call Management Functional Descriptor. */ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */ + USB_DESC_BYTE (0x01), /* bDataInterface. */ + /* ACM Functional Descriptor.*/ + USB_DESC_BYTE (4), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract + Control Management Descriptor). */ + USB_DESC_BYTE (0x02), /* bmCapabilities. */ + /* Union Functional Descriptor.*/ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bMasterInterface (Communication + Class Interface). */ + USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class + Interface). */ + /* Endpoint 2 Descriptor.*/ + USB_DESC_ENDPOINT (USBD2_INTERRUPT_REQUEST_EP|0x80, + 0x03, /* bmAttributes (Interrupt). */ + 0x0008, /* wMaxPacketSize. */ + 0xFF), /* bInterval. */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x02, /* bNumEndpoints. */ + 0x0A, /* bInterfaceClass (Data Class + Interface, CDC section 4.5). */ + 0x00, /* bInterfaceSubClass (CDC section + 4.6). */ + 0x00, /* bInterfaceProtocol (CDC section + 4.7). */ + 0x00), /* iInterface. */ + /* Endpoint 3 Descriptor.*/ + USB_DESC_ENDPOINT (USBD2_DATA_AVAILABLE_EP, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00), /* bInterval. */ + /* Endpoint 1 Descriptor.*/ + USB_DESC_ENDPOINT (USBD2_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00) /* bInterval. */ +}; + +/* + * Configuration Descriptor wrapper. + */ +static const USBDescriptor vcom_configuration_descriptor = { + sizeof vcom_configuration_descriptor_data, + vcom_configuration_descriptor_data +}; + +/* + * U.S. English language identifier. + */ +static const uint8_t vcom_string0[] = { + USB_DESC_BYTE(4), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */ +}; + + +// Vendor string +static const usb_string_vendor usb_vendor = { + sizeof(usb_vendor), + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), + USB_STRING_VENDOR +}; + + +// Device Description string +static const usb_string_device_description usb_device_description = { + sizeof(usb_device_description), + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), + USB_STRING_DEVICE_DESCRIPTION +}; + + +// Serial Number string. +static usb_string_serial_number usb_serial_number = { + sizeof(usb_serial_number), + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), + USB_STRING_SERIAL_NUMBER +}; + + +/* + * Strings wrappers array. + */ +static const USBDescriptor vcom_strings[] = { + {sizeof vcom_string0, vcom_string0}, + {sizeof usb_vendor, (uint8_t*)(&usb_vendor)}, + {sizeof usb_device_description, (uint8_t*)(&usb_device_description)}, + {sizeof usb_serial_number, (uint8_t*)(&usb_serial_number)}, +}; + + +// Convert Hex 32Bits value into char +// value: value to convert +// pbuf: pointer to the buffer +// len: buffer length +void IntToUnicode(uint32_t value , uint8_t *pbuf, uint8_t len) +{ + uint8_t idx = 0; + + for( idx = 0; idx < len; idx ++) + { + if( ((value >> 28)) < 0xA ) + { + pbuf[ 2* idx] = (value >> 28) + '0'; + } + else + { + pbuf[2* idx] = (value >> 28) + 'A' - 10; + } + + value = value << 4; + + pbuf[ 2* idx + 1] = 0; + } +} + +// Create the serial number string descriptor +void Get_SerialNum(uint8_t* pbuf) +{ + uint32_t deviceserial0, deviceserial1, deviceserial2; + + deviceserial0 = *(uint32_t*)DEVICE_ID1; + deviceserial1 = *(uint32_t*)DEVICE_ID2; + deviceserial2 = *(uint32_t*)DEVICE_ID3; + + deviceserial0 += deviceserial2; + + if (deviceserial0 != 0) + { + IntToUnicode(deviceserial0, pbuf, 8); + pbuf += 16; + IntToUnicode(deviceserial1, pbuf, 4); + } +} + +/* + * Handles the GET_DESCRIPTOR callback. All required descriptors must be + * handled here. + */ +static const USBDescriptor *get_descriptor(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang) { + + (void)usbp; + (void)lang; + + switch (dtype) { + case USB_DESCRIPTOR_DEVICE: + return &vcom_device_descriptor; + case USB_DESCRIPTOR_CONFIGURATION: + return &vcom_configuration_descriptor; + case USB_DESCRIPTOR_STRING: + if (dindex < 4) + { + if(dindex == 3) + { + // request is for serial number + // get it from the silicon unique ID + Get_SerialNum((uint8_t*)&usb_serial_number.bPropertyData[INDEX_OF_WCHAR_FOR_UNIQUE_ID]); + } + + return &vcom_strings[dindex]; + } + } + return NULL; +} + +/** + * @brief IN EP1 state. + */ +static USBInEndpointState ep1instate; + +/** + * @brief OUT EP1 state. + */ +static USBOutEndpointState ep1outstate; + +/** + * @brief EP1 initialization structure (both IN and OUT). + */ +static const USBEndpointConfig ep1config = { + USB_EP_MODE_TYPE_BULK, + NULL, + sduDataTransmitted, + sduDataReceived, + 0x0040, + 0x0040, + &ep1instate, + &ep1outstate, + 2, + NULL +}; + +/** + * @brief IN EP2 state. + */ +static USBInEndpointState ep2instate; + +/** + * @brief EP2 initialization structure (IN only). + */ +static const USBEndpointConfig ep2config = { + USB_EP_MODE_TYPE_INTR, + NULL, + sduInterruptTransmitted, + NULL, + 0x0010, + 0x0000, + &ep2instate, + NULL, + 1, + NULL +}; + +/* + * Handles the USB driver global events. + */ +static void usb_event(USBDriver *usbp, usbevent_t event) { + extern SerialUSBDriver SDU1; + + switch (event) { + case USB_EVENT_ADDRESS: + return; + case USB_EVENT_CONFIGURED: + chSysLockFromISR(); + + if (usbp->state == USB_ACTIVE) { + /* Enables the endpoints specified into the configuration. + Note, this callback is invoked from an ISR so I-Class functions + must be used.*/ + usbInitEndpointI(usbp, USBD2_DATA_REQUEST_EP, &ep1config); + usbInitEndpointI(usbp, USBD2_INTERRUPT_REQUEST_EP, &ep2config); + + /* Resetting the state of the CDC subsystem.*/ + sduConfigureHookI(&SDU1); + } + else if (usbp->state == USB_SELECTED) { + usbDisableEndpointsI(usbp); + } + + chSysUnlockFromISR(); + return; + case USB_EVENT_RESET: + /* Falls into.*/ + case USB_EVENT_UNCONFIGURED: + /* Falls into.*/ + case USB_EVENT_SUSPEND: + chSysLockFromISR(); + + /* Disconnection event on suspend.*/ + sduSuspendHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_WAKEUP: + chSysLockFromISR(); + + /* Disconnection event on suspend.*/ + sduWakeupHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_STALLED: + return; + } + return; +} + +/* + * Handling messages not implemented in the default handler nor in the + * SerialUSB handler. + */ +static bool requests_hook(USBDriver *usbp) { + + if (((usbp->setup[0] & USB_RTYPE_RECIPIENT_MASK) == USB_RTYPE_RECIPIENT_INTERFACE) && + (usbp->setup[1] == USB_REQ_SET_INTERFACE)) { + usbSetupTransfer(usbp, NULL, 0, NULL); + return true; + } + return sduRequestsHook(usbp); +} + +/* + * Handles the USB driver global events. + */ +static void sof_handler(USBDriver *usbp) { + + (void)usbp; + + osalSysLockFromISR(); + sduSOFHookI(&SDU1); + osalSysUnlockFromISR(); +} + +/* + * USB driver configuration. + */ +const USBConfig usbcfg = { + usb_event, + get_descriptor, + requests_hook, + sof_handler +}; + +/* + * Serial over USB driver configuration. + */ +const SerialUSBConfig serusbcfg = { + &USBD1, + USBD2_DATA_REQUEST_EP, + USBD2_DATA_AVAILABLE_EP, + USBD2_INTERRUPT_REQUEST_EP +}; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/common/usbcfg.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/common/usbcfg.h new file mode 100644 index 00000000..167e1df8 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/common/usbcfg.h @@ -0,0 +1,17 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef USBCFG_H +#define USBCFG_H + +extern const USBConfig usbcfg; +extern SerialUSBConfig serusbcfg; +extern SerialUSBDriver SDU1; + +#endif /* USBCFG_H */ + +/** @} */ + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/CMakeLists.txt new file mode 100644 index 00000000..291f47e1 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/CMakeLists.txt @@ -0,0 +1,9 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# # append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/chconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/chconf.h new file mode 100644 index 00000000..57d60bed --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/chconf.h @@ -0,0 +1,616 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 10000 // this is 1 millisecond + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#define CH_CFG_INTERVALS_SIZE 32 + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_TIME_TYPES_SIZE 32 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES FALSE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS FALSE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT FALSE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES FALSE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_OBJ_FIFOS TRUE + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#define CH_CFG_USE_FACTORY FALSE + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 + +/** + * @brief Enables the registry of generic objects. + */ +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE + +/** + * @brief Enables factory for generic buffers. + */ +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE + +/** + * @brief Enables factory for semaphores. + */ +#define CH_CFG_FACTORY_SEMAPHORES TRUE + +/** + * @brief Enables factory for mailboxes. + */ +#define CH_CFG_FACTORY_MAILBOXES TRUE + +/** + * @brief Enables factory for objects FIFOs. + */ +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/halconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/halconf.h new file mode 100644 index 00000000..117bbda7 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/halconf.h @@ -0,0 +1,513 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/halconf_nf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/halconf_nf.h new file mode 100644 index 00000000..809a6cfa --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/halconf_nf.h @@ -0,0 +1,15 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +#endif // _HALCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/main.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/main.c new file mode 100644 index 00000000..6465edf2 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/main.c @@ -0,0 +1,69 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); + +// Application entry point. +int main(void) { + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // check for valid CLR image at address contiguous to nanoBooter + // this target DOES NOT have configuration block, so we need to use the __nanoImage_end__ address here + if(CheckValidCLRImage((uint32_t)&__nanoImage_end__)) + { + // there seems to be a valid CLR image + // launch nanoCLR + LaunchCLR((uint32_t)&__nanoImage_end__); + } + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // Initializes a serial-over-USB CDC driver. + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + // Activates the USB driver and then the USB bus pull-up on D+. + // Note, a delay is inserted in order to not have to disconnect the cable after a reset. + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1500); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // Normal main() thread + while (true) { + palSetPad(GPIOE, GPIOE_LED1); + osDelay(500); + palClearPad(GPIOE, GPIOE_LED1); + osDelay(500); + } +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/mbn_quail_booter-DEBUG.ld b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/mbn_quail_booter-DEBUG.ld new file mode 100644 index 00000000..505f0a7a --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/mbn_quail_booter-DEBUG.ld @@ -0,0 +1,80 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F427Vx memory setup. + * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash : org = 0x08000000, len = 32k /* space reserved for nanoBooter (1st two sectors 0x08000000 to 0x08007FFF)*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */ + ram1 : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20020000, len = 64k /* SRAM3 */ + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram4); + +/* Stacks rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/mbn_quail_booter.ld b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/mbn_quail_booter.ld new file mode 100644 index 00000000..31588162 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/mbn_quail_booter.ld @@ -0,0 +1,80 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F427Vx memory setup. + * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash : org = 0x08000000, len = 16k /* space reserved for nanoBooter (1st sector 0x08000000 to 0x08003FFF)*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */ + ram1 : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20020000, len = 64k /* SRAM3 */ + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram4); + +/* Stacks rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/mcuconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/mcuconf.h new file mode 100644 index 00000000..11c84d5f --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/mcuconf.h @@ -0,0 +1,335 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 6 +#define STM32_PLLN_VALUE 168 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 2 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 +#define STM32_I2SSRC STM32_I2SSRC_PLLI2S +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 2 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 250 +#define STM32_SDC_READ_TIMEOUT_MS 25 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/mcuconf_nf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/mcuconf_nf.h new file mode 100644 index 00000000..574b9636 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/mcuconf_nf.h @@ -0,0 +1,10 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/target_board.h.in b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/target_board.h.in new file mode 100644 index 00000000..19531d9c --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoBooter/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOBOOTER_H_ */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/CMakeLists.txt new file mode 100644 index 00000000..e5496b7e --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/chconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/chconf.h new file mode 100644 index 00000000..15a95e76 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/chconf.h @@ -0,0 +1,616 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 10000 // this is 1 millisecond + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#define CH_CFG_INTERVALS_SIZE 32 + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_TIME_TYPES_SIZE 32 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_OBJ_FIFOS TRUE + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#define CH_CFG_USE_FACTORY FALSE + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 + +/** + * @brief Enables the registry of generic objects. + */ +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE + +/** + * @brief Enables factory for generic buffers. + */ +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE + +/** + * @brief Enables factory for semaphores. + */ +#define CH_CFG_FACTORY_SEMAPHORES TRUE + +/** + * @brief Enables factory for mailboxes. + */ +#define CH_CFG_FACTORY_MAILBOXES TRUE + +/** + * @brief Enables factory for objects FIFOs. + */ +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/halconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/halconf.h new file mode 100644 index 00000000..a838d4cb --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/halconf.h @@ -0,0 +1,525 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +// #define HAL_USE_ADC TRUE +// #endif + +/** + * @brief Enables the CAN subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +// #define HAL_USE_CAN FALSE +// #endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +// /** +// * @brief Enables the DAC subsystem. +// */ +// #if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +// #define HAL_USE_DAC FALSE +// #endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +// this option is set at target_platform.h (from config file) +//#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +//#define HAL_USE_I2C TRUE +//#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +// #define HAL_USE_MAC TRUE +// #endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +// #define HAL_USE_PWM TRUE +// #endif + +/** + * @brief Enables the RTC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +// #define HAL_USE_RTC TRUE +// #endif + +/** + * @brief Enables the SDC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +// #define HAL_USE_SDC FALSE +// #endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + + +/** + * @brief Enables the SPI subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +// #define HAL_USE_SPI TRUE +// #endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +// #define HAL_USE_UART FALSE +// #endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +// #define HAL_USE_WDG FALSE +// #endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS TRUE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/halconf_nf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/halconf_nf.h new file mode 100644 index 00000000..5ac68c7c --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/halconf_nf.h @@ -0,0 +1,14 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +#endif // _HALCONF_NF_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/main.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/main.c new file mode 100644 index 00000000..18e0c329 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/main.c @@ -0,0 +1,102 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +// Using Devantech LCD03 display in I2C mode @ address 0xC8 + +#include +#include +#include + +#include "usbcfg.h" +#include +#include +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 4096, "ReceiverThread"); +// declare CLRStartup thread here +osThreadDef(CLRStartupThread, osPriorityNormal, 4096, "CLRStartupThread"); + +// Application entry point. +int main(void) { + + // find out wakeup reason + if((RTC->ISR & RTC_ISR_ALRAF) == RTC_ISR_ALRAF) + { + // standby, match WakeupReason_FromStandby enum + WakeupReasonStore = 1; + } + else if((PWR->CSR & PWR_CSR_WUF) == PWR_CSR_WUF) + { + // wake from pin, match WakeupReason_FromPin enum + WakeupReasonStore = 2; + } + else + { + // undetermined reason, match WakeupReason_Undetermined enum + WakeupReasonStore = 0; + } + + // first things first: need to clear any possible wakeup flags + // if this is not done here the next standby -> wakeup sequence won't work + CLEAR_BIT(RTC->CR, RTC_CR_ALRAIE); + CLEAR_BIT(RTC->ISR, RTC_ISR_ALRAF); + SET_BIT(PWR->CR, PWR_CR_CWUF); + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init SWO as soon as possible to make it available to output ASAP + #if (SWO_OUTPUT == TRUE) + SwoInit(); + #endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // start watchdog + /////////////////////////////////////////////////////////////////////////////////////////////////////// + // for STM32F4 family if watchdog is enabled can't use standby mode because the IWDG can't be stoped // + /////////////////////////////////////////////////////////////////////////////////////////////////////// + Watchdog_Init(); + + // Initializes a serial-over-USB CDC driver. + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + // Activates the USB driver and then the USB bus pull-up on D+. + // Note, a delay is inserted in order to not have to disconnect the cable after a reset + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1500); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // CLR settings to launch CLR thread + CLR_SETTINGS clrSettings; + (void)memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.EnterDebuggerLoopAfterExit = true; + + // create the CLR Startup thread + osThreadCreate(osThread(CLRStartupThread), &clrSettings); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + while (true) { + osDelay(100); + } +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/mbn_quail_CLR-DEBUG.ld b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/mbn_quail_CLR-DEBUG.ld new file mode 100644 index 00000000..d2ef582b --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/mbn_quail_CLR-DEBUG.ld @@ -0,0 +1,76 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F427Vx memory setup. + * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash : org = 0x08008000, len = 2M - 32k - 1408k /* flash size less the space reserved for nanoBooter and application deployment*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x080A0000, len = 1408k /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */ + ram1 : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20020000, len = 64k /* SRAM3 */ + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram4); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/mbn_quail_CLR.ld b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/mbn_quail_CLR.ld new file mode 100644 index 00000000..5a59730e --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/mbn_quail_CLR.ld @@ -0,0 +1,76 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F427Vx memory setup. + * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash : org = 0x08004000, len = 2M - 16k - 1792k /* flash size less the space reserved for nanoBooter and application deployment*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x08040000, len = 1792k /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */ + ram1 : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20020000, len = 64k /* SRAM3 */ + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram4); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/mcuconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/mcuconf.h new file mode 100644 index 00000000..0570b319 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/mcuconf.h @@ -0,0 +1,335 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 6 +#define STM32_PLLN_VALUE 168 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 2 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 +#define STM32_I2SSRC STM32_I2SSRC_PLLI2S +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 2 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 TRUE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 TRUE +#define STM32_PWM_USE_TIM8 TRUE +#define STM32_PWM_USE_TIM9 TRUE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 1000 +#define STM32_SDC_READ_TIMEOUT_MS 1000 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 TRUE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 TRUE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 TRUE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 TRUE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG TRUE + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/mcuconf_nf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/mcuconf_nf.h new file mode 100644 index 00000000..574b9636 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/mcuconf_nf.h @@ -0,0 +1,10 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/nanoHAL.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/nanoHAL.cpp new file mode 100644 index 00000000..076a50fc --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/nanoHAL.cpp @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +void HAL_EnterBooterMode() +{ +} + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/target_board.h.in b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/target_board.h.in new file mode 100644 index 00000000..b980bc05 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/nanoCLR/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOCLR_H_ */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_BlockStorage.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_BlockStorage.c new file mode 100644 index 00000000..9e7c7f55 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_BlockStorage.c @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice STM32Flash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &STM32Flash_BlockStorageInterface, &Device_BlockStorageConfig, false); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_BlockStorage.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_BlockStorage.h new file mode 100644 index 00000000..aa50b1b7 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_common.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_common.c new file mode 100644 index 00000000..ccee7c5e --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_common.c @@ -0,0 +1,31 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include "target_common.h" +#include + +HAL_SYSTEM_CONFIG HalSystemConfig = +{ + { true }, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, //ConvertCOM_DebugHandle(1), + 0, //ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + { RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size }, + { FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size } +}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; + +// this target use DFU for updates +uint32_t GetTargetCapabilities() +{ + return TargetCapabilities_DfuUpdate; +}; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_common.h.in b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_common.h.in new file mode 100644 index 00000000..f1449ae9 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_common.h.in @@ -0,0 +1,41 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x200000C0) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x00030000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x08000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00200000) + +///////////////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////// +#define TARGETNAMESTRING "@CHIBIOS_BOARD@" +#define PLATFORMNAMESTRING "STM32F4" +////////////////////////////////////////////// + +///////////////////////////////////// +//#define EVENTS_HEART_BEAT palToggleLine(GPIOE_LED1) +///////////////////////////////////// + +#endif /* _TARGET_COMMON_H_ */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_nf_devices_onewire_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_nf_devices_onewire_config.cpp new file mode 100644 index 00000000..5df22a7d --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_nf_devices_onewire_config.cpp @@ -0,0 +1,29 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_nf_devices_onewire_config.h" +#include + +/////////// +// UART6 // +/////////// + +// pin configuration for UART6 +// port for TX pin is: GPIOC +// TX pin: is GPIOC_6 +// GPIO alternate pin function is 8 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in STM32F405xx/STM32F407xx datasheet) +UART_CONFIG_PINS(6, GPIOC, 10, 8) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart6_TxBuffer[UART6_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart6_RxBuffer[UART6_RX_SIZE]; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_nf_devices_onewire_config.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_nf_devices_onewire_config.h new file mode 100644 index 00000000..d0fb1c87 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_nf_devices_onewire_config.h @@ -0,0 +1,17 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////// +// UART6 // +/////////// + +// enable USART6 +#define NF_ONEWIRE_STM32_UART_USE_USART6 TRUE + +// buffers size +// tx buffer size: 32 bytes +#define UART6_TX_SIZE 32 +// rx buffer size: 32 bytes +#define UART6_RX_SIZE 32 \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_system_devices_dac_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_system_devices_dac_config.cpp new file mode 100644 index 00000000..97181d6f --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_system_devices_dac_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T HAVE SUPPORT FOR DAC PINS // +////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_windows_devices_i2c_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_windows_devices_i2c_config.cpp new file mode 100644 index 00000000..18b1cd19 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_windows_devices_i2c_config.cpp @@ -0,0 +1,18 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for SCL pin is: GPIOB +// port for SDA pin is: GPIOB +// SCL pin: is GPIOB_6 +// SDA pin: is GPIOB_7 +// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, GPIOB, GPIOB, 6, 7, 4) diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_windows_devices_serialcommunication_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_windows_devices_serialcommunication_config.cpp new file mode 100644 index 00000000..d4957c6d --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_windows_devices_serialcommunication_config.cpp @@ -0,0 +1,131 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_windows_devices_serialcommunication_config.h" +#include + +/////////// +// UART1 // +/////////// + +// pin configuration for UART1 +// port for TX pin is: GPIOA +// port for RX pin is: GPIOA +// TX pin: is GPIOA_9 +// RX pin: is GPIOA_10 +// GPIO alternate pin function is 7 (see "Table 12. STM32F427xx and STM32F429xx alternate function mapping" in STM32F427xx and STM32F429xx datasheet) +UART_CONFIG_PINS(1, GPIOA, GPIOA, 9, 10, 7) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart1_TxBuffer[UART1_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart1_RxBuffer[UART1_RX_SIZE]; + +// initialization for UART1 +UART_INIT(1, UART1_TX_SIZE, UART1_RX_SIZE) + +// un-initialization for UART1 +UART_UNINIT(1) + + +/////////// +// UART2 // +/////////// + +// pin configuration for UART2 +// port for TX pin is: GPIOD +// port for RX pin is: GPIOD +// TX pin: is GPIOD_5 +// RX pin: is GPIOD_6 +// GPIO alternate pin function is 7 (see "Table 12. STM32F427xx and STM32F429xx alternate function mapping" in STM32F427xx and STM32F429xx datasheet) +UART_CONFIG_PINS(2, GPIOD, GPIOD, 5, 6, 7) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart2_TxBuffer[UART2_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart2_RxBuffer[UART2_RX_SIZE]; + +// initialization for UART2 +UART_INIT(2, UART2_TX_SIZE, UART2_RX_SIZE) + +// un-initialization for UART2 +UART_UNINIT(2) + + +/////////// +// UART3 // +/////////// + +// pin configuration for UART3 +// port for TX pin is: GPIOD +// port for RX pin is: GPIOD +// TX pin: is GPIOD_8 +// RX pin: is GPIOD_9 +// GPIO alternate pin function is 7 (see "Table 12. STM32F427xx and STM32F429xx alternate function mapping" in STM32F427xx and STM32F429xx datasheet) +UART_CONFIG_PINS(3, GPIOD, GPIOD, 8, 9, 7) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart3_TxBuffer[UART3_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart3_RxBuffer[UART3_RX_SIZE]; + +// initialization for UART3 +UART_INIT(3, UART3_TX_SIZE, UART3_RX_SIZE) + +// un-initialization for UART3 +UART_UNINIT(3) + + +// /////////// +// // UART6 // +// /////////// + +// // pin configuration for UART6 +// // port for TX pin is: GPIOC +// // port for RX pin is: GPIOC +// // TX pin: is GPIOC_6 +// // RX pin: is GPIOC_7 +// // GPIO alternate pin function is 8 (see "Table 12. STM32F427xx and STM32F429xx alternate function mapping" in STM32F427xx and STM32F429xx datasheet) +// UART_CONFIG_PINS(6, GPIOC, GPIOC, 6, 7, 8) + +// // buffers +// // buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// // because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +// #if defined(__GNUC__) +// __attribute__((aligned (32))) +// #endif +// uint8_t Uart6_TxBuffer[UART6_TX_SIZE]; + +// #if defined(__GNUC__) +// __attribute__((aligned (32))) +// #endif +// uint8_t Uart6_RxBuffer[UART6_RX_SIZE]; + +// // initialization for UART6 +// UART_INIT(6, UART6_TX_SIZE, UART6_RX_SIZE) + +// // un-initialization for UART6 +// UART_UNINIT(6) diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_windows_devices_serialcommunication_config.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_windows_devices_serialcommunication_config.h new file mode 100644 index 00000000..9f7ead72 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_windows_devices_serialcommunication_config.h @@ -0,0 +1,59 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////// +// UART1 // +/////////// + +// enable USART1 +#define NF_SERIAL_COMM_STM32_UART_USE_USART1 TRUE + +// buffers size +// tx buffer size: 256 bytes +#define UART1_TX_SIZE 256 +// rx buffer size: 256 bytes +#define UART1_RX_SIZE 256 + + +/////////// +// UART2 // +/////////// + +// enable USART2 +#define NF_SERIAL_COMM_STM32_UART_USE_USART2 TRUE + +// buffers size +// tx buffer size: 256 bytes +#define UART2_TX_SIZE 256 +// rx buffer size: 256 bytes +#define UART2_RX_SIZE 256 + + +/////////// +// UART3 // +/////////// + +// enable USART3 +#define NF_SERIAL_COMM_STM32_UART_USE_USART3 TRUE + +// buffers size +// tx buffer size: 256 bytes +#define UART3_TX_SIZE 256 +// rx buffer size: 256 bytes +#define UART3_RX_SIZE 256 + + +// /////////// +// // UART6 // +// /////////// + +// // enable USART6 +// #define NF_SERIAL_COMM_STM32_UART_USE_USART6 TRUE + +// // buffers size +// // tx buffer size: 256 bytes +// #define UART6_TX_SIZE 256 +// // rx buffer size: 256 bytes +// #define UART6_RX_SIZE 256 diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_windows_devices_spi_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_windows_devices_spi_config.cpp new file mode 100644 index 00000000..76238dbe --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/MBN_QUAIL/target_windows_devices_spi_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/CMakeLists.txt new file mode 100644 index 00000000..8fa69c82 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/CMakeLists.txt @@ -0,0 +1,242 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +cmake_minimum_required(VERSION 3.0) +ENABLE_LANGUAGE(ASM) + +# add header files with common OS definitions and board definitions specific for each image +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/target_common.h" @ONLY) + +set(NANOBOOTER_PROJECT_NAME "nanoBooter") +set(NANOCLR_PROJECT_NAME "nanoCLR") + +find_package(BuildUtils REQUIRED) +find_package(CHIBIOS REQUIRED) +find_package(ChibiOSnfOverlay REQUIRED) +find_package(WireProtocol REQUIRED) + +# packages for nanoFramework libraries +####################################### +# mandatory +find_package(NF_CoreCLR REQUIRED) + +####################################### +# optional + +# ChibiOS contrib repo +if(CHIBIOS_CONTRIB_REQUIRED) + find_package(ChibiOS-Contrib REQUIRED) +endif() + +# nF feature: debugger +if(NF_FEATURE_DEBUGGER) + find_package(NF_Debugger REQUIRED) + find_package(NF_Diagnostics REQUIRED) +endif() + +# nF feature: networking +if(USE_NETWORKING_OPTION) + find_package(CHIBIOS_LWIP REQUIRED) +endif() + +# nF feature: filesystem +if(USE_FILESYSTEM_OPTION) + find_package(CHIBIOS_FATFS REQUIRED) +endif() + +####################################### + +add_subdirectory("common") +add_subdirectory("nanoBooter") +add_subdirectory("nanoCLR") + +####################### +# nanoBooter executable + +add_executable( + # executables for project, project sources + ${NANOBOOTER_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + "${CMAKE_CURRENT_SOURCE_DIR}/target_BlockStorage.c" + + # need to add configuration manager to allow get/store configuration blocks + "${PROJECT_SOURCE_DIR}/src/HAL/nanoHAL_ConfigurationManager_stubs.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOBOOTER_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOBOOTER_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOBOOTER_SOURCES} + + ${CHIBIOS_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} +) + +####################### +# nanoCLR executable + +add_executable( + # executables for project, project sources + ${NANOCLR_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOCLR_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOCLR_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOCLR_SOURCES} + + ${CHIBIOS_SOURCES} + ${CHIBIOS_CONTRIB_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} + + # sources for nanoFramework libraries + ${NF_CoreCLR_SOURCES} + ${NF_Debugger_SOURCES} + ${NF_Diagnostics_SOURCES} + + # sources for ChibiOS FatFS + ${CHIBIOS_FATFS_SOURCES} + + # sources for nanoFramework APIs + ${TARGET_NANO_APIS_SOURCES} +) + +# add dependency from ChibiOS (this is required to make sure the ChibiOS repo is downloaded before the build starts) +add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf ChibiOS) +add_dependencies(${NANOCLR_PROJECT_NAME}.elf ChibiOS) + +# add dependencies from CHIBIOS_FILESYSTEM_COMPONENTS (this is required to make sure that ChibiOS filesystem components are unzip at the proper locations before the build starts) +# only required if filesystem is ON +if(USE_FILESYSTEM_OPTION) + add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf CHIBIOS_FILESYSTEM_COMPONENTS) + add_dependencies(${NANOCLR_PROJECT_NAME}.elf CHIBIOS_FILESYSTEM_COMPONENTS) +endif() + +# include common directories +include_directories( + ${CMAKE_CURRENT_BINARY_DIR} + ${CMAKE_CURRENT_SOURCE_DIR} + ${CMAKE_CURRENT_SOURCE_DIR}/common + ${PROJECT_SOURCE_DIR}/src/CLR/Core + ${PROJECT_SOURCE_DIR}/src/CLR/Include + ${PROJECT_SOURCE_DIR}/src/HAL/Include + ${PROJECT_SOURCE_DIR}/src/PAL/Include + + ${WireProtocol_INCLUDE_DIRS} + ${CHIBIOS_INCLUDE_DIRS} + ${ChibiOSnfOverlay_INCLUDE_DIRS} + ${CHIBIOS_CONTRIB_INCLUDE_DIRS} + + ${TARGET_CMSIS_COMMON_INCLUDE_DIRS} + ${TARGET_CHIBIOS_COMMON_INCLUDE_DIRS} +) + +# include directories for nanoBooter +target_include_directories(${NANOBOOTER_PROJECT_NAME}.elf PUBLIC + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter" + ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter + + ${TARGET_CMSIS_NANOBOOTER_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOBOOTER_INCLUDE_DIRS} +) + +# include directories for nanoCLR +target_include_directories(${NANOCLR_PROJECT_NAME}.elf PUBLIC + ${CMAKE_CURRENT_BINARY_DIR}/nanoCLR + ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR + + ${TARGET_CMSIS_NANOCLR_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOCLR_INCLUDE_DIRS} + + # directories for nanoFramework libraries + ${NF_CoreCLR_INCLUDE_DIRS} + ${NF_Debugger_INCLUDE_DIRS} + ${NF_Diagnostics_INCLUDE_DIRS} + + # includes for nanoFramework APIs + ${TARGET_NANO_APIS_INCLUDES} + + # includes for ChibiOS FatFS + ${CHIBIOS_FATFS_INCLUDE_DIRS} + + # includes for ChibiOS LwIP + ${CHIBIOS_LWIP_INCLUDE_DIRS} +) + +# set compiler options +nf_set_compiler_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_options(${NANOCLR_PROJECT_NAME}.elf) + +# set compiler definitions +nf_set_compiler_definitions(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_definitions(${NANOCLR_PROJECT_NAME}.elf) + +# set linker files +if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/netduino3wifi_booter-DEBUG.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/netduino3wifi_CLR-DEBUG.ld) +else() + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/netduino3wifi_booter.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/netduino3wifi_CLR.ld) +endif() + +# set linker options +nf_set_linker_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_linker_options(${NANOCLR_PROJECT_NAME}.elf) + +# add other linker flags +########################################################### +# the sizes of CRT heap and ChibiOS stacks are defined here +############################################################################ +# CRT heap is assigned to RAM4 region @ CCM SRAM so we are OK to use it all +############################################################################ +set_property(TARGET ${NANOBOOTER_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x400,--defsym=__crt_heap_size__=0x10000") +set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x10000") + +# generate output files +nf_generate_build_output_files(${NANOBOOTER_PROJECT_NAME}.elf) +nf_generate_build_output_files(${NANOCLR_PROJECT_NAME}.elf) + +# if HEX2DFU tool is available pack the binaries into a DFU package +if(HEX2DFU_TOOL_AVAILABLE) + + #################################################################################################### + ## when changing the linker file make sure to update the new addresses for the image files below ## + ## DO NOT use the leading 0x notation, just the address in plain hexadecimal formating ## + #################################################################################################### + + if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + NF_GENERATE_DFU_PACKAGE( + ${PROJECT_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin 08000000 + ${PROJECT_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin 08008000 + ${PROJECT_SOURCE_DIR}/build/nanobooter-nanoclr.dfu + ) + else() + NF_GENERATE_DFU_PACKAGE( + ${PROJECT_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin 08000000 + ${PROJECT_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin 08004000 + ${PROJECT_SOURCE_DIR}/build/nanobooter-nanoclr.dfu + ) + endif() + +endif() diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/README.md b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/README.md new file mode 100644 index 00000000..f42f6d25 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/README.md @@ -0,0 +1,28 @@ +## Configuration of Chibios, HAL and MCU ## + +In this folder you'll find a 'port' of the nanoframework to work on a WildernessLabs Netduino 3 Wifi board. You can find [here] some more information on the board specifics, used MCU, RAM and FLASH memory available. + + + +**NOTE: the configuration was successfully tested on a WildernessLabs NETDUINO3_WIFI board using the Serial over USB connection on USB port 1 that creates a virtual COM port.** + +## ADC configurations + +The following ADC channels (and respective GPIO pins) are available to the managed API, in the respective index: +- PC0, ADC1 IN10 +- PC1 ADC1 IN11 +- PC2 ADC2 IN14 +- PC3 ADC2 IN15 +- PC4 ADC3 IN12 +- PC5 ADC3 IN13 +- Temp Sensor ADC1 +- VrefInt ADC1 +- Vbatt ADC1 + +These first 6 channels are exposed in the board J4 connector as A0 to A5. + + +## Floating point + +The current build is set to add support for single-precision floating point. +Meaning that `System.Math` API supports only the `float` overloads. The `double` ones will throw a `NotImplementedException`. diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/board.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/board.c new file mode 100644 index 00000000..5d508db9 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/board.c @@ -0,0 +1,266 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +// #if STM32_HAS_GPIOF || defined(__DOXYGEN__) +// gpio_setup_t PFData; +// #endif +// #if STM32_HAS_GPIOG || defined(__DOXYGEN__) +// gpio_setup_t PGData; +// #endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +// #if STM32_HAS_GPIOI || defined(__DOXYGEN__) +// gpio_setup_t PIData; +// #endif +// #if STM32_HAS_GPIOJ || defined(__DOXYGEN__) +// gpio_setup_t PJData; +// #endif +// #if STM32_HAS_GPIOK || defined(__DOXYGEN__) +// gpio_setup_t PKData; +// #endif +} gpio_config_t; + +/** + * @brief STM32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +// #if STM32_HAS_GPIOF +// {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, +// VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +// #endif +// #if STM32_HAS_GPIOG +// {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, +// VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +// #endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +// #if STM32_HAS_GPIOI +// {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, +// VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +// #endif +// #if STM32_HAS_GPIOJ +// {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, +// VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +// #endif +// #if STM32_HAS_GPIOK +// {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, +// VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +// #endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB1(STM32_GPIO_EN_MASK); + rccEnableAHB1(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +// #if STM32_HAS_GPIOF +// gpio_init(GPIOF, &gpio_default_config.PFData); +// #endif +// #if STM32_HAS_GPIOG +// gpio_init(GPIOG, &gpio_default_config.PGData); +// #endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +// #if STM32_HAS_GPIOI +// gpio_init(GPIOI, &gpio_default_config.PIData); +// #endif +// #if STM32_HAS_GPIOJ +// gpio_init(GPIOJ, &gpio_default_config.PJData); +// #endif +// #if STM32_HAS_GPIOK +// gpio_init(GPIOK, &gpio_default_config.PKData); +// #endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + * else. + */ +void __early_init(void) { + + stm32_gpio_init(); + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + + return !palReadLine(LINE_SD_DETECT); +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { + +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/board.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/board.h new file mode 100644 index 00000000..b72dcb4e --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/board.h @@ -0,0 +1,893 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef BOARD_H +#define BOARD_H + +/* + * Board identifier. + */ +#define BOARD_NETDUINO3WIFI +#define BOARD_NAME "Netduino 3 Wifi" + +#define BOARD_OTG_NOVBUSSENS + +/* + * Board oscillators-related settings. + * NOTE: LSE not fitted. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768U +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 25000000U +#endif + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U + +/* + * MCU type as defined in the ST header. + */ +#define STM32F427xx + +/* + * IO pins assignments. + */ +#define GPIOA_D8 0U +#define GPIOA_D7 1U +#define GPIOA_D3 2U +#define GPIOA_D2 3U +#define GPIOA_CC_IRQ 4U +#define GPIOA_CC_SCK 5U +#define GPIOA_CC_MISO 6U +#define GPIOA_CC_MOSI 7U +#define GPIOA_STATE_LED 8U +#define GPIOA_VBUS 9U +#define GPIOA_USR_LED 10U +#define GPIOA_OTG_FS_DM 11U +#define GPIOA_OTG_FS_DP 12U +#define GPIOA_JTMS 13U +#define GPIOA_JTCK 14U +#define GPIOA_JTDI 15U + +#define GPIOB_MICROSD_CS 0U +#define GPIOB_MICROSD_CTRL 1U +#define GPIOB_BOOT1 2U +#define GPIOB_JTDO 3U +#define GPIOB_PB4 4U +#define GPIOB_SWITCH1 5U +#define GPIOB_I2C1_SCL 6U +#define GPIOB_I2C1_SDA 7U +#define GPIOB_D5 8U +#define GPIOB_D6 9U +#define GPIOB_D10 10U +#define GPIOB_MICROSD_INS 11U +#define GPIOB_D4 12U +#define GPIOB_D13 13U +#define GPIOB_D12 14U +#define GPIOB_D11 15U + +#define GPIOC_A0 0U +#define GPIOC_A1 1U +#define GPIOC_A2 2U +#define GPIOC_A3 3U +#define GPIOC_A4 4U +#define GPIOC_A5 5U +#define GPIOC_D1 6U +#define GPIOC_D0 7U +#define GPIOC_CC_CS 8U +#define GPIOC_LINK_LED 9U +#define GPIOC_SPI3_CLK 10U +#define GPIOC_SPI3_MISO 11U +#define GPIOC_SPI3_MOSI 12U +#define GPIOC_POWER_LED 13U +#define GPIOC_OSC32_IN 14U +#define GPIOC_OSC32_OUT 15U + +#define GPIOD_SPI_CS_GOPORT1 0U +#define GPIOD_SPI_CS_GOPORT2 1U +#define GPIOD_SPI_CS_GOPORT3 2U +#define GPIOD_CC_RTS 3U +#define GPIOD_CC_CTS 4U +#define GPIOD_CC_RX 5U +#define GPIOD_CC_TX 6U +#define GPIOD_PWR_ON_GOPORT1 7U +#define GPIOD_USART3_TX_GOPORT1 8U +#define GPIOD_USART3_RX_GOPORT1 9U +#define GPIOD_PWR_ON_GOPORT2 10U +#define GPIOD_SWITCH1 11U +#define GPIOD_PWR_ON_GOPORT3 12U +#define GPIOD_INT_GOPORT1 13U +#define GPIOD_INT_GOPORT2 14U +#define GPIOD_INT_GOPORT3 15U + +#define GPIOE_USART8_RX_GOPORT3 0U +#define GPIOE_USART8_TX_GOPORT3 1U +#define GPIOE_SPI4_SCK 2U +#define GPIOE_EN_UART_TX_PU_GOPORT1 3U +#define GPIOE_CC_HIB 4U +#define GPIOE_D9 5U +#define GPIOE_SPI4_MOSI 6U +#define GPIOE_USART7_RX_GOPORT2 7U +#define GPIOE_USART7_TX_GOPORT2 8U +#define GPIOE_LED_GOPORT1 9U +#define GPIOE_EN_UART_TX_PU_GOPORT2 10U +#define GPIOE_LED_GOPORT2 11U +#define GPIOE_EN_UART_TX_PU_GOPORT3 12U +#define GPIOE_SPI4_MISO 13U +#define GPIOE_LED_GOPORT3 14U +#define GPIOE_CC_TCXO_EN_SOP2 15U + +#define GPIOH_OSC_IN 0U +#define GPIOH_OSC_OUT 1U +#define GPIOH_PIN2 2U +#define GPIOH_PIN3 3U +#define GPIOH_PIN4 4U +#define GPIOH_PIN5 5U +#define GPIOH_PIN6 6U +#define GPIOH_PIN7 7U +#define GPIOH_PIN8 8U +#define GPIOH_PIN9 9U +#define GPIOH_PIN10 10U +#define GPIOH_PIN11 11U +#define GPIOH_PIN12 12U +#define GPIOH_PIN13 13U +#define GPIOH_PIN14 14U +#define GPIOH_PIN15 15U + +/* + * IO lines assignments. + */ +#define LINE_LED1 PAL_LINE(GPIOA, 10U) +#define LINE_SD_DETECT PAL_LINE(GPIOB, 11U) + +#define LINE_LED_GOPORT1 PAL_LINE(GPIOE, 9U) + +#define LINE_LED_GOPORT2 PAL_LINE(GPIOE, 11U) + +#define LINE_LED_GOPORT3 PAL_LINE(GPIOE, 14U) + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * GPIOA setup: + * + * PA0 - D8 + * PA1 - D7 + * PA2 - D3 + * PA3 - D2 + * PA4 - CC_IRQ + * PA5 - CC_SCK + * PA6 - CC_MISO + * PA7 - CC_MOSI + * PA8 - STATE_LED + * PA9 - VBUS + * PA10 - USR_LED + * PA11 - OTG_FS_DM + * PA12 - OTG_FS_DP + * PA13 - JTMS + * PA14 - JTCK + * PA15 - JTDI + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_D8) | \ + PIN_MODE_INPUT(GPIOA_D7) | \ + PIN_MODE_INPUT(GPIOA_D3) | \ + PIN_MODE_INPUT(GPIOA_D2) | \ + PIN_MODE_INPUT(GPIOA_CC_IRQ) | \ + PIN_MODE_ALTERNATE(GPIOA_CC_SCK) | \ + PIN_MODE_ALTERNATE(GPIOA_CC_MISO) | \ + PIN_MODE_ALTERNATE(GPIOA_CC_MOSI) | \ + PIN_MODE_OUTPUT(GPIOA_STATE_LED) | \ + PIN_MODE_INPUT(GPIOA_VBUS) | \ + PIN_MODE_OUTPUT(GPIOA_USR_LED) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \ + PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \ + PIN_MODE_INPUT(GPIOA_JTMS) | \ + PIN_MODE_INPUT(GPIOA_JTCK) | \ + PIN_MODE_INPUT(GPIOA_JTDI)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_D8) | \ + PIN_OTYPE_PUSHPULL(GPIOA_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOA_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOA_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_CC_IRQ) | \ + PIN_OTYPE_PUSHPULL(GPIOA_CC_SCK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_CC_MISO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_CC_MOSI) | \ + PIN_OTYPE_PUSHPULL(GPIOA_STATE_LED) | \ + PIN_OTYPE_PUSHPULL(GPIOA_VBUS) | \ + PIN_OTYPE_PUSHPULL(GPIOA_USR_LED) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \ + PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \ + PIN_OTYPE_PUSHPULL(GPIOA_JTMS) | \ + PIN_OTYPE_PUSHPULL(GPIOA_JTCK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_JTDI)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_D8) | \ + PIN_OSPEED_HIGH(GPIOA_D7) | \ + PIN_OSPEED_HIGH(GPIOA_D3) | \ + PIN_OSPEED_HIGH(GPIOA_D2) | \ + PIN_OSPEED_HIGH(GPIOA_CC_IRQ) | \ + PIN_OSPEED_HIGH(GPIOA_CC_SCK) | \ + PIN_OSPEED_HIGH(GPIOA_CC_MISO) | \ + PIN_OSPEED_HIGH(GPIOA_CC_MOSI) | \ + PIN_OSPEED_HIGH(GPIOA_STATE_LED) | \ + PIN_OSPEED_HIGH(GPIOA_VBUS) | \ + PIN_OSPEED_HIGH(GPIOA_USR_LED) | \ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_OSPEED_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_OSPEED_HIGH(GPIOA_JTMS) | \ + PIN_OSPEED_HIGH(GPIOA_JTCK) | \ + PIN_OSPEED_HIGH(GPIOA_JTDI)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_D8) | \ + PIN_PUPDR_FLOATING(GPIOA_D7) | \ + PIN_PUPDR_FLOATING(GPIOA_D3) | \ + PIN_PUPDR_FLOATING(GPIOA_D2) | \ + PIN_PUPDR_FLOATING(GPIOA_CC_IRQ) | \ + PIN_PUPDR_FLOATING(GPIOA_CC_SCK) | \ + PIN_PUPDR_FLOATING(GPIOA_CC_MISO) | \ + PIN_PUPDR_FLOATING(GPIOA_CC_MOSI) | \ + PIN_PUPDR_FLOATING(GPIOA_STATE_LED) | \ + PIN_PUPDR_FLOATING(GPIOA_VBUS) | \ + PIN_PUPDR_FLOATING(GPIOA_USR_LED) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \ + PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \ + PIN_PUPDR_FLOATING(GPIOA_JTMS) | \ + PIN_PUPDR_FLOATING(GPIOA_JTCK) | \ + PIN_PUPDR_FLOATING(GPIOA_JTDI)) +#define VAL_GPIOA_ODR (PIN_ODR_LOW(GPIOA_D8) | \ + PIN_ODR_LOW(GPIOA_D7) | \ + PIN_ODR_LOW(GPIOA_D3) | \ + PIN_ODR_LOW(GPIOA_D2) | \ + PIN_ODR_LOW(GPIOA_CC_IRQ) | \ + PIN_ODR_LOW(GPIOA_CC_SCK) | \ + PIN_ODR_LOW(GPIOA_CC_MISO) | \ + PIN_ODR_LOW(GPIOA_CC_MOSI) | \ + PIN_ODR_LOW(GPIOA_STATE_LED) | \ + PIN_ODR_LOW(GPIOA_VBUS) | \ + PIN_ODR_LOW(GPIOA_USR_LED) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \ + PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \ + PIN_ODR_LOW(GPIOA_JTMS) | \ + PIN_ODR_LOW(GPIOA_JTCK) | \ + PIN_ODR_LOW(GPIOA_JTDI)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_D8, 0U) | \ + PIN_AFIO_AF(GPIOA_D7, 0U) | \ + PIN_AFIO_AF(GPIOA_D3, 0U) | \ + PIN_AFIO_AF(GPIOA_D2, 0U) | \ + PIN_AFIO_AF(GPIOA_CC_IRQ, 0U) | \ + PIN_AFIO_AF(GPIOA_CC_SCK, 5U) | \ + PIN_AFIO_AF(GPIOA_CC_MISO, 5U) | \ + PIN_AFIO_AF(GPIOA_CC_MOSI, 5U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_STATE_LED, 0U) | \ + PIN_AFIO_AF(GPIOA_VBUS, 0U) | \ + PIN_AFIO_AF(GPIOA_USR_LED, 0U) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10U) | \ + PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10U) | \ + PIN_AFIO_AF(GPIOA_JTMS, 0U) | \ + PIN_AFIO_AF(GPIOA_JTCK, 0U) | \ + PIN_AFIO_AF(GPIOA_JTDI, 0U)) + +/* + * GPIOB setup: + * + * PB0 - MICROSD_CS + * PB1 - MICROSD_CTRL + * PB2 - BOOT1 + * PB3 - JTDO + * PB4 - PB4 + * PB5 - SWITCH1 + * PB6 - I2C1_SCL + * PB7 - I2C1_SDA + * PB8 - D5 + * PB9 - D6 + * PB10 - D10 (=SPI2_SS) + * PB11 - MICROSD_INS + * PB12 - D4 + * PB13 - D13 (=SPI2_SCK) + * PB14 - D12 (=SPI2_MISO) + * PB15 - D11 (=SPI2_MOSI) + */ +#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_MICROSD_CS) | \ + PIN_MODE_OUTPUT(GPIOB_MICROSD_CTRL) | \ + PIN_MODE_OUTPUT(GPIOB_BOOT1) | \ + PIN_MODE_OUTPUT(GPIOB_JTDO) | \ + PIN_MODE_INPUT(GPIOB_PB4) | \ + PIN_MODE_INPUT(GPIOB_SWITCH1) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ + PIN_MODE_INPUT(GPIOB_D5) | \ + PIN_MODE_INPUT(GPIOB_D6) | \ + PIN_MODE_OUTPUT(GPIOB_D10) | \ + PIN_MODE_INPUT(GPIOB_MICROSD_INS) | \ + PIN_MODE_INPUT(GPIOB_D4) | \ + PIN_MODE_ALTERNATE(GPIOB_D13) | \ + PIN_MODE_ALTERNATE(GPIOB_D12) | \ + PIN_MODE_ALTERNATE(GPIOB_D11)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_MICROSD_CS) | \ + PIN_OTYPE_PUSHPULL(GPIOB_MICROSD_CTRL) | \ + PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_JTDO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PB4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SWITCH1) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOB_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_D10) | \ + PIN_OTYPE_PUSHPULL(GPIOB_MICROSD_INS) | \ + PIN_OTYPE_PUSHPULL(GPIOB_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_D13) |\ + PIN_OTYPE_PUSHPULL(GPIOB_D12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_D11)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_MICROSD_CS) | \ + PIN_OSPEED_HIGH(GPIOB_MICROSD_CTRL) | \ + PIN_OSPEED_HIGH(GPIOB_BOOT1) | \ + PIN_OSPEED_HIGH(GPIOB_JTDO) | \ + PIN_OSPEED_HIGH(GPIOB_PB4) | \ + PIN_OSPEED_HIGH(GPIOB_SWITCH1) | \ + PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ + PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ + PIN_OSPEED_HIGH(GPIOB_D5) | \ + PIN_OSPEED_HIGH(GPIOB_D6) | \ + PIN_OSPEED_HIGH(GPIOB_D10) | \ + PIN_OSPEED_HIGH(GPIOB_MICROSD_INS) | \ + PIN_OSPEED_HIGH(GPIOB_D4) | \ + PIN_OSPEED_HIGH(GPIOB_D13) |\ + PIN_OSPEED_HIGH(GPIOB_D12) | \ + PIN_OSPEED_HIGH(GPIOB_D11)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(GPIOB_MICROSD_CS) | \ + PIN_PUPDR_FLOATING(GPIOB_MICROSD_CTRL) | \ + PIN_PUPDR_FLOATING(GPIOB_BOOT1) | \ + PIN_PUPDR_FLOATING(GPIOB_JTDO) | \ + PIN_PUPDR_FLOATING(GPIOB_PB4) | \ + PIN_PUPDR_FLOATING(GPIOB_SWITCH1) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \ + PIN_PUPDR_FLOATING(GPIOB_D5) | \ + PIN_PUPDR_FLOATING(GPIOB_D6) | \ + PIN_PUPDR_FLOATING(GPIOB_D10) | \ + PIN_PUPDR_FLOATING(GPIOB_MICROSD_INS) | \ + PIN_PUPDR_FLOATING(GPIOB_D4) | \ + PIN_PUPDR_FLOATING(GPIOB_D13) |\ + PIN_PUPDR_FLOATING(GPIOB_D12) | \ + PIN_PUPDR_FLOATING(GPIOB_D11)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_MICROSD_CS) | \ + PIN_ODR_HIGH(GPIOB_MICROSD_CTRL) | \ + PIN_ODR_HIGH(GPIOB_BOOT1) | \ + PIN_ODR_LOW(GPIOB_JTDO) | \ + PIN_ODR_LOW(GPIOB_PB4) | \ + PIN_ODR_LOW(GPIOB_SWITCH1) | \ + PIN_ODR_LOW(GPIOB_I2C1_SCL) | \ + PIN_ODR_LOW(GPIOB_I2C1_SDA) | \ + PIN_ODR_LOW(GPIOB_D5) | \ + PIN_ODR_LOW(GPIOB_D6) | \ + PIN_ODR_LOW(GPIOB_D10) | \ + PIN_ODR_HIGH(GPIOB_MICROSD_INS) | \ + PIN_ODR_LOW(GPIOB_D4) | \ + PIN_ODR_LOW(GPIOB_D13) | \ + PIN_ODR_LOW(GPIOB_D12) | \ + PIN_ODR_LOW(GPIOB_D11)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_MICROSD_CS, 0U) | \ + PIN_AFIO_AF(GPIOB_MICROSD_CTRL, 0U) | \ + PIN_AFIO_AF(GPIOB_BOOT1, 0U) | \ + PIN_AFIO_AF(GPIOB_JTDO, 0U) | \ + PIN_AFIO_AF(GPIOB_PB4, 0U) | \ + PIN_AFIO_AF(GPIOB_SWITCH1, 0U) | \ + PIN_AFIO_AF(GPIOB_I2C1_SCL, 4U) | \ + PIN_AFIO_AF(GPIOB_I2C1_SDA, 4U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_D5, 0U) | \ + PIN_AFIO_AF(GPIOB_D6, 0U) | \ + PIN_AFIO_AF(GPIOB_D10, 0U) | \ + PIN_AFIO_AF(GPIOB_MICROSD_INS, 0U) | \ + PIN_AFIO_AF(GPIOB_D4, 0U) | \ + PIN_AFIO_AF(GPIOB_D13, 5U) | \ + PIN_AFIO_AF(GPIOB_D12, 5U) | \ + PIN_AFIO_AF(GPIOB_D11, 5U)) + +/* + * GPIOC setup: + * + * PC0 - A0 + * PC1 - A1 + * PC2 - A2 + * PC3 - A3 + * PC4 - A4 + * PC5 - A5 + * PC6 - USART6_TX_D1 + * PC7 - USART6_RX_D0 + * PC8 - CC_CS + * PC9 - LINK_LED + * PC10 - SPI3_CLK + * PC11 - SPI3_MISO + * PC12 - SPI3_MOSI + * PC13 - POWER_LED + * PC14 - OSC32_IN + * PC15 - OSC32_OUT + */ +#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(GPIOC_A0) | \ + PIN_MODE_ANALOG(GPIOC_A1) | \ + PIN_MODE_ANALOG(GPIOC_A2) | \ + PIN_MODE_ANALOG(GPIOC_A3) | \ + PIN_MODE_ANALOG(GPIOC_A4) | \ + PIN_MODE_ANALOG(GPIOC_A5) | \ + PIN_MODE_ALTERNATE(GPIOC_D1) | \ + PIN_MODE_ALTERNATE(GPIOC_D0) | \ + PIN_MODE_OUTPUT(GPIOC_CC_CS) | \ + PIN_MODE_OUTPUT(GPIOC_LINK_LED) | \ + PIN_MODE_ALTERNATE(GPIOC_SPI3_CLK) | \ + PIN_MODE_ALTERNATE(GPIOC_SPI3_MISO) | \ + PIN_MODE_ALTERNATE(GPIOC_SPI3_MOSI) | \ + PIN_MODE_OUTPUT(GPIOC_POWER_LED) | \ + PIN_MODE_ALTERNATE(GPIOC_OSC32_IN) | \ + PIN_MODE_ALTERNATE(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_A0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_A1) |\ + PIN_OTYPE_PUSHPULL(GPIOC_A2) |\ + PIN_OTYPE_PUSHPULL(GPIOC_A3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_A4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_A5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_CC_CS) | \ + PIN_OTYPE_PUSHPULL(GPIOC_LINK_LED) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SPI3_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SPI3_MISO) | \ + PIN_OTYPE_PUSHPULL(GPIOC_SPI3_MOSI) | \ + PIN_OTYPE_PUSHPULL(GPIOC_POWER_LED) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_A0) | \ + PIN_OSPEED_HIGH(GPIOC_A1) | \ + PIN_OSPEED_HIGH(GPIOC_A2) | \ + PIN_OSPEED_HIGH(GPIOC_A3) | \ + PIN_OSPEED_HIGH(GPIOC_A4) | \ + PIN_OSPEED_HIGH(GPIOC_A5) | \ + PIN_OSPEED_HIGH(GPIOC_D1) | \ + PIN_OSPEED_HIGH(GPIOC_D0) | \ + PIN_OSPEED_HIGH(GPIOC_CC_CS) | \ + PIN_OSPEED_HIGH(GPIOC_LINK_LED) | \ + PIN_OSPEED_HIGH(GPIOC_SPI3_CLK) | \ + PIN_OSPEED_HIGH(GPIOC_SPI3_MISO) | \ + PIN_OSPEED_HIGH(GPIOC_SPI3_MOSI) | \ + PIN_OSPEED_HIGH(GPIOC_POWER_LED) | \ + PIN_OSPEED_HIGH(GPIOC_OSC32_IN) | \ + PIN_OSPEED_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_A0) | \ + PIN_PUPDR_FLOATING(GPIOC_A1) |\ + PIN_PUPDR_FLOATING(GPIOC_A2) |\ + PIN_PUPDR_FLOATING(GPIOC_A3) | \ + PIN_PUPDR_FLOATING(GPIOC_A4) | \ + PIN_PUPDR_FLOATING(GPIOC_A5) | \ + PIN_PUPDR_FLOATING(GPIOC_D1) | \ + PIN_PUPDR_FLOATING(GPIOC_D0) | \ + PIN_PUPDR_FLOATING(GPIOC_CC_CS) | \ + PIN_PUPDR_FLOATING(GPIOC_LINK_LED) | \ + PIN_PUPDR_FLOATING(GPIOC_SPI3_CLK) | \ + PIN_PUPDR_FLOATING(GPIOC_SPI3_MISO) | \ + PIN_PUPDR_FLOATING(GPIOC_SPI3_MOSI) | \ + PIN_PUPDR_FLOATING(GPIOC_POWER_LED) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_LOW(GPIOC_A0) | \ + PIN_ODR_LOW(GPIOC_A1) | \ + PIN_ODR_LOW(GPIOC_A2) | \ + PIN_ODR_LOW(GPIOC_A3) | \ + PIN_ODR_LOW(GPIOC_A4) | \ + PIN_ODR_LOW(GPIOC_A5) | \ + PIN_ODR_LOW(GPIOC_D1) | \ + PIN_ODR_LOW(GPIOC_D0) | \ + PIN_ODR_LOW(GPIOC_CC_CS) | \ + PIN_ODR_LOW(GPIOC_LINK_LED) | \ + PIN_ODR_LOW(GPIOC_SPI3_CLK) | \ + PIN_ODR_LOW(GPIOC_SPI3_MISO) | \ + PIN_ODR_LOW(GPIOC_SPI3_MOSI) | \ + PIN_ODR_LOW(GPIOC_POWER_LED) | \ + PIN_ODR_LOW(GPIOC_OSC32_IN) | \ + PIN_ODR_LOW(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_A0, 0U) | \ + PIN_AFIO_AF(GPIOC_A1, 0U) | \ + PIN_AFIO_AF(GPIOC_A2, 0U) | \ + PIN_AFIO_AF(GPIOC_A3, 0U) | \ + PIN_AFIO_AF(GPIOC_A4, 0U) | \ + PIN_AFIO_AF(GPIOC_A5, 0U) | \ + PIN_AFIO_AF(GPIOC_D1, 8U) | \ + PIN_AFIO_AF(GPIOC_D0, 8U)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_CC_CS, 0U) | \ + PIN_AFIO_AF(GPIOC_LINK_LED, 0U) | \ + PIN_AFIO_AF(GPIOC_SPI3_CLK, 6U) | \ + PIN_AFIO_AF(GPIOC_SPI3_MISO, 6U) | \ + PIN_AFIO_AF(GPIOC_SPI3_MOSI, 6U) | \ + PIN_AFIO_AF(GPIOC_POWER_LED, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) + +/* + * GPIOD setup: + * + * PD0 - SPI_CS_GOPORT1 + * PD1 - SPI_CS_GOPORT2 + * PD2 - SPI_CS_GOPORT3 + * PD3 - CC_RTS + * PD4 - CC_CTS + * PD5 - CC_RX + * PD6 - CC_TX + * PD7 - PWR_ON_GOPORT1 + * PD8 - USART3_TX_GOPORT1 + * PD9 - USART3_RX_GOPORT1 + * PD10 - PWR_ON_GOPORT2 + * PD11 - SWITCH1 + * PD12 - PWR_ON_GOPORT3 + * PD13 - INT_GOPORT1 + * PD14 - INT_GOPORT2 + * PD15 - INT_GOPORT3 + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_SPI_CS_GOPORT1) | \ + PIN_MODE_INPUT(GPIOD_SPI_CS_GOPORT2) | \ + PIN_MODE_INPUT(GPIOD_SPI_CS_GOPORT3) | \ + PIN_MODE_ALTERNATE(GPIOD_CC_RTS) | \ + PIN_MODE_ALTERNATE(GPIOD_CC_CTS) | \ + PIN_MODE_ALTERNATE(GPIOD_CC_RX) | \ + PIN_MODE_ALTERNATE(GPIOD_CC_TX) | \ + PIN_MODE_OUTPUT(GPIOD_PWR_ON_GOPORT1) | \ + PIN_MODE_ALTERNATE(GPIOD_USART3_TX_GOPORT1) | \ + PIN_MODE_ALTERNATE(GPIOD_USART3_RX_GOPORT1) | \ + PIN_MODE_OUTPUT(GPIOD_PWR_ON_GOPORT2) | \ + PIN_MODE_INPUT(GPIOD_SWITCH1) | \ + PIN_MODE_OUTPUT(GPIOD_PWR_ON_GOPORT3) | \ + PIN_MODE_OUTPUT(GPIOD_INT_GOPORT1) | \ + PIN_MODE_OUTPUT(GPIOD_INT_GOPORT2) | \ + PIN_MODE_OUTPUT(GPIOD_INT_GOPORT3)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_SPI_CS_GOPORT1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_SPI_CS_GOPORT2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_SPI_CS_GOPORT3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_CC_RTS) | \ + PIN_OTYPE_PUSHPULL(GPIOD_CC_CTS) | \ + PIN_OTYPE_PUSHPULL(GPIOD_CC_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_CC_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PWR_ON_GOPORT1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_USART3_TX_GOPORT1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_USART3_RX_GOPORT1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PWR_ON_GOPORT2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_SWITCH1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PWR_ON_GOPORT3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_INT_GOPORT1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_INT_GOPORT2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_INT_GOPORT3)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_SPI_CS_GOPORT1) | \ + PIN_OSPEED_HIGH(GPIOD_SPI_CS_GOPORT2) | \ + PIN_OSPEED_HIGH(GPIOD_SPI_CS_GOPORT3) | \ + PIN_OSPEED_HIGH(GPIOD_CC_RTS) | \ + PIN_OSPEED_HIGH(GPIOD_CC_CTS) | \ + PIN_OSPEED_HIGH(GPIOD_CC_RX) | \ + PIN_OSPEED_HIGH(GPIOD_CC_TX) | \ + PIN_OSPEED_HIGH(GPIOD_PWR_ON_GOPORT1) | \ + PIN_OSPEED_HIGH(GPIOD_USART3_TX_GOPORT1) | \ + PIN_OSPEED_HIGH(GPIOD_USART3_RX_GOPORT1) | \ + PIN_OSPEED_HIGH(GPIOD_PWR_ON_GOPORT2) | \ + PIN_OSPEED_HIGH(GPIOD_SWITCH1) | \ + PIN_OSPEED_HIGH(GPIOD_PWR_ON_GOPORT3) | \ + PIN_OSPEED_HIGH(GPIOD_INT_GOPORT1) | \ + PIN_OSPEED_HIGH(GPIOD_INT_GOPORT2) | \ + PIN_OSPEED_HIGH(GPIOD_INT_GOPORT3)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_SPI_CS_GOPORT1) | \ + PIN_PUPDR_FLOATING(GPIOD_SPI_CS_GOPORT2) | \ + PIN_PUPDR_FLOATING(GPIOD_SPI_CS_GOPORT3) | \ + PIN_PUPDR_FLOATING(GPIOD_CC_RTS) | \ + PIN_PUPDR_FLOATING(GPIOD_CC_CTS) | \ + PIN_PUPDR_FLOATING(GPIOD_CC_RX) | \ + PIN_PUPDR_FLOATING(GPIOD_CC_TX) | \ + PIN_PUPDR_FLOATING(GPIOD_PWR_ON_GOPORT1) | \ + PIN_PUPDR_FLOATING(GPIOD_USART3_TX_GOPORT1) | \ + PIN_PUPDR_FLOATING(GPIOD_USART3_RX_GOPORT1) | \ + PIN_PUPDR_FLOATING(GPIOD_PWR_ON_GOPORT2) | \ + PIN_PUPDR_PULLDOWN(GPIOD_SWITCH1) | \ + PIN_PUPDR_FLOATING(GPIOD_PWR_ON_GOPORT3) | \ + PIN_PUPDR_FLOATING(GPIOD_INT_GOPORT1) | \ + PIN_PUPDR_FLOATING(GPIOD_INT_GOPORT2) | \ + PIN_PUPDR_FLOATING(GPIOD_INT_GOPORT3)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_SPI_CS_GOPORT1) | \ + PIN_ODR_HIGH(GPIOD_SPI_CS_GOPORT2) | \ + PIN_ODR_HIGH(GPIOD_SPI_CS_GOPORT3) | \ + PIN_ODR_LOW(GPIOD_CC_RTS) | \ + PIN_ODR_LOW(GPIOD_CC_CTS) | \ + PIN_ODR_LOW(GPIOD_CC_RX) | \ + PIN_ODR_LOW(GPIOD_CC_TX) | \ + PIN_ODR_LOW(GPIOD_PWR_ON_GOPORT1) | \ + PIN_ODR_LOW(GPIOD_USART3_TX_GOPORT1) | \ + PIN_ODR_LOW(GPIOD_USART3_RX_GOPORT1) | \ + PIN_ODR_LOW(GPIOD_PWR_ON_GOPORT2) | \ + PIN_ODR_LOW(GPIOD_SWITCH1) | \ + PIN_ODR_LOW(GPIOD_PWR_ON_GOPORT3) | \ + PIN_ODR_HIGH(GPIOD_INT_GOPORT1) | \ + PIN_ODR_HIGH(GPIOD_INT_GOPORT2) | \ + PIN_ODR_HIGH(GPIOD_INT_GOPORT3)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_SPI_CS_GOPORT1, 0U) | \ + PIN_AFIO_AF(GPIOD_SPI_CS_GOPORT2, 0U) | \ + PIN_AFIO_AF(GPIOD_SPI_CS_GOPORT3, 0U) | \ + PIN_AFIO_AF(GPIOD_CC_RTS, 7U) | \ + PIN_AFIO_AF(GPIOD_CC_CTS, 7U) | \ + PIN_AFIO_AF(GPIOD_CC_RX, 7U) | \ + PIN_AFIO_AF(GPIOD_CC_TX, 7U) | \ + PIN_AFIO_AF(GPIOD_PWR_ON_GOPORT1, 0U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_USART3_TX_GOPORT1, 7U) | \ + PIN_AFIO_AF(GPIOD_USART3_RX_GOPORT1, 7U) | \ + PIN_AFIO_AF(GPIOD_PWR_ON_GOPORT2, 0U) | \ + PIN_AFIO_AF(GPIOD_SWITCH1, 0U) | \ + PIN_AFIO_AF(GPIOD_PWR_ON_GOPORT3, 0U) | \ + PIN_AFIO_AF(GPIOD_INT_GOPORT1, 0U) | \ + PIN_AFIO_AF(GPIOD_INT_GOPORT2, 0U) | \ + PIN_AFIO_AF(GPIOD_INT_GOPORT3, 0U)) + +/* + * GPIOE setup: + * + * PE0 - USART8_RX_GOPORT3 + * PE1 - USART8_TX_GOPORT3 + * PE2 - SPI4_SCK + * PE3 - EN_UART_TX_PU_GOPORT1 + * PE4 - CC_HIB + * PE5 - D9 + * PE6 - SPI4_MOSI + * PE7 - USART7_RX_GOPORT2 + * PE8 - USART7_TX_GOPORT2 + * PE9 - LED_GOPORT1 + * PE10 - EN_UART_TX_PU_GOPORT2 + * PE11 - LED_GOPORT2 + * PE12 - EN_UART_TX_PU_GOPORT3 + * PE13 - SPI4_MISO + * PE14 - LED_GOPORT3 + * PE15 - CC_TCXO_EN_SOP2 + */ +#define VAL_GPIOE_MODER (PIN_MODE_ALTERNATE(GPIOE_USART8_RX_GOPORT3) | \ + PIN_MODE_ALTERNATE(GPIOE_USART8_TX_GOPORT3) | \ + PIN_MODE_ALTERNATE(GPIOE_SPI4_SCK) | \ + PIN_MODE_ALTERNATE(GPIOE_EN_UART_TX_PU_GOPORT1) | \ + PIN_MODE_OUTPUT(GPIOE_CC_HIB) | \ + PIN_MODE_INPUT(GPIOE_D9) | \ + PIN_MODE_ALTERNATE(GPIOE_SPI4_MOSI) | \ + PIN_MODE_ALTERNATE(GPIOE_USART7_RX_GOPORT2) | \ + PIN_MODE_ALTERNATE(GPIOE_USART7_TX_GOPORT2) | \ + PIN_MODE_OUTPUT(GPIOE_LED_GOPORT1) | \ + PIN_MODE_OUTPUT(GPIOE_EN_UART_TX_PU_GOPORT2) | \ + PIN_MODE_OUTPUT(GPIOE_LED_GOPORT2) | \ + PIN_MODE_OUTPUT(GPIOE_EN_UART_TX_PU_GOPORT3) | \ + PIN_MODE_ALTERNATE(GPIOE_SPI4_MISO) | \ + PIN_MODE_OUTPUT(GPIOE_LED_GOPORT3) | \ + PIN_MODE_INPUT(GPIOE_CC_TCXO_EN_SOP2)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_USART8_RX_GOPORT3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_USART8_TX_GOPORT3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SPI4_SCK) | \ + PIN_OTYPE_PUSHPULL(GPIOE_EN_UART_TX_PU_GOPORT1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_CC_HIB) | \ + PIN_OTYPE_PUSHPULL(GPIOE_D9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SPI4_MOSI) | \ + PIN_OTYPE_PUSHPULL(GPIOE_USART7_RX_GOPORT2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_USART7_TX_GOPORT2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_LED_GOPORT1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_EN_UART_TX_PU_GOPORT2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_LED_GOPORT2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_EN_UART_TX_PU_GOPORT3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SPI4_MISO) | \ + PIN_OTYPE_PUSHPULL(GPIOE_LED_GOPORT3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_CC_TCXO_EN_SOP2)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_USART8_RX_GOPORT3) | \ + PIN_OSPEED_HIGH(GPIOE_USART8_TX_GOPORT3) | \ + PIN_OSPEED_HIGH(GPIOE_SPI4_SCK) | \ + PIN_OSPEED_HIGH(GPIOE_EN_UART_TX_PU_GOPORT1) | \ + PIN_OSPEED_HIGH(GPIOE_CC_HIB) | \ + PIN_OSPEED_HIGH(GPIOE_D9) | \ + PIN_OSPEED_HIGH(GPIOE_SPI4_MOSI) | \ + PIN_OSPEED_HIGH(GPIOE_USART7_RX_GOPORT2) | \ + PIN_OSPEED_HIGH(GPIOE_USART7_TX_GOPORT2) | \ + PIN_OSPEED_HIGH(GPIOE_LED_GOPORT1) | \ + PIN_OSPEED_HIGH(GPIOE_EN_UART_TX_PU_GOPORT2) | \ + PIN_OSPEED_HIGH(GPIOE_LED_GOPORT2) | \ + PIN_OSPEED_HIGH(GPIOE_EN_UART_TX_PU_GOPORT3) | \ + PIN_OSPEED_HIGH(GPIOE_SPI4_MISO) | \ + PIN_OSPEED_HIGH(GPIOE_LED_GOPORT3) | \ + PIN_OSPEED_HIGH(GPIOE_CC_TCXO_EN_SOP2)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_USART8_RX_GOPORT3) | \ + PIN_PUPDR_FLOATING(GPIOE_USART8_TX_GOPORT3) | \ + PIN_PUPDR_FLOATING(GPIOE_SPI4_SCK) | \ + PIN_PUPDR_PULLDOWN(GPIOE_EN_UART_TX_PU_GOPORT1) | \ + PIN_PUPDR_PULLDOWN(GPIOE_CC_HIB) | \ + PIN_PUPDR_FLOATING(GPIOE_D9) | \ + PIN_PUPDR_FLOATING(GPIOE_SPI4_MOSI) | \ + PIN_PUPDR_FLOATING(GPIOE_USART7_RX_GOPORT2) | \ + PIN_PUPDR_FLOATING(GPIOE_USART7_TX_GOPORT2) | \ + PIN_PUPDR_FLOATING(GPIOE_LED_GOPORT1) | \ + PIN_PUPDR_PULLDOWN(GPIOE_EN_UART_TX_PU_GOPORT2) | \ + PIN_PUPDR_FLOATING(GPIOE_LED_GOPORT2) | \ + PIN_PUPDR_PULLDOWN(GPIOE_EN_UART_TX_PU_GOPORT3) | \ + PIN_PUPDR_FLOATING(GPIOE_SPI4_MISO) | \ + PIN_PUPDR_FLOATING(GPIOE_LED_GOPORT3) | \ + PIN_PUPDR_FLOATING(GPIOE_CC_TCXO_EN_SOP2)) +#define VAL_GPIOE_ODR (PIN_ODR_LOW(GPIOE_USART8_RX_GOPORT3) | \ + PIN_ODR_LOW(GPIOE_USART8_TX_GOPORT3) | \ + PIN_ODR_LOW(GPIOE_SPI4_SCK) | \ + PIN_ODR_LOW(GPIOE_EN_UART_TX_PU_GOPORT1) | \ + PIN_ODR_LOW(GPIOE_CC_HIB) | \ + PIN_ODR_LOW(GPIOE_D9) | \ + PIN_ODR_LOW(GPIOE_SPI4_MOSI) | \ + PIN_ODR_LOW(GPIOE_USART7_RX_GOPORT2) | \ + PIN_ODR_LOW(GPIOE_USART7_TX_GOPORT2) | \ + PIN_ODR_LOW(GPIOE_LED_GOPORT1) | \ + PIN_ODR_LOW(GPIOE_EN_UART_TX_PU_GOPORT2) | \ + PIN_ODR_LOW(GPIOE_LED_GOPORT2) | \ + PIN_ODR_LOW(GPIOE_EN_UART_TX_PU_GOPORT3) | \ + PIN_ODR_LOW(GPIOE_SPI4_MISO) | \ + PIN_ODR_LOW(GPIOE_LED_GOPORT3) | \ + PIN_ODR_LOW(GPIOE_CC_TCXO_EN_SOP2)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_USART8_RX_GOPORT3, 8U) | \ + PIN_AFIO_AF(GPIOE_USART8_TX_GOPORT3, 8U) | \ + PIN_AFIO_AF(GPIOE_SPI4_SCK, 5U) | \ + PIN_AFIO_AF(GPIOE_EN_UART_TX_PU_GOPORT1, 0U) | \ + PIN_AFIO_AF(GPIOE_CC_HIB, 0U) | \ + PIN_AFIO_AF(GPIOE_D9, 0U) | \ + PIN_AFIO_AF(GPIOE_SPI4_MOSI, 5U) | \ + PIN_AFIO_AF(GPIOE_USART7_RX_GOPORT2, 8U)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_USART7_TX_GOPORT2, 8U) | \ + PIN_AFIO_AF(GPIOE_LED_GOPORT1, 0U) | \ + PIN_AFIO_AF(GPIOE_EN_UART_TX_PU_GOPORT2, 0U) | \ + PIN_AFIO_AF(GPIOE_LED_GOPORT2, 0U) | \ + PIN_AFIO_AF(GPIOE_EN_UART_TX_PU_GOPORT3, 0U) | \ + PIN_AFIO_AF(GPIOE_SPI4_MISO, 0U) | \ + PIN_AFIO_AF(GPIOE_LED_GOPORT3, 0U) | \ + PIN_AFIO_AF(GPIOE_CC_TCXO_EN_SOP2, 0U)) + + +/* + * GPIOH setup: + * + * PH0 - OSC_IN + * PH1 - OSC_OUT + * PH2 - PIN2 + * PH3 - PIN3 + * PH4 - PIN4 + * PH5 - PIN5 + * PH6 - PIN6 + * PH7 - PIN7 + * PH8 - PIN8 + * PH9 - PIN9 + * PH10 - PIN10 + * PH11 - PIN11 + * PH12 - PIN12 + * PH13 - PIN13 + * PH14 - PIN14 + * PH15 - PIN15 + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_INPUT(GPIOH_PIN2) | \ + PIN_MODE_INPUT(GPIOH_PIN3) | \ + PIN_MODE_INPUT(GPIOH_PIN4) | \ + PIN_MODE_INPUT(GPIOH_PIN5) | \ + PIN_MODE_INPUT(GPIOH_PIN6) | \ + PIN_MODE_INPUT(GPIOH_PIN7) | \ + PIN_MODE_INPUT(GPIOH_PIN8) | \ + PIN_MODE_INPUT(GPIOH_PIN9) | \ + PIN_MODE_INPUT(GPIOH_PIN10) | \ + PIN_MODE_INPUT(GPIOH_PIN11) | \ + PIN_MODE_INPUT(GPIOH_PIN12) | \ + PIN_MODE_INPUT(GPIOH_PIN13) | \ + PIN_MODE_INPUT(GPIOH_PIN14) | \ + PIN_MODE_INPUT(GPIOH_PIN15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOH_PIN15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ + PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOH_PIN15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOH_PIN15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_PIN2) | \ + PIN_ODR_HIGH(GPIOH_PIN3) | \ + PIN_ODR_HIGH(GPIOH_PIN4) | \ + PIN_ODR_HIGH(GPIOH_PIN5) | \ + PIN_ODR_HIGH(GPIOH_PIN6) | \ + PIN_ODR_HIGH(GPIOH_PIN7) | \ + PIN_ODR_HIGH(GPIOH_PIN8) | \ + PIN_ODR_HIGH(GPIOH_PIN9) | \ + PIN_ODR_HIGH(GPIOH_PIN10) | \ + PIN_ODR_HIGH(GPIOH_PIN11) | \ + PIN_ODR_HIGH(GPIOH_PIN12) | \ + PIN_ODR_HIGH(GPIOH_PIN13) | \ + PIN_ODR_HIGH(GPIOH_PIN14) | \ + PIN_ODR_HIGH(GPIOH_PIN15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN7, 0U)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOH_PIN15, 0U)) + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/common/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/common/CMakeLists.txt new file mode 100644 index 00000000..aa7f1d54 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/common/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/usbcfg.c") +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c") + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/common/Device_BlockStorage-DEBUG.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 00000000..a970be77 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,142 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +//16kB block +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 1 }, // 0x08000000 nanoBooter + { BlockRange_BLOCKTYPE_CODE , 2, 3 } // 0x08008000 nanoCLR +}; + +//64kB block +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 0x08010000 nanoCLR +}; + +//128kB block +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 3 }, // 0x08020000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 4, 6 }, // 0x080A0000 deployment +}; + +//16kB block +const BlockRange BlockRange4[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 3 } // 0x08100000 deployment +}; + +//64kB block +const BlockRange BlockRange5[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 0 } // 0x08110000 deployment +}; + +//128kB block +const BlockRange BlockRange6[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 6 } // 0x08120000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08010000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 7, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + + { + (0), // no attributes for this region + 0x08100000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange4), + BlockRange4, + }, + + { + (0), // no attributes for this region + 0x08110000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange5), + BlockRange5, + }, + + { + (0), // no attributes for this region + 0x08120000, // start address for block region + 7, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange6), + BlockRange6, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), // STM32 flash memory is XIP + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/common/Device_BlockStorage.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/common/Device_BlockStorage.c new file mode 100644 index 00000000..23428263 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/common/Device_BlockStorage.c @@ -0,0 +1,142 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +//16kB block +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 0 }, // 0x08000000 nanoBooter + { BlockRange_BLOCKTYPE_CODE , 1, 3 } // 0x08004000 nanoCLR +}; + +//64kB block +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 0x08010000 nanoCLR +}; + +//128kB block +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 }, // 0x08020000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 1, 6 }, // 0x08040000 deployment +}; + +//16kB block +const BlockRange BlockRange4[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 3 } // 0x08100000 deployment +}; + +//64kB block +const BlockRange BlockRange5[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 0 } // 0x08110000 deployment +}; + +//128kB block +const BlockRange BlockRange6[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 6 } // 0x08120000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08010000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 7, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + + { + (0), // no attributes for this region + 0x08100000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange4), + BlockRange4, + }, + + { + (0), // no attributes for this region + 0x08110000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange5), + BlockRange5, + }, + + { + (0), // no attributes for this region + 0x08120000, // start address for block region + 7, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange6), + BlockRange6, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), // STM32 flash memory is XIP + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/common/usbcfg.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/common/usbcfg.c new file mode 100644 index 00000000..9fd0a5ad --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/common/usbcfg.c @@ -0,0 +1,454 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "hal.h" + +/* Virtual serial port over USB.*/ +SerialUSBDriver SDU1; + +/* + * Endpoints to be used for USBD2. + */ +#define USBD2_DATA_REQUEST_EP 1 +#define USBD2_DATA_AVAILABLE_EP 1 +#define USBD2_INTERRUPT_REQUEST_EP 2 + +// address for device unique ID +// valid for STM32F4 series +#define DEVICE_ID1 (0x1FFF7A10) +#define DEVICE_ID2 (0x1FFF7A14) +#define DEVICE_ID3 (0x1FFF7A18) + +// // size of string serial is 36 = 2 + 5x2 + 26 from silicon unique ID precedeed of string "NANO_" and descriptor codes +// #define USB_SIZ_STRING_SERIAL 36 + +//////////////////////////////////////////////// +// vendor +#define USB_STRING_VENDOR L"WildernessLabs" +//////////////////////////////////////////////// + +// structure for USB Vendor with Unicode string +typedef struct usb_string_vendor +{ + uint8_t bLength; + uint8_t bDescriptorType; + wchar_t bPropertyData[sizeof(USB_STRING_VENDOR)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec) + +}usb_string_vendor; + + +///////////////////////////////////////////////////////////////////////// +// device description +#define USB_STRING_DEVICE_DESCRIPTION L"Netduino3_Wifi" +///////////////////////////////////////////////////////////////////////// + +// structure for USB device descriptor with Unicode string +typedef struct usb_string_device_description +{ + uint8_t bLength; + uint8_t bDescriptorType; + wchar_t bPropertyData[sizeof(USB_STRING_DEVICE_DESCRIPTION)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec) + +}usb_string_device_description; + + +///////////////////////////////////////////////////////////////////////// +// device serial number +// this will produce a string with NANO_ prefix followed +// by the hexadecimal representation of the silicon unique ID of the CPU +#define USB_STRING_SERIAL_NUMBER L"NANO_xxxxxxxxxxx" +///////////////////////////////////////////////////////////////////////// +#define INDEX_OF_WCHAR_FOR_UNIQUE_ID 5 + +// structure for USB serial number descriptor with Unicode string +typedef struct usb_string_serial_number +{ + uint8_t bLength; + uint8_t bDescriptorType; + wchar_t bPropertyData[sizeof(USB_STRING_SERIAL_NUMBER)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec) + +}usb_string_serial_number; + + +/* + * USB Device Descriptor. + */ +static const uint8_t vcom_device_descriptor_data[] = { + USB_DESC_DEVICE (0x0200, /* bcdUSB (2.0). */ + 0x02, /* bDeviceClass (CDC). */ + 0x00, /* bDeviceSubClass. */ + 0x00, /* bDeviceProtocol. */ + 0x40, /* bMaxPacketSize. */ + 0x0483, /* idVendor (ST). */ + 0x5740, /* idProduct. */ + 0x0200, /* bcdDevice. */ + 1, /* iManufacturer. */ + 2, /* iProduct. */ + 3, /* iSerialNumber. */ + 1) /* bNumConfigurations. */ +}; + +/* + * Device Descriptor wrapper. + */ +static const USBDescriptor vcom_device_descriptor = { + sizeof vcom_device_descriptor_data, + vcom_device_descriptor_data +}; + +/* Configuration Descriptor tree for a CDC.*/ +static const uint8_t vcom_configuration_descriptor_data[] = { + /* Configuration Descriptor.*/ + USB_DESC_CONFIGURATION(0x0043, /* wTotalLength. */ + 0x02, /* bNumInterfaces. */ + 0x01, /* bConfigurationValue. */ + 0, /* iConfiguration. */ + 0xC0, /* bmAttributes (self powered). */ + 50), /* bMaxPower (100mA). */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x01, /* bNumEndpoints. */ + 0x02, /* bInterfaceClass (Communications + Interface Class, CDC section + 4.2). */ + 0x02, /* bInterfaceSubClass (Abstract + Control Model, CDC section 4.3). */ + 0x01, /* bInterfaceProtocol (AT commands, + CDC section 4.4). */ + 0), /* iInterface. */ + /* Header Functional Descriptor (CDC section 5.2.3).*/ + USB_DESC_BYTE (5), /* bLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header + Functional Descriptor. */ + USB_DESC_BCD (0x0110), /* bcdCDC. */ + /* Call Management Functional Descriptor. */ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */ + USB_DESC_BYTE (0x01), /* bDataInterface. */ + /* ACM Functional Descriptor.*/ + USB_DESC_BYTE (4), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract + Control Management Descriptor). */ + USB_DESC_BYTE (0x02), /* bmCapabilities. */ + /* Union Functional Descriptor.*/ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bMasterInterface (Communication + Class Interface). */ + USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class + Interface). */ + /* Endpoint 2 Descriptor.*/ + USB_DESC_ENDPOINT (USBD2_INTERRUPT_REQUEST_EP|0x80, + 0x03, /* bmAttributes (Interrupt). */ + 0x0008, /* wMaxPacketSize. */ + 0xFF), /* bInterval. */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x02, /* bNumEndpoints. */ + 0x0A, /* bInterfaceClass (Data Class + Interface, CDC section 4.5). */ + 0x00, /* bInterfaceSubClass (CDC section + 4.6). */ + 0x00, /* bInterfaceProtocol (CDC section + 4.7). */ + 0x00), /* iInterface. */ + /* Endpoint 3 Descriptor.*/ + USB_DESC_ENDPOINT (USBD2_DATA_AVAILABLE_EP, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00), /* bInterval. */ + /* Endpoint 1 Descriptor.*/ + USB_DESC_ENDPOINT (USBD2_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00) /* bInterval. */ +}; + +/* + * Configuration Descriptor wrapper. + */ +static const USBDescriptor vcom_configuration_descriptor = { + sizeof vcom_configuration_descriptor_data, + vcom_configuration_descriptor_data +}; + +/* + * U.S. English language identifier. + */ +static const uint8_t vcom_string0[] = { + USB_DESC_BYTE(4), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */ +}; + + +// Vendor string +static const usb_string_vendor usb_vendor = { + sizeof(usb_vendor), + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), + USB_STRING_VENDOR +}; + + +// Device Description string +static const usb_string_device_description usb_device_description = { + sizeof(usb_device_description), + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), + USB_STRING_DEVICE_DESCRIPTION +}; + + +// Serial Number string. +static usb_string_serial_number usb_serial_number = { + sizeof(usb_serial_number), + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), + USB_STRING_SERIAL_NUMBER +}; + + +/* + * Strings wrappers array. + */ +static const USBDescriptor vcom_strings[] = { + {sizeof vcom_string0, vcom_string0}, + {sizeof usb_vendor, (uint8_t*)(&usb_vendor)}, + {sizeof usb_device_description, (uint8_t*)(&usb_device_description)}, + {sizeof usb_serial_number, (uint8_t*)(&usb_serial_number)}, +}; + + +// Convert Hex 32Bits value into char +// value: value to convert +// pbuf: pointer to the buffer +// len: buffer length +void IntToUnicode(uint32_t value , uint8_t *pbuf, uint8_t len) +{ + uint8_t idx = 0; + + for( idx = 0; idx < len; idx ++) + { + if( ((value >> 28)) < 0xA ) + { + pbuf[ 2* idx] = (value >> 28) + '0'; + } + else + { + pbuf[2* idx] = (value >> 28) + 'A' - 10; + } + + value = value << 4; + + pbuf[ 2* idx + 1] = 0; + } +} + +// Create the serial number string descriptor +void Get_SerialNum(uint8_t* pbuf) +{ + uint32_t deviceserial0, deviceserial1, deviceserial2; + + deviceserial0 = *(uint32_t*)DEVICE_ID1; + deviceserial1 = *(uint32_t*)DEVICE_ID2; + deviceserial2 = *(uint32_t*)DEVICE_ID3; + + deviceserial0 += deviceserial2; + + if (deviceserial0 != 0) + { + IntToUnicode(deviceserial0, pbuf, 8); + pbuf += 16; + IntToUnicode(deviceserial1, pbuf, 4); + } +} + +/* + * Handles the GET_DESCRIPTOR callback. All required descriptors must be + * handled here. + */ +static const USBDescriptor *get_descriptor(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang) { + + (void)usbp; + (void)lang; + + switch (dtype) { + case USB_DESCRIPTOR_DEVICE: + return &vcom_device_descriptor; + case USB_DESCRIPTOR_CONFIGURATION: + return &vcom_configuration_descriptor; + case USB_DESCRIPTOR_STRING: + if (dindex < 4) + { + if(dindex == 3) + { + // request is for serial number + // get it from the silicon unique ID + Get_SerialNum((uint8_t*)&usb_serial_number.bPropertyData[INDEX_OF_WCHAR_FOR_UNIQUE_ID]); + } + + return &vcom_strings[dindex]; + } + } + return NULL; +} + +/** + * @brief IN EP1 state. + */ +static USBInEndpointState ep1instate; + +/** + * @brief OUT EP1 state. + */ +static USBOutEndpointState ep1outstate; + +/** + * @brief EP1 initialization structure (both IN and OUT). + */ +static const USBEndpointConfig ep1config = { + USB_EP_MODE_TYPE_BULK, + NULL, + sduDataTransmitted, + sduDataReceived, + 0x0040, + 0x0040, + &ep1instate, + &ep1outstate, + 2, + NULL +}; + +/** + * @brief IN EP2 state. + */ +static USBInEndpointState ep2instate; + +/** + * @brief EP2 initialization structure (IN only). + */ +static const USBEndpointConfig ep2config = { + USB_EP_MODE_TYPE_INTR, + NULL, + sduInterruptTransmitted, + NULL, + 0x0010, + 0x0000, + &ep2instate, + NULL, + 1, + NULL +}; + +/* + * Handles the USB driver global events. + */ +static void usb_event(USBDriver *usbp, usbevent_t event) { + extern SerialUSBDriver SDU1; + + switch (event) { + case USB_EVENT_ADDRESS: + return; + case USB_EVENT_CONFIGURED: + chSysLockFromISR(); + + if (usbp->state == USB_ACTIVE) { + /* Enables the endpoints specified into the configuration. + Note, this callback is invoked from an ISR so I-Class functions + must be used.*/ + usbInitEndpointI(usbp, USBD2_DATA_REQUEST_EP, &ep1config); + usbInitEndpointI(usbp, USBD2_INTERRUPT_REQUEST_EP, &ep2config); + + /* Resetting the state of the CDC subsystem.*/ + sduConfigureHookI(&SDU1); + } + else if (usbp->state == USB_SELECTED) { + usbDisableEndpointsI(usbp); + } + + chSysUnlockFromISR(); + return; + case USB_EVENT_RESET: + /* Falls into.*/ + case USB_EVENT_UNCONFIGURED: + /* Falls into.*/ + case USB_EVENT_SUSPEND: + chSysLockFromISR(); + + /* Disconnection event on suspend.*/ + sduSuspendHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_WAKEUP: + chSysLockFromISR(); + + /* Disconnection event on suspend.*/ + sduWakeupHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_STALLED: + return; + } + return; +} + +/* + * Handling messages not implemented in the default handler nor in the + * SerialUSB handler. + */ +static bool requests_hook(USBDriver *usbp) { + + if (((usbp->setup[0] & USB_RTYPE_RECIPIENT_MASK) == USB_RTYPE_RECIPIENT_INTERFACE) && + (usbp->setup[1] == USB_REQ_SET_INTERFACE)) { + usbSetupTransfer(usbp, NULL, 0, NULL); + return true; + } + return sduRequestsHook(usbp); +} + +/* + * Handles the USB driver global events. + */ +static void sof_handler(USBDriver *usbp) { + + (void)usbp; + + osalSysLockFromISR(); + sduSOFHookI(&SDU1); + osalSysUnlockFromISR(); +} + +/* + * USB driver configuration. + */ +const USBConfig usbcfg = { + usb_event, + get_descriptor, + requests_hook, + sof_handler +}; + +/* + * Serial over USB driver configuration. + */ +const SerialUSBConfig serusbcfg = { + &USBD1, + USBD2_DATA_REQUEST_EP, + USBD2_DATA_AVAILABLE_EP, + USBD2_INTERRUPT_REQUEST_EP +}; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/common/usbcfg.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/common/usbcfg.h new file mode 100644 index 00000000..167e1df8 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/common/usbcfg.h @@ -0,0 +1,17 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef USBCFG_H +#define USBCFG_H + +extern const USBConfig usbcfg; +extern SerialUSBConfig serusbcfg; +extern SerialUSBDriver SDU1; + +#endif /* USBCFG_H */ + +/** @} */ + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/ffconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/ffconf.h new file mode 100644 index 00000000..85b623af --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/ffconf.h @@ -0,0 +1,272 @@ +/* CHIBIOS FIX */ +#include "ch.h" + +/*---------------------------------------------------------------------------/ +/ FatFs - Configuration file +/---------------------------------------------------------------------------*/ + +#define FFCONF_DEF 87030 /* Revision ID */ + +/*---------------------------------------------------------------------------/ +/ Function Configurations +/---------------------------------------------------------------------------*/ + +#define FF_FS_READONLY 0 +/* This option switches read-only configuration. (0:Read/Write or 1:Read-only) +/ Read-only configuration removes writing API functions, f_write(), f_sync(), +/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree() +/ and optional writing functions as well. */ + + +#define FF_FS_MINIMIZE 0 +/* This option defines minimization level to remove some basic API functions. +/ +/ 0: All basic functions are enabled. +/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename() +/ are removed. +/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1. +/ 3: f_lseek() function is removed in addition to 2. */ + + +#define FF_USE_STRFUNC 1 +/* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf(). +/ +/ 0: Disable string functions. +/ 1: Enable without LF-CRLF conversion. +/ 2: Enable with LF-CRLF conversion. */ + + +#define FF_USE_FIND 1 +/* This option switches filtered directory read functions, f_findfirst() and +/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */ + + +#define FF_USE_MKFS 0 +/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */ + + +#define FF_USE_FASTSEEK 0 +/* This option switches fast seek function. (0:Disable or 1:Enable) */ + + +#define FF_USE_EXPAND 0 +/* This option switches f_expand function. (0:Disable or 1:Enable) */ + + +#define FF_USE_CHMOD 0 +/* This option switches attribute manipulation functions, f_chmod() and f_utime(). +/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */ + + +#define FF_USE_LABEL 1 +/* This option switches volume label functions, f_getlabel() and f_setlabel(). +/ (0:Disable or 1:Enable) */ + + +#define FF_USE_FORWARD 0 +/* This option switches f_forward() function. (0:Disable or 1:Enable) */ + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/---------------------------------------------------------------------------*/ + +#define FF_CODE_PAGE 850 +/* This option specifies the OEM code page to be used on the target system. +/ Incorrect code page setting can cause a file open failure. +/ +/ 437 - U.S. +/ 720 - Arabic +/ 737 - Greek +/ 771 - KBL +/ 775 - Baltic +/ 850 - Latin 1 +/ 852 - Latin 2 +/ 855 - Cyrillic +/ 857 - Turkish +/ 860 - Portuguese +/ 861 - Icelandic +/ 862 - Hebrew +/ 863 - Canadian French +/ 864 - Arabic +/ 865 - Nordic +/ 866 - Russian +/ 869 - Greek 2 +/ 932 - Japanese (DBCS) +/ 936 - Simplified Chinese (DBCS) +/ 949 - Korean (DBCS) +/ 950 - Traditional Chinese (DBCS) +/ 0 - Include all code pages above and configured by f_setcp() +*/ + + +#define FF_USE_LFN 3 +#define FF_MAX_LFN 255 +/* The FF_USE_LFN switches the support for LFN (long file name). +/ +/ 0: Disable LFN. FF_MAX_LFN has no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ To enable the LFN, Unicode handling functions (option/unicode.c) must be added +/ to the project. The working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and +/ additional 608 bytes at exFAT enabled. FF_MAX_LFN can be in range from 12 to 255. +/ It should be set 255 to support full featured LFN operations. +/ When use stack for the working buffer, take care on stack overflow. When use heap +/ memory for the working buffer, memory management functions, ff_memalloc() and +/ ff_memfree(), must be added to the project. */ + + +#define FF_LFN_UNICODE 0 +/* This option switches character encoding on the API, 0:ANSI/OEM or 1:UTF-16, +/ when LFN is enabled. Also behavior of string I/O functions will be affected by +/ this option. When LFN is not enabled, this option has no effect. +*/ + + +#define FF_STRF_ENCODE 3 +/* When FF_LFN_UNICODE = 1 with LFN enabled, string I/O functions, f_gets(), +/ f_putc(), f_puts and f_printf() convert the character encoding in it. +/ This option selects assumption of character encoding ON THE FILE to be +/ read/written via those functions. +/ +/ 0: ANSI/OEM +/ 1: UTF-16LE +/ 2: UTF-16BE +/ 3: UTF-8 +*/ + + +#define FF_FS_RPATH 2 +/* This option configures support for relative path. +/ +/ 0: Disable relative path and remove related functions. +/ 1: Enable relative path. f_chdir() and f_chdrive() are available. +/ 2: f_getcwd() function is available in addition to 1. +*/ + + +/*---------------------------------------------------------------------------/ +/ Drive/Volume Configurations +/---------------------------------------------------------------------------*/ + +#define FF_VOLUMES 3 +/* Number of volumes (logical drives) to be used. (1-10) */ + + +#define FF_STR_VOLUME_ID 1 +#define FF_VOLUME_STRS "D","E","F" +/* FF_STR_VOLUME_ID switches string support for volume ID. +/ When FF_STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive +/ number in the path name. FF_VOLUME_STRS defines the drive ID strings for each +/ logical drives. Number of items must be equal to FF_VOLUMES. Valid characters for +/ the drive ID strings are: A-Z and 0-9. */ + + +#define FF_MULTI_PARTITION 0 +/* This option switches support for multiple volumes on the physical drive. +/ By default (0), each logical drive number is bound to the same physical drive +/ number and only an FAT volume found on the physical drive will be mounted. +/ When this function is enabled (1), each logical drive number can be bound to +/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk() +/ funciton will be available. */ + + +#define FF_MIN_SS 512 +#define FF_MAX_SS 512 +/* This set of options configures the range of sector size to be supported. (512, +/ 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and +/ harddisk. But a larger value may be required for on-board flash memory and some +/ type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured +/ for variable sector size mode and disk_ioctl() function needs to implement +/ GET_SECTOR_SIZE command. */ + + +#define FF_USE_TRIM 0 +/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable) +/ To enable Trim function, also CTRL_TRIM command should be implemented to the +/ disk_ioctl() function. */ + + +#define FF_FS_NOFSINFO 0 +/* If you need to know correct free space on the FAT32 volume, set bit 0 of this +/ option, and f_getfree() function at first time after volume mount will force +/ a full FAT scan. Bit 1 controls the use of last allocated cluster number. +/ +/ bit0=0: Use free cluster count in the FSINFO if available. +/ bit0=1: Do not trust free cluster count in the FSINFO. +/ bit1=0: Use last allocated cluster number in the FSINFO if available. +/ bit1=1: Do not trust last allocated cluster number in the FSINFO. +*/ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/---------------------------------------------------------------------------*/ + +#define FF_FS_TINY 0 +/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny) +/ At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes. +/ Instead of private sector buffer eliminated from the file object, common sector +/ buffer in the filesystem object (FATFS) is used for the file data transfer. */ + + +#define FF_FS_EXFAT 0 +/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable) +/ When enable exFAT, also LFN needs to be enabled. +/ Note that enabling exFAT discards ANSI C (C89) compatibility. */ + + +#define FF_FS_NORTC 1 +#define FF_NORTC_MON 8 +#define FF_NORTC_MDAY 1 +#define FF_NORTC_YEAR 2018 +/* The option FF_FS_NORTC switches timestamp functiton. If the system does not have +/ any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable +/ the timestamp function. All objects modified by FatFs will have a fixed timestamp +/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time. +/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be +/ added to the project to read current time form real-time clock. FF_NORTC_MON, +/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect. +/ These options have no effect at read-only configuration (FF_FS_READONLY = 1). */ + + +#define FF_FS_LOCK 0 +/* The option FF_FS_LOCK switches file lock function to control duplicated file open +/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY +/ is 1. +/ +/ 0: Disable file lock function. To avoid volume corruption, application program +/ should avoid illegal open, remove and rename to the open objects. +/ >0: Enable file lock function. The value defines how many files/sub-directories +/ can be opened simultaneously under file lock control. Note that the file +/ lock control is independent of re-entrancy. */ + + +#define FF_FS_REENTRANT 1 +#define FF_FS_TIMEOUT TIME_MS2I(1000) +#define FF_SYNC_t semaphore_t* +/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs +/ module itself. Note that regardless of this option, file access to different +/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs() +/ and f_fdisk() function, are always not re-entrant. Only file/directory access +/ to the same volume is under control of this function. +/ +/ 0: Disable re-entrancy. FF_FS_TIMEOUT and FF_SYNC_t have no effect. +/ 1: Enable re-entrancy. Also user provided synchronization handlers, +/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj() +/ function, must be added to the project. Samples are available in +/ option/syscall.c. +/ +/ The FF_FS_TIMEOUT defines timeout period in unit of time tick. +/ The FF_SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*, +/ SemaphoreHandle_t and etc. A header file for O/S definitions needs to be +/ included somewhere in the scope of ff.h. */ + +/* #include // O/S definitions */ + + + +/*--- End of configuration options ---*/ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/managed_helpers/NETDUINO3_WIFI.Adc.cs b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/managed_helpers/NETDUINO3_WIFI.Adc.cs new file mode 100644 index 00000000..825543d5 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/managed_helpers/NETDUINO3_WIFI.Adc.cs @@ -0,0 +1,58 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +namespace nanoFramework.Targets.NETDUINO3_WIFI +{ + /// + /// Enumeration of ADC channels available in NETDUINO3_WIFI + /// + public static class AdcChannels + { + /// + /// Channel 0, connected to PC0 (ADC1 - IN10) + /// + public const int Channel_0 = 0; + + /// + /// Channel 1, connected to PC1 (ADC1 - IN11) + /// + public const int Channel_1 = 1; + + /// + /// Channel 2, connected to PC2 (ADC2 - IN14) + /// + public const int Channel_2 = 2; + + /// + /// Channel 3, connected to PC3 (ADC2 - IN15) + /// + public const int Channel_3 = 3; + + /// + /// Channel 4, connected to PC4 (ADC3 - IN12) + /// + public const int Channel_4 = 4; + + /// + /// Channel 5, connected to PC5 (ADC3 - IN13) + /// + public const int Channel_5 = 5; + + /// + /// Channel 6, internal temperature sensor, connected to ADC1 + /// + public const int Channel_TemperatureSensor = 6; + + /// + /// Channel 7, internal voltage reference, connected to ADC1 + /// + public const int Channel_VrefIn = 7; + + /// + /// Channel 8, connected to VBatt pin, ADC1 + /// + public const int Channel_Vbatt = 8; + } +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/managed_helpers/README.md b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/managed_helpers/README.md new file mode 100644 index 00000000..d3c16dd1 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/managed_helpers/README.md @@ -0,0 +1,5 @@ +## Managed code helpers + +This folder contains helper classes to make developers life easier when coding for this target board. + +* [Adc](NETDUINO3_WIFI.Adc.cs) diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/managed_helpers/package.nuspec b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/managed_helpers/package.nuspec new file mode 100644 index 00000000..4a89a9c1 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/managed_helpers/package.nuspec @@ -0,0 +1,28 @@ + + + + nanoFramework.Targets.NETDUINO3_WIFI + nanoFramework.Targets.NETDUINO3_WIFI + 1.0.0 + nanoFramework project contributors + nanoFramework project contributors + false + + Helper classes to use NETDUINO3_WIFI target in C# applications. + + + + + This is an extension for .NET nanoFramework enhacing support for Windows.Devices.Gpio.GpioController when using STM32 MCUs. + + https://github.com/nanoframework + https://secure.gravatar.com/avatar/97d0e092247f0716db6d4b47b7d1d1ad + https://github.com/nanoframework/nf-interpreter/blob/develop/LICENSE.md + Copyright (c) 2019 The nanoFramework project contributors + + nanoFramework, nano Framework, NETNF, NETMF, Micro Framework, STM32, .net, NETDUINO3_WIFI + + + + + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/CMakeLists.txt new file mode 100644 index 00000000..291f47e1 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/CMakeLists.txt @@ -0,0 +1,9 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# # append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/chconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/chconf.h new file mode 100644 index 00000000..13cec578 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/chconf.h @@ -0,0 +1,616 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 10000 + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#define CH_CFG_INTERVALS_SIZE 32 + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_TIME_TYPES_SIZE 32 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES FALSE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS FALSE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT FALSE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES FALSE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_OBJ_FIFOS TRUE + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#define CH_CFG_USE_FACTORY FALSE + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 + +/** + * @brief Enables the registry of generic objects. + */ +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE + +/** + * @brief Enables factory for generic buffers. + */ +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE + +/** + * @brief Enables factory for semaphores. + */ +#define CH_CFG_FACTORY_SEMAPHORES TRUE + +/** + * @brief Enables factory for mailboxes. + */ +#define CH_CFG_FACTORY_MAILBOXES TRUE + +/** + * @brief Enables factory for objects FIFOs. + */ +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/halconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/halconf.h new file mode 100644 index 00000000..b970c22f --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/halconf.h @@ -0,0 +1,513 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/halconf_nf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/halconf_nf.h new file mode 100644 index 00000000..809a6cfa --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/halconf_nf.h @@ -0,0 +1,15 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +#endif // _HALCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/main.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/main.c new file mode 100644 index 00000000..f10973a0 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/main.c @@ -0,0 +1,77 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); + +// Application entry point. +int main(void) { + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // check for valid CLR image at address contiguous to nanoBooter + // this target DOES NOT have configuration block, so we need to use the __nanoImage_end__ address here + if(CheckValidCLRImage((uint32_t)&__nanoImage_end__)) + { + // there seems to be a valid CLR image + // launch nanoCLR + LaunchCLR((uint32_t)&__nanoImage_end__); + } + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // Initializes a serial-over-USB CDC driver. + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + // Activates the USB driver and then the USB bus pull-up on D+. + // Note, a delay is inserted in order to not have to disconnect the cable after a reset. + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1500); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // Normal main() thread + while (true) { + palClearPad(GPIOE, GPIOE_LED_GOPORT3); + palSetPad(GPIOA, GPIOA_USR_LED); + osDelay(250); + palClearPad(GPIOA, GPIOA_USR_LED); + palSetPad(GPIOE, GPIOE_LED_GOPORT1); + osDelay(250); + palClearPad(GPIOE, GPIOE_LED_GOPORT1); + palSetPad(GPIOE, GPIOE_LED_GOPORT2); + osDelay(250); + palClearPad(GPIOE, GPIOE_LED_GOPORT2); + palSetPad(GPIOE, GPIOE_LED_GOPORT3); + osDelay(250); + } +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/mcuconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/mcuconf.h new file mode 100644 index 00000000..0ac31e2c --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/mcuconf.h @@ -0,0 +1,335 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 25 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 +#define STM32_I2SSRC STM32_I2SSRC_PLLI2S +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 2 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 250 +#define STM32_SDC_READ_TIMEOUT_MS 25 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/mcuconf_nf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/mcuconf_nf.h new file mode 100644 index 00000000..574b9636 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/mcuconf_nf.h @@ -0,0 +1,10 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/netduino3wifi_booter-DEBUG.ld b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/netduino3wifi_booter-DEBUG.ld new file mode 100644 index 00000000..505f0a7a --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/netduino3wifi_booter-DEBUG.ld @@ -0,0 +1,80 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F427Vx memory setup. + * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash : org = 0x08000000, len = 32k /* space reserved for nanoBooter (1st two sectors 0x08000000 to 0x08007FFF)*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */ + ram1 : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20020000, len = 64k /* SRAM3 */ + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram4); + +/* Stacks rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/netduino3wifi_booter.ld b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/netduino3wifi_booter.ld new file mode 100644 index 00000000..31588162 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/netduino3wifi_booter.ld @@ -0,0 +1,80 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F427Vx memory setup. + * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash : org = 0x08000000, len = 16k /* space reserved for nanoBooter (1st sector 0x08000000 to 0x08003FFF)*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */ + ram1 : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20020000, len = 64k /* SRAM3 */ + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram4); + +/* Stacks rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/target_board.h.in b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/target_board.h.in new file mode 100644 index 00000000..19531d9c --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoBooter/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOBOOTER_H_ */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/CMakeLists.txt new file mode 100644 index 00000000..e5496b7e --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/chconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/chconf.h new file mode 100644 index 00000000..390ce3a6 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/chconf.h @@ -0,0 +1,616 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 10000 + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#define CH_CFG_INTERVALS_SIZE 32 + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_TIME_TYPES_SIZE 32 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_OBJ_FIFOS TRUE + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#define CH_CFG_USE_FACTORY FALSE + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 + +/** + * @brief Enables the registry of generic objects. + */ +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE + +/** + * @brief Enables factory for generic buffers. + */ +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE + +/** + * @brief Enables factory for semaphores. + */ +#define CH_CFG_FACTORY_SEMAPHORES TRUE + +/** + * @brief Enables factory for mailboxes. + */ +#define CH_CFG_FACTORY_MAILBOXES TRUE + +/** + * @brief Enables factory for objects FIFOs. + */ +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/halconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/halconf.h new file mode 100644 index 00000000..264cfad6 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/halconf.h @@ -0,0 +1,525 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +// #define HAL_USE_ADC TRUE +// #endif + +/** + * @brief Enables the CAN subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +// #define HAL_USE_CAN FALSE +// #endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +// /** +// * @brief Enables the DAC subsystem. +// */ +// #if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +// #define HAL_USE_DAC FALSE +// #endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +// this option is set at target_platform.h (from config file) +//#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +//#define HAL_USE_I2C TRUE +//#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +// #define HAL_USE_MAC TRUE +// #endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +// #define HAL_USE_PWM TRUE +// #endif + +/** + * @brief Enables the RTC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +// #define HAL_USE_RTC TRUE +// #endif + +/** + * @brief Enables the SDC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +// #define HAL_USE_SDC FALSE +// #endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + + +/** + * @brief Enables the SPI subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +// #define HAL_USE_SPI TRUE +// #endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +// #define HAL_USE_UART FALSE +// #endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +// #define HAL_USE_WDG FALSE +// #endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS TRUE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/halconf_nf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/halconf_nf.h new file mode 100644 index 00000000..af4677fe --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/halconf_nf.h @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +// enables STM32 Can driver +#if !defined(HAL_USE_STM32_CAN) +#define HAL_USE_STM32_CAN TRUE +#endif + +#endif // _HALCONF_NF_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/main.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/main.c new file mode 100644 index 00000000..1902b00c --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/main.c @@ -0,0 +1,104 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include "usbcfg.h" +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); +// declare CLRStartup thread here +osThreadDef(CLRStartupThread, osPriorityNormal, 4096, "CLRStartupThread"); + +// Application entry point. +int main(void) { + + // find out wakeup reason + if((RTC->ISR & RTC_ISR_ALRAF) == RTC_ISR_ALRAF) + { + // standby, match WakeupReason_FromStandby enum + WakeupReasonStore = 1; + } + else if((PWR->CSR & PWR_CSR_WUF) == PWR_CSR_WUF) + { + // wake from pin, match WakeupReason_FromPin enum + WakeupReasonStore = 2; + } + else + { + // undetermined reason, match WakeupReason_Undetermined enum + WakeupReasonStore = 0; + } + + // first things first: need to clear any possible wakeup flags + // if this is not done here the next standby -> wakeup sequence won't work + CLEAR_BIT(RTC->CR, RTC_CR_ALRAIE); + CLEAR_BIT(RTC->ISR, RTC_ISR_ALRAF); + SET_BIT(PWR->CR, PWR_CR_CWUF); + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init SWO as soon as possible to make it available to output ASAP + #if (SWO_OUTPUT == TRUE) + SwoInit(); + #endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // start watchdog + /////////////////////////////////////////////////////////////////////////////////////////////////////// + // for STM32F4 family if watchdog is enabled can't use standby mode because the IWDG can't be stoped // + /////////////////////////////////////////////////////////////////////////////////////////////////////// + Watchdog_Init(); + + // Initializes a serial-over-USB CDC driver. + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + // Activates the USB driver and then the USB bus pull-up on D+. + // Note, a delay is inserted in order to not have to disconnect the cable after a reset + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1500); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // CLR settings to launch CLR thread + CLR_SETTINGS clrSettings; + (void)memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.EnterDebuggerLoopAfterExit = true; + + // create the CLR Startup thread + osThreadCreate(osThread(CLRStartupThread), &clrSettings); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + while (true) { + osDelay(100); + } +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/mcuconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/mcuconf.h new file mode 100644 index 00000000..01dd9af2 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/mcuconf.h @@ -0,0 +1,357 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 25 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#define STM32_RTCPRE_VALUE 25 +#define STM32_RTC_PRESA_VALUE 125 +#define STM32_RTC_PRESS_VALUE 8000 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 +#define STM32_I2SSRC STM32_I2SSRC_PLLI2S +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 2 +#define STM32_PLLI2SQ_VALUE 2 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 TRUE +#define STM32_ADC_USE_ADC3 TRUE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_USE_CAN2 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE TRUE +#define STM32_DAC_USE_DAC1_CH1 TRUE +#define STM32_DAC_USE_DAC1_CH2 TRUE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 TRUE +#define STM32_PWM_USE_TIM8 TRUE +#define STM32_PWM_USE_TIM9 TRUE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 1000 +#define STM32_SDC_READ_TIMEOUT_MS 1000 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 +#define STM32_SERIAL_UART7_PRIORITY 12 +#define STM32_SERIAL_UART8_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE +#define STM32_SPI_USE_SPI4 TRUE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 TRUE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 TRUE +#define STM32_UART_USE_UART7 FALSE +#define STM32_UART_USE_UART8 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(0, 0) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(0, 0) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(0, 0) +#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(0, 0) +#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_UART7_IRQ_PRIORITY 12 +#define STM32_UART_UART8_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_UART7_DMA_PRIORITY 0 +#define STM32_UART_UART8_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG TRUE + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/mcuconf_nf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/mcuconf_nf.h new file mode 100644 index 00000000..5ff03534 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/mcuconf_nf.h @@ -0,0 +1,9 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/nanoHAL.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/nanoHAL.cpp new file mode 100644 index 00000000..076a50fc --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/nanoHAL.cpp @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +void HAL_EnterBooterMode() +{ +} + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/netduino3wifi_CLR-DEBUG.ld b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/netduino3wifi_CLR-DEBUG.ld new file mode 100644 index 00000000..d2ef582b --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/netduino3wifi_CLR-DEBUG.ld @@ -0,0 +1,76 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F427Vx memory setup. + * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash : org = 0x08008000, len = 2M - 32k - 1408k /* flash size less the space reserved for nanoBooter and application deployment*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x080A0000, len = 1408k /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */ + ram1 : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20020000, len = 64k /* SRAM3 */ + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram4); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/netduino3wifi_CLR.ld b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/netduino3wifi_CLR.ld new file mode 100644 index 00000000..5a59730e --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/netduino3wifi_CLR.ld @@ -0,0 +1,76 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F427Vx memory setup. + * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash : org = 0x08004000, len = 2M - 16k - 1792k /* flash size less the space reserved for nanoBooter and application deployment*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x08040000, len = 1792k /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */ + ram1 : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20020000, len = 64k /* SRAM3 */ + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram4); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/target_board.h.in b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/target_board.h.in new file mode 100644 index 00000000..b980bc05 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOCLR_H_ */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_BlockStorage.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_BlockStorage.c new file mode 100644 index 00000000..9e7c7f55 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_BlockStorage.c @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice STM32Flash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &STM32Flash_BlockStorageInterface, &Device_BlockStorageConfig, false); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_BlockStorage.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_BlockStorage.h new file mode 100644 index 00000000..aa50b1b7 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_common.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_common.c new file mode 100644 index 00000000..ccee7c5e --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_common.c @@ -0,0 +1,31 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include "target_common.h" +#include + +HAL_SYSTEM_CONFIG HalSystemConfig = +{ + { true }, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, //ConvertCOM_DebugHandle(1), + 0, //ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + { RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size }, + { FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size } +}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; + +// this target use DFU for updates +uint32_t GetTargetCapabilities() +{ + return TargetCapabilities_DfuUpdate; +}; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_common.h.in b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_common.h.in new file mode 100644 index 00000000..563fe883 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_common.h.in @@ -0,0 +1,38 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x200000C0) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x00030000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x08000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00200000) + +///////////////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////// +#define TARGETNAMESTRING "@CHIBIOS_BOARD@" +#define PLATFORMNAMESTRING "STM32F4" +////////////////////////////////////////////// + + +#endif /* _TARGET_COMMON_H_ */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_nf_devices_can_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_nf_devices_can_config.cpp new file mode 100644 index 00000000..7dbe7ff1 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_nf_devices_can_config.cpp @@ -0,0 +1,44 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_nf_devices_can_config.h" +#include + +/////////// +// CAN1 // +/////////// + +// pin configuration for CAN1 +// port for TX pin is: GPIOB +// TX pin: is GPIOB_09 +// port for RX pin is: GPIOB +// RX pin: is GPIOB_08 +// GPIO alternate pin function is 9 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in STM32F405xx/STM32F407xx datasheet) +CAN_CONFIG_PINS(1, GPIOB, GPIOB, 9, 8, 9) + +// buffer +CANRxFrame Can1_MsgBuffer[CAN1_RX_BUFFER_SIZE]; + +// initialization for CAN1 +CAN_INIT(1, CAN1_RX_BUFFER_SIZE) + +/////////// +// CAN2 // +/////////// + +// pin configuration for CAN2 +// port for TX pin is: GPIOB +// TX pin: is GPIOB_06 +// port for RX pin is: GPIOB +// RX pin: is GPIOB_05 +// GPIO alternate pin function is 9 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in STM32F405xx/STM32F407xx datasheet) +CAN_CONFIG_PINS(2, GPIOB, GPIOB, 6, 5, 9) + +// buffer +CANRxFrame Can2_MsgBuffer[CAN2_RX_BUFFER_SIZE]; + +// initialization for CAN1 +CAN_INIT(2, CAN2_RX_BUFFER_SIZE) diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_nf_devices_can_config.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_nf_devices_can_config.h new file mode 100644 index 00000000..adc8ace3 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_nf_devices_can_config.h @@ -0,0 +1,25 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +////////// +// CAN1 // +////////// + +// enable CAN1 +#define NF_CAN_STM32_CAN_USE_CAN1 TRUE + +// buffers size +#define CAN1_RX_BUFFER_SIZE 16 + +////////// +// CAN2 // +////////// + +// enable CAN2 +#define NF_CAN_STM32_CAN_USE_CAN2 TRUE + +// buffers size +#define CAN2_RX_BUFFER_SIZE 16 diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_nf_devices_onewire_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_nf_devices_onewire_config.cpp new file mode 100644 index 00000000..89ad1d83 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_nf_devices_onewire_config.cpp @@ -0,0 +1,29 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_nf_devices_onewire_config.h" +#include + +/////////// +// UART6 // +/////////// + +// pin configuration for UART6 +// port for TX pin is: GPIOC +// TX pin: is GPIOC_6 +// GPIO alternate pin function is 8 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in STM32F405xx/STM32F407xx datasheet) +UART_CONFIG_PINS(6, GPIOC, 6, 8) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart6_TxBuffer[UART6_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart6_RxBuffer[UART6_RX_SIZE]; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_nf_devices_onewire_config.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_nf_devices_onewire_config.h new file mode 100644 index 00000000..d0fb1c87 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_nf_devices_onewire_config.h @@ -0,0 +1,17 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////// +// UART6 // +/////////// + +// enable USART6 +#define NF_ONEWIRE_STM32_UART_USE_USART6 TRUE + +// buffers size +// tx buffer size: 32 bytes +#define UART6_TX_SIZE 32 +// rx buffer size: 32 bytes +#define UART6_RX_SIZE 32 \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_system_devices_dac_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_system_devices_dac_config.cpp new file mode 100644 index 00000000..97181d6f --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_system_devices_dac_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T HAVE SUPPORT FOR DAC PINS // +////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_windows_devices_adc_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_windows_devices_adc_config.cpp new file mode 100644 index 00000000..362011df --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_windows_devices_adc_config.cpp @@ -0,0 +1,29 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // ADC1 + {1, GPIOC, 0, ADC_CHANNEL_IN10}, + {1, GPIOC, 1, ADC_CHANNEL_IN11}, + + // ADC2 + {2, GPIOC, 2, ADC_CHANNEL_IN14}, + {2, GPIOC, 3, ADC_CHANNEL_IN15}, + + // ADC3 + {3, GPIOC, 4, ADC_CHANNEL_IN12}, + {3, GPIOC, 5, ADC_CHANNEL_IN13}, + + // these are the internal sources, available only at ADC1 + {1, NULL, 0, ADC_CHANNEL_SENSOR}, + {1, NULL, 0, ADC_CHANNEL_VREFINT}, + {1, NULL, 0, ADC_CHANNEL_VBAT}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_windows_devices_i2c_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_windows_devices_i2c_config.cpp new file mode 100644 index 00000000..18b1cd19 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_windows_devices_i2c_config.cpp @@ -0,0 +1,18 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for SCL pin is: GPIOB +// port for SDA pin is: GPIOB +// SCL pin: is GPIOB_6 +// SDA pin: is GPIOB_7 +// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, GPIOB, GPIOB, 6, 7, 4) diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_windows_devices_serialcommunication_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_windows_devices_serialcommunication_config.cpp new file mode 100644 index 00000000..6f13e26c --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_windows_devices_serialcommunication_config.cpp @@ -0,0 +1,67 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_windows_devices_serialcommunication_config.h" +#include + +/////////// +// UART3 // +/////////// + +// pin configuration for UART3 +// port for TX pin is: GPIOD +// port for RX pin is: GPIOD +// TX pin: is GPIOD_8 +// RX pin: is GPIOD_9 +// GPIO alternate pin function is 7 (see "Table 12. STM32F427xx and STM32F429xx alternate function mapping" in STM32F427xx and STM32F429xx datasheet) +UART_CONFIG_PINS(3, GPIOD, GPIOD, 8, 9, 7) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart3_TxBuffer[UART3_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart3_RxBuffer[UART3_RX_SIZE]; + +// initialization for UART3 +UART_INIT(3, UART3_TX_SIZE, UART3_RX_SIZE) + +// un-initialization for UART3 +UART_UNINIT(3) + +// /////////// +// // UART6 // +// /////////// + +// // pin configuration for UART6 +// // port for TX pin is: GPIOC +// // port for RX pin is: GPIOC +// // TX pin: is GPIOC_6 +// // RX pin: is GPIOC_7 +// // GPIO alternate pin function is 7 (see "Table 12. STM32F427xx and STM32F429xx alternate function mapping" in STM32F427xx and STM32F429xx datasheet) +// UART_CONFIG_PINS(6, GPIOC, GPIOC, 6, 7, 8) + +// // buffers +// // buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// // because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +// #if defined(__GNUC__) +// __attribute__((aligned (32))) +// #endif +// uint8_t Uart6_TxBuffer[UART6_TX_SIZE]; +// #if defined(__GNUC__) +// __attribute__((aligned (32))) +// #endif +// uint8_t Uart6_RxBuffer[UART6_RX_SIZE]; + +// // initialization for UART6 +// UART_INIT(6, UART6_TX_SIZE, UART6_RX_SIZE) + +// // un-initialization for UART6 +// UART_UNINIT(6) diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_windows_devices_serialcommunication_config.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_windows_devices_serialcommunication_config.h new file mode 100644 index 00000000..07dc7c6f --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_windows_devices_serialcommunication_config.h @@ -0,0 +1,31 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////// +// UART3 // +/////////// + +// enable USART3 +#define NF_SERIAL_COMM_STM32_UART_USE_USART3 TRUE + +// buffers size +// tx buffer size: 256 bytes +#define UART3_TX_SIZE 256 +// rx buffer size: 256 bytes +#define UART3_RX_SIZE 256 + + +// /////////// +// // UART6 // +// /////////// + +// // enable USART6 +// #define NF_SERIAL_COMM_STM32_UART_USE_USART6 TRUE + +// // buffers size +// // tx buffer size: 256 bytes +// #define UART6_TX_SIZE 256 +// // rx buffer size: 256 bytes +// #define UART6_RX_SIZE 256 diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_windows_devices_spi_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_windows_devices_spi_config.cpp new file mode 100644 index 00000000..76238dbe --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_windows_devices_spi_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_windows_storage_config.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_windows_storage_config.h new file mode 100644 index 00000000..8601cffd --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_windows_storage_config.h @@ -0,0 +1,13 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +// maps the SD Card driver +#define SD_CARD_DRIVER SDCD1 + +// maps the SD Card detect GPIO definition (in Target_Windows_Storage.c) to board GPIO line (in board.h) +#define SDCARD_LINE_DETECT LINE_SD_DETECT + +// includes SPIFFS in storage +#define USE_SPIFFS_FOR_STORAGE FALSE diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/CMakeLists.txt new file mode 100644 index 00000000..d3e4d14f --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/CMakeLists.txt @@ -0,0 +1,209 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +cmake_minimum_required(VERSION 3.0) +ENABLE_LANGUAGE(ASM) + +# add header files with common OS definitions and board definitions specific for each image +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/target_common.h" @ONLY) + +set(NANOBOOTER_PROJECT_NAME "nanoBooter") +set(NANOCLR_PROJECT_NAME "nanoCLR") + +find_package(BuildUtils REQUIRED) +find_package(CHIBIOS REQUIRED) +find_package(ChibiOSnfOverlay REQUIRED) +find_package(WireProtocol REQUIRED) + +# packages for nanoFramework libraries +####################################### +# mandatory +find_package(NF_CoreCLR REQUIRED) + +####################################### +# optional + +# ChibiOS contrib repo +if(CHIBIOS_CONTRIB_REQUIRED) + find_package(ChibiOS-Contrib REQUIRED) +endif() + +# nF feature: debugger +if(NF_FEATURE_DEBUGGER) + find_package(NF_Debugger REQUIRED) + find_package(NF_Diagnostics REQUIRED) +endif() + +# nF feature: networking +if(USE_NETWORKING_OPTION) + find_package(CHIBIOS_LWIP REQUIRED) +endif() + +# nF feature: filesystem +if(USE_FILESYSTEM_OPTION) + find_package(CHIBIOS_FATFS REQUIRED) +endif() + +####################################### + + +add_subdirectory("common") +add_subdirectory("nanoBooter") +add_subdirectory("nanoCLR") + +####################### +# nanoBooter executable + +add_executable( + # executables for project, project sources + ${NANOBOOTER_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + "${CMAKE_CURRENT_SOURCE_DIR}/target_BlockStorage.c" + + # need to add configuration manager to allow get/store configuration blocks + "${PROJECT_SOURCE_DIR}/src/HAL/nanoHAL_ConfigurationManager_stubs.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOBOOTER_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOBOOTER_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOBOOTER_SOURCES} + + ${CHIBIOS_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} +) + +####################### +# nanoCLR executable + +add_executable( + # executables for project, project sources + ${NANOCLR_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOCLR_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOCLR_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOCLR_SOURCES} + + ${CHIBIOS_SOURCES} + ${CHIBIOS_CONTRIB_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} + + # sources for nanoFramework libraries + ${NF_CoreCLR_SOURCES} + ${NF_Debugger_SOURCES} + ${NF_Diagnostics_SOURCES} + + # sources for ChibiOS FatFS + ${CHIBIOS_FATFS_SOURCES} + + # sources for nanoFramework APIs + ${TARGET_NANO_APIS_SOURCES} +) + +# add dependency from ChibiOS (this is required to make sure the ChibiOS repo is downloaded before the build starts) +add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf ChibiOS) +add_dependencies(${NANOCLR_PROJECT_NAME}.elf ChibiOS) + +# include common directories +include_directories( + ${CMAKE_CURRENT_BINARY_DIR} + ${CMAKE_CURRENT_SOURCE_DIR} + ${CMAKE_CURRENT_SOURCE_DIR}/common + ${PROJECT_SOURCE_DIR}/src/CLR/Core + ${PROJECT_SOURCE_DIR}/src/CLR/Include + ${PROJECT_SOURCE_DIR}/src/HAL/Include + ${PROJECT_SOURCE_DIR}/src/PAL/Include + + ${WireProtocol_INCLUDE_DIRS} + ${CHIBIOS_INCLUDE_DIRS} + ${ChibiOSnfOverlay_INCLUDE_DIRS} + ${CHIBIOS_CONTRIB_INCLUDE_DIRS} + + ${TARGET_CMSIS_COMMON_INCLUDE_DIRS} + ${TARGET_CHIBIOS_COMMON_INCLUDE_DIRS} +) + +# include directories for nanoBooter +target_include_directories(${NANOBOOTER_PROJECT_NAME}.elf PUBLIC + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter" + ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter + + ${TARGET_CMSIS_NANOBOOTER_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOBOOTER_INCLUDE_DIRS} +) + +# include directories for nanoCLR +target_include_directories(${NANOCLR_PROJECT_NAME}.elf PUBLIC + ${CMAKE_CURRENT_BINARY_DIR}/nanoCLR + ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR + + ${TARGET_CMSIS_NANOCLR_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOCLR_INCLUDE_DIRS} + + # directories for nanoFramework libraries + ${NF_CoreCLR_INCLUDE_DIRS} + ${NF_Debugger_INCLUDE_DIRS} + ${NF_Diagnostics_INCLUDE_DIRS} + + # includes for nanoFramework APIs + ${TARGET_NANO_APIS_INCLUDES} + + # includes for ChibiOS FatFS + ${CHIBIOS_FATFS_INCLUDE_DIRS} + + # includes for ChibiOS LwIP + ${CHIBIOS_LWIP_INCLUDE_DIRS} +) + +# set compiler options +nf_set_compiler_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_options(${NANOCLR_PROJECT_NAME}.elf) + +# set compiler definitions +nf_set_compiler_definitions(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_definitions(${NANOCLR_PROJECT_NAME}.elf -DRUNTIME_MEMORY_PROFILE__extrasmall=1) + +# set linker files +if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F091xC_booter-DEBUG.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/STM32F091xC_CLR-DEBUG.ld) +else() + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F091xC_booter.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/STM32F091xC_CLR.ld) +endif() + +# set linker options +nf_set_linker_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_linker_options(${NANOCLR_PROJECT_NAME}.elf) + +# add other linker flags +########################################################### +# the sizes of CRT heap and ChibiOS stacks are defined here +set_property(TARGET ${NANOBOOTER_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x1000") +set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x2800") + +# generate output files +nf_generate_build_output_files(${NANOBOOTER_PROJECT_NAME}.elf) +nf_generate_build_output_files(${NANOCLR_PROJECT_NAME}.elf) diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/README.md b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/README.md new file mode 100644 index 00000000..6e63d062 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/README.md @@ -0,0 +1,42 @@ +## Configuration of Chibios, HAL and MCU ## + +For a successful build the following changes are required: + +In _halconf.g_ (in both nanoBooter and nanoCLR folders), when compared with a default file: +- HAL_USE_SERIAL to TRUE +- SERIAL_DEFAULT_BITRATE to 921600 +- SERIAL_BUFFERS_SIZE has to be at least 64 (2x the Wire Protocol packet size) otherwise the transmission will be garbled as the packets overrun each other + +In _mcuconf.h_ (in both nanoBooter and nanoCLR folders), when compared with a default file: +- STM32_SERIAL_USE_USART2 to TRUE + + +## Definitions for each image ## + +Any defines specific to an image (nanoBooter or nanoCLR) that are to be made available throughout the code should be added to the _target_board.h.in_. There is one in [nanoBooter](nanoBooter/target_board.h.in) and another in [nanoCLR](nanoCLR/target_board.h.in) directories, allowing different defines for each one. +Defines that are common to a target board should be added to the [_target_common.h.in_](target_common.h.in). +The content of these files is parsed by CMake. It can include CMake variables. Check the documentation of CMake config files [here](https://cmake.org/cmake/help/v3.7/command/configure_file.html?highlight=configure_file). + + +## nanoCLR image start address ## + +The start address of nanoCLR (it's vector table) is defined in the linker file (STM32F091xC.ld)[nanoCLR/STM32F091xC.ld] by setting the initial address of the _flash_ region. The total size has to be the flash region size less the space reserved for nanoBooter. + + +## Vector table copy to RAM ## + +Because the STM32F0 series don't have the SCB->VTOR register that allows offsetting the vector table another approach as to be taken: copy the vector table to a RAM location and remap the memory mode using SYSCFG->CFGR1. This is accomplished by reserving in RAM0 region the required space (in the linker file) and by performing the copy of the vector table right after the nanoCLR starts. This code block is located in main() right after the call to halInit(). + +If porting this reference board to another SMT32F0 (or L0) series make sure this piece of code is kept there. + + + + +**NOTE: this configuration was successfully tested in a NUCLEO_F091RC board using the virtual COM port through the ST Link USB connection.** + + +## Floating point + +The current build is set to add support for single-precision floating point. +Meaning that `System.Math` API supports only the `float` overloads. The `double` ones will throw a `NotImplementedException`. +There is no FPU available, so floating point is provided through software implementation. diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/common/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/common/CMakeLists.txt new file mode 100644 index 00000000..777d4ec3 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/common/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append source files required for ChibiOS interface +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c") + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/common/Device_BlockStorage-DEBUG.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 00000000..eb549300 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,67 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +//2kB block +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0 , 5 }, // 0x08000000 nanoBooter + { BlockRange_BLOCKTYPE_CODE , 6 , 101 }, // 0x08003000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 102, 127 } // 0x08033000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 128, // total number of blocks in this region + 0x800, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), // STM32 flash memory is XIP + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00040000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +__attribute__((__used__)) BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/common/Device_BlockStorage.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/common/Device_BlockStorage.c new file mode 100644 index 00000000..ecd9b529 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/common/Device_BlockStorage.c @@ -0,0 +1,66 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +//2kB block +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 4 }, // 0x08000000 nanoBooter + { BlockRange_BLOCKTYPE_CODE , 5, 83 }, // 0x08002800 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 84, 127 } // 0x0802A000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 128, // total number of blocks in this region + 0x800, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), // STM32 flash memory is XIP + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00040000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +__attribute__((__used__)) BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/common/serialcfg.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/common/serialcfg.h new file mode 100644 index 00000000..a9e1b9b5 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/common/serialcfg.h @@ -0,0 +1,15 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef SERIALCFG_H +#define SERIALCFG_H + +// define which serial driver the Wire Protocol will be using +#define SERIAL_DRIVER SD2 + +#endif /* SERIALCFG_H */ + +/** @} */ + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/CMakeLists.txt new file mode 100644 index 00000000..291f47e1 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/CMakeLists.txt @@ -0,0 +1,9 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# # append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/STM32F091xC_booter-DEBUG.ld b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/STM32F091xC_booter-DEBUG.ld new file mode 100644 index 00000000..d7a37aba --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/STM32F091xC_booter-DEBUG.ld @@ -0,0 +1,80 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + + +/* + * STM32F091xC memory setup. + */ +MEMORY +{ + flash : org = 0x08000000, len = 12k /* space reserved for nanoBooter */ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 32k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Stacks rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/STM32F091xC_booter.ld b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/STM32F091xC_booter.ld new file mode 100644 index 00000000..94753e9d --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/STM32F091xC_booter.ld @@ -0,0 +1,80 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + + +/* + * STM32F091xC memory setup. + */ +MEMORY +{ + flash : org = 0x08000000, len = 10k /* space reserved for nanoBooter */ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 32k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Stacks rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/chconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/chconf.h new file mode 100644 index 00000000..e6e3fc71 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/chconf.h @@ -0,0 +1,704 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 1000 // this is 1 millisecond +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM FALSE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES FALSE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS FALSE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT FALSE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES FALSE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY FALSE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/halconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/halconf.h new file mode 100644 index 00000000..f0824d67 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/halconf.h @@ -0,0 +1,513 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 64 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/halconf_nf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/halconf_nf.h new file mode 100644 index 00000000..e35b7bec --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/halconf_nf.h @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +#if !defined(HAL_USE_STM32_RNG) +#define HAL_USE_STM32_RNG FALSE +#endif + +#endif // _HALCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/main.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/main.c new file mode 100644 index 00000000..b8de9ab5 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/main.c @@ -0,0 +1,80 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 512, "ReceiverThread"); + +// configuration for debugger serial port +// dev notes: +// conservative baud rate value as 921600 has a high error percentage on baud rate clocking +// OVER8 bit on CR1 to further decrease baud rate clocking error +static const SerialConfig uartConfig = +{ + 460800, + USART_CR1_OVER8, + USART_CR2_STOP1_BITS, + 0 +}; + +// Application entry point. +int main(void) { + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // the following IF is not mandatory, it's just providing a way for a user to 'force' + // the board to remain in nanoBooter and not launching nanoCLR + + // if the USER button (blue one) is pressed, skip the check for a valid CLR image and remain in booter + if (palReadPad(GPIOC, GPIOC_BUTTON)) + { + // check for valid CLR image at address contiguous to nanoBooter + // this target DOES NOT have configuration block, so we need to use the __nanoImage_end__ address here + if(CheckValidCLRImage((uint32_t)&__nanoImage_end__)) + { + // there seems to be a valid CLR image + // launch nanoCLR + LaunchCLR((uint32_t)&__nanoImage_end__); + } + } + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // starts the serial driver + sdStart(&SERIAL_DRIVER, &uartConfig); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // Normal main() thread + while (true) { + palClearPad(GPIOA, GPIOA_LED_GREEN); + osDelay(500); + palSetPad(GPIOA, GPIOA_LED_GREEN); + osDelay(500); + } +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/mcuconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/mcuconf.h new file mode 100644 index 00000000..08bc4e02 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/mcuconf.h @@ -0,0 +1,246 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F0xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F0xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_HSI14_ENABLED TRUE +#define STM32_HSI48_ENABLED FALSE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 2 +#define STM32_PLLMUL_VALUE 12 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE STM32_PPRE_DIV1 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_MCOPRE STM32_MCOPRE_DIV1 +#define STM32_PLLNODIV STM32_PLLNODIV_DIV2 +#define STM32_CECSW STM32_CECSW_HSI +#define STM32_I2C1SW STM32_I2C1SW_HSI +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_RTCSEL STM32_RTCSEL_LSI + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_1_IRQ_PRIORITY 3 +#define STM32_IRQ_EXTI2_3_IRQ_PRIORITY 3 +#define STM32_IRQ_EXTI4_15_IRQ_PRIORITY 3 +#define STM32_IRQ_EXTI16_IRQ_PRIORITY 3 +#define STM32_IRQ_EXTI17_20_IRQ_PRIORITY 3 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 3 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 2 +#define STM32_GPT_TIM2_IRQ_PRIORITY 2 +#define STM32_GPT_TIM3_IRQ_PRIORITY 2 +#define STM32_GPT_TIM6_IRQ_PRIORITY 2 +#define STM32_GPT_TIM7_IRQ_PRIORITY 2 +#define STM32_GPT_TIM14_IRQ_PRIORITY 2 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_IRQ_PRIORITY 3 +#define STM32_I2C_I2C2_IRQ_PRIORITY 3 +#define STM32_I2C_USE_DMA TRUE +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI1 FALSE +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \ + STM32_I2S_MODE_RX) +#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \ + STM32_I2S_MODE_RX) +#define STM32_I2S_SPI1_IRQ_PRIORITY 2 +#define STM32_I2S_SPI2_IRQ_PRIORITY 2 +#define STM32_I2S_SPI1_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 3 +#define STM32_ICU_TIM2_IRQ_PRIORITY 3 +#define STM32_ICU_TIM3_IRQ_PRIORITY 3 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 3 +#define STM32_PWM_TIM2_IRQ_PRIORITY 3 +#define STM32_PWM_TIM3_IRQ_PRIORITY 3 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE +#define STM32_SERIAL_USART1_PRIORITY 3 +#define STM32_SERIAL_USART2_PRIORITY 3 +#define STM32_SERIAL_USART3_8_PRIORITY 3 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 2 +#define STM32_SPI_SPI2_IRQ_PRIORITY 2 +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 2 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USE_UART7 FALSE +#define STM32_UART_USE_UART8 FALSE +#define STM32_UART_USART1_IRQ_PRIORITY 3 +#define STM32_UART_USART2_IRQ_PRIORITY 3 +#define STM32_UART_USART3_8_IRQ_PRIORITY 3 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_UART7_DMA_PRIORITY 0 +#define STM32_UART_UART8_DMA_PRIORITY 0 +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/mcuconf_nf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/mcuconf_nf.h new file mode 100644 index 00000000..574b9636 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/mcuconf_nf.h @@ -0,0 +1,10 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/target_board.h.in b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/target_board.h.in new file mode 100644 index 00000000..19531d9c --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoBooter/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOBOOTER_H_ */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/CMakeLists.txt new file mode 100644 index 00000000..e5496b7e --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/STM32F091xC_CLR-DEBUG.ld b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/STM32F091xC_CLR-DEBUG.ld new file mode 100644 index 00000000..6f8e270f --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/STM32F091xC_CLR-DEBUG.ld @@ -0,0 +1,76 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + + +/* + * STM32F091xC memory setup. + */ +MEMORY +{ + flash : org = 0x08003000, len = 256k - 12k - 50k /* flash size less the space reserved for nanoBooter and application deployment*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x08033000, len = 50k /* space reserved for application deployment */ + ramvt : org = 0x20000000, len = 0xC0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x200000C0, len = 32k - 0xC0 /* remaining RAM is free for use */ + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/STM32F091xC_CLR.ld b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/STM32F091xC_CLR.ld new file mode 100644 index 00000000..d622e155 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/STM32F091xC_CLR.ld @@ -0,0 +1,76 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + + +/* + * STM32F091xC memory setup. + */ +MEMORY +{ + flash : org = 0x08002800, len = 256k - 10k - 88k /* flash size less the space reserved for nanoBooter and application deployment*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x0802A000, len = 88k /* space reserved for application deployment */ + ramvt : org = 0x20000000, len = 0xC0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x200000C0, len = 32k - 0xC0 /* remaining RAM is free for use */ + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/chconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/chconf.h new file mode 100644 index 00000000..83434f36 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/chconf.h @@ -0,0 +1,704 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 1000 // this is 1 millisecond +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM FALSE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY FALSE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/halconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/halconf.h new file mode 100644 index 00000000..a99b33ac --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/halconf.h @@ -0,0 +1,524 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +// #define HAL_USE_ADC FALSE +// #endif + +/** + * @brief Enables the CAN subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +// #define HAL_USE_CAN FALSE +// #endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +// /** +// * @brief Enables the DAC subsystem. +// */ +// #if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +// #define HAL_USE_DAC FALSE +// #endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +// this option is set at target_platform.h (from config file) +//#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +//#define HAL_USE_I2C TRUE +//#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +// #define HAL_USE_MAC TRUE +// #endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +// #define HAL_USE_PWM FALSE +// #endif + +/** + * @brief Enables the RTC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +// #define HAL_USE_RTC TRUE +// #endif + +/** + * @brief Enables the SDC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +// #define HAL_USE_SDC FALSE +// #endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + + +/** + * @brief Enables the SPI subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +// #define HAL_USE_SPI FALSE +// #endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +// #define HAL_USE_UART FALSE +// #endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +// #define HAL_USE_WDG FALSE +// #endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS TRUE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 64 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/halconf_nf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/halconf_nf.h new file mode 100644 index 00000000..e35b7bec --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/halconf_nf.h @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +#if !defined(HAL_USE_STM32_RNG) +#define HAL_USE_STM32_RNG FALSE +#endif + +#endif // _HALCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/main.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/main.c new file mode 100644 index 00000000..1e7ec5b3 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/main.c @@ -0,0 +1,98 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/////////////////////////////////////////////////////////////////////////////////////////// +// RAM vector table declaration (valid for GCC only) +__IO uint32_t vectorTable[48] __attribute__((section(".RAMVectorTable"))); + +#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03) + +/////////////////////////////////////////////////////////////////////////////////////////// + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 512, "ReceiverThread"); +// declare CLRStartup thread here +osThreadDef(CLRStartupThread, osPriorityNormal, 4096, "CLRStartupThread"); + +// configuration for debugger serial port +// dev notes: +// conservative baud rate value as 921600 has a high error percentage on baud rate clocking +// OVER8 bit on CR1 to further decrease baud rate clocking error +static const SerialConfig uartConfig = +{ + 460800, + USART_CR1_OVER8, + USART_CR2_STOP1_BITS, + 0 +}; + +// Application entry point. +int main(void) { + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init SWO as soon as possible to make it available to output ASAP + #if (SWO_OUTPUT == TRUE) + SwoInit(); + #endif + + // relocate the vector table to RAM + // Copy the vector table from the Flash (mapped at the base of the application + // load address) to the base address of the SRAM at 0x20000000. + for(int i = 0; i < 48; i++) + { + vectorTable[i] = *(__IO uint32_t*)((uint32_t)&__nanoImage_start__ + (i<<2)); + } + + // set CFGR1 register MEM_MODE bits value as "memory remap to SRAM" + SYSCFG->CFGR1 |= SYSCFG_MemoryRemap_SRAM; + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // start watchdog + Watchdog_Init(); + + // starts the serial driver + sdStart(&SERIAL_DRIVER, &uartConfig); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // CLR settings to launch CLR thread + CLR_SETTINGS clrSettings; + (void)memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.EnterDebuggerLoopAfterExit = true; + + // create the CLR Startup thread + osThreadCreate(osThread(CLRStartupThread), &clrSettings); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + while (true) { + osDelay(100); + } +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/mcuconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/mcuconf.h new file mode 100644 index 00000000..d023f997 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/mcuconf.h @@ -0,0 +1,253 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F0xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F0xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_HSI_ENABLED TRUE +#define STM32_HSI14_ENABLED TRUE +#define STM32_HSI48_ENABLED FALSE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PREDIV_VALUE 2 +#define STM32_PLLMUL_VALUE 12 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE STM32_PPRE_DIV1 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_MCOPRE STM32_MCOPRE_DIV1 +#define STM32_PLLNODIV STM32_PLLNODIV_DIV2 +#define STM32_CECSW STM32_CECSW_HSI +#define STM32_I2C1SW STM32_I2C1SW_HSI +#define STM32_USART1SW STM32_USART1SW_PCLK +#define STM32_RTCSEL STM32_RTCSEL_LSI + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_1_IRQ_PRIORITY 3 +#define STM32_IRQ_EXTI2_3_IRQ_PRIORITY 3 +#define STM32_IRQ_EXTI4_15_IRQ_PRIORITY 3 +#define STM32_IRQ_EXTI16_IRQ_PRIORITY 3 +#define STM32_IRQ_EXTI17_20_IRQ_PRIORITY 3 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2 +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 3 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 TRUE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 2 +#define STM32_GPT_TIM2_IRQ_PRIORITY 2 +#define STM32_GPT_TIM3_IRQ_PRIORITY 2 +#define STM32_GPT_TIM6_IRQ_PRIORITY 2 +#define STM32_GPT_TIM7_IRQ_PRIORITY 2 +#define STM32_GPT_TIM14_IRQ_PRIORITY 2 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_IRQ_PRIORITY 3 +#define STM32_I2C_I2C2_IRQ_PRIORITY 3 +#define STM32_I2C_USE_DMA TRUE +#define STM32_I2C_I2C1_DMA_PRIORITY 1 +#define STM32_I2C_I2C2_DMA_PRIORITY 1 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI1 TRUE +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \ + STM32_I2S_MODE_RX) +#define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \ + STM32_I2S_MODE_RX) +#define STM32_I2S_SPI1_IRQ_PRIORITY 2 +#define STM32_I2S_SPI2_IRQ_PRIORITY 2 +#define STM32_I2S_SPI1_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 3 +#define STM32_ICU_TIM2_IRQ_PRIORITY 3 +#define STM32_ICU_TIM3_IRQ_PRIORITY 3 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_TIM1_IRQ_PRIORITY 3 +#define STM32_PWM_TIM2_IRQ_PRIORITY 3 +#define STM32_PWM_TIM3_IRQ_PRIORITY 3 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE +#define STM32_SERIAL_USART1_PRIORITY 3 +#define STM32_SERIAL_USART2_PRIORITY 3 +#define STM32_SERIAL_USART3_8_PRIORITY 3 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 2 +#define STM32_SPI_SPI2_IRQ_PRIORITY 2 +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 2 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USE_UART7 FALSE +#define STM32_UART_USE_UART8 TRUE +#define STM32_UART_USART1_IRQ_PRIORITY 3 +#define STM32_UART_USART2_IRQ_PRIORITY 3 +#define STM32_UART_USART3_8_IRQ_PRIORITY 3 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_UART7_DMA_PRIORITY 0 +#define STM32_UART_UART8_DMA_PRIORITY 0 +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_USB1 FALSE +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_LP_IRQ_PRIORITY 3 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG TRUE + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/mcuconf_nf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/mcuconf_nf.h new file mode 100644 index 00000000..574b9636 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/mcuconf_nf.h @@ -0,0 +1,10 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/nanoHAL.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/nanoHAL.cpp new file mode 100644 index 00000000..076a50fc --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/nanoHAL.cpp @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +void HAL_EnterBooterMode() +{ +} + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/target_board.h.in b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/target_board.h.in new file mode 100644 index 00000000..b980bc05 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/nanoCLR/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOCLR_H_ */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_BlockStorage.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_BlockStorage.c new file mode 100644 index 00000000..9e7c7f55 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_BlockStorage.c @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice STM32Flash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &STM32Flash_BlockStorageInterface, &Device_BlockStorageConfig, false); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_BlockStorage.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_BlockStorage.h new file mode 100644 index 00000000..aa50b1b7 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_common.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_common.c new file mode 100644 index 00000000..c633da5b --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_common.c @@ -0,0 +1,24 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include "target_common.h" + +HAL_SYSTEM_CONFIG HalSystemConfig = +{ + { true }, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, //ConvertCOM_DebugHandle(1), + 0, //ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + { RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size }, + { FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size } +}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_common.h.in b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_common.h.in new file mode 100644 index 00000000..e629d90b --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_common.h.in @@ -0,0 +1,48 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x20000000) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x00008000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x08000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00040000) + +///////////////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////// +// set Wire Protocol packet size +// valid sizes are 1024, 512, 256, 128 +// check Monitor_Ping_Source_Flags enum +#define WP_PACKET_SIZE 256U +////////////////////////////////////////////// + +////////////////////////////////////////////// +#define TARGETNAMESTRING "@CHIBIOS_BOARD@" +#define PLATFORMNAMESTRING "STM32F0" +////////////////////////////////////////////// + +///////////////////////////////////// +//#define EVENTS_HEART_BEAT palToggleLine(GPIOA_LED_GREEN) +///////////////////////////////////// + +#endif /* _TARGET_COMMON_H_ */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_system_devices_dac_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_system_devices_dac_config.cpp new file mode 100644 index 00000000..049422f7 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_system_devices_dac_config.cpp @@ -0,0 +1,14 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_DAC_PORT_PIN_CHANNEL DacPortPinConfig[] = { + + // DAC1, channel 1, GPIO port A, pin 4 + {1, 1, GPIOA, 4}, +}; + +const int DacChannelCount = ARRAYSIZE(DacPortPinConfig); diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_windows_devices_i2c_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_windows_devices_i2c_config.cpp new file mode 100644 index 00000000..2618ec3e --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_windows_devices_i2c_config.cpp @@ -0,0 +1,18 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for SCL pin is: GPIOB +// port for SDA pin is: GPIOB +// SCL pin: is GPIOB_8 +// SDA pin: is GPIOB_9 +// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, GPIOB, GPIOB, 8, 9, 4) diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_windows_devices_serialcommunication_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_windows_devices_serialcommunication_config.cpp new file mode 100644 index 00000000..673d3b7e --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_windows_devices_serialcommunication_config.cpp @@ -0,0 +1,37 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_windows_devices_serialcommunication_config.h" +#include + +//////////// +// USART8 // +//////////// + +// pin configuration for USART8 +// port for TX pin is: GPIOC +// port for RX pin is: GPIOC +// TX pin: is GPIOC_2 +// RX pin: is GPIOC_3 +// GPIO alternate pin function is 1 (see "Table 16. Alternate functions selected through GPIOC_AFR registers for port C" in STM32F091RC datasheet) +UART_CONFIG_PINS(8, GPIOC, GPIOC, 2, 3, 2) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart8_TxBuffer[UART8_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart8_RxBuffer[UART8_RX_SIZE]; + +// initialization for UART8 +UART_INIT(8, UART8_TX_SIZE, UART8_RX_SIZE) + +// un-initialization for UART8 +UART_UNINIT(8) diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_windows_devices_serialcommunication_config.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_windows_devices_serialcommunication_config.h new file mode 100644 index 00000000..6def329e --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_windows_devices_serialcommunication_config.h @@ -0,0 +1,17 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +//////////// +// USART8 // +//////////// + +// enable USART8 +#define NF_SERIAL_COMM_STM32_UART_USE_UART8 TRUE + +// buffers size +// tx buffer size: 256 bytes +#define UART8_TX_SIZE 256 +// rx buffer size: 256 bytes +#define UART8_RX_SIZE 256 diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_windows_devices_spi_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_windows_devices_spi_config.cpp new file mode 100644 index 00000000..76238dbe --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_NUCLEO64_F091RC/target_windows_devices_spi_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/CMakeLists.txt new file mode 100644 index 00000000..77249ac0 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/CMakeLists.txt @@ -0,0 +1,213 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +cmake_minimum_required(VERSION 3.0) +ENABLE_LANGUAGE(ASM) + +# add header files with common OS definitions and board definitions specific for each image +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/target_common.h" @ONLY) + +set(NANOBOOTER_PROJECT_NAME "nanoBooter") +set(NANOCLR_PROJECT_NAME "nanoCLR") + +find_package(BuildUtils REQUIRED) +find_package(CHIBIOS REQUIRED) +find_package(ChibiOSnfOverlay REQUIRED) +find_package(WireProtocol REQUIRED) + +# packages for nanoFramework libraries +####################################### +# mandatory +find_package(NF_CoreCLR REQUIRED) + +####################################### +# optional + +# ChibiOS contrib repo +if(CHIBIOS_CONTRIB_REQUIRED) + find_package(ChibiOS-Contrib REQUIRED) +endif() + +# nF feature: debugger +if(NF_FEATURE_DEBUGGER) + find_package(NF_Debugger REQUIRED) + find_package(NF_Diagnostics REQUIRED) +endif() + +# nF feature: networking +if(USE_NETWORKING_OPTION) + find_package(CHIBIOS_LWIP REQUIRED) +endif() + +# nF feature: filesystem +if(USE_FILESYSTEM_OPTION) + find_package(CHIBIOS_FATFS REQUIRED) +endif() + +####################################### + +add_subdirectory("common") +add_subdirectory("nanoBooter") +add_subdirectory("nanoCLR") + +####################### +# nanoBooter executable + +add_executable( + # executables for project, project sources + ${NANOBOOTER_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + "${CMAKE_CURRENT_SOURCE_DIR}/target_BlockStorage.c" + + # need to add configuration manager to allow get/store configuration blocks + "${PROJECT_SOURCE_DIR}/src/HAL/nanoHAL_ConfigurationManager_stubs.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOBOOTER_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOBOOTER_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOBOOTER_SOURCES} + + ${CHIBIOS_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} +) + +####################### +# nanoCLR executable + +add_executable( + # executables for project, project sources + ${NANOCLR_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + # the next one is required is the target implements and it's using external memory + "${CMAKE_CURRENT_SOURCE_DIR}/target_external_memory.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOCLR_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOCLR_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOCLR_SOURCES} + + ${CHIBIOS_SOURCES} + ${CHIBIOS_CONTRIB_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} + + # sources for nanoFramework libraries + ${NF_CoreCLR_SOURCES} + ${NF_Debugger_SOURCES} + ${NF_Diagnostics_SOURCES} + + # sources for ChibiOS FatFS + ${CHIBIOS_FATFS_SOURCES} + + # sources for nanoFramework APIs + ${TARGET_NANO_APIS_SOURCES} +) + +# add dependency from ChibiOS (this is required to make sure the ChibiOS repo is downloaded before the build starts) +add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf ChibiOS) +add_dependencies(${NANOCLR_PROJECT_NAME}.elf ChibiOS) + +# include common directories +include_directories( + ${CMAKE_CURRENT_BINARY_DIR} + ${CMAKE_CURRENT_SOURCE_DIR} + ${CMAKE_CURRENT_SOURCE_DIR}/common + ${PROJECT_SOURCE_DIR}/src/CLR/Core + ${PROJECT_SOURCE_DIR}/src/CLR/Include + ${PROJECT_SOURCE_DIR}/src/HAL/Include + ${PROJECT_SOURCE_DIR}/src/PAL/Include + + ${WireProtocol_INCLUDE_DIRS} + ${CHIBIOS_INCLUDE_DIRS} + ${ChibiOSnfOverlay_INCLUDE_DIRS} + ${CHIBIOS_CONTRIB_INCLUDE_DIRS} + + ${TARGET_CMSIS_COMMON_INCLUDE_DIRS} + ${TARGET_CHIBIOS_COMMON_INCLUDE_DIRS} +) + +# include directories for nanoBooter +target_include_directories(${NANOBOOTER_PROJECT_NAME}.elf PUBLIC + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter" + ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter + + ${TARGET_CMSIS_NANOBOOTER_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOBOOTER_INCLUDE_DIRS} +) + +# include directories for nanoCLR +target_include_directories(${NANOCLR_PROJECT_NAME}.elf PUBLIC + ${CMAKE_CURRENT_BINARY_DIR}/nanoCLR + ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR + + ${TARGET_CMSIS_NANOCLR_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOCLR_INCLUDE_DIRS} + + # directories for nanoFramework libraries + ${NF_CoreCLR_INCLUDE_DIRS} + ${NF_Debugger_INCLUDE_DIRS} + ${NF_Diagnostics_INCLUDE_DIRS} + + # includes for nanoFramework APIs + ${TARGET_NANO_APIS_INCLUDES} + + # includes for ChibiOS FatFS + ${CHIBIOS_FATFS_INCLUDE_DIRS} + + # includes for ChibiOS LwIP + ${CHIBIOS_LWIP_INCLUDE_DIRS} +) + +# set compiler options +nf_set_compiler_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_options(${NANOCLR_PROJECT_NAME}.elf) + +# set compiler definitions +nf_set_compiler_definitions(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_definitions(${NANOCLR_PROJECT_NAME}.elf) + +# set linker files +if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F429xI_booter-DEBUG.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/STM32F429xI_CLR-DEBUG.ld) +else() + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F429xI_booter.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/STM32F429xI_CLR.ld) +endif() + +# set linker options +nf_set_linker_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_linker_options(${NANOCLR_PROJECT_NAME}.elf) + +# add other linker flags +########################################################### +# the sizes of CRT heap and ChibiOS stacks are defined here +############################################################################ +# CRT heap is assigned to RAM4 region @ CCM SRAM so we are OK to use it all +############################################################################ +set_property(TARGET ${NANOBOOTER_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x400,--defsym=__crt_heap_size__=0x10000") +set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x10000") + +# generate output files +nf_generate_build_output_files(${NANOBOOTER_PROJECT_NAME}.elf) +nf_generate_build_output_files(${NANOCLR_PROJECT_NAME}.elf) diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/README.md b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/README.md new file mode 100644 index 00000000..4ddda46f --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/README.md @@ -0,0 +1,34 @@ +## Configuration of Chibios, HAL and MCU ## + +For a successful build the following changes are required: + +In _halconf.g_ (in both nanoBooter and nanoCLR folders), when compared with a default file: +- HAL_USE_SERIAL to TRUE +- HAL_USE_SERIAL_USB to TRUE +- HAL_USE_USB to TRUE +- SERIAL_DEFAULT_BITRATE to 921600 + +In _mcuconf.h_ (in both nanoBooter and nanoCLR folders), when compared with a default file: +- STM32_SERIAL_USE_USART2 to TRUE +- STM32_USB_USE_OTG1 to TRUE + +In _chconf.h_ (_**only**_ for nanoCLR folder), when compared with a default file: +- set the CORTEX_VTOR_INIT with the appropriate address of the vector table for nanoCLR + + +## Definitions for each image ## + +Any defines specific to an image (nanoBooter or nanoCLR) that are to be made available throughout the code should be added to the _target_board.h.in_. There is one in [nanoBooter](nanoBooter/target_board.h.in) and another in [nanoCLR](nanoCLR/target_board.h.in) directories, allowing different defines for each one. +Defines that are common to a target board should be added to the [_target_common.h.in_](target_common.h.in). +The content of these files is parsed by CMake. It can include CMake variables. Check the documentation of CMake config files [here](https://cmake.org/cmake/help/v3.7/command/configure_file.html?highlight=configure_file). + + + + +**NOTE: this configuration was successfully tested in a ST_STM32F429I_DISCOVERY board using the Serial over USB connection on USB port 1 that creates a virtual COM port.** + + +## Floating point + +The current build is set to add support for single-precision floating point. +Meaning that `System.Math` API supports only the `float` overloads. The `double` ones will throw a `NotImplementedException`. diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/common/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/common/CMakeLists.txt new file mode 100644 index 00000000..aa7f1d54 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/common/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/usbcfg.c") +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c") + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/common/Device_BlockStorage-DEBUG.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 00000000..66a8d940 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,142 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 16kB blocks +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 1 }, // 0x08000000 nanoBooter + { BlockRange_BLOCKTYPE_CODE , 2, 3 } // 0x08008000 nanoCLR +}; + +// 64kB blocks +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 0x08010000 nanoCLR +}; + +// 128kB blocks +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 3 }, // 0x08020000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 4, 6 }, // 0x080A0000 deployment +}; + +// 16kB blocks +const BlockRange BlockRange4[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 3 } // 0x08100000 deployment +}; + +// 64kB blocks +const BlockRange BlockRange5[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 0 } // 0x08110000 deployment +}; + +// 128kB blocks +const BlockRange BlockRange6[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 6 } // 0x08120000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08010000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 7, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + + { + (0), // no attributes for this region + 0x08100000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange4), + BlockRange4, + }, + + { + (0), // no attributes for this region + 0x08110000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange5), + BlockRange5, + }, + + { + (0), // no attributes for this region + 0x08120000, // start address for block region + 7, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange6), + BlockRange6, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), // STM32 flash memory is XIP + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/common/Device_BlockStorage.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/common/Device_BlockStorage.c new file mode 100644 index 00000000..7e34313e --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/common/Device_BlockStorage.c @@ -0,0 +1,142 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 16kB blocks +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 0 }, // 0x08000000 nanoBooter + { BlockRange_BLOCKTYPE_CODE , 1, 3 } // 0x08004000 nanoCLR +}; + +// 64kB blocks +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 0x08010000 nanoCLR +}; + +// 128kB blocks +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 }, // 0x08020000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 1, 6 }, // 0x08040000 deployment +}; + +// 16kB blocks +const BlockRange BlockRange4[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 3 } // 0x08100000 deployment +}; + +// 64kB blocks +const BlockRange BlockRange5[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 0 } // 0x08110000 deployment +}; + +// 128kB blocks +const BlockRange BlockRange6[] = +{ + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 6 } // 0x08120000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08010000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 7, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + + { + (0), // no attributes for this region + 0x08100000, // start address for block region + 4, // total number of blocks in this region + 0x4000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange4), + BlockRange4, + }, + + { + (0), // no attributes for this region + 0x08110000, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange5), + BlockRange5, + }, + + { + (0), // no attributes for this region + 0x08120000, // start address for block region + 7, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange6), + BlockRange6, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), // STM32 flash memory is XIP + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/common/usbcfg.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/common/usbcfg.c new file mode 100644 index 00000000..217a411e --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/common/usbcfg.c @@ -0,0 +1,454 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "hal.h" + +/* Virtual serial port over USB.*/ +SerialUSBDriver SDU1; + +/* + * Endpoints to be used for USBD2. + */ +#define USBD2_DATA_REQUEST_EP 1 +#define USBD2_DATA_AVAILABLE_EP 1 +#define USBD2_INTERRUPT_REQUEST_EP 2 + +// address for device unique ID +// valid for STM32F4 series +#define DEVICE_ID1 (0x1FFF7A10) +#define DEVICE_ID2 (0x1FFF7A14) +#define DEVICE_ID3 (0x1FFF7A18) + +// // size of string serial is 36 = 2 + 5x2 + 26 from silicon unique ID precedeed of string "NANO_" and descriptor codes +// #define USB_SIZ_STRING_SERIAL 36 + +//////////////////////////////////////////////// +// vendor +#define USB_STRING_VENDOR L"STMicroelectronics" +//////////////////////////////////////////////// + +// structure for USB Vendor with Unicode string +typedef struct usb_string_vendor +{ + uint8_t bLength; + uint8_t bDescriptorType; + wchar_t bPropertyData[sizeof(USB_STRING_VENDOR)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec) + +}usb_string_vendor; + + +///////////////////////////////////////////////////////////////////////// +// device description +#define USB_STRING_DEVICE_DESCRIPTION L"nanoFramework Virtual COM Port" +///////////////////////////////////////////////////////////////////////// + +// structure for USB device descriptor with Unicode string +typedef struct usb_string_device_description +{ + uint8_t bLength; + uint8_t bDescriptorType; + wchar_t bPropertyData[sizeof(USB_STRING_DEVICE_DESCRIPTION)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec) + +}usb_string_device_description; + + +///////////////////////////////////////////////////////////////////////// +// device serial number +// this will produce a string with NANO_ prefix followed +// by the hexadecimal representation of the silicon unique ID of the CPU +#define USB_STRING_SERIAL_NUMBER L"NANO_xxxxxxxxxxx" +///////////////////////////////////////////////////////////////////////// +#define INDEX_OF_WCHAR_FOR_UNIQUE_ID 5 + +// structure for USB serial number descriptor with Unicode string +typedef struct usb_string_serial_number +{ + uint8_t bLength; + uint8_t bDescriptorType; + wchar_t bPropertyData[sizeof(USB_STRING_SERIAL_NUMBER)/sizeof(wchar_t) - 1]; // that's the 'w_char' string length less 1 because we are not storing the terminator (according to the USB spec) + +}usb_string_serial_number; + + +/* + * USB Device Descriptor. + */ +static const uint8_t vcom_device_descriptor_data[18] = { + USB_DESC_DEVICE (0x0200, /* bcdUSB (2.0). */ + 0x02, /* bDeviceClass (CDC). */ + 0x00, /* bDeviceSubClass. */ + 0x00, /* bDeviceProtocol. */ + 0x40, /* bMaxPacketSize. */ + 0x0483, /* idVendor (ST). */ + 0x5740, /* idProduct. */ + 0x0200, /* bcdDevice. */ + 1, /* iManufacturer. */ + 2, /* iProduct. */ + 3, /* iSerialNumber. */ + 1) /* bNumConfigurations. */ +}; + +/* + * Device Descriptor wrapper. + */ +static const USBDescriptor vcom_device_descriptor = { + sizeof vcom_device_descriptor_data, + vcom_device_descriptor_data +}; + +/* Configuration Descriptor tree for a CDC.*/ +static const uint8_t vcom_configuration_descriptor_data[67] = { + /* Configuration Descriptor.*/ + USB_DESC_CONFIGURATION(67, /* wTotalLength. */ + 0x02, /* bNumInterfaces. */ + 0x01, /* bConfigurationValue. */ + 0, /* iConfiguration. */ + 0xC0, /* bmAttributes (self powered). */ + 50), /* bMaxPower (100mA). */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x01, /* bNumEndpoints. */ + 0x02, /* bInterfaceClass (Communications + Interface Class, CDC section + 4.2). */ + 0x02, /* bInterfaceSubClass (Abstract + Control Model, CDC section 4.3). */ + 0x01, /* bInterfaceProtocol (AT commands, + CDC section 4.4). */ + 0), /* iInterface. */ + /* Header Functional Descriptor (CDC section 5.2.3).*/ + USB_DESC_BYTE (5), /* bLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header + Functional Descriptor. */ + USB_DESC_BCD (0x0110), /* bcdCDC. */ + /* Call Management Functional Descriptor. */ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */ + USB_DESC_BYTE (0x01), /* bDataInterface. */ + /* ACM Functional Descriptor.*/ + USB_DESC_BYTE (4), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract + Control Management Descriptor). */ + USB_DESC_BYTE (0x02), /* bmCapabilities. */ + /* Union Functional Descriptor.*/ + USB_DESC_BYTE (5), /* bFunctionLength. */ + USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */ + USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union + Functional Descriptor). */ + USB_DESC_BYTE (0x00), /* bMasterInterface (Communication + Class Interface). */ + USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class + Interface). */ + /* Endpoint 2 Descriptor.*/ + USB_DESC_ENDPOINT (USBD2_INTERRUPT_REQUEST_EP|0x80, + 0x03, /* bmAttributes (Interrupt). */ + 0x0008, /* wMaxPacketSize. */ + 0xFF), /* bInterval. */ + /* Interface Descriptor.*/ + USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */ + 0x00, /* bAlternateSetting. */ + 0x02, /* bNumEndpoints. */ + 0x0A, /* bInterfaceClass (Data Class + Interface, CDC section 4.5). */ + 0x00, /* bInterfaceSubClass (CDC section + 4.6). */ + 0x00, /* bInterfaceProtocol (CDC section + 4.7). */ + 0x00), /* iInterface. */ + /* Endpoint 3 Descriptor.*/ + USB_DESC_ENDPOINT (USBD2_DATA_AVAILABLE_EP, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00), /* bInterval. */ + /* Endpoint 1 Descriptor.*/ + USB_DESC_ENDPOINT (USBD2_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/ + 0x02, /* bmAttributes (Bulk). */ + 0x0040, /* wMaxPacketSize. */ + 0x00) /* bInterval. */ +}; + +/* + * Configuration Descriptor wrapper. + */ +static const USBDescriptor vcom_configuration_descriptor = { + sizeof vcom_configuration_descriptor_data, + vcom_configuration_descriptor_data +}; + +/* + * U.S. English language identifier. + */ +static const uint8_t vcom_string0[] = { + USB_DESC_BYTE(4), /* bLength. */ + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */ + USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */ +}; + + +// Vendor string +static const usb_string_vendor usb_vendor = { + sizeof(usb_vendor), + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), + USB_STRING_VENDOR +}; + + +// Device Description string +static const usb_string_device_description usb_device_description = { + sizeof(usb_device_description), + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), + USB_STRING_DEVICE_DESCRIPTION +}; + + +// Serial Number string. +static usb_string_serial_number usb_serial_number = { + sizeof(usb_serial_number), + USB_DESC_BYTE(USB_DESCRIPTOR_STRING), + USB_STRING_SERIAL_NUMBER +}; + + +/* + * Strings wrappers array. + */ +static const USBDescriptor vcom_strings[] = { + {sizeof vcom_string0, vcom_string0}, + {sizeof usb_vendor, (uint8_t*)(&usb_vendor)}, + {sizeof usb_device_description, (uint8_t*)(&usb_device_description)}, + {sizeof usb_serial_number, (uint8_t*)(&usb_serial_number)}, +}; + + +// Convert Hex 32Bits value into char +// value: value to convert +// pbuf: pointer to the buffer +// len: buffer length +void IntToUnicode(uint32_t value , uint8_t *pbuf, uint8_t len) +{ + uint8_t idx = 0; + + for( idx = 0; idx < len; idx ++) + { + if( ((value >> 28)) < 0xA ) + { + pbuf[ 2* idx] = (value >> 28) + '0'; + } + else + { + pbuf[2* idx] = (value >> 28) + 'A' - 10; + } + + value = value << 4; + + pbuf[ 2* idx + 1] = 0; + } +} + +// Create the serial number string descriptor +void Get_SerialNum(uint8_t* pbuf) +{ + uint32_t deviceserial0, deviceserial1, deviceserial2; + + deviceserial0 = *(uint32_t*)DEVICE_ID1; + deviceserial1 = *(uint32_t*)DEVICE_ID2; + deviceserial2 = *(uint32_t*)DEVICE_ID3; + + deviceserial0 += deviceserial2; + + if (deviceserial0 != 0) + { + IntToUnicode(deviceserial0, pbuf, 8); + pbuf += 16; + IntToUnicode(deviceserial1, pbuf, 4); + } +} + +/* + * Handles the GET_DESCRIPTOR callback. All required descriptors must be + * handled here. + */ +static const USBDescriptor *get_descriptor(USBDriver *usbp, + uint8_t dtype, + uint8_t dindex, + uint16_t lang) { + + (void)usbp; + (void)lang; + + switch (dtype) { + case USB_DESCRIPTOR_DEVICE: + return &vcom_device_descriptor; + case USB_DESCRIPTOR_CONFIGURATION: + return &vcom_configuration_descriptor; + case USB_DESCRIPTOR_STRING: + if (dindex < 4) + { + if(dindex == 3) + { + // request is for serial number + // get it from the silicon unique ID + Get_SerialNum((uint8_t*)&usb_serial_number.bPropertyData[INDEX_OF_WCHAR_FOR_UNIQUE_ID]); + } + + return &vcom_strings[dindex]; + } + } + return NULL; +} + +/** + * @brief IN EP1 state. + */ +static USBInEndpointState ep1instate; + +/** + * @brief OUT EP1 state. + */ +static USBOutEndpointState ep1outstate; + +/** + * @brief EP1 initialization structure (both IN and OUT). + */ +static const USBEndpointConfig ep1config = { + USB_EP_MODE_TYPE_BULK, + NULL, + sduDataTransmitted, + sduDataReceived, + 0x0040, + 0x0040, + &ep1instate, + &ep1outstate, + 2, + NULL +}; + +/** + * @brief IN EP2 state. + */ +static USBInEndpointState ep2instate; + +/** + * @brief EP2 initialization structure (IN only). + */ +static const USBEndpointConfig ep2config = { + USB_EP_MODE_TYPE_INTR, + NULL, + sduInterruptTransmitted, + NULL, + 0x0010, + 0x0000, + &ep2instate, + NULL, + 1, + NULL +}; + +/* + * Handles the USB driver global events. + */ +static void usb_event(USBDriver *usbp, usbevent_t event) { + extern SerialUSBDriver SDU1; + + switch (event) { + case USB_EVENT_ADDRESS: + return; + case USB_EVENT_CONFIGURED: + chSysLockFromISR(); + + if (usbp->state == USB_ACTIVE) { + /* Enables the endpoints specified into the configuration. + Note, this callback is invoked from an ISR so I-Class functions + must be used.*/ + usbInitEndpointI(usbp, USBD2_DATA_REQUEST_EP, &ep1config); + usbInitEndpointI(usbp, USBD2_INTERRUPT_REQUEST_EP, &ep2config); + + /* Resetting the state of the CDC subsystem.*/ + sduConfigureHookI(&SDU1); + } + else if (usbp->state == USB_SELECTED) { + usbDisableEndpointsI(usbp); + } + + chSysUnlockFromISR(); + return; + case USB_EVENT_RESET: + /* Falls into.*/ + case USB_EVENT_UNCONFIGURED: + /* Falls into.*/ + case USB_EVENT_SUSPEND: + chSysLockFromISR(); + + /* Disconnection event on suspend.*/ + sduSuspendHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_WAKEUP: + chSysLockFromISR(); + + /* Disconnection event on suspend.*/ + sduWakeupHookI(&SDU1); + + chSysUnlockFromISR(); + return; + case USB_EVENT_STALLED: + return; + } + return; +} + +/* + * Handling messages not implemented in the default handler nor in the + * SerialUSB handler. + */ +static bool requests_hook(USBDriver *usbp) { + + if (((usbp->setup[0] & USB_RTYPE_RECIPIENT_MASK) == USB_RTYPE_RECIPIENT_INTERFACE) && + (usbp->setup[1] == USB_REQ_SET_INTERFACE)) { + usbSetupTransfer(usbp, NULL, 0, NULL); + return true; + } + return sduRequestsHook(usbp); +} + +/* + * Handles the USB driver global events. + */ +static void sof_handler(USBDriver *usbp) { + + (void)usbp; + + osalSysLockFromISR(); + sduSOFHookI(&SDU1); + osalSysUnlockFromISR(); +} + +/* + * USB driver configuration. + */ +const USBConfig usbcfg = { + usb_event, + get_descriptor, + requests_hook, + sof_handler +}; + +/* + * Serial over USB driver configuration. + */ +const SerialUSBConfig serusbcfg = { + &USBD2, + USBD2_DATA_REQUEST_EP, + USBD2_DATA_AVAILABLE_EP, + USBD2_INTERRUPT_REQUEST_EP +}; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/common/usbcfg.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/common/usbcfg.h new file mode 100644 index 00000000..167e1df8 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/common/usbcfg.h @@ -0,0 +1,17 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef USBCFG_H +#define USBCFG_H + +extern const USBConfig usbcfg; +extern SerialUSBConfig serusbcfg; +extern SerialUSBDriver SDU1; + +#endif /* USBCFG_H */ + +/** @} */ + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/ffconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/ffconf.h new file mode 100644 index 00000000..7ffb3957 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/ffconf.h @@ -0,0 +1,272 @@ +/* CHIBIOS FIX */ +#include "ch.h" + +/*---------------------------------------------------------------------------/ +/ FatFs - Configuration file +/---------------------------------------------------------------------------*/ + +#define FFCONF_DEF 87030 /* Revision ID */ + +/*---------------------------------------------------------------------------/ +/ Function Configurations +/---------------------------------------------------------------------------*/ + +#define FF_FS_READONLY 0 +/* This option switches read-only configuration. (0:Read/Write or 1:Read-only) +/ Read-only configuration removes writing API functions, f_write(), f_sync(), +/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree() +/ and optional writing functions as well. */ + + +#define FF_FS_MINIMIZE 0 +/* This option defines minimization level to remove some basic API functions. +/ +/ 0: All basic functions are enabled. +/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename() +/ are removed. +/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1. +/ 3: f_lseek() function is removed in addition to 2. */ + + +#define FF_USE_STRFUNC 0 +/* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf(). +/ +/ 0: Disable string functions. +/ 1: Enable without LF-CRLF conversion. +/ 2: Enable with LF-CRLF conversion. */ + + +#define FF_USE_FIND 0 +/* This option switches filtered directory read functions, f_findfirst() and +/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */ + + +#define FF_USE_MKFS 0 +/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */ + + +#define FF_USE_FASTSEEK 0 +/* This option switches fast seek function. (0:Disable or 1:Enable) */ + + +#define FF_USE_EXPAND 0 +/* This option switches f_expand function. (0:Disable or 1:Enable) */ + + +#define FF_USE_CHMOD 0 +/* This option switches attribute manipulation functions, f_chmod() and f_utime(). +/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */ + + +#define FF_USE_LABEL 0 +/* This option switches volume label functions, f_getlabel() and f_setlabel(). +/ (0:Disable or 1:Enable) */ + + +#define FF_USE_FORWARD 0 +/* This option switches f_forward() function. (0:Disable or 1:Enable) */ + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/---------------------------------------------------------------------------*/ + +#define FF_CODE_PAGE 850 +/* This option specifies the OEM code page to be used on the target system. +/ Incorrect code page setting can cause a file open failure. +/ +/ 437 - U.S. +/ 720 - Arabic +/ 737 - Greek +/ 771 - KBL +/ 775 - Baltic +/ 850 - Latin 1 +/ 852 - Latin 2 +/ 855 - Cyrillic +/ 857 - Turkish +/ 860 - Portuguese +/ 861 - Icelandic +/ 862 - Hebrew +/ 863 - Canadian French +/ 864 - Arabic +/ 865 - Nordic +/ 866 - Russian +/ 869 - Greek 2 +/ 932 - Japanese (DBCS) +/ 936 - Simplified Chinese (DBCS) +/ 949 - Korean (DBCS) +/ 950 - Traditional Chinese (DBCS) +/ 0 - Include all code pages above and configured by f_setcp() +*/ + + +#define FF_USE_LFN 3 +#define FF_MAX_LFN 255 +/* The FF_USE_LFN switches the support for LFN (long file name). +/ +/ 0: Disable LFN. FF_MAX_LFN has no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ To enable the LFN, Unicode handling functions (option/unicode.c) must be added +/ to the project. The working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and +/ additional 608 bytes at exFAT enabled. FF_MAX_LFN can be in range from 12 to 255. +/ It should be set 255 to support full featured LFN operations. +/ When use stack for the working buffer, take care on stack overflow. When use heap +/ memory for the working buffer, memory management functions, ff_memalloc() and +/ ff_memfree(), must be added to the project. */ + + +#define FF_LFN_UNICODE 0 +/* This option switches character encoding on the API, 0:ANSI/OEM or 1:UTF-16, +/ when LFN is enabled. Also behavior of string I/O functions will be affected by +/ this option. When LFN is not enabled, this option has no effect. +*/ + + +#define FF_STRF_ENCODE 3 +/* When FF_LFN_UNICODE = 1 with LFN enabled, string I/O functions, f_gets(), +/ f_putc(), f_puts and f_printf() convert the character encoding in it. +/ This option selects assumption of character encoding ON THE FILE to be +/ read/written via those functions. +/ +/ 0: ANSI/OEM +/ 1: UTF-16LE +/ 2: UTF-16BE +/ 3: UTF-8 +*/ + + +#define FF_FS_RPATH 0 +/* This option configures support for relative path. +/ +/ 0: Disable relative path and remove related functions. +/ 1: Enable relative path. f_chdir() and f_chdrive() are available. +/ 2: f_getcwd() function is available in addition to 1. +*/ + + +/*---------------------------------------------------------------------------/ +/ Drive/Volume Configurations +/---------------------------------------------------------------------------*/ + +#define FF_VOLUMES 1 +/* Number of volumes (logical drives) to be used. (1-10) */ + + +#define FF_STR_VOLUME_ID 0 +#define FF_VOLUME_STRS "RAM","NAND","CF","SD","SD2","USB","USB2","USB3" +/* FF_STR_VOLUME_ID switches string support for volume ID. +/ When FF_STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive +/ number in the path name. FF_VOLUME_STRS defines the drive ID strings for each +/ logical drives. Number of items must be equal to FF_VOLUMES. Valid characters for +/ the drive ID strings are: A-Z and 0-9. */ + + +#define FF_MULTI_PARTITION 0 +/* This option switches support for multiple volumes on the physical drive. +/ By default (0), each logical drive number is bound to the same physical drive +/ number and only an FAT volume found on the physical drive will be mounted. +/ When this function is enabled (1), each logical drive number can be bound to +/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk() +/ funciton will be available. */ + + +#define FF_MIN_SS 512 +#define FF_MAX_SS 512 +/* This set of options configures the range of sector size to be supported. (512, +/ 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and +/ harddisk. But a larger value may be required for on-board flash memory and some +/ type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured +/ for variable sector size mode and disk_ioctl() function needs to implement +/ GET_SECTOR_SIZE command. */ + + +#define FF_USE_TRIM 0 +/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable) +/ To enable Trim function, also CTRL_TRIM command should be implemented to the +/ disk_ioctl() function. */ + + +#define FF_FS_NOFSINFO 0 +/* If you need to know correct free space on the FAT32 volume, set bit 0 of this +/ option, and f_getfree() function at first time after volume mount will force +/ a full FAT scan. Bit 1 controls the use of last allocated cluster number. +/ +/ bit0=0: Use free cluster count in the FSINFO if available. +/ bit0=1: Do not trust free cluster count in the FSINFO. +/ bit1=0: Use last allocated cluster number in the FSINFO if available. +/ bit1=1: Do not trust last allocated cluster number in the FSINFO. +*/ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/---------------------------------------------------------------------------*/ + +#define FF_FS_TINY 0 +/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny) +/ At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes. +/ Instead of private sector buffer eliminated from the file object, common sector +/ buffer in the filesystem object (FATFS) is used for the file data transfer. */ + + +#define FF_FS_EXFAT 0 +/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable) +/ When enable exFAT, also LFN needs to be enabled. +/ Note that enabling exFAT discards ANSI C (C89) compatibility. */ + + +#define FF_FS_NORTC 1 +#define FF_NORTC_MON 8 +#define FF_NORTC_MDAY 1 +#define FF_NORTC_YEAR 2018 +/* The option FF_FS_NORTC switches timestamp functiton. If the system does not have +/ any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable +/ the timestamp function. All objects modified by FatFs will have a fixed timestamp +/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time. +/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be +/ added to the project to read current time form real-time clock. FF_NORTC_MON, +/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect. +/ These options have no effect at read-only configuration (FF_FS_READONLY = 1). */ + + +#define FF_FS_LOCK 0 +/* The option FF_FS_LOCK switches file lock function to control duplicated file open +/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY +/ is 1. +/ +/ 0: Disable file lock function. To avoid volume corruption, application program +/ should avoid illegal open, remove and rename to the open objects. +/ >0: Enable file lock function. The value defines how many files/sub-directories +/ can be opened simultaneously under file lock control. Note that the file +/ lock control is independent of re-entrancy. */ + + +#define FF_FS_REENTRANT 0 +#define FF_FS_TIMEOUT TIME_MS2I(1000) +#define FF_SYNC_t semaphore_t* +/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs +/ module itself. Note that regardless of this option, file access to different +/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs() +/ and f_fdisk() function, are always not re-entrant. Only file/directory access +/ to the same volume is under control of this function. +/ +/ 0: Disable re-entrancy. FF_FS_TIMEOUT and FF_SYNC_t have no effect. +/ 1: Enable re-entrancy. Also user provided synchronization handlers, +/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj() +/ function, must be added to the project. Samples are available in +/ option/syscall.c. +/ +/ The FF_FS_TIMEOUT defines timeout period in unit of time tick. +/ The FF_SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*, +/ SemaphoreHandle_t and etc. A header file for O/S definitions needs to be +/ included somewhere in the scope of ff.h. */ + +/* #include // O/S definitions */ + + + +/*--- End of configuration options ---*/ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/managed_helpers/README.md b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/managed_helpers/README.md new file mode 100644 index 00000000..87944cda --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/managed_helpers/README.md @@ -0,0 +1,5 @@ +## Managed code helpers + +This folder contains helper classes to make developers life easier when coding for this target board. + +* [Adc](STM32F429I_DISCOVERY.Adc.cs) diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/managed_helpers/STM32F429I_DISCOVERY.Adc.cs b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/managed_helpers/STM32F429I_DISCOVERY.Adc.cs new file mode 100644 index 00000000..78d7cb98 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/managed_helpers/STM32F429I_DISCOVERY.Adc.cs @@ -0,0 +1,43 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +namespace nanoFramework.Targets.STM32F429I_DISCOVERY +{ + /// + /// Enumeration of ADC channels available in STM32F429I_DISCOVERY + /// + public static class AdcChannels + { + /// + /// Channel 0, exposed on PA5, connected to PA5 (ADC1 - IN5) + /// + public const int Channel_0 = 0; + + /// + /// Channel 1, exposed on PC3, connected to PC3 (ADC2 - IN13) + /// + public const int Channel_1 = 1; + + /// + /// Channel 2, exposed on PF6, connected to PF6 (ADC3 - IN4) + /// + public const int Channel_2 = 2; + + /// + /// Channel 3, internal temperature sensor, connected to ADC1 + /// + public const int Channel_TemperatureSensor = 3; + + /// + /// Channel 4, internal voltage reference, connected to ADC1 + /// + public const int Channel_VrefIn = 4; + + /// + /// Channel 5, connected to VBatt pin, ADC1 + /// + public const int Channel_Vbatt = 5; + } +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/managed_helpers/package.nuspec b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/managed_helpers/package.nuspec new file mode 100644 index 00000000..2bec8324 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/managed_helpers/package.nuspec @@ -0,0 +1,28 @@ + + + + nanoFramework.Targets.ST_STM32F429I_DISCOVERY + nanoFramework.Targets.ST_STM32F429I_DISCOVERY + 1.0.0 + nanoFramework project contributors + nanoFramework project contributors + false + + Helper classes to use ST_STM32F429I_DISCOVERY target in C# applications. + + + + + This is an extension for .NET nanoFramework enhacing support for Windows.Devices.Gpio.GpioController when using STM32 MCUs. + + https://github.com/nanoframework + https://secure.gravatar.com/avatar/97d0e092247f0716db6d4b47b7d1d1ad + https://github.com/nanoframework/nf-interpreter/blob/develop/LICENSE.md + Copyright (c) 2019 The nanoFramework project contributors + + nanoFramework, nano Framework, NETNF, NETMF, Micro Framework, STM32, .net, STM32F429I + + + + + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/CMakeLists.txt new file mode 100644 index 00000000..291f47e1 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/CMakeLists.txt @@ -0,0 +1,9 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# # append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/STM32F429xI_booter-DEBUG.ld b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/STM32F429xI_booter-DEBUG.ld new file mode 100644 index 00000000..c0e72445 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/STM32F429xI_booter-DEBUG.ld @@ -0,0 +1,80 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * ST32F429xI memory setup. + * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash : org = 0x08000000, len = 32k /* space reserved for nanoBooter (1st two sectors 0x08000000 to 0x08008000)*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */ + ram1 : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20020000, len = 64k /* SRAM3 */ + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram4); + +/* Stacks rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/STM32F429xI_booter.ld b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/STM32F429xI_booter.ld new file mode 100644 index 00000000..306edee7 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/STM32F429xI_booter.ld @@ -0,0 +1,80 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * ST32F429xI memory setup. + * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash : org = 0x08000000, len = 16k /* space reserved for nanoBooter (1st sector 0x08000000 to 0x08004000)*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */ + ram1 : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20020000, len = 64k /* SRAM3 */ + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram4); + +/* Stacks rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/chconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/chconf.h new file mode 100644 index 00000000..ef98a914 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/chconf.h @@ -0,0 +1,616 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 1000 // this is 1 millisecond + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#define CH_CFG_INTERVALS_SIZE 32 + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_TIME_TYPES_SIZE 32 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES FALSE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS FALSE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT FALSE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES FALSE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_OBJ_FIFOS TRUE + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#define CH_CFG_USE_FACTORY FALSE + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 + +/** + * @brief Enables the registry of generic objects. + */ +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE + +/** + * @brief Enables factory for generic buffers. + */ +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE + +/** + * @brief Enables factory for semaphores. + */ +#define CH_CFG_FACTORY_SEMAPHORES TRUE + +/** + * @brief Enables factory for mailboxes. + */ +#define CH_CFG_FACTORY_MAILBOXES TRUE + +/** + * @brief Enables factory for objects FIFOs. + */ +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/halconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/halconf.h new file mode 100644 index 00000000..13104b34 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/halconf.h @@ -0,0 +1,519 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/halconf_nf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/halconf_nf.h new file mode 100644 index 00000000..809a6cfa --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/halconf_nf.h @@ -0,0 +1,15 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +#endif // _HALCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/main.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/main.c new file mode 100644 index 00000000..d5540458 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/main.c @@ -0,0 +1,84 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); + +// Application entry point. +int main(void) { + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init SWO as soon as possible to make it available to output ASAP + #if (SWO_OUTPUT == TRUE) + SwoInit(); + #endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + osDelay(20); // Let init stabilize + + // the following IF is not mandatory, it's just providing a way for a user to 'force' + // the board to remain in nanoBooter and not launching nanoCLR + + // if the USER button (blue one) is pressed, skip the check for a valid CLR image and remain in booter + // the user button in this board has a pull-up resistor so the check has to be inverted + if (!palReadPad(GPIOA, GPIOA_BUTTON)) + { + // check for valid CLR image + // this target DOES NOT have configuration block, so we need to use the __nanoImage_end__ address here + if(CheckValidCLRImage((uint32_t)&__nanoImage_end__)) + { + // there seems to be a valid CLR image + // launch nanoCLR + LaunchCLR((uint32_t)&__nanoImage_end__); + } + } + + // Initializes a serial-over-USB CDC driver. + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + // Activates the USB driver and then the USB bus pull-up on D+. + // Note, a delay is inserted in order to not have to disconnect the cable after a reset. + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1500); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // Normal main() thread + while (true) { + palSetPad(GPIOG, GPIOG_LED3_GREEN); + osDelay(250); + palClearPad(GPIOG, GPIOG_LED3_GREEN); + osDelay(250); + } +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/mcuconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/mcuconf.h new file mode 100644 index 00000000..10f82577 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/mcuconf.h @@ -0,0 +1,354 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV8 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 250 +#define STM32_SDC_READ_TIMEOUT_MS 25 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 +#define STM32_SERIAL_UART7_PRIORITY 12 +#define STM32_SERIAL_UART8_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 FALSE +#define STM32_SPI_USE_SPI5 FALSE +#define STM32_SPI_USE_SPI6 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI5_DMA_PRIORITY 1 +#define STM32_SPI_SPI6_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 TRUE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/mcuconf_nf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/mcuconf_nf.h new file mode 100644 index 00000000..5ff03534 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/mcuconf_nf.h @@ -0,0 +1,9 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/target_board.h.in b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/target_board.h.in new file mode 100644 index 00000000..19531d9c --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoBooter/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOBOOTER_H_ */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/CMakeLists.txt new file mode 100644 index 00000000..e5496b7e --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/STM32F429xI_CLR-DEBUG.ld b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/STM32F429xI_CLR-DEBUG.ld new file mode 100644 index 00000000..bd27c829 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/STM32F429xI_CLR-DEBUG.ld @@ -0,0 +1,77 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * ST32F429xI memory setup. + * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash : org = 0x08008000, len = 2M - 32k - 1408k /* flash size less the space reserved for nanoBooter and application deployment*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x080A0000, len = 1408k /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */ + ram1 : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20020000, len = 64k /* SRAM3 */ + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 + ext_ram : org = 0xD0000000, len = 8M /* external SDRAM */ +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram4); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ext_ram); + +INCLUDE rules.ld diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/STM32F429xI_CLR.ld b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/STM32F429xI_CLR.ld new file mode 100644 index 00000000..1c731acf --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/STM32F429xI_CLR.ld @@ -0,0 +1,77 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * ST32F429xI memory setup. + * Note: Use of ram1, ram2 and ram3 is mutually exclusive with use of ram0. + */ +MEMORY +{ + flash : org = 0x08004000, len = 2M - 16k - 1664k /* flash size less the space reserved for nanoBooter and application deployment*/ + config : org = 0x00000000, len = 0 /* space reserved for configuration block */ + deployment : org = 0x08040000, len = 1664k /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20000000, len = 192k /* SRAM1 + SRAM2 + SRAM3 */ + ram1 : org = 0x20000000, len = 112k /* SRAM1 */ + ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20020000, len = 64k /* SRAM3 */ + ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 + ext_ram : org = 0xD0000000, len = 8M /* external SDRAM */ +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram4); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ext_ram); + +INCLUDE rules.ld diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/chconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/chconf.h new file mode 100644 index 00000000..ef39575e --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/chconf.h @@ -0,0 +1,616 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 1000 // this is 1 millisecond + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#define CH_CFG_INTERVALS_SIZE 32 + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_TIME_TYPES_SIZE 32 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_OBJ_FIFOS TRUE + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#define CH_CFG_USE_FACTORY FALSE + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 + +/** + * @brief Enables the registry of generic objects. + */ +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE + +/** + * @brief Enables factory for generic buffers. + */ +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE + +/** + * @brief Enables factory for semaphores. + */ +#define CH_CFG_FACTORY_SEMAPHORES TRUE + +/** + * @brief Enables factory for mailboxes. + */ +#define CH_CFG_FACTORY_MAILBOXES TRUE + +/** + * @brief Enables factory for objects FIFOs. + */ +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/halconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/halconf.h new file mode 100644 index 00000000..554a9b96 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/halconf.h @@ -0,0 +1,541 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +// #define HAL_USE_ADC FALSE +// #endif + +/** + * @brief Enables the CAN subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +// #define HAL_USE_CAN FALSE +// #endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +// /** +// * @brief Enables the DAC subsystem. +// */ +// #if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +// #define HAL_USE_DAC FALSE +// #endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +// this option is set at target_platform.h (from config file) +//#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +//#define HAL_USE_I2C TRUE +//#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +// #define HAL_USE_MAC TRUE +// #endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +// #define HAL_USE_PWM FALSE +// #endif + +/** + * @brief Enables the RTC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +// #define HAL_USE_RTC TRUE +// #endif + +/** + * @brief Enables the SDC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +// #define HAL_USE_SDC FALSE +// #endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB TRUE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + + +/** + * @brief Enables the SPI subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +// #define HAL_USE_SPI FALSE +// #endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +// #define HAL_USE_UART FALSE +// #endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB TRUE +#endif + +/** + * @brief Enables the WDG subsystem. + */ + +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +// #define HAL_USE_WDG FALSE +// #endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS TRUE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/halconf_nf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/halconf_nf.h new file mode 100644 index 00000000..07183116 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/halconf_nf.h @@ -0,0 +1,24 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +// Enables the FSMC subsystem. +#if !defined(HAL_USE_FSMC) +#define HAL_USE_FSMC TRUE +#endif + +// enables STM32 Can driver +#if !defined(HAL_USE_STM32_CAN) +#define HAL_USE_STM32_CAN TRUE +#endif + +#endif // _HALCONF_NF_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/main.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/main.c new file mode 100644 index 00000000..2cb1bf2b --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/main.c @@ -0,0 +1,104 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include "usbcfg.h" +#include +#include +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); +// declare CLRStartup thread here +osThreadDef(CLRStartupThread, osPriorityNormal, 4096, "CLRStartupThread"); + +// Application entry point. +int main(void) { + + // find out wakeup reason + if((RTC->ISR & RTC_ISR_ALRAF) == RTC_ISR_ALRAF) + { + // standby, match WakeupReason_FromStandby enum + WakeupReasonStore = 1; + } + else if((PWR->CSR & PWR_CSR_WUF) == PWR_CSR_WUF) + { + // wake from pin, match WakeupReason_FromPin enum + WakeupReasonStore = 2; + } + else + { + // undetermined reason, match WakeupReason_Undetermined enum + WakeupReasonStore = 0; + } + + // first things first: need to clear any possible wakeup flags + // if this is not done here the next standby -> wakeup sequence won't work + CLEAR_BIT(RTC->CR, RTC_CR_ALRAIE); + CLEAR_BIT(RTC->ISR, RTC_ISR_ALRAF); + SET_BIT(PWR->CR, PWR_CR_CWUF); + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init SWO as soon as possible to make it available to output ASAP +#if (SWO_OUTPUT == TRUE) + SwoInit(); +#endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // start watchdog + /////////////////////////////////////////////////////////////////////////////////////////////////////// + // for STM32F4 family if watchdog is enabled can't use standby mode because the IWDG can't be stoped // + /////////////////////////////////////////////////////////////////////////////////////////////////////// + Watchdog_Init(); + + // config and init external memory + // this has to be called after osKernelInitialize, otherwise an hard fault will occur + Target_ExternalMemoryInit(); + + // Initializes a serial-over-USB CDC driver. + sduObjectInit(&SDU1); + sduStart(&SDU1, &serusbcfg); + + // Activates the USB driver and then the USB bus pull-up on D+. + // Note, a delay is inserted in order to not have to disconnect the cable after a reset + usbDisconnectBus(serusbcfg.usbp); + chThdSleepMilliseconds(1500); + usbStart(serusbcfg.usbp, &usbcfg); + usbConnectBus(serusbcfg.usbp); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // CLR settings to launch CLR thread + CLR_SETTINGS clrSettings; + (void)memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.EnterDebuggerLoopAfterExit = true; + + // create the CLR Startup thread + osThreadCreate(osThread(CLRStartupThread), &clrSettings); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + while (true) { + osDelay(100); + } +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf.h new file mode 100644 index 00000000..e5a11f75 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf.h @@ -0,0 +1,355 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF +#define STM32F429_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV8 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 2 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 TRUE +#define STM32_ADC_USE_ADC3 TRUE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_USE_CAN2 TRUE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 TRUE +#define STM32_DAC_USE_DAC1_CH2 TRUE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 TRUE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 TRUE +#define STM32_PWM_USE_TIM8 TRUE +#define STM32_PWM_USE_TIM9 TRUE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 1000 +#define STM32_SDC_READ_TIMEOUT_MS 1000 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 +#define STM32_SERIAL_UART7_PRIORITY 12 +#define STM32_SERIAL_UART8_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 FALSE +#define STM32_SPI_USE_SPI5 TRUE +#define STM32_SPI_USE_SPI6 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI5_DMA_PRIORITY 1 +#define STM32_SPI_SPI6_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 TRUE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 TRUE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 TRUE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 TRUE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG TRUE + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf_nf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf_nf.h new file mode 100644 index 00000000..b34976b4 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/mcuconf_nf.h @@ -0,0 +1,25 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + + +/* + * FSMC driver system settings. + */ +#define STM32_FSMC_USE_FSMC1 TRUE +#define STM32_FSMC_FSMC1_IRQ_PRIORITY 10 +#define STM32_FSMC_DMA_CHN 0x03010201 + +/* + * FSMC SDRAM driver system settings. + */ +#define STM32_USE_FSMC_SDRAM TRUE +#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE +#define STM32_SDRAM_USE_FSMC_SDRAM2 TRUE + +#endif // _MCUCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/nanoHAL.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/nanoHAL.cpp new file mode 100644 index 00000000..076a50fc --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/nanoHAL.cpp @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +void HAL_EnterBooterMode() +{ +} + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/target_board.h.in b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/target_board.h.in new file mode 100644 index 00000000..b980bc05 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/nanoCLR/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOCLR_H_ */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_BlockStorage.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_BlockStorage.c new file mode 100644 index 00000000..9e7c7f55 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_BlockStorage.c @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice STM32Flash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &STM32Flash_BlockStorageInterface, &Device_BlockStorageConfig, false); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_BlockStorage.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_BlockStorage.h new file mode 100644 index 00000000..aa50b1b7 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_common.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_common.c new file mode 100644 index 00000000..c633da5b --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_common.c @@ -0,0 +1,24 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include "target_common.h" + +HAL_SYSTEM_CONFIG HalSystemConfig = +{ + { true }, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, //ConvertCOM_DebugHandle(1), + 0, //ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + { RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size }, + { FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size } +}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_common.h.in b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_common.h.in new file mode 100644 index 00000000..8ca77162 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_common.h.in @@ -0,0 +1,41 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0xD0000000) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x00800000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x08000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00200000) + +///////////////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////// +#define TARGETNAMESTRING "@CHIBIOS_BOARD@" +#define PLATFORMNAMESTRING "STM32F4" +////////////////////////////////////////////// + +///////////////////////////////////// +//#define EVENTS_HEART_BEAT palToggleLine(GPIOG_LED3_GREEN) +///////////////////////////////////// + +#endif /* _TARGET_COMMON_H_ */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_external_memory.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_external_memory.c new file mode 100644 index 00000000..61e2bfae --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_external_memory.c @@ -0,0 +1,106 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "hal.h" +#include "fsmc_sdram_lld.h" + + +// SDRAM Mode definition register defines +#define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001) +#define FMC_SDCMR_MRD_BURST_LENGTH_4 ((uint16_t)0x0002) +#define FMC_SDCMR_MRD_BURST_LENGTH_8 ((uint16_t)0x0004) +#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define FMC_SDCMR_MRD_CAS_LATENCY_2 ((uint16_t)0x0020) +#define FMC_SDCMR_MRD_CAS_LATENCY_3 ((uint16_t)0x0030) +#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) + +// FMC_ReadPipe_Delay +#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000) +#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000) +#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000) +#define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000) + +// FMC_Read_Burst +#define FMC_Read_Burst_Disable ((uint32_t)0x00000000) +#define FMC_Read_Burst_Enable ((uint32_t)0x00001000) +#define FMC_Read_Burst_Mask ((uint32_t)0x00001000) + +// FMC_SDClock_Period +#define FMC_SDClock_Disable ((uint32_t)0x00000000) +#define FMC_SDClock_Period_2 ((uint32_t)0x00000800) +#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00) +#define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00) + +// FMC_ColumnBits_Number +#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000) +#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001) +#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002) +#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003) + +// FMC_RowBits_Number +#define FMC_RowBits_Number_11b ((uint32_t)0x00000000) +#define FMC_RowBits_Number_12b ((uint32_t)0x00000004) +#define FMC_RowBits_Number_13b ((uint32_t)0x00000008) + +// FMC_SDMemory_Data_Width +#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000) +#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010) +#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020) + +// FMC_InternalBank_Number +#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000) +#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040) + +// FMC_CAS_Latency +#define FMC_CAS_Latency_1 ((uint32_t)0x00000080) +#define FMC_CAS_Latency_2 ((uint32_t)0x00000100) +#define FMC_CAS_Latency_3 ((uint32_t)0x00000180) + +// FMC_Write_Protection +#define FMC_Write_Protection_Disable ((uint32_t)0x00000000) +#define FMC_Write_Protection_Enable ((uint32_t)0x00000200) + +#define SDRAM_SIZE (8 * 1024 * 1024) +#define SDRAM_START ((void *)FSMC_Bank6_MAP_BASE) + + +// SDRAM driver configuration structure. +static const SDRAMConfig sdram_cfg = { + .sdcr = (uint32_t) FMC_ColumnBits_Number_8b | + FMC_RowBits_Number_12b | + FMC_SDMemory_Width_16b | + FMC_InternalBank_Number_4 | + FMC_CAS_Latency_3 | + FMC_Write_Protection_Disable | + FMC_SDClock_Period_2 | + FMC_Read_Burst_Enable | + FMC_ReadPipe_Delay_1, + .sdtr = (uint32_t) (2 - 1) | // FMC_LoadToActiveDelay = 2 (TMRD: 2 Clock cycles) + (7 << 4) | // FMC_ExitSelfRefreshDelay = 7 (TXSR: min=70ns (7x11.11ns)) + (4 << 8) | // FMC_SelfRefreshTime = 4 (TRAS: min=42ns (4x11.11ns) max=120k (ns)) + (7 << 12) | // FMC_RowCycleDelay = 7 (TRC: min=70 (7x11.11ns)) + (3 << 16) | // FMC_WriteRecoveryTime = 2 (TWR: min=1+ 7ns (1+1x11.11ns)) + (2 << 20) | // FMC_RPDelay = 2 (TRP: 20ns => 2x11.11ns) + (2 << 24), // FMC_RCDDelay = 2 (TRCD: 20ns => 2x11.11ns) + // NRFS = 4-1 + .sdcmr = (3 << 5) | (FMC_SDCMR_MRD_BURST_LENGTH_2 | + FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL | + FMC_SDCMR_MRD_CAS_LATENCY_3 | + FMC_SDCMR_MRD_OPERATING_MODE_STANDARD | + FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE) << 9, + + .sdrtr = (uint32_t)(683 << 1), +}; + +void Target_ExternalMemoryInit() +{ + fsmcSdramInit(); + fsmcSdramStart(&SDRAMD, &sdram_cfg); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_nf_devices_can_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_nf_devices_can_config.cpp new file mode 100644 index 00000000..7dbe7ff1 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_nf_devices_can_config.cpp @@ -0,0 +1,44 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_nf_devices_can_config.h" +#include + +/////////// +// CAN1 // +/////////// + +// pin configuration for CAN1 +// port for TX pin is: GPIOB +// TX pin: is GPIOB_09 +// port for RX pin is: GPIOB +// RX pin: is GPIOB_08 +// GPIO alternate pin function is 9 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in STM32F405xx/STM32F407xx datasheet) +CAN_CONFIG_PINS(1, GPIOB, GPIOB, 9, 8, 9) + +// buffer +CANRxFrame Can1_MsgBuffer[CAN1_RX_BUFFER_SIZE]; + +// initialization for CAN1 +CAN_INIT(1, CAN1_RX_BUFFER_SIZE) + +/////////// +// CAN2 // +/////////// + +// pin configuration for CAN2 +// port for TX pin is: GPIOB +// TX pin: is GPIOB_06 +// port for RX pin is: GPIOB +// RX pin: is GPIOB_05 +// GPIO alternate pin function is 9 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in STM32F405xx/STM32F407xx datasheet) +CAN_CONFIG_PINS(2, GPIOB, GPIOB, 6, 5, 9) + +// buffer +CANRxFrame Can2_MsgBuffer[CAN2_RX_BUFFER_SIZE]; + +// initialization for CAN1 +CAN_INIT(2, CAN2_RX_BUFFER_SIZE) diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_nf_devices_can_config.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_nf_devices_can_config.h new file mode 100644 index 00000000..adc8ace3 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_nf_devices_can_config.h @@ -0,0 +1,25 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +////////// +// CAN1 // +////////// + +// enable CAN1 +#define NF_CAN_STM32_CAN_USE_CAN1 TRUE + +// buffers size +#define CAN1_RX_BUFFER_SIZE 16 + +////////// +// CAN2 // +////////// + +// enable CAN2 +#define NF_CAN_STM32_CAN_USE_CAN2 TRUE + +// buffers size +#define CAN2_RX_BUFFER_SIZE 16 diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_nf_devices_onewire_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_nf_devices_onewire_config.cpp new file mode 100644 index 00000000..22cb4e03 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_nf_devices_onewire_config.cpp @@ -0,0 +1,30 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_nf_devices_onewire_config.h" +#include + +/////////// +// UART6 // +/////////// + +// pin configuration for UART6 +// port for TX pin is: GPIOC +// TX pin: is GPIOC_6 +// GPIO alternate pin function is 8 (see "Table 12. STM32F427xx and STM32F429xx alternate function mapping" in STM32F427xx and STM32F429xx datasheet) +UART_CONFIG_PINS(6, GPIOC, 6, 8) + + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart6_TxBuffer[UART6_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart6_RxBuffer[UART6_RX_SIZE]; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_nf_devices_onewire_config.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_nf_devices_onewire_config.h new file mode 100644 index 00000000..56079a65 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_nf_devices_onewire_config.h @@ -0,0 +1,17 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////// +// UART6 // +/////////// + +// enable USART4 +#define NF_ONEWIRE_STM32_UART_USE_USART6 TRUE + +// buffers size +// tx buffer size: 32 bytes +#define UART6_TX_SIZE 32 +// rx buffer size: 32 bytes +#define UART6_RX_SIZE 32 \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_system_devices_dac_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_system_devices_dac_config.cpp new file mode 100644 index 00000000..e3a0eee9 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_system_devices_dac_config.cpp @@ -0,0 +1,17 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_DAC_PORT_PIN_CHANNEL DacPortPinConfig[] = { + + // DAC1, channel 1, GPIO port A, pin 4 + {1, 1, GPIOA, 4}, + + // DAC1, channel 2, GPIO port A, pin 5 + {1, 2, GPIOA, 5}, +}; + +const int DacChannelCount = ARRAYSIZE(DacPortPinConfig); diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_windows_devices_adc_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_windows_devices_adc_config.cpp new file mode 100644 index 00000000..88d00fa8 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_windows_devices_adc_config.cpp @@ -0,0 +1,26 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // ADC1 + {1, GPIOA, 5, ADC_CHANNEL_IN5}, + + // ADC2 + {2, GPIOC, 3, ADC_CHANNEL_IN13}, + + // ADC3 + {3, GPIOF, 6, ADC_CHANNEL_IN4}, + + // these are the internal sources, available only at ADC1 + {1, NULL, 0, ADC_CHANNEL_SENSOR}, + {1, NULL, 0, ADC_CHANNEL_VREFINT}, + {1, NULL, 0, ADC_CHANNEL_VBAT}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_windows_devices_i2c_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_windows_devices_i2c_config.cpp new file mode 100644 index 00000000..2563aa28 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_windows_devices_i2c_config.cpp @@ -0,0 +1,18 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +////////// +// I2C3 // +////////// + +// pin configuration for I2C3 +// port for SCL pin is: GPIOA +// port for SDA pin is: GPIOC +// SCL pin: is GPIOA_8 +// SDA pin: is GPIOC_9 +// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(3, GPIOA, GPIOC, 8, 9, 4) diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_windows_devices_serialcommunication_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_windows_devices_serialcommunication_config.cpp new file mode 100644 index 00000000..6a9ad77f --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_windows_devices_serialcommunication_config.cpp @@ -0,0 +1,68 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_windows_devices_serialcommunication_config.h" +#include + +/////////// +// UART1 // +/////////// + +// pin configuration for UART1 +// port for TX pin is: GPIOA +// port for RX pin is: GPIOA +// TX pin: is GPIOA_9 +// RX pin: is GPIOA_10 +// GPIO alternate pin function is 7 (see "Table 12. STM32F427xx and STM32F429xx alternate function mapping" in STM32F427xx and STM32F429xx datasheet) +UART_CONFIG_PINS(1, GPIOA, GPIOA, 9, 10, 7) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart1_TxBuffer[UART1_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart1_RxBuffer[UART1_RX_SIZE]; + +// initialization for UART1 +UART_INIT(1, UART1_TX_SIZE, UART1_RX_SIZE) + +// un-initialization for UART1 +UART_UNINIT(1) + + +/////////// +// UART3 // +/////////// + +// pin configuration for UART3 +// port for TX pin is: GPIOD +// port for RX pin is: GPIOD +// TX pin: is GPIOD_8 +// RX pin: is GPIOD_9 +// GPIO alternate pin function is 7 (see "Table 12. STM32F427xx and STM32F429xx alternate function mapping" in STM32F427xx and STM32F429xx datasheet) +UART_CONFIG_PINS(3, GPIOD, GPIOD, 8, 9, 7) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart3_TxBuffer[UART3_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart3_RxBuffer[UART3_RX_SIZE]; + +// initialization for UART3 +UART_INIT(3, UART3_TX_SIZE, UART3_RX_SIZE) + +// un-initialization for UART3 +UART_UNINIT(3) diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_windows_devices_serialcommunication_config.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_windows_devices_serialcommunication_config.h new file mode 100644 index 00000000..66229d12 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_windows_devices_serialcommunication_config.h @@ -0,0 +1,31 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////// +// UART1 // +/////////// + +// enable USART1 +#define NF_SERIAL_COMM_STM32_UART_USE_USART1 TRUE + +// buffers size +// tx buffer size: 256 bytes +#define UART1_TX_SIZE 256 +// rx buffer size: 256 bytes +#define UART1_RX_SIZE 256 + + +/////////// +// UART3 // +/////////// + +// enable USART3 +#define NF_SERIAL_COMM_STM32_UART_USE_USART3 TRUE + +// buffers size +// tx buffer size: 256 bytes +#define UART3_TX_SIZE 256 +// rx buffer size: 256 bytes +#define UART3_RX_SIZE 256 diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_windows_devices_spi_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_windows_devices_spi_config.cpp new file mode 100644 index 00000000..76238dbe --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F429I_DISCOVERY/target_windows_devices_spi_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/CMakeLists.txt new file mode 100644 index 00000000..f733d882 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/CMakeLists.txt @@ -0,0 +1,268 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +cmake_minimum_required(VERSION 3.0) +ENABLE_LANGUAGE(ASM) + +# add header files with common OS definitions and board definitions specific for each image +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoBooter/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/target_common.h" @ONLY) + +set(NANOBOOTER_PROJECT_NAME "nanoBooter") +set(NANOCLR_PROJECT_NAME "nanoCLR") + +find_package(BuildUtils REQUIRED) +find_package(CHIBIOS REQUIRED) +find_package(ChibiOSnfOverlay REQUIRED) +find_package(WireProtocol REQUIRED) + +# packages for nanoFramework libraries +####################################### +# mandatory +find_package(NF_CoreCLR REQUIRED) + +####################################### +# optional + +# ChibiOS contrib repo +if(CHIBIOS_CONTRIB_REQUIRED) + find_package(ChibiOS-Contrib REQUIRED) +endif() + +# nF feature: debugger +if(NF_FEATURE_DEBUGGER) + find_package(NF_Debugger REQUIRED) + find_package(NF_Diagnostics REQUIRED) +endif() + +# nF feature: networking +if(USE_NETWORKING_OPTION) + find_package(CHIBIOS_LWIP REQUIRED) + find_package(NF_NETWORKING REQUIRED) +endif() + +# nF feature: filesystem +if(USE_FILESYSTEM_OPTION) + find_package(CHIBIOS_FATFS REQUIRED) +endif() + +# security provider is mbedTLS +if(USE_SECURITY_MBEDTLS_OPTION) + find_package(mbedTLS REQUIRED) +endif() + +# SPIFFS +if(NF_FEATURE_USE_SPIFFS) + find_package(STM32F7_CubePackage REQUIRED) + find_package(SPIFFS REQUIRED) +endif() + +####################################### + +add_subdirectory("common") +add_subdirectory("nanoBooter") +add_subdirectory("nanoCLR") + +####################### +# nanoBooter executable + +add_executable( + # executables for project, project sources + ${NANOBOOTER_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + "${CMAKE_CURRENT_SOURCE_DIR}/target_BlockStorage.c" + + # need to add configuration manager to allow get/store configuration blocks + "${PROJECT_SOURCE_DIR}/src/HAL/nanoHAL_ConfigurationManager.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOBOOTER_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOBOOTER_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOBOOTER_SOURCES} + + ${CHIBIOS_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + + ${WireProtocol_SOURCES} +) + +####################### +# nanoCLR executable + +add_executable( + # executables for project, project sources + ${NANOCLR_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + + # the next one is required is the target implements and it's using external memory + "${CMAKE_CURRENT_SOURCE_DIR}/target_external_memory.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOCLR_PROJECT_SOURCES} + + ${TARGET_CMSIS_COMMON_SOURCES} + ${TARGET_CMSIS_NANOCLR_SOURCES} + + ${TARGET_CHIBIOS_COMMON_SOURCES} + ${TARGET_CHIBIOS_NANOCLR_SOURCES} + + ${CHIBIOS_SOURCES} + ${CHIBIOS_CONTRIB_SOURCES} + ${ChibiOSnfOverlay_SOURCES} + ${STM32F7_CubePackage_SOURCES} + ${WireProtocol_SOURCES} + + # sources for nanoFramework libraries + ${NF_CoreCLR_SOURCES} + ${NF_Debugger_SOURCES} + ${NF_Diagnostics_SOURCES} + + # sources for ChibiOS FatFS + ${CHIBIOS_FATFS_SOURCES} + + # sources for nanoFramework Network LWIP, Sockets and TLS + ${CHIBIOS_LWIP_SOURCES} + ${NF_Networking_SOURCES} + ${mbedTLS_SOURCES} + + # sources for SPIFFS + ${SPIFFS_SOURCES} + + # sources for nanoFramework APIs + ${TARGET_NANO_APIS_SOURCES} +) + +# add dependency from ChibiOS (this is required to make sure the ChibiOS repo is downloaded before the build starts) +add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf ChibiOS) +add_dependencies(${NANOCLR_PROJECT_NAME}.elf ChibiOS) + +# add dependencies from CHIBIOS_NETWORK_COMPONENTS (this is required to make sure that ChibiOS network components are unzip at the proper locations before the build starts) +# only required if networking is ON +if(USE_NETWORKING_OPTION) + add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf CHIBIOS_NETWORK_COMPONENTS) + add_dependencies(${NANOCLR_PROJECT_NAME}.elf CHIBIOS_NETWORK_COMPONENTS) + + # add dependency for security provider mbedTLS + if(USE_SECURITY_MBEDTLS_OPTION) + add_dependencies(${NANOCLR_PROJECT_NAME}.elf mbedTLS) + endif() +endif() + +# add dependencies from CHIBIOS_FILESYSTEM_COMPONENTS (this is required to make sure that ChibiOS filesystem components are unzip at the proper locations before the build starts) +# only required if filesystem is ON +if(USE_FILESYSTEM_OPTION) + add_dependencies(${NANOBOOTER_PROJECT_NAME}.elf CHIBIOS_FILESYSTEM_COMPONENTS) + add_dependencies(${NANOCLR_PROJECT_NAME}.elf CHIBIOS_FILESYSTEM_COMPONENTS) +endif() + +# include common directories +include_directories( + ${CMAKE_CURRENT_BINARY_DIR} + ${CMAKE_CURRENT_SOURCE_DIR} + ${CMAKE_CURRENT_SOURCE_DIR}/common + ${PROJECT_SOURCE_DIR}/src/CLR/Core + ${PROJECT_SOURCE_DIR}/src/CLR/Include + ${PROJECT_SOURCE_DIR}/src/HAL/Include + ${PROJECT_SOURCE_DIR}/src/PAL/Include + + ${WireProtocol_INCLUDE_DIRS} + ${CHIBIOS_INCLUDE_DIRS} + ${ChibiOSnfOverlay_INCLUDE_DIRS} + ${CHIBIOS_CONTRIB_INCLUDE_DIRS} + ${STM32F7_CubePackage_INCLUDE_DIRS} + + ${TARGET_CMSIS_COMMON_INCLUDE_DIRS} + ${TARGET_CHIBIOS_COMMON_INCLUDE_DIRS} +) + +# include directories for nanoBooter +target_include_directories(${NANOBOOTER_PROJECT_NAME}.elf PUBLIC + ${CMAKE_CURRENT_BINARY_DIR}/nanoBooter + ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter + + ${TARGET_CMSIS_NANOBOOTER_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOBOOTER_INCLUDE_DIRS} + + # includes for ChibiOS LwIP + ${CHIBIOS_LWIP_INCLUDE_DIRS} +) + +# include directories for nanoCLR +target_include_directories(${NANOCLR_PROJECT_NAME}.elf PUBLIC + ${CMAKE_CURRENT_BINARY_DIR}/nanoCLR + ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR + + ${TARGET_CMSIS_NANOCLR_INCLUDE_DIRS} + ${TARGET_CHIBIOS_NANOCLR_INCLUDE_DIRS} + + # directories for nanoFramework libraries + ${NF_CoreCLR_INCLUDE_DIRS} + ${NF_Debugger_INCLUDE_DIRS} + ${NF_Diagnostics_INCLUDE_DIRS} + + # includes for nanoFramework APIs + ${TARGET_NANO_APIS_INCLUDES} + + # includes for ChibiOS FatFS + ${CHIBIOS_FATFS_INCLUDE_DIRS} + + # includes for ChibiOS LwIP + ${CHIBIOS_LWIP_INCLUDE_DIRS} + + # incudes for Networking and TLS + ${NF_Networking_INCLUDE_DIRS} + ${mbedTLS_INCLUDE_DIRS} + + # includes for SPIFFS + ${SPIFFS_INCLUDE_DIRS} +) + +# set compiler options +nf_set_compiler_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_options(${NANOCLR_PROJECT_NAME}.elf) + +# mbed TLS requires a config file +if(USE_SECURITY_MBEDTLS_OPTION) + # this seems to be only option to properly set a compiler define through the command line that needs to be a string literal + SET(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -DMBEDTLS_CONFIG_FILE=\"<${PROJECT_SOURCE_DIR}/src/PAL/COM/sockets/ssl/mbedTLS/nf_mbedtls_config.h>\"") + SET(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -DMBEDTLS_CONFIG_FILE=\"<${PROJECT_SOURCE_DIR}/src/PAL/COM/sockets/ssl/mbedTLS/nf_mbedtls_config.h>\"") +endif() + +# set compiler definitions +nf_set_compiler_definitions(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_compiler_definitions(${NANOCLR_PROJECT_NAME}.elf) + +# set linker files +if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F76xx_booter-DEBUG.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/STM32F76xx_CLR-DEBUG.ld) +else() + nf_set_linker_file(${NANOBOOTER_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoBooter/STM32F76xx_booter.ld) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/STM32F76xx_CLR.ld) +endif() + +# set linker options +nf_set_linker_options(${NANOBOOTER_PROJECT_NAME}.elf) +nf_set_linker_options(${NANOCLR_PROJECT_NAME}.elf) + +# add other linker flags +########################################################### +# the sizes of CRT heap and ChibiOS stacks are defined here +set_property(TARGET ${NANOBOOTER_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x2000") +set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__main_stack_size__=0x400,--defsym=__process_stack_size__=0x800,--defsym=__crt_heap_size__=0x3B000") + +# generate output files +nf_generate_build_output_files(${NANOBOOTER_PROJECT_NAME}.elf) +nf_generate_build_output_files(${NANOCLR_PROJECT_NAME}.elf) diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/README.md b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/README.md new file mode 100644 index 00000000..f39844f1 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/README.md @@ -0,0 +1,32 @@ +## Configuration of ChibiOS, HAL and MCU + +For a successful build the following changes are required: + +For memory maps, uuid etc. the reference document used was: http://www.st.com/content/ccc/resource/technical/document/reference_manual/group0/96/8b/0d/ec/16/22/43/71/DM00224583/files/DM00224583.pdf/jcr:content/translations/en.DM00224583.pdf + +In _halconf.g_ (in both nanoBooter and nanoCLR folders), when compared with a default file available from (https://github.com/ChibiOS/ChibiOS/tree/master/demos/STM32/RT-STM32F769I-DISCOVERY): +- HAL_USE_SERIAL to TRUE +- SERIAL_DEFAULT_BITRATE to 921600 + +In _mcuconf.h_ (in both nanoBooter and nanoCLR folders), when compared with a default file available from (https://github.com/ChibiOS/ChibiOS/tree/master/demos/STM32/RT-STM32F769I-DISCOVERY): +- STM32_SERIAL_USE_USART1 to TRUE + +NOTE: this configuration was successfully tested in an ST_STM32F769I_DISCOVERY board using the Serial port through the onboard 7ST Link USB connection. + +## ADC configurations + +The following ADC channels (and respective GPIO pins) are available to the managed API, in the respective index: +- PA6, ADC1 IN6 +- PA4 ADC1 IN4 +- PC2 ADC1 IN12 +- PF10 ADC1 IN8 +- PF8 ADC3 IN6 +- PB8 ADC3 IN7 +- Temp Sensor ADC1 +- VrefInt ADC1 +- Vbatt ADC1 + +## Floating point + +The current build is set to add support for single-precision floating point. +Meaning that `System.Math` API supports only the `float` overloads. The `double` ones will throw a `NotImplementedException`. diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/board.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/board.c new file mode 100644 index 00000000..d08d4203 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/board.c @@ -0,0 +1,266 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) + gpio_setup_t PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_setup_t PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) + gpio_setup_t PKData; +#endif +} gpio_config_t; + +/** + * @brief STM32 GPIO static initialization data. + */ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +#endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB1(STM32_GPIO_EN_MASK); + rccEnableAHB1(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); +#endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG + gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI + gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ + gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK + gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Early initialization code. + * @details GPIO ports and system clocks are initialized before everything + * else. + */ +void __early_init(void) { + + stm32_gpio_init(); + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + + return !palReadLine(LINE_SD_DETECT); +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { + +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/board.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/board.h new file mode 100644 index 00000000..7da9cd17 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/board.h @@ -0,0 +1,1768 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + +#ifndef BOARD_H +#define BOARD_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* + * Setup for STMicroelectronics STM32F769I-Discovery board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_STM32F769I_DISCOVERY +#define BOARD_NAME "STMicroelectronics STM32F769I-Discovery" + +/* + * Ethernet PHY type. + */ +#define BOARD_PHY_ID MII_LAN8742A_ID +#define BOARD_PHY_RMII + +/* + * The board has an ULPI USB PHY. + */ +#define BOARD_OTG2_USES_ULPI + +/* + * Board oscillators-related settings. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768U +#endif + +#define STM32_LSEDRV (3U << 3U) + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 25000000U +#endif + +#define STM32_HSE_BYPASS + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U + +/* + * MCU type as defined in the ST header. + */ +#define STM32F769xx + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON_USER 0U +#define GPIOA_RMII_REF_CLK 1U +#define GPIOA_RMII_MDIO 2U +#define GPIOA_ULPI_D0 3U +#define GPIOA_ARD_A1 4U +#define GPIOA_ULPI_CK 5U +#define GPIOA_ARD_A0 6U +#define GPIOA_RMII_CRS_DV 7U +#define GPIOA_CEC_CLK 8U +#define GPIOA_VCP_TX 9U +#define GPIOA_VCP_RX 10U +#define GPIOA_ARD_D10 11U +#define GPIOA_ARD_D13 12U +#define GPIOA_SWDIO 13U +#define GPIOA_SWCLK 14U +#define GPIOA_CEC 15U + +#define GPIOB_ULPI_D1 0U +#define GPIOB_ULPI_D2 1U +#define GPIOB_QSPI_CLK 2U +#define GPIOB_SD_D2 3U +#define GPIOB_SD_D3 4U +#define GPIOB_ULPI_D7 5U +#define GPIOB_QUADSPI_BK1_NCS 6U +#define GPIOB_AUDIO_SDA 7U +#define GPIOB_LCD_SDA 7U +#define GPIOB_ARD_D15 8U +#define GPIOB_ARD_D14 9U +#define GPIOB_ULPI_D3 10U +#define GPIOB_ULPI_D4 11U +#define GPIOB_ULPI_D5 12U +#define GPIOB_ULPI_D6 13U +#define GPIOB_ARD_D12 14U +#define GPIOB_ARD_D11 15U + +#define GPIOC_ULPI_STP 0U +#define GPIOC_RMII_MDC 1U +#define GPIOC_ARD_A2 2U +#define GPIOC_DFSDM_DATIN1 3U +#define GPIOC_RMII_RXD0 4U +#define GPIOC_RMII_RXD1 5U +#define GPIOC_ARD_D1 6U +#define GPIOC_ARD_D0 7U +#define GPIOC_ARD_D5 8U +#define GPIOB_I2C1_SCL 8U +#define GPIOC_QSPI_D0 9U +#define GPIOB_I2C1_SDA 9U +#define GPIOC_QSPI_D1 10U +#define GPIOC_DFSDM_DATIN5 11U +#define GPIOC_WIFI_RX 12U +#define GPIOC_PIN13 13U +#define GPIOC_OSC32_IN 14U +#define GPIOC_OSC32_OUT 15U + +#define GPIOD_FMC_D2 0U +#define GPIOD_FMC_D3 1U +#define GPIOD_WIFI_TX 2U +#define GPIOD_DFSDM_CKOUT 3U +#define GPIOD_OTG_HS_OVER_CURRENT 4U +#define GPIOD_RMII_RXER 5U +#define GPIOD_SD_CLK 6U +#define GPIOD_SD_CMD 7U +#define GPIOD_FMC_D13 8U +#define GPIOD_FMC_D14 9U +#define GPIOD_FMC_D15 10U +#define GPIOD_SPDIF_I2S 11U +#define GPIOD_AUDIO_SCL 12U +#define GPIOD_LCD_SCL 12U +#define GPIOD_QSPI_D3 13U +#define GPIOD_FMC_D0 14U +#define GPIOD_FMC_D1 15U + +#define GPIOE_FMC_NBL0 0U +#define GPIOE_FMC_NBL1 1U +#define GPIOE_QSPI_D2 2U +#define GPIOE_SAI1_SDB 3U +#define GPIOE_SAI1_FSA 4U +#define GPIOE_SAI1_SCKA 5U +#define GPIOE_SAI1_SDA 6U +#define GPIOE_FMC_D4 7U +#define GPIOE_FMC_D5 8U +#define GPIOE_FMC_D6 9U +#define GPIOE_FMC_D7 10U +#define GPIOE_FMC_D8 11U +#define GPIOE_FMC_D9 12U +#define GPIOE_FMC_D10 13U +#define GPIOE_FMC_11 14U +#define GPIOE_FMC_D12 15U + +#define GPIOF_FMC_A0 0U +#define GPIOF_FMC_A1 1U +#define GPIOF_FMC_A2 2U +#define GPIOF_FMC_A3 3U +#define GPIOF_FMC_A4 4U +#define GPIOF_FMC_A5 5U +#define GPIOF_ARD_D3 6U +#define GPIOF_ARD_D6 7U +#define GPIOF_ARD_A4 8U +#define GPIOF_ARD_A5 9U +#define GPIOF_ARD_A3 10U +#define GPIOF_FMC_SDNRAS 11U +#define GPIOF_FMC_A6 12U +#define GPIOF_FMC_A7 13U +#define GPIOF_FMC_A8 14U +#define GPIOF_FMC_A9 15U + +#define GPIOG_FMC_A10 0U +#define GPIOG_FMC_A11 1U +#define GPIOG_FMC_A12 2U +#define GPIOG_EXT_SCL 3U +#define GPIOG_FMC_BA0 4U +#define GPIOG_FMC_BA1 5U +#define GPIOG_EXT_SDA 6U +#define GPIOG_SAI1_MCLKA 7U +#define GPIOG_FMC_SDCLK 8U +#define GPIOG_SD_D0 9U +#define GPIOG_SD_D1 10U +#define GPIOG_RMII_TX_EN 11U +#define GPIOG_SPDIF_RX 12U +#define GPIOG_RMII_TXD0 13U +#define GPIOG_RMII_TXD1 14U +#define GPIOG_FMC_SDNCAS 15U + +#define GPIOH_OSC_IN 0U +#define GPIOH_OSC_OUT 1U +#define GPIOH_FMC_SDCKE0 2U +#define GPIOH_FMC_SDNE0 3U +#define GPIOH_ULPI_NXT 4U +#define GPIOH_FMC_SDNWE 5U +#define GPIOH_ARD_D9 6U +#define GPIOH_EXT_RST 7U +#define GPIOH_FMC_D16 8U +#define GPIOH_FMC_D17 9U +#define GPIOH_FMC_D18 10U +#define GPIOH_FMC_D19 11U +#define GPIOH_FMC_D20 12U +#define GPIOH_FMC_D21 13U +#define GPIOH_FMC_D22 14U +#define GPIOH_FMC_D23 15U + +#define GPIOI_FMC_D24 0U +#define GPIOI_FMC_D25 1U +#define GPIOI_FMC_D26 2U +#define GPIOI_FMC_D27 3U +#define GPIOI_FMC_NBL2 4U +#define GPIOI_FMC_NBL3 5U +#define GPIOI_FMC_D28 6U +#define GPIOI_FMC_D29 7U +#define GPIOI_PIN8 8U +#define GPIOI_FMC_D30 9U +#define GPIOI_FMC_D31 10U +#define GPIOI_ULPI_DIR 11U +#define GPIOI_PIN12 12U +#define GPIOI_LCD_INT 13U +#define GPIOI_LCD_BL_CTRL 14U +#define GPIOI_SD_DETECT 15U + +#define GPIOJ_ARD_D4 0U +#define GPIOJ_ARD_D2 1U +#define GPIOJ_DSI_TE 2U +#define GPIOJ_ARD_D7 3U +#define GPIOJ_ARD_D8 4U +#define GPIOJ_LED2_GREEN 5U +#define GPIOJ_PIN6 6U +#define GPIOJ_PIN7 7U +#define GPIOJ_PIN8 8U +#define GPIOJ_PIN9 9U +#define GPIOJ_PIN10 10U +#define GPIOJ_PIN11 11U +#define GPIOJ_AUDIO_INT 12U +#define GPIOJ_LED1_RED 13U +#define GPIOJ_WIFI_RST 14U +#define GPIOJ_DSI_RESET 15U + +#define GPIOK_PIN0 0U +#define GPIOK_PIN1 1U +#define GPIOK_PIN2 2U +#define GPIOK_PIN3 3U +#define GPIOK_PIN4 4U +#define GPIOK_PIN5 5U +#define GPIOK_PIN6 6U +#define GPIOK_PIN7 7U +#define GPIOK_PIN8 8U +#define GPIOK_PIN9 9U +#define GPIOK_PIN10 10U +#define GPIOK_PIN11 11U +#define GPIOK_PIN12 12U +#define GPIOK_PIN13 13U +#define GPIOK_PIN14 14U +#define GPIOK_PIN15 15U + +/* + * IO lines assignments. + */ +#define LINE_BUTTON_USER PAL_LINE(GPIOA, 0U) +#define LINE_RMII_REF_CLK PAL_LINE(GPIOA, 1U) +#define LINE_RMII_MDIO PAL_LINE(GPIOA, 2U) +#define LINE_ULPI_D0 PAL_LINE(GPIOA, 3U) +#define LINE_ARD_A1 PAL_LINE(GPIOA, 4U) +#define LINE_ULPI_CK PAL_LINE(GPIOA, 5U) +#define LINE_ARD_A0 PAL_LINE(GPIOA, 6U) +#define LINE_RMII_CRS_DV PAL_LINE(GPIOA, 7U) +#define LINE_CEC_CLK PAL_LINE(GPIOA, 8U) +#define LINE_VCP_TX PAL_LINE(GPIOA, 9U) +#define LINE_VCP_RX PAL_LINE(GPIOA, 10U) +#define LINE_ARD_D10 PAL_LINE(GPIOA, 11U) +#define LINE_ARD_D13 PAL_LINE(GPIOA, 12U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) +#define LINE_CEC PAL_LINE(GPIOA, 15U) +#define LINE_ULPI_D1 PAL_LINE(GPIOB, 0U) +#define LINE_ULPI_D2 PAL_LINE(GPIOB, 1U) +#define LINE_QSPI_CLK PAL_LINE(GPIOB, 2U) +#define LINE_SD_D2 PAL_LINE(GPIOB, 3U) +#define LINE_SD_D3 PAL_LINE(GPIOB, 4U) +#define LINE_ULPI_D7 PAL_LINE(GPIOB, 5U) +#define LINE_QUADSPI_BK1_NCS PAL_LINE(GPIOB, 6U) +#define LINE_AUDIO_SDA PAL_LINE(GPIOB, 7U) +#define LINE_LCD_SDA PAL_LINE(GPIOB, 7U) +#define LINE_ARD_D15 PAL_LINE(GPIOB, 8U) +#define LINE_I2C1_SCL PAL_LINE(GPIOB, 8U) +#define LINE_ARD_D14 PAL_LINE(GPIOB, 9U) +#define LINE_I2C1_SDA PAL_LINE(GPIOB, 9U) +#define LINE_ULPI_D3 PAL_LINE(GPIOB, 10U) +#define LINE_ULPI_D4 PAL_LINE(GPIOB, 11U) +#define LINE_ULPI_D5 PAL_LINE(GPIOB, 12U) +#define LINE_ULPI_D6 PAL_LINE(GPIOB, 13U) +#define LINE_ARD_D12 PAL_LINE(GPIOB, 14U) +#define LINE_ARD_D11 PAL_LINE(GPIOB, 15U) +#define LINE_ULPI_STP PAL_LINE(GPIOC, 0U) +#define LINE_RMII_MDC PAL_LINE(GPIOC, 1U) +#define LINE_ARD_A2 PAL_LINE(GPIOC, 2U) +#define LINE_DFSDM_DATIN1 PAL_LINE(GPIOC, 3U) +#define LINE_RMII_RXD0 PAL_LINE(GPIOC, 4U) +#define LINE_RMII_RXD1 PAL_LINE(GPIOC, 5U) +#define LINE_ARD_D1 PAL_LINE(GPIOC, 6U) +#define LINE_ARD_D0 PAL_LINE(GPIOC, 7U) +#define LINE_ARD_D5 PAL_LINE(GPIOC, 8U) +#define LINE_QSPI_D0 PAL_LINE(GPIOC, 9U) +#define LINE_QSPI_D1 PAL_LINE(GPIOC, 10U) +#define LINE_DFSDM_DATIN5 PAL_LINE(GPIOC, 11U) +#define LINE_WIFI_RX PAL_LINE(GPIOC, 12U) +#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) +#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) +#define LINE_FMC_D2 PAL_LINE(GPIOD, 0U) +#define LINE_FMC_D3 PAL_LINE(GPIOD, 1U) +#define LINE_WIFI_TX PAL_LINE(GPIOD, 2U) +#define LINE_DFSDM_CKOUT PAL_LINE(GPIOD, 3U) +#define LINE_OTG_HS_OVER_CURRENT PAL_LINE(GPIOD, 4U) +#define LINE_RMII_RXER PAL_LINE(GPIOD, 5U) +#define LINE_SD_CLK PAL_LINE(GPIOD, 6U) +#define LINE_SD_CMD PAL_LINE(GPIOD, 7U) +#define LINE_FMC_D13 PAL_LINE(GPIOD, 8U) +#define LINE_FMC_D14 PAL_LINE(GPIOD, 9U) +#define LINE_FMC_D15 PAL_LINE(GPIOD, 10U) +#define LINE_SPDIF_I2S PAL_LINE(GPIOD, 11U) +#define LINE_AUDIO_SCL PAL_LINE(GPIOD, 12U) +#define LINE_LCD_SCL PAL_LINE(GPIOD, 12U) +#define LINE_QSPI_D3 PAL_LINE(GPIOD, 13U) +#define LINE_FMC_D0 PAL_LINE(GPIOD, 14U) +#define LINE_FMC_D1 PAL_LINE(GPIOD, 15U) +#define LINE_FMC_NBL0 PAL_LINE(GPIOE, 0U) +#define LINE_FMC_NBL1 PAL_LINE(GPIOE, 1U) +#define LINE_QSPI_D2 PAL_LINE(GPIOE, 2U) +#define LINE_SAI1_SDB PAL_LINE(GPIOE, 3U) +#define LINE_SAI1_FSA PAL_LINE(GPIOE, 4U) +#define LINE_SAI1_SCKA PAL_LINE(GPIOE, 5U) +#define LINE_SAI1_SDA PAL_LINE(GPIOE, 6U) +#define LINE_FMC_D4 PAL_LINE(GPIOE, 7U) +#define LINE_FMC_D5 PAL_LINE(GPIOE, 8U) +#define LINE_FMC_D6 PAL_LINE(GPIOE, 9U) +#define LINE_FMC_D7 PAL_LINE(GPIOE, 10U) +#define LINE_FMC_D8 PAL_LINE(GPIOE, 11U) +#define LINE_FMC_D9 PAL_LINE(GPIOE, 12U) +#define LINE_FMC_D10 PAL_LINE(GPIOE, 13U) +#define LINE_FMC_11 PAL_LINE(GPIOE, 14U) +#define LINE_FMC_D12 PAL_LINE(GPIOE, 15U) +#define LINE_FMC_A0 PAL_LINE(GPIOF, 0U) +#define LINE_FMC_A1 PAL_LINE(GPIOF, 1U) +#define LINE_FMC_A2 PAL_LINE(GPIOF, 2U) +#define LINE_FMC_A3 PAL_LINE(GPIOF, 3U) +#define LINE_FMC_A4 PAL_LINE(GPIOF, 4U) +#define LINE_FMC_A5 PAL_LINE(GPIOF, 5U) +#define LINE_ARD_D3 PAL_LINE(GPIOF, 6U) +#define LINE_ARD_D6 PAL_LINE(GPIOF, 7U) +#define LINE_ARD_A4 PAL_LINE(GPIOF, 8U) +#define LINE_ARD_A5 PAL_LINE(GPIOF, 9U) +#define LINE_ARD_A3 PAL_LINE(GPIOF, 10U) +#define LINE_FMC_SDNRAS PAL_LINE(GPIOF, 11U) +#define LINE_FMC_A6 PAL_LINE(GPIOF, 12U) +#define LINE_FMC_A7 PAL_LINE(GPIOF, 13U) +#define LINE_FMC_A8 PAL_LINE(GPIOF, 14U) +#define LINE_FMC_A9 PAL_LINE(GPIOF, 15U) +#define LINE_FMC_A10 PAL_LINE(GPIOG, 0U) +#define LINE_FMC_A11 PAL_LINE(GPIOG, 1U) +#define LINE_FMC_A12 PAL_LINE(GPIOG, 2U) +#define LINE_EXT_SCL PAL_LINE(GPIOG, 3U) +#define LINE_FMC_BA0 PAL_LINE(GPIOG, 4U) +#define LINE_FMC_BA1 PAL_LINE(GPIOG, 5U) +#define LINE_EXT_SDA PAL_LINE(GPIOG, 6U) +#define LINE_SAI1_MCLKA PAL_LINE(GPIOG, 7U) +#define LINE_FMC_SDCLK PAL_LINE(GPIOG, 8U) +#define LINE_SD_D0 PAL_LINE(GPIOG, 9U) +#define LINE_SD_D1 PAL_LINE(GPIOG, 10U) +#define LINE_RMII_TX_EN PAL_LINE(GPIOG, 11U) +#define LINE_SPDIF_RX PAL_LINE(GPIOG, 12U) +#define LINE_RMII_TXD0 PAL_LINE(GPIOG, 13U) +#define LINE_RMII_TXD1 PAL_LINE(GPIOG, 14U) +#define LINE_FMC_SDNCAS PAL_LINE(GPIOG, 15U) +#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) +#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) +#define LINE_FMC_SDCKE0 PAL_LINE(GPIOH, 2U) +#define LINE_FMC_SDNE0 PAL_LINE(GPIOH, 3U) +#define LINE_ULPI_NXT PAL_LINE(GPIOH, 4U) +#define LINE_FMC_SDNWE PAL_LINE(GPIOH, 5U) +#define LINE_ARD_D9 PAL_LINE(GPIOH, 6U) +#define LINE_EXT_RST PAL_LINE(GPIOH, 7U) +#define LINE_FMC_D16 PAL_LINE(GPIOH, 8U) +#define LINE_FMC_D17 PAL_LINE(GPIOH, 9U) +#define LINE_FMC_D18 PAL_LINE(GPIOH, 10U) +#define LINE_FMC_D19 PAL_LINE(GPIOH, 11U) +#define LINE_FMC_D20 PAL_LINE(GPIOH, 12U) +#define LINE_FMC_D21 PAL_LINE(GPIOH, 13U) +#define LINE_FMC_D22 PAL_LINE(GPIOH, 14U) +#define LINE_FMC_D23 PAL_LINE(GPIOH, 15U) +#define LINE_FMC_D24 PAL_LINE(GPIOI, 0U) +#define LINE_FMC_D25 PAL_LINE(GPIOI, 1U) +#define LINE_FMC_D26 PAL_LINE(GPIOI, 2U) +#define LINE_FMC_D27 PAL_LINE(GPIOI, 3U) +#define LINE_FMC_NBL2 PAL_LINE(GPIOI, 4U) +#define LINE_FMC_NBL3 PAL_LINE(GPIOI, 5U) +#define LINE_FMC_D28 PAL_LINE(GPIOI, 6U) +#define LINE_FMC_D29 PAL_LINE(GPIOI, 7U) +#define LINE_FMC_D30 PAL_LINE(GPIOI, 9U) +#define LINE_FMC_D31 PAL_LINE(GPIOI, 10U) +#define LINE_ULPI_DIR PAL_LINE(GPIOI, 11U) +#define LINE_LCD_INT PAL_LINE(GPIOI, 13U) +#define LINE_LCD_BL_CTRL PAL_LINE(GPIOI, 14U) +#define LINE_SD_DETECT PAL_LINE(GPIOI, 15U) +#define LINE_ARD_D4 PAL_LINE(GPIOJ, 0U) +#define LINE_ARD_D2 PAL_LINE(GPIOJ, 1U) +#define LINE_DSI_TE PAL_LINE(GPIOJ, 2U) +#define LINE_ARD_D7 PAL_LINE(GPIOJ, 3U) +#define LINE_ARD_D8 PAL_LINE(GPIOJ, 4U) +#define LINE_LED2_GREEN PAL_LINE(GPIOJ, 5U) +#define LINE_AUDIO_INT PAL_LINE(GPIOJ, 12U) +#define LINE_LED1_RED PAL_LINE(GPIOJ, 13U) +#define LINE_WIFI_RST PAL_LINE(GPIOJ, 14U) +#define LINE_DSI_RESET PAL_LINE(GPIOJ, 15U) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * GPIOA setup: + * + * PA0 - BUTTON_USER (input floating). + * PA1 - RMII_REF_CLK (alternate 11). + * PA2 - RMII_MDIO (alternate 11). + * PA3 - ULPI_D0 (alternate 10). + * PA4 - ARD_A1 (input pullup). + * PA5 - ULPI_CK (alternate 10). + * PA6 - ARD_A0 (input pullup). + * PA7 - RMII_CRS_DV (alternate 11). + * PA8 - CEC_CLK (alternate 0). + * PA9 - VCP_TX (alternate 7). + * PA10 - VCP_RX (alternate 7). + * PA11 - ARD_D10 (input pullup). + * PA12 - ARD_D13 (input pullup). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - CEC (alternate 3). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON_USER) | \ + PIN_MODE_ALTERNATE(GPIOA_RMII_REF_CLK) |\ + PIN_MODE_ALTERNATE(GPIOA_RMII_MDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_ULPI_D0) | \ + PIN_MODE_INPUT(GPIOA_ARD_A1) | \ + PIN_MODE_ALTERNATE(GPIOA_ULPI_CK) | \ + PIN_MODE_INPUT(GPIOA_ARD_A0) | \ + PIN_MODE_ALTERNATE(GPIOA_RMII_CRS_DV) |\ + PIN_MODE_ALTERNATE(GPIOA_CEC_CLK) | \ + PIN_MODE_ALTERNATE(GPIOA_VCP_TX) | \ + PIN_MODE_ALTERNATE(GPIOA_VCP_RX) | \ + PIN_MODE_INPUT(GPIOA_ARD_D10) | \ + PIN_MODE_INPUT(GPIOA_ARD_D13) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_ALTERNATE(GPIOA_CEC)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON_USER) |\ + PIN_OTYPE_PUSHPULL(GPIOA_RMII_REF_CLK) |\ + PIN_OTYPE_PUSHPULL(GPIOA_RMII_MDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ULPI_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_A1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ULPI_CK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_RMII_CRS_DV) |\ + PIN_OTYPE_PUSHPULL(GPIOA_CEC_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_VCP_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOA_VCP_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D10) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D13) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_CEC)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_BUTTON_USER) | \ + PIN_OSPEED_HIGH(GPIOA_RMII_REF_CLK) | \ + PIN_OSPEED_HIGH(GPIOA_RMII_MDIO) | \ + PIN_OSPEED_HIGH(GPIOA_ULPI_D0) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_A1) | \ + PIN_OSPEED_HIGH(GPIOA_ULPI_CK) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \ + PIN_OSPEED_VERYLOW(GPIOA_RMII_CRS_DV) |\ + PIN_OSPEED_HIGH(GPIOA_CEC_CLK) | \ + PIN_OSPEED_HIGH(GPIOA_VCP_TX) | \ + PIN_OSPEED_HIGH(GPIOA_VCP_RX) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D10) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D13) | \ + PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ + PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ + PIN_OSPEED_HIGH(GPIOA_CEC)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON_USER) |\ + PIN_PUPDR_FLOATING(GPIOA_RMII_REF_CLK) |\ + PIN_PUPDR_PULLUP(GPIOA_RMII_MDIO) | \ + PIN_PUPDR_FLOATING(GPIOA_ULPI_D0) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_A1) | \ + PIN_PUPDR_FLOATING(GPIOA_ULPI_CK) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_A0) | \ + PIN_PUPDR_FLOATING(GPIOA_RMII_CRS_DV) |\ + PIN_PUPDR_FLOATING(GPIOA_CEC_CLK) | \ + PIN_PUPDR_FLOATING(GPIOA_VCP_TX) | \ + PIN_PUPDR_FLOATING(GPIOA_VCP_RX) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D10) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D13) | \ + PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \ + PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \ + PIN_PUPDR_FLOATING(GPIOA_CEC)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON_USER) | \ + PIN_ODR_HIGH(GPIOA_RMII_REF_CLK) | \ + PIN_ODR_HIGH(GPIOA_RMII_MDIO) | \ + PIN_ODR_HIGH(GPIOA_ULPI_D0) | \ + PIN_ODR_HIGH(GPIOA_ARD_A1) | \ + PIN_ODR_HIGH(GPIOA_ULPI_CK) | \ + PIN_ODR_HIGH(GPIOA_ARD_A0) | \ + PIN_ODR_HIGH(GPIOA_RMII_CRS_DV) | \ + PIN_ODR_HIGH(GPIOA_CEC_CLK) | \ + PIN_ODR_HIGH(GPIOA_VCP_TX) | \ + PIN_ODR_HIGH(GPIOA_VCP_RX) | \ + PIN_ODR_HIGH(GPIOA_ARD_D10) | \ + PIN_ODR_HIGH(GPIOA_ARD_D13) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_CEC)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON_USER, 0U) | \ + PIN_AFIO_AF(GPIOA_RMII_REF_CLK, 11U) | \ + PIN_AFIO_AF(GPIOA_RMII_MDIO, 11U) | \ + PIN_AFIO_AF(GPIOA_ULPI_D0, 10U) | \ + PIN_AFIO_AF(GPIOA_ARD_A1, 0U) | \ + PIN_AFIO_AF(GPIOA_ULPI_CK, 10U) | \ + PIN_AFIO_AF(GPIOA_ARD_A0, 0U) | \ + PIN_AFIO_AF(GPIOA_RMII_CRS_DV, 11U)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_CEC_CLK, 0U) | \ + PIN_AFIO_AF(GPIOA_VCP_TX, 7U) | \ + PIN_AFIO_AF(GPIOA_VCP_RX, 7U) | \ + PIN_AFIO_AF(GPIOA_ARD_D10, 0U) | \ + PIN_AFIO_AF(GPIOA_ARD_D13, 0U) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0U) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0U) | \ + PIN_AFIO_AF(GPIOA_CEC, 3U)) + +/* + * GPIOB setup: + * + * PB0 - ULPI_D1 (alternate 10). + * PB1 - ULPI_D2 (alternate 10). + * PB2 - QSPI_CLK (alternate 9). + * PB3 - SD_D2 (alternate 10). + * PB4 - SD_D3 (alternate 10). + * PB5 - ULPI_D7 (alternate 10). + * PB6 - QUADSPI_BK1_NCS (alternate 10). + * PB7 - AUDIO_SDA LCD_SDA (alternate 11). + * PB8 - ARD_D15 (input pullup). + * PB9 - ARD_D14 (input pullup). + * PB10 - ULPI_D3 (alternate 10). + * PB11 - ULPI_D4 (alternate 10). + * PB12 - ULPI_D5 (alternate 10). + * PB13 - ULPI_D6 (alternate 10). + * PB14 - ARD_D12 (input pullup). + * PB15 - ARD_D11 (input pullup). + */ +#define VAL_GPIOB_MODER (PIN_MODE_ALTERNATE(GPIOB_ULPI_D1) | \ + PIN_MODE_ALTERNATE(GPIOB_ULPI_D2) | \ + PIN_MODE_ALTERNATE(GPIOB_QSPI_CLK) | \ + PIN_MODE_ALTERNATE(GPIOB_SD_D2) | \ + PIN_MODE_ALTERNATE(GPIOB_SD_D3) | \ + PIN_MODE_ALTERNATE(GPIOB_ULPI_D7) | \ + PIN_MODE_ALTERNATE(GPIOB_QUADSPI_BK1_NCS) | \ + PIN_MODE_ALTERNATE(GPIOB_AUDIO_SDA) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \ + PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \ + PIN_MODE_ALTERNATE(GPIOB_ULPI_D3) | \ + PIN_MODE_ALTERNATE(GPIOB_ULPI_D4) | \ + PIN_MODE_ALTERNATE(GPIOB_ULPI_D5) | \ + PIN_MODE_ALTERNATE(GPIOB_ULPI_D6) | \ + PIN_MODE_INPUT(GPIOB_ARD_D12) | \ + PIN_MODE_INPUT(GPIOB_ARD_D11)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_QSPI_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SD_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SD_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOB_QUADSPI_BK1_NCS) | \ + PIN_OTYPE_PUSHPULL(GPIOB_AUDIO_SDA) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \ + PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D11)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ULPI_D1) | \ + PIN_OSPEED_HIGH(GPIOB_ULPI_D2) | \ + PIN_OSPEED_HIGH(GPIOB_QSPI_CLK) | \ + PIN_OSPEED_HIGH(GPIOB_SD_D2) | \ + PIN_OSPEED_HIGH(GPIOB_SD_D3) | \ + PIN_OSPEED_HIGH(GPIOB_ULPI_D7) | \ + PIN_OSPEED_HIGH(GPIOB_QUADSPI_BK1_NCS) | \ + PIN_OSPEED_HIGH(GPIOB_AUDIO_SDA) | \ + PIN_OSPEED_HIGH(GPIOB_I2C1_SCL) | \ + PIN_OSPEED_HIGH(GPIOB_I2C1_SDA) | \ + PIN_OSPEED_HIGH(GPIOB_ULPI_D3) | \ + PIN_OSPEED_HIGH(GPIOB_ULPI_D4) | \ + PIN_OSPEED_HIGH(GPIOB_ULPI_D5) | \ + PIN_OSPEED_HIGH(GPIOB_ULPI_D6) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D12) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D11)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_ULPI_D1) | \ + PIN_PUPDR_FLOATING(GPIOB_ULPI_D2) | \ + PIN_PUPDR_FLOATING(GPIOB_QSPI_CLK) | \ + PIN_PUPDR_FLOATING(GPIOB_SD_D2) | \ + PIN_PUPDR_FLOATING(GPIOB_SD_D3) | \ + PIN_PUPDR_PULLUP(GPIOB_ULPI_D7) | \ + PIN_PUPDR_FLOATING(GPIOB_QUADSPI_BK1_NCS) | \ + PIN_PUPDR_FLOATING(GPIOB_AUDIO_SDA) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SCL) | \ + PIN_PUPDR_FLOATING(GPIOB_I2C1_SDA) | \ + PIN_PUPDR_FLOATING(GPIOB_ULPI_D3) | \ + PIN_PUPDR_FLOATING(GPIOB_ULPI_D4) | \ + PIN_PUPDR_FLOATING(GPIOB_ULPI_D5) | \ + PIN_PUPDR_FLOATING(GPIOB_ULPI_D6) | \ + PIN_PUPDR_PULLUP(GPIOB_ARD_D12) | \ + PIN_PUPDR_PULLUP(GPIOB_ARD_D11)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_ULPI_D1) | \ + PIN_ODR_HIGH(GPIOB_ULPI_D2) | \ + PIN_ODR_HIGH(GPIOB_QSPI_CLK) | \ + PIN_ODR_HIGH(GPIOB_SD_D2) | \ + PIN_ODR_HIGH(GPIOB_SD_D3) | \ + PIN_ODR_HIGH(GPIOB_ULPI_D7) | \ + PIN_ODR_HIGH(GPIOB_QUADSPI_BK1_NCS) | \ + PIN_ODR_HIGH(GPIOB_AUDIO_SDA) | \ + PIN_ODR_LOW(GPIOB_I2C1_SCL) | \ + PIN_ODR_LOW(GPIOB_I2C1_SDA) | \ + PIN_ODR_HIGH(GPIOB_ULPI_D3) | \ + PIN_ODR_HIGH(GPIOB_ULPI_D4) | \ + PIN_ODR_HIGH(GPIOB_ULPI_D5) | \ + PIN_ODR_HIGH(GPIOB_ULPI_D6) | \ + PIN_ODR_HIGH(GPIOB_ARD_D12) | \ + PIN_ODR_HIGH(GPIOB_ARD_D11)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ULPI_D1, 10U) | \ + PIN_AFIO_AF(GPIOB_ULPI_D2, 10U) | \ + PIN_AFIO_AF(GPIOB_QSPI_CLK, 9U) | \ + PIN_AFIO_AF(GPIOB_SD_D2, 10U) | \ + PIN_AFIO_AF(GPIOB_SD_D3, 10U) | \ + PIN_AFIO_AF(GPIOB_ULPI_D7, 10U) | \ + PIN_AFIO_AF(GPIOB_QUADSPI_BK1_NCS, 10U) | \ + PIN_AFIO_AF(GPIOB_AUDIO_SDA, 11U)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SCL, 4U) | \ + PIN_AFIO_AF(GPIOB_I2C1_SDA, 4U) | \ + PIN_AFIO_AF(GPIOB_ULPI_D3, 10U) | \ + PIN_AFIO_AF(GPIOB_ULPI_D4, 10U) | \ + PIN_AFIO_AF(GPIOB_ULPI_D5, 10U) | \ + PIN_AFIO_AF(GPIOB_ULPI_D6, 10U) | \ + PIN_AFIO_AF(GPIOB_ARD_D12, 0U) | \ + PIN_AFIO_AF(GPIOB_ARD_D11, 0U)) + +/* + * GPIOC setup: + * + * PC0 - ULPI_STP (alternate 10). + * PC1 - RMII_MDC (alternate 11). + * PC2 - ARD_A2 (input pullup). + * PC3 - DFSDM_DATIN1 (alternate 3). + * PC4 - RMII_RXD0 (alternate 11). + * PC5 - RMII_RXD1 (alternate 11). + * PC6 - ARD_D1 (input pullup). + * PC7 - ARD_D0 (input floating). + * PC8 - ARD_D5 (input floating). + * PC9 - QSPI_D0 (alternate 9). + * PC10 - QSPI_D1 (alternate 9). + * PC11 - DFSDM_DATIN5 (alternate 3). + * PC12 - WIFI_RX (alternate 8). + * PC13 - PIN13 (input pullup). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_ALTERNATE(GPIOC_ULPI_STP) | \ + PIN_MODE_ALTERNATE(GPIOC_RMII_MDC) | \ + PIN_MODE_INPUT(GPIOC_ARD_A2) | \ + PIN_MODE_ALTERNATE(GPIOC_DFSDM_DATIN1) |\ + PIN_MODE_ALTERNATE(GPIOC_RMII_RXD0) | \ + PIN_MODE_ALTERNATE(GPIOC_RMII_RXD1) | \ + PIN_MODE_INPUT(GPIOC_ARD_D1) | \ + PIN_MODE_INPUT(GPIOC_ARD_D0) | \ + PIN_MODE_INPUT(GPIOC_ARD_D5) | \ + PIN_MODE_ALTERNATE(GPIOC_QSPI_D0) | \ + PIN_MODE_ALTERNATE(GPIOC_QSPI_D1) | \ + PIN_MODE_ALTERNATE(GPIOC_DFSDM_DATIN5) |\ + PIN_MODE_ALTERNATE(GPIOC_WIFI_RX) | \ + PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ULPI_STP) | \ + PIN_OTYPE_PUSHPULL(GPIOC_RMII_MDC) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_A2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_DFSDM_DATIN1) |\ + PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_QSPI_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_QSPI_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_DFSDM_DATIN5) |\ + PIN_OTYPE_PUSHPULL(GPIOC_WIFI_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ULPI_STP) | \ + PIN_OSPEED_HIGH(GPIOC_RMII_MDC) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_A2) | \ + PIN_OSPEED_HIGH(GPIOC_DFSDM_DATIN1) | \ + PIN_OSPEED_HIGH(GPIOC_RMII_RXD0) | \ + PIN_OSPEED_HIGH(GPIOC_RMII_RXD1) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_D1) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_D0) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_D5) | \ + PIN_OSPEED_HIGH(GPIOC_QSPI_D0) | \ + PIN_OSPEED_HIGH(GPIOC_QSPI_D1) | \ + PIN_OSPEED_HIGH(GPIOC_DFSDM_DATIN5) | \ + PIN_OSPEED_HIGH(GPIOC_WIFI_RX) | \ + PIN_OSPEED_HIGH(GPIOC_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOC_OSC32_IN) | \ + PIN_OSPEED_VERYLOW(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_ULPI_STP) | \ + PIN_PUPDR_FLOATING(GPIOC_RMII_MDC) | \ + PIN_PUPDR_PULLUP(GPIOC_ARD_A2) | \ + PIN_PUPDR_FLOATING(GPIOC_DFSDM_DATIN1) |\ + PIN_PUPDR_FLOATING(GPIOC_RMII_RXD0) | \ + PIN_PUPDR_FLOATING(GPIOC_RMII_RXD1) | \ + PIN_PUPDR_PULLUP(GPIOC_ARD_D1) | \ + PIN_PUPDR_FLOATING(GPIOC_ARD_D0) | \ + PIN_PUPDR_FLOATING(GPIOC_ARD_D5) | \ + PIN_PUPDR_FLOATING(GPIOC_QSPI_D0) | \ + PIN_PUPDR_FLOATING(GPIOC_QSPI_D1) | \ + PIN_PUPDR_FLOATING(GPIOC_DFSDM_DATIN5) |\ + PIN_PUPDR_FLOATING(GPIOC_WIFI_RX) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_ULPI_STP) | \ + PIN_ODR_HIGH(GPIOC_RMII_MDC) | \ + PIN_ODR_HIGH(GPIOC_ARD_A2) | \ + PIN_ODR_HIGH(GPIOC_DFSDM_DATIN1) | \ + PIN_ODR_HIGH(GPIOC_RMII_RXD0) | \ + PIN_ODR_HIGH(GPIOC_RMII_RXD1) | \ + PIN_ODR_HIGH(GPIOC_ARD_D1) | \ + PIN_ODR_HIGH(GPIOC_ARD_D0) | \ + PIN_ODR_HIGH(GPIOC_ARD_D5) | \ + PIN_ODR_HIGH(GPIOC_QSPI_D0) | \ + PIN_ODR_HIGH(GPIOC_QSPI_D1) | \ + PIN_ODR_HIGH(GPIOC_DFSDM_DATIN5) | \ + PIN_ODR_HIGH(GPIOC_WIFI_RX) | \ + PIN_ODR_HIGH(GPIOC_PIN13) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ULPI_STP, 10U) | \ + PIN_AFIO_AF(GPIOC_RMII_MDC, 11U) | \ + PIN_AFIO_AF(GPIOC_ARD_A2, 0U) | \ + PIN_AFIO_AF(GPIOC_DFSDM_DATIN1, 3U) | \ + PIN_AFIO_AF(GPIOC_RMII_RXD0, 11U) | \ + PIN_AFIO_AF(GPIOC_RMII_RXD1, 11U) | \ + PIN_AFIO_AF(GPIOC_ARD_D1, 0U) | \ + PIN_AFIO_AF(GPIOC_ARD_D0, 0U)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_ARD_D5, 0U) | \ + PIN_AFIO_AF(GPIOC_QSPI_D0, 9U) | \ + PIN_AFIO_AF(GPIOC_QSPI_D1, 9U) | \ + PIN_AFIO_AF(GPIOC_DFSDM_DATIN5, 3U) | \ + PIN_AFIO_AF(GPIOC_WIFI_RX, 8U) | \ + PIN_AFIO_AF(GPIOC_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0U) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0U)) + +/* + * GPIOD setup: + * + * PD0 - FMC_D2 (alternate 12). + * PD1 - FMC_D3 (alternate 12). + * PD2 - WIFI_TX (alternate 8). + * PD3 - DFSDM_CKOUT (alternate 3). + * PD4 - OTG_HS_OVER_CURRENT (input floating). + * PD5 - RMII_RXER (alternate 11). + * PD6 - SD_CLK (alternate 11). + * PD7 - SD_CMD (alternate 11). + * PD8 - FMC_D13 (alternate 12). + * PD9 - FMC_D14 (alternate 12). + * PD10 - FMC_D15 (alternate 12). + * PD11 - SPDIF_I2S (alternate 10). + * PD12 - AUDIO_SCL LCD_SCL (alternate 4). + * PD13 - QSPI_D3 (alternate 9). + * PD14 - FMC_D0 (alternate 12). + * PD15 - FMC_D1 (alternate 12). + */ +#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(GPIOD_FMC_D2) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D3) | \ + PIN_MODE_ALTERNATE(GPIOD_WIFI_TX) | \ + PIN_MODE_ALTERNATE(GPIOD_DFSDM_CKOUT) |\ + PIN_MODE_INPUT(GPIOD_OTG_HS_OVER_CURRENT) |\ + PIN_MODE_ALTERNATE(GPIOD_RMII_RXER) | \ + PIN_MODE_ALTERNATE(GPIOD_SD_CLK) | \ + PIN_MODE_ALTERNATE(GPIOD_SD_CMD) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D13) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D14) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D15) | \ + PIN_MODE_ALTERNATE(GPIOD_SPDIF_I2S) | \ + PIN_MODE_ALTERNATE(GPIOD_AUDIO_SCL) | \ + PIN_MODE_ALTERNATE(GPIOD_QSPI_D3) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D0) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D1)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_FMC_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_WIFI_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_DFSDM_CKOUT) |\ + PIN_OTYPE_PUSHPULL(GPIOD_OTG_HS_OVER_CURRENT) |\ + PIN_OTYPE_PUSHPULL(GPIOD_RMII_RXER) | \ + PIN_OTYPE_PUSHPULL(GPIOD_SD_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOD_SD_CMD) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D15) | \ + PIN_OTYPE_PUSHPULL(GPIOD_SPDIF_I2S) | \ + PIN_OTYPE_PUSHPULL(GPIOD_AUDIO_SCL) | \ + PIN_OTYPE_PUSHPULL(GPIOD_QSPI_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D1)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_FMC_D2) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D3) | \ + PIN_OSPEED_HIGH(GPIOD_WIFI_TX) | \ + PIN_OSPEED_HIGH(GPIOD_DFSDM_CKOUT) | \ + PIN_OSPEED_HIGH(GPIOD_OTG_HS_OVER_CURRENT) |\ + PIN_OSPEED_HIGH(GPIOD_RMII_RXER) | \ + PIN_OSPEED_HIGH(GPIOD_SD_CLK) | \ + PIN_OSPEED_HIGH(GPIOD_SD_CMD) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D13) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D14) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D15) | \ + PIN_OSPEED_HIGH(GPIOD_SPDIF_I2S) | \ + PIN_OSPEED_HIGH(GPIOD_AUDIO_SCL) | \ + PIN_OSPEED_HIGH(GPIOD_QSPI_D3) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D0) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D1)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_FMC_D2) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D3) | \ + PIN_PUPDR_FLOATING(GPIOD_WIFI_TX) | \ + PIN_PUPDR_FLOATING(GPIOD_DFSDM_CKOUT) |\ + PIN_PUPDR_FLOATING(GPIOD_OTG_HS_OVER_CURRENT) |\ + PIN_PUPDR_FLOATING(GPIOD_RMII_RXER) | \ + PIN_PUPDR_FLOATING(GPIOD_SD_CLK) | \ + PIN_PUPDR_FLOATING(GPIOD_SD_CMD) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D13) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D14) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D15) | \ + PIN_PUPDR_FLOATING(GPIOD_SPDIF_I2S) | \ + PIN_PUPDR_FLOATING(GPIOD_AUDIO_SCL) | \ + PIN_PUPDR_FLOATING(GPIOD_QSPI_D3) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D0) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D1)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_FMC_D2) | \ + PIN_ODR_HIGH(GPIOD_FMC_D3) | \ + PIN_ODR_HIGH(GPIOD_WIFI_TX) | \ + PIN_ODR_HIGH(GPIOD_DFSDM_CKOUT) | \ + PIN_ODR_HIGH(GPIOD_OTG_HS_OVER_CURRENT) |\ + PIN_ODR_HIGH(GPIOD_RMII_RXER) | \ + PIN_ODR_HIGH(GPIOD_SD_CLK) | \ + PIN_ODR_HIGH(GPIOD_SD_CMD) | \ + PIN_ODR_HIGH(GPIOD_FMC_D13) | \ + PIN_ODR_HIGH(GPIOD_FMC_D14) | \ + PIN_ODR_HIGH(GPIOD_FMC_D15) | \ + PIN_ODR_HIGH(GPIOD_SPDIF_I2S) | \ + PIN_ODR_HIGH(GPIOD_AUDIO_SCL) | \ + PIN_ODR_HIGH(GPIOD_QSPI_D3) | \ + PIN_ODR_LOW(GPIOD_FMC_D0) | \ + PIN_ODR_LOW(GPIOD_FMC_D1)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_FMC_D2, 12U) | \ + PIN_AFIO_AF(GPIOD_FMC_D3, 12U) | \ + PIN_AFIO_AF(GPIOD_WIFI_TX, 8U) | \ + PIN_AFIO_AF(GPIOD_DFSDM_CKOUT, 3U) | \ + PIN_AFIO_AF(GPIOD_OTG_HS_OVER_CURRENT, 0U) |\ + PIN_AFIO_AF(GPIOD_RMII_RXER, 11U) | \ + PIN_AFIO_AF(GPIOD_SD_CLK, 11U) | \ + PIN_AFIO_AF(GPIOD_SD_CMD, 11U)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_FMC_D13, 12U) | \ + PIN_AFIO_AF(GPIOD_FMC_D14, 12U) | \ + PIN_AFIO_AF(GPIOD_FMC_D15, 12U) | \ + PIN_AFIO_AF(GPIOD_SPDIF_I2S, 10U) | \ + PIN_AFIO_AF(GPIOD_AUDIO_SCL, 4U) | \ + PIN_AFIO_AF(GPIOD_QSPI_D3, 9U) | \ + PIN_AFIO_AF(GPIOD_FMC_D0, 12U) | \ + PIN_AFIO_AF(GPIOD_FMC_D1, 12U)) + +/* + * GPIOE setup: + * + * PE0 - FMC_NBL0 (alternate 12). + * PE1 - FMC_NBL1 (alternate 12). + * PE2 - QSPI_D2 (alternate 9). + * PE3 - SAI1_SDB (alternate 6). + * PE4 - SAI1_FSA (alternate 6). + * PE5 - SAI1_SCKA (alternate 6). + * PE6 - SAI1_SDA (alternate 6). + * PE7 - FMC_D4 (alternate 12). + * PE8 - FMC_D5 (alternate 12). + * PE9 - FMC_D6 (alternate 12). + * PE10 - FMC_D7 (alternate 12). + * PE11 - FMC_D8 (alternate 12). + * PE12 - FMC_D9 (alternate 12). + * PE13 - FMC_D10 (alternate 12). + * PE14 - FMC_11 (alternate 12). + * PE15 - FMC_D12 (alternate 12). + */ +#define VAL_GPIOE_MODER (PIN_MODE_ALTERNATE(GPIOE_FMC_NBL0) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_NBL1) | \ + PIN_MODE_ALTERNATE(GPIOE_QSPI_D2) | \ + PIN_MODE_ALTERNATE(GPIOE_SAI1_SDB) | \ + PIN_MODE_ALTERNATE(GPIOE_SAI1_FSA) | \ + PIN_MODE_ALTERNATE(GPIOE_SAI1_SCKA) | \ + PIN_MODE_ALTERNATE(GPIOE_SAI1_SDA) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D4) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D5) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D6) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D7) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D8) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D9) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D10) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_11) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D12)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_FMC_NBL0) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_NBL1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_QSPI_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SAI1_SDB) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SAI1_FSA) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SAI1_SCKA) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SAI1_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D12)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_FMC_NBL0) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_NBL1) | \ + PIN_OSPEED_HIGH(GPIOE_QSPI_D2) | \ + PIN_OSPEED_HIGH(GPIOE_SAI1_SDB) | \ + PIN_OSPEED_HIGH(GPIOE_SAI1_FSA) | \ + PIN_OSPEED_HIGH(GPIOE_SAI1_SCKA) | \ + PIN_OSPEED_HIGH(GPIOE_SAI1_SDA) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D4) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D5) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D6) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D7) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D8) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D9) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D10) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_11) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D12)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_FMC_NBL0) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_NBL1) | \ + PIN_PUPDR_FLOATING(GPIOE_QSPI_D2) | \ + PIN_PUPDR_FLOATING(GPIOE_SAI1_SDB) | \ + PIN_PUPDR_FLOATING(GPIOE_SAI1_FSA) | \ + PIN_PUPDR_FLOATING(GPIOE_SAI1_SCKA) | \ + PIN_PUPDR_FLOATING(GPIOE_SAI1_SDA) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D4) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D5) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D6) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D7) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D8) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D9) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D10) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_11) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D12)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_FMC_NBL0) | \ + PIN_ODR_HIGH(GPIOE_FMC_NBL1) | \ + PIN_ODR_HIGH(GPIOE_QSPI_D2) | \ + PIN_ODR_HIGH(GPIOE_SAI1_SDB) | \ + PIN_ODR_HIGH(GPIOE_SAI1_FSA) | \ + PIN_ODR_HIGH(GPIOE_SAI1_SCKA) | \ + PIN_ODR_HIGH(GPIOE_SAI1_SDA) | \ + PIN_ODR_HIGH(GPIOE_FMC_D4) | \ + PIN_ODR_HIGH(GPIOE_FMC_D5) | \ + PIN_ODR_HIGH(GPIOE_FMC_D6) | \ + PIN_ODR_HIGH(GPIOE_FMC_D7) | \ + PIN_ODR_HIGH(GPIOE_FMC_D8) | \ + PIN_ODR_HIGH(GPIOE_FMC_D9) | \ + PIN_ODR_HIGH(GPIOE_FMC_D10) | \ + PIN_ODR_HIGH(GPIOE_FMC_11) | \ + PIN_ODR_HIGH(GPIOE_FMC_D12)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_FMC_NBL0, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_NBL1, 12U) | \ + PIN_AFIO_AF(GPIOE_QSPI_D2, 9U) | \ + PIN_AFIO_AF(GPIOE_SAI1_SDB, 6U) | \ + PIN_AFIO_AF(GPIOE_SAI1_FSA, 6U) | \ + PIN_AFIO_AF(GPIOE_SAI1_SCKA, 6U) | \ + PIN_AFIO_AF(GPIOE_SAI1_SDA, 6U) | \ + PIN_AFIO_AF(GPIOE_FMC_D4, 12U)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_FMC_D5, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D6, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D7, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D8, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D9, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D10, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_11, 12U) | \ + PIN_AFIO_AF(GPIOE_FMC_D12, 12U)) + +/* + * GPIOF setup: + * + * PF0 - FMC_A0 (alternate 12). + * PF1 - FMC_A1 (alternate 12). + * PF2 - FMC_A2 (alternate 12). + * PF3 - FMC_A3 (alternate 12). + * PF4 - FMC_A4 (alternate 12). + * PF5 - FMC_A5 (alternate 12). + * PF6 - ARD_D3 (input pullup). + * PF7 - ARD_D6 (input pullup). + * PF8 - ARD_A4 (input pullup). + * PF9 - ARD_A5 (input pullup). + * PF10 - ARD_A3 (input pullup). + * PF11 - FMC_SDNRAS (alternate 12). + * PF12 - FMC_A6 (alternate 12). + * PF13 - FMC_A7 (alternate 12). + * PF14 - FMC_A8 (alternate 12). + * PF15 - FMC_A9 (alternate 12). + */ +#define VAL_GPIOF_MODER (PIN_MODE_ALTERNATE(GPIOF_FMC_A0) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A1) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A2) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A3) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A4) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A5) | \ + PIN_MODE_INPUT(GPIOF_ARD_D3) | \ + PIN_MODE_INPUT(GPIOF_ARD_D6) | \ + PIN_MODE_INPUT(GPIOF_ARD_A4) | \ + PIN_MODE_INPUT(GPIOF_ARD_A5) | \ + PIN_MODE_INPUT(GPIOF_ARD_A3) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_SDNRAS) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A6) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A7) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A8) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A9)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_FMC_A0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_A4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_A5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_A3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_SDNRAS) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A9)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_FMC_A0) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A1) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A2) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A3) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A4) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A5) | \ + PIN_OSPEED_HIGH(GPIOF_ARD_D3) | \ + PIN_OSPEED_HIGH(GPIOF_ARD_D6) | \ + PIN_OSPEED_HIGH(GPIOF_ARD_A4) | \ + PIN_OSPEED_HIGH(GPIOF_ARD_A5) | \ + PIN_OSPEED_HIGH(GPIOF_ARD_A3) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_SDNRAS) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A6) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A7) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A8) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A9)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_FMC_A0) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A1) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A2) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A3) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A4) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A5) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D3) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D6) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_A4) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_A5) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_A3) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_SDNRAS) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A6) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A7) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A8) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A9)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_FMC_A0) | \ + PIN_ODR_HIGH(GPIOF_FMC_A1) | \ + PIN_ODR_HIGH(GPIOF_FMC_A2) | \ + PIN_ODR_HIGH(GPIOF_FMC_A3) | \ + PIN_ODR_HIGH(GPIOF_FMC_A4) | \ + PIN_ODR_HIGH(GPIOF_FMC_A5) | \ + PIN_ODR_HIGH(GPIOF_ARD_D3) | \ + PIN_ODR_HIGH(GPIOF_ARD_D6) | \ + PIN_ODR_HIGH(GPIOF_ARD_A4) | \ + PIN_ODR_HIGH(GPIOF_ARD_A5) | \ + PIN_ODR_HIGH(GPIOF_ARD_A3) | \ + PIN_ODR_HIGH(GPIOF_FMC_SDNRAS) | \ + PIN_ODR_HIGH(GPIOF_FMC_A6) | \ + PIN_ODR_HIGH(GPIOF_FMC_A7) | \ + PIN_ODR_HIGH(GPIOF_FMC_A8) | \ + PIN_ODR_HIGH(GPIOF_FMC_A9)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_FMC_A0, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A1, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A2, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A3, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A4, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A5, 12U) | \ + PIN_AFIO_AF(GPIOF_ARD_D3, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_D6, 0U)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_ARD_A4, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_A5, 0U) | \ + PIN_AFIO_AF(GPIOF_ARD_A3, 0U) | \ + PIN_AFIO_AF(GPIOF_FMC_SDNRAS, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A6, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A7, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A8, 12U) | \ + PIN_AFIO_AF(GPIOF_FMC_A9, 12U)) + +/* + * GPIOG setup: + * + * PG0 - FMC_A10 (alternate 12). + * PG1 - FMC_A11 (alternate 12). + * PG2 - FMC_A12 (alternate 12). + * PG3 - EXT_SCL (input pullup). + * PG4 - FMC_BA0 (alternate 12). + * PG5 - FMC_BA1 (alternate 12). + * PG6 - EXT_SDA (input pullup). + * PG7 - SAI1_MCLKA (alternate 6). + * PG8 - FMC_SDCLK (alternate 12). + * PG9 - SD_D0 (alternate 11). + * PG10 - SD_D1 (alternate 11). + * PG11 - RMII_TX_EN (alternate 11). + * PG12 - SPDIF_RX (alternate 7). + * PG13 - RMII_TXD0 (alternate 11). + * PG14 - RMII_TXD1 (alternate 11). + * PG15 - FMC_SDNCAS (alternate 12). + */ +#define VAL_GPIOG_MODER (PIN_MODE_ALTERNATE(GPIOG_FMC_A10) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_A11) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_A12) | \ + PIN_MODE_INPUT(GPIOG_EXT_SCL) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_BA0) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_BA1) | \ + PIN_MODE_INPUT(GPIOG_EXT_SDA) | \ + PIN_MODE_ALTERNATE(GPIOG_SAI1_MCLKA) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_SDCLK) | \ + PIN_MODE_ALTERNATE(GPIOG_SD_D0) | \ + PIN_MODE_ALTERNATE(GPIOG_SD_D1) | \ + PIN_MODE_ALTERNATE(GPIOG_RMII_TX_EN) | \ + PIN_MODE_ALTERNATE(GPIOG_SPDIF_RX) | \ + PIN_MODE_ALTERNATE(GPIOG_RMII_TXD0) | \ + PIN_MODE_ALTERNATE(GPIOG_RMII_TXD1) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_FMC_A10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_A11) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_A12) | \ + PIN_OTYPE_PUSHPULL(GPIOG_EXT_SCL) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_BA0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_BA1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_EXT_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOG_SAI1_MCLKA) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_SDCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOG_SD_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_SD_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_RMII_TX_EN) | \ + PIN_OTYPE_PUSHPULL(GPIOG_SPDIF_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOG_RMII_TXD0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_RMII_TXD1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_FMC_A10) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_A11) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_A12) | \ + PIN_OSPEED_HIGH(GPIOG_EXT_SCL) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_BA0) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_BA1) | \ + PIN_OSPEED_HIGH(GPIOG_EXT_SDA) | \ + PIN_OSPEED_HIGH(GPIOG_SAI1_MCLKA) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_SDCLK) | \ + PIN_OSPEED_HIGH(GPIOG_SD_D0) | \ + PIN_OSPEED_HIGH(GPIOG_SD_D1) | \ + PIN_OSPEED_HIGH(GPIOG_RMII_TX_EN) | \ + PIN_OSPEED_HIGH(GPIOG_SPDIF_RX) | \ + PIN_OSPEED_HIGH(GPIOG_RMII_TXD0) | \ + PIN_OSPEED_HIGH(GPIOG_RMII_TXD1) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_FMC_A10) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_A11) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_A12) | \ + PIN_PUPDR_PULLUP(GPIOG_EXT_SCL) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_BA0) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_BA1) | \ + PIN_PUPDR_PULLUP(GPIOG_EXT_SDA) | \ + PIN_PUPDR_PULLUP(GPIOG_SAI1_MCLKA) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_SDCLK) | \ + PIN_PUPDR_FLOATING(GPIOG_SD_D0) | \ + PIN_PUPDR_FLOATING(GPIOG_SD_D1) | \ + PIN_PUPDR_FLOATING(GPIOG_RMII_TX_EN) | \ + PIN_PUPDR_FLOATING(GPIOG_SPDIF_RX) | \ + PIN_PUPDR_FLOATING(GPIOG_RMII_TXD0) | \ + PIN_PUPDR_FLOATING(GPIOG_RMII_TXD1) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_FMC_A10) | \ + PIN_ODR_HIGH(GPIOG_FMC_A11) | \ + PIN_ODR_HIGH(GPIOG_FMC_A12) | \ + PIN_ODR_HIGH(GPIOG_EXT_SCL) | \ + PIN_ODR_HIGH(GPIOG_FMC_BA0) | \ + PIN_ODR_HIGH(GPIOG_FMC_BA1) | \ + PIN_ODR_HIGH(GPIOG_EXT_SDA) | \ + PIN_ODR_HIGH(GPIOG_SAI1_MCLKA) | \ + PIN_ODR_HIGH(GPIOG_FMC_SDCLK) | \ + PIN_ODR_HIGH(GPIOG_SD_D0) | \ + PIN_ODR_HIGH(GPIOG_SD_D1) | \ + PIN_ODR_HIGH(GPIOG_RMII_TX_EN) | \ + PIN_ODR_HIGH(GPIOG_SPDIF_RX) | \ + PIN_ODR_HIGH(GPIOG_RMII_TXD0) | \ + PIN_ODR_HIGH(GPIOG_RMII_TXD1) | \ + PIN_ODR_HIGH(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_FMC_A10, 12U) | \ + PIN_AFIO_AF(GPIOG_FMC_A11, 12U) | \ + PIN_AFIO_AF(GPIOG_FMC_A12, 12U) | \ + PIN_AFIO_AF(GPIOG_EXT_SCL, 0U) | \ + PIN_AFIO_AF(GPIOG_FMC_BA0, 12U) | \ + PIN_AFIO_AF(GPIOG_FMC_BA1, 12U) | \ + PIN_AFIO_AF(GPIOG_EXT_SDA, 0U) | \ + PIN_AFIO_AF(GPIOG_SAI1_MCLKA, 6U)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_FMC_SDCLK, 12U) | \ + PIN_AFIO_AF(GPIOG_SD_D0, 11U) | \ + PIN_AFIO_AF(GPIOG_SD_D1, 11U) | \ + PIN_AFIO_AF(GPIOG_RMII_TX_EN, 11U) | \ + PIN_AFIO_AF(GPIOG_SPDIF_RX, 7U) | \ + PIN_AFIO_AF(GPIOG_RMII_TXD0, 11U) | \ + PIN_AFIO_AF(GPIOG_RMII_TXD1, 11U) | \ + PIN_AFIO_AF(GPIOG_FMC_SDNCAS, 12U)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - FMC_SDCKE0 (alternate 12). + * PH3 - FMC_SDNE0 (alternate 12). + * PH4 - ULPI_NXT (alternate 10). + * PH5 - FMC_SDNWE (alternate 12). + * PH6 - ARD_D9 (input pullup). + * PH7 - EXT_RST (input floating). + * PH8 - FMC_D16 (alternate 12). + * PH9 - FMC_D17 (alternate 12). + * PH10 - FMC_D18 (alternate 12). + * PH11 - FMC_D19 (alternate 12). + * PH12 - FMC_D20 (alternate 12). + * PH13 - FMC_D21 (alternate 12). + * PH14 - FMC_D22 (alternate 12). + * PH15 - FMC_D23 (alternate 12). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_SDCKE0) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_SDNE0) | \ + PIN_MODE_ALTERNATE(GPIOH_ULPI_NXT) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_SDNWE) | \ + PIN_MODE_INPUT(GPIOH_ARD_D9) | \ + PIN_MODE_INPUT(GPIOH_EXT_RST) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_D16) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_D17) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_D18) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_D19) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_D20) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_D21) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_D22) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_D23)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_SDCKE0) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_SDNE0) | \ + PIN_OTYPE_PUSHPULL(GPIOH_ULPI_NXT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_SDNWE) | \ + PIN_OTYPE_PUSHPULL(GPIOH_ARD_D9) | \ + PIN_OTYPE_OPENDRAIN(GPIOH_EXT_RST) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_D16) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_D17) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_D18) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_D19) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_D20) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_D21) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_D22) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_D23)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ + PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_SDCKE0) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_SDNE0) | \ + PIN_OSPEED_HIGH(GPIOH_ULPI_NXT) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_SDNWE) | \ + PIN_OSPEED_HIGH(GPIOH_ARD_D9) | \ + PIN_OSPEED_HIGH(GPIOH_EXT_RST) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_D16) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_D17) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_D18) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_D19) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_D20) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_D21) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_D22) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_D23)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_SDCKE0) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_SDNE0) | \ + PIN_PUPDR_FLOATING(GPIOH_ULPI_NXT) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_SDNWE) | \ + PIN_PUPDR_PULLUP(GPIOH_ARD_D9) | \ + PIN_PUPDR_FLOATING(GPIOH_EXT_RST) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_D16) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_D17) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_D18) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_D19) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_D20) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_D21) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_D22) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_D23)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_FMC_SDCKE0) | \ + PIN_ODR_HIGH(GPIOH_FMC_SDNE0) | \ + PIN_ODR_HIGH(GPIOH_ULPI_NXT) | \ + PIN_ODR_HIGH(GPIOH_FMC_SDNWE) | \ + PIN_ODR_HIGH(GPIOH_ARD_D9) | \ + PIN_ODR_HIGH(GPIOH_EXT_RST) | \ + PIN_ODR_HIGH(GPIOH_FMC_D16) | \ + PIN_ODR_HIGH(GPIOH_FMC_D17) | \ + PIN_ODR_HIGH(GPIOH_FMC_D18) | \ + PIN_ODR_HIGH(GPIOH_FMC_D19) | \ + PIN_ODR_HIGH(GPIOH_FMC_D20) | \ + PIN_ODR_HIGH(GPIOH_FMC_D21) | \ + PIN_ODR_HIGH(GPIOH_FMC_D22) | \ + PIN_ODR_HIGH(GPIOH_FMC_D23)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0U) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0U) | \ + PIN_AFIO_AF(GPIOH_FMC_SDCKE0, 12U) | \ + PIN_AFIO_AF(GPIOH_FMC_SDNE0, 12U) | \ + PIN_AFIO_AF(GPIOH_ULPI_NXT, 10U) | \ + PIN_AFIO_AF(GPIOH_FMC_SDNWE, 12U) | \ + PIN_AFIO_AF(GPIOH_ARD_D9, 0U) | \ + PIN_AFIO_AF(GPIOH_EXT_RST, 0U)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_FMC_D16, 12U) | \ + PIN_AFIO_AF(GPIOH_FMC_D17, 12U) | \ + PIN_AFIO_AF(GPIOH_FMC_D18, 12U) | \ + PIN_AFIO_AF(GPIOH_FMC_D19, 12U) | \ + PIN_AFIO_AF(GPIOH_FMC_D20, 12U) | \ + PIN_AFIO_AF(GPIOH_FMC_D21, 12U) | \ + PIN_AFIO_AF(GPIOH_FMC_D22, 12U) | \ + PIN_AFIO_AF(GPIOH_FMC_D23, 12U)) + +/* + * GPIOI setup: + * + * PI0 - FMC_D24 (alternate 12). + * PI1 - FMC_D25 (alternate 12). + * PI2 - FMC_D26 (alternate 12). + * PI3 - FMC_D27 (alternate 12). + * PI4 - FMC_NBL2 (alternate 12). + * PI5 - FMC_NBL3 (alternate 12). + * PI6 - FMC_D28 (alternate 12). + * PI7 - FMC_D29 (alternate 12). + * PI8 - PIN8 (input pullup). + * PI9 - FMC_D30 (alternate 12). + * PI10 - FMC_D31 (alternate 12). + * PI11 - ULPI_DIR (alternate 10). + * PI12 - PIN12 (input pullup). + * PI13 - LCD_INT (alternate 14). + * PI14 - LCD_BL_CTRL (alternate 14). + * PI15 - SD_DETECT (input pullup). + */ +#define VAL_GPIOI_MODER (PIN_MODE_ALTERNATE(GPIOI_FMC_D24) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_D25) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_D26) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_D27) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_NBL2) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_NBL3) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_D28) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_D29) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_D30) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_D31) | \ + PIN_MODE_ALTERNATE(GPIOI_ULPI_DIR) | \ + PIN_MODE_INPUT(GPIOI_PIN12) | \ + PIN_MODE_ALTERNATE(GPIOI_LCD_INT) | \ + PIN_MODE_ALTERNATE(GPIOI_LCD_BL_CTRL) |\ + PIN_MODE_INPUT(GPIOI_SD_DETECT)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_FMC_D24) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_D25) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_D26) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_D27) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_NBL2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_NBL3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_D28) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_D29) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_D30) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_D31) | \ + PIN_OTYPE_PUSHPULL(GPIOI_ULPI_DIR) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOI_LCD_INT) | \ + PIN_OTYPE_PUSHPULL(GPIOI_LCD_BL_CTRL) |\ + PIN_OTYPE_PUSHPULL(GPIOI_SD_DETECT)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_HIGH(GPIOI_FMC_D24) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_D25) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_D26) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_D27) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_NBL2) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_NBL3) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_D28) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_D29) | \ + PIN_OSPEED_HIGH(GPIOI_PIN8) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_D30) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_D31) | \ + PIN_OSPEED_HIGH(GPIOI_ULPI_DIR) | \ + PIN_OSPEED_HIGH(GPIOI_PIN12) | \ + PIN_OSPEED_HIGH(GPIOI_LCD_INT) | \ + PIN_OSPEED_HIGH(GPIOI_LCD_BL_CTRL) | \ + PIN_OSPEED_HIGH(GPIOI_SD_DETECT)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_FMC_D24) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_D25) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_D26) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_D27) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_NBL2) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_NBL3) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_D28) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_D29) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_D30) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_D31) | \ + PIN_PUPDR_FLOATING(GPIOI_ULPI_DIR) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOI_LCD_INT) | \ + PIN_PUPDR_FLOATING(GPIOI_LCD_BL_CTRL) |\ + PIN_PUPDR_PULLUP(GPIOI_SD_DETECT)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_FMC_D24) | \ + PIN_ODR_HIGH(GPIOI_FMC_D25) | \ + PIN_ODR_HIGH(GPIOI_FMC_D26) | \ + PIN_ODR_HIGH(GPIOI_FMC_D27) | \ + PIN_ODR_HIGH(GPIOI_FMC_NBL2) | \ + PIN_ODR_HIGH(GPIOI_FMC_NBL3) | \ + PIN_ODR_HIGH(GPIOI_FMC_D28) | \ + PIN_ODR_HIGH(GPIOI_FMC_D29) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_FMC_D30) | \ + PIN_ODR_HIGH(GPIOI_FMC_D31) | \ + PIN_ODR_HIGH(GPIOI_ULPI_DIR) | \ + PIN_ODR_HIGH(GPIOI_PIN12) | \ + PIN_ODR_HIGH(GPIOI_LCD_INT) | \ + PIN_ODR_HIGH(GPIOI_LCD_BL_CTRL) | \ + PIN_ODR_HIGH(GPIOI_SD_DETECT)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_FMC_D24, 12U) | \ + PIN_AFIO_AF(GPIOI_FMC_D25, 12U) | \ + PIN_AFIO_AF(GPIOI_FMC_D26, 12U) | \ + PIN_AFIO_AF(GPIOI_FMC_D27, 12U) | \ + PIN_AFIO_AF(GPIOI_FMC_NBL2, 12U) | \ + PIN_AFIO_AF(GPIOI_FMC_NBL3, 12U) | \ + PIN_AFIO_AF(GPIOI_FMC_D28, 12U) | \ + PIN_AFIO_AF(GPIOI_FMC_D29, 12U)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOI_FMC_D30, 12U) | \ + PIN_AFIO_AF(GPIOI_FMC_D31, 12U) | \ + PIN_AFIO_AF(GPIOI_ULPI_DIR, 10U) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOI_LCD_INT, 14U) | \ + PIN_AFIO_AF(GPIOI_LCD_BL_CTRL, 14U) | \ + PIN_AFIO_AF(GPIOI_SD_DETECT, 0U)) + +/* + * GPIOJ setup: + * + * PJ0 - ARD_D4 (input floating). + * PJ1 - ARD_D2 (input floating). + * PJ2 - DSI_TE (alternate 13). + * PJ3 - ARD_D7 (input floating). + * PJ4 - ARD_D8 (input floating). + * PJ5 - LED2_GREEN (output pushpull maximum). + * PJ6 - PIN6 (input floating). + * PJ7 - PIN7 (input floating). + * PJ8 - PIN8 (input floating). + * PJ9 - PIN9 (input floating). + * PJ10 - PIN10 (input floating). + * PJ11 - PIN11 (input floating). + * PJ12 - AUDIO_INT (input floating). + * PJ13 - LED1_RED (output pushpull maximum). + * PJ14 - WIFI_RST (input floating). + * PJ15 - DSI_RESET (input floating). + */ +#define VAL_GPIOJ_MODER (PIN_MODE_INPUT(GPIOJ_ARD_D4) | \ + PIN_MODE_INPUT(GPIOJ_ARD_D2) | \ + PIN_MODE_ALTERNATE(GPIOJ_DSI_TE) | \ + PIN_MODE_INPUT(GPIOJ_ARD_D7) | \ + PIN_MODE_INPUT(GPIOJ_ARD_D8) | \ + PIN_MODE_OUTPUT(GPIOJ_LED2_GREEN) | \ + PIN_MODE_INPUT(GPIOJ_PIN6) | \ + PIN_MODE_INPUT(GPIOJ_PIN7) | \ + PIN_MODE_INPUT(GPIOJ_PIN8) | \ + PIN_MODE_INPUT(GPIOJ_PIN9) | \ + PIN_MODE_INPUT(GPIOJ_PIN10) | \ + PIN_MODE_INPUT(GPIOJ_PIN11) | \ + PIN_MODE_INPUT(GPIOJ_AUDIO_INT) | \ + PIN_MODE_OUTPUT(GPIOJ_LED1_RED) | \ + PIN_MODE_INPUT(GPIOJ_WIFI_RST) | \ + PIN_MODE_INPUT(GPIOJ_DSI_RESET)) +#define VAL_GPIOJ_OTYPER (PIN_OTYPE_PUSHPULL(GPIOJ_ARD_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_ARD_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_DSI_TE) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_ARD_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_ARD_D8) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_LED2_GREEN) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_AUDIO_INT) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_LED1_RED) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_WIFI_RST) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_DSI_RESET)) +#define VAL_GPIOJ_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOJ_ARD_D4) | \ + PIN_OSPEED_VERYLOW(GPIOJ_ARD_D2) | \ + PIN_OSPEED_VERYLOW(GPIOJ_DSI_TE) | \ + PIN_OSPEED_VERYLOW(GPIOJ_ARD_D7) | \ + PIN_OSPEED_VERYLOW(GPIOJ_ARD_D8) | \ + PIN_OSPEED_HIGH(GPIOJ_LED2_GREEN) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOJ_AUDIO_INT) | \ + PIN_OSPEED_HIGH(GPIOJ_LED1_RED) | \ + PIN_OSPEED_VERYLOW(GPIOJ_WIFI_RST) | \ + PIN_OSPEED_VERYLOW(GPIOJ_DSI_RESET)) +#define VAL_GPIOJ_PUPDR (PIN_PUPDR_FLOATING(GPIOJ_ARD_D4) | \ + PIN_PUPDR_FLOATING(GPIOJ_ARD_D2) | \ + PIN_PUPDR_FLOATING(GPIOJ_DSI_TE) | \ + PIN_PUPDR_FLOATING(GPIOJ_ARD_D7) | \ + PIN_PUPDR_FLOATING(GPIOJ_ARD_D8) | \ + PIN_PUPDR_FLOATING(GPIOJ_LED2_GREEN) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOJ_AUDIO_INT) | \ + PIN_PUPDR_FLOATING(GPIOJ_LED1_RED) | \ + PIN_PUPDR_FLOATING(GPIOJ_WIFI_RST) | \ + PIN_PUPDR_FLOATING(GPIOJ_DSI_RESET)) +#define VAL_GPIOJ_ODR (PIN_ODR_HIGH(GPIOJ_ARD_D4) | \ + PIN_ODR_HIGH(GPIOJ_ARD_D2) | \ + PIN_ODR_HIGH(GPIOJ_DSI_TE) | \ + PIN_ODR_HIGH(GPIOJ_ARD_D7) | \ + PIN_ODR_HIGH(GPIOJ_ARD_D8) | \ + PIN_ODR_LOW(GPIOJ_LED2_GREEN) | \ + PIN_ODR_HIGH(GPIOJ_PIN6) | \ + PIN_ODR_HIGH(GPIOJ_PIN7) | \ + PIN_ODR_HIGH(GPIOJ_PIN8) | \ + PIN_ODR_HIGH(GPIOJ_PIN9) | \ + PIN_ODR_HIGH(GPIOJ_PIN10) | \ + PIN_ODR_HIGH(GPIOJ_PIN11) | \ + PIN_ODR_HIGH(GPIOJ_AUDIO_INT) | \ + PIN_ODR_LOW(GPIOJ_LED1_RED) | \ + PIN_ODR_HIGH(GPIOJ_WIFI_RST) | \ + PIN_ODR_HIGH(GPIOJ_DSI_RESET)) +#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(GPIOJ_ARD_D4, 0U) | \ + PIN_AFIO_AF(GPIOJ_ARD_D2, 0U) | \ + PIN_AFIO_AF(GPIOJ_DSI_TE, 13U) | \ + PIN_AFIO_AF(GPIOJ_ARD_D7, 0U) | \ + PIN_AFIO_AF(GPIOJ_ARD_D8, 0U) | \ + PIN_AFIO_AF(GPIOJ_LED2_GREEN, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN7, 0U)) +#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(GPIOJ_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOJ_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOJ_AUDIO_INT, 0U) | \ + PIN_AFIO_AF(GPIOJ_LED1_RED, 0U) | \ + PIN_AFIO_AF(GPIOJ_WIFI_RST, 0U) | \ + PIN_AFIO_AF(GPIOJ_DSI_RESET, 0U)) + +/* + * GPIOK setup: + * + * PK0 - PIN0 (input floating). + * PK1 - PIN1 (input floating). + * PK2 - PIN2 (input floating). + * PK3 - PIN3 (input floating). + * PK4 - PIN4 (input floating). + * PK5 - PIN5 (input floating). + * PK6 - PIN6 (input floating). + * PK7 - PIN7 (input floating). + * PK8 - PIN8 (input floating). + * PK9 - PIN9 (input floating). + * PK10 - PIN10 (input floating). + * PK11 - PIN11 (input floating). + * PK12 - PIN12 (input floating). + * PK13 - PIN13 (input floating). + * PK14 - PIN14 (input floating). + * PK15 - PIN15 (input floating). + */ +#define VAL_GPIOK_MODER (PIN_MODE_INPUT(GPIOK_PIN0) | \ + PIN_MODE_INPUT(GPIOK_PIN1) | \ + PIN_MODE_INPUT(GPIOK_PIN2) | \ + PIN_MODE_INPUT(GPIOK_PIN3) | \ + PIN_MODE_INPUT(GPIOK_PIN4) | \ + PIN_MODE_INPUT(GPIOK_PIN5) | \ + PIN_MODE_INPUT(GPIOK_PIN6) | \ + PIN_MODE_INPUT(GPIOK_PIN7) | \ + PIN_MODE_INPUT(GPIOK_PIN8) | \ + PIN_MODE_INPUT(GPIOK_PIN9) | \ + PIN_MODE_INPUT(GPIOK_PIN10) | \ + PIN_MODE_INPUT(GPIOK_PIN11) | \ + PIN_MODE_INPUT(GPIOK_PIN12) | \ + PIN_MODE_INPUT(GPIOK_PIN13) | \ + PIN_MODE_INPUT(GPIOK_PIN14) | \ + PIN_MODE_INPUT(GPIOK_PIN15)) +#define VAL_GPIOK_OTYPER (PIN_OTYPE_PUSHPULL(GPIOK_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN15)) +#define VAL_GPIOK_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOK_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN15)) +#define VAL_GPIOK_PUPDR (PIN_PUPDR_FLOATING(GPIOK_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN15)) +#define VAL_GPIOK_ODR (PIN_ODR_HIGH(GPIOK_PIN0) | \ + PIN_ODR_HIGH(GPIOK_PIN1) | \ + PIN_ODR_HIGH(GPIOK_PIN2) | \ + PIN_ODR_HIGH(GPIOK_PIN3) | \ + PIN_ODR_HIGH(GPIOK_PIN4) | \ + PIN_ODR_HIGH(GPIOK_PIN5) | \ + PIN_ODR_HIGH(GPIOK_PIN6) | \ + PIN_ODR_HIGH(GPIOK_PIN7) | \ + PIN_ODR_HIGH(GPIOK_PIN8) | \ + PIN_ODR_HIGH(GPIOK_PIN9) | \ + PIN_ODR_HIGH(GPIOK_PIN10) | \ + PIN_ODR_HIGH(GPIOK_PIN11) | \ + PIN_ODR_HIGH(GPIOK_PIN12) | \ + PIN_ODR_HIGH(GPIOK_PIN13) | \ + PIN_ODR_HIGH(GPIOK_PIN14) | \ + PIN_ODR_HIGH(GPIOK_PIN15)) +#define VAL_GPIOK_AFRL (PIN_AFIO_AF(GPIOK_PIN0, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN1, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN2, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN3, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN4, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN5, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN6, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN7, 0U)) +#define VAL_GPIOK_AFRH (PIN_AFIO_AF(GPIOK_PIN8, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN9, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN10, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN11, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN12, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN13, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN14, 0U) | \ + PIN_AFIO_AF(GPIOK_PIN15, 0U)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* BOARD_H */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/common/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/common/CMakeLists.txt new file mode 100644 index 00000000..7c21ff9b --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/common/CMakeLists.txt @@ -0,0 +1,13 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c") +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_ConfigurationManager.cpp") + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") + +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/common/Device_BlockStorage-DEBUG.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 00000000..3695ffd0 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,106 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 32kB blocks +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 0 }, // 08000000 nanoBooter + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + { BlockRange_BLOCKTYPE_CONFIG , 1, 1 }, // 08008000 configuration block + /////////////////////////////////////////////////////////////////////////////////////// + + { BlockRange_BLOCKTYPE_CODE , 2, 3 } // 08010000 nanoCLR +}; + +//128kB block +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 08020000 nanoCLR +}; + +// 256kB blocks +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 1 }, // 08040000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 2, 6 } // 080C0000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x8000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 1, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08040000, // start address for block region + 7, // total number of blocks in this region + 0x40000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), // STM32 flash memory is XIP + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/common/Device_BlockStorage.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/common/Device_BlockStorage.c new file mode 100644 index 00000000..d5aa4657 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/common/Device_BlockStorage.c @@ -0,0 +1,106 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 32kB blocks +const BlockRange BlockRange1[] = +{ + { BlockRange_BLOCKTYPE_BOOTSTRAP , 0, 0 }, // 0x08000000 nanoBooter + + /////////////////////////////////////////////////////////////////////////////////////// + // because this target is using a configuration block need to add the + // configuration manager files to the CMake and call ConfigurationManager_Initialize() + // in nanoBooter so the configuration can be managed when in booter mode + /////////////////////////////////////////////////////////////////////////////////////// + { BlockRange_BLOCKTYPE_CONFIG , 1, 1 }, // 0x08008000 configuration block + /////////////////////////////////////////////////////////////////////////////////////// + + { BlockRange_BLOCKTYPE_CODE , 2, 3 } // 0x08010000 nanoCLR +}; + +//128kB block +const BlockRange BlockRange2[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 } // 0x08020000 nanoCLR +}; + +// 256kB blocks +const BlockRange BlockRange3[] = +{ + { BlockRange_BLOCKTYPE_CODE , 0, 0 }, // 08040000 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT, 1, 6 } // 08080000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x08000000, // start address for block region + 4, // total number of blocks in this region + 0x8000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + { + (0), // no attributes for this region + 0x08020000, // start address for block region + 1, // total number of blocks in this region + 0x20000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + { + (0), // no attributes for this region + 0x08040000, // start address for block region + 7, // total number of blocks in this region + 0x40000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + }, + +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), // STM32 flash memory is XIP + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/common/serialcfg.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/common/serialcfg.h new file mode 100644 index 00000000..cbe6b254 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/common/serialcfg.h @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef SERIALCFG_H +#define SERIALCFG_H + +// define which serial driver the Wire Protocol will be using +#define SERIAL_DRIVER SD1 + +#endif /* SERIALCFG_H */ + +/** @} */ + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/common/targetHAL_ConfigurationManager.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/common/targetHAL_ConfigurationManager.cpp new file mode 100644 index 00000000..178f6aa7 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/common/targetHAL_ConfigurationManager.cpp @@ -0,0 +1,35 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include + +// Default initialisation for Network interface config blocks +// strong implementation replacing ChibiOS 'weak' one +bool InitialiseNetworkDefaultConfig(HAL_Configuration_NetworkInterface * pconfig, uint32_t configurationIndex) +{ + (void)configurationIndex; + + // make sure the config block marker is set + memcpy(pconfig->Marker, c_MARKER_CONFIGURATION_NETWORK_V1, sizeof(c_MARKER_CONFIGURATION_NETWORK_V1)); + + pconfig->InterfaceType = NetworkInterfaceType_Ethernet; + pconfig->StartupAddressMode = AddressMode_DHCP; + pconfig->AutomaticDNS = 1; + pconfig->SpecificConfigId = 0; + + // set MAC address with ST provided MAC for development boards + // 00:80:E1:01:35:D1 + pconfig->MacAddress[0] = 0x00; + pconfig->MacAddress[1] = 0x80; + pconfig->MacAddress[2] = 0xE1; + pconfig->MacAddress[3] = 0x01; + pconfig->MacAddress[4] = 0x35; + pconfig->MacAddress[5] = 0xD1; + + return true; +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/ffconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/ffconf.h new file mode 100644 index 00000000..85b623af --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/ffconf.h @@ -0,0 +1,272 @@ +/* CHIBIOS FIX */ +#include "ch.h" + +/*---------------------------------------------------------------------------/ +/ FatFs - Configuration file +/---------------------------------------------------------------------------*/ + +#define FFCONF_DEF 87030 /* Revision ID */ + +/*---------------------------------------------------------------------------/ +/ Function Configurations +/---------------------------------------------------------------------------*/ + +#define FF_FS_READONLY 0 +/* This option switches read-only configuration. (0:Read/Write or 1:Read-only) +/ Read-only configuration removes writing API functions, f_write(), f_sync(), +/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree() +/ and optional writing functions as well. */ + + +#define FF_FS_MINIMIZE 0 +/* This option defines minimization level to remove some basic API functions. +/ +/ 0: All basic functions are enabled. +/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename() +/ are removed. +/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1. +/ 3: f_lseek() function is removed in addition to 2. */ + + +#define FF_USE_STRFUNC 1 +/* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf(). +/ +/ 0: Disable string functions. +/ 1: Enable without LF-CRLF conversion. +/ 2: Enable with LF-CRLF conversion. */ + + +#define FF_USE_FIND 1 +/* This option switches filtered directory read functions, f_findfirst() and +/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */ + + +#define FF_USE_MKFS 0 +/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */ + + +#define FF_USE_FASTSEEK 0 +/* This option switches fast seek function. (0:Disable or 1:Enable) */ + + +#define FF_USE_EXPAND 0 +/* This option switches f_expand function. (0:Disable or 1:Enable) */ + + +#define FF_USE_CHMOD 0 +/* This option switches attribute manipulation functions, f_chmod() and f_utime(). +/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */ + + +#define FF_USE_LABEL 1 +/* This option switches volume label functions, f_getlabel() and f_setlabel(). +/ (0:Disable or 1:Enable) */ + + +#define FF_USE_FORWARD 0 +/* This option switches f_forward() function. (0:Disable or 1:Enable) */ + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/---------------------------------------------------------------------------*/ + +#define FF_CODE_PAGE 850 +/* This option specifies the OEM code page to be used on the target system. +/ Incorrect code page setting can cause a file open failure. +/ +/ 437 - U.S. +/ 720 - Arabic +/ 737 - Greek +/ 771 - KBL +/ 775 - Baltic +/ 850 - Latin 1 +/ 852 - Latin 2 +/ 855 - Cyrillic +/ 857 - Turkish +/ 860 - Portuguese +/ 861 - Icelandic +/ 862 - Hebrew +/ 863 - Canadian French +/ 864 - Arabic +/ 865 - Nordic +/ 866 - Russian +/ 869 - Greek 2 +/ 932 - Japanese (DBCS) +/ 936 - Simplified Chinese (DBCS) +/ 949 - Korean (DBCS) +/ 950 - Traditional Chinese (DBCS) +/ 0 - Include all code pages above and configured by f_setcp() +*/ + + +#define FF_USE_LFN 3 +#define FF_MAX_LFN 255 +/* The FF_USE_LFN switches the support for LFN (long file name). +/ +/ 0: Disable LFN. FF_MAX_LFN has no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ To enable the LFN, Unicode handling functions (option/unicode.c) must be added +/ to the project. The working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and +/ additional 608 bytes at exFAT enabled. FF_MAX_LFN can be in range from 12 to 255. +/ It should be set 255 to support full featured LFN operations. +/ When use stack for the working buffer, take care on stack overflow. When use heap +/ memory for the working buffer, memory management functions, ff_memalloc() and +/ ff_memfree(), must be added to the project. */ + + +#define FF_LFN_UNICODE 0 +/* This option switches character encoding on the API, 0:ANSI/OEM or 1:UTF-16, +/ when LFN is enabled. Also behavior of string I/O functions will be affected by +/ this option. When LFN is not enabled, this option has no effect. +*/ + + +#define FF_STRF_ENCODE 3 +/* When FF_LFN_UNICODE = 1 with LFN enabled, string I/O functions, f_gets(), +/ f_putc(), f_puts and f_printf() convert the character encoding in it. +/ This option selects assumption of character encoding ON THE FILE to be +/ read/written via those functions. +/ +/ 0: ANSI/OEM +/ 1: UTF-16LE +/ 2: UTF-16BE +/ 3: UTF-8 +*/ + + +#define FF_FS_RPATH 2 +/* This option configures support for relative path. +/ +/ 0: Disable relative path and remove related functions. +/ 1: Enable relative path. f_chdir() and f_chdrive() are available. +/ 2: f_getcwd() function is available in addition to 1. +*/ + + +/*---------------------------------------------------------------------------/ +/ Drive/Volume Configurations +/---------------------------------------------------------------------------*/ + +#define FF_VOLUMES 3 +/* Number of volumes (logical drives) to be used. (1-10) */ + + +#define FF_STR_VOLUME_ID 1 +#define FF_VOLUME_STRS "D","E","F" +/* FF_STR_VOLUME_ID switches string support for volume ID. +/ When FF_STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive +/ number in the path name. FF_VOLUME_STRS defines the drive ID strings for each +/ logical drives. Number of items must be equal to FF_VOLUMES. Valid characters for +/ the drive ID strings are: A-Z and 0-9. */ + + +#define FF_MULTI_PARTITION 0 +/* This option switches support for multiple volumes on the physical drive. +/ By default (0), each logical drive number is bound to the same physical drive +/ number and only an FAT volume found on the physical drive will be mounted. +/ When this function is enabled (1), each logical drive number can be bound to +/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk() +/ funciton will be available. */ + + +#define FF_MIN_SS 512 +#define FF_MAX_SS 512 +/* This set of options configures the range of sector size to be supported. (512, +/ 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and +/ harddisk. But a larger value may be required for on-board flash memory and some +/ type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured +/ for variable sector size mode and disk_ioctl() function needs to implement +/ GET_SECTOR_SIZE command. */ + + +#define FF_USE_TRIM 0 +/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable) +/ To enable Trim function, also CTRL_TRIM command should be implemented to the +/ disk_ioctl() function. */ + + +#define FF_FS_NOFSINFO 0 +/* If you need to know correct free space on the FAT32 volume, set bit 0 of this +/ option, and f_getfree() function at first time after volume mount will force +/ a full FAT scan. Bit 1 controls the use of last allocated cluster number. +/ +/ bit0=0: Use free cluster count in the FSINFO if available. +/ bit0=1: Do not trust free cluster count in the FSINFO. +/ bit1=0: Use last allocated cluster number in the FSINFO if available. +/ bit1=1: Do not trust last allocated cluster number in the FSINFO. +*/ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/---------------------------------------------------------------------------*/ + +#define FF_FS_TINY 0 +/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny) +/ At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes. +/ Instead of private sector buffer eliminated from the file object, common sector +/ buffer in the filesystem object (FATFS) is used for the file data transfer. */ + + +#define FF_FS_EXFAT 0 +/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable) +/ When enable exFAT, also LFN needs to be enabled. +/ Note that enabling exFAT discards ANSI C (C89) compatibility. */ + + +#define FF_FS_NORTC 1 +#define FF_NORTC_MON 8 +#define FF_NORTC_MDAY 1 +#define FF_NORTC_YEAR 2018 +/* The option FF_FS_NORTC switches timestamp functiton. If the system does not have +/ any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable +/ the timestamp function. All objects modified by FatFs will have a fixed timestamp +/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time. +/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be +/ added to the project to read current time form real-time clock. FF_NORTC_MON, +/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect. +/ These options have no effect at read-only configuration (FF_FS_READONLY = 1). */ + + +#define FF_FS_LOCK 0 +/* The option FF_FS_LOCK switches file lock function to control duplicated file open +/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY +/ is 1. +/ +/ 0: Disable file lock function. To avoid volume corruption, application program +/ should avoid illegal open, remove and rename to the open objects. +/ >0: Enable file lock function. The value defines how many files/sub-directories +/ can be opened simultaneously under file lock control. Note that the file +/ lock control is independent of re-entrancy. */ + + +#define FF_FS_REENTRANT 1 +#define FF_FS_TIMEOUT TIME_MS2I(1000) +#define FF_SYNC_t semaphore_t* +/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs +/ module itself. Note that regardless of this option, file access to different +/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs() +/ and f_fdisk() function, are always not re-entrant. Only file/directory access +/ to the same volume is under control of this function. +/ +/ 0: Disable re-entrancy. FF_FS_TIMEOUT and FF_SYNC_t have no effect. +/ 1: Enable re-entrancy. Also user provided synchronization handlers, +/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj() +/ function, must be added to the project. Samples are available in +/ option/syscall.c. +/ +/ The FF_FS_TIMEOUT defines timeout period in unit of time tick. +/ The FF_SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*, +/ SemaphoreHandle_t and etc. A header file for O/S definitions needs to be +/ included somewhere in the scope of ff.h. */ + +/* #include // O/S definitions */ + + + +/*--- End of configuration options ---*/ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/lwipopts.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/lwipopts.h new file mode 100644 index 00000000..e3e393c3 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/lwipopts.h @@ -0,0 +1,2167 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2001-2004 Swedish Institute of Computer Science, All Rights Reserved +// See LICENSE file in the project root for full license information. +// +/** + * @file + * + * lwIP Options Configuration + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ +#ifndef __LWIPOPT_H__ +#define __LWIPOPT_H__ + + +#define _REENT_ONLY +#define set_errno(err) +#include +#include +#include + +/* + ----------------------------------------------- + ---------- Platform specific locking ---------- + ----------------------------------------------- +*/ + +/** + * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain + * critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#ifndef SYS_LIGHTWEIGHT_PROT +#define SYS_LIGHTWEIGHT_PROT 1 +#endif + +/** + * NO_SYS==1: Provides VERY minimal functionality. Otherwise, + * use lwIP facilities. + */ +#ifndef NO_SYS +#define NO_SYS 0 +#endif + +/** + * NO_SYS_NO_TIMERS==1: Drop support for sys_timeout when NO_SYS==1 + * Mainly for compatibility to old versions. + */ +#ifndef NO_SYS_NO_TIMERS +#define NO_SYS_NO_TIMERS 0 +#endif + +// empty on purpose +#define LWIP_TCPIP_THREAD_ALIVE() + +/** + * MEMCPY: override this if you have a faster implementation at hand than the + * one included in your C library + */ +#ifndef MEMCPY +#define MEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/** + * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a + * call to memcpy() if the length is known at compile time and is small. + */ +#ifndef SMEMCPY +#define SMEMCPY(dst,src,len) memcpy(dst,src,len) +#endif + +/* + ------------------------------------ + ---------- Memory options ---------- + ------------------------------------ +*/ +/** + * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library + * instead of the lwip internal allocator. Can save code size if you + * already use it. + */ +#ifndef MEM_LIBC_MALLOC +#define MEM_LIBC_MALLOC 1 +#endif + +/** +* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator. +* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution +* speed and usage from interrupts! +*/ +#ifndef MEMP_MEM_MALLOC +#define MEMP_MEM_MALLOC 1 +#endif + +/** + * MEM_ALIGNMENT: should be set to the alignment of the CPU + * 4 byte alignment -> #define MEM_ALIGNMENT 4 + * 2 byte alignment -> #define MEM_ALIGNMENT 2 + */ +#ifndef MEM_ALIGNMENT +#define MEM_ALIGNMENT 4 +#endif + +/** + * MEM_SIZE: the size of the heap memory. If the application will send + * a lot of data that needs to be copied, this should be set high. + */ +#ifndef MEM_SIZE +#define MEM_SIZE (16 * 1024) +#endif + +/** + * MEMP_SEPARATE_POOLS: if defined to 1, each pool is placed in its own array. + * This can be used to individually change the location of each pool. + * Default is one big array for all pools + */ +#ifndef MEMP_SEPARATE_POOLS +#define MEMP_SEPARATE_POOLS 0 +#endif + +/** + * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable + * amount of bytes before and after each memp element in every pool and fills + * it with a prominent default value. + * MEMP_OVERFLOW_CHECK == 0 no checking + * MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed + * MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time + * memp_malloc() or memp_free() is called (useful but slow!) + */ +#ifndef MEMP_OVERFLOW_CHECK +#define MEMP_OVERFLOW_CHECK 0 +#endif + +/** + * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make + * sure that there are no cycles in the linked lists. + */ +#ifndef MEMP_SANITY_CHECK +#define MEMP_SANITY_CHECK 0 +#endif + +/** + * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set + * of memory pools of various sizes. When mem_malloc is called, an element of + * the smallest pool that can provide the length needed is returned. + * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled. + */ +#ifndef MEM_USE_POOLS +#define MEM_USE_POOLS 0 +#endif + +/** + * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next + * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more + * reliable. */ +#ifndef MEM_USE_POOLS_TRY_BIGGER_POOL +#define MEM_USE_POOLS_TRY_BIGGER_POOL 0 +#endif + +/** + * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h + * that defines additional pools beyond the "standard" ones required + * by lwIP. If you set this to 1, you must have lwippools.h in your + * inlude path somewhere. + */ +#ifndef MEMP_USE_CUSTOM_POOLS +#define MEMP_USE_CUSTOM_POOLS 0 +#endif + +/** + * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from + * interrupt context (or another context that doesn't allow waiting for a + * semaphore). + * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT, + * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs + * with each loop so that mem_free can run. + * + * ATTENTION: As you can see from the above description, this leads to dis-/ + * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc + * can need longer. + * + * If you don't want that, at least for NO_SYS=0, you can still use the following + * functions to enqueue a deallocation call which then runs in the tcpip_thread + * context: + * - pbuf_free_callback(p); + * - mem_free_callback(m); + */ +#ifndef LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT +#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0 +#endif + +/* + --------------------------------------- + ---------- IPv6 options --------------- + --------------------------------------- +*/ +/** + * LWIP_IPV6==1: Enable IPv6 + */ +#define LWIP_IPV6 0 + +/* + ------------------------------------------------ + ---------- Internal Memory Pool Sizes ---------- + ------------------------------------------------ +*/ +/** + * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF). + * If the application sends a lot of data out of ROM (or other static memory), + * this should be set high. + */ +#ifndef MEMP_NUM_PBUF +#define MEMP_NUM_PBUF 16 +#endif + +/** + * MEMP_NUM_RAW_PCB: Number of raw connection PCBs + * (requires the LWIP_RAW option) + */ +#ifndef MEMP_NUM_RAW_PCB +#define MEMP_NUM_RAW_PCB 4 +#endif + +/** + * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + * per active UDP "connection". + * (requires the LWIP_UDP option) + */ +#ifndef MEMP_NUM_UDP_PCB +#define MEMP_NUM_UDP_PCB 4 +#endif + +/** + * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB +#define MEMP_NUM_TCP_PCB 5 +#endif + +/** + * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_PCB_LISTEN +#define MEMP_NUM_TCP_PCB_LISTEN 8 +#endif + +/** + * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments. + * (requires the LWIP_TCP option) + */ +#ifndef MEMP_NUM_TCP_SEG +#define MEMP_NUM_TCP_SEG 16 +#endif + +/** + * MEMP_NUM_REASSDATA: the number of IP packets simultaneously queued for + * reassembly (whole packets, not fragments!) + */ +#ifndef MEMP_NUM_REASSDATA +#define MEMP_NUM_REASSDATA 5 +#endif + +/** + * MEMP_NUM_FRAG_PBUF: the number of IP fragments simultaneously sent + * (fragments, not whole packets!). + * This is only used with IP_FRAG_USES_STATIC_BUF==0 and + * LWIP_NETIF_TX_SINGLE_PBUF==0 and only has to be > 1 with DMA-enabled MACs + * where the packet is not yet sent when netif->output returns. + */ +#ifndef MEMP_NUM_FRAG_PBUF +#define MEMP_NUM_FRAG_PBUF 15 +#endif + +/** + * MEMP_NUM_ARP_QUEUE: the number of simulateously queued outgoing + * packets (pbufs) that are waiting for an ARP request (to resolve + * their destination address) to finish. + * (requires the ARP_QUEUEING option) + */ +#ifndef MEMP_NUM_ARP_QUEUE +#define MEMP_NUM_ARP_QUEUE 30 +#endif + +/** + * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces + * can be members et the same time (one per netif - allsystems group -, plus one + * per netif membership). + * (requires the LWIP_IGMP option) + */ +#ifndef MEMP_NUM_IGMP_GROUP +#define MEMP_NUM_IGMP_GROUP 8 +#endif + +/** + * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts. + * (requires NO_SYS==0) + * The default number of timeouts is calculated here for all enabled modules. + * The formula expects settings to be either '0' or '1'. + */ +#ifndef MEMP_NUM_SYS_TIMEOUT +#define MEMP_NUM_SYS_TIMEOUT (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + PPP_SUPPORT + (LWIP_IPV6 ? (1 + LWIP_IPV6_REASS + LWIP_IPV6_MLD) : 0)) +#endif + +/** + * MEMP_NUM_NETBUF: the number of struct netbufs. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETBUF +#define MEMP_NUM_NETBUF 2 +#endif + +/** + * MEMP_NUM_NETCONN: the number of struct netconns. + * (only needed if you use the sequential API, like api_lib.c) + */ +#ifndef MEMP_NUM_NETCONN +#define MEMP_NUM_NETCONN 4 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used + * for callback/timeout API communication. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_API +#define MEMP_NUM_TCPIP_MSG_API 8 +#endif + +/** + * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used + * for incoming packets. + * (only needed if you use tcpip.c) + */ +#ifndef MEMP_NUM_TCPIP_MSG_INPKT +#define MEMP_NUM_TCPIP_MSG_INPKT 8 +#endif + +/** + * MEMP_NUM_SNMP_NODE: the number of leafs in the SNMP tree. + */ +#ifndef MEMP_NUM_SNMP_NODE +#define MEMP_NUM_SNMP_NODE 50 +#endif + +/** + * MEMP_NUM_SNMP_ROOTNODE: the number of branches in the SNMP tree. + * Every branch has one leaf (MEMP_NUM_SNMP_NODE) at least! + */ +#ifndef MEMP_NUM_SNMP_ROOTNODE +#define MEMP_NUM_SNMP_ROOTNODE 30 +#endif + +/** + * MEMP_NUM_SNMP_VARBIND: the number of concurrent requests (does not have to + * be changed normally) - 2 of these are used per request (1 for input, + * 1 for output) + */ +#ifndef MEMP_NUM_SNMP_VARBIND +#define MEMP_NUM_SNMP_VARBIND 2 +#endif + +/** + * MEMP_NUM_SNMP_VALUE: the number of OID or values concurrently used + * (does not have to be changed normally) - 3 of these are used per request + * (1 for the value read and 2 for OIDs - input and output) + */ +#ifndef MEMP_NUM_SNMP_VALUE +#define MEMP_NUM_SNMP_VALUE 3 +#endif + +/** + * MEMP_NUM_NETDB: the number of concurrently running lwip_addrinfo() calls + * (before freeing the corresponding memory using lwip_freeaddrinfo()). + */ +#ifndef MEMP_NUM_NETDB +#define MEMP_NUM_NETDB 1 +#endif + +/** + * MEMP_NUM_LOCALHOSTLIST: the number of host entries in the local host list + * if DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1. + */ +#ifndef MEMP_NUM_LOCALHOSTLIST +#define MEMP_NUM_LOCALHOSTLIST 1 +#endif + +/** + * MEMP_NUM_PPPOE_INTERFACES: the number of concurrently active PPPoE + * interfaces (only used with PPPOE_SUPPORT==1) + */ +#ifndef MEMP_NUM_PPPOE_INTERFACES +#define MEMP_NUM_PPPOE_INTERFACES 1 +#endif + +/** + * PBUF_POOL_SIZE: the number of buffers in the pbuf pool. + */ +#ifndef PBUF_POOL_SIZE +#define PBUF_POOL_SIZE 16 +#endif + +/* + --------------------------------- + ---------- ARP options ---------- + --------------------------------- +*/ +/** + * LWIP_ARP==1: Enable ARP functionality. + */ +#ifndef LWIP_ARP +#define LWIP_ARP 1 +#endif + +/** + * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached. + */ +#ifndef ARP_TABLE_SIZE +#define ARP_TABLE_SIZE 10 +#endif + +/** + * ARP_QUEUEING==1: Multiple outgoing packets are queued during hardware address + * resolution. By default, only the most recent packet is queued per IP address. + * This is sufficient for most protocols and mainly reduces TCP connection + * startup time. Set this to 1 if you know your application sends more than one + * packet in a row to an IP address that is not in the ARP cache. + */ +#ifndef ARP_QUEUEING +#define ARP_QUEUEING 0 +#endif + +/** + * ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be + * updated with the source MAC and IP addresses supplied in the packet. + * You may want to disable this if you do not trust LAN peers to have the + * correct addresses, or as a limited approach to attempt to handle + * spoofing. If disabled, lwIP will need to make a new ARP request if + * the peer is not already in the ARP table, adding a little latency. + * The peer *is* in the ARP table if it requested our address before. + * Also notice that this slows down input processing of every IP packet! + */ +#ifndef ETHARP_TRUST_IP_MAC +#define ETHARP_TRUST_IP_MAC 0 +#endif + +/** + * ETHARP_SUPPORT_VLAN==1: support receiving ethernet packets with VLAN header. + * Additionally, you can define ETHARP_VLAN_CHECK to an u16_t VLAN ID to check. + * If ETHARP_VLAN_CHECK is defined, only VLAN-traffic for this VLAN is accepted. + * If ETHARP_VLAN_CHECK is not defined, all traffic is accepted. + * Alternatively, define a function/define ETHARP_VLAN_CHECK_FN(eth_hdr, vlan) + * that returns 1 to accept a packet or 0 to drop a packet. + */ +#ifndef ETHARP_SUPPORT_VLAN +#define ETHARP_SUPPORT_VLAN 0 +#endif + +/** LWIP_ETHERNET==1: enable ethernet support for PPPoE even though ARP + * might be disabled + */ +#ifndef LWIP_ETHERNET +#define LWIP_ETHERNET (LWIP_ARP || PPPOE_SUPPORT) +#endif + +/** ETH_PAD_SIZE: number of bytes added before the ethernet header to ensure + * alignment of payload after that header. Since the header is 14 bytes long, + * without this padding e.g. addresses in the IP header will not be aligned + * on a 32-bit boundary, so setting this to 2 can speed up 32-bit-platforms. + */ +#ifndef ETH_PAD_SIZE +#define ETH_PAD_SIZE 0 +#endif + +/** ETHARP_SUPPORT_STATIC_ENTRIES==1: enable code to support static ARP table + * entries (using etharp_add_static_entry/etharp_remove_static_entry). + */ +#ifndef ETHARP_SUPPORT_STATIC_ENTRIES +#define ETHARP_SUPPORT_STATIC_ENTRIES 0 +#endif + +/* + -------------------------------- + ---------- IP options ---------- + -------------------------------- +*/ +/** + * IP_FORWARD==1: Enables the ability to forward IP packets across network + * interfaces. If you are going to run lwIP on a device with only one network + * interface, define this to 0. + */ +#ifndef IP_FORWARD +#define IP_FORWARD 0 +#endif + +/** + * IP_OPTIONS_ALLOWED: Defines the behavior for IP options. + * IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped. + * IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed). + */ +#ifndef IP_OPTIONS_ALLOWED +#define IP_OPTIONS_ALLOWED 1 +#endif + +/** + * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that + * this option does not affect outgoing packet sizes, which can be controlled + * via IP_FRAG. + */ +#ifndef IP_REASSEMBLY +#define IP_REASSEMBLY 1 +#endif + +/** + * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note + * that this option does not affect incoming packet sizes, which can be + * controlled via IP_REASSEMBLY. + */ +#ifndef IP_FRAG +#define IP_FRAG 1 +#endif + +/** + * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally) + * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived + * in this time, the whole packet is discarded. + */ +#ifndef IP_REASS_MAXAGE +#define IP_REASS_MAXAGE 3 +#endif + +/** + * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled. + * Since the received pbufs are enqueued, be sure to configure + * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive + * packets even if the maximum amount of fragments is enqueued for reassembly! + */ +#ifndef IP_REASS_MAX_PBUFS +#define IP_REASS_MAX_PBUFS 10 +#endif + +/** + * IP_FRAG_USES_STATIC_BUF==1: Use a static MTU-sized buffer for IP + * fragmentation. Otherwise pbufs are allocated and reference the original + * packet data to be fragmented (or with LWIP_NETIF_TX_SINGLE_PBUF==1, + * new PBUF_RAM pbufs are used for fragments). + * ATTENTION: IP_FRAG_USES_STATIC_BUF==1 may not be used for DMA-enabled MACs! + */ +#ifndef IP_FRAG_USES_STATIC_BUF +#define IP_FRAG_USES_STATIC_BUF 0 +#endif + +/** + * IP_FRAG_MAX_MTU: Assumed max MTU on any interface for IP frag buffer + * (requires IP_FRAG_USES_STATIC_BUF==1) + */ +#if IP_FRAG_USES_STATIC_BUF && !defined(IP_FRAG_MAX_MTU) +#define IP_FRAG_MAX_MTU 1500 +#endif + +/** + * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers. + */ +#ifndef IP_DEFAULT_TTL +#define IP_DEFAULT_TTL 255 +#endif + +/** + * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast + * filter per pcb on udp and raw send operations. To enable broadcast filter + * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1. + */ +#ifndef IP_SOF_BROADCAST +#define IP_SOF_BROADCAST 0 +#endif + +/** + * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast + * filter on recv operations. + */ +#ifndef IP_SOF_BROADCAST_RECV +#define IP_SOF_BROADCAST_RECV 0 +#endif + +/** + * IP_FORWARD_ALLOW_TX_ON_RX_NETIF==1: allow ip_forward() to send packets back + * out on the netif where it was received. This should only be used for + * wireless networks. + * ATTENTION: When this is 1, make sure your netif driver correctly marks incoming + * link-layer-broadcast/multicast packets as such using the corresponding pbuf flags! + */ +#ifndef IP_FORWARD_ALLOW_TX_ON_RX_NETIF +#define IP_FORWARD_ALLOW_TX_ON_RX_NETIF 0 +#endif + +/** + * LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS==1: randomize the local port for the first + * local TCP/UDP pcb (default==0). This can prevent creating predictable port + * numbers after booting a device. + */ +#ifndef LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS +#define LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS 1 +#endif + +#define LWIP_RAND rand + +/* + ---------------------------------- + ---------- ICMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_ICMP==1: Enable ICMP module inside the IP stack. + * Be careful, disable that make your product non-compliant to RFC1122 + */ +#ifndef LWIP_ICMP +#define LWIP_ICMP 1 +#endif + +/** + * ICMP_TTL: Default value for Time-To-Live used by ICMP packets. + */ +#ifndef ICMP_TTL +#define ICMP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only) + */ +#ifndef LWIP_BROADCAST_PING +#define LWIP_BROADCAST_PING 0 +#endif + +/** + * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only) + */ +#ifndef LWIP_MULTICAST_PING +#define LWIP_MULTICAST_PING 0 +#endif + +/* + --------------------------------- + ---------- RAW options ---------- + --------------------------------- +*/ +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef LWIP_RAW +#define LWIP_RAW 1 +#endif + +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#ifndef RAW_TTL +#define RAW_TTL (IP_DEFAULT_TTL) +#endif + +/* + ---------------------------------- + ---------- DHCP options ---------- + ---------------------------------- +*/ +/** + * LWIP_DHCP==1: Enable DHCP module. + */ +#ifndef LWIP_DHCP +#define LWIP_DHCP 1 +#endif + +/** + * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address. + */ +#ifndef DHCP_DOES_ARP_CHECK +#define DHCP_DOES_ARP_CHECK ((LWIP_DHCP) && (LWIP_ARP)) +#endif + +#define LWIP_DHCP_CHECK_LINK_UP 1 + +/* + ------------------------------------ + ---------- AUTOIP options ---------- + ------------------------------------ +*/ +/** + * LWIP_AUTOIP==1: Enable AUTOIP module. + */ +#ifndef LWIP_AUTOIP +#define LWIP_AUTOIP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on + * the same interface at the same time. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP +#define LWIP_DHCP_AUTOIP_COOP 0 +#endif + +/** + * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes + * that should be sent before falling back on AUTOIP. This can be set + * as low as 1 to get an AutoIP address very quickly, but you should + * be prepared to handle a changing IP address when DHCP overrides + * AutoIP. + */ +#ifndef LWIP_DHCP_AUTOIP_COOP_TRIES +#define LWIP_DHCP_AUTOIP_COOP_TRIES 9 +#endif + +/* + ---------------------------------- + ---------- SNMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_SNMP==1: Turn on SNMP module. UDP must be available for SNMP + * transport. + */ +#ifndef LWIP_SNMP +#define LWIP_SNMP 0 +#endif + +/** + * SNMP_CONCURRENT_REQUESTS: Number of concurrent requests the module will + * allow. At least one request buffer is required. + * Does not have to be changed unless external MIBs answer request asynchronously + */ +#ifndef SNMP_CONCURRENT_REQUESTS +#define SNMP_CONCURRENT_REQUESTS 1 +#endif + +/** + * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap + * destination is required + */ +#ifndef SNMP_TRAP_DESTINATIONS +#define SNMP_TRAP_DESTINATIONS 1 +#endif + +/** + * SNMP_PRIVATE_MIB: + * When using a private MIB, you have to create a file 'private_mib.h' that contains + * a 'struct mib_array_node mib_private' which contains your MIB. + */ +#ifndef SNMP_PRIVATE_MIB +#define SNMP_PRIVATE_MIB 0 +#endif + +/** + * Only allow SNMP write actions that are 'safe' (e.g. disabeling netifs is not + * a safe action and disabled when SNMP_SAFE_REQUESTS = 1). + * Unsafe requests are disabled by default! + */ +#ifndef SNMP_SAFE_REQUESTS +#define SNMP_SAFE_REQUESTS 1 +#endif + +/** + * The maximum length of strings used. This affects the size of + * MEMP_SNMP_VALUE elements. + */ +#ifndef SNMP_MAX_OCTET_STRING_LEN +#define SNMP_MAX_OCTET_STRING_LEN 127 +#endif + +/** + * The maximum depth of the SNMP tree. + * With private MIBs enabled, this depends on your MIB! + * This affects the size of MEMP_SNMP_VALUE elements. + */ +#ifndef SNMP_MAX_TREE_DEPTH +#define SNMP_MAX_TREE_DEPTH 15 +#endif + +/** + * The size of the MEMP_SNMP_VALUE elements, normally calculated from + * SNMP_MAX_OCTET_STRING_LEN and SNMP_MAX_TREE_DEPTH. + */ +#ifndef SNMP_MAX_VALUE_SIZE +#define SNMP_MAX_VALUE_SIZE LWIP_MAX((SNMP_MAX_OCTET_STRING_LEN)+1, sizeof(s32_t)*(SNMP_MAX_TREE_DEPTH)) +#endif + +/* + ---------------------------------- + ---------- IGMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_IGMP==1: Turn on IGMP module. + */ +#ifndef LWIP_IGMP +#define LWIP_IGMP 0 +#endif + +/* + ---------------------------------- + ---------- DNS options ----------- + ---------------------------------- +*/ +/** + * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS + * transport. + */ +#ifndef LWIP_DNS +#define LWIP_DNS 1 +#endif + +/** DNS maximum number of entries to maintain locally. */ +#ifndef DNS_TABLE_SIZE +#define DNS_TABLE_SIZE 4 +#endif + +/** DNS maximum host name length supported in the name table. */ +#ifndef DNS_MAX_NAME_LENGTH +#define DNS_MAX_NAME_LENGTH 256 +#endif + +/** The maximum of DNS servers */ +#ifndef DNS_MAX_SERVERS +#define DNS_MAX_SERVERS 2 +#endif + +/** DNS do a name checking between the query and the response. */ +#ifndef DNS_DOES_NAME_CHECK +#define DNS_DOES_NAME_CHECK 1 +#endif + +/** DNS message max. size. Default value is RFC compliant. */ +#ifndef DNS_MSG_SIZE +#define DNS_MSG_SIZE 512 +#endif + +/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled, + * you have to define + * #define DNS_LOCAL_HOSTLIST_INIT {{"host1", 0x123}, {"host2", 0x234}} + * (an array of structs name/address, where address is an u32_t in network + * byte order). + * + * Instead, you can also use an external function: + * #define DNS_LOOKUP_LOCAL_EXTERN(x) extern u32_t my_lookup_function(const char *name) + * that returns the IP address or INADDR_NONE if not found. + */ +#ifndef DNS_LOCAL_HOSTLIST +#define DNS_LOCAL_HOSTLIST 0 +#endif /* DNS_LOCAL_HOSTLIST */ + +/** If this is turned on, the local host-list can be dynamically changed + * at runtime. */ +#ifndef DNS_LOCAL_HOSTLIST_IS_DYNAMIC +#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC 0 +#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */ + +/* + --------------------------------- + ---------- UDP options ---------- + --------------------------------- +*/ +/** + * LWIP_UDP==1: Turn on UDP. + */ +#ifndef LWIP_UDP +#define LWIP_UDP 1 +#endif + +/** + * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP) + */ +#ifndef LWIP_UDPLITE +#define LWIP_UDPLITE 0 +#endif + +/** + * UDP_TTL: Default Time-To-Live value. + */ +#ifndef UDP_TTL +#define UDP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * LWIP_NETBUF_RECVINFO==1: append destination addr and port to every netbuf. + */ +#ifndef LWIP_NETBUF_RECVINFO +#define LWIP_NETBUF_RECVINFO 0 +#endif + +/* + --------------------------------- + ---------- TCP options ---------- + --------------------------------- +*/ +/** + * LWIP_TCP==1: Turn on TCP. + */ +#ifndef LWIP_TCP +#define LWIP_TCP 1 +#endif + +/** + * TCP_TTL: Default Time-To-Live value. + */ +#ifndef TCP_TTL +#define TCP_TTL (IP_DEFAULT_TTL) +#endif + +/** + * TCP_WND: The size of a TCP window. This must be at least + * (2 * TCP_MSS) for things to work well + */ +#ifndef TCP_WND +#define TCP_WND (4 * TCP_MSS) +#endif + +/** + * TCP_MAXRTX: Maximum number of retransmissions of data segments. + */ +#ifndef TCP_MAXRTX +#define TCP_MAXRTX 12 +#endif + +/** + * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments. + */ +#ifndef TCP_SYNMAXRTX +#define TCP_SYNMAXRTX 6 +#endif + +/** + * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order. + * Define to 0 if your device is low on memory. + */ +#ifndef TCP_QUEUE_OOSEQ +#define TCP_QUEUE_OOSEQ (LWIP_TCP) +#endif + +/** + * TCP_MSS: TCP Maximum segment size. (default is 536, a conservative default, + * you might want to increase this.) + * For the receive side, this MSS is advertised to the remote side + * when opening a connection. For the transmit size, this MSS sets + * an upper limit on the MSS advertised by the remote host. + */ +#ifndef TCP_MSS +#define TCP_MSS 1480 +#endif + +/** + * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really + * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which + * reflects the available reassembly buffer size at the remote host) and the + * largest size permitted by the IP layer" (RFC 1122) + * Setting this to 1 enables code that checks TCP_MSS against the MTU of the + * netif used for a connection and limits the MSS if it would be too big otherwise. + */ +#ifndef TCP_CALCULATE_EFF_SEND_MSS +#define TCP_CALCULATE_EFF_SEND_MSS 1 +#endif + + +/** + * TCP_SND_BUF: TCP sender buffer space (bytes). + * To achieve good performance, this should be at least 2 * TCP_MSS. + */ +#ifndef TCP_SND_BUF +#define TCP_SND_BUF (2 * TCP_MSS) +#endif + +/** + * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least + * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. + */ +#ifndef TCP_SND_QUEUELEN +#define TCP_SND_QUEUELEN ((4 * (TCP_SND_BUF) + (TCP_MSS - 1))/(TCP_MSS)) +#endif + +/** + * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than + * TCP_SND_BUF. It is the amount of space which must be available in the + * TCP snd_buf for select to return writable (combined with TCP_SNDQUEUELOWAT). + */ +#ifndef TCP_SNDLOWAT +#define TCP_SNDLOWAT LWIP_MIN(LWIP_MAX(((TCP_SND_BUF)/2), (2 * TCP_MSS) + 1), (TCP_SND_BUF) - 1) +#endif + +/** + * TCP_SNDQUEUELOWAT: TCP writable bufs (pbuf count). This must be less + * than TCP_SND_QUEUELEN. If the number of pbufs queued on a pcb drops below + * this number, select returns writable (combined with TCP_SNDLOWAT). + */ +#ifndef TCP_SNDQUEUELOWAT +#define TCP_SNDQUEUELOWAT LWIP_MAX(((TCP_SND_QUEUELEN)/2), 5) +#endif + +/** + * TCP_OOSEQ_MAX_BYTES: The maximum number of bytes queued on ooseq per pcb. + * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==0. + */ +#ifndef TCP_OOSEQ_MAX_BYTES +#define TCP_OOSEQ_MAX_BYTES 0 +#endif + +/** + * TCP_OOSEQ_MAX_PBUFS: The maximum number of pbufs queued on ooseq per pcb. + * Default is 0 (no limit). Only valid for TCP_QUEUE_OOSEQ==0. + */ +#ifndef TCP_OOSEQ_MAX_PBUFS +#define TCP_OOSEQ_MAX_PBUFS 0 +#endif + +/** + * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb. + */ +#ifndef TCP_LISTEN_BACKLOG +#define TCP_LISTEN_BACKLOG 1 +#endif + +/** + * The maximum allowed backlog for TCP listen netconns. + * This backlog is used unless another is explicitly specified. + * 0xff is the maximum (u8_t). + */ +#ifndef TCP_DEFAULT_LISTEN_BACKLOG +#define TCP_DEFAULT_LISTEN_BACKLOG 0xff +#endif + +/** + * TCP_OVERSIZE: The maximum number of bytes that tcp_write may + * allocate ahead of time in an attempt to create shorter pbuf chains + * for transmission. The meaningful range is 0 to TCP_MSS. Some + * suggested values are: + * + * 0: Disable oversized allocation. Each tcp_write() allocates a new + pbuf (old behaviour). + * 1: Allocate size-aligned pbufs with minimal excess. Use this if your + * scatter-gather DMA requires aligned fragments. + * 128: Limit the pbuf/memory overhead to 20%. + * TCP_MSS: Try to create unfragmented TCP packets. + * TCP_MSS/4: Try to create 4 fragments or less per TCP packet. + */ +#ifndef TCP_OVERSIZE +#define TCP_OVERSIZE TCP_MSS +#endif + +/** + * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option. + */ +#ifndef LWIP_TCP_TIMESTAMPS +#define LWIP_TCP_TIMESTAMPS 0 +#endif + +/** + * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an + * explicit window update + */ +#ifndef TCP_WND_UPDATE_THRESHOLD +#define TCP_WND_UPDATE_THRESHOLD (TCP_WND / 4) +#endif + +/** + * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1. + * LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all + * events (accept, sent, etc) that happen in the system. + * LWIP_CALLBACK_API==1: The PCB callback function is called directly + * for the event. This is the default. + */ +#if !defined(LWIP_EVENT_API) && !defined(LWIP_CALLBACK_API) +#define LWIP_EVENT_API 0 +#define LWIP_CALLBACK_API 1 +#endif + + +/* + ---------------------------------- + ---------- Pbuf options ---------- + ---------------------------------- +*/ +/** + * PBUF_LINK_HLEN: the number of bytes that should be allocated for a + * link level header. The default is 14, the standard value for + * Ethernet. + */ +#ifndef PBUF_LINK_HLEN +#define PBUF_LINK_HLEN (14 + ETH_PAD_SIZE) +#endif + +/** + * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is + * designed to accomodate single full size TCP frame in one pbuf, including + * TCP_MSS, IP header, and link header. + */ +#ifndef PBUF_POOL_BUFSIZE +#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_HLEN) +#endif + +/* + ------------------------------------------------ + ---------- Network Interfaces options ---------- + ------------------------------------------------ +*/ +/** + * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname + * field. + */ +#ifndef LWIP_NETIF_HOSTNAME +#define LWIP_NETIF_HOSTNAME 1 +#endif + +/** + * LWIP_NETIF_API==1: Support netif api (in netifapi.c) + */ +#ifndef LWIP_NETIF_API +#define LWIP_NETIF_API 0 +#endif + +/** + * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface + * changes its up/down status (i.e., due to DHCP IP acquistion) + */ +#ifndef LWIP_NETIF_STATUS_CALLBACK +#define LWIP_NETIF_STATUS_CALLBACK 1 +#endif + +/** + * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface + * whenever the link changes (i.e., link down) + */ +#ifndef LWIP_NETIF_LINK_CALLBACK +#define LWIP_NETIF_LINK_CALLBACK 1 +#endif + +/** + * LWIP_NETIF_REMOVE_CALLBACK==1: Support a callback function that is called + * when a netif has been removed + */ +#ifndef LWIP_NETIF_REMOVE_CALLBACK +#define LWIP_NETIF_REMOVE_CALLBACK 0 +#endif + +/** + * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table + * indices) in struct netif. TCP and UDP can make use of this to prevent + * scanning the ARP table for every sent packet. While this is faster for big + * ARP tables or many concurrent connections, it might be counterproductive + * if you have a tiny ARP table or if there never are concurrent connections. + */ +#ifndef LWIP_NETIF_HWADDRHINT +#define LWIP_NETIF_HWADDRHINT 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP + * address equal to the netif IP address, looping them back up the stack. + */ +#ifndef LWIP_NETIF_LOOPBACK +#define LWIP_NETIF_LOOPBACK 0 +#endif + +/** + * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback + * sending for each netif (0 = disabled) + */ +#ifndef LWIP_LOOPBACK_MAX_PBUFS +#define LWIP_LOOPBACK_MAX_PBUFS 0 +#endif + +/** + * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in + * the system, as netifs must change how they behave depending on this setting + * for the LWIP_NETIF_LOOPBACK option to work. + * Setting this is needed to avoid reentering non-reentrant functions like + * tcp_input(). + * LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a + * multithreaded environment like tcpip.c. In this case, netif->input() + * is called directly. + * LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup. + * The packets are put on a list and netif_poll() must be called in + * the main application loop. + */ +#ifndef LWIP_NETIF_LOOPBACK_MULTITHREADING +#define LWIP_NETIF_LOOPBACK_MULTITHREADING (!NO_SYS) +#endif + +/** + * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data + * to be sent into one single pbuf. This is for compatibility with DMA-enabled + * MACs that do not support scatter-gather. + * Beware that this might involve CPU-memcpy before transmitting that would not + * be needed without this flag! Use this only if you need to! + * + * @todo: TCP and IP-frag do not work with this, yet: + */ +#ifndef LWIP_NETIF_TX_SINGLE_PBUF +#define LWIP_NETIF_TX_SINGLE_PBUF 0 +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + +/* + ------------------------------------ + ---------- LOOPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1) and loopif.c + */ +#ifndef LWIP_HAVE_LOOPIF +#define LWIP_HAVE_LOOPIF 0 +#endif + +/* + ------------------------------------ + ---------- SLIPIF options ---------- + ------------------------------------ +*/ +/** + * LWIP_HAVE_SLIPIF==1: Support slip interface and slipif.c + */ +#ifndef LWIP_HAVE_SLIPIF +#define LWIP_HAVE_SLIPIF 0 +#endif + +/* + ------------------------------------ + ---------- Thread options ---------- + ------------------------------------ +*/ +/** + * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread. + */ +#ifndef TCPIP_THREAD_NAME +#define TCPIP_THREAD_NAME "tcpip_thread" +#endif + +/** + * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_STACKSIZE +#define TCPIP_THREAD_STACKSIZE 1024 +#endif + +/** + * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef TCPIP_THREAD_PRIO +#define TCPIP_THREAD_PRIO (NORMALPRIO) +#endif + +/** + * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when tcpip_init is called. + */ +#ifndef TCPIP_MBOX_SIZE +#define TCPIP_MBOX_SIZE MEMP_NUM_PBUF +#endif + +/** + * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread. + */ +#ifndef SLIPIF_THREAD_NAME +#define SLIPIF_THREAD_NAME "slipif_loop" +#endif + +/** + * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_STACKSIZE +#define SLIPIF_THREAD_STACKSIZE 1024 +#endif + +/** + * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef SLIPIF_THREAD_PRIO +#define SLIPIF_THREAD_PRIO (NORMALPRIO) +#endif + +/** + * PPP_THREAD_NAME: The name assigned to the pppInputThread. + */ +#ifndef PPP_THREAD_NAME +#define PPP_THREAD_NAME "pppInputThread" +#endif + +/** + * PPP_THREAD_STACKSIZE: The stack size used by the pppInputThread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_STACKSIZE +#define PPP_THREAD_STACKSIZE 1024 +#endif + +/** + * PPP_THREAD_PRIO: The priority assigned to the pppInputThread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef PPP_THREAD_PRIO +#define PPP_THREAD_PRIO (NORMALPRIO) +#endif + +/** + * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread. + */ +#ifndef DEFAULT_THREAD_NAME +#define DEFAULT_THREAD_NAME "lwIP" +#endif + +/** + * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_STACKSIZE +#define DEFAULT_THREAD_STACKSIZE 1024 +#endif + +/** + * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#ifndef DEFAULT_THREAD_PRIO +#define DEFAULT_THREAD_PRIO (NORMALPRIO) +#endif + +/** + * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_RAW_RECVMBOX_SIZE +#define DEFAULT_RAW_RECVMBOX_SIZE 4 +#endif + +/** + * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_UDP_RECVMBOX_SIZE +#define DEFAULT_UDP_RECVMBOX_SIZE 4 +#endif + +/** + * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#ifndef DEFAULT_TCP_RECVMBOX_SIZE +#define DEFAULT_TCP_RECVMBOX_SIZE 40 +#endif + +/** + * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections. + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when the acceptmbox is created. + */ +#ifndef DEFAULT_ACCEPTMBOX_SIZE +#define DEFAULT_ACCEPTMBOX_SIZE 4 +#endif + +/* + ---------------------------------------------- + ---------- Sequential layer options ---------- + ---------------------------------------------- +*/ +/** + * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!) + * Don't use it if you're not an active lwIP project member + */ +#ifndef LWIP_TCPIP_CORE_LOCKING +#define LWIP_TCPIP_CORE_LOCKING 0 +#endif + +/** + * LWIP_TCPIP_CORE_LOCKING_INPUT: (EXPERIMENTAL!) + * Don't use it if you're not an active lwIP project member + */ +#ifndef LWIP_TCPIP_CORE_LOCKING_INPUT +#define LWIP_TCPIP_CORE_LOCKING_INPUT 0 +#endif + +/** + * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c) + */ +#ifndef LWIP_NETCONN +#define LWIP_NETCONN 1 +#endif + +/** LWIP_TCPIP_TIMEOUT==1: Enable tcpip_timeout/tcpip_untimeout tod create + * timers running in tcpip_thread from another thread. + */ +#ifndef LWIP_TCPIP_TIMEOUT +#define LWIP_TCPIP_TIMEOUT 1 +#endif + +/* + ------------------------------------ + ---------- Socket options ---------- + ------------------------------------ +*/ +/** + * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) + */ +#ifndef LWIP_SOCKET +#define LWIP_SOCKET 1 +#endif + +/** + * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names. + * (only used if you use sockets.c) + */ +#ifndef LWIP_COMPAT_SOCKETS +#define LWIP_COMPAT_SOCKETS 1 +#endif + +/** + * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names. + * Disable this option if you use a POSIX operating system that uses the same + * names (read, write & close). (only used if you use sockets.c) + */ +#ifndef LWIP_POSIX_SOCKETS_IO_NAMES +#define LWIP_POSIX_SOCKETS_IO_NAMES 1 +#endif + +/** + * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT + * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set + * in seconds. (does not require sockets.c, and will affect tcp.c) + */ +#ifndef LWIP_TCP_KEEPALIVE +#define LWIP_TCP_KEEPALIVE 0 +#endif + +/** + * LWIP_SO_SNDTIMEO==1: Enable send timeout for sockets/netconns and + * SO_SNDTIMEO processing. + */ +#ifndef LWIP_SO_SNDTIMEO +#define LWIP_SO_SNDTIMEO 1 +#endif + +/** + * LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and + * SO_RCVTIMEO processing. + */ +#ifndef LWIP_SO_RCVTIMEO +#define LWIP_SO_RCVTIMEO 1 +#endif + +/** + * LWIP_SO_LINGER==1: Enable linger option for sockets/netconns + */ +#define LWIP_SO_LINGER 1 + +/** + * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing. + */ +#ifndef LWIP_SO_RCVBUF +#define LWIP_SO_RCVBUF 1 +#endif + +/** + * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize. + */ +#ifndef RECV_BUFSIZE_DEFAULT +#define RECV_BUFSIZE_DEFAULT INT_MAX +#endif + +/** + * SO_REUSE==1: Enable SO_REUSEADDR option. + */ +#ifndef SO_REUSE +#define SO_REUSE 1 +#endif + +/** + * SO_REUSE_RXTOALL==1: Pass a copy of incoming broadcast/multicast packets + * to all local matches if SO_REUSEADDR is turned on. + * WARNING: Adds a memcpy for every packet if passing to more than one pcb! + */ +#ifndef SO_REUSE_RXTOALL +#define SO_REUSE_RXTOALL 1 +#endif + +/* + ---------------------------------------- + ---------- Statistics options ---------- + ---------------------------------------- +*/ +/** + * LWIP_STATS==1: Enable statistics collection in lwip_stats. + */ +#ifndef LWIP_STATS +#define LWIP_STATS 0 +#endif + +#if LWIP_STATS + +/** + * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions. + */ +#ifndef LWIP_STATS_DISPLAY +#define LWIP_STATS_DISPLAY 0 +#endif + +/** + * LINK_STATS==1: Enable link stats. + */ +#ifndef LINK_STATS +#define LINK_STATS 1 +#endif + +/** + * ETHARP_STATS==1: Enable etharp stats. + */ +#ifndef ETHARP_STATS +#define ETHARP_STATS (LWIP_ARP) +#endif + +/** + * IP_STATS==1: Enable IP stats. + */ +#ifndef IP_STATS +#define IP_STATS 1 +#endif + +/** + * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is + * on if using either frag or reass. + */ +#ifndef IPFRAG_STATS +#define IPFRAG_STATS (IP_REASSEMBLY || IP_FRAG) +#endif + +/** + * ICMP_STATS==1: Enable ICMP stats. + */ +#ifndef ICMP_STATS +#define ICMP_STATS 1 +#endif + +/** + * IGMP_STATS==1: Enable IGMP stats. + */ +#ifndef IGMP_STATS +#define IGMP_STATS (LWIP_IGMP) +#endif + +/** + * UDP_STATS==1: Enable UDP stats. Default is on if + * UDP enabled, otherwise off. + */ +#ifndef UDP_STATS +#define UDP_STATS (LWIP_UDP) +#endif + +/** + * TCP_STATS==1: Enable TCP stats. Default is on if TCP + * enabled, otherwise off. + */ +#ifndef TCP_STATS +#define TCP_STATS (LWIP_TCP) +#endif + +/** + * MEM_STATS==1: Enable mem.c stats. + */ +#ifndef MEM_STATS +#define MEM_STATS ((MEM_LIBC_MALLOC == 0) && (MEM_USE_POOLS == 0)) +#endif + +/** + * MEMP_STATS==1: Enable memp.c pool stats. + */ +#ifndef MEMP_STATS +#define MEMP_STATS (MEMP_MEM_MALLOC == 0) +#endif + +/** + * SYS_STATS==1: Enable system stats (sem and mbox counts, etc). + */ +#ifndef SYS_STATS +#define SYS_STATS (NO_SYS == 0) +#endif + +#else + +#define LINK_STATS 0 +#define IP_STATS 0 +#define IPFRAG_STATS 0 +#define ICMP_STATS 0 +#define IGMP_STATS 0 +#define UDP_STATS 0 +#define TCP_STATS 0 +#define MEM_STATS 0 +#define MEMP_STATS 0 +#define SYS_STATS 0 +#define LWIP_STATS_DISPLAY 0 + +#endif /* LWIP_STATS */ + +/* + --------------------------------- + ---------- PPP options ---------- + --------------------------------- +*/ +/** + * PPP_SUPPORT==1: Enable PPP. + */ +#ifndef PPP_SUPPORT +#define PPP_SUPPORT 0 +#endif + +/** + * PPPOE_SUPPORT==1: Enable PPP Over Ethernet + */ +#ifndef PPPOE_SUPPORT +#define PPPOE_SUPPORT 0 +#endif + +/** + * PPPOS_SUPPORT==1: Enable PPP Over Serial + */ +#ifndef PPPOS_SUPPORT +#define PPPOS_SUPPORT PPP_SUPPORT +#endif + +#if PPP_SUPPORT + +/** + * NUM_PPP: Max PPP sessions. + */ +#ifndef NUM_PPP +#define NUM_PPP 1 +#endif + +/** + * PAP_SUPPORT==1: Support PAP. + */ +#ifndef PAP_SUPPORT +#define PAP_SUPPORT 0 +#endif + +/** + * CHAP_SUPPORT==1: Support CHAP. + */ +#ifndef CHAP_SUPPORT +#define CHAP_SUPPORT 0 +#endif + +/** + * MSCHAP_SUPPORT==1: Support MSCHAP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef MSCHAP_SUPPORT +#define MSCHAP_SUPPORT 0 +#endif + +/** + * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CBCP_SUPPORT +#define CBCP_SUPPORT 0 +#endif + +/** + * CCP_SUPPORT==1: Support CCP. CURRENTLY NOT SUPPORTED! DO NOT SET! + */ +#ifndef CCP_SUPPORT +#define CCP_SUPPORT 0 +#endif + +/** + * VJ_SUPPORT==1: Support VJ header compression. + */ +#ifndef VJ_SUPPORT +#define VJ_SUPPORT 0 +#endif + +/** + * MD5_SUPPORT==1: Support MD5 (see also CHAP). + */ +#ifndef MD5_SUPPORT +#define MD5_SUPPORT 0 +#endif + +/* + * Timeouts + */ +#ifndef FSM_DEFTIMEOUT +#define FSM_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef FSM_DEFMAXTERMREQS +#define FSM_DEFMAXTERMREQS 2 /* Maximum Terminate-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXCONFREQS +#define FSM_DEFMAXCONFREQS 10 /* Maximum Configure-Request transmissions */ +#endif + +#ifndef FSM_DEFMAXNAKLOOPS +#define FSM_DEFMAXNAKLOOPS 5 /* Maximum number of nak loops */ +#endif + +#ifndef UPAP_DEFTIMEOUT +#define UPAP_DEFTIMEOUT 6 /* Timeout (seconds) for retransmitting req */ +#endif + +#ifndef UPAP_DEFREQTIME +#define UPAP_DEFREQTIME 30 /* Time to wait for auth-req from peer */ +#endif + +#ifndef CHAP_DEFTIMEOUT +#define CHAP_DEFTIMEOUT 6 /* Timeout time in seconds */ +#endif + +#ifndef CHAP_DEFTRANSMITS +#define CHAP_DEFTRANSMITS 10 /* max # times to send challenge */ +#endif + +/* Interval in seconds between keepalive echo requests, 0 to disable. */ +#ifndef LCP_ECHOINTERVAL +#define LCP_ECHOINTERVAL 0 +#endif + +/* Number of unanswered echo requests before failure. */ +#ifndef LCP_MAXECHOFAILS +#define LCP_MAXECHOFAILS 3 +#endif + +/* Max Xmit idle time (in jiffies) before resend flag char. */ +#ifndef PPP_MAXIDLEFLAG +#define PPP_MAXIDLEFLAG 100 +#endif + +/* + * Packet sizes + * + * Note - lcp shouldn't be allowed to negotiate stuff outside these + * limits. See lcp.h in the pppd directory. + * (XXX - these constants should simply be shared by lcp.c instead + * of living in lcp.h) + */ +#define PPP_MTU 1500 /* Default MTU (size of Info field) */ +#ifndef PPP_MAXMTU +/* #define PPP_MAXMTU 65535 - (PPP_HDRLEN + PPP_FCSLEN) */ +#define PPP_MAXMTU 1500 /* Largest MTU we allow */ +#endif +#define PPP_MINMTU 64 +#define PPP_MRU 1500 /* default MRU = max length of info field */ +#define PPP_MAXMRU 1500 /* Largest MRU we allow */ +#ifndef PPP_DEFMRU +#define PPP_DEFMRU 296 /* Try for this */ +#endif +#define PPP_MINMRU 128 /* No MRUs below this */ + +#ifndef MAXNAMELEN +#define MAXNAMELEN 256 /* max length of hostname or name for auth */ +#endif +#ifndef MAXSECRETLEN +#define MAXSECRETLEN 256 /* max length of password or secret */ +#endif + +#endif /* PPP_SUPPORT */ + +/* + -------------------------------------- + ---------- Checksum options ---------- + -------------------------------------- +*/ +/** + * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets. + */ +#ifndef CHECKSUM_GEN_IP +#define CHECKSUM_GEN_IP 1 +#endif + +/** + * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets. + */ +#ifndef CHECKSUM_GEN_UDP +#define CHECKSUM_GEN_UDP 1 +#endif + +/** + * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets. + */ +#ifndef CHECKSUM_GEN_TCP +#define CHECKSUM_GEN_TCP 1 +#endif + +/** + * CHECKSUM_GEN_ICMP==1: Generate checksums in software for outgoing ICMP packets. + */ +#ifndef CHECKSUM_GEN_ICMP +#define CHECKSUM_GEN_ICMP 1 +#endif + +/** + * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets. + */ +#ifndef CHECKSUM_CHECK_IP +#define CHECKSUM_CHECK_IP 1 +#endif + +/** + * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets. + */ +#ifndef CHECKSUM_CHECK_UDP +#define CHECKSUM_CHECK_UDP 1 +#endif + +/** + * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets. + */ +#ifndef CHECKSUM_CHECK_TCP +#define CHECKSUM_CHECK_TCP 1 +#endif + +/** + * LWIP_CHECKSUM_ON_COPY==1: Calculate checksum when copying data from + * application buffers to pbufs. + */ +#ifndef LWIP_CHECKSUM_ON_COPY +#define LWIP_CHECKSUM_ON_COPY 0 +#endif + +/* + --------------------------------------- + ---------- Hook options --------------- + --------------------------------------- +*/ + +/* Hooks are undefined by default, define them to a function if you need them. */ + +/** + * LWIP_HOOK_IP4_INPUT(pbuf, input_netif): + * - called from ip_input() (IPv4) + * - pbuf: received struct pbuf passed to ip_input() + * - input_netif: struct netif on which the packet has been received + * Return values: + * - 0: Hook has not consumed the packet, packet is processed as normal + * - != 0: Hook has consumed the packet. + * If the hook consumed the packet, 'pbuf' is in the responsibility of the hook + * (i.e. free it when done). + */ + +/** + * LWIP_HOOK_IP4_ROUTE(dest): + * - called from ip_route() (IPv4) + * - dest: destination IPv4 address + * Returns the destination netif or NULL if no destination netif is found. In + * that case, ip_route() continues as normal. + */ + +/* + --------------------------------------- + ---------- Debugging options ---------- + --------------------------------------- +*/ +/** + * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is + * compared against this value. If it is smaller, then debugging + * messages are written. + */ +#ifndef LWIP_DBG_MIN_LEVEL +#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_ALL +#endif + +/** + * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable + * debug messages of certain types. + */ +#ifndef LWIP_DBG_TYPES_ON +#define LWIP_DBG_TYPES_ON LWIP_DBG_OFF +#endif + +/** + * ETHARP_DEBUG: Enable debugging in etharp.c. + */ +#ifndef ETHARP_DEBUG +#define ETHARP_DEBUG LWIP_DBG_OFF +#endif + +/** + * NETIF_DEBUG: Enable debugging in netif.c. + */ +#ifndef NETIF_DEBUG +#define NETIF_DEBUG LWIP_DBG_OFF +#endif + +/** + * PBUF_DEBUG: Enable debugging in pbuf.c. + */ +#ifndef PBUF_DEBUG +#define PBUF_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_LIB_DEBUG: Enable debugging in api_lib.c. + */ +#ifndef API_LIB_DEBUG +#define API_LIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * API_MSG_DEBUG: Enable debugging in api_msg.c. + */ +#ifndef API_MSG_DEBUG +#define API_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SOCKETS_DEBUG: Enable debugging in sockets.c. + */ +#ifndef SOCKETS_DEBUG +#define SOCKETS_DEBUG LWIP_DBG_OFF +#endif + +/** + * ICMP_DEBUG: Enable debugging in icmp.c. + */ +#ifndef ICMP_DEBUG +#define ICMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IGMP_DEBUG: Enable debugging in igmp.c. + */ +#ifndef IGMP_DEBUG +#define IGMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * INET_DEBUG: Enable debugging in inet.c. + */ +#ifndef INET_DEBUG +#define INET_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_DEBUG: Enable debugging for IP. + */ +#ifndef IP_DEBUG +#define IP_DEBUG LWIP_DBG_OFF +#endif + +/** + * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass. + */ +#ifndef IP_REASS_DEBUG +#define IP_REASS_DEBUG LWIP_DBG_OFF +#endif + +/** + * RAW_DEBUG: Enable debugging in raw.c. + */ +#ifndef RAW_DEBUG +#define RAW_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEM_DEBUG: Enable debugging in mem.c. + */ +#ifndef MEM_DEBUG +#define MEM_DEBUG LWIP_DBG_OFF +#endif + +/** + * MEMP_DEBUG: Enable debugging in memp.c. + */ +#ifndef MEMP_DEBUG +#define MEMP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SYS_DEBUG: Enable debugging in sys.c. + */ +#ifndef SYS_DEBUG +#define SYS_DEBUG LWIP_DBG_OFF +#endif + +/** + * TIMERS_DEBUG: Enable debugging in timers.c. + */ +#ifndef TIMERS_DEBUG +#define TIMERS_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_DEBUG: Enable debugging for TCP. + */ +#ifndef TCP_DEBUG +#define TCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug. + */ +#ifndef TCP_INPUT_DEBUG +#define TCP_INPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit. + */ +#ifndef TCP_FR_DEBUG +#define TCP_FR_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit + * timeout. + */ +#ifndef TCP_RTO_DEBUG +#define TCP_RTO_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_CWND_DEBUG: Enable debugging for TCP congestion window. + */ +#ifndef TCP_CWND_DEBUG +#define TCP_CWND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating. + */ +#ifndef TCP_WND_DEBUG +#define TCP_WND_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions. + */ +#ifndef TCP_OUTPUT_DEBUG +#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_RST_DEBUG: Enable debugging for TCP with the RST message. + */ +#ifndef TCP_RST_DEBUG +#define TCP_RST_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths. + */ +#ifndef TCP_QLEN_DEBUG +#define TCP_QLEN_DEBUG LWIP_DBG_OFF +#endif + +/** + * UDP_DEBUG: Enable debugging in UDP. + */ +#ifndef UDP_DEBUG +#define UDP_DEBUG LWIP_DBG_OFF +#endif + +/** + * TCPIP_DEBUG: Enable debugging in tcpip.c. + */ +#ifndef TCPIP_DEBUG +#define TCPIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * PPP_DEBUG: Enable debugging for PPP. + */ +#ifndef PPP_DEBUG +#define PPP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SLIP_DEBUG: Enable debugging in slipif.c. + */ +#ifndef SLIP_DEBUG +#define SLIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * DHCP_DEBUG: Enable debugging in dhcp.c. + */ +#ifndef DHCP_DEBUG +#define DHCP_DEBUG LWIP_DBG_OFF +#endif + +/** + * AUTOIP_DEBUG: Enable debugging in autoip.c. + */ +#ifndef AUTOIP_DEBUG +#define AUTOIP_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MSG_DEBUG: Enable debugging for SNMP messages. + */ +#ifndef SNMP_MSG_DEBUG +#define SNMP_MSG_DEBUG LWIP_DBG_OFF +#endif + +/** + * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs. + */ +#ifndef SNMP_MIB_DEBUG +#define SNMP_MIB_DEBUG LWIP_DBG_OFF +#endif + +/** + * DNS_DEBUG: Enable debugging for DNS. + */ +#ifndef DNS_DEBUG +#define DNS_DEBUG LWIP_DBG_OFF +#endif + +// in order to enable the lwIP debug output the below has to be uncomment and +// the options above changed to LWIP_DBG_ON for the features that are to output debug information +//#define LWIP_DEBUG 1 + +// enable full duplex comms on multiple threads +// this requires adding an extra field in ChibiOS thread_t (see comment on platform_sys_arch.c) +//#define LWIP_NETCONN_FULLDUPLEX 1 + +#endif /* __LWIPOPT_H__ */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/managed_helpers/README.md b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/managed_helpers/README.md new file mode 100644 index 00000000..ac46ddc7 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/managed_helpers/README.md @@ -0,0 +1,5 @@ +## Managed code helpers + +This folder contains helper classes to make developers life easier when coding for this target board. + +* [Adc](STM32F769I_DISCOVERY.Adc.cs) diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/managed_helpers/STM32F769I_DISCOVERY.Adc.cs b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/managed_helpers/STM32F769I_DISCOVERY.Adc.cs new file mode 100644 index 00000000..b78ba6eb --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/managed_helpers/STM32F769I_DISCOVERY.Adc.cs @@ -0,0 +1,53 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +namespace nanoFramework.Targets.STM32F769I_DISCOVERY +{ + /// + /// Enumeration of ADC channels available in STM32F769I_DISCOVERY + /// + public static class AdcChannels + { + /// + /// Channel 0, exposed on A0, connected to PA6 (ADC1 - IN6) + /// + public const int Channel_0 = 0; + + /// + /// Channel 1, exposed on A1, connected to PA4 (ADC1 - IN4) + /// + public const int Channel_1 = 1; + + /// + /// Channel 2, exposed on A2, connected to PC2 (ADC1 - IN12) + /// + public const int Channel_2 = 2; + + /// + /// Channel 3, exposed on A3, connected to PF10 (ADC1 - IN8) + /// + public const int Channel_3 = 3; + + /// + /// Channel 4, exposed on A4, connected to PF8 (ADC3 - IN6) + /// + public const int Channel_4 = 4; + + /// + /// Channel 5, internal temperature sensor, connected to ADC1 + /// + public const int Channel_TemperatureSensor = 5; + + /// + /// Channel 6, internal voltage reference, connected to ADC1 + /// + public const int Channel_VrefIn = 6; + + /// + /// Channel 7, connected to VBatt pin, ADC1 + /// + public const int Channel_Vbatt = 7; + } +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/managed_helpers/package.nuspec b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/managed_helpers/package.nuspec new file mode 100644 index 00000000..58e7f992 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/managed_helpers/package.nuspec @@ -0,0 +1,28 @@ + + + + nanoFramework.Targets.ST_STM32F769I_DISCOVERY + nanoFramework.Targets.ST_STM32F769I_DISCOVERY + 1.0.0 + nanoFramework project contributors + nanoFramework project contributors + false + + Helper classes to use ST_STM32F769I_DISCOVERY target in C# applications. + + + + + This is an extension for .NET nanoFramework enhacing support for Windows.Devices.Gpio.GpioController when using STM32 MCUs. + + https://github.com/nanoframework + https://secure.gravatar.com/avatar/97d0e092247f0716db6d4b47b7d1d1ad + https://github.com/nanoframework/nf-interpreter/blob/develop/LICENSE.md + Copyright (c) 2019 The nanoFramework project contributors + + nanoFramework, nano Framework, NETNF, NETMF, Micro Framework, STM32, .net, STM32F769I + + + + + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/mbedtls_config.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/mbedtls_config.h new file mode 100644 index 00000000..344adf5b --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/mbedtls_config.h @@ -0,0 +1,53 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2006-2015, ARM Limited, All Rights Reserved +// See LICENSE file in the project root for full license information. +// + +#ifndef MBEDTLS_CONFIG_H +#define MBEDTLS_CONFIG_H + +/* For test certificates */ +// #define MBEDTLS_CERTS_C +// #define MBEDTLS_PEM_PARSE_C + +// #define SSL_DEBUG_BUF MBEDTLS_SSL_DEBUG_BUF +// #define SSL_DEBUG_CRT MBEDTLS_SSL_DEBUG_CRT +// #define SSL_DEBUG_ECP MBEDTLS_SSL_DEBUG_ECP +// #define SSL_DEBUG_MPI MBEDTLS_SSL_DEBUG_MPI +// #define SSL_DEBUG_MSG MBEDTLS_SSL_DEBUG_MSG +// #define SSL_DEBUG_RET MBEDTLS_SSL_DEBUG_RET + +// #define MBEDTLS_SSL_ALL_ALERT_MESSAGES +// #define MBEDTLS_VERSION_FEATURES +// #define MBEDTLS_CERTS_C +// #define MBEDTLS_ERROR_C +// #define MBEDTLS_VERSION_C + +// uncomment the defines below to enable static memory allocation feature +#if 0 +#define MBEDTLS_MEMORY_BUFFER_ALLOC_C +#define MBEDTLS_PLATFORM_MEMORY +#endif + +#ifdef USE_LCD +#include "lcd_log.h" +#define MBEDTLS_PLATFORM_PRINTF_MACRO LCD_UsrLog +#endif + +// uncomment the defines bellow to generate debug output +// set below the threshold level for debug messages +// check mbed TLS mbedtls/debug.h header for details. +// Debug levels: +// 0 No debug +// 1 Error +// 2 State change +// 3 Informational +// 4 Verbose + +// #define MBEDTLS_DEBUG_C +// #define MBEDTLS_SSL_DEBUG_ALL +// #define MBEDTLS_SSL_ALL_ALERT_MESSAGES +// #define MBEDTLS_DEBUG_THRESHOLD 2 + +#endif // MBEDTLS_CONFIG_H diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/CMakeLists.txt new file mode 100644 index 00000000..f0e921f7 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# # append nanoBooter source files +list(APPEND NANOBOOTER_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") + +# make var global +set(NANOBOOTER_PROJECT_SOURCES ${NANOBOOTER_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/STM32F76xx_booter-DEBUG.ld b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/STM32F76xx_booter-DEBUG.ld new file mode 100644 index 00000000..0637fbd7 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/STM32F76xx_booter-DEBUG.ld @@ -0,0 +1,122 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F76xx generic setup. + * + * RAM0 - Data, Heap. + * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. + * + * Notes: + * BSS is placed in DTCM RAM in order to simplify DMA buffers management. + */ +MEMORY +{ + flash : org = 0x08000000, len = 32k /* space reserved for nanoBooter (1st sector 0x08000000 to 0x08008000)*/ + flash_itcm : org = 0x00200000, len = 32k + config : org = 0x08008000, len = 32k /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ + ram1 : org = 0x20020000, len = 368k /* SRAM1 */ + ram2 : org = 0x2007C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20000000, len = 128k /* DTCM-RAM */ + ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash_itcm); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash_itcm); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash_itcm); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash_itcm); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram3); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram3); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram3); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + + +/* rules inclusion.*/ +INCLUDE rules_stacks.ld + +/*===========================================================================*/ +/* Custom sections for STM32F7xx. */ +/*===========================================================================*/ + +/* RAM region to be used for nocache segment.*/ +REGION_ALIAS("NOCACHE_RAM", ram3); + +/* RAM region to be used for eth segment.*/ +REGION_ALIAS("ETH_RAM", ram3); + +SECTIONS +{ + /* Special section for non cache-able areas.*/ + .nocache (NOLOAD) : ALIGN(4) + { + __nocache_base__ = .; + *(.nocache) + *(.nocache.*) + *(.bss.__nocache_*) + . = ALIGN(4); + __nocache_end__ = .; + } > NOCACHE_RAM + + /* Special section for Ethernet DMA non cache-able areas.*/ + .eth (NOLOAD) : ALIGN(4) + { + __eth_base__ = .; + *(.eth) + *(.eth.*) + *(.bss.__eth_*) + . = ALIGN(4); + __eth_end__ = .; + } > ETH_RAM +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/STM32F76xx_booter.ld b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/STM32F76xx_booter.ld new file mode 100644 index 00000000..0637fbd7 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/STM32F76xx_booter.ld @@ -0,0 +1,122 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F76xx generic setup. + * + * RAM0 - Data, Heap. + * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. + * + * Notes: + * BSS is placed in DTCM RAM in order to simplify DMA buffers management. + */ +MEMORY +{ + flash : org = 0x08000000, len = 32k /* space reserved for nanoBooter (1st sector 0x08000000 to 0x08008000)*/ + flash_itcm : org = 0x00200000, len = 32k + config : org = 0x08008000, len = 32k /* space reserved for configuration block */ + deployment : org = 0x00000000, len = 0 /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ + ram1 : org = 0x20020000, len = 368k /* SRAM1 */ + ram2 : org = 0x2007C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20000000, len = 128k /* DTCM-RAM */ + ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash_itcm); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash_itcm); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash_itcm); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash_itcm); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram3); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram3); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram3); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + + +/* rules inclusion.*/ +INCLUDE rules_stacks.ld + +/*===========================================================================*/ +/* Custom sections for STM32F7xx. */ +/*===========================================================================*/ + +/* RAM region to be used for nocache segment.*/ +REGION_ALIAS("NOCACHE_RAM", ram3); + +/* RAM region to be used for eth segment.*/ +REGION_ALIAS("ETH_RAM", ram3); + +SECTIONS +{ + /* Special section for non cache-able areas.*/ + .nocache (NOLOAD) : ALIGN(4) + { + __nocache_base__ = .; + *(.nocache) + *(.nocache.*) + *(.bss.__nocache_*) + . = ALIGN(4); + __nocache_end__ = .; + } > NOCACHE_RAM + + /* Special section for Ethernet DMA non cache-able areas.*/ + .eth (NOLOAD) : ALIGN(4) + { + __eth_base__ = .; + *(.eth) + *(.eth.*) + *(.bss.__eth_*) + . = ALIGN(4); + __eth_end__ = .; + } > ETH_RAM +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/chconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/chconf.h new file mode 100644 index 00000000..0bd93fbe --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/chconf.h @@ -0,0 +1,606 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 10000 + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#define CH_CFG_INTERVALS_SIZE 32 + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_TIME_TYPES_SIZE 32 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES FALSE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS FALSE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT FALSE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES FALSE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_OBJ_FIFOS TRUE + +#define CH_CFG_USE_PIPES TRUE + + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#define CH_CFG_USE_FACTORY FALSE + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 + +/** + * @brief Enables the registry of generic objects. + */ +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE + +/** + * @brief Enables factory for generic buffers. + */ +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE + +/** + * @brief Enables factory for semaphores. + */ +#define CH_CFG_FACTORY_SEMAPHORES TRUE + +/** + * @brief Enables factory for mailboxes. + */ +#define CH_CFG_FACTORY_MAILBOXES TRUE + +/** + * @brief Enables factory for objects FIFOs. + */ +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE + +/** + * @brief Enables factory for Pipes. + */ +#define CH_CFG_FACTORY_PIPES TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/halconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/halconf.h new file mode 100644 index 00000000..fb74d8ed --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/halconf.h @@ -0,0 +1,518 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 64 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + + +// header for nanoFramework overlay +#include "halconf_nf.h" +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/halconf_nf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/halconf_nf.h new file mode 100644 index 00000000..809a6cfa --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/halconf_nf.h @@ -0,0 +1,15 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +#endif // _HALCONF_NF_H_ + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/main.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/main.c new file mode 100644 index 00000000..6c7fd212 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/main.c @@ -0,0 +1,86 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); + +// Application entry point. +int main(void) { + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init SWO as soon as possible to make it available to output ASAP + #if (SWO_OUTPUT == TRUE) + SwoInit(); + #endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + osDelay(20); // Let init stabilize + + // the following IF is not mandatory, it's just providing a way for a user to 'force' + // the board to remain in nanoBooter and not launching nanoCLR + + // if the USER button (blue one) is pressed, skip the check for a valid CLR image and remain in booter + // the user button in this board has a pull-up resistor so the check has to be inverted + if (!palReadLine(LINE_BUTTON_USER)) + { + // check for valid CLR image + // we are checking for a valid image right after the configuration block + if(CheckValidCLRImage((uint32_t)&__nanoConfig_end__)) + { + // there seems to be a valid CLR image + // launch nanoCLR + LaunchCLR((uint32_t)&__nanoConfig_end__); + } + } + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // starts the serial driver + sdStart(&SERIAL_DRIVER, NULL); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + // initialize block storage list and devices + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it in order to provide the flash map for Monitor_FlashSectorMap command + BlockStorageList_Initialize(); + BlockStorage_AddDevices(); + + // initialize configuration manager + // in CLR this is called in nanoHAL_Initialize() + // for nanoBooter we have to init it here to have access to network configuration blocks + ConfigurationManager_Initialize(); + + // Normal main() thread + while (true) { + palSetLine(LINE_LED2_GREEN); + osDelay(500); + palClearLine(LINE_LED2_GREEN); + osDelay(500); + } +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/mcuconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/mcuconf.h new file mode 100644 index 00000000..be56ce44 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/mcuconf.h @@ -0,0 +1,395 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F7xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F7xx_MCUCONF +//#define STM32F765_MCUCONF +//#define STM32F767_MCUCONF +//#define STM32F777_MCUCONF +#define STM32F769_MCUCONF +//#define STM32F779_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 25 +#define STM32_PLLN_VALUE 432 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 9 +#define STM32_PLLR_VALUE 4 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 25 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_I2SSRC STM32_I2SSRC_OFF +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SP_VALUE 4 +#define STM32_PLLI2SQ_VALUE 4 +#define STM32_PLLI2SR_VALUE 4 +#define STM32_PLLI2SDIVQ_VALUE 2 +#define STM32_PLLSAIN_VALUE 192 +#define STM32_PLLSAIP_VALUE 4 +#define STM32_PLLSAIQ_VALUE 4 +#define STM32_PLLSAIR_VALUE 4 +#define STM32_PLLSAIDIVQ_VALUE 2 +#define STM32_PLLSAIDIVR_VALUE 2 +#define STM32_SAI1SEL STM32_SAI1SEL_OFF +#define STM32_SAI2SEL STM32_SAI2SEL_OFF +#define STM32_LCDTFT_REQUIRED FALSE +#define STM32_USART1SEL STM32_USART1SEL_PCLK2 +#define STM32_USART2SEL STM32_USART2SEL_PCLK1 +#define STM32_USART3SEL STM32_USART3SEL_PCLK1 +#define STM32_UART4SEL STM32_UART4SEL_PCLK1 +#define STM32_UART5SEL STM32_UART5SEL_PCLK1 +#define STM32_USART6SEL STM32_USART6SEL_PCLK2 +#define STM32_UART7SEL STM32_UART7SEL_PCLK1 +#define STM32_UART8SEL STM32_UART8SEL_PCLK1 +#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 +#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1 +#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1 +#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1 +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 +#define STM32_CECSEL STM32_CECSEL_LSE +#define STM32_CK48MSEL STM32_CK48MSEL_PLL +#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK +#define STM32_SRAM2_NOCACHE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_USE_CAN3 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 +#define STM32_CAN_CAN3_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_USE_I2C4 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C4_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C4_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 FALSE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000 +#define STM32_SDC_SDMMC_READ_TIMEOUT 1000 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 +#define STM32_SERIAL_UART7_PRIORITY 12 +#define STM32_SERIAL_UART8_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 FALSE +#define STM32_SPI_USE_SPI5 FALSE +#define STM32_SPI_USE_SPI6 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI5_DMA_PRIORITY 1 +#define STM32_SPI_SPI6_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USE_UART7 FALSE +#define STM32_UART_USE_UART8 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_UART7_IRQ_PRIORITY 12 +#define STM32_UART_UART8_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_UART7_DMA_PRIORITY 0 +#define STM32_UART_UART8_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +/* + * WSPI driver system settings. + */ +#define STM32_WSPI_USE_QUADSPI1 FALSE +#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) + +#endif /* MCUCONF_H */ \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/mcuconf_nf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/mcuconf_nf.h new file mode 100644 index 00000000..5ff03534 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/mcuconf_nf.h @@ -0,0 +1,9 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ + +#endif // _MCUCONF_NF_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/target_board.h.in b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/target_board.h.in new file mode 100644 index 00000000..19531d9c --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoBooter/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOBOOTER_H_ +#define _TARGET_BOARD_NANOBOOTER_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoBooter running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOBOOTER_H_ */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/CMakeLists.txt new file mode 100644 index 00000000..e5496b7e --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/STM32F76xx_CLR-DEBUG.ld b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/STM32F76xx_CLR-DEBUG.ld new file mode 100644 index 00000000..63725eeb --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/STM32F76xx_CLR-DEBUG.ld @@ -0,0 +1,128 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F76xxI generic setup. + * + * RAM0 - Data, Heap. + * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. + * + * Notes: + * BSS is placed in DTCM RAM in order to simplify DMA buffers management. + */ +MEMORY +{ + flash : org = 0x08010000, len = 2M - 32k - 32k - 1280k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + flash_itcm : org = 0x00210000, len = 2M - 32k - 32k - 1280k + config : org = 0x08008000, len = 32k /* space reserved for configuration block */ + deployment : org = 0x080C0000, len = 1280k /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ + ram1 : org = 0x20020000, len = 368k /* SRAM1 */ + ram2 : org = 0x2007C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20000000, len = 128k /* DTCM-RAM */ + ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 + ext_ram : org = 0xC0000000, len = 16M /* external SDRAM */ +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash_itcm); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash_itcm); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash_itcm); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash_itcm); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram3); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram3); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram3); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ext_ram); + +/* rules inclusion.*/ +INCLUDE rules_stacks.ld + +/*===========================================================================*/ +/* Custom sections for STM32F7xx. */ +/*===========================================================================*/ + +/* RAM region to be used for nocache segment.*/ +REGION_ALIAS("NOCACHE_RAM", ram3); + +/* RAM region to be used for eth segment.*/ +REGION_ALIAS("ETH_RAM", ram3); + +SECTIONS +{ + /* Special section for non cache-able areas.*/ + .nocache (NOLOAD) : ALIGN(4) + { + __nocache_base__ = .; + *(.nocache) + *(.nocache.*) + *(.bss.__nocache_*) + . = ALIGN(4); + __nocache_end__ = .; + } > NOCACHE_RAM + + /* Special section for Ethernet DMA non cache-able areas.*/ + .eth (NOLOAD) : ALIGN(4) + { + __eth_base__ = .; + *(.eth) + *(.eth.*) + *(.bss.__eth_*) + . = ALIGN(4); + __eth_end__ = .; + } > ETH_RAM +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld + +/* nanoCLR rules inclusion.*/ +INCLUDE rules_clr.ld diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/STM32F76xx_CLR.ld b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/STM32F76xx_CLR.ld new file mode 100644 index 00000000..3bc7ae37 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/STM32F76xx_CLR.ld @@ -0,0 +1,128 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* + * STM32F76xxI generic setup. + * + * RAM0 - Data, Heap. + * RAM3 - Main Stack, Process Stack, BSS, NOCACHE, ETH. + * + * Notes: + * BSS is placed in DTCM RAM in order to simplify DMA buffers management. + */ +MEMORY +{ + flash : org = 0x08010000, len = 2M - 32k - 32k - 1536k /* flash size less the space reserved for nanoBooter, configuration block and application deployment*/ + flash_itcm : org = 0x00210000, len = 2M - 32k - 32k - 1536k + config : org = 0x08008000, len = 32k /* space reserved for configuration block */ + deployment : org = 0x08080000, len = 1536k /* space reserved for application deployment */ + ramvt : org = 0x00000000, len = 0 /* initial RAM address is reserved for a copy of the vector table */ + ram0 : org = 0x20020000, len = 384k /* SRAM1 + SRAM2 */ + ram1 : org = 0x20020000, len = 368k /* SRAM1 */ + ram2 : org = 0x2007C000, len = 16k /* SRAM2 */ + ram3 : org = 0x20000000, len = 128k /* DTCM-RAM */ + ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */ + ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 + ext_ram : org = 0xC0000000, len = 16M /* external SDRAM */ +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash_itcm); +REGION_ALIAS("VECTORS_FLASH_LMA", flash); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash_itcm); +REGION_ALIAS("XTORS_FLASH_LMA", flash); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash_itcm); +REGION_ALIAS("TEXT_FLASH_LMA", flash); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash); +REGION_ALIAS("RODATA_FLASH_LMA", flash); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash_itcm); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram3); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram3); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram3); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", ext_ram); + +/* rules inclusion.*/ +INCLUDE rules_stacks.ld + +/*===========================================================================*/ +/* Custom sections for STM32F7xx. */ +/*===========================================================================*/ + +/* RAM region to be used for nocache segment.*/ +REGION_ALIAS("NOCACHE_RAM", ram3); + +/* RAM region to be used for eth segment.*/ +REGION_ALIAS("ETH_RAM", ram3); + +SECTIONS +{ + /* Special section for non cache-able areas.*/ + .nocache (NOLOAD) : ALIGN(4) + { + __nocache_base__ = .; + *(.nocache) + *(.nocache.*) + *(.bss.__nocache_*) + . = ALIGN(4); + __nocache_end__ = .; + } > NOCACHE_RAM + + /* Special section for Ethernet DMA non cache-able areas.*/ + .eth (NOLOAD) : ALIGN(4) + { + __eth_base__ = .; + *(.eth) + *(.eth.*) + *(.bss.__eth_*) + . = ALIGN(4); + __eth_end__ = .; + } > ETH_RAM +} + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld + +/* nanoCLR rules inclusion.*/ +INCLUDE rules_clr.ld diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/chconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/chconf.h new file mode 100644 index 00000000..214cbcd6 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/chconf.h @@ -0,0 +1,705 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM FALSE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY FALSE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + // this field is required in case lwIP options has LWIP_NETCONN_SEM_PER_THREAD + // void* localStorage; + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/halconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/halconf.h new file mode 100644 index 00000000..32abfdc5 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/halconf.h @@ -0,0 +1,535 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +#if !defined(FATFS_HAL_DEVICE) || defined(__DOXYGEN__) +//this board requires SDCD2 not SDCD1 +#define FATFS_HAL_DEVICE SDCD2 +#endif + +//#define STM32_SDC_SDMMC_50MHZ TRUE + +/** + * @brief Enables the ADC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +// #define HAL_USE_ADC FALSE +// #endif + +/** + * @brief Enables the CAN subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +// #define HAL_USE_CAN FALSE +// #endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +// /** +// * @brief Enables the DAC subsystem. +// */ +// #if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +// #define HAL_USE_DAC FALSE +// #endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +// this option is set at target_platform.h (from config file) +//#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +//#define HAL_USE_I2C TRUE +//#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +// #define HAL_USE_MAC TRUE +// #endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +// #define HAL_USE_PWM FALSE +// #endif + +/** + * @brief Enables the RTC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +// #define HAL_USE_RTC TRUE +// #endif + +/** + * @brief Enables the SDC subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +// #define HAL_USE_SDC TRUE +// #endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +// #define HAL_USE_SPI FALSE +// #endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +// #define HAL_USE_UART FALSE +// #endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +// this option is set at target_platform.h (from config file) +// #if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +// #define HAL_USE_WDG FALSE +// #endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS TRUE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 921600 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 64 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 64 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 1 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +// header for nanoFramework overlay +#include "halconf_nf.h" +#endif /* HALCONF_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/halconf_nf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/halconf_nf.h new file mode 100644 index 00000000..c2edaf78 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/halconf_nf.h @@ -0,0 +1,29 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _HALCONF_NF_H_ +#define _HALCONF_NF_H_ 1 + +// enables STM32 Flash driver +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH TRUE +#endif + +// Enables the FSMC subsystem. +#if !defined(HAL_USE_FSMC) +#define HAL_USE_FSMC TRUE +#endif + +// enables STM32 Can driver +#if !defined(HAL_USE_STM32_CAN) +#define HAL_USE_STM32_CAN TRUE +#endif + +// enables STM32 QSPI driver +#if !defined(HAL_USE_STM32_QSPI) +#define HAL_USE_STM32_QSPI FALSE +#endif + +#endif // _HALCONF_NF_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/main.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/main.c new file mode 100644 index 00000000..b7bd381f --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/main.c @@ -0,0 +1,101 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +extern uint8_t hal_spiffs_config(); + +// need to declare the Receiver thread here +osThreadDef(ReceiverThread, osPriorityHigh, 2048, "ReceiverThread"); +// declare CLRStartup thread here +osThreadDef(CLRStartupThread, osPriorityNormal, 4096, "CLRStartupThread"); + +#if HAL_USE_SDC +// declare SD Card working thread here +osThreadDef(SdCardWorkingThread, osPriorityNormal, 1024, "SDCWT"); +#endif +#if HAL_USBH_USE_MSD +// declare USB MSD thread here +osThreadDef(UsbMsdWorkingThread, osPriorityNormal, 1024, "USBMSDWT"); +#endif + +// Application entry point. +int main(void) { + + // HAL initialization, this also initializes the configured device drivers + // and performs the board-specific initializations. + halInit(); + + // init SWO as soon as possible to make it available to output ASAP + #if (SWO_OUTPUT == TRUE) + SwoInit(); + #endif + + // The kernel is initialized but not started yet, this means that + // main() is executing with absolute priority but interrupts are already enabled. + osKernelInitialize(); + + // start watchdog + Watchdog_Init(); + + // config and init external memory + // this has to be called after osKernelInitialize, otherwise an hard fault will occur + Target_ExternalMemoryInit(); + + #if NF_FEATURE_USE_SPIFFS + // config and init SPIFFS + hal_spiffs_config(); + #endif + + // starts the serial driver + sdStart(&SERIAL_DRIVER, NULL); + + // create the receiver thread + osThreadCreate(osThread(ReceiverThread), NULL); + + // CLR settings to launch CLR thread + CLR_SETTINGS clrSettings; + (void)memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.EnterDebuggerLoopAfterExit = true; + + // create the CLR Startup thread + osThreadCreate(osThread(CLRStartupThread), &clrSettings); + + #if HAL_USE_SDC + // creates the SD card working thread + osThreadCreate(osThread(SdCardWorkingThread), NULL); + #endif + + #if HAL_USBH_USE_MSD + // create the USB MSD working thread + osThreadCreate(osThread(UsbMsdWorkingThread), &MSBLKD[0]); + #endif + + // start kernel, after this main() will behave like a thread with priority osPriorityNormal + osKernelStart(); + + while (true) { + osDelay(100); + } +} \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h new file mode 100644 index 00000000..2853d5c5 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf.h @@ -0,0 +1,404 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F7xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F7xx_MCUCONF +//#define STM32F765_MCUCONF +//#define STM32F767_MCUCONF +//#define STM32F777_MCUCONF +#define STM32F769_MCUCONF +//#define STM32F779_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 25 +#define STM32_PLLN_VALUE 384 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 8 +#define STM32_PLLR_VALUE 2 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 25 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV1 +#define STM32_I2SSRC STM32_I2SSRC_OFF +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SP_VALUE 2 +#define STM32_PLLI2SQ_VALUE 2 +#define STM32_PLLI2SR_VALUE 2 +#define STM32_PLLI2SDIVQ_VALUE 1 +#define STM32_PLLSAIN_VALUE 192 +#define STM32_PLLSAIP_VALUE 4 +#define STM32_PLLSAIQ_VALUE 3 +#define STM32_PLLSAIR_VALUE 2 +#define STM32_PLLSAIDIVQ_VALUE 1 +#define STM32_PLLSAIDIVR_VALUE 2 +#define STM32_SAI1SEL STM32_SAI1SEL_SAIPLL +#define STM32_SAI2SEL STM32_SAI2SEL_SAIPLL +#define STM32_LCDTFT_REQUIRED FALSE +#define STM32_USART1SEL STM32_USART1SEL_PCLK2 +#define STM32_USART2SEL STM32_USART2SEL_PCLK1 +#define STM32_USART3SEL STM32_USART3SEL_PCLK1 +#define STM32_UART4SEL STM32_UART4SEL_PCLK1 +#define STM32_UART5SEL STM32_UART5SEL_PCLK1 +#define STM32_USART6SEL STM32_USART6SEL_PCLK2 +#define STM32_UART7SEL STM32_UART7SEL_PCLK1 +#define STM32_UART8SEL STM32_UART8SEL_PCLK1 +#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 +#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1 +#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1 +#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1 +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 +#define STM32_CECSEL STM32_CECSEL_LSE +#define STM32_CK48MSEL STM32_CK48MSEL_PLL +#define STM32_SDMMC1SEL STM32_SDMMC1SEL_PLL48CLK +#define STM32_SDMMC2SEL STM32_SDMMC2SEL_PLL48CLK +#define STM32_SRAM2_NOCACHE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 TRUE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 TRUE +#define STM32_CAN_USE_CAN2 TRUE +#define STM32_CAN_USE_CAN3 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 +#define STM32_CAN_CAN3_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 TRUE +#define STM32_DAC_USE_DAC1_CH2 TRUE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 TRUE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_USE_I2C4 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C4_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C4_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED TRUE +#define STM32_PWM_USE_TIM1 TRUE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 TRUE +#define STM32_PWM_USE_TIM5 TRUE +#define STM32_PWM_USE_TIM8 TRUE +#define STM32_PWM_USE_TIM9 TRUE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 FALSE +#define STM32_SDC_USE_SDMMC2 TRUE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000 +#define STM32_SDC_SDMMC_READ_TIMEOUT 1000 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SDC_SDMMC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC2_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 +#define STM32_SDC_SDMMC2_IRQ_PRIORITY 9 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 +#define STM32_SERIAL_UART7_PRIORITY 12 +#define STM32_SERIAL_UART8_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 FALSE +#define STM32_SPI_USE_SPI5 FALSE +#define STM32_SPI_USE_SPI6 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI5_DMA_PRIORITY 1 +#define STM32_SPI_SPI6_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 TRUE +#define STM32_UART_USE_USART3 TRUE +#define STM32_UART_USE_UART4 TRUE +#define STM32_UART_USE_UART5 TRUE +#define STM32_UART_USE_USART6 TRUE +#define STM32_UART_USE_UART7 TRUE +#define STM32_UART_USE_UART8 TRUE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_UART7_IRQ_PRIORITY 12 +#define STM32_UART_UART8_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_UART7_DMA_PRIORITY 0 +#define STM32_UART_UART8_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG TRUE + +/* + * WSPI driver system settings. + */ +#define STM32_WSPI_USE_QUADSPI1 FALSE +#define STM32_WSPI_QUADSPI1_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE 2 + +// header for nanoFramework overlay drivers +#include "mcuconf_nf.h" + +#endif /* MCUCONF_H */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf_nf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf_nf.h new file mode 100644 index 00000000..bf6b31e3 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/mcuconf_nf.h @@ -0,0 +1,22 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _MCUCONF_NF_H_ +#define _MCUCONF_NF_H_ +/* + * FSMC driver system settings. + */ +#define STM32_FSMC_USE_FSMC1 TRUE +#define STM32_FSMC_FSMC1_IRQ_PRIORITY 10 +#define STM32_FSMC_DMA_CHN 0x03010201 + +/* + * FSMC SDRAM driver system settings. + */ +#define STM32_USE_FSMC_SDRAM TRUE +#define STM32_SDRAM_USE_FSMC_SDRAM1 TRUE +#define STM32_SDRAM_USE_FSMC_SDRAM2 FALSE + +#endif // _MCUCONF_NF_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/nanoHAL.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/nanoHAL.cpp new file mode 100644 index 00000000..076a50fc --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/nanoHAL.cpp @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +void HAL_EnterBooterMode() +{ +} + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/target_board.h.in b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/target_board.h.in new file mode 100644 index 00000000..b980bc05 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/nanoCLR/target_board.h.in @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include +#include + +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @CHIBIOS_BOARD@ built with ChibiOS v" CH_VERSION "." STR(CH_VERSION_MONTH) + +#endif /* _TARGET_BOARD_NANOCLR_H_ */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/spiffs_config.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/spiffs_config.h new file mode 100644 index 00000000..f0fba80b --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/spiffs_config.h @@ -0,0 +1,378 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2013, petera, All Rights Reserved +// See LICENSE file in the project root for full license information. +// + + +///////////////////////////////////////////////////////////////////////////// +// the configurations below are tunned for the MX25L51245G (from MACRONIX) +// that's fitted in the STM32F769I-DISCO board +///////////////////////////////////////////////////////////////////////////// + +#ifndef SPIFFS_CONFIG_H_ +#define SPIFFS_CONFIG_H_ + +#include +#include +#include +#include +#include + +///////////////////////////////////// +// need to map these types +typedef int32_t s32_t; +typedef uint32_t u32_t; +typedef int16_t s16_t; +typedef uint16_t u16_t; +typedef int8_t s8_t; +typedef uint8_t u8_t; + +// compile time switches + +// Set generic spiffs debug output call. +#ifndef SPIFFS_DBG +#define SPIFFS_DBG(_f, ...) //printf(_f, ## __VA_ARGS__) +#endif +// Set spiffs debug output call for garbage collecting. +#ifndef SPIFFS_GC_DBG +#define SPIFFS_GC_DBG(_f, ...) //printf(_f, ## __VA_ARGS__) +#endif +// Set spiffs debug output call for caching. +#ifndef SPIFFS_CACHE_DBG +#define SPIFFS_CACHE_DBG(_f, ...) //printf(_f, ## __VA_ARGS__) +#endif +// Set spiffs debug output call for system consistency checks. +#ifndef SPIFFS_CHECK_DBG +#define SPIFFS_CHECK_DBG(_f, ...) //printf(_f, ## __VA_ARGS__) +#endif +// Set spiffs debug output call for all api invocations. +#ifndef SPIFFS_API_DBG +#define SPIFFS_API_DBG(_f, ...) //printf(_f, ## __VA_ARGS__) +#endif + + + +// Defines spiffs debug print formatters +// some general signed number +#ifndef _SPIPRIi +#define _SPIPRIi "%d" +#endif +// address +#ifndef _SPIPRIad +#define _SPIPRIad "%08x" +#endif +// block +#ifndef _SPIPRIbl +#define _SPIPRIbl "%04x" +#endif +// page +#ifndef _SPIPRIpg +#define _SPIPRIpg "%04x" +#endif +// span index +#ifndef _SPIPRIsp +#define _SPIPRIsp "%04x" +#endif +// file descriptor +#ifndef _SPIPRIfd +#define _SPIPRIfd "%d" +#endif +// file object id +#ifndef _SPIPRIid +#define _SPIPRIid "%04x" +#endif +// file flags +#ifndef _SPIPRIfl +#define _SPIPRIfl "%02x" +#endif + + +// Enable/disable API functions to determine exact number of bytes +// for filedescriptor and cache buffers. Once decided for a configuration, +// this can be disabled to reduce flash. +#ifndef SPIFFS_BUFFER_HELP +#define SPIFFS_BUFFER_HELP 0 +#endif + +// Enables/disable memory read caching of nucleus file system operations. +// If enabled, memory area must be provided for cache in SPIFFS_mount. +#ifndef SPIFFS_CACHE +#define SPIFFS_CACHE 1 +#endif +#if SPIFFS_CACHE +// Enables memory write caching for file descriptors in hydrogen +#ifndef SPIFFS_CACHE_WR +#define SPIFFS_CACHE_WR 1 +#endif + +// Enable/disable statistics on caching. Debug/test purpose only. +#ifndef SPIFFS_CACHE_STATS +#define SPIFFS_CACHE_STATS 1 +#endif +#endif + +// Always check header of each accessed page to ensure consistent state. +// If enabled it will increase number of reads, will increase flash. +#ifndef SPIFFS_PAGE_CHECK +#define SPIFFS_PAGE_CHECK 1 +#endif + +// Define maximum number of gc runs to perform to reach desired free pages. +#ifndef SPIFFS_GC_MAX_RUNS +#define SPIFFS_GC_MAX_RUNS 5 +#endif + +// Enable/disable statistics on gc. Debug/test purpose only. +#ifndef SPIFFS_GC_STATS +#define SPIFFS_GC_STATS 1 +#endif + +// Garbage collecting examines all pages in a block which and sums up +// to a block score. Deleted pages normally gives positive score and +// used pages normally gives a negative score (as these must be moved). +// To have a fair wear-leveling, the erase age is also included in score, +// whose factor normally is the most positive. +// The larger the score, the more likely it is that the block will +// picked for garbage collection. + +// Garbage collecting heuristics - weight used for deleted pages. +#ifndef SPIFFS_GC_HEUR_W_DELET +#define SPIFFS_GC_HEUR_W_DELET (5) +#endif +// Garbage collecting heuristics - weight used for used pages. +#ifndef SPIFFS_GC_HEUR_W_USED +#define SPIFFS_GC_HEUR_W_USED (-1) +#endif +// Garbage collecting heuristics - weight used for time between +// last erased and erase of this block. +#ifndef SPIFFS_GC_HEUR_W_ERASE_AGE +#define SPIFFS_GC_HEUR_W_ERASE_AGE (50) +#endif + +// Object name maximum length. Note that this length include the +// zero-termination character, meaning maximum string of characters +// can at most be SPIFFS_OBJ_NAME_LEN - 1. +#ifndef SPIFFS_OBJ_NAME_LEN +#define SPIFFS_OBJ_NAME_LEN (256) +#endif + +// Maximum length of the metadata associated with an object. +// Setting to non-zero value enables metadata-related API but also +// changes the on-disk format, so the change is not backward-compatible. +// +// Do note: the meta length must never exceed +// logical_page_size - (SPIFFS_OBJ_NAME_LEN + 64) +// +// This is derived from following: +// logical_page_size - (SPIFFS_OBJ_NAME_LEN + sizeof(spiffs_page_header) + +// spiffs_object_ix_header fields + at least some LUT entries) +#ifndef SPIFFS_OBJ_META_LEN +#define SPIFFS_OBJ_META_LEN (0) +#endif + +// Size of buffer allocated on stack used when copying data. +// Lower value generates more read/writes. No meaning having it bigger +// than logical page size. +#ifndef SPIFFS_COPY_BUFFER_STACK +#define SPIFFS_COPY_BUFFER_STACK (64) +#endif + +// Enable this to have an identifiable spiffs filesystem. This will look for +// a magic in all sectors to determine if this is a valid spiffs system or +// not on mount point. If not, SPIFFS_format must be called prior to mounting +// again. +#ifndef SPIFFS_USE_MAGIC +#define SPIFFS_USE_MAGIC (0) +#endif + +#if SPIFFS_USE_MAGIC +// Only valid when SPIFFS_USE_MAGIC is enabled. If SPIFFS_USE_MAGIC_LENGTH is +// enabled, the magic will also be dependent on the length of the filesystem. +// For example, a filesystem configured and formatted for 4 megabytes will not +// be accepted for mounting with a configuration defining the filesystem as 2 +// megabytes. +#ifndef SPIFFS_USE_MAGIC_LENGTH +#define SPIFFS_USE_MAGIC_LENGTH (0) +#endif +#endif + +// SPIFFS_LOCK and SPIFFS_UNLOCK protects spiffs from reentrancy on api level +// These should be defined on a multithreaded system + +// define this to enter a mutex if you're running on a multithreaded system +#ifndef SPIFFS_LOCK +extern void hal_spiffs_lock(); +#define SPIFFS_LOCK(fs) hal_spiffs_lock(); +#endif +// define this to exit a mutex if you're running on a multithreaded system +#ifndef SPIFFS_UNLOCK +extern void hal_spiffs_unlock(); +#define SPIFFS_UNLOCK(fs) hal_spiffs_unlock(); +#endif + +// Enable if only one spiffs instance with constant configuration will exist +// on the target. This will reduce calculations, flash and memory accesses. +// Parts of configuration must be defined below instead of at time of mount. +#ifndef SPIFFS_SINGLETON +#define SPIFFS_SINGLETON 0 +#endif + +#if SPIFFS_SINGLETON +// Instead of giving parameters in config struct, singleton build must +// give parameters in defines below. +#ifndef SPIFFS_CFG_PHYS_SZ +#define SPIFFS_CFG_PHYS_SZ(ignore) (1024*1024*2) +#endif +#ifndef SPIFFS_CFG_PHYS_ERASE_SZ +#define SPIFFS_CFG_PHYS_ERASE_SZ(ignore) (65536) +#endif +#ifndef SPIFFS_CFG_PHYS_ADDR +#define SPIFFS_CFG_PHYS_ADDR(ignore) (0) +#endif +#ifndef SPIFFS_CFG_LOG_PAGE_SZ +#define SPIFFS_CFG_LOG_PAGE_SZ(ignore) (256) +#endif +#ifndef SPIFFS_CFG_LOG_BLOCK_SZ +#define SPIFFS_CFG_LOG_BLOCK_SZ(ignore) (65536) +#endif +#endif + +// Enable this if your target needs aligned data for index tables +#ifndef SPIFFS_ALIGNED_OBJECT_INDEX_TABLES +#define SPIFFS_ALIGNED_OBJECT_INDEX_TABLES 0 +#endif + +// Enable this if you want the HAL callbacks to be called with the spiffs struct +#ifndef SPIFFS_HAL_CALLBACK_EXTRA +#define SPIFFS_HAL_CALLBACK_EXTRA 0 +#endif + +// Enable this if you want to add an integer offset to all file handles +// (spiffs_file). This is useful if running multiple instances of spiffs on +// same target, in order to recognise to what spiffs instance a file handle +// belongs. +// NB: This adds config field fh_ix_offset in the configuration struct when +// mounting, which must be defined. +#ifndef SPIFFS_FILEHDL_OFFSET +#define SPIFFS_FILEHDL_OFFSET 0 +#endif + +// Enable this to compile a read only version of spiffs. +// This will reduce binary size of spiffs. All code comprising modification +// of the file system will not be compiled. Some config will be ignored. +// HAL functions for erasing and writing to spi-flash may be null. Cache +// can be disabled for even further binary size reduction (and ram savings). +// Functions modifying the fs will return SPIFFS_ERR_RO_NOT_IMPL. +// If the file system cannot be mounted due to aborted erase operation and +// SPIFFS_USE_MAGIC is enabled, SPIFFS_ERR_RO_ABORTED_OPERATION will be +// returned. +// Might be useful for e.g. bootloaders and such. +#ifndef SPIFFS_READ_ONLY +#define SPIFFS_READ_ONLY 0 +#endif + +// Enable this to add a temporal file cache using the fd buffer. +// The effects of the cache is that SPIFFS_open will find the file faster in +// certain cases. It will make it a lot easier for spiffs to find files +// opened frequently, reducing number of readings from the spi flash for +// finding those files. +// This will grow each fd by 6 bytes. If your files are opened in patterns +// with a degree of temporal locality, the system is optimized. +// Examples can be letting spiffs serve web content, where one file is the css. +// The css is accessed for each html file that is opened, meaning it is +// accessed almost every second time a file is opened. Another example could be +// a log file that is often opened, written, and closed. +// The size of the cache is number of given file descriptors, as it piggybacks +// on the fd update mechanism. The cache lives in the closed file descriptors. +// When closed, the fd know the whereabouts of the file. Instead of forgetting +// this, the temporal cache will keep handling updates to that file even if the +// fd is closed. If the file is opened again, the location of the file is found +// directly. If all available descriptors become opened, all cache memory is +// lost. +#ifndef SPIFFS_TEMPORAL_FD_CACHE +#define SPIFFS_TEMPORAL_FD_CACHE 1 +#endif + +// Temporal file cache hit score. Each time a file is opened, all cached files +// will lose one point. If the opened file is found in cache, that entry will +// gain SPIFFS_TEMPORAL_CACHE_HIT_SCORE points. One can experiment with this +// value for the specific access patterns of the application. However, it must +// be between 1 (no gain for hitting a cached entry often) and 255. +#ifndef SPIFFS_TEMPORAL_CACHE_HIT_SCORE +#define SPIFFS_TEMPORAL_CACHE_HIT_SCORE 4 +#endif + +// Enable to be able to map object indices to memory. +// This allows for faster and more deterministic reading if cases of reading +// large files and when changing file offset by seeking around a lot. +// When mapping a file's index, the file system will be scanned for index pages +// and the info will be put in memory provided by user. When reading, the +// memory map can be looked up instead of searching for index pages on the +// medium. This way, user can trade memory against performance. +// Whole, parts of, or future parts not being written yet can be mapped. The +// memory array will be owned by spiffs and updated accordingly during garbage +// collecting or when modifying the indices. The latter is invoked by when the +// file is modified in some way. The index buffer is tied to the file +// descriptor. +#ifndef SPIFFS_IX_MAP +#define SPIFFS_IX_MAP 1 +#endif + +// By default SPIFFS in some cases relies on the property of NOR flash that bits +// cannot be set from 0 to 1 by writing and that controllers will ignore such +// bit changes. This results in fewer reads as SPIFFS can in some cases perform +// blind writes, with all bits set to 1 and only those it needs reset set to 0. +// Most of the chips and controllers allow this behavior, so the default is to +// use this technique. If your controller is one of the rare ones that don't, +// turn this option on and SPIFFS will perform a read-modify-write instead. +#ifndef SPIFFS_NO_BLIND_WRITES +#define SPIFFS_NO_BLIND_WRITES 0 +#endif + +// SPIFFS_vis disabled +#define SPIFFS_TEST_VISUALISATION 0 + +#if SPIFFS_TEST_VISUALISATION +#ifndef spiffs_printf +#define spiffs_printf(...) printf(__VA_ARGS__) +#endif +// spiffs_printf argument for a free page +#ifndef SPIFFS_TEST_VIS_FREE_STR +#define SPIFFS_TEST_VIS_FREE_STR "_" +#endif +// spiffs_printf argument for a deleted page +#ifndef SPIFFS_TEST_VIS_DELE_STR +#define SPIFFS_TEST_VIS_DELE_STR "/" +#endif +// spiffs_printf argument for an index page for given object id +#ifndef SPIFFS_TEST_VIS_INDX_STR +#define SPIFFS_TEST_VIS_INDX_STR(id) "i" +#endif +// spiffs_printf argument for a data page for given object id +#ifndef SPIFFS_TEST_VIS_DATA_STR +#define SPIFFS_TEST_VIS_DATA_STR(id) "d" +#endif +#endif + +// Types depending on configuration such as the amount of flash bytes +// given to spiffs file system in total (spiffs_file_system_size), +// the logical block size (log_block_size), and the logical page size +// (log_page_size) + +// Block index type. Make sure the size of this type can hold +// the highest number of all blocks - i.e. spiffs_file_system_size / log_block_size +typedef u16_t spiffs_block_ix; +// Page index type. Make sure the size of this type can hold +// the highest page number of all pages - i.e. spiffs_file_system_size / log_page_size +typedef u16_t spiffs_page_ix; +// Object id type - most significant bit is reserved for index flag. Make sure the +// size of this type can hold the highest object id on a full system, +// i.e. 2 + (spiffs_file_system_size / (2*log_page_size))*2 +typedef u16_t spiffs_obj_id; +// Object span index type. Make sure the size of this type can +// hold the largest possible span index on the system - +// i.e. (spiffs_file_system_size / log_page_size) - 1 +typedef u16_t spiffs_span_ix; + +#endif /* SPIFFS_CONFIG_H_ */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/stm32f7xx_hal_conf.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/stm32f7xx_hal_conf.h new file mode 100644 index 00000000..a6c88c05 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/stm32f7xx_hal_conf.h @@ -0,0 +1,56 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2016 STMicroelectronics. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef __STM32F7xx_HAL_CONF_H +#define __STM32F7xx_HAL_CONF_H + +#define STM32F769xx + +#ifdef __cplusplus + extern "C" { +#endif + +#define HAL_DMA_MODULE_ENABLED +#define HAL_QSPI_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED + +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + + +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + + +#ifdef __cplusplus +} +#endif + +#endif // __STM32F7xx_HAL_CONF_H diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_BlockStorage.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_BlockStorage.c new file mode 100644 index 00000000..9e7c7f55 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_BlockStorage.c @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice STM32Flash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &STM32Flash_BlockStorageInterface, &Device_BlockStorageConfig, false); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_BlockStorage.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_BlockStorage.h new file mode 100644 index 00000000..aa50b1b7 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_common.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_common.c new file mode 100644 index 00000000..ee602ba0 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_common.c @@ -0,0 +1,24 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include "target_common.h" + +HAL_SYSTEM_CONFIG HalSystemConfig = +{ + { true }, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, //ConvertCOM_DebugHandle(1), + 0,//ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + { RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size }, + { FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size } +}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_common.h.in b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_common.h.in new file mode 100644 index 00000000..ec25526b --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_common.h.in @@ -0,0 +1,45 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0xC0000000) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x01000000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x08000000) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x00200000) + +///////////////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////// +#define TARGETNAMESTRING "@CHIBIOS_BOARD@" +#define PLATFORMNAMESTRING "STM32F7" +////////////////////////////////////////////// + +///////////////////////////////////// +#define PLATFORM_HAS_RNG TRUE +///////////////////////////////////// + +///////////////////////////////////// +//#define EVENTS_HEART_BEAT palToggleLine(LINE_LED2_GREEN) +///////////////////////////////////// + +#endif /* _TARGET_COMMON_H_ */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_external_memory.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_external_memory.c new file mode 100644 index 00000000..299fe1ef --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_external_memory.c @@ -0,0 +1,111 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "hal.h" +#include "fsmc_sdram_lld.h" + + +// SDRAM Mode definition register defines +#define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001) +#define FMC_SDCMR_MRD_BURST_LENGTH_4 ((uint16_t)0x0002) +#define FMC_SDCMR_MRD_BURST_LENGTH_8 ((uint16_t)0x0004) +#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define FMC_SDCMR_MRD_CAS_LATENCY_2 ((uint16_t)0x0020) +#define FMC_SDCMR_MRD_CAS_LATENCY_3 ((uint16_t)0x0030) +#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) + +// FMC_ReadPipe_Delay +#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000) +#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000) +#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000) +#define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000) + +// FMC_Read_Burst +#define FMC_Read_Burst_Disable ((uint32_t)0x00000000) +#define FMC_Read_Burst_Enable ((uint32_t)0x00001000) +#define FMC_Read_Burst_Mask ((uint32_t)0x00001000) + +// FMC_SDClock_Period +#define FMC_SDClock_Disable ((uint32_t)0x00000000) +#define FMC_SDClock_Period_2 ((uint32_t)0x00000800) +#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00) +#define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00) + +// FMC_ColumnBits_Number +#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000) +#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001) +#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002) +#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003) + +// FMC_RowBits_Number +#define FMC_RowBits_Number_11b ((uint32_t)0x00000000) +#define FMC_RowBits_Number_12b ((uint32_t)0x00000004) +#define FMC_RowBits_Number_13b ((uint32_t)0x00000008) + +// FMC_SDMemory_Data_Width +#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000) +#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010) +#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020) + +// FMC_InternalBank_Number +#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000) +#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040) + +// FMC_CAS_Latency +#define FMC_CAS_Latency_1 ((uint32_t)0x00000080) +#define FMC_CAS_Latency_2 ((uint32_t)0x00000100) +#define FMC_CAS_Latency_3 ((uint32_t)0x00000180) + +// FMC_Write_Protection +#define FMC_Write_Protection_Disable ((uint32_t)0x00000000) +#define FMC_Write_Protection_Enable ((uint32_t)0x00000200) + +#define SDRAM_SIZE (16 * 1024 * 1024) +#define SDRAM_START ((void *)FSMC_Bank5_MAP_BASE) + + +// SDRAM driver configuration structure. +static const SDRAMConfig sdram_cfg = { + .sdcr = (uint32_t) FMC_ColumnBits_Number_8b | + FMC_RowBits_Number_12b | + FMC_SDMemory_Width_32b | + FMC_InternalBank_Number_4 | + FMC_CAS_Latency_3 | + FMC_Write_Protection_Disable | + FMC_SDClock_Period_2 | + FMC_Read_Burst_Enable | + FMC_ReadPipe_Delay_0, + .sdtr = (uint32_t) (2 - 1) | // FMC_LoadToActiveDelay = 2 (TMRD: 2 Clock cycles) + (7 << 4) | // FMC_ExitSelfRefreshDelay = 7 (TXSR: min=70ns (7x11.11ns)) + (4 << 8) | // FMC_SelfRefreshTime = 4 (TRAS: min=42ns (4x11.11ns) max=120k (ns)) + (7 << 12) | // FMC_RowCycleDelay = 7 (TRC: min=70 (7x11.11ns)) + (3 << 16) | // FMC_WriteRecoveryTime = 2 (TWR: min=1+ 7ns (1+1x11.11ns)) + (2 << 20) | // FMC_RPDelay = 2 (TRP: 20ns => 2x11.11ns) + (2 << 24), // FMC_RCDDelay = 2 (TRCD: 20ns => 2x11.11ns) + // NRFS = 4-1 + .sdcmr = (3 << 5) | (FMC_SDCMR_MRD_BURST_LENGTH_2 | + FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL | + FMC_SDCMR_MRD_CAS_LATENCY_3 | + FMC_SDCMR_MRD_OPERATING_MODE_STANDARD | + FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE) << 9, + + .sdrtr = (uint32_t)(683 << 1), +}; + +void Target_ExternalMemoryInit() +{ + fsmcSdramInit(); + + // FIXME + // this swaps SDRAM address to 0x60000000 and makes it L1 cacheable + //SYSCFG->MEMRMP |= SYSCFG_MEMRMP_SWP_FMC_0; + + fsmcSdramStart(&SDRAMD, &sdram_cfg); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_lwip_sntp_opts.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_lwip_sntp_opts.h new file mode 100644 index 00000000..c115cd67 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_lwip_sntp_opts.h @@ -0,0 +1,18 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#define SNTP_SERVER_DEFAULT_ADDRESS "0.pool.ntp.org" + +// update delay (default 1 hour) +// (value in milliseconds) +#define SNTP_UPDATE_DELAY 3600000 + +// better have a startup delay because we can have DHCP enabled (default 30 seconds) +// value in milliseconds +#define SNTP_STARTUP_DELAY 30000 + +// retry timeout (15 minutes) +// value in milliseconds +#define SNTP_RETRY_TIMEOUT 900000 diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_nf_devices_can_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_nf_devices_can_config.cpp new file mode 100644 index 00000000..7dbe7ff1 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_nf_devices_can_config.cpp @@ -0,0 +1,44 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_nf_devices_can_config.h" +#include + +/////////// +// CAN1 // +/////////// + +// pin configuration for CAN1 +// port for TX pin is: GPIOB +// TX pin: is GPIOB_09 +// port for RX pin is: GPIOB +// RX pin: is GPIOB_08 +// GPIO alternate pin function is 9 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in STM32F405xx/STM32F407xx datasheet) +CAN_CONFIG_PINS(1, GPIOB, GPIOB, 9, 8, 9) + +// buffer +CANRxFrame Can1_MsgBuffer[CAN1_RX_BUFFER_SIZE]; + +// initialization for CAN1 +CAN_INIT(1, CAN1_RX_BUFFER_SIZE) + +/////////// +// CAN2 // +/////////// + +// pin configuration for CAN2 +// port for TX pin is: GPIOB +// TX pin: is GPIOB_06 +// port for RX pin is: GPIOB +// RX pin: is GPIOB_05 +// GPIO alternate pin function is 9 (see "Table 9. STM32F405xx and STM32F407xx alternate function mapping" in STM32F405xx/STM32F407xx datasheet) +CAN_CONFIG_PINS(2, GPIOB, GPIOB, 6, 5, 9) + +// buffer +CANRxFrame Can2_MsgBuffer[CAN2_RX_BUFFER_SIZE]; + +// initialization for CAN1 +CAN_INIT(2, CAN2_RX_BUFFER_SIZE) diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_nf_devices_can_config.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_nf_devices_can_config.h new file mode 100644 index 00000000..adc8ace3 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_nf_devices_can_config.h @@ -0,0 +1,25 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +////////// +// CAN1 // +////////// + +// enable CAN1 +#define NF_CAN_STM32_CAN_USE_CAN1 TRUE + +// buffers size +#define CAN1_RX_BUFFER_SIZE 16 + +////////// +// CAN2 // +////////// + +// enable CAN2 +#define NF_CAN_STM32_CAN_USE_CAN2 TRUE + +// buffers size +#define CAN2_RX_BUFFER_SIZE 16 diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_nf_devices_onewire_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_nf_devices_onewire_config.cpp new file mode 100644 index 00000000..09f1420e --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_nf_devices_onewire_config.cpp @@ -0,0 +1,29 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_nf_devices_onewire_config.h" +#include + +/////////// +// UART4 // +/////////// + +// pin configuration for UART4 +// port for TX pin is: GPIOC +// TX pin: is GPIOC_10 +// GPIO alternate pin function is 8 +UART_CONFIG_PINS(4, GPIOC, 10, 8) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart4_TxBuffer[UART4_TX_SIZE]; +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart4_RxBuffer[UART4_RX_SIZE]; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_nf_devices_onewire_config.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_nf_devices_onewire_config.h new file mode 100644 index 00000000..76f90a10 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_nf_devices_onewire_config.h @@ -0,0 +1,17 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////// +// UART4 // +/////////// + +// enable USART4 +#define NF_ONEWIRE_STM32_UART_USE_USART4 TRUE + +// buffers size +// tx buffer size: 32 bytes +#define UART4_TX_SIZE 32 +// rx buffer size: 32 bytes +#define UART4_RX_SIZE 32 \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_spiffs.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_spiffs.c new file mode 100644 index 00000000..103930bb --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_spiffs.c @@ -0,0 +1,853 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) 2016 STMicroelectronics. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include "target_spiffs.h" +#include + +static uint8_t QSPI_ResetMemory(QSPI_HandleTypeDef *hqspi); +static uint8_t QSPI_EnterFourBytesAddress(QSPI_HandleTypeDef *hqspi); +static uint8_t QSPI_DummyCyclesCfg(QSPI_HandleTypeDef *hqspi); +static uint8_t QSPI_EnterMemory_QPI(QSPI_HandleTypeDef *hqspi); +// static uint8_t QSPI_ExitMemory_QPI(QSPI_HandleTypeDef *hqspi); +static uint8_t QSPI_OutDrvStrengthCfg(QSPI_HandleTypeDef *hqspi); +static uint8_t QSPI_WriteEnable(QSPI_HandleTypeDef *hqspi); +static uint8_t QSPI_AutoPollingMemReady (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); +static uint8_t QSPI_ReadChipID(QSPI_HandleTypeDef *hqspi, uint8_t* buffer); + +uint8_t QSPI_Read(uint8_t* pData, uint32_t readAddr, uint32_t size); +uint8_t QSPI_Write(uint8_t* pData, uint32_t writeAddr, uint32_t size); +uint8_t QSPI_Erase_Block(uint32_t blockAddress); + +// initialization of everything required for SPIFFS +// for this target is the QSPI driver +uint8_t target_spiffs_init() +{ + uint8_t device_id[3] = { 0, 0, 0 }; + + /* QSPI initialization */ + /* QSPI freq = SYSCLK /(1 + ClockPrescaler) = 216 MHz/(1+1) = 108 Mhz */ + QSPID1.Init.ClockPrescaler = 1; /* QSPI freq = 216 MHz/(1+1) = 108 Mhz */ + QSPID1.Init.FifoThreshold = 16; + QSPID1.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE; + QSPID1.Init.FlashSize = POSITION_VAL(MX25L512_FLASH_SIZE) - 1; + QSPID1.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE; /* Min 30ns for nonRead */ + QSPID1.Init.ClockMode = QSPI_CLOCK_MODE_0; + QSPID1.Init.FlashID = QSPI_FLASH_ID_1; + QSPID1.Init.DualFlash = QSPI_DUALFLASH_DISABLE; + + // init driver + qspiStart(&QSPID1); + + if (HAL_QSPI_Init(&QSPID1) != HAL_OK) + { + return QSPI_ERROR; + } + + /* QSPI memory reset */ + if(QSPI_ResetMemory( &QSPID1 ) != QSPI_OK) + { + return QSPI_NOT_SUPPORTED; + } + + /* Put QSPI memory in QPI mode */ + if(QSPI_EnterMemory_QPI( &QSPID1 )!=QSPI_OK ) + { + return QSPI_NOT_SUPPORTED; + } + + /* Set the QSPI memory in 4-bytes address mode */ + if(QSPI_EnterFourBytesAddress(&QSPID1) != QSPI_OK) + { + return QSPI_NOT_SUPPORTED; + } + + /* Configuration of the dummy cycles on QSPI memory side */ + if (QSPI_DummyCyclesCfg(&QSPID1) != QSPI_OK) + { + return QSPI_NOT_SUPPORTED; + } + + /* Configuration of the Output driver strength on memory side */ + if( QSPI_OutDrvStrengthCfg( &QSPID1 ) != QSPI_OK ) + { + return QSPI_NOT_SUPPORTED; + } + + HAL_Delay(10); + + // sanity check: read device ID and unique ID + if( QSPI_ReadChipID( &QSPID1, device_id ) != QSPI_OK ) + { + return QSPI_ERROR; + } + + // // invalidate cache over read buffer to ensure that content from DMA is read + // // (only required for Cortex-M7) + // cacheBufferInvalidate(device_id, 3); + + // constants from ID Definitions table in MX25L51245G datasheet + ASSERT(device_id[0] == MX25L512_MANUFACTURER_ID); + ASSERT(device_id[1] == MX25L512_DEVICE_ID_MEM_TYPE); + ASSERT(device_id[2] == MX25L512_DEVICE_ID_MEM_CAPACITY); + + return QSPI_OK; +} + +// target specific implementation of hal_spiffs_erase +s32_t hal_spiffs_erase(u32_t addr, u32_t size) +{ + uint32_t i = 0; + + // how many sectors need to be erased? + uint32_t erase_count = (size + SPIFFS_ERASE_BLOCK_SIZE - 1) / SPIFFS_ERASE_BLOCK_SIZE; + + for (i = 0; i < erase_count; i++) + { + if( QSPI_Erase_Block(addr) != QSPI_OK) + { + return SPIFFS_ERROR; + } + + // adjust sector address + addr += i * SPIFFS_ERASE_BLOCK_SIZE; + } + + return SPIFFS_SUCCESS; +} + +// target specific implementation of hal_spiffs_read +s32_t hal_spiffs_read(u32_t addr, u32_t size, u8_t *dst) +{ + if(QSPI_Read(dst, addr, size) != QSPI_OK) + { + return SPIFFS_ERROR; + } + + return SPIFFS_SUCCESS; +} + +// target specific implementation of hal_spiffs_write +s32_t hal_spiffs_write(u32_t addr, u32_t size, u8_t *src) +{ + if( QSPI_Write(src, addr, size) != QSPI_OK) + { + return SPIFFS_ERROR; + } + + return SPIFFS_SUCCESS; +} + +static uint8_t QSPI_ResetMemory(QSPI_HandleTypeDef *hqspi) +{ + QSPI_CommandTypeDef s_command; + QSPI_AutoPollingTypeDef s_config; + uint8_t reg; + + /* Send command RESET command in QPI mode (QUAD I/Os) */ + /* Initialize the reset enable command */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = RESET_ENABLE_CMD; + s_command.AddressMode = QSPI_ADDRESS_NONE; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_NONE; + s_command.DummyCycles = 0; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + /* Send the command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Send the reset memory command */ + s_command.Instruction = RESET_MEMORY_CMD; + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Send command RESET command in SPI mode */ + /* Initialize the reset enable command */ + s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; + s_command.Instruction = RESET_ENABLE_CMD; + /* Send the command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + /* Send the reset memory command */ + s_command.Instruction = RESET_MEMORY_CMD; + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* After reset CMD, 1000ms requested if QSPI memory SWReset occured during full chip erase operation */ + HAL_Delay( 1000 ); + + /* Configure automatic polling mode to wait the WIP bit=0 */ + s_config.Match = 0; + s_config.Mask = MX25L512_SR_WIP; + s_config.MatchMode = QSPI_MATCH_MODE_AND; + s_config.StatusBytesSize = 1; + s_config.Interval = 0x10; + s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; + + s_command.Instruction = READ_STATUS_REG_CMD; + s_command.DataMode = QSPI_DATA_1_LINE; + + if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Initialize the reading of status register */ + s_command.Instruction = READ_STATUS_REG_CMD; + s_command.NbData = 1; + + /* Configure the command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Reception of the data */ + if (HAL_QSPI_Receive(hqspi, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Enable write operations, command in 1 bit */ + /* Enable write operations */ + s_command.Instruction = WRITE_ENABLE_CMD; + s_command.DataMode = QSPI_DATA_NONE; + s_command.DummyCycles = 0; + s_command.NbData = 0; + + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Configure automatic polling mode to wait for write enabling */ + s_config.Match = MX25L512_SR_WREN; + s_config.Mask = MX25L512_SR_WREN; + s_config.MatchMode = QSPI_MATCH_MODE_AND; + s_config.StatusBytesSize = 1; + s_config.Interval = 0x10; + s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; + + s_command.Instruction = READ_STATUS_REG_CMD; + s_command.DataMode = QSPI_DATA_1_LINE; + s_command.NbData = 0; + + if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Update the configuration register with new dummy cycles */ + s_command.Instruction = WRITE_STATUS_CFG_REG_CMD; + s_command.DataMode = QSPI_DATA_1_LINE; + s_command.NbData = 1; + + /* Enable the Quad IO on the QSPI memory (Non-volatile bit) */ + reg |= MX25L512_SR_QUADEN; + + /* Configure the command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Transmission of the data */ + if (HAL_QSPI_Transmit(hqspi, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* 40ms Write Status/Configuration Register Cycle Time */ + HAL_Delay( 40 ); + + // read back register to check MX25L512_SR_QUADEN + s_command.Instruction = READ_STATUS_REG_CMD; + s_command.DataMode = QSPI_DATA_1_LINE; + s_command.DummyCycles = 0; + s_command.NbData = 1; + + /* Configure the command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Reception of the data */ + if (HAL_QSPI_Receive(hqspi, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + if(reg & MX25L512_SR_QUADEN) + { + return QSPI_OK; + } + else + { + return QSPI_ERROR; + } +} + +static uint8_t QSPI_DummyCyclesCfg(QSPI_HandleTypeDef *hqspi) +{ + QSPI_CommandTypeDef s_command; + uint8_t reg[2]; + + /* Initialize the reading of status register */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = READ_STATUS_REG_CMD; + s_command.AddressMode = QSPI_ADDRESS_NONE; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_4_LINES; + s_command.DummyCycles = 0; + s_command.NbData = 1; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + /* Configure the command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Reception of the data */ + if (HAL_QSPI_Receive(hqspi, &(reg[0]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Initialize the reading of configuration register */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = READ_CFG_REG_CMD; + s_command.AddressMode = QSPI_ADDRESS_NONE; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_4_LINES; + s_command.DummyCycles = 0; + s_command.NbData = 1; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + /* Configure the command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Reception of the data */ + if (HAL_QSPI_Receive(hqspi, &(reg[1]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Enable write operations */ + if (QSPI_WriteEnable(hqspi) != QSPI_OK) + { + return QSPI_ERROR; + } + + /* Update the configuration register with new dummy cycles */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = WRITE_STATUS_CFG_REG_CMD; + s_command.AddressMode = QSPI_ADDRESS_NONE; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_4_LINES; + s_command.DummyCycles = 0; + s_command.NbData = 2; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + /* MX25L512_DUMMY_CYCLES_READ_QUAD = 3 for 10 cycles in QPI mode */ + MODIFY_REG( reg[1], MX25L512_CR_NB_DUMMY, (MX25L512_DUMMY_CYCLES_READ_QUAD << POSITION_VAL(MX25L512_CR_NB_DUMMY))); + + /* Configure the write volatile configuration register command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Transmission of the data */ + if (HAL_QSPI_Transmit(hqspi, &(reg[0]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* 40ms Write Status/Configuration Register Cycle Time */ + HAL_Delay( 40 ); + + return QSPI_OK; +} + +static uint8_t QSPI_EnterMemory_QPI( QSPI_HandleTypeDef *hqspi ) +{ + QSPI_CommandTypeDef s_command; + QSPI_AutoPollingTypeDef s_config; + + /* Initialize the QPI enable command */ + /* QSPI memory is supported to be in SPI mode, so CMD on 1 LINE */ + s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; + s_command.Instruction = ENTER_QUAD_CMD; + s_command.AddressMode = QSPI_ADDRESS_NONE; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_NONE; + s_command.DummyCycles = 0; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + /* Send the command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Configure automatic polling mode to wait the QUADEN bit=1 and WIP bit=0 */ + s_config.Match = MX25L512_SR_QUADEN; + s_config.Mask = MX25L512_SR_QUADEN|MX25L512_SR_WIP; + s_config.MatchMode = QSPI_MATCH_MODE_AND; + s_config.StatusBytesSize = 1; + s_config.Interval = 0x10; + s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; + + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = READ_STATUS_REG_CMD; + s_command.DataMode = QSPI_DATA_4_LINES; + + if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + return QSPI_OK; +} + +// static uint8_t QSPI_ExitMemory_QPI( QSPI_HandleTypeDef *hqspi) +// { +// QSPI_CommandTypeDef s_command; + +// /* Initialize the QPI enable command */ +// /* QSPI memory is supported to be in QPI mode, so CMD on 4 LINES */ +// s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; +// s_command.Instruction = EXIT_QUAD_CMD; +// s_command.AddressMode = QSPI_ADDRESS_NONE; +// s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; +// s_command.DataMode = QSPI_DATA_NONE; +// s_command.DummyCycles = 0; +// s_command.DdrMode = QSPI_DDR_MODE_DISABLE; +// s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; +// s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + +// /* Send the command */ +// if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) +// { +// return QSPI_ERROR; +// } + +// return QSPI_OK; +// } + +static uint8_t QSPI_EnterFourBytesAddress(QSPI_HandleTypeDef *hqspi) +{ + QSPI_CommandTypeDef s_command; + + /* Initialize the command */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = ENTER_4_BYTE_ADDR_MODE_CMD; + s_command.AddressMode = QSPI_ADDRESS_NONE; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_NONE; + s_command.DummyCycles = 0; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + /* Enable write operations */ + if (QSPI_WriteEnable(hqspi) != QSPI_OK) + { + return QSPI_ERROR; + } + + /* Send the command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Configure automatic polling mode to wait the memory is ready */ + if (QSPI_AutoPollingMemReady(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK) + { + return QSPI_ERROR; + } + + return QSPI_OK; +} + +static uint8_t QSPI_WriteEnable(QSPI_HandleTypeDef *hqspi) +{ + + //HAL_QSPI_Abort(&QSPID1); + + QSPI_CommandTypeDef s_command; + QSPI_AutoPollingTypeDef s_config; + + /* Enable write operations */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = WRITE_ENABLE_CMD; + s_command.AddressMode = QSPI_ADDRESS_NONE; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_NONE; + s_command.DummyCycles = 0; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Configure automatic polling mode to wait for write enabling */ + s_config.Match = MX25L512_SR_WREN; + s_config.Mask = MX25L512_SR_WREN; + s_config.MatchMode = QSPI_MATCH_MODE_AND; + s_config.StatusBytesSize = 1; + s_config.Interval = 0x10; + s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; + + s_command.Instruction = READ_STATUS_REG_CMD; + s_command.DataMode = QSPI_DATA_4_LINES; + + if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + return QSPI_OK; +} + +static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) +{ + QSPI_CommandTypeDef s_command; + QSPI_AutoPollingTypeDef s_config; + + /* Configure automatic polling mode to wait for memory ready */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = READ_STATUS_REG_CMD; + s_command.AddressMode = QSPI_ADDRESS_NONE; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_4_LINES; + s_command.DummyCycles = 0; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + s_config.Match = 0; + s_config.Mask = MX25L512_SR_WIP; + s_config.MatchMode = QSPI_MATCH_MODE_AND; + s_config.StatusBytesSize = 1; + s_config.Interval = 0x10; + s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; + + if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, Timeout) != HAL_OK) + { + return QSPI_ERROR; + } + + return QSPI_OK; +} + +static uint8_t QSPI_OutDrvStrengthCfg( QSPI_HandleTypeDef *hqspi ) +{ + QSPI_CommandTypeDef s_command; + uint8_t reg[2]; + + /* Initialize the reading of status register */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = READ_STATUS_REG_CMD; + s_command.AddressMode = QSPI_ADDRESS_NONE; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_4_LINES; + s_command.DummyCycles = 0; + s_command.NbData = 1; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + /* Configure the command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Reception of the data */ + if (HAL_QSPI_Receive(hqspi, &(reg[0]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Initialize the reading of configuration register */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = READ_CFG_REG_CMD; + s_command.AddressMode = QSPI_ADDRESS_NONE; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_4_LINES; + s_command.DummyCycles = 0; + s_command.NbData = 1; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + /* Configure the command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Reception of the data */ + if (HAL_QSPI_Receive(hqspi, &(reg[1]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Enable write operations */ + if (QSPI_WriteEnable(&QSPID1) != QSPI_OK) + { + return QSPI_ERROR; + } + + /* Update the configuration register with new output driver strength */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = WRITE_STATUS_CFG_REG_CMD; + s_command.AddressMode = QSPI_ADDRESS_NONE; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_4_LINES; + s_command.DummyCycles = 0; + s_command.NbData = 2; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + /* Set Output Strength of the QSPI memory 15 ohms */ + MODIFY_REG( reg[1], MX25L512_CR_ODS, (MX25L512_CR_ODS_15 << POSITION_VAL(MX25L512_CR_ODS))); + + /* Configure the write volatile configuration register command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Transmission of the data */ + if (HAL_QSPI_Transmit(hqspi, &(reg[0]), HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + return QSPI_OK; +} + +static uint8_t QSPI_ReadChipID(QSPI_HandleTypeDef *hqspi, uint8_t* buffer) +{ + QSPI_CommandTypeDef s_command; + + /* Initialize the reading of status register */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = MULTIPLE_IO_READ_ID_CMD; + s_command.AddressMode = QSPI_ADDRESS_NONE; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_4_LINES; + s_command.DummyCycles = 0; + s_command.NbData = 3; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + /* Configure the command */ + if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Reception of the data */ + if (HAL_QSPI_Receive(hqspi, buffer, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + return QSPI_OK; +} + +uint8_t QSPI_Read(uint8_t* pData, uint32_t readAddr, uint32_t size) +{ + QSPI_CommandTypeDef s_command; + + /* Initialize the read command */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = QSPI_READ_4_BYTE_ADDR_CMD; + s_command.AddressMode = QSPI_ADDRESS_4_LINES; + s_command.AddressSize = QSPI_ADDRESS_32_BITS; + s_command.Address = readAddr; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_4_LINES; + s_command.DummyCycles = MX25L512_DUMMY_CYCLES_READ_QUAD_IO; + s_command.NbData = size; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + /* Configure the command */ + if (HAL_QSPI_Command(&QSPID1, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Set S# timing for Read command */ + MODIFY_REG(QSPID1.Instance->DCR, QUADSPI_DCR_CSHT, QSPI_CS_HIGH_TIME_1_CYCLE); + + /* Reception of the data */ + if (HAL_QSPI_Receive(&QSPID1, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + // // invalidate cache over read buffer to ensure that content from DMA is read + // // (only required for Cortex-M7) + // cacheBufferInvalidate(pData, size); + + /* Restore S# timing for nonRead commands */ + MODIFY_REG(QSPID1.Instance->DCR, QUADSPI_DCR_CSHT, QSPI_CS_HIGH_TIME_4_CYCLE); + +SET_BIT(QSPID1.Instance->CR, QUADSPI_CR_ABORT); + + return QSPI_OK; +} + +uint8_t QSPI_Write(uint8_t* pData, uint32_t writeAddr, uint32_t size) +{ + QSPI_CommandTypeDef s_command; + uint32_t end_addr, current_size, current_addr; + + /* Calculation of the size between the write address and the end of the page */ + current_size = MX25L512_PAGE_SIZE - (writeAddr % MX25L512_PAGE_SIZE); + + /* Check if the size of the data is less than the remaining place in the page */ + if (current_size > size) + { + current_size = size; + } + + /* Initialize the address variables */ + current_addr = writeAddr; + end_addr = writeAddr + size; + + /* Initialize the program command */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = PAGE_PROG_CMD; + s_command.AddressMode = QSPI_ADDRESS_4_LINES; + s_command.AddressSize = QSPI_ADDRESS_32_BITS; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_4_LINES; + s_command.DummyCycles = 0; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + /* Perform the write page by page */ + do + { + s_command.Address = current_addr; + s_command.NbData = current_size; + + /* Enable write operations */ + if (QSPI_WriteEnable(&QSPID1) != QSPI_OK) + { + return QSPI_ERROR; + } + + /* Configure the command */ + if (HAL_QSPI_Command(&QSPID1, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + // // flush DMA buffer to ensure cache coherency + // // (only required for Cortex-M7) + // cacheBufferFlush(pData, current_size); + + /* Transmission of the data */ + if (HAL_QSPI_Transmit(&QSPID1, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Configure automatic polling mode to wait for end of program */ + if (QSPI_AutoPollingMemReady(&QSPID1, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK) + { + return QSPI_ERROR; + } + + /* Update the address and size variables for next page programming */ + current_addr += current_size; + pData += current_size; + current_size = ((current_addr + MX25L512_PAGE_SIZE) > end_addr) ? (end_addr - current_addr) : MX25L512_PAGE_SIZE; + + } + while (current_addr < end_addr); + + return QSPI_OK; +} + +uint8_t QSPI_Erase_Block(uint32_t blockAddress) +{ + QSPI_CommandTypeDef s_command; + + /* Initialize the erase command */ + s_command.InstructionMode = QSPI_INSTRUCTION_4_LINES; + s_command.Instruction = SECTOR_ERASE_4_BYTE_ADDR_CMD; + s_command.AddressMode = QSPI_ADDRESS_4_LINES; + s_command.AddressSize = QSPI_ADDRESS_32_BITS; + s_command.Address = blockAddress; + s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; + s_command.DataMode = QSPI_DATA_NONE; + s_command.DummyCycles = 0; + s_command.DdrMode = QSPI_DDR_MODE_DISABLE; + s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; + s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; + + /* Enable write operations */ + if (QSPI_WriteEnable(&QSPID1) != QSPI_OK) + { + return QSPI_ERROR; + } + + /* Send the command */ + if (HAL_QSPI_Command(&QSPID1, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) + { + return QSPI_ERROR; + } + + /* Configure automatic polling mode to wait for end of erase */ + if (QSPI_AutoPollingMemReady(&QSPID1, MX25L512_SECTOR_ERASE_MAX_TIME) != QSPI_OK) + { + return QSPI_ERROR; + } + + return QSPI_OK; +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_spiffs.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_spiffs.h new file mode 100644 index 00000000..c6d1b86a --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_spiffs.h @@ -0,0 +1,148 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +//////////////////////////////////// +// buffers configuration +#define SPIFFS_LOGICAL_PAGE_SIZE (256) + +#define SPIFFS_WORK_BUFFER_SIZE (SPIFFS_LOGICAL_PAGE_SIZE * 2) +#define SPIFFS_FILE_DESCRIPTORS_SPACE (32 * 2) +#define SPIFFS_CACHE_SIZE ((SPIFFS_LOGICAL_PAGE_SIZE + 32) * 4) + +#define SPIFFS_DRIVER_QSPI (1) + +// MX25L512 Configuration +#define MX25L512_FLASH_SIZE 0x4000000 /* 512 MBits => 64MBytes */ +#define MX25L512_SECTOR_SIZE 0x10000 /* 1024 sectors of 64KBytes */ +#define MX25L512_SUBSECTOR_SIZE 0x1000 /* 16384 subsectors of 4kBytes */ +#define MX25L512_PAGE_SIZE 0x100 /* 262144 pages of 256 bytes */ + +#define MX25L512_DUMMY_CYCLES_READ_QUAD 3 +#define MX25L512_DUMMY_CYCLES_READ 8 +#define MX25L512_DUMMY_CYCLES_READ_QUAD_IO 10 +#define MX25L512_DUMMY_CYCLES_READ_DTR 6 +#define MX25L512_DUMMY_CYCLES_READ_QUAD_DTR 8 + +#define MX25L512_BULK_ERASE_MAX_TIME 600000 +#define MX25L512_SECTOR_ERASE_MAX_TIME 2000 +#define MX25L512_SUBSECTOR_ERASE_MAX_TIME 800 + +// MX25L512 Commands +/* Reset Operations */ +#define RESET_ENABLE_CMD 0x66 +#define RESET_MEMORY_CMD 0x99 + +/* Identification Operations */ +#define READ_ID_CMD 0x9F +#define MULTIPLE_IO_READ_ID_CMD 0xAF +#define READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5A + +/* Read Operations */ +#define READ_CMD 0x03 +#define READ_4_BYTE_ADDR_CMD 0x13 + +#define FAST_READ_CMD 0x0B +#define FAST_READ_DTR_CMD 0x0D +#define FAST_READ_4_BYTE_ADDR_CMD 0x0C + +#define DUAL_OUT_FAST_READ_CMD 0x3B +#define DUAL_OUT_FAST_READ_4_BYTE_ADDR_CMD 0x3C + +#define DUAL_INOUT_FAST_READ_CMD 0xBB +#define DUAL_INOUT_FAST_READ_DTR_CMD 0xBD +#define DUAL_INOUT_FAST_READ_4_BYTE_ADDR_CMD 0xBC + +#define QUAD_OUT_FAST_READ_CMD 0x6B +#define QUAD_OUT_FAST_READ_4_BYTE_ADDR_CMD 0x6C + +#define QUAD_INOUT_FAST_READ_CMD 0xEB +#define QUAD_INOUT_FAST_READ_DTR_CMD 0xED +#define QSPI_READ_4_BYTE_ADDR_CMD 0xEC + +/* Write Operations */ +#define WRITE_ENABLE_CMD 0x06 +#define WRITE_DISABLE_CMD 0x04 + +/* Register Operations */ +#define READ_STATUS_REG_CMD 0x05 +#define READ_CFG_REG_CMD 0x15 +#define WRITE_STATUS_CFG_REG_CMD 0x01 + +#define READ_LOCK_REG_CMD 0x2D +#define WRITE_LOCK_REG_CMD 0x2C + +#define READ_EXT_ADDR_REG_CMD 0xC8 +#define WRITE_EXT_ADDR_REG_CMD 0xC5 + +/* Program Operations */ +#define PAGE_PROG_CMD 0x02 +#define QSPI_PAGE_PROG_4_BYTE_ADDR_CMD 0x12 + +#define QUAD_IN_FAST_PROG_CMD 0x38 +#define EXT_QUAD_IN_FAST_PROG_CMD 0x38 +#define QUAD_IN_FAST_PROG_4_BYTE_ADDR_CMD 0x3E + +/* Erase Operations */ +#define SUBSECTOR_ERASE_CMD 0x20 +#define SUBSECTOR_ERASE_4_BYTE_ADDR_CMD 0x21 + +#define SECTOR_ERASE_CMD 0xD8 +#define SECTOR_ERASE_4_BYTE_ADDR_CMD 0xDC + +#define BULK_ERASE_CMD 0xC7 + +#define PROG_ERASE_RESUME_CMD 0x30 +#define PROG_ERASE_SUSPEND_CMD 0xB0 + +/* 4-byte Address Mode Operations */ +#define ENTER_4_BYTE_ADDR_MODE_CMD 0xB7 +#define EXIT_4_BYTE_ADDR_MODE_CMD 0xE9 + +/* Quad Operations */ +#define ENTER_QUAD_CMD 0x35 +#define EXIT_QUAD_CMD 0xF5 + +/* Added for compatibility */ +#define QPI_READ_4_BYTE_ADDR_CMD QSPI_READ_4_BYTE_ADDR_CMD +#define QPI_PAGE_PROG_4_BYTE_ADDR_CMD QSPI_PAGE_PROG_4_BYTE_ADDR_CMD + + +// MX25L512 Registers +/* Status Register */ +#define MX25L512_SR_WIP ((uint8_t)0x01) /*!< Write in progress */ +#define MX25L512_SR_WREN ((uint8_t)0x02) /*!< Write enable latch */ +#define MX25L512_SR_BLOCKPR ((uint8_t)0x5C) /*!< Block protected against program and erase operations */ +#define MX25L512_SR_PRBOTTOM ((uint8_t)0x20) /*!< Protected memory area defined by BLOCKPR starts from top or bottom */ +#define MX25L512_SR_QUADEN ((uint8_t)0x40) /*!< Quad IO mode enabled if =1 */ +#define MX25L512_SR_SRWREN ((uint8_t)0x80) /*!< Status register write enable/disable */ + +/* Configuration Register */ +#define MX25L512_CR_ODS ((uint8_t)0x07) /*!< Output driver strength */ +#define MX25L512_CR_ODS_30 ((uint8_t)0x07) /*!< Output driver strength 30 ohms (default)*/ +#define MX25L512_CR_ODS_15 ((uint8_t)0x06) /*!< Output driver strength 15 ohms */ +#define MX25L512_CR_ODS_20 ((uint8_t)0x05) /*!< Output driver strength 20 ohms */ +#define MX25L512_CR_ODS_45 ((uint8_t)0x03) /*!< Output driver strength 45 ohms */ +#define MX25L512_CR_ODS_60 ((uint8_t)0x02) /*!< Output driver strength 60 ohms */ +#define MX25L512_CR_ODS_90 ((uint8_t)0x01) /*!< Output driver strength 90 ohms */ +#define MX25L512_CR_TB ((uint8_t)0x08) /*!< Top/Bottom bit used to configure the block protect area */ +#define MX25L512_CR_PBE ((uint8_t)0x10) /*!< Preamble Bit Enable */ +#define MX25L512_CR_4BYTE ((uint8_t)0x20) /*!< 3-bytes or 4-bytes addressing */ +#define MX25L512_CR_NB_DUMMY ((uint8_t)0xC0) /*!< Number of dummy clock cycles */ + +#define MX25L512_FLASH_SIZE 0x4000000 // 512MBits => 64MBytes +#define MX25L512_SECTOR_SIZE 0x10000 // 1024 sectors of 64KBytes +#define MX25L512_SUBSECTOR_SIZE 0x1000 // 16384 subsectors of 4kBytes +#define MX25L512_PAGE_SIZE 0x100 // 262144 pages of 256 bytes + +#define MX25L512_SUBSECTOR_ERASE_MAX_TIME 800 +#define MX25L512_MANUFACTURER_ID ((uint8_t)0xC2) +#define MX25L512_DEVICE_ID_MEM_TYPE ((uint8_t)0x20) +#define MX25L512_DEVICE_ID_MEM_CAPACITY ((uint8_t)0x1A) + +//////////////////////////////// + +#define SPIFFS_TOTAL_SIZE MX25L512_FLASH_SIZE +#define SPIFFS_ERASE_BLOCK_SIZE MX25L512_SECTOR_SIZE +#define SPIFFS_LOGICAL_BLOCK_SIZE (64*1024) diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_system_devices_dac_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_system_devices_dac_config.cpp new file mode 100644 index 00000000..049422f7 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_system_devices_dac_config.cpp @@ -0,0 +1,14 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +const NF_PAL_DAC_PORT_PIN_CHANNEL DacPortPinConfig[] = { + + // DAC1, channel 1, GPIO port A, pin 4 + {1, 1, GPIOA, 4}, +}; + +const int DacChannelCount = ARRAYSIZE(DacPortPinConfig); diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_windows_devices_adc_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_windows_devices_adc_config.cpp new file mode 100644 index 00000000..3a886009 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_windows_devices_adc_config.cpp @@ -0,0 +1,25 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_adc_native_target.h" + +const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[] = { + + // ADC1 + {1, GPIOA, 6, ADC_CHANNEL_IN6}, + {1, GPIOA, 4, ADC_CHANNEL_IN4}, + {1, GPIOC, 2, ADC_CHANNEL_IN12}, + {1, GPIOF, 10, ADC_CHANNEL_IN8}, + + // ADC3 + {3, GPIOF, 8, ADC_CHANNEL_IN6}, + + // these are the internal sources, available only at ADC1 + {1, NULL, 0, ADC_CHANNEL_SENSOR}, + {1, NULL, 0, ADC_CHANNEL_VREFINT}, + {1, NULL, 0, ADC_CHANNEL_VBAT}, +}; + +const int AdcChannelCount = ARRAYSIZE(AdcPortPinConfig); diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_windows_devices_i2c_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_windows_devices_i2c_config.cpp new file mode 100644 index 00000000..2a60a22f --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_windows_devices_i2c_config.cpp @@ -0,0 +1,18 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_i2c_native_target.h" + +////////// +// I2C1 // +////////// + +// pin configuration for I2C1 +// port for SCL pin is: GPIOB +// port for SDA pin is: GPIOB +// SCL pin: is GPIOB_8 +// SDA pin: is GPIOB_9 +// GPIO alternate pin function is 4 (see alternate function mapping table in device datasheet) +I2C_CONFIG_PINS(1, GPIOB, GPIOB, 8, 9, 4) diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_windows_devices_serialcommunication_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_windows_devices_serialcommunication_config.cpp new file mode 100644 index 00000000..2f2f4148 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_windows_devices_serialcommunication_config.cpp @@ -0,0 +1,255 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "target_windows_devices_serialcommunication_config.h" +#include + +// /////////// +// // UART1 // +// /////////// + +// // pin configuration for UART1 +// // port for TX pin is: GPIOD +// // port for RX pin is: GPIOC +// // TX pin: is GPIOD_2 +// // RX pin: is GPIOC_12 +// // GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping" in STM32F769I datasheet) +// UART_CONFIG_PINS(1, GPIOD, GPIOC, 2, 12, 8) + +// // buffers +// // buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// // because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +// #if defined(__GNUC__) +// __attribute__((aligned (32))) +// #endif +// uint8_t Uart1_TxBuffer[UART1_TX_SIZE]; + +// #if defined(__GNUC__) +// __attribute__((aligned (32))) +// #endif +// uint8_t Uart1_RxBuffer[UART1_RX_SIZE]; + +// // initialization for UART1 +// UART_INIT(1, UART1_TX_SIZE, UART1_RX_SIZE) + +// // un-initialization for UART1 +// UART_UNINIT(1) + +// /////////// +// // UART2 // +// /////////// + +// // pin configuration for UART2 +// // port for TX pin is: GPIOD +// // port for RX pin is: GPIOC +// // TX pin: is GPIOD_2 +// // RX pin: is GPIOC_12 +// // GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping" in STM32F769I datasheet) +// UART_CONFIG_PINS(2, GPIOD, GPIOC, 2, 12, 8) + +// // buffers +// // buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// // because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +// #if defined(__GNUC__) +// __attribute__((aligned (32))) +// #endif +// uint8_t Uart2_TxBuffer[UART2_TX_SIZE]; + +// #if defined(__GNUC__) +// __attribute__((aligned (32))) +// #endif +// uint8_t Uart2_RxBuffer[UART2_RX_SIZE]; + +// // initialization for UART2 +// UART_INIT(2, UART2_TX_SIZE, UART2_RX_SIZE) + +// // un-initialization for UART2 +// UART_UNINIT(2) + +// /////////// +// // UART3 // +// /////////// + +// // pin configuration for UART3 +// // port for TX pin is: GPIOD +// // port for RX pin is: GPIOC +// // TX pin: is GPIOD_2 +// // RX pin: is GPIOC_12 +// // GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping" in STM32F769I datasheet) +// UART_CONFIG_PINS(3, GPIOD, GPIOC, 2, 12, 8) + +// // buffers +// // buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// // because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +// #if defined(__GNUC__) +// __attribute__((aligned (32))) +// #endif +// uint8_t Uart3_TxBuffer[UART3_TX_SIZE]; + +// #if defined(__GNUC__) +// __attribute__((aligned (32))) +// #endif +// uint8_t Uart3_RxBuffer[UART3_RX_SIZE]; + +// // initialization for UART3 +// UART_INIT(3, UART3_TX_SIZE, UART3_RX_SIZE) + +// // un-initialization for UART3 +// UART_UNINIT(3) + +// /////////// +// // UART4 // +// /////////// + +// // pin configuration for UART4 +// // port for TX pin is: GPIOD +// // port for RX pin is: GPIOC +// // TX pin: is GPIOD_2 +// // RX pin: is GPIOC_12 +// // GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping" in STM32F769I datasheet) +// UART_CONFIG_PINS(4, GPIOD, GPIOC, 2, 12, 8) + +// // buffers +// // buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// // because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +// #if defined(__GNUC__) +// __attribute__((aligned (32))) +// #endif +// uint8_t Uart4_TxBuffer[UART4_TX_SIZE]; + +// #if defined(__GNUC__) +// __attribute__((aligned (32))) +// #endif +// uint8_t Uart4_RxBuffer[UART4_RX_SIZE]; + +// // initialization for UART4 +// UART_INIT(4, UART4_TX_SIZE, UART4_RX_SIZE) + +// // un-initialization for UART4 +// UART_UNINIT(4) + +/////////// +// UART5 // +/////////// + +// pin configuration for UART5 +// port for TX pin is: GPIOD +// port for RX pin is: GPIOC +// TX pin: is GPIOD_2 +// RX pin: is GPIOC_12 +// GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping" in STM32F769I datasheet) +UART_CONFIG_PINS(5, GPIOD, GPIOC, 2, 12, 8) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart5_TxBuffer[UART5_TX_SIZE]; + +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart5_RxBuffer[UART5_RX_SIZE]; + +// initialization for UART5 +UART_INIT(5, UART5_TX_SIZE, UART5_RX_SIZE) + +// un-initialization for UART5 +UART_UNINIT(5) + +/////////// +// UART6 // +/////////// + +// pin configuration for UART6 +// port for TX pin is: GPIOC +// port for RX pin is: GPIOC +// TX pin: is GPIOC_6 +// RX pin: is GPIOC_7 +// GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping" in STM32F769I datasheet) +UART_CONFIG_PINS(6, GPIOC, GPIOC, 6, 7, 8) + +// buffers +// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart6_TxBuffer[UART6_TX_SIZE]; + +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t Uart6_RxBuffer[UART6_RX_SIZE]; + +// initialization for UART6 +UART_INIT(6, UART6_TX_SIZE, UART6_RX_SIZE) + +// un-initialization for UART6 +UART_UNINIT(6) + +// /////////// +// // UART7 // +// /////////// + +// // pin configuration for UART7 +// // port for TX pin is: GPIOF +// // port for RX pin is: GPIOF +// // TX pin: is GPIOF_7 +// // RX pin: is GPIOF_6 +// // GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping" in STM32F769I datasheet) +// UART_CONFIG_PINS(7, GPIOF, GPIOF, 7, 6, 8) + +// // buffers +// // buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// // because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +// #if defined(__GNUC__) +// __attribute__((aligned (32))) +// #endif +// uint8_t Uart6_TxBuffer[UART7_TX_SIZE]; + +// #if defined(__GNUC__) +// __attribute__((aligned (32))) +// #endif +// uint8_t Uart6_RxBuffer[UART7_RX_SIZE]; + +// // initialization for UART6 +// UART_INIT(7, UART7_TX_SIZE, UART7_RX_SIZE) + +// // un-initialization for UART6 +// UART_UNINIT(7) + +// /////////// +// // UART8 // +// /////////// + +// // pin configuration for UART8 +// // port for TX pin is: GPIOC +// // port for RX pin is: GPIOC +// // TX pin: is GPIOC_6 +// // RX pin: is GPIOC_7 +// // GPIO alternate pin function is 8 (see "Table 13. STM32F765xx, STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping" in STM32F769I datasheet) +// UART_CONFIG_PINS(8, GPIOC, GPIOC, 6, 7, 8) + +// // buffers +// // buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary +// // because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache) +// #if defined(__GNUC__) +// __attribute__((aligned (32))) +// #endif +// uint8_t Uart8_TxBuffer[UART8_TX_SIZE]; + +// #if defined(__GNUC__) +// __attribute__((aligned (32))) +// #endif +// uint8_t Uart8_RxBuffer[UART8_RX_SIZE]; + +// // initialization for UART6 +// UART_INIT(8, UART8_TX_SIZE, UART8_RX_SIZE) + +// // un-initialization for UART6 +// UART_UNINIT(8) diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_windows_devices_serialcommunication_config.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_windows_devices_serialcommunication_config.h new file mode 100644 index 00000000..346f5674 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_windows_devices_serialcommunication_config.h @@ -0,0 +1,108 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +// /////////// +// // UART1 // +// /////////// + +// // enable UART1 +// #define NF_SERIAL_COMM_STM32_UART_USE_UART1 TRUE + +// // buffers size +// // tx buffer size: 256 bytes +// #define UART1_TX_SIZE 256 +// // rx buffer size: 256 bytes +// #define UART1_RX_SIZE 256 + +// /////////// +// // UART2 // +// /////////// + +// // enable UART2 +// #define NF_SERIAL_COMM_STM32_UART_USE_UART2 TRUE + +// // buffers size +// // tx buffer size: 256 bytes +// #define UART2_TX_SIZE 256 +// // rx buffer size: 256 bytes +// #define UART2_RX_SIZE 256 + +// /////////// +// // UART3 // +// /////////// + +// // enable UART5 +// #define NF_SERIAL_COMM_STM32_UART_USE_UART3 TRUE + +// // buffers size +// // tx buffer size: 256 bytes +// #define UART3_TX_SIZE 256 +// // rx buffer size: 256 bytes +// #define UART3_RX_SIZE 256 + +// /////////// +// // UART4 // +// /////////// + +// // enable UART4 +// #define NF_SERIAL_COMM_STM32_UART_USE_UART4 TRUE + +// // buffers size +// // tx buffer size: 256 bytes +// #define UART4_TX_SIZE 256 +// // rx buffer size: 256 bytes +// #define UART4_RX_SIZE 256 + +/////////// +// UART5 // +/////////// + +// enable UART5 +#define NF_SERIAL_COMM_STM32_UART_USE_UART5 TRUE + +// buffers size +// tx buffer size: 256 bytes +#define UART5_TX_SIZE 256 +// rx buffer size: 256 bytes +#define UART5_RX_SIZE 256 + +/////////// +// UART6 // +/////////// + +// enable USART6 +#define NF_SERIAL_COMM_STM32_UART_USE_USART6 TRUE + +// buffers size +// tx buffer size: 256 bytes +#define UART6_TX_SIZE 256 +// rx buffer size: 256 bytes +#define UART6_RX_SIZE 256 + +// /////////// +// // UART7 // +// /////////// + +// // enable UART7 +// #define NF_SERIAL_COMM_STM32_UART_USE_UART7 TRUE + +// // buffers size +// // tx buffer size: 256 bytes +// #define UART7_TX_SIZE 256 +// // rx buffer size: 256 bytes +// #define UART7_RX_SIZE 256 + +// /////////// +// // UART8 // +// /////////// + +// // enable UART8 +// #define NF_SERIAL_COMM_STM32_UART_USE_UART8 TRUE + +// // buffers size +// // tx buffer size: 256 bytes +// #define UART8_TX_SIZE 256 +// // rx buffer size: 256 bytes +// #define UART8_RX_SIZE 256 diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_windows_devices_spi_config.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_windows_devices_spi_config.cpp new file mode 100644 index 00000000..76238dbe --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_windows_devices_spi_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_windows_storage_config.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_windows_storage_config.h new file mode 100644 index 00000000..5dc140d8 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/ST_STM32F769I_DISCOVERY/target_windows_storage_config.h @@ -0,0 +1,13 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +// maps the SD Card driver +#define SD_CARD_DRIVER SDCD2 + +// maps the SD Card detect GPIO definition (in Target_Windows_Storage.c) to board GPIO line (in board.h) +#define SDCARD_LINE_DETECT LINE_SD_DETECT + +// includes SPIFFS in storage +#define USE_SPIFFS_FOR_STORAGE FALSE diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/CMakeLists.txt new file mode 100644 index 00000000..ba2bf0f7 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/CMakeLists.txt @@ -0,0 +1,38 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append target ChibiOS source files +list(APPEND TARGET_CHIBIOS_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/LaunchCLR.c") +list(APPEND TARGET_CHIBIOS_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoSupport_CRC32.c") +list(APPEND TARGET_CHIBIOS_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_ReceiverThread.c") +list(APPEND TARGET_CHIBIOS_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_HAL_Interface.c") +list(APPEND TARGET_CHIBIOS_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/platform_heap.c") +list(APPEND TARGET_CHIBIOS_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Target_BlockStorage_STM32FlashDriver.c") + +# append Target files +list(APPEND TARGET_CHIBIOS_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/platform_BlockStorage.c") + +# include configuration manager file, if feature is enabled +if(NF_FEATURE_HAS_CONFIG_BLOCK) + list(APPEND TARGET_CHIBIOS_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_ConfigurationManager.cpp") +endif() + +# append nanoHAL +list(APPEND TARGET_CHIBIOS_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL.c") +list(APPEND TARGET_CHIBIOS_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Time.cpp") + +# append hard fault handler if the build type is to include debug info +if(CMAKE_BUILD_TYPE STREQUAL "Debug" OR CMAKE_BUILD_TYPE STREQUAL "RelWithDebInfo") + list(APPEND TARGET_CHIBIOS_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/hard_fault_handler.c") +endif() + +# append networking files, if enabled +if(USE_NETWORKING_OPTION) + list(APPEND TARGET_CHIBIOS_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Network.cpp") + list(APPEND TARGET_CHIBIOS_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/target_Network.cpp") +endif() + +# make var global +set(TARGET_CHIBIOS_COMMON_SOURCES ${TARGET_CHIBIOS_COMMON_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/LaunchCLR.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/LaunchCLR.c new file mode 100644 index 00000000..19f441a3 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/LaunchCLR.c @@ -0,0 +1,99 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include + +void LaunchCLR(uint32_t address) +{ + // function pointer to load nanoCLR ResetHandler address + irq_vector_t JumpToNanoCLR; + + // load nanoCLR vector table + const vectors_t* nanoCLRVectorTable = (vectors_t*) address; + + // load the jump address with the nanoCLR ResetHandler address + JumpToNanoCLR = nanoCLRVectorTable->reset_handler; + + // disable all interrupts in ChibiOS + chSysDisable(); + + // clear any pending interrupts to make sure we are jumping straight to nanoCLR ResetHandler + SCB->ICSR &= SCB_ICSR_PENDSVCLR_Msk; + + // need to set stack pointer from CLR vector table + __set_MSP((uint32_t)nanoCLRVectorTable->init_stack); + + // make the jump to nanoCLR, at last + JumpToNanoCLR(); +} + +bool CheckValidCLRImage(uint32_t address) +{ + uint32_t resetVectorAddress; + + // load nanoCLR vector table + const vectors_t* nanoCLRVectorTable = (vectors_t*) address; + + // 1st check: the flash content pointed by the address can't be all 0's neither all F's + // meaning that the Flash is neither 'all burnt' or erased + if( (uint32_t)(*(uint32_t**)((uint32_t*)address)) == 0xFFFFFFFF || + (uint32_t)(*(uint32_t**)((uint32_t*)address)) == 0x00000000 ) + { + // check failed, there is no valid CLR image + return false; + } + + // 2nd check: the content pointed by the reset vector has to be 0xE002 + // that's an assembly "b.n" (branch instruction) the very first one in the Reset_Handler function + // see os\common\startup\ARMCMx\compilers\GCC\vectors.S + + + // for series that have ART Accelerator the handlers addresses stored in the vector table are for ITCM access + // need to parsed them to reach the equivalent address in AXI access + #ifdef FLASHITCM_BASE + + // read address (ITCM) + resetVectorAddress = (uint32_t)((uint32_t*)nanoCLRVectorTable->reset_handler); + // parse it to get the address in the AXI range + resetVectorAddress -= FLASHITCM_BASE; + resetVectorAddress += FLASHAXI_BASE; + + #else + + // "regular" address mapping + resetVectorAddress = (uint32_t)((uint32_t*)nanoCLRVectorTable->reset_handler); + + #endif + + // sanity check for invalid address (out of flash range which causes a hard fault) + if( resetVectorAddress <= FLASH1_MEMORY_StartAddress || + resetVectorAddress >= (FLASH1_MEMORY_StartAddress + FLASH1_MEMORY_Size) ) + { + // check failed, doesn't seem to be a valid CLR image + return false; + } + + // the linker can place this anywhere on the address space because of optimizations so we better check where the reset pointer points to + uint32_t opCodeAddress = (uint32_t)((uint32_t**)nanoCLRVectorTable->reset_handler); + + // real address is -1 + opCodeAddress -= 1; + + uint32_t opCode = *((uint32_t*)opCodeAddress); + if((uint16_t)opCode == 0xE002) + { + // check, there seems to be a valid CLR image + return true; + } + else + { + // got here so there isn't a valid CLR imaged flashed + return false; + } +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/Target_BlockStorage_STM32FlashDriver.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/Target_BlockStorage_STM32FlashDriver.c new file mode 100644 index 00000000..deb991a4 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/Target_BlockStorage_STM32FlashDriver.c @@ -0,0 +1,64 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + + +bool STM32FlashDriver_InitializeDevice(void* context) +{ + (void)context; + + // ChibiOS driver takes care of this, so always true + return true; +} + +bool STM32FlashDriver_UninitializeDevice(void* context) +{ + (void)context; + + // ChibiOS driver takes care of this, so always true + return true; +} + +DeviceBlockInfo* STM32FlashDriver_GetDeviceInfo(void* context) +{ + + MEMORY_MAPPED_NOR_BLOCK_CONFIG* config = context; + + return config->BlockConfig.BlockDeviceInformation; +} + +bool STM32FlashDriver_Read(void* context, ByteAddress startAddress, unsigned int numBytes, unsigned char* buffer) +{ + (void)context; + + // driver doesn't return anything so: we have to perform the operation here... + stm32FlashReadBytes(startAddress, numBytes, buffer); + + // ... and always return true + return true; +} + +bool STM32FlashDriver_Write(void* context, ByteAddress startAddress, unsigned int numBytes, unsigned char* buffer, bool readModifyWrite) +{ + (void)context; + (void)readModifyWrite; + + return stm32FlashWrite(startAddress, numBytes, buffer); +} + +bool STM32FlashDriver_IsBlockErased(void* context, ByteAddress blockAddress, unsigned int length) +{ + (void)context; + + return stm32FlashIsErased(blockAddress, length); +} + +bool STM32FlashDriver_EraseBlock(void* context, ByteAddress address) +{ + (void)context; + + return stm32FlashErase(address); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/Target_Network.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/Target_Network.cpp new file mode 100644 index 00000000..e69baef2 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/Target_Network.cpp @@ -0,0 +1,62 @@ + +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +extern "C" struct netif * nf_getNetif(); +// +// Works with the Target_NetworkConfig to map the Network_Interface_XXXXX calls to the correct driver + + +bool Network_Interface_Bind(int index) +{ + (void)index; + + return true; +} + +int Network_Interface_Open(int index) +{ + HAL_Configuration_NetworkInterface networkConfiguration; + + // load network interface configuration from storage + if(!ConfigurationManager_GetConfigurationBlock((void*)&networkConfiguration, DeviceConfigurationOption_Network, index)) + { + // failed to load configuration + // FIXME output error? + return SOCK_SOCKET_ERROR; + } + _ASSERTE(networkConfiguration.StartupAddressMode > 0); + + switch(index) + { + case 0: + { + // Open the network interface and set its config + // TODO / FIXME + + // Return index to NetIF in its linked list, return 0 (probably right if only interface) + // This used by Network stack to hook in to status/address changes for events to users + + // For now get the Netif number form original Chibios binding code + struct netif * nptr = nf_getNetif(); + return nptr->num; + } + break; + } + return SOCK_SOCKET_ERROR; +} + +bool Network_Interface_Close(int index) +{ + switch(index) + { + case 0: + return true; + } + return false; +} \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/Target_Windows_Storage.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/Target_Windows_Storage.c new file mode 100644 index 00000000..84e61617 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/Target_Windows_Storage.c @@ -0,0 +1,266 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include +#include +#include + +#if HAL_USBH_USE_MSD +#include "usbh/dev/msd.h" +#endif + +// need to declare this here as extern +extern void PostManagedEvent(uint8_t category, uint8_t subCategory, uint16_t data1, uint32_t data2); + +// the drive indexes have to be used instead of fixed drive letters because a target can have one or more +// and those have to follow the sequence that is used in ChibiOS FatFS wrappers +// SD Card (or SPI) is 1st and USB MAS is 2nd (if SD Card is enabled) +// this is also mapped in the FatFS configuration +#if defined(HAL_USE_SDC) + +#define SD_CARD_DRIVE_INDEX "0:" +#define SD_CARD_DRIVE_INDEX_NUMERIC (0) + +#endif + +#if defined(HAL_USE_SDC) + +#define USB_MSD_DRIVE_INDEX "1:" +#define USB_MSD_DRIVE_INDEX_NUMERIC (1) + +#endif + +/////////////////////////////////////////// +// code specific to SD Card + +#if HAL_USE_SDC + +// FS for SD Card mounted and ready +bool sdCardFileSystemReady; + +static FATFS sdCard_FS; +static SDCConfig SDC_CFG; + +// SD Card event sources +static event_source_t sdInsertedEvent, sdRemovedEvent; + +// this timer is used to handle the debounce of SD card detect line +static virtual_timer_t sdCardDebounceTimer; +static bool sdCardPresent; + +// Insertion monitor timer callback function. +static void SdCardInsertionMonitorCallback(void *p) +{ + BaseBlockDevice *bbdp = p; + bool currentStatus; + + chSysLockFromISR(); + + // get current status + currentStatus = blkIsInserted(bbdp); + + if(sdCardPresent == currentStatus) + { + // value hasn't change for debounce interval so this is a valid change + if(currentStatus) + { + chEvtBroadcastI(&sdInsertedEvent); + } + else + { + chEvtBroadcastI(&sdRemovedEvent); + } + } + + chSysUnlockFromISR(); +} + +static void SdCardDetectCallback(void *arg) +{ + BaseBlockDevice* bbdp = (BaseBlockDevice*)arg; + + if(chVTIsArmed(&sdCardDebounceTimer)) + { + // there is a debounce timer already running so this change in pin value should be discarded + return; + } + + // save current status + sdCardPresent = blkIsInserted(bbdp); + + // setup timer + chVTSetI(&sdCardDebounceTimer, TIME_MS2I(SDCARD_POLLING_DELAY), SdCardInsertionMonitorCallback, arg); +} + +// Card insertion event handler +void SdcardInsertHandler(eventid_t id) +{ + FRESULT err; + + (void)id; + + // On insertion SDC initialization and FS mount + if (sdcConnect(&SD_CARD_DRIVER)) + { + return; + } + + err = f_mount(&sdCard_FS, SD_CARD_DRIVE_INDEX, 1); + + if (err != FR_OK) + { + osDelay(1000); + + sdcDisconnect(&SD_CARD_DRIVER); + return; + } + else + { + sdCardFileSystemReady = true; + + // post event to managed app + PostManagedEvent( EVENT_STORAGE, 0, StorageEventType_RemovableDeviceInsertion, SD_CARD_DRIVE_INDEX_NUMERIC ); + } +} + +// Card removal event handler +void SdCardRemoveHandler(eventid_t id) +{ + (void)id; + + sdcDisconnect(&SD_CARD_DRIVER); + + sdCardFileSystemReady = false; + + // post event to managed app + PostManagedEvent( EVENT_STORAGE, 0, StorageEventType_RemovableDeviceRemoval, SD_CARD_DRIVE_INDEX_NUMERIC ); +} + +__attribute__((noreturn)) +void SdCardWorkingThread(void const * argument) +{ + (void)argument; + + event_listener_t sdEventListener0, sdEventListener1; + + const evhandler_t sdcardEventHandler[] = + { + SdcardInsertHandler, + SdCardRemoveHandler + }; + + sdCardFileSystemReady = false; + + // activates the SDC driver using default configuration + sdcStart(&SD_CARD_DRIVER, &SDC_CFG); + + // setup line event in SD Card detect GPIO + palEnableLineEvent(SDCARD_LINE_DETECT, PAL_EVENT_MODE_BOTH_EDGES); + palSetLineCallback(SDCARD_LINE_DETECT, SdCardDetectCallback, &SD_CARD_DRIVER); + + // init timer + chVTObjectInit(&sdCardDebounceTimer); + + // init events + chEvtObjectInit(&sdInsertedEvent); + chEvtObjectInit(&sdRemovedEvent); + + // register events + chEvtRegister(&sdInsertedEvent, &sdEventListener0, 0); + chEvtRegister(&sdRemovedEvent, &sdEventListener1, 1); + + // force initial check + SdCardDetectCallback(&SD_CARD_DRIVER); + + for(;;) + { + chEvtDispatch(sdcardEventHandler, chEvtWaitOneTimeout(ALL_EVENTS, TIME_MS2I(SDCARD_POLLING_DELAY))); + } +} + +#endif + +/////////////////////////////////////////// + +/////////////////////////////////////////// +// code specific to USB MSD +#if HAL_USBH_USE_MSD + +// FS for USB MSD mounted and ready +bool usbMsdFileSystemReady; + +static FATFS usbMsd_FS; + +__attribute__((noreturn)) +void UsbMsdWorkingThread(void const * argument) +{ + (void)argument; + + FRESULT err; + + usbMsdFileSystemReady = false; + + // start USB host + usbhStart(&USB_MSD_DRIVER); + + USBHMassStorageLUNDriver* msBlk = (USBHMassStorageLUNDriver*)&MSBLKD[0]; + + for(;;) + { + osDelay(USB_MSD_POLLING_INTERVAL); + + if (blkGetDriverState(msBlk) == BLK_ACTIVE) + { + // file system can't be ready + usbMsdFileSystemReady = false; + + // BLK: Active, connect + usbhmsdLUNConnect(msBlk); + } + + if (blkGetDriverState(msBlk) == BLK_READY) + { + // BLK: Ready + if(!usbMsdFileSystemReady) + { + // USB MSD file system not ready + // mount drive + err = f_mount(&usbMsd_FS, USB_MSD_DRIVE_INDEX, 1); + + if (err != FR_OK) + { + // mount operation failed, disconnect + usbhmsdLUNDisconnect(msBlk); + } + else + { + usbMsdFileSystemReady = true; + + // post event to managed app + PostManagedEvent( EVENT_STORAGE, 0, StorageEventType_RemovableDeviceInsertion, USB_MSD_DRIVE_INDEX_NUMERIC ); + } + } + } + + if (blkGetDriverState(msBlk) == BLK_STOP) + { + if(usbMsdFileSystemReady) + { + usbMsdFileSystemReady = false; + + // post event to managed app + PostManagedEvent( EVENT_STORAGE, 0, StorageEventType_RemovableDeviceRemoval, USB_MSD_DRIVE_INDEX_NUMERIC ); + } + } + + usbhMainLoop(&USB_MSD_DRIVER); + } +} + +#endif diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/WireProtocol_HAL_Interface.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/WireProtocol_HAL_Interface.c new file mode 100644 index 00000000..bcfbbbc0 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/WireProtocol_HAL_Interface.c @@ -0,0 +1,201 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include + +#if (HAL_USE_SERIAL_USB == TRUE) +#include "usbcfg.h" +#elif (HAL_USE_SERIAL == TRUE) +#include +#endif + +WP_Message inboundMessage; + +//////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////// +// The functions below are the ones that need to be ported to new channels/HALs when required +// These are to be considered as a reference implementations when working on new ports +// +// This reference implementation provides communication through: +// - serial port (UART/USART) +// - serial over USB (USB CDC class device) +// +//////////////////////////////////////////////////////////////////////////////////////////////// + +#if (HAL_USE_SERIAL_USB == TRUE) + +int WP_ReceiveBytes(uint8_t* ptr, uint16_t* size) +{ + // save for latter comparison + uint16_t requestedSize = *size; + + // sanity check for request of 0 size + if(*size) + { + ////////////////////////////////////////////////////////// + // PORTING CHANGE REQUIRED HERE // + ////////////////////////////////////////////////////////// + // change here to read (size) bytes from the input stream + // preferably with read timeout and being able to check + // if the requested number of bytes was actually read + ////////////////////////////////////////////////////////// + + // read from serial stream + size_t read = streamRead(&SDU1, ptr, *size); + + ptr += read; + *size -= read; + + TRACE( TRACE_STATE, "RXMSG: Expecting %d bytes, received %d.\n",requestedSize, read); + + // check if the requested read matches the actual read count + return (requestedSize == read); + } + + return true; +} +#elif (HAL_USE_SERIAL == TRUE) + +int WP_ReceiveBytes(uint8_t* ptr, uint16_t* size) +{ + // save for latter comparison + uint16_t requestedSize = *size; + + // sanity check for request of 0 size + if(*size) + { + ////////////////////////////////////////////////////////// + // PORTING CHANGE REQUIRED HERE // + ////////////////////////////////////////////////////////// + // change here to read (size) bytes from the input stream + // preferably with read timeout and being able to check + // if the requested number of bytes was actually read + ////////////////////////////////////////////////////////// + + // non blocking read from serial port with 100ms timeout + volatile size_t read = sdReadTimeout(&SERIAL_DRIVER, ptr, *size, TIME_MS2I(250)); + + ptr += read; + *size -= read; + + TRACE( TRACE_STATE, "RXMSG: Expecting %d bytes, received %d.\n",requestedSize, read); + + // check if the requested read matches the actual read count + return (requestedSize == read); + } + + return true; +} + +#else +#error "Wire Protocol needs a transport. Please make sure that HAL_USE_SERIAL and/or HAL_USE_SERIAL_USB are set to TRUE in 'halconf.h'" +#endif + +#if (HAL_USE_SERIAL_USB == TRUE) + +int WP_TransmitMessage(WP_Message* message) +{ + uint32_t writeResult; + bool operationResult = false; + + /////////////////////////////////////////////////////////// + // PORTING CHANGE REQUIRED HERE // + /////////////////////////////////////////////////////////// + // change here to write (size) bytes to the output stream + // preferably with timeout and being able to check + // if the write was sucessfull or at least buffered + ////////////////////////////////////////////////////////// + + TRACE( TRACE_HEADERS, "TXMSG: 0x%08X, 0x%08X, 0x%08X\n", message->m_header.m_cmd, message->m_header.m_flags, message->m_header.m_size ); + + // write header to output stream + writeResult = streamWrite(&SDU1, (const uint8_t *)&message->m_header, sizeof(message->m_header)); + + if(writeResult == sizeof(message->m_header)) + { + operationResult = true; + + // if there is anything on the payload send it to the output stream + if(message->m_header.m_size && message->m_payload) + { + /////////////////////////////////////////////////////////// + // PORTING CHANGE REQUIRED HERE // + /////////////////////////////////////////////////////////// + // see description above + ////////////////////////////////////////////////////////// + + // reset flag + operationResult = false; + + writeResult = streamWrite(&SDU1, message->m_payload, message->m_header.m_size); + + if(writeResult == message->m_header.m_size) + { + operationResult = true; + + TRACE0( TRACE_ERRORS, "TXMSG: OK\n"); + } + } + } + + return operationResult; +} +#elif (HAL_USE_SERIAL == TRUE) + +int WP_TransmitMessage(WP_Message* message) +{ + uint32_t writeResult; + bool operationResult = false; + + /////////////////////////////////////////////////////////// + // PORTING CHANGE REQUIRED HERE // + /////////////////////////////////////////////////////////// + // change here to write (size) bytes to the output stream + // preferably with timeout and being able to check + // if the write was sucessfull or at least buffered + ////////////////////////////////////////////////////////// + + TRACE( TRACE_HEADERS, "TXMSG: 0x%08X, 0x%08X, 0x%08X\n", message->m_header.m_cmd, message->m_header.m_flags, message->m_header.m_size ); + + // write header to output stream + writeResult = chnWriteTimeout(&SERIAL_DRIVER, (const uint8_t *)&message->m_header, sizeof(message->m_header), TIME_MS2I(250)); + + if(writeResult == sizeof(message->m_header)) + { + operationResult = true; + + // if there is anything on the payload send it to the output stream + if(message->m_header.m_size && message->m_payload) + { + /////////////////////////////////////////////////////////// + // PORTING CHANGE REQUIRED HERE // + /////////////////////////////////////////////////////////// + // see description above + ////////////////////////////////////////////////////////// + + // reset flag + operationResult = false; + + writeResult = chnWriteTimeout(&SERIAL_DRIVER, message->m_payload, message->m_header.m_size, TIME_MS2I(250)); + + if(writeResult == message->m_header.m_size) + { + operationResult = true; + + TRACE0( TRACE_ERRORS, "TXMSG: OK\n"); + } + } + } + + return operationResult; +} + +#else +#error "Wire Protocol needs a transport. Please make sure that HAL_USE_SERIAL and/or HAL_USE_SERIAL_USB are set to TRUE in 'halconf.h'" +#endif diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/WireProtocol_ReceiverThread.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/WireProtocol_ReceiverThread.c new file mode 100644 index 00000000..e2a4aa9f --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/WireProtocol_ReceiverThread.c @@ -0,0 +1,63 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include + +extern WP_Message inboundMessage; + +#if (HAL_USE_SERIAL_USB == TRUE) +extern SerialUSBDriver SDU1; +#endif + +// This thread needs to be implemented at ChibiOS level because it has to include a call to chThdShouldTerminateX() +// in case the thread is requested to terminate by the CMSIS call osThreadTerminate() + +__attribute__((noreturn)) +void ReceiverThread(void const * argument) +{ + (void)argument; + + osDelay(500); + + #if (HAL_USE_STM32_CRC == TRUE) + // startup crc + crcStart(NULL); + #endif + + // loop until thread receives a request to terminate + while (1) { + + #if (HAL_USE_SERIAL_USB == TRUE) + // only bother to wait for WP message is USB is connected + if (SDU1.config->usbp->state == USB_ACTIVE) + { + #endif + + WP_Message_Initialize(&inboundMessage); + WP_Message_PrepareReception(&inboundMessage); + + WP_Message_Process(&inboundMessage); + + #if (HAL_USE_SERIAL_USB == TRUE) + // pass control to the OS + osThreadYield(); + } + else + { + osDelay(1000); + } + + #elif (HAL_USE_SERIAL == TRUE) + // delay here to give other threads a chance to run + osDelay(100); + #endif + + } + + // this function never returns +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/hard_fault_handler.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/hard_fault_handler.c new file mode 100644 index 00000000..97668a42 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/hard_fault_handler.c @@ -0,0 +1,161 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +//See http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/BABBGBEC.html +typedef enum { + Reset = 1, + NMI = 2, + HardFault = 3, + MemManage = 4, + BusFault = 5, + UsageFault = 6, +} FaultType; + +#if defined(STM32F4XX) || defined(STM32F7XX) + +void NMI_Handler(void) { + while(1); +} + +#endif + +// dev note: on all the following the variables need to be declared as volatile so they don't get optimized out by the linker +// dev note: the pragma below is to ignore the warning because the variables aren't actually being used despite needing to remain there for debug + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-variable" +#endif + +void HardFault_Handler(void) { + + //Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info + struct port_extctx ctx; + + //Get thread context. Contains main registers including PC and LR + memcpy(&ctx, (void*)__get_PSP(), sizeof(struct port_extctx)); + (void)ctx; + + //Interrupt status register: Which interrupt have we encountered, e.g. HardFault? + volatile FaultType faultType = (FaultType)__get_IPSR(); + + // these are not available in all the STM32 series +#if defined(STM32F4XX) || defined(STM32F7XX) + + //Flags about hardfault / busfault + //See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference + volatile bool isFaultPrecise = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 1) ? true : false); + volatile bool isFaultImprecise = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 2) ? true : false); + volatile bool isFaultOnUnstacking = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 3) ? true : false); + volatile bool isFaultOnStacking = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 4) ? true : false); + volatile bool isFaultAddressValid = ((SCB->CFSR >> SCB_CFSR_BUSFAULTSR_Pos) & (1 << 7) ? true : false); + + // Hard Fault Status Register + volatile unsigned long _HFSR = (*((volatile unsigned long *)(0xE000ED2C))) ; + + // Debug Fault Status Register + volatile unsigned long _DFSR = (*((volatile unsigned long *)(0xE000ED30))) ; + + // Auxiliary Fault Status Register + volatile unsigned long _AFSR = (*((volatile unsigned long *)(0xE000ED3C))) ; + + // Read the Fault Address Registers. These may not contain valid values. + // Check BFARVALID/MMARVALID to see if they are valid values + + // MemManage Fault Address Register + volatile unsigned long _MMAR = (*((volatile unsigned long *)(0xE000ED34))) ; + + //For HardFault/BusFault this is the address that was accessed causing the error + volatile uint32_t faultAddress = SCB->BFAR; + +#endif + + // forces a breakpoint causing the debugger to stop + // if no debugger is attached this is ignored + __asm volatile("BKPT #0\n"); + + // If no debugger connected, just reset the board + NVIC_SystemReset(); +} + +void BusFault_Handler(void) __attribute__((alias("HardFault_Handler"))); + +void UsageFault_Handler(void) { + + //Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info + //Get thread context. Contains main registers including PC and LR + struct port_extctx ctx; + memcpy(&ctx, (void*)__get_PSP(), sizeof(struct port_extctx)); + (void)ctx; + + //Interrupt status register: Which interrupt have we encountered, e.g. HardFault? + FaultType faultType = (FaultType)__get_IPSR(); + (void)faultType; + + // these are not available in all the STM32 series +#if defined(STM32F4XX) || defined(STM32F7XX) + + //Flags about hardfault / busfault + //See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference + volatile bool isUndefinedInstructionFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 0) ? true : false); + volatile bool isEPSRUsageFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 1) ? true : false); + volatile bool isInvalidPCFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 2) ? true : false); + volatile bool isNoCoprocessorFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 3) ? true : false); + volatile bool isUnalignedAccessFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 8) ? true : false); + volatile bool isDivideByZeroFault = ((SCB->CFSR >> SCB_CFSR_USGFAULTSR_Pos) & (1 << 9) ? true : false); + +#endif + + // forces a breakpoint causing the debugger to stop + // if no debugger is attached this is ignored + __asm volatile("BKPT #0\n"); + + // If no debugger connected, just reset the board + NVIC_SystemReset(); +} + +void MemManage_Handler(void) { + + //Copy to local variables (not pointers) to allow GDB "i loc" to directly show the info + //Get thread context. Contains main registers including PC and LR + struct port_extctx ctx; + memcpy(&ctx, (void*)__get_PSP(), sizeof(struct port_extctx)); + (void)ctx; + + //Interrupt status register: Which interrupt have we encountered, e.g. HardFault? + FaultType faultType = (FaultType)__get_IPSR(); + (void)faultType; + + // these are not available in all the STM32 series +#if defined(STM32F4XX) || defined(STM32F7XX) + + //For HardFault/BusFault this is the address that was accessed causing the error + volatile uint32_t faultAddress = SCB->MMFAR; + + //Flags about hardfault / busfault + //See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/Cihdjcfc.html for reference + volatile bool isInstructionAccessViolation = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 0) ? true : false); + volatile bool isDataAccessViolation = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 1) ? true : false); + volatile bool isExceptionUnstackingFault = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 3) ? true : false); + volatile bool isExceptionStackingFault = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 4) ? true : false); + volatile bool isFaultAddressValid = ((SCB->CFSR >> SCB_CFSR_MEMFAULTSR_Pos) & (1 << 7) ? true : false); + +#endif + + // forces a breakpoint causing the debugger to stop + // if no debugger is attached this is ignored + __asm volatile("BKPT #0\n"); + + // If no debugger connected, just reset the board + NVIC_SystemReset(); +} + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/nanoSupport_CRC32.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/nanoSupport_CRC32.c new file mode 100644 index 00000000..3979ff2a --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/nanoSupport_CRC32.c @@ -0,0 +1,26 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#if defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F2XX) || \ + defined(STM32F4XX) || defined(STM32F7XX) || defined(STM32L0XX) || \ + defined(STM32L1XX) || defined(STM32H7XX) + +// strong implementation of this function specific to the STM32 targets +unsigned int SUPPORT_ComputeCRC(const void* rgBlock, int nLength, unsigned int crc) +{ + crcAquireModule(); + + crc = crcCompute(rgBlock, nLength, crc); + + crcReleaseModule(); + + return crc; +}; + +#endif diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/platform_BlockStorage.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/platform_BlockStorage.c new file mode 100644 index 00000000..868a5878 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/platform_BlockStorage.c @@ -0,0 +1,22 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// map here the Block Storage Interface to the STM32 driver +IBlockStorageDevice STM32Flash_BlockStorageInterface = +{ + &STM32FlashDriver_InitializeDevice, + &STM32FlashDriver_UninitializeDevice, + &STM32FlashDriver_GetDeviceInfo, + &STM32FlashDriver_Read, + &STM32FlashDriver_Write, + NULL, + &STM32FlashDriver_IsBlockErased, + &STM32FlashDriver_EraseBlock, + NULL, + NULL +}; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/platform_heap.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/platform_heap.c new file mode 100644 index 00000000..87c648d3 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/platform_heap.c @@ -0,0 +1,20 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +void* platform_malloc(size_t size) { + return chHeapAlloc(NULL, size); +} + +void platform_free(void* ptr) { + chHeapFree(ptr); +} + +void* platform_realloc(void* ptr, size_t size) { + (void)size; + + return ptr; +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/rules.ld b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/rules.ld new file mode 100644 index 00000000..4e323fa8 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/rules.ld @@ -0,0 +1,19 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +/* Stack rules inclusion.*/ +INCLUDE rules_stacks.ld + +/* Code rules inclusion.*/ +INCLUDE rules_code.ld + +/* Data rules inclusion.*/ +INCLUDE rules_data.ld + +/* nanoCLR rules inclusion.*/ +INCLUDE rules_clr.ld diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/rules_clr.ld b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/rules_clr.ld new file mode 100644 index 00000000..80cedd4f --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/rules_clr.ld @@ -0,0 +1,21 @@ + SECTIONS +{ + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = LOADADDR(.clr_managed_heap)); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM) - LENGTH(ramvt); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM + + /* RAM space reserved for the vector table */ + .RAMVectorTable (NOLOAD) : ALIGN(4) + { + *(.RAMVectorTable) + } > ramvt +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/rules_code.ld b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/rules_code.ld new file mode 100644 index 00000000..80a49318 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/rules_code.ld @@ -0,0 +1,79 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +__nanoImage_start__ = ORIGIN(flash); +__nanoImage_size__ = LENGTH(flash); +__nanoImage_end__ = __nanoImage_start__ + __nanoImage_size__; +__nanoConfig_start__ = ORIGIN(config); +__nanoConfig_size__ = LENGTH(config); +__nanoConfig_end__ = __nanoConfig_start__ + __nanoConfig_size__; +__deployment_start__ = ORIGIN(deployment); +__deployment_size__ = LENGTH(deployment); +__deployment_end__ = __deployment_start__ + __deployment_size__; + +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : ALIGN(16) + { + KEEP(*(.vectors)) + } > VECTORS_FLASH AT > VECTORS_FLASH_LMA + + .xtors : ALIGN(4) + { + __init_array_start = .; + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + __init_array_end = .; + __fini_array_start = .; + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + __fini_array_end = .; + } > XTORS_FLASH AT > XTORS_FLASH_LMA + + .text : ALIGN(16) + { + *(.text) + *(.text.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > TEXT_FLASH AT > TEXT_FLASH_LMA + + .rodata : ALIGN(4) + { + . = ALIGN(4); + __rodata_base__ = .; + *(.rodata) + *(.rodata.*) + . = ALIGN(4); + __rodata_end__ = .; + } > RODATA_FLASH AT > RODATA_FLASH_LMA + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > VARIOUS_FLASH AT > VARIOUS_FLASH_LMA + + .ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > VARIOUS_FLASH AT > VARIOUS_FLASH_LMA + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > VARIOUS_FLASH AT > VARIOUS_FLASH_LMA + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > VARIOUS_FLASH AT > VARIOUS_FLASH_LMA +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/rules_data.ld b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/rules_data.ld new file mode 100644 index 00000000..18da2784 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/rules_data.ld @@ -0,0 +1,266 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +__ram0_start__ = ORIGIN(ram0); +__ram0_size__ = LENGTH(ram0); +__ram0_end__ = __ram0_start__ + __ram0_size__; +__ram1_start__ = ORIGIN(ram1); +__ram1_size__ = LENGTH(ram1); +__ram1_end__ = __ram1_start__ + __ram1_size__; +__ram2_start__ = ORIGIN(ram2); +__ram2_size__ = LENGTH(ram2); +__ram2_end__ = __ram2_start__ + __ram2_size__; +__ram3_start__ = ORIGIN(ram3); +__ram3_size__ = LENGTH(ram3); +__ram3_end__ = __ram3_start__ + __ram3_size__; +__ram4_start__ = ORIGIN(ram4); +__ram4_size__ = LENGTH(ram4); +__ram4_end__ = __ram4_start__ + __ram4_size__; +__ram5_start__ = ORIGIN(ram5); +__ram5_size__ = LENGTH(ram5); +__ram5_end__ = __ram5_start__ + __ram5_size__; +__ram6_start__ = ORIGIN(ram6); +__ram6_size__ = LENGTH(ram6); +__ram6_end__ = __ram6_start__ + __ram6_size__; +__ram7_start__ = ORIGIN(ram7); +__ram7_size__ = LENGTH(ram7); +__ram7_end__ = __ram7_start__ + __ram7_size__; + +ENTRY(Reset_Handler) + +SECTIONS +{ + .data : ALIGN(4) + { + . = ALIGN(4); + PROVIDE(_textdata = LOADADDR(.data)); + PROVIDE(_data = .); + _textdata_start = LOADADDR(.data); + _data_start = .; + *(.data) + *(.data.*) + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + _data_end = .; + } > DATA_RAM AT > DATA_RAM_LMA + + .bss (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + _bss_start = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(4); + _bss_end = .; + PROVIDE(end = .); + } > BSS_RAM + + .ram0_init : ALIGN(4) + { + . = ALIGN(4); + __ram0_init_text__ = LOADADDR(.ram0_init); + __ram0_init__ = .; + KEEP(*(.ram0_init)) + KEEP(*(.ram0_init.*)) + . = ALIGN(4); + } > ram0 AT > RAM_INIT_FLASH_LMA + + .ram0 (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + __ram0_clear__ = .; + *(.ram0_clear) + *(.ram0_clear.*) + . = ALIGN(4); + __ram0_noinit__ = .; + *(.ram0) + *(.ram0.*) + . = ALIGN(4); + __ram0_free__ = .; + } > ram0 + + .ram1_init : ALIGN(4) + { + . = ALIGN(4); + __ram1_init_text__ = LOADADDR(.ram1_init); + __ram1_init__ = .; + KEEP(*(.ram1_init)) + KEEP(*(.ram1_init.*)) + . = ALIGN(4); + } > ram1 AT > RAM_INIT_FLASH_LMA + + .ram1 (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + __ram1_clear__ = .; + *(.ram1_clear) + *(.ram1_clear.*) + . = ALIGN(4); + __ram1_noinit__ = .; + *(.ram1) + *(.ram1.*) + . = ALIGN(4); + __ram1_free__ = .; + } > ram1 + + .ram2_init : ALIGN(4) + { + . = ALIGN(4); + __ram2_init_text__ = LOADADDR(.ram2_init); + __ram2_init__ = .; + KEEP(*(.ram2_init)) + KEEP(*(.ram2_init.*)) + . = ALIGN(4); + } > ram2 AT > RAM_INIT_FLASH_LMA + + .ram2 (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + __ram2_clear__ = .; + *(.ram2_clear) + *(.ram2_clear.*) + . = ALIGN(4); + __ram2_noinit__ = .; + *(.ram2) + *(.ram2.*) + . = ALIGN(4); + __ram2_free__ = .; + } > ram2 + + .ram3_init : ALIGN(4) + { + . = ALIGN(4); + __ram3_init_text__ = LOADADDR(.ram3_init); + __ram3_init__ = .; + KEEP(*(.ram3_init)) + KEEP(*(.ram3_init.*)) + . = ALIGN(4); + } > ram3 AT > RAM_INIT_FLASH_LMA + + .ram3 (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + __ram3_clear__ = .; + *(.ram3_clear) + *(.ram3_clear.*) + . = ALIGN(4); + __ram3_noinit__ = .; + *(.ram3) + *(.ram3.*) + . = ALIGN(4); + __ram3_free__ = .; + } > ram3 + + .ram4_init : ALIGN(4) + { + . = ALIGN(4); + __ram4_init_text__ = LOADADDR(.ram4_init); + __ram4_init__ = .; + KEEP(*(.ram4_init)) + KEEP(*(.ram4_init.*)) + . = ALIGN(4); + } > ram4 AT > RAM_INIT_FLASH_LMA + + .ram4 (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + __ram4_clear__ = .; + *(.ram4_clear) + *(.ram4_clear.*) + . = ALIGN(4); + __ram4_noinit__ = .; + *(.ram4) + *(.ram4.*) + . = ALIGN(4); + __ram4_free__ = .; + } > ram4 + + .ram5_init : ALIGN(4) + { + . = ALIGN(4); + __ram5_init_text__ = LOADADDR(.ram5_init); + __ram5_init__ = .; + KEEP(*(.ram5_init)) + KEEP(*(.ram5_init.*)) + . = ALIGN(4); + } > ram5 AT > RAM_INIT_FLASH_LMA + + .ram5 (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + __ram5_clear__ = .; + *(.ram5_clear) + *(.ram5_clear.*) + . = ALIGN(4); + __ram5_noinit__ = .; + *(.ram5) + *(.ram5.*) + . = ALIGN(4); + __ram5_free__ = .; + } > ram5 + + .ram6_init : ALIGN(4) + { + . = ALIGN(4); + __ram6_init_text__ = LOADADDR(.ram6_init); + __ram6_init__ = .; + KEEP(*(.ram6_init)) + KEEP(*(.ram6_init.*)) + . = ALIGN(4); + } > ram6 AT > RAM_INIT_FLASH_LMA + + .ram6 (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + __ram6_clear__ = .; + *(.ram6_clear) + *(.ram6_clear.*) + . = ALIGN(4); + __ram6_noinit__ = .; + *(.ram6) + *(.ram6.*) + . = ALIGN(4); + __ram6_free__ = .; + } > ram6 + + .ram7_init : ALIGN(4) + { + . = ALIGN(4); + __ram7_init_text__ = LOADADDR(.ram7_init); + __ram7_init__ = .; + KEEP(*(.ram7_init)) + KEEP(*(.ram7_init.*)) + . = ALIGN(4); + } > ram7 AT > RAM_INIT_FLASH_LMA + + .ram7 (NOLOAD) : ALIGN(4) + { + . = ALIGN(4); + __ram7_clear__ = .; + *(.ram7_clear) + *(.ram7_clear.*) + . = ALIGN(4); + __ram7_noinit__ = .; + *(.ram7) + *(.ram7.*) + . = ALIGN(4); + __ram7_free__ = .; + } > ram7 + + /* The default heap uses the (statically) unused part of a RAM section.*/ + .heap (NOLOAD) : + { + . = ALIGN(8); + __heap_base__ = .; + . += __crt_heap_size__; + . = ALIGN(8); + __heap_end__ = .; + } > HEAP_RAM +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/rules_stacks.ld b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/rules_stacks.ld new file mode 100644 index 00000000..227a90c6 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/rules_stacks.ld @@ -0,0 +1,31 @@ +/* +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2006..2015 Giovanni Di Sirio. All rights reserved. +// See LICENSE file in the project root for full license information. +// +*/ + +SECTIONS +{ + /* Special section for exceptions stack.*/ + .mstack : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + } > MAIN_STACK_RAM + + /* Special section for process stack.*/ + .pstack : + { + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > PROCESS_STACK_RAM +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/targetHAL.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/targetHAL.c new file mode 100644 index 00000000..0088b871 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/targetHAL.c @@ -0,0 +1,50 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +void HAL_AssertEx() +{ + __BKPT(0); + while(true) { /*nop*/ } +} + +#if !defined(BUILD_RTM) + +void HARD_Breakpoint() +{ + __BKPT(0); + while(true) { /*nop*/ } +}; + +#endif // !defined(BUILD_RTM) + +// Provides information whether the configuration block storage requires erase command before sending the update command +// The 'weak' implementation for ChibiOS targets is true +// If a target implements the store differently it has to provide a 'strong' implementation of this. +__nfweak bool Target_ConfigUpdateRequiresErase() +{ + return true; +}; + +bool Target_HasNanoBooter() +{ + return false; +}; + +// declarations of platform capabilities +uint32_t GetPlatformCapabilities() +{ + return 0; +}; + +// declarations of target capabilities +// If a target has something to declare it has to provide a 'strong' implementation of this. +__nfweak uint32_t GetTargetCapabilities() +{ + return TargetCapabilities_JtagUpdate; +}; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/targetHAL_ConfigurationManager.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/targetHAL_ConfigurationManager.cpp new file mode 100644 index 00000000..8a84adf0 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/targetHAL_ConfigurationManager.cpp @@ -0,0 +1,379 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include + +// initialization of configuration manager +// provided as weak so it can be replaced at target level, if required because of the target implementing the storage with a mechanism other then saving to flash +__nfweak void ConfigurationManager_Initialize() +{ + // init g_TargetConfiguration + memset(&g_TargetConfiguration, 0, sizeof(HAL_TARGET_CONFIGURATION)); + + // enumerate the blocks + ConfigurationManager_EnumerateConfigurationBlocks(); +}; + +// Enumerates the configuration blocks from the configuration flash sector +// it's implemented with 'weak' attribute so it can be replaced at target level if a different persistance mechanism is used +__nfweak void ConfigurationManager_EnumerateConfigurationBlocks() +{ + // start checking if this device has config block + if(((uint32_t)&__nanoConfig_end__ - (uint32_t)&__nanoConfig_start__) > 0) + { + // find network configuration blocks + HAL_CONFIGURATION_NETWORK* networkConfigs = (HAL_CONFIGURATION_NETWORK*)ConfigurationManager_FindNetworkConfigurationBlocks((uint32_t)&__nanoConfig_start__, (uint32_t)&__nanoConfig_end__); + + // check network configs count + if(networkConfigs->Count == 0) + { + // there is no network config block available, get a default + HAL_Configuration_NetworkInterface* networkConfig = (HAL_Configuration_NetworkInterface*)platform_malloc(sizeof(HAL_Configuration_NetworkInterface)); + + if(InitialiseNetworkDefaultConfig(networkConfig, 0)) + { + // config block created, store it + ConfigurationManager_StoreConfigurationBlock(networkConfig, DeviceConfigurationOption_Network, 0, sizeof(HAL_Configuration_NetworkInterface), 0); + + // have to enumerate again to pick it up + networkConfigs = (HAL_CONFIGURATION_NETWORK*)ConfigurationManager_FindNetworkConfigurationBlocks((uint32_t)&__nanoConfig_start__, (uint32_t)&__nanoConfig_end__); + } + + platform_free(networkConfig); + } + + // find wireless 80211 network configuration blocks + HAL_CONFIGURATION_NETWORK_WIRELESS80211* networkWirelessConfigs = (HAL_CONFIGURATION_NETWORK_WIRELESS80211*)ConfigurationManager_FindNetworkWireless80211ConfigurationBlocks((uint32_t)&__nanoConfig_start__, (uint32_t)&__nanoConfig_end__); + + // find X509 certificate blocks + HAL_CONFIGURATION_X509_CERTIFICATE* certificateStore = (HAL_CONFIGURATION_X509_CERTIFICATE*)ConfigurationManager_FindX509CertificateConfigurationBlocks((uint32_t)&__nanoConfig_start__, (uint32_t)&__nanoConfig_end__); + + // alloc memory for g_TargetConfiguration + // because this is a struct of structs that use flexible members the memory has to be allocated from the heap + // the malloc size for each struct is computed separately + uint32_t sizeOfNetworkInterfaceConfigs = offsetof(HAL_CONFIGURATION_NETWORK, Configs) + networkConfigs->Count * sizeof(networkConfigs->Configs[0]); + uint32_t sizeOfWireless80211Configs = offsetof(HAL_CONFIGURATION_NETWORK_WIRELESS80211, Configs) + networkWirelessConfigs->Count * sizeof(networkWirelessConfigs->Configs[0]); + uint32_t sizeOfX509CertificateStore = offsetof(HAL_CONFIGURATION_X509_CERTIFICATE, Certificates) + certificateStore->Count * sizeof(certificateStore->Certificates[0]); + + g_TargetConfiguration.NetworkInterfaceConfigs = (HAL_CONFIGURATION_NETWORK*)platform_malloc(sizeOfNetworkInterfaceConfigs); + g_TargetConfiguration.Wireless80211Configs = (HAL_CONFIGURATION_NETWORK_WIRELESS80211*)platform_malloc(sizeOfWireless80211Configs); + g_TargetConfiguration.CertificateStore = (HAL_CONFIGURATION_X509_CERTIFICATE*)platform_malloc(sizeOfX509CertificateStore); + + // copy structs to g_TargetConfiguration + memcpy((HAL_CONFIGURATION_NETWORK*)g_TargetConfiguration.NetworkInterfaceConfigs, networkConfigs, sizeOfNetworkInterfaceConfigs); + memcpy((HAL_CONFIGURATION_NETWORK_WIRELESS80211*)g_TargetConfiguration.Wireless80211Configs, networkWirelessConfigs, sizeOfWireless80211Configs); + memcpy((HAL_CONFIGURATION_X509_CERTIFICATE*)g_TargetConfiguration.CertificateStore, certificateStore, sizeOfX509CertificateStore); + + // now free the memory of the original structs + platform_free(networkConfigs); + platform_free(networkWirelessConfigs); + platform_free(certificateStore); + } + else + { + // no config block + } +} + +// Gets the network configuration block from the configuration flash sector +// it's implemented with 'weak' attribute so it can be replaced at target level if a different persistance mechanism is used +__nfweak bool ConfigurationManager_GetConfigurationBlock(void* configurationBlock, DeviceConfigurationOption configuration, uint32_t configurationIndex) +{ + int sizeOfBlock = 0; + uint8_t* blockAddress = NULL; + + // validate if the requested block exists + // Count has to be non zero + // requested Index has to exist (array index starts at zero, so need to add one) + if(configuration == DeviceConfigurationOption_Network) + { + if( g_TargetConfiguration.NetworkInterfaceConfigs->Count == 0 || + (configurationIndex + 1) > g_TargetConfiguration.NetworkInterfaceConfigs->Count) + { + // the requested config block is beyond the available count + return false; + } + + // set block size + sizeOfBlock = sizeof(HAL_Configuration_NetworkInterface); + + // get block address + blockAddress = (uint8_t*)g_TargetConfiguration.NetworkInterfaceConfigs->Configs[configurationIndex]; + } + else if(configuration == DeviceConfigurationOption_Wireless80211Network) + { + if(g_TargetConfiguration.Wireless80211Configs->Count == 0 || + (configurationIndex + 1) > g_TargetConfiguration.Wireless80211Configs->Count) + { + return FALSE; + } + + // set block size + sizeOfBlock = sizeof(HAL_Configuration_Wireless80211); + + // get block address + blockAddress = (uint8_t*)g_TargetConfiguration.Wireless80211Configs->Configs[configurationIndex]; + } + else if(configuration == DeviceConfigurationOption_X509CaRootBundle) + { + if(g_TargetConfiguration.CertificateStore->Count == 0 || + (configurationIndex + 1) > g_TargetConfiguration.CertificateStore->Count) + { + return FALSE; + } + + // get block address + blockAddress = (uint8_t*)g_TargetConfiguration.CertificateStore->Certificates[configurationIndex]; + + // set block size + // because X509 certificate has a variable length need to compute the block size in two steps + sizeOfBlock = offsetof(HAL_Configuration_X509CaRootBundle, Certificate); + sizeOfBlock += ((HAL_Configuration_X509CaRootBundle*)blockAddress)->CertificateSize; + } + + // copy the config block content to the pointer in the argument + memcpy(configurationBlock, blockAddress, sizeOfBlock); + + return TRUE; +} + +// Stores the configuration block to the configuration flash sector +// NOTE: because inserting or removing a configuration block it's very 'RAM expensive' we choose not to support those operations +// the host debugger will have to be used to manage these operations on the device configuration collection +// it's implemented with 'weak' attribute so it can be replaced at target level if a different persistance mechanism is used +__nfweak bool ConfigurationManager_StoreConfigurationBlock(void* configurationBlock, DeviceConfigurationOption configuration, uint32_t configurationIndex, uint32_t blockSize, uint32_t offset) +{ + ByteAddress storageAddress = 0; + bool requiresEnumeration = FALSE; + bool success = FALSE; + + if(configuration == DeviceConfigurationOption_Network) + { + if( g_TargetConfiguration.NetworkInterfaceConfigs == NULL || + ( g_TargetConfiguration.NetworkInterfaceConfigs->Count == 0 && + configurationIndex == 0 )) + { + // there is no network config block, we are storing the default one + // THIS IS THE ONLY CONFIG BLOCK THAT'S AUTO-CREATED + // OK to continue + // set storage address as the start of the flash configuration sector + storageAddress = (ByteAddress)&__nanoConfig_start__; + } + else + { + // the requested config block is beyond the available count + if((configurationIndex + 1) > g_TargetConfiguration.NetworkInterfaceConfigs->Count) + { + return FALSE; + } + + // set storage address from block address, plus the requested offset + storageAddress = (ByteAddress)g_TargetConfiguration.NetworkInterfaceConfigs->Configs[configurationIndex] + offset; + } + + // set block size, in case it's not already set + blockSize = sizeof(HAL_Configuration_NetworkInterface); + + // make sure the config block marker is set + memcpy(configurationBlock, c_MARKER_CONFIGURATION_NETWORK_V1, sizeof(c_MARKER_CONFIGURATION_NETWORK_V1)); + + _ASSERTE(((HAL_Configuration_NetworkInterface*)configurationBlock)->StartupAddressMode > 0); + } + else if(configuration == DeviceConfigurationOption_Wireless80211Network) + { + if( g_TargetConfiguration.Wireless80211Configs == NULL || + (g_TargetConfiguration.Wireless80211Configs->Count == 0 || + (configurationIndex + 1) > g_TargetConfiguration.Wireless80211Configs->Count)) + { + // there is no room for this block, or there are no blocks stored at all + // failing the operation + return FALSE; + } + + // set storage address from block address, plus the requested offset + storageAddress = (ByteAddress)g_TargetConfiguration.Wireless80211Configs->Configs[configurationIndex] + offset; + + // set block size, in case it's not already set + blockSize = sizeof(HAL_Configuration_Wireless80211); + + // make sure the config block marker is set + memcpy(configurationBlock, c_MARKER_CONFIGURATION_WIRELESS80211_V1, sizeof(c_MARKER_CONFIGURATION_WIRELESS80211_V1)); + } + else if(configuration == DeviceConfigurationOption_X509CaRootBundle) + { + if( g_TargetConfiguration.Wireless80211Configs == NULL || + (g_TargetConfiguration.CertificateStore->Count == 0 || + (configurationIndex + 1) > g_TargetConfiguration.CertificateStore->Count)) + { + // there is no room for this block, or there are no blocks stored at all + // failing the operation + return FALSE; + } + + // set storage address from block address, plus the requested offset + storageAddress = (ByteAddress)g_TargetConfiguration.CertificateStore->Certificates[configurationIndex] + offset; + + // set block size, in case it's not already set + // because X509 certificate has a variable length need to compute the block size in two steps + blockSize = offsetof(HAL_Configuration_X509CaRootBundle, Certificate); + blockSize += ((HAL_Configuration_X509CaRootBundle*)configurationBlock)->CertificateSize; + + // make sure the config block marker is set + memcpy(configurationBlock, c_MARKER_CONFIGURATION_X509CAROOTBUNDLE_V1, sizeof(c_MARKER_CONFIGURATION_X509CAROOTBUNDLE_V1)); + } + else if(configuration == DeviceConfigurationOption_All) + { + // particular situation where we are receiving the full configuration block + + // set storage address as the start of the flash configuration sector, plus the requested offset + storageAddress = (ByteAddress)&__nanoConfig_start__ + offset; + + // always enumerate the blocks again after storing it + requiresEnumeration = TRUE; + + // for save all the block size has to be provided, check that + if(blockSize == 0) + { + return FALSE; + } + } + + // copy the config block content to the config block storage + success = STM32FlashDriver_Write(NULL, storageAddress, blockSize, (unsigned char*)configurationBlock, true); + + if(success == TRUE && requiresEnumeration) + { + // free the current allocation(s) + platform_free(g_TargetConfiguration.NetworkInterfaceConfigs); + platform_free(g_TargetConfiguration.Wireless80211Configs); + platform_free(g_TargetConfiguration.CertificateStore); + + // perform enumeration of configuration blocks + ConfigurationManager_EnumerateConfigurationBlocks(); + } + + return success; +} + +// Updates a configuration block in the configuration flash sector +// The flash sector has to be erased before writing the updated block +// it's implemented with 'weak' attribute so it can be replaced at target level if a different persistance mechanism is used +__nfweak bool ConfigurationManager_UpdateConfigurationBlock(void* configurationBlock, DeviceConfigurationOption configuration, uint32_t configurationIndex) +{ + ByteAddress storageAddress; + uint32_t blockOffset; + uint8_t* blockAddressInCopy; + uint32_t blockSize; + bool success = FALSE; + + // config sector size + int sizeOfConfigSector = (uint32_t)&__nanoConfig_end__ - (uint32_t)&__nanoConfig_start__; + + // allocate memory from CRT heap + uint8_t* configSectorCopy = (uint8_t*)platform_malloc(sizeOfConfigSector); + + if(configSectorCopy != NULL) + { + // copy config sector from flash to RAM + memcpy(configSectorCopy, &__nanoConfig_start__, sizeOfConfigSector); + + // find out the address for the config block to update in the configSectorCopy + // because we are copying back the config block to flash and just replacing the config block content + // the addresses in g_TargetConfiguration will remain the same + // plus we can calculate the offset of the config block from g_TargetConfiguration + if(configuration == DeviceConfigurationOption_Network) + { + // get storage address from block address + storageAddress = (ByteAddress)g_TargetConfiguration.NetworkInterfaceConfigs->Configs[configurationIndex]; + + // set block size, in case it's not already set + blockSize = sizeof(HAL_Configuration_NetworkInterface); + + // make sure the config block marker is set + memcpy(configurationBlock, c_MARKER_CONFIGURATION_NETWORK_V1, sizeof(c_MARKER_CONFIGURATION_NETWORK_V1)); + + _ASSERTE(((HAL_Configuration_NetworkInterface*)configurationBlock)->StartupAddressMode > 0); + } + else if(configuration == DeviceConfigurationOption_Wireless80211Network) + { + // storage address from block address + storageAddress = (ByteAddress)g_TargetConfiguration.Wireless80211Configs->Configs[configurationIndex]; + + // set block size, in case it's not already set + blockSize = sizeof(HAL_Configuration_Wireless80211); + + // make sure the config block marker is set + memcpy(configurationBlock, c_MARKER_CONFIGURATION_WIRELESS80211_V1, sizeof(c_MARKER_CONFIGURATION_WIRELESS80211_V1)); + } + else if(configuration == DeviceConfigurationOption_X509CaRootBundle) + { + // storage address from block address + storageAddress = (ByteAddress)g_TargetConfiguration.CertificateStore->Certificates[configurationIndex]; + + // set block size, in case it's not already set + // because X509 certificate has a variable length need to compute the block size in two steps + blockSize = offsetof(HAL_Configuration_X509CaRootBundle, Certificate); + blockSize += ((HAL_Configuration_X509CaRootBundle*)configurationBlock)->CertificateSize; + + // make sure the config block marker is set + memcpy(configurationBlock, c_MARKER_CONFIGURATION_X509CAROOTBUNDLE_V1, sizeof(c_MARKER_CONFIGURATION_X509CAROOTBUNDLE_V1)); + } + else + { + // this not a valid configuration option to update, quit + // free memory first + platform_free(configSectorCopy); + + return FALSE; + } + + // erase config sector + if(STM32FlashDriver_EraseBlock(NULL, (uint32_t)&__nanoConfig_start__) == TRUE) + { + // flash block is erased + + // subtract the start address of config sector to get the offset + blockOffset = storageAddress - (uint32_t)&__nanoConfig_start__; + + // set pointer to block to udpate + blockAddressInCopy = configSectorCopy + blockOffset; + + // replace config block with new content by replacing memory + memcpy(blockAddressInCopy, configSectorCopy, blockSize); + + // copy the config block copy back to the config block storage + success = STM32FlashDriver_Write(NULL, (uint32_t)&__nanoConfig_start__, sizeOfConfigSector, (unsigned char*)configSectorCopy, true); + } + + // free memory + platform_free(configSectorCopy); + } + + return success; +} + +// Default initialisation for wireless config block +// it's implemented with 'weak' attribute so it can be replaced at target level if different configurations are intended +__nfweak void InitialiseWirelessDefaultConfig(HAL_Configuration_Wireless80211 * pconfig, uint32_t configurationIndex) +{ + (void)pconfig; + (void)configurationIndex; + + // currently empty as no ChibiOS target has Wireless 802.11 interface +} + +// Default initialisation for Network interface config blocks +// it's implemented with 'weak' attribute so it can be replaced at target level if different configurations are intended +__nfweak bool InitialiseNetworkDefaultConfig(HAL_Configuration_NetworkInterface * pconfig, uint32_t configurationIndex) +{ + (void)pconfig; + (void)configurationIndex; + + // can't create a "default" network config because we are lacking definition of a MAC address + return FALSE; +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/targetHAL_Network.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/targetHAL_Network.cpp new file mode 100644 index 00000000..e7b265ca --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/targetHAL_Network.cpp @@ -0,0 +1,71 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +// This file includes the platform and board specific Network Intialisation + +#include +#include + + +// this is the declaration for the callback implement in nf_sys_arch.c +extern "C" void set_signal_sock_function( void (*funcPtr)() ); + +// +// Callback from lwIP on event +// +void sys_signal_sock_event() +{ + Events_Set(SYSTEM_EVENT_FLAG_SOCKET); +} + +void nanoHAL_Network_Initialize() +{ + // Initialise the lwIP CLR signal callback + set_signal_sock_function( &sys_signal_sock_event ); + + // get network configuration, if available + if(g_TargetConfiguration.NetworkInterfaceConfigs->Count == 0) + { + // there is no networking configuration block, can't proceed + return; + } + + HAL_Configuration_NetworkInterface networkConfig; + + if(ConfigurationManager_GetConfigurationBlock((void *)&networkConfig, DeviceConfigurationOption_Network, 0) == true) + { + // build lwIP configuration + struct lwipthread_opts lwipOptions; + + // grab MAC address + lwipOptions.macaddress = (uint8_t *)networkConfig.MacAddress; + + // static or dinamic address + if(networkConfig.StartupAddressMode == AddressMode_Static) + { + // IPv4 configs + lwipOptions.address = networkConfig.IPv4Address; + lwipOptions.netmask = networkConfig.IPv4NetMask; + lwipOptions.gateway = networkConfig.IPv4GatewayAddress; + } + else if(networkConfig.StartupAddressMode == AddressMode_DHCP) + { + // clear IPv4 configs + lwipOptions.address = 0; + lwipOptions.netmask = 0; + lwipOptions.gateway = 0; + } + + // set address mode option + // our enum follows lwIP defines for address mode + lwipOptions.addrMode = (net_addr_mode_t)networkConfig.StartupAddressMode; + + // we could consider making the device name configurable (or maybe not) + lwipOptions.ourHostName = "nanodevice"; + + // Start lwIP thread in ChibiOS bindings using the above options + lwipInit(&lwipOptions); + } +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/targetHAL_Time.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/targetHAL_Time.cpp new file mode 100644 index 00000000..4b11d4f0 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/common/targetHAL_Time.cpp @@ -0,0 +1,54 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// Converts CMSIS sysTicks to .NET ticks (100 nanoseconds) +uint64_t HAL_Time_SysTicksToTime(unsigned int sysTicks) +{ + // convert to microseconds from CMSIS SysTicks + // this is a rewrite of ChibiOS TIME_I2US(n) macro because it will overflow if doing the math using uint32_t + // need to convert from microseconds to 100 nanoseconds + return (((sysTicks * (uint64_t)1000000) + (int64_t)CH_CFG_ST_FREQUENCY - 1) / (int64_t)CH_CFG_ST_FREQUENCY) * 10; +} + +// because HAL_Time_SysTicksToTime needs to be called from C we need a proxy to allow it to be called from 'C' code +extern "C" { + + uint64_t HAL_Time_SysTicksToTime_C(unsigned int sysTicks) + { + return HAL_Time_SysTicksToTime(sysTicks); + } +} + +// implementation required for STM Cube package +// Provides a tick value in millisecond. +extern "C" { + +uint32_t HAL_GetTick(void) +{ + return TIME_I2MS(chVTGetSystemTimeX()); +} + +} + +// implementation required for STM Cube package +// This function provides minimum delay (in milliseconds). +extern "C" { + +void HAL_Delay(uint32_t delay) +{ + systime_t start = chVTGetSystemTime(); + systime_t end = start + TIME_MS2I(delay); + + do + { + // do nothing until the timeout expires + chThdYield(); + } + while(chVTIsSystemTimeWithin(start, end)); +} + +} \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoBooter/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoBooter/CMakeLists.txt new file mode 100644 index 00000000..d88eae23 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoBooter/CMakeLists.txt @@ -0,0 +1,18 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append target ChibiOS nanoBooter source files +list(APPEND TARGET_CHIBIOS_NANOBOOTER_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_App_Interface.c") +list(APPEND TARGET_CHIBIOS_NANOBOOTER_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_MonitorCommands.c") +# make var global +set(TARGET_CHIBIOS_NANOBOOTER_SOURCES ${TARGET_CHIBIOS_NANOBOOTER_SOURCES} CACHE INTERNAL "make global") + +# append include directory for debugger +list(APPEND TARGET_CHIBIOS_NANOBOOTER_INCLUDE_DIRS "${PROJECT_SOURCE_DIR}/src/CLR/Debugger") + +# append target ChibiOS nanoBooter include directory +list(APPEND TARGET_CHIBIOS_NANOBOOTER_INCLUDE_DIRS "${CMAKE_CURRENT_SOURCE_DIR}") +# make var global +set(TARGET_CHIBIOS_NANOBOOTER_INCLUDE_DIRS ${TARGET_CHIBIOS_NANOBOOTER_INCLUDE_DIRS} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoBooter/WireProtocol_App_Interface.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoBooter/WireProtocol_App_Interface.c new file mode 100644 index 00000000..d2be2eeb --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoBooter/WireProtocol_App_Interface.c @@ -0,0 +1,118 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +// Initialize to a packet sequence number impossible to encounter +static uint32_t lastPacketSequence = 0x00FEFFFF; + +// defining this array here makes is local helping reduce the image size because of compiler opmitizations +static const CommandHandlerLookup c_Lookup_Request[] = +{ + /*******************************************************************************************************************************************************************/ +#define DEFINE_CMD(cmd) { CLR_DBG_Commands_c_Monitor_##cmd, &Monitor_##cmd } + DEFINE_CMD(Ping ), + DEFINE_CMD(Reboot ), + // // + DEFINE_CMD(ReadMemory ), + DEFINE_CMD(WriteMemory), + DEFINE_CMD(CheckMemory), + DEFINE_CMD(EraseMemory), + DEFINE_CMD(QueryConfiguration), + DEFINE_CMD(UpdateConfiguration), + // // + // DEFINE_CMD(Execute ), + DEFINE_CMD(MemoryMap ), + // // + // DEFINE_CMD(CheckSignature), + // // + DEFINE_CMD(FlashSectorMap), + // DEFINE_CMD(SignatureKeyUpdate), + + DEFINE_CMD(OemInfo), + +#undef DEFINE_CMD + /*******************************************************************************************************************************************************************/ +}; + +//////////////////////////////////////////////////// + +// defining this array here makes is local helping reduce the image size because of compiler opmitizations +static const CommandHandlerLookup c_Lookup_Reply[] = +{ + /*******************************************************************************************************************************************************************/ +#define DEFINE_CMD(cmd) { CLR_DBG_Commands_c_Monitor_##cmd, &Monitor_##cmd } + DEFINE_CMD(Ping), +#undef DEFINE_CMD + /*******************************************************************************************************************************************************************/ +}; + +int WP_App_ProcessHeader(WP_Message* message) +{ + // check for reception buffer overflow + if(message->m_header.m_size > sizeof(receptionBuffer)) + { + return false; + } + + message->m_payload = receptionBuffer; + return true; +} + +int WP_App_ProcessPayload(WP_Message* message) +{ + // Prevent processing duplicate packets + if(message->m_header.m_seq == lastPacketSequence) + { + return false; // Do not even respond to a repeat packet + } + + // save this packet sequence number + lastPacketSequence = message->m_header.m_seq; + + if(message->m_header.m_flags & WP_Flags_c_NACK) + { + // + // Bad packet... + // + return true; + } + + size_t num; + const CommandHandlerLookup* cmd; + + if(message->m_header.m_flags & WP_Flags_c_Reply) + { + num = ARRAYSIZE(c_Lookup_Reply); + cmd = c_Lookup_Reply; + } + else + { + num = ARRAYSIZE(c_Lookup_Request); + cmd = c_Lookup_Request; + } + + while(num--) + { + if(cmd->command == message->m_header.m_cmd) + { + // execute command handler and save the result + int commandHandlerExecuteResult = ((int(*)(WP_Message*))cmd->handler)(message); + + WP_ReplyToCommand(message, commandHandlerExecuteResult, false, NULL, 0); + return true; + } + + cmd++; + } + + WP_ReplyToCommand(message, false, false, NULL, 0); + + return true; +} + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoBooter/WireProtocol_MonitorCommands.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoBooter/WireProtocol_MonitorCommands.c new file mode 100644 index 00000000..8c9864b3 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoBooter/WireProtocol_MonitorCommands.c @@ -0,0 +1,399 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +////////////////////////////////////////////////////////////////////// +// helper functions + +int NanoBooter_GetReleaseInfo(ReleaseInfo* releaseInfo) +{ + releaseInfo->version.usMajor = VERSION_MAJOR; + releaseInfo->version.usMinor = VERSION_MINOR; + releaseInfo->version.usBuild = VERSION_BUILD; + releaseInfo->version.usRevision = VERSION_REVISION; + + memcpy(&releaseInfo->InfoString, OEMSYSTEMINFOSTRING, ARRAYSIZE(OEMSYSTEMINFOSTRING)); + memcpy(&releaseInfo->TargetName, TARGETNAMESTRING, ARRAYSIZE(TARGETNAMESTRING)); + memcpy(&releaseInfo->PlatformName, PLATFORMNAMESTRING, ARRAYSIZE(PLATFORMNAMESTRING)); + + return true; +} + +static int AccessMemory(uint32_t location, uint32_t lengthInBytes, uint8_t* buffer, int32_t mode, uint32_t* errorCode) +{ + // reset error code + *errorCode = AccessMemoryErrorCode_NoError; + + switch(mode) + { + case AccessMemory_Write: + // use FLASH driver to perform write operation + // this requires that HAL_USE_STM32_FLASH is set to TRUE on halconf_nf.h + return stm32FlashWrite(location, lengthInBytes, buffer); + + case AccessMemory_Erase: + // erase using FLASH driver + // this requires that HAL_USE_STM32_FLASH is set to TRUE on halconf_nf.h + return stm32FlashErase(location); + + case AccessMemory_Check: + // use FLASH driver to check is FLASH segment is erased + // this requires that HAL_USE_STM32_FLASH is set to TRUE on halconf_nf.h + return stm32FlashIsErased(location, lengthInBytes); + + case AccessMemory_Read: + // use FLASH driver to perform read operation + // this requires that HAL_USE_STM32_FLASH is set to TRUE on halconf_nf.h + stm32FlashReadBytes(location, lengthInBytes, buffer); + return true; + + default: + // default return is FALSE + return false; + } +} + +//////////////////////////////////////////////////// + +int Monitor_Ping(WP_Message* message) +{ + if((message->m_header.m_flags & WP_Flags_c_Reply) == 0) + { + Monitor_Ping_Reply cmdReply; + cmdReply.m_source = Monitor_Ping_c_Ping_Source_NanoBooter; + cmdReply.m_dbg_flags = 0; + + #if defined(WP_IMPLEMENTS_CRC32) + cmdReply.m_dbg_flags |= Monitor_Ping_c_Ping_WPFlag_SupportsCRC32; + #endif + + // Wire Protocol packet size + #if (WP_PACKET_SIZE == 512) + cmdReply.m_dbg_flags |= Monitor_Ping_c_PacketSize_0512; + #elif (WP_PACKET_SIZE == 256) + cmdReply.m_dbg_flags |= Monitor_Ping_c_PacketSize_0256; + #elif (WP_PACKET_SIZE == 128) + cmdReply.m_dbg_flags |= Monitor_Ping_c_PacketSize_0128; + #elif (WP_PACKET_SIZE == 1024) + cmdReply.m_dbg_flags |= Monitor_Ping_c_PacketSize_1024; + #endif + + + WP_ReplyToCommand(message, true, false, &cmdReply, sizeof(cmdReply)); + } + + return true; +} + +int Monitor_OemInfo(WP_Message* message) +{ + if((message->m_header.m_flags & WP_Flags_c_Reply) == 0) + { + Monitor_OemInfo_Reply cmdReply; + + bool fOK = NanoBooter_GetReleaseInfo(&cmdReply.m_releaseInfo) == true; + + WP_ReplyToCommand(message, fOK, false, &cmdReply, sizeof(cmdReply)); + } + + return true; +} + +int Monitor_ReadMemory(WP_Message* message) +{ + CLR_DBG_Commands_Monitor_ReadMemory* cmd = (CLR_DBG_Commands_Monitor_ReadMemory*)message->m_payload; + + unsigned char buf[ 1024 ]; + unsigned int len = cmd->length; if(len > sizeof(buf)) len = sizeof(buf); + uint32_t errorCode; + + AccessMemory(cmd->address, len, buf, AccessMemory_Read, &errorCode ); + + WP_ReplyToCommand(message, true, false, buf, len); + + return true; +} + +int Monitor_WriteMemory(WP_Message* message) +{ + CLR_DBG_Commands_Monitor_WriteMemory* cmd = (CLR_DBG_Commands_Monitor_WriteMemory*)message->m_payload; + CLR_DBG_Commands_Monitor_WriteMemory_Reply cmdReply; + + + // TODO: not sure if we really need this + // if(!m_signedDataState.VerifyContiguousData(cmd->m_address, cmd->m_length)) + // { + // m_signedDataState.EraseMemoryAndReset(); + + // return false; + // } + + // TODO: not sure if we really need this + // nanoBooter_OnStateChange(State_MemoryWrite, (void*)cmd->m_address); + + // assume at RAM, directly use the original address + AccessMemory(cmd->address, cmd->length, cmd->data, AccessMemory_Write, &cmdReply.ErrorCode); + + WP_ReplyToCommand(message, true, false, &cmdReply, sizeof(cmdReply)); + + return true; +} + +int Monitor_Reboot(WP_Message* message) +{ + Monitor_Reboot_Command* cmd = (Monitor_Reboot_Command*)message->m_payload; + + WP_ReplyToCommand(message, true, false, NULL, 0); + + if(cmd != NULL) + { + // only reset if we are not trying to get into the bootloader + if((cmd->m_flags & Monitor_Reboot_c_EnterBootloader) != Monitor_Reboot_c_EnterBootloader) + { + // RESET CPU + // because ChibiOS relies on CMSIS it's recommended to make use of the CMSIS API + NVIC_SystemReset(); + } + } + + return true; +} + +int Monitor_EraseMemory(WP_Message* message) +{ + CLR_DBG_Commands_Monitor_EraseMemory* cmd = (CLR_DBG_Commands_Monitor_EraseMemory*)message->m_payload; + CLR_DBG_Commands_Monitor_EraseMemory_Reply cmdReply; + + // TODO: not sure if we really need this + // nanoBooter_OnStateChange( State_MemoryErase, (void*)cmd->m_address ); + + AccessMemory(cmd->address, cmd->length, NULL, AccessMemory_Erase, &cmdReply.ErrorCode); + + WP_ReplyToCommand(message, true, false, &cmdReply, sizeof(cmdReply)); + + return true; +} + +int Monitor_QueryConfiguration(WP_Message* message) +{ + bool success = false; + + // include handling of configuration block only if feature is available + #if (HAS_CONFIG_BLOCK == TRUE) + + Monitor_QueryConfiguration_Command *cmd = (Monitor_QueryConfiguration_Command*)message->m_payload; + int size = 0; + + HAL_Configuration_NetworkInterface configNetworkInterface; + HAL_Configuration_Wireless80211 configWireless80211NetworkInterface; + + switch((DeviceConfigurationOption)cmd->Configuration) + { + case DeviceConfigurationOption_Network: + + if(ConfigurationManager_GetConfigurationBlock((void *)&configNetworkInterface, (DeviceConfigurationOption)cmd->Configuration, cmd->BlockIndex) == true) + { + size = sizeof(HAL_Configuration_NetworkInterface); + success = true; + + WP_ReplyToCommand( message, success, false, (uint8_t*)&configNetworkInterface, size ); + } + break; + + case DeviceConfigurationOption_Wireless80211Network: + + if(ConfigurationManager_GetConfigurationBlock((void *)&configWireless80211NetworkInterface, (DeviceConfigurationOption)cmd->Configuration, cmd->BlockIndex) == true) + { + size = sizeof(HAL_Configuration_Wireless80211); + success = true; + + WP_ReplyToCommand( message, success, false, (uint8_t*)&configWireless80211NetworkInterface, size ); + } + break; + + case DeviceConfigurationOption_WirelessNetworkAP: + // TODO missing implementation for now + break; + + default: + break; + } + + if(!success) + { + WP_ReplyToCommand( message, success, false, NULL, size ); + } + + #else + + (void)message; + + #endif // (HAS_CONFIG_BLOCK == TRUE) + + return success; +} + +int Monitor_UpdateConfiguration(WP_Message* message) +{ + bool success = false; + + // include handling of configuration block only if feature is available + #if (HAS_CONFIG_BLOCK == TRUE) + + Monitor_UpdateConfiguration_Command* cmd = (Monitor_UpdateConfiguration_Command*)message->m_payload; + Monitor_UpdateConfiguration_Reply cmdReply; + + switch((DeviceConfigurationOption)cmd->Configuration) + { + case DeviceConfigurationOption_Network: + case DeviceConfigurationOption_Wireless80211Network: + case DeviceConfigurationOption_X509CaRootBundle: + case DeviceConfigurationOption_All: + if(ConfigurationManager_StoreConfigurationBlock(cmd->Data, (DeviceConfigurationOption)cmd->Configuration, cmd->BlockIndex, cmd->Length, cmd->Offset) == true) + { + cmdReply.ErrorCode = 0; + success = true; + } + else + { + cmdReply.ErrorCode = 100; + } + break; + + default: + cmdReply.ErrorCode = 10; + } + + WP_ReplyToCommand(message, success, false, &cmdReply, sizeof(cmdReply)); + + #else + + (void)message; + + #endif // (HAS_CONFIG_BLOCK == TRUE) + + return success; +} + +int Monitor_CheckMemory(WP_Message* message) +{ + bool ret = false; + + CLR_DBG_Commands_Monitor_CheckMemory* cmd = (CLR_DBG_Commands_Monitor_CheckMemory*)message->m_payload; + CLR_DBG_Commands_Monitor_CheckMemory_Reply cmdReply; + uint32_t errorCode; + + ret = AccessMemory(cmd->address, cmd->length, (uint8_t*)&cmdReply.crc, AccessMemory_Check, &errorCode); + + WP_ReplyToCommand(message, ret, false, &cmdReply, sizeof(cmdReply)); + + return ret; +} + +int Monitor_MemoryMap(WP_Message* message) +{ + MemoryMap_Range map[2]; + + // if(m_signedDataState.CheckDirty()) + // { + // m_signedDataState.EraseMemoryAndReset(); + + // return false; + // } + + map[0].m_address = HalSystemConfig.RAM1.Base; + map[0].m_length = HalSystemConfig.RAM1.Size; + map[0].m_flags = Monitor_MemoryMap_c_RAM; + + map[1].m_address = HalSystemConfig.FLASH1.Base; + map[1].m_length = HalSystemConfig.FLASH1.Size; + map[1].m_flags = Monitor_MemoryMap_c_FLASH; + + WP_ReplyToCommand(message, true, false, map, sizeof(map)); + + return true; +} + +int Monitor_FlashSectorMap(WP_Message* message) +{ + + if((message->m_header.m_flags & WP_Flags_c_Reply) == 0) + { + struct Flash_BlockRegionInfo + { + unsigned int StartAddress; + unsigned int NumBlocks; + unsigned int BytesPerBlock; + unsigned int Usage; + + } *pData = NULL; + + unsigned int rangeCount = 0; + unsigned int rangeIndex = 0; + + for(int cnt = 0; cnt < 2; cnt++) + { + BlockStorageDevice* device = BlockStorageList_GetFirstDevice(); + + if(device == NULL) + { + WP_ReplyToCommand(message, true, false, NULL, 0); + return false; + } + + if(cnt == 1) + { + pData = (struct Flash_BlockRegionInfo*)platform_malloc(rangeCount * sizeof(struct Flash_BlockRegionInfo)); + + if(pData == NULL) + { + WP_ReplyToCommand(message, true, false, NULL, 0); + return false; + } + } + + DeviceBlockInfo* deviceInfo = BlockStorageDevice_GetDeviceInfo(device); + + for(unsigned int i = 0; i < deviceInfo->NumRegions; i++) + { + const BlockRegionInfo* pRegion = &deviceInfo->Regions[ i ]; + + for(unsigned int j = 0; j < pRegion->NumBlockRanges; j++) + { + + if(cnt == 0) + { + rangeCount++; + } + else + { + pData[ rangeIndex ].StartAddress = BlockRegionInfo_BlockAddress(pRegion, pRegion->BlockRanges[ j ].StartBlock); + pData[ rangeIndex ].NumBlocks = BlockRange_GetBlockCount(pRegion->BlockRanges[j]); + pData[ rangeIndex ].BytesPerBlock = pRegion->BytesPerBlock; + pData[ rangeIndex ].Usage = pRegion->BlockRanges[ j ].RangeType & BlockRange_USAGE_MASK; + rangeIndex++; + } + } + } + } + + + WP_ReplyToCommand(message, true, false, (void*)pData, rangeCount * sizeof(struct Flash_BlockRegionInfo)); + + platform_free(pData); + } + + return true; +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/CLR_RT_InteropAssembliesTable.cpp.in b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/CLR_RT_InteropAssembliesTable.cpp.in new file mode 100644 index 00000000..78ae4af5 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/CLR_RT_InteropAssembliesTable.cpp.in @@ -0,0 +1,23 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#include + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_mscorlib; +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Runtime_Native; +@CLR_RT_NativeAssemblyDataDeclarations@ + +const CLR_RT_NativeAssemblyData *g_CLR_InteropAssembliesNativeData[] = +{ + &g_CLR_AssemblyNative_mscorlib, + &g_CLR_AssemblyNative_nanoFramework_Runtime_Native, + @CLR_RT_NativeAssemblyDataTableEntries@ + NULL +}; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/CLR_Startup_Thread.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/CLR_Startup_Thread.c new file mode 100644 index 00000000..9e0b66f1 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/CLR_Startup_Thread.c @@ -0,0 +1,89 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +void AssertBlockStorage() +{ + // if the target Device_BlockStorageConfig (and collections) and the linker file have an address mismatch + // the assertions below will cause an exception + // these checks are only included when RTM build option isn't specified + BlockStorageStream stream; + memset(&stream, 0, sizeof(BlockStorageStream)); + + // DEPLOYMENT block + // this one lives in a single block so we are OK with checking start, end and length + BlockStorageStream_Initialize(&stream, BlockUsage_DEPLOYMENT); + ASSERT(stream.BaseAddress == (uint32_t)&__deployment_start__); + //ASSERT(stream.Length == ((uint32_t)&__deployment_end__) - ((uint32_t)&__deployment_start__)); + + // CODE block (CLR) + // this one can be spread accross several blocks so we can only check the start address + memset(&stream, 0, sizeof(BlockStorageStream)); + BlockStorageStream_Initialize(&stream, BlockUsage_CODE); + ASSERT(stream.BaseAddress == (uint32_t)&__nanoImage_start__); + //ASSERT(stream.Length == ((uint32_t)&__nanoImage_end__) - ((uint32_t)&__nanoImage_start__)); + + // CONFIG block + // this one lives in a single block so we are OK with checking start, end and length + memset(&stream, 0, sizeof(BlockStorageStream)); + BlockStorageStream_Initialize(&stream, BlockUsage_CONFIG); + ASSERT(stream.BaseAddress == (uint32_t)&__nanoConfig_start__); + ASSERT(stream.Length == ((uint32_t)&__nanoConfig_end__) - ((uint32_t)&__nanoConfig_start__)); +} + +__attribute__((noreturn)) +void CLRStartupThread(void const * argument) +{ + CLR_SETTINGS* clrSettings = (CLR_SETTINGS*)argument; + + #if (HAL_USE_STM32_CRC == TRUE) + // startup crc + crcStart(NULL); + #endif + + #if (HAL_USE_STM32_ONEWIRE == TRUE) + // startup 1-Wire driver + oneWireStart(); + #endif + + // initialize nanoHAL + nanoHAL_Initialize_C(); + + /////////////////////////////////////////// + // sanity check of block storage addresses + #if !defined(BUILD_RTM) + AssertBlockStorage(); + #endif + /////////////////////////////////////////// + + #if LWIP_NETCONN_SEM_PER_THREAD + // need to create a semaphore for lwIP + semaphore_t *semaphore = chPoolAlloc(NULL); + chSemObjectInit(semaphore, (cnt_t)1); + chSemWaitTimeout(semaphore, 0); + thread_t* currentThread = chThdGetSelfX(); + currentThread->localStorage = semaphore; + #endif + + ClrStartup(*clrSettings); + + // loop until thread receives a request to terminate + while (1) + { + osDelay(500); + } + + // this function never returns +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/CMakeLists.txt new file mode 100644 index 00000000..824c46e2 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/CMakeLists.txt @@ -0,0 +1,79 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +include(NF_NativeAssemblies) + +# add header file with common target definitions +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_platform.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/target_platform.h" @ONLY) + +# append nanoHAL +list(APPEND TARGET_CHIBIOS_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL.cpp") + +# append target ChibiOS nanoCLR source files +list(APPEND TARGET_CHIBIOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_App_Interface.c) +list(APPEND TARGET_CHIBIOS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_MonitorCommands.c) +list(APPEND TARGET_CHIBIOS_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/CLR_Startup_Thread.c") +list(APPEND TARGET_CHIBIOS_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetPAL.c") + +# append target HAL source files +list(APPEND TARGET_CHIBIOS_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Power.c") +list(APPEND TARGET_CHIBIOS_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Time.cpp") + +# append watchdog only if option is ON +if(HAL_USE_WDG_OPTION) + list(APPEND TARGET_CHIBIOS_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Watchdog.c") +endif() + +# append target PAL source files +list(APPEND TARGET_CHIBIOS_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetPAL_Events.cpp") +list(APPEND TARGET_CHIBIOS_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetPAL_Time.cpp") + +# append other CLR core files +list(APPEND TARGET_CHIBIOS_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Memory.cpp") + +# append nanoCRT +list(APPEND TARGET_CHIBIOS_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoCRT.cpp") + +# append files from Runtime.Native +list(APPEND TARGET_CHIBIOS_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Native_Rtc.cpp") + +# append TRNG only if option is ON +if(USE_RNG) + + # append random implementation for all series, except F0 + if( ${TARGET_SERIES} STREQUAL "STM32L0xx" OR + ${TARGET_SERIES} STREQUAL "STM32F4xx" OR + ${TARGET_SERIES} STREQUAL "STM32F7xx" OR + ${TARGET_SERIES} STREQUAL "STM32H7xx") + + list(APPEND TARGET_CHIBIOS_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetRandom.cpp") + + else() + # this series doesn't feature hardware TRNG, report + message(ERROR "This CPU doesn't have a Random Number Generation. Please change USE_RNG option to OFF.") + endif() + +endif() + +# add native assemblies +ParseNativeAssemblies() + +# make var global +set(TARGET_CHIBIOS_NANOCLR_SOURCES ${TARGET_CHIBIOS_NANOCLR_SOURCES} CACHE INTERNAL "make global") + +# append target ChibiOS nanoCLR include directory +list(APPEND TARGET_CHIBIOS_NANOCLR_INCLUDE_DIRS ${CMAKE_CURRENT_SOURCE_DIR}) +list(APPEND TARGET_CHIBIOS_NANOCLR_INCLUDE_DIRS ${CMAKE_CURRENT_BINARY_DIR}) +list(APPEND TARGET_CHIBIOS_NANOCLR_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Core) + +# append PAL include directory +list(APPEND TARGET_CHIBIOS_NANOCLR_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/PAL/Include) + +# append Runtime.Native include directory +list(APPEND TARGET_CHIBIOS_NANOCLR_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Runtime.Native) + +# make var global +set(TARGET_CHIBIOS_NANOCLR_INCLUDE_DIRS ${TARGET_CHIBIOS_NANOCLR_INCLUDE_DIRS} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Memory.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Memory.cpp new file mode 100644 index 00000000..312e8ce4 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Memory.cpp @@ -0,0 +1,23 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include + +extern "C" { + void HeapLocation_C(unsigned char** baseAddress, unsigned int* sizeInBytes) + { + *baseAddress = (unsigned char*)(unsigned char*) &HeapBegin; + *sizeInBytes = (unsigned int)((size_t)&HeapEnd - (size_t)&HeapBegin); + } +} + +void HeapLocation(unsigned char*& baseAddress, unsigned int& sizeInBytes) +{ + NATIVE_PROFILE_PAL_HEAP(); + + baseAddress = (unsigned char*) &HeapBegin; + sizeInBytes = (unsigned int)((size_t)&HeapEnd - (size_t)&HeapBegin); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/System.Devices.Dac/sys_dev_dac_native_System_Devices_Dac_DacChannel.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/System.Devices.Dac/sys_dev_dac_native_System_Devices_Dac_DacChannel.cpp new file mode 100644 index 00000000..ccbe64cb --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/System.Devices.Dac/sys_dev_dac_native_System_Devices_Dac_DacChannel.cpp @@ -0,0 +1,157 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "sys_dev_dac_native_target.h" + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-function" +#endif + +// not used, just left here if needed for debugging purposes +static void dacerrorcallback(DACDriver *dacp, dacerror_t err) +{ + (void)dacp; + (void)err; +} + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + +HRESULT Library_sys_dev_dac_native_System_Devices_Dac_DacChannel::NativeWriteValue___VOID__U2( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* dacController = NULL; + + // we are filling this below with the appropriate DAC port pin config and DAC driver + NF_PAL_DAC_PORT_PIN_CHANNEL dacDefinition; + NF_PAL_DAC* palDac; + + dacsample_t sample; + int channelNumber; + int controllerId; + + // assign the value to the buffer + sample = (dacsample_t)stack.Arg1().NumericByRef().u2; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Get channel from _channelNumber field + channelNumber = pThis[FIELD___channelNumber].NumericByRef().s4; + + // need to get the controllerId for the DAC controller of this channel + // get pointer to DacController field + dacController = pThis[FIELD___dacController].Dereference(); + + // get pointer to _controllerId field in DacController + controllerId = dacController[Library_sys_dev_dac_native_System_Devices_Dac_DacController::FIELD___controllerId].NumericByRef().s4; + + // only one DAC controller for now, but check it anyways + if(controllerId == 1) + { + dacDefinition = DacPortPinConfig[channelNumber]; + + // we should remove form the build the DAC controller & channel combinations that aren't implemented + // plus we have to use the default to catch invalid DAC Ids + switch(ENCODED_DAC_REF(dacDefinition.dacIndex, dacDefinition.dacChannel)) + { + #if STM32_DAC_USE_DAC1_CH1 + case 11: + palDac = &Dac1_1_PAL; + break; + #endif + + #if STM32_DAC_USE_DAC1_CH2 + case 12: + palDac = &Dac1_2_PAL; + break; + #endif + + #if STM32_DAC_USE_DAC2_CH1 + case 21: + palDac = &Dac2_1_PAL; + break; + #endif + + #if STM32_DAC_USE_DAC2_CH2 + case 22: + palDac = &Dac2_2_PAL; + break; + #endif + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // perform the conversion + dacPutChannelX(palDac->Driver, palDac->Channel, sample); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_dac_native_System_Devices_Dac_DacChannel::NativeDispose___VOID__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NF_PAL_DAC_PORT_PIN_CHANNEL dacDefinition; + int channelNumber; + bool disposeController = false; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get disposeController + disposeController = (bool)stack.Arg0().NumericByRef().u1; + + // Get channel from _channelNumber field + channelNumber = pThis[FIELD___channelNumber].NumericByRef().s4; + + if(disposeController) + { + dacDefinition = DacPortPinConfig[channelNumber]; + + switch(ENCODED_DAC_REF(dacDefinition.dacIndex, dacDefinition.dacChannel)) + { + #if STM32_DAC_USE_DAC1_CH1 + case 11: + dacStop(&DACD1); + break; + #endif + + #if STM32_DAC_USE_DAC1_CH2 + case 12: + dacStop(&DACD2); + break; + #endif + + #if STM32_DAC_USE_DAC2_CH1 + case 21: + dacStop(&DACD3); + break; + #endif + + #if STM32_DAC_USE_DAC2_CH2 + case 22: + dacStop(&DACD4); + break; + #endif + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + } + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/System.Devices.Dac/sys_dev_dac_native_System_Devices_Dac_DacController.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/System.Devices.Dac/sys_dev_dac_native_System_Devices_Dac_DacController.cpp new file mode 100644 index 00000000..6206f386 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/System.Devices.Dac/sys_dev_dac_native_System_Devices_Dac_DacController.cpp @@ -0,0 +1,188 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "sys_dev_dac_native_target.h" + +//////////////////////////////////////////////////////////// +// DAC PAL strucs delcared in sys_dev_dac_native_target.h // +//////////////////////////////////////////////////////////// +#if STM32_DAC_USE_DAC1_CH1 +NF_PAL_DAC Dac1_1_PAL; +#endif +#if STM32_DAC_USE_DAC1_CH2 +NF_PAL_DAC Dac1_2_PAL; +#endif +#if STM32_DAC_USE_DAC2_CH1 +NF_PAL_DAC Dac2_1_PAL; +#endif +#if STM32_DAC_USE_DAC2_CH2 +NF_PAL_DAC Dac2_2_PAL; +#endif + +HRESULT Library_sys_dev_dac_native_System_Devices_Dac_DacController::NativeOpenChannel___VOID__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + // we are filling this below with the appropriate ADC port pin config and ADC driver + NF_PAL_DAC_PORT_PIN_CHANNEL dacDefinition; + NF_PAL_DAC* palDac; + int controllerId; + + // Get channel from argument + int channel = stack.Arg1().NumericByRef().s4; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get controller ID + controllerId = pThis[FIELD___controllerId].NumericByRef().s4; + + // only one DAC controller for now, but check it anyways + if(controllerId == 1) + { + dacDefinition = DacPortPinConfig[channel]; + + switch(ENCODED_DAC_REF(dacDefinition.dacIndex, dacDefinition.dacChannel)) + { + #if STM32_DAC_USE_DAC1_CH1 + case 11: + Dac1_1_PAL.Driver = &DACD1; + palDac = &Dac1_1_PAL; + // unlike STM documentation, ChibiOS uses a 0 index for DAC channels + palDac->Channel = 1 - 1; + break; + #endif + + #if STM32_DAC_USE_DAC1_CH2 + case 12: + Dac1_2_PAL.Driver = &DACD2; + palDac = &Dac1_2_PAL; + // unlike STM documentation, ChibiOS uses a 0 index for DAC channels + palDac->Channel = 2 - 1; + break; + #endif + + #if STM32_DAC_USE_DAC2_CH1 + case 21: + Dac2_1_PAL.Driver = &DACD3; + palDac = &Dac2_1_PAL; + // unlike STM documentation, ChibiOS uses a 0 index for DAC channels + palDac->Channel = 1 - 1; + break; + #endif + + #if STM32_DAC_USE_DAC2_CH2 + case 22: + Dac2_2_PAL.Driver = &DACD4; + palDac = &Dac2_2_PAL; + // unlike STM documentation, ChibiOS uses a 0 index for DAC channels + palDac->Channel = 2 - 1; + break; + #endif + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // start DAC driver if it's not already started + if(palDac->Driver->state < DAC_READY) + { + if(dacDefinition.portId != NULL) + { + palSetPadMode(dacDefinition.portId, dacDefinition.pin, PAL_MODE_INPUT_ANALOG); + } + + // set DAC config: 12 bits data mode, others registers to defaults + memset(&palDac->Config, 0, sizeof(DACConfig)); + + palDac->Config.init = 0; + palDac->Config.datamode = DAC_DHRM_12BIT_RIGHT; + palDac->Config.cr = 0; + + // start DAC + dacStart(palDac->Driver, &palDac->Config); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_dac_native_System_Devices_Dac_DacController::NativeGetChannelCount___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + int channelCount; + int controllerId; + + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + controllerId = pThis[ FIELD___controllerId ].NumericByRefConst().s4; + + switch(controllerId) + { + case 1: + channelCount = DacChannelCount; + break; + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // Return value to the managed application + stack.SetResult_I4(channelCount); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_dac_native_System_Devices_Dac_DacController::NativeGetResolutionInBits___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // Fixed at 12 bit + stack.SetResult_I4(12); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_sys_dev_dac_native_System_Devices_Dac_DacController::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + int controllerId; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get pointer to _controllerId field in DacController + controllerId = pThis[FIELD___controllerId].NumericByRef().s4; + + // all required initialization for DAC is already handled in ChibiOS driver + + switch(controllerId) + { + case 1: + break; + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_dac_native_System_Devices_Dac_DacController::GetDeviceSelector___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // because the caller is expecting a result to be returned + // we need set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + stack.SetResult_String("DAC1"); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/System.Devices.Dac/sys_dev_dac_native_target.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/System.Devices.Dac/sys_dev_dac_native_target.h new file mode 100644 index 00000000..a237eadb --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/System.Devices.Dac/sys_dev_dac_native_target.h @@ -0,0 +1,64 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#ifndef _SYS_DEV_DAC_NATIVE_TARGET_H_ +#define _SYS_DEV_DAC_NATIVE_TARGET_H_ + +#include +#include + +struct NF_PAL_DAC_PORT_PIN_CHANNEL +{ + // Index of DAC converter + // on most STM32 devices can be converter 1 or 2 + uint8_t dacIndex; + + // DAC channel + // on most STM32 devices can be channel 1 or 2 + uint8_t dacChannel; + + // GPIO port ID + stm32_gpio_t* portId; + + // GPIO pin of the DAC channel + uint8_t pin; +}; + +// struct representing the DAC controller +struct NF_PAL_DAC +{ + DACDriver* Driver; + DACConfig Config; + uint8_t Channel; +}; + +//////////////////////////////////////////// +// declaration of the the DAC PAL strucs // +//////////////////////////////////////////// +#if STM32_DAC_USE_DAC1_CH1 +extern NF_PAL_DAC Dac1_1_PAL; +#endif +#if STM32_DAC_USE_DAC1_CH2 +extern NF_PAL_DAC Dac1_2_PAL; +#endif +#if STM32_DAC_USE_DAC2_CH1 +extern NF_PAL_DAC Dac2_1_PAL; +#endif +#if STM32_DAC_USE_DAC2_CH2 +extern NF_PAL_DAC Dac2_2_PAL; +#endif + + +// there is a driver for each pair DAC converter + channel +// let's code the options with DAC controller on the tens place and the channel on the ones place +// like this: channel 2 of DAC controller 1 being => (1 * 10) + 12 = 12 +#define ENCODED_DAC_REF( dac, channel) (dac * 10 + channel) + + +extern const NF_PAL_DAC_PORT_PIN_CHANNEL DacPortPinConfig[]; +extern const int DacChannelCount; + +#endif //_SYS_DEV_DAC_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcChannel.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcChannel.cpp new file mode 100644 index 00000000..9d7d04fa --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcChannel.cpp @@ -0,0 +1,139 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_adc_native_target.h" + +// this has to be an array because ChibiOS ADC API expects that +static adcsample_t sampleBuffer[1 * 1]; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-function" +#endif + +// not used, just left here if needed for debugging purposes +static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) +{ + (void)adcp; + (void)err; +} + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcChannel::NativeReadValue___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Get channel from _channelNumber field + int channelNumber = pThis[FIELD___channelNumber].NumericByRef().s4; + + // need to get the controllerId for the ADC controller of this channel + // get pointer to AdcController field + CLR_RT_HeapBlock* adcController = pThis[FIELD___adcController].Dereference(); + + // get pointer to _controllerId field in AdcController + int controllerId = adcController[Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::FIELD___controllerId].NumericByRef().s4; + + // we are filling this below with the appropriate ADC port pin config and ADC driver + NF_PAL_ADC_PORT_PIN_CHANNEL adcDefinition; + ADCDriver* adcDriver = NULL; + + // only one ADC controller for now, but check it anyways + if(controllerId == 1) + { + adcDefinition = AdcPortPinConfig[channelNumber]; + + // we should remove form the build the ADC options that aren't implemented + // plus we have to use the default to catch invalid ADC Ids + switch(adcDefinition.adcIndex) + { + #if STM32_ADC_USE_ADC1 + case 1: + adcDriver = &ADCD1; + break; + #endif + + #if STM32_ADC_USE_ADC2 + case 2: + adcDriver = &ADCD2; + break; + #endif + + #if STM32_ADC_USE_ADC3 + case 3: + adcDriver = &ADCD3; + break; + #endif + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + bool enableVref = (adcDefinition.adcChannel == ADC_CHANNEL_SENSOR) \ + | (adcDefinition.adcChannel == ADC_CHANNEL_VREFINT) \ + | (adcDefinition.adcChannel == ADC_CHANNEL_VBAT); + + // need to enable VREF? + if(enableVref) + { + adcSTM32EnableTSVREFE(); + + osDelay(10); + } + + // need to setup the conversion group parameters + ADCConversionGroup adcgrpcfg1 = { + FALSE, + 1, + NULL, + NULL, // replace with adcerrorcallback if required for debug + 0, /* CR1 */ + ADC_CR2_SWSTART, /* CR2 */ + ADC_SMPR1_SMP_AN11(ADC_SAMPLE_3), /* SMPR1 */ + 0, /* SMPR2 */ + 0, /* HTR */ + 0, /* LTR */ + 0, /* SQR1 */ + 0, /* SQR2 */ + ADC_SQR3_SQ1_N(adcDefinition.adcChannel) + }; + + // perform the conversion + adcConvert(adcDriver, &adcgrpcfg1, sampleBuffer, 1); + + // need to turn off VREF? + if(enableVref) + { + adcSTM32DisableTSVREFE(); + } + + // set the return result with the conversion value from the array + stack.SetResult_I4(sampleBuffer[0]); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcChannel::NativeDisposeChannel___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + + // left empty on purpose, nothing to do here + + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcController.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcController.cpp new file mode 100644 index 00000000..7b9671cc --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcController.cpp @@ -0,0 +1,177 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_adc_native_target.h" + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeOpenChannel___VOID__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Get channel from argument + int channel = stack.Arg1().NumericByRef().s4; + + // get controller ID + int controllerId = pThis[FIELD___controllerId].NumericByRef().s4; + + // we are filling this below with the appropriate ADC port pin config and ADC driver + NF_PAL_ADC_PORT_PIN_CHANNEL adcDefinition; + ADCDriver* adcDriver = NULL; + + // only one ADC controller for now, but check it anyways + if(controllerId == 1) + { + adcDefinition = AdcPortPinConfig[channel]; + + // we should remove form the build the ADC options that aren't implemented + // plus we have to use the default to catch invalid ADC Ids + switch(adcDefinition.adcIndex) + { + #if STM32_ADC_USE_ADC1 + case 1: + adcDriver = &ADCD1; + break; + #endif + + #if STM32_ADC_USE_ADC2 + case 2: + adcDriver = &ADCD2; + break; + #endif + + #if STM32_ADC_USE_ADC3 + case 3: + adcDriver = &ADCD3; + break; + #endif + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + if(adcDefinition.portId != NULL) + { + palSetGroupMode(adcDefinition.portId, PAL_PORT_BIT(adcDefinition.pin), 0, PAL_MODE_INPUT_ANALOG); + } + + // start ADC + adcStart(adcDriver, NULL); + + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeGetChannelCount___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + int channelCount; + + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + int controllerId = pThis[ FIELD___controllerId ].NumericByRefConst().s4; + + switch(controllerId) + { + case 1: + channelCount = AdcChannelCount; + break; + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // Return value to the managed application + stack.SetResult_I4(channelCount); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeGetMaxValue___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // Currently fixed at 12 bit so return 4095 = ((2^12) - 1) + stack.SetResult_I4(4095); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeGetMinValue___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + stack.SetResult_I4(0); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeIsChannelModeSupported___BOOLEAN__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + int mode = stack.Arg1().NumericByRef().s4; + + // Only support Single ended mode for now + stack.SetResult_Boolean( (mode == (int)AdcChannelMode::SingleEnded) ) ; + } + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeGetResolutionInBits___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // Fixed at 12 bit + stack.SetResult_I4(12); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + int controllerId; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get pointer to _controllerId field in AdcController + controllerId = pThis[FIELD___controllerId].NumericByRef().s4; + + // all required initialization for ADC is already handled in ChibiOS driver + + switch(controllerId) + { + case 1: + break; + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::GetDeviceSelector___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // because the caller is expecting a result to be returned + // we need set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + stack.SetResult_String("ADC1"); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_target.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_target.h new file mode 100644 index 00000000..e2cdb666 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_target.h @@ -0,0 +1,24 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#ifndef _WIN_DEV_ADC_NATIVE_TARGET_H_ +#define _WIN_DEV_ADC_NATIVE_TARGET_H_ + +#include +#include + +struct NF_PAL_ADC_PORT_PIN_CHANNEL +{ + uint8_t adcIndex; + stm32_gpio_t* portId; + uint8_t pin; + uint32_t adcChannel; +}; + +extern const NF_PAL_ADC_PORT_PIN_CHANNEL AdcPortPinConfig[]; +extern const int AdcChannelCount; + +#endif //_WIN_DEV_ADC_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter.cpp new file mode 100644 index 00000000..d6c6623a --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter.cpp @@ -0,0 +1,86 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_gpio_native.h" + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + { + //CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + //int16_t pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + //bool InputMode = (bool)pThis[FIELD___inputMode].NumericByRefConst().u1; + + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter::NativeRead___U8__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + { + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter::NativeStart___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + { + //CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + //int pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + + //GpioChangePolarity polarity = (GpioChangePolarity)pThis[ FIELD___Polarity ].NumericByRefConst().s4; + + + // TODO + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter::NativeStop___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + { + //CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + //int pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter::NativeDispose___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + { + //CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + //int pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + } + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioController.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioController.cpp new file mode 100644 index 00000000..5a5c948a --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioController.cpp @@ -0,0 +1,19 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#include "win_dev_gpio_native_target.h" + + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioController::get_PinCount___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // return count ot available GPIO pins + stack.SetResult_I4( 256 ); // Fixme: temporary arbitrary value + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioPin.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioPin.cpp new file mode 100644 index 00000000..270adcc8 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioPin.cpp @@ -0,0 +1,423 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#include +#include +#include + +#include +#include "win_dev_gpio_native_target.h" + +// this timer is used to handle the debounce time +static virtual_timer_t debounceTimer; + +volatile uint16_t lastPadValue; + +// this is an utility function to get a ChibiOS PAL IoLine from our "encoded" pin number +ioline_t GetIoLine(int16_t pinNumber) +{ + stm32_gpio_t* port = GPIO_PORT(pinNumber); + int16_t pad = pinNumber % 16; + + return PAL_LINE(port, pad); + +} + +static void debounceTimer_Callback( void* arg ) +{ + CLR_RT_HeapBlock* pThis = (CLR_RT_HeapBlock*)arg; + + if(pThis == NULL) + { + // no Gpio pin here, leave now + chSysUnlockFromISR(); + return; + } + + // check if object has been disposed + if(pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + // object has been disposed, leave now + chSysUnlockFromISR(); + return; + } + + // get pin number + int16_t pinNumber = pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___pinNumber ].NumericByRefConst().s4; + + // read line + uint16_t currentValue = palReadLine(GetIoLine(pinNumber)); + + // read pad + uint16_t lastPadValue = pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___lastInputValue ].NumericByRef().s4; + + if(lastPadValue == currentValue) + { + // value hasn't change for debounce interval so this is a valid change + + // flag to determine if there are any callbacks registered in managed code + bool callbacksRegistered = (pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___callbacks ].Dereference() != NULL); + + // post a managed event with the current pin value, only if there is anyone listening otherwise don't bother + if(callbacksRegistered) + { + PostManagedEvent( EVENT_GPIO, 0, pinNumber, currentValue ); + } + } +} + +static void GpioEventCallback(void *arg) +{ + CLR_RT_HeapBlock* pThis = (CLR_RT_HeapBlock*)arg; + + NATIVE_INTERRUPT_START + + chSysLockFromISR(); + + //CLR_RT_HeapBlock* pThis = channelPinMapping[channel]; + + if(pThis == NULL) + { + // no Gpio pin here, leave now + chSysUnlockFromISR(); + return; + } + + // check if object has been disposed + if(pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + // object has been disposed, leave now + chSysUnlockFromISR(); + + NATIVE_INTERRUPT_END + + return; + } + + // get pin number and take the port and pad references from that one + int16_t pinNumber = pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___pinNumber ].NumericByRefConst().s4; + + // get IoLine from pin number + ioline_t ioLine = GetIoLine(pinNumber); + + // check if there is a debounce time set + int64_t debounceTimeoutMilsec = (CLR_INT64_TEMP_CAST) pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___debounceTimeout ].NumericByRefConst().s8 / TIME_CONVERSION__TO_MILLISECONDS; + + if(debounceTimeoutMilsec > 0) + { + // debounce set, need to handle it + + if(chVTIsArmed(&debounceTimer)) + { + // there is a debounce timer already running so this change in pin value should be discarded + chSysUnlockFromISR(); + + NATIVE_INTERRUPT_END + + return; + } + + // read pad + pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___lastInputValue ].NumericByRef().s4 = palReadLine(ioLine); + + // setup timer + chVTSetI(&debounceTimer, TIME_MS2I(debounceTimeoutMilsec), debounceTimer_Callback, pThis); + } + else + { + // read pad + pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___lastInputValue ].NumericByRef().s4 = palReadLine(ioLine); + + // flag to determine if there are any callbacks registered in managed code + bool callbacksRegistered = (pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___callbacks ].Dereference() != NULL); + + // post a managed event with the current pin reading, only if there is anyone listening otherwise don't bother + if(callbacksRegistered) + { + PostManagedEvent( EVENT_GPIO, 0, pinNumber, palReadLine(ioLine) ); + } + } + + chSysUnlockFromISR(); + + NATIVE_INTERRUPT_END + +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::Read___WindowsDevicesGpioGpioPinValue( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // check if object has been disposed + if(pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + stack.SetResult_I4( palReadLine(GetIoLine(pThis[ FIELD___pinNumber ].NumericByRefConst().s4)) ); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::Toggle___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // check if object has been disposed + if(pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + // get IoLine from pin number + ioline_t ioLine = GetIoLine(pThis[ FIELD___pinNumber ].NumericByRefConst().s4); + + GpioPinDriveMode driveMode = (GpioPinDriveMode)pThis[ FIELD___driveMode ].NumericByRefConst().s4; + + // sanity check for drive mode set to output so we don't mess up writing to an input pin + if ((driveMode == GpioPinDriveMode_Output) || + (driveMode == GpioPinDriveMode_OutputOpenDrain) || + (driveMode == GpioPinDriveMode_OutputOpenDrainPullUp) || + (driveMode == GpioPinDriveMode_OutputOpenSource) || + (driveMode == GpioPinDriveMode_OutputOpenSourcePullDown)) + { + palToggleLine(ioLine); + + // store new state + pThis[ FIELD___lastOutputValue ].NumericByRef().s4 = (GpioPinValue)(GpioPinValue_High ^ (GpioPinValue)pThis[ FIELD___lastOutputValue ].NumericByRef().s4); + } + + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::DisposeNative___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get IoLine from pin number + ioline_t ioLine = GetIoLine(pThis[ FIELD___pinNumber ].NumericByRefConst().s4); + + // disable the EXT interrupt channel + // it's OK to do always this, no matter if it's enabled or not + palDisableLineEvent(ioLine); + + // set pin to input to save power + palSetLineMode(ioLine, PAL_MODE_INPUT); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeIsDriveModeSupported___BOOLEAN__WindowsDevicesGpioGpioPinDriveMode( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + GpioPinDriveMode driveMode = (GpioPinDriveMode)stack.Arg1().NumericByRef().s4; + + bool driveModeSupported = false; + + // check if the requested drive mode is support by ChibiOS config + if ((driveMode == GpioPinDriveMode_Input) || + (driveMode == GpioPinDriveMode_InputPullDown) || + (driveMode == GpioPinDriveMode_InputPullUp) || + (driveMode == GpioPinDriveMode_Output) || + (driveMode == GpioPinDriveMode_OutputOpenDrain)) + { + driveModeSupported = true; + } + + // Return value to the managed application + stack.SetResult_Boolean( driveModeSupported ) ; + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeSetDriveMode___VOID__WindowsDevicesGpioGpioPinDriveMode( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + if(pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + // get IoLine from pin number + ioline_t ioLine = GetIoLine(pThis[ FIELD___pinNumber ].NumericByRefConst().s4); + + // it's better cast this this to the appropriate enum + GpioPinDriveMode driveMode = (GpioPinDriveMode)stack.Arg1().NumericByRef().s4; + + // check if drive mode is input + bool driveModeIsInput = false; + + if( driveMode == GpioPinDriveMode_Input || + driveMode == GpioPinDriveMode_InputPullDown || + driveMode == GpioPinDriveMode_InputPullUp) + { + driveModeIsInput = true; + } + + // flag to signal that interrupts need to be setup + bool setupInterrupt = false; + + // flag to determine if there are any callbacks registered in managed code + bool callbacksRegistered = (pThis[ FIELD___callbacks ].Dereference() != NULL); + + switch (driveMode) + { + case GpioPinDriveMode_Input: + palSetLineMode(ioLine, PAL_MODE_INPUT); + setupInterrupt = true; + break; + + case GpioPinDriveMode_InputPullDown: + palSetLineMode(ioLine, PAL_MODE_INPUT_PULLDOWN); + setupInterrupt = true; + break; + + case GpioPinDriveMode_InputPullUp: + palSetLineMode(ioLine, PAL_MODE_INPUT_PULLUP); + setupInterrupt = true; + break; + + case GpioPinDriveMode_Output: + palSetLineMode(ioLine, PAL_MODE_OUTPUT_PUSHPULL); + break; + + case GpioPinDriveMode_OutputOpenDrain: + palSetLineMode(ioLine, PAL_MODE_OUTPUT_OPENDRAIN); + break; + + default: + // all other modes are NOT supported + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // if drive mode is output, read the pad to update the managed field _lastOutputValue + if(!driveModeIsInput) + { + pThis[ FIELD___lastOutputValue ].NumericByRef().s4 = palReadLine(ioLine); + } + + if(callbacksRegistered && setupInterrupt) + { + // there are callbacks registered and... + // the drive mode is input so need to setup the interrupt + + // save pin + //channelPinMapping[pad] = pThis; + + palEnableLineEvent(ioLine, PAL_EVENT_MODE_BOTH_EDGES); + palSetLineCallback(ioLine, GpioEventCallback, pThis); + + // protect this from GC so that the callback is where it's supposed to + CLR_RT_ProtectFromGC gc( *pThis ); + + // read pad and store current value to check on debounce callback + lastPadValue = palReadLine(ioLine); + } + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeInit___BOOLEAN__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + //int16_t pinNumber = stack.Arg1().NumericByRef().s4; + + // TODO is probably a good idea keep track of the used pins, so we can check that here + // TODO is probably a good idea to check if this pin exists + + // Return value to the managed application + stack.SetResult_Boolean(true ); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeSetDebounceTimeout___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + + // nothing to do here as the debounce timeout is grabbed from the managed object when required + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::WriteNative___VOID__WindowsDevicesGpioGpioPinValue( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // check if object has been disposed + if(pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + // get IoLine from pin number + ioline_t ioLine = GetIoLine(pThis[ FIELD___pinNumber ].NumericByRefConst().s4); + + GpioPinDriveMode driveMode = (GpioPinDriveMode)pThis[ FIELD___driveMode ].NumericByRefConst().s4; + + GpioPinValue state = (GpioPinValue)stack.Arg1().NumericByRef().s4; + + // sanity check for drive mode set to output so we don't mess up writing to an input pin + if ((driveMode == GpioPinDriveMode_Output) || + (driveMode == GpioPinDriveMode_OutputOpenDrain) || + (driveMode == GpioPinDriveMode_OutputOpenDrainPullUp) || + (driveMode == GpioPinDriveMode_OutputOpenSource) || + (driveMode == GpioPinDriveMode_OutputOpenSourcePullDown)) + { + palWriteLine(ioLine, state); + + // update the managed field _lastOutputValue + pThis[ FIELD___lastOutputValue ].NumericByRef().s4 = state; + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeSetAlternateFunction___VOID__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // check if object has been disposed + if(pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + // get IoLine from pin number + ioline_t ioLine = GetIoLine(pThis[ FIELD___pinNumber ].NumericByRefConst().s4); + + // get alternate function argument + int32_t alternateFunction = stack.Arg1().NumericByRef().s4; + + palSetLineMode(ioLine, PAL_MODE_ALTERNATE(alternateFunction)); + + } + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_target.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_target.h new file mode 100644 index 00000000..7666fe1c --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_target.h @@ -0,0 +1,13 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#ifndef _WIN_DEV_GPIO_NATIVE_TARGET_H_ +#define _WIN_DEV_GPIO_NATIVE_TARGET_H_ + +#include + +#endif //_WIN_DEV_GPIO_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2C_I2cDevice.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2C_I2cDevice.cpp new file mode 100644 index 00000000..bd2f39fa --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2C_I2cDevice.cpp @@ -0,0 +1,537 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include +#include "win_dev_i2c_native_target.h" + +typedef Library_win_dev_i2c_native_Windows_Devices_I2c_I2cConnectionSettings I2cConnectionSettings; + +///////////////////////////////////////////////////// +// I2C PAL strucs declared in win_dev_i2c_native.h // +///////////////////////////////////////////////////// +#if STM32_I2C_USE_I2C1 + NF_PAL_I2C I2C1_PAL; +#endif +#if STM32_I2C_USE_I2C2 + NF_PAL_I2C I2C2_PAL; +#endif +#if STM32_I2C_USE_I2C3 + NF_PAL_I2C I2C3_PAL; +#endif +#if STM32_I2C_USE_I2C4 + NF_PAL_I2C I2C4_PAL; +#endif + + +// ChibiOS I2C working thread +static THD_FUNCTION(I2CWorkingThread, arg) +{ + NF_PAL_I2C* palI2c = (NF_PAL_I2C*)arg; + msg_t result; + int estimatedDurationMiliseconds = palI2c->ByteTime * (palI2c->WriteSize + palI2c->ReadSize + 1); + + if (palI2c->ReadSize != 0 && palI2c->WriteSize != 0) + { + // this is a Write/Read transaction + result = i2cMasterTransmitTimeout(palI2c->Driver, palI2c->Address, palI2c->WriteBuffer, palI2c->WriteSize, palI2c->ReadBuffer, palI2c->ReadSize, TIME_MS2I(estimatedDurationMiliseconds)); + } + else + { + if (palI2c->ReadSize == 0) + { + // this is Write only transaction + + estimatedDurationMiliseconds = palI2c->ByteTime * (palI2c->WriteSize + 1); + + result = i2cMasterTransmitTimeout(palI2c->Driver, palI2c->Address, palI2c->WriteBuffer, palI2c->WriteSize, NULL, 0, TIME_MS2I(estimatedDurationMiliseconds)); + } + else + { + // this is a Read only transaction + + estimatedDurationMiliseconds = palI2c->ByteTime * (palI2c->ReadSize + 1); + + result = i2cMasterReceiveTimeout (palI2c->Driver, palI2c->Address, palI2c->ReadBuffer, palI2c->ReadSize, TIME_MS2I(estimatedDurationMiliseconds)); + } + } + + // fire event for I2C transaction complete + Events_Set(SYSTEM_EVENT_FLAG_I2C_MASTER); + + chThdExit(result); +} + +void GetI2cConfig(CLR_RT_HeapBlock* managedConfig, I2CConfig* llConfig) +{ + I2cBusSpeed busSpeed = (I2cBusSpeed)managedConfig[ I2cConnectionSettings::FIELD___busSpeed ].NumericByRef().s4; + + // set the LL I2C configuration (according to I2C driver version) + #if defined(STM32F1XX) || defined(STM32F4XX) || defined(STM32L1XX) + + llConfig->op_mode = OPMODE_I2C; + llConfig->clock_speed = busSpeed == I2cBusSpeed_StandardMode ? 100000U : 400000U; + llConfig->duty_cycle = busSpeed == I2cBusSpeed_StandardMode ? STD_DUTY_CYCLE : FAST_DUTY_CYCLE_2; + + #endif + + #if defined(STM32F7XX) || defined(STM32F3XX) || defined(STM32F0XX) || \ + defined(STM32L0XX) || defined(STM32L4XX) || \ + defined(STM32H7XX) + + // Standard mode : 100 KHz, Rise time 120 ns, Fall time 25 ns, 54MHz clock source + // Fast mode : 400 KHz, Rise time 120 ns, Fall time 25 ns, 54MHz clock source + // Timing register value calculated by STM32 CubeMx + llConfig->timingr = busSpeed == I2cBusSpeed_StandardMode ? 0x80201721 : 0x00B01B59; + llConfig->cr1 = 0; + llConfig->cr2 = 0; + + #endif + +} + +// estimate the time required to perform the I2C transaction +bool IsLongRunningOperation(uint16_t writeSize, uint16_t readSize, float byteTime, uint32_t& estimatedDurationMiliseconds) +{ + // add an extra byte to account for the address + estimatedDurationMiliseconds = byteTime * (writeSize + readSize + 1); + + if(estimatedDurationMiliseconds > CLR_RT_Thread::c_TimeQuantum_Milliseconds) + { + // total operation time will exceed thread quantum, so this is a long running operation + return true; + } + else + { + return false; + } +} + +HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + NF_PAL_I2C* palI2c = NULL; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the managed I2C connectionSettings object instance + CLR_RT_HeapBlock* pConfig = pThis[ FIELD___connectionSettings ].Dereference(); + + // get bus index + // this is coded with a multiplication, need to perform and int division to get the number + // see the comments in the I2cDevice() constructor in managed code for details + uint8_t busIndex = (uint8_t)(pThis[ FIELD___deviceId ].NumericByRef().s4 / 1000); + + // config GPIO pins used by the I2C peripheral + // init the PAL struct for this I2C bus and assign the respective driver + // all this occurs if not already done + // why do we need to check if this is already done? because several I2cDevice objects can be created associated to the same bus just using different addresses + switch (busIndex) + { + #if STM32_I2C_USE_I2C1 + case 1: + if(I2C1_PAL.Driver == NULL) + { + ConfigPins_I2C1(); + + I2C1_PAL.Driver = &I2CD1; + palI2c = &I2C1_PAL; + } + break; + #endif + #if STM32_I2C_USE_I2C2 + case 2: + if(I2C2_PAL.Driver == NULL) + { + ConfigPins_I2C2(); + + I2C2_PAL.Driver = &I2CD2; + palI2c = &I2C2_PAL; + } + break; + #endif + #if STM32_I2C_USE_I2C3 + case 3: + if(I2C3_PAL.Driver == NULL) + { + ConfigPins_I2C3(); + + I2C3_PAL.Driver = &I2CD3; + palI2c = &I2C3_PAL; + } + break; + #endif + #if STM32_I2C_USE_I2C4 + case 4: + if(I2C4_PAL.Driver == NULL) + { + ConfigPins_I2C4(); + + I2C4_PAL.Driver = &I2CD4; + palI2c = &I2C4_PAL; + } + break; + #endif + + default: + // this I2C bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // Get a general low-level I2C configuration, depending on user's managed parameters + GetI2cConfig(pConfig, &palI2c->Configuration); + + // compute rough estimate on the time to tx/rx a byte (in milliseconds) + if((I2cBusSpeed)pConfig[ I2cConnectionSettings::FIELD___busSpeed ].NumericByRef().s4 == I2cBusSpeed_StandardMode) + { + // 100kbit/s: this is roughly 0.10ms per byte, give or take + palI2c->ByteTime = 0.1; + } + else + { + // 400kbit/s: this is roughly 0.02ms per byte, give or take + palI2c->ByteTime = 0.02; + } + + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::NativeDispose___VOID__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + uint8_t busIndex; + bool disposeController = false; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get disposeController + disposeController = (bool)stack.Arg0().NumericByRef().u1; + + if(disposeController) + { + // get bus index + // this is coded with a multiplication, need to perform and int division to get the number + // see the comments in the I2cDevice() constructor in managed code for details + busIndex = (uint8_t)(pThis[ FIELD___deviceId ].NumericByRef().s4 / 1000); + + // get the driver for the I2C bus + switch (busIndex) + { + #if STM32_I2C_USE_I2C1 + case 1 : + // deactivates the I2C peripheral + i2cStop(&I2CD1); + // nulls driver + I2C1_PAL.Driver = NULL; + break; + #endif + + #if STM32_I2C_USE_I2C2 + case 2 : + // deactivates the I2C peripheral + i2cStop(&I2CD2); + // nulls driver + I2C2_PAL.Driver = NULL; + break; + #endif + + #if STM32_I2C_USE_I2C3 + case 3 : + // deactivates the I2C peripheral + i2cStop(&I2CD3); + // nulls driver + I2C3_PAL.Driver = NULL; + break; + #endif + + #if STM32_I2C_USE_I2C4 + case 4 : + // deactivates the I2C peripheral + i2cStop(&I2CD4); + // nulls driver + I2C4_PAL.Driver = NULL; + break; + #endif + + default: + // the requested I2C bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::NativeTransmit___WindowsDevicesI2cI2cTransferResult__SZARRAY_U1__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + uint8_t busIndex; + NF_PAL_I2C* palI2c = NULL; + bool isLongRunningOperation = false; + msg_t transactionResult = MSG_OK; + + CLR_RT_HeapBlock hbTimeout; + CLR_INT64* timeout; + bool eventResult = true; + uint32_t estimatedDurationMiliseconds; + + CLR_RT_HeapBlock_Array* writeBuffer; + CLR_RT_HeapBlock_Array* readBuffer; + CLR_RT_HeapBlock* result; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get pointer to connection settings field + CLR_RT_HeapBlock* connectionSettings = pThis[ FIELD___connectionSettings ].Dereference(); + + // get bus index + // this is coded with a multiplication, need to perform and int division to get the number + // see the comments in the I2cDevice() constructor in managed code for details + busIndex = (uint8_t)(pThis[ FIELD___deviceId ].NumericByRef().s4 / 1000); + + // get the driver for the I2C bus + switch (busIndex) + { + #if STM32_I2C_USE_I2C1 + case 1 : + palI2c = &I2C1_PAL; + break; + #endif + #if STM32_I2C_USE_I2C2 + case 2 : + palI2c = &I2C2_PAL; + break; + #endif + #if STM32_I2C_USE_I2C3 + case 3 : + palI2c = &I2C3_PAL; + break; + #endif + #if STM32_I2C_USE_I2C4 + case 4 : + palI2c = &I2C4_PAL; + break; + #endif + default: + // the requested I2C bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // dereference the write and read buffers from the arguments + writeBuffer = stack.Arg1().DereferenceArray(); + if (writeBuffer != NULL) + { + // get the size of the buffer by reading the number of elements in the CLR_RT_HeapBlock_Array + palI2c->WriteSize = writeBuffer->m_numOfElements; + } + else + { + // nothing to write, have to zero this + palI2c->WriteSize = 0; + } + + readBuffer = stack.Arg2().DereferenceArray(); + if (readBuffer != NULL) + { + // get the size of the buffer by reading the number of elements in the CLR_RT_HeapBlock_Array + palI2c->ReadSize = readBuffer->m_numOfElements; + } + else + { + // nothing to read, have to zero this + palI2c->ReadSize = 0; + } + + // check if this is a long running operation + isLongRunningOperation = IsLongRunningOperation(palI2c->WriteSize, palI2c->ReadSize, palI2c->ByteTime, (uint32_t&)estimatedDurationMiliseconds); + + if(isLongRunningOperation) + { + // if this is a long running operation, set a timeout equal to the estimated transaction duration in milliseconds + // this value has to be in ticks to be properly loaded by SetupTimeoutFromTicks() below + hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); + + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks( hbTimeout, timeout )); + + // protect the buffers from GC so DMA can find them where they are supposed to be + CLR_RT_ProtectFromGC gcWriteBuffer( *writeBuffer ); + CLR_RT_ProtectFromGC gcReadBuffer( *readBuffer ); + } + + // this is going to be used to check for the right event in case of simultaneous I2C transaction + if(!isLongRunningOperation || stack.m_customState == 1) + { + // get slave address from connection settings field + palI2c->Address = (i2caddr_t)connectionSettings[Library_win_dev_i2c_native_Windows_Devices_I2c_I2cConnectionSettings::FIELD___slaveAddress].NumericByRef().s4; + + // when using I2Cv1 driver the address needs to be loaded in the I2C driver struct + #if defined(STM32F1XX) || defined(STM32F4XX) || defined(STM32L1XX) + palI2c->Driver->addr = palI2c->Address; + #endif + + if (writeBuffer != NULL) + { + palI2c->WriteBuffer = (uint8_t*)writeBuffer->GetFirstElement(); + + // flush DMA buffer to ensure cache coherency + // (only required for Cortex-M7) + cacheBufferFlush(palI2c->WriteBuffer, palI2c->WriteSize); + } + + if (readBuffer != NULL) + { + palI2c->ReadBuffer = (uint8_t*)readBuffer->GetFirstElement(); + } + + // because the bus access is shared, acquire the appropriate bus + i2cAcquireBus(palI2c->Driver); + i2cStart(palI2c->Driver, &palI2c->Configuration); + } + + if(isLongRunningOperation) + { + // this is a long running operation and hasn't started yet + // perform I2C transaction using driver's ASYNC API which is launching a thread to perform it + if(stack.m_customState == 1) + { + // spawn working thread to perform the I2C transaction + palI2c->WorkingThread = chThdCreateFromHeap(NULL, THD_WORKING_AREA_SIZE(256), + "I2CWT", NORMALPRIO, I2CWorkingThread, palI2c); + + if(palI2c->WorkingThread == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } + + // bump custom state + stack.m_customState = 2; + } + } + else + { + // this is NOT a long running operation + // perform I2C transaction using driver's SYNC API + + if (palI2c->ReadSize != 0 && palI2c->WriteSize != 0) + { + // this is a Write/Read transaction + transactionResult = i2cMasterTransmitTimeout(palI2c->Driver, palI2c->Address, palI2c->WriteBuffer, palI2c->WriteSize, palI2c->ReadBuffer, palI2c->ReadSize, TIME_MS2I(20)); + } + else + { + if (palI2c->ReadSize == 0) + { + // this is Write only transaction + transactionResult = i2cMasterTransmitTimeout(palI2c->Driver, palI2c->Address, palI2c->WriteBuffer, palI2c->WriteSize, NULL, 0, TIME_MS2I(20)); + } + else + { + // this is a Read only transaction + transactionResult = i2cMasterReceiveTimeout (palI2c->Driver, palI2c->Address, palI2c->ReadBuffer, palI2c->ReadSize, TIME_MS2I(20)); + } + } + } + + while(eventResult) + { + if(!isLongRunningOperation) + { + // this is not a long running operation so nothing to do here + break; + } + + if(palI2c->WorkingThread->state == CH_STATE_FINAL) + { + // I2C working thread is now complete + break; + } + + // non-blocking wait allowing other threads to run while we wait for the I2C transaction to complete + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_I2cMaster, eventResult )); + } + + if(isLongRunningOperation) + { + // pop timeout heap block from stack + stack.PopValue(); + } + + if(eventResult || !isLongRunningOperation) + { + // event occurred + // OR this is NOT a long running operation + + i2cReleaseBus(palI2c->Driver); + + // create the return object (I2cTransferResult) + // only at this point we are sure that there will be a return from this thread so it's OK to use the managed stack + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_I2cTransferResult)); + result = top.Dereference(); FAULT_ON_NULL(result); + + if(isLongRunningOperation) + { + // ChibiOS requirement: need to call chThdWait for I2C working thread in order to have it's memory released to the heap, otherwise it won't be returned + transactionResult = chThdWait(palI2c->WorkingThread); + } + + // get the result from the working thread execution + if (transactionResult != MSG_OK) + { + // error in transaction + int errors = i2cGetErrors(palI2c->Driver); + + // figure out what was the error and set the status field + switch(errors) + { + case I2C_ACK_FAILURE: + result[ Library_win_dev_i2c_native_Windows_Devices_I2c_I2cTransferResult::FIELD___status ].SetInteger((CLR_UINT32)I2cTransferStatus_SlaveAddressNotAcknowledged); + break; + + case I2C_TIMEOUT: + result[ Library_win_dev_i2c_native_Windows_Devices_I2c_I2cTransferResult::FIELD___status ].SetInteger((CLR_UINT32)I2cTransferStatus_ClockStretchTimeout); + break; + + default: + result[ Library_win_dev_i2c_native_Windows_Devices_I2c_I2cTransferResult::FIELD___status ].SetInteger((CLR_UINT32)I2cTransferStatus_UnknownError); + } + + // set the bytes transferred count to 0 because we don't have a way to know how many bytes were actually sent/received + result[ Library_win_dev_i2c_native_Windows_Devices_I2c_I2cTransferResult::FIELD___bytesTransferred ].SetInteger(0); + } + else + { + // successfull transaction + // set the result field + result[ Library_win_dev_i2c_native_Windows_Devices_I2c_I2cTransferResult::FIELD___status ].SetInteger((CLR_UINT32)I2cTransferStatus_FullTransfer); + + // set the bytes transferred field + result[ Library_win_dev_i2c_native_Windows_Devices_I2c_I2cTransferResult::FIELD___bytesTransferred ].SetInteger((CLR_UINT32)(palI2c->WriteSize + palI2c->ReadSize)); + } + + if(palI2c->ReadSize > 0) + { + // invalidate cache over read buffer to ensure that content from DMA is read + // (only required for Cortex-M7) + cacheBufferInvalidate(palI2c->ReadBuffer, palI2c->ReadSize); + } + } + + } + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2c_I2cController.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2c_I2cController.cpp new file mode 100644 index 00000000..d718a27e --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2c_I2cController.cpp @@ -0,0 +1,52 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include +#include "win_dev_i2c_native_target.h" + + +HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cController::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + { + + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cController::GetDeviceSelector___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // declare the device selector string whose max size is "I2C1,I2C2,I2C3,I2C4," + terminator and init with the terminator + char deviceSelectorString[20 + 1] = { 0 }; + + #if STM32_I2C_USE_I2C1 + strcat(deviceSelectorString, "I2C1,"); + #endif + #if STM32_I2C_USE_I2C2 + strcat(deviceSelectorString, "I2C2,"); + #endif + #if STM32_I2C_USE_I2C3 + strcat(deviceSelectorString, "I2C3,"); + #endif + #if STM32_I2C_USE_I2C4 + strcat(deviceSelectorString, "I2C4,"); + #endif + // replace the last comma with a terminator + deviceSelectorString[hal_strlen_s(deviceSelectorString) - 1] = '\0'; + + // because the caller is expecting a result to be returned + // we need set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + stack.SetResult_String(deviceSelectorString); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_target.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_target.h new file mode 100644 index 00000000..734e1ca2 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_target.h @@ -0,0 +1,63 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIN_DEV_I2C_NATIVE_TARGET_H_ +#define _WIN_DEV_I2C_NATIVE_TARGET_H_ + +#include +#include + +// struct representing the I2C +struct NF_PAL_I2C +{ + I2CDriver* Driver; + I2CConfig Configuration; + thread_t* WorkingThread; + i2caddr_t Address; + float ByteTime; + + uint8_t* WriteBuffer; + uint8_t WriteSize; + + uint8_t* ReadBuffer; + uint8_t ReadSize; +}; + +/////////////////////////////////////////// +// declaration of the the I2C PAL strucs // +/////////////////////////////////////////// +#if STM32_I2C_USE_I2C1 + extern NF_PAL_I2C I2C1_PAL; +#endif +#if STM32_I2C_USE_I2C2 + extern NF_PAL_I2C I2C2_PAL; +#endif +#if STM32_I2C_USE_I2C3 + extern NF_PAL_I2C I2C3_PAL; +#endif +#if STM32_I2C_USE_I2C4 + extern NF_PAL_I2C I2C4_PAL; +#endif + + +// the following macro defines a function that configures the GPIO pins for a STM32 I2C peripheral +// it gets called in the Windows_Devices_I2c_I2cDevice::NativeInit function +// this is required because the I2C peripherals can use multiple GPIO configuration combinations +#define I2C_CONFIG_PINS(num, gpio_port_scl, gpio_port_sda, scl_pin, sda_pin, alternate_function) void ConfigPins_I2C##num() \ +{ \ + palSetPadMode(gpio_port_scl, scl_pin, (PAL_MODE_ALTERNATE(alternate_function) | PAL_STM32_OSPEED_HIGHEST | PAL_STM32_OTYPE_OPENDRAIN) ); \ + palSetPadMode(gpio_port_sda, sda_pin, (PAL_MODE_ALTERNATE(alternate_function) | PAL_STM32_OSPEED_HIGHEST | PAL_STM32_OTYPE_OPENDRAIN)); \ +} + +////////////////////////////////////////////////////////////////////////////////////////////// +// when an I2C is defined the declarations below will have the real function/configuration // +// in the target folder @ target_windows_devices_i2c_config.cpp // +////////////////////////////////////////////////////////////////////////////////////////////// +void ConfigPins_I2C1(); +void ConfigPins_I2C2(); +void ConfigPins_I2C3(); +void ConfigPins_I2C4(); + +#endif //_WIN_DEV_I2C_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp new file mode 100644 index 00000000..f4ff01b3 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp @@ -0,0 +1,161 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include +#include "win_dev_pwm_native_target.h" + +PWMConfig _pwmConfig; + +extern PWMDriver* GetDriver(int timerId); + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_MaxFrequency___R8( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties + double maxFrequency = 0.0; + +#if defined(STM32F4XX) || defined(STM32F7XX) + int timerId = (int)(pThis[ FIELD___controllerId ].NumericByRef().u4); + + if (timerId == 1 || timerId >= 8) maxFrequency = (double)STM32_PCLK2_MAX; // TIM1, TIM8 and TIM9 on APB2 + else maxFrequency = (double)STM32_PCLK1_MAX; // other timers on APB1 + +#elif defined(STM32F0XX) + + maxFrequency = (double)STM32_PCLK_MAX; // Only APB1 on this MCU + +#endif + stack.SetResult_R8(maxFrequency); + + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_MinFrequency___R8( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // FIXME : how can this value be determined ? + stack.SetResult_R8(1.0); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_PinCount___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + int pinCount = 0; +#if defined(STM32F4XX) + pinCount = 42; +#elif defined(STM32F7XX) + //FIXME: arbitrary value, here. Where do I find the information ? + pinCount = 42; +#elif defined(STM32F0XX) + pinCount = 24; +#endif + stack.SetResult_I4(pinCount); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::NativeSetDesiredFrequency___U4__U4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties + int timerId = (int)(pThis[ FIELD___controllerId ].NumericByRef().u4); + unsigned int desiredFrequency = (unsigned int)stack.Arg1().NumericByRef().u4; + + // Gets the PWM driver associated with the requested timer + PWMDriver * _drv; + _drv = GetDriver(timerId); + + // Sets the period to something able to be precise enough with low and high frequencies + // and that allows the clock frequency parameter to fit in an unsigned int + int period = 1000; + if (desiredFrequency >= 1000) period = 100; + else if (desiredFrequency >= 1000000) period = 10; + + // Build the PWM config structure + PWMConfig pwmConfig = + { + (desiredFrequency * period), // PWM clock frequency + (pwmcnt_t)period, // PWM period + NULL, // No callback + // Enable all channels + { + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, + {PWM_OUTPUT_ACTIVE_HIGH, NULL}, + {PWM_OUTPUT_ACTIVE_HIGH, NULL} + }, + 0, + #if STM32_PWM_USE_ADVANCED + 0, + #endif + 0, + }; + + // Starts the pwm driver + pwmStop(_drv); + osDelay(5); + pwmStart(_drv, &pwmConfig); + + stack.SetResult_R8((double)desiredFrequency); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::GetDeviceSelector___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // declare the device selector string whose max size is "TIM1,TIM3,TIM4,TIM5,TIM8,TIM9," + terminator and init with the terminator + char deviceSelectorString[ 30 + 1] = { 0 }; + + #if STM32_PWM_USE_TIM1 + strcat(deviceSelectorString, "TIM1,"); + #endif + #if STM32_PWM_USE_TIM2 + strcat(deviceSelectorString, "TIM2,"); + #endif + #if STM32_PWM_USE_TIM3 + strcat(deviceSelectorString, "TIM3,"); + #endif +#ifndef STM32F0XX + #if STM32_PWM_USE_TIM4 + strcat(deviceSelectorString, "TIM4,"); + #endif + #if STM32_PWM_USE_TIM5 + strcat(deviceSelectorString, "TIM5,"); + #endif + #if STM32_PWM_USE_TIM8 + strcat(deviceSelectorString, "TIM8,"); + #endif + #if STM32_PWM_USE_TIM9 + strcat(deviceSelectorString, "TIM9,"); + #endif +#endif + // replace the last comma with a terminator + deviceSelectorString[hal_strlen_s(deviceSelectorString) - 1] = '\0'; + + // because the caller is expecting a result to be returned + // we need set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + stack.SetResult_String(deviceSelectorString); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp new file mode 100644 index 00000000..db025708 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp @@ -0,0 +1,975 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include "win_dev_pwm_native_target.h" +#include + +int GetChannel (int pin, int timerId) +{ + int channel = -1; +#if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + switch (timerId) + { + case 1 : + switch (pin) + { + case 8 : // PA8 + case 4*16+9 : // PE9 + channel = 0; + break; + case 9 : // PA9 + case 4*16+11 : // PE11 + channel = 1; + break; + case 10 : // PA10 + case 4*16+13 : // PE13 + channel = 2; + break; + case 11 : // PA11 + case 4*16+14 : // PE14 + channel = 3; + break; + } + break; + + case 2 : + switch (pin) + { + case 0 : // PA0, PA5, PA15 + case 5 : + case 15 : + channel = 0; + break; + case 1 : // PA1, PB3 + case 1 * 16 + 3 : + channel = 1; + break; + case 2 : // PA2, PB10 + case 1 * 16 + 10 : + channel = 2; + break; + case 3 : // PA3, PB11 + case 1 * 16 + 11 : + channel = 3; + break; + } + break; + + case 3 : + switch (pin) + { + case 0 : + case 5 : + case 15 : + channel = 0; + break; + case 1 : + case 1*16+3 : + channel = 1; + break; + case 2 : + case 1*16+10 : + channel = 2; + break; + case 3 : + case 1*16+11 : + channel = 3; + break; + } + break; + case 4 : + switch (pin) + { + case 1 * 16 + 6 : // PB6, PD12 + case 3 * 16 + 12 : + channel = 0; + break; + case 1 * 16 + 7 : // PB7, PD13 + case 3 * 16 + 13 : + channel = 1; + break; + case 1 * 16 + 8 : // PB8, PD14 + case 3 * 16 + 14 : + channel = 2; + break; + case 1 * 16 + 9 : // PB9, PD15 + case 3 * 16 + 15 : + channel = 3; + break; + } + break; + + case 5 : + switch (pin) + { + case 0 : // PA0, PH10 + case 7 * 16 + 10 : + channel = 0; + break; + case 1 : // PA1, PH11 + case 7 * 16 + 11 : + channel = 1; + break; + case 2 : // PA2, PH12 + case 7 * 16 + 12 : + channel = 2; + break; + case 3 : // PA3, PI0 + case 8 * 16 + 0 : + channel = 3; + break; + } + break; + + case 8 : + switch (pin) + { + case 2 * 16 + 6 : // PC6, PI5 + case 7 * 16 + 5 : + channel = 0; + break; + case 2 * 16 + 7 : // PC7, PI6 + case 7 * 16 + 6 : + channel = 1; + break; + case 2 * 16 + 8 : // PC8, PI7 + case 7 * 16 + 7 : + channel = 2; + break; + case 2 * 16 + 9 : // PC9 + channel = 3; + break; + } + break; + + case 9 : + switch (pin) + { + case 2 * 16 + 6 : // PC6, PI5 + case 7 * 16 + 5 : + channel = 0; + break; + case 2 * 16 + 7 : // PC7, PI6 + case 7 * 16 + 6 : + channel = 1; + break; + case 2 * 16 + 8 : // PC8, PI7 + case 7 * 16 + 7 : + channel = 2; + break; + case 2 * 16 + 9 : // PC9 + channel = 3; + break; + } + break; + + default : + channel = 0xFF; + break; + } +#endif +#if defined(STM32F411xx) || defined(STM32F412xx) || defined(STM32F401xx) +switch (timerId) + { + case 1 : + switch (pin) + { + case 8 : // PA8 + channel = 0; + break; + case 9 : // PA9 + channel = 1; + break; + case 10 : // PA10 + channel = 2; + break; + case 11 : // PA11 + channel = 3; + break; + } + break; + + case 2 : + switch (pin) + { + case 0 : // PA0, PA5, PA15 + case 5 : + case 15 : + channel = 0; + break; + case 1 : // PA1, PB3 + case 1 * 16 + 3 : + channel = 1; + break; + case 2 : // PA2, PB10 + case 1 * 16 + 10 : + channel = 2; + break; + case 3 : // PA3 + channel = 3; + break; + } + break; + case 3 : + switch (pin) + { + case 6 : // PA6, PB4 + case 1 * 16 + 4 : + channel = 0; + break; + case 7 : // PA7, PB5 + case 1 * 16 + 5 : + channel = 1; + break; + case 1 * 16 + 0 : // PB0 + channel = 2; + break; + case 1 * 16 + 1 : // PB1 + channel = 3; + break; + } + break; + case 4 : + switch (pin) + { + case 1 * 16 + 6 : // PB6 + channel = 0; + break; + case 1 * 16 + 7 : // PB7 + channel = 1; + break; + case 1 * 16 + 8 : // PB8 + channel = 2; + break; + case 1 * 16 + 9 : // PB9 + channel = 3; + break; + } + break; + + case 5 : + switch (pin) + { + case 0 : // PA0 + channel = 0; + break; + case 1 : // PA1 + channel = 1; + break; + case 2 : // PA2 + channel = 2; + break; + case 3 : // PA3 + channel = 3; + break; + } + break; + + case 9 : + switch (pin) + { + case 2 : // PA2 + channel = 0; + break; + case 3 : // PA3 + channel = 1; + break; + } + break; + + default : + channel = 0xFF; + break; + } +#endif +#if defined(STM32F746xx) +switch (timerId) + { + case 1 : + switch (pin) + { + case 8 : // PA8, PE9 + case 4*16+9 : + channel = 0; + break; + case 9 : // PA9, PE11 + case 4*16+11 : + channel = 1; + break; + case 10 : // PA10, PE13 + case 4*16+13 : + channel = 2; + break; + case 11 : // PA11, PE14 + case 4*16+14 : + channel = 3; + break; + } + break; + + case 2 : + switch (pin) + { + case 0 : // PA0, PA5, PA15 + case 5 : + case 15 : + channel = 0; + break; + case 1 : // PA1, PB3 + case 1*16+3 : + channel = 1; + break; + case 2 : // PA2, PB10 + case 1*16+10 : + channel = 2; + break; + case 3 : // PA3, PB11 + case 1*16+11 : + channel = 3; + break; + } + break; + case 3 : + switch (pin) + { + case 6 : // PA6, PB4, PC6 + case 1 * 16 + 4 : + case 2 * 16 + 6 : + channel = 0; + break; + case 7 : // PA7, PB5, PC7 + case 1 * 16 + 5 : + case 2 * 16 + 7 : + channel = 1; + break; + case 1 * 16 + 0 : // PB0, PC8 + case 2 * 16 + 8 : + channel = 2; + break; + case 1 * 16 + 1 : // PB1, PC9 + case 2 * 16 + 9 : + channel = 3; + break; + } + break; + case 4 : + switch (pin) + { + case 1*16+6 : // PB6, PD12 + case 3*16+12 : + channel = 0; + break; + case 1*16+7 : // PB7, PD13 + case 3*16+13 : + channel = 1; + break; + case 1*16+8 : // PB8, PD14 + case 3*16+14 : + channel = 2; + break; + case 1*16+9 : // PB9, PD15 + case 3*16+15 : + channel = 3; + break; + } + break; + + case 5 : + switch (pin) + { + case 0 : // PA0 + channel = 0; + break; + case 1 : // PA1 + channel = 1; + break; + case 2 : // PA2 + channel = 2; + break; + case 3 : // PA3 + channel = 3; + break; + } + break; + + case 8 : + switch (pin) + { + case 2*16+6 : // PC6 + channel = 0; + break; + case 2*16+7 : // PC7 + channel = 1; + break; + case 2*16+8 : // PC8 + channel = 2; + break; + case 2*16+9 : // PC9 + channel = 3; + break; + } + break; + + + case 9 : + switch (pin) + { + case 2 : // PA2, PE5 + case 4*16+5 : + channel = 0; + break; + case 3 : // PA3, PE6 + case 4*16+6 : + channel = 1; + break; + } + break; + + default : + channel = 0xFF; + break; + } +#endif +#if defined(STM32F769xx) +switch (timerId) + { + case 1 : + switch (pin) + { + case 8 : // PA8, PE9 + case 4*16+9 : + channel = 0; + break; + case 9 : // PA9, PE11 + case 4*16+11 : + channel = 1; + break; + case 10 : // PA10, PE13 + case 4*16+13 : + channel = 2; + break; + case 11 : // PA11, PE14 + case 4*16+14 : + channel = 3; + break; + } + break; + + case 2 : + switch (pin) + { + case 0 : // PA0, PA5, PA15 + case 5 : + case 15 : + channel = 0; + break; + case 1 : // PA1, PB3 + case 1*16+3 : + channel = 1; + break; + case 2 : // PA2, PB10 + case 1*16+10 : + channel = 2; + break; + case 3 : // PA3, PB11 + case 1*16+11 : + channel = 3; + break; + } + break; + case 3 : + switch (pin) + { + case 6 : // PA6, PB4, PC6 + case 1 * 16 + 4 : + case 2 * 16 + 6 : + channel = 0; + break; + case 7 : // PA7, PB5, PC7 + case 1 * 16 + 5 : + case 2 * 16 + 7 : + channel = 1; + break; + case 1 * 16 + 0 : // PB0, PC8 + case 2 * 16 + 8 : + channel = 2; + break; + case 1 * 16 + 1 : // PB1, PC9 + case 2 * 16 + 9 : + channel = 3; + break; + } + break; + case 4 : + switch (pin) + { + case 1*16+6 : // PB6, PD12 + case 3*16+12 : + channel = 0; + break; + case 1*16+7 : // PB7, PD13 + case 3*16+13 : + channel = 1; + break; + case 1*16+8 : // PB8, PD14 + case 3*16+14 : + channel = 2; + break; + case 1*16+9 : // PB9, PD15 + case 3*16+15 : + channel = 3; + break; + } + break; + + case 5 : + switch (pin) + { + case 0 : // PA0, PH10 + case 7*16+10 : + channel = 0; + break; + case 1 : // PA1, PH11 + case 7*16+11 : + channel = 1; + break; + case 2 : // PA2, PH12 + case 7*16+12 : + channel = 2; + break; + case 3 : // PA3, PI0 + case 8*16+0 : + channel = 3; + break; + } + break; + + case 8 : + switch (pin) + { + case 2*16+6 : // PC6, PI5 + case 8*16+5 : + channel = 0; + break; + case 2*16+7 : // PC7, PI6 + case 8*16+6 : + channel = 1; + break; + case 2*16+8 : // PC8, PI7 + case 8*16+7 : + channel = 2; + break; + case 2*16+9 : // PC9, PI2 + case 8*16+2 : + channel = 3; + break; + } + break; + + + case 9 : + switch (pin) + { + case 2 : // PA2, PE5 + case 4*16+5 : + channel = 0; + break; + case 3 : // PA3, PE6 + case 4*16+6 : + channel = 1; + break; + } + break; + + default : + channel = 0xFF; + break; + } +#endif +#if defined(STM32F091xC) +switch (timerId) + { + case 1 : + switch (pin) + { + case 8 : // PA8 + channel = 0; + break; + case 9 : // PA9 + channel = 1; + break; + case 10 : // PA10 + channel = 2; + break; + case 11 : // PA11 + channel = 3; + break; + } + break; + + case 2 : + switch (pin) + { + case 0 : // PA0, PA5, PA15 + case 5 : + case 15 : + channel = 0; + break; + case 1 : // PA1, PB3 + case 1*16+3 : + channel = 1; + break; + case 2 : // PA2, PB10 + case 1*16+10 : + channel = 2; + break; + case 3 : // PA3, PB11 + case 1*16+11 : + channel = 3; + break; + } + break; + case 3 : + switch (pin) + { + case 6 : // PA6, PB4, PC6 + case 1 * 16 + 4 : + case 2 * 16 + 6 : + channel = 0; + break; + case 7 : // PA7, PB5, PC7 + case 1 * 16 + 5 : + case 2 * 16 + 7 : + channel = 1; + break; + case 1 * 16 + 0 : // PB0, PC8 + case 2 * 16 + 8 : + channel = 2; + break; + case 1 * 16 + 1 : // PB1, PC9 + case 2 * 16 + 9 : + channel = 3; + break; + } + break; + default : + channel = 0xFF; + break; + } +#endif +#if defined(STM32F407xx) || defined(STM32F405xx) + switch (timerId) + { + case 1 : + switch (pin) + { + case 8 : // PA8 + case 4*16+9 : // PE9 + channel = 0; + break; + case 9 : // PA9 + case 4*16+11 : // PE11 + channel = 1; + break; + case 10 : // PA10 + case 4*16+13 : // PE13 + channel = 2; + break; + case 11 : // PA11 + case 4*16+14 : // PE14 + channel = 3; + break; + } + break; + + case 2 : + switch (pin) + { + case 0 : // PA0, PA5, PA15 + case 5 : + case 15 : + channel = 0; + break; + case 1 : // PA1, PB3 + case 1 * 16 + 3 : + channel = 1; + break; + case 2 : // PA2, PB10 + case 1 * 16 + 10 : + channel = 2; + break; + case 3 : // PA3, PB11 + case 1 * 16 + 11 : + channel = 3; + break; + } + break; + + case 3 : + switch (pin) + { + case 6 : + case 1*16+4 : + case 2*16+6 : + channel = 0; + break; + case 7 : + case 1*16+5 : + case 2*16+7 : + channel = 1; + break; + case 1*16+0 : + case 2*16+8 : + channel = 2; + break; + case 1*16+1 : + case 2*16+9 : + channel = 3; + break; + } + break; + case 4 : + switch (pin) + { + case 1 * 16 + 6 : // PB6, PD12 + case 3 * 16 + 12 : + channel = 0; + break; + case 1 * 16 + 7 : // PB7, PD13 + case 3 * 16 + 13 : + channel = 1; + break; + case 1 * 16 + 8 : // PB8, PD14 + case 3 * 16 + 14 : + channel = 2; + break; + case 1 * 16 + 9 : // PB9, PD15 + case 3 * 16 + 15 : + channel = 3; + break; + } + break; + + case 5 : + switch (pin) + { + case 0 : // PA0 + channel = 0; + break; + case 1 : // PA1 + channel = 1; + break; + case 2 : // PA2 + channel = 2; + break; + case 3 : // PA3 + channel = 3; + break; + } + break; + + case 8 : + switch (pin) + { + case 2 * 16 + 6 : // PC6 + channel = 0; + break; + case 2 * 16 + 7 : // PC7 + channel = 1; + break; + case 2 * 16 + 8 : // PC8 + channel = 2; + break; + case 2 * 16 + 9 : // PC9 + channel = 3; + break; + } + break; + + case 9 : + switch (pin) + { + case 2 : // PA2, PE5 + case 4 * 16 + 5 : + channel = 0; + break; + case 3 : // PA3, PE6 + case 4 * 16 + 6 : + channel = 1; + break; + } + break; + + default : + channel = 0xFF; + break; + } +#endif + return channel; +} + +int GetAlternateFunction (int timerId) +{ + if (timerId >= 8) return 3; + if (timerId >= 3) return 2; + return 1; +} + +PWMDriver * GetDriver(int timerId) +{ + PWMDriver * _drv = NULL; + + switch (timerId) + { +#if STM32_PWM_USE_TIM1 + case 1 : _drv = &PWMD1; + break; +#endif +#if STM32_PWM_USE_TIM2 + case 2 : _drv = &PWMD2; + break; +#endif +#if STM32_PWM_USE_TIM3 + case 3 : _drv = &PWMD3; + break; +#endif +#if STM32_PWM_USE_TIM4 + case 4 : _drv = &PWMD4; + break; +#endif +#if STM32_PWM_USE_TIM5 + case 5 : _drv = &PWMD5; + break; +#endif +#if STM32_PWM_USE_TIM8 + case 8 : _drv = &PWMD8; + break; +#endif +#if STM32_PWM_USE_TIM9 + case 9 : _drv = &PWMD9; + break; +#endif + } + + return _drv; +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeSetActiveDutyCyclePercentage___VOID__U4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + PWMDriver * _drv; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties or method parameters + int timerId = (int)(pThis[ FIELD___pwmTimer ].NumericByRef().u4); + int pinNumber = (int)(pThis[ FIELD___pinNumber ].NumericByRef().u4); + unsigned int dutyCycle = (unsigned int)stack.Arg1().NumericByRef().u4; + + // Gets the PWM driver associated with the requested timer + _drv = GetDriver(timerId); + + // get channel for this pin and timer + int channelId = GetChannel(pinNumber, timerId); + if(channelId < 0) + { + // no channel available for combination pinNumber/timerId provided + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + // Enables the channel associated with the selected pin on that timer + pwmEnableChannel(_drv, channelId ,PWM_PERCENTAGE_TO_WIDTH(_drv, dutyCycle)); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeSetPolarity___VOID__U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeStart___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + PWMDriver * _drv; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties or method parameters + int timerId = (int)(pThis[ FIELD___pwmTimer ].NumericByRef().u4); + int pinNumber = (int)(pThis[ FIELD___pinNumber ].NumericByRef().u4); + unsigned int dutyCycle = (int)(pThis[ FIELD___dutyCycle ].NumericByRef().u4); + + // Gets the PWM driver associated with the requested timer + _drv = GetDriver(timerId); + + // get channel for this pin and timer + int channelId = GetChannel(pinNumber, timerId); + if(channelId < 0) + { + // no channel available for combination pinNumber/timerId provided + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + // Sets the pin to the correct pwm alternate functin and enables the associated channel + palSetPadMode(GPIO_PORT(pinNumber), pinNumber % 16, PAL_MODE_ALTERNATE(GetAlternateFunction(timerId))); + pwmEnableChannel(_drv, channelId,PWM_PERCENTAGE_TO_WIDTH(_drv, dutyCycle)); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeStop___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties or method parameters + int timerId = (int)(pThis[ FIELD___pwmTimer ].NumericByRef().u4); + int pinNumber = (int)(pThis[ FIELD___pinNumber ].NumericByRef().u4); + + // get channel for this pin and timer + int channelId = GetChannel(pinNumber, timerId); + if(channelId < 0) + { + // no channel available for combination pinNumber/timerId provided + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + // Stops pwm output on the channel associated with the selected pin + pwmDisableChannel(GetDriver(timerId), channelId); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::DisposeNative___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_target.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_target.h new file mode 100644 index 00000000..802c8c78 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_target.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIN_DEV_PWM_NATIVE_TARGET_H_ +#define _WIN_DEV_PWM_NATIVE_TARGET_H_ + +#include +#include + +#endif //_WIN_DEV_PWM_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.SerialCommunication/win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.SerialCommunication/win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice.cpp new file mode 100644 index 00000000..70bdf3cb --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.SerialCommunication/win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice.cpp @@ -0,0 +1,1162 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include "win_dev_serial_native_target.h" + +///////////////////////////////////////////////////////// +// UART PAL strucs delcared in win_dev_serial_native.h // +///////////////////////////////////////////////////////// +#if NF_SERIAL_COMM_STM32_UART_USE_USART1 + NF_PAL_UART Uart1_PAL; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_USART2 + NF_PAL_UART Uart2_PAL; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_USART3 + NF_PAL_UART Uart3_PAL; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_UART4 + NF_PAL_UART Uart4_PAL; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_UART5 + NF_PAL_UART Uart5_PAL; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_USART6 + NF_PAL_UART Uart6_PAL; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_UART7 + NF_PAL_UART Uart7_PAL; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_UART8 + NF_PAL_UART Uart8_PAL; +#endif + +// This callback is invoked when a transmission buffer has been completely read by the driver. +static void TxEnd1(UARTDriver *uartp) +{ + (void)uartp; + + NATIVE_INTERRUPT_START + + NF_PAL_UART* palUart; + + #if NF_SERIAL_COMM_STM32_UART_USE_USART1 + if (uartp == &UARTD1) + { + palUart = &Uart1_PAL; + } + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART2 + if (uartp == &UARTD2) + { + palUart = &Uart2_PAL; + } + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART3 + if (uartp == &UARTD3) + { + palUart = &Uart3_PAL; + } + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART4 + if (uartp == &UARTD4) + { + palUart = &Uart4_PAL; + } + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART5 + if (uartp == &UARTD5) + { + palUart = &Uart5_PAL; + } + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART6 + if (uartp == &UARTD6) + { + palUart = &Uart6_PAL; + } + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART7 + if (uartp == &UARTD7) + { + palUart = &Uart7_PAL; + } + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART8 + if (uartp == &UARTD8) + { + palUart = &Uart8_PAL; + } + #endif + + // pop elements from ring buffer, just pop + palUart->TxRingBuffer.Pop(palUart->TxOngoingCount); + + // reset Tx ongoing count + palUart->TxOngoingCount = 0; + + Events_Set( SYSTEM_EVENT_FLAG_COM_OUT ); + + NATIVE_INTERRUPT_END +} + +// This callback is invoked when a character is received but the application was not ready to receive it, the character is passed as parameter. +static void RxChar(UARTDriver *uartp, uint16_t c) +{ + NATIVE_INTERRUPT_START + + NF_PAL_UART* palUart; + uint8_t portIndex = 0; + + #if NF_SERIAL_COMM_STM32_UART_USE_USART1 + if (uartp == &UARTD1) + { + palUart = &Uart1_PAL; + portIndex = 1; + } + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART2 + if (uartp == &UARTD2) + { + palUart = &Uart2_PAL; + portIndex = 2; + } + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART3 + if (uartp == &UARTD3) + { + palUart = &Uart3_PAL; + portIndex = 3; + } + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART4 + if (uartp == &UARTD4) + { + palUart = &Uart4_PAL; + portIndex = 4; + } + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART5 + if (uartp == &UARTD5) + { + palUart = &Uart5_PAL; + portIndex = 5; + } + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART6 + if (uartp == &UARTD6) + { + palUart = &Uart6_PAL; + portIndex = 6; + } + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART7 + if (uartp == &UARTD7) + { + palUart = &Uart7_PAL; + portIndex = 7; + } + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART8 + if (uartp == &UARTD8) + { + palUart = &Uart8_PAL; + portIndex = 8; + } + #endif + + // store this into the UART Rx buffer + + // push char to ring buffer + // don't care about the success of the operation, if it's full we are droping the char anyway + palUart->RxRingBuffer.Push((uint8_t)c); + + // is there a read operation going on? + if(palUart->RxBytesToRead > 0) + { + // yes + // check if the requested bytes are available in the buffer... + //... or if the watch char was received + if((palUart->RxRingBuffer.Length() >= palUart->RxBytesToRead) || + (c == palUart->WatchChar)) + { + // reset Rx bytes to read count + palUart->RxBytesToRead = 0; + + // fire event for Rx buffer complete + Events_Set(SYSTEM_EVENT_FLAG_COM_IN); + } + } + else + { + // no read operation ongoing, so fire an event + + // post a managed event with the port index and event code (check if this is the watch char or just another another) + // TODO: check if callbacks are registered so this is called only if there is anyone listening otherwise don't bother + // for that to happen ChibiOS callback has to accept arg which we would passing the GpioPin CLR_RT_HeapBlock (see Gpio handler) + // check http://www.chibios.com/forum/viewtopic.php?f=36&t=4798 + PostManagedEvent( EVENT_SERIAL, 0, portIndex, (c == palUart->WatchChar) ? SerialData_WatchChar : SerialData_Chars ); + } + + NATIVE_INTERRUPT_END +} + +HRESULT Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::NativeDispose___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Choose the driver for this SerialDevice + switch ((int)pThis[ FIELD___portIndex ].NumericByRef().s4) + { + + #if NF_SERIAL_COMM_STM32_UART_USE_USART1 + case 1 : + UnInit_UART1(); + // stop UART + uartStop(&UARTD1); + Uart1_PAL.UartDriver = NULL; + break; + #endif + + #if NF_SERIAL_COMM_STM32_UART_USE_USART2 + case 2 : + UnInit_UART2(); + // stop UART + uartStop(&UARTD2); + Uart2_PAL.UartDriver = NULL; + break; + #endif + + #if NF_SERIAL_COMM_STM32_UART_USE_USART3 + case 3 : + UnInit_UART3(); + // stop UART + uartStop(&UARTD3); + Uart3_PAL.UartDriver = NULL; + break; + #endif + + #if NF_SERIAL_COMM_STM32_UART_USE_UART4 + case 4 : + UnInit_UART4(); + // stop UART + uartStop(&UARTD4); + Uart4_PAL.UartDriver = NULL; + break; + #endif + + #if NF_SERIAL_COMM_STM32_UART_USE_UART5 + case 5 : + UnInit_UART5(); + // stop UART + uartStop(&UARTD5); + Uart5_PAL.UartDriver = NULL; + break; + #endif + + #if NF_SERIAL_COMM_STM32_UART_USE_USART6 + case 6 : + UnInit_UART6(); + // stop UART + uartStop(&UARTD6); + Uart6_PAL.UartDriver = NULL; + break; + #endif + + #if NF_SERIAL_COMM_STM32_UART_USE_UART7 + case 7 : + UnInit_UART7(); + // stop UART + uartStop(&UARTD7); + Uart7_PAL.UartDriver = NULL; + break; + #endif + + #if NF_SERIAL_COMM_STM32_UART_USE_UART8 + case 8 : + UnInit_UART8(); + // stop UART + uartStop(&UARTD8); + Uart8_PAL.UartDriver = NULL; + break; + #endif + + default: + // this COM port is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + NF_PAL_UART* palUart; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Choose the driver for this SerialDevice + switch ((int)pThis[ FIELD___portIndex ].NumericByRef().s4) + { + #if NF_SERIAL_COMM_STM32_UART_USE_USART1 + case 1 : + Init_UART1(); + Uart1_PAL.UartDriver = &UARTD1; + palUart = &Uart1_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART2 + case 2 : + Init_UART2(); + Uart2_PAL.UartDriver = &UARTD2; + palUart = &Uart2_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART3 + case 3 : + Init_UART3(); + Uart3_PAL.UartDriver = &UARTD3; + palUart = &Uart3_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART4 + case 4 : + Init_UART4(); + Uart4_PAL.UartDriver = &UARTD4; + palUart = &Uart4_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART5 + case 5 : + Init_UART5(); + Uart5_PAL.UartDriver = &UARTD5; + palUart = &Uart5_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART6 + case 6 : + Init_UART6(); + Uart6_PAL.UartDriver = &UARTD6; + palUart = &Uart6_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART7 + case 7 : + Init_UART7(); + Uart7_PAL.UartDriver = &UARTD7; + palUart = &Uart7_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART8 + case 8 : + Init_UART8(); + Uart8_PAL.UartDriver = &UARTD8; + palUart = &Uart8_PAL; + break; + #endif + default: + // this COM port is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // configure UART handlers + palUart->Uart_cfg.txend1_cb = TxEnd1; + palUart->Uart_cfg.rxchar_cb = RxChar; + //palUart->Uart_cfg.rxend_cb = RxEnd; + + // call the configure + return NativeConfig___VOID(stack); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::NativeConfig___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + NF_PAL_UART* palUart = NULL; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Choose the driver for this SerialDevice + switch ((int)pThis[ FIELD___portIndex ].NumericByRef().s4) + { + #if NF_SERIAL_COMM_STM32_UART_USE_USART1 + case 1 : + palUart = &Uart1_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART2 + case 2 : + palUart = &Uart2_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART3 + case 3 : + palUart = &Uart3_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART4 + case 4 : + palUart = &Uart4_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART5 + case 5 : + palUart = &Uart5_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART6 + case 6 : + palUart = &Uart6_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART7 + case 7 : + palUart = &Uart7_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART8 + case 8 : + palUart = &Uart8_PAL; + break; + #endif + } + + // setup configuration + + // data bits @ CR1:M1&M0 + // TODO + + // parity @ CR1:PS + // TODO + + // stop bits @ CR2:STOP1&STOP0 + // clear bits for stop bits setting + palUart->Uart_cfg.cr2 &= ~USART_CR2_STOP; + + switch ((SerialStopBitCount)pThis[ FIELD___stopBits ].NumericByRef().s4) + { + case SerialStopBitCount_One : + // already set with the above + break; + case SerialStopBitCount_OnePointFive : + palUart->Uart_cfg.cr2 |= USART_CR2_STOP_1 + USART_CR2_STOP_0; + break; + case SerialStopBitCount_Two : + palUart->Uart_cfg.cr2 |= USART_CR2_STOP_1; + break; + } + + // baud rate + palUart->Uart_cfg.speed = (int)pThis[ FIELD___baudRate ].NumericByRef().s4; + + // stop UART, better do this before changing configuration + uartStop(palUart->UartDriver); + + // get pointer to PAL UART + switch ((int)pThis[ FIELD___portIndex ].NumericByRef().s4) + { + #if NF_SERIAL_COMM_STM32_UART_USE_USART1 + case 1 : + ConfigPins_UART1(); + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART2 + case 2 : + ConfigPins_UART2(); + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART3 + case 3 : + ConfigPins_UART3(); + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART4 + case 4 : + ConfigPins_UART4(); + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART5 + case 5 : + ConfigPins_UART5(); + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART6 + case 6 : + ConfigPins_UART6(); + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART7 + case 7 : + ConfigPins_UART7(); + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART8 + case 8 : + ConfigPins_UART8(); + break; + #endif + } + + uartStart(palUart->UartDriver, &palUart->Uart_cfg); + uartStopSend(palUart->UartDriver); + uartStopReceive(palUart->UartDriver); + + // null pointers and vars + pThis = NULL; + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::NativeWrite___VOID__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + NF_PAL_UART* palUart = NULL; + + uint8_t* data; + unsigned int length = 0; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + if(pThis[ FIELD___disposed ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + // dereference the data buffer from the argument + CLR_RT_HeapBlock_Array* dataBuffer = stack.Arg1().DereferenceArray(); + + // get a the pointer to the array by using the first element of the array + data = dataBuffer->GetFirstElement(); + + // get the size of the buffer + length = dataBuffer->m_numOfElements; + + // get pointer to PAL UART + switch ((int)pThis[ FIELD___portIndex ].NumericByRef().s4) + { + #if NF_SERIAL_COMM_STM32_UART_USE_USART1 + case 1 : + palUart = &Uart1_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART2 + case 2 : + palUart = &Uart2_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART3 + case 3 : + palUart = &Uart3_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART4 + case 4 : + palUart = &Uart4_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART5 + case 5 : + palUart = &Uart5_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART6 + case 6 : + palUart = &Uart6_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART7 + case 7 : + palUart = &Uart7_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART8 + case 8 : + palUart = &Uart8_PAL; + break; + #endif + } + + // check if there is enough room in the buffer + if(palUart->TxRingBuffer.Capacity() - palUart->TxRingBuffer.Length() < length) + { + // not enough room in the buffer + NANOCLR_SET_AND_LEAVE(CLR_E_BUFFER_TOO_SMALL); + } + + // push data to buffer + size_t bytesWritten = palUart->TxRingBuffer.Push(data, length); + + // check if all requested bytes were written + if(bytesWritten != length) + { + // not sure if this is the best exception to throw here... + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + + // need to update the _unstoredBufferLength field in the SerialDeviceOutputStream + // get pointer to outputStream field + CLR_RT_HeapBlock* outputStream = pThis[Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::FIELD___outputStream].Dereference(); + // get pointer to _unstoredBufferLength field and udpate field value + outputStream[Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDeviceOutputStream::FIELD___unstoredBufferLength].NumericByRef().s4 = palUart->TxRingBuffer.Length(); + + // null pointers and vars + pThis = NULL; + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::NativeStore___U4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NF_PAL_UART* palUart = NULL; + + size_t length = 0; + + CLR_RT_HeapBlock* writeTimeout; + int64_t* timeoutTicks; + bool eventResult = true; + bool txOk = false; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + if(pThis[ FIELD___disposed ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + // Choose the driver for this SerialDevice + switch ((int)pThis[ FIELD___portIndex ].NumericByRef().s4) + { +#if NF_SERIAL_COMM_STM32_UART_USE_USART1 + case 1 : + palUart = &Uart1_PAL; + break; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_USART2 + case 2 : + palUart = &Uart2_PAL; + break; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_USART3 + case 3 : + palUart = &Uart3_PAL; + break; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_UART4 + case 4 : + palUart = &Uart4_PAL; + break; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_UART5 + case 5 : + palUart = &Uart5_PAL; + break; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_USART6 + case 6 : + palUart = &Uart6_PAL; + break; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_UART7 + case 7 : + palUart = &Uart7_PAL; + break; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_UART8 + case 8 : + palUart = &Uart8_PAL; + break; +#endif + } + + // get value for _readtimeout field (pointer!) + writeTimeout = &pThis[ Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::FIELD___writeTimeout ]; + + // setup timeout + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks(*writeTimeout, timeoutTicks)); + + // push dummy length value onto the eval stack + // this is going to be used to store how many bytes where buffered to Tx + if(stack.m_customState == 1) + { + stack.PushValueI4(0); + + // bump custom state so the read value above is pushed only once + stack.m_customState = 2; + } + + // check if there is anything the buffer + if(palUart->TxRingBuffer.Length() > 0) + { + // check if there is a TX operation ongoing + if(palUart->TxOngoingCount == 0) + { + // OK to Tx + txOk = true; + } + else + { + // need to wait for the ongoing operation to complete before starting a new one + } + } + + if(txOk) + { + // optimize buffer for sequential reading + palUart->TxRingBuffer.OptimizeSequence(); + + // get data length available in the buffer + length = palUart->TxRingBuffer.Length(); + + // push to the stack how many bytes bytes where buffered for Tx + stack.m_evalStack[1].NumericByRef().s4 = length; + + // flush DMA buffer to ensure cache coherency + // (only required for Cortex-M7) + cacheBufferFlush(palUart->TxRingBuffer.Reader(), length); + + // set TX ongoing count + palUart->TxOngoingCount = length; + + // because the UART can be accessed from several threads need to get exclusive access to it + uartAcquireBus(palUart->UartDriver); + + // start sending data (DMA will read from the ring buffer) + uartStartSend(palUart->UartDriver, length, (uint8_t*)palUart->TxRingBuffer.Reader()); + } + + while(eventResult) + { + // non-blocking wait allowing other threads to run while we wait for the Tx operation to complete + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeoutTicks, CLR_RT_ExecutionEngine::c_Event_SerialPortOut, eventResult )); + + // done here, release the UART + uartReleaseBus(palUart->UartDriver); + + if(eventResult) + { + // event occurred + // get from the eval stack how many bytes were buffered to Tx + length = stack.m_evalStack[1].NumericByRef().s4; + + // done here + break; + } + else + { + NANOCLR_SET_AND_LEAVE( CLR_E_TIMEOUT ); + } + } + + // pop length heap block from stack + stack.PopValue(); + + // pop timeout heap block from stack + stack.PopValue(); + + stack.SetResult_U4(length); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::NativeRead___U4__SZARRAY_U1__I4__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* dataBuffer; + NF_PAL_UART* palUart = NULL; + + uint8_t* data; + size_t dataLength = 0; + + size_t count = 0; + size_t bytesRead = 0; + size_t bytesToRead = 0; + + InputStreamOptions options = InputStreamOptions_None; + + CLR_RT_HeapBlock* readTimeout; + int64_t* timeoutTicks; + bool eventResult = true; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); if(!(pThis)) FAULT_ON_NULL(pThis); + + if(pThis[ FIELD___disposed ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + // dereference the data buffer from the argument + dataBuffer = stack.Arg1().DereferenceArray(); + + // get a the pointer to the array by using the first element of the array + data = dataBuffer->GetFirstElement(); + + // get the length of the data buffer + dataLength = dataBuffer->m_numOfElements; + + // get how many bytes are requested to read + count = stack.Arg2().NumericByRef().s4; + + // get the InputStreamOptions option + options = (InputStreamOptions)stack.Arg3().NumericByRef().s4; + + // Choose the driver for this SerialDevice + switch ((int)pThis[ FIELD___portIndex ].NumericByRef().s4) + { +#if NF_SERIAL_COMM_STM32_UART_USE_USART1 + case 1 : + palUart = &Uart1_PAL; + break; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_USART2 + case 2 : + palUart = &Uart2_PAL; + break; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_USART3 + case 3 : + palUart = &Uart3_PAL; + break; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_UART4 + case 4 : + palUart = &Uart4_PAL; + break; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_UART5 + case 5 : + palUart = &Uart5_PAL; + break; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_USART6 + case 6 : + palUart = &Uart6_PAL; + break; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_UART7 + case 7 : + palUart = &Uart7_PAL; + break; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_UART8 + case 8 : + palUart = &Uart8_PAL; + break; +#endif + } + + // get value for _readtimeout field (pointer!) + readTimeout = &pThis[ Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::FIELD___readTimeout ]; + + // setup timeout from the _readtimeout heap block + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks( *readTimeout, timeoutTicks )); + + // figure out what's available in the Rx ring buffer + if(palUart->RxRingBuffer.Length() >= count) + { + // read from Rx ring buffer + bytesToRead = count; + + // is the read ahead option enabled? + if(options == InputStreamOptions_ReadAhead) + { + // yes + // check how many bytes we can store in the buffer argument + if(dataLength < palUart->RxRingBuffer.Length()) + { + // read as many bytes has the buffer can hold + bytesToRead = dataLength; + } + else + { + // read everything that's available in the ring buffer + bytesToRead = palUart->RxRingBuffer.Length(); + } + } + + // we have enough bytes, skip wait for event + eventResult = false; + + // clear event by getting it + Events_Get(SYSTEM_EVENT_FLAG_COM_IN); + } + else + { + if(stack.m_customState == 1) + { + // not enough bytes available, have to read from UART + palUart->RxBytesToRead = count; + + // clear event by getting it + Events_Get(SYSTEM_EVENT_FLAG_COM_IN); + + // don't read anything from the buffer yet + bytesToRead = 0; + } + } + + while(eventResult) + { + if(stack.m_customState == 1) + { + if(bytesToRead > 0) + { + // enough bytes available + eventResult = false; + } + else + { + // need to read from the UART + // update custom state + stack.m_customState = 2; + } + } + else + { + // wait for event + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents(stack.m_owningThread, *timeoutTicks, CLR_RT_ExecutionEngine::c_Event_SerialPortIn, eventResult)); + + if(!eventResult) + { + // event timeout + + // compute how many bytes to read + // considering the InputStreamOptions read ahead option + if(options == InputStreamOptions_ReadAhead) + { + // yes + // check how many bytes we can store in the buffer argument + if(dataLength < palUart->RxRingBuffer.Length()) + { + // read as many bytes has the buffer can hold + bytesToRead = dataLength; + } + else + { + // read everything that's available in the ring buffer + bytesToRead = palUart->RxRingBuffer.Length(); + } + } + else + { + // take InputStreamOptions_Partial as default and read requested quantity or what's available + bytesToRead = count; + + if(count > palUart->RxRingBuffer.Length()) + { + // need to adjust because there aren't enough bytes available + bytesToRead = palUart->RxRingBuffer.Length(); + } + } + } + } + } + + if(bytesToRead > 0) + { + // pop the requested bytes from the ring buffer + bytesRead = palUart->RxRingBuffer.Pop(data, bytesToRead); + } + + // pop timeout heap block from stack + stack.PopValue(); + + // return how many bytes were read + stack.SetResult_U4(bytesRead); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::NativeSetWatchChar___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + NF_PAL_UART* palUart; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Choose the driver for this SerialDevice + switch ((int)pThis[ FIELD___portIndex ].NumericByRef().s4) + { + #if NF_SERIAL_COMM_STM32_UART_USE_USART1 + case 1 : + palUart = &Uart1_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART2 + case 2 : + palUart = &Uart2_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART3 + case 3 : + palUart = &Uart3_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART4 + case 4 : + palUart = &Uart4_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART5 + case 5 : + palUart = &Uart5_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART6 + case 6 : + palUart = &Uart6_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART7 + case 7 : + palUart = &Uart7_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART8 + case 8 : + palUart = &Uart8_PAL; + break; + #endif + default: + // this COM port is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // set watch char + palUart->WatchChar = (uint8_t)pThis[ FIELD___watchChar ].NumericByRef().u1; + + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::get_BytesToRead___U4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + NF_PAL_UART* palUart; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Choose the driver for this SerialDevice + switch ((int)pThis[ FIELD___portIndex ].NumericByRef().s4) + { + #if NF_SERIAL_COMM_STM32_UART_USE_USART1 + case 1 : + palUart = &Uart1_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART2 + case 2 : + palUart = &Uart2_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART3 + case 3 : + palUart = &Uart3_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART4 + case 4 : + palUart = &Uart4_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART5 + case 5 : + palUart = &Uart5_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART6 + case 6 : + palUart = &Uart6_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART7 + case 7 : + palUart = &Uart7_PAL; + break; + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART8 + case 8 : + palUart = &Uart8_PAL; + break; + #endif + default: + // this COM port is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // get length of Rx ring buffer + stack.SetResult_U4(palUart->RxRingBuffer.Length()); + + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::GetDeviceSelector___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // declare the device selector string whose max size is "COM1,COM2,COM3,COM4,COM5,COM6,COM7,COM8," + terminator and init with the terminator + char deviceSelectorString[ 40 + 1] = { 0 }; + + #if NF_SERIAL_COMM_STM32_UART_USE_USART1 + strcat(deviceSelectorString, "COM1,"); + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART2 + strcat(deviceSelectorString, "COM2,"); + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART3 + strcat(deviceSelectorString, "COM3,"); + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART4 + strcat(deviceSelectorString, "COM4,"); + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART5 + strcat(deviceSelectorString, "COM5,"); + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART6 + strcat(deviceSelectorString, "COM6,"); + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART7 + strcat(deviceSelectorString, "COM7,"); + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART8 + strcat(deviceSelectorString, "COM8,"); + #endif + + // replace the last comma with a terminator + deviceSelectorString[hal_strlen_s(deviceSelectorString) - 1] = '\0'; + + // because the caller is expecting a result to be returned + // we need set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + stack.SetResult_String(deviceSelectorString); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.SerialCommunication/win_dev_serial_native_target.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.SerialCommunication/win_dev_serial_native_target.h new file mode 100644 index 00000000..57f70acc --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.SerialCommunication/win_dev_serial_native_target.h @@ -0,0 +1,182 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIN_DEV_SERIAL_NATIVE_TARGET_H_ +#define _WIN_DEV_SERIAL_NATIVE_TARGET_H_ + +#include +#include +#include + +// struct representing the UART +struct NF_PAL_UART +{ + UARTDriver* UartDriver; + UARTConfig Uart_cfg; + + HAL_RingBuffer TxRingBuffer; + uint8_t* TxBuffer; + uint16_t TxOngoingCount; + + HAL_RingBuffer RxRingBuffer; + uint8_t* RxBuffer; + uint16_t RxBytesToRead; + + uint8_t WatchChar; +}; + + +//////////////////////////////////////////// +// declaration of the the UART PAL strucs // +//////////////////////////////////////////// +#if NF_SERIAL_COMM_STM32_UART_USE_USART1 + extern NF_PAL_UART Uart1_PAL; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_USART2 + extern NF_PAL_UART Uart2_PAL; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_USART3 + extern NF_PAL_UART Uart3_PAL; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_UART4 + extern NF_PAL_UART Uart4_PAL; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_UART5 + extern NF_PAL_UART Uart5_PAL; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_USART6 + extern NF_PAL_UART Uart6_PAL; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_UART7 + extern NF_PAL_UART Uart7_PAL; +#endif +#if NF_SERIAL_COMM_STM32_UART_USE_UART8 + extern NF_PAL_UART Uart8_PAL; +#endif + +// the following macro defines a function that configures the GPIO pins for a STM32 UART/USART +// it gets called in the Windows_Devices_SerialCommunication_SerialDevice::NativeConfig function +// this is required because the UART/USART peripherals can use multiple GPIO configuration combinations +#define UART_CONFIG_PINS(num, gpio_port_tx, gpio_port_rx, tx_pin, rx_pin, alternate_function) void ConfigPins_UART##num() { \ + palSetPadMode(gpio_port_tx, tx_pin, PAL_MODE_ALTERNATE(alternate_function)); \ + palSetPadMode(gpio_port_rx, rx_pin, PAL_MODE_ALTERNATE(alternate_function)); \ + } + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// when a UART/USART is defined the declarations below will have the real function/configuration +// in the target folder @ target_windows_devices_serialcommunication_config.cpp +/////////////////////////////////////////////////////////////////////////////////////////////////// +void ConfigPins_UART1(); +void ConfigPins_UART2(); +void ConfigPins_UART3(); +void ConfigPins_UART4(); +void ConfigPins_UART5(); +void ConfigPins_UART6(); +void ConfigPins_UART7(); +void ConfigPins_UART8(); + + +///////////////////////////////////// +// UART Tx buffers // +// these live in the target folder // +///////////////////////////////////// +extern uint8_t Uart1_TxBuffer[]; +extern uint8_t Uart2_TxBuffer[]; +extern uint8_t Uart3_TxBuffer[]; +extern uint8_t Uart4_TxBuffer[]; +extern uint8_t Uart5_TxBuffer[]; +extern uint8_t Uart6_TxBuffer[]; +extern uint8_t Uart7_TxBuffer[]; +extern uint8_t Uart8_TxBuffer[]; + + +///////////////////////////////////// +// UART Rx buffers // +// these live in the target folder // +///////////////////////////////////// +extern uint8_t Uart1_RxBuffer[]; +extern uint8_t Uart2_RxBuffer[]; +extern uint8_t Uart3_RxBuffer[]; +extern uint8_t Uart4_RxBuffer[]; +extern uint8_t Uart5_RxBuffer[]; +extern uint8_t Uart6_RxBuffer[]; +extern uint8_t Uart7_RxBuffer[]; +extern uint8_t Uart8_RxBuffer[]; + + +// the following macro defines a function that initializes an UART struct +// it gets called in the Windows_Devices_SerialCommunication_SerialDevice::NativeInit function + +#if defined(STM32F7XX) || defined(STM32F0XX) + +// STM32F7 and STM32F0 use UART driver v2 +#define UART_INIT(num, tx_buffer_size, rx_buffer_size) void Init_UART##num() { \ + Uart##num##_PAL.Uart_cfg.txend2_cb = NULL; \ + Uart##num##_PAL.Uart_cfg.rxend_cb = NULL; \ + Uart##num##_PAL.Uart_cfg.rxerr_cb = NULL; \ + Uart##num##_PAL.Uart_cfg.timeout_cb = NULL; \ + Uart##num##_PAL.Uart_cfg.timeout = 0; \ + Uart##num##_PAL.Uart_cfg.speed = 9600; \ + Uart##num##_PAL.Uart_cfg.cr1 = 0; \ + Uart##num##_PAL.Uart_cfg.cr2 = 0; \ + Uart##num##_PAL.Uart_cfg.cr3 = 0; \ + Uart##num##_PAL.TxBuffer = Uart##num##_TxBuffer; \ + Uart##num##_PAL.TxRingBuffer.Initialize( Uart##num##_PAL.TxBuffer, tx_buffer_size); \ + Uart##num##_PAL.TxOngoingCount = 0; \ + Uart##num##_PAL.RxBuffer = Uart##num##_RxBuffer; \ + Uart##num##_PAL.RxRingBuffer.Initialize( Uart##num##_PAL.RxBuffer, rx_buffer_size); \ + Uart##num##_PAL.WatchChar = 0; \ +} + +#else + +// all other STM32F use UART driver v1 which has a different UARTConfig struct +#define UART_INIT(num, tx_buffer_size, rx_buffer_size) void Init_UART##num() { \ + Uart##num##_PAL.Uart_cfg.txend2_cb = NULL; \ + Uart##num##_PAL.Uart_cfg.rxend_cb = NULL; \ + Uart##num##_PAL.Uart_cfg.rxerr_cb = NULL; \ + Uart##num##_PAL.Uart_cfg.speed = 9600; \ + Uart##num##_PAL.Uart_cfg.cr1 = 0; \ + Uart##num##_PAL.Uart_cfg.cr2 = 0; \ + Uart##num##_PAL.Uart_cfg.cr3 = 0; \ + Uart##num##_PAL.TxBuffer = Uart##num##_TxBuffer; \ + Uart##num##_PAL.TxRingBuffer.Initialize( Uart##num##_PAL.TxBuffer, tx_buffer_size); \ + Uart##num##_PAL.TxOngoingCount = 0; \ + Uart##num##_PAL.RxBuffer = Uart##num##_RxBuffer; \ + Uart##num##_PAL.RxRingBuffer.Initialize( Uart##num##_PAL.RxBuffer, rx_buffer_size); \ + Uart##num##_PAL.WatchChar = 0; \ +} + +#endif + + +// when a UART/USART is defined the declarations below will have the real function/configuration +// in the target folder @ target_windows_devices_serialcommunication_config.cpp +void Init_UART1(); +void Init_UART2(); +void Init_UART3(); +void Init_UART4(); +void Init_UART5(); +void Init_UART6(); +void Init_UART7(); +void Init_UART8(); + + +// the following macro defines a function that un initializes an UART struct +// it gets called in the Windows_Devices_SerialCommunication_SerialDevice::NativeDispose function +#define UART_UNINIT(num) void UnInit_UART##num() { return; } + +// when a UART/USART is defined the declarations below will have the real function/configuration +// in the target folder @ target_windows_devices_serialcommunication_config.cpp +void UnInit_UART1(); +void UnInit_UART2(); +void UnInit_UART3(); +void UnInit_UART4(); +void UnInit_UART5(); +void UnInit_UART6(); +void UnInit_UART7(); +void UnInit_UART8(); + +#endif //_WIN_DEV_SERIAL_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo.cpp new file mode 100644 index 00000000..3f777bf7 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo.cpp @@ -0,0 +1,43 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#include "win_dev_spi_native_target.h" + + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo::get_MaxClockFrequency___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pArg = &(stack.Arg1()); + + // spiBus is an ASCII string with the bus name in format 'SPIn' + // need to grab 'n' from the string and convert to the integer value from the ASCII code + uint8_t bus = (uint8_t)pArg[0].RecoverString()[3] - 48; + + // According to STM : "At a minimum, the clock frequency should be twice the required communication frequency." + // So maximum useable frequency is CoreClock / 2. + // SPI2 or SPI3 are on APB1, so divide max frequency by four. + stack.SetResult_I4 ((bus == 2 or bus == 3) ? SystemCoreClock >>= 2 : SystemCoreClock >> 1); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo::get_MinClockFrequency___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pArg = &(stack.Arg1()); + + // spiBus is an ASCII string with the bus name in format 'SPIn' + // need to grab 'n' from the string and convert to the integer value from the ASCII code + uint8_t bus = (uint8_t)pArg[0].RecoverString()[3] - 48; + + // Max prescaler value = 256 + // SPI2 or SPI3 are on APB1, so divide max frequency by four. + stack.SetResult_I4 ((bus == 2 or bus == 3) ? SystemCoreClock >>= 9 : SystemCoreClock >> 8); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiController.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiController.cpp new file mode 100644 index 00000000..17e41c97 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiController.cpp @@ -0,0 +1,44 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#include "win_dev_spi_native_target.h" + + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiController::GetDeviceSelector___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // declare the device selector string whose max size is "SPI1,SPI2,SPI3,SPI4,SPI5,SPI6," + terminator and init with the terminator + char deviceSelectorString[ 30 + 1] = { 0 }; + + #if STM32_SPI_USE_SPI1 + strcat(deviceSelectorString, "SPI1,"); + #endif + #if STM32_SPI_USE_SPI2 + strcat(deviceSelectorString, "SPI2,"); + #endif + #if STM32_SPI_USE_SPI3 + strcat(deviceSelectorString, "SPI3,"); + #endif + #if STM32_SPI_USE_SPI4 + strcat(deviceSelectorString, "SPI4,"); + #endif + #if STM32_SPI_USE_SPI5 + strcat(deviceSelectorString, "SPI5,"); + #endif + #if STM32_SPI_USE_SPI6 + strcat(deviceSelectorString, "SPI6,"); + #endif + + // replace the last comma with a terminator + deviceSelectorString[hal_strlen_s(deviceSelectorString) - 1] = '\0'; + + // because the caller is expecting a result to be returned + // we need set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + stack.SetResult_String(deviceSelectorString); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiDevice.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiDevice.cpp new file mode 100644 index 00000000..ebfe4d4a --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiDevice.cpp @@ -0,0 +1,812 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#include +#include +#include +#include +#include +#include +#include "win_dev_spi_native_target.h" + + +// define this type here to make it shorter and improve code readability +typedef Library_win_dev_spi_native_Windows_Devices_Spi_SpiConnectionSettings SpiConnectionSettings; + + +///////////////////////////////////////////////////// +// SPI PAL strucs declared in win_dev_spi_native.h // +///////////////////////////////////////////////////// +#if STM32_SPI_USE_SPI1 +NF_PAL_SPI SPI1_PAL; +#endif +#if STM32_SPI_USE_SPI2 +NF_PAL_SPI SPI2_PAL; +#endif +#if STM32_SPI_USE_SPI3 +NF_PAL_SPI SPI3_PAL; +#endif +#if STM32_SPI_USE_SPI4 +NF_PAL_SPI SPI4_PAL; +#endif +#if STM32_SPI_USE_SPI5 +NF_PAL_SPI SPI5_PAL; +#endif +#if STM32_SPI_USE_SPI6 +NF_PAL_SPI SPI6_PAL; +#endif + +static void SpiCallback(SPIDriver *spip) +{ + (void)spip; + + NATIVE_INTERRUPT_START + + NF_PAL_SPI* palSpi = NULL; + + #if STM32_SPI_USE_SPI1 + if (spip == &SPID1) + { + palSpi = &SPI1_PAL; + } + #endif + #if STM32_SPI_USE_SPI2 + if (spip == &SPID2) + { + palSpi = &SPI2_PAL; + } + #endif + #if STM32_SPI_USE_SPI3 + if (spip == &SPID3) + { + palSpi = &SPI3_PAL; + } + #endif + #if STM32_SPI_USE_SPI4 + if (spip == &SPID4) + { + palSpi = &SPI4_PAL; + } + #endif + #if STM32_SPI_USE_SPI5 + if (spip == &SPID5) + { + palSpi = &SPI5_PAL; + } + #endif + #if STM32_SPI_USE_SPI6 + if (spip == &SPID6) + { + palSpi = &SPI6_PAL; + } + #endif + + // check if there is any Rx operation due + if(palSpi->SequentialTxRx) + { + // yes there is! + // clear flag and... + palSpi->SequentialTxRx = false; + + // ... start it + spiStartReceive(palSpi->Driver, palSpi->ReadSize, palSpi->ReadBuffer); + } + else + { + // all done here! + + spiUnselect(palSpi->Driver); + + // fire event for SPI transaction complete + Events_Set( SYSTEM_EVENT_FLAG_SPI_MASTER ); + } + + NATIVE_INTERRUPT_END +}; + +// Computes the SPI peripheral baud rate according to the requested frequency +uint16_t ComputeBaudRate(uint8_t busIndex, int32_t requestedFrequency, int32_t& actualFrequency) +{ + uint16_t divider = 0; + int32_t maxSpiFrequency; + + #if defined(STM32L0XX) + + // SP1 is feed by APB2 (STM32_PCLK2) + actualFrequency = STM32_PCLK2; + + // SPI2 is feed by APB1 (STM32_PCLK1) + if (busIndex == 1) + { + actualFrequency = STM32_PCLK1; + } + + // from datasheet + maxSpiFrequency = 12000000; + + #elif defined(STM32F0XX) + + (void)busIndex; + + // STM32F0 SPI is always feed by APB1 + actualFrequency = STM32_PCLK1; + + // from datasheet + maxSpiFrequency = 18000000; + + #elif defined(STM32F4XX) || defined(STM32F7XX) + + // SP1, SPI4, SPI5 and SPI6 are feed by APB2 (STM32_PCLK2) + actualFrequency = STM32_PCLK2; + + // SPI2 and SPI3 are feed by APB1 (STM32_PCLK1) + if (busIndex == 2 || busIndex == 3) + { + actualFrequency = STM32_PCLK1; + } + + // this is not really accurate because there are different max SPI clocks depending on which APB clock source if feeding the SPI + // because ChibiOS doesn't offer that we have to go with minimum common denominator + maxSpiFrequency = STM32_SPII2S_MAX; + + #elif defined(STM32H7XX) + + // SP1, SPI4, SPI5 and SPI6 are feed by APB2 (STM32_PCLK2) + actualFrequency = STM32_PCLK2; + maxSpiFrequency = STM32_SPI456_MAX; + + // SPI1, SPI2 and SPI3 are feed by APB1 (STM32_PCLK1) + if (busIndex == 2 || busIndex == 3) + { + actualFrequency = STM32_PCLK1; + maxSpiFrequency = STM32_SPI123_MAX; + } + + #else + + #error "Error setting max SPI frequency. Check if the target series is defined." + + #endif + + + // when requested frequency is 0, means that the developer hasn't set ClockFrequency in SpiConnectionSettings + // default to the max possible SPI frequency + if(requestedFrequency == 0) + { + requestedFrequency = maxSpiFrequency; + } + + for( ; divider < 8; divider++) + { + actualFrequency = actualFrequency / 2; + + if(actualFrequency <= requestedFrequency) + { + // best match for the requested frequency + // just check if it's below the max SPI frequency + if(actualFrequency <= maxSpiFrequency) + { + // we are good with this value + break; + } + } + } + + // the baud rate bits are in the position B5:3 so need to left shit the divider value + return divider << 3; +} + +// Give a complete low-level SPI configuration from user's managed connectionSettings +void GetSPIConfig(int busIndex, CLR_RT_HeapBlock* config, SPIConfig* llConfig, bool bufferIs16bits) +{ + int32_t actualFrequency; + + // clear values + llConfig->cr1 = 0; + llConfig->cr2 = 0; + + // get chip select pin + int csPin = config[ SpiConnectionSettings::FIELD___csLine ].NumericByRef().s4; + + // SPI mode + switch (config[ SpiConnectionSettings::FIELD___spiMode ].NumericByRef().s4) + { + case SpiModes_Mode1: + llConfig->cr1 |= SPI_CR1_CPHA; + break; + + case SpiModes_Mode2: + llConfig->cr1 |= SPI_CR1_CPOL; + break; + + case SpiModes_Mode3: + llConfig->cr1 |= SPI_CR1_CPHA | SPI_CR1_CPOL; + break; + + default: // Default to Mode0 if invalid mode specified + break; + } + + // compute baud rate of SPI peripheral according to the requested frequency + llConfig->cr1 |= ComputeBaudRate(busIndex, config[ SpiConnectionSettings::FIELD___clockFrequency ].NumericByRef().s4, (int32_t&)actualFrequency); + + // set data transfer length according to SPI connection settings and... + // ... buffer data size. Have to use the shortest one. + if (config[ SpiConnectionSettings::FIELD___databitLength ].NumericByRef().s4 == 16) + { + // databitLength is 16bits + + if(bufferIs16bits) + { + // Set data transfer length to 16 bits + #ifdef STM32F4XX + llConfig->cr1 |= SPI_CR1_DFF; + #endif + #ifdef STM32F7XX + llConfig->cr2 = SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0; + #endif + // Sets the order of bytes transmission : MSB first or LSB first + int bitOrder = config[ SpiConnectionSettings::FIELD___bitOrder ].NumericByRef().s4; + if (bitOrder == DataBitOrder_LSB) + { + llConfig->cr1 |= SPI_CR1_LSBFIRST; + } + } + else + { + // have to force transfer length to 8bit + #ifdef STM32F4XX + llConfig->cr1 &= ~SPI_CR1_DFF; + #endif + #ifdef STM32F7XX + llConfig->cr2 = SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0; + #endif + } + } + else + { + // databitLength is 8bits + + if(bufferIs16bits) + { + // have to force transfer length to 16bit + #ifdef STM32F4XX + llConfig->cr1 |= SPI_CR1_DFF; + #endif + #ifdef STM32F7XX + llConfig->cr2 = SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0; + #endif + + } + else + { + // set transfer length to 8bits + #ifdef STM32F4XX + llConfig->cr1 &= ~SPI_CR1_DFF; + #endif + #ifdef STM32F7XX + llConfig->cr2 |= SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0; + #endif + } + } + + // Create the low level configuration + #if (SPI_SUPPORTS_CIRCULAR == TRUE) + llConfig->circular = SPI_USE_CIRCULAR; + #endif + llConfig->end_cb = SpiCallback; + llConfig->ssport = GPIO_PORT(csPin); + llConfig->sspad = csPin % 16; +} + +// estimate the time required to perform the SPI transaction +bool IsLongRunningOperation(uint32_t writeSize, uint32_t readSize, bool bufferIs16bits, float byteTime, uint32_t& estimatedDurationMiliseconds) +{ + if(bufferIs16bits) + { + // double the buffers size + writeSize = 2 * writeSize; + readSize = 2 * readSize; + } + + estimatedDurationMiliseconds = byteTime * (writeSize + readSize); + + if(estimatedDurationMiliseconds > CLR_RT_Thread::c_TimeQuantum_Milliseconds) + { + // total operation time will exceed thread quantum, so this is a long running operation + return true; + } + else + { + return false; + } +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer___VOID__SZARRAY_U1__SZARRAY_U1__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + return NativeTransfer( stack, false ); +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer___VOID__SZARRAY_U2__SZARRAY_U2__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + return NativeTransfer( stack, true ); +} +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer( CLR_RT_StackFrame& stack, bool bufferIs16bits ) +{ + NANOCLR_HEADER(); + { + NF_PAL_SPI* palSpi = NULL; + uint8_t busIndex; + bool fullDuplex; + bool isLongRunningOperation = false; + + CLR_RT_HeapBlock hbTimeout; + CLR_INT64* timeout; + bool eventResult = true; + uint32_t estimatedDurationMiliseconds; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the managed spi connectionSettings object instance + CLR_RT_HeapBlock* pConfig = pThis[ FIELD___connectionSettings ].Dereference(); + + // get bus index + // this is coded with a multiplication, need to perform and int division to get the number + // see the comments in the SpiDevice() constructor in managed code for details + busIndex = (uint8_t)(pThis[ FIELD___deviceId ].NumericByRef().s4 / 1000); + + // get the PAL struct for the SPI bus + switch (busIndex) + { + #if STM32_SPI_USE_SPI1 + case 1: + palSpi = &SPI1_PAL; + break; + #endif + #if STM32_SPI_USE_SPI2 + case 2: + palSpi = &SPI2_PAL; + break; + #endif + #if STM32_SPI_USE_SPI3 + case 3: + palSpi = &SPI3_PAL; + break; + #endif + #if STM32_SPI_USE_SPI4 + case 4: + palSpi = &SPI4_PAL; + break; + #endif + #if STM32_SPI_USE_SPI5 + case 5: + palSpi = &SPI5_PAL; + break; + #endif + #if STM32_SPI_USE_SPI6 + case 6: + palSpi = &SPI6_PAL; + break; + #endif + default: + // the requested SPI bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // Are we using SPI full-duplex for transfer? + fullDuplex = (bool)stack.Arg3().NumericByRef().u1; + + // dereference the write and read buffers from the arguments + CLR_RT_HeapBlock_Array* writeBuffer = stack.Arg1().DereferenceArray(); + if (writeBuffer != NULL) + { + // get the size of the buffer by reading the number of elements in the CLR_RT_HeapBlock_Array + palSpi->WriteSize = writeBuffer->m_numOfElements; + } + + CLR_RT_HeapBlock_Array* readBuffer = stack.Arg2().DereferenceArray(); + if (readBuffer != NULL) + { + // get the size of the buffer by reading the number of elements in the CLR_RT_HeapBlock_Array + palSpi->ReadSize = readBuffer->m_numOfElements; + } + + // check if this is a long running operation + isLongRunningOperation = IsLongRunningOperation(palSpi->WriteSize, palSpi->ReadSize, bufferIs16bits, palSpi->ByteTime, (uint32_t&)estimatedDurationMiliseconds); + + if(isLongRunningOperation) + { + // if this is a long running operation, set a timeout equal to the estimated transaction duration in milliseconds + // this value has to be in ticks to be properly loaded by SetupTimeoutFromTicks() below + hbTimeout.SetInteger((CLR_INT64)estimatedDurationMiliseconds * TIME_CONVERSION__TO_MILLISECONDS); + + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks( hbTimeout, timeout )); + + // protect the buffers from GC so DMA can find them where they are supposed to be + CLR_RT_ProtectFromGC gcWriteBuffer( *writeBuffer ); + CLR_RT_ProtectFromGC gcReadBuffer( *readBuffer ); + } + + // setup the operation and init buffers + if(!isLongRunningOperation || stack.m_customState == 1) + { + // get the LL SPI configuration, depending on user's managed parameters and buffer element size + GetSPIConfig(busIndex, pConfig, &palSpi->Configuration, bufferIs16bits); + + // if this is not a long run operation we'll be using the async API thus operations are sequencial + // need to remove the callback from the SPI LL config + if(!isLongRunningOperation) + { + palSpi->Configuration.end_cb = NULL; + } + + if (writeBuffer != NULL) + { + // set DMA write buffer + if(bufferIs16bits) + { + // buffer data width is 16bits + // get the pointer to the write buffer as UINT16 because it's really an UINT16 (2 bytes) + palSpi->WriteBuffer = (uint8_t*)writeBuffer->GetFirstElementUInt16(); + + // flush DMA buffer to ensure cache coherency + // (only required for Cortex-M7) + cacheBufferFlush(palSpi->WriteBuffer, (palSpi->WriteSize * 2)); + } + else + { + // buffer data width is 8bits + // get the pointer to the write buffer as BYTE + palSpi->WriteBuffer = (uint8_t*)writeBuffer->GetFirstElement(); + + // flush DMA buffer to ensure cache coherency + // (only required for Cortex-M7) + cacheBufferFlush(palSpi->WriteBuffer, palSpi->WriteSize); + } + } + + if (readBuffer != NULL) + { + // set DMA read buffer + if(palSpi->ReadSize > 0) + { + if(bufferIs16bits) + { + // buffer data width is 16bits + palSpi->ReadBuffer = (uint8_t*)readBuffer->GetFirstElementUInt16(); + } + else + { + // buffer data width is 8bits + // get the pointer to the read buffer as BYTE + palSpi->ReadBuffer = (uint8_t*)readBuffer->GetFirstElement(); + } + } + } + + // because the bus access is shared, acquire and select the appropriate bus + spiAcquireBus(palSpi->Driver); + spiStart(palSpi->Driver, &palSpi->Configuration); + + // just to satisfy the driver ceremony, no actual implementation for STM32 + spiSelect(palSpi->Driver); + } + + if(isLongRunningOperation) + { + // this is a long running operation and hasn't started yet + // perform SPI operation using driver's ASYNC API + if(stack.m_customState == 1) + { + if (palSpi->WriteSize != 0 && palSpi->ReadSize != 0) + { + // Transmit+Receive + if (fullDuplex) + { + // Full duplex + // single operation, clear flag + palSpi->SequentialTxRx = false; + + // Uses the largest buffer size as transfer size + spiStartExchange(palSpi->Driver, palSpi->WriteSize > palSpi->ReadSize ? palSpi->WriteSize : palSpi->ReadSize, palSpi->WriteBuffer, palSpi->ReadBuffer); + } + else + { + // flag that an Rx is required after the Tx operation completes + palSpi->SequentialTxRx = true; + + // start send operation + spiStartSend(palSpi->Driver, palSpi->WriteSize, palSpi->WriteBuffer); + // receive operation will be started in the callback after the above completes + } + } + else + { + // Transmit only or Receive only + if (palSpi->ReadSize != 0) + { + // single operation, clear flag + palSpi->SequentialTxRx = false; + + // start receive + spiStartReceive(palSpi->Driver, palSpi->ReadSize, palSpi->ReadBuffer); + } + else + { + // single operation, clear flag + palSpi->SequentialTxRx = false; + + // start send + spiStartSend(palSpi->Driver, palSpi->WriteSize, palSpi->WriteBuffer); + } + } + + // bump custom state + stack.m_customState = 2; + } + } + else + { + // this is NOT a long running operation + // perform SPI operation using driver's SYNC API + if (palSpi->WriteSize != 0 && palSpi->ReadSize != 0) + { + // Transmit+Receive + if (fullDuplex) + { + // Full duplex + // Uses the largest buffer size as transfer size + spiExchange(palSpi->Driver, palSpi->WriteSize > palSpi->ReadSize ? palSpi->WriteSize : palSpi->ReadSize, palSpi->WriteBuffer, palSpi->ReadBuffer); + } + else + { + // send operation + spiSend(palSpi->Driver, palSpi->WriteSize, palSpi->WriteBuffer); + // receive operation + spiReceive(palSpi->Driver, palSpi->ReadSize, palSpi->ReadBuffer); + } + } + else + { + // Transmit only or Receive only + if (palSpi->ReadSize != 0) + { + // receive + spiReceive(palSpi->Driver, palSpi->ReadSize, palSpi->ReadBuffer); + } + else + { + // send + spiSend(palSpi->Driver, palSpi->WriteSize, palSpi->WriteBuffer); + } + } + + // just to satisfy the driver ceremony, no actual implementation for STM32 + spiUnselect(palSpi->Driver); + + // Release the bus + spiReleaseBus(palSpi->Driver); + } + + while(eventResult) + { + if(!isLongRunningOperation) + { + // this is not a long running operation so nothing to do here + break; + } + + if(palSpi->Driver->state == SPI_READY) + { + // SPI driver is ready meaning that the SPI transaction(s) is(are) completed + break; + } + + // non-blocking wait allowing other threads to run while we wait for the Spi transaction to complete + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_SpiMaster, eventResult )); + } + + if(isLongRunningOperation) + { + // pop timeout heap block from stack + stack.PopValue(); + } + + if(eventResult) + { + spiReleaseBus(palSpi->Driver); + + // event occurred + if(palSpi->ReadSize > 0) + { + // because this was a Read transaction, need to copy from DMA buffer to managed buffer + if(bufferIs16bits) + { + // buffer data width is 16bits + + // invalidate cache over read buffer to ensure that content from DMA is read + // (only required for Cortex-M7) + // get the pointer to the read buffer as UINT16 because it's really an UINT16 (2 bytes) + cacheBufferInvalidate(palSpi->ReadBuffer, (palSpi->ReadSize * 2)); + } + else + { + // buffer data width is 8bits + + // invalidate cache over read buffer to ensure that content from DMA is read + // (only required for Cortex-M7) + // get the pointer to the read buffer as BYTE + cacheBufferInvalidate(palSpi->ReadBuffer, palSpi->ReadSize); + } + } + } + + // null pointers and vars + pThis = NULL; + pConfig = NULL; + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + NF_PAL_SPI* palSpi = NULL; + int32_t actualFrequency; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the managed spi connectionSettings object instance + CLR_RT_HeapBlock* pConfig = pThis[ FIELD___connectionSettings ].Dereference(); + + // get bus index + // this is coded with a multiplication, need to perform and int division to get the number + // see the comments in the SpiDevice() constructor in managed code for details + uint8_t busIndex = (uint8_t)(pThis[ FIELD___deviceId ].NumericByRef().s4 / 1000); + + // init the PAL struct for this SPI bus and assign the respective driver + // all this occurs if not already done + // why do we need this? because several SPIDevice objects can be created associated to the same bus + switch (busIndex) + { + #if STM32_SPI_USE_SPI1 + case 1: + if(SPI1_PAL.Driver == NULL) + { + SPI1_PAL.Driver = &SPID1; + palSpi = &SPI1_PAL; + } + break; + #endif + #if STM32_SPI_USE_SPI2 + case 2: + if(SPI2_PAL.Driver == NULL) + { + SPI2_PAL.Driver = &SPID2; + palSpi = &SPI2_PAL; + } + break; + #endif + #if STM32_SPI_USE_SPI3 + case 3: + if(SPI3_PAL.Driver == NULL) + { + SPI3_PAL.Driver = &SPID3; + palSpi = &SPI3_PAL; + } + break; + #endif + #if STM32_SPI_USE_SPI4 + case 4: + if(SPI4_PAL.Driver == NULL) + { + SPI4_PAL.Driver = &SPID4; + palSpi = &SPI4_PAL; + } + break; + #endif + #if STM32_SPI_USE_SPI5 + case 5: + if(SPI5_PAL.Driver == NULL) + { + SPI5_PAL.Driver = &SPID5; + palSpi = &SPI5_PAL; + } + break; + #endif + #if STM32_SPI_USE_SPI6 + case 6: + if(SPI6_PAL.Driver == NULL) + { + SPI6_PAL.Driver = &SPID6; + palSpi = &SPI6_PAL; + } + break; + #endif + default: + // this SPI bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // compute rough estimate on the time to tx/rx a byte (in milliseconds) + ComputeBaudRate(busIndex, pConfig[ SpiConnectionSettings::FIELD___clockFrequency ].NumericByRef().s4, (int32_t&)actualFrequency); + palSpi->ByteTime = (1.0 / actualFrequency) * 1000; + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::DisposeNative___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + uint8_t busIndex; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get bus index + // this is coded with a multiplication, need to perform and int division to get the number + // see the comments in the SpiDevice() constructor in managed code for details + busIndex = (uint8_t)(pThis[ FIELD___deviceId ].NumericByRef().s4 / 1000); + + // get the PAL struct for the SPI bus + switch (busIndex) + { + #if STM32_SPI_USE_SPI1 + case 1: + spiStop(&SPID1); + SPI1_PAL.Driver = NULL; + break; + #endif + + #if STM32_SPI_USE_SPI2 + case 2: + spiStop(&SPID2); + SPI2_PAL.Driver = NULL; + break; + #endif + + #if STM32_SPI_USE_SPI3 + case 3: + spiStop(&SPID3); + SPI3_PAL.Driver = NULL; + break; + #endif + + #if STM32_SPI_USE_SPI4 + case 4: + spiStop(&SPID4); + SPI4_PAL.Driver = NULL; + break; + #endif + + #if STM32_SPI_USE_SPI5 + case 5: + spiStop(&SPID5); + SPI5_PAL.Driver = NULL; + break; + #endif + + #if STM32_SPI_USE_SPI6 + case 6: + spiStop(&SPID6); + SPI6_PAL.Driver = NULL; + break; + #endif + + default: + // the requested SPI bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_target.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_target.h new file mode 100644 index 00000000..3176688b --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_target.h @@ -0,0 +1,50 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#ifndef _WIN_DEV_SPI_NATIVE_TARGET_H_ +#define _WIN_DEV_SPI_NATIVE_TARGET_H_ + +#include +#include + +// struct representing the SPI +struct NF_PAL_SPI +{ + SPIDriver* Driver; + SPIConfig Configuration; + float ByteTime; + bool SequentialTxRx; + + uint8_t* WriteBuffer; + uint16_t WriteSize; + + uint8_t* ReadBuffer; + uint16_t ReadSize; +}; + +/////////////////////////////////////////// +// declaration of the the SPI PAL strucs // +/////////////////////////////////////////// +#if STM32_SPI_USE_SPI1 + extern NF_PAL_SPI SPI1_PAL; +#endif +#if STM32_SPI_USE_SPI2 + extern NF_PAL_SPI SPI2_PAL; +#endif +#if STM32_SPI_USE_SPI3 + extern NF_PAL_SPI SPI3_PAL; +#endif +#if STM32_SPI_USE_SPI4 + extern NF_PAL_SPI SPI4_PAL; +#endif +#if STM32_SPI_USE_SPI5 + extern NF_PAL_SPI SPI5_PAL; +#endif +#if STM32_SPI_USE_SPI6 + extern NF_PAL_SPI SPI6_PAL; +#endif + +#endif //_WIN_DEV_SPI_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Networking.Sockets/win_net_sockets_native_Windows_Networking_Sockets_SocketNative.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Networking.Sockets/win_net_sockets_native_Windows_Networking_Sockets_SocketNative.cpp new file mode 100644 index 00000000..ceba4d66 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Networking.Sockets/win_net_sockets_native_Windows_Networking_Sockets_SocketNative.cpp @@ -0,0 +1,593 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "win_net_sockets_native_target.h" + +// TODO - Check if required, for now just ignore +#define SwapEndianIfBEc16(x) (x) + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::socket___STATIC__I4__I4__I4__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_INT32 family = stack.Arg0().NumericByRef().s4; + CLR_INT32 type = stack.Arg1().NumericByRef().s4; + CLR_INT32 protocol = stack.Arg2().NumericByRef().s4; + + CLR_INT32 nonBlocking = 1; + CLR_INT32 sock = SOCK_socket( family, type, protocol ); + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, sock )); + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, SOCK_ioctl( sock, SOCK_FIONBIO, &nonBlocking ) )); + + stack.SetResult_I4( sock ); + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::bind___STATIC__VOID__OBJECT__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + return BindConnectHelper( stack, true ); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::connect___STATIC__VOID__OBJECT__SZARRAY_U1__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + return BindConnectHelper( stack, false ); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::send___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::recv___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::close___STATIC__I4__OBJECT( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_INT32 handle, ret; + + CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); FAULT_ON_NULL(socket); + + handle = socket[ FIELD__m_Handle ].NumericByRef().s4; + + ret = SOCK_close( handle ); + + //If a socket gets closed, we need to make sure to wake up any threads that are waiting on it. + Events_Set( SYSTEM_EVENT_FLAG_SOCKET ); + + stack.SetResult_I4( ret ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::listen___STATIC__VOID__OBJECT__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); + CLR_INT32 handle; + CLR_INT32 backlog = stack.Arg1().NumericByRef().s4; + CLR_INT32 ret; + + FAULT_ON_NULL(socket); + handle = socket[ FIELD__m_Handle ].NumericByRef().s4; + + ret = SOCK_listen( handle, backlog ); + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, ret )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::accept___STATIC__I4__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); + CLR_INT32 handle; + CLR_INT32 ret; + CLR_INT32 nonBlocking = 1; + + FAULT_ON_NULL(socket); + handle = socket[ FIELD__m_Handle ].NumericByRef().s4; + + + /* Because we could have been a rescheduled call due to a prior call that would have blocked, we need to see + * if our handle has been shutdown before continuing. */ + if (handle == DISPOSED_HANDLE) + { + ThrowError(stack, CLR_E_OBJECT_DISPOSED); + NANOCLR_SET_AND_LEAVE (CLR_E_PROCESS_EXCEPTION); + } + + ret = SOCK_accept( handle, NULL, NULL ); + + if(ret != SOCK_SOCKET_ERROR) + { + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, SOCK_ioctl( ret, SOCK_FIONBIO, &nonBlocking ) )); + } + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, ret )); + + stack.SetResult_I4( ret ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::getaddrinfo___STATIC__VOID__STRING__BYREF_STRING__BYREF_SZARRAY_SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::shutdown___STATIC__VOID__OBJECT__I4__BYREF_I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::sendto___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::recvfrom___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4__BYREF_SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::getpeername___STATIC__VOID__OBJECT__BYREF_SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::getsockname___STATIC__VOID__OBJECT__BYREF_SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::getsockopt___STATIC__VOID__OBJECT__I4__I4__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::setsockopt___STATIC__VOID__OBJECT__I4__I4__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::poll___STATIC__BOOLEAN__OBJECT__I4__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::ioctl___STATIC__VOID__OBJECT__U4__BYREF_U4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + + + +//--// + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::BindConnectHelper( CLR_RT_StackFrame& stack, bool fBind ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); + CLR_INT32 handle; + SOCK_sockaddr addr; + CLR_UINT32 addrLen = sizeof(addr); + CLR_INT32 ret; + bool fThrowOnWouldBlock = false; + + FAULT_ON_NULL(socket); + handle = socket[ FIELD__m_Handle ].NumericByRef().s4; + + NANOCLR_CHECK_HRESULT(MarshalSockAddress( &addr, addrLen, stack.Arg1() )); + + if(fBind) + { + ret = SOCK_bind( handle, &addr, addrLen ); + } + else + { + ret = SOCK_connect( handle, &addr, addrLen ); + + fThrowOnWouldBlock = (stack.Arg2().NumericByRefConst().s4 != 0); + + if(!fThrowOnWouldBlock && SOCK_getlasterror() == SOCK_EWOULDBLOCK) + { + NANOCLR_SET_AND_LEAVE(S_OK); + } + } + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, ret )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::MarshalSockAddress( CLR_RT_HeapBlock& blkDst, const struct SOCK_sockaddr* addrSrc, CLR_UINT32 addrLenSrc ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* arr = NULL; + + CLR_RT_HeapBlock blkArr; blkArr.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc( blkArr ); + SOCK_sockaddr_in* dst; + SOCK_sockaddr_in* src = (SOCK_sockaddr_in*)addrSrc; + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( blkArr, addrLenSrc, g_CLR_RT_WellKnownTypes.m_UInt8 )); + + arr = blkArr.DereferenceArray(); + + _ASSERTE(arr); + + dst = (SOCK_sockaddr_in*)arr->GetFirstElement(); + + dst->sin_family = SwapEndianIfBEc16(src->sin_family); + dst->sin_port = src->sin_port; + dst->sin_addr.S_un.S_addr = src->sin_addr.S_un.S_addr; + + memcpy(dst->sin_zero, src->sin_zero, sizeof(dst->sin_zero)); + + _ASSERTE(blkDst.DataType() == DATATYPE_BYREF || blkDst.DataType() == DATATYPE_ARRAY_BYREF); + + NANOCLR_CHECK_HRESULT(blkArr.StoreToReference( blkDst, 0 )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::MarshalSockAddress( struct SOCK_sockaddr* addrDst, CLR_UINT32& addrLen, const CLR_RT_HeapBlock& blkSockAddress ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* ptrSockAddress; + SOCK_sockaddr_in* dst = (SOCK_sockaddr_in*)addrDst; + SOCK_sockaddr_in* src; + + ptrSockAddress = blkSockAddress.DereferenceArray(); + FAULT_ON_NULL(ptrSockAddress); + + if(ptrSockAddress->m_numOfElements > addrLen) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + src = (SOCK_sockaddr_in*)ptrSockAddress->GetFirstElement(); + + dst->sin_family = SwapEndianIfBEc16(src->sin_family); + dst->sin_port = src->sin_port; + dst->sin_addr.S_un.S_addr = src->sin_addr.S_un.S_addr; //already in network byte order + + memcpy(dst->sin_zero, src->sin_zero, sizeof(dst->sin_zero)); + + addrLen = ptrSockAddress->m_numOfElements; + + NANOCLR_NOCLEANUP(); +} + +// HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::SendRecvHelper( CLR_RT_StackFrame& stack, bool fSend, bool fAddress ) +// { +// NATIVE_PROFILE_CLR_NETWORK(); +// NANOCLR_HEADER(); + +// CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); +// CLR_INT32 handle; +// CLR_RT_HeapBlock_Array* arrData = stack.Arg1().DereferenceArray(); +// CLR_UINT32 offset = stack.Arg2().NumericByRef().u4; +// CLR_UINT32 count = stack.Arg3().NumericByRef().u4; +// CLR_INT32 flags = stack.Arg4().NumericByRef().s4; +// CLR_INT32 timeout_ms = stack.Arg5().NumericByRef().s4; +// CLR_RT_HeapBlock hbTimeout; + +// CLR_INT64* timeout; +// CLR_UINT8* buf; +// bool fRes = true; +// CLR_INT32 totReadWrite; +// CLR_INT32 ret = 0; + +// FAULT_ON_NULL(socket); +// FAULT_ON_NULL(arrData); + +// handle = socket[ FIELD__m_Handle ].NumericByRef().s4; + +// /* Because we could have been a rescheduled call due to a prior call that would have blocked, we need to see +// * if our handle has been shutdown before continuing. */ +// if (handle == DISPOSED_HANDLE) +// { +// ThrowError( stack, CLR_E_OBJECT_DISPOSED ); +// NANOCLR_SET_AND_LEAVE (CLR_E_PROCESS_EXCEPTION); +// } + +// if(offset + count > arrData->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_INDEX_OUT_OF_RANGE); + + +// hbTimeout.SetInteger( timeout_ms ); + +// NANOCLR_CHECK_HRESULT(stack.SetupTimeout( hbTimeout, timeout )); + +// // +// // Push "totReadWrite" onto the eval stack. +// // +// if(stack.m_customState == 1) +// { +// stack.PushValueI4( 0 ); + +// stack.m_customState = 2; +// } + +// totReadWrite = stack.m_evalStack[ 1 ].NumericByRef().s4; + +// buf = arrData->GetElement( offset + totReadWrite ); +// count -= totReadWrite; + +// while(count > 0) +// { +// CLR_INT32 bytes = 0; + +// // first make sure we have data to read or ability to write +// while(fRes) +// { +// ret = Helper__SelectSocket( handle, fSend ? 1 : 0 ); + +// if(ret != 0) break; + +// // non-blocking - allow other threads to run while we wait for handle activity +// NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_Socket, fRes )); +// } + +// // timeout expired +// if(!fRes) +// { +// ret = SOCK_SOCKET_ERROR; + +// ThrowError( stack, SOCK_ETIMEDOUT ); + +// NANOCLR_SET_AND_LEAVE( CLR_E_PROCESS_EXCEPTION ); +// } + +// // socket is in the excepted state, so let's bail out +// if(SOCK_SOCKET_ERROR == ret) +// { +// break; +// } + +// if(fAddress) +// { +// struct SOCK_sockaddr addr; +// CLR_UINT32 addrLen = sizeof(addr); +// CLR_RT_HeapBlock& blkAddr = stack.Arg6(); + +// if(fSend) +// { +// NANOCLR_CHECK_HRESULT(MarshalSockAddress( &addr, addrLen, blkAddr )); + +// bytes = SOCK_sendto( handle, (const char*)buf, count, flags, &addr, addrLen ); +// } +// else +// { +// CLR_RT_HeapBlock* pBlkAddr = blkAddr.Dereference(); + +// NANOCLR_CHECK_HRESULT(MarshalSockAddress( &addr, addrLen, *pBlkAddr )); + +// bytes = SOCK_recvfrom( handle, (char*)buf, count, flags, &addr, (int*)&addrLen ); + +// if(bytes != SOCK_SOCKET_ERROR) +// { +// NANOCLR_CHECK_HRESULT(MarshalSockAddress( blkAddr, &addr, addrLen )); +// } +// } +// } +// else +// { +// if(fSend) +// { +// bytes = SOCK_send( handle, (const char*)buf, count, flags ); +// } +// else +// { +// bytes = SOCK_recv( handle, (char*)buf, count, flags ); +// } +// } + +// // send/recv/sendto/recvfrom failed +// if(bytes == SOCK_SOCKET_ERROR) +// { +// CLR_INT32 err = SOCK_getlasterror(); + +// if(err != SOCK_EWOULDBLOCK) +// { +// ret = SOCK_SOCKET_ERROR; +// break; +// } + +// continue; +// } +// // zero recv bytes indicates the handle has been closed. +// else if(!fSend && (bytes == 0)) +// { +// break; +// } + +// buf += bytes; +// totReadWrite += bytes; +// count -= bytes; + +// stack.m_evalStack[ 1 ].NumericByRef().s4 = totReadWrite; + +// // receive returns immediately after receiving bytes. +// if(!fSend && (totReadWrite > 0)) +// { +// break; +// } + +// } + +// stack.PopValue(); // totReadWrite +// stack.PopValue(); // Timeout + +// NANOCLR_CHECK_HRESULT(ThrowOnError( stack, ret )); + +// stack.SetResult_I4( totReadWrite ); + +// NANOCLR_NOCLEANUP(); +// } + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::SockOptHelper( CLR_RT_StackFrame& stack, bool fGet ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); + CLR_INT32 handle; + CLR_INT32 level = stack.Arg1().NumericByRef().s4; + CLR_INT32 optname = stack.Arg2().NumericByRef().s4; + CLR_RT_HeapBlock_Array* arrOpt = stack.Arg3().DereferenceArray(); + char* optval; + CLR_INT32 optlen; + CLR_INT32 ret; + + FAULT_ON_NULL(socket); + handle = socket[ FIELD__m_Handle ].NumericByRef().s4; + + FAULT_ON_NULL(arrOpt); + + optval = (char*)arrOpt->GetFirstElement(); + optlen = arrOpt->m_numOfElements; + + if(fGet) + { + ret = SOCK_getsockopt( handle, level, optname, optval, &optlen ); + _ASSERTE( optlen <= (CLR_INT32)arrOpt->m_numOfElements ); + } + else + { + ret = SOCK_setsockopt( handle, level, optname, optval, optlen ); + } + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, ret )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::SockNameHelper( CLR_RT_StackFrame& stack, bool fPeer ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); + CLR_INT32 handle; + CLR_INT32 ret; + + struct SOCK_sockaddr addr; + CLR_INT32 addrLen = sizeof(addr); + + FAULT_ON_NULL(socket); + handle = socket[ FIELD__m_Handle ].NumericByRef().s4; + + if(fPeer) + { + ret = SOCK_getpeername( handle, &addr, &addrLen ); + } + else + { + ret = SOCK_getsockname( handle, &addr, &addrLen ); + } + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, ret )); + + NANOCLR_CHECK_HRESULT(MarshalSockAddress( stack.Arg1(), &addr, addrLen )); + + NANOCLR_NOCLEANUP(); +} + + + + +void Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::ThrowError( CLR_RT_StackFrame& stack, CLR_INT32 errorCode ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + // CLR_RT_HeapBlock& res = stack.m_owningThread->m_currentException; + + // if((Library_corlib_native_System_Exception::CreateInstance( res, g_CLR_RT_WellKnownTypes.m_SocketException, CLR_E_FAIL, &stack )) == S_OK) + // { + // res.Dereference()[ Library_system_sockets_System_Net_Sockets_SocketException::FIELD___errorCode ].SetInteger( errorCode ); + // } +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::ThrowOnError( CLR_RT_StackFrame& stack, CLR_INT32 res ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + if(res == SOCK_SOCKET_ERROR) + { + CLR_INT32 err = SOCK_getlasterror(); + + ThrowError( stack, err ); + + NANOCLR_SET_AND_LEAVE( CLR_E_PROCESS_EXCEPTION ); + } + + NANOCLR_NOCLEANUP(); +} \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Networking.Sockets/win_net_sockets_native_target.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Networking.Sockets/win_net_sockets_native_target.h new file mode 100644 index 00000000..90131221 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Networking.Sockets/win_net_sockets_native_target.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +//--------------------------------------------------------------------------- + +#ifndef _WIN_NET_SOCKETS_NATIVE_TARGET_H_ +#define _WIN_NET_SOCKETS_NATIVE_TARGET_H_ + +#include + +#endif //_WIN_NET_SOCKETS_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Storage/win_storage_native_Windows_Storage_Devices_SDCard.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Storage/win_storage_native_Windows_Storage_Devices_SDCard.cpp new file mode 100644 index 00000000..4c10bd7e --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Storage/win_storage_native_Windows_Storage_Devices_SDCard.cpp @@ -0,0 +1,37 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_storage_native_target.h" + +HRESULT Library_win_storage_native_Windows_Storage_Devices_SDCard::MountMMCNative___STATIC__VOID__BOOLEAN(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + (void)stack; + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_storage_native_Windows_Storage_Devices_SDCard::MountSpiNative___STATIC__VOID__I4__I4(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + (void)stack; + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + + +HRESULT Library_win_storage_native_Windows_Storage_Devices_SDCard::UnmountNative___STATIC__VOID(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + (void)stack; + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Storage/win_storage_native_Windows_Storage_FileIO.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Storage/win_storage_native_Windows_Storage_FileIO.cpp new file mode 100644 index 00000000..983b9c9b --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Storage/win_storage_native_Windows_Storage_FileIO.cpp @@ -0,0 +1,1104 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#if (HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE) +#include +#endif +#include "win_storage_native_target.h" +#include +#include + +#if (HAL_USBH_USE_MSD == TRUE) +#include "usbh/dev/msd.h" +#endif +#if (USE_SPIFFS_FOR_STORAGE == TRUE) +#include +#endif + +// defining these types here to make it shorter and improve code readability +typedef Library_win_storage_native_Windows_Storage_StorageFolder StorageFolder; +typedef Library_win_storage_native_Windows_Storage_StorageFile StorageFile; + +////////////////////////////////////////// +enum FileOperationResult +{ + FileOperationResult_OK = 0, + FileOperationResult_Error = 10, + FileOperationResult_NoFile = 20, + FileOperationResult_InvalidDrive = 30, +}; + +////////////////////////////////////////// + +struct FileOperation +{ + #if (HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE) + FIL* FatFile; + #endif + #if USE_SPIFFS_FOR_STORAGE + spiffs_file* SpiffsFile; + #endif + char* Content; + uint32_t ContentLength; +}; + +// this is the FileIO working thread +// because FatFS is supposed to be atomic we won't have any concurrent threads +static thread_t* fileIoWorkingThread; + +// ReadText working thread +static THD_FUNCTION(ReadTextWorkingThread, arg) +{ + FileOperationResult opResult = FileOperationResult_OK; + + FileOperation* fileIoOperation = (FileOperation*)arg; + + // need an extra one for the terminator + uint32_t readLength = fileIoOperation->ContentLength + 1; + + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + if(fileIoOperation->FatFile != NULL) + { + // read string + if(f_gets((TCHAR*)fileIoOperation->Content, readLength, fileIoOperation->FatFile)) + { + // operation succesfull + } + else + { + switch((FRESULT)f_error(fileIoOperation->FatFile)) + { + case FR_NO_FILE: + opResult = FileOperationResult_NoFile; + break; + + case FR_INVALID_DRIVE: + opResult = FileOperationResult_InvalidDrive; + break; + + default: + opResult = FileOperationResult_Error; + break; + } + } + + // close file + f_close(fileIoOperation->FatFile); + + // free memory + platform_free(fileIoOperation->FatFile); + + } + #endif + #if USE_SPIFFS_FOR_STORAGE + if(fileIoOperation->SpiffsFile != NULL) + { + uint32_t bytesRead = SPIFFS_read(&fs, *fileIoOperation->SpiffsFile, fileIoOperation->Content, fileIoOperation->ContentLength); + + if (bytesRead == fileIoOperation->ContentLength) + { + // expected number of bytes read + } + else + { + // failed to read expected number of bytes + opResult = FileOperationResult_Error; + } + + // close file + SPIFFS_close(&fs, *fileIoOperation->SpiffsFile); + + // free memory + platform_free(fileIoOperation->SpiffsFile); + } + #endif + + // free memory + platform_free(fileIoOperation); + + // fire event for FileIO operation complete + Events_Set(SYSTEM_EVENT_FLAG_STORAGE_IO); + + chThdExit((msg_t)opResult); +} + +// WriteText working thread +static THD_FUNCTION(WriteTextWorkingThread, arg) +{ + FileOperationResult opResult = FileOperationResult_OK; + + FileOperation* fileIoOperation = (FileOperation*)arg; + + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + if(fileIoOperation->FatFile != NULL) + { + if(f_puts(fileIoOperation->Content, fileIoOperation->FatFile) == (int)fileIoOperation->ContentLength) + { + // expected number of bytes written + } + else + { + switch((FRESULT)f_error(fileIoOperation->FatFile)) + { + case FR_NO_FILE: + opResult = FileOperationResult_NoFile; + break; + + case FR_INVALID_DRIVE: + opResult = FileOperationResult_InvalidDrive; + break; + + default: + opResult = FileOperationResult_Error; + break; + } + } + + // close file + f_close(fileIoOperation->FatFile); + + // free memory + platform_free(fileIoOperation->FatFile); + + } + #endif + #if USE_SPIFFS_FOR_STORAGE + if(fileIoOperation->SpiffsFile != NULL) + { + if (SPIFFS_write(&fs, *fileIoOperation->SpiffsFile, fileIoOperation->Content, fileIoOperation->ContentLength) < 0) + { + // failed to write expected number of bytes + opResult = FileOperationResult_Error; + } + + // close file + SPIFFS_close(&fs, *fileIoOperation->SpiffsFile); + + // free memory + platform_free(fileIoOperation->SpiffsFile); + } + #endif + + platform_free(fileIoOperation); + + // fire event for FileIO operation complete + Events_Set(SYSTEM_EVENT_FLAG_STORAGE_IO); + + chThdExit((msg_t)opResult); +} + +// WriteBinary working thread +static THD_FUNCTION(WriteBinaryWorkingThread, arg) +{ + FileOperationResult opResult = FileOperationResult_OK; + + FileOperation* fileIoOperation = (FileOperation*)arg; + + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + if(fileIoOperation->FatFile != NULL) + { + UINT bytesWritten; + + FRESULT operationResult = f_write(fileIoOperation->FatFile, fileIoOperation->Content, fileIoOperation->ContentLength, &bytesWritten); + + if( (operationResult == FR_OK) && + (bytesWritten == fileIoOperation->ContentLength)) + { + // expected number of bytes written + } + else + { + switch((FRESULT)f_error(fileIoOperation->FatFile)) + { + case FR_NO_FILE: + opResult = FileOperationResult_NoFile; + break; + + case FR_INVALID_DRIVE: + opResult = FileOperationResult_InvalidDrive; + break; + + default: + opResult = FileOperationResult_Error; + break; + } + } + + // close file + f_close(fileIoOperation->FatFile); + + // free memory + platform_free(fileIoOperation->FatFile); + + } + #endif + #if USE_SPIFFS_FOR_STORAGE + if(fileIoOperation->SpiffsFile != NULL) + { + if (SPIFFS_write(&fs, *fileIoOperation->SpiffsFile, fileIoOperation->Content, fileIoOperation->ContentLength) < 0) + { + // failed to write expected number of bytes + opResult = FileOperationResult_Error; + } + + // close file + SPIFFS_close(&fs, *fileIoOperation->SpiffsFile); + + // free memory + platform_free(fileIoOperation->SpiffsFile); + } + #endif + + // free memory + platform_free(fileIoOperation); + + // fire event for FileIO operation complete + Events_Set(SYSTEM_EVENT_FLAG_STORAGE_IO); + + chThdExit((msg_t)opResult); +} + +// ReadBinary working thread +static THD_FUNCTION(ReadBinaryWorkingThread, arg) +{ + FileOperationResult opResult = FileOperationResult_OK; + + FileOperation* fileIoOperation = (FileOperation*)arg; + + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + if(fileIoOperation->FatFile != NULL) + { + UINT bytesRead; + + FileOperation* fileIoOperation = (FileOperation*)arg; + + FRESULT operationResult = f_read(fileIoOperation->FatFile, fileIoOperation->Content, fileIoOperation->ContentLength, &bytesRead); + + if( (operationResult == FR_OK) && + (bytesRead == fileIoOperation->ContentLength)) + { + // expected number of bytes read + } + else + { + switch((FRESULT)f_error(fileIoOperation->FatFile)) + { + case FR_NO_FILE: + opResult = FileOperationResult_NoFile; + break; + + case FR_INVALID_DRIVE: + opResult = FileOperationResult_InvalidDrive; + break; + + default: + opResult = FileOperationResult_Error; + break; + } + } + + // close file + f_close(fileIoOperation->FatFile); + + // free memory + platform_free(fileIoOperation->FatFile); + + } + #endif + #if USE_SPIFFS_FOR_STORAGE + if(fileIoOperation->SpiffsFile != NULL) + { + uint32_t bytesRead = SPIFFS_read(&fs, *fileIoOperation->SpiffsFile, fileIoOperation->Content, fileIoOperation->ContentLength); + + if (bytesRead == fileIoOperation->ContentLength) + { + // expected number of bytes read + } + else + { + // failed to read expected number of bytes + opResult = FileOperationResult_Error; + } + + // close file + SPIFFS_close(&fs, *fileIoOperation->SpiffsFile); + + // free memory + platform_free(fileIoOperation->SpiffsFile); + } + #endif + + // free memory + platform_free(fileIoOperation); + + // fire event for FileIO operation complete + Events_Set(SYSTEM_EVENT_FLAG_STORAGE_IO); + + chThdExit((msg_t)opResult); +} + +//////////////////////////////////////////////// +// Developer notes: +// Depending on the content size these operations have the potential to be a long running ones as the string or buffer is written to the storage. +// Despite we are not (yet!) async this is better handled by spawning a thread where the actual data transfer occurs and not blocking the execution. +// The underlying RTOS inheritably takes care of making this happen "in the background". +// When the operation is completed a CLR event is fired and the thread execution resumes. +// Being hard to estimate the expected duration of the operation (depends on storage hardware, CPU clock, transfer speed, etc) +// the timeout is set to an infinite timeout +// the catch is that the working thread MUST ALWAYS return at some point +//////////////////////////////////////////////// + +HRESULT Library_win_storage_native_Windows_Storage_FileIO::WriteBytes___STATIC__VOID__WindowsStorageIStorageFile__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* bufferArray; + + CLR_RT_HeapBlock hbTimeout; + CLR_INT64* timeout; + bool eventResult = true; + + char workingDrive[DRIVE_LETTER_LENGTH]; + const char* filePath; + char* workingBuffer = NULL; + FileOperation* fileIoOperation; + + char* buffer; + uint32_t bufferLength; + + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + FIL* fatFile = NULL; + FRESULT operationResult; + #endif + #if (USE_SPIFFS_FOR_STORAGE == TRUE) + spiffs_file* spiffsFile = NULL; + #endif + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the buffer + bufferArray = stack.Arg1().DereferenceArray(); + + buffer = (char*)bufferArray->GetFirstElement(); + + bufferLength = bufferArray->m_numOfElements; + + // get a pointer to the file path + filePath = pThis[ StorageFile::FIELD___path ].DereferenceString()->StringText(); + + // !! need to cast to CLR_INT64 otherwise it wont setup a proper timeout infinite + hbTimeout.SetInteger((CLR_INT64)-1); + + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks( hbTimeout, timeout )); + + if(stack.m_customState == 1) + { + // copy the first 2 letters of the path for the drive + // path is 'D:\folder\file.txt', so we need 'D:' + memcpy(workingDrive, filePath, DRIVE_LETTER_LENGTH); + + if(WORKING_DRIVE_IS_INTERNAL_DRIVE) + { + #if (USE_SPIFFS_FOR_STORAGE == TRUE) + // SPIFFS drive workflow + + // create file struct + spiffsFile = (spiffs_file*)platform_malloc(sizeof(spiffs_file)); + // check allocation + if(spiffsFile == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // get file name removing the drive letter + workingBuffer = (char*)platform_malloc(SPIFFS_OBJ_NAME_LEN); + // sanity check for successfull malloc + if(workingBuffer == NULL) + { + // failed to allocate memory + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + memcpy(workingBuffer, (filePath + 3), SPIFFS_OBJ_NAME_LEN - 3); + + *spiffsFile = SPIFFS_open(&fs, workingBuffer, SPIFFS_TRUNC | SPIFFS_RDWR, 0); + if(*spiffsFile < 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + } + + #endif + } + else + { + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + // FatFS workflow + + // create file struct + fatFile = (FIL*)platform_malloc(sizeof(FIL)); + // check allocation + if(fatFile == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // open file (which is supposed to already exist) + // need to use FA_OPEN_ALWAYS because we are writting the file content from start + operationResult = f_open(fatFile, filePath, FA_OPEN_ALWAYS | FA_WRITE); + + if(operationResult != FR_OK) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + } + + #endif + } + + // protect the content buffer from GC so the working thread can access those + CLR_RT_ProtectFromGC gcContent( *bufferArray ); + + // setup FileIO operation + fileIoOperation = (FileOperation*)platform_malloc(sizeof(FileOperation)); + + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + fileIoOperation->FatFile = fatFile; + #endif + #if USE_SPIFFS_FOR_STORAGE + fileIoOperation->SpiffsFile = spiffsFile; + #endif + + fileIoOperation->Content = buffer; + fileIoOperation->ContentLength = bufferLength; + + // spawn working thread to perform the write transaction + fileIoWorkingThread = chThdCreateFromHeap(NULL, THD_WORKING_AREA_SIZE(2048), + "STWT", NORMALPRIO, WriteBinaryWorkingThread, fileIoOperation); + + if(fileIoWorkingThread == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } + + // bump custom state + stack.m_customState = 2; + + } + + while(eventResult) + { + // non-blocking wait allowing other threads to run while we wait for the write operation to complete + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_StorageIo, eventResult )); + + if(eventResult) + { + // event occurred + + // ChibiOS requirement: need to call chThdWait on working thread in order to have it's memory released to the heap, otherwise it won't be returned + FileOperationResult result = (FileOperationResult)chThdWait(fileIoWorkingThread); + + if(result == FileOperationResult_Error) + { + NANOCLR_SET_AND_LEAVE( CLR_E_FILE_IO ); + } + else if(result == FileOperationResult_NoFile) + { + NANOCLR_SET_AND_LEAVE( CLR_E_FILE_NOT_FOUND ); + } + else if(result == FileOperationResult_InvalidDrive) + { + // failed to change drive + NANOCLR_SET_AND_LEAVE(CLR_E_VOLUME_NOT_FOUND); + } + + // done here + break; + } + else + { + NANOCLR_SET_AND_LEAVE( CLR_E_TIMEOUT ); + } + } + + // pop timeout heap block from stack + stack.PopValue(); + + NANOCLR_CLEANUP(); + + if(workingBuffer != NULL) + { + platform_free(workingBuffer); + } + + NANOCLR_CLEANUP_END(); +} + +HRESULT Library_win_storage_native_Windows_Storage_FileIO::WriteText___STATIC__VOID__WindowsStorageIStorageFile__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_String* content; + + CLR_RT_HeapBlock hbTimeout; + CLR_INT64* timeout; + bool eventResult = true; + + char workingDrive[DRIVE_LETTER_LENGTH]; + const char* filePath; + char* workingBuffer = NULL; + FileOperation* fileIoOperation; + + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + FIL* fatFile = NULL; + FRESULT operationResult; + #endif + #if (USE_SPIFFS_FOR_STORAGE == TRUE) + spiffs_file* spiffsFile = NULL; + #endif + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the content + content = stack.Arg1().DereferenceString(); + + // get a pointer to the file path + filePath = pThis[ StorageFile::FIELD___path ].DereferenceString()->StringText(); + + // !! need to cast to CLR_INT64 otherwise it wont setup a proper timeout infinite + hbTimeout.SetInteger((CLR_INT64)-1); + + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks( hbTimeout, timeout )); + + if(stack.m_customState == 1) + { + // copy the first 2 letters of the path for the drive + // path is 'D:\folder\file.txt', so we need 'D:' + memcpy(workingDrive, filePath, DRIVE_LETTER_LENGTH); + + if(WORKING_DRIVE_IS_INTERNAL_DRIVE) + { + #if (USE_SPIFFS_FOR_STORAGE == TRUE) + // SPIFFS drive workflow + + // create file struct + spiffsFile = (spiffs_file*)platform_malloc(sizeof(spiffs_file)); + // check allocation + if(spiffsFile == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // get file name removing the drive letter + workingBuffer = (char*)platform_malloc(SPIFFS_OBJ_NAME_LEN); + // sanity check for successfull malloc + if(workingBuffer == NULL) + { + // failed to allocate memory + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + memcpy(workingBuffer, (filePath + 3), SPIFFS_OBJ_NAME_LEN - 3); + + *spiffsFile = SPIFFS_open(&fs, workingBuffer, SPIFFS_TRUNC | SPIFFS_RDWR, 0); + if(*spiffsFile < 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + } + + #endif + } + else + { + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + // FatFS workflow + + // create file struct + fatFile = (FIL*)platform_malloc(sizeof(FIL)); + // check allocation + if(fatFile == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // open file (which is supposed to already exist) + // need to use FA_OPEN_ALWAYS because we are writting the file content from start + operationResult = f_open(fatFile, filePath, FA_OPEN_ALWAYS | FA_WRITE); + + if(operationResult != FR_OK) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + } + + #endif + } + + // protect the content buffer from GC so the working thread can access those + CLR_RT_ProtectFromGC gcContent( *content ); + + // setup FileIO operation + fileIoOperation = (FileOperation*)platform_malloc(sizeof(FileOperation)); + + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + fileIoOperation->FatFile = fatFile; + #endif + #if USE_SPIFFS_FOR_STORAGE + fileIoOperation->SpiffsFile = spiffsFile; + #endif + + fileIoOperation->Content = (char*)content->StringText(); + fileIoOperation->ContentLength = hal_strlen_s(fileIoOperation->Content); + + // spawn working thread to perform the write transaction + fileIoWorkingThread = chThdCreateFromHeap(NULL, THD_WORKING_AREA_SIZE(2048), + "STWT", NORMALPRIO, WriteTextWorkingThread, fileIoOperation); + + if(fileIoWorkingThread == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } + + // bump custom state + stack.m_customState = 2; + } + + while(eventResult) + { + // non-blocking wait allowing other threads to run while we wait for the write operation to complete + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_StorageIo, eventResult )); + + if(eventResult) + { + // event occurred + + // ChibiOS requirement: need to call chThdWait on working thread in order to have it's memory released to the heap, otherwise it won't be returned + FileOperationResult result = (FileOperationResult)chThdWait(fileIoWorkingThread); + + if(result == FileOperationResult_Error) + { + NANOCLR_SET_AND_LEAVE( CLR_E_FILE_IO ); + } + else if(result == FileOperationResult_NoFile) + { + NANOCLR_SET_AND_LEAVE( CLR_E_FILE_NOT_FOUND ); + } + else if(result == FileOperationResult_InvalidDrive) + { + // failed to change drive + NANOCLR_SET_AND_LEAVE(CLR_E_VOLUME_NOT_FOUND); + } + + // done here + break; + } + else + { + NANOCLR_SET_AND_LEAVE( CLR_E_TIMEOUT ); + } + } + + // pop timeout heap block from stack + stack.PopValue(); + + NANOCLR_CLEANUP(); + + if(workingBuffer != NULL) + { + platform_free(workingBuffer); + } + + NANOCLR_CLEANUP_END(); +} + +HRESULT Library_win_storage_native_Windows_Storage_FileIO::ReadBufferNative___STATIC__VOID__WindowsStorageIStorageFile__BYREF_SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock hbTimeout; + CLR_INT64* timeout; + bool eventResult = true; + uint32_t fileSize; + + char workingDrive[DRIVE_LETTER_LENGTH]; + const char* filePath; + char* workingBuffer = NULL; + FileOperation* fileIoOperation; + + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + FIL* fatFile = NULL; + FRESULT operationResult; + #endif + #if (USE_SPIFFS_FOR_STORAGE == TRUE) + spiffs_file* spiffsFile = NULL; + #endif + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // !! need to cast to CLR_INT64 otherwise it wont setup a proper timeout infinite + hbTimeout.SetInteger((CLR_INT64)-1); + + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks( hbTimeout, timeout )); + + // get a pointer to the file path + filePath = pThis[ StorageFile::FIELD___path ].DereferenceString()->StringText(); + + if(stack.m_customState == 1) + { + // copy the first 2 letters of the path for the drive + // path is 'D:\folder\file.txt', so we need 'D:' + memcpy(workingDrive, filePath, DRIVE_LETTER_LENGTH); + + if(WORKING_DRIVE_IS_INTERNAL_DRIVE) + { + #if (USE_SPIFFS_FOR_STORAGE == TRUE) + // SPIFFS drive workflow + + // create file struct + spiffsFile = (spiffs_file*)platform_malloc(sizeof(spiffs_file)); + // check allocation + if(spiffsFile == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // get file name removing the drive letter + workingBuffer = (char*)platform_malloc(SPIFFS_OBJ_NAME_LEN); + // sanity check for successfull malloc + if(workingBuffer == NULL) + { + // failed to allocate memory + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + memcpy(workingBuffer, (filePath + 3), SPIFFS_OBJ_NAME_LEN - 3); + + *spiffsFile = SPIFFS_open(&fs, workingBuffer, SPIFFS_RDONLY, 0); + if(*spiffsFile < 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + } + + // get file details + spiffs_stat fileInfo; + SPIFFS_stat(&fs, workingBuffer, &fileInfo); + + // we are only interested in the file size + fileSize = fileInfo.size; + + #endif + } + else + { + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + // FatFS workflow + + // create file struct + fatFile = (FIL*)platform_malloc(sizeof(FIL)); + // check allocation + if(fatFile == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // open file (which is supposed to already exist) + operationResult = f_open(fatFile, filePath, FA_OPEN_EXISTING | FA_READ); + + if(operationResult != FR_OK) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + } + + // get file details + FILINFO fileInfo; + f_stat(filePath, &fileInfo); + + // we are only interested in the file size + fileSize = fileInfo.fsize; + + #endif + } + + CLR_RT_HeapBlock buffer; + buffer.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc2( buffer ); + + // create a new byte array with the appropriate size (and type) + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( buffer, (CLR_INT32)fileSize, g_CLR_RT_WellKnownTypes.m_UInt8 )); + + // store this to the argument passed byref + NANOCLR_CHECK_HRESULT(buffer.StoreToReference( stack.Arg1(), 0 )); + + // get a pointer to the buffer array to improve readability on the code ahead + CLR_RT_HeapBlock_Array* bufferArray = buffer.DereferenceArray(); + + // setup FileIO operation + fileIoOperation = (FileOperation*)platform_malloc(sizeof(FileOperation)); + + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + fileIoOperation->FatFile = fatFile; + #endif + #if USE_SPIFFS_FOR_STORAGE + fileIoOperation->SpiffsFile = spiffsFile; + #endif + + fileIoOperation->Content = (char*)bufferArray->GetFirstElement(); + fileIoOperation->ContentLength = bufferArray->m_numOfElements; + + // spawn working thread to perform the read transaction + fileIoWorkingThread = chThdCreateFromHeap(NULL, THD_WORKING_AREA_SIZE(2048), + "STRB", NORMALPRIO, ReadBinaryWorkingThread, fileIoOperation); + + if(fileIoWorkingThread == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } + + // bump custom state + stack.m_customState = 2; + } + + while(eventResult) + { + // non-blocking wait allowing other threads to run while we wait for the write operation to complete + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_StorageIo, eventResult )); + + if(eventResult) + { + // event occurred + + // ChibiOS requirement: need to call chThdWait on working thread in order to have it's memory released to the heap, otherwise it won't be returned + FileOperationResult result = (FileOperationResult)chThdWait(fileIoWorkingThread); + + if(result == FileOperationResult_Error) + { + NANOCLR_SET_AND_LEAVE( CLR_E_FILE_IO ); + } + else if(result == FileOperationResult_NoFile) + { + NANOCLR_SET_AND_LEAVE( CLR_E_FILE_NOT_FOUND ); + } + else if(result == FileOperationResult_InvalidDrive) + { + // failed to change drive + NANOCLR_SET_AND_LEAVE(CLR_E_VOLUME_NOT_FOUND); + } + + // done here + break; + } + else + { + NANOCLR_SET_AND_LEAVE( CLR_E_TIMEOUT ); + } + } + + // pop timeout heap block from stack + stack.PopValue(); + + NANOCLR_CLEANUP(); + + if(workingBuffer != NULL) + { + platform_free(workingBuffer); + } + + NANOCLR_CLEANUP_END(); +} + +HRESULT Library_win_storage_native_Windows_Storage_FileIO::ReadTextNative___STATIC__VOID__WindowsStorageIStorageFile__BYREF_STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock hbTimeout; + CLR_INT64* timeout; + bool eventResult = true; + uint32_t fileSize = 0; + + char workingDrive[DRIVE_LETTER_LENGTH]; + const char* filePath; + char* workingBuffer = NULL; + FileOperation* fileIoOperation; + + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + FIL* fatFile = NULL; + FRESULT operationResult; + #endif + #if (USE_SPIFFS_FOR_STORAGE == TRUE) + spiffs_file* spiffsFile = NULL; + #endif + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // !! need to cast to CLR_INT64 otherwise it wont setup a proper timeout infinite + hbTimeout.SetInteger((CLR_INT64)-1); + + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks( hbTimeout, timeout )); + + // get a pointer to the file path + filePath = pThis[ StorageFile::FIELD___path ].DereferenceString()->StringText(); + + if(stack.m_customState == 1) + { + // copy the first 2 letters of the path for the drive + // path is 'D:\folder\file.txt', so we need 'D:' + memcpy(workingDrive, filePath, DRIVE_LETTER_LENGTH); + + if(WORKING_DRIVE_IS_INTERNAL_DRIVE) + { + #if (USE_SPIFFS_FOR_STORAGE == TRUE) + // SPIFFS drive workflow + + // create file struct + spiffsFile = (spiffs_file*)platform_malloc(sizeof(spiffs_file)); + // check allocation + if(spiffsFile == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // get file name removing the drive letter + workingBuffer = (char*)platform_malloc(SPIFFS_OBJ_NAME_LEN); + // sanity check for successfull malloc + if(workingBuffer == NULL) + { + // failed to allocate memory + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + memcpy(workingBuffer, (filePath + 3), SPIFFS_OBJ_NAME_LEN - 3); + + *spiffsFile = SPIFFS_open(&fs, workingBuffer, SPIFFS_RDONLY, 0); + if(*spiffsFile < 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + } + + // get file details + spiffs_stat fileInfo; + SPIFFS_stat(&fs, workingBuffer, &fileInfo); + + // we are only interested in the file size + fileSize = fileInfo.size; + + #endif + } + else + { + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + // FatFS workflow + + // create file struct + fatFile = (FIL*)platform_malloc(sizeof(FIL)); + // check allocation + if(fatFile == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // open file (which is supposed to already exist) + operationResult = f_open(fatFile, filePath, FA_OPEN_EXISTING | FA_READ); + + if(operationResult != FR_OK) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + } + + // get file details + FILINFO fileInfo; + f_stat(filePath, &fileInfo); + + // we are only interested in the file size + fileSize = fileInfo.fsize; + + #endif + } + + // create a new string object with the appropriate size + CLR_RT_HeapBlock hbText; + hbText.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc( hbText ); + + CLR_RT_HeapBlock_String* textString = CLR_RT_HeapBlock_String::CreateInstance( hbText, (CLR_UINT32)fileSize ); + FAULT_ON_NULL(textString); + + // store this to the argument passed byref + NANOCLR_CHECK_HRESULT(hbText.StoreToReference( stack.Arg1(), 0 )); + + // get a pointer to the buffer array to improve readability on the code ahead + hbText.DereferenceString(); + + // setup FileIO operation + fileIoOperation = (FileOperation*)platform_malloc(sizeof(FileOperation)); + + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + fileIoOperation->FatFile = fatFile; + #endif + #if USE_SPIFFS_FOR_STORAGE + fileIoOperation->SpiffsFile = spiffsFile; + #endif + + fileIoOperation->Content = (char*)textString->StringText(); + fileIoOperation->ContentLength = fileSize; + + // spawn working thread to perform the read transaction + fileIoWorkingThread = chThdCreateFromHeap(NULL, THD_WORKING_AREA_SIZE(2048), + "STRT", NORMALPRIO, ReadTextWorkingThread, fileIoOperation); + + if(fileIoWorkingThread == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } + + // bump custom state + stack.m_customState = 2; + } + + while(eventResult) + { + // non-blocking wait allowing other threads to run while we wait for the write operation to complete + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_StorageIo, eventResult )); + + if(eventResult) + { + // event occurred + + // ChibiOS requirement: need to call chThdWait on working thread in order to have it's memory released to the heap, otherwise it won't be returned + FileOperationResult result = (FileOperationResult)chThdWait(fileIoWorkingThread); + + if(result == FileOperationResult_Error) + { + NANOCLR_SET_AND_LEAVE( CLR_E_FILE_IO ); + } + else if(result == FileOperationResult_NoFile) + { + NANOCLR_SET_AND_LEAVE( CLR_E_FILE_NOT_FOUND ); + } + else if(result == FileOperationResult_InvalidDrive) + { + // failed to change drive + NANOCLR_SET_AND_LEAVE(CLR_E_VOLUME_NOT_FOUND); + } + + // done here + break; + } + else + { + NANOCLR_SET_AND_LEAVE( CLR_E_TIMEOUT ); + } + } + + // pop timeout heap block from stack + stack.PopValue(); + + NANOCLR_CLEANUP(); + + if(workingBuffer != NULL) + { + platform_free(workingBuffer); + } + + NANOCLR_CLEANUP_END(); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Storage/win_storage_native_Windows_Storage_StorageFile.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Storage/win_storage_native_Windows_Storage_StorageFile.cpp new file mode 100644 index 00000000..dbb07cfc --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Storage/win_storage_native_Windows_Storage_StorageFile.cpp @@ -0,0 +1,325 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#if (HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE) +#include +#endif +#include "win_storage_native_target.h" +#include +#include + +#if (HAL_USBH_USE_MSD == TRUE) +#include "usbh/dev/msd.h" +#endif +#if (USE_SPIFFS_FOR_STORAGE == TRUE) +#include +#endif + +extern SYSTEMTIME GetDateTime(uint16_t date, uint16_t time); + +HRESULT Library_win_storage_native_Windows_Storage_StorageFile::DeleteFileNative___VOID(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + + char workingDrive[DRIVE_LETTER_LENGTH]; + const char* workingPath; + char* workingBuffer = NULL; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the path in managed field + workingPath = pThis[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___path].DereferenceString()->StringText(); + + // copy the first 2 letters of the path for the drive + // path is 'D:\folder\file.txt', so we need 'D:' + memcpy(workingDrive, workingPath, DRIVE_LETTER_LENGTH); + + if(WORKING_DRIVE_IS_INTERNAL_DRIVE) + { + #if (USE_SPIFFS_FOR_STORAGE == TRUE) + // SPIFFS drive workflow + + // get file name removing the drive letter + workingBuffer = (char*)platform_malloc(SPIFFS_OBJ_NAME_LEN); + // sanity check for successfull malloc + if(workingBuffer == NULL) + { + // failed to allocate memory + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + memcpy(workingBuffer, (workingPath + 3), SPIFFS_OBJ_NAME_LEN - 3); + + if(SPIFFS_remove(&fs, workingBuffer) < 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + } + + #endif + } + else + { + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + // FatFS workflow + + // Delete folder + FRESULT operationResult = f_unlink(workingPath); + if (operationResult != FR_OK) + { + // folder doesn't exist + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + } + #endif + } + + NANOCLR_CLEANUP(); + + if(workingBuffer != NULL) + { + platform_free(workingBuffer); + } + + NANOCLR_CLEANUP_END(); +} + +HRESULT Library_win_storage_native_Windows_Storage_StorageFile::RenameFileNative___VOID__STRING(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + + char workingDrive[DRIVE_LETTER_LENGTH]; + const char* workingPath; + const char* desiredPath; + char* workingBuffer = NULL; + char* workingBuffer1 = NULL; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the path in managed field + workingPath = pThis[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___path].DereferenceString()->StringText(); + + // get a pointer to the desired folder path + desiredPath = stack.Arg1().DereferenceString()->StringText(); + + // copy the first 2 letters of the path for the drive + // path is 'D:\folder\file.txt', so we need 'D:' + memcpy(workingDrive, workingPath, DRIVE_LETTER_LENGTH); + + if(WORKING_DRIVE_IS_INTERNAL_DRIVE) + { + #if (USE_SPIFFS_FOR_STORAGE == TRUE) + // SPIFFS drive workflow + + // get origin and desired file names removing the drive letter + // need to malloc these + workingBuffer = (char*)platform_malloc(SPIFFS_OBJ_NAME_LEN); + workingBuffer1 = (char*)platform_malloc(SPIFFS_OBJ_NAME_LEN); + // sanity check for successfull malloc + if( (workingBuffer == NULL) || + (workingBuffer1 == NULL)) + { + // failed to allocate memory + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + memcpy(workingBuffer, (workingPath + 3), SPIFFS_OBJ_NAME_LEN - 3); + memcpy(workingBuffer1, (desiredPath + 3), SPIFFS_OBJ_NAME_LEN - 3); + + if(SPIFFS_rename(&fs, workingBuffer, workingBuffer1) < 0) + { + switch(SPIFFS_errno(&fs)) + { + case SPIFFS_ERR_NOT_FOUND: + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + break; + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_IO); + break; + } + } + + #endif + } + else + { + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + // FatFS workflow + + // rename folder + FRESULT operationResult = f_rename(workingPath, desiredPath); + if (operationResult == FR_INVALID_NAME) + { + // invalid path + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + else if (operationResult != FR_OK) + { + // folder doesn't exist + NANOCLR_SET_AND_LEAVE(CLR_E_DIRECTORY_NOT_FOUND); + } + #endif + } + + NANOCLR_CLEANUP(); + + if(workingBuffer != NULL) + { + platform_free(workingBuffer); + } + if(workingBuffer1 != NULL) + { + platform_free(workingBuffer1); + } + + NANOCLR_CLEANUP_END(); +} + +HRESULT Library_win_storage_native_Windows_Storage_StorageFile::GetFileFromPathNative___STATIC__WindowsStorageStorageFile__STRING__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Index storageFileTypeDef; + CLR_RT_HeapBlock* storageFile; + + char workingDrive[DRIVE_LETTER_LENGTH]; + char* workingBuffer = NULL; + const char* filePath; + const char* fileName; + + // get a pointer to the file path + filePath = stack.Arg0().DereferenceString()->StringText(); + + // get a pointer to the file name + fileName = stack.Arg1().DereferenceString()->StringText(); + + // copy the first 2 letters of the path for the drive + // path is 'D:\folder\file.txt', so we need 'D:' + memcpy(workingDrive, filePath, DRIVE_LETTER_LENGTH); + + if(WORKING_DRIVE_IS_INTERNAL_DRIVE) + { + #if (USE_SPIFFS_FOR_STORAGE == TRUE) + // SPIFFS drive workflow + + // get file name removing the drive letter + // need to malloc this + workingBuffer = (char*)platform_malloc(SPIFFS_OBJ_NAME_LEN); + // sanity check for successfull malloc + if(workingBuffer == NULL) + { + // failed to allocate memory + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + memcpy(workingBuffer, (filePath + 3), SPIFFS_OBJ_NAME_LEN - 3); + + spiffs_file file = SPIFFS_open(&fs, workingBuffer, SPIFFS_RDONLY, 0); + if(file < 0) + { + switch(SPIFFS_errno(&fs)) + { + case SPIFFS_ERR_NOT_FOUND: + SPIFFS_close(&fs, file); + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + break; + + default: + SPIFFS_close(&fs, file); + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_IO); + break; + } + } + + SPIFFS_close(&fs, file); + + // compose return object + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef("StorageFile", "Windows.Storage", storageFileTypeDef); + + // create a + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(stack.PushValue(), storageFileTypeDef)); + + // get a handle to the storage file + storageFile = stack.TopValue().Dereference(); + + // file name + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance(storageFile[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___name], fileName)); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance(storageFile[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___path], filePath)); + + // SPIFFS files don't have date information so we are done here + + #endif + } + else + { + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + // FatFS workflow + + FILINFO fileInfo; + SYSTEMTIME fileInfoTime; + + FRESULT fr = f_stat(filePath, &fileInfo); + if(fr == FR_OK) + { + // is this a file? + if ( !(fileInfo.fattrib & AM_DIR) ) + { + // path represents a file, we are good + + // compose return object + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef("StorageFile", "Windows.Storage", storageFileTypeDef); + + // create a + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(stack.PushValue(), storageFileTypeDef)); + + // get a handle to the storage file + storageFile = stack.TopValue().Dereference(); + + // file name + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance(storageFile[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___name], fileName)); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance(storageFile[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___path], filePath)); + + // get the date time details and fill in the managed field + // compute directory date + fileInfoTime = GetDateTime(fileInfo.fdate, fileInfo.ftime); + + // get a reference to the dateCreated managed field... + CLR_RT_HeapBlock& dateFieldRef = storageFile[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___dateCreated]; + CLR_INT64* pRes = (CLR_INT64*)&dateFieldRef.NumericByRef().s8; + // ...and set it with the fileInfoTime + *pRes = HAL_Time_ConvertFromSystemTime( &fileInfoTime ); + } + else + { + // path exists but it's a folder + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + } + } + else if(fr == FR_NO_FILE) + { + // file doesn't exist + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + } + else + { + // IO error + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_IO); + } + + #endif + } + + NANOCLR_CLEANUP(); + + if(workingBuffer != NULL) + { + platform_free(workingBuffer); + } + + NANOCLR_CLEANUP_END(); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Storage/win_storage_native_Windows_Storage_StorageFolder.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Storage/win_storage_native_Windows_Storage_StorageFolder.cpp new file mode 100644 index 00000000..4a2bdb29 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Storage/win_storage_native_Windows_Storage_StorageFolder.cpp @@ -0,0 +1,1625 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#if (HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE) +#include +#endif +#include "win_storage_native_target.h" +#include +#include +#include + +#if (HAL_USBH_USE_MSD == TRUE) +#include "usbh/dev/msd.h" +#endif +#if (USE_SPIFFS_FOR_STORAGE == TRUE) +#include +#endif + +// flags for file system ready +#if (HAL_USE_SDC == TRUE) +extern bool sdCardFileSystemReady; +#endif +#if (HAL_USBH_USE_MSD == TRUE) +extern bool usbMsdFileSystemReady; +#endif +#if (USE_SPIFFS_FOR_STORAGE == TRUE) +extern bool spiffsFileSystemReady; +extern spiffs fs; +#endif + +void CombinePath(char * outpath, const char * path1, const char * path2) +{ + strcat(outpath, path1); + + // Add "\" to path if required + if (outpath[hal_strlen_s(outpath) - 1] != '\\') + { + strcat(outpath, "\\"); + } + strcat(outpath, path2); +} + +SYSTEMTIME GetDateTime(uint16_t date, uint16_t time) +{ + SYSTEMTIME fileTime; + + memset(&fileTime, 0, sizeof(SYSTEMTIME)); + + // date (bit15:9) Year origin from 1980 (0..127) + fileTime.wYear = (date >> 9) + 1980; + // date (bit8:5) Month (1..12) + fileTime.wMonth = (date >> 5) & 0x000F; + // date (bit4:0) Day (1..31) + fileTime.wDay = date & 0x001F; + + // time (bit15:11) Hour (0..23) + fileTime.wHour = (time >> 11) & 0x001F; + // time (bit10:5) Minute (0..59) + fileTime.wMinute = (time >> 5) & 0x003F; + // time (bit4:0) Second / 2 (0..29) + fileTime.wSecond = time & 0x001F; + + return fileTime; +} + +HRESULT Library_win_storage_native_Windows_Storage_StorageFolder::GetRemovableStorageFoldersNative___SZARRAY_WindowsStorageStorageFolder( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + char* stringBuffer; + uint32_t driveCount = 0; + char workingDrive[sizeof(DRIVE_PATH_LENGTH)]; + uint16_t driveIterator = 0; + + CLR_RT_HeapBlock* storageFolder; + CLR_RT_TypeDef_Index storageFolderTypeDef; + CLR_RT_HeapBlock* hbObj; + CLR_RT_HeapBlock& top = stack.PushValue(); + + #if HAL_USE_SDC + bool sdCardEnumerated = false; + #endif + + #if HAL_USE_SDC + // is the SD card file system ready? + if(sdCardFileSystemReady) + { + // add count + driveCount++; + } + #endif + + #if HAL_USBH_USE_MSD + bool usbMsdEnumerated = false; + + // is the USB mass storage device file system ready? + if(usbMsdFileSystemReady) + { + // add count + driveCount++; + } + #endif + + // start composing the reply + // find type definition, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef( "StorageFolder", "Windows.Storage", storageFolderTypeDef ); + + // create an array of + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( top, driveCount, storageFolderTypeDef )); + + #if (HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE) + + if(driveCount > 0) + { + // there are driver present and enumerated + + // get a pointer to the first object in the array (which is of type ) + storageFolder = (CLR_RT_HeapBlock*)top.DereferenceArray()->GetFirstElement(); + + // create an instance of + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*storageFolder, storageFolderTypeDef)); + + // loop until we've loaded all the possible drives + // because we are iterating through an enum, need to use its integer values + for(; driveIterator < driveCount; driveIterator++ ) + { + // fill the folder name and path + + #if HAL_USE_SDC + // is the SD card file system ready? + if(sdCardFileSystemReady && !sdCardEnumerated) + { + memcpy(workingDrive, INDEX0_DRIVE_PATH, DRIVE_PATH_LENGTH); + + // flag as enumerated + sdCardEnumerated = true; + } + #endif + + #if HAL_USBH_USE_MSD + // is the USB mass storage device file system ready? + if(usbMsdFileSystemReady && !usbMsdEnumerated) + { + memcpy(workingDrive, INDEX1_DRIVE_PATH, DRIVE_PATH_LENGTH); + + // flag as enumerated + usbMsdEnumerated = true; + } + #endif + + // dereference the object in order to reach its fields + hbObj = storageFolder->Dereference(); + + // set the managed fields + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( hbObj[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___name ], workingDrive )); + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( hbObj[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path ], workingDrive )); + + // malloc stringBuffer to work with FS + stringBuffer = (char*)platform_malloc(FF_LFN_BUF + 1); + + // sanity check for successfull malloc + if(stringBuffer == NULL) + { + // failed to allocate memory + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + else + { + // clear buffer + memset(stringBuffer, 0, FF_LFN_BUF + 1); + + // read the drive volume label + // don't bother checking the result, if anything goes wrong we'll end up with an empty string which is OK + f_getlabel(workingDrive, stringBuffer, NULL); + + // add the driver letter separated it with an empty space, if the volume label isn't empty + if(*stringBuffer != '\0') + { + strcat(stringBuffer, " "); + } + strcat(stringBuffer, "("); + strcat(stringBuffer, workingDrive); + strcat(stringBuffer, ")"); + + // set the field with the volume label + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( hbObj[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___name ], stringBuffer )); + + + // free stringBuffer + platform_free(stringBuffer); + } + + // move pointer to the next folder item + storageFolder++; + } + } + + #endif + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_storage_native_Windows_Storage_StorageFolder::GetInternalStorageFoldersNative___SZARRAY_WindowsStorageStorageFolder(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + + uint32_t driveCount = 0; + char workingDrive[sizeof(DRIVE_PATH_LENGTH)]; + + CLR_RT_HeapBlock* storageFolder; + CLR_RT_TypeDef_Index storageFolderTypeDef; + CLR_RT_HeapBlock* hbObj; + CLR_RT_HeapBlock& top = stack.PushValue(); + + #if (USE_SPIFFS_FOR_STORAGE == TRUE) + // is the SPIFFS file system available and mounted? + if(spiffsFileSystemReady) + { + // add count + driveCount++; + } + #endif + + // start composing the reply + // find type definition, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef( "StorageFolder", "Windows.Storage", storageFolderTypeDef ); + + // create an array of + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( top, driveCount, storageFolderTypeDef )); + + if(driveCount > 0) + { + // SPIFFS is mounted + // currently there is support for a single SPIFFS instance + + // get a pointer to the first object in the array (which is of type ) + storageFolder = (CLR_RT_HeapBlock*)top.DereferenceArray()->GetFirstElement(); + + // create an instance of + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*storageFolder, storageFolderTypeDef)); + + // fill the folder name and path + memcpy(workingDrive, INTERNAL_DRIVE_PATH, DRIVE_PATH_LENGTH); + + // dereference the object in order to reach its fields + hbObj = storageFolder->Dereference(); + + // set the managed fields + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( hbObj[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___name ], workingDrive )); + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( hbObj[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path ], workingDrive )); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_storage_native_Windows_Storage_StorageFolder::GetStorageFoldersNative___SZARRAY_WindowsStorageStorageFolder( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Index storageFolderTypeDef; + CLR_RT_HeapBlock* storageFolder; + CLR_RT_HeapBlock* hbObj; + SYSTEMTIME fileInfoTime; + + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + + const char* workingPath; + char workingDrive[DRIVE_LETTER_LENGTH]; + + DIR currentDirectory; + FRESULT operationResult; + static FILINFO fileInfo; + uint16_t directoryCount = 0; + char* stringBuffer = NULL; + char* workingBuffer = NULL; + + CLR_RT_HeapBlock& top = stack.PushValue(); + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // copy the first 2 letters of the path for the drive + // path is 'D:\folder\file.txt', so we need 'D:' + memcpy(workingDrive, pThis[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path ].DereferenceString()->StringText(), DRIVE_LETTER_LENGTH); + + // get a pointer to the path in managed field + workingPath = pThis[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path ].DereferenceString()->StringText(); + + // open directory + operationResult = f_opendir(¤tDirectory, workingPath); + + if(operationResult != FR_OK) + { + if(operationResult == FR_INVALID_DRIVE) + { + // failed to change drive + + // check if the working drive is the SPIFFS drive + #if (USE_SPIFFS_FOR_STORAGE == TRUE) + if(WORKING_DRIVE_IS_INTERNAL_DRIVE) + { + // this is the SPIFFS drive, + // do nothing here and return an empty collection because folders aren't supported in SPIFFS + } + else + { + #else + { + #endif + // invalid drive + NANOCLR_SET_AND_LEAVE(CLR_E_VOLUME_NOT_FOUND); + } + } + + // error or directory empty + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef( "StorageFolder", "Windows.Storage", storageFolderTypeDef ); + + // create an array of + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( top, directoryCount, storageFolderTypeDef )); + } + else + { + // need to perform this in two steps + // 1st: count the directory objects + // 2nd: create the array items with each directory object + + // perform 1st pass + for (;;) + { + // read next directory item + operationResult = f_readdir(¤tDirectory, &fileInfo); + + // break on error or at end of dir + if (operationResult != FR_OK || fileInfo.fname[0] == 0) + { + break; + } + + // check if this is a directory + // but skip if: + // - has system attribute set + // - has hidden attribute set + if ((fileInfo.fattrib & AM_DIR) && + !(fileInfo.fattrib & AM_SYS) && + !(fileInfo.fattrib & AM_HID)) + { + directoryCount++; + } + } + + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef( "StorageFolder", "Windows.Storage", storageFolderTypeDef ); + + // create an array of + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( top, directoryCount, storageFolderTypeDef )); + + // get a pointer to the first object in the array (which is of type ) + storageFolder = (CLR_RT_HeapBlock*)top.DereferenceArray()->GetFirstElement(); + + if(directoryCount > 0) + { + // allocate memory for buffers + stringBuffer = (char*)platform_malloc(FF_LFN_BUF + 1); + workingBuffer = (char*)platform_malloc(2 * FF_LFN_BUF + 1); + + // sanity check for successfull malloc + if(stringBuffer == NULL || workingBuffer == NULL) + { + // failed to allocate memory + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // perform 2nd pass + // need to rewind the directory read index first + f_readdir(¤tDirectory, NULL); + + for (;;) + { + // read next directory item + operationResult = f_readdir(¤tDirectory, &fileInfo); + + // break on error or at end of dir + if (operationResult != FR_OK || fileInfo.fname[0] == 0) + { + break; + } + + // check if this is a directory + // but skip if: + // - has system attribute set + // - has hidden attribute set + if ((fileInfo.fattrib & AM_DIR) && + !(fileInfo.fattrib & AM_SYS) && + !(fileInfo.fattrib & AM_HID)) + { + // create an instance of + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*storageFolder, storageFolderTypeDef)); + + // dereference the object in order to reach its fields + hbObj = storageFolder->Dereference(); + + // directory name + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( hbObj[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___name ], fileInfo.fname )); + + // clear working buffer + memset(workingBuffer, 0, 2 * FF_LFN_BUF + 1); + + // compose directory path + CombinePath(workingBuffer, workingPath, fileInfo.fname); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( hbObj[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path ], workingBuffer )); + + // compute directory date + fileInfoTime = GetDateTime(fileInfo.fdate, fileInfo.ftime); + + // get a reference to the dateCreated managed field... + CLR_RT_HeapBlock& dateFieldRef = hbObj[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___dateCreated ]; + CLR_INT64* pRes = (CLR_INT64*)&dateFieldRef.NumericByRef().s8; + // ...and set it with the fileInfoTime + *pRes = HAL_Time_ConvertFromSystemTime( &fileInfoTime ); + + // move the storage folder pointer to the next item in the array + storageFolder++; + } + } + } + } + + #elif (USE_SPIFFS_FOR_STORAGE == TRUE) + + // SPIFFS doesn't support folders so return an empty collection + CLR_RT_HeapBlock& top = stack.PushValue(); + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef( "StorageFolder", "Windows.Storage", storageFolderTypeDef ); + + // create an array of + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( top, directoryCount, storageFolderTypeDef )); + + #endif + + NANOCLR_CLEANUP(); + + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + // close directory + f_closedir(¤tDirectory); + + // free buffers memory, if allocated + if(stringBuffer != NULL) + { + platform_free(stringBuffer); + } + if(workingBuffer != NULL) + { + platform_free(workingBuffer); + } + #endif + + NANOCLR_CLEANUP_END(); +} + +HRESULT Library_win_storage_native_Windows_Storage_StorageFolder::GetStorageFilesNative___SZARRAY_WindowsStorageStorageFile__U4__U4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Index storageFileTypeDef; + CLR_RT_HeapBlock* storageFile; + CLR_RT_HeapBlock* hbObj; + SYSTEMTIME fileInfoTime; + + const char* workingPath; + char workingDrive[DRIVE_LETTER_LENGTH]; + + uint32_t startIndex; + uint32_t maxItemsToRetrieve; + uint32_t itemIndex = 0; + + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + + DIR currentDirectory; + FRESULT operationResult; + static FILINFO fileInfo; + uint16_t fileCount = 0; + char* stringBuffer = NULL; + char* workingBuffer = NULL; + + CLR_RT_HeapBlock& top = stack.PushValue(); + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get start index + startIndex = stack.Arg1().NumericByRef().u4; + + // get max items to retrieve + maxItemsToRetrieve = stack.Arg2().NumericByRef().u4; + + // copy the first 2 letters of the path for the drive + // path is 'D:\folder\file.txt', so we need 'D:' + memcpy(workingDrive, pThis[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path ].DereferenceString()->StringText(), DRIVE_LETTER_LENGTH); + + // get a pointer to the path in managed field + workingPath = pThis[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path ].DereferenceString()->StringText(); + + // change drive + if(f_chdrive(workingDrive) == FR_OK) + { + // open directory + operationResult = f_opendir(¤tDirectory, workingPath); + + if(operationResult != FR_OK) + { + // error or directory empty + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef( "StorageFile", "Windows.Storage", storageFileTypeDef ); + + // create an array of + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( top, fileCount, storageFileTypeDef )); + } + else + { + // need to perform this in two steps + // 1st: count the file objects + // 2nd: create the array items with each file object + + // perform 1st pass + for (;;) + { + // read next directory item + operationResult = f_readdir(¤tDirectory, &fileInfo); + + // break on error or at end of dir + if (operationResult != FR_OK || fileInfo.fname[0] == 0) + { + break; + } + + // check if this is a file + // but skip if: + // - has system attribute set + // - has hidden attribute set + if ((fileInfo.fattrib & AM_ARC) && + !(fileInfo.fattrib & AM_SYS) && + !(fileInfo.fattrib & AM_HID)) + { + // check if this file is within the requested parameters + if( (itemIndex >= startIndex) && + (fileCount < maxItemsToRetrieve)) + { + fileCount++; + } + + itemIndex++; + } + } + + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef( "StorageFile", "Windows.Storage", storageFileTypeDef ); + + // create an array of + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( top, fileCount, storageFileTypeDef )); + + // get a pointer to the first object in the array (which is of type ) + storageFile = (CLR_RT_HeapBlock*)top.DereferenceArray()->GetFirstElement(); + + if(fileCount > 0) + { + // allocate memory for buffers + stringBuffer = (char*)platform_malloc(FF_LFN_BUF + 1); + workingBuffer = (char*)platform_malloc(2 * FF_LFN_BUF + 1); + + // sanity check for successfull malloc + if(stringBuffer == NULL || workingBuffer == NULL) + { + // failed to allocate memory + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // perform 2nd pass + // need to rewind the directory read index first + f_readdir(¤tDirectory, NULL); + + // and reset the file iterator vars too + itemIndex = 0; + fileCount = 0; + + + for (;;) + { + // read next directory item + operationResult = f_readdir(¤tDirectory, &fileInfo); + + // break on error or at end of dir + if (operationResult != FR_OK || fileInfo.fname[0] == 0) + { + break; + } + + // check if this is a file + // but skip if: + // - has system attribute set + // - has hidden attribute set + if ((fileInfo.fattrib & AM_ARC) && + !(fileInfo.fattrib & AM_SYS) && + !(fileInfo.fattrib & AM_HID)) + { + // check if this file is within the requested parameters + if( (itemIndex >= startIndex) && + (fileCount < maxItemsToRetrieve)) + { + // create an instance of + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*storageFile, storageFileTypeDef)); + + // dereference the object in order to reach its fields + hbObj = storageFile->Dereference(); + + // file name + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( hbObj[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___name ], fileInfo.fname )); + + // clear working buffer + memset(workingBuffer, 0, 2 * FF_LFN_BUF + 1); + + // compose file path + CombinePath(workingBuffer, workingPath, fileInfo.fname); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( hbObj[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___path ], workingBuffer )); + + // compute directory date + fileInfoTime = GetDateTime(fileInfo.fdate, fileInfo.ftime); + + // get a reference to the dateCreated managed field... + CLR_RT_HeapBlock& dateFieldRef = hbObj[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___dateCreated ]; + CLR_INT64* pRes = (CLR_INT64*)&dateFieldRef.NumericByRef().s8; + // ...and set it with the fileInfoTime + *pRes = HAL_Time_ConvertFromSystemTime( &fileInfoTime ); + + // move the storage folder pointer to the next item in the array + storageFile++; + + // update iterator var + fileCount++; + } + + // update iterator var + itemIndex++; + } + } + } + else + { + // empty directory + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef( "StorageFile", "Windows.Storage", storageFileTypeDef ); + + // create an array of + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( top, fileCount, storageFileTypeDef )); + } + } + } + else + { + // check if the working drive is the SPIFFS drive and... + // ... that the path is the drive root (because SPIFFS doesn't support folders) + #if (USE_SPIFFS_FOR_STORAGE == TRUE) + if( (WORKING_DRIVE_IS_INTERNAL_DRIVE) && + (hal_strlen_s(workingPath) == DRIVE_PATH_LENGTH - 1)) + { + // this is the SPIFFS drive + spiffs_DIR drive; + struct spiffs_dirent e; + struct spiffs_dirent *pe = &e; + + // need to perform this in two steps + // 1st: count the file objects + // 2nd: create the array items with each file object + + // perform 1st pass + SPIFFS_opendir(&fs, "/", &drive); + while ((pe = SPIFFS_readdir(&drive, pe))) + { + fileCount++; + } + + // have to close dir + SPIFFS_closedir(&drive); + + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef( "StorageFile", "Windows.Storage", storageFileTypeDef ); + + // create an array of + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( top, fileCount, storageFileTypeDef )); + + // get a pointer to the first object in the array (which is of type ) + storageFile = (CLR_RT_HeapBlock*)top.DereferenceArray()->GetFirstElement(); + + if(fileCount > 0) + { + // allocate memory for buffer + workingBuffer = (char*)platform_malloc(2 * FF_LFN_BUF + 1); + + // sanity check for successfull malloc + if(workingBuffer == NULL) + { + // failed to allocate memory + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // perform 2nd pass + // need to open the directory again + SPIFFS_opendir(&fs, "/", &drive); + + // and reset the file iterator vars too + itemIndex = 0; + fileCount = 0; + pe = &e; + + while ((pe = SPIFFS_readdir(&drive, pe))) + { + // create an instance of + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*storageFile, storageFileTypeDef)); + + // dereference the object in order to reach its fields + hbObj = storageFile->Dereference(); + + // file name + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( hbObj[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___name ], (const char*)pe->name )); + + // clear working buffer + memset(workingBuffer, 0, 2 * FF_LFN_BUF + 1); + + // compose file path + CombinePath(workingBuffer, workingPath, (const char*)pe->name); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( hbObj[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___path ], workingBuffer )); + + // SPIFFS files don't have date information + + // move the storage folder pointer to the next item in the array + storageFile++; + } + + // done here, close dir + SPIFFS_closedir(&drive); + } + } + else + { + #else + { + #endif + // failed to change drive + NANOCLR_SET_AND_LEAVE(CLR_E_VOLUME_NOT_FOUND); + } + } + + #elif (USE_SPIFFS_FOR_STORAGE == TRUE) + + CLR_RT_HeapBlock& top = stack.PushValue(); + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + spiffs_DIR drive; + struct spiffs_dirent e; + struct spiffs_dirent *pe = &e; + + // need to perform this in two steps + // 1st: count the file objects + // 2nd: create the array items with each file object + + // perform 1st pass + SPIFFS_opendir(&fs, "/", &drive); + while ((pe = SPIFFS_readdir(&drive, pe))) + { + fileCount++; + } + + // have to close dir + SPIFFS_closedir(&drive); + + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef( "StorageFile", "Windows.Storage", storageFileTypeDef ); + + // create an array of + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( top, fileCount, storageFileTypeDef )); + + // get a pointer to the first object in the array (which is of type ) + storageFile = (CLR_RT_HeapBlock*)top.DereferenceArray()->GetFirstElement(); + + if(fileCount > 0) + { + // allocate memory for buffer + workingBuffer = (char*)platform_malloc(2 * FF_LFN_BUF + 1); + + // sanity check for successfull malloc + if(workingBuffer == NULL) + { + // failed to allocate memory + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // perform 2nd pass + // need to open the directory again + SPIFFS_opendir(&fs, "/", &drive); + + // and reset the file iterator vars too + itemIndex = 0; + fileCount = 0; + + while ((pe = SPIFFS_readdir(&drive, pe))) + { + // create an instance of + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*storageFile, storageFileTypeDef)); + + // dereference the object in order to reach its fields + hbObj = storageFile->Dereference(); + + // file name + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( hbObj[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___name ], (const char*)pe->name )); + + // clear working buffer + memset(workingBuffer, 0, 2 * FF_LFN_BUF + 1); + + // compose file path + CombinePath(workingBuffer, workingPath, (const char*)pe->name); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( hbObj[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___path ], workingBuffer )); + + // SPIFFS files don't have date information + + // move the storage folder pointer to the next item in the array + storageFile++; + } + + // done here, close dir + SPIFFS_closedir(&drive); + } + #endif + + NANOCLR_CLEANUP(); + + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + // close directory + f_closedir(¤tDirectory); + #endif + + // free buffers memory, if allocated + if(stringBuffer != NULL) + { + platform_free(stringBuffer); + } + if(workingBuffer != NULL) + { + platform_free(workingBuffer); + } + + NANOCLR_CLEANUP_END(); +} + +HRESULT Library_win_storage_native_Windows_Storage_StorageFolder::CreateFileNative___WindowsStorageStorageFile__STRING__U4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Index storageFileTypeDef; + CLR_RT_HeapBlock* storageFile; + + const char* fileName; + const char* workingPath; + char workingDrive[DRIVE_LETTER_LENGTH]; + + CreationCollisionOption options; + + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + + FIL file; + static FILINFO fileInfo; + SYSTEMTIME fileInfoTime; + FRESULT operationResult; + uint8_t modeFlags = 0; + char* filePath = NULL; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // copy the first 2 letters of the path for the drive + // path is 'D:\folder\file.txt', so we need 'D:' + memcpy(workingDrive, pThis[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path ].DereferenceString()->StringText(), DRIVE_LETTER_LENGTH); + + // get creation collision options + options = (CreationCollisionOption)stack.Arg2().NumericByRef().u4; + + // get a pointer to the StorageFolder path in managed field + workingPath = pThis[ Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path ].DereferenceString()->StringText(); + + // get a pointer to the desired file name + fileName = stack.Arg1().DereferenceString()->StringText(); + + // setup file path + filePath = (char*)platform_malloc(2 * FF_LFN_BUF + 1); + + // sanity check for successfull malloc + if(filePath == NULL) + { + // failed to allocate memory + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // clear working buffer + memset(filePath, 0, 2 * FF_LFN_BUF + 1); + + // compose file path + CombinePath(filePath, workingPath, fileName); + + // change directory + operationResult = f_chdir(workingPath); + + if(operationResult != FR_OK) + { + if(operationResult == FR_INVALID_DRIVE) + { + // check if the working drive is the SPIFFS drive + #if (USE_SPIFFS_FOR_STORAGE == TRUE) + if(WORKING_DRIVE_IS_INTERNAL_DRIVE) + { + // this is the SPIFFS drive + // proceed to create the file + + // compute mode flags from CreationCollisionOption + switch (options) + { + case CreationCollisionOption_ReplaceExisting: + modeFlags = SPIFFS_CREAT | SPIFFS_TRUNC | SPIFFS_RDWR; + break; + + case CreationCollisionOption_FailIfExists: + modeFlags = SPIFFS_RDWR; + break; + + case CreationCollisionOption_OpenIfExists: + modeFlags = SPIFFS_CREAT | SPIFFS_RDWR; + break; + + case CreationCollisionOption_GenerateUniqueName: + // this operation is not supported in nanoFramework + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + + default: + break; + } + + spiffs_file fd = SPIFFS_open(&fs, fileName, modeFlags, 0); + if (fd < 0) + { + int32_t error = SPIFFS_errno(&fs); + + // process operation result according to creation options + if( (error == SPIFFS_ERR_FILE_EXISTS) && + (options == CreationCollisionOption_FailIfExists)) + { + // file already exists + NANOCLR_SET_AND_LEAVE(CLR_E_PATH_ALREADY_EXISTS); + } + if(options == CreationCollisionOption_OpenIfExists) + { + // file doesn't exist + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + } + + // failed to create the file + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_IO); + } + else + { + // file created (or opened) succesfully + // OK to close it + SPIFFS_close(&fs, fd); + + // compose return object + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef( "StorageFile", "Windows.Storage", storageFileTypeDef ); + + // create a + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(stack.PushValue(), storageFileTypeDef)); + + // get a handle to the storage file + storageFile = stack.TopValue().Dereference(); + + // file name + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( storageFile[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___name ], fileName )); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( storageFile[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___path ], filePath )); + + // SPIFFS don't have date time details, so we are done here + } + } + else + { + #else + { + #endif + // invalid drive + NANOCLR_SET_AND_LEAVE(CLR_E_VOLUME_NOT_FOUND); + } + } + else + { + // error opening the directoty + NANOCLR_SET_AND_LEAVE(CLR_E_DIRECTORY_NOT_FOUND); + } + } + else + { + // compute mode flags from CreationCollisionOption + switch (options) + { + case CreationCollisionOption_ReplaceExisting: + modeFlags = FA_CREATE_ALWAYS; + break; + + case CreationCollisionOption_FailIfExists: + modeFlags = FA_CREATE_NEW; + break; + + case CreationCollisionOption_OpenIfExists: + modeFlags = FA_OPEN_EXISTING; + break; + + case CreationCollisionOption_GenerateUniqueName: + // this operation is not supported in nanoFramework + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + + default: + break; + } + + // open file + operationResult = f_open(&file, filePath, modeFlags); + + // process operation result according to creation options + if( (operationResult == FR_EXIST) && + (options == CreationCollisionOption_FailIfExists)) + { + // file already exists + NANOCLR_SET_AND_LEAVE(CLR_E_PATH_ALREADY_EXISTS); + } + if( (operationResult == FR_NO_FILE) && + (options == CreationCollisionOption_OpenIfExists)) + { + // file doesn't exist + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + } + + if(operationResult == FR_OK) + { + // file created (or opened) succesfully + // OK to close it + f_close(&file); + + // now get the details + f_stat(fileName, &fileInfo); + + // compose return object + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef( "StorageFile", "Windows.Storage", storageFileTypeDef ); + + // create a + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(stack.PushValue(), storageFileTypeDef)); + + // get a handle to the storage file + storageFile = stack.TopValue().Dereference(); + + // file name + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( storageFile[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___name ], fileName )); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( storageFile[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___path ], filePath )); + + // get the date time details and fill in the managed field + // compute directory date + fileInfoTime = GetDateTime(fileInfo.fdate, fileInfo.ftime); + + // get a reference to the dateCreated managed field... + CLR_RT_HeapBlock& dateFieldRef = storageFile[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___dateCreated ]; + CLR_INT64* pRes = (CLR_INT64*)&dateFieldRef.NumericByRef().s8; + // ...and set it with the fileInfoTime + *pRes = HAL_Time_ConvertFromSystemTime( &fileInfoTime ); + } + else + { + // failed to create the file + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_IO); + } + } + + #elif (USE_SPIFFS_FOR_STORAGE == TRUE) + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // copy the first 2 letters of the path for the drive + // path is 'D:\folder\file.txt', so we need 'D:' + memcpy(workingDrive, pThis[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path ].DereferenceString()->StringText(), DRIVE_LETTER_LENGTH); + + // get creation collision options + options = (CreationCollisionOption)stack.Arg2().NumericByRef().u4; + + // get a pointer to the StorageFolder path in managed field + workingPath = pThis[ Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path ].DereferenceString()->StringText(); + + // get a pointer to the desired file name + fileName = stack.Arg1().DereferenceString()->StringText(); + + // setup file path + filePath = (char*)platform_malloc(2 * FF_LFN_BUF + 1); + + // sanity check for successfull malloc + if(filePath == NULL) + { + // failed to allocate memory + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // clear working buffer + memset(filePath, 0, 2 * FF_LFN_BUF + 1); + + // compose file path + CombinePath(filePath, workingPath, fileName); + + // compute mode flags from CreationCollisionOption + switch (options) + { + case CreationCollisionOption_ReplaceExisting: + modeFlags = SPIFFS_CREAT | SPIFFS_TRUNC; + break; + + case CreationCollisionOption_FailIfExists: + modeFlags = 0; + break; + + case CreationCollisionOption_OpenIfExists: + modeFlags = SPIFFS_CREAT; + break; + + case CreationCollisionOption_GenerateUniqueName: + // this operation is not supported in nanoFramework + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + + default: + break; + } + + spiffs_file fd = SPIFFS_open(&fs, filePath, modeFlags, 0); + if (fd < 0) + { + int32_t error = SPIFFS_errno(&fs); + + // process operation result according to creation options + if( (error == SPIFFS_ERR_FILE_EXISTS) && + (options == CreationCollisionOption_FailIfExists)) + { + // file already exists + NANOCLR_SET_AND_LEAVE(CLR_E_PATH_ALREADY_EXISTS); + } + if(options == CreationCollisionOption_OpenIfExists) + { + // file doesn't exist + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + } + + // failed to create the file + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_IO); + } + else + { + // file created (or opened) succesfully + // OK to close it + SPIFFS_close(&fs, fd); + + // compose return object + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef( "StorageFile", "Windows.Storage", storageFileTypeDef ); + + // create a + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(stack.PushValue(), storageFileTypeDef)); + + // get a handle to the storage file + storageFile = stack.TopValue().Dereference(); + + // file name + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( storageFile[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___name ], fileName )); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( storageFile[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___path ], filePath )); + + // SPIFFS don't have date time details, so we are done here + } + #endif + + NANOCLR_CLEANUP(); + + // free buffer memory, if allocated + if(filePath != NULL) + { + platform_free(filePath); + } + + NANOCLR_CLEANUP_END(); +} + +HRESULT Library_win_storage_native_Windows_Storage_StorageFolder::CreateFolderNative___WindowsStorageStorageFolder__STRING__U4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Index storageFolderTypeDef; + CLR_RT_HeapBlock* storageFolder; + + const char* folderName; + const char* workingPath; + char workingDrive[DRIVE_LETTER_LENGTH]; + + CreationCollisionOption options; + + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + + static FILINFO fileInfo; + SYSTEMTIME fileInfoTime; + FRESULT operationResult; + char* folderPath = NULL; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // copy the first 2 letters of the path for the drive + // path is 'D:\folder\file.txt', so we need 'D:' + memcpy(workingDrive, pThis[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path ].DereferenceString()->StringText(), DRIVE_LETTER_LENGTH); + + // get creation collision options + options = (CreationCollisionOption)stack.Arg2().NumericByRef().u4; + + // get a pointer to the path in managed field + workingPath = pThis[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path ].DereferenceString()->StringText(); + + // get a pointer to the desired folder name + folderName = stack.Arg1().DereferenceString()->StringText(); + + folderPath = (char*)platform_malloc(2 * FF_LFN_BUF + 1); + + // sanity check for successfull malloc + if(folderPath == NULL) + { + // failed to allocate memory + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // clear working buffer + memset(folderPath, 0, 2 * FF_LFN_BUF + 1); + + // compose folder path + CombinePath(folderPath, workingPath, folderName); + + // check if folder exists + operationResult = f_stat(folderPath, &fileInfo); + + // folder doesn't exist + if (operationResult == FR_NO_FILE) + { + if (options == CreationCollisionOption_OpenIfExists) + { + // folder doesn't exist + NANOCLR_SET_AND_LEAVE(CLR_E_DIRECTORY_NOT_FOUND); + } + else + { + // create directory + operationResult = f_mkdir(folderPath); + + if(operationResult == FR_OK) + { + operationResult = f_stat(folderPath, &fileInfo); + } + else + { + // failed to create the folder + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_IO); + } + } + } + else + { + if (options == CreationCollisionOption_FailIfExists) + { + // folder already exists + NANOCLR_SET_AND_LEAVE(CLR_E_PATH_ALREADY_EXISTS); + } + } + + if(operationResult == FR_OK) + { + // compose return object + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef( "StorageFolder", "Windows.Storage", storageFolderTypeDef ); + + // create a + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(stack.PushValue(), storageFolderTypeDef)); + + // get a handle to the storage folder + storageFolder = stack.TopValue().Dereference(); + + // folder name + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( storageFolder[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___name ], folderName )); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( storageFolder[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path ], folderPath )); + + // get the date time details and fill in the managed field + // compute directory date + fileInfoTime = GetDateTime(fileInfo.fdate, fileInfo.ftime); + + // get a reference to the dateCreated managed field... + CLR_RT_HeapBlock& dateFieldRef = storageFolder[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___dateCreated ]; + CLR_INT64* pRes = (CLR_INT64*)&dateFieldRef.NumericByRef().s8; + // ...and set it with the fileInfoTime + *pRes = HAL_Time_ConvertFromSystemTime( &fileInfoTime ); + } + else + { + // failed to get folder details + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_IO); + } + + #elif (USE_SPIFFS_FOR_STORAGE == TRUE) + + // throw not supported exception because folders aren't supported in SPIFFS + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + #endif + + NANOCLR_CLEANUP(); + + // free buffer memory, if allocated + if(folderPath != NULL) + { + platform_free(folderPath); + } + + NANOCLR_CLEANUP_END(); +} + +HRESULT Library_win_storage_native_Windows_Storage_StorageFolder::DeleteFolderNative___VOID(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + + const char* workingPath; + // need extra room for the change dir command + char workingDrive[DRIVE_LETTER_LENGTH + 2]; + + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + + FRESULT operationResult; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the path in managed field + workingPath = pThis[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path].DereferenceString()->StringText(); + + // remove folder + operationResult = f_unlink(workingPath); + if (operationResult == FR_INVALID_NAME) + { + // Invalid path + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + else if (operationResult == FR_DENIED) + { + // this could be because the folder is not empty or because it's the current folder + + // change directory to the parent directory using f_chdir("2:..") + + // copy the first 2 letters of the path for the drive + // path is 'D:\folder\file.txt', so we need 'D:' + memcpy(workingDrive, pThis[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path ].DereferenceString()->StringText(), DRIVE_LETTER_LENGTH); + // make sure there is a terminator + workingDrive[2] = '\0'; + strcat(workingDrive, ".."); + + // change dir to parent + operationResult = f_chdir(workingDrive); + + // try remove again + operationResult = f_unlink(workingPath); + + if (operationResult == FR_DENIED) + { + // folder not empty + NANOCLR_SET_AND_LEAVE(CLR_E_DIRECTORY_NOT_EMPTY); + } + else if (operationResult != FR_OK) + { + // something else is failing + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_IO); + } + } + else if (operationResult != FR_OK) + { + // folder doesn't exist + #if (USE_SPIFFS_FOR_STORAGE == TRUE) + if(WORKING_DRIVE_IS_INTERNAL_DRIVE) + { + // this is the SPIFFS drive + // throw not supported exception because folders aren't supported in SPIFFS + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + } + else + { + #else + { + #endif + NANOCLR_SET_AND_LEAVE(CLR_E_DIRECTORY_NOT_FOUND); + } + } + + #elif (USE_SPIFFS_FOR_STORAGE == TRUE) + + // throw not supported exception because folders aren't supported in SPIFFS + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + #endif + + NANOCLR_CLEANUP(); + + NANOCLR_CLEANUP_END(); +} + +HRESULT Library_win_storage_native_Windows_Storage_StorageFolder::RenameFolderNative___VOID__STRING(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + + const char* workingPath; + const char* desiredPath; + char workingDrive[DRIVE_LETTER_LENGTH]; + + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + + FRESULT operationResult; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // copy the first 2 letters of the path for the drive + // path is 'D:\folder\file.txt', so we need 'D:' + memcpy(workingDrive, pThis[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path ].DereferenceString()->StringText(), DRIVE_LETTER_LENGTH); + + // get a pointer to the path in managed field + workingPath = pThis[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path].DereferenceString()->StringText(); + + // get a pointer to the desired folder name + desiredPath = stack.Arg1().DereferenceString()->StringText(); + + // rename folder + operationResult = f_rename(workingPath, desiredPath); + if (operationResult == FR_INVALID_NAME) + { + // invalid path + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + else if (operationResult != FR_OK) + { + // folder doesn't exist + #if (USE_SPIFFS_FOR_STORAGE == TRUE) + if(WORKING_DRIVE_IS_INTERNAL_DRIVE) + { + // this is the SPIFFS drive + // throw not supported exception because folders aren't supported in SPIFFS + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + } + else + { + #else + { + #endif + NANOCLR_SET_AND_LEAVE(CLR_E_DIRECTORY_NOT_FOUND); + } + } + + #elif (USE_SPIFFS_FOR_STORAGE == TRUE) + + // throw not supported exception because folders aren't supported in SPIFFS + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + #endif + + NANOCLR_CLEANUP(); + + NANOCLR_CLEANUP_END(); +} + +HRESULT Library_win_storage_native_Windows_Storage_StorageFolder::GetFolderNative___WindowsStorageStorageFolder__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Index storageFolderTypeDef; + CLR_RT_HeapBlock* storageFolder; + + const char* folderName; + const char* workingPath; + char* folderPath = NULL; + + #if (USE_SPIFFS_FOR_STORAGE == TRUE) + char workingDrive[DRIVE_LETTER_LENGTH]; + #endif + + #if ((HAL_USE_SDC == TRUE) || (HAL_USBH_USE_MSD == TRUE)) + + FILINFO fileInfo; + SYSTEMTIME fileInfoTime; + + FRESULT operationResult; + + CLR_INT64* pRes; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the path in managed field + workingPath = pThis[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path].DereferenceString()->StringText(); + + // get a pointer to the desired folder name + folderName = stack.Arg1().DereferenceString()->StringText(); + + folderPath = (char*)platform_malloc(2 * FF_LFN_BUF + 1); + + // sanity check for successfull malloc + if (folderPath == NULL) + { + // failed to allocate memory + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // clear working buffer + memset(folderPath, 0, 2 * FF_LFN_BUF + 1); + + // compose folder path + CombinePath(folderPath, workingPath, folderName); + + // check if directory exists + operationResult = f_stat(folderPath, &fileInfo); + if (operationResult != FR_OK) + { + // folder doesn't exist + #if (USE_SPIFFS_FOR_STORAGE == TRUE) + if(WORKING_DRIVE_IS_INTERNAL_DRIVE) + { + // this is the SPIFFS drive + // throw not supported exception because folders aren't supported in SPIFFS + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + } + else + { + #else + { + #endif + NANOCLR_SET_AND_LEAVE(CLR_E_DIRECTORY_NOT_FOUND); + } + } + else + { + // is this a file? + if ( !(fileInfo.fattrib & AM_DIR) ) + { + // Path represents a file + NANOCLR_SET_AND_LEAVE(CLR_E_DIRECTORY_NOT_FOUND); + } + else + { + // compose return object + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef("StorageFolder", "Windows.Storage", storageFolderTypeDef); + + // create a + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(stack.PushValue(), storageFolderTypeDef)); + + // get a handle to the storage folder + storageFolder = stack.TopValue().Dereference(); + + // folder name + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance(storageFolder[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___name], folderName)); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance(storageFolder[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path], folderPath)); + + // get the date time details and fill in the managed field + // compute directory date + fileInfoTime = GetDateTime(fileInfo.fdate, fileInfo.ftime); + + // get a reference to the dateCreated managed field... + CLR_RT_HeapBlock& dateFieldRef = storageFolder[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___dateCreated]; + pRes = (CLR_INT64*)&dateFieldRef.NumericByRef().s8; + // ...and set it with the fileInfoTime + *pRes = HAL_Time_ConvertFromSystemTime(&fileInfoTime); + } + } + + #elif (USE_SPIFFS_FOR_STORAGE == TRUE) + + // throw not supported exception because folders aren't supported in SPIFFS + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + #endif + + NANOCLR_CLEANUP(); + + // free buffer memory, if allocated + if (folderPath != NULL) + { + platform_free(folderPath); + } + + NANOCLR_CLEANUP_END(); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Storage/win_storage_native_target.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Storage/win_storage_native_target.h new file mode 100644 index 00000000..ac692517 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/Windows.Storage/win_storage_native_target.h @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#ifndef _WIN_STORAGE_NATIVE_TARGET_H_ +#define _WIN_STORAGE_NATIVE_TARGET_H_ + +#include +#include + +#define WORKING_DRIVE_IS_INTERNAL_DRIVE memcmp(workingDrive, INTERNAL_DRIVE_LETTER, sizeof(INTERNAL_DRIVE_LETTER) - 1) == 0 + +#endif //_WIN_STORAGE_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/WireProtocol_App_Interface.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/WireProtocol_App_Interface.c new file mode 100644 index 00000000..7582fbfc --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/WireProtocol_App_Interface.c @@ -0,0 +1,30 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +// declaration for wrapper function +extern int CLR_Messaging_ProcessPayload(WP_Message* msg); + +//////////////////////////////////////////////////// + +int WP_App_ProcessHeader(WP_Message* message) +{ + // check for reception buffer overflow + if(message->m_header.m_size > sizeof(receptionBuffer)) + { + return false; + } + + message->m_payload = receptionBuffer; + return true; +} + +int WP_App_ProcessPayload(WP_Message* message) +{ + return CLR_Messaging_ProcessPayload(message); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/WireProtocol_MonitorCommands.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/WireProtocol_MonitorCommands.c new file mode 100644 index 00000000..3a3646b0 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/WireProtocol_MonitorCommands.c @@ -0,0 +1,7 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +// file empty on purpose +// in nanoCLR the MonitorCommands are implemented in Debugger diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/mbedtls_entropy_hardware_pool.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/mbedtls_entropy_hardware_pool.c new file mode 100644 index 00000000..99a8416a --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/mbedtls_entropy_hardware_pool.c @@ -0,0 +1,32 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// Get len bytes of entropy from the hardware RNG. +int mbedtls_hardware_poll( void *data, unsigned char *output, size_t len, size_t *olen ) +{ + (void)data; + + // start random generator + rngStart(); + + for(size_t i = 0; i < len; i++) + { + // our generator returns 32bits numbers + *output = rngGenerateRandomNumber(); + + output++; + } + + // callers require this to be set + *olen = len; + + // stop random generator + rngStop(); + + return 0; +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoCRT.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoCRT.cpp new file mode 100644 index 00000000..10f90972 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoCRT.cpp @@ -0,0 +1,205 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include + +//--// +/* STDIO stubs */ +//--// + +#if !defined(BUILD_RTM) + +void hal_fprintf_SetLoggingCallback( LOGGING_CALLBACK fpn ) +{ + (void)fpn; + NATIVE_PROFILE_PAL_CRT(); + +} + +#endif + +//--// + +#if defined(PLATFORM_EMULATED_FLOATINGPOINT) + +// no floating point, fixed point + +int hal_snprintf_float( char* buffer, size_t len, const char* format, int32_t f ) +{ + NATIVE_PROFILE_PAL_CRT(); + + uint32_t i ; + uint32_t dec; + + if ( f < 0 ) + { + // negative number + i = (uint32_t) -f ; + dec = i & (( 1<>HAL_FLOAT_SHIFT); + + if (dec !=0) dec = (dec * (uint32_t)HAL_FLOAT_PRECISION + (1<< (HAL_FLOAT_SHIFT-1))) >>HAL_FLOAT_SHIFT; + + return hal_snprintf( buffer, len, "-%d.%03u", i, (uint32_t)dec); + + } + else + { + // positive number + i = (uint32_t) f ; + dec = f & (( 1<>HAL_FLOAT_SHIFT); + + if (dec !=0) dec = (dec * (uint32_t)HAL_FLOAT_PRECISION + (1<< (HAL_FLOAT_SHIFT-1))) >>HAL_FLOAT_SHIFT; + + return hal_snprintf( buffer, len, "%d.%03u", i, (uint32_t)dec); + } +} + +int hal_snprintf_double( char* buffer, size_t len, const char* format, int64_t& d ) +{ + NATIVE_PROFILE_PAL_CRT(); + + uint64_t i; + uint32_t dec; // 32 bit is enough for decimal part + + if ( d < 0 ) + { + // negative number + i = (uint64_t)-d; + + i += ((1 << (HAL_DOUBLE_SHIFT-1)) / HAL_DOUBLE_PRECISION); // add broad part of rounding increment before split + + dec = i & (( 1<> HAL_DOUBLE_SHIFT ; + + if (dec !=0) dec = (dec * HAL_DOUBLE_PRECISION + ((1 << (HAL_DOUBLE_SHIFT-1)) % HAL_DOUBLE_PRECISION)) >> HAL_DOUBLE_SHIFT; + + return hal_snprintf( buffer, len, "-%lld.%04u", (int64_t)i, (uint32_t)dec); + + } + else + { + + // positive number + i = (uint64_t)d; + + i += ((1 << (HAL_DOUBLE_SHIFT-1)) / HAL_DOUBLE_PRECISION); // add broad part of rounding increment before split + + dec = i & (( 1<> HAL_DOUBLE_SHIFT; + + if (dec !=0) dec = (dec * HAL_DOUBLE_PRECISION + ((1 << (HAL_DOUBLE_SHIFT-1)) % HAL_DOUBLE_PRECISION)) >> HAL_DOUBLE_SHIFT; + + return hal_snprintf( buffer, len, "%lld.%04u", (int64_t)i, (uint32_t)dec); + } +} + +#else + +#endif + +// because debug_printf needs to be called in both C and C++ we need a proxy to allow it to be called in 'C' +extern "C" { + +#if !defined(BUILD_RTM) + + void debug_printf(const char* format, ...) + { + char buffer[256]; + va_list arg_ptr; + + va_start( arg_ptr, format ); + + int len = vsnprintf( buffer, sizeof(buffer)-1, format, arg_ptr ); + + DebuggerPort_Write( HalSystemConfig.stdio, buffer, len, 0 ); // skip null terminator + + va_end( arg_ptr ); + } + +#else + __inline void debug_printf( const char *format, ... ) {} +#endif // !defined(BUILD_RTM) +} + +int hal_strcpy_s ( char* strDst, size_t sizeInBytes, const char* strSrc ) +{ + NATIVE_PROFILE_PAL_CRT(); +#undef strcpy + + size_t len; + if(strDst == NULL || strSrc == NULL || sizeInBytes == 0) {_ASSERTE(FALSE); return 1;} + + len = hal_strlen_s(strSrc); + if(sizeInBytes < len + 1) {_ASSERTE(FALSE); return 1;} + + strcpy( strDst, strSrc ); + return 0; + +#define strcpy DoNotUse_*strcpy [] +} + +int hal_strncpy_s ( char* strDst, size_t sizeInBytes, const char* strSrc, size_t count ) +{ + NATIVE_PROFILE_PAL_CRT(); +#undef strncpy + if(strDst == NULL || strSrc == NULL || sizeInBytes == 0) {_ASSERTE(FALSE); return 1;} + + if (sizeInBytes < count + 1) + { + _ASSERTE(FALSE); + strDst[0] = 0; + return 1; + } + + strDst[count] = 0; + strncpy( strDst, strSrc, count ); + return 0; + +#define strncpy DoNotUse_*strncpy [] +} + +size_t hal_strlen_s (const char * str) +{ + NATIVE_PROFILE_PAL_CRT(); + + const char *eos = str; + while( *eos++ ) ; + return( eos - str - 1 ); +} + +int hal_strncmp_s ( const char* str1, const char* str2, size_t num ) +{ + NATIVE_PROFILE_PAL_CRT(); +#undef strncmp + if(str1 == NULL || str2 == NULL) {_ASSERTE(FALSE); return 1;} + + return strncmp( str1, str2, num ); + +#define strncmp DoNotUse_*strncmp [] +} + +// Compares 2 ASCII strings case insensitive. Does not take locale into account. +int hal_stricmp( const char * dst, const char * src ) +{ + int f = 0, l = 0; + + do + { + if ( ((f = (unsigned char)(*(dst++))) >= 'A') && (f <= 'Z') ) + { + f -= 'A' - 'a'; + } + if ( ((l = (unsigned char)(*(src++))) >= 'A') && (l <= 'Z') ) + { + l -= 'A' - 'a'; + } + } + while ( f && (f == l) ); + + return(f - l); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Devices.Can/nf_devices_can_native_nanoFramework_Devices_Can_CanController.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Devices.Can/nf_devices_can_native_nanoFramework_Devices_Can_CanController.cpp new file mode 100644 index 00000000..798fa59a --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Devices.Can/nf_devices_can_native_nanoFramework_Devices_Can_CanController.cpp @@ -0,0 +1,460 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "nf_devices_can_native_target.h" + +// define these types here to make it shorter and improve code readability +typedef Library_nf_devices_can_native_nanoFramework_Devices_Can_CanSettings CanSettings; +typedef Library_nf_devices_can_native_nanoFramework_Devices_Can_CanMessage ManagedCanMessage; + +static void RxMessage(CANDriver *canp, uint32_t flags) +{ + NATIVE_INTERRUPT_START + + NF_PAL_CAN* palCan; + uint8_t controllerId = 0; + CANRxFrame rxMsg; + + (void)flags; + + #if STM32_CAN_USE_CAN1 + if (canp == &CAND1) + { + palCan = &Can1_PAL; + controllerId = 1; + } + #endif + #if STM32_CAN_USE_CAN2 + if (canp == &CAND2) + { + palCan = &Can2_PAL; + controllerId = 2; + } + #endif + #if STM32_CAN_USE_CAN3 + if (canp == &CAND3) + { + palCan = &Can3_PAL; + controllerId = 3; + } + #endif + + while (canReceiveTimeout(palCan->Driver, CAN_ANY_MAILBOX, &rxMsg, TIME_IMMEDIATE) == MSG_OK) + { + // got message + + // store message in the CAN buffer + // don't care about the success of the operation, if it's full we are droping the message anyway + palCan->MsgRingBuffer.Push(rxMsg); + + // fire event for CAN message received + PostManagedEvent( EVENT_CAN, 0, controllerId, CanEvent_MessageReceived ); + } + + NATIVE_INTERRUPT_END +} + +///////////////////////////////////////////////////////// +// CAN PAL strucs delcared in nf_devices_can_native.h // +///////////////////////////////////////////////////////// +#if STM32_CAN_USE_CAN1 + NF_PAL_CAN Can1_PAL; +#endif +#if STM32_CAN_USE_CAN2 + NF_PAL_CAN Can2_PAL; +#endif +#if STM32_CAN_USE_CAN3 + NF_PAL_CAN Can3_PAL; +#endif + +HRESULT Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController::WriteMessage___VOID__nanoFrameworkDevicesCanCanMessage( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + uint32_t id; + CanMessageIdType msgIdType; + CanMessageFrameType msgFrameType; + CLR_RT_HeapBlock_Array* message; + CANTxFrame txmsg; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + CLR_RT_HeapBlock* pMessage = stack.Arg1().Dereference(); + + // get controller index + uint8_t controllerIndex = (uint8_t)(pThis[ FIELD___controllerId ].NumericByRef().s4); + + // dereference message fields + id = (uint32_t)(pMessage[ Library_nf_devices_can_native_nanoFramework_Devices_Can_CanMessage::FIELD___id ].NumericByRef().u4); + msgIdType = (CanMessageIdType)(pMessage[ Library_nf_devices_can_native_nanoFramework_Devices_Can_CanMessage::FIELD___identifierType ].NumericByRefConst().u1); + msgFrameType = (CanMessageFrameType)(pMessage[ Library_nf_devices_can_native_nanoFramework_Devices_Can_CanMessage::FIELD___frameType ].NumericByRefConst().u1); + + // get message to transmite + message = pMessage[ Library_nf_devices_can_native_nanoFramework_Devices_Can_CanMessage::FIELD___message ].DereferenceArray(); + + // message max length is 8 bytes + if(message->m_numOfElements > 8) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + + // compose the transmite packet to send + if(message != NULL) + { + // copy message to structure + memcpy(txmsg.data8, (uint8_t*)message->GetFirstElement(), message->m_numOfElements); + } + // message id according to it's type + if(msgIdType == CanMessageIdType_SID) + { + txmsg.IDE = CAN_IDE_STD; + txmsg.SID = id; + } + else + { + txmsg.IDE = CAN_IDE_EXT; + txmsg.EID = id; + } + // remote transmission request + txmsg.RTR = msgFrameType == CanMessageFrameType_Data ? CAN_RTR_DATA : CAN_RTR_REMOTE; + // data length + txmsg.DLC = message->m_numOfElements; + + switch (controllerIndex) + { + #if STM32_CAN_USE_CAN1 + case 1: + canTransmit(Can1_PAL.Driver, CAN_ANY_MAILBOX, &txmsg, TIME_MS2I(100)); + break; + #endif + #if STM32_CAN_USE_CAN2 + case 2: + canTransmit(Can2_PAL.Driver, CAN_ANY_MAILBOX, &txmsg, TIME_MS2I(100)); + break; + #endif + #if STM32_CAN_USE_CAN3 + case 3: + canTransmit(Can3_PAL.Driver, CAN_ANY_MAILBOX, &txmsg, TIME_MS2I(100)); + break; + #endif + default: + // this CAN bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController::GetMessage___nanoFrameworkDevicesCanCanMessage( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Index canMessageTypeDef; + CLR_RT_HeapBlock* canMessage = NULL; + + CANRxFrame canFrame; + NF_PAL_CAN* palCan; + uint8_t controllerIndex; + size_t messageCount = 0; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get controller index + controllerIndex = (uint8_t)(pThis[ FIELD___controllerId ].NumericByRef().s4); + + // get the PAL struct for this CAN bus + switch (controllerIndex) + { + + #if STM32_CAN_USE_CAN1 + case 1: + palCan = &Can1_PAL; + + break; + #endif + + #if STM32_CAN_USE_CAN2 + case 2: + palCan = &Can2_PAL; + + break; + #endif + + #if STM32_CAN_USE_CAN3 + case 3: + palCan = &Can3_PAL; + + break; + #endif + + default: + // this CAN bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // get next CAN frame from ring buffer + messageCount = palCan->MsgRingBuffer.Pop(&canFrame, 1); + + // find type, don't bother checking the result as the type exists for sure + g_CLR_RT_TypeSystem.FindTypeDef( "CanMessage", "nanoFramework.Devices.Can", canMessageTypeDef ); + + // create an instance of + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(stack.PushValue(), canMessageTypeDef)); + + canMessage = stack.TopValue().Dereference(); + + if(messageCount == 1) + { + // we have a message + + // get pointer to each managed field and set appropriate value + CLR_RT_HeapBlock& identifierTypeFieldRef = canMessage[ ManagedCanMessage::FIELD___identifierType ]; + CLR_RT_HeapBlock& frameTypeFieldRef = canMessage[ ManagedCanMessage::FIELD___frameType ]; + + // get message frame type + uint8_t* fr = (uint8_t*)&frameTypeFieldRef.NumericByRef().u1; + *fr = canFrame.RTR; + + // get message id type + uint8_t* idType = (uint8_t*)&identifierTypeFieldRef.NumericByRef().u1; + *idType = canFrame.IDE; + + // get message id + CLR_RT_HeapBlock& idFieldRef = canMessage[ ManagedCanMessage::FIELD___id ]; + uint32_t* id = (uint32_t*)&idFieldRef.NumericByRef().u4; + + if(canFrame.IDE == 0) + { + *id = canFrame.SID; + } + else + { + *id = canFrame.EID; + } + + // get data if any + if(canFrame.data8) + { + CLR_RT_HeapBlock& dataArrayField = canMessage[ ManagedCanMessage::FIELD___message ]; + // create an array of + NANOCLR_CHECK_HRESULT( CLR_RT_HeapBlock_Array::CreateInstance( dataArrayField, 8, g_CLR_RT_WellKnownTypes.m_UInt8 ) ); + + // get a pointer to the first object in the array + CLR_UINT8* dataBuffer = (CLR_UINT8*)(dataArrayField.DereferenceArray()->GetFirstElement()); + memcpy(dataBuffer, &canFrame.data8[0], 8); + } + } + else + { + // no more messages, return null + stack.SetResult_Object(NULL); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController::DisposeNative___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + uint8_t controllerIndex; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get controller index + controllerIndex = (uint8_t)(pThis[ FIELD___controllerId ].NumericByRef().s4); + + // init the PAL struct for this CAN bus and assign the respective driver + // all this occurs if not already done + switch (controllerIndex) + { + #if STM32_CAN_USE_CAN1 + case 1: + Can1_PAL.Driver = NULL; + // stop CAN + canStop(&CAND1); + break; + #endif + + #if STM32_CAN_USE_CAN2 + case 2: + Can2_PAL.Driver = NULL; + // stop CAN + canStop(&CAND2); + break; + #endif + + #if STM32_CAN_USE_CAN3 + case 3: + Can3_PAL.Driver = NULL; + // stop CAN + canStop(&CAND3); + break; + #endif + + default: + // this CAN bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + NF_PAL_CAN* palCan = NULL; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the managed spi connectionSettings object instance + CLR_RT_HeapBlock* pConfig = pThis[ FIELD___settings ].Dereference(); + + // get controller index + uint8_t controllerIndex = (uint8_t)(pThis[ FIELD___controllerId ].NumericByRef().s4); + + // init the PAL struct for this CAN bus and assign the respective driver + // all this occurs if not already done + switch (controllerIndex) + { + #if STM32_CAN_USE_CAN1 + case 1: + Init_Can1(); + ConfigPins_CAN1(); + Can1_PAL.Driver = &CAND1; + palCan = &Can1_PAL; + break; + #endif + #if STM32_CAN_USE_CAN2 + case 2: + Init_Can2(); + ConfigPins_CAN2(); + Can2_PAL.Driver = &CAND2; + palCan = &Can2_PAL; + break; + #endif + #if STM32_CAN_USE_CAN3 + case 3: + Init_Can3(); + ConfigPins_CAN3(); + Can3_PAL.Driver = &CAND3; + palCan = &Can3_PAL; + break; + #endif + default: + // this CAN bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // get config + palCan->Configuration = { + CAN_MCR_ABOM | CAN_MCR_AWUM | CAN_MCR_TXFP, + (uint32_t)( + CAN_BTR_SJW((uint8_t)pConfig[ CanSettings::FIELD___syncJumpWidth ].NumericByRef().u1) | + CAN_BTR_TS2((uint8_t)pConfig[ CanSettings::FIELD___phaseSegment2 ].NumericByRef().u1) | + CAN_BTR_TS1((uint8_t)pConfig[ CanSettings::FIELD___phaseSegment1 ].NumericByRef().u1) | + CAN_BTR_BRP((uint8_t)pConfig[ CanSettings::FIELD___baudRatePrescaler ].NumericByRef().u1) + ) + }; + + // start CAN + canStart(palCan->Driver, &palCan->Configuration); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController::NativeUpdateCallbacks___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NF_PAL_CAN* palCan = NULL; + bool callbacksRegistered; + uint8_t controllerIndex; + + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get controller index + controllerIndex = (uint8_t)(pThis[ FIELD___controllerId ].NumericByRef().s4); + + // flag to determine if there are any callbacks registered in managed code + callbacksRegistered = (pThis[ FIELD___callbacks ].Dereference() != NULL); + + switch (controllerIndex) + { + #if STM32_CAN_USE_CAN1 + case 1: + palCan = &Can1_PAL; + break; + #endif + #if STM32_CAN_USE_CAN2 + case 2: + palCan = &Can2_PAL; + break; + #endif + #if STM32_CAN_USE_CAN3 + case 3: + palCan = &Can3_PAL; + break; + #endif + default: + // this CAN bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // need to start CAN again + // it's safe to stop first + canStop(palCan->Driver); + + if(callbacksRegistered) + { + // there is someone listening on the managed end + palCan->Driver->rxfull_cb = RxMessage; + } + else + { + // no one listening, OK to remove + palCan->Driver->rxfull_cb = NULL; + } + + // start CAN + canStart(palCan->Driver, &palCan->Configuration); + + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_devices_can_native_nanoFramework_Devices_Can_CanController::GetDeviceSelector___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // declare the device selector string whose max size is "SPI1,SPI2,SPI3,SPI4,SPI5,SPI6," + terminator and init with the terminator + char deviceSelectorString[ 30 + 1] = { 0 }; + + #if STM32_CAN_USE_CAN1 + strcat(deviceSelectorString, "CAN1,"); + #endif + #if STM32_CAN_USE_CAN2 + strcat(deviceSelectorString, "CAN2,"); + #endif + #if STM32_CAN_USE_CAN3 + strcat(deviceSelectorString, "CAN3,"); + #endif + + // replace the last comma with a terminator + deviceSelectorString[hal_strlen_s(deviceSelectorString) - 1] = '\0'; + + // because the caller is expecting a result to be returned + // we need set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + stack.SetResult_String(deviceSelectorString); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Devices.Can/nf_devices_can_native_target.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Devices.Can/nf_devices_can_native_target.h new file mode 100644 index 00000000..44211206 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Devices.Can/nf_devices_can_native_target.h @@ -0,0 +1,77 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#ifndef _NF_DEVICES_CAN_NATIVE_TARGET_H_ +#define _NF_DEVICES_CAN_NATIVE_TARGET_H_ + +#include +#include "target_nf_devices_can_config.h" +#include + + +// struct representing the CAN +struct NF_PAL_CAN +{ + CANDriver* Driver; + CANConfig Configuration; + thread_t* ReceiverThread; + + HAL_RingBuffer MsgRingBuffer; + CANRxFrame* MsgBuffer; +}; + +/////////////////////////////////////////// +// declaration of the CAN PAL strucs // +/////////////////////////////////////////// +#if STM32_CAN_USE_CAN1 + extern NF_PAL_CAN Can1_PAL; +#endif +#if STM32_CAN_USE_CAN2 + extern NF_PAL_CAN Can2_PAL; +#endif +#if STM32_CAN_USE_CAN3 + extern NF_PAL_CAN Can3_PAL; +#endif + +// the following macro defines a function that configures the GPIO pins for a STM32 CAN +// it gets called in the can_lld_start function// this is required because the CAN peripherals can use multiple GPIO configuration combinations +#define CAN_CONFIG_PINS(num, gpio_port_tx, gpio_port_rx, tx_pin, rx_pin, alternate_function) void ConfigPins_CAN##num() { \ + palSetPadMode(gpio_port_tx, tx_pin, PAL_MODE_ALTERNATE(alternate_function) | PAL_STM32_OTYPE_PUSHPULL \ + | PAL_STM32_OSPEED_HIGHEST | PAL_STM32_MODE_ALTERNATE); \ + palSetPadMode(gpio_port_rx, rx_pin, PAL_MODE_ALTERNATE(alternate_function) | PAL_STM32_OTYPE_PUSHPULL \ + | PAL_STM32_OSPEED_HIGHEST | PAL_STM32_MODE_ALTERNATE); \ +} + +/////////////////////////////////////////////////////////////////////////////////////////// +// when a CAN is defined the declarations below will have the real function/configuration +// in the target folder @ target_nf_devices_can_config.cpp +/////////////////////////////////////////////////////////////////////////////////////////// +void ConfigPins_CAN1(); +void ConfigPins_CAN2(); +void ConfigPins_CAN3(); + + +///////////////////////////////////// +// CAN Msg buffers // +// these live in the target folder // +///////////////////////////////////// +extern CANRxFrame Can1_MsgBuffer[]; +extern CANRxFrame Can2_MsgBuffer[]; +extern CANRxFrame Can3_MsgBuffer[]; + +// +#define CAN_INIT(num, buffer_size) void Init_Can##num() { \ + Can##num##_PAL.MsgBuffer = Can##num##_MsgBuffer; \ + Can##num##_PAL.MsgRingBuffer.Initialize( Can##num##_PAL.MsgBuffer, buffer_size); \ +} + +// when a CAN is defined the declarations below will have the real function/configuration +// in the target folder @ target_nf_devices_can_config.cpp +void Init_Can1(); +void Init_Can2(); +void Init_Can3(); + +#endif //_NF_DEVICES_CAN_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Devices.OneWire/nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Devices.OneWire/nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController.cpp new file mode 100644 index 00000000..08345362 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Devices.OneWire/nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController.cpp @@ -0,0 +1,261 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "nf_devices_onewire_native_target.h" + +// working thread to execute long running 1-Wire operations +static thread_t* OneWireWorkingThread; + +// struct for working threads +OneWireFindStruct FindStruct; + +// ChibiOS OneWire working thread +static THD_FUNCTION(OneWireFindFirstWorkingThread, arg) +{ + msg_t deviceFound; + + OneWireFindStruct* findStruct = (OneWireFindStruct*)arg; + + deviceFound = oneWireFindFirst(findStruct->DoReset, findStruct->AlarmOnly); + + // fire event for 1-Wire operarion completed + Events_Set(SYSTEM_EVENT_FLAG_ONEWIRE_MASTER); + + chThdExit(deviceFound); +} + +static THD_FUNCTION(OneWireFindNextWorkingThread, arg) +{ + msg_t deviceFound; + + OneWireFindStruct* findStruct = (OneWireFindStruct*)arg; + + deviceFound = oneWireFindNext(findStruct->DoReset, findStruct->AlarmOnly); + + // fire event for 1-Wire operarion completed + Events_Set(SYSTEM_EVENT_FLAG_ONEWIRE_MASTER); + + chThdExit(deviceFound); +} + + +HRESULT Library_nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController::TouchReset___BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + volatile bool reset = oneWireTouchReset(); + stack.SetResult_Boolean( reset ) ; + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController::TouchBit___BOOLEAN__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + bool value = stack.Arg1().NumericByRefConst().u1 != 0; + + stack.SetResult_Boolean( oneWireTouchBit(value) ) ; + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController::TouchByte___U1__U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + uint8_t value = (uint8_t)stack.Arg1().NumericByRefConst().u1; + uint8_t result = oneWireTouchByte(value); + stack.SetResult_U1( result ) ; + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController::WriteByte___U1__U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + uint8_t cmd = (uint8_t)stack.Arg1().NumericByRefConst().u1; + uint8_t result = oneWireWriteByte(cmd); + stack.SetResult_U1( result ) ; + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController::ReadByte___U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + uint8_t result = oneWireReadByte(); + stack.SetResult_U1( result ) ; + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController::FindFirstDevice___BOOLEAN__BOOLEAN__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + uint8_t* serialNumberPointer; + msg_t oneWireOperationResult = FALSE; + + CLR_RT_HeapBlock hbTimeout; + CLR_INT64* timeout; + bool eventResult = true; + + // set an infinite timeout to wait forever for the operation to complete + // this value has to be in ticks to be properly loaded by SetupTimeoutFromTicks() below + hbTimeout.SetInteger((CLR_INT64)-1); + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks( hbTimeout, timeout )); + + // this is going to be used to check for the right event in case of simultaneous 1-Wire operations + if(stack.m_customState == 1) + { + FindStruct.DoReset = stack.Arg1().NumericByRefConst().u1 != 0; + FindStruct.AlarmOnly = stack.Arg2().NumericByRefConst().u1 != 0; + + // because the 1-Wire bus is shared, acquire the module + oneWireAcquireModule(); + + // spawn working thread to perform the 1-Wire operations + OneWireWorkingThread = chThdCreateFromHeap(NULL, THD_WORKING_AREA_SIZE(256), + "OWWT", NORMALPRIO, OneWireFindFirstWorkingThread, &FindStruct); + + // bump custom state + stack.m_customState = 2; + } + + while(eventResult) + { + if(OneWireWorkingThread->state == CH_STATE_FINAL) + { + // OneWire working thread is now complete + break; + } + + // non-blocking wait allowing other threads to run while we wait for the 1-Wire operations to complete + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_OneWireMaster, eventResult )); + } + + if(eventResult) + { + // event occurred + + // ChibiOS requirement: need to call chThdWait for working thread in order to have it's memory released to the heap, otherwise it won't be returned + oneWireOperationResult = chThdWait(OneWireWorkingThread); + + oneWireReleaseModule(); + + // get the result from the working thread execution + if(oneWireOperationResult) + { + // if a device was found update serialNumber field in managed class + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the serial number field in the OneWireController instance + CLR_RT_HeapBlock_Array* serialNumberField = pThis[ FIELD___serialNumber ].DereferenceArray(); + + _ASSERTE(serialNumberField->m_numOfElements == 8); + + // get a pointer to the first element of the byte array + serialNumberPointer = (uint8_t*)serialNumberField->GetFirstElement(); + + oneWireSerialNum(serialNumberPointer, TRUE); + } + } + + // pop timeout heap block from stack + stack.PopValue(); + + // set result + stack.SetResult_Boolean( oneWireOperationResult ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController::FindNextDevice___BOOLEAN__BOOLEAN__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + uint8_t* serialNumberPointer; + msg_t oneWireOperationResult = FALSE; + + CLR_RT_HeapBlock hbTimeout; + CLR_INT64* timeout; + bool eventResult = true; + + // set an infinite timeout to wait forever for the operation to complete + // this value has to be in ticks to be properly loaded by SetupTimeoutFromTicks() below + hbTimeout.SetInteger((CLR_INT64)-1); + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks( hbTimeout, timeout )); + + // this is going to be used to check for the right event in case of simultaneous 1-Wire operations + if(stack.m_customState == 1) + { + FindStruct.DoReset = stack.Arg1().NumericByRefConst().u1 != 0; + FindStruct.AlarmOnly = stack.Arg2().NumericByRefConst().u1 != 0; + + // because the 1-Wire bus is shared, acquire the module + oneWireAcquireModule(); + + // spawn working thread to perform the 1-Wire operations + OneWireWorkingThread = chThdCreateFromHeap(NULL, THD_WORKING_AREA_SIZE(256), + "OWWT", NORMALPRIO, OneWireFindNextWorkingThread, &FindStruct); + + // bump custom state + stack.m_customState = 2; + } + + while(eventResult) + { + if(OneWireWorkingThread->state == CH_STATE_FINAL) + { + // OneWire working thread is now complete + break; + } + + // non-blocking wait allowing other threads to run while we wait for the 1-Wire operations to complete + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_OneWireMaster, eventResult )); + } + + if(eventResult) + { + // event occurred + + // ChibiOS requirement: need to call chThdWait for working thread in order to have it's memory released to the heap, otherwise it won't be returned + oneWireOperationResult = chThdWait(OneWireWorkingThread); + + oneWireReleaseModule(); + + // get the result from the working thread execution + if(oneWireOperationResult) + { + // update serialNumber field + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the serial number field in the OneWireController instance + CLR_RT_HeapBlock_Array* serialNumberField = pThis[ FIELD___serialNumber ].DereferenceArray(); + + _ASSERTE(serialNumberField->m_numOfElements == 8); + + // get a pointer to the first element of the byte array + serialNumberPointer = (uint8_t*)serialNumberField->GetFirstElement(); + + oneWireSerialNum(serialNumberPointer, TRUE); + } + } + + // pop timeout heap block from stack + stack.PopValue(); + + // set result + stack.SetResult_Boolean( oneWireOperationResult ); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Devices.OneWire/nf_devices_onewire_native_target.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Devices.OneWire/nf_devices_onewire_native_target.h new file mode 100644 index 00000000..f89b8d1c --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Devices.OneWire/nf_devices_onewire_native_target.h @@ -0,0 +1,28 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _NF_DEVICES_ONEWIRE_NATIVE_TARGET_H_ +#define _NF_DEVICES_ONEWIRE_NATIVE_TARGET_H_ + +#include +#include +#include + +// struct with parameters for 1-Wire working thread +struct OneWireFindStruct +{ + bool DoReset; + bool AlarmOnly; +}; + +// the following macro defines a function that configures the GPIO pins for a STM32 UART/USART +// it gets called in the oneWire_lld_start function +// this is required because the UART/USART peripherals can use multiple GPIO configuration combinations +#define UART_CONFIG_PINS(num, gpio_port_tx, tx_pin, alternate_function) void ConfigPins_UART##num() { \ + palSetPadMode(gpio_port_tx, tx_pin, PAL_MODE_ALTERNATE(alternate_function) | PAL_STM32_OTYPE_OPENDRAIN \ + | PAL_MODE_INPUT_PULLUP | PAL_STM32_OSPEED_HIGHEST | PAL_STM32_MODE_ALTERNATE); \ +} + +#endif //_NF_DEVICES_ONEWIRE_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Hardware.Stm32/nf_hardware_stm32_native.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Hardware.Stm32/nf_hardware_stm32_native.cpp new file mode 100644 index 00000000..d6a2cd9a --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Hardware.Stm32/nf_hardware_stm32_native.cpp @@ -0,0 +1,62 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "nf_hardware_stm32_native.h" +#include + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_Power::get_WakeupReason___STATIC__nanoFrameworkHardwareStm32PowerWakeupReasonType, + Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_Power::DisableWakeupPin___STATIC__VOID__nanoFrameworkHardwareStm32PowerWakeupPin, + Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_Power::EnableWakeupPin___STATIC__VOID__nanoFrameworkHardwareStm32PowerWakeupPin, + Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_Power::NativeEnterStandbyMode___STATIC__VOID, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_BackupMemory::ReadBytes___STATIC__VOID__U4__SZARRAY_U1, + Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_BackupMemory::WriteBytes___STATIC__VOID__U4__SZARRAY_U1, + Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_BackupMemory::GetSize___STATIC__I4, + NULL, + NULL, + Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_RTC::GetAlarm___STATIC__mscorlibSystemDateTime, + Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_RTC::Native_RTC_SetAlarm___STATIC__VOID__U1__U1__U1__U1, + NULL, + NULL, + NULL, + Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_Utilities::NativeGetDeviceUniqueId___STATIC__VOID__SZARRAY_U1, + Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_Utilities::NativeGetDeviceId___STATIC__U4, + Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_Utilities::NativeGetDeviceRevisionId___STATIC__U4, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Hardware_Stm32 = +{ + "nanoFramework.Hardware.Stm32", + 0x3E87EA8A, + method_lookup, + { 100, 0, 4, 3 } +}; diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Hardware.Stm32/nf_hardware_stm32_native.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Hardware.Stm32/nf_hardware_stm32_native.h new file mode 100644 index 00000000..d14ea279 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Hardware.Stm32/nf_hardware_stm32_native.h @@ -0,0 +1,64 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _NF_HARDWARE_STM32_NATIVE_H_ +#define _NF_HARDWARE_STM32_NATIVE_H_ + +#include +#include +#include + +struct Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_Power +{ + NANOCLR_NATIVE_DECLARE(get_WakeupReason___STATIC__nanoFrameworkHardwareStm32PowerWakeupReasonType); + NANOCLR_NATIVE_DECLARE(DisableWakeupPin___STATIC__VOID__nanoFrameworkHardwareStm32PowerWakeupPin); + NANOCLR_NATIVE_DECLARE(EnableWakeupPin___STATIC__VOID__nanoFrameworkHardwareStm32PowerWakeupPin); + NANOCLR_NATIVE_DECLARE(NativeEnterStandbyMode___STATIC__VOID); + + //--// + +}; + +struct Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_BackupMemory +{ + static const int FIELD_STATIC___size = 0; + + NANOCLR_NATIVE_DECLARE(ReadBytes___STATIC__VOID__U4__SZARRAY_U1); + NANOCLR_NATIVE_DECLARE(WriteBytes___STATIC__VOID__U4__SZARRAY_U1); + NANOCLR_NATIVE_DECLARE(GetSize___STATIC__I4); + + //--// + + // need to address the fact that the majority of the series have 32 bits wide registers and F1 has 16bits wide. + // the backup size is calculated with the number of available backup registers and their size (in bytes) + static const int BACKUP_SIZE = RTC_BKP_NUMBER * sizeof(RTC_BKP0R_Msk); +}; + +struct Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_RTC +{ + NANOCLR_NATIVE_DECLARE(GetAlarm___STATIC__mscorlibSystemDateTime); + NANOCLR_NATIVE_DECLARE(Native_RTC_SetAlarm___STATIC__VOID__U1__U1__U1__U1); + + //--// + +}; + +struct Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_Utilities +{ + static const int FIELD_STATIC___deviceUniqueId = 1; + static const int FIELD_STATIC___deviceId = 2; + static const int FIELD_STATIC___deviceRevisionId = 3; + + NANOCLR_NATIVE_DECLARE(NativeGetDeviceUniqueId___STATIC__VOID__SZARRAY_U1); + NANOCLR_NATIVE_DECLARE(NativeGetDeviceId___STATIC__U4); + NANOCLR_NATIVE_DECLARE(NativeGetDeviceRevisionId___STATIC__U4); + + //--// + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Hardware_Stm32; + +#endif //_NF_HARDWARE_STM32_NATIVE_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Hardware.Stm32/nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_BackupMemory.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Hardware.Stm32/nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_BackupMemory.cpp new file mode 100644 index 00000000..d75a399d --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Hardware.Stm32/nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_BackupMemory.cpp @@ -0,0 +1,245 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "nf_hardware_stm32_native.h" + + +HRESULT Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_BackupMemory::ReadBytes___STATIC__VOID__U4__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + uint32_t position = stack.Arg0().NumericByRef().u4; + + // dereference the data buffer from the argument + CLR_RT_HeapBlock_Array* buffer = stack.Arg1().DereferenceArray(); + // get a the pointer to the byffer by using the first element of the array + uint8_t* data = buffer->GetFirstElement(); + // get the length of the data buffer + uint32_t dataLength = buffer->m_numOfElements; + + // address of bkp register 0 + __IO uint32_t* baseAddress = &(RTC->BKP0R); + uint8_t* storeAddress = ((uint8_t*)baseAddress + position); + uint32_t* registerAddress = NULL; + uint32_t tempRegisterValue; + uint32_t counter = 0; + uint32_t remainder; + int32_t index = 3; + + // sanity check for out of range position + if(position > (BACKUP_SIZE - 1) ) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + // sanity check for over sized data buffer + if( (position + dataLength) > BACKUP_SIZE) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + + // check if the store address is starting at a register address boundary + remainder = (uint32_t)((uint32_t*)storeAddress) % sizeof(RTC_BKP0R_Msk); + + if(remainder > 0) + { + // read register + registerAddress = (uint32_t*)(storeAddress - remainder); + tempRegisterValue = *registerAddress; + + // adjust remainder to the amount of bytes to move + remainder = 4 - remainder; + + do + { + *data = (uint8_t)(tempRegisterValue >> ( (remainder - 1) * 8)); + data++; + remainder--; + counter++; + } + while(remainder && (counter < dataLength)); + registerAddress++; + } + + // keep reading into the buffer if there enough bytes + if( (dataLength - counter) >= 4) + { + // load register + tempRegisterValue = *registerAddress; + + do + { + *data = (uint8_t)(tempRegisterValue >> (index-- * 8)); + data++; + counter++; + + if(index < 0) + { + index = 3; + registerAddress++; + + // is there enough data in buffer for another round + if( (dataLength - counter) < 4) + { + // no, exit loop + break; + } + + // load register + tempRegisterValue = *registerAddress; + } + } + while(1); + } + + // now read the remaining bytes, if any + if((dataLength - counter) > 0) + { + remainder = dataLength - counter; + + // read register + tempRegisterValue = *registerAddress; + + // adjust remainder to the amount of bytes to move + remainder = 4 - remainder; + + do + { + *data = (uint8_t)(tempRegisterValue >> (remainder * 8)); + remainder--; + data++; + counter++; + } + while(remainder); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_BackupMemory::WriteBytes___STATIC__VOID__U4__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + // get position to write to + uint32_t position = stack.Arg0().NumericByRef().u4; + + // dereference the data buffer from the argument + CLR_RT_HeapBlock_Array* buffer = stack.Arg1().DereferenceArray(); + // get a the pointer to the byffer by using the first element of the array + uint8_t* data = buffer->GetFirstElement(); + // get the length of the data buffer + uint32_t dataLength = buffer->m_numOfElements; + + // address of bkp register 0 + __IO uint32_t* baseAddress = &(RTC->BKP0R); + uint8_t* storeAddress = ((uint8_t*)baseAddress + position); + uint32_t* registerAddress = NULL; + uint32_t tempRegisterValue; + uint32_t counter = 0; + uint32_t remainder; + int32_t index = 3; + + // sanity check for out of range position + if(position > (BACKUP_SIZE - 1) ) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + // sanity check for over sized data buffer + if( (position + dataLength) > BACKUP_SIZE) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + + // write has to be done register wide, so if a write address is "in the middle" of a register, need to read it first and overwrite as required + // this can happen at the begining and/or at the end of the buffer + + // check if the store address is starting at a register address boundary + remainder = (uint32_t)((uint32_t*)storeAddress) % sizeof(RTC_BKP0R_Msk); + + if(remainder > 0) + { + // read register + registerAddress = (uint32_t*)(storeAddress - remainder); + tempRegisterValue = *registerAddress; + + // adjust remainder to the amount of bytes to move + remainder = 4 - remainder; + + // clear the bytes we'll be filling + tempRegisterValue &= (uint32_t)(0xFFFFFF00 << ( (remainder - 1) * 8)); + + do + { + tempRegisterValue |= (uint32_t)((uint32_t)*data << ( (remainder - 1) * 8)); + remainder--; + data++; + counter++; + } + while(remainder && (counter < dataLength)); + + // write back register + *registerAddress = tempRegisterValue; + registerAddress++; + } + + // keep processing the buffer if there enough bytes + if( (dataLength - counter) >= 4) + { + // clear register + *registerAddress = 0; + + do + { + *registerAddress |= (uint32_t)((uint32_t)*data << (index-- * 8)); + data++; + counter++; + + if(index < 0) + { + index = 3; + registerAddress++; + + // is there enough data in buffer for another round + if( (dataLength - counter) < 4) + { + // no, exit loop + break; + } + + // clear register + *registerAddress = 0; + } + } + while(1); + } + + // take care of the remaining bytes, if any + if((dataLength - counter) > 0) + { + remainder = dataLength - counter; + + // read register + tempRegisterValue = *registerAddress; + + // clear the bytes we'll be filling + tempRegisterValue &= (uint32_t)(0x00FFFFFF >> ( (remainder - 1) * 8)); + + // adjust remainder to the amount of bytes to move + remainder = 4 - remainder; + + do + { + tempRegisterValue |= (uint32_t)((uint32_t)*data << (remainder * 8)); + remainder--; + data++; + counter++; + } + while(remainder); + + // write back register + *registerAddress = tempRegisterValue; + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_BackupMemory::GetSize___STATIC__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + stack.SetResult_I4(BACKUP_SIZE); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Hardware.Stm32/nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_Power.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Hardware.Stm32/nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_Power.cpp new file mode 100644 index 00000000..83854bb6 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Hardware.Stm32/nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_Power.cpp @@ -0,0 +1,251 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "nf_hardware_stm32_native.h" +#include + +///////////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH nanoFramework.Hardware.Stm32.Power.WakeupPin (in managed code) !!! // +///////////////////////////////////////////////////////////////////////////////////////////////// +enum WakeupPin +{ + WakeupPin_Pin1 = 1, + WakeupPin_Pin2, + WakeupPin_Pin3 +}; + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH nanoFramework.Hardware.Stm32.Power.WakeupReason (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////////////////// +enum WakeupReason +{ + WakeupReason_Undetermined = 0, + WakeupReason_FromStandby, + WakeupReason_FromPin +}; + +HRESULT Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_Power::get_WakeupReason___STATIC__nanoFrameworkHardwareStm32PowerWakeupReasonType( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + stack.SetResult_U4( WakeupReasonStore ); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_Power::DisableWakeupPin___STATIC__VOID__nanoFrameworkHardwareStm32PowerWakeupPin( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + uint32_t wakeUpPin; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + switch((WakeupPin)stack.Arg0().NumericByRef().u4) + { + #if defined(PWR_CSR_EWUP) + case WakeupPin_Pin1: + wakeUpPin = PWR_CSR_EWUP; + break; + #elif defined(PWR_CSR_EWUP1) + case WakeupPin_Pin1: + wakeUpPin = PWR_CSR_EWUP1; + break; + #elif defined(PWR_CSR2_EWUP1) + case WakeupPin_Pin1: + wakeUpPin = PWR_CSR2_EWUP1; + break; + #else + #error "missing include for STM32 target PAL" + #endif + + #if defined(PWR_CSR_EWUP2) + case WakeupPin_Pin2: + wakeUpPin = PWR_CSR_EWUP2; + break; + #elif defined(PWR_CSR2_EWUP2) + case WakeupPin_Pin2: + wakeUpPin = PWR_CSR2_EWUP2; + break; + #endif + + #if defined(PWR_CSR_EWUP3) + case WakeupPin_Pin3: + wakeUpPin = PWR_CSR_EWUP3; + break; + #elif defined(PWR_CSR2_EWUP3) + case WakeupPin_Pin3: + wakeUpPin = PWR_CSR2_EWUP3; + break; + #endif + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // disable the wake up pin + #if defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F2XX) || \ + defined(STM32F3XX) ||defined(STM32F4XX) || defined(STM32L0XX) || defined(STM32L1XX) + + CLEAR_BIT(PWR->CSR, wakeUpPin); + + #endif + + #if defined(STM32F7XX) || defined(STM32H7XX) || defined(STM32L4XX) + + CLEAR_BIT(PWR->CSR2, wakeUpPin); + + #endif + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_Power::EnableWakeupPin___STATIC__VOID__nanoFrameworkHardwareStm32PowerWakeupPin( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + uint32_t wakeUpPin; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + switch((WakeupPin)stack.Arg0().NumericByRef().u4) + { + #if defined(PWR_CSR_EWUP) + + case WakeupPin_Pin1: + wakeUpPin = PWR_CSR_EWUP; + + // need to config the respective EXTI line (PA0) + EXTI->IMR |= EXTI_IMR_IM0; + EXTI->RTSR |= EXTI_RTSR_TR0; + + break; + + #elif defined(PWR_CSR_EWUP1) + + case WakeupPin_Pin1: + wakeUpPin = PWR_CSR_EWUP1; + // need to config the respective EXTI line (PA0) + EXTI->IMR |= EXTI_IMR_IM0; + EXTI->RTSR |= EXTI_RTSR_TR0; + break; + + #elif defined(PWR_CSR2_EWUP1) + + case WakeupPin_Pin1: + wakeUpPin = PWR_CSR2_EWUP1; + + // need to config the respective EXTI line (PA0) + EXTI->IMR |= EXTI_IMR_IM0; + EXTI->RTSR |= EXTI_RTSR_TR0; + + break; + + #else + #error "missing include for STM32 target PAL" + #endif + + #if defined(PWR_CSR_EWUP2) + + case WakeupPin_Pin2: + wakeUpPin = PWR_CSR_EWUP2; + + // need to config the respective EXTI line (PA2) + EXTI->IMR |= EXTI_IMR_IM2; + EXTI->RTSR |= EXTI_RTSR_TR2; + break; + + #elif defined(PWR_CSR2_EWUP2) + + case WakeupPin_Pin2: + wakeUpPin = PWR_CSR2_EWUP2; + + // need to config the respective EXTI line (PA2) + EXTI->IMR |= EXTI_IMR_IM2; + EXTI->RTSR |= EXTI_RTSR_TR2; + + break; + + #endif + + #if defined(PWR_CSR_EWUP3) + + case WakeupPin_Pin3: + wakeUpPin = PWR_CSR_EWUP3; + + // need to config the respective EXTI line (PC1) + EXTI->IMR |= EXTI_IMR_IM1; + EXTI->RTSR |= EXTI_RTSR_TR1; + + break; + + #elif defined(PWR_CSR2_EWUP3) + + case WakeupPin_Pin3: + wakeUpPin = PWR_CSR2_EWUP3; + + // need to config the respective EXTI line (PC1) + EXTI->IMR |= EXTI_IMR_IM1; + EXTI->RTSR |= EXTI_RTSR_TR1; + + break; + + #endif + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // according to the STM32 documentation it's highly recommended to first disable and then enable the wake-up source + + #if defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F2XX) || \ + defined(STM32F3XX) ||defined(STM32F4XX) || defined(STM32L0XX) || defined(STM32L1XX) + // clear PWR wake up Flag + PWR->CR |= PWR_CSR_WUF; + + // disable the wake up pin + CLEAR_BIT(PWR->CSR, wakeUpPin); + + // enable the wake up pin + SET_BIT(PWR->CSR, wakeUpPin); + + #endif + + #if defined(STM32F7XX) || defined(STM32H7XX) || defined(STM32L4XX) + + // enable the wake up pin + SET_BIT(PWR->CSR2, wakeUpPin); + + #endif + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_Power::NativeEnterStandbyMode___STATIC__VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + (void)stack; + + // set flags to stop debug... + CLR_EE_DBG_SET( RebootPending ); + // ... reboot CLR so execution ends gracefully ... + CLR_EE_REBOOT_CLR; + // ... and set power level to OFF + g_CLR_HW_Hardware.m_powerLevel = PowerLevel__Off; + + ////////////////////////////////////////////////////////// + // developer notes: + // - the "goto sleep" is actually handled in ClrStartup() loop when calling CPU_SetPowerMode() + // - the execution engine has to exit the current thread execution to be able to check the reboot flags set above and shutdown gracefully + // - a clean approach to accomplish this is to add a Thread.Sleep(Inifinite) in the caller + ////////////////////////////////////////////////////////// + + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Hardware.Stm32/nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_RTC.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Hardware.Stm32/nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_RTC.cpp new file mode 100644 index 00000000..09f5f6c6 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Hardware.Stm32/nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_RTC.cpp @@ -0,0 +1,202 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "nf_hardware_stm32_native.h" + +// we are using always Alarm 0 (alarm A, if there are two alarms) +#define ALARM_ID 0 + + +HRESULT Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_RTC::Native_RTC_SetAlarm___STATIC__VOID__U1__U1__U1__U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + #if (HAL_USE_RTC == TRUE) + + RTCAlarm alarmTime; + + uint32_t value = 0; + uint32_t alarmRegister = 0; + + #if defined(STM32F7XX) || defined(STM32F3XX) || defined(STM32F0XX) || \ + defined(STM32F4XX) || defined(STM32L0XX) || defined(STM32L4XX) || \ + defined(STM32H7XX) + + // these series are using driver RTCv2 + // the alarm is set on a register with the various values BCD coded + // to keep the configuration simple, it's assumed that + // it's only possible to set seconds, minutes, hours and date (day) + + // to set the alarm, it has to be stoped first (in case there is one already set) + rtcSetAlarm(&RTCD1, ALARM_ID, NULL); + + // alarm date (day) tens and units + value = stack.Arg0().NumericByRef().u1; + alarmRegister |= ((value % 10) << RTC_ALRMAR_DU_Pos); + value /= 10; + alarmRegister |= ((value % 10) << RTC_ALRMAR_DT_Pos); + + // alarm hours tens and units + value = stack.Arg1().NumericByRef().u1; + alarmRegister |= ((value % 10) << RTC_ALRMAR_HU_Pos); + value /= 10; + alarmRegister |= ((value % 10) << RTC_ALRMAR_HT_Pos); + + // alarm minutes tens and units + value = stack.Arg2().NumericByRef().u1; + alarmRegister |= ((value % 10) << RTC_ALRMAR_MNU_Pos); + value /= 10; + alarmRegister |= ((value % 10) << RTC_ALRMAR_MNT_Pos); + + // alarm seconds tens and units + value = stack.Arg3().NumericByRef().u1; + alarmRegister |= ((value % 10) << RTC_ALRMAR_SU_Pos); + value /= 10; + alarmRegister |= ((value % 10) << RTC_ALRMAR_ST_Pos); + + alarmTime.alrmr = alarmRegister; + + #else + #error "Setting an alarm for this series in not supported. Care to look into it and submit a PR?" + #endif + + #if defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F2XX) || \ + defined(STM32F3XX) ||defined(STM32F4XX) || defined(STM32L0XX) || defined(STM32L1XX) + // clear PWR wake up Flag + PWR->CR |= PWR_CSR_WUF; + #endif + + #if defined(STM32F7XX) || defined(STM32H7XX) || defined(STM32L4XX) + + CLEAR_BIT(RTC->CR, RTC_CR_ALRAIE); + CLEAR_BIT(RTC->ISR, RTC_ISR_ALRAF); + + #endif + + rtcSetAlarm(&RTCD1, ALARM_ID, &alarmTime); + + NANOCLR_NOCLEANUP_NOLABEL(); + + #else + + (void)stack; + + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + NANOCLR_NOCLEANUP(); + + #endif // (HAL_USE_RTC == TRUE) + +} + +HRESULT Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_RTC::GetAlarm___STATIC__mscorlibSystemDateTime( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + #if (HAL_USE_RTC == TRUE) + + RTCAlarm alarmValue; + RTCDateTime currentTime; + SYSTEMTIME alarmTime; + uint32_t value; + + rtcGetAlarm(&RTCD1, ALARM_ID, &alarmValue); + + #if defined(STM32F7XX) || defined(STM32F3XX) || defined(STM32F0XX) || \ + defined(STM32F4XX) || defined(STM32L0XX) || defined(STM32L4XX) || \ + defined(STM32H7XX) + + // these series are using driver RTCv2 + // the alarm is set on a register with the various values BCD coded + // to keep the configuration simple, it's assumed that + // it's only possible to set seconds, minutes, hours and date (day) + + // convert from BCD assuming the alarm is always set for a future date/time + + // get current time from RTC + rtcGetTime(&RTCD1, ¤tTime); + + // fill in alarmTime struct + alarmTime.wYear = (unsigned short) (currentTime.year + 1980); // ChibiOS is counting years since 1980 + alarmTime.wMonth = (unsigned short) currentTime.month; + + // date (day) tens and units + value = alarmValue.alrmr & RTC_ALRMAR_DT_Msk; + value = value >> RTC_ALRMAR_DT_Pos; + alarmTime.wDay = value * 10; + + value = alarmValue.alrmr & RTC_ALRMAR_DU_Msk; + value = value >> RTC_ALRMAR_DU_Pos; + alarmTime.wDay += value; + + // alarm hours tens and units + value = alarmValue.alrmr & RTC_ALRMAR_HT_Msk; + value = value >> RTC_ALRMAR_HT_Pos; + alarmTime.wHour = value * 10; + + value = alarmValue.alrmr & RTC_ALRMAR_HU_Msk; + value = value >> RTC_ALRMAR_HU_Pos; + alarmTime.wHour += value; + + // alarm minutes tens and units + value = alarmValue.alrmr & RTC_ALRMAR_MNT_Msk; + value = value >> RTC_ALRMAR_MNT_Pos; + alarmTime.wMinute = value * 10; + + value = alarmValue.alrmr & RTC_ALRMAR_MNU_Msk; + value = value >> RTC_ALRMAR_MNU_Pos; + alarmTime.wMinute += value; + + // alarm seconds tens and units + value = alarmValue.alrmr & RTC_ALRMAR_ST_Msk; + value = value >> RTC_ALRMAR_ST_Pos; + alarmTime.wSecond = value * 10; + + value = alarmValue.alrmr & RTC_ALRMAR_SU_Msk; + value = value >> RTC_ALRMAR_SU_Pos; + alarmTime.wSecond += value; + + // clear unused fields + alarmTime.wMilliseconds = 0; + alarmTime.wDayOfWeek = 0; + + // if alarm day is lower than the current day, means that the alarm was set for a date on the next month + if(alarmTime.wDay < currentTime.day) + { + alarmTime.wMonth++; + + // check for December + 1 + if(alarmTime.wMonth > 12) + { + // adjust to January + alarmTime.wMonth = 1; + } + } + + #else + #error "Setting an alarm for this series in not supported. Care to look into it and submit a PR?" + #endif + + CLR_RT_HeapBlock& ref = stack.PushValue(); + + ref.SetDataId( CLR_RT_HEAPBLOCK_RAW_ID(DATATYPE_DATETIME, 0, 1) ); + ref.ClearData(); + + CLR_INT64* pRes = (CLR_INT64*)&ref.NumericByRef().s8; + *pRes = HAL_Time_ConvertFromSystemTime( &alarmTime ); + + NANOCLR_NOCLEANUP_NOLABEL(); + + #else + + (void)stack; + + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + NANOCLR_NOCLEANUP(); + + #endif // (HAL_USE_RTC == TRUE) + +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Hardware.Stm32/nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_Utilities.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Hardware.Stm32/nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_Utilities.cpp new file mode 100644 index 00000000..4d2d2525 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Hardware.Stm32/nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_Utilities.cpp @@ -0,0 +1,49 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "nf_hardware_stm32_native.h" + +HRESULT Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_Utilities::NativeGetDeviceUniqueId___STATIC__VOID__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // dereference the data buffer from the argument + CLR_RT_HeapBlock_Array* buffer = stack.Arg0().DereferenceArray(); + + // get a the pointer to the byffer by using the first element of the array + uint8_t* data = buffer->GetFirstElement(); + + // 96 bit unique device ID => 12 bytes + // memory copy from the address pointed by UID_BASE define (from STM32 HAL) + memcpy(data, ((uint8_t *)UID_BASE), 12); + + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_Utilities::NativeGetDeviceId___STATIC__U4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // this ID is provided by debug MCU register + uint32_t deviceId = READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID); + + stack.SetResult_U4(deviceId); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nf_hardware_stm32_native_nanoFramework_Hardware_Stm32_Utilities::NativeGetDeviceRevisionId___STATIC__U4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // this ID is provided by debug MCU register + // need to right shift 16 bits because it shows as 0xFFFF0000 + uint32_t deviceRevisionId = (READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); + + stack.SetResult_U4(deviceRevisionId); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Native_Rtc.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Native_Rtc.cpp new file mode 100644 index 00000000..735f3323 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Native_Rtc.cpp @@ -0,0 +1,56 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include "nf_rt_native.h" + + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// these functions are the real implementation of the 'weak' ones declared at src\CLR\Runtime.Native\nf_rt_native_nanoFramework_Runtime_Native_Rtc_stubs.cpp // +// the stubs for this class are generated by nanoFramework.Runtime.Native // +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +// for all these to work we need the RTC to be enabled +#if !defined(HAL_USE_RTC) + #error "Need the RTC to be enabled. Please set CMake option NF_FEATURE_RTC to ON." +#endif + +HRESULT Library_nf_rt_native_nanoFramework_Runtime_Native_Rtc::Native_RTC_SetSystemTime___STATIC__BOOLEAN__I4__U1__U1__U1__U1__U1__U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + #if (HAL_USE_RTC == TRUE) + + RTCDateTime newTime; + + newTime.year = stack.Arg0().NumericByRef().s4 - 1980; // ChibiOS time base is 1980-01-01 + newTime.month = (uint8_t)stack.Arg1().NumericByRef().u1; + newTime.day = stack.Arg2().NumericByRef().u1; + newTime.dayofweek = stack.Arg3().NumericByRef().u1; + newTime.millisecond = ((((uint32_t)stack.Arg4().NumericByRef().u1 * 3600) + + ((uint32_t)stack.Arg5().NumericByRef().u1 * 60) + + (uint32_t)stack.Arg6().NumericByRef().u1) * 1000); + + // set RTC time + rtcSetTime(&RTCD1, &newTime); + + // Return value to the managed application + stack.SetResult_Boolean(true); + + NANOCLR_NOCLEANUP_NOLABEL(); + + #else + + (void)stack; + + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + NANOCLR_NOCLEANUP(); + + #endif // (HAL_USE_RTC == TRUE) + +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/targetHAL.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/targetHAL.cpp new file mode 100644 index 00000000..0e0abb90 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/targetHAL.cpp @@ -0,0 +1,212 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include +#include +#include +#include + +// global mutex protecting the internal state of the interpreter, including event flags +//mutex_t interpreterGlobalMutex; + +// because nanoHAL_Initialize/Uninitialize needs to be called in both C and C++ we need a proxy to allow it to be called in 'C' +extern "C" { + + void nanoHAL_Initialize_C() + { + nanoHAL_Initialize(); + } + + void nanoHAL_Uninitialize_C() + { + nanoHAL_Uninitialize(); + } +} + +void nanoHAL_Initialize() +{ + // initialize global mutex + //chMtxObjectInit(&interpreterGlobalMutex); + + HAL_CONTINUATION::InitializeList(); + HAL_COMPLETION ::InitializeList(); + + BlockStorageList_Initialize(); + + // initialize block storage devices + BlockStorage_AddDevices(); + + BlockStorageList_InitializeDevices(); + + // clear managed heap region + unsigned char* heapStart = NULL; + unsigned int heapSize = 0; + + ::HeapLocation( heapStart, heapSize ); + memset(heapStart, 0, heapSize); + + ConfigurationManager_Initialize(); + + Events_Initialize(); + + // no PAL events required until now + //PalEvent_Initialize(); + + // Initialise Network Stack + Network_Initialize(); +} + +void nanoHAL_Uninitialize() +{ + // release the global mutex, just in case it's locked somewhere + //chMtxUnlock(&interpreterGlobalMutex); + + // TODO check for s_rebootHandlers + // for(int i = 0; i< ARRAYSIZE(s_rebootHandlers); i++) + // { + // if(s_rebootHandlers[i] != NULL) + // { + // s_rebootHandlers[i](); + // } + // else + // { + // break; + // } + // } + + SOCKETS_CloseConnections(); + + #if !defined(HAL_REDUCESIZE) + // TODO need to call this but it's preventing the debug session from starting + //Network_Uninitialize(); + #endif + + BlockStorageList_UnInitializeDevices(); + + // need to be sure that all mutexes for drivers that use them are released +#if (HAL_USE_SPI == TRUE) + + #if STM32_SPI_USE_SPI1 + spiReleaseBus(&SPID1); + #endif + #if STM32_SPI_USE_SPI2 + spiReleaseBus(&SPID2); + #endif + #if STM32_SPI_USE_SPI3 + spiReleaseBus(&SPID3); + #endif + #if STM32_SPI_USE_SPI4 + spiReleaseBus(&SPID4); + #endif + #if STM32_SPI_USE_SPI5 + spiReleaseBus(&SPID5); + #endif + #if STM32_SPI_USE_SPI6 + spiReleaseBus(&SPID6); + #endif + +#endif + +#if (HAL_USE_I2C == TRUE) + + #if STM32_I2C_USE_I2C1 + i2cReleaseBus(&I2CD1); + #endif + #if STM32_I2C_USE_I2C2 + i2cReleaseBus(&I2CD2); + #endif + #if STM32_I2C_USE_I2C3 + i2cReleaseBus(&I2CD3); + #endif + #if STM32_I2C_USE_I2C4 + i2cReleaseBus(&I2CD4); + #endif + +#endif + +#if (HAL_USE_UART == TRUE) + + #if NF_SERIAL_COMM_STM32_UART_USE_USART1 + uartReleaseBus(&UARTD1); + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART2 + uartReleaseBus(&UARTD2); + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART3 + uartReleaseBus(&UARTD3); + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART4 + uartReleaseBus(&UARTD4); + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART5 + uartReleaseBus(&UARTD5); + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_USART6 + uartReleaseBus(&UARTD6); + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART7 + uartReleaseBus(&UARTD7); + #endif + #if NF_SERIAL_COMM_STM32_UART_USE_UART8 + uartReleaseBus(&UARTD8); + #endif + +#endif + + Events_Uninitialize(); + + HAL_CONTINUATION::Uninitialize(); + HAL_COMPLETION ::Uninitialize(); +} + +volatile int32_t SystemStates[SYSTEM_STATE_TOTAL_STATES]; + +void SystemState_SetNoLock(SYSTEM_STATE_type state) +{ + SystemStates[state]++; +} + +void SystemState_ClearNoLock(SYSTEM_STATE_type state) +{ + SystemStates[state]--; +} + +bool SystemState_QueryNoLock(SYSTEM_STATE_type state) +{ + return (SystemStates[state] > 0) ? true : false; +} + +void SystemState_Set(SYSTEM_STATE_type state) +{ + GLOBAL_LOCK(); + + SystemState_SetNoLock(state); + + GLOBAL_UNLOCK(); +} + +void SystemState_Clear(SYSTEM_STATE_type state) +{ + GLOBAL_LOCK(); + + SystemState_ClearNoLock(state ); + + GLOBAL_UNLOCK(); +} + +bool SystemState_Query(SYSTEM_STATE_type state) +{ + GLOBAL_LOCK(); + + bool systemStateCopy = SystemState_QueryNoLock(state); + + GLOBAL_UNLOCK(); + + return systemStateCopy; +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/targetHAL_Power.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/targetHAL_Power.c new file mode 100644 index 00000000..766376de --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/targetHAL_Power.c @@ -0,0 +1,166 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include +#include +#include + +#if (HAL_USE_FSMC == TRUE) +#include +#include +#endif + +uint32_t WakeupReasonStore; + +inline void CPU_Reset() +{ + NVIC_SystemReset(); +}; + +inline bool CPU_IsSoftRebootSupported() +{ + return true; +}; + +// CPU sleep is not currently implemented in this target +inline void CPU_Sleep(SLEEP_LEVEL_type level, uint64_t wakeEvents) +{ + (void)level; + (void)wakeEvents; + +}; + +void CPU_SetPowerMode(PowerLevel_type powerLevel) +{ + // default to false + bool success = false; + + switch(powerLevel) + { + case PowerLevel__Off: + // stop watchdog + wdgStop(&WDGD1); + + #if (HAL_USE_FSMC == TRUE) + // shutdown memory + #if (STM32_USE_FSMC_SDRAM == TRUE) + fsmcSdramStop(&SDRAMD); + #endif + #if (STM32_USE_FSMC_SRAM == TRUE) + #if (STM32_SRAM_USE_FSMC_SRAM1 == TRUE) + fsmcSramStop(&SRAMD1); + #endif + #if (STM32_SRAM_USE_FSMC_SRAM2 == TRUE) + fsmcSramStop(&SRAMD2); + #endif + #if (STM32_SRAM_USE_FSMC_SRAM3 == TRUE) + fsmcSramStop(&SRAMD3); + #endif + #if (STM32_SRAM_USE_FSMC_SRAM4 == TRUE) + fsmcSramStop(&SRAMD4); + #endif + #endif + #endif + + // gracefully shutdown everything + nanoHAL_Uninitialize_C(); + + chSysDisable(); + + ///////////////////////////////////////////////////////////////////////// + // stop the idependent watchdog, for series where the option is available + #if defined(STM32L4XX) + + (void)success; + // TODO FIXME this code needs to follow the same workflow as the STM32F7 + CLEAR_BIT(FLASH->OPTR, FLASH_OPTR_IWDG_STDBY); + + #elif defined(STM32F7XX) + + // only need to change this option bit if not already done + if((FLASH->OPTCR & FLASH_OPTCR_IWDG_STDBY)) + { + // developer notes: + // follow workflow recommended @ 3.4.2 Option bytes programming (from programming manual) + // Authorizes the Option Byte register programming + FLASH->OPTKEYR = FLASH_OPT_KEY1; + FLASH->OPTKEYR = FLASH_OPT_KEY2; + + // wait 500ms for any flash operation to be completed + success = FLASH_WaitForLastOperation(500); + + if(success) + { + // write option value (clear the FLASH_OPTCR_IWDG_STDBY) + CLEAR_BIT(FLASH->OPTCR, FLASH_OPTCR_IWDG_STDBY); + + // set the option start bit + FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT; + + // Data synchronous Barrier, forcing the CPU to respect the sequence of instruction without optimization + __DSB(); + + // wait 100ms for the flash operation to be completed + success = FLASH_WaitForLastOperation(100); + } + + // Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access + FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; + } + (void)success; + + #elif defined(STM32H7XX) + + (void)success; + // TODO FIXME this code needs to follow the same workflow as the STM32F7 + CLEAR_BIT(FLASH->OPTSR, FLASH_OPTSR_FZ_IWDG_SDBY); + + #else + (void)success; + #endif + + /////////////////////////////////////////////////////// + // set alarm interrupt enable + // set power control register to: power down deep sleep + /////////////////////////////////////////////////////// + + #if defined(STM32F0XX) || defined(STM32F1XX) || defined(STM32F2XX) || \ + defined(STM32F3XX) ||defined(STM32F4XX) || defined(STM32L0XX) || defined(STM32L1XX) + SET_BIT(RTC->CR, RTC_CR_ALRAIE); + SET_BIT(PWR->CR, PWR_CR_PDDS); + #endif + + #if defined(STM32F7XX) + + ////////////////////////////////////////////////////////////////////////////////////////////////////// + // workaround recommended in section 2.2.2 at STM32F77xxx errata document (DM00257543 - ES0334 Rev 5) // + PWR->CSR1 |= PWR_CSR1_EIWUP; + ////////////////////////////////////////////////////////////////////////////////////////////////////// + + SET_BIT(PWR->CR1, PWR_CR1_PDDS); + + #endif + + #if defined(STM32H7XX) + SET_BIT(PWR->CR1, PWR_CR1_PDDS); + #endif + + // set SLEEPDEEP bit of Cortex SCR + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + // wait for interrupt, and the execution dies here + __WFI(); + + break; + + default: + // all the other power modes are unsupported here + break; + } +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/targetHAL_Time.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/targetHAL_Time.cpp new file mode 100644 index 00000000..de1fa4a9 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/targetHAL_Time.cpp @@ -0,0 +1,172 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include +#include +#include + +// Returns the current date time from the system tick or from the RTC if it's available (this depends on the respective configuration option) +uint64_t HAL_Time_CurrentDateTime(bool datePartOnly) +{ + #if (HAL_USE_RTC == TRUE) + + // use RTC to get date time + SYSTEMTIME st; + RTCDateTime _dateTime; + + rtcGetTime(&RTCD1, &_dateTime); + + st.wDay = (unsigned short) _dateTime.day; + st.wMonth = (unsigned short) _dateTime.month; + st.wYear = (unsigned short) (_dateTime.year + 1980); // ChibiOS is counting years since 1980 + st.wDayOfWeek = (unsigned short) _dateTime.dayofweek; + + // zero 'time' fields if date part only is required + if(datePartOnly) + { + st.wMilliseconds = 0; + st.wSecond = 0; + st.wMinute = 0; + st.wHour = 0; + } + else + { + // full date&time required, fill in 'time' fields too + + st.wMilliseconds =(unsigned short) (_dateTime.millisecond % 1000); + _dateTime.millisecond /= 1000; + st.wSecond = (unsigned short) (_dateTime.millisecond % 60); + _dateTime.millisecond /= 60; + st.wMinute = (unsigned short) (_dateTime.millisecond % 60); + _dateTime.millisecond /= 60; + st.wHour = (unsigned short) (_dateTime.millisecond % 24); + } + + return HAL_Time_ConvertFromSystemTime( &st ); + + #else + + if (datePartOnly) + { + SYSTEMTIME st; + HAL_Time_ToSystemTime(HAL_Time_CurrentTime(), &st); + + st.wHour = 0; + st.wMinute = 0; + st.wSecond = 0; + st.wMilliseconds = 0; + + return HAL_Time_ConvertFromSystemTime(&st); + } + else + { + return HAL_Time_CurrentTime(); + } + + #endif +}; + +void HAL_Time_SetUtcTime(uint64_t utcTime) +{ + SYSTEMTIME systemTime; + + HAL_Time_ToSystemTime(utcTime, &systemTime); + + #if (HAL_USE_RTC == TRUE) + + // set RTC + RTCDateTime newTime; + + newTime.year = systemTime.wYear - 1980; // ChibiOS time base is 1980-01-01 + newTime.month = systemTime.wMonth; + newTime.day = systemTime.wDay; + newTime.dayofweek = systemTime.wDayOfWeek; + newTime.millisecond = ((((uint32_t)systemTime.wHour * 3600) + + ((uint32_t)systemTime.wMinute * 60) + + (uint32_t)systemTime.wSecond) * 1000); + + // set RTC time + rtcSetTime(&RTCD1, &newTime); + + #else + + // TODO FIXME + // need to add implementation when RTC is not being used + // can't mess with the systicks because the scheduling can fail + + #endif +} + +bool HAL_Time_TimeSpanToStringEx( const int64_t& ticks, char*& buf, size_t& len ) +{ + uint64_t ticksAbs; + uint64_t rest; + + if(ticks < 0) + { + ticksAbs = -ticks; + + CLR_SafeSprintf( buf, len, "-" ); + } + else + { + ticksAbs = ticks; + } + + rest = ticksAbs % ( 1000 * TIME_CONVERSION__TICKUNITS); + ticksAbs = ticksAbs / ( 1000 * TIME_CONVERSION__TICKUNITS); // Convert to seconds. + + if(ticksAbs > TIME_CONVERSION__ONEDAY) // More than one day. + { + CLR_SafeSprintf( buf, len, "%d.", (int32_t)(ticksAbs / TIME_CONVERSION__ONEDAY) ); ticksAbs %= TIME_CONVERSION__ONEDAY; + } + + CLR_SafeSprintf( buf, len, "%02d:", (int32_t)(ticksAbs / TIME_CONVERSION__ONEHOUR) ); ticksAbs %= TIME_CONVERSION__ONEHOUR ; + CLR_SafeSprintf( buf, len, "%02d:", (int32_t)(ticksAbs / TIME_CONVERSION__ONEMINUTE)); ticksAbs %= TIME_CONVERSION__ONEMINUTE; + CLR_SafeSprintf( buf, len, "%02d" , (int32_t)(ticksAbs / TIME_CONVERSION__ONESECOND)); ticksAbs %= TIME_CONVERSION__ONESECOND; + + ticksAbs = (uint32_t)rest; + if(ticksAbs) + { + CLR_SafeSprintf( buf, len, ".%07d", (uint32_t)ticksAbs ); + } + + return len != 0; +} + +bool DateTimeToString(const uint64_t& time, char*& buf, size_t& len ) +{ + SYSTEMTIME st; + + HAL_Time_ToSystemTime( time, &st ); + + return CLR_SafeSprintf(buf, len, "%4d/%02d/%02d %02d:%02d:%02d.%03d", st.wYear, st.wMonth, st.wDay, st.wHour, st.wMinute, st.wSecond, st.wMilliseconds ); +} + +char* DateTimeToString(const uint64_t& time) +{ + static char rgBuffer[128]; + char* szBuffer = rgBuffer; + size_t iBuffer = ARRAYSIZE(rgBuffer); + + DateTimeToString( time, szBuffer, iBuffer ); + + return rgBuffer; +} + +const char* HAL_Time_CurrentDateTimeToString() +{ + return DateTimeToString(HAL_Time_CurrentDateTime(false)); +} + +uint64_t CPU_MillisecondsToTicks(uint64_t ticks) +{ + // this is a rewrite of ChibiOS TIME_MS2I(n) macro because it will overflow if doing the math using uint32_t + return (((ticks * (uint64_t)CH_CFG_ST_FREQUENCY) + 999) / (uint64_t)1000); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/targetHAL_Watchdog.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/targetHAL_Watchdog.c new file mode 100644 index 00000000..ae40f26d --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/targetHAL_Watchdog.c @@ -0,0 +1,86 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include + +// LSI clock value (series dependent) +#if defined(STM32L0xx_MCUCONF) +#define LSI_CLK_TYPICAL 38000 +#elif defined(STM32F0xx_MCUCONF) +#define LSI_CLK_TYPICAL 40000 +#elif defined(STM32F4xx_MCUCONF) || defined(STM32F7xx_MCUCONF) || defined(STM32H7xx_MCUCONF) +#define LSI_CLK_TYPICAL 32000 +#else +#error "The LSI value for this STM32 series hasn't been defined." +#endif + + +//Watchdog configuration structure required by ChibiOS +#if (STM32_IWDG_IS_WINDOWED == TRUE) + static WDGConfig wdgConfig = {STM32_IWDG_PR_256, STM32_IWDG_RL(0xFFF), 0x0FFF}; //default is max +#else + static WDGConfig wdgConfig = {STM32_IWDG_PR_256, STM32_IWDG_RL(0xFFF)}; //default is max +#endif + +/** +* Method to initialize the watchdog. In ChibiOS, the watchdog sub-system is +* initialized when halInit() is called. In this method, we perform +* further specific initializations and also start the watchdog +*/ +void Watchdog_Init() +{ + //setup required watchdog timeout...(for IWATCHDOG_TIMEOUT_MILLIS) + /* + There are minor variations in STM32 LSI clock across models (e.g STM32F091 has 40KHz LSI + and STM32F401 has 32 KHz). Also, across the same model, due to manufacturing differences + the LSI clock has a minimum and maximum range. Therefore, the timeout is always an approximation + and not exact + */ + uint32_t ticksForTimeout=0; + + uint16_t prescaler[] = {STM32_IWDG_PR_4,STM32_IWDG_PR_8,STM32_IWDG_PR_16, + STM32_IWDG_PR_32,STM32_IWDG_PR_64,STM32_IWDG_PR_128, + STM32_IWDG_PR_256}; + + uint8_t length = (sizeof(prescaler)/sizeof(prescaler[0])); + + uint16_t divisor= 4; + + for(uint8_t index=0; index < length;index++) + { + divisor = 4 << prescaler[index]; + ticksForTimeout = (LSI_CLK_TYPICAL / divisor) * (IWATCHDOG_TIMEOUT_MILLIS/1000) - 1; + + if(ticksForTimeout <= 0xFFF) + { + // the max reload register value + + wdgConfig.pr = prescaler[index]; + wdgConfig.rlr = ticksForTimeout; + break; + } + } + + wdgStart(&WDGD1,&wdgConfig); + + #if !defined(BUILD_RTM) + // these are required to stop the watchdog peripheral when stopping the core + // useful for debugging without the watchdog triggering + DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_IWDG_STOP; + DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_WWDG_STOP; + #endif +} + +/** + * Reset the watchdog. If not done within the timout period, + * the watchdog will trigger and MCU will reset + */ +void Watchdog_Reset() +{ + wdgReset(&WDGD1); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/targetPAL.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/targetPAL.c new file mode 100644 index 00000000..8c63f2e7 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/targetPAL.c @@ -0,0 +1,40 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +#if defined(STM32L0XX) || defined(STM32F0XX) || defined(STM32F4XX) || defined(STM32F7XX) || defined(STM32H7XX) + +stm32_gpio_t* gpioPort[] = { GPIOA, GPIOB +#if STM32_HAS_GPIOC +, GPIOC +#endif +#if STM32_HAS_GPIOD +, GPIOD +#endif +#if STM32_HAS_GPIOE +, GPIOE +#endif +#if STM32_HAS_GPIOF +, GPIOF +#endif +#if STM32_HAS_GPIOG +, GPIOG +#endif +#if STM32_HAS_GPIOH +, GPIOH +#endif +#if STM32_HAS_GPIOI +, GPIOI +#endif +#if STM32_HAS_GPIOJ +, GPIOJ +#endif +#if STM32_HAS_GPIOK +, GPIOK +#endif +}; + +#endif diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/targetPAL_Events.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/targetPAL_Events.cpp new file mode 100644 index 00000000..da69a771 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/targetPAL_Events.cpp @@ -0,0 +1,170 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include + +uint64_t CPU_MillisecondsToTicks(uint64_t ticks); + +// timer for bool events +static virtual_timer_t boolEventsTimer; +uint32_t systemEvents; + +set_Event_Callback g_Event_Callback = NULL; +void* g_Event_Callback_Arg = NULL; + +bool Events_Initialize() +{ + NATIVE_PROFILE_PAL_EVENTS(); + + // init events + GLOBAL_LOCK(); + systemEvents = 0; + GLOBAL_UNLOCK(); + + return true; +} + +bool Events_Uninitialize() +{ + NATIVE_PROFILE_PAL_EVENTS(); + + chVTResetI(&boolEventsTimer); + + return true; +} + +void Events_Set( uint32_t events ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + + // set events + GLOBAL_LOCK(); + systemEvents |= events; + GLOBAL_UNLOCK(); + + if( g_Event_Callback != NULL ) + { + g_Event_Callback( g_Event_Callback_Arg ); + } +} + +uint32_t Events_Get( uint32_t eventsOfInterest ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + + // get the requested flags from system events state and... + uint32_t returnEvents = (systemEvents & eventsOfInterest); + + // ... clear the requested flags atomically + GLOBAL_LOCK(); + systemEvents &= ~eventsOfInterest; + GLOBAL_UNLOCK(); + + // give the caller notice of just the events they asked for ( and were cleared already ) + return returnEvents; +} + +uint32_t Events_MaskedRead( uint32_t eventsOfInterest ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + return (systemEvents & eventsOfInterest); +} + +static void local_Events_SetBoolTimer_Callback( void* arg ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + bool* timerCompleteFlag = (bool*)arg; + + *timerCompleteFlag = true; +} + +void Events_SetCallback( set_Event_Callback pfn, void* arg ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + + g_Event_Callback = pfn; + g_Event_Callback_Arg = arg; +} + +void Events_SetBoolTimer( bool* timerCompleteFlag, uint32_t millisecondsFromNow ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + + if(timerCompleteFlag != NULL) + { + // no need to stop the timer even if it's running because the API does it anyway + chVTSetI(&boolEventsTimer, TIME_MS2I(millisecondsFromNow), local_Events_SetBoolTimer_Callback, timerCompleteFlag); + } +} + +uint32_t Events_WaitForEvents( uint32_t powerLevel, uint32_t wakeupSystemEvents, uint32_t timeoutMilliseconds ) +{ + // schedule an interrupt for this far in the future + // timeout is in milliseconds, need to convert to ticks + uint64_t countsRemaining = CPU_MillisecondsToTicks( timeoutMilliseconds ); + +#if defined(HAL_PROFILE_ENABLED) + Events_WaitForEvents_Calls++; +#endif + + uint64_t expireTimeInTicks = HAL_Time_CurrentTime() + countsRemaining; + bool runContinuations = true; + + while(true) + { + EVENTS_HEART_BEAT; + + uint32_t events = Events_MaskedRead( wakeupSystemEvents ); + if(events) + { + return events; + } + + if(expireTimeInTicks <= HAL_Time_CurrentTime()) + { + break; + } + + // first check and possibly run any continuations + // but only if we have slept after stalling + if(runContinuations && !SystemState_QueryNoLock(SYSTEM_STATE_NO_CONTINUATIONS)) + { + // if we stall on time, don't check again until after we sleep + runContinuations = HAL_CONTINUATION::Dequeue_And_Execute(); + } + else + { + // try stalled continuations again after sleeping + runContinuations = true; + + HAL_COMPLETION::WaitForInterrupts(expireTimeInTicks, powerLevel, wakeupSystemEvents ); + } + + // no events, pass control to the OS + osThreadYield(); + + // check if reboot or exit flags were set when the other OS threads executed + if(CLR_EE_DBG_IS(RebootPending) || CLR_EE_DBG_IS(ExitPending)) + { + break; + } + } + + return 0; +} + +void FreeManagedEvent(uint8_t category, uint8_t subCategory, uint16_t data1, uint32_t data2) +{ + (void)category; + (void)subCategory; + (void)data1; + (void)data2; + + NATIVE_PROFILE_PAL_EVENTS(); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/targetPAL_Time.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/targetPAL_Time.cpp new file mode 100644 index 00000000..1009fc55 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/targetPAL_Time.cpp @@ -0,0 +1,71 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include + + +// timer for next event +static virtual_timer_t nextEventTimer; +void* nextEventCallbackDummyArg = NULL; + +static void NextEventTimer_Callback( void* arg ) +{ + (void)arg; + + // this call also schedules the next one, if there is one + HAL_COMPLETION::DequeueAndExec(); +} + +HRESULT Time_Initialize() +{ + // need to setup the timer at boot, but stoped + chVTSet(&nextEventTimer, TIME_INFINITE, NextEventTimer_Callback, nextEventCallbackDummyArg); + + return S_OK; +} + +HRESULT Time_Uninitialize() +{ + chVTReset(&nextEventTimer); + + // nothing to do here has time management is handled by ChibiOS + return S_OK; +} + +void Time_SetCompare ( uint64_t compareValueTicks ) +{ + if(compareValueTicks == 0) + { + // compare value is 0 so dequeue and schedule immediately + // can't call chVTSet with 'immidiate delay value', so use value 1 to get it executed ASAP + chVTSet(&nextEventTimer, 1, NextEventTimer_Callback, nextEventCallbackDummyArg); + } + else if(compareValueTicks == HAL_COMPLETION_IDLE_VALUE) + { + // wait for infinity, don't need to do anything here + } + else + { + if (HAL_Time_CurrentTime() >= compareValueTicks) + { + // already missed the event, dequeue and execute immediately + // can't call chVTSet with 'immidiate delay value', so use value 1 to get it executed ASAP + chVTSet(&nextEventTimer, 1, NextEventTimer_Callback, nextEventCallbackDummyArg); + } + else + { + // compareValueTicks is the time (in sys ticks) that is being requested to fire an HAL_COMPLETION::DequeueAndExec() + // need to subtract the current system time to set when the timer will fire + compareValueTicks -= HAL_Time_CurrentTime(); + + // no need to stop the timer if it's running because the API does it anyway + // need to convert from nF ticks to milliseconds and then to ChibiOS sys ticks to load the timer + chVTSet(&nextEventTimer, TIME_MS2I(compareValueTicks/ TIME_CONVERSION__TO_MILLISECONDS), NextEventTimer_Callback, nextEventCallbackDummyArg); + } + } +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/targetRandom.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/targetRandom.cpp new file mode 100644 index 00000000..1b5aa12f --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/targetRandom.cpp @@ -0,0 +1,40 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// +#include "Core.h" +#include +#include + +void CLR_RT_Random::Initialize() +{ + rngStart(); +} + +void CLR_RT_Random::Initialize( int seed ) +{ + (void)seed; + + rngStart(); +} + +uint32_t CLR_RT_Random::Next() +{ + return rngGenerateRandomNumber(); +} + +double CLR_RT_Random::NextDouble() +{ + // the hardware generator returns a value between 0 - 0xFFFFFFFF + return ((double)rngGenerateRandomNumber()) / ((double)0xFFFFFFFF); +} + +void CLR_RT_Random::NextBytes(unsigned char* buffer, unsigned int count) +{ + unsigned int i; + + for(i = 0; i < count; i++) + { + buffer[i] = (unsigned char)rngGenerateRandomNumber(); + } +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/target_platform.h.in b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/target_platform.h.in new file mode 100644 index 00000000..08b5aa2e --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nanoCLR/target_platform.h.in @@ -0,0 +1,58 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_CHIBIOS_NANOCLR_H_ +#define _TARGET_CHIBIOS_NANOCLR_H_ + +// enable SPIFFS +#define NF_FEATURE_USE_SPIFFS @NF_FEATURE_USE_SPIFFS_OPTION@ + +// set preference to enable (or not) the RTC subsystem +#define HAL_USE_RTC @HAL_USE_RTC_OPTION@ + +// takes care of enabling the HAL subsystems required for API options + +// enable SPI +#define HAL_USE_SPI @HAL_USE_SPI_OPTION@ + +// enable I2C +#define HAL_USE_I2C @HAL_USE_I2C_OPTION@ + +// enable PWM +#define HAL_USE_PWM @HAL_USE_PWM_OPTION@ + +// enable ADC +#define HAL_USE_ADC @HAL_USE_ADC_OPTION@ + +// enable DAC +#define HAL_USE_DAC @HAL_USE_DAC_OPTION@ + +// enable UART subsystem +#define HAL_USE_UART @HAL_USE_UART_OPTION@ + +// set when networking is enabled +#define HAL_USE_MAC @HAL_USE_MAC_OPTION@ + +// set when filesystem is enabled +#define HAL_USE_SDC @HAL_USE_SDC_OPTION@ + +// set when watchod is enabled +#define HAL_USE_WDG @HAL_USE_WDG_OPTION@ + +// enable CAN +#define HAL_USE_CAN @HAL_USE_CAN_OPTION@ + +// enable STM32 ONEWIRE (from nf overlay) +#define HAL_USE_STM32_ONEWIRE @HAL_USE_STM32_ONEWIRE_OPTION@ + +// enable USB MSD (from ChibiOS Contrib) + #define HAL_USBH_USE_MSD @HAL_USBH_USE_MSDC_OPTION@ + +#endif /* _TARGET_CHIBIOS_NANOCLR_H_ */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/README.md b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/README.md new file mode 100644 index 00000000..460e0849 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/README.md @@ -0,0 +1,23 @@ +# **nanoFramework** overlay for ChibiOS + +This folder contains code that _extends_ ChibiOS features/functionalities for the purpose of **nanoFramework**. +ChibiOS core code is architecture to include seamless integration of third party code (HAL drivers, boards, etc). That is explained [here](http://wiki.chibios.org/dokuwiki/doku.php?id=chibios:community:guides:community_overlay). +The structure below this folder mimics the structure and organization of ChibiOS Community overlay. +Note that this is designed in a way that in order to use a specific driver, the only thing that a developer has to do is enable the corresponding define in the HAL configuration file at the target folder e.g. HAL_USE_STM32_FLASH in order to enable the flash driver. + + +## Adding components to **nanoFramework** overlay + +When adding HAL components, drivers, boards or any other code to the **nanoFramework** overlay make sure you follow the following guide. + +- Add the required source code to the appropriate folder below this one. Follow the existing structure and make sure it follows the one established by ChibiOS. It makes it easier to maintain and for newcomers to better understand it. In particular try to follow (if it makes sense) the design approach of providing a 'main' driver and a low level driver. +- Add a compiler define following the pattern HAL_USE_NNNN for the component and add any required includes in [hal_community.h](os/hal/include/hal_community.h). +- If it requires an initialization function add a call to it wrapped in the appropriate compiler define in [hal_community.c](os/hal/src/hal_community.c). +- Add an entry for each source file (both main and low level driver) and include directories to the CMake module [FindChibiOSnfOverlay.cmake](../../../../CMake/Modules/FindChibiOSnfOverlay.cmake). + + +## **nanoFramework** overlay components + +Follows a list of available components in **nanoFramework** overlay. + +- [Driver for internal flash of STM32 parts](stm32-internal-flash-driver.md) (supports F0, F4 and F7 series) diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/asmdefs.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/asmdefs.h new file mode 100644 index 00000000..c2a6f973 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/asmdefs.h @@ -0,0 +1,229 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +//***************************************************************************** +// +// asmdefs.h - Macros to allow assembly code be portable among toolchains. +// +//***************************************************************************** + +#ifndef __ASMDEFS_H__ +#define __ASMDEFS_H__ + +//***************************************************************************** +// +// The defines required for code_red. +// +//***************************************************************************** +#ifdef codered + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler nmenonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // codered + +//***************************************************************************** +// +// The defines required for EW-ARM. +// +//***************************************************************************** +#ifdef ewarm + +// +// Section headers. +// +#define __LIBRARY__ module +#define __TEXT__ rseg CODE:CODE(2) +#define __DATA__ rseg DATA:DATA(2) +#define __BSS__ rseg DATA:DATA(2) +#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2) + +// +// Assembler nmenonics. +// +#define __ALIGN__ alignrom 2 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ thumb +#define __WORD__ dcd +#define __INLINE_DATA__ data + +#endif // ewarm + +//***************************************************************************** +// +// The defines required for GCC. +// +//***************************************************************************** +#if defined(gcc) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler nmenonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // gcc + +//***************************************************************************** +// +// The defines required for RV-MDK. +// +//***************************************************************************** +#ifdef rvmdk + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + thumb + require8 + preserve8 + +// +// Section headers. +// +#define __LIBRARY__ ; +#define __TEXT__ area ||.text||, code, readonly, align=2 +#define __DATA__ area ||.data||, data, align=2 +#define __BSS__ area ||.bss||, noinit, align=2 +#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2 + +// +// Assembler nmenonics. +// +#define __ALIGN__ align 4 +#define __END__ end +#define __EXPORT__ export +#define __IMPORT__ import +#define __LABEL__ +#define __STR__ dcb +#define __THUMB_LABEL__ +#define __WORD__ dcd +#define __INLINE_DATA__ + +#endif // rvmdk + +//***************************************************************************** +// +// The defines required for Sourcery G++. +// +//***************************************************************************** +#if defined(sourcerygxx) + +// +// The assembly code preamble required to put the assembler into the correct +// configuration. +// + .syntax unified + .thumb + +// +// Section headers. +// +#define __LIBRARY__ @ +#define __TEXT__ .text +#define __DATA__ .data +#define __BSS__ .bss +#define __TEXT_NOROOT__ .text + +// +// Assembler nmenonics. +// +#define __ALIGN__ .balign 4 +#define __END__ .end +#define __EXPORT__ .globl +#define __IMPORT__ .extern +#define __LABEL__ : +#define __STR__ .ascii +#define __THUMB_LABEL__ .thumb_func +#define __WORD__ .word +#define __INLINE_DATA__ + +#endif // sourcerygxx + +#endif // __ASMDEF_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_adc.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_adc.h new file mode 100644 index 00000000..525ce905 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_adc.h @@ -0,0 +1,888 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_ADC_H__ +#define __HW_ADC_H__ + +//***************************************************************************** +// +// The following are defines for the ADC register offsets. +// +//***************************************************************************** +#define ADC_O_ADC_CTRL 0x00000000 // ADC control register. +#define ADC_O_adc_ch0_gain 0x00000004 // Channel 0 gain setting +#define ADC_O_adc_ch1_gain 0x00000008 // Channel 1 gain setting +#define ADC_O_adc_ch2_gain 0x0000000C // Channel 2 gain setting +#define ADC_O_adc_ch3_gain 0x00000010 // Channel 3 gain setting +#define ADC_O_adc_ch4_gain 0x00000014 // Channel 4 gain setting +#define ADC_O_adc_ch5_gain 0x00000018 // Channel 5 gain setting +#define ADC_O_adc_ch6_gain 0x0000001C // Channel 6 gain setting +#define ADC_O_adc_ch7_gain 0x00000020 // Channel 7 gain setting +#define ADC_O_adc_ch0_irq_en 0x00000024 // Channel 0 interrupt enable + // register +#define ADC_O_adc_ch1_irq_en 0x00000028 // Channel 1 interrupt enable + // register +#define ADC_O_adc_ch2_irq_en 0x0000002C // Channel 2 interrupt enable + // register +#define ADC_O_adc_ch3_irq_en 0x00000030 // Channel 3 interrupt enable + // register +#define ADC_O_adc_ch4_irq_en 0x00000034 // Channel 4 interrupt enable + // register +#define ADC_O_adc_ch5_irq_en 0x00000038 // Channel 5 interrupt enable + // register +#define ADC_O_adc_ch6_irq_en 0x0000003C // Channel 6 interrupt enable + // register +#define ADC_O_adc_ch7_irq_en 0x00000040 // Channel 7 interrupt enable + // register +#define ADC_O_adc_ch0_irq_status \ + 0x00000044 // Channel 0 interrupt status + // register + +#define ADC_O_adc_ch1_irq_status \ + 0x00000048 // Channel 1 interrupt status + // register + +#define ADC_O_adc_ch2_irq_status \ + 0x0000004C + +#define ADC_O_adc_ch3_irq_status \ + 0x00000050 // Channel 3 interrupt status + // register + +#define ADC_O_adc_ch4_irq_status \ + 0x00000054 // Channel 4 interrupt status + // register + +#define ADC_O_adc_ch5_irq_status \ + 0x00000058 + +#define ADC_O_adc_ch6_irq_status \ + 0x0000005C // Channel 6 interrupt status + // register + +#define ADC_O_adc_ch7_irq_status \ + 0x00000060 // Channel 7 interrupt status + // register + +#define ADC_O_adc_dma_mode_en 0x00000064 // DMA mode enable register +#define ADC_O_adc_timer_configuration \ + 0x00000068 // ADC timer configuration register + +#define ADC_O_adc_timer_current_count \ + 0x00000070 // ADC timer current count register + +#define ADC_O_channel0FIFODATA 0x00000074 // CH0 FIFO DATA register +#define ADC_O_channel1FIFODATA 0x00000078 // CH1 FIFO DATA register +#define ADC_O_channel2FIFODATA 0x0000007C // CH2 FIFO DATA register +#define ADC_O_channel3FIFODATA 0x00000080 // CH3 FIFO DATA register +#define ADC_O_channel4FIFODATA 0x00000084 // CH4 FIFO DATA register +#define ADC_O_channel5FIFODATA 0x00000088 // CH5 FIFO DATA register +#define ADC_O_channel6FIFODATA 0x0000008C // CH6 FIFO DATA register +#define ADC_O_channel7FIFODATA 0x00000090 // CH7 FIFO DATA register +#define ADC_O_adc_ch0_fifo_lvl 0x00000094 // channel 0 FIFO Level register +#define ADC_O_adc_ch1_fifo_lvl 0x00000098 // Channel 1 interrupt status + // register +#define ADC_O_adc_ch2_fifo_lvl 0x0000009C +#define ADC_O_adc_ch3_fifo_lvl 0x000000A0 // Channel 3 interrupt status + // register +#define ADC_O_adc_ch4_fifo_lvl 0x000000A4 // Channel 4 interrupt status + // register +#define ADC_O_adc_ch5_fifo_lvl 0x000000A8 +#define ADC_O_adc_ch6_fifo_lvl 0x000000AC // Channel 6 interrupt status + // register +#define ADC_O_adc_ch7_fifo_lvl 0x000000B0 // Channel 7 interrupt status + // register + +#define ADC_O_ADC_CH_ENABLE 0x000000B8 + +//****************************************************************************** +// +// The following are defines for the bit fields in the ADC_O_ADC_CTRL register. +// +//****************************************************************************** +#define ADC_ADC_CTRL_adc_cap_scale \ + 0x00000020 // ADC CAP SCALE. + +#define ADC_ADC_CTRL_adc_buf_bypass \ + 0x00000010 // ADC ANA CIO buffer bypass. + // Signal is modelled in ANA TOP. + // When '1': ADC buffer is bypassed. + +#define ADC_ADC_CTRL_adc_buf_en 0x00000008 // ADC ANA buffer enable. When 1: + // ADC buffer is enabled. +#define ADC_ADC_CTRL_adc_core_en \ + 0x00000004 // ANA ADC core en. This signal act + // as glbal enable to ADC CIO. When + // 1: ADC core is enabled. + +#define ADC_ADC_CTRL_adc_soft_reset \ + 0x00000002 // ADC soft reset. When '1' : reset + // ADC internal logic. + +#define ADC_ADC_CTRL_adc_en 0x00000001 // ADC global enable. When set ADC + // module is enabled +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch0_gain register. +// +//****************************************************************************** +#define ADC_adc_ch0_gain_adc_channel0_gain_M \ + 0x00000003 // gain setting for ADC channel 0. + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch0_gain_adc_channel0_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch1_gain register. +// +//****************************************************************************** +#define ADC_adc_ch1_gain_adc_channel1_gain_M \ + 0x00000003 // gain setting for ADC channel 1. + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch1_gain_adc_channel1_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch2_gain register. +// +//****************************************************************************** +#define ADC_adc_ch2_gain_adc_channel2_gain_M \ + 0x00000003 // gain setting for ADC channel 2. + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch2_gain_adc_channel2_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch3_gain register. +// +//****************************************************************************** +#define ADC_adc_ch3_gain_adc_channel3_gain_M \ + 0x00000003 // gain setting for ADC channel 3. + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch3_gain_adc_channel3_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch4_gain register. +// +//****************************************************************************** +#define ADC_adc_ch4_gain_adc_channel4_gain_M \ + 0x00000003 // gain setting for ADC channel 4 + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch4_gain_adc_channel4_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch5_gain register. +// +//****************************************************************************** +#define ADC_adc_ch5_gain_adc_channel5_gain_M \ + 0x00000003 // gain setting for ADC channel 5. + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch5_gain_adc_channel5_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch6_gain register. +// +//****************************************************************************** +#define ADC_adc_ch6_gain_adc_channel6_gain_M \ + 0x00000003 // gain setting for ADC channel 6 + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch6_gain_adc_channel6_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch7_gain register. +// +//****************************************************************************** +#define ADC_adc_ch7_gain_adc_channel7_gain_M \ + 0x00000003 // gain setting for ADC channel 7. + // when "00": 1x when "01: 2x when + // "10":3x when "11" 4x + +#define ADC_adc_ch7_gain_adc_channel7_gain_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch0_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch0_irq_en_adc_channel0_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch0_irq_en_adc_channel0_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch1_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch1_irq_en_adc_channel1_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch1_irq_en_adc_channel1_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch2_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch2_irq_en_adc_channel2_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch2_irq_en_adc_channel2_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch3_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch3_irq_en_adc_channel3_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch3_irq_en_adc_channel3_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch4_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch4_irq_en_adc_channel4_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch4_irq_en_adc_channel4_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch5_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch5_irq_en_adc_channel5_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch5_irq_en_adc_channel5_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch6_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch6_irq_en_adc_channel6_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch6_irq_en_adc_channel6_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch7_irq_en register. +// +//****************************************************************************** +#define ADC_adc_ch7_irq_en_adc_channel7_irq_en_M \ + 0x0000000F // interrupt enable register for + // per ADC channel bit 3: when '1' + // -> enable FIFO overflow interrupt + // bit 2: when '1' -> enable FIFO + // underflow interrupt bit 1: when + // "1' -> enable FIFO empty + // interrupt bit 0: when "1" -> + // enable FIFO full interrupt + +#define ADC_adc_ch7_irq_en_adc_channel7_irq_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch0_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch0_irq_status_adc_channel0_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch0_irq_status_adc_channel0_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch1_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch1_irq_status_adc_channel1_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch1_irq_status_adc_channel1_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch2_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch2_irq_status_adc_channel2_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch2_irq_status_adc_channel2_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch3_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch3_irq_status_adc_channel3_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch3_irq_status_adc_channel3_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch4_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch4_irq_status_adc_channel4_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch4_irq_status_adc_channel4_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch5_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch5_irq_status_adc_channel5_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch5_irq_status_adc_channel5_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch6_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch6_irq_status_adc_channel6_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch6_irq_status_adc_channel6_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch7_irq_status register. +// +//****************************************************************************** +#define ADC_adc_ch7_irq_status_adc_channel7_irq_status_M \ + 0x0000000F // interrupt status register for + // per ADC channel. Interrupt status + // can be cleared on write. bit 3: + // when value '1' is written -> + // would clear FIFO overflow + // interrupt status in the next + // cycle. if same interrupt is set + // in the same cycle then interurpt + // would be set and clear command + // will be ignored. bit 2: when + // value '1' is written -> would + // clear FIFO underflow interrupt + // status in the next cycle. bit 1: + // when value '1' is written -> + // would clear FIFO empty interrupt + // status in the next cycle. bit 0: + // when value '1' is written -> + // would clear FIFO full interrupt + // status in the next cycle. + +#define ADC_adc_ch7_irq_status_adc_channel7_irq_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_dma_mode_en register. +// +//****************************************************************************** +#define ADC_adc_dma_mode_en_DMA_MODEenable_M \ + 0x000000FF // this register enable DMA mode. + // when '1' respective ADC channel + // is enabled for DMA. When '0' only + // interrupt mode is enabled. Bit 0: + // channel 0 DMA mode enable. Bit 1: + // channel 1 DMA mode enable. Bit 2: + // channel 2 DMA mode enable. Bit 3: + // channel 3 DMA mode enable. bit 4: + // channel 4 DMA mode enable. bit 5: + // channel 5 DMA mode enable. bit 6: + // channel 6 DMA mode enable. bit 7: + // channel 7 DMA mode enable. + +#define ADC_adc_dma_mode_en_DMA_MODEenable_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_timer_configuration register. +// +//****************************************************************************** +#define ADC_adc_timer_configuration_timeren \ + 0x02000000 // when '1' timer is enabled. + +#define ADC_adc_timer_configuration_timerreset \ + 0x01000000 // when '1' reset timer. + +#define ADC_adc_timer_configuration_timercount_M \ + 0x00FFFFFF // Timer count configuration. 17 + // bit counter is supported. Other + // MSB's are redundent. + +#define ADC_adc_timer_configuration_timercount_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_timer_current_count register. +// +//****************************************************************************** +#define ADC_adc_timer_current_count_timercurrentcount_M \ + 0x0001FFFF // Timer count configuration + +#define ADC_adc_timer_current_count_timercurrentcount_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel0FIFODATA register. +// +//****************************************************************************** +#define ADC_channel0FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel0FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel1FIFODATA register. +// +//****************************************************************************** +#define ADC_channel1FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel1FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel2FIFODATA register. +// +//****************************************************************************** +#define ADC_channel2FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel2FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel3FIFODATA register. +// +//****************************************************************************** +#define ADC_channel3FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel3FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel4FIFODATA register. +// +//****************************************************************************** +#define ADC_channel4FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel4FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel5FIFODATA register. +// +//****************************************************************************** +#define ADC_channel5FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel5FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel6FIFODATA register. +// +//****************************************************************************** +#define ADC_channel6FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel6FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_channel7FIFODATA register. +// +//****************************************************************************** +#define ADC_channel7FIFODATA_FIFO_RD_DATA_M \ + 0xFFFFFFFF // read to this register would + // return ADC data along with time + // stamp information in following + // format: bits [13:0] : ADC sample + // bits [31:14]: : time stamp per + // ADC sample + +#define ADC_channel7FIFODATA_FIFO_RD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch0_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch0_fifo_lvl_adc_channel0_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch1_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch1_fifo_lvl_adc_channel1_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch2_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch2_fifo_lvl_adc_channel2_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch3_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch3_fifo_lvl_adc_channel3_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch4_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch4_fifo_lvl_adc_channel4_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch5_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch5_fifo_lvl_adc_channel5_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch6_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch6_fifo_lvl_adc_channel6_fifo_lvl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// ADC_O_adc_ch7_fifo_lvl register. +// +//****************************************************************************** +#define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_M \ + 0x00000007 // This register shows current FIFO + // level. FIFO is 4 word wide. + // Possible supported levels are : + // 0x0 to 0x3 + +#define ADC_adc_ch7_fifo_lvl_adc_channel7_fifo_lvl_S 0 + + + +#endif // __HW_ADC_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_aes.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_aes.h new file mode 100644 index 00000000..3ab0398b --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_aes.h @@ -0,0 +1,802 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_AES_H__ +#define __HW_AES_H__ + +//***************************************************************************** +// +// The following are defines for the AES_P register offsets. +// +//***************************************************************************** +#define AES_O_KEY2_6 0x00000000 // XTS second key / CBC-MAC third + // key +#define AES_O_KEY2_7 0x00000004 // XTS second key (MSW for 256-bit + // key) / CBC-MAC third key (MSW) +#define AES_O_KEY2_4 0x00000008 // XTS / CCM second key / CBC-MAC + // third key (LSW) +#define AES_O_KEY2_5 0x0000000C // XTS second key (MSW for 192-bit + // key) / CBC-MAC third key +#define AES_O_KEY2_2 0x00000010 // XTS / CCM / CBC-MAC second key / + // Hash Key input +#define AES_O_KEY2_3 0x00000014 // XTS second key (MSW for 128-bit + // key) + CCM/CBC-MAC second key + // (MSW) / Hash Key input (MSW) +#define AES_O_KEY2_0 0x00000018 // XTS / CCM / CBC-MAC second key + // (LSW) / Hash Key input (LSW) +#define AES_O_KEY2_1 0x0000001C // XTS / CCM / CBC-MAC second key / + // Hash Key input +#define AES_O_KEY1_6 0x00000020 // Key (LSW for 256-bit key) +#define AES_O_KEY1_7 0x00000024 // Key (MSW for 256-bit key) +#define AES_O_KEY1_4 0x00000028 // Key (LSW for 192-bit key) +#define AES_O_KEY1_5 0x0000002C // Key (MSW for 192-bit key) +#define AES_O_KEY1_2 0x00000030 // Key +#define AES_O_KEY1_3 0x00000034 // Key (MSW for 128-bit key) +#define AES_O_KEY1_0 0x00000038 // Key (LSW for 128-bit key) +#define AES_O_KEY1_1 0x0000003C // Key +#define AES_O_IV_IN_0 0x00000040 // Initialization Vector input + // (LSW) +#define AES_O_IV_IN_1 0x00000044 // Initialization vector input +#define AES_O_IV_IN_2 0x00000048 // Initialization vector input +#define AES_O_IV_IN_3 0x0000004C // Initialization Vector input + // (MSW) +#define AES_O_CTRL 0x00000050 // register determines the mode of + // operation of the AES Engine +#define AES_O_C_LENGTH_0 0x00000054 // Crypto data length registers + // (LSW and MSW) store the + // cryptographic data length in + // bytes for all modes. Once + // processing with this context is + // started@@ this length decrements + // to zero. Data lengths up to (2^61 + // – 1) bytes are allowed. For GCM@@ + // any value up to 2^36 - 32 bytes + // can be used. This is because a + // 32-bit counter mode is used; the + // maximum number of 128-bit blocks + // is 2^32 – 2@@ resulting in a + // maximum number of bytes of 2^36 - + // 32. A write to this register + // triggers the engine to start + // using this context. This is valid + // for all modes except GCM and CCM. + // Note that for the combined + // modes@@ this length does not + // include the authentication only + // data; the authentication length + // is specified in the + // AES_AUTH_LENGTH register below. + // All modes must have a length > 0. + // For the combined modes@@ it is + // allowed to have one of the + // lengths equal to zero. For the + // basic encryption modes + // (ECB/CBC/CTR/ICM/CFB128) it is + // allowed to program zero to the + // length field; in that case the + // length is assumed infinite. All + // data must be byte (8-bit) + // aligned; bit aligned data streams + // are not supported by the AES + // Engine. For a Host read + // operation@@ these registers + // return all-zeroes. +#define AES_O_C_LENGTH_1 0x00000058 // Crypto data length registers + // (LSW and MSW) store the + // cryptographic data length in + // bytes for all modes. Once + // processing with this context is + // started@@ this length decrements + // to zero. Data lengths up to (2^61 + // – 1) bytes are allowed. For GCM@@ + // any value up to 2^36 - 32 bytes + // can be used. This is because a + // 32-bit counter mode is used; the + // maximum number of 128-bit blocks + // is 2^32 – 2@@ resulting in a + // maximum number of bytes of 2^36 - + // 32. A write to this register + // triggers the engine to start + // using this context. This is valid + // for all modes except GCM and CCM. + // Note that for the combined + // modes@@ this length does not + // include the authentication only + // data; the authentication length + // is specified in the + // AES_AUTH_LENGTH register below. + // All modes must have a length > 0. + // For the combined modes@@ it is + // allowed to have one of the + // lengths equal to zero. For the + // basic encryption modes + // (ECB/CBC/CTR/ICM/CFB128) it is + // allowed to program zero to the + // length field; in that case the + // length is assumed infinite. All + // data must be byte (8-bit) + // aligned; bit aligned data streams + // are not supported by the AES + // Engine. For a Host read + // operation@@ these registers + // return all-zeroes. +#define AES_O_AUTH_LENGTH 0x0000005C // AAD data length. The + // authentication length register + // store the authentication data + // length in bytes for combined + // modes only (GCM or CCM) Supported + // AAD-lengths for CCM are from 0 to + // (2^16 - 2^8) bytes. For GCM any + // value up to (2^32 - 1) bytes can + // be used. Once processing with + // this context is started@@ this + // length decrements to zero. A + // write to this register triggers + // the engine to start using this + // context for GCM and CCM. For XTS + // this register is optionally used + // to load ‘j’. Loading of ‘j’ is + // only required if ‘j’ != 0. ‘j’ is + // a 28-bit value and must be + // written to bits [31-4] of this + // register. ‘j’ represents the + // sequential number of the 128-bit + // block inside the data unit. For + // the first block in a unit@@ this + // value is zero. It is not required + // to provide a ‘j’ for each new + // data block within a unit. Note + // that it is possible to start with + // a ‘j’ unequal to zero; refer to + // Table 4 for more details. For a + // Host read operation@@ these + // registers return all-zeroes. +#define AES_O_DATA_IN_0 0x00000060 // Data register to read and write + // plaintext/ciphertext (MSW) +#define AES_O_DATA_IN_1 0x00000064 // Data register to read and write + // plaintext/ciphertext +#define AES_O_DATA_IN_2 0x00000068 // Data register to read and write + // plaintext/ciphertext +#define AES_O_DATA_IN_3 0x0000006C // Data register to read and write + // plaintext/ciphertext (LSW) +#define AES_O_TAG_OUT_0 0x00000070 +#define AES_O_TAG_OUT_1 0x00000074 +#define AES_O_TAG_OUT_2 0x00000078 +#define AES_O_TAG_OUT_3 0x0000007C +#define AES_O_REVISION 0x00000080 // Register AES_REVISION +#define AES_O_SYSCONFIG 0x00000084 // Register AES_SYSCONFIG.This + // register configures the DMA + // signals and controls the IDLE and + // reset logic +#define AES_O_SYSSTATUS 0x00000088 +#define AES_O_IRQSTATUS 0x0000008C // This register indicates the + // interrupt status. If one of the + // interrupt bits is set the + // interrupt output will be asserted +#define AES_O_IRQENABLE 0x00000090 // This register contains an enable + // bit for each unique interrupt + // generated by the module. It + // matches the layout of + // AES_IRQSTATUS register. An + // interrupt is enabled when the bit + // in this register is set to ‘1’. + // An interrupt that is enabled is + // propagated to the SINTREQUEST_x + // output. All interrupts need to be + // enabled explicitly by writing + // this register. + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_6 register. +// +//****************************************************************************** +#define AES_KEY2_6_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_6_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_7 register. +// +//****************************************************************************** +#define AES_KEY2_7_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_7_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_4 register. +// +//****************************************************************************** +#define AES_KEY2_4_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_4_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_5 register. +// +//****************************************************************************** +#define AES_KEY2_5_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_5_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_2 register. +// +//****************************************************************************** +#define AES_KEY2_2_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_2_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_3 register. +// +//****************************************************************************** +#define AES_KEY2_3_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_3_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_0 register. +// +//****************************************************************************** +#define AES_KEY2_0_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_0_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY2_1 register. +// +//****************************************************************************** +#define AES_KEY2_1_KEY_M 0xFFFFFFFF // key data +#define AES_KEY2_1_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_6 register. +// +//****************************************************************************** +#define AES_KEY1_6_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_6_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_7 register. +// +//****************************************************************************** +#define AES_KEY1_7_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_7_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_4 register. +// +//****************************************************************************** +#define AES_KEY1_4_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_4_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_5 register. +// +//****************************************************************************** +#define AES_KEY1_5_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_5_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_2 register. +// +//****************************************************************************** +#define AES_KEY1_2_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_2_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_3 register. +// +//****************************************************************************** +#define AES_KEY1_3_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_3_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_0 register. +// +//****************************************************************************** +#define AES_KEY1_0_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_0_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_KEY1_1 register. +// +//****************************************************************************** +#define AES_KEY1_1_KEY_M 0xFFFFFFFF // key data +#define AES_KEY1_1_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IV_IN_0 register. +// +//****************************************************************************** +#define AES_IV_IN_0_DATA_M 0xFFFFFFFF // IV data +#define AES_IV_IN_0_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IV_IN_1 register. +// +//****************************************************************************** +#define AES_IV_IN_1_DATA_M 0xFFFFFFFF // IV data +#define AES_IV_IN_1_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IV_IN_2 register. +// +//****************************************************************************** +#define AES_IV_IN_2_DATA_M 0xFFFFFFFF // IV data +#define AES_IV_IN_2_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IV_IN_3 register. +// +//****************************************************************************** +#define AES_IV_IN_3_DATA_M 0xFFFFFFFF // IV data +#define AES_IV_IN_3_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_CTRL register. +// +//****************************************************************************** +#define AES_CTRL_CONTEXT_READY \ + 0x80000000 // If ‘1’@@ this read-only status + // bit indicates that the context + // data registers can be overwritten + // and the host is permitted to + // write the next context. + +#define AES_CTRL_SVCTXTRDY \ + 0x40000000 // If ‘1’@@ this read-only status + // bit indicates that an AES + // authentication TAG and/or IV + // block(s) is/are available for the + // host to retrieve. This bit is + // only asserted if the + // ‘save_context’ bit is set to ‘1’. + // The bit is mutual exclusive with + // the ‘context_ready’ bit. + +#define AES_CTRL_SAVE_CONTEXT 0x20000000 // This bit is used to indicate + // that an authentication TAG or + // result IV needs to be stored as a + // result context. If this bit is + // set@@ context output DMA and/or + // interrupt will be asserted if the + // operation is finished and related + // signals are enabled. +#define AES_CTRL_CCM_M 0x01C00000 // Defines “M” that indicated the + // length of the authentication + // field for CCM operations; the + // authentication field length + // equals two times (the value of + // CCM-M plus one). Note that the + // AES Engine always returns a + // 128-bit authentication field@@ of + // which the M least significant + // bytes are valid. All values are + // supported. +#define AES_CTRL_CCM_S 22 +#define AES_CTRL_CCM_L_M 0x00380000 // Defines “L” that indicated the + // width of the length field for CCM + // operations; the length field in + // bytes equals the value of CMM-L + // plus one. Supported values for L + // are (programmed value): 2 (1)@@ 4 + // (3) and 8 (7). +#define AES_CTRL_CCM_L_S 19 +#define AES_CTRL_CCM 0x00040000 // AES-CCM is selected@@ this is a + // combined mode@@ using AES for + // both authentication and + // encryption. No additional mode + // selection is required. 0 Other + // mode selected 1 ccm mode selected +#define AES_CTRL_GCM_M 0x00030000 // AES-GCM mode is selected.this is + // a combined mode@@ using the + // Galois field multiplier GF(2^128) + // for authentication and AES-CTR + // mode for encryption@@ the bits + // specify the GCM mode. 0x0 No + // operation 0x1 GHASH with H loaded + // and Y0-encrypted forced to zero + // 0x2 GHASH with H loaded and + // Y0-encrypted calculated + // internally 0x3 Autonomous GHASH + // (both H and Y0-encrypted + // calculated internally) +#define AES_CTRL_GCM_S 16 +#define AES_CTRL_CBCMAC 0x00008000 // AES-CBC MAC is selected@@ the + // Direction bit must be set to ‘1’ + // for this mode. 0 Other mode + // selected 1 cbcmac mode selected +#define AES_CTRL_F9 0x00004000 // AES f9 mode is selected@@ the + // AES key size must be set to + // 128-bit for this mode. 0 Other + // mode selected 1 f9 selected +#define AES_CTRL_F8 0x00002000 // AES f8 mode is selected@@ the + // AES key size must be set to + // 128-bit for this mode. 0 Other + // mode selected 1 f8 selected +#define AES_CTRL_XTS_M 0x00001800 // AES-XTS operation is selected; + // the bits specify the XTS mode.01 + // = Previous/intermediate tweak + // value and ‘j’ loaded (value is + // loaded via IV@@ j is loaded via + // the AAD length register) 0x0 No + // operation 0x1 + // Previous/intermediate tweak value + // and ‘j’ loaded (value is loaded + // via IV@@ j is loaded via the AAD + // length register) 0x2 Key2@@ i and + // j loaded (i is loaded via IV@@ j + // is loaded via the AAD length + // register) 0x3 Key2 and i loaded@@ + // j=0 (i is loaded via IV) +#define AES_CTRL_XTS_S 11 +#define AES_CTRL_CFB 0x00000400 // full block AES cipher feedback + // mode (CFB128) is selected. 0 + // other mode selected 1 cfb + // selected +#define AES_CTRL_ICM 0x00000200 // AES integer counter mode (ICM) + // is selected@@ this is a counter + // mode with a 16-bit wide counter. + // 0 Other mode selected. 1 ICM mode + // selected +#define AES_CTRL_CTR_WIDTH_M 0x00000180 // Specifies the counter width for + // AES-CTR mode 0x0 Counter is 32 + // bits 0x1 Counter is 64 bits 0x2 + // Counter is 128 bits 0x3 Counter + // is 192 bits +#define AES_CTRL_CTR_WIDTH_S 7 +#define AES_CTRL_CTR 0x00000040 // Tthis bit must also be set for + // GCM and CCM@@ when + // encryption/decryption is + // required. 0 Other mode selected 1 + // Counter mode +#define AES_CTRL_MODE 0x00000020 // ecb/cbc mode 0 ecb mode 1 cbc + // mode +#define AES_CTRL_KEY_SIZE_M 0x00000018 // key size 0x0 reserved 0x1 Key is + // 128 bits. 0x2 Key is 192 bits 0x3 + // Key is 256 +#define AES_CTRL_KEY_SIZE_S 3 +#define AES_CTRL_DIRECTION 0x00000004 // If set to ‘1’ an encrypt + // operation is performed. If set to + // ‘0’ a decrypt operation is + // performed. Read 0 decryption is + // selected Read 1 Encryption is + // selected +#define AES_CTRL_INPUT_READY 0x00000002 // If ‘1’@@ this read-only status + // bit indicates that the 16-byte + // input buffer is empty@@ and the + // host is permitted to write the + // next block of data. +#define AES_CTRL_OUTPUT_READY 0x00000001 // If ‘1’@@ this read-only status + // bit indicates that an AES output + // block is available for the host + // to retrieve. +//****************************************************************************** +// +// The following are defines for the bit fields in the +// AES_O_C_LENGTH_0 register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the +// AES_O_C_LENGTH_1 register. +// +//****************************************************************************** +#define AES_C_LENGTH_1_LENGTH_M \ + 0x1FFFFFFF // Data length (MSW) length + // registers (LSW and MSW) store the + // cryptographic data length in + // bytes for all modes. Once + // processing with this context is + // started@@ this length decrements + // to zero. Data lengths up to (2^61 + // – 1) bytes are allowed. For GCM@@ + // any value up to 2^36 - 32 bytes + // can be used. This is because a + // 32-bit counter mode is used; the + // maximum number of 128-bit blocks + // is 2^32 – 2@@ resulting in a + // maximum number of bytes of 2^36 - + // 32. A write to this register + // triggers the engine to start + // using this context. This is valid + // for all modes except GCM and CCM. + // Note that for the combined + // modes@@ this length does not + // include the authentication only + // data; the authentication length + // is specified in the + // AES_AUTH_LENGTH register below. + // All modes must have a length > 0. + // For the combined modes@@ it is + // allowed to have one of the + // lengths equal to zero. For the + // basic encryption modes + // (ECB/CBC/CTR/ICM/CFB128) it is + // allowed to program zero to the + // length field; in that case the + // length is assumed infinite. All + // data must be byte (8-bit) + // aligned; bit aligned data streams + // are not supported by the AES + // Engine. For a Host read + // operation@@ these registers + // return all-zeroes. + +#define AES_C_LENGTH_1_LENGTH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// AES_O_AUTH_LENGTH register. +// +//****************************************************************************** +#define AES_AUTH_LENGTH_AUTH_M \ + 0xFFFFFFFF // data + +#define AES_AUTH_LENGTH_AUTH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DATA_IN_0 register. +// +//****************************************************************************** +#define AES_DATA_IN_0_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt +#define AES_DATA_IN_0_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DATA_IN_1 register. +// +//****************************************************************************** +#define AES_DATA_IN_1_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt +#define AES_DATA_IN_1_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DATA_IN_2 register. +// +//****************************************************************************** +#define AES_DATA_IN_2_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt +#define AES_DATA_IN_2_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_DATA_IN_3 register. +// +//****************************************************************************** +#define AES_DATA_IN_3_DATA_M 0xFFFFFFFF // Data to encrypt/decrypt +#define AES_DATA_IN_3_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_TAG_OUT_0 register. +// +//****************************************************************************** +#define AES_TAG_OUT_0_HASH_M 0xFFFFFFFF // Hash result (MSW) +#define AES_TAG_OUT_0_HASH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_TAG_OUT_1 register. +// +//****************************************************************************** +#define AES_TAG_OUT_1_HASH_M 0xFFFFFFFF // Hash result (MSW) +#define AES_TAG_OUT_1_HASH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_TAG_OUT_2 register. +// +//****************************************************************************** +#define AES_TAG_OUT_2_HASH_M 0xFFFFFFFF // Hash result (MSW) +#define AES_TAG_OUT_2_HASH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_TAG_OUT_3 register. +// +//****************************************************************************** +#define AES_TAG_OUT_3_HASH_M 0xFFFFFFFF // Hash result (LSW) +#define AES_TAG_OUT_3_HASH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_REVISION register. +// +//****************************************************************************** +#define AES_REVISION_SCHEME_M 0xC0000000 +#define AES_REVISION_SCHEME_S 30 +#define AES_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software + // compatible module family. If + // there is no level of software + // compatibility a new Func number + // (and hence REVISION) should be + // assigned. +#define AES_REVISION_FUNC_S 16 +#define AES_REVISION_R_RTL_M 0x0000F800 // RTL Version (R)@@ maintained by + // IP design owner. RTL follows a + // numbering such as X.Y.R.Z which + // are explained in this table. R + // changes ONLY when: (1) PDS + // uploads occur which may have been + // due to spec changes (2) Bug fixes + // occur (3) Resets to '0' when X or + // Y changes. Design team has an + // internal 'Z' (customer invisible) + // number which increments on every + // drop that happens due to DV and + // RTL updates. Z resets to 0 when R + // increments. +#define AES_REVISION_R_RTL_S 11 +#define AES_REVISION_X_MAJOR_M \ + 0x00000700 // Major Revision (X)@@ maintained + // by IP specification owner. X + // changes ONLY when: (1) There is a + // major feature addition. An + // example would be adding Master + // Mode to Utopia Level2. The Func + // field (or Class/Type in old PID + // format) will remain the same. X + // does NOT change due to: (1) Bug + // fixes (2) Change in feature + // parameters. + +#define AES_REVISION_X_MAJOR_S 8 +#define AES_REVISION_CUSTOM_M 0x000000C0 +#define AES_REVISION_CUSTOM_S 6 +#define AES_REVISION_Y_MINOR_M \ + 0x0000003F // Minor Revision (Y)@@ maintained + // by IP specification owner. Y + // changes ONLY when: (1) Features + // are scaled (up or down). + // Flexibility exists in that this + // feature scalability may either be + // represented in the Y change or a + // specific register in the IP that + // indicates which features are + // exactly available. (2) When + // feature creeps from Is-Not list + // to Is list. But this may not be + // the case once it sees silicon; in + // which case X will change. Y does + // NOT change due to: (1) Bug fixes + // (2) Typos or clarifications (3) + // major functional/feature + // change/addition/deletion. Instead + // these changes may be reflected + // via R@@ S@@ X as applicable. Spec + // owner maintains a + // customer-invisible number 'S' + // which changes due to: (1) + // Typos/clarifications (2) Bug + // documentation. Note that this bug + // is not due to a spec change but + // due to implementation. + // Nevertheless@@ the spec tracks + // the IP bugs. An RTL release (say + // for silicon PG1.1) that occurs + // due to bug fix should document + // the corresponding spec number + // (X.Y.S) in its release notes. + +#define AES_REVISION_Y_MINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_SYSCONFIG register. +// +//****************************************************************************** +#define AES_SYSCONFIG_MACONTEXT_OUT_ON_DATA_OUT \ + 0x00000200 // If set to '1' the two context + // out requests + // (dma_req_context_out_en@@ Bit [8] + // above@@ and context_out interrupt + // enable@@ Bit [3] of AES_IRQENABLE + // register) are mapped on the + // corresponding data output request + // bit. In this case@@ the original + // ‘context out’ bit values are + // ignored. + +#define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN \ + 0x00000100 // If set to ‘1’@@ the DMA context + // output request is enabled (for + // context data out@@ e.g. TAG for + // authentication modes). 0 Dma + // disabled 1 Dma enabled + +#define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ + 0x00000080 // If set to ‘1’@@ the DMA context + // request is enabled. 0 Dma + // disabled 1 Dma enabled + +#define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ + 0x00000040 // If set to ‘1’@@ the DMA output + // request is enabled. 0 Dma + // disabled 1 Dma enabled + +#define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ + 0x00000020 // If set to ‘1’@@ the DMA input + // request is enabled. 0 Dma + // disabled 1 Dma enabled + +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_SYSSTATUS register. +// +//****************************************************************************** +#define AES_SYSSTATUS_RESETDONE \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IRQSTATUS register. +// +//****************************************************************************** +#define AES_IRQSTATUS_CONTEXT_OUT \ + 0x00000008 // This bit indicates + // authentication tag (and IV) + // interrupt(s) is/are active and + // triggers the interrupt output. + +#define AES_IRQSTATUS_DATA_OUT \ + 0x00000004 // This bit indicates data output + // interrupt is active and triggers + // the interrupt output. + +#define AES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input + // interrupt is active and triggers + // the interrupt output. +#define AES_IRQSTATUS_CONTEX_IN \ + 0x00000001 // This bit indicates context + // interrupt is active and triggers + // the interrupt output. + +//****************************************************************************** +// +// The following are defines for the bit fields in the AES_O_IRQENABLE register. +// +//****************************************************************************** +#define AES_IRQENABLE_CONTEXT_OUT \ + 0x00000008 // This bit indicates + // authentication tag (and IV) + // interrupt(s) is/are active and + // triggers the interrupt output. + +#define AES_IRQENABLE_DATA_OUT \ + 0x00000004 // This bit indicates data output + // interrupt is active and triggers + // the interrupt output. + +#define AES_IRQENABLE_DATA_IN 0x00000002 // This bit indicates data input + // interrupt is active and triggers + // the interrupt output. +#define AES_IRQENABLE_CONTEX_IN \ + 0x00000001 // This bit indicates context + // interrupt is active and triggers + // the interrupt output. + + + + +#endif // __HW_AES_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_apps_config.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_apps_config.h new file mode 100644 index 00000000..b8789b98 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_apps_config.h @@ -0,0 +1,747 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + + +#ifndef __HW_APPS_CONFIG_H__ +#define __HW_APPS_CONFIG_H__ + +//***************************************************************************** +// +// The following are defines for the APPS_CONFIG register offsets. +// +//***************************************************************************** +#define APPS_CONFIG_O_PATCH_TRAP_ADDR_REG \ + 0x00000000 // Patch trap address Register + // array + +#define APPS_CONFIG_O_PATCH_TRAP_EN_REG \ + 0x00000078 + +#define APPS_CONFIG_O_FAULT_STATUS_REG \ + 0x0000007C + +#define APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG \ + 0x00000080 + +#define APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG \ + 0x00000084 + +#define APPS_CONFIG_O_DMA_DONE_INT_MASK \ + 0x0000008C + +#define APPS_CONFIG_O_DMA_DONE_INT_MASK_SET \ + 0x00000090 + +#define APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR \ + 0x00000094 + +#define APPS_CONFIG_O_DMA_DONE_INT_STS_CLR \ + 0x00000098 + +#define APPS_CONFIG_O_DMA_DONE_INT_ACK \ + 0x0000009C + +#define APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED \ + 0x000000A0 + +#define APPS_CONFIG_O_DMA_DONE_INT_STS_RAW \ + 0x000000A4 + +#define APPS_CONFIG_O_FAULT_STATUS_CLR_REG \ + 0x000000A8 + +#define APPS_CONFIG_O_RESERVD_REG_0 \ + 0x000000AC + +#define APPS_CONFIG_O_GPT_TRIG_SEL \ + 0x000000B0 + +#define APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG \ + 0x000000B4 + +#define APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG \ + 0x000000B8 + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_PATCH_TRAP_ADDR_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_M \ + 0xFFFFFFFF // When PATCH_TRAP_EN[n] is set bus + // fault is generated for the + // address + // PATCH_TRAP_ADDR_REG[n][31:0] from + // Idcode bus. The exception routine + // should take care to jump to the + // location where the patch + // correspond to this address is + // kept. + +#define APPS_CONFIG_PATCH_TRAP_ADDR_REG_PATCH_TRAP_ADDR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_PATCH_TRAP_EN_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_M \ + 0x3FFFFFFF // When PATCH_TRAP_EN[n] is set bus + // fault is generated for the + // address PATCH_TRAP_ADD[n][31:0] + // from Idcode bus. The exception + // routine should take care to jump + // to the location where the patch + // correspond to this address is + // kept. + +#define APPS_CONFIG_PATCH_TRAP_EN_REG_PATCH_TRAP_EN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_FAULT_STATUS_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_M \ + 0x0000003E // This field shows because of + // which patch trap address the + // bus_fault is generated. If the + // PATCH_ERR bit is set, then it + // means the bus fault is generated + // because of + // PATCH_TRAP_ADDR_REG[2^PATCH_ERR_INDEX] + +#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR_INDEX_S 1 +#define APPS_CONFIG_FAULT_STATUS_REG_PATCH_ERR \ + 0x00000001 // This bit is set when there is a + // bus fault because of patched + // address access to the Apps boot + // rom. Write 0 to clear this + // register. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_MEMSS_WR_ERR_CLR_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_MEMSS_WR_ERR_CLR_REG_MEMSS_WR_ERR_CLR \ + 0x00000001 // This bit is set when there is a + // an error in memss write access. + // And the address causing this + // error is captured in + // MEMSS_ERR_ADDR_REG. To capture + // the next error address one have + // to clear this bit. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_MEMSS_WR_ERR_ADDR_REG register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_MASK register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_M \ + 0x0000F000 // 1= disable corresponding + // interrupt;0 = interrupt enabled + // bit 14: ADC channel 7 interrupt + // enable/disable bit 13: ADC + // channel 5 interrupt + // enable/disable bit 12: ADC + // channel 3 interrupt + // enable/disable bit 11: ADC + // channel 1 interrupt + // enable/disable + +#define APPS_CONFIG_DMA_DONE_INT_MASK_ADC_WR_DMA_DONE_INT_MASK_S 12 +#define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_WR_DMA_DONE_INT_MASK \ + 0x00000800 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_MCASP_RD_DMA_DONE_INT_MASK \ + 0x00000400 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK \ + 0x00000200 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CAM_THRESHHOLD_DMA_DONE_INT_MASK \ + 0x00000100 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_WR_DMA_DONE_INT_MASK \ + 0x00000080 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SHSPI_RD_DMA_DONE_INT_MASK \ + 0x00000040 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_WR_DMA_DONE_INT_MASK \ + 0x00000020 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_HOSTSPI_RD_DMA_DONE_INT_MASK \ + 0x00000010 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_WR_DMA_DONE_INT_MASK \ + 0x00000008 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_APPS_SPI_RD_DMA_DONE_INT_MASK \ + 0x00000004 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_WR_DMA_DONE_INT_MASK \ + 0x00000002 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SDIOM_RD_DMA_DONE_INT_MASK \ + 0x00000001 // 1= disable corresponding + // interrupt;0 = interrupt enabled + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_MASK_SET register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_M \ + 0x0000F000 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect bit 14: ADC channel 7 DMA + // Done IRQ bit 13: ADC channel 5 + // DMA Done IRQ bit 12: ADC channel + // 3 DMA Done IRQ bit 11: ADC + // channel 1 DMA Done IRQ + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_ADC_WR_DMA_DONE_INT_MASK_SET_S 12 +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_WR_DMA_DONE_INT_MASK_SET \ + 0x00000800 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_MCASP_RD_DMA_DONE_INT_MASK_SET \ + 0x00000400 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_SET \ + 0x00000200 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_CAM_THRESHHOLD_DMA_DONE_INT_MASK_SET \ + 0x00000100 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_WR_DMA_DONE_INT_MASK_SET \ + 0x00000080 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SHSPI_RD_DMA_DONE_INT_MASK_SET \ + 0x00000040 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_WR_DMA_DONE_INT_MASK_SET \ + 0x00000020 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_HOSTSPI_RD_DMA_DONE_INT_MASK_SET \ + 0x00000010 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_WR_DMA_DONE_INT_MASK_SET \ + 0x00000008 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_APPS_SPI_RD_DMA_DONE_INT_MASK_SET \ + 0x00000004 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_WR_DMA_DONE_INT_MASK_SET \ + 0x00000002 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_SET_SDIOM_RD_DMA_DONE_INT_MASK_SET \ + 0x00000001 // write 1 to set mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_MASK_CLR register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_M \ + 0x0000F000 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect bit 14: ADC channel 7 DMA + // Done IRQ mask bit 13: ADC channel + // 5 DMA Done IRQ mask bit 12: ADC + // channel 3 DMA Done IRQ mask bit + // 11: ADC channel 1 DMA Done IRQ + // mask + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_ADC_WR_DMA_DONE_INT_MASK_CLR_S 12 +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MACASP_WR_DMA_DONE_INT_MASK_CLR \ + 0x00000800 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_MCASP_RD_DMA_DONE_INT_MASK_CLR \ + 0x00000400 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_FIFO_EMPTY_DMA_DONE_INT_MASK_CLR \ + 0x00000200 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_CAM_THRESHHOLD_DMA_DONE_INT_MASK_CLR \ + 0x00000100 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_WR_DMA_DONE_INT_MASK_CLR \ + 0x00000080 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SHSPI_RD_DMA_DONE_INT_MASK_CLR \ + 0x00000040 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_WR_DMA_DONE_INT_MASK_CLR \ + 0x00000020 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_HOSTSPI_RD_DMA_DONE_INT_MASK_CLR \ + 0x00000010 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_WR_DMA_DONE_INT_MASK_CLR \ + 0x00000008 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_APPS_SPI_RD_DMA_DONE_INT_MASK_CLR \ + 0x00000004 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_WR_DMA_DONE_INT_MASK_CLR \ + 0x00000002 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +#define APPS_CONFIG_DMA_DONE_INT_MASK_CLR_SDIOM_RD_DMA_DONE_INT_MASK_CLR \ + 0x00000001 // write 1 to clear mask of the + // corresponding DMA DONE IRQ;0 = no + // effect + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_STS_CLR register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_M \ + 0xFFFFFFFF // write 1 or 0 to clear all + // DMA_DONE interrupt; + +#define APPS_CONFIG_DMA_DONE_INT_STS_CLR_DMA_INT_STS_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_ACK register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_M \ + 0x0000F000 // write 1 to clear corresponding + // interrupt; 0 = no effect; bit 14: + // ADC channel 7 DMA Done IRQ bit + // 13: ADC channel 5 DMA Done IRQ + // bit 12: ADC channel 3 DMA Done + // IRQ bit 11: ADC channel 1 DMA + // Done IRQ + +#define APPS_CONFIG_DMA_DONE_INT_ACK_ADC_WR_DMA_DONE_INT_ACK_S 12 +#define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_WR_DMA_DONE_INT_ACK \ + 0x00000800 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_MCASP_RD_DMA_DONE_INT_ACK \ + 0x00000400 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_FIFO_EMPTY_DMA_DONE_INT_ACK \ + 0x00000200 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_CAM_THRESHHOLD_DMA_DONE_INT_ACK \ + 0x00000100 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_WR_DMA_DONE_INT_ACK \ + 0x00000080 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_SHSPI_RD_DMA_DONE_INT_ACK \ + 0x00000040 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_WR_DMA_DONE_INT_ACK \ + 0x00000020 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_HOSTSPI_RD_DMA_DONE_INT_ACK \ + 0x00000010 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_WR_DMA_DONE_INT_ACK \ + 0x00000008 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_APPS_SPI_RD_DMA_DONE_INT_ACK \ + 0x00000004 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_WR_DMA_DONE_INT_ACK \ + 0x00000002 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +#define APPS_CONFIG_DMA_DONE_INT_ACK_SDIOM_RD_DMA_DONE_INT_ACK \ + 0x00000001 // write 1 to clear corresponding + // interrupt; 0 = no effect; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_STS_MASKED register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_M \ + 0x0000F000 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask bit 14: ADC + // channel 7 DMA Done IRQ bit 13: + // ADC channel 5 DMA Done IRQ bit + // 12: ADC channel 3 DMA Done IRQ + // bit 11: ADC channel 1 DMA Done + // IRQ + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_ADC_WR_DMA_DONE_INT_STS_MASKED_S 12 +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_WR_DMA_DONE_INT_STS_MASKED \ + 0x00000800 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_MCASP_RD_DMA_DONE_INT_STS_MASKED \ + 0x00000400 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_FIFO_EMPTY_DMA_DONE_INT_STS_MASKED \ + 0x00000200 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_CAM_THRESHHOLD_DMA_DONE_INT_STS_MASKED \ + 0x00000100 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_WR_DMA_DONE_INT_STS_MASKED \ + 0x00000080 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SHSPI_RD_DMA_DONE_INT_STS_MASKED \ + 0x00000040 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_WR_DMA_DONE_INT_STS_MASKED \ + 0x00000020 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_HOSTSPI_RD_DMA_DONE_INT_STS_MASKED \ + 0x00000010 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_WR_DMA_DONE_INT_STS_MASKED \ + 0x00000008 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_APPS_SPI_RD_DMA_DONE_INT_STS_MASKED \ + 0x00000004 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_WR_DMA_DONE_INT_STS_MASKED \ + 0x00000002 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +#define APPS_CONFIG_DMA_DONE_INT_STS_MASKED_SDIOM_RD_DMA_DONE_INT_STS_MASKED \ + 0x00000001 // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by DMA_DONE_INT mask + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_DMA_DONE_INT_STS_RAW register. +// +//****************************************************************************** +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_M \ + 0x0000F000 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive bit 14: ADC channel 7 + // DMA Done IRQ bit 13: ADC channel + // 5 DMA Done IRQ bit 12: ADC + // channel 3 DMA Done IRQ bit 11: + // ADC channel 1 DMA Done IRQ + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_ADC_WR_DMA_DONE_INT_STS_RAW_S 12 +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_WR_DMA_DONE_INT_STS_RAW \ + 0x00000800 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_MCASP_RD_DMA_DONE_INT_STS_RAW \ + 0x00000400 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_EPMTY_FIFO_DMA_DONE_INT_STS_RAW \ + 0x00000200 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_CAM_THRESHHOLD_DMA_DONE_INT_STS_RAW \ + 0x00000100 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_WR_DMA_DONE_INT_STS_RAW \ + 0x00000080 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SHSPI_RD_DMA_DONE_INT_STS_RAW \ + 0x00000040 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_WR_DMA_DONE_INT_STS_RAW \ + 0x00000020 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_HOSTSPI_RD_DMA_DONE_INT_STS_RAW \ + 0x00000010 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_WR_DMA_DONE_INT_STS_RAW \ + 0x00000008 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_APPS_SPI_RD_DMA_DONE_INT_STS_RAW \ + 0x00000004 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_WR_DMA_DONE_INT_STS_RAW \ + 0x00000002 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define APPS_CONFIG_DMA_DONE_INT_STS_RAW_SDIOM_RD_DMA_DONE_INT_STS_RAW \ + 0x00000001 // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_FAULT_STATUS_CLR_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_FAULT_STATUS_CLR_REG_PATCH_ERR_CLR \ + 0x00000001 // Write 1 to clear the LSB of + // FAULT_STATUS_REG + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_RESERVD_REG_0 register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_GPT_TRIG_SEL register. +// +//****************************************************************************** +#define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_M \ + 0x000000FF // This bit is implemented for GPT + // trigger mode select. GPT IP + // support 2 modes: RTC mode and + // external trigger. When this bit + // is set to logic '1': enable + // external trigger mode for APPS + // GPT CP0 and CP1 pin. bit 0: when + // set '1' enable external GPT + // trigger 0 on GPIO0 CP0 pin else + // RTC mode is selected. bit 1: when + // set '1' enable external GPT + // trigger 1 on GPIO0 CP1 pin else + // RTC mode is selected. bit 2: when + // set '1' enable external GPT + // trigger 2 on GPIO1 CP0 pin else + // RTC mode is selected. bit 3: when + // set '1' enable external GPT + // trigger 3 on GPIO1 CP1 pin else + // RTC mode is selected. bit 4: when + // set '1' enable external GPT + // trigger 4 on GPIO2 CP0 pin else + // RTC mode is selected. bit 5: when + // set '1' enable external GPT + // trigger 5 on GPIO2 CP1 pin else + // RTC mode is selected. bit 6: when + // set '1' enable external GPT + // trigger 6 on GPIO3 CP0 pin else + // RTC mode is selected. bit 7: when + // set '1' enable external GPT + // trigger 7 on GPIO3 CP1 pin else + // RTC mode is selected. + +#define APPS_CONFIG_GPT_TRIG_SEL_GPT_TRIG_SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_TOP_DIE_SPARE_DIN_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_M \ + 0x00000007 // Capture data from d2d_spare pads + +#define APPS_CONFIG_TOP_DIE_SPARE_DIN_REG_D2D_SPARE_DIN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_CONFIG_O_TOP_DIE_SPARE_DOUT_REG register. +// +//****************************************************************************** +#define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_M \ + 0x00000007 // Send data to d2d_spare pads - + // eventually this will get + // registered in top die + +#define APPS_CONFIG_TOP_DIE_SPARE_DOUT_REG_D2D_SPARE_DOUT_S 0 + + + +#endif // __HW_APPS_CONFIG_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_apps_rcm.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_apps_rcm.h new file mode 100644 index 00000000..edb52d26 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_apps_rcm.h @@ -0,0 +1,1506 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_APPS_RCM_H__ +#define __HW_APPS_RCM_H__ + +//***************************************************************************** +// +// The following are defines for the APPS_RCM register offsets. +// +//***************************************************************************** +#define APPS_RCM_O_CAMERA_CLK_GEN \ + 0x00000000 + +#define APPS_RCM_O_CAMERA_CLK_GATING \ + 0x00000004 + +#define APPS_RCM_O_CAMERA_SOFT_RESET \ + 0x00000008 + +#define APPS_RCM_O_MCASP_CLK_GATING \ + 0x00000014 + +#define APPS_RCM_O_MCASP_SOFT_RESET \ + 0x00000018 + +#define APPS_RCM_O_MMCHS_CLK_GEN \ + 0x00000020 + +#define APPS_RCM_O_MMCHS_CLK_GATING \ + 0x00000024 + +#define APPS_RCM_O_MMCHS_SOFT_RESET \ + 0x00000028 + +#define APPS_RCM_O_MCSPI_A1_CLK_GEN \ + 0x0000002C + +#define APPS_RCM_O_MCSPI_A1_CLK_GATING \ + 0x00000030 + +#define APPS_RCM_O_MCSPI_A1_SOFT_RESET \ + 0x00000034 + +#define APPS_RCM_O_MCSPI_A2_CLK_GEN \ + 0x00000038 + +#define APPS_RCM_O_MCSPI_A2_CLK_GATING \ + 0x00000040 + +#define APPS_RCM_O_MCSPI_A2_SOFT_RESET \ + 0x00000044 + +#define APPS_RCM_O_UDMA_A_CLK_GATING \ + 0x00000048 + +#define APPS_RCM_O_UDMA_A_SOFT_RESET \ + 0x0000004C + +#define APPS_RCM_O_GPIO_A_CLK_GATING \ + 0x00000050 + +#define APPS_RCM_O_GPIO_A_SOFT_RESET \ + 0x00000054 + +#define APPS_RCM_O_GPIO_B_CLK_GATING \ + 0x00000058 + +#define APPS_RCM_O_GPIO_B_SOFT_RESET \ + 0x0000005C + +#define APPS_RCM_O_GPIO_C_CLK_GATING \ + 0x00000060 + +#define APPS_RCM_O_GPIO_C_SOFT_RESET \ + 0x00000064 + +#define APPS_RCM_O_GPIO_D_CLK_GATING \ + 0x00000068 + +#define APPS_RCM_O_GPIO_D_SOFT_RESET \ + 0x0000006C + +#define APPS_RCM_O_GPIO_E_CLK_GATING \ + 0x00000070 + +#define APPS_RCM_O_GPIO_E_SOFT_RESET \ + 0x00000074 + +#define APPS_RCM_O_WDOG_A_CLK_GATING \ + 0x00000078 + +#define APPS_RCM_O_WDOG_A_SOFT_RESET \ + 0x0000007C + +#define APPS_RCM_O_UART_A0_CLK_GATING \ + 0x00000080 + +#define APPS_RCM_O_UART_A0_SOFT_RESET \ + 0x00000084 + +#define APPS_RCM_O_UART_A1_CLK_GATING \ + 0x00000088 + +#define APPS_RCM_O_UART_A1_SOFT_RESET \ + 0x0000008C + +#define APPS_RCM_O_GPT_A0_CLK_GATING \ + 0x00000090 + +#define APPS_RCM_O_GPT_A0_SOFT_RESET \ + 0x00000094 + +#define APPS_RCM_O_GPT_A1_CLK_GATING \ + 0x00000098 + +#define APPS_RCM_O_GPT_A1_SOFT_RESET \ + 0x0000009C + +#define APPS_RCM_O_GPT_A2_CLK_GATING \ + 0x000000A0 + +#define APPS_RCM_O_GPT_A2_SOFT_RESET \ + 0x000000A4 + +#define APPS_RCM_O_GPT_A3_CLK_GATING \ + 0x000000A8 + +#define APPS_RCM_O_GPT_A3_SOFT_RESET \ + 0x000000AC + +#define APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0 \ + 0x000000B0 + +#define APPS_RCM_O_MCASP_FRAC_CLK_CONFIG1 \ + 0x000000B4 + +#define APPS_RCM_O_CRYPTO_CLK_GATING \ + 0x000000B8 + +#define APPS_RCM_O_CRYPTO_SOFT_RESET \ + 0x000000BC + +#define APPS_RCM_O_MCSPI_S0_CLK_GATING \ + 0x000000C8 + +#define APPS_RCM_O_MCSPI_S0_SOFT_RESET \ + 0x000000CC + +#define APPS_RCM_O_MCSPI_S0_CLKDIV_CFG \ + 0x000000D0 + +#define APPS_RCM_O_I2C_CLK_GATING \ + 0x000000D8 + +#define APPS_RCM_O_I2C_SOFT_RESET \ + 0x000000DC + +#define APPS_RCM_O_APPS_LPDS_REQ \ + 0x000000E4 + +#define APPS_RCM_O_APPS_TURBO_REQ \ + 0x000000EC + +#define APPS_RCM_O_APPS_DSLP_WAKE_CONFIG \ + 0x00000108 + +#define APPS_RCM_O_APPS_DSLP_WAKE_TIMER_CFG \ + 0x0000010C + +#define APPS_RCM_O_APPS_RCM_SLP_WAKE_ENABLE \ + 0x00000110 + +#define APPS_RCM_O_APPS_SLP_WAKETIMER_CFG \ + 0x00000114 + +#define APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST \ + 0x00000118 + +#define APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS \ + 0x00000120 + +#define APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE \ + 0x00000124 + + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_CAMERA_CLK_GEN register. +// +//****************************************************************************** +#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_OFF_TIME_M \ + 0x00000700 // Configuration of OFF-TIME for + // dividing PLL clk (240 MHz) in + // generation of Camera func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_OFF_TIME_S 8 +#define APPS_RCM_CAMERA_CLK_GEN_NU1_M \ + 0x000000F8 + +#define APPS_RCM_CAMERA_CLK_GEN_NU1_S 3 +#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_ON_TIME_M \ + 0x00000007 // Configuration of ON-TIME for + // dividing PLL clk (240 MHz) in + // generation of Camera func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_CAMERA_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_CAMERA_CLK_GATING_NU1_M \ + 0x00FE0000 + +#define APPS_RCM_CAMERA_CLK_GATING_NU1_S 17 +#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable camera clk during + // deep-sleep mode + +#define APPS_RCM_CAMERA_CLK_GATING_NU2_M \ + 0x0000FE00 + +#define APPS_RCM_CAMERA_CLK_GATING_NU2_S 9 +#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_SLP_CLK_ENABLE \ + 0x00000100 // 1- Enable camera clk during + // sleep mode ; 0- Disable camera + // clk during sleep mode + +#define APPS_RCM_CAMERA_CLK_GATING_NU3_M \ + 0x000000FE + +#define APPS_RCM_CAMERA_CLK_GATING_NU3_S 1 +#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_RUN_CLK_ENABLE \ + 0x00000001 // 1- Enable camera clk during run + // mode ; 0- Disable camera clk + // during run mode + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_CAMERA_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_CAMERA_SOFT_RESET_CAMERA_ENABLED_STATUS \ + 0x00000002 // 1 - Camera clocks/resets are + // enabled ; 0 - Camera + // clocks/resets are disabled + +#define APPS_RCM_CAMERA_SOFT_RESET_CAMERA_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for Camera-core + // ; 0 - De-assert reset for + // Camera-core + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCASP_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_MCASP_CLK_GATING_NU1_M \ + 0x00FE0000 + +#define APPS_RCM_MCASP_CLK_GATING_NU1_S 17 +#define APPS_RCM_MCASP_CLK_GATING_MCASP_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable MCASP clk during + // deep-sleep mode + +#define APPS_RCM_MCASP_CLK_GATING_NU2_M \ + 0x0000FE00 + +#define APPS_RCM_MCASP_CLK_GATING_NU2_S 9 +#define APPS_RCM_MCASP_CLK_GATING_MCASP_SLP_CLK_ENABLE \ + 0x00000100 // 1- Enable MCASP clk during sleep + // mode ; 0- Disable MCASP clk + // during sleep mode + +#define APPS_RCM_MCASP_CLK_GATING_NU3_M \ + 0x000000FE + +#define APPS_RCM_MCASP_CLK_GATING_NU3_S 1 +#define APPS_RCM_MCASP_CLK_GATING_MCASP_RUN_CLK_ENABLE \ + 0x00000001 // 1- Enable MCASP clk during run + // mode ; 0- Disable MCASP clk + // during run mode + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCASP_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_MCASP_SOFT_RESET_MCASP_ENABLED_STATUS \ + 0x00000002 // 1 - MCASP Clocks/resets are + // enabled ; 0 - MCASP Clocks/resets + // are disabled + +#define APPS_RCM_MCASP_SOFT_RESET_MCASP_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for MCASP-core + // ; 0 - De-assert reset for + // MCASP-core + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MMCHS_CLK_GEN register. +// +//****************************************************************************** +#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_OFF_TIME_M \ + 0x00000700 // Configuration of OFF-TIME for + // dividing PLL clk (240 MHz) in + // generation of MMCHS func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_OFF_TIME_S 8 +#define APPS_RCM_MMCHS_CLK_GEN_NU1_M \ + 0x000000F8 + +#define APPS_RCM_MMCHS_CLK_GEN_NU1_S 3 +#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_ON_TIME_M \ + 0x00000007 // Configuration of ON-TIME for + // dividing PLL clk (240 MHz) in + // generation of MMCHS func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MMCHS_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_MMCHS_CLK_GATING_NU1_M \ + 0x00FE0000 + +#define APPS_RCM_MMCHS_CLK_GATING_NU1_S 17 +#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable MMCHS clk during + // deep-sleep mode + +#define APPS_RCM_MMCHS_CLK_GATING_NU2_M \ + 0x0000FE00 + +#define APPS_RCM_MMCHS_CLK_GATING_NU2_S 9 +#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_SLP_CLK_ENABLE \ + 0x00000100 // 1- Enable MMCHS clk during sleep + // mode ; 0- Disable MMCHS clk + // during sleep mode + +#define APPS_RCM_MMCHS_CLK_GATING_NU3_M \ + 0x000000FE + +#define APPS_RCM_MMCHS_CLK_GATING_NU3_S 1 +#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_RUN_CLK_ENABLE \ + 0x00000001 // 1- Enable MMCHS clk during run + // mode ; 0- Disable MMCHS clk + // during run mode + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MMCHS_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_MMCHS_SOFT_RESET_MMCHS_ENABLED_STATUS \ + 0x00000002 // 1 - MMCHS Clocks/resets are + // enabled ; 0 - MMCHS Clocks/resets + // are disabled + +#define APPS_RCM_MMCHS_SOFT_RESET_MMCHS_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for MMCHS-core + // ; 0 - De-assert reset for + // MMCHS-core + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_A1_CLK_GEN register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_BAUD_CLK_SEL \ + 0x00010000 // 0 - XTAL clk is used as baud clk + // for MCSPI_A1 ; 1 - PLL divclk is + // used as baud clk for MCSPI_A1. + +#define APPS_RCM_MCSPI_A1_CLK_GEN_NU1_M \ + 0x0000F800 + +#define APPS_RCM_MCSPI_A1_CLK_GEN_NU1_S 11 +#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_OFF_TIME_M \ + 0x00000700 // Configuration of OFF-TIME for + // dividing PLL clk (240 MHz) in + // generation of MCSPI_A1 func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_OFF_TIME_S 8 +#define APPS_RCM_MCSPI_A1_CLK_GEN_NU2_M \ + 0x000000F8 + +#define APPS_RCM_MCSPI_A1_CLK_GEN_NU2_S 3 +#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_ON_TIME_M \ + 0x00000007 // Configuration of ON-TIME for + // dividing PLL clk (240 MHz) in + // generation of MCSPI_A1 func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_A1_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_A1_CLK_GATING_NU1_M \ + 0x00FE0000 + +#define APPS_RCM_MCSPI_A1_CLK_GATING_NU1_S 17 +#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable MCSPI_A1 clk during + // deep-sleep mode + +#define APPS_RCM_MCSPI_A1_CLK_GATING_NU2_M \ + 0x0000FE00 + +#define APPS_RCM_MCSPI_A1_CLK_GATING_NU2_S 9 +#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_SLP_CLK_ENABLE \ + 0x00000100 // 1- Enable MCSPI_A1 clk during + // sleep mode ; 0- Disable MCSPI_A1 + // clk during sleep mode + +#define APPS_RCM_MCSPI_A1_CLK_GATING_NU3_M \ + 0x000000FE + +#define APPS_RCM_MCSPI_A1_CLK_GATING_NU3_S 1 +#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_RUN_CLK_ENABLE \ + 0x00000001 // 1- Enable MCSPI_A1 clk during + // run mode ; 0- Disable MCSPI_A1 + // clk during run mode + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_A1_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_A1_SOFT_RESET_MCSPI_A1_ENABLED_STATUS \ + 0x00000002 // 1 - MCSPI_A1 Clocks/Resets are + // enabled ; 0 - MCSPI_A1 + // Clocks/Resets are disabled + +#define APPS_RCM_MCSPI_A1_SOFT_RESET_MCSPI_A1_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for + // MCSPI_A1-core ; 0 - De-assert + // reset for MCSPI_A1-core + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_A2_CLK_GEN register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_BAUD_CLK_SEL \ + 0x00010000 // 0 - XTAL clk is used as baud-clk + // for MCSPI_A2 ; 1 - PLL divclk is + // used as baud-clk for MCSPI_A2 + +#define APPS_RCM_MCSPI_A2_CLK_GEN_NU1_M \ + 0x0000F800 + +#define APPS_RCM_MCSPI_A2_CLK_GEN_NU1_S 11 +#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_OFF_TIME_M \ + 0x00000700 // Configuration of OFF-TIME for + // dividing PLL clk (240 MHz) in + // generation of MCSPI_A2 func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_OFF_TIME_S 8 +#define APPS_RCM_MCSPI_A2_CLK_GEN_NU2_M \ + 0x000000F8 + +#define APPS_RCM_MCSPI_A2_CLK_GEN_NU2_S 3 +#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_ON_TIME_M \ + 0x00000007 // Configuration of OFF-TIME for + // dividing PLL clk (240 MHz) in + // generation of MCSPI_A2 func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_A2_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_A2_CLK_GATING_NU1_M \ + 0x00FE0000 + +#define APPS_RCM_MCSPI_A2_CLK_GATING_NU1_S 17 +#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable MCSPI_A2 clk during + // deep-sleep mode + +#define APPS_RCM_MCSPI_A2_CLK_GATING_NU2_M \ + 0x0000FE00 + +#define APPS_RCM_MCSPI_A2_CLK_GATING_NU2_S 9 +#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_SLP_CLK_ENABLE \ + 0x00000100 // 1- Enable MCSPI_A2 clk during + // sleep mode ; 0- Disable MCSPI_A2 + // clk during sleep mode + +#define APPS_RCM_MCSPI_A2_CLK_GATING_NU3_M \ + 0x000000FE + +#define APPS_RCM_MCSPI_A2_CLK_GATING_NU3_S 1 +#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_RUN_CLK_ENABLE \ + 0x00000001 // 1- Enable MCSPI_A2 clk during + // run mode ; 0- Disable MCSPI_A2 + // clk during run mode + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_A2_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_A2_SOFT_RESET_MCSPI_A2_ENABLED_STATUS \ + 0x00000002 // 1 - MCSPI_A2 Clocks/Resets are + // enabled ; 0 - MCSPI_A2 + // Clocks/Resets are disabled + +#define APPS_RCM_MCSPI_A2_SOFT_RESET_MCSPI_A2_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for + // MCSPI_A2-core ; 0 - De-assert + // reset for MCSPI_A2-core + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_UDMA_A_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable UDMA_A clk during + // deep-sleep mode 0 - Disable + // UDMA_A clk during deep-sleep mode + // ; + +#define APPS_RCM_UDMA_A_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_UDMA_A_CLK_GATING_NU1_S 9 +#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable UDMA_A clk during + // sleep mode 0 - Disable UDMA_A clk + // during sleep mode ; + +#define APPS_RCM_UDMA_A_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_UDMA_A_CLK_GATING_NU2_S 1 +#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable UDMA_A clk during run + // mode 0 - Disable UDMA_A clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_UDMA_A_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_UDMA_A_SOFT_RESET_UDMA_A_ENABLED_STATUS \ + 0x00000002 // 1 - UDMA_A Clocks/Resets are + // enabled ; 0 - UDMA_A + // Clocks/Resets are disabled + +#define APPS_RCM_UDMA_A_SOFT_RESET_UDMA_A_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for DMA_A ; 0 - + // De-assert reset for DMA_A + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_A_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable GPIO_A clk during + // deep-sleep mode 0 - Disable + // GPIO_A clk during deep-sleep mode + // ; + +#define APPS_RCM_GPIO_A_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPIO_A_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable GPIO_A clk during + // sleep mode 0 - Disable GPIO_A clk + // during sleep mode ; + +#define APPS_RCM_GPIO_A_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPIO_A_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable GPIO_A clk during run + // mode 0 - Disable GPIO_A clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_A_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_A_SOFT_RESET_GPIO_A_ENABLED_STATUS \ + 0x00000002 // 1 - GPIO_A Clocks/Resets are + // enabled ; 0 - GPIO_A + // Clocks/Resets are disabled + +#define APPS_RCM_GPIO_A_SOFT_RESET_GPIO_A_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for GPIO_A ; 0 + // - De-assert reset for GPIO_A + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_B_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable GPIO_B clk during + // deep-sleep mode 0 - Disable + // GPIO_B clk during deep-sleep mode + // ; + +#define APPS_RCM_GPIO_B_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPIO_B_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable GPIO_B clk during + // sleep mode 0 - Disable GPIO_B clk + // during sleep mode ; + +#define APPS_RCM_GPIO_B_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPIO_B_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable GPIO_B clk during run + // mode 0 - Disable GPIO_B clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_B_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_B_SOFT_RESET_GPIO_B_ENABLED_STATUS \ + 0x00000002 // 1 - GPIO_B Clocks/Resets are + // enabled ; 0 - GPIO_B + // Clocks/Resets are disabled + +#define APPS_RCM_GPIO_B_SOFT_RESET_GPIO_B_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for GPIO_B ; 0 + // - De-assert reset for GPIO_B + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_C_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable GPIO_C clk during + // deep-sleep mode 0 - Disable + // GPIO_C clk during deep-sleep mode + // ; + +#define APPS_RCM_GPIO_C_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPIO_C_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable GPIO_C clk during + // sleep mode 0 - Disable GPIO_C clk + // during sleep mode ; + +#define APPS_RCM_GPIO_C_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPIO_C_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable GPIO_C clk during run + // mode 0 - Disable GPIO_C clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_C_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_C_SOFT_RESET_GPIO_C_ENABLED_STATUS \ + 0x00000002 // 1 - GPIO_C Clocks/Resets are + // enabled ; 0 - GPIO_C + // Clocks/Resets are disabled + +#define APPS_RCM_GPIO_C_SOFT_RESET_GPIO_C_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for GPIO_C ; 0 + // - De-assert reset for GPIO_C + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_D_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable GPIO_D clk during + // deep-sleep mode 0 - Disable + // GPIO_D clk during deep-sleep mode + // ; + +#define APPS_RCM_GPIO_D_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPIO_D_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable GPIO_D clk during + // sleep mode 0 - Disable GPIO_D clk + // during sleep mode ; + +#define APPS_RCM_GPIO_D_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPIO_D_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable GPIO_D clk during run + // mode 0 - Disable GPIO_D clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_D_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_D_SOFT_RESET_GPIO_D_ENABLED_STATUS \ + 0x00000002 // 1 - GPIO_D Clocks/Resets are + // enabled ; 0 - GPIO_D + // Clocks/Resets are disabled + +#define APPS_RCM_GPIO_D_SOFT_RESET_GPIO_D_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for GPIO_D ; 0 + // - De-assert reset for GPIO_D + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_E_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable GPIO_E clk during + // deep-sleep mode 0 - Disable + // GPIO_E clk during deep-sleep mode + // ; + +#define APPS_RCM_GPIO_E_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPIO_E_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable GPIO_E clk during + // sleep mode 0 - Disable GPIO_E clk + // during sleep mode ; + +#define APPS_RCM_GPIO_E_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPIO_E_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable GPIO_E clk during run + // mode 0 - Disable GPIO_E clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPIO_E_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPIO_E_SOFT_RESET_GPIO_E_ENABLED_STATUS \ + 0x00000002 // 1 - GPIO_E Clocks/Resets are + // enabled ; 0 - GPIO_E + // Clocks/Resets are disabled + +#define APPS_RCM_GPIO_E_SOFT_RESET_GPIO_E_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for GPIO_E ; 0 + // - De-assert reset for GPIO_E + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_WDOG_A_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_BAUD_CLK_SEL_M \ + 0x03000000 // "00" - Sysclk ; "01" - REF_CLK + // (38.4 MHz) ; "10/11" - Slow_clk + +#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_BAUD_CLK_SEL_S 24 +#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable WDOG_A clk during + // deep-sleep mode 0 - Disable + // WDOG_A clk during deep-sleep mode + // ; + +#define APPS_RCM_WDOG_A_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_WDOG_A_CLK_GATING_NU1_S 9 +#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable WDOG_A clk during + // sleep mode 0 - Disable WDOG_A clk + // during sleep mode ; + +#define APPS_RCM_WDOG_A_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_WDOG_A_CLK_GATING_NU2_S 1 +#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable WDOG_A clk during run + // mode 0 - Disable WDOG_A clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_WDOG_A_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_WDOG_A_SOFT_RESET_WDOG_A_ENABLED_STATUS \ + 0x00000002 // 1 - WDOG_A Clocks/Resets are + // enabled ; 0 - WDOG_A + // Clocks/Resets are disabled + +#define APPS_RCM_WDOG_A_SOFT_RESET_WDOG_A_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for WDOG_A ; 0 + // - De-assert reset for WDOG_A + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_UART_A0_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable UART_A0 clk during + // deep-sleep mode 0 - Disable + // UART_A0 clk during deep-sleep + // mode ; + +#define APPS_RCM_UART_A0_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_UART_A0_CLK_GATING_NU1_S 9 +#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable UART_A0 clk during + // sleep mode 0 - Disable UART_A0 + // clk during sleep mode ; + +#define APPS_RCM_UART_A0_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_UART_A0_CLK_GATING_NU2_S 1 +#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable UART_A0 clk during + // run mode 0 - Disable UART_A0 clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_UART_A0_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_UART_A0_SOFT_RESET_UART_A0_ENABLED_STATUS \ + 0x00000002 // 1 - UART_A0 Clocks/Resets are + // enabled ; 0 - UART_A0 + // Clocks/Resets are disabled + +#define APPS_RCM_UART_A0_SOFT_RESET_UART_A0_SOFT_RESET \ + 0x00000001 // 1 - Assert reset for UART_A0 ; 0 + // - De-assert reset for UART_A0 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_UART_A1_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable UART_A1 clk during + // deep-sleep mode 0 - Disable + // UART_A1 clk during deep-sleep + // mode ; + +#define APPS_RCM_UART_A1_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_UART_A1_CLK_GATING_NU1_S 9 +#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable UART_A1 clk during + // sleep mode 0 - Disable UART_A1 + // clk during sleep mode ; + +#define APPS_RCM_UART_A1_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_UART_A1_CLK_GATING_NU2_S 1 +#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable UART_A1 clk during + // run mode 0 - Disable UART_A1 clk + // during run mode ; + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_UART_A1_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_UART_A1_SOFT_RESET_UART_A1_ENABLED_STATUS \ + 0x00000002 // 1 - UART_A1 Clocks/Resets are + // enabled ; 0 - UART_A1 + // Clocks/Resets are disabled + +#define APPS_RCM_UART_A1_SOFT_RESET_UART_A1_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // UART_A1 ; 0 - De-assert the soft + // reset for UART_A1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A0_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable the GPT_A0 clock + // during deep-sleep ; 0 - Disable + // the GPT_A0 clock during + // deep-sleep + +#define APPS_RCM_GPT_A0_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPT_A0_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the GPT_A0 clock + // during sleep ; 0 - Disable the + // GPT_A0 clock during sleep + +#define APPS_RCM_GPT_A0_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPT_A0_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the GPT_A0 clock + // during run ; 0 - Disable the + // GPT_A0 clock during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A0_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A0_SOFT_RESET_GPT_A0_ENABLED_STATUS \ + 0x00000002 // 1 - GPT_A0 clocks/resets are + // enabled ; 0 - GPT_A0 + // clocks/resets are disabled + +#define APPS_RCM_GPT_A0_SOFT_RESET_GPT_A0_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // GPT_A0 ; 0 - De-assert the soft + // reset for GPT_A0 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A1_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable the GPT_A1 clock + // during deep-sleep ; 0 - Disable + // the GPT_A1 clock during + // deep-sleep + +#define APPS_RCM_GPT_A1_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPT_A1_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the GPT_A1 clock + // during sleep ; 0 - Disable the + // GPT_A1 clock during sleep + +#define APPS_RCM_GPT_A1_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPT_A1_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the GPT_A1 clock + // during run ; 0 - Disable the + // GPT_A1 clock during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A1_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A1_SOFT_RESET_GPT_A1_ENABLED_STATUS \ + 0x00000002 // 1 - GPT_A1 clocks/resets are + // enabled ; 0 - GPT_A1 + // clocks/resets are disabled + +#define APPS_RCM_GPT_A1_SOFT_RESET_GPT_A1_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // GPT_A1 ; 0 - De-assert the soft + // reset for GPT_A1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A2_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable the GPT_A2 clock + // during deep-sleep ; 0 - Disable + // the GPT_A2 clock during + // deep-sleep + +#define APPS_RCM_GPT_A2_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPT_A2_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the GPT_A2 clock + // during sleep ; 0 - Disable the + // GPT_A2 clock during sleep + +#define APPS_RCM_GPT_A2_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPT_A2_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the GPT_A2 clock + // during run ; 0 - Disable the + // GPT_A2 clock during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A2_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A2_SOFT_RESET_GPT_A2_ENABLED_STATUS \ + 0x00000002 // 1 - GPT_A2 clocks/resets are + // enabled ; 0 - GPT_A2 + // clocks/resets are disabled + +#define APPS_RCM_GPT_A2_SOFT_RESET_GPT_A2_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // GPT_A2 ; 0 - De-assert the soft + // reset for GPT_A2 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A3_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable the GPT_A3 clock + // during deep-sleep ; 0 - Disable + // the GPT_A3 clock during + // deep-sleep + +#define APPS_RCM_GPT_A3_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_GPT_A3_CLK_GATING_NU1_S 9 +#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the GPT_A3 clock + // during sleep ; 0 - Disable the + // GPT_A3 clock during sleep + +#define APPS_RCM_GPT_A3_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_GPT_A3_CLK_GATING_NU2_S 1 +#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the GPT_A3 clock + // during run ; 0 - Disable the + // GPT_A3 clock during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_GPT_A3_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_GPT_A3_SOFT_RESET_GPT_A3_ENABLED_STATUS \ + 0x00000002 // 1 - GPT_A3 Clocks/resets are + // enabled ; 0 - GPT_A3 + // Clocks/resets are disabled + +#define APPS_RCM_GPT_A3_SOFT_RESET_GPT_A3_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // GPT_A3 ; 0 - De-assert the soft + // reset for GPT_A3 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0 register. +// +//****************************************************************************** +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_DIVISOR_M \ + 0x03FF0000 + +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_DIVISOR_S 16 +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_FRACTION_M \ + 0x0000FFFF + +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_FRACTION_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCASP_FRAC_CLK_CONFIG1 register. +// +//****************************************************************************** +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_SOFT_RESET \ + 0x00010000 // 1 - Assert the reset for MCASP + // Frac-clk div; 0 - Donot assert + // the reset for MCASP frac clk-div + +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_PERIOD_M \ + 0x000003FF + +#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_PERIOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_CRYPTO_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable the Crypto clock + // during deep-sleep + +#define APPS_RCM_CRYPTO_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_CRYPTO_CLK_GATING_NU1_S 9 +#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the Crypto clock + // during sleep ; 0 - Disable the + // Crypto clock during sleep + +#define APPS_RCM_CRYPTO_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_CRYPTO_CLK_GATING_NU2_S 1 +#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the Crypto clock + // during run ; 0 - Disable the + // Crypto clock during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_CRYPTO_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_CRYPTO_SOFT_RESET_CRYPTO_ENABLED_STATUS \ + 0x00000002 // 1 - Crypto clocks/resets are + // enabled ; 0 - Crypto + // clocks/resets are disabled + +#define APPS_RCM_CRYPTO_SOFT_RESET_CRYPTO_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // Crypto ; 0 - De-assert the soft + // reset for Crypto + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_S0_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_DSLP_CLK_ENABLE \ + 0x00010000 // 0 - Disable the MCSPI_S0 clock + // during deep-sleep + +#define APPS_RCM_MCSPI_S0_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_MCSPI_S0_CLK_GATING_NU1_S 9 +#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the MCSPI_S0 clock + // during sleep ; 0 - Disable the + // MCSPI_S0 clock during sleep + +#define APPS_RCM_MCSPI_S0_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_MCSPI_S0_CLK_GATING_NU2_S 1 +#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the MCSPI_S0 clock + // during run ; 0 - Disable the + // MCSPI_S0 clock during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_S0_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_S0_SOFT_RESET_MCSPI_S0_ENABLED_STATUS \ + 0x00000002 // 1 - MCSPI_S0 Clocks/Resets are + // enabled ; 0 - MCSPI_S0 + // Clocks/resets are disabled + +#define APPS_RCM_MCSPI_S0_SOFT_RESET_MCSPI_S0_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // MCSPI_S0 ; 0 - De-assert the soft + // reset for MCSPI_S0 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_MCSPI_S0_CLKDIV_CFG register. +// +//****************************************************************************** +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_BAUD_CLK_SEL \ + 0x00010000 // 0 - XTAL clk is used as baud-clk + // for MCSPI_S0 ; 1 - PLL divclk is + // used as buad-clk for MCSPI_S0 + +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU1_M \ + 0x0000F800 + +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU1_S 11 +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_OFF_TIME_M \ + 0x00000700 // Configuration of OFF-TIME for + // dividing PLL clk (240 MHz) in + // generation of MCSPI_S0 func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_OFF_TIME_S 8 +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU2_M \ + 0x000000F8 + +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU2_S 3 +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_ON_TIME_M \ + 0x00000007 // Configuration of ON-TIME for + // dividing PLL clk (240 MHz) in + // generation of MCSPI_S0 func-clk : + // "000" - 1 "001" - 2 "010" - 3 + // "011" - 4 "100" - 5 "101" - 6 + // "110" - 7 "111" - 8 + +#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_I2C_CLK_GATING register. +// +//****************************************************************************** +#define APPS_RCM_I2C_CLK_GATING_I2C_DSLP_CLK_ENABLE \ + 0x00010000 // 1 - Enable the I2C Clock during + // deep-sleep 0 - Disable the I2C + // clock during deep-sleep + +#define APPS_RCM_I2C_CLK_GATING_NU1_M \ + 0x0000FE00 + +#define APPS_RCM_I2C_CLK_GATING_NU1_S 9 +#define APPS_RCM_I2C_CLK_GATING_I2C_SLP_CLK_ENABLE \ + 0x00000100 // 1 - Enable the I2C clock during + // sleep ; 0 - Disable the I2C clock + // during sleep + +#define APPS_RCM_I2C_CLK_GATING_NU2_M \ + 0x000000FE + +#define APPS_RCM_I2C_CLK_GATING_NU2_S 1 +#define APPS_RCM_I2C_CLK_GATING_I2C_RUN_CLK_ENABLE \ + 0x00000001 // 1 - Enable the I2C clock during + // run ; 0 - Disable the I2C clock + // during run + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_I2C_SOFT_RESET register. +// +//****************************************************************************** +#define APPS_RCM_I2C_SOFT_RESET_I2C_ENABLED_STATUS \ + 0x00000002 // 1 - I2C Clocks/Resets are + // enabled ; 0 - I2C clocks/resets + // are disabled + +#define APPS_RCM_I2C_SOFT_RESET_I2C_SOFT_RESET \ + 0x00000001 // 1 - Assert the soft reset for + // Shared-I2C ; 0 - De-assert the + // soft reset for Shared-I2C + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_LPDS_REQ register. +// +//****************************************************************************** +#define APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ \ + 0x00000001 // 1 - Request for LPDS + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_TURBO_REQ register. +// +//****************************************************************************** +#define APPS_RCM_APPS_TURBO_REQ_APPS_TURBO_REQ \ + 0x00000001 // 1 - Request for TURBO + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_DSLP_WAKE_CONFIG register. +// +//****************************************************************************** +#define APPS_RCM_APPS_DSLP_WAKE_CONFIG_DSLP_WAKE_FROM_NWP_ENABLE \ + 0x00000002 // 1 - Enable the NWP to wake APPS + // from deep-sleep ; 0 - Disable NWP + // to wake APPS from deep-sleep + +#define APPS_RCM_APPS_DSLP_WAKE_CONFIG_DSLP_WAKE_TIMER_ENABLE \ + 0x00000001 // 1 - Enable deep-sleep wake timer + // in APPS RCM for deep-sleep; 0 - + // Disable deep-sleep wake timer in + // APPS RCM + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_DSLP_WAKE_TIMER_CFG register. +// +//****************************************************************************** +#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_OPP_CFG_M \ + 0xFFFF0000 // Configuration (in slow_clks) + // which says when to request for + // OPP during deep-sleep exit + +#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_OPP_CFG_S 16 +#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_WAKE_CFG_M \ + 0x0000FFFF // Configuration (in slow_clks) + // which says when to request for + // WAKE during deep-sleep exit + +#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_WAKE_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_RCM_SLP_WAKE_ENABLE register. +// +//****************************************************************************** +#define APPS_RCM_APPS_RCM_SLP_WAKE_ENABLE_SLP_WAKE_FROM_NWP_ENABLE \ + 0x00000002 // 1- Enable the sleep wakeup due + // to NWP request. 0- Disable the + // sleep wakeup due to NWP request + +#define APPS_RCM_APPS_RCM_SLP_WAKE_ENABLE_SLP_WAKE_TIMER_ENABLE \ + 0x00000001 // 1- Enable the sleep wakeup due + // to sleep-timer; 0-Disable the + // sleep wakeup due to sleep-timer + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_SLP_WAKETIMER_CFG register. +// +//****************************************************************************** +#define APPS_RCM_APPS_SLP_WAKETIMER_CFG_SLP_WAKE_TIMER_CFG_M \ + 0xFFFFFFFF // Configuration (number of + // sysclks-80MHz) for the Sleep + // wakeup timer + +#define APPS_RCM_APPS_SLP_WAKETIMER_CFG_SLP_WAKE_TIMER_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST register. +// +//****************************************************************************** +#define APPS_RCM_APPS_TO_NWP_WAKE_REQUEST_APPS_TO_NWP_WAKEUP_REQUEST \ + 0x00000001 // When 1 => APPS generated a wake + // request to NWP (When NWP is in + // any of its low-power modes : + // SLP/DSLP/LPDS) + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS register. +// +//****************************************************************************** +#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_deep_sleep_timer_wake \ + 0x00000008 // 1 - Indicates that deep-sleep + // timer expiry had caused the + // wakeup from deep-sleep + +#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_sleep_timer_wake \ + 0x00000004 // 1 - Indicates that sleep timer + // expiry had caused the wakeup from + // sleep + +#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_deep_sleep_wake_from_nwp \ + 0x00000002 // 1 - Indicates that NWP had + // caused the wakeup from deep-sleep + +#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_sleep_wake_from_nwp \ + 0x00000001 // 1 - Indicates that NWP had + // caused the wakeup from Sleep + + + + +#endif // __HW_APPS_RCM_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_camera.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_camera.h new file mode 100644 index 00000000..4461a284 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_camera.h @@ -0,0 +1,519 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_CAMERA_H__ +#define __HW_CAMERA_H__ + +//***************************************************************************** +// +// The following are defines for the CAMERA register offsets. +// +//***************************************************************************** +#define CAMERA_O_CC_REVISION 0x00000000 // This register contains the IP + // revision code ( Parallel Mode) +#define CAMERA_O_CC_SYSCONFIG 0x00000010 // This register controls the + // various parameters of the OCP + // interface (CCP and Parallel Mode) +#define CAMERA_O_CC_SYSSTATUS 0x00000014 // This register provides status + // information about the module + // excluding the interrupt status + // information (CCP and Parallel + // Mode) +#define CAMERA_O_CC_IRQSTATUS 0x00000018 // The interrupt status regroups + // all the status of the module + // internal events that can generate + // an interrupt (CCP & Parallel + // Mode) +#define CAMERA_O_CC_IRQENABLE 0x0000001C // The interrupt enable register + // allows to enable/disable the + // module internal sources of + // interrupt on an event-by-event + // basis (CCP & Parallel Mode) +#define CAMERA_O_CC_CTRL 0x00000040 // This register controls the + // various parameters of the Camera + // Core block (CCP & Parallel Mode) +#define CAMERA_O_CC_CTRL_DMA 0x00000044 // This register controls the DMA + // interface of the Camera Core + // block (CCP & Parallel Mode) +#define CAMERA_O_CC_CTRL_XCLK 0x00000048 // This register control the value + // of the clock divisor used to + // generate the external clock + // (Parallel Mode) +#define CAMERA_O_CC_FIFO_DATA 0x0000004C // This register allows to write to + // the FIFO and read from the FIFO + // (CCP & Parallel Mode) +#define CAMERA_O_CC_TEST 0x00000050 // This register shows the status + // of some important variables of + // the camera core module (CCP & + // Parallel Mode) +#define CAMERA_O_CC_GEN_PAR 0x00000054 // This register shows the values + // of the generic parameters of the + // module + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_REVISION register. +// +//****************************************************************************** +#define CAMERA_CC_REVISION_REV_M \ + 0x000000FF // IP revision [7:4] Major revision + // [3:0] Minor revision Examples: + // 0x10 for 1.0 0x21 for 2.1 + +#define CAMERA_CC_REVISION_REV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_SYSCONFIG register. +// +//****************************************************************************** +#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_M \ + 0x00000018 // Slave interface power management + // req/ack control """00"" + // Force-idle. An idle request is + // acknoledged unconditionally" + // """01"" No-idle. An idle request + // is never acknowledged" """10"" + // reserved (Smart-idle not + // implemented)" + +#define CAMERA_CC_SYSCONFIG_S_IDLE_MODE_S 3 +#define CAMERA_CC_SYSCONFIG_SOFT_RESET \ + 0x00000002 // Software reset. Set this bit to + // 1 to trigger a module reset. The + // bit is automatically reset by the + // hardware. During reset it always + // returns 0. 0 Normal mode 1 The + // module is reset + +#define CAMERA_CC_SYSCONFIG_AUTO_IDLE \ + 0x00000001 // Internal OCP clock gating + // strategy 0 OCP clock is + // free-running 1 Automatic OCP + // clock gating strategy is applied + // based on the OCP interface + // activity + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_SYSSTATUS register. +// +//****************************************************************************** +#define CAMERA_CC_SYSSTATUS_RESET_DONE2 \ + 0x00000001 // Internal Reset Monitoring 0 + // Internal module reset is on-going + // 1 Reset completed + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_IRQSTATUS register. +// +//****************************************************************************** +#define CAMERA_CC_IRQSTATUS_FS_IRQ \ + 0x00080000 // Frame Start has occurred 0 Event + // false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_LE_IRQ \ + 0x00040000 // Line End has occurred 0 Event + // false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_LS_IRQ \ + 0x00020000 // Line Start has occurred 0 Event + // false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_FE_IRQ \ + 0x00010000 // Frame End has occurred 0 Event + // false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_FSP_ERR_IRQ \ + 0x00000800 // FSP code error 0 Event false "1 + // Event is true (""pending"")" 0 + // Event status bit unchanged 1 + // Event status bit is reset + +#define CAMERA_CC_IRQSTATUS_FW_ERR_IRQ \ + 0x00000400 // Frame Height Error 0 Event false + // "1 Event is true (""pending"")" 0 + // Event status bit unchanged 1 + // Event status bit is reset + +#define CAMERA_CC_IRQSTATUS_FSC_ERR_IRQ \ + 0x00000200 // False Synchronization Code 0 + // Event false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_SSC_ERR_IRQ \ + 0x00000100 // Shifted Synchronization Code 0 + // Event false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_FIFO_NONEMPTY_IRQ \ + 0x00000010 // FIFO is not empty 0 Event false + // "1 Event is true (""pending"")" 0 + // Event status bit unchanged 1 + // Event status bit is reset + +#define CAMERA_CC_IRQSTATUS_FIFO_FULL_IRQ \ + 0x00000008 // FIFO is full 0 Event false "1 + // Event is true (""pending"")" 0 + // Event status bit unchanged 1 + // Event status bit is reset + +#define CAMERA_CC_IRQSTATUS_FIFO_THR_IRQ \ + 0x00000004 // FIFO threshold has been reached + // 0 Event false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_FIFO_OF_IRQ \ + 0x00000002 // FIFO overflow has occurred 0 + // Event false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +#define CAMERA_CC_IRQSTATUS_FIFO_UF_IRQ \ + 0x00000001 // FIFO underflow has occurred 0 + // Event false "1 Event is true + // (""pending"")" 0 Event status bit + // unchanged 1 Event status bit is + // reset + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_IRQENABLE register. +// +//****************************************************************************** +#define CAMERA_CC_IRQENABLE_FS_IRQ_EN \ + 0x00080000 // Frame Start Interrupt Enable 0 + // Event is masked 1 Event generates + // an interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_LE_IRQ_EN \ + 0x00040000 // Line End Interrupt Enable 0 + // Event is masked 1 Event generates + // an interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_LS_IRQ_EN \ + 0x00020000 // Line Start Interrupt Enable 0 + // Event is masked 1 Event generates + // an interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_FE_IRQ_EN \ + 0x00010000 // Frame End Interrupt Enable 0 + // Event is masked 1 Event generates + // an interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_FSP_IRQ_EN \ + 0x00000800 // FSP code Interrupt Enable 0 + // Event is masked 1 Event generates + // an interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_FW_ERR_IRQ_EN \ + 0x00000400 // Frame Height Error Interrupt + // Enable 0 Event is masked 1 Event + // generates an interrupt when it + // occurs + +#define CAMERA_CC_IRQENABLE_FSC_ERR_IRQ_EN \ + 0x00000200 // False Synchronization Code + // Interrupt Enable 0 Event is + // masked 1 Event generates an + // interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_SSC_ERR_IRQ_EN \ + 0x00000100 // False Synchronization Code + // Interrupt Enable 0 Event is + // masked 1 Event generates an + // interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_FIFO_NONEMPTY_IRQ_EN \ + 0x00000010 // FIFO Threshold Interrupt Enable + // 0 Event is masked 1 Event + // generates an interrupt when it + // occurs + +#define CAMERA_CC_IRQENABLE_FIFO_FULL_IRQ_EN \ + 0x00000008 // FIFO Threshold Interrupt Enable + // 0 Event is masked 1 Event + // generates an interrupt when it + // occurs + +#define CAMERA_CC_IRQENABLE_FIFO_THR_IRQ_EN \ + 0x00000004 // FIFO Threshold Interrupt Enable + // 0 Event is masked 1 Event + // generates an interrupt when it + // occurs + +#define CAMERA_CC_IRQENABLE_FIFO_OF_IRQ_EN \ + 0x00000002 // FIFO Overflow Interrupt Enable 0 + // Event is masked 1 Event generates + // an interrupt when it occurs + +#define CAMERA_CC_IRQENABLE_FIFO_UF_IRQ_EN \ + 0x00000001 // FIFO Underflow Interrupt Enable + // 0 Event is masked 1 Event + // generates an interrupt when it + // occurs + +//****************************************************************************** +// +// The following are defines for the bit fields in the CAMERA_O_CC_CTRL register. +// +//****************************************************************************** +#define CAMERA_CC_CTRL_CC_IF_SYNCHRO \ + 0x00080000 // Synchronize all camera sensor + // inputs This must be set during + // the configuration phase before + // CC_EN set to '1'. This can be + // used in very high frequency to + // avoid dependancy to the IO + // timings. 0 No synchro (most of + // applications) 1 Synchro enabled + // (should never be required) + +#define CAMERA_CC_CTRL_CC_RST 0x00040000 // Resets all the internal finite + // states machines of the camera + // core module - by writing a 1 to + // this bit. must be applied when + // CC_EN = 0 Reads returns 0 +#define CAMERA_CC_CTRL_CC_FRAME_TRIG \ + 0x00020000 // Set the modality in which CC_EN + // works when a disabling of the + // sensor camera core is wanted "If + // CC_FRAME_TRIG = 1 by writing + // ""0"" to CC_EN" the module is + // disabled at the end of the frame + // "If CC_FRAME_TRIG = 0 by writing + // ""0"" to CC_EN" the module is + // disabled immediately + +#define CAMERA_CC_CTRL_CC_EN 0x00010000 // Enables the sensor interface of + // the camera core module "By + // writing ""1"" to this field the + // module is enabled." "By writing + // ""0"" to this field the module is + // disabled at" the end of the frame + // if CC_FRAM_TRIG =1 and is + // disabled immediately if + // CC_FRAM_TRIG = 0 +#define CAMERA_CC_CTRL_NOBT_SYNCHRO \ + 0x00002000 // Enables to start at the + // beginning of the frame or not in + // NoBT 0 Acquisition starts when + // Vertical synchro is high 1 + // Acquisition starts when Vertical + // synchro goes from low to high + // (beginning of the frame) - + // Recommended. + +#define CAMERA_CC_CTRL_BT_CORRECT \ + 0x00001000 // Enables the correction within + // the sync codes in BT mode 0 + // correction is not enabled 1 + // correction is enabled + +#define CAMERA_CC_CTRL_PAR_ORDERCAM \ + 0x00000800 // Enables swap between image-data + // in parallel mode 0 swap is not + // enabled 1 swap is enabled + +#define CAMERA_CC_CTRL_PAR_CLK_POL \ + 0x00000400 // Inverts the clock coming from + // the sensor in parallel mode 0 + // clock not inverted - data sampled + // on rising edge 1 clock inverted - + // data sampled on falling edge + +#define CAMERA_CC_CTRL_NOBT_HS_POL \ + 0x00000200 // Sets the polarity of the + // synchronization signals in NOBT + // parallel mode 0 CAM_P_HS is + // active high 1 CAM_P_HS is active + // low + +#define CAMERA_CC_CTRL_NOBT_VS_POL \ + 0x00000100 // Sets the polarity of the + // synchronization signals in NOBT + // parallel mode 0 CAM_P_VS is + // active high 1 CAM_P_VS is active + // low + +#define CAMERA_CC_CTRL_PAR_MODE_M \ + 0x0000000E // Sets the Protocol Mode of the + // Camera Core module in parallel + // mode (when CCP_MODE = 0) """000"" + // Parallel NOBT 8-bit" """001"" + // Parallel NOBT 10-bit" """010"" + // Parallel NOBT 12-bit" """011"" + // reserved" """100"" Parallet BT + // 8-bit" """101"" Parallel BT + // 10-bit" """110"" reserved" + // """111"" FIFO test mode. Refer to + // Table 12 - FIFO Write and Read + // access" + +#define CAMERA_CC_CTRL_PAR_MODE_S 1 +#define CAMERA_CC_CTRL_CCP_MODE 0x00000001 // Set the Camera Core in CCP mode + // 0 CCP mode disabled 1 CCP mode + // enabled +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_CTRL_DMA register. +// +//****************************************************************************** +#define CAMERA_CC_CTRL_DMA_DMA_EN \ + 0x00000100 // Sets the number of dma request + // lines 0 DMA interface disabled + // The DMA request line stays + // inactive 1 DMA interface enabled + // The DMA request line is + // operational + +#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_M \ + 0x0000007F // Sets the threshold of the FIFO + // the assertion of the dmarequest + // line takes place when the + // threshold is reached. + // """0000000"" threshold set to 1" + // """0000001"" threshold set to 2" + // … """1111111"" threshold set to + // 128" + +#define CAMERA_CC_CTRL_DMA_FIFO_THRESHOLD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_CTRL_XCLK register. +// +//****************************************************************************** +#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_M \ + 0x0000001F // Sets the clock divisor value for + // CAM_XCLK generation. based on + // CAM_MCK (value of CAM_MCLK is + // 96MHz) """00000"" CAM_XCLK Stable + // Low Level" Divider not enabled + // """00001"" CAM_XCLK Stable High + // Level" Divider not enabled from 2 + // to 30 CAM_XCLK = CAM_MCLK / + // XCLK_DIV """11111"" Bypass - + // CAM_XCLK = CAM_MCLK" + +#define CAMERA_CC_CTRL_XCLK_XCLK_DIV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_FIFO_DATA register. +// +//****************************************************************************** +#define CAMERA_CC_FIFO_DATA_FIFO_DATA_M \ + 0xFFFFFFFF // Writes the 32-bit word into the + // FIFO Reads the 32-bit word from + // the FIFO + +#define CAMERA_CC_FIFO_DATA_FIFO_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the CAMERA_O_CC_TEST register. +// +//****************************************************************************** +#define CAMERA_CC_TEST_FIFO_RD_POINTER_M \ + 0xFF000000 // FIFO READ Pointer This field + // shows the value of the FIFO read + // pointer Expected value ranges + // from 0 to 127 + +#define CAMERA_CC_TEST_FIFO_RD_POINTER_S 24 +#define CAMERA_CC_TEST_FIFO_WR_POINTER_M \ + 0x00FF0000 // FIFO WRITE pointer This field + // shows the value of the FIFO write + // pointer Expected value ranges + // from 0 to 127 + +#define CAMERA_CC_TEST_FIFO_WR_POINTER_S 16 +#define CAMERA_CC_TEST_FIFO_LEVEL_M \ + 0x0000FF00 // FIFO level (how many 32-bit + // words the FIFO contains) This + // field shows the value of the FIFO + // level and can assume values from + // 0 to 128 + +#define CAMERA_CC_TEST_FIFO_LEVEL_S 8 +#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_M \ + 0x000000FF // FIFO level peak This field shows + // the max value of the FIFO level + // and can assume values from 0 to + // 128 + +#define CAMERA_CC_TEST_FIFO_LEVEL_PEAK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// CAMERA_O_CC_GEN_PAR register. +// +//****************************************************************************** +#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_M \ + 0x00000007 // Camera Core FIFO DEPTH generic + // parameter + +#define CAMERA_CC_GEN_PAR_CC_FIFO_DEPTH_S 0 + + + +#endif // __HW_CAMERA_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_common_reg.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_common_reg.h new file mode 100644 index 00000000..417544ad --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_common_reg.h @@ -0,0 +1,1117 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_COMMON_REG_H__ +#define __HW_COMMON_REG_H__ + +//***************************************************************************** +// +// The following are defines for the COMMON_REG register offsets. +// +//***************************************************************************** +#define COMMON_REG_O_I2C_Properties_Register \ + 0x00000000 + +#define COMMON_REG_O_SPI_Properties_Register \ + 0x00000004 + +#define COMMON_REG_O_APPS_sh_resource_Interrupt_enable \ + 0x0000000C + +#define COMMON_REG_O_APPS_sh_resource_Interrupt_status \ + 0x00000010 + +#define COMMON_REG_O_NWP_sh_resource_Interrupt_enable \ + 0x00000014 + +#define COMMON_REG_O_NWP_sh_resource_Interrupt_status \ + 0x00000018 + +#define COMMON_REG_O_Flash_ctrl_reg \ + 0x0000001C + +#define COMMON_REG_O_Bus_matrix_M0_segment_access_config \ + 0x00000024 + +#define COMMON_REG_O_Bus_matrix_M1_segment_access_config \ + 0x00000028 + +#define COMMON_REG_O_Bus_matrix_M2_segment_access_config \ + 0x0000002C + +#define COMMON_REG_O_Bus_matrix_M3_segment_access_config \ + 0x00000030 + +#define COMMON_REG_O_Bus_matrix_M4_segment_access_config \ + 0x00000034 + +#define COMMON_REG_O_Bus_matrix_M5_segment_access_config \ + 0x00000038 + +#define COMMON_REG_O_GPIO_properties_register \ + 0x0000003C + +#define COMMON_REG_O_APPS_NW_SEMAPHORE1 \ + 0x00000040 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE2 \ + 0x00000044 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE3 \ + 0x00000048 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE4 \ + 0x0000004C + +#define COMMON_REG_O_APPS_NW_SEMAPHORE5 \ + 0x00000050 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE6 \ + 0x00000054 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE7 \ + 0x00000058 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE8 \ + 0x0000005C + +#define COMMON_REG_O_APPS_NW_SEMAPHORE9 \ + 0x00000060 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE10 \ + 0x00000064 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE11 \ + 0x00000068 + +#define COMMON_REG_O_APPS_NW_SEMAPHORE12 \ + 0x0000006C + +#define COMMON_REG_O_APPS_SEMAPPHORE_PEND \ + 0x00000070 + +#define COMMON_REG_O_NW_SEMAPPHORE_PEND \ + 0x00000074 + +#define COMMON_REG_O_SEMAPHORE_STATUS \ + 0x00000078 + +#define COMMON_REG_O_IDMEM_TIM_Update \ + 0x0000007C + +#define COMMON_REG_O_FPGA_ROM_WR_EN \ + 0x00000080 + +#define COMMON_REG_O_NW_INT_MASK \ + 0x00000084 + +#define COMMON_REG_O_NW_INT_MASK_SET \ + 0x00000088 + +#define COMMON_REG_O_NW_INT_MASK_CLR \ + 0x0000008C + +#define COMMON_REG_O_NW_INT_STS_CLR \ + 0x00000090 + +#define COMMON_REG_O_NW_INT_ACK 0x00000094 +#define COMMON_REG_O_NW_INT_TRIG \ + 0x00000098 + +#define COMMON_REG_O_NW_INT_STS_MASKED \ + 0x0000009C + +#define COMMON_REG_O_NW_INT_STS_RAW \ + 0x000000A0 + +#define COMMON_REG_O_APPS_INT_MASK \ + 0x000000A4 + +#define COMMON_REG_O_APPS_INT_MASK_SET \ + 0x000000A8 + +#define COMMON_REG_O_APPS_INT_MASK_CLR \ + 0x000000AC + +#define COMMON_REG_O_APPS_INT_STS_CLR \ + 0x000000B0 + +#define COMMON_REG_O_APPS_INT_ACK \ + 0x000000B4 + +#define COMMON_REG_O_APPS_INT_TRIG \ + 0x000000B8 + +#define COMMON_REG_O_APPS_INT_STS_MASKED \ + 0x000000BC + +#define COMMON_REG_O_APPS_INT_STS_RAW \ + 0x000000C0 + +#define COMMON_REG_O_IDMEM_TIM_Updated \ + 0x000000C4 + +#define COMMON_REG_O_APPS_GPIO_TRIG_EN \ + 0x000000C8 + +#define COMMON_REG_O_EMU_DEBUG_REG \ + 0x000000CC + +#define COMMON_REG_O_SEMAPHORE_STATUS2 \ + 0x000000D0 + +#define COMMON_REG_O_SEMAPHORE_PREV_OWNER1 \ + 0x000000D4 + +#define COMMON_REG_O_SEMAPHORE_PREV_OWNER2 \ + 0x000000D8 + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_I2C_Properties_Register register. +// +//****************************************************************************** +#define COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_M \ + 0x00000003 // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_SPI_Properties_Register register. +// +//****************************************************************************** +#define COMMON_REG_SPI_Properties_Register_SPI_Properties_Register_M \ + 0x00000003 // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_SPI_Properties_Register_SPI_Properties_Register_S 0 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_sh_resource_Interrupt_enable register. +// +//****************************************************************************** +#define COMMON_REG_APPS_sh_resource_Interrupt_enable_APPS_sh_resource_Interrupt_enable_M \ + 0x0000000F // Interrupt enable APPS bit 0 -> + // when '1' enable I2C interrupt bit + // 1 -> when '1' enable SPI + // interrupt bit 3 -> + // when '1' enable GPIO interrupt + +#define COMMON_REG_APPS_sh_resource_Interrupt_enable_APPS_sh_resource_Interrupt_enable_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_sh_resource_Interrupt_status register. +// +//****************************************************************************** +#define COMMON_REG_APPS_sh_resource_Interrupt_status_APPS_sh_resource_Interrupt_status_M \ + 0x0000000F // Interrupt enable APPS bit 0 -> + // when '1' enable I2C interrupt bit + // 1 -> when '1' enable SPI + // interrupt bit 3 -> + // when '1' enable GPIO interrupt + +#define COMMON_REG_APPS_sh_resource_Interrupt_status_APPS_sh_resource_Interrupt_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NWP_sh_resource_Interrupt_enable register. +// +//****************************************************************************** +#define COMMON_REG_NWP_sh_resource_Interrupt_enable_NWP_sh_resource_Interrupt_enable_M \ + 0x0000000F // Interrupt enable NWP bit 0 -> + // when '1' enable I2C interrupt bit + // 1 -> when '1' enable SPI + // interrupt bit 3 -> + // when '1' enable GPIO interrupt + +#define COMMON_REG_NWP_sh_resource_Interrupt_enable_NWP_sh_resource_Interrupt_enable_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NWP_sh_resource_Interrupt_status register. +// +//****************************************************************************** +#define COMMON_REG_NWP_sh_resource_Interrupt_status_NWP_sh_resource_Interrupt_status_M \ + 0x0000000F // Interrupt enable NWP bit 0 -> + // when '1' enable I2C interrupt bit + // 1 -> when '1' enable SPI + // interrupt bit 3 -> + // when '1' enable GPIO interrupt + +#define COMMON_REG_NWP_sh_resource_Interrupt_status_NWP_sh_resource_Interrupt_status_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Flash_ctrl_reg register. +// +//****************************************************************************** +#define COMMON_REG_Flash_ctrl_reg_Flash_ctrl_reg_M \ + 0x00000003 // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_Flash_ctrl_reg_Flash_ctrl_reg_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Bus_matrix_M0_segment_access_config register. +// +//****************************************************************************** +#define COMMON_REG_Bus_matrix_M0_segment_access_config_Bus_matrix_M0_segment_access_config_M \ + 0x0003FFFF // Master 0 control word matrix to + // each segment. Tieoff. Bit value 1 + // indicates segment is accesable. + +#define COMMON_REG_Bus_matrix_M0_segment_access_config_Bus_matrix_M0_segment_access_config_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Bus_matrix_M1_segment_access_config register. +// +//****************************************************************************** +#define COMMON_REG_Bus_matrix_M1_segment_access_config_Bus_matrix_M1_segment_access_config_M \ + 0x0003FFFF // Master 1 control word matrix to + // each segment. Tieoff. Bit value 1 + // indicates segment is accesable. + +#define COMMON_REG_Bus_matrix_M1_segment_access_config_Bus_matrix_M1_segment_access_config_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Bus_matrix_M2_segment_access_config register. +// +//****************************************************************************** +#define COMMON_REG_Bus_matrix_M2_segment_access_config_Bus_matrix_M2_segment_access_config_M \ + 0x0003FFFF // Master 2 control word matrix to + // each segment. Tieoff. Bit value 1 + // indicates segment is accesable. + +#define COMMON_REG_Bus_matrix_M2_segment_access_config_Bus_matrix_M2_segment_access_config_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Bus_matrix_M3_segment_access_config register. +// +//****************************************************************************** +#define COMMON_REG_Bus_matrix_M3_segment_access_config_Bus_matrix_M3_segment_access_config_M \ + 0x0003FFFF // Master 3 control word matrix to + // each segment. Tieoff. Bit value 1 + // indicates segment is accesable. + +#define COMMON_REG_Bus_matrix_M3_segment_access_config_Bus_matrix_M3_segment_access_config_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Bus_matrix_M4_segment_access_config register. +// +//****************************************************************************** +#define COMMON_REG_Bus_matrix_M4_segment_access_config_Bus_matrix_M4_segment_access_config_M \ + 0x0003FFFF // Master 4 control word matrix to + // each segment. Tieoff. Bit value 1 + // indicates segment is accesable. + +#define COMMON_REG_Bus_matrix_M4_segment_access_config_Bus_matrix_M4_segment_access_config_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_Bus_matrix_M5_segment_access_config register. +// +//****************************************************************************** +#define COMMON_REG_Bus_matrix_M5_segment_access_config_Bus_matrix_M5_segment_access_config_M \ + 0x0003FFFF // Master 5 control word matrix to + // each segment. Tieoff. Bit value 1 + // indicates segment is accesable. + +#define COMMON_REG_Bus_matrix_M5_segment_access_config_Bus_matrix_M5_segment_access_config_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_GPIO_properties_register register. +// +//****************************************************************************** +#define COMMON_REG_GPIO_properties_register_GPIO_properties_register_M \ + 0x000003FF // Shared GPIO configuration + // register. Bit [1:0] to configure + // GPIO0 Bit [3:2] to configure + // GPIO1 Bit [5:4] to configure + // GPIO2 Bit [7:6] to configure + // GPIO3 Bit [9:8] to configure + // GPIO4 each GPIO can be + // individully selected. When “00” + // GPIO is free resource. When “01” + // GPIO is APPS resource. When “10” + // GPIO is NWP resource. Writing 11 + // doesnt have any affect, i.e. If + // one write only relevant gpio + // semaphore and other bits are 1s, + // it'll not disturb the other + // semaphore bits. For example : Say + // If NW wants to take control of + // gpio-1, one should write + // 10'b11_1111_1011 and if one wants + // to release it write + // 10'b11_1111_0011. + +#define COMMON_REG_GPIO_properties_register_GPIO_properties_register_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE1 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE1_APPS_NW_SEMAPHORE1_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE1_APPS_NW_SEMAPHORE1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE2 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE2_APPS_NW_SEMAPHORE2_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE2_APPS_NW_SEMAPHORE2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE3 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE3_APPS_NW_SEMAPHORE3_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE3_APPS_NW_SEMAPHORE3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE4 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE4_APPS_NW_SEMAPHORE4_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE4_APPS_NW_SEMAPHORE4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE5 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE5_APPS_NW_SEMAPHORE5_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE5_APPS_NW_SEMAPHORE5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE6 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE6_APPS_NW_SEMAPHORE6_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE6_APPS_NW_SEMAPHORE6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE7 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE7_APPS_NW_SEMAPHORE7_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE7_APPS_NW_SEMAPHORE7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE8 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE8_APPS_NW_SEMAPHORE8_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE8_APPS_NW_SEMAPHORE8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE9 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE9_APPS_NW_SEMAPHORE9_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE9_APPS_NW_SEMAPHORE9_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE10 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE10_APPS_NW_SEMAPHORE10_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE10_APPS_NW_SEMAPHORE10_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE11 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE11_APPS_NW_SEMAPHORE11_M \ + 0xFFFFFFFF // • Each semaphore register is of + // 2 bit. • When this register is + // set to 2’b01 – Apps have access + // and when set to 2’b10 – NW have + // access. • Ideally both the master + // can modify any of this 2 bit, but + // assumption apps will write only + // 2’b01 or 2’b00 to this register + // and nw will write only 2’b10 or + // 2’b00. • Implementation is when + // any of the bit of this register + // is set, only next write + // allowedvis 2’b00 – Again + // assumption is one master will not + // write 2’b00 if other is already + // holding the semaphore. + +#define COMMON_REG_APPS_NW_SEMAPHORE11_APPS_NW_SEMAPHORE11_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_NW_SEMAPHORE12 register. +// +//****************************************************************************** +#define COMMON_REG_APPS_NW_SEMAPHORE12_APPS_NW_SEMAPHORE12_M \ + 0xFFFFFFFF // APPS NW semaphore register - not + // reflected in status. + +#define COMMON_REG_APPS_NW_SEMAPHORE12_APPS_NW_SEMAPHORE12_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_SEMAPPHORE_PEND register. +// +//****************************************************************************** +#define COMMON_REG_APPS_SEMAPPHORE_PEND_APPS_SEMAPPHORE_PEND_M \ + 0xFFFFFFFF // APPS SEMAPOHORE STATUS + +#define COMMON_REG_APPS_SEMAPPHORE_PEND_APPS_SEMAPPHORE_PEND_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_SEMAPPHORE_PEND register. +// +//****************************************************************************** +#define COMMON_REG_NW_SEMAPPHORE_PEND_NW_SEMAPPHORE_PEND_M \ + 0xFFFFFFFF // NW SEMAPHORE STATUS + +#define COMMON_REG_NW_SEMAPPHORE_PEND_NW_SEMAPPHORE_PEND_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_SEMAPHORE_STATUS register. +// +//****************************************************************************** +#define COMMON_REG_SEMAPHORE_STATUS_SEMAPHORE_STATUS_M \ + 0xFFFFFFFF // SEMAPHORE STATUS 9:8 :semaphore + // status of flash_control 7:6 + // :semaphore status of + // gpio_properties 5:4 + // :semaphore status of + // spi_propertie 1:0 :semaphore + // status of i2c_propertie + +#define COMMON_REG_SEMAPHORE_STATUS_SEMAPHORE_STATUS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_IDMEM_TIM_Update register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_FPGA_ROM_WR_EN register. +// +//****************************************************************************** +#define COMMON_REG_FPGA_ROM_WR_EN_FPGA_ROM_WR_EN \ + 0x00000001 // when '1' enables Write into + // IDMEM CORE ROM, APPS ROM, NWP ROM + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_MASK register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_MASK_NW_INT_MASK_M \ + 0xFFFFFFFF // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define COMMON_REG_NW_INT_MASK_NW_INT_MASK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_MASK_SET register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_MASK_SET_NW_INT_MASK_SET_M \ + 0xFFFFFFFF // write 1 to set corresponding bit + // in NW_INT_MASK;0 = no effect + +#define COMMON_REG_NW_INT_MASK_SET_NW_INT_MASK_SET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_MASK_CLR register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_MASK_CLR_NW_INT_MASK_CLR_M \ + 0xFFFFFFFF // write 1 to clear corresponding + // bit in NW_INT_MASK;0 = no effect + +#define COMMON_REG_NW_INT_MASK_CLR_NW_INT_MASK_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_STS_CLR register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_STS_CLR_NW_INT_STS_CLR_M \ + 0xFFFFFFFF // write 1 to clear corresponding + // interrupt; 0 = no effect; + // interrupt is not lost if coincide + // with write operation + +#define COMMON_REG_NW_INT_STS_CLR_NW_INT_STS_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_ACK register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_ACK_NW_INT_ACK_M \ + 0xFFFFFFFF // write 1 to clear corresponding + // interrupt;0 = no effect + +#define COMMON_REG_NW_INT_ACK_NW_INT_ACK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_TRIG register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_TRIG_NW_INT_TRIG_M \ + 0xFFFFFFFF // Writing a 1 to a bit in this + // register causes the the Host CPU + // if enabled (not masked). This + // register is self-clearing. + // Writing 0 has no effect + +#define COMMON_REG_NW_INT_TRIG_NW_INT_TRIG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_STS_MASKED register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_STS_MASKED_NW_INT_STS_MASKED_M \ + 0xFFFFFFFF // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by NW_INT mask + +#define COMMON_REG_NW_INT_STS_MASKED_NW_INT_STS_MASKED_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_NW_INT_STS_RAW register. +// +//****************************************************************************** +#define COMMON_REG_NW_INT_STS_RAW_NW_INT_STS_RAW_M \ + 0xFFFFFFFF // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define COMMON_REG_NW_INT_STS_RAW_NW_INT_STS_RAW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_MASK register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_MASK_APPS_INT_MASK_M \ + 0xFFFFFFFF // 1= disable corresponding + // interrupt;0 = interrupt enabled + +#define COMMON_REG_APPS_INT_MASK_APPS_INT_MASK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_MASK_SET register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_MASK_SET_APPS_INT_MASK_SET_M \ + 0xFFFFFFFF // write 1 to set corresponding bit + // in APPS_INT_MASK;0 = no effect + +#define COMMON_REG_APPS_INT_MASK_SET_APPS_INT_MASK_SET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_MASK_CLR register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_MASK_CLR_APPS_INT_MASK_CLR_M \ + 0xFFFFFFFF // write 1 to clear corresponding + // bit in APPS_INT_MASK;0 = no + // effect + +#define COMMON_REG_APPS_INT_MASK_CLR_APPS_INT_MASK_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_STS_CLR register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_STS_CLR_APPS_INT_STS_CLR_M \ + 0xFFFFFFFF // write 1 to clear corresponding + // interrupt; 0 = no effect; + // interrupt is not lost if coincide + // with write operation + +#define COMMON_REG_APPS_INT_STS_CLR_APPS_INT_STS_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_ACK register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_ACK_APPS_INT_ACK_M \ + 0xFFFFFFFF // write 1 to clear corresponding + // interrupt;0 = no effect + +#define COMMON_REG_APPS_INT_ACK_APPS_INT_ACK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_TRIG register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_TRIG_APPS_INT_TRIG_M \ + 0xFFFFFFFF // Writing a 1 to a bit in this + // register causes the the Host CPU + // if enabled (not masked). This + // register is self-clearing. + // Writing 0 has no effect + +#define COMMON_REG_APPS_INT_TRIG_APPS_INT_TRIG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_STS_MASKED register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_STS_MASKED_APPS_INT_STS_MASKED_M \ + 0xFFFFFFFF // 1= corresponding interrupt is + // active and not masked. read is + // non-destructive;0 = corresponding + // interrupt is inactive or masked + // by APPS_INT mask + +#define COMMON_REG_APPS_INT_STS_MASKED_APPS_INT_STS_MASKED_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_INT_STS_RAW register. +// +//****************************************************************************** +#define COMMON_REG_APPS_INT_STS_RAW_APPS_INT_STS_RAW_M \ + 0xFFFFFFFF // 1= corresponding interrupt is + // active. read is non-destructive;0 + // = corresponding interrupt is + // inactive + +#define COMMON_REG_APPS_INT_STS_RAW_APPS_INT_STS_RAW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_IDMEM_TIM_Updated register. +// +//****************************************************************************** +#define COMMON_REG_IDMEM_TIM_Updated_TIM_UPDATED \ + 0x00000001 // toggle in this signal + // indicatesIDMEM_TIM_UPDATE + // register mentioned above is + // updated. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_APPS_GPIO_TRIG_EN register. +// +//****************************************************************************** +#define COMMON_REG_APPS_GPIO_TRIG_EN_APPS_GPIO_TRIG_EN_M \ + 0x0000001F // APPS GPIO Trigger EN control. + // Bit 0: when '1' enable GPIO 0 + // trigger. This bit enables trigger + // for all GPIO 0 pins (GPIO 0 to + // GPIO7). Bit 1: when '1' enable + // GPIO 1 trigger. This bit enables + // trigger for all GPIO 1 pins ( + // GPIO8 to GPIO15). Bit 2: when '1' + // enable GPIO 2 trigger. This bit + // enables trigger for all GPIO 2 + // pins (GPIO16 to GPIO23). Bit 3: + // when '1' enable GPIO 3 trigger. + // This bit enables trigger for all + // GPIO 3 pins (GPIO24 to GPIO31). + // Bit 4: when '1' enable GPIO 4 + // trigger. This bit enables trigger + // for all GPIO 4 pins.(GPIO32 to + // GPIO39) + +#define COMMON_REG_APPS_GPIO_TRIG_EN_APPS_GPIO_TRIG_EN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_EMU_DEBUG_REG register. +// +//****************************************************************************** +#define COMMON_REG_EMU_DEBUG_REG_EMU_DEBUG_REG_M \ + 0xFFFFFFFF // 0 th bit used for stalling APPS + // DMA and 1st bit is used for + // stalling NWP DMA for debug + // purpose. Other bits are unused. + +#define COMMON_REG_EMU_DEBUG_REG_EMU_DEBUG_REG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_SEMAPHORE_STATUS2 register. +// +//****************************************************************************** +#define COMMON_REG_SEMAPHORE_STATUS2_SEMPAPHORE_STATUS2_M \ + 0x00FFFFFF // SEMAPHORE STATUS 23:22 + // :semaphore status of + // apps_nw_semaphore11 21:20 + // :semaphore status of + // apps_nw_semaphore11 19:18 + // :semaphore status of + // apps_nw_semaphore10 17:16 + // :semaphore status of + // apps_nw_semaphore9 15:14 + // :semaphore status of + // apps_nw_semaphore8 13:12 + // :semaphore status of + // apps_nw_semaphore7 11:10 + // :semaphore status of + // apps_nw_semaphore6 9:8 :semaphore + // status of apps_nw_semaphore5 7:6 + // :semaphore status of + // apps_nw_semaphore4 5:4 :semaphore + // status of apps_nw_semaphore3 3:2 + // :semaphore status of + // apps_nw_semaphore2 1:0 :semaphore + // status of apps_nw_semaphore1 + +#define COMMON_REG_SEMAPHORE_STATUS2_SEMPAPHORE_STATUS2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_SEMAPHORE_PREV_OWNER1 register. +// +//****************************************************************************** +#define COMMON_REG_SEMAPHORE_PREV_OWNER1_SEMAPHORE_PREV_OWNER1_M \ + 0x0003FFFF // 1:0 : prvious owner of + // i2c_properties_reg[1:0] 3:2 : + // prvious owner of + // spi_properties_reg[1:0] 5:4 : + // prvious owner of + // gpio_properties_reg[1:0] 9:8 : + // prvious owner of + // gpio_properties_reg[3:2] 11:10 : + // prvious owner of + // gpio_properties_reg[5:4] 13:12 : + // prvious owner of + // gpio_properties_reg[7:6] 15:14 : + // prvious owner of + // gpio_properties_reg[9:8] 17:16 : + // prvious owner of + // flash_control_reg[1:0] + +#define COMMON_REG_SEMAPHORE_PREV_OWNER1_SEMAPHORE_PREV_OWNER1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// COMMON_REG_O_SEMAPHORE_PREV_OWNER2 register. +// +//****************************************************************************** +#define COMMON_REG_SEMAPHORE_PREV_OWNER2_SEMAPHORE_PREV_OWNER2_M \ + 0x00FFFFFF // 1:0 : previous owner of + // apps_nw_semaphore1_reg[1:0] 3:2 : + // previous owner of + // apps_nw_semaphore2_reg[1:0] 5:4 : + // previous owner of + // apps_nw_semaphore3_reg[1:0] 7:6 : + // previous owner of + // apps_nw_semaphore4_reg[1:0] 9:8 : + // previous owner of + // apps_nw_semaphore5_reg[1:0] 11:10 + // : previous owner of + // apps_nw_semaphore6_reg[1:0] 13:12 + // : previous owner of + // apps_nw_semaphore7_reg[1:0] 15:14 + // : previous owner of + // apps_nw_semaphore8_reg[1:0] 17:16 + // : previous owner of + // apps_nw_semaphore9_reg[1:0] 19:18 + // : previous owner of + // apps_nw_semaphore10_reg[1:0] + // 21:20 : previous owner of + // apps_nw_semaphore11_reg[1:0] + // 23:22 : previous owner of + // apps_nw_semaphore12_reg[1:0] + +#define COMMON_REG_SEMAPHORE_PREV_OWNER2_SEMAPHORE_PREV_OWNER2_S 0 + + + +#endif // __HW_COMMON_REG_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_des.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_des.h new file mode 100644 index 00000000..c3aed656 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_des.h @@ -0,0 +1,339 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_DES_H__ +#define __HW_DES_H__ + +//***************************************************************************** +// +// The following are defines for the DES_P register offsets. +// +//***************************************************************************** +#define DES_O_KEY3_L 0x00000000 // KEY3 (LSW) for 192-bit key +#define DES_O_KEY3_H 0x00000004 // KEY3 (MSW) for 192-bit key +#define DES_O_KEY2_L 0x00000008 // KEY2 (LSW) for 192-bit key +#define DES_O_KEY2_H 0x0000000C // KEY2 (MSW) for 192-bit key +#define DES_O_KEY1_L 0x00000010 // KEY1 (LSW) for 128-bit + // key/192-bit key +#define DES_O_KEY1_H 0x00000014 // KEY1 (LSW) for 128-bit + // key/192-bit key +#define DES_O_IV_L 0x00000018 // Initialization vector LSW +#define DES_O_IV_H 0x0000001C // Initialization vector MSW +#define DES_O_CTRL 0x00000020 +#define DES_O_LENGTH 0x00000024 // Indicates the cryptographic data + // length in bytes for all modes. + // Once processing is started with + // this context this length + // decrements to zero. Data lengths + // up to (2^32 – 1) bytes are + // allowed. A write to this register + // triggers the engine to start + // using this context. For a Host + // read operation these registers + // return all-zeroes. +#define DES_O_DATA_L 0x00000028 // Data register(LSW) to read/write + // encrypted/decrypted data. +#define DES_O_DATA_H 0x0000002C // Data register(MSW) to read/write + // encrypted/decrypted data. +#define DES_O_REVISION 0x00000030 +#define DES_O_SYSCONFIG 0x00000034 +#define DES_O_SYSSTATUS 0x00000038 +#define DES_O_IRQSTATUS 0x0000003C // This register indicates the + // interrupt status. If one of the + // interrupt bits is set the + // interrupt output will be asserted +#define DES_O_IRQENABLE 0x00000040 // This register contains an enable + // bit for each unique interrupt + // generated by the module. It + // matches the layout of + // DES_IRQSTATUS register. An + // interrupt is enabled when the bit + // in this register is set to 1 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY3_L register. +// +//****************************************************************************** +#define DES_KEY3_L_KEY3_L_M 0xFFFFFFFF // data for key3 +#define DES_KEY3_L_KEY3_L_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY3_H register. +// +//****************************************************************************** +#define DES_KEY3_H_KEY3_H_M 0xFFFFFFFF // data for key3 +#define DES_KEY3_H_KEY3_H_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY2_L register. +// +//****************************************************************************** +#define DES_KEY2_L_KEY2_L_M 0xFFFFFFFF // data for key2 +#define DES_KEY2_L_KEY2_L_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY2_H register. +// +//****************************************************************************** +#define DES_KEY2_H_KEY2_H_M 0xFFFFFFFF // data for key2 +#define DES_KEY2_H_KEY2_H_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY1_L register. +// +//****************************************************************************** +#define DES_KEY1_L_KEY1_L_M 0xFFFFFFFF // data for key1 +#define DES_KEY1_L_KEY1_L_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_KEY1_H register. +// +//****************************************************************************** +#define DES_KEY1_H_KEY1_H_M 0xFFFFFFFF // data for key1 +#define DES_KEY1_H_KEY1_H_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_IV_L register. +// +//****************************************************************************** +#define DES_IV_L_IV_L_M 0xFFFFFFFF // initialization vector for CBC + // CFB modes +#define DES_IV_L_IV_L_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_IV_H register. +// +//****************************************************************************** +#define DES_IV_H_IV_H_M 0xFFFFFFFF // initialization vector for CBC + // CFB modes +#define DES_IV_H_IV_H_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_CTRL register. +// +//****************************************************************************** +#define DES_CTRL_CONTEXT 0x80000000 // If ‘1’ this read-only status bit + // indicates that the context data + // registers can be overwritten and + // the host is permitted to write + // the next context. +#define DES_CTRL_MODE_M 0x00000030 // Select CBC ECB or CFB mode 0x0 + // ecb mode 0x1 cbc mode 0x2 cfb + // mode 0x3 reserved +#define DES_CTRL_MODE_S 4 +#define DES_CTRL_TDES 0x00000008 // Select DES or triple DES + // encryption/decryption. 0 des mode + // 1 tdes mode +#define DES_CTRL_DIRECTION 0x00000004 // select encryption/decryption 0 + // decryption is selected 1 + // Encryption is selected +#define DES_CTRL_INPUT_READY 0x00000002 // When '1' ready to + // encrypt/decrypt data +#define DES_CTRL_OUTPUT_READY 0x00000001 // When '1' Data + // decrypted/encrypted ready +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_LENGTH register. +// +//****************************************************************************** +#define DES_LENGTH_LENGTH_M 0xFFFFFFFF +#define DES_LENGTH_LENGTH_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_DATA_L register. +// +//****************************************************************************** +#define DES_DATA_L_DATA_L_M 0xFFFFFFFF // data for encryption/decryption +#define DES_DATA_L_DATA_L_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_DATA_H register. +// +//****************************************************************************** +#define DES_DATA_H_DATA_H_M 0xFFFFFFFF // data for encryption/decryption +#define DES_DATA_H_DATA_H_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_REVISION register. +// +//****************************************************************************** +#define DES_REVISION_SCHEME_M 0xC0000000 +#define DES_REVISION_SCHEME_S 30 +#define DES_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software + // compatible module family. If + // there is no level of software + // compatibility a new Func number + // (and hence REVISION) should be + // assigned. +#define DES_REVISION_FUNC_S 16 +#define DES_REVISION_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP + // design owner. RTL follows a + // numbering such as X.Y.R.Z which + // are explained in this table. R + // changes ONLY when: (1) PDS + // uploads occur which may have been + // due to spec changes (2) Bug fixes + // occur (3) Resets to '0' when X or + // Y changes. Design team has an + // internal 'Z' (customer invisible) + // number which increments on every + // drop that happens due to DV and + // RTL updates. Z resets to 0 when R + // increments. +#define DES_REVISION_R_RTL_S 11 +#define DES_REVISION_X_MAJOR_M \ + 0x00000700 // Major Revision (X) maintained by + // IP specification owner. X changes + // ONLY when: (1) There is a major + // feature addition. An example + // would be adding Master Mode to + // Utopia Level2. The Func field (or + // Class/Type in old PID format) + // will remain the same. X does NOT + // change due to: (1) Bug fixes (2) + // Change in feature parameters. + +#define DES_REVISION_X_MAJOR_S 8 +#define DES_REVISION_CUSTOM_M 0x000000C0 +#define DES_REVISION_CUSTOM_S 6 +#define DES_REVISION_Y_MINOR_M \ + 0x0000003F // Minor Revision (Y) maintained by + // IP specification owner. Y changes + // ONLY when: (1) Features are + // scaled (up or down). Flexibility + // exists in that this feature + // scalability may either be + // represented in the Y change or a + // specific register in the IP that + // indicates which features are + // exactly available. (2) When + // feature creeps from Is-Not list + // to Is list. But this may not be + // the case once it sees silicon; in + // which case X will change. Y does + // NOT change due to: (1) Bug fixes + // (2) Typos or clarifications (3) + // major functional/feature + // change/addition/deletion. Instead + // these changes may be reflected + // via R S X as applicable. Spec + // owner maintains a + // customer-invisible number 'S' + // which changes due to: (1) + // Typos/clarifications (2) Bug + // documentation. Note that this bug + // is not due to a spec change but + // due to implementation. + // Nevertheless the spec tracks the + // IP bugs. An RTL release (say for + // silicon PG1.1) that occurs due to + // bug fix should document the + // corresponding spec number (X.Y.S) + // in its release notes. + +#define DES_REVISION_Y_MINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_SYSCONFIG register. +// +//****************************************************************************** +#define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \ + 0x00000080 // If set to ‘1’ the DMA context + // request is enabled. 0 Dma + // disabled 1 Dma enabled + +#define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \ + 0x00000040 // If set to ‘1’ the DMA output + // request is enabled. 0 Dma + // disabled 1 Dma enabled + +#define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN \ + 0x00000020 // If set to ‘1’ the DMA input + // request is enabled. 0 Dma + // disabled 1 Dma enabled + +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_SYSSTATUS register. +// +//****************************************************************************** +#define DES_SYSSTATUS_RESETDONE \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_IRQSTATUS register. +// +//****************************************************************************** +#define DES_IRQSTATUS_DATA_OUT \ + 0x00000004 // This bit indicates data output + // interrupt is active and triggers + // the interrupt output. + +#define DES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input + // interrupt is active and triggers + // the interrupt output. +#define DES_IRQSTATUS_CONTEX_IN \ + 0x00000001 // This bit indicates context + // interrupt is active and triggers + // the interrupt output. + +//****************************************************************************** +// +// The following are defines for the bit fields in the DES_O_IRQENABLE register. +// +//****************************************************************************** +#define DES_IRQENABLE_M_DATA_OUT \ + 0x00000004 // If this bit is set to ‘1’ the + // secure data output interrupt is + // enabled. + +#define DES_IRQENABLE_M_DATA_IN \ + 0x00000002 // If this bit is set to ‘1’ the + // secure data input interrupt is + // enabled. + +#define DES_IRQENABLE_M_CONTEX_IN \ + 0x00000001 // If this bit is set to ‘1’ the + // secure context interrupt is + // enabled. + + + + +#endif // __HW_DES_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_dthe.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_dthe.h new file mode 100644 index 00000000..1d302f42 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_dthe.h @@ -0,0 +1,392 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** +//***************************************************************************** + +#ifndef __HW_DTHE_H__ +#define __HW_DTHE_H__ + +//***************************************************************************** +// +// The following are defines for the DTHE register offsets. +// +//***************************************************************************** +#define DTHE_O_SHA_IM 0x00000810 +#define DTHE_O_SHA_RIS 0x00000814 +#define DTHE_O_SHA_MIS 0x00000818 +#define DTHE_O_SHA_IC 0x0000081C +#define DTHE_O_AES_IM 0x00000820 +#define DTHE_O_AES_RIS 0x00000824 +#define DTHE_O_AES_MIS 0x00000828 +#define DTHE_O_AES_IC 0x0000082C +#define DTHE_O_DES_IM 0x00000830 +#define DTHE_O_DES_RIS 0x00000834 +#define DTHE_O_DES_MIS 0x00000838 +#define DTHE_O_DES_IC 0x0000083C +#define DTHE_O_EIP_CGCFG 0x00000A00 +#define DTHE_O_EIP_CGREQ 0x00000A04 +#define DTHE_O_CRC_CTRL 0x00000C00 +#define DTHE_O_CRC_SEED 0x00000C10 +#define DTHE_O_CRC_DIN 0x00000C14 +#define DTHE_O_CRC_RSLT_PP 0x00000C18 +#define DTHE_O_RAND_KEY0 0x00000F00 +#define DTHE_O_RAND_KEY1 0x00000F04 +#define DTHE_O_RAND_KEY2 0x00000F08 +#define DTHE_O_RAND_KEY3 0x00000F0C + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_SHAMD5_IMST register. +// +//****************************************************************************** +#define DTHE_SHAMD5_IMST_DIN 0x00000004 // Data in: this interrupt is + // raised when DMA writes last word + // of input data to internal FIFO of + // the engine +#define DTHE_SHAMD5_IMST_COUT 0x00000002 // Context out: this interrupt is + // raised when DMA complets the + // output context movement from + // internal register +#define DTHE_SHAMD5_IMST_CIN 0x00000001 // context in: this interrupt is + // raised when DMA complets Context + // write to internal register +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_SHAMD5_IRIS register. +// +//****************************************************************************** +#define DTHE_SHAMD5_IRIS_DIN 0x00000004 // input Data movement is done +#define DTHE_SHAMD5_IRIS_COUT 0x00000002 // Context output is done +#define DTHE_SHAMD5_IRIS_CIN 0x00000001 // context input is done +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_SHAMD5_IMIS register. +// +//****************************************************************************** +#define DTHE_SHAMD5_IMIS_DIN 0x00000004 // input Data movement is done +#define DTHE_SHAMD5_IMIS_COUT 0x00000002 // Context output is done +#define DTHE_SHAMD5_IMIS_CIN 0x00000001 // context input is done +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_SHAMD5_ICIS register. +// +//****************************************************************************** +#define DTHE_SHAMD5_ICIS_DIN 0x00000004 // Clear “input Data movement done” + // flag +#define DTHE_SHAMD5_ICIS_COUT 0x00000002 // Clear “Context output done” flag +#define DTHE_SHAMD5_ICIS_CIN 0x00000001 // Clear “context input done” flag +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_AES_IMST register. +// +//****************************************************************************** +#define DTHE_AES_IMST_DOUT 0x00000008 // Data out: this interrupt is + // raised when DMA finishes writing + // last word of the process result +#define DTHE_AES_IMST_DIN 0x00000004 // Data in: this interrupt is + // raised when DMA writes last word + // of input data to internal FIFO of + // the engine +#define DTHE_AES_IMST_COUT 0x00000002 // Context out: this interrupt is + // raised when DMA complets the + // output context movement from + // internal register +#define DTHE_AES_IMST_CIN 0x00000001 // context in: this interrupt is + // raised when DMA complets Context + // write to internal register +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_AES_IRIS register. +// +//****************************************************************************** +#define DTHE_AES_IRIS_DOUT 0x00000008 // Output Data movement is done +#define DTHE_AES_IRIS_DIN 0x00000004 // input Data movement is done +#define DTHE_AES_IRIS_COUT 0x00000002 // Context output is done +#define DTHE_AES_IRIS_CIN 0x00000001 // context input is done +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_AES_IMIS register. +// +//****************************************************************************** +#define DTHE_AES_IMIS_DOUT 0x00000008 // Output Data movement is done +#define DTHE_AES_IMIS_DIN 0x00000004 // input Data movement is done +#define DTHE_AES_IMIS_COUT 0x00000002 // Context output is done +#define DTHE_AES_IMIS_CIN 0x00000001 // context input is done +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_AES_ICIS register. +// +//****************************************************************************** +#define DTHE_AES_ICIS_DOUT 0x00000008 // Clear “output Data movement + // done” flag +#define DTHE_AES_ICIS_DIN 0x00000004 // Clear “input Data movement done” + // flag +#define DTHE_AES_ICIS_COUT 0x00000002 // Clear “Context output done” flag +#define DTHE_AES_ICIS_CIN 0x00000001 // Clear “context input done” flag +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_DES_IMST register. +// +//****************************************************************************** +#define DTHE_DES_IMST_DOUT 0x00000008 // Data out: this interrupt is + // raised when DMA finishes writing + // last word of the process result +#define DTHE_DES_IMST_DIN 0x00000004 // Data in: this interrupt is + // raised when DMA writes last word + // of input data to internal FIFO of + // the engine +#define DTHE_DES_IMST_CIN 0x00000001 // context in: this interrupt is + // raised when DMA complets Context + // write to internal register +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_DES_IRIS register. +// +//****************************************************************************** +#define DTHE_DES_IRIS_DOUT 0x00000008 // Output Data movement is done +#define DTHE_DES_IRIS_DIN 0x00000004 // input Data movement is done +#define DTHE_DES_IRIS_CIN 0x00000001 // context input is done +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_DES_IMIS register. +// +//****************************************************************************** +#define DTHE_DES_IMIS_DOUT 0x00000008 // Output Data movement is done +#define DTHE_DES_IMIS_DIN 0x00000004 // input Data movement is done +#define DTHE_DES_IMIS_CIN 0x00000001 // context input is done +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_DES_ICIS register. +// +//****************************************************************************** +#define DTHE_DES_ICIS_DOUT 0x00000008 // Clear “output Data movement + // done” flag +#define DTHE_DES_ICIS_DIN 0x00000004 // Clear “input Data movement done” + // flag +#define DTHE_DES_ICIS_CIN 0x00000001 // Clear "context input done” flag +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_EIP_CGCFG register. +// +//****************************************************************************** +#define DTHE_EIP_CGCFG_EIP29_CFG \ + 0x00000010 // Clock gating protocol setting + // for EIP29T. 0 – Follow direct + // protocol 1 – Follow idle_req/ack + // protocol. + +#define DTHE_EIP_CGCFG_EIP75_CFG \ + 0x00000008 // Clock gating protocol setting + // for EIP75T. 0 – Follow direct + // protocol 1 – Follow idle_req/ack + // protocol. + +#define DTHE_EIP_CGCFG_EIP16_CFG \ + 0x00000004 // Clock gating protocol setting + // for DES. 0 – Follow direct + // protocol 1 – Follow idle_req/ack + // protocol. + +#define DTHE_EIP_CGCFG_EIP36_CFG \ + 0x00000002 // Clock gating protocol setting + // for AES. 0 – Follow direct + // protocol 1 – Follow idle_req/ack + // protocol. + +#define DTHE_EIP_CGCFG_EIP57_CFG \ + 0x00000001 // Clock gating protocol setting + // for SHAMD5. 0 – Follow direct + // protocol 1 – Follow idle_req/ack + // protocol. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_EIP_CGREQ register. +// +//****************************************************************************** +#define DTHE_EIP_CGREQ_Key_M 0xF0000000 // When “0x5” write “1” to lower + // bits [4:0] will set the bit. + // Write “0” will be ignored When + // “0x2” write “1” to lower bit + // [4:0] will clear the bit. Write + // “0” will be ignored for other key + // value, regular read write + // operation +#define DTHE_EIP_CGREQ_Key_S 28 +#define DTHE_EIP_CGREQ_EIP29_REQ \ + 0x00000010 // 0 – request clock gating 1 – + // request to un-gate the clock. + +#define DTHE_EIP_CGREQ_EIP75_REQ \ + 0x00000008 // 0 – request clock gating 1 – + // request to un-gate the clock. + +#define DTHE_EIP_CGREQ_EIP16_REQ \ + 0x00000004 // 0 – request clock gating 1 – + // request to un-gate the clock. + +#define DTHE_EIP_CGREQ_EIP36_REQ \ + 0x00000002 // 0 – request clock gating 1 – + // request to un-gate the clock. + +#define DTHE_EIP_CGREQ_EIP57_REQ \ + 0x00000001 // 0 – request clock gating 1 – + // request to un-gate the clock. + +//****************************************************************************** +// +// The following are defines for the bit fields in the DTHE_O_CRC_CTRL register. +// +//****************************************************************************** +#define DTHE_CRC_CTRL_INIT_M 0x00006000 // Initialize the CRC 00 – use SEED + // register context as starting + // value 10 – all “zero” 11 – all + // “one” This is self clearing. With + // first write to data register this + // value clears to zero and remain + // zero for rest of the operation + // unless written again +#define DTHE_CRC_CTRL_INIT_S 13 +#define DTHE_CRC_CTRL_SIZE 0x00001000 // Input data size 0 – 32 bit 1 – 8 + // bit +#define DTHE_CRC_CTRL_OINV 0x00000200 // Inverse the bits of result + // before storing to CRC_RSLT_PP0 +#define DTHE_CRC_CTRL_OBR 0x00000100 // Bit reverse the output result + // byte before storing to + // CRC_RSLT_PP0. applicable for all + // bytes in word +#define DTHE_CRC_CTRL_IBR 0x00000080 // Bit reverse the input byte. For + // all bytes in word +#define DTHE_CRC_CTRL_ENDIAN_M \ + 0x00000030 // Endian control [0] – swap byte + // in half-word [1] – swap half word + +#define DTHE_CRC_CTRL_ENDIAN_S 4 +#define DTHE_CRC_CTRL_TYPE_M 0x0000000F // Type of operation 0000 – + // polynomial 0x8005 0001 – + // polynomial 0x1021 0010 – + // polynomial 0x4C11DB7 0011 – + // polynomial 0x1EDC6F41 1000 – TCP + // checksum TYPE in DTHE_S_CRC_CTRL + // & DTHE_S_CRC_CTRL should be + // exclusive +#define DTHE_CRC_CTRL_TYPE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DTHE_O_CRC_SEED register. +// +//****************************************************************************** +#define DTHE_CRC_SEED_SEED_M 0xFFFFFFFF // Starting seed of CRC and + // checksum operation. Please see + // CTRL register for more detail. + // This resister also holds the + // latest result of CRC or checksum + // operation +#define DTHE_CRC_SEED_SEED_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the DTHE_O_CRC_DIN register. +// +//****************************************************************************** +#define DTHE_CRC_DIN_DATA_IN_M \ + 0xFFFFFFFF // Input data for CRC or checksum + // operation + +#define DTHE_CRC_DIN_DATA_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_CRC_RSLT_PP register. +// +//****************************************************************************** +#define DTHE_CRC_RSLT_PP_RSLT_PP_M \ + 0xFFFFFFFF // Input data for CRC or checksum + // operation + +#define DTHE_CRC_RSLT_PP_RSLT_PP_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_RAND_KEY0 register. +// +//****************************************************************************** +#define DTHE_RAND_KEY0_KEY_M 0xFFFFFFFF // Device Specific Randon key + // [31:0] +#define DTHE_RAND_KEY0_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_RAND_KEY1 register. +// +//****************************************************************************** +#define DTHE_RAND_KEY1_KEY_M 0xFFFFFFFF // Device Specific Randon key + // [63:32] +#define DTHE_RAND_KEY1_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_RAND_KEY2 register. +// +//****************************************************************************** +#define DTHE_RAND_KEY2_KEY_M 0xFFFFFFFF // Device Specific Randon key + // [95:34] +#define DTHE_RAND_KEY2_KEY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// DTHE_O_RAND_KEY3 register. +// +//****************************************************************************** +#define DTHE_RAND_KEY3_KEY_M 0xFFFFFFFF // Device Specific Randon key + // [127:96] +#define DTHE_RAND_KEY3_KEY_S 0 + + + +#endif // __HW_DTHE_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_flash_ctrl.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_flash_ctrl.h new file mode 100644 index 00000000..b57044aa --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_flash_ctrl.h @@ -0,0 +1,1862 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_FLASH_CTRL_H__ +#define __HW_FLASH_CTRL_H__ + +//***************************************************************************** +// +// The following are defines for the FLASH_CTRL register offsets. +// +//***************************************************************************** +#define FLASH_CTRL_O_FMA 0x00000000 // Flash Memory Address (FMA) + // offset 0x000 During a write + // operation this register contains + // a 4-byte-aligned address and + // specifies where the data is + // written. During erase operations + // this register contains a 1 + // KB-aligned CPU byte address and + // specifies which block is erased. + // Note that the alignment + // requirements must be met by + // software or the results of the + // operation are unpredictable. +#define FLASH_CTRL_O_FMD 0x00000004 // Flash Memory Data (FMD) offset + // 0x004 This register contains the + // data to be written during the + // programming cycle or read during + // the read cycle. Note that the + // contents of this register are + // undefined for a read access of an + // execute-only block. This register + // is not used during erase cycles. +#define FLASH_CTRL_O_FMC 0x00000008 // Flash Memory Control (FMC) + // offset 0x008 When this register + // is written the Flash memory + // controller initiates the + // appropriate access cycle for the + // location specified by the Flash + // Memory Address (FMA) register . + // If the access is a write access + // the data contained in the Flash + // Memory Data (FMD) register is + // written to the specified address. + // This register must be the final + // register written and initiates + // the memory operation. The four + // control bits in the lower byte of + // this register are used to + // initiate memory operations. +#define FLASH_CTRL_O_FCRIS 0x0000000C // Flash Controller Raw Interrupt + // Status (FCRIS) offset 0x00C This + // register indicates that the Flash + // memory controller has an + // interrupt condition. An interrupt + // is sent to the interrupt + // controller only if the + // corresponding FCIM register bit + // is set. +#define FLASH_CTRL_O_FCIM 0x00000010 // Flash Controller Interrupt Mask + // (FCIM) offset 0x010 This register + // controls whether the Flash memory + // controller generates interrupts + // to the controller. +#define FLASH_CTRL_O_FCMISC 0x00000014 // Flash Controller Masked + // Interrupt Status and Clear + // (FCMISC) offset 0x014 This + // register provides two functions. + // First it reports the cause of an + // interrupt by indicating which + // interrupt source or sources are + // signalling the interrupt. Second + // it serves as the method to clear + // the interrupt reporting. +#define FLASH_CTRL_O_FMC2 0x00000020 // Flash Memory Control 2 (FMC2) + // offset 0x020 When this register + // is written the Flash memory + // controller initiates the + // appropriate access cycle for the + // location specified by the Flash + // Memory Address (FMA) register . + // If the access is a write access + // the data contained in the Flash + // Write Buffer (FWB) registers is + // written. This register must be + // the final register written as it + // initiates the memory operation. +#define FLASH_CTRL_O_FWBVAL 0x00000030 // Flash Write Buffer Valid + // (FWBVAL) offset 0x030 This + // register provides a bitwise + // status of which FWBn registers + // have been written by the + // processor since the last write of + // the Flash memory write buffer. + // The entries with a 1 are written + // on the next write of the Flash + // memory write buffer. This + // register is cleared after the + // write operation by hardware. A + // protection violation on the write + // operation also clears this + // status. Software can program the + // same 32 words to various Flash + // memory locations by setting the + // FWB[n] bits after they are + // cleared by the write operation. + // The next write operation then + // uses the same data as the + // previous one. In addition if a + // FWBn register change should not + // be written to Flash memory + // software can clear the + // corresponding FWB[n] bit to + // preserve the existing data when + // the next write operation occurs. +#define FLASH_CTRL_O_FWB1 0x00000100 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB2 0x00000104 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB3 0x00000108 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB4 0x0000010C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB5 0x00000110 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB6 0x00000114 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB7 0x00000118 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB8 0x0000011C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB9 0x00000120 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB10 0x00000124 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB11 0x00000128 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB12 0x0000012C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB13 0x00000130 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB14 0x00000134 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB15 0x00000138 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB16 0x0000013C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB17 0x00000140 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB18 0x00000144 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB19 0x00000148 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB20 0x0000014C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB21 0x00000150 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB22 0x00000154 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB23 0x00000158 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB24 0x0000015C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB25 0x00000160 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB26 0x00000164 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB27 0x00000168 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB28 0x0000016C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB29 0x00000170 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB30 0x00000174 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB31 0x00000178 // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FWB32 0x0000017C // Flash Write Buffer n (FWBn) + // offset 0x100 - 0x17C These 32 + // registers hold the contents of + // the data to be written into the + // Flash memory on a buffered Flash + // memory write operation. The + // offset selects one of the 32-bit + // registers. Only FWBn registers + // that have been updated since the + // preceding buffered Flash memory + // write operation are written into + // the Flash memory so it is not + // necessary to write the entire + // bank of registers in order to + // write 1 or 2 words. The FWBn + // registers are written into the + // Flash memory with the FWB0 + // register corresponding to the + // address contained in FMA. FWB1 is + // written to the address FMA+0x4 + // etc. Note that only data bits + // that are 0 result in the Flash + // memory being modified. A data bit + // that is 1 leaves the content of + // the Flash memory bit at its + // previous value. +#define FLASH_CTRL_O_FSIZE 0x00000FC0 // Flash Size (FSIZE) offset 0xFC0 + // This register indicates the size + // of the on-chip Flash memory. + // Important: This register should + // be used to determine the size of + // the Flash memory that is + // implemented on this + // microcontroller. However to + // support legacy software the DC0 + // register is available. A read of + // the DC0 register correctly + // identifies legacy memory sizes. + // Software must use the FSIZE + // register for memory sizes that + // are not listed in the DC0 + // register description. +#define FLASH_CTRL_O_SSIZE 0x00000FC4 // SRAM Size (SSIZE) offset 0xFC4 + // This register indicates the size + // of the on-chip SRAM. Important: + // This register should be used to + // determine the size of the SRAM + // that is implemented on this + // microcontroller. However to + // support legacy software the DC0 + // register is available. A read of + // the DC0 register correctly + // identifies legacy memory sizes. + // Software must use the SSIZE + // register for memory sizes that + // are not listed in the DC0 + // register description. + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FMA register. +// +//****************************************************************************** +#define FLASH_CTRL_FMA_OFFSET_M 0x0003FFFF // Address Offset Address offset in + // Flash memory where operation is + // performed except for nonvolatile + // registers +#define FLASH_CTRL_FMA_OFFSET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FMD register. +// +//****************************************************************************** +#define FLASH_CTRL_FMD_DATA_M 0xFFFFFFFF // Data Value Data value for write + // operation. +#define FLASH_CTRL_FMD_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FMC register. +// +//****************************************************************************** +#define FLASH_CTRL_FMC_WRKEY_M 0xFFFF0000 // Flash Memory Write Key This + // field contains a write key which + // is used to minimize the incidence + // of accidental Flash memory + // writes. The value 0xA442 must be + // written into this field for a + // Flash memory write to occur. + // Writes to the FMC register + // without this WRKEY value are + // ignored. A read of this field + // returns the value 0. +#define FLASH_CTRL_FMC_WRKEY_S 16 +#define FLASH_CTRL_FMC_COMT 0x00000008 // Commit Register Value This bit + // is used to commit writes to + // Flash-memory-resident registers + // and to monitor the progress of + // that process. Value Description 1 + // Set this bit to commit (write) + // the register value to a + // Flash-memory-resident register. + // When read a 1 indicates that the + // previous commit access is not + // complete. 0 A write of 0 has no + // effect on the state of this bit. + // When read a 0 indicates that the + // previous commit access is + // complete. +#define FLASH_CTRL_FMC_MERASE1 0x00000004 // Mass Erase Flash Memory This bit + // is used to mass erase the Flash + // main memory and to monitor the + // progress of that process. Value + // Description 1 Set this bit to + // erase the Flash main memory. When + // read a 1 indicates that the + // previous mass erase access is not + // complete. 0 A write of 0 has no + // effect on the state of this bit. + // When read a 0 indicates that the + // previous mass erase access is + // complete. +#define FLASH_CTRL_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory + // This bit is used to erase a page + // of Flash memory and to monitor + // the progress of that process. + // Value Description 1 Set this bit + // to erase the Flash memory page + // specified by the contents of the + // FMA register. When read a 1 + // indicates that the previous page + // erase access is not complete. 0 A + // write of 0 has no effect on the + // state of this bit. When read a 0 + // indicates that the previous page + // erase access is complete. +#define FLASH_CTRL_FMC_WRITE 0x00000001 // Write a Word into Flash Memory + // This bit is used to write a word + // into Flash memory and to monitor + // the progress of that process. + // Value Description 1 Set this bit + // to write the data stored in the + // FMD register into the Flash + // memory location specified by the + // contents of the FMA register. + // When read a 1 indicates that the + // write update access is not + // complete. 0 A write of 0 has no + // effect on the state of this bit. + // When read a 0 indicates that the + // previous write update access is + // complete. +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FCRIS register. +// +//****************************************************************************** +#define FLASH_CTRL_FCRIS_PROGRIS \ + 0x00002000 // Program Verify Error Raw + // Interrupt Status Value + // Description 1 An interrupt is + // pending because the verify of a + // PROGRAM operation failed. 0 An + // interrupt has not occurred. This + // bit is cleared by writing a 1 to + // the PROGMISC bit in the FCMISC + // register. + +#define FLASH_CTRL_FCRIS_ERRIS 0x00000800 // Erase Verify Error Raw Interrupt + // Status Value Description 1 An + // interrupt is pending because the + // verify of an ERASE operation + // failed. 0 An interrupt has not + // occurred. This bit is cleared by + // writing a 1 to the ERMISC bit in + // the FCMISC register. +#define FLASH_CTRL_FCRIS_INVDRIS \ + 0x00000400 // Invalid Data Raw Interrupt + // Status Value Description 1 An + // interrupt is pending because a + // bit that was previously + // programmed as a 0 is now being + // requested to be programmed as a + // 1. 0 An interrupt has not + // occurred. This bit is cleared by + // writing a 1 to the INVMISC bit in + // the FCMISC register. + +#define FLASH_CTRL_FCRIS_VOLTRIS \ + 0x00000200 // Pump Voltage Raw Interrupt + // Status Value Description 1 An + // interrupt is pending because the + // regulated voltage of the pump + // went out of spec during the Flash + // operation and the operation was + // terminated. 0 An interrupt has + // not occurred. This bit is cleared + // by writing a 1 to the VOLTMISC + // bit in the FCMISC register. + +#define FLASH_CTRL_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status This + // bit provides status EEPROM + // operation. Value Description 1 An + // EEPROM interrupt has occurred. 0 + // An EEPROM interrupt has not + // occurred. This bit is cleared by + // writing a 1 to the EMISC bit in + // the FCMISC register. +#define FLASH_CTRL_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status + // This bit provides status on + // programming cycles which are + // write or erase actions generated + // through the FMC or FMC2 register + // bits (see page 537 and page 549). + // Value Description 1 The + // programming or erase cycle has + // completed. 0 The programming or + // erase cycle has not completed. + // This status is sent to the + // interrupt controller when the + // PMASK bit in the FCIM register is + // set. This bit is cleared by + // writing a 1 to the PMISC bit in + // the FCMISC register. +#define FLASH_CTRL_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status + // Value Description 1 A program or + // erase action was attempted on a + // block of Flash memory that + // contradicts the protection policy + // for that block as set in the + // FMPPEn registers. 0 No access has + // tried to improperly program or + // erase the Flash memory. This + // status is sent to the interrupt + // controller when the AMASK bit in + // the FCIM register is set. This + // bit is cleared by writing a 1 to + // the AMISC bit in the FCMISC + // register. +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FCIM register. +// +//****************************************************************************** +#define FLASH_CTRL_FCIM_ILLMASK 0x00004000 // Illegal Address Interrupt Mask + // Value Description 1 An interrupt + // is sent to the interrupt + // controller when the ILLARIS bit + // is set. 0 The ILLARIS interrupt + // is suppressed and not sent to the + // interrupt controller. +#define FLASH_CTRL_FCIM_PROGMASK \ + 0x00002000 // PROGVER Interrupt Mask Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the PROGRIS bit is set. 0 + // The PROGRIS interrupt is + // suppressed and not sent to the + // interrupt controller. + +#define FLASH_CTRL_FCIM_PREMASK 0x00001000 // PREVER Interrupt Mask Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the PRERIS bit is set. 0 The + // PRERIS interrupt is suppressed + // and not sent to the interrupt + // controller. +#define FLASH_CTRL_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the ERRIS bit is set. 0 The + // ERRIS interrupt is suppressed and + // not sent to the interrupt + // controller. +#define FLASH_CTRL_FCIM_INVDMASK \ + 0x00000400 // Invalid Data Interrupt Mask + // Value Description 1 An interrupt + // is sent to the interrupt + // controller when the INVDRIS bit + // is set. 0 The INVDRIS interrupt + // is suppressed and not sent to the + // interrupt controller. + +#define FLASH_CTRL_FCIM_VOLTMASK \ + 0x00000200 // VOLT Interrupt Mask Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the VOLTRIS bit is set. 0 + // The VOLTRIS interrupt is + // suppressed and not sent to the + // interrupt controller. + +#define FLASH_CTRL_FCIM_LOCKMASK \ + 0x00000100 // LOCK Interrupt Mask Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the LOCKRIS bit is set. 0 + // The LOCKRIS interrupt is + // suppressed and not sent to the + // interrupt controller. + +#define FLASH_CTRL_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the ERIS bit is set. 0 The + // ERIS interrupt is suppressed and + // not sent to the interrupt + // controller. +#define FLASH_CTRL_FCIM_PMASK 0x00000002 // Programming Interrupt Mask This + // bit controls the reporting of the + // programming raw interrupt status + // to the interrupt controller. + // Value Description 1 An interrupt + // is sent to the interrupt + // controller when the PRIS bit is + // set. 0 The PRIS interrupt is + // suppressed and not sent to the + // interrupt controller. +#define FLASH_CTRL_FCIM_AMASK 0x00000001 // Access Interrupt Mask This bit + // controls the reporting of the + // access raw interrupt status to + // the interrupt controller. Value + // Description 1 An interrupt is + // sent to the interrupt controller + // when the ARIS bit is set. 0 The + // ARIS interrupt is suppressed and + // not sent to the interrupt + // controller. +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FCMISC register. +// +//****************************************************************************** +#define FLASH_CTRL_FCMISC_ILLMISC \ + 0x00004000 // Illegal Address Masked Interrupt + // Status and Clear Value + // Description 1 When read a 1 + // indicates that an unmasked + // interrupt was signaled. Writing a + // 1 to this bit clears ILLAMISC and + // also the ILLARIS bit in the FCRIS + // register (see page 540). 0 When + // read a 0 indicates that an + // interrupt has not occurred. A + // write of 0 has no effect on the + // state of this bit. + +#define FLASH_CTRL_FCMISC_PROGMISC \ + 0x00002000 // PROGVER Masked Interrupt Status + // and Clear Value Description 1 + // When read a 1 indicates that an + // unmasked interrupt was signaled. + // Writing a 1 to this bit clears + // PROGMISC and also the PROGRIS bit + // in the FCRIS register (see page + // 540). 0 When read a 0 indicates + // that an interrupt has not + // occurred. A write of 0 has no + // effect on the state of this bit. + +#define FLASH_CTRL_FCMISC_PREMISC \ + 0x00001000 // PREVER Masked Interrupt Status + // and Clear Value Description 1 + // When read a 1 indicates that an + // unmasked interrupt was signaled. + // Writing a 1 to this bit clears + // PREMISC and also the PRERIS bit + // in the FCRIS register . 0 When + // read a 0 indicates that an + // interrupt has not occurred. A + // write of 0 has no effect on the + // state of this bit. + +#define FLASH_CTRL_FCMISC_ERMISC \ + 0x00000800 // ERVER Masked Interrupt Status + // and Clear Value Description 1 + // When read a 1 indicates that an + // unmasked interrupt was signaled. + // Writing a 1 to this bit clears + // ERMISC and also the ERRIS bit in + // the FCRIS register 0 When read a + // 0 indicates that an interrupt has + // not occurred. A write of 0 has no + // effect on the state of this bit. + +#define FLASH_CTRL_FCMISC_INVDMISC \ + 0x00000400 // Invalid Data Masked Interrupt + // Status and Clear Value + // Description 1 When read a 1 + // indicates that an unmasked + // interrupt was signaled. Writing a + // 1 to this bit clears INVDMISC and + // also the INVDRIS bit in the FCRIS + // register (see page 540). 0 When + // read a 0 indicates that an + // interrupt has not occurred. A + // write of 0 has no effect on the + // state of this bit. + +#define FLASH_CTRL_FCMISC_VOLTMISC \ + 0x00000200 // VOLT Masked Interrupt Status and + // Clear Value Description 1 When + // read a 1 indicates that an + // unmasked interrupt was signaled. + // Writing a 1 to this bit clears + // VOLTMISC and also the VOLTRIS bit + // in the FCRIS register (see page + // 540). 0 When read a 0 indicates + // that an interrupt has not + // occurred. A write of 0 has no + // effect on the state of this bit. + +#define FLASH_CTRL_FCMISC_LOCKMISC \ + 0x00000100 // LOCK Masked Interrupt Status and + // Clear Value Description 1 When + // read a 1 indicates that an + // unmasked interrupt was signaled. + // Writing a 1 to this bit clears + // LOCKMISC and also the LOCKRIS bit + // in the FCRIS register (see page + // 540). 0 When read a 0 indicates + // that an interrupt has not + // occurred. A write of 0 has no + // effect on the state of this bit. + +#define FLASH_CTRL_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status + // and Clear Value Description 1 + // When read a 1 indicates that an + // unmasked interrupt was signaled. + // Writing a 1 to this bit clears + // EMISC and also the ERIS bit in + // the FCRIS register 0 When read a + // 0 indicates that an interrupt has + // not occurred. A write of 0 has no + // effect on the state of this bit. +#define FLASH_CTRL_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt + // Status and Clear Value + // Description 1 When read a 1 + // indicates that an unmasked + // interrupt was signaled because a + // programming cycle completed. + // Writing a 1 to this bit clears + // PMISC and also the PRIS bit in + // the FCRIS register 0 When read a + // 0 indicates that a programming + // cycle complete interrupt has not + // occurred. A write of 0 has no + // effect on the state of this bit. +#define FLASH_CTRL_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status + // and Clear Value Description 1 + // When read a 1 indicates that an + // unmasked interrupt was signaled + // because a program or erase action + // was attempted on a block of Flash + // memory that contradicts the + // protection policy for that block + // as set in the FMPPEn registers. + // Writing a 1 to this bit clears + // AMISC and also the ARIS bit in + // the FCRIS register 0 When read a + // 0 indicates that no improper + // accesses have occurred. A write + // of 0 has no effect on the state + // of this bit. +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FMC2 register. +// +//****************************************************************************** +#define FLASH_CTRL_FMC2_WRKEY_M 0xFFFF0000 // Flash Memory Write Key This + // field contains a write key which + // is used to minimize the incidence + // of accidental Flash memory + // writes. The value 0xA442 must be + // written into this field for a + // write to occur. Writes to the + // FMC2 register without this WRKEY + // value are ignored. A read of this + // field returns the value 0. +#define FLASH_CTRL_FMC2_WRKEY_S 16 +#define FLASH_CTRL_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write This + // bit is used to start a buffered + // write to Flash memory. Value + // Description 1 Set this bit to + // write the data stored in the FWBn + // registers to the location + // specified by the contents of the + // FMA register. When read a 1 + // indicates that the previous + // buffered Flash memory write + // access is not complete. 0 A write + // of 0 has no effect on the state + // of this bit. When read a 0 + // indicates that the previous + // buffered Flash memory write + // access is complete. +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWBVAL register. +// +//****************************************************************************** +#define FLASH_CTRL_FWBVAL_FWBN_M \ + 0xFFFFFFFF // Flash Memory Write Buffer Value + // Description 1 The corresponding + // FWBn register has been updated + // since the last buffer write + // operation and is ready to be + // written to Flash memory. 0 The + // corresponding FWBn register has + // no new data to be written. Bit 0 + // corresponds to FWB0 offset 0x100 + // and bit 31 corresponds to FWB31 + // offset 0x13C. + +#define FLASH_CTRL_FWBVAL_FWBN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB1 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB1_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB1_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB2 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB2_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB2_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB3 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB3_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB3_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB4 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB4_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB4_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB5 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB5_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB5_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB6 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB6_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB6_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB7 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB7_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB7_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB8 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB8_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB8_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the FLASH_CTRL_O_FWB9 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB9_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB9_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB10 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB10_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB10_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB11 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB11_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB11_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB12 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB12_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB12_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB13 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB13_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB13_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB14 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB14_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB14_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB15 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB15_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB15_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB16 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB16_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB16_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB17 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB17_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB17_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB18 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB18_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB18_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB19 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB19_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB19_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB20 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB20_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB20_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB21 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB21_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB21_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB22 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB22_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB22_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB23 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB23_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB23_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB24 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB24_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB24_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB25 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB25_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB25_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB26 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB26_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB26_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB27 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB27_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB27_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB28 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB28_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB28_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB29 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB29_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB29_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB30 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB30_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB30_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB31 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB31_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB31_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FWB32 register. +// +//****************************************************************************** +#define FLASH_CTRL_FWB32_DATA_M 0xFFFFFFFF // Data Data to be written into the + // Flash memory. +#define FLASH_CTRL_FWB32_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_FSIZE register. +// +//****************************************************************************** +#define FLASH_CTRL_FSIZE_SIZE_M 0x0000FFFF // Flash Size Indicates the size of + // the on-chip Flash memory. Value + // Description 0x0003 8 KB of Flash + // 0x0007 16 KB of Flash 0x000F 32 + // KB of Flash 0x001F 64 KB of Flash + // 0x002F 96 KB of Flash 0x003F 128 + // KB of Flash 0x005F 192 KB of + // Flash 0x007F 256 KB of Flash +#define FLASH_CTRL_FSIZE_SIZE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// FLASH_CTRL_O_SSIZE register. +// +//****************************************************************************** +#define FLASH_CTRL_SSIZE_SRAM_SIZE_M \ + 0x0000FFFF // SRAM Size Indicates the size of + // the on-chip SRAM. Value + // Description 0x0007 2 KB of SRAM + // 0x000F 4 KB of SRAM 0x0017 6 KB + // of SRAM 0x001F 8 KB of SRAM + // 0x002F 12 KB of SRAM 0x003F 16 KB + // of SRAM 0x004F 20 KB of SRAM + // 0x005F 24 KB of SRAM 0x007F 32 KB + // of SRAM + +#define FLASH_CTRL_SSIZE_SRAM_SIZE_S 0 +#define FLASH_CTRL_FMC_WRKEY 0xA4420000 // FLASH write key +#define FLASH_CTRL_FMC2_WRKEY 0xA4420000 // FLASH write key +#define FLASH_CTRL_O_FWBN FLASH_CTRL_O_FWB1 +#define FLASH_ERASE_SIZE 0x00000400 +#define FLASH_PROTECT_SIZE 0x00000800 +#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 + +#define FLASH_FMPRE0 0x400FE200 // Flash Memory Protection Read + // Enable 0 +#define FLASH_FMPRE1 0x400FE204 // Flash Memory Protection Read + // Enable 1 +#define FLASH_FMPRE2 0x400FE208 // Flash Memory Protection Read + // Enable 2 +#define FLASH_FMPRE3 0x400FE20C // Flash Memory Protection Read + // Enable 3 +#define FLASH_FMPRE4 0x400FE210 // Flash Memory Protection Read + // Enable 4 +#define FLASH_FMPRE5 0x400FE214 // Flash Memory Protection Read + // Enable 5 +#define FLASH_FMPRE6 0x400FE218 // Flash Memory Protection Read + // Enable 6 +#define FLASH_FMPRE7 0x400FE21C // Flash Memory Protection Read + // Enable 7 +#define FLASH_FMPRE8 0x400FE220 // Flash Memory Protection Read + // Enable 8 +#define FLASH_FMPRE9 0x400FE224 // Flash Memory Protection Read + // Enable 9 +#define FLASH_FMPRE10 0x400FE228 // Flash Memory Protection Read + // Enable 10 +#define FLASH_FMPRE11 0x400FE22C // Flash Memory Protection Read + // Enable 11 +#define FLASH_FMPRE12 0x400FE230 // Flash Memory Protection Read + // Enable 12 +#define FLASH_FMPRE13 0x400FE234 // Flash Memory Protection Read + // Enable 13 +#define FLASH_FMPRE14 0x400FE238 // Flash Memory Protection Read + // Enable 14 +#define FLASH_FMPRE15 0x400FE23C // Flash Memory Protection Read + // Enable 15 + +#define FLASH_FMPPE0 0x400FE400 // Flash Memory Protection Program + // Enable 0 +#define FLASH_FMPPE1 0x400FE404 // Flash Memory Protection Program + // Enable 1 +#define FLASH_FMPPE2 0x400FE408 // Flash Memory Protection Program + // Enable 2 +#define FLASH_FMPPE3 0x400FE40C // Flash Memory Protection Program + // Enable 3 +#define FLASH_FMPPE4 0x400FE410 // Flash Memory Protection Program + // Enable 4 +#define FLASH_FMPPE5 0x400FE414 // Flash Memory Protection Program + // Enable 5 +#define FLASH_FMPPE6 0x400FE418 // Flash Memory Protection Program + // Enable 6 +#define FLASH_FMPPE7 0x400FE41C // Flash Memory Protection Program + // Enable 7 +#define FLASH_FMPPE8 0x400FE420 // Flash Memory Protection Program + // Enable 8 +#define FLASH_FMPPE9 0x400FE424 // Flash Memory Protection Program + // Enable 9 +#define FLASH_FMPPE10 0x400FE428 // Flash Memory Protection Program + // Enable 10 +#define FLASH_FMPPE11 0x400FE42C // Flash Memory Protection Program + // Enable 11 +#define FLASH_FMPPE12 0x400FE430 // Flash Memory Protection Program + // Enable 12 +#define FLASH_FMPPE13 0x400FE434 // Flash Memory Protection Program + // Enable 13 +#define FLASH_FMPPE14 0x400FE438 // Flash Memory Protection Program + // Enable 14 +#define FLASH_FMPPE15 0x400FE43C // Flash Memory Protection Program + // Enable 15 + +#define FLASH_USECRL 0x400FE140 // USec Reload +#define FLASH_CTRL_ERASE_SIZE 0x00000400 + + +#endif // __HW_FLASH_CTRL_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_gpio.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_gpio.h new file mode 100644 index 00000000..2bd6e0f3 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_gpio.h @@ -0,0 +1,1349 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_GPIO_H__ +#define __HW_GPIO_H__ + +//***************************************************************************** +// +// The following are defines for the GPIO register offsets. +// +//***************************************************************************** +#define GPIO_O_GPIO_DATA 0x00000000 // 0x4000 5000 0x4000 6000 0x4000 + // 7000 0x4002 4000 GPIO Data + // (GPIODATA)@@ offset 0x000 The + // GPIODATA register is the data + // register. In software control + // mode@@ values written in the + // GPIODATA register are transferred + // onto the GPIO port pins if the + // respective pins have been + // configured as outputs through the + // GPIO Direction (GPIODIR) register + // (see page 653). In order to write + // to GPIODATA@@ the corresponding + // bits in the mask@@ resulting from + // the address bus bits [9:2]@@ must + // be set. Otherwise@@ the bit + // values remain unchanged by the + // write. Similarly@@ the values + // read from this register are + // determined for each bit by the + // mask bit derived from the address + // used to access the data + // register@@ bits [9:2]. Bits that + // are set in the address mask cause + // the corresponding bits in + // GPIODATA to be read@@ and bits + // that are clear in the address + // mask cause the corresponding bits + // in GPIODATA to be read as 0@@ + // regardless of their value. A read + // from GPIODATA returns the last + // bit value written if the + // respective pins are configured as + // outputs@@ or it returns the value + // on the corresponding input pin + // when these are configured as + // inputs. All bits are cleared by a + // reset. +#define GPIO_O_GPIO_DIR 0x00000400 // 0x4000 5400 0x4000 6400 0x4000 + // 7400 0x4002 4400 GPIO Direction + // (GPIODIR)@@ offset 0x400 The + // GPIODIR register is the data + // direction register. Setting a bit + // in the GPIODIR register + // configures the corresponding pin + // to be an output@@ while clearing + // a bit configures the + // corresponding pin to be an input. + // All bits are cleared by a reset@@ + // meaning all GPIO pins are inputs + // by default. +#define GPIO_O_GPIO_IS 0x00000404 // 0x4000 5404 0x4000 6404 0x4000 + // 7404 0x4002 4404 GPIO Interrupt + // Sense (GPIOIS)@@ offset 0x404 The + // GPIOIS register is the interrupt + // sense register. Setting a bit in + // the GPIOIS register configures + // the corresponding pin to detect + // levels@@ while clearing a bit + // configures the corresponding pin + // to detect edges. All bits are + // cleared by a reset. +#define GPIO_O_GPIO_IBE 0x00000408 // 0x4000 5408 0x4000 6408 0x4000 + // 7408 0x4002 4408 GPIO Interrupt + // Both Edges (GPIOIBE)@@ offset + // 0x408 The GPIOIBE register allows + // both edges to cause interrupts. + // When the corresponding bit in the + // GPIO Interrupt Sense (GPIOIS) + // register is set to detect edges@@ + // setting a bit in the GPIOIBE + // register configures the + // corresponding pin to detect both + // rising and falling edges@@ + // regardless of the corresponding + // bit in the GPIO Interrupt Event + // (GPIOIEV) register . Clearing a + // bit configures the pin to be + // controlled by the GPIOIEV + // register. All bits are cleared by + // a reset. +#define GPIO_O_GPIO_IEV 0x0000040C // 0x4000 540C 0x4000 640C 0x4000 + // 740C 0x4002 440C GPIO Interrupt + // Event (GPIOIEV)@@ offset 0x40C + // The GPIOIEV register is the + // interrupt event register. Setting + // a bit in the GPIOIEV register + // configures the corresponding pin + // to detect rising edges or high + // levels@@ depending on the + // corresponding bit value in the + // GPIO Interrupt Sense (GPIOIS) + // register . Clearing a bit + // configures the pin to detect + // falling edges or low levels@@ + // depending on the corresponding + // bit value in the GPIOIS register. + // All bits are cleared by a reset. +#define GPIO_O_GPIO_IM 0x00000410 // 0x4000 5410 0x4000 6410 0x4000 + // 7410 0x4002 4410 GPIO Interrupt + // Mask (GPIOIM)@@ offset 0x410 The + // GPIOIM register is the interrupt + // mask register. Setting a bit in + // the GPIOIM register allows + // interrupts that are generated by + // the corresponding pin to be sent + // to the interrupt controller on + // the combined interrupt signal. + // Clearing a bit prevents an + // interrupt on the corresponding + // pin from being sent to the + // interrupt controller. All bits + // are cleared by a reset. +#define GPIO_O_GPIO_RIS 0x00000414 // 0x4000 5414 0x4000 6414 0x4000 + // 7414 0x4002 4414 GPIO Raw + // Interrupt Status (GPIORIS)@@ + // offset 0x414 The GPIORIS register + // is the raw interrupt status + // register. A bit in this register + // is set when an interrupt + // condition occurs on the + // corresponding GPIO pin. If the + // corresponding bit in the GPIO + // Interrupt Mask (GPIOIM) register + // is set@@ the interrupt is sent to + // the interrupt controller. Bits + // read as zero indicate that + // corresponding input pins have not + // initiated an interrupt. A bit in + // this register can be cleared by + // writing a 1 to the corresponding + // bit in the GPIO Interrupt Clear + // (GPIOICR) register. +#define GPIO_O_GPIO_MIS 0x00000418 // 0x4000 5418 0x4000 6418 0x4000 + // 7418 0x4002 4418 GPIO Masked + // Interrupt Status (GPIOMIS)@@ + // offset 0x418 The GPIOMIS register + // is the masked interrupt status + // register. If a bit is set in this + // register@@ the corresponding + // interrupt has triggered an + // interrupt to the interrupt + // controller. If a bit is clear@@ + // either no interrupt has been + // generated@@ or the interrupt is + // masked. If no port pin@@ other + // than the one that is being used + // as an ADC trigger@@ is being used + // to generate interrupts@@ the + // appropriate Interrupt Set Enable + // (ENn) register can disable the + // interrupts for the port@@ and the + // ADC interrupt can be used to read + // back the converted data. + // Otherwise@@ the port interrupt + // handler must ignore and clear + // interrupts on the port pin and + // wait for the ADC interrupt@@ or + // the ADC interrupt must be + // disabled in the EN0 register and + // the port interrupt handler must + // poll the ADC registers until the + // conversion is completed. If no + // port pin@@ other than the one + // that is being used as an ADC + // trigger@@ is being used to + // generate interrupts@@ the + // appropriate Interrupt Set Enable + // (ENn) register can disable the + // interrupts for the port@@ and the + // ADC interrupt can be used to read + // back the converted data. + // Otherwise@@ the port interrupt + // handler must ignore and clear + // interrupts on the port pin and + // wait for the ADC interrupt@@ or + // the ADC interrupt must be + // disabled in the EN0 register and + // the port interrupt handler must + // poll the ADC registers until the + // conversion is completed. Note + // that if the Port B GPIOADCCTL + // register is cleared@@ PB4 can + // still be used as an external + // trigger for the ADC. This is a + // legacy mode which allows code + // written for previous Stellaris + // devices to operate on this + // microcontroller. GPIOMIS is the + // state of the interrupt after + // masking. +#define GPIO_O_GPIO_ICR 0x0000041C // 0x4000 541C 0x4000 641C 0x4000 + // 741C 0x4002 441C GPIO Interrupt + // Clear (GPIOICR)@@ offset 0x41C + // The GPIOICR register is the + // interrupt clear register. Writing + // a 1 to a bit in this register + // clears the corresponding + // interrupt bit in the GPIORIS and + // GPIOMIS registers. Writing a 0 + // has no effect. +#define GPIO_O_GPIO_AFSEL 0x00000420 // 0x4000 5420 0x4000 6420 0x4000 + // 7420 0x4002 4420 GPIO Alternate + // Function Select (GPIOAFSEL)@@ + // offset 0x420 The GPIOAFSEL + // register is the mode control + // select register. If a bit is + // clear@@ the pin is used as a GPIO + // and is controlled by the GPIO + // registers. Setting a bit in this + // register configures the + // corresponding GPIO line to be + // controlled by an associated + // peripheral. Several possible + // peripheral functions are + // multiplexed on each GPIO. The + // GPIO Port Control (GPIOPCTL) + // register is used to select one of + // the possible functions. +#define GPIO_O_GPIO_DR2R 0x00000500 // 0x4000 5500 0x4000 6500 0x4000 + // 7500 0x4002 4500 GPIO 2-mA Drive + // Select (GPIODR2R)@@ offset 0x500 + // The GPIODR2R register is the 2-mA + // drive control register. Each GPIO + // signal in the port can be + // individually configured without + // affecting the other pads. When + // setting the DRV2 bit for a GPIO + // signal@@ the corresponding DRV4 + // bit in the GPIODR4R register and + // DRV8 bit in the GPIODR8R register + // are automatically cleared by + // hardware. By default@@ all GPIO + // pins have 2-mA drive. +#define GPIO_O_GPIO_DR4R 0x00000504 // 0x4000 5504 0x4000 6504 0x4000 + // 7504 0x4002 4504 GPIO 4-mA Drive + // Select (GPIODR4R)@@ offset 0x504 + // The GPIODR4R register is the 4-mA + // drive control register. Each GPIO + // signal in the port can be + // individually configured without + // affecting the other pads. When + // setting the DRV4 bit for a GPIO + // signal@@ the corresponding DRV2 + // bit in the GPIODR2R register and + // DRV8 bit in the GPIODR8R register + // are automatically cleared by + // hardware. +#define GPIO_O_GPIO_DR8R 0x00000508 // 0x4000 5508 0x4000 6508 0x4000 + // 7508 0x4002 4508 GPIO 8-mA Drive + // Select (GPIODR8R)@@ offset 0x508 + // The GPIODR8R register is the 8-mA + // drive control register. Each GPIO + // signal in the port can be + // individually configured without + // affecting the other pads. When + // setting the DRV8 bit for a GPIO + // signal@@ the corresponding DRV2 + // bit in the GPIODR2R register and + // DRV4 bit in the GPIODR4R register + // are automatically cleared by + // hardware. The 8-mA setting is + // also used for high-current + // operation. Note: There is no + // configuration difference between + // 8-mA and high-current operation. + // The additional current capacity + // results from a shift in the + // VOH/VOL levels. +#define GPIO_O_GPIO_ODR 0x0000050C // 0x4000 550C 0x4000 650C 0x4000 + // 750C 0x4002 450C GPIO Open Drain + // Select (GPIOODR)@@ offset 0x50C + // The GPIOODR register is the open + // drain control register. Setting a + // bit in this register enables the + // open-drain configuration of the + // corresponding GPIO pad. When + // open-drain mode is enabled@@ the + // corresponding bit should also be + // set in the GPIO Digital Input + // Enable (GPIODEN) register . + // Corresponding bits in the drive + // strength and slew rate control + // registers (GPIODR2R@@ GPIODR4R@@ + // GPIODR8R@@ and GPIOSLR) can be + // set to achieve the desired rise + // and fall times. The GPIO acts as + // an open-drain input if the + // corresponding bit in the GPIODIR + // register is cleared. If open + // drain is selected while the GPIO + // is configured as an input@@ the + // GPIO will remain an input and the + // open-drain selection has no + // effect until the GPIO is changed + // to an output. When using the I2C + // module@@ in addition to + // configuring the pin to open + // drain@@ the GPIO Alternate + // Function Select (GPIOAFSEL) + // register bits for the I2C clock + // and data pins should be set +#define GPIO_O_GPIO_PUR 0x00000510 // 0x4000 5510 0x4000 6510 0x4000 + // 7510 0x4002 4510 GPIO Pull-Up + // Select (GPIOPUR)@@ offset 0x510 + // The GPIOPUR register is the + // pull-up control register. When a + // bit is set@@ a weak pull-up + // resistor on the corresponding + // GPIO signal is enabled. Setting a + // bit in GPIOPUR automatically + // clears the corresponding bit in + // the GPIO Pull-Down Select + // (GPIOPDR) register . Write access + // to this register is protected + // with the GPIOCR register. Bits in + // GPIOCR that are cleared prevent + // writes to the equivalent bit in + // this register. +#define GPIO_O_GPIO_PDR 0x00000514 // 0x4000 5514 0x4000 6514 0x4000 + // 7514 0x4002 4514 GPIO Pull-Down + // Select (GPIOPDR)@@ offset 0x514 + // The GPIOPDR register is the + // pull-down control register. When + // a bit is set@@ a weak pull-down + // resistor on the corresponding + // GPIO signal is enabled. Setting a + // bit in GPIOPDR automatically + // clears the corresponding bit in + // the GPIO Pull-Up Select (GPIOPUR) + // register +#define GPIO_O_GPIO_SLR 0x00000518 // 0x4000 5518 0x4000 6518 0x4000 + // 7518 0x4002 4518 The GPIOSLR + // register is the slew rate control + // register. Slew rate control is + // only available when using the + // 8-mA drive strength option via + // the GPIO 8-mA Drive Select + // (GPIODR8R) register +#define GPIO_O_GPIO_DEN 0x0000051C // 0x4000 551C 0x4000 651C 0x4000 + // 751C 0x4002 451C GPIO Digital + // Enable (GPIODEN)@@ offset 0x51C + // Note: Pins configured as digital + // inputs are Schmitt-triggered. The + // GPIODEN register is the digital + // enable register. By default@@ all + // GPIO signals except those listed + // below are configured out of reset + // to be undriven (tristate). Their + // digital function is disabled; + // they do not drive a logic value + // on the pin and they do not allow + // the pin voltage into the GPIO + // receiver. To use the pin as a + // digital input or output (either + // GPIO or alternate function)@@ the + // corresponding GPIODEN bit must be + // set. +#define GPIO_O_GPIO_LOCK 0x00000520 // 0x4000 5520 0x4000 6520 0x4000 + // 7520 0x4002 4520 GPIO Lock + // (GPIOLOCK)@@ offset 0x520 The + // GPIOLOCK register enables write + // access to the GPIOCR register . + // Writing 0x4C4F.434B to the + // GPIOLOCK register unlocks the + // GPIOCR register. Writing any + // other value to the GPIOLOCK + // register re-enables the locked + // state. Reading the GPIOLOCK + // register returns the lock status + // rather than the 32-bit value that + // was previously written. + // Therefore@@ when write accesses + // are disabled@@ or locked@@ + // reading the GPIOLOCK register + // returns 0x0000.0001. When write + // accesses are enabled@@ or + // unlocked@@ reading the GPIOLOCK + // register returns 0x0000.0000. +#define GPIO_O_GPIO_CR 0x00000524 // 0x4000 5524 0x4000 6524 0x4000 + // 7524 0x4002 4524 GPIO Commit + // (GPIOCR)@@ offset 0x524 The + // GPIOCR register is the commit + // register. The value of the GPIOCR + // register determines which bits of + // the GPIOAFSEL@@ GPIOPUR@@ + // GPIOPDR@@ and GPIODEN registers + // are committed when a write to + // these registers is performed. If + // a bit in the GPIOCR register is + // cleared@@ the data being written + // to the corresponding bit in the + // GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@ + // or GPIODEN registers cannot be + // committed and retains its + // previous value. If a bit in the + // GPIOCR register is set@@ the data + // being written to the + // corresponding bit of the + // GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@ + // or GPIODEN registers is committed + // to the register and reflects the + // new value. The contents of the + // GPIOCR register can only be + // modified if the status in the + // GPIOLOCK register is unlocked. + // Writes to the GPIOCR register are + // ignored if the status in the + // GPIOLOCK register is locked. +#define GPIO_O_GPIO_AMSEL 0x00000528 // 0x4000 5528 0x4000 6528 0x4000 + // 7528 0x4002 4528 The GPIOAMSEL + // register controls isolation + // circuits to the analog side of a + // unified I/O pad. Because the + // GPIOs may be driven by a 5-V + // source and affect analog + // operation@@ analog circuitry + // requires isolation from the pins + // when they are not used in their + // analog function. Each bit of this + // register controls the isolation + // circuitry for the corresponding + // GPIO signal. +#define GPIO_O_GPIO_PCTL 0x0000052C // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) 0x4000 552C + // 0x4000 652C 0x4000 752C 0x4002 + // 452C GPIO Port Control + // (GPIOPCTL)@@ offset 0x52C The + // GPIOPCTL register is used in + // conjunction with the GPIOAFSEL + // register and selects the specific + // peripheral signal for each GPIO + // pin when using the alternate + // function mode. Most bits in the + // GPIOAFSEL register are cleared on + // reset@@ therefore most GPIO pins + // are configured as GPIOs by + // default. When a bit is set in the + // GPIOAFSEL register@@ the + // corresponding GPIO signal is + // controlled by an associated + // peripheral. The GPIOPCTL register + // selects one out of a set of + // peripheral functions for each + // GPIO@@ providing additional + // flexibility in signal definition. +#define GPIO_O_GPIO_ADCCTL 0x00000530 // This register is not used in + // cc3xx. ADC trigger via GPIO is + // not supported. 0x4000 5530 0x4000 + // 6530 0x4000 7530 0x4002 4530 GPIO + // ADC Control (GPIOADCCTL)@@ offset + // 0x530 This register is used to + // configure a GPIO pin as a source + // for the ADC trigger. Note that if + // the Port B GPIOADCCTL register is + // cleared@@ PB4 can still be used + // as an external trigger for the + // ADC. This is a legacy mode which + // allows code written for previous + // Stellaris devices to operate on + // this microcontroller. +#define GPIO_O_GPIO_DMACTL 0x00000534 // 0x4000 5534 0x4000 6534 0x4000 + // 7534 0x4002 4534 GPIO DMA Control + // (GPIODMACTL)@@ offset 0x534 This + // register is used to configure a + // GPIO pin as a source for the ?DMA + // trigger. +#define GPIO_O_GPIO_SI 0x00000538 // 0x4000 5538 0x4000 6538 0x4000 + // 7538 0x4002 4538 GPIO Select + // Interrupt (GPIOSI)@@ offset 0x538 + // This register is used to enable + // individual interrupts for each + // pin. Note: This register is only + // available on Port P and Port Q. +#define GPIO_O_GPIO_PERIPHID4 0x00000FD0 // 0x4000 5FD0 0x4000 6FD0 0x4000 + // 7FD0 0x4002 4FD0 GPIO Peripheral + // Identification 4 + // (GPIOPeriphID4)@@ offset 0xFD0 + // The GPIOPeriphID4@@ + // GPIOPeriphID5@@ GPIOPeriphID6@@ + // and GPIOPeriphID7 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID5 0x00000FD4 // 0x4000 5FD4 0x4000 6FD4 0x4000 + // 7FD4 0x4002 4FD4 GPIO Peripheral + // Identification 5 + // (GPIOPeriphID5)@@ offset 0xFD4 + // The GPIOPeriphID4@@ + // GPIOPeriphID5@@ GPIOPeriphID6@@ + // and GPIOPeriphID7 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID6 0x00000FD8 // 0x4000 5FD8 0x4000 6FD8 0x4000 + // 7FD8 0x4002 4FD8 GPIO Peripheral + // Identification 6 + // (GPIOPeriphID6)@@ offset 0xFD8 + // The GPIOPeriphID4@@ + // GPIOPeriphID5@@ GPIOPeriphID6@@ + // and GPIOPeriphID7 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID7 0x00000FDC // 0x4000 5FDC 0x4000 6FDC 0x4000 + // 7FDC 0x4002 4FDC GPIO Peripheral + // Identification 7 + // (GPIOPeriphID7)@@ offset 0xFDC + // The GPIOPeriphID4@@ + // GPIOPeriphID5@@ GPIOPeriphID6@@ + // and GPIOPeriphID7 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID0 0x00000FE0 // 0x4000 5FE0 0x4000 6FE0 0x4000 + // 7FE0 0x4002 4FE0 GPIO Peripheral + // Identification 0 + // (GPIOPeriphID0)@@ offset 0xFE0 + // The GPIOPeriphID0@@ + // GPIOPeriphID1@@ GPIOPeriphID2@@ + // and GPIOPeriphID3 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID1 0x00000FE4 // 0x4000 5FE4 0x4000 6FE4 0x4000 + // 7FE4 0x4002 4FE4 GPIO Peripheral + // Identification 1 + // (GPIOPeriphID1)@@ offset 0xFE4 + // The GPIOPeriphID0@@ + // GPIOPeriphID1@@ GPIOPeriphID2@@ + // and GPIOPeriphID3 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID2 0x00000FE8 // 0x4000 5FE8 0x4000 6FE8 0x4000 + // 7FE8 0x4002 4FE8 GPIO Peripheral + // Identification 2 + // (GPIOPeriphID2)@@ offset 0xFE8 + // The GPIOPeriphID0@@ + // GPIOPeriphID1@@ GPIOPeriphID2@@ + // and GPIOPeriphID3 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PERIPHID3 0x00000FEC // 0x4000 5FEC 0x4000 6FEC 0x4000 + // 7FEC 0x4002 4FEC GPIO Peripheral + // Identification 3 + // (GPIOPeriphID3)@@ offset 0xFEC + // The GPIOPeriphID0@@ + // GPIOPeriphID1@@ GPIOPeriphID2@@ + // and GPIOPeriphID3 registers can + // conceptually be treated as one + // 32-bit register; each register + // contains eight bits of the 32-bit + // register@@ used by software to + // identify the peripheral. +#define GPIO_O_GPIO_PCELLID0 0x00000FF0 // 0x4000 5FF0 0x4000 6FF0 0x4000 + // 7FF0 0x4002 4FF0 GPIO PrimeCell + // Identification 0 (GPIOPCellID0)@@ + // offset 0xFF0 The GPIOPCellID0@@ + // GPIOPCellID1@@ GPIOPCellID2@@ and + // GPIOPCellID3 registers are four + // 8-bit wide registers@@ that can + // conceptually be treated as one + // 32-bit register. The register is + // used as a standard + // cross-peripheral identification + // system. +#define GPIO_O_GPIO_PCELLID1 0x00000FF4 // 0x4000 5FF4 0x4000 6FF4 0x4000 + // 7FF4 0x4002 4FF4 GPIO PrimeCell + // Identification 1 (GPIOPCellID1)@@ + // offset 0xFF4 The GPIOPCellID0@@ + // GPIOPCellID1@@ GPIOPCellID2@@ and + // GPIOPCellID3 registers are four + // 8-bit wide registers@@ that can + // conceptually be treated as one + // 32-bit register. The register is + // used as a standard + // cross-peripheral identification + // system. +#define GPIO_O_GPIO_PCELLID2 0x00000FF8 // 0x4000 5FF8 0x4000 6FF8 0x4000 + // 7FF8 0x4002 4FF8 GPIO PrimeCell + // Identification 2 (GPIOPCellID2)@@ + // offset 0xFF8 The GPIOPCellID0@@ + // GPIOPCellID1@@ GPIOPCellID2@@ and + // GPIOPCellID3 registers are four + // 8-bit wide registers@@ that can + // conceptually be treated as one + // 32-bit register. The register is + // used as a standard + // cross-peripheral identification + // system. +#define GPIO_O_GPIO_PCELLID3 0x00000FFC // 0x4000 5FFC 0x4000 6FFC 0x4000 + // 7FFC 0x4002 4FFC GPIO PrimeCell + // Identification 3 (GPIOPCellID3)@@ + // offset 0xFFC The GPIOPCellID0@@ + // GPIOPCellID1@@ GPIOPCellID2@@ and + // GPIOPCellID3 registers are four + // 8-bit wide registers@@ that can + // conceptually be treated as one + // 32-bit register. The register is + // used as a standard + // cross-peripheral identification + // system.0xb1 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_DATA register. +// +//****************************************************************************** +#define GPIO_GPIO_DATA_DATA_M 0x000000FF // GPIO Data This register is + // virtually mapped to 256 locations + // in the address space. To + // facilitate the reading and + // writing of data to these + // registers by independent + // drivers@@ the data read from and + // written to the registers are + // masked by the eight address lines + // [9:2]. Reads from this register + // return its current state. Writes + // to this register only affect bits + // that are not masked by ADDR[9:2] + // and are configured as outputs. +#define GPIO_GPIO_DATA_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_DIR register. +// +//****************************************************************************** +#define GPIO_GPIO_DIR_DIR_M 0x000000FF // GPIO Data Direction Value + // Description 0 Corresponding pin + // is an input. 1 Corresponding pins + // is an output. +#define GPIO_GPIO_DIR_DIR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_IS register. +// +//****************************************************************************** +#define GPIO_GPIO_IS_IS_M 0x000000FF // GPIO Interrupt Sense Value + // Description 0 The edge on the + // corresponding pin is detected + // (edge-sensitive). 1 The level on + // the corresponding pin is detected + // (level-sensitive). +#define GPIO_GPIO_IS_IS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_IBE register. +// +//****************************************************************************** +#define GPIO_GPIO_IBE_IBE_M 0x000000FF // GPIO Interrupt Both Edges Value + // Description 0 Interrupt + // generation is controlled by the + // GPIO Interrupt Event (GPIOIEV) + // register. 1 Both edges on the + // corresponding pin trigger an + // interrupt. +#define GPIO_GPIO_IBE_IBE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_IEV register. +// +//****************************************************************************** +#define GPIO_GPIO_IEV_IEV_M 0x000000FF // GPIO Interrupt Event Value + // Description 1 A falling edge or a + // Low level on the corresponding + // pin triggers an interrupt. 0 A + // rising edge or a High level on + // the corresponding pin triggers an + // interrupt. +#define GPIO_GPIO_IEV_IEV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_IM register. +// +//****************************************************************************** +#define GPIO_GPIO_IM_IME_M 0x000000FF // GPIO Interrupt Mask Enable Value + // Description 0 The interrupt from + // the corresponding pin is masked. + // 1 The interrupt from the + // corresponding pin is sent to the + // interrupt controller. +#define GPIO_GPIO_IM_IME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_RIS register. +// +//****************************************************************************** +#define GPIO_GPIO_RIS_RIS_M 0x000000FF // GPIO Interrupt Raw Status Value + // Description 1 An interrupt + // condition has occurred on the + // corresponding pin. 0 interrupt + // condition has not occurred on the + // corresponding pin. A bit is + // cleared by writing a 1 to the + // corresponding bit in the GPIOICR + // register. +#define GPIO_GPIO_RIS_RIS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_MIS register. +// +//****************************************************************************** +#define GPIO_GPIO_MIS_MIS_M 0x000000FF // GPIO Masked Interrupt Status + // Value Description 1 An interrupt + // condition on the corresponding + // pin has triggered an interrupt to + // the interrupt controller. 0 An + // interrupt condition on the + // corresponding pin is masked or + // has not occurred. A bit is + // cleared by writing a 1 to the + // corresponding bit in the GPIOICR + // register. +#define GPIO_GPIO_MIS_MIS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_ICR register. +// +//****************************************************************************** +#define GPIO_GPIO_ICR_IC_M 0x000000FF // GPIO Interrupt Clear Value + // Description 1 The corresponding + // interrupt is cleared. 0 The + // corresponding interrupt is + // unaffected. +#define GPIO_GPIO_ICR_IC_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_AFSEL register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_DR2R register. +// +//****************************************************************************** +#define GPIO_GPIO_DR2R_DRV2_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Output Pad + // 2-mA Drive Enable Value + // Description 1 The corresponding + // GPIO pin has 2-mA drive. The + // drive for the corresponding GPIO + // pin is controlled by the GPIODR4R + // or GPIODR8R register. 0 Setting a + // bit in either the GPIODR4 + // register or the GPIODR8 register + // clears the corresponding 2-mA + // enable bit. The change is + // effective on the second clock + // cycle after the write if + // accessing GPIO via the APB memory + // aperture. If using AHB access@@ + // the change is effective on the + // next clock cycle. +#define GPIO_GPIO_DR2R_DRV2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_DR4R register. +// +//****************************************************************************** +#define GPIO_GPIO_DR4R_DRV4_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Output Pad + // 4-mA Drive Enable Value + // Description 1 The corresponding + // GPIO pin has 4-mA drive. The + // drive for the corresponding GPIO + // pin is controlled by the GPIODR2R + // or GPIODR8R register. 0 Setting a + // bit in either the GPIODR2 + // register or the GPIODR8 register + // clears the corresponding 4-mA + // enable bit. The change is + // effective on the second clock + // cycle after the write if + // accessing GPIO via the APB memory + // aperture. If using AHB access@@ + // the change is effective on the + // next clock cycle. +#define GPIO_GPIO_DR4R_DRV4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_DR8R register. +// +//****************************************************************************** +#define GPIO_GPIO_DR8R_DRV8_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Output Pad + // 8-mA Drive Enable Value + // Description 1 The corresponding + // GPIO pin has 8-mA drive. The + // drive for the corresponding GPIO + // pin is controlled by the GPIODR2R + // or GPIODR4R register. 0 Setting a + // bit in either the GPIODR2 + // register or the GPIODR4 register + // clears the corresponding 8-mA + // enable bit. The change is + // effective on the second clock + // cycle after the write if + // accessing GPIO via the APB memory + // aperture. If using AHB access@@ + // the change is effective on the + // next clock cycle. +#define GPIO_GPIO_DR8R_DRV8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_ODR register. +// +//****************************************************************************** +#define GPIO_GPIO_ODR_ODE_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Output Pad + // Open Drain Enable Value + // Description 1 The corresponding + // pin is configured as open drain. + // 0 The corresponding pin is not + // configured as open drain. +#define GPIO_GPIO_ODR_ODE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_PUR register. +// +//****************************************************************************** +#define GPIO_GPIO_PUR_PUE_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Pad Weak + // Pull-Up Enable Value Description + // 1 The corresponding pin has a + // weak pull-up resistor. 0 The + // corresponding pin is not + // affected. Setting a bit in the + // GPIOPDR register clears the + // corresponding bit in the GPIOPUR + // register. The change is effective + // on the second clock cycle after + // the write if accessing GPIO via + // the APB memory aperture. If using + // AHB access@@ the change is + // effective on the next clock + // cycle. +#define GPIO_GPIO_PUR_PUE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_PDR register. +// +//****************************************************************************** +#define GPIO_GPIO_PDR_PDE_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Pad Weak + // Pull-Down Enable Value + // Description 1 The corresponding + // pin has a weak pull-down + // resistor. 0 The corresponding pin + // is not affected. Setting a bit in + // the GPIOPUR register clears the + // corresponding bit in the GPIOPDR + // register. The change is effective + // on the second clock cycle after + // the write if accessing GPIO via + // the APB memory aperture. If using + // AHB access@@ the change is + // effective on the next clock + // cycle. +#define GPIO_GPIO_PDR_PDE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_SLR register. +// +//****************************************************************************** +#define GPIO_GPIO_SLR_SRL_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Slew Rate + // Limit Enable (8-mA drive only) + // Value Description 1 Slew rate + // control is enabled for the + // corresponding pin. 0 Slew rate + // control is disabled for the + // corresponding pin. +#define GPIO_GPIO_SLR_SRL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_DEN register. +// +//****************************************************************************** +#define GPIO_GPIO_DEN_DEN_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Digital Enable + // Value Description 0 The digital + // functions for the corresponding + // pin are disabled. 1 The digital + // functions for the corresponding + // pin are enabled. +#define GPIO_GPIO_DEN_DEN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_LOCK register. +// +//****************************************************************************** +#define GPIO_GPIO_LOCK_LOCK_M 0xFFFFFFFF // This register is not used in + // cc3xx. GPIO Lock A write of the + // value 0x4C4F.434B unlocks the + // GPIO Commit (GPIOCR) register for + // write access.A write of any other + // value or a write to the GPIOCR + // register reapplies the lock@@ + // preventing any register updates. + // A read of this register returns + // the following values: Value + // Description 0x1 The GPIOCR + // register is locked and may not be + // modified. 0x0 The GPIOCR register + // is unlocked and may be modified. +#define GPIO_GPIO_LOCK_LOCK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_CR register. +// +//****************************************************************************** +#define GPIO_GPIO_CR_CR_M 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) GPIO Commit + // Value Description The + // corresponding GPIOAFSEL@@ + // GPIOPUR@@ GPIOPDR@@ or GPIODEN + // bits can be written. 1 The + // corresponding GPIOAFSEL@@ + // GPIOPUR@@ GPIOPDR@@ or GPIODEN + // bits cannot be written. 0 Note: + // The default register type for the + // GPIOCR register is RO for all + // GPIO pins with the exception of + // the NMI pin and the four JTAG/SWD + // pins (PD7@@ PF0@@ and PC[3:0]). + // These six pins are the only GPIOs + // that are protected by the GPIOCR + // register. Because of this@@ the + // register type for GPIO Port D7@@ + // GPIO Port F0@@ and GPIO Port + // C[3:0] is R/W. The default reset + // value for the GPIOCR register is + // 0x0000.00FF for all GPIO pins@@ + // with the exception of the NMI pin + // and the four JTAG/SWD pins (PD7@@ + // PF0@@ and PC[3:0]). To ensure + // that the JTAG port is not + // accidentally programmed as GPIO + // pins@@ the PC[3:0] pins default + // to non-committable. Similarly@@ + // to ensure that the NMI pin is not + // accidentally programmed as a GPIO + // pin@@ the PD7 and PF0 pins + // default to non-committable. + // Because of this@@ the default + // reset value of GPIOCR for GPIO + // Port C is 0x0000.00F0@@ for GPIO + // Port D is 0x0000.007F@@ and for + // GPIO Port F is 0x0000.00FE. +#define GPIO_GPIO_CR_CR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_AMSEL register. +// +//****************************************************************************** +#define GPIO_GPIO_AMSEL_GPIO_AMSEL_M \ + 0x000000FF // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) GPIO Analog + // Mode Select Value Description 1 + // The analog function of the pin is + // enabled@@ the isolation is + // disabled@@ and the pin is capable + // of analog functions. 0 The analog + // function of the pin is disabled@@ + // the isolation is enabled@@ and + // the pin is capable of digital + // functions as specified by the + // other GPIO configuration + // registers. Note: This register + // and bits are only valid for GPIO + // signals that share analog + // function through a unified I/O + // pad. The reset state of this + // register is 0 for all signals. + +#define GPIO_GPIO_AMSEL_GPIO_AMSEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_PCTL register. +// +//****************************************************************************** +#define GPIO_GPIO_PCTL_PMC7_M 0xF0000000 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 7 This field controls the + // configuration for GPIO pin 7. +#define GPIO_GPIO_PCTL_PMC7_S 28 +#define GPIO_GPIO_PCTL_PMC6_M 0x0F000000 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 6 This field controls the + // configuration for GPIO pin 6. +#define GPIO_GPIO_PCTL_PMC6_S 24 +#define GPIO_GPIO_PCTL_PMC5_M 0x00F00000 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 5 This field controls the + // configuration for GPIO pin 5. +#define GPIO_GPIO_PCTL_PMC5_S 20 +#define GPIO_GPIO_PCTL_PMC4_M 0x000F0000 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 4 This field controls the + // configuration for GPIO pin 4. +#define GPIO_GPIO_PCTL_PMC4_S 16 +#define GPIO_GPIO_PCTL_PMC3_M 0x0000F000 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 43 This field controls + // the configuration for GPIO pin 3. +#define GPIO_GPIO_PCTL_PMC3_S 12 +#define GPIO_GPIO_PCTL_PMC1_M 0x00000F00 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 1 This field controls the + // configuration for GPIO pin 1. +#define GPIO_GPIO_PCTL_PMC1_S 8 +#define GPIO_GPIO_PCTL_PMC2_M 0x000000F0 // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 2 This field controls the + // configuration for GPIO pin 2. +#define GPIO_GPIO_PCTL_PMC2_S 4 +#define GPIO_GPIO_PCTL_PMC0_M 0x0000000F // This register is not used in + // cc3xx. equivalant register exsist + // outside GPIO IP (refer + // PAD*_config register in the + // shared comn space) Port Mux + // Control 0 This field controls the + // configuration for GPIO pin 0. +#define GPIO_GPIO_PCTL_PMC0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_ADCCTL register. +// +//****************************************************************************** +#define GPIO_GPIO_ADCCTL_ADCEN_M \ + 0x000000FF // This register is not used in + // cc3xx. ADC trigger via GPIO is + // not supported. ADC Trigger Enable + // Value Description 1 The + // corresponding pin is used to + // trigger the ADC. 0 The + // corresponding pin is not used to + // trigger the ADC. + +#define GPIO_GPIO_ADCCTL_ADCEN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_DMACTL register. +// +//****************************************************************************** +#define GPIO_GPIO_DMACTL_DMAEN_M \ + 0x000000FF // This register is not used in the + // cc3xx. Alternate register to + // support this feature is coded in + // the APPS_NWP_CMN space. refer + // register as offset 0x400F70D8 + // ?DMA Trigger Enable Value + // Description 1 The corresponding + // pin is used to trigger the ?DMA. + // 0 The corresponding pin is not + // used to trigger the ?DMA. + +#define GPIO_GPIO_DMACTL_DMAEN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPIO_O_GPIO_SI register. +// +//****************************************************************************** +#define GPIO_GPIO_SI_SUM 0x00000001 // Summary Interrupt Value + // Description 1 Each pin has its + // own interrupt vector. 0 All port + // pin interrupts are OR'ed together + // to produce a summary interrupt. +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID4 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID4_PID4_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO Peripheral ID + // Register [7:0] + +#define GPIO_GPIO_PERIPHID4_PID4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID5 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID5_PID5_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO Peripheral ID + // Register [15:8] + +#define GPIO_GPIO_PERIPHID5_PID5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID6 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID6_PID6_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO Peripheral ID + // Register [23:16] + +#define GPIO_GPIO_PERIPHID6_PID6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID7 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID7_PID7_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO Peripheral ID + // Register [31:24] + +#define GPIO_GPIO_PERIPHID7_PID7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID0 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID0_PID0_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO Peripheral ID + // Register [7:0] Can be used by + // software to identify the presence + // of this peripheral. + +#define GPIO_GPIO_PERIPHID0_PID0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID1 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID1_PID1_M \ + 0x000000FF // GPIO Peripheral ID Register + // [15:8] Can be used by software to + // identify the presence of this + // peripheral. + +#define GPIO_GPIO_PERIPHID1_PID1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID2 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID2_PID2_M \ + 0x000000FF // This register is not used in + // CC3XX.v GPIO Peripheral ID + // Register [23:16] Can be used by + // software to identify the presence + // of this peripheral. + +#define GPIO_GPIO_PERIPHID2_PID2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PERIPHID3 register. +// +//****************************************************************************** +#define GPIO_GPIO_PERIPHID3_PID3_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO Peripheral ID + // Register [31:24] Can be used by + // software to identify the presence + // of this peripheral. + +#define GPIO_GPIO_PERIPHID3_PID3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PCELLID0 register. +// +//****************************************************************************** +#define GPIO_GPIO_PCELLID0_CID0_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO PrimeCell ID Register + // [7:0] Provides software a + // standard cross-peripheral + // identification system. + +#define GPIO_GPIO_PCELLID0_CID0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PCELLID1 register. +// +//****************************************************************************** +#define GPIO_GPIO_PCELLID1_CID1_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO PrimeCell ID Register + // [15:8] Provides software a + // standard cross-peripheral + // identification system. + +#define GPIO_GPIO_PCELLID1_CID1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PCELLID2 register. +// +//****************************************************************************** +#define GPIO_GPIO_PCELLID2_CID2_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO PrimeCell ID Register + // [23:16] Provides software a + // standard cross-peripheral + // identification system. + +#define GPIO_GPIO_PCELLID2_CID2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPIO_O_GPIO_PCELLID3 register. +// +//****************************************************************************** +#define GPIO_GPIO_PCELLID3_CID3_M \ + 0x000000FF // This register is not used in + // CC3XX. GPIO PrimeCell ID Register + // [31:24] Provides software a + // standard cross-peripheral + // identification system. + +#define GPIO_GPIO_PCELLID3_CID3_S 0 + + + +#endif // __HW_GPIO_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_gprcm.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_gprcm.h new file mode 100644 index 00000000..43628f4a --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_gprcm.h @@ -0,0 +1,3322 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_GPRCM_H__ +#define __HW_GPRCM_H__ + +//***************************************************************************** +// +// The following are defines for the GPRCM register offsets. +// +//***************************************************************************** +#define GPRCM_O_APPS_SOFT_RESET 0x00000000 +#define GPRCM_O_APPS_LPDS_WAKEUP_CFG \ + 0x00000004 + +#define GPRCM_O_APPS_LPDS_WAKEUP_SRC \ + 0x00000008 + +#define GPRCM_O_APPS_RESET_CAUSE \ + 0x0000000C + +#define GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG \ + 0x00000010 + +#define GPRCM_O_APPS_SRAM_DSLP_CFG \ + 0x00000018 + +#define GPRCM_O_APPS_SRAM_LPDS_CFG \ + 0x0000001C + +#define GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG \ + 0x00000020 + +#define GPRCM_O_TOP_DIE_ENABLE 0x00000100 +#define GPRCM_O_TOP_DIE_ENABLE_PARAMETERS \ + 0x00000104 + +#define GPRCM_O_MCU_GLOBAL_SOFT_RESET \ + 0x00000108 + +#define GPRCM_O_ADC_CLK_CONFIG 0x0000010C +#define GPRCM_O_APPS_GPIO_WAKE_CONF \ + 0x00000110 + +#define GPRCM_O_EN_NWP_BOOT_WO_DEVINIT \ + 0x00000114 + +#define GPRCM_O_MEM_HCLK_DIV_CFG \ + 0x00000118 + +#define GPRCM_O_MEM_SYSCLK_DIV_CFG \ + 0x0000011C + +#define GPRCM_O_APLLMCS_LOCK_TIME_CONF \ + 0x00000120 + +#define GPRCM_O_NWP_SOFT_RESET 0x00000400 +#define GPRCM_O_NWP_LPDS_WAKEUP_CFG \ + 0x00000404 + +#define GPRCM_O_NWP_LPDS_WAKEUP_SRC \ + 0x00000408 + +#define GPRCM_O_NWP_RESET_CAUSE 0x0000040C +#define GPRCM_O_NWP_LPDS_WAKETIME_OPP_CFG \ + 0x00000410 + +#define GPRCM_O_NWP_SRAM_DSLP_CFG \ + 0x00000418 + +#define GPRCM_O_NWP_SRAM_LPDS_CFG \ + 0x0000041C + +#define GPRCM_O_NWP_LPDS_WAKETIME_WAKE_CFG \ + 0x00000420 + +#define GPRCM_O_NWP_AUTONMS_SPI_MASTER_SEL \ + 0x00000424 + +#define GPRCM_O_NWP_AUTONMS_SPI_IDLE_REQ \ + 0x00000428 + +#define GPRCM_O_WLAN_TO_NWP_WAKE_REQUEST \ + 0x0000042C + +#define GPRCM_O_NWP_TO_WLAN_WAKE_REQUEST \ + 0x00000430 + +#define GPRCM_O_NWP_GPIO_WAKE_CONF \ + 0x00000434 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG12 \ + 0x00000438 + +#define GPRCM_O_GPRCM_DIEID_READ_REG5 \ + 0x00000448 + +#define GPRCM_O_GPRCM_DIEID_READ_REG6 \ + 0x0000044C + +#define GPRCM_O_REF_FSM_CFG0 0x00000800 +#define GPRCM_O_REF_FSM_CFG1 0x00000804 +#define GPRCM_O_APLLMCS_WLAN_CONFIG0_40 \ + 0x00000808 + +#define GPRCM_O_APLLMCS_WLAN_CONFIG1_40 \ + 0x0000080C + +#define GPRCM_O_APLLMCS_WLAN_CONFIG0_26 \ + 0x00000810 + +#define GPRCM_O_APLLMCS_WLAN_CONFIG1_26 \ + 0x00000814 + +#define GPRCM_O_APLLMCS_WLAN_OVERRIDES \ + 0x00000818 + +#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_38P4 \ + 0x0000081C + +#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_38P4 \ + 0x00000820 + +#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_26 \ + 0x00000824 + +#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_26 \ + 0x00000828 + +#define GPRCM_O_SPARE_RW0 0x0000082C +#define GPRCM_O_SPARE_RW1 0x00000830 +#define GPRCM_O_APLLMCS_MCU_OVERRIDES \ + 0x00000834 + +#define GPRCM_O_SYSCLK_SWITCH_STATUS \ + 0x00000838 + +#define GPRCM_O_REF_LDO_CONTROLS \ + 0x0000083C + +#define GPRCM_O_REF_RTRIM_CONTROL \ + 0x00000840 + +#define GPRCM_O_REF_SLICER_CONTROLS0 \ + 0x00000844 + +#define GPRCM_O_REF_SLICER_CONTROLS1 \ + 0x00000848 + +#define GPRCM_O_REF_ANA_BGAP_CONTROLS0 \ + 0x0000084C + +#define GPRCM_O_REF_ANA_BGAP_CONTROLS1 \ + 0x00000850 + +#define GPRCM_O_REF_ANA_SPARE_CONTROLS0 \ + 0x00000854 + +#define GPRCM_O_REF_ANA_SPARE_CONTROLS1 \ + 0x00000858 + +#define GPRCM_O_MEMSS_PSCON_OVERRIDES0 \ + 0x0000085C + +#define GPRCM_O_MEMSS_PSCON_OVERRIDES1 \ + 0x00000860 + +#define GPRCM_O_PLL_REF_LOCK_OVERRIDES \ + 0x00000864 + +#define GPRCM_O_MCU_PSCON_DEBUG 0x00000868 +#define GPRCM_O_MEMSS_PWR_PS 0x0000086C +#define GPRCM_O_REF_FSM_DEBUG 0x00000870 +#define GPRCM_O_MEM_SYS_OPP_REQ_OVERRIDE \ + 0x00000874 + +#define GPRCM_O_MEM_TESTCTRL_PD_OPP_CONFIG \ + 0x00000878 + +#define GPRCM_O_MEM_WL_FAST_CLK_REQ_OVERRIDES \ + 0x0000087C + +#define GPRCM_O_MEM_MCU_PD_MODE_REQ_OVERRIDES \ + 0x00000880 + +#define GPRCM_O_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES \ + 0x00000884 + +#define GPRCM_O_MEM_WLAN_APLLMCS_OVERRIDES \ + 0x00000888 + +#define GPRCM_O_MEM_REF_FSM_CFG2 \ + 0x0000088C + +#define GPRCM_O_TESTCTRL_POWER_CTRL \ + 0x00000C10 + +#define GPRCM_O_SSDIO_POWER_CTRL \ + 0x00000C14 + +#define GPRCM_O_MCSPI_N1_POWER_CTRL \ + 0x00000C18 + +#define GPRCM_O_WELP_POWER_CTRL 0x00000C1C +#define GPRCM_O_WL_SDIO_POWER_CTRL \ + 0x00000C20 + +#define GPRCM_O_WLAN_SRAM_ACTIVE_PWR_CFG \ + 0x00000C24 + +#define GPRCM_O_WLAN_SRAM_SLEEP_PWR_CFG \ + 0x00000C28 + +#define GPRCM_O_APPS_SECURE_INIT_DONE \ + 0x00000C30 + +#define GPRCM_O_APPS_DEV_MODE_INIT_DONE \ + 0x00000C34 + +#define GPRCM_O_EN_APPS_REBOOT 0x00000C38 +#define GPRCM_O_MEM_APPS_PERIPH_PRESENT \ + 0x00000C3C + +#define GPRCM_O_MEM_NWP_PERIPH_PRESENT \ + 0x00000C40 + +#define GPRCM_O_MEM_SHARED_PERIPH_PRESENT \ + 0x00000C44 + +#define GPRCM_O_NWP_PWR_STATE 0x00000C48 +#define GPRCM_O_APPS_PWR_STATE 0x00000C4C +#define GPRCM_O_MCU_PWR_STATE 0x00000C50 +#define GPRCM_O_WTOP_PM_PS 0x00000C54 +#define GPRCM_O_WTOP_PD_RESETZ_OVERRIDE_REG \ + 0x00000C58 + +#define GPRCM_O_WELP_PD_RESETZ_OVERRIDE_REG \ + 0x00000C5C + +#define GPRCM_O_WL_SDIO_PD_RESETZ_OVERRIDE_REG \ + 0x00000C60 + +#define GPRCM_O_SSDIO_PD_RESETZ_OVERRIDE_REG \ + 0x00000C64 + +#define GPRCM_O_MCSPI_N1_PD_RESETZ_OVERRIDE_REG \ + 0x00000C68 + +#define GPRCM_O_TESTCTRL_PD_RESETZ_OVERRIDE_REG \ + 0x00000C6C + +#define GPRCM_O_MCU_PD_RESETZ_OVERRIDE_REG \ + 0x00000C70 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG0 \ + 0x00000C78 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG1 \ + 0x00000C7C + +#define GPRCM_O_GPRCM_EFUSE_READ_REG2 \ + 0x00000C80 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG3 \ + 0x00000C84 + +#define GPRCM_O_WTOP_MEM_RET_CFG \ + 0x00000C88 + +#define GPRCM_O_COEX_CLK_SWALLOW_CFG0 \ + 0x00000C8C + +#define GPRCM_O_COEX_CLK_SWALLOW_CFG1 \ + 0x00000C90 + +#define GPRCM_O_COEX_CLK_SWALLOW_CFG2 \ + 0x00000C94 + +#define GPRCM_O_COEX_CLK_SWALLOW_ENABLE \ + 0x00000C98 + +#define GPRCM_O_DCDC_CLK_GEN_CONFIG \ + 0x00000C9C + +#define GPRCM_O_GPRCM_EFUSE_READ_REG4 \ + 0x00000CA0 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG5 \ + 0x00000CA4 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG6 \ + 0x00000CA8 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG7 \ + 0x00000CAC + +#define GPRCM_O_GPRCM_EFUSE_READ_REG8 \ + 0x00000CB0 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG9 \ + 0x00000CB4 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG10 \ + 0x00000CB8 + +#define GPRCM_O_GPRCM_EFUSE_READ_REG11 \ + 0x00000CBC + +#define GPRCM_O_GPRCM_DIEID_READ_REG0 \ + 0x00000CC0 + +#define GPRCM_O_GPRCM_DIEID_READ_REG1 \ + 0x00000CC4 + +#define GPRCM_O_GPRCM_DIEID_READ_REG2 \ + 0x00000CC8 + +#define GPRCM_O_GPRCM_DIEID_READ_REG3 \ + 0x00000CCC + +#define GPRCM_O_GPRCM_DIEID_READ_REG4 \ + 0x00000CD0 + +#define GPRCM_O_APPS_SS_OVERRIDES \ + 0x00000CD4 + +#define GPRCM_O_NWP_SS_OVERRIDES \ + 0x00000CD8 + +#define GPRCM_O_SHARED_SS_OVERRIDES \ + 0x00000CDC + +#define GPRCM_O_IDMEM_CORE_RST_OVERRIDES \ + 0x00000CE0 + +#define GPRCM_O_TOP_DIE_FSM_OVERRIDES \ + 0x00000CE4 + +#define GPRCM_O_MCU_PSCON_OVERRIDES \ + 0x00000CE8 + +#define GPRCM_O_WTOP_PSCON_OVERRIDES \ + 0x00000CEC + +#define GPRCM_O_WELP_PSCON_OVERRIDES \ + 0x00000CF0 + +#define GPRCM_O_WL_SDIO_PSCON_OVERRIDES \ + 0x00000CF4 + +#define GPRCM_O_MCSPI_PSCON_OVERRIDES \ + 0x00000CF8 + +#define GPRCM_O_SSDIO_PSCON_OVERRIDES \ + 0x00000CFC + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_SOFT_RESET register. +// +//****************************************************************************** +#define GPRCM_APPS_SOFT_RESET_APPS_SOFT_RESET1 \ + 0x00000002 // Soft-reset1 for APPS : Cortex + // sysrstn is asserted and in + // addition to that the associated + // APPS Peripherals are also reset. + // This is an auto-clear bit. + +#define GPRCM_APPS_SOFT_RESET_APPS_SOFT_RESET0 \ + 0x00000001 // Soft-reset0 for APPS : Only + // sys-resetn for Cortex will be + // asserted. This is an auto-clear + // bit. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_LPDS_WAKEUP_CFG register. +// +//****************************************************************************** +#define GPRCM_APPS_LPDS_WAKEUP_CFG_APPS_LPDS_WAKEUP_CFG_M \ + 0x000000FF // Mask for LPDS Wakeup interrupt : + // [7] - Host IRQ from NWP [6] - + // NWP_LPDS_Wake_irq (TRUE_LPDS) [5] + // - NWP Wake-request to APPS [4] - + // GPIO [3:1] - Reserved [0] - LPDS + // Wakeup-timer + +#define GPRCM_APPS_LPDS_WAKEUP_CFG_APPS_LPDS_WAKEUP_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_LPDS_WAKEUP_SRC register. +// +//****************************************************************************** +#define GPRCM_APPS_LPDS_WAKEUP_SRC_APPS_LPDS_WAKEUP_SRC_M \ + 0x000000FF // Indicates the cause for wakeup + // from LPDS : [7] - Host IRQ from + // NWP [6] - NWP_LPDS_Wake_irq + // (TRUE_LPDS) [5] - NWP + // Wake-request to APPS [4] - GPIO + // [3:1] - Reserved [0] - LPDS + // Wakeup-timer + +#define GPRCM_APPS_LPDS_WAKEUP_SRC_APPS_LPDS_WAKEUP_SRC_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_RESET_CAUSE register. +// +//****************************************************************************** +#define GPRCM_APPS_RESET_CAUSE_APPS_RESET_CAUSE_M \ + 0x000000FF // Indicates the reset cause for + // APPS : "0000" - Wake from HIB/OFF + // mode; "0001" - Wake from LPDS ; + // "0010" - Reserved ; "0011" - + // Soft-reset0 (Only APPS + // Cortex-sysrstn is asserted); + // "0100" - Soft-reset1 (APPS + // Cortex-sysrstn and APPS + // peripherals are reset); "0101" - + // WDOG0 (APPS Cortex-sysrstn and + // APPS peripherals are reset); + // "0110" - MCU Soft-reset (APPS + + // NWP Cortex-sysrstn + Peripherals + // are reset); "0111" - Secure Init + // done (Indication that reset has + // happened after DevInit); "1000" - + // Dev Mode Patch Init done (During + // development mode, patch + // downloading and Cortex + // re-vectoring is completed) + +#define GPRCM_APPS_RESET_CAUSE_APPS_RESET_CAUSE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG register. +// +//****************************************************************************** +#define GPRCM_APPS_LPDS_WAKETIME_OPP_CFG_APPS_LPDS_WAKETIME_OPP_CFG_M \ + 0xFFFFFFFF // OPP Request Configuration + // (Number of slow-clk cycles) for + // LPDS Wake-timer : This + // configuration implies the RTC + // time-stamp, which must be few + // slow-clks prior to + // APPS_LPDS_WAKETIME_WAKE_CFG, such + // that by the time actual wakeup is + // given, OPP is already switched to + // ACTIVE (RUN). + +#define GPRCM_APPS_LPDS_WAKETIME_OPP_CFG_APPS_LPDS_WAKETIME_OPP_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_SRAM_DSLP_CFG register. +// +//****************************************************************************** +#define GPRCM_APPS_SRAM_DSLP_CFG_APPS_SRAM_DSLP_CFG_M \ + 0x000FFFFF // Configuration of APPS Memories + // during Deep-sleep : 0 - SRAMs are + // OFF ; 1 - SRAMs are Retained. + // APPS SRAM Cluster information : + // [0] - 1st column in MEMSS + // (Applicable only when owned by + // APPS); [1] - 2nd column in MEMSS + // (Applicable only when owned by + // APPS); [2] - 3rd column in MEMSS + // (Applicable only when owned by + // APPS) ; [3] - 4th column in MEMSS + // (Applicable only when owned by + // APPS) ; [16] - MCU-PD - Apps + // cluster 0 (TBD); [19:18] - + // Reserved. + +#define GPRCM_APPS_SRAM_DSLP_CFG_APPS_SRAM_DSLP_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_SRAM_LPDS_CFG register. +// +//****************************************************************************** +#define GPRCM_APPS_SRAM_LPDS_CFG_APPS_SRAM_LPDS_CFG_M \ + 0x000FFFFF // Configuration of APPS Memories + // during LPDS : 0 - SRAMs are OFF ; + // 1 - SRAMs are Retained. APPS SRAM + // Cluster information : [0] - 1st + // column in MEMSS (Applicable only + // when owned by APPS); [1] - 2nd + // column in MEMSS (Applicable only + // when owned by APPS); [2] - 3rd + // column in MEMSS (Applicable only + // when owned by APPS) ; [3] - 4th + // column in MEMSS (Applicable only + // when owned by APPS) ; [16] - + // MCU-PD - Apps cluster 0 (TBD); + // [19:18] - Reserved. + +#define GPRCM_APPS_SRAM_LPDS_CFG_APPS_SRAM_LPDS_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG register. +// +//****************************************************************************** +#define GPRCM_APPS_LPDS_WAKETIME_WAKE_CFG_APPS_LPDS_WAKETIME_WAKE_CFG_M \ + 0xFFFFFFFF // Configuration (in no of + // slow_clks) which says when the + // actual wakeup request for + // removing the PD-reset be given. + +#define GPRCM_APPS_LPDS_WAKETIME_WAKE_CFG_APPS_LPDS_WAKETIME_WAKE_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_TOP_DIE_ENABLE register. +// +//****************************************************************************** +#define GPRCM_TOP_DIE_ENABLE_FLASH_BUSY \ + 0x00001000 + +#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_PWR_PS_M \ + 0x00000F00 + +#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_PWR_PS_S 8 +#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_ENABLE_STATUS \ + 0x00000002 // 1 - Top-die is enabled ; + +#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_ENABLE \ + 0x00000001 // 1 - Enable the top-die ; 0 - + // Disable the top-die + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_TOP_DIE_ENABLE_PARAMETERS register. +// +//****************************************************************************** +#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_FLASH_3P3_RSTN2D2D_POR_RSTN_M \ + 0xF0000000 // Configuration (in slow_clks) for + // number of clks between + // Flash-3p3-rstn to D2D POR Resetn. + +#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_FLASH_3P3_RSTN2D2D_POR_RSTN_S 28 +#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_SW_EN2TOP_DIE_FLASH_3P3_RSTN_M \ + 0x00FF0000 // Configuration (in slow_clks) for + // number of clks between Top-die + // Switch-Enable and Top-die Flash + // 3p3 Reset removal + +#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_SW_EN2TOP_DIE_FLASH_3P3_RSTN_S 16 +#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_POR_RSTN2BOTT_DIE_FMC_RSTN_M \ + 0x000000FF // Configuration (in slow_clks) for + // number of clks between D2D POR + // Reset removal and bottom die FMC + // reset removal + +#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_POR_RSTN2BOTT_DIE_FMC_RSTN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCU_GLOBAL_SOFT_RESET register. +// +//****************************************************************************** +#define GPRCM_MCU_GLOBAL_SOFT_RESET_MCU_GLOBAL_SOFT_RESET \ + 0x00000001 // 1 - Assert the global reset for + // MCU (APPS + NWP) ; Asserts both + // Cortex sysrstn and its + // peripherals 0 - Deassert the + // global reset for MCU (APPS + NWP) + // ; Asserts both Cortex sysrstn and + // its peripherals Note : Reset for + // shared peripherals is not + // affected here. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_ADC_CLK_CONFIG register. +// +//****************************************************************************** +#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_OFF_TIME_M \ + 0x000007C0 // Configuration (in number of 38.4 + // MHz clks) for the OFF-Time in + // generation of ADC_CLK + +#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_OFF_TIME_S 6 +#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_ON_TIME_M \ + 0x0000003E // Configuration (in number of 38.4 + // MHz clks) for the ON-Time in + // generation of ADC_CLK + +#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_ON_TIME_S 1 +#define GPRCM_ADC_CLK_CONFIG_ADC_CLK_ENABLE \ + 0x00000001 // 1 - Enable the ADC_CLK ; 0 - + // Disable the ADC_CLK + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_GPIO_WAKE_CONF register. +// +//****************************************************************************** +#define GPRCM_APPS_GPIO_WAKE_CONF_APPS_GPIO_WAKE_CONF_M \ + 0x00000003 // "00" - Wake on Level0 on + // selected GPIO pin (GPIO is + // selected inside the HIB3p3 + // module); "01" - Wakeup on + // fall-edge of GPIO pin. + +#define GPRCM_APPS_GPIO_WAKE_CONF_APPS_GPIO_WAKE_CONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_EN_NWP_BOOT_WO_DEVINIT register. +// +//****************************************************************************** +#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_reserved_M \ + 0xFFFFFFFE + +#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_reserved_S 1 +#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_mem_en_nwp_boot_wo_devinit \ + 0x00000001 // 1 - Override the secure-mode + // done for booting up NWP (Wakeup + // NWP on its event independent of + // CM4 state) ; 0 - Donot override + // the secure-mode done for NWP boot + // (NWP must be enabled by CM4 only) + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_HCLK_DIV_CFG register. +// +//****************************************************************************** +#define GPRCM_MEM_HCLK_DIV_CFG_mem_hclk_div_cfg_M \ + 0x00000007 // Division configuration for + // HCLKDIVOUT : "000" - Divide by 1 + // ; "001" - Divide by 2 ; "010" - + // Divide by 3 ; "011" - Divide by 4 + // ; "100" - Divide by 5 ; "101" - + // Divide by 6 ; "110" - Divide by 7 + // ; "111" - Divide by 8 + +#define GPRCM_MEM_HCLK_DIV_CFG_mem_hclk_div_cfg_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_SYSCLK_DIV_CFG register. +// +//****************************************************************************** +#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_off_time_M \ + 0x00000038 + +#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_off_time_S 3 +#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_on_time_M \ + 0x00000007 + +#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_on_time_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_LOCK_TIME_CONF register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_wlan_lock_time_M \ + 0x0000FF00 + +#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_wlan_lock_time_S 8 +#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_mcu_lock_time_M \ + 0x000000FF + +#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_mcu_lock_time_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_SOFT_RESET register. +// +//****************************************************************************** +#define GPRCM_NWP_SOFT_RESET_NWP_SOFT_RESET1 \ + 0x00000002 // Soft-reset1 for NWP - Cortex + // sysrstn and NWP associated + // peripherals are - This is an + // auto-clr bit. + +#define GPRCM_NWP_SOFT_RESET_NWP_SOFT_RESET0 \ + 0x00000001 // Soft-reset0 for NWP - Only + // Cortex-sysrstn is asserted - This + // is an auto-clear bit. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_LPDS_WAKEUP_CFG register. +// +//****************************************************************************** +#define GPRCM_NWP_LPDS_WAKEUP_CFG_NWP_LPDS_WAKEUP_CFG_M \ + 0x000000FF // Mask for LPDS Wakeup interrupt : + // 7 - WLAN Host Interrupt ; 6 - + // WLAN to NWP Wake request ; 5 - + // APPS to NWP Wake request; 4 - + // GPIO Wakeup ; 3 - Autonomous UART + // Wakeup ; 2 - SSDIO Wakeup ; 1 - + // Autonomous SPI Wakeup ; 0 - LPDS + // Wakeup-timer + +#define GPRCM_NWP_LPDS_WAKEUP_CFG_NWP_LPDS_WAKEUP_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_LPDS_WAKEUP_SRC register. +// +//****************************************************************************** +#define GPRCM_NWP_LPDS_WAKEUP_SRC_NWP_LPDS_WAKEUP_SRC_M \ + 0x000000FF // Indicates the cause for NWP + // LPDS-Wakeup : 7 - WLAN Host + // Interrupt ; 6 - WLAN to NWP Wake + // request ; 5 - APPS to NWP Wake + // request; 4 - GPIO Wakeup ; 3 - + // Autonomous UART Wakeup ; 2 - + // SSDIO Wakeup ; 1 - Autonomous SPI + // Wakeup ; 0 - LPDS Wakeup-timer + +#define GPRCM_NWP_LPDS_WAKEUP_SRC_NWP_LPDS_WAKEUP_SRC_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_RESET_CAUSE register. +// +//****************************************************************************** +#define GPRCM_NWP_RESET_CAUSE_NWP_RESET_CAUSE_M \ + 0x000000FF // Indicates the reset cause for + // NWP : "0000" - Wake from HIB/OFF + // mode; "0001" - Wake from LPDS ; + // "0010" - Reserved ; "0011" - + // Soft-reset0 (Only NWP + // Cortex-sysrstn is asserted); + // "0100" - Soft-reset1 (NWP + // Cortex-sysrstn and NWP + // peripherals are reset); "0101" - + // WDOG0 (NWP Cortex-sysrstn and NWP + // peripherals are reset); "0110" - + // MCU Soft-reset (APPS + NWP + // Cortex-sysrstn + Peripherals are + // reset); "0111" - SSDIO Function2 + // reset (Only Cortex-sysrstn is + // asserted) ; "1000" - Reset due to + // WDOG of APPS (NWP Cortex-sysrstn + // and NWP peripherals are reset); + +#define GPRCM_NWP_RESET_CAUSE_NWP_RESET_CAUSE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_LPDS_WAKETIME_OPP_CFG register. +// +//****************************************************************************** +#define GPRCM_NWP_LPDS_WAKETIME_OPP_CFG_NWP_LPDS_WAKETIME_OPP_CFG_M \ + 0xFFFFFFFF // OPP Request Configuration + // (Number of slow-clk cycles) for + // LPDS Wake-timer + +#define GPRCM_NWP_LPDS_WAKETIME_OPP_CFG_NWP_LPDS_WAKETIME_OPP_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_SRAM_DSLP_CFG register. +// +//****************************************************************************** +#define GPRCM_NWP_SRAM_DSLP_CFG_NWP_SRAM_DSLP_CFG_M \ + 0x000FFFFF // Configuration of NWP Memories + // during DSLP : 0 - SRAMs are OFF ; + // 1 - SRAMs are Retained. NWP SRAM + // Cluster information : [2] - 3rd + // column in MEMSS (Applicable only + // when owned by NWP) ; [3] - 4th + // column in MEMSS (Applicable only + // when owned by NWP) ; [4] - 5th + // column in MEMSS (Applicable only + // when owned by NWP) ; [5] - 6th + // column in MEMSS (Applicable only + // when owned by NWP) ; [6] - 7th + // column in MEMSS (Applicable only + // when owned by NWP) ; [7] - 8th + // column in MEMSS (Applicable only + // when owned by NWP) ; [8] - 9th + // column in MEMSS (Applicable only + // when owned by NWP) ; [9] - 10th + // column in MEMSS (Applicable only + // when owned by NWP) ; [10] - 11th + // column in MEMSS (Applicable only + // when owned by NWP) ; [11] - 12th + // column in MEMSS (Applicable only + // when owned by NWP) ; [12] - 13th + // column in MEMSS (Applicable only + // when owned by NWP) ; [13] - 14th + // column in MEMSS (Applicable only + // when owned by NWP) ; [14] - 15th + // column in MEMSS (Applicable only + // when owned by NWP) ; [19:18] - + // Reserved. + +#define GPRCM_NWP_SRAM_DSLP_CFG_NWP_SRAM_DSLP_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_SRAM_LPDS_CFG register. +// +//****************************************************************************** +#define GPRCM_NWP_SRAM_LPDS_CFG_NWP_SRAM_LPDS_CFG_M \ + 0x000FFFFF // Configuration of NWP Memories + // during LPDS : 0 - SRAMs are OFF ; + // 1 - SRAMs are Retained. NWP SRAM + // Cluster information : [2] - 3rd + // column in MEMSS (Applicable only + // when owned by NWP) ; [3] - 4th + // column in MEMSS (Applicable only + // when owned by NWP) ; [4] - 5th + // column in MEMSS (Applicable only + // when owned by NWP) ; [5] - 6th + // column in MEMSS (Applicable only + // when owned by NWP) ; [6] - 7th + // column in MEMSS (Applicable only + // when owned by NWP) ; [7] - 8th + // column in MEMSS (Applicable only + // when owned by NWP) ; [8] - 9th + // column in MEMSS (Applicable only + // when owned by NWP) ; [9] - 10th + // column in MEMSS (Applicable only + // when owned by NWP) ; [10] - 11th + // column in MEMSS (Applicable only + // when owned by NWP) ; [11] - 12th + // column in MEMSS (Applicable only + // when owned by NWP) ; [12] - 13th + // column in MEMSS (Applicable only + // when owned by NWP) ; [13] - 14th + // column in MEMSS (Applicable only + // when owned by NWP) ; [14] - 15th + // column in MEMSS (Applicable only + // when owned by NWP) ; [19:18] - + // Reserved. + +#define GPRCM_NWP_SRAM_LPDS_CFG_NWP_SRAM_LPDS_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_LPDS_WAKETIME_WAKE_CFG register. +// +//****************************************************************************** +#define GPRCM_NWP_LPDS_WAKETIME_WAKE_CFG_NWP_LPDS_WAKETIME_WAKE_CFG_M \ + 0xFFFFFFFF // Wake time configuration (no of + // slow clks) for NWP wake from + // LPDS. + +#define GPRCM_NWP_LPDS_WAKETIME_WAKE_CFG_NWP_LPDS_WAKETIME_WAKE_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_AUTONMS_SPI_MASTER_SEL register. +// +//****************************************************************************** +#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_F_M \ + 0xFFFE0000 + +#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_F_S 17 +#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_MEM_AUTONMS_SPI_MASTER_SEL \ + 0x00010000 // 0 - APPS is selected as host for + // Autonms SPI ; 1 - External host + // is selected as host for Autonms + // SPI + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_AUTONMS_SPI_IDLE_REQ register. +// +//****************************************************************************** +#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_WAKEUP \ + 0x00010000 + +#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_ACK \ + 0x00000002 // When 1 => IDLE-mode is + // acknowledged by the SPI-IP. (This + // is for MCSPI_N1) + +#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_REQ \ + 0x00000001 // When 1 => Request for IDLE-mode + // for autonomous SPI. (This is for + // MCSPI_N1) + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WLAN_TO_NWP_WAKE_REQUEST register. +// +//****************************************************************************** +#define GPRCM_WLAN_TO_NWP_WAKE_REQUEST_WLAN_TO_NWP_WAKE_REQUEST \ + 0x00000001 // 1 - Request for waking up NWP + // from any of its low-power modes + // (SLP/DSLP/LPDS) + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_TO_WLAN_WAKE_REQUEST register. +// +//****************************************************************************** +#define GPRCM_NWP_TO_WLAN_WAKE_REQUEST_NWP_TO_WLAN_WAKE_REQUEST \ + 0x00000001 // 1 - Request for wakinp up WLAN + // from its ELP Mode (This gets + // triggered to ELP-logic of WLAN) + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_GPIO_WAKE_CONF register. +// +//****************************************************************************** +#define GPRCM_NWP_GPIO_WAKE_CONF_NWP_GPIO_WAKE_CONF_M \ + 0x00000003 // "00" - Wakeup on level0 of the + // selected GPIO (GPIO gets selected + // inside HIB3P3-module); "01" - + // Wakeup on fall-edge of selected + // GPIO. + +#define GPRCM_NWP_GPIO_WAKE_CONF_NWP_GPIO_WAKE_CONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG12 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG12_FUSEFARM_ROW_32_MSW_M \ + 0x0000FFFF // This corrsponds to ROW_32 + // [31:16] of the FUSEFARM. SPARE + +#define GPRCM_GPRCM_EFUSE_READ_REG12_FUSEFARM_ROW_32_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG5 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG5_FUSEFARM_ROW_10_M \ + 0xFFFFFFFF // Corresponds to ROW10 of FUSEFARM + // : [5:0] - ADC OFFSET ; [13:6] - + // TEMP_SENSE ; [14:14] - DFT_GSG ; + // [15:15] - FMC_DISABLE ; [31:16] - + // WLAN_MAC ID + +#define GPRCM_GPRCM_DIEID_READ_REG5_FUSEFARM_ROW_10_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG6 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG6_FUSEFARM_ROW_11_M \ + 0xFFFFFFFF // Corresponds to ROW11 of FUSEFARM + // : [31:0] : WLAN MAC ID + +#define GPRCM_GPRCM_DIEID_READ_REG6_FUSEFARM_ROW_11_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_FSM_CFG0 register. +// +//****************************************************************************** +#define GPRCM_REF_FSM_CFG0_BGAP_SETTLING_TIME_M \ + 0x00FF0000 // ANA-BGAP Settling time (In + // number of slow_clks) + +#define GPRCM_REF_FSM_CFG0_BGAP_SETTLING_TIME_S 16 +#define GPRCM_REF_FSM_CFG0_FREF_LDO_SETTLING_TIME_M \ + 0x0000FF00 // Slicer LDO settling time (In + // number of slow clks) + +#define GPRCM_REF_FSM_CFG0_FREF_LDO_SETTLING_TIME_S 8 +#define GPRCM_REF_FSM_CFG0_DIG_BUF_SETTLING_TIME_M \ + 0x000000FF // Dig-buffer settling time (In + // number of slow clks) + +#define GPRCM_REF_FSM_CFG0_DIG_BUF_SETTLING_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_FSM_CFG1 register. +// +//****************************************************************************** +#define GPRCM_REF_FSM_CFG1_XTAL_SETTLING_TIME_M \ + 0xFF000000 // XTAL settling time (In number of + // slow clks) + +#define GPRCM_REF_FSM_CFG1_XTAL_SETTLING_TIME_S 24 +#define GPRCM_REF_FSM_CFG1_SLICER_LV_SETTLING_TIME_M \ + 0x00FF0000 // LV Slicer settling time + +#define GPRCM_REF_FSM_CFG1_SLICER_LV_SETTLING_TIME_S 16 +#define GPRCM_REF_FSM_CFG1_SLICER_HV_PD_SETTLING_TIME_M \ + 0x0000FF00 // HV Slicer Pull-down settling + // time + +#define GPRCM_REF_FSM_CFG1_SLICER_HV_PD_SETTLING_TIME_S 8 +#define GPRCM_REF_FSM_CFG1_SLICER_HV_SETTLING_TIME_M \ + 0x000000FF // HV Slicer settling time + +#define GPRCM_REF_FSM_CFG1_SLICER_HV_SETTLING_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_WLAN_CONFIG0_40 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_N_40_M \ + 0x00007F00 // Configuration for WLAN APLLMCS - + // N[6:0], if the XTAL frequency is + // 40 MHz (Selected by efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_N_40_S 8 +#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_M_40_M \ + 0x000000FF // Configuration for WLAN APLLMCS - + // M[7:0], if the XTAL frequency is + // 40 MHz (Selected by efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_M_40_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_WLAN_CONFIG1_40 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_HISPEED_40 \ + 0x00000010 // Configuration for WLAN APLLMCS - + // if the XTAL frequency if 40 MHz + // (Selected by Efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SEL96_40 \ + 0x00000008 // Configuration for WLAN APLLMCS - + // Sel96, if the XTAL frequency is + // 40 MHz (Selected by Efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SELINPFREQ_40_M \ + 0x00000007 // Configuration for WLAN APLLMCS - + // Selinpfreq, if the XTAL frequency + // is 40 MHz (Selected by Efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SELINPFREQ_40_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_WLAN_CONFIG0_26 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_N_26_M \ + 0x00007F00 // Configuration for WLAN APLLMCS - + // N[6:0], if the XTAL frequency is + // 26 MHz (Selected by efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_N_26_S 8 +#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_M_26_M \ + 0x000000FF // Configuration for WLAN APLLMCS - + // M[7:0], if the XTAL frequency is + // 26 MHz (Selected by efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_M_26_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_WLAN_CONFIG1_26 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_HISPEED_26 \ + 0x00000010 // Configuration for WLAN APLLMCS - + // if the XTAL frequency if 26 MHz + // (Selected by Efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SEL96_26 \ + 0x00000008 // Configuration for WLAN APLLMCS - + // Sel96, if the XTAL frequency is + // 26 MHz (Selected by Efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SELINPFREQ_26_M \ + 0x00000007 // Configuration for WLAN APLLMCS - + // Selinpfreq, if the XTAL frequency + // is 26 MHz (Selected by Efuse) + +#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SELINPFREQ_26_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_WLAN_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_CTRL \ + 0x00080000 + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_M \ + 0x00070000 + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_S 16 +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_SPARE_M \ + 0x00000700 + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_SPARE_S 8 +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_M_8_OVERRIDE_CTRL \ + 0x00000020 // Override control for + // WLAN_APLLMCS_M[8]. When set to1, + // M[8] will be selected by bit [3]. + // (Else controlled from WTOP) + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_M_8_OVERRIDE \ + 0x00000010 // Override for WLAN_APLLMCS_M[8]. + // Applicable only when bit [4] is + // set to 1. (Else controlled from + // WTOP) + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_CTRL \ + 0x00000004 // Override control for + // WLAN_APLLMCS_N[8:7]. When set + // to1, N[8:7] will be selected by + // bits [2:1]. (Else controlled from + // WTOP) + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_M \ + 0x00000003 // Override value for + // WLAN_APLLMCS_N[8:7] bits. + // Applicable only when bit [1] is + // set to 1. (Else controlled from + // WTOP) + +#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_38P4 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_POSTDIV_M \ + 0x38000000 + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_POSTDIV_S 27 +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_SPARE_M \ + 0x07000000 + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_SPARE_S 24 +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_38P4_M \ + 0x007F0000 // Configuration for MCU-APLLMCS : + // N during RUN mode. Selected if + // the XTAL frequency is 38.4 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_38P4_S 16 +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_38P4_M \ + 0x0000FF00 // Configuration for MCU-APLLMCS : + // M during RUN mode. Selected if + // the XTAL frequency is 38.4 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_38P4_S 8 +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_8_38P4 \ + 0x00000010 // Configuration for MCU-APLLMCS : + // M[8] during RUN mode. Selected if + // the XTAL frequency is 38.4 MHz + // (From Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_7_8_38P4_M \ + 0x00000003 // Configuration for MCU-APLLMCS : + // N[8:7] during RUN mode. Selected + // if the XTAL frequency is 38.4 MHz + // (From Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_7_8_38P4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_38P4 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_HISPEED_38P4 \ + 0x00000010 // Configuration for MCU-APLLMCS : + // HISPEED during RUN mode. Selected + // if the XTAL frequency is 38.4 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SEL96_38P4 \ + 0x00000008 // Configuration for MCU-APLLMCS : + // SEL96 during RUN mode. Selected + // if the XTAL frequency is 38.4 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SELINPFREQ_38P4_M \ + 0x00000007 // Configuration for MCU-APLLMCS : + // SELINPFREQ during RUN mode. + // Selected if the XTAL frequency is + // 38.4 MHz (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SELINPFREQ_38P4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_26 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_26_M \ + 0x007F0000 // Configuration for MCU-APLLMCS : + // N during RUN mode. Selected if + // the XTAL frequency is 26 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_26_S 16 +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_26_M \ + 0x0000FF00 // Configuration for MCU-APLLMCS : + // M during RUN mode. Selected if + // the XTAL frequency is 26 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_26_S 8 +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_8_26 \ + 0x00000010 // Configuration for MCU-APLLMCS : + // M[8] during RUN mode. Selected if + // the XTAL frequency is 26 MHz + // (From Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_7_8_26_M \ + 0x00000003 // Configuration for MCU-APLLMCS : + // N[8:7] during RUN mode. Selected + // if the XTAL frequency is 26 MHz + // (From Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_7_8_26_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_26 register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_HISPEED_26 \ + 0x00000010 // Configuration for MCU-APLLMCS : + // HISPEED during RUN mode. Selected + // if the XTAL frequency is 26 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SEL96_26 \ + 0x00000008 // Configuration for MCU-APLLMCS : + // SEL96 during RUN mode. Selected + // if the XTAL frequency is 26 MHz + // (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SELINPFREQ_26_M \ + 0x00000007 // Configuration for MCU-APLLMCS : + // SELINPFREQ during RUN mode. + // Selected if the XTAL frequency is + // 26 MHz (from Efuse) + +#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SELINPFREQ_26_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the GPRCM_O_SPARE_RW0 register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the GPRCM_O_SPARE_RW1 register. +// +//****************************************************************************** +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APLLMCS_MCU_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_LOCK \ + 0x00000400 // 1 - APLLMCS_MCU is locked ; 0 - + // APLLMCS_MCU is not locked + +#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_ENABLE_OVERRIDE \ + 0x00000200 // Override for APLLMCS_MCU Enable. + // Applicable if bit [8] is set + +#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_ENABLE_OVERRIDE_CTRL \ + 0x00000100 // 1 - Enable for APLLMCS_MCU comes + // from bit [9]. 0 - Enable for + // APLLMCS_MCU comes from FSM. + +#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_M \ + 0x00000006 // Override for sysclk src + // (applicable only if bit [0] is + // set to 1. "00"- SLOW_CLK "01"- + // XTAL_CLK "10"- PLL_CLK + +#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_S 1 +#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_CTRL \ + 0x00000001 // 1 - Sysclk src is selected from + // bits [2:1] of this register. 0 - + // Sysclk src is selected from FSM + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_SYSCLK_SWITCH_STATUS register. +// +//****************************************************************************** +#define GPRCM_SYSCLK_SWITCH_STATUS_SYSCLK_SWITCH_STATUS \ + 0x00000001 // 1 - Sysclk switching is + // complete. 0 - Sysclk switching is + // in progress. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_LDO_CONTROLS register. +// +//****************************************************************************** +#define GPRCM_REF_LDO_CONTROLS_REF_LDO_ENABLE_OVERRIDE_CTRL \ + 0x00010000 // 1 - Enable for REF_LDO comes + // from bit [0] of this register ; 0 + // - Enable for REF_LDO comes from + // the FSM. Note : Final REF_LDO_EN + // reaches on the port + // TOP_PM_REG2[0] of gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_SPARE_CONTROL_M \ + 0x0000C000 // Spare bits for REF_CTRL_FSM. + // Reaches directly on port + // TOP_PM_REG2[15:14] of gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_SPARE_CONTROL_S 14 +#define GPRCM_REF_LDO_CONTROLS_REF_TLOAD_ENABLE_M \ + 0x00003800 // REF TLOAD Enable. Reaches + // directly on port + // TOP_PM_REG2[13:11] of gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_TLOAD_ENABLE_S 11 +#define GPRCM_REF_LDO_CONTROLS_REF_LDO_TMUX_CONTROL_M \ + 0x00000700 // REF_LDO Test-mux control. + // Reaches directly on port + // TOP_PM_REG2[10:8] of gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_LDO_TMUX_CONTROL_S 8 +#define GPRCM_REF_LDO_CONTROLS_REF_BW_CONTROL_M \ + 0x000000C0 // REF BW Control. Reaches directly + // on port TOP_PM_REG2[7:6] of + // gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_BW_CONTROL_S 6 +#define GPRCM_REF_LDO_CONTROLS_REF_VTRIM_CONTROL_M \ + 0x0000003C // REF VTRIM Control. Reaches + // directly on port TOP_PM_REG2[5:2] + // of gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_VTRIM_CONTROL_S 2 +#define GPRCM_REF_LDO_CONTROLS_REF_LDO_BYPASS_ENABLE \ + 0x00000002 // REF LDO Bypass Enable. Reaches + // directly on port TOP_PM_REG2[1] + // of gprcm. + +#define GPRCM_REF_LDO_CONTROLS_REF_LDO_ENABLE \ + 0x00000001 // Override for REF_LDO Enable. + // Applicable only if bit [16] of + // this register is set. Note : + // Final REF_LDO_EN reaches on the + // port TOP_PM_REG2[0] of gprcm. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_RTRIM_CONTROL register. +// +//****************************************************************************** +#define GPRCM_REF_RTRIM_CONTROL_TOP_PM_REG0_5_4_M \ + 0x18000000 // This is [5:4] bits of + // TOP_PM_REG0 + +#define GPRCM_REF_RTRIM_CONTROL_TOP_PM_REG0_5_4_S 27 +#define GPRCM_REF_RTRIM_CONTROL_TOP_CLKM_REG0_15_5_M \ + 0x07FF0000 // This is [15:5] bits of + // TOP_CLKM_REG0 + +#define GPRCM_REF_RTRIM_CONTROL_TOP_CLKM_REG0_15_5_S 16 +#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_OVERRIDE_CTRL \ + 0x00000100 // 1 - CLKM_RTRIM comes for + // bits[4:0] of this register. 0 - + // CLKM_RTRIM comes from Efuse + // (after efuse_done = 1). + +#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_M \ + 0x0000001F // CLKM_TRIM Override. Applicable + // when efuse_done = 0 or bit[8] is + // set to 1. + +#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_SLICER_CONTROLS0 register. +// +//****************************************************************************** +#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_WLAN_LOWV_OVERRIDE_CTRL \ + 0x00200000 // 1 - EN_DIG_BUF_TOP comes from + // bit [14] of this register. 0 - + // EN_DIG_BUF_TOP comes from the + // FSM. Note : Final EN_DIG_BUF_WLAN + // reaches on TOP_CLKM_REG1_IN[14] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_TOP_LOWV_OVERRIDE_CTRL \ + 0x00100000 // 1 - EN_DIG_BUF_TOP comes from + // bit [15] of this register. 0 - + // EN_DIG_BUF_TOP comes from the + // FSM. Note : Final EN_DIG_BUF_TOP + // reaches on TOP_CLKM_REG1_IN[15] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_EN_XTAL_OVERRIDE_CTRL \ + 0x00080000 // 1 - EN_XTAL comes from bit [3] + // of this register. 0 - EN_XTAL + // comes from FSM. Note : Final + // XTAL_EN reaches on + // TOP_CLKM_REG1_IN[3] of gprcm. + +#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_HV_OVERRIDE_CTRL \ + 0x00040000 // 1 - Enable HV Slicer comes from + // bit [2] of this register. 0 - + // Enable HV Slicer comes from FSM. + // Note : Final HV_SLICER_EN reaches + // on port TOP_CLKM_REG1_IN[1] of + // gprcm. + +#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_LV_OVERRIDE_CTRL \ + 0x00020000 // 1 - Enable LV Slicer comes from + // bit[1] of this register. 0 - + // Enable LV Slicer comes from FSM. + // Note : final LV_SLICER_EN reaches + // on port TOP_CLKM_REG1_IN[2] of + // gprcm. + +#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_HV_PDN_OVERRIDE_CTRL \ + 0x00010000 // 1 - Enable HV Pull-down comes + // from bit[0] of this register. 0 - + // Enable HV Pull-down comes from + // FSM. Note : Final HV_PULL_DOWN + // reaches on port + // TOP_CLKM_REG1_IN[0] of gprcm. + +#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_TOP_LOWV \ + 0x00008000 // Override for EN_DIG_BUF_TOP. + // Applicable if bit[20] is set to + // 1. Note : Final EN_DIG_BUF_TOP + // reaches on TOP_CLKM_REG1_IN[15] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_WLAN_LOWV \ + 0x00004000 // Override for EN_DIG_BUF_WLAN. + // Applicable if bit[19] is set to + // 1. Note : Final EN_DIG_BUF_WLAN + // reaches on TOP_CLKM_REG1_IN[14] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_CLKOUT_FLIP_EN \ + 0x00002000 // CLKOUT Flip Enable. Reaches on + // bit[13] of TOP_CLKM_REG1_IN[13] + // port of gprcm. + +#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV2_WLAN_CLK \ + 0x00001000 // Enable divide2 in WLAN Clk-path. + // Reaches on TOP_CLKM_REG1_IN[12] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV3_WLAN_CLK \ + 0x00000800 // Enable divide3 in WLAN Clk-path. + // Reaches on TOP_CLKM_REG1_IN[11] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV4_WLAN_CLK \ + 0x00000400 // Enable divide4 in WLAN Clk-path. + // Reaches on TOP_CLKM_REG1_IN[10] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_CM_TMUX_SEL_LOWV_M \ + 0x000003C0 // CM Test-mux select. Reaches on + // TOP_CLMM_REG1_IN[9:6] port of + // gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_CM_TMUX_SEL_LOWV_S 6 +#define GPRCM_REF_SLICER_CONTROLS0_SLICER_SPARE0_M \ + 0x00000030 // Slicer spare0 control. Reaches + // on TOP_CLKM_REG1_IN[5:4] port of + // gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_SLICER_SPARE0_S 4 +#define GPRCM_REF_SLICER_CONTROLS0_EN_XTAL \ + 0x00000008 // Enable XTAL override. Reaches on + // TOP_CLKM_REG1_IN[3] port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_HV \ + 0x00000004 // Enable HV Slicer override. + // Reaches on TOP_CLKM_REG1_IN[1] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_LV \ + 0x00000002 // Enable LV Slicer override. + // Reaches on TOP_CLKM_REG1_IN[2] + // port of gprcm + +#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_HV_PDN \ + 0x00000001 // Enable HV Pull-down override. + // Reaches on TOP_CLKM_REG1_IN[0] + // port of gprcm + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_SLICER_CONTROLS1 register. +// +//****************************************************************************** +#define GPRCM_REF_SLICER_CONTROLS1_SLICER_SPARE1_M \ + 0x0000FC00 // Slicer spare1. Reaches on port + // TOP_CLKM_REG2_IN[15:10] of gprcm. + +#define GPRCM_REF_SLICER_CONTROLS1_SLICER_SPARE1_S 10 +#define GPRCM_REF_SLICER_CONTROLS1_XOSC_TRIM_M \ + 0x000003F0 // XOSC Trim. Reaches on port + // TOP_CLKM_REG2_IN[9:4] of gprcm + +#define GPRCM_REF_SLICER_CONTROLS1_XOSC_TRIM_S 4 +#define GPRCM_REF_SLICER_CONTROLS1_SLICER_ITRIM_CHANGE_TOGGLE \ + 0x00000008 // Slicer ITRIM Toggle. Reaches on + // port TOP_CLKM_REG2_IN[3] of + // gprcm. + +#define GPRCM_REF_SLICER_CONTROLS1_SLICER_LV_TRIM_M \ + 0x00000007 // LV Slicer trim. Reaches on port + // TOP_CLKM_REG2_IN[2:0] of gprcm. + +#define GPRCM_REF_SLICER_CONTROLS1_SLICER_LV_TRIM_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_ANA_BGAP_CONTROLS0 register. +// +//****************************************************************************** +#define GPRCM_REF_ANA_BGAP_CONTROLS0_reserved_M \ + 0xFF800000 + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_reserved_S 23 +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_mag_trim_override_ctrl \ + 0x00400000 // 1 - REF_MAG_TRIM comes from + // bit[4:0] of register + // REF_ANA_BGAP_CONTROLS1 [Addr : + // 0x0850]; 0 - REF_MAG_TRIM comes + // from efuse (After efc_done = 1). + // Note : Final REF_MAG_TRIM reaches + // on port TOP_PM_REG1[4:0] of gprcm + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_override_ctrl \ + 0x00200000 // 1 - REF_V2I_TRIM comes from + // bit[9:6] of this register ; 0 - + // REF_V2I_TRIM comes from efuse + // (After efc_done = 1). Note : + // Final REF_V2I_TRIM reaches on + // port TOP_PM_REG0[9:6] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_override_ctrl \ + 0x00100000 // 1 - REF_TEMP_TRIM comes from + // bit[15:10] of this register ; 0 - + // REF_TEMP_TRIM comes from efuse + // (After efc_done = 1). Note : + // Final REF_TEMP_TRIM reaches on + // port TOP_PM_REG0[15:10] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_startup_en_override_ctrl \ + 0x00080000 // 1 - REF_STARTUP_EN comes from + // bit [3] of this register ; 0 - + // REF_STARTUP_EN comes from FSM. + // Note : Final REF_STARTUP_EN + // reaches on port TOP_PM_REG0[3] of + // gprcm + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_en_override_ctrl \ + 0x00040000 // 1 - REF_V2I_EN comes from bit + // [2] of this register ; 0 - + // REF_V2I_EN comes from FSM. Note : + // Final REF_V2I_EN reaches on port + // TOP_PM_REG0[2] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_fc_en_override_ctrl \ + 0x00020000 // 1 - REF_FC_EN comes from bit [1] + // of this register ; 0 - REF_FC_EN + // comes from FSM. Note : Final + // REF_FC_EN reaches on port + // TOP_PM_REG0[1] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_bgap_en_override_ctrl \ + 0x00010000 // 1 - REF_BGAP_EN comes from bit + // [0] of this register ; 0 - + // REF_BGAP_EN comes from FSM. Note + // : Final REF_BGAP_EN reaches on + // port TOP_PM_REG0[0] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_M \ + 0x0000FC00 // REF_TEMP_TRIM override. + // Applicable when bit [20] of this + // register set to 1. (or efc_done = + // 0) Note : Final REF_TEMP_TRIM + // reaches on port + // TOP_PM_REG0[15:10] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_S 10 +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_M \ + 0x000003C0 // REF_V2I_TRIM Override. + // Applicable when bit [21] of this + // register set to 1 . (of efc_done + // = 0) Note : Final REF_V2I_TRIM + // reaches on port TOP_PM_REG0[9:6] + // of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_S 6 +#define GPRCM_REF_ANA_BGAP_CONTROLS0_NU1_M \ + 0x00000030 + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_NU1_S 4 +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_startup_en \ + 0x00000008 // REF_STARTUP_EN override. + // Applicable when bit [19] of this + // register is set to 1. Note : + // Final REF_STARTUP_EN reaches on + // port TOP_PM_REG0[3] of gprcm + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_en \ + 0x00000004 // REF_V2I_EN override. Applicable + // when bit [21] of this register is + // set to 1. Note : Final REF_V2I_EN + // reaches on port TOP_PM_REG0[2] of + // gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_fc_en \ + 0x00000002 // REF_FC_EN override. Applicable + // when bit [17] of this register is + // set to 1. Note : Final REF_FC_EN + // reaches on port TOP_PM_REG0[1] of + // gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_bgap_en \ + 0x00000001 // REF_BGAP_EN override. Applicable + // when bit [16] of this register + // set to 1. Note : Final + // REF_BGAP_EN reaches on port + // TOP_PM_REG0[0] of gprcm. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_ANA_BGAP_CONTROLS1 register. +// +//****************************************************************************** +#define GPRCM_REF_ANA_BGAP_CONTROLS1_reserved_M \ + 0xFFFF0000 + +#define GPRCM_REF_ANA_BGAP_CONTROLS1_reserved_S 16 +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bg_spare_M \ + 0x0000C000 // REF_BGAP_SPARE. Reaches on port + // TOP_PM_REG1[15:14] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bg_spare_S 14 +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bgap_tmux_ctrl_M \ + 0x00003E00 // REF_BGAP_TMUX_CTRL. Reaches on + // port TOP_PM_REG1[13:9] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bgap_tmux_ctrl_S 9 +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_filt_trim_M \ + 0x000001E0 // REF_FILT_TRIM. Reaches on port + // TOP_PM_REG1[8:5] of gprcm. + +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_filt_trim_S 5 +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_mag_trim_M \ + 0x0000001F // REF_MAG_TRIM Override. + // Applicable when bit[22] of + // REF_ANA_BGAP_CONTROLS0 [0x084C] + // set to 1 (of efc_done = 0). Note + // : Final REF_MAG_TRIM reaches on + // port TOP_PM_REG1[4:0] of gprcm + +#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_mag_trim_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_ANA_SPARE_CONTROLS0 register. +// +//****************************************************************************** +#define GPRCM_REF_ANA_SPARE_CONTROLS0_reserved_M \ + 0xFFFF0000 + +#define GPRCM_REF_ANA_SPARE_CONTROLS0_reserved_S 16 +#define GPRCM_REF_ANA_SPARE_CONTROLS0_mem_top_pm_reg3_M \ + 0x0000FFFF // Spare control. Reaches on + // TOP_PM_REG3 [15:0] of gprcm. + +#define GPRCM_REF_ANA_SPARE_CONTROLS0_mem_top_pm_reg3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_ANA_SPARE_CONTROLS1 register. +// +//****************************************************************************** +#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg3_M \ + 0xFFFF0000 // Spare control. Reaches on + // TOP_CLKM_REG3 [15:0] of gprcm. + +#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg3_S 16 +#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg4_M \ + 0x0000FFFF // Spare control. Reaches on + // TOP_CLKM_REG4 [15:0] of gprcm. + +#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEMSS_PSCON_OVERRIDES0 register. +// +//****************************************************************************** +#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_off_override_M \ + 0xFFFF0000 + +#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_off_override_S 16 +#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_retain_override_M \ + 0x0000FFFF + +#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_retain_override_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEMSS_PSCON_OVERRIDES1 register. +// +//****************************************************************************** +#define GPRCM_MEMSS_PSCON_OVERRIDES1_reserved_M \ + 0xFFFFFFC0 + +#define GPRCM_MEMSS_PSCON_OVERRIDES1_reserved_S 6 +#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_update_override_ctrl \ + 0x00000020 + +#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_update_override \ + 0x00000010 + +#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_sleep_override_ctrl \ + 0x00000008 + +#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_sleep_override \ + 0x00000004 + +#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_off_override_ctrl \ + 0x00000002 + +#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memms_pscon_mem_retain_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_PLL_REF_LOCK_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_PLL_REF_LOCK_OVERRIDES_reserved_M \ + 0xFFFFFFF8 + +#define GPRCM_PLL_REF_LOCK_OVERRIDES_reserved_S 3 +#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_mcu_apllmcs_lock_override \ + 0x00000004 + +#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_wlan_apllmcs_lock_override \ + 0x00000002 + +#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_ref_clk_valid_override \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCU_PSCON_DEBUG register. +// +//****************************************************************************** +#define GPRCM_MCU_PSCON_DEBUG_reserved_M \ + 0xFFFFFFC0 + +#define GPRCM_MCU_PSCON_DEBUG_reserved_S 6 +#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_rtc_ps_M \ + 0x00000038 // MCU_PSCON_RTC_ON = "0000"; + // MCU_PSCON_RTC_OFF = "0001"; + // MCU_PSCON_RTC_RET = "0010"; + // MCU_PSCON_RTC_OFF_TO_ON = "0011"; + // MCU_PSCON_RTC_RET_TO_ON = "0100"; + // MCU_PSCON_RTC_ON_TO_RET = "0101"; + // MCU_PSCON_RTC_ON_TO_OFF = "0110"; + // MCU_PSCON_RTC_RET_TO_ON_WAIT_OPP + // = "0111"; + // MCU_PSCON_RTC_OFF_TO_ON_WAIT_OPP + // = "1000"; + +#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_rtc_ps_S 3 +#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_sys_ps_M \ + 0x00000007 + +#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_sys_ps_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEMSS_PWR_PS register. +// +//****************************************************************************** +#define GPRCM_MEMSS_PWR_PS_reserved_M \ + 0xFFFFFFF8 + +#define GPRCM_MEMSS_PWR_PS_reserved_S 3 +#define GPRCM_MEMSS_PWR_PS_pwr_ps_memss_M \ + 0x00000007 // MEMSS_PM_SLEEP = "000"; + // MEMSS_PM_WAIT_OPP = "010"; + // MEMSS_PM_ACTIVE = "011"; + // MEMSS_PM_SLEEP_TO_ACTIVE = "100"; + // MEMSS_PM_ACTIVE_TO_SLEEP = "101"; + +#define GPRCM_MEMSS_PWR_PS_pwr_ps_memss_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_REF_FSM_DEBUG register. +// +//****************************************************************************** +#define GPRCM_REF_FSM_DEBUG_reserved_M \ + 0xFFFFFFC0 + +#define GPRCM_REF_FSM_DEBUG_reserved_S 6 +#define GPRCM_REF_FSM_DEBUG_fref_mode_M \ + 0x00000030 // 01 - HV Mode ; 10 - LV Mode ; 11 + // - XTAL Mode + +#define GPRCM_REF_FSM_DEBUG_fref_mode_S 4 +#define GPRCM_REF_FSM_DEBUG_ref_fsm_ps_M \ + 0x0000000F // constant FREF_CLK_OFF = "00000"; + // constant FREF_EN_BGAP = "00001"; + // constant FREF_EN_LDO = "00010"; + // constant FREF_EN_SLI_HV = + // "00011"; constant + // FREF_EN_SLI_HV_PD = "00100"; + // constant FREF_EN_DIG_BUF = + // "00101"; constant FREF_EN_OSC = + // "00110"; constant FREF_EN_SLI_LV + // = "00111"; constant + // FREF_EN_CLK_REQ = "01000"; + // constant FREF_CLK_VALID = + // "01001"; constant FREF_MODE_DET0 + // = "01010"; constant + // FREF_MODE_DET1 = "01011"; + // constant FREF_MODE_DET2 = + // "10010"; constant FREF_MODE_DET3 + // = "10011"; constant FREF_VALID = + // "01100"; constant FREF_VALID0 = + // "01101"; constant FREF_VALID1 = + // "01110"; constant FREF_VALID2 = + // "01111"; constant + // FREF_WAIT_EXT_TCXO0 = "10000"; + // constant FREF_WAIT_EXT_TCXO1 = + // "10001"; + +#define GPRCM_REF_FSM_DEBUG_ref_fsm_ps_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_SYS_OPP_REQ_OVERRIDE register. +// +//****************************************************************************** +#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_reserved_M \ + 0xFFFFFFE0 + +#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_reserved_S 5 +#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_ctrl \ + 0x00000010 // 1 - Override the sytem-opp + // request to ANATOP using bit0 of + // this register + +#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_M \ + 0x0000000F // "0001" - RUN ; "0010" - DSLP ; + // "0100" - LPDS ; Others - NA + +#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_TESTCTRL_PD_OPP_CONFIG register. +// +//****************************************************************************** +#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_reserved_M \ + 0xFFFFFFFE + +#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_reserved_S 1 +#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_mem_sleep_opp_enter_with_testpd_on \ + 0x00000001 // 1 - Enable sleep-opp (DSLP/LPDS) + // entry even if Test-Pd is kept ON + // ; 0 - Donot enable sleep-opp + // (DSLP/LPDS) entry with Test-Pd + // ON. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_WL_FAST_CLK_REQ_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_reserved_M \ + 0xFFFFFFF8 + +#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_reserved_S 3 +#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_fast_clk_req_override_ctrl \ + 0x00000004 // NA + +#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_fast_clk_req_override \ + 0x00000002 // NA + +#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_sleep_with_clk_req_override \ + 0x00000001 // NA + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_MCU_PD_MODE_REQ_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_mode_req_override_ctrl \ + 0x00000004 // 1 - Override the MCU-PD power + // modes using bits [1] & [0] ; + +#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_pwrdn_req_override \ + 0x00000002 // 1 - Request for power-down of + // MCU-PD ; + +#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_ret_req_override \ + 0x00000001 // 1 - Request for retention mode + // of MCU-PD. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES_mem_mcspi_sram_off_req_override_ctrl \ + 0x00000002 // 1- Override the MCSPI + // (Autonomous SPI) memory state + // using bit [0] + +#define GPRCM_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES_mem_mcspi_sram_off_req_override \ + 0x00000001 // 1 - Request for power-down of + // Autonomous SPI 8k memory ; 0 - + // Donot request power-down of + // Autonomous SPI 8k Memory + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_WLAN_APLLMCS_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_wlan_apllmcs_lock \ + 0x00000100 + +#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_mem_wlan_apllmcs_enable_override \ + 0x00000002 + +#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_mem_wlan_apllmcs_enable_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_REF_FSM_CFG2 register. +// +//****************************************************************************** +#define GPRCM_MEM_REF_FSM_CFG2_MEM_FC_DEASSERT_DELAY_M \ + 0x00380000 // Number of RTC clocks for keeping + // the FC_EN asserted high + +#define GPRCM_MEM_REF_FSM_CFG2_MEM_FC_DEASSERT_DELAY_S 19 +#define GPRCM_MEM_REF_FSM_CFG2_MEM_STARTUP_DEASSERT_DELAY_M \ + 0x00070000 // Number of RTC clocks for keeping + // the STARTUP_EN asserted high + +#define GPRCM_MEM_REF_FSM_CFG2_MEM_STARTUP_DEASSERT_DELAY_S 16 +#define GPRCM_MEM_REF_FSM_CFG2_MEM_EXT_TCXO_SETTLING_TIME_M \ + 0x0000FFFF // Number of RTC clocks for waiting + // for clock to settle. + +#define GPRCM_MEM_REF_FSM_CFG2_MEM_EXT_TCXO_SETTLING_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_TESTCTRL_POWER_CTRL register. +// +//****************************************************************************** +#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_STATUS_M \ + 0x00000006 + +#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_STATUS_S 1 +#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_ENABLE \ + 0x00000001 // 0 - Disable the TestCtrl-pd ; 1 + // - Enable the TestCtrl-pd. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_SSDIO_POWER_CTRL register. +// +//****************************************************************************** +#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_STATUS_M \ + 0x00000006 // 1 - SSDIO-PD is ON ; 0 - + // SSDIO-PD is OFF + +#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_STATUS_S 1 +#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_ENABLE \ + 0x00000001 // 0 - Disable the SSDIO-pd ; 1 - + // Enable the SSDIO-pd. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCSPI_N1_POWER_CTRL register. +// +//****************************************************************************** +#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_STATUS_M \ + 0x00000006 // 1 - MCSPI_N1-PD is ON ; 0 - + // MCSPI_N1-PD if OFF + +#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_STATUS_S 1 +#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_ENABLE \ + 0x00000001 // 0 - Disable the MCSPI_N1-pd ; 1 + // - Enable the MCSPI_N1-pd. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WELP_POWER_CTRL register. +// +//****************************************************************************** +#define GPRCM_WELP_POWER_CTRL_WTOP_PD_STATUS_M \ + 0x00001C00 + +#define GPRCM_WELP_POWER_CTRL_WTOP_PD_STATUS_S 10 +#define GPRCM_WELP_POWER_CTRL_WTOP_PD_REQ_OVERRIDE \ + 0x00000200 + +#define GPRCM_WELP_POWER_CTRL_WTOP_PD_REQ_OVERRIDE_CTRL \ + 0x00000100 + +#define GPRCM_WELP_POWER_CTRL_WELP_PD_STATUS_M \ + 0x00000006 + +#define GPRCM_WELP_POWER_CTRL_WELP_PD_STATUS_S 1 +#define GPRCM_WELP_POWER_CTRL_WELP_PD_ENABLE \ + 0x00000001 // 0 - Disable the WELP-pd ; 1 - + // Enable the WELP-pd. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WL_SDIO_POWER_CTRL register. +// +//****************************************************************************** +#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_STATUS_M \ + 0x00000006 + +#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_STATUS_S 1 +#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_ENABLE \ + 0x00000001 // 0 - Disable the WL_SDIO-pd ; 1 - + // Enable the WL_SDIO-pd. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WLAN_SRAM_ACTIVE_PWR_CFG register. +// +//****************************************************************************** +#define GPRCM_WLAN_SRAM_ACTIVE_PWR_CFG_WLAN_SRAM_ACTIVE_PWR_CFG_M \ + 0x00FFFFFF // SRAM (WTOP+DRP) state during + // Active-mode : 1 - SRAMs are ON ; + // 0 - SRAMs are OFF. Cluster + // information : [0] - 1st column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) [1] - 2nd column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) ; [2] - 3rd column + // of MEMSS (Applicable only when + // owned by WTOP/PHY) ; [3] - 4th + // column of MEMSS (Applicable only + // when owned by WTOP/PHY) ; [4] - + // 5th column of MEMSS (Applicable + // only when owned by WTOP/PHY) ; + // [5] - 6th column of MEMSS + // (Applicable only when owned by + // WTOP/PHY) ; [6] - 7th column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) ; [7] - 8th column + // of MEMSS (Applicable only when + // owned by WTOP/PHY) ; [8] - 9th + // column of MEMSS (Applicable only + // when owned by WTOP/PHY) ; [9] - + // 10th column of MEMSS (Applicable + // only when owned by WTOP/PHY) ; + // [10] - 11th column of MEMSS + // (Applicable only when owned by + // WTOP/PHY) ; [11] - 12th column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) ; [12] - 13th column + // of MEMSS (Applicable only when + // owned by WTOP/PHY) ; [13] - 14th + // column of MEMSS (Applicable only + // when owned by WTOP/PHY) ; [14] - + // 15th column of MEMSS (Applicable + // only when owned by WTOP/PHY) ; + // [15] - 16th column of MEMSS + // (Applicable only when owned by + // WTOP/PHY) ; [23:16] - Internal to + // WTOP Cluster + +#define GPRCM_WLAN_SRAM_ACTIVE_PWR_CFG_WLAN_SRAM_ACTIVE_PWR_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WLAN_SRAM_SLEEP_PWR_CFG register. +// +//****************************************************************************** +#define GPRCM_WLAN_SRAM_SLEEP_PWR_CFG_WLAN_SRAM_SLEEP_PWR_CFG_M \ + 0x00FFFFFF // SRAM (WTOP+DRP) state during + // Sleep-mode : 1 - SRAMs are RET ; + // 0 - SRAMs are OFF. Cluster + // information : [0] - 1st column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) [1] - 2nd column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) ; [2] - 3rd column + // of MEMSS (Applicable only when + // owned by WTOP/PHY) ; [3] - 4th + // column of MEMSS (Applicable only + // when owned by WTOP/PHY) ; [4] - + // 5th column of MEMSS (Applicable + // only when owned by WTOP/PHY) ; + // [5] - 6th column of MEMSS + // (Applicable only when owned by + // WTOP/PHY) ; [6] - 7th column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) ; [7] - 8th column + // of MEMSS (Applicable only when + // owned by WTOP/PHY) ; [8] - 9th + // column of MEMSS (Applicable only + // when owned by WTOP/PHY) ; [9] - + // 10th column of MEMSS (Applicable + // only when owned by WTOP/PHY) ; + // [10] - 11th column of MEMSS + // (Applicable only when owned by + // WTOP/PHY) ; [11] - 12th column of + // MEMSS (Applicable only when owned + // by WTOP/PHY) ; [12] - 13th column + // of MEMSS (Applicable only when + // owned by WTOP/PHY) ; [13] - 14th + // column of MEMSS (Applicable only + // when owned by WTOP/PHY) ; [14] - + // 15th column of MEMSS (Applicable + // only when owned by WTOP/PHY) ; + // [15] - 16th column of MEMSS + // (Applicable only when owned by + // WTOP/PHY) ; [23:16] - Internal to + // WTOP Cluster + +#define GPRCM_WLAN_SRAM_SLEEP_PWR_CFG_WLAN_SRAM_SLEEP_PWR_CFG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_SECURE_INIT_DONE register. +// +//****************************************************************************** +#define GPRCM_APPS_SECURE_INIT_DONE_SECURE_INIT_DONE_STATUS \ + 0x00000002 // 1-Secure mode init is done ; + // 0-Secure mode init is not done + +#define GPRCM_APPS_SECURE_INIT_DONE_APPS_SECURE_INIT_DONE \ + 0x00000001 // Must be programmed 1 in order to + // say that secure-mode device init + // is done + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_DEV_MODE_INIT_DONE register. +// +//****************************************************************************** +#define GPRCM_APPS_DEV_MODE_INIT_DONE_APPS_DEV_MODE_INIT_DONE \ + 0x00000001 // 1 - Patch download and other + // initializations are done (before + // removing APPS resetn) for + // development mode (#3) . 0 - + // Development mode (#3) init is not + // done yet + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_EN_APPS_REBOOT register. +// +//****************************************************************************** +#define GPRCM_EN_APPS_REBOOT_EN_APPS_REBOOT \ + 0x00000001 // 1 - When 1, disable the reboot + // of APPS after DevInit is + // completed. In this case, APPS + // will permanantly help in reset. 0 + // - When 0, enable the reboot of + // APPS after DevInit is completed. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_APPS_PERIPH_PRESENT register. +// +//****************************************************************************** +#define GPRCM_MEM_APPS_PERIPH_PRESENT_WLAN_GEM_PP \ + 0x00010000 // 1 - Enable ; 0 - Disable + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_AES_PP \ + 0x00008000 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_DES_PP \ + 0x00004000 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_SHA_PP \ + 0x00002000 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_CAMERA_PP \ + 0x00001000 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MMCHS_PP \ + 0x00000800 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCASP_PP \ + 0x00000400 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCSPI_A1_PP \ + 0x00000200 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCSPI_A2_PP \ + 0x00000100 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UDMA_PP \ + 0x00000080 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_WDOG_PP \ + 0x00000040 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UART_A0_PP \ + 0x00000020 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UART_A1_PP \ + 0x00000010 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A0_PP \ + 0x00000008 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A1_PP \ + 0x00000004 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A2_PP \ + 0x00000002 + +#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A3_PP \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_NWP_PERIPH_PRESENT register. +// +//****************************************************************************** +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_ASYNC_BRIDGE_PP \ + 0x00000200 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_MCSPI_N2_PP \ + 0x00000100 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_GPT_N0_PP \ + 0x00000080 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_GPT_N1_PP \ + 0x00000040 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_WDOG_PP \ + 0x00000020 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UDMA_PP \ + 0x00000010 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UART_N0_PP \ + 0x00000008 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UART_N1_PP \ + 0x00000004 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_SSDIO_PP \ + 0x00000002 + +#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_MCSPI_N1_PP \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MEM_SHARED_PERIPH_PRESENT register. +// +//****************************************************************************** + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_MCSPI_PP \ + 0x00000040 + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_I2C_PP \ + 0x00000020 + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_A_PP \ + 0x00000010 + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_B_PP \ + 0x00000008 + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_C_PP \ + 0x00000004 + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_D_PP \ + 0x00000002 + +#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_E_PP \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_PWR_STATE register. +// +//****************************************************************************** +#define GPRCM_NWP_PWR_STATE_NWP_PWR_STATE_PS_M \ + 0x00000F00 // "0000"- PORZ :- NWP is yet to be + // enabled by APPS during powerup + // (from HIB/OFF) ; "0011"- ACTIVE + // :- NWP is enabled, clocks and + // resets to NWP-SubSystem are + // enabled ; "0010"- LPDS :- NWP is + // in LPDS-mode ; Clocks and reset + // to NWP-SubSystem are gated ; + // "0101"- WAIT_FOR_OPP :- NWP is in + // transition from LPDS to ACTIVE, + // where it is waiting for OPP to be + // stable ; "1000"- + // WAKE_TIMER_OPP_REQ :- NWP is in + // transition from LPDS, where the + // wakeup cause is LPDS_Wake timer + // OTHERS : NA + +#define GPRCM_NWP_PWR_STATE_NWP_PWR_STATE_PS_S 8 +#define GPRCM_NWP_PWR_STATE_NWP_RCM_PS_M \ + 0x00000007 // "000" - NWP_RUN : NWP is in RUN + // state (default) - Applicable only + // when NWP_PWR_STATE_PS = ACTIVE ; + // "001" - NWP_SLP : NWP is in SLEEP + // state (default) - Applicable only + // when NWP_PWR_STATE_PS = ACTIVE ; + // "010" - NWP_DSLP : NWP is in + // Deep-Sleep state (default) - + // Applicable only when + // NWP_PWR_STATE_PS = ACTIVE ; "011" + // - WAIT_FOR_ACTIVE : NWP is in + // transition from Deep-sleep to + // Run, where it is waiting for OPP + // to be stable ; "100" - + // WAIT_FOR_DSLP_TIMER_WAKE_REQ : + // NWP is in transition from + // Deep-sleep to Run, where the + // wakeup cause is deep-sleep + // wake-timer + +#define GPRCM_NWP_PWR_STATE_NWP_RCM_PS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_PWR_STATE register. +// +//****************************************************************************** +#define GPRCM_APPS_PWR_STATE_APPS_PWR_STATE_PS_M \ + 0x00000F00 // "0000"- PORZ :- APPS is waiting + // for PLL_clock during powerup + // (from HIB/OFF) ; "0011"- ACTIVE + // :- APPS is enabled, clocks and + // resets to APPS-SubSystem are + // enabled ; APPS might be either in + // Secure or Un-secure mode during + // this state. "1001" - + // SECURE_MODE_LPDS :- While in + // ACTIVE (Secure-mode), APPS had to + // program the DevInit_done bit at + // the end, after which it enters + // into this state, where the reset + // to APPS will be asserted. From + // this state APPS might either + // re-boot itself or enter into LPDS + // depending upon whether the device + // is 3200 or 3100. "0010"- LPDS :- + // APPS is in LPDS-mode ; Clocks and + // reset to APPS-SubSystem are gated + // ; "0101"- WAIT_FOR_OPP :- APPS is + // in transition from LPDS to + // ACTIVE, where it is waiting for + // OPP to be stable ; "1000" - + // WAKE_TIMER_OPP_REQ : APPS is in + // transition from LPDS, where the + // wakeup cause is LPDS_Wake timer ; + // "1010" - WAIT_FOR_PATCH_INIT : + // APPS enters into this state + // during development-mode #3 (SOP = + // 3), where it is waiting for patch + // download to complete and 0x4 hack + // is programmed. OTHERS : NA + +#define GPRCM_APPS_PWR_STATE_APPS_PWR_STATE_PS_S 8 +#define GPRCM_APPS_PWR_STATE_APPS_RCM_PS_M \ + 0x00000007 // "000" - APPS_RUN : APPS is in + // RUN state (default) - Applicable + // only when APPS_PWR_STATE_PS = + // ACTIVE ; "001" - APPS_SLP : APPS + // is in SLEEP state (default) - + // Applicable only when + // APPS_PWR_STATE_PS = ACTIVE ; + // "010" - APPS_DSLP : APPS is in + // Deep-Sleep state (default) - + // Applicable only when + // APPS_PWR_STATE_PS = ACTIVE ; + // "011" - WAIT_FOR_ACTIVE : APPS is + // in transition from Deep-sleep to + // Run, where it is waiting for OPP + // to be stable ; "100" - + // WAIT_FOR_DSLP_TIMER_WAKE_REQ : + // APPS is in transition from + // Deep-sleep to Run, where the + // wakeup cause is deep-sleep + // wake-timer + +#define GPRCM_APPS_PWR_STATE_APPS_RCM_PS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCU_PWR_STATE register. +// +//****************************************************************************** +#define GPRCM_MCU_PWR_STATE_MCU_OPP_PS_M \ + 0x0000001F // TBD + +#define GPRCM_MCU_PWR_STATE_MCU_OPP_PS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WTOP_PM_PS register. +// +//****************************************************************************** +#define GPRCM_WTOP_PM_PS_WTOP_PM_PS_M \ + 0x00000007 // "011" - WTOP_PM_ACTIVE (Default) + // :- WTOP_Pd is in ACTIVE mode; + // "100" - WTOP_PM_ACTIVE_TO_SLEEP + // :- WTOP_Pd is in transition from + // ACTIVE to SLEEP ; "000" - + // WTOP_PM_SLEEP : WTOP-Pd is in + // Sleep-state ; "100" - + // WTOP_PM_SLEEP_TO_ACTIVE : WTOP_Pd + // is in transition from SLEEP to + // ACTIVE ; "000" - + // WTOP_PM_WAIT_FOR_OPP : Wait for + // OPP to be stable ; + +#define GPRCM_WTOP_PM_PS_WTOP_PM_PS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WTOP_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_WTOP_PD_RESETZ_OVERRIDE_REG_WTOP_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for WTOP PD + // Resetz. When set to 1, + // WTOP_Resetz will be controlled by + // bit [0] + +#define GPRCM_WTOP_PD_RESETZ_OVERRIDE_REG_WTOP_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for WTOP PD Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WELP_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_WELP_PD_RESETZ_OVERRIDE_REG_WELP_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for WELP PD + // Resetz. When set to 1, + // WELP_Resetz will be controlled by + // bit [0] + +#define GPRCM_WELP_PD_RESETZ_OVERRIDE_REG_WELP_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for WELP PD Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WL_SDIO_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_WL_SDIO_PD_RESETZ_OVERRIDE_REG_WL_SDIO_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for WL_SDIO + // Resetz. When set to 1, + // WL_SDIO_Resetz will be controlled + // by bit [0] + +#define GPRCM_WL_SDIO_PD_RESETZ_OVERRIDE_REG_WL_SDIO_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for WL_SDIO Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_SSDIO_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_SSDIO_PD_RESETZ_OVERRIDE_REG_SSDIO_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for SSDIO + // Resetz. When set to 1, + // SSDIO_Resetz will be controlled + // by bit [0] + +#define GPRCM_SSDIO_PD_RESETZ_OVERRIDE_REG_SSDIO_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for SSDIO Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCSPI_N1_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_MCSPI_N1_PD_RESETZ_OVERRIDE_REG_MCSPI_N1_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for MCSPI_N1 + // Resetz. When set to 1, + // MCSPI_N1_Resetz will be + // controlled by bit [0] + +#define GPRCM_MCSPI_N1_PD_RESETZ_OVERRIDE_REG_MCSPI_N1_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for MCSPI_N1 Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_TESTCTRL_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_TESTCTRL_PD_RESETZ_OVERRIDE_REG_TESTCTRL_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for TESTCTRL-PD + // Resetz. When set to 1, + // TESTCTRL_Resetz will be + // controlled by bit [0] + +#define GPRCM_TESTCTRL_PD_RESETZ_OVERRIDE_REG_TESTCTRL_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for TESTCTRL Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCU_PD_RESETZ_OVERRIDE_REG register. +// +//****************************************************************************** +#define GPRCM_MCU_PD_RESETZ_OVERRIDE_REG_MCU_PD_RESETZ_OVERRIDE_CTRL \ + 0x00000100 // Override control for MCU-PD + // Resetz. When set to 1, MCU_Resetz + // will be controlled by bit [0] + +#define GPRCM_MCU_PD_RESETZ_OVERRIDE_REG_MCU_PD_RESETZ_OVERRIDE \ + 0x00000001 // Override for MCU Resetz. + // Applicable only when bit[8] is + // set to 1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG0 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG0_FUSEFARM_ROW_14_M \ + 0xFFFFFFFF // This is ROW_14 [31:0] of + // FUSEFARM. [0:0] : XTAL_IS_26MHZ + // [5:1] : TOP_CLKM_RTRIM[4:0] + // [10:6] : ANA_BGAP_MAG_TRIM[4:0] + // [16:11] : ANA_BGAP_TEMP_TRIM[5:0] + // [20:17] : ANA_BGAP_V2I_TRIM[3:0] + // [25:22] : PROCESS INDICATOR + // [26:26] : Reserved [31:27] : + // FUSEROM Version + +#define GPRCM_GPRCM_EFUSE_READ_REG0_FUSEFARM_ROW_14_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG1 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG1_FUSEFARM_ROW_15_LSW_M \ + 0x0000FFFF // This is ROW_15[15:0] of FUSEFARM + // 1. NWP Peripheral Present bits + // [15:8] NWP_GPT_N0_PP [15:15] + // NWP_GPT_N1_PP [14:14] NWP_WDOG_PP + // [13:13] NWP_UDMA_PP [12:12] + // NWP_UART_N0_PP [11:11] + // NWP_UART_N1_PP [10:10] + // NWP_SSDIO_PP [9:9] + // NWP_MCSPI_N1_PP [8:8] 2. Shared + // Peripheral Present bits [7:0] + // SHARED SPI PP [6:6] + // SHARED I2C PP [5:5] SHARED + // GPIO-A PP [4:4] SHARED GPIO-B PP + // [3:3] SHARED GPIO-C PP [2:2] + // SHARED GPIO-D PP [1:1] SHARED + // GPIO-E PP [0:0] + +#define GPRCM_GPRCM_EFUSE_READ_REG1_FUSEFARM_ROW_15_LSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG2 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG2_FUSEFARM_ROW_16_LSW_ROW_15_MSW_M \ + 0xFFFFFFFF // This is ROW_16[15:0] & + // ROW_15[31:16] of FUSEFARM. + // [31:21] - Reserved [20:16] - + // CHIP_ID [15:15] - SSBD SOP + // Control [14:14] - SSBD TAP + // Control [13:2] - APPS Peripheral + // Present bits : APPS_CAMERA_PP + // [13:13] APPS_MMCHS_PP [12:12] + // APPS_MCASP_PP [11:11] + // APPS_MCSPI_A1_PP [10:10] + // APPS_MCSPI_A2_PP [9:9] + // APPS_UDMA_PP [8:8] APPS_WDOG_PP + // [7:7] APPS_UART_A0_PP [6:6] + // APPS_UART_A1_PP [5:5] + // APPS_GPT_A0_PP [4:4] + // APPS_GPT_A1_PP [3:3] + // APPS_GPT_A2_PP [2:2] + // APPS_GPT_A3_PP [1:1] [0:0] - NWP + // Peripheral present bits + // NWP_ACSPI_PP [0:0] + +#define GPRCM_GPRCM_EFUSE_READ_REG2_FUSEFARM_ROW_16_LSW_ROW_15_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG3 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG3_FUSEFARM_ROW_17_LSW_ROW_16_MSW_M \ + 0xFFFFFFFF // This is ROW_17[15:0] & + // ROW_16[31:16] of FUSEFARM : + // [31:16] - TEST_TAP_KEY(15:0) + // [15:0] - Reserved + +#define GPRCM_GPRCM_EFUSE_READ_REG3_FUSEFARM_ROW_17_LSW_ROW_16_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WTOP_MEM_RET_CFG register. +// +//****************************************************************************** +#define GPRCM_WTOP_MEM_RET_CFG_WTOP_MEM_RET_CFG \ + 0x00000001 // 1 - Soft-compile memories in + // WTOP can be turned-off during + // WTOP-sleep mode ; 0 - + // Soft-compile memories in WTOP + // must be kept on during WTOP-sleep + // mode. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_COEX_CLK_SWALLOW_CFG0 register. +// +//****************************************************************************** +#define GPRCM_COEX_CLK_SWALLOW_CFG0_Q_FACTOR_M \ + 0x007FFFFF // TBD + +#define GPRCM_COEX_CLK_SWALLOW_CFG0_Q_FACTOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_COEX_CLK_SWALLOW_CFG1 register. +// +//****************************************************************************** +#define GPRCM_COEX_CLK_SWALLOW_CFG1_P_FACTOR_M \ + 0x000FFFFF // TBD + +#define GPRCM_COEX_CLK_SWALLOW_CFG1_P_FACTOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_COEX_CLK_SWALLOW_CFG2 register. +// +//****************************************************************************** +#define GPRCM_COEX_CLK_SWALLOW_CFG2_CONSECUTIVE_SWALLOW_M \ + 0x00000018 + +#define GPRCM_COEX_CLK_SWALLOW_CFG2_CONSECUTIVE_SWALLOW_S 3 +#define GPRCM_COEX_CLK_SWALLOW_CFG2_PRBS_GAIN \ + 0x00000004 + +#define GPRCM_COEX_CLK_SWALLOW_CFG2_PRBS_ENABLE \ + 0x00000002 + +#define GPRCM_COEX_CLK_SWALLOW_CFG2_SWALLOW_ENABLE \ + 0x00000001 // TBD + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_COEX_CLK_SWALLOW_ENABLE register. +// +//****************************************************************************** +#define GPRCM_COEX_CLK_SWALLOW_ENABLE_COEX_CLK_SWALLOW_ENABLE \ + 0x00000001 // 1 - Enable switching of sysclk + // to Coex-clk path ; 0 - Disable + // switching of sysclk to Coex-clk + // path. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_DCDC_CLK_GEN_CONFIG register. +// +//****************************************************************************** +#define GPRCM_DCDC_CLK_GEN_CONFIG_DCDC_CLK_ENABLE \ + 0x00000001 // 1 - Enable the clock for DCDC + // (PWM-mode) ; 0 - Disable the + // clock for DCDC (PWM-mode) + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG4 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG4_FUSEFARM_ROW_17_MSW_M \ + 0x0000FFFF // This corresponds to + // ROW_17[31:16] of the FUSEFARM : + // [15:0] : TEST_TAP_KEY(31:16) + +#define GPRCM_GPRCM_EFUSE_READ_REG4_FUSEFARM_ROW_17_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG5 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG5_FUSEFARM_ROW_18_M \ + 0xFFFFFFFF // Corresponds to ROW_18 of + // FUSEFARM. [29:0] - + // MEMSS_COLUMN_SEL_LSW ; [30:30] - + // WLAN GEM DISABLE ; [31:31] - + // SERIAL WIRE JTAG SELECT + +#define GPRCM_GPRCM_EFUSE_READ_REG5_FUSEFARM_ROW_18_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG6 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG6_FUSEFARM_ROW_19_LSW_M \ + 0x0000FFFF // Corresponds to ROW_19[15:0] of + // FUSEFARM. [15:0] : + // MEMSS_COLUMN_SEL_MSW + +#define GPRCM_GPRCM_EFUSE_READ_REG6_FUSEFARM_ROW_19_LSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG7 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG7_FUSEFARM_ROW_20_LSW_ROW_19_MSW_M \ + 0xFFFFFFFF // Corresponds to ROW_20[15:0] & + // ROW_19[31:16] of FUSEFARM. + // FLASH_REGION0 + +#define GPRCM_GPRCM_EFUSE_READ_REG7_FUSEFARM_ROW_20_LSW_ROW_19_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG8 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG8_FUSEFARM_ROW_21_LSW_ROW_20_MSW_M \ + 0xFFFFFFFF // Corresponds to ROW_21[15:0] & + // ROW_20[31:16] of FUSEFARM. + // FLASH_REGION1 + +#define GPRCM_GPRCM_EFUSE_READ_REG8_FUSEFARM_ROW_21_LSW_ROW_20_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG9 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG9_FUSEFARM_ROW_22_LSW_ROW_21_MSW_M \ + 0xFFFFFFFF // Corresponds to ROW_22[15:0] & + // ROW_21[31:16] of FUSEFARM. + // FLASH_REGION2 + +#define GPRCM_GPRCM_EFUSE_READ_REG9_FUSEFARM_ROW_22_LSW_ROW_21_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG10 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG10_FUSEFARM_ROW_23_LSW_ROW_22_MSW_M \ + 0xFFFFFFFF // Corresponds to ROW_23[15:0] & + // ROW_22[31:16] of FUSEFARM. + // FLASH_REGION3 + +#define GPRCM_GPRCM_EFUSE_READ_REG10_FUSEFARM_ROW_23_LSW_ROW_22_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_EFUSE_READ_REG11 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_EFUSE_READ_REG11_FUSEFARM_ROW_24_LSW_ROW_23_MSW_M \ + 0xFFFFFFFF // Corresponds to ROW_24[15:0] & + // ROW_23[31:16] of FUSEFARM. + // FLASH_DESCRIPTOR + +#define GPRCM_GPRCM_EFUSE_READ_REG11_FUSEFARM_ROW_24_LSW_ROW_23_MSW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG0 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG0_FUSEFARM_191_160_M \ + 0xFFFFFFFF // Corresponds to bits [191:160] of + // the FUSEFARM. This is ROW_5 of + // FUSEFARM [191:160] : [31:0] : + // DIE_ID0 [31:0] : DEVX [11:0] DEVY + // [23:12] DEVWAF [29:24] DEV_SPARE + // [31:30] + +#define GPRCM_GPRCM_DIEID_READ_REG0_FUSEFARM_191_160_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG1 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG1_FUSEFARM_223_192_M \ + 0xFFFFFFFF // Corresponds to bits [223:192] of + // the FUSEFARM. This is ROW_6 of + // FUSEFARM :- DEVLOT [23:0] DEVFAB + // [28:24] DEVFABBE [31:29] + +#define GPRCM_GPRCM_DIEID_READ_REG1_FUSEFARM_223_192_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG2 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG2_FUSEFARM_255_224_M \ + 0xFFFFFFFF // Corresponds to bits [255:224] of + // the FUSEFARM. This is ROW_7 of + // FUSEFARM:- DEVDESREV[4:0] + // Memrepair[5:5] MakeDefined[16:6] + // CHECKSUM[30:17] Reserved : + // [31:31] + +#define GPRCM_GPRCM_DIEID_READ_REG2_FUSEFARM_255_224_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG3 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG3_FUSEFARM_287_256_M \ + 0xFFFFFFFF // Corresponds to bits [287:256] of + // the FUSEFARM. This is ROW_8 of + // FUSEFARM :- DIEID0 - DEVREG + // [31:0] + +#define GPRCM_GPRCM_DIEID_READ_REG3_FUSEFARM_287_256_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_GPRCM_DIEID_READ_REG4 register. +// +//****************************************************************************** +#define GPRCM_GPRCM_DIEID_READ_REG4_FUSEFARM_319_288_M \ + 0xFFFFFFFF // Corresponds to bits [319:288] of + // the FUSEFARM. This is ROW_9 of + // FUSEFARM :- [7:0] - VBATMON ; + // [13:8] - BUFF_OFFSET ; [15:15] - + // DFT_GXG ; [14:14] - DFT_GLX ; + // [19:16] - PHY ROM Version ; + // [23:20] - MAC ROM Version ; + // [27:24] - NWP ROM Version ; + // [31:28] - APPS ROM Version + +#define GPRCM_GPRCM_DIEID_READ_REG4_FUSEFARM_319_288_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_APPS_SS_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_APPS_SS_OVERRIDES_reserved_M \ + 0xFFFFFC00 + +#define GPRCM_APPS_SS_OVERRIDES_reserved_S 10 +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_refclk_gating_override \ + 0x00000200 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_refclk_gating_override_ctrl \ + 0x00000100 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_pllclk_gating_override \ + 0x00000080 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_pllclk_gating_override_ctrl \ + 0x00000040 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_por_rstn_override \ + 0x00000020 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysrstn_override \ + 0x00000010 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysclk_gating_override \ + 0x00000008 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_por_rstn_override_ctrl \ + 0x00000004 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysrstn_override_ctrl \ + 0x00000002 + +#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysclk_gating_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_NWP_SS_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_NWP_SS_OVERRIDES_reserved_M \ + 0xFFFFFC00 + +#define GPRCM_NWP_SS_OVERRIDES_reserved_S 10 +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_refclk_gating_override \ + 0x00000200 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_refclk_gating_override_ctrl \ + 0x00000100 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_pllclk_gating_override \ + 0x00000080 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_pllclk_gating_override_ctrl \ + 0x00000040 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_por_rstn_override \ + 0x00000020 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysrstn_override \ + 0x00000010 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysclk_gating_override \ + 0x00000008 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_por_rstn_override_ctrl \ + 0x00000004 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysrstn_override_ctrl \ + 0x00000002 + +#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysclk_gating_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_SHARED_SS_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_SHARED_SS_OVERRIDES_reserved_M \ + 0xFFFFFF00 + +#define GPRCM_SHARED_SS_OVERRIDES_reserved_S 8 +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_pllclk_gating_override_ctrl \ + 0x00000080 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_pllclk_gating_override \ + 0x00000040 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_refclk_gating_override_ctrl \ + 0x00000020 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_refclk_gating_override \ + 0x00000010 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_rstn_override \ + 0x00000008 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_sysclk_gating_override \ + 0x00000004 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_rstn_override_ctrl \ + 0x00000002 + +#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_sysclk_gating_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_IDMEM_CORE_RST_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_reserved_M \ + 0xFFFFFF00 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_reserved_S 8 +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_sysrstn_override \ + 0x00000080 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_fmc_rstn_override \ + 0x00000040 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_SPARE_RW1 \ + 0x00000020 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_piosc_gating_override \ + 0x00000010 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_sysrstn_override_ctrl \ + 0x00000008 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_fmc_rstn_override_ctrl \ + 0x00000004 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_SPARE_RW0 \ + 0x00000002 + +#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_piosc_gating_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_TOP_DIE_FSM_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_TOP_DIE_FSM_OVERRIDES_reserved_M \ + 0xFFFFF000 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_reserved_S 12 +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_pgoodin_override_ctrl \ + 0x00000800 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_pgoodin_override \ + 0x00000400 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_hclk_gating_override \ + 0x00000200 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_piosc_gating_override \ + 0x00000100 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_rstn_override \ + 0x00000080 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_ponin_override \ + 0x00000040 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_flash_ready_override \ + 0x00000020 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_hclk_gating_override_ctrl \ + 0x00000010 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_piosc_gating_override_ctrl \ + 0x00000008 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_rstn_override_ctrl \ + 0x00000004 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_ponin_override_ctrl \ + 0x00000002 + +#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_flash_ready_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCU_PSCON_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_MCU_PSCON_OVERRIDES_reserved_M \ + 0xFFF00000 + +#define GPRCM_MCU_PSCON_OVERRIDES_reserved_S 20 +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_sleep_override_ctrl \ + 0x00080000 + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_update_override_ctrl \ + 0x00040000 + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_ctrl \ + 0x00020000 + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_ctrl \ + 0x00010000 + +#define GPRCM_MCU_PSCON_OVERRIDES_NU1_M \ + 0x0000FC00 + +#define GPRCM_MCU_PSCON_OVERRIDES_NU1_S 10 +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_sleep_override \ + 0x00000200 + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_update_override \ + 0x00000100 + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_M \ + 0x000000F0 + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_S 4 +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_M \ + 0x0000000F + +#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WTOP_PSCON_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_WTOP_PSCON_OVERRIDES_reserved_M \ + 0xFFC00000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_reserved_S 22 +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_sleep_override_ctrl \ + 0x00200000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_update_override_ctrl \ + 0x00100000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_ctrl \ + 0x00080000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_ctrl \ + 0x00040000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_sleep_override \ + 0x00020000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_update_override \ + 0x00010000 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_M \ + 0x0000FF00 + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_S 8 +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_M \ + 0x000000FF + +#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WELP_PSCON_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_WELP_PSCON_OVERRIDES_reserved_M \ + 0xFFFFFFFC + +#define GPRCM_WELP_PSCON_OVERRIDES_reserved_S 2 +#define GPRCM_WELP_PSCON_OVERRIDES_mem_welp_pscon_sleep_override_ctrl \ + 0x00000002 + +#define GPRCM_WELP_PSCON_OVERRIDES_mem_welp_pscon_sleep_override \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_WL_SDIO_PSCON_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_WL_SDIO_PSCON_OVERRIDES_reserved_M \ + 0xFFFFFFFC + +#define GPRCM_WL_SDIO_PSCON_OVERRIDES_reserved_S 2 +#define GPRCM_WL_SDIO_PSCON_OVERRIDES_mem_wl_sdio_pscon_sleep_override_ctrl \ + 0x00000002 + +#define GPRCM_WL_SDIO_PSCON_OVERRIDES_mem_wl_sdio_pscon_sleep_override \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_MCSPI_PSCON_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_MCSPI_PSCON_OVERRIDES_reserved_M \ + 0xFFFFFF00 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_reserved_S 8 +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_retain_override_ctrl \ + 0x00000080 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_off_override_ctrl \ + 0x00000040 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_retain_override \ + 0x00000020 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_off_override \ + 0x00000010 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_update_override_ctrl \ + 0x00000008 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_update_override \ + 0x00000004 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_sleep_override_ctrl \ + 0x00000002 + +#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_sleep_override \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// GPRCM_O_SSDIO_PSCON_OVERRIDES register. +// +//****************************************************************************** +#define GPRCM_SSDIO_PSCON_OVERRIDES_reserved_M \ + 0xFFFFFFFC + +#define GPRCM_SSDIO_PSCON_OVERRIDES_reserved_S 2 +#define GPRCM_SSDIO_PSCON_OVERRIDES_mem_ssdio_pscon_sleep_override_ctrl \ + 0x00000002 + +#define GPRCM_SSDIO_PSCON_OVERRIDES_mem_ssdio_pscon_sleep_override \ + 0x00000001 + + + + +#endif // __HW_GPRCM_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_hib1p2.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_hib1p2.h new file mode 100644 index 00000000..95e25ff7 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_hib1p2.h @@ -0,0 +1,1750 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_HIB1P2_H__ +#define __HW_HIB1P2_H__ + +//***************************************************************************** +// +// The following are defines for the HIB1P2 register offsets. +// +//***************************************************************************** +#define HIB1P2_O_SRAM_SKA_LDO_PARAMETERS0 \ + 0x00000000 + +#define HIB1P2_O_SRAM_SKA_LDO_PARAMETERS1 \ + 0x00000004 + +#define HIB1P2_O_DIG_DCDC_PARAMETERS0 \ + 0x00000008 + +#define HIB1P2_O_DIG_DCDC_PARAMETERS1 \ + 0x0000000C + +#define HIB1P2_O_DIG_DCDC_PARAMETERS2 \ + 0x00000010 + +#define HIB1P2_O_DIG_DCDC_PARAMETERS3 \ + 0x00000014 + +#define HIB1P2_O_DIG_DCDC_PARAMETERS4 \ + 0x00000018 + +#define HIB1P2_O_DIG_DCDC_PARAMETERS5 \ + 0x0000001C + +#define HIB1P2_O_DIG_DCDC_PARAMETERS6 \ + 0x00000020 + +#define HIB1P2_O_ANA_DCDC_PARAMETERS0 \ + 0x00000024 + +#define HIB1P2_O_ANA_DCDC_PARAMETERS1 \ + 0x00000028 + +#define HIB1P2_O_ANA_DCDC_PARAMETERS16 \ + 0x00000064 + +#define HIB1P2_O_ANA_DCDC_PARAMETERS17 \ + 0x00000068 + +#define HIB1P2_O_ANA_DCDC_PARAMETERS18 \ + 0x0000006C + +#define HIB1P2_O_ANA_DCDC_PARAMETERS19 \ + 0x00000070 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS0 \ + 0x00000074 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS1 \ + 0x00000078 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS2 \ + 0x0000007C + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS3 \ + 0x00000080 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS4 \ + 0x00000084 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS5 \ + 0x00000088 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS6 \ + 0x0000008C + +#define HIB1P2_O_PMBIST_PARAMETERS0 \ + 0x00000094 + +#define HIB1P2_O_PMBIST_PARAMETERS1 \ + 0x00000098 + +#define HIB1P2_O_PMBIST_PARAMETERS2 \ + 0x0000009C + +#define HIB1P2_O_PMBIST_PARAMETERS3 \ + 0x000000A0 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS8 \ + 0x000000A4 + +#define HIB1P2_O_ANA_DCDC_PARAMETERS_OVERRIDE \ + 0x000000A8 + +#define HIB1P2_O_FLASH_DCDC_PARAMETERS_OVERRIDE \ + 0x000000AC + +#define HIB1P2_O_DIG_DCDC_VTRIM_CFG \ + 0x000000B0 + +#define HIB1P2_O_DIG_DCDC_FSM_PARAMETERS \ + 0x000000B4 + +#define HIB1P2_O_ANA_DCDC_FSM_PARAMETERS \ + 0x000000B8 + +#define HIB1P2_O_SRAM_SKA_LDO_FSM_PARAMETERS \ + 0x000000BC + +#define HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG \ + 0x000000C0 + +#define HIB1P2_O_CM_OSC_16M_CONFIG \ + 0x000000C4 + +#define HIB1P2_O_SOP_SENSE_VALUE \ + 0x000000C8 + +#define HIB1P2_O_HIB_RTC_TIMER_LSW_1P2 \ + 0x000000CC + +#define HIB1P2_O_HIB_RTC_TIMER_MSW_1P2 \ + 0x000000D0 + +#define HIB1P2_O_HIB1P2_BGAP_TRIM_OVERRIDES \ + 0x000000D4 + +#define HIB1P2_O_HIB1P2_EFUSE_READ_REG0 \ + 0x000000D8 + +#define HIB1P2_O_HIB1P2_EFUSE_READ_REG1 \ + 0x000000DC + +#define HIB1P2_O_HIB1P2_POR_TEST_CTRL \ + 0x000000E0 + +#define HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG0 \ + 0x000000E4 + +#define HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG1 \ + 0x000000E8 + +#define HIB1P2_O_HIB_TIMER_SYNC_CFG2 \ + 0x000000EC + +#define HIB1P2_O_HIB_TIMER_SYNC_TSF_ADJ_VAL \ + 0x000000F0 + +#define HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW \ + 0x000000F4 + +#define HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW \ + 0x000000F8 + +#define HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW \ + 0x000000FC + +#define HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW \ + 0x00000100 + +#define HIB1P2_O_HIB_TIMER_SYNC_WAKE_OFFSET_ERR \ + 0x00000104 + +#define HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW \ + 0x00000108 + +#define HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW \ + 0x0000010C + +#define HIB1P2_O_CM_SPARE 0x00000110 +#define HIB1P2_O_PORPOL_SPARE 0x00000114 +#define HIB1P2_O_MEM_DIG_DCDC_CLK_CONFIG \ + 0x00000118 + +#define HIB1P2_O_MEM_ANA_DCDC_CLK_CONFIG \ + 0x0000011C + +#define HIB1P2_O_MEM_FLASH_DCDC_CLK_CONFIG \ + 0x00000120 + +#define HIB1P2_O_MEM_PA_DCDC_CLK_CONFIG \ + 0x00000124 + +#define HIB1P2_O_MEM_SLDO_VNWA_OVERRIDE \ + 0x00000128 + +#define HIB1P2_O_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE \ + 0x0000012C + +#define HIB1P2_O_MEM_HIB_FSM_DEBUG \ + 0x00000130 + +#define HIB1P2_O_MEM_SLDO_VNWA_SW_CTRL \ + 0x00000134 + +#define HIB1P2_O_MEM_SLDO_WEAK_PROCESS \ + 0x00000138 + +#define HIB1P2_O_MEM_PA_DCDC_OV_UV_STATUS \ + 0x0000013C + +#define HIB1P2_O_MEM_CM_TEST_MODE \ + 0x00000140 + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_SRAM_SKA_LDO_PARAMETERS0 register. +// +//****************************************************************************** +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_itrim_lowv_M \ + 0xC0000000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_itrim_lowv_S 30 +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_iq_trim_lowv_M \ + 0x30000000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_iq_trim_lowv_S 28 +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_prot_lowv \ + 0x08000000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_lowv_override \ + 0x04000000 // FSM Override value for SLDO_EN : + // Applicable only when bit [4] of + // this register is set to 1. + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_low_pwr_lowv \ + 0x02000000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_int_cap_sel_lowv \ + 0x01000000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_vtrim_lowv_M \ + 0x00FC0000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_vtrim_lowv_S 18 +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_spare_lowv_M \ + 0x0003FF00 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_spare_lowv_S 8 +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_lowv_override \ + 0x00000080 // FSM Override value for + // SKA_LDO_EN : Applicable only when + // bit [3] of this register is set + // to 1. + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_cap_ref_lowv \ + 0x00000040 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_resdiv_ref_lowv \ + 0x00000020 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_lowv_fsm_override_ctrl \ + 0x00000010 // When 1, bit[26] of this register + // will be used as SLDO_EN + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_lowv_fsm_override_ctrl \ + 0x00000008 // When 1, bit[26] of this register + // will be used as SKA_LDO_EN + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_NA1_M \ + 0x00000007 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_NA1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_SRAM_SKA_LDO_PARAMETERS1 register. +// +//****************************************************************************** +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_ctrl_lowv_M \ + 0xFFC00000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_ctrl_lowv_S 22 +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_vtrim_lowv_M \ + 0x003F0000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_vtrim_lowv_S 16 +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_sldo_en_tload_lowv \ + 0x00008000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_tload_lowv \ + 0x00004000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_cap_sw_en_lowv \ + 0x00002000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_hib_lowv \ + 0x00001000 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_vref_buf_lowv \ + 0x00000800 + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_NA2_M \ + 0x000007FF + +#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_NA2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS0 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_lowv_override \ + 0x80000000 // Override value for DCDC_DIG_EN : + // Applicable only when bit [31] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1. Else from FSM + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_delayed_en_lowv \ + 0x40000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_subreg_1p8v_lowv_override \ + 0x20000000 // Override value for + // DCDC_DIG_EN_SUBREG_1P8V : + // Applicable only when bit [30] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1. Else from FSM + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_subreg_1p2v_lowv_override \ + 0x10000000 // Override value for + // DCDC_DIG_EN_SUBREG_1P2V : + // Applicable only when bit [29] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1. Else from FSM + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_slp_mode_lowv_override \ + 0x08000000 // Override value for + // DCDC_DIG_SLP_EN : Applicable only + // when bit [28] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1. Else from FSM + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_ldo_mode_lowv \ + 0x04000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_nfet_rds_mode_lowv \ + 0x02000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_pfet_rds_mode_lowv \ + 0x01000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_ext_smps_override_mode_lowv \ + 0x00800000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_clk_in_lowv_enable \ + 0x00400000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_vtrim_lowv_override_M \ + 0x003F0000 // Override value for + // DCDC_DIG_VTRIM : Applicable only + // when bit [27] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1. + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_vtrim_lowv_override_S 16 +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_pfm_ripple_trim_lowv_M \ + 0x0000C000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_pfm_ripple_trim_lowv_S 14 +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_iq_ctrl_lowv_M \ + 0x00003000 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_iq_ctrl_lowv_S 12 +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_cl_non_ov_lowv \ + 0x00000800 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_non_ov_ctrl_lowv_M \ + 0x00000780 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_non_ov_ctrl_lowv_S 7 +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_slp_drv_dly_sel_lowv_M \ + 0x00000078 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_slp_drv_dly_sel_lowv_S 3 +#define HIB1P2_DIG_DCDC_PARAMETERS0_NA3_M \ + 0x00000007 + +#define HIB1P2_DIG_DCDC_PARAMETERS0_NA3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS1 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_lowv_fsm_override_ctrl \ + 0x80000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_subreg_1p8v_fsm_override_ctrl \ + 0x40000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_subreg_1p2v_fsm_override_ctrl \ + 0x20000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_slp_mode_lowv_fsm_override_ctrl \ + 0x10000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_vtrim_fsm_override_ctrl \ + 0x08000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_cot_mode_en_lowv_fsm_override_ctrl \ + 0x04000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_ilim_trim_lowv_efc_override_ctrl \ + 0x02000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS1_NA4_M \ + 0x01FFFFFF + +#define HIB1P2_DIG_DCDC_PARAMETERS1_NA4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS2 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pfet_sel_lowv_M \ + 0xF0000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pfet_sel_lowv_S 28 +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_nfet_sel_lowv_M \ + 0x0F000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_nfet_sel_lowv_S 24 +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_stagger_ctrl_lowv_M \ + 0x00C00000 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_stagger_ctrl_lowv_S 22 +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_stagger_ctrl_lowv_M \ + 0x00300000 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_stagger_ctrl_lowv_S 20 +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_str_sel_lowv_M \ + 0x000F0000 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_str_sel_lowv_S 16 +#define HIB1P2_DIG_DCDC_PARAMETERS2_NA5 \ + 0x00008000 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_str_sel_lowv_M \ + 0x00007800 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_str_sel_lowv_S 11 +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_en_shootthru_ctrl_lowv \ + 0x00000400 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ton_trim_lowv_M \ + 0x000003FC + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ton_trim_lowv_S 2 +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_swcap_res_hf_clk_lowv \ + 0x00000002 + +#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_cot_mode_en_lowv_override \ + 0x00000001 // Override value for + // DCDC_DIG_COT_EN : Applicable only + // when bit[26] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS3 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS3_NA6 \ + 0x80000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_cot_ctrl_lowv_M \ + 0x7F800000 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_cot_ctrl_lowv_S 23 +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ilim_lowv \ + 0x00400000 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ilim_hib_lowv \ + 0x00200000 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_trim_lowv_override_M \ + 0x001FE000 // Override value for + // DCDC_DIG_ILIM_TRIM : Applicable + // only when bit [25] of + // DIG_DCDC_PARAMETERS1 [0x000C] is + // set to 1 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_trim_lowv_override_S 13 +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_mask_dly_sel_lowv_M \ + 0x00001800 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_mask_dly_sel_lowv_S 11 +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ncomp_lowv \ + 0x00000400 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ncomp_hib_lowv \ + 0x00000200 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_trim_lowv_M \ + 0x000001F0 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_trim_lowv_S 4 +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_mask_dly_sel_lowv_M \ + 0x0000000C + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_mask_dly_sel_lowv_S 2 +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_uv_prot_lowv \ + 0x00000002 + +#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ov_prot_lowv \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS4 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS4_dcdc_dig_uv_prot_out_lowv \ + 0x80000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS4_dcdc_dig_ov_prot_out_lowv \ + 0x40000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS4_mem_dcdc_dig_en_tmux_lowv \ + 0x20000000 + +#define HIB1P2_DIG_DCDC_PARAMETERS4_NA7_M \ + 0x1FFFFFFF + +#define HIB1P2_DIG_DCDC_PARAMETERS4_NA7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS5 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS5_mem_dcdc_dig_tmux_ctrl_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_DIG_DCDC_PARAMETERS5_mem_dcdc_dig_tmux_ctrl_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_PARAMETERS6 register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_PARAMETERS6_mem_dcdc_dig_spare_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_DIG_DCDC_PARAMETERS6_mem_dcdc_dig_spare_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS0 register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_lowv_override \ + 0x80000000 // Override for ANA DCDC EN + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_delayed_en_lowv \ + 0x40000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_subreg_1p8v_lowv \ + 0x20000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_subreg_1p2v_lowv \ + 0x10000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_pwm_mode_lowv_override \ + 0x08000000 // Override for ANA DCDC PWM + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_slp_mode_lowv_override \ + 0x04000000 // Override for ANA DCDC SLP + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_ldo_mode_lowv \ + 0x02000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_pfet_rds_mode_lowv \ + 0x01000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_nfet_rds_mode_lowv \ + 0x00800000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_ext_smps_override_mode_lowv \ + 0x00400000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_clk_in_lowv_enable \ + 0x00200000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_vtrim_lowv_M \ + 0x001E0000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_vtrim_lowv_S 17 +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfm_ripple_trim_lowv_M \ + 0x00018000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfm_ripple_trim_lowv_S 15 +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_iq_ctrl_lowv_M \ + 0x00006000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_iq_ctrl_lowv_S 13 +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_cl_non_ov_lowv \ + 0x00001000 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_non_ov_ctrl_lowv_M \ + 0x00000F00 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_non_ov_ctrl_lowv_S 8 +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_slp_drv_dly_sel_lowv_M \ + 0x000000F0 + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_slp_drv_dly_sel_lowv_S 4 +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfet_sel_lowv_M \ + 0x0000000F + +#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfet_sel_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS1 register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_nfet_sel_lowv_M \ + 0xF0000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_nfet_sel_lowv_S 28 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_stagger_ctrl_lowv_M \ + 0x0C000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_stagger_ctrl_lowv_S 26 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_stagger_ctrl_lowv_M \ + 0x03000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_stagger_ctrl_lowv_S 24 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_str_sel_lowv_M \ + 0x00F00000 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_str_sel_lowv_S 20 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_str_sel_lowv_M \ + 0x000F0000 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_str_sel_lowv_S 16 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_rtrim_lowv \ + 0x00008000 // (Earlier SHOOTTHRU CTRL) + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_apwm_en_lowv \ + 0x00004000 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ramp_hgt_lowv_M \ + 0x00003E00 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ramp_hgt_lowv_S 9 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_anti_glitch_lowv \ + 0x00000100 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_hi_clamp_lowv \ + 0x00000080 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_hi_clamp_trim_lowv_M \ + 0x00000060 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_hi_clamp_trim_lowv_S 5 +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_lo_clamp_lowv \ + 0x00000010 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_lo_clamp_trim_lowv_M \ + 0x0000000C + +#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_lo_clamp_trim_lowv_S 2 +#define HIB1P2_ANA_DCDC_PARAMETERS1_NA8_M \ + 0x00000003 + +#define HIB1P2_ANA_DCDC_PARAMETERS1_NA8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS16 register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ilim_lowv \ + 0x00200000 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ilim_hib_lowv \ + 0x00100000 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_trim_lowv_override_M \ + 0x000FF000 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_trim_lowv_override_S 12 +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_mask_dly_sel_lowv_M \ + 0x00000C00 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_mask_dly_sel_lowv_S 10 +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ncomp_lowv \ + 0x00000200 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ncomp_hib_lowv \ + 0x00000100 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_trim_lowv_M \ + 0x000000F8 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_trim_lowv_S 3 +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_mask_dly_sel_lowv_M \ + 0x00000006 + +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_mask_dly_sel_lowv_S 1 +#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ov_prot_lowv \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS17 register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS17_dcdc_ana_ov_prot_out_lowv \ + 0x80000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS17_mem_dcdc_ana_en_tmux_lowv \ + 0x40000000 + +#define HIB1P2_ANA_DCDC_PARAMETERS17_NA17_M \ + 0x3FFFFFFF + +#define HIB1P2_ANA_DCDC_PARAMETERS17_NA17_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS18 register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS18_mem_dcdc_ana_tmux_ctrl_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_ANA_DCDC_PARAMETERS18_mem_dcdc_ana_tmux_ctrl_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS19 register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS19_mem_dcdc_ana_spare_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_ANA_DCDC_PARAMETERS19_mem_dcdc_ana_spare_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS0 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_lowv \ + 0x80000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_delayed_en_lowv \ + 0x40000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_clk_in_lowv_enable \ + 0x20000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_iq_ctrl_lowv_M \ + 0x18000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_iq_ctrl_lowv_S 27 +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_buck_mode_lowv \ + 0x04000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_boost_mode_lowv \ + 0x02000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_buck_boost_mode_lowv \ + 0x01000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_bb_alt_cycles_lowv \ + 0x00800000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_cl_non_ov_lowv \ + 0x00400000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_non_ov_ctrl_lowv_M \ + 0x003C0000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_non_ov_ctrl_lowv_S 18 +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_drv_lowv \ + 0x00020000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_pwm_mode_lowv \ + 0x00010000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_pfm_comp_lowv \ + 0x00008000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_slp_mode_lowv \ + 0x00004000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_n1fet_rds_mode_lowv \ + 0x00002000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_n2fet_rds_mode_lowv \ + 0x00001000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_p1fet_rds_mode_lowv \ + 0x00000800 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_p2fet_rds_mode_lowv \ + 0x00000400 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_ext_smps_mode_override_lowv \ + 0x00000200 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_p1fet_sel_lowv_M \ + 0x000001E0 + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_p1fet_sel_lowv_S 5 +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_n1fet_sel_lowv_M \ + 0x0000001E + +#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_n1fet_sel_lowv_S 1 +#define HIB1P2_FLASH_DCDC_PARAMETERS0_NA18 \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS1 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_sel_lowv_M \ + 0xF0000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_sel_lowv_S 28 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_sel_lowv_M \ + 0x0F000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_sel_lowv_S 24 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1drv_str_sel_lowv_M \ + 0x00F00000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1drv_str_sel_lowv_S 20 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1drv_str_sel_lowv_M \ + 0x000F0000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1drv_str_sel_lowv_S 16 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2drv_str_sel_lowv_M \ + 0x0000F000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2drv_str_sel_lowv_S 12 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2drv_str_sel_lowv_M \ + 0x00000F00 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2drv_str_sel_lowv_S 8 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1fet_non_ov_lowv_M \ + 0x000000C0 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1fet_non_ov_lowv_S 6 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1fet_non_ov_lowv_M \ + 0x00000030 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1fet_non_ov_lowv_S 4 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_non_ov_lowv_M \ + 0x0000000C + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_non_ov_lowv_S 2 +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_non_ov_lowv_M \ + 0x00000003 + +#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_non_ov_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS2 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p1fet_stagger_lowv_M \ + 0xC0000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p1fet_stagger_lowv_S 30 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n1fet_stagger_lowv_M \ + 0x30000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n1fet_stagger_lowv_S 28 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p2fet_stagger_lowv_M \ + 0x0C000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p2fet_stagger_lowv_S 26 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n2fet_stagger_lowv_M \ + 0x03000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n2fet_stagger_lowv_S 24 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_shoot_thru_ctrl_lowv \ + 0x00800000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ncomp_lowv \ + 0x00400000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ncomp_hib_lowv \ + 0x00200000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_trim_lowv_M \ + 0x001F0000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_trim_lowv_S 16 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_mask_dly_trim_lowv_M \ + 0x0000F000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_mask_dly_trim_lowv_S 12 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ilim_lowv \ + 0x00000800 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ilim_hib_lowv \ + 0x00000400 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_trim_lowv_override_M \ + 0x000003FC + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_trim_lowv_override_S 2 +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_mask_dly_sel_lowv_M \ + 0x00000003 + +#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_mask_dly_sel_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS3 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_anti_glitch_lowv \ + 0x80000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_hi_clamp_lowv \ + 0x40000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_lo_clamp_lowv \ + 0x20000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_ramp_hgt_lowv_M \ + 0x1F000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_ramp_hgt_lowv_S 24 +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclamph_trim_lowv_M \ + 0x00E00000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclamph_trim_lowv_S 21 +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclampl_trim_lowv_M \ + 0x001C0000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclampl_trim_lowv_S 18 +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vtrim_lowv_M \ + 0x0003C000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vtrim_lowv_S 14 +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_pfm_ripple_trim_lowv_M \ + 0x00003C00 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_pfm_ripple_trim_lowv_S 10 +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_slp_drv_dly_sel_lowv_M \ + 0x00000300 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_slp_drv_dly_sel_lowv_S 8 +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_ov_prot_lowv \ + 0x00000080 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_uv_prot_lowv \ + 0x00000040 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_tmux_lowv \ + 0x00000020 + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_NA19_M \ + 0x0000001F + +#define HIB1P2_FLASH_DCDC_PARAMETERS3_NA19_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS4 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS4_mem_dcdc_flash_tmux_ctrl_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_FLASH_DCDC_PARAMETERS4_mem_dcdc_flash_tmux_ctrl_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS5 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS5_mem_dcdc_flash_spare_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_FLASH_DCDC_PARAMETERS5_mem_dcdc_flash_spare_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS6 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS6_dcdc_flash_ov_prot_out_lowv \ + 0x80000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS6_dcdc_flash_uv_prot_out_lowv \ + 0x40000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS6_NA20_M \ + 0x3FFFFFFF + +#define HIB1P2_FLASH_DCDC_PARAMETERS6_NA20_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_PMBIST_PARAMETERS0 register. +// +//****************************************************************************** +#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_en_lowv \ + 0x80000000 + +#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_ctrl_lowv_M \ + 0x7FFFF800 + +#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_ctrl_lowv_S 11 +#define HIB1P2_PMBIST_PARAMETERS0_NA21_M \ + 0x000007FF + +#define HIB1P2_PMBIST_PARAMETERS0_NA21_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_PMBIST_PARAMETERS1 register. +// +//****************************************************************************** +#define HIB1P2_PMBIST_PARAMETERS1_mem_pm_bist_spare_lowv_M \ + 0xFFFF0000 + +#define HIB1P2_PMBIST_PARAMETERS1_mem_pm_bist_spare_lowv_S 16 +#define HIB1P2_PMBIST_PARAMETERS1_mem_pmtest_en_lowv \ + 0x00008000 + +#define HIB1P2_PMBIST_PARAMETERS1_NA22_M \ + 0x00007FFF + +#define HIB1P2_PMBIST_PARAMETERS1_NA22_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_PMBIST_PARAMETERS2 register. +// +//****************************************************************************** +#define HIB1P2_PMBIST_PARAMETERS2_mem_pmtest_tmux_ctrl_lowv_M \ + 0xFFFFFFFF + +#define HIB1P2_PMBIST_PARAMETERS2_mem_pmtest_tmux_ctrl_lowv_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_PMBIST_PARAMETERS3 register. +// +//****************************************************************************** +#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_spare_lowv_M \ + 0xFFFF0000 + +#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_spare_lowv_S 16 +#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_load_trim_lowv_M \ + 0x0000E000 + +#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_load_trim_lowv_S 13 +#define HIB1P2_PMBIST_PARAMETERS3_mem_rnwell_calib_en_lowv \ + 0x00001000 + +#define HIB1P2_PMBIST_PARAMETERS3_NA23_M \ + 0x00000FFF + +#define HIB1P2_PMBIST_PARAMETERS3_NA23_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS8 register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_en_flash_sup_comp_lowv \ + 0x80000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_high_sup_trim_lowv_M \ + 0x7C000000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_high_sup_trim_lowv_S 26 +#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_low_sup_trim_lowv_M \ + 0x03E00000 + +#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_low_sup_trim_lowv_S 21 +#define HIB1P2_FLASH_DCDC_PARAMETERS8_NA24_M \ + 0x001FFFFF + +#define HIB1P2_FLASH_DCDC_PARAMETERS8_NA24_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_PARAMETERS_OVERRIDE register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_reserved_M \ + 0xFFFFFFC0 + +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_reserved_S 6 +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_subreg_1p2v_lowv_override_ctrl \ + 0x00000020 + +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_subreg_1p8v_lowv_override_ctrl \ + 0x00000010 + +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_ilim_trim_lowv_efc_override_ctrl \ + 0x00000008 + +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_slp_mode_lowv_fsm_override_ctrl \ + 0x00000004 + +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_pwm_mode_lowv_fsm_override_ctrl \ + 0x00000002 + +#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_lowv_fsm_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_FLASH_DCDC_PARAMETERS_OVERRIDE register. +// +//****************************************************************************** +#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_reserved_M \ + 0xFFFFFFFC + +#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_reserved_S 2 +#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_flash_en_lowv_override_ctrl \ + 0x00000002 + +#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_flash_ilim_trim_lowv_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_VTRIM_CFG register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_VTRIM_CFG_reserved_M \ + 0xFF000000 + +#define HIB1P2_DIG_DCDC_VTRIM_CFG_reserved_S 24 +#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_run_vtrim_M \ + 0x00FC0000 + +#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_run_vtrim_S 18 +#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_dslp_vtrim_M \ + 0x0003F000 + +#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_dslp_vtrim_S 12 +#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_lpds_vtrim_M \ + 0x00000FC0 + +#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_lpds_vtrim_S 6 +#define HIB1P2_DIG_DCDC_VTRIM_CFG_Spare_RW_M \ + 0x0000003F + +#define HIB1P2_DIG_DCDC_VTRIM_CFG_Spare_RW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_DIG_DCDC_FSM_PARAMETERS register. +// +//****************************************************************************** +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_reserved_M \ + 0xFFFF8000 + +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_reserved_S 15 +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_cot_to_vtrim_M \ + 0x00007000 + +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_cot_to_vtrim_S 12 +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_vtrim_to_sleep_M \ + 0x00000E00 + +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_vtrim_to_sleep_S 9 +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_sleep_to_vtrim_M \ + 0x000001C0 + +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_sleep_to_vtrim_S 6 +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_vtrim_to_cot_M \ + 0x00000038 + +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_vtrim_to_cot_S 3 +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_cot_to_run_M \ + 0x00000007 + +#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_cot_to_run_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_ANA_DCDC_FSM_PARAMETERS register. +// +//****************************************************************************** +#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_reserved_M \ + 0xFFFFFFF8 + +#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_reserved_S 3 +#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_mem_dcdc_ana_dslp_exit_sleep_to_run_M \ + 0x00000007 + +#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_mem_dcdc_ana_dslp_exit_sleep_to_run_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_SRAM_SKA_LDO_FSM_PARAMETERS register. +// +//****************************************************************************** +#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_reserved_M \ + 0xFFFFFFC0 + +#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_reserved_S 6 +#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_ska_ldo_en_to_sram_ldo_dis_M \ + 0x00000038 + +#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_ska_ldo_en_to_sram_ldo_dis_S 3 +#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_sram_ldo_en_to_ska_ldo_dis_M \ + 0x00000007 + +#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_sram_ldo_en_to_ska_ldo_dis_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG register. +// +//****************************************************************************** +#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_reserved_M \ + 0xFFFFFFF8 + +#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_reserved_S 3 +#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_mem_bgap_duty_cycling_exit_time_M \ + 0x00000007 + +#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_mem_bgap_duty_cycling_exit_time_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_CM_OSC_16M_CONFIG register. +// +//****************************************************************************** +#define HIB1P2_CM_OSC_16M_CONFIG_reserved_M \ + 0xFFFC0000 + +#define HIB1P2_CM_OSC_16M_CONFIG_reserved_S 18 +#define HIB1P2_CM_OSC_16M_CONFIG_cm_clk_good_16m \ + 0x00020000 + +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_en_osc_16m \ + 0x00010000 + +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_trim_M \ + 0x0000FC00 + +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_trim_S 10 +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_spare_M \ + 0x000003F0 + +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_spare_S 4 +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_en_sli_16m \ + 0x00000008 + +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_sli_16m_trim_M \ + 0x00000007 + +#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_sli_16m_trim_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_SOP_SENSE_VALUE register. +// +//****************************************************************************** +#define HIB1P2_SOP_SENSE_VALUE_reserved_M \ + 0xFFFFFF00 + +#define HIB1P2_SOP_SENSE_VALUE_reserved_S 8 +#define HIB1P2_SOP_SENSE_VALUE_sop_sense_value_M \ + 0x000000FF + +#define HIB1P2_SOP_SENSE_VALUE_sop_sense_value_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_RTC_TIMER_LSW_1P2 register. +// +//****************************************************************************** +#define HIB1P2_HIB_RTC_TIMER_LSW_1P2_hib_rtc_timer_lsw_M \ + 0xFFFFFFFF + +#define HIB1P2_HIB_RTC_TIMER_LSW_1P2_hib_rtc_timer_lsw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_RTC_TIMER_MSW_1P2 register. +// +//****************************************************************************** +#define HIB1P2_HIB_RTC_TIMER_MSW_1P2_hib_rtc_timer_msw_M \ + 0x0000FFFF + +#define HIB1P2_HIB_RTC_TIMER_MSW_1P2_hib_rtc_timer_msw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB1P2_BGAP_TRIM_OVERRIDES register. +// +//****************************************************************************** +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_reserved_M \ + 0xFF800000 + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_reserved_S 23 +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_ctrl \ + 0x00400000 + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_M \ + 0x003FC000 + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_S 14 +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_ctrl \ + 0x00002000 + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_M \ + 0x00001FC0 + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_S 6 +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_ctrl \ + 0x00000020 + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_M \ + 0x0000001F + +#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB1P2_EFUSE_READ_REG0 register. +// +//****************************************************************************** +#define HIB1P2_HIB1P2_EFUSE_READ_REG0_FUSEFARM_ROW_12_M \ + 0xFFFFFFFF // Corresponds to ROW_12 of + // FUSEFARM. [7:0] : + // DCDC_DIG_ILIM_TRIM_LOWV(7:0) + // [15:8] : + // DCDC_ANA_ILIM_TRIM_LOWV(7:0) + // [23:16] : + // DCDC_FLASH_ILIM_TRIM_LOWV(7:0) + // [24:24] : DTHE SHA DISABLE + // [25:25] : DTHE DES DISABLE + // [26:26] : DTHE AES DISABLE + // [31:27] : HD_BG_RTRIM (4:0) + +#define HIB1P2_HIB1P2_EFUSE_READ_REG0_FUSEFARM_ROW_12_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB1P2_EFUSE_READ_REG1 register. +// +//****************************************************************************** +#define HIB1P2_HIB1P2_EFUSE_READ_REG1_FUSEFARM_ROW_13_M \ + 0xFFFFFFFF // Corresponds to ROW_13 of the + // FUSEFARM. [7:0] : HD_BG_MAG_TRIM + // (7:0) [14:8] : HD_BG_TEMP_TRIM + // (6:0) [15:15] : GREYOUT ENABLE + // DUTY CYCLING [31:16] : + // Reserved/Checksum + +#define HIB1P2_HIB1P2_EFUSE_READ_REG1_FUSEFARM_ROW_13_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB1P2_POR_TEST_CTRL register. +// +//****************************************************************************** +#define HIB1P2_HIB1P2_POR_TEST_CTRL_reserved_M \ + 0xFFFFFF00 + +#define HIB1P2_HIB1P2_POR_TEST_CTRL_reserved_S 8 +#define HIB1P2_HIB1P2_POR_TEST_CTRL_mem_prcm_por_test_ctrl_M \ + 0x000000FF + +#define HIB1P2_HIB1P2_POR_TEST_CTRL_mem_prcm_por_test_ctrl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG0 register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_reserved_M \ + 0xFFFF0000 + +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_reserved_S 16 +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_time_M \ + 0x0000FF00 + +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_time_S 8 +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_NU1_M \ + 0x000000FE + +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_NU1_S 1 +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_start \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG1 register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_reserved_M \ + 0xFFF00000 + +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_reserved_S 20 +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_fast_calib_count_M \ + 0x000FFFFF + +#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_fast_calib_count_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_CFG2 register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_CFG2_reserved_M \ + 0xFFFFFE00 + +#define HIB1P2_HIB_TIMER_SYNC_CFG2_reserved_S 9 +#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_hib_unload \ + 0x00000100 + +#define HIB1P2_HIB_TIMER_SYNC_CFG2_NU1_M \ + 0x000000FC + +#define HIB1P2_HIB_TIMER_SYNC_CFG2_NU1_S 2 +#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_tsf_adj \ + 0x00000002 + +#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_update_tsf \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_TSF_ADJ_VAL register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_TSF_ADJ_VAL_mem_tsf_adj_val_M \ + 0xFFFFFFFF + +#define HIB1P2_HIB_TIMER_SYNC_TSF_ADJ_VAL_mem_tsf_adj_val_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW_rtc_gts_timestamp_lsw_M \ + 0xFFFFFFFF + +#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW_rtc_gts_timestamp_lsw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_reserved_M \ + 0xFFFF0000 + +#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_reserved_S 16 +#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_rtc_gts_timestamp_msw_M \ + 0x0000FFFF + +#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_rtc_gts_timestamp_msw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW_rtc_wup_timestamp_lsw_M \ + 0xFFFFFFFF + +#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW_rtc_wup_timestamp_lsw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_reserved_M \ + 0xFFFF0000 + +#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_reserved_S 16 +#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_rtc_wup_timestamp_msw_M \ + 0x0000FFFF + +#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_rtc_wup_timestamp_msw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_WAKE_OFFSET_ERR register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_reserved_M \ + 0xFFFFF000 + +#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_reserved_S 12 +#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_wup_offset_error_M \ + 0x00000FFF + +#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_wup_offset_error_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW_tsf_curr_val_lsw_M \ + 0xFFFFFFFF + +#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW_tsf_curr_val_lsw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW register. +// +//****************************************************************************** +#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW_tsf_curr_val_msw_M \ + 0xFFFFFFFF + +#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW_tsf_curr_val_msw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the HIB1P2_O_CM_SPARE register. +// +//****************************************************************************** +#define HIB1P2_CM_SPARE_CM_SPARE_OUT_M \ + 0xFF000000 + +#define HIB1P2_CM_SPARE_CM_SPARE_OUT_S 24 +#define HIB1P2_CM_SPARE_MEM_CM_TEST_CTRL_M \ + 0x00FF0000 + +#define HIB1P2_CM_SPARE_MEM_CM_TEST_CTRL_S 16 +#define HIB1P2_CM_SPARE_MEM_CM_SPARE_M \ + 0x0000FFFF + +#define HIB1P2_CM_SPARE_MEM_CM_SPARE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_PORPOL_SPARE register. +// +//****************************************************************************** +#define HIB1P2_PORPOL_SPARE_MEM_PORPOL_SPARE_M \ + 0xFFFFFFFF + +#define HIB1P2_PORPOL_SPARE_MEM_PORPOL_SPARE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_DIG_DCDC_CLK_CONFIG register. +// +//****************************************************************************** +#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_ENABLE \ + 0x00000100 + +#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_OFF_TIME_M \ + 0x000000F0 + +#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_OFF_TIME_S 4 +#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_ON_TIME_M \ + 0x0000000F + +#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_ANA_DCDC_CLK_CONFIG register. +// +//****************************************************************************** +#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_ENABLE \ + 0x00000100 + +#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_OFF_TIME_M \ + 0x000000F0 + +#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_OFF_TIME_S 4 +#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_ON_TIME_M \ + 0x0000000F + +#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_FLASH_DCDC_CLK_CONFIG register. +// +//****************************************************************************** +#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_ENABLE \ + 0x00000100 + +#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_OFF_TIME_M \ + 0x000000F0 + +#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_OFF_TIME_S 4 +#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_ON_TIME_M \ + 0x0000000F + +#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_PA_DCDC_CLK_CONFIG register. +// +//****************************************************************************** +#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_ENABLE \ + 0x00000100 + +#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_OFF_TIME_M \ + 0x000000F0 + +#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_OFF_TIME_S 4 +#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_ON_TIME_M \ + 0x0000000F + +#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_ON_TIME_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_SLDO_VNWA_OVERRIDE register. +// +//****************************************************************************** +#define HIB1P2_MEM_SLDO_VNWA_OVERRIDE_MEM_SLDO_EN_TOP_VNWA_OVERRIDE_CTRL \ + 0x00000002 + +#define HIB1P2_MEM_SLDO_VNWA_OVERRIDE_MEM_SLDO_EN_TOP_VNWA_OVERRIDE \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE register. +// +//****************************************************************************** +#define HIB1P2_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE_MEM_BGAP_DUTY_CYCLING_OVERRIDE_CTRL \ + 0x00000002 + +#define HIB1P2_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE_MEM_BGAP_DUTY_CYCLING_OVERRIDE \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_HIB_FSM_DEBUG register. +// +//****************************************************************************** +#define HIB1P2_MEM_HIB_FSM_DEBUG_SRAM_PS_M \ + 0x00000700 + +#define HIB1P2_MEM_HIB_FSM_DEBUG_SRAM_PS_S 8 +#define HIB1P2_MEM_HIB_FSM_DEBUG_ANA_DCDC_PS_M \ + 0x000000F0 + +#define HIB1P2_MEM_HIB_FSM_DEBUG_ANA_DCDC_PS_S 4 +#define HIB1P2_MEM_HIB_FSM_DEBUG_DIG_DCDC_PS_M \ + 0x0000000F + +#define HIB1P2_MEM_HIB_FSM_DEBUG_DIG_DCDC_PS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_SLDO_VNWA_SW_CTRL register. +// +//****************************************************************************** +#define HIB1P2_MEM_SLDO_VNWA_SW_CTRL_MEM_SLDO_VNWA_SW_CTRL_M \ + 0x000FFFFF + +#define HIB1P2_MEM_SLDO_VNWA_SW_CTRL_MEM_SLDO_VNWA_SW_CTRL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_SLDO_WEAK_PROCESS register. +// +//****************************************************************************** +#define HIB1P2_MEM_SLDO_WEAK_PROCESS_MEM_SLDO_WEAK_PROCESS \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_PA_DCDC_OV_UV_STATUS register. +// +//****************************************************************************** +#define HIB1P2_MEM_PA_DCDC_OV_UV_STATUS_dcdc_pa_ov_prot_out_lowv \ + 0x00000002 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB1P2_O_MEM_CM_TEST_MODE register. +// +//****************************************************************************** +#define HIB1P2_MEM_CM_TEST_MODE_mem_cm_test_mode \ + 0x00000001 + + + + +#endif // __HW_HIB1P2_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_hib3p3.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_hib3p3.h new file mode 100644 index 00000000..97016891 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_hib3p3.h @@ -0,0 +1,1138 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_HIB3P3_H__ +#define __HW_HIB3P3_H__ + +//***************************************************************************** +// +// The following are defines for the HIB3P3 register offsets. +// +//***************************************************************************** +#define HIB3P3_O_MEM_HIB_REQ 0x00000000 +#define HIB3P3_O_MEM_HIB_RTC_TIMER_ENABLE \ + 0x00000004 + +#define HIB3P3_O_MEM_HIB_RTC_TIMER_RESET \ + 0x00000008 + +#define HIB3P3_O_MEM_HIB_RTC_TIMER_READ \ + 0x0000000C + +#define HIB3P3_O_MEM_HIB_RTC_TIMER_LSW \ + 0x00000010 + +#define HIB3P3_O_MEM_HIB_RTC_TIMER_MSW \ + 0x00000014 + +#define HIB3P3_O_MEM_HIB_RTC_WAKE_EN \ + 0x00000018 + +#define HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF \ + 0x0000001C + +#define HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF \ + 0x00000020 + +#define HIB3P3_O_MEM_INT_OSC_CONF \ + 0x0000002C + +#define HIB3P3_O_MEM_XTAL_OSC_CONF \ + 0x00000034 + +#define HIB3P3_O_MEM_BGAP_PARAMETERS0 \ + 0x00000038 + +#define HIB3P3_O_MEM_BGAP_PARAMETERS1 \ + 0x0000003C + +#define HIB3P3_O_MEM_HIB_DETECTION_STATUS \ + 0x00000040 + +#define HIB3P3_O_MEM_HIB_MISC_CONTROLS \ + 0x00000044 + +#define HIB3P3_O_MEM_HIB_CONFIG 0x00000050 +#define HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE \ + 0x00000054 + +#define HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF \ + 0x00000058 + +#define HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF \ + 0x0000005C + +#define HIB3P3_O_MEM_HIB_UART_CONF \ + 0x00000400 + +#define HIB3P3_O_MEM_GPIO_WAKE_EN \ + 0x00000404 + +#define HIB3P3_O_MEM_GPIO_WAKE_CONF \ + 0x00000408 + +#define HIB3P3_O_MEM_PAD_OEN_RET33_CONF \ + 0x0000040C + +#define HIB3P3_O_MEM_UART_RTS_OEN_RET33_CONF \ + 0x00000410 + +#define HIB3P3_O_MEM_JTAG_CONF 0x00000414 +#define HIB3P3_O_MEM_HIB_REG0 0x00000418 +#define HIB3P3_O_MEM_HIB_REG1 0x0000041C +#define HIB3P3_O_MEM_HIB_REG2 0x00000420 +#define HIB3P3_O_MEM_HIB_REG3 0x00000424 +#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG0 \ + 0x0000045C + +#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG1 \ + 0x00000460 + +#define HIB3P3_O_MEM_HIB_MISC_CONFIG \ + 0x00000464 + +#define HIB3P3_O_MEM_HIB_WAKE_STATUS \ + 0x00000468 + +#define HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL \ + 0x0000046C + +#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG2 \ + 0x00000470 + +#define HIB3P3_O_HIBANA_SPARE_LOWV \ + 0x00000474 + +#define HIB3P3_O_HIB_TMUX_CTRL 0x00000478 +#define HIB3P3_O_HIB_1P2_1P8_LDO_TRIM \ + 0x0000047C + +#define HIB3P3_O_HIB_COMP_TRIM 0x00000480 +#define HIB3P3_O_HIB_EN_TS 0x00000484 +#define HIB3P3_O_HIB_1P8V_DET_EN \ + 0x00000488 + +#define HIB3P3_O_HIB_VBAT_MON_EN \ + 0x0000048C + +#define HIB3P3_O_HIB_NHIB_ENABLE \ + 0x00000490 + +#define HIB3P3_O_HIB_UART_RTS_SW_ENABLE \ + 0x00000494 + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_REQ register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_REQ_reserved_M \ + 0xFFFFFE00 + +#define HIB3P3_MEM_HIB_REQ_reserved_S 9 +#define HIB3P3_MEM_HIB_REQ_NU1_M \ + 0x000001FC + +#define HIB3P3_MEM_HIB_REQ_NU1_S 2 +#define HIB3P3_MEM_HIB_REQ_mem_hib_clk_disable \ + 0x00000002 // 1 - Specifies that the Hiberante + // mode is without clocks ; 0 - + // Specified that the Hibernate mode + // is with clocks This register will + // be reset during Hibernate + // -WO-Clks mode (but not during + // Hibernate-W-Clks mode). + +#define HIB3P3_MEM_HIB_REQ_mem_hib_req \ + 0x00000001 // 1 - Request for hibernate mode + // (This is an auto-clear bit) ; 0 - + // Donot request for hibernate mode + // This register will be reset + // during Hibernate -WO-Clks mode + // (but not during Hibernate-W-Clks + // mode). + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_TIMER_ENABLE register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_reserved_S 1 +#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_mem_hib_rtc_timer_enable \ + 0x00000001 // 1 - Enable the RTC timer to + // start running ; 0 - Keep the RTC + // timer disabled This register will + // be reset during Hibernate + // -WO-Clks mode (but not during + // Hibernate-W-Clks mode). + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_TIMER_RESET register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_reserved_S 1 +#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_mem_hib_rtc_timer_reset \ + 0x00000001 // 1 - Reset the RTC timer ; 0 - + // Donot reset the RTC timer. This + // is an auto-clear bit. This + // register will be reset during + // Hibernate -WO-Clks mode (but not + // during Hibernate-W-Clks mode). + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_TIMER_READ register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_TIMER_READ_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_MEM_HIB_RTC_TIMER_READ_reserved_S 1 +#define HIB3P3_MEM_HIB_RTC_TIMER_READ_mem_hib_rtc_timer_read \ + 0x00000001 // 1 - Latch the running RTC timer + // into local registers. After + // programming this bit to 1, the + // F/w can read the latched RTC + // timer values from + // MEM_HIB_RTC_TIMER_LSW and + // MEM_HIB_RTC_TIMER_MSW. Before the + // F/w (APPS or NWP) wants to read + // the RTC-Timer, it has to program + // this bit to 1, then only read the + // MSW and LSW values. This is an + // auto-clear bit. This register + // will be reset during Hibernate + // -WO-Clks mode (but not during + // Hibernate-W-Clks mode). + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_TIMER_LSW register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_TIMER_LSW_hib_rtc_timer_lsw_M \ + 0xFFFFFFFF // Lower 32b value of the latched + // RTC-Timer. + +#define HIB3P3_MEM_HIB_RTC_TIMER_LSW_hib_rtc_timer_lsw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_TIMER_MSW register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_reserved_M \ + 0xFFFF0000 + +#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_reserved_S 16 +#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_hib_rtc_timer_msw_M \ + 0x0000FFFF // Upper 32b value of the latched + // RTC-Timer. + +#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_hib_rtc_timer_msw_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_WAKE_EN register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_WAKE_EN_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_MEM_HIB_RTC_WAKE_EN_reserved_S 1 +#define HIB3P3_MEM_HIB_RTC_WAKE_EN_mem_hib_rtc_wake_en \ + 0x00000001 // 1 - Enable the RTC timer based + // wakeup during Hibernate mode ; 0 + // - Disable the RTC timer based + // wakeup during Hibernate mode This + // register will be reset during + // Hibernate-WO-Clks mode (but not + // during Hibernate-W-Clks mode). + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_WAKE_LSW_CONF_mem_hib_rtc_wake_lsw_conf_M \ + 0xFFFFFFFF // Configuration for RTC-Timer + // Wakeup (Lower 32b word) + +#define HIB3P3_MEM_HIB_RTC_WAKE_LSW_CONF_mem_hib_rtc_wake_lsw_conf_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_reserved_M \ + 0xFFFF0000 + +#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_reserved_S 16 +#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_mem_hib_rtc_wake_msw_conf_M \ + 0x0000FFFF // Configuration for RTC-Timer + // Wakeup (Upper 16b word) + +#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_mem_hib_rtc_wake_msw_conf_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_INT_OSC_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_INT_OSC_CONF_reserved_M \ + 0xFFFF0000 + +#define HIB3P3_MEM_INT_OSC_CONF_reserved_S 16 +#define HIB3P3_MEM_INT_OSC_CONF_cm_clk_good_32k_int \ + 0x00008000 // 1 - Internal 32kHz Oscillator is + // valid ; 0 - Internal 32k + // oscillator clk is not valid + +#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_spare_M \ + 0x00007E00 + +#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_spare_S 9 +#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_en_intosc_32k_override_ctrl \ + 0x00000100 // When 1, the INT_32K_OSC_EN comes + // from bit [0] of this register, + // else comes from the FSM. This + // register will be reset during + // Hibernate-WO-Clks mode (but not + // during Hibernate-W-Clks mode) + +#define HIB3P3_MEM_INT_OSC_CONF_NU1 \ + 0x00000080 + +#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_trim_M \ + 0x0000007E + +#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_trim_S 1 +#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_en_intosc_32k \ + 0x00000001 // Override value for INT_OSC_EN. + // Applicable only when bit [3] of + // this register is set to 1. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_XTAL_OSC_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_XTAL_OSC_CONF_reserved_M \ + 0xFFF00000 + +#define HIB3P3_MEM_XTAL_OSC_CONF_reserved_S 20 +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_sli_32k_override_ctrl \ + 0x00080000 // When 1, the SLICER_EN comes from + // bit [10] of this register, else + // comes from the FSM. + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_xtal_32k_override_ctrl \ + 0x00040000 // When 1, the XTAL_EN comes from + // bit [0] of this register, else + // comes from the FSM. + +#define HIB3P3_MEM_XTAL_OSC_CONF_cm_clk_good_xtal \ + 0x00020000 // 1 - XTAL Clk is good ; 0 - XTAL + // Clk is yet to be valid. + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_xtal_trim_M \ + 0x0001F800 + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_xtal_trim_S 11 +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_sli_32k \ + 0x00000400 // SLICER_EN Override value : + // Applicable only when bit [19] of + // this register is set to 1. + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_sli_32k_trim_M \ + 0x00000380 + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_sli_32k_trim_S 7 +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_fref_32k_slicer_itrim_M \ + 0x00000070 + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_fref_32k_slicer_itrim_S 4 +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_fref_32k_slicer \ + 0x00000008 + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_input_sense_M \ + 0x00000006 + +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_input_sense_S 1 +#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_xtal_32k \ + 0x00000001 // XTAL_EN Override value : + // Applicable only when bit [18] of + // this register is set to 1. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_BGAP_PARAMETERS0 register. +// +//****************************************************************************** +#define HIB3P3_MEM_BGAP_PARAMETERS0_reserved_M \ + 0xFFF80000 + +#define HIB3P3_MEM_BGAP_PARAMETERS0_reserved_S 19 +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_en_seq \ + 0x00040000 + +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_vbok4bg_comp_trim_M \ + 0x0001C000 + +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_vbok4bg_comp_trim_S 14 +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbat_ok_4bg \ + 0x00001000 + +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbok4bg_comp \ + 0x00000800 + +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbok4bg_comp_ref \ + 0x00000400 + +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_spare_M \ + 0x000003FF + +#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_spare_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_BGAP_PARAMETERS1 register. +// +//****************************************************************************** +#define HIB3P3_MEM_BGAP_PARAMETERS1_reserved_M \ + 0xE0000000 + +#define HIB3P3_MEM_BGAP_PARAMETERS1_reserved_S 29 +#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_act_iref_itrim_M \ + 0x1F000000 + +#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_act_iref_itrim_S 24 +#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_act_iref \ + 0x00000008 + +#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_v2i \ + 0x00000004 + +#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_cap_sw \ + 0x00000002 + +#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_DETECTION_STATUS register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_DETECTION_STATUS_reserved_M \ + 0xFFFFFF80 + +#define HIB3P3_MEM_HIB_DETECTION_STATUS_reserved_S 7 +#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_forced_ana_status \ + 0x00000040 // 1 - 1.8 V supply forced mode. + +#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_forced_flash_status \ + 0x00000004 // 1 - 3.3 V supply forced mode for + // Flash supply + +#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_ext_clk_det_out_status \ + 0x00000002 // 1 - Forced clock mode + +#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_xtal_det_out_status \ + 0x00000001 // 1 - XTAL clock mode + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_MISC_CONTROLS register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_MISC_CONTROLS_reserved_M \ + 0xFFFFF800 + +#define HIB3P3_MEM_HIB_MISC_CONTROLS_reserved_S 11 +#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_pok_por_comp \ + 0x00000400 + +#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_pok_por_comp_ref \ + 0x00000200 + +#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_pok_por_comp_trim_M \ + 0x000001C0 + +#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_pok_por_comp_trim_S 6 +#define HIB3P3_MEM_HIB_MISC_CONTROLS_NU1 \ + 0x00000020 + +#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_flash_det_en \ + 0x00000010 + +#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_tmux \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_CONFIG register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_CONFIG_TOP_MUX_CTRL_SOP_SPIO_M \ + 0xFF000000 + +#define HIB3P3_MEM_HIB_CONFIG_TOP_MUX_CTRL_SOP_SPIO_S 24 +#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED3 \ + 0x00080000 // 1 - Enable VDD_FLASH_INDP_PAD + // for digital path (SHARED4) ; 0 - + // Disable VDD_FLASH_INDP_PAD for + // digital path (SHARED4) ; Before + // programming this bit to 1, ensure + // that the device is in FORCED 3.3 + // supply Mode, which can be + // inferred from the register : + // MEM_HIB_DETECTION_STATUS : 0x0040 + +#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED2 \ + 0x00040000 // 1 - Enable the + // VDD_FB_GPIO_MUX_PAD for digital + // path (SHARED3) ; 0 - Disable the + // VDD_FB_GPIO_MUX_PAD for digital + // path (SHARED3) ; This pin can be + // used only in modes other than + // SOP("111") + +#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED1 \ + 0x00020000 // 1 - Enable the PM_TEST_PAD for + // digital GPIO path (SHARED2) ; 0 - + // Disable the PM_TEST_PAD for + // digital GPIO path (SHARED2) This + // pin can be used for digital only + // in modes other then SOP-111 + +#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED0 \ + 0x00010000 // 1 - Enable the XTAL_N pin + // digital GPIO path (SHARED1); 0 - + // Disable the XTAL_N pin digital + // GPIO path (SHARED1). Before + // programming this bit to 1, ensure + // that the device is in FORCED CLK + // Mode, which can inferred from the + // register : + // MEM_HIB_DETECTION_STATUS : + // 0x0040. + +#define HIB3P3_MEM_HIB_CONFIG_mem_hib_xtal_enable \ + 0x00000100 // 1 - Enable the XTAL Clock ; 0 - + // Donot enable the XTAL Clock. This + // bit has to be programmed to 1 (by + // APPS Devinit F/w), during exit + // from OFF or Hib_wo_clks modes, + // after checking if the slow_clk + // mode is XTAL_CLK mode. Once + // enabled the XTAL will be disabled + // only after entering HIB_WO_CLKS + // mode. This register will be reset + // during Hibernate -WO-Clks mode + // (but not during Hibernate-W-Clks + // mode). + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_IRQ_ENABLE_HIB_RTC_IRQ_ENABLE \ + 0x00000001 // 1 - Enable the HIB RTC - IRQ ; 0 + // - Disable the HIB RTC - IRQ + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_IRQ_LSW_CONF_HIB_RTC_IRQ_LSW_CONF_M \ + 0xFFFFFFFF // Configuration for LSW of the + // RTC-Timestamp at which interrupt + // need to be generated + +#define HIB3P3_MEM_HIB_RTC_IRQ_LSW_CONF_HIB_RTC_IRQ_LSW_CONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_RTC_IRQ_MSW_CONF_HIB_RTC_IRQ_MSW_CONF_M \ + 0x0000FFFF // Configuration for MSW of thr + // RTC-Timestamp at which the + // interrupt need to be generated + +#define HIB3P3_MEM_HIB_RTC_IRQ_MSW_CONF_HIB_RTC_IRQ_MSW_CONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_UART_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_UART_CONF_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_MEM_HIB_UART_CONF_reserved_S 1 +#define HIB3P3_MEM_HIB_UART_CONF_mem_hib_uart_wake_en \ + 0x00000001 // 1 - Enable the UART-Autonomous + // mode wakeup during Hibernate mode + // ; This is an auto-clear bit, once + // programmed to 1, it will latched + // into an internal register which + // remain asserted until the + // Hib-wakeup is initiated. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_GPIO_WAKE_EN register. +// +//****************************************************************************** +#define HIB3P3_MEM_GPIO_WAKE_EN_reserved_M \ + 0xFFFFFF00 + +#define HIB3P3_MEM_GPIO_WAKE_EN_reserved_S 8 +#define HIB3P3_MEM_GPIO_WAKE_EN_mem_gpio_wake_en_M \ + 0x000000FF // 1 - Enable the GPIO-Autonomous + // mode wakeup during Hibernate mode + // ; This is an auto-clear bit, once + // programmed to 1, it will latched + // into an internal register which + // remain asserted until the + // Hib-wakeup is initiated. + +#define HIB3P3_MEM_GPIO_WAKE_EN_mem_gpio_wake_en_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_GPIO_WAKE_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_GPIO_WAKE_CONF_reserved_M \ + 0xFFFF0000 + +#define HIB3P3_MEM_GPIO_WAKE_CONF_reserved_S 16 +#define HIB3P3_MEM_GPIO_WAKE_CONF_mem_gpio_wake_conf_M \ + 0x0000FFFF // Configuration to say whether the + // GPIO wakeup has to happen on + // Level0 or falling-edge for the + // given group. “00” – Level0 “01” – + // Level1 “10”- Fall-edge “11”- + // Rise-edge [1:0] – Conf for GPIO0 + // [3:2] – Conf for GPIO1 [5:4] – + // Conf for GPIO2 [7:6] – Conf for + // GPIO3 [9:8] – Conf for GPIO4 + // [11:10] – Conf for GPIO5 [13:12] + // – Conf for GPIO6 + +#define HIB3P3_MEM_GPIO_WAKE_CONF_mem_gpio_wake_conf_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_PAD_OEN_RET33_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_PAD_OEN_RET33_CONF_mem_pad_oen_ret33_override_ctrl \ + 0x00000004 // 1 - Override the OEN33 and RET33 + // controls of GPIOs during + // SOP-Bootdebug mode ; 0 - Donot + // override the OEN33 and RET33 + // controls of GPIOs during + // SOP-Bootdebug mode + +#define HIB3P3_MEM_PAD_OEN_RET33_CONF_PAD_OEN33_CONF \ + 0x00000002 + +#define HIB3P3_MEM_PAD_OEN_RET33_CONF_PAD_RET33_CONF \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_UART_RTS_OEN_RET33_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_mem_uart_nrts_oen_ret33_override_ctrl \ + 0x00000004 // 1 - Override the OEN33 and RET33 + // controls of UART NRTS GPIO during + // SOP-Bootdebug mode ; 0 - Donot + // override the OEN33 and RET33 + // controls of UART NRTS GPIO during + // SOP-Bootdebug mode + +#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_PAD_UART_RTS_OEN33_CONF \ + 0x00000002 + +#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_PAD_UART_RTS_RET33_CONF \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_JTAG_CONF register. +// +//****************************************************************************** +#define HIB3P3_MEM_JTAG_CONF_mem_jtag1_oen_ret33_override_ctrl \ + 0x00000200 + +#define HIB3P3_MEM_JTAG_CONF_mem_jtag0_oen_ret33_override_ctrl \ + 0x00000100 + +#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG1_RTS_OEN33_CONF \ + 0x00000008 + +#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG1_RTS_RET33_CONF \ + 0x00000004 + +#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG0_RTS_OEN33_CONF \ + 0x00000002 + +#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG0_RTS_RET33_CONF \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_REG0 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_REG0_mem_hib_reg0_M \ + 0xFFFFFFFF + +#define HIB3P3_MEM_HIB_REG0_mem_hib_reg0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_REG1 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_REG1_mem_hib_reg1_M \ + 0xFFFFFFFF + +#define HIB3P3_MEM_HIB_REG1_mem_hib_reg1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_REG2 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_REG2_mem_hib_reg2_M \ + 0xFFFFFFFF + +#define HIB3P3_MEM_HIB_REG2_mem_hib_reg2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_REG3 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_REG3_mem_hib_reg3_M \ + 0xFFFFFFFF + +#define HIB3P3_MEM_HIB_REG3_mem_hib_reg3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_SEQUENCER_CFG0 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev0_to_ev1_time_M \ + 0xFFFF0000 // Configuration for the number of + // slow-clks between de-assertion of + // EN_BG_3P3V to assertion of + // EN_BG_3P3V + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev0_to_ev1_time_S 16 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_NU1 \ + 0x00008000 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev3_to_ev4_time_M \ + 0x00006000 // Configuration for the number of + // slow-clks between assertion of + // EN_COMP_3P3V and assertion of + // EN_COMP_LATCH_3P3V + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev3_to_ev4_time_S 13 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev2_to_ev3_time_M \ + 0x00001800 // Configuration for the number of + // slow-clks between assertion of + // (EN_CAP_SW_3P3V,EN_COMP_REF) and + // assertion of (EN_COMP_3P3V) + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev2_to_ev3_time_S 11 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev1_to_ev2_time_M \ + 0x00000600 // Configuration for the number of + // slow-clks between assertion of + // (EN_BG_3P3V) and assertion of + // (EN_CAP_SW_3P3V, + // EN_COMP_REF_3P3V) + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev1_to_ev2_time_S 9 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_crude_ref_comp \ + 0x00000100 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_vbok4bg_ref_override_ctrl \ + 0x00000080 // 1 - EN_VBOK4BG_REF comes from + // bit[10] of the register + // MEM_BGAP_PARAMETERS0 [0x0038]. 0 + // - EN_VBOK4BG_REF comes directly + // from the Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_vbok4bg_comp_override_ctrl \ + 0x00000040 // 1 - EN_VBOK4BG comes from + // bit[11] of the register + // MEM_BGAP_PARAMETERS0 [0x0038]. 0 + // - EN_VBOK4BG comes directly from + // the Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_v2i_override_ctrl \ + 0x00000020 // 1 - EN_V2I comes from bit[2] of + // the register MEM_BGAP_PARAMETERS1 + // [0x003C]. 0 - EN_V2I comes + // directly from the Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_por_comp_ref_override_ctrl \ + 0x00000010 // 1 - EN_POR_COMP_REF comes from + // bit[9] of the register + // MEM_HIB_MISC_CONTROLS [0x0044]. 0 + // - EN_POR_COMP_REF comes directly + // from the Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_por_comp_override_ctrl \ + 0x00000008 // 1 - EN_POR_COMP comes from + // bit[10] of the register + // MEM_HIB_MISC_CONTROLS [0x044]. 0 + // - EN_POR_COMP comes directly from + // the Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_cap_sw_override_ctrl \ + 0x00000004 // 1 - EN_CAP_SW comes from bit[1] + // of the register + // MEM_BGAP_PARAMETERS1 [0x003C]. 0 + // - EN_CAP_SW comes directly from + // Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bg_override_ctrl \ + 0x00000002 // 1 - EN_BGAP comes from bit[0] of + // the register MEM_BGAP_PARAMETERS1 + // [0x003C]. 0 - EN_BGAP comes + // directly from Hib-Sequencer. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_act_iref_override_ctrl \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_SEQUENCER_CFG1 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_reserved_M \ + 0xFFFF0000 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_reserved_S 16 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_ev5_to_ev6_time_M \ + 0x0000C000 // Configuration for number of + // slow-clks between de-assertion of + // EN_COMP_LATCH and assertion of + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_ev5_to_ev6_time_S 14 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev1_to_ev2_time_M \ + 0x00003000 // Configuration for number of + // slow-clks between assertion of + // EN_COMP_REF to assertion of + // EN_COMP during HIB-Exit + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev1_to_ev2_time_S 12 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_ev1_time_M \ + 0x00000C00 // TBD + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_ev1_time_S 10 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_active_M \ + 0x00000300 // Configuration in number of + // slow-clks between assertion of + // (EN_BGAP_3P3V, EN_CAP_SW_3P3V, + // EN_ACT_IREF_3P3V, EN_COMP_REF) to + // assertion of EN_COMP_3P3V + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_active_S 8 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_active_to_bdc_ev1_to_bdc_ev0_time_M \ + 0x000000C0 // Configuration in number of + // slow-clks between de-assertion of + // (EN_COMP_3P3V, EN_COMP_REF_3P3V, + // EN_ACT_IREF_3P3V, EN_CAP_SW_3P3V) + // to deassertion of EN_BGAP_3P3V. + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_active_to_bdc_ev1_to_bdc_ev0_time_S 6 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_NU1_M \ + 0x0000003F + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_NU1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_MISC_CONFIG register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_MISC_CONFIG_mem_en_pll_untrim_current \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_WAKE_STATUS register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_src_M \ + 0x0000001E // "0100" - GPIO ; "0010" - RTC ; + // "0001" - UART Others - Reserved + +#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_src_S 1 +#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_status \ + 0x00000001 // 1 - Wake from Hibernate ; 0 - + // Wake from OFF + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_LPDS_GPIO_SEL_HIB_LPDS_GPIO_SEL_M \ + 0x00000007 + +#define HIB3P3_MEM_HIB_LPDS_GPIO_SEL_HIB_LPDS_GPIO_SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_MEM_HIB_SEQUENCER_CFG2 register. +// +//****************************************************************************** +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_reserved_M \ + 0xFFFFF800 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_reserved_S 11 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_active_to_bdc_ev0_to_active_to_bdc_ev1_time_M \ + 0x00000600 // Deassertion of EN_COMP_LATCH_3P3 + // to deassertion of (EN_COMP_3P3, + // EN_COMP_REF_3P3, EN_ACT_IREF_3P3, + // EN_CAP_SW_3P3) + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_active_to_bdc_ev0_to_active_to_bdc_ev1_time_S 9 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev4_to_ev5_time_M \ + 0x000001C0 // Assertion of EN_COMP_LATCH_3P3 + // to deassertion of + // EN_COMP_LATCH_3P3 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev4_to_ev5_time_S 6 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev6_to_ev7_time_M \ + 0x00000030 // Deassertion of (EN_CAP_SW_3P3, + // EN_COMP_REF_3P3, EN_COMP_3P3, + // EN_COMP_OUT_LATCH_3P3) to + // deassertion of EN_BGAP_3P3 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev6_to_ev7_time_S 4 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_to_active_ev1_to_ev2_time_M \ + 0x0000000C // Assertion of EN_COMP_3P3 to + // assertion of EN_COMPOUT_LATCH_3P3 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_to_active_ev1_to_ev2_time_S 2 +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_hib_to_active_ev2_to_ev3_time_M \ + 0x00000003 // Assertion of EN_COMP_3P3 to + // assertion of EN_COMPOUT_LATCH_3P3 + +#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_hib_to_active_ev2_to_ev3_time_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIBANA_SPARE_LOWV register. +// +//****************************************************************************** +#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare1_M \ + 0xFFC00000 + +#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare1_S 22 +#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare0_M \ + 0x0001FFFF + +#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_TMUX_CTRL register. +// +//****************************************************************************** +#define HIB3P3_HIB_TMUX_CTRL_reserved_M \ + 0xFFFFFC00 + +#define HIB3P3_HIB_TMUX_CTRL_reserved_S 10 +#define HIB3P3_HIB_TMUX_CTRL_mem_hd_tmux_cntrl_M \ + 0x000003FF + +#define HIB3P3_HIB_TMUX_CTRL_mem_hd_tmux_cntrl_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_1P2_1P8_LDO_TRIM register. +// +//****************************************************************************** +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_reserved_M \ + 0xFFFFF000 + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_reserved_S 12 +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_en_override_ctrl \ + 0x00000800 + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_en_override_ctrl \ + 0x00000400 + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_en_override \ + 0x00000200 + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_en_override \ + 0x00000100 + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_vtrim_M \ + 0x000000F0 + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_vtrim_S 4 +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_vtrim_M \ + 0x0000000F + +#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_vtrim_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_COMP_TRIM register. +// +//****************************************************************************** +#define HIB3P3_HIB_COMP_TRIM_reserved_M \ + 0xFFFFFFF8 + +#define HIB3P3_HIB_COMP_TRIM_reserved_S 3 +#define HIB3P3_HIB_COMP_TRIM_mem_hd_comp_trim_M \ + 0x00000007 + +#define HIB3P3_HIB_COMP_TRIM_mem_hd_comp_trim_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_EN_TS register. +// +//****************************************************************************** +#define HIB3P3_HIB_EN_TS_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_HIB_EN_TS_reserved_S 1 +#define HIB3P3_HIB_EN_TS_mem_hd_en_ts \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_1P8V_DET_EN register. +// +//****************************************************************************** +#define HIB3P3_HIB_1P8V_DET_EN_reserved_M \ + 0xFFFFFFFE + +#define HIB3P3_HIB_1P8V_DET_EN_reserved_S 1 +#define HIB3P3_HIB_1P8V_DET_EN_mem_hib_1p8v_det_en \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_VBAT_MON_EN register. +// +//****************************************************************************** +#define HIB3P3_HIB_VBAT_MON_EN_reserved_M \ + 0xFFFFFFFC + +#define HIB3P3_HIB_VBAT_MON_EN_reserved_S 2 +#define HIB3P3_HIB_VBAT_MON_EN_mem_hib_vbat_mon_del_en \ + 0x00000002 + +#define HIB3P3_HIB_VBAT_MON_EN_mem_hib_vbat_mon_en \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_NHIB_ENABLE register. +// +//****************************************************************************** +#define HIB3P3_HIB_NHIB_ENABLE_mem_hib_nhib_enable \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// HIB3P3_O_HIB_UART_RTS_SW_ENABLE register. +// +//****************************************************************************** +#define HIB3P3_HIB_UART_RTS_SW_ENABLE_mem_hib_uart_rts_sw_enable \ + 0x00000001 + + + + +#endif // __HW_HIB3P3_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_i2c.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_i2c.h new file mode 100644 index 00000000..17536d3e --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_i2c.h @@ -0,0 +1,503 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_I2C_H__ +#define __HW_I2C_H__ + +//***************************************************************************** +// +// The following are defines for the I2C register offsets. +// +//***************************************************************************** +#define I2C_O_MSA 0x00000000 +#define I2C_O_MCS 0x00000004 +#define I2C_O_MDR 0x00000008 +#define I2C_O_MTPR 0x0000000C +#define I2C_O_MIMR 0x00000010 +#define I2C_O_MRIS 0x00000014 +#define I2C_O_MMIS 0x00000018 +#define I2C_O_MICR 0x0000001C +#define I2C_O_MCR 0x00000020 +#define I2C_O_MCLKOCNT 0x00000024 +#define I2C_O_MBMON 0x0000002C +#define I2C_O_MBLEN 0x00000030 +#define I2C_O_MBCNT 0x00000034 +#define I2C_O_SOAR 0x00000800 +#define I2C_O_SCSR 0x00000804 +#define I2C_O_SDR 0x00000808 +#define I2C_O_SIMR 0x0000080C +#define I2C_O_SRIS 0x00000810 +#define I2C_O_SMIS 0x00000814 +#define I2C_O_SICR 0x00000818 +#define I2C_O_SOAR2 0x0000081C +#define I2C_O_SACKCTL 0x00000820 +#define I2C_O_FIFODATA 0x00000F00 +#define I2C_O_FIFOCTL 0x00000F04 +#define I2C_O_FIFOSTATUS 0x00000F08 +#define I2C_O_OBSMUXSEL0 0x00000F80 +#define I2C_O_OBSMUXSEL1 0x00000F84 +#define I2C_O_MUXROUTE 0x00000F88 +#define I2C_O_PV 0x00000FB0 +#define I2C_O_PP 0x00000FC0 +#define I2C_O_PC 0x00000FC4 +#define I2C_O_CC 0x00000FC8 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MSA register. +// +//****************************************************************************** +#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address +#define I2C_MSA_SA_S 1 +#define I2C_MSA_RS 0x00000001 // Receive not send +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCS register. +// +//****************************************************************************** +#define I2C_MCS_ACTDMARX 0x80000000 // DMA RX Active Status +#define I2C_MCS_ACTDMATX 0x40000000 // DMA TX Active Status +#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error +#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy +#define I2C_MCS_IDLE 0x00000020 // I2C Idle +#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost +#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable +#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address +#define I2C_MCS_ERROR 0x00000002 // Error +#define I2C_MCS_BUSY 0x00000001 // I2C Busy +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MDR register. +// +//****************************************************************************** +#define I2C_MDR_DATA_M 0x000000FF // Data Transferred +#define I2C_MDR_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MTPR register. +// +//****************************************************************************** +#define I2C_MTPR_HS 0x00000080 // High-Speed Enable +#define I2C_MTPR_TPR_M 0x0000007F // SCL Clock Period +#define I2C_MTPR_TPR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MIMR register. +// +//****************************************************************************** +#define I2C_MIMR_RXFFIM 0x00000800 // Receive FIFO Full Interrupt Mask +#define I2C_MIMR_TXFEIM 0x00000400 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_MIMR_RXIM 0x00000200 // Receive FIFO Request Interrupt + // Mask +#define I2C_MIMR_TXIM 0x00000100 // Transmit FIFO Request Interrupt + // Mask +#define I2C_MIMR_ARBLOSTIM 0x00000080 // Arbitration Lost Interrupt Mask +#define I2C_MIMR_STOPIM 0x00000040 // STOP Detection Interrupt Mask +#define I2C_MIMR_STARTIM 0x00000020 // START Detection Interrupt Mask +#define I2C_MIMR_NACKIM 0x00000010 // Address/Data NACK Interrupt Mask +#define I2C_MIMR_DMATXIM 0x00000008 // Transmit DMA Interrupt Mask +#define I2C_MIMR_DMARXIM 0x00000004 // Receive DMA Interrupt Mask +#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask +#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MRIS register. +// +//****************************************************************************** +#define I2C_MRIS_RXFFRIS 0x00000800 // Receive FIFO Full Raw Interrupt + // Status +#define I2C_MRIS_TXFERIS 0x00000400 // Transmit FIFO Empty Raw + // Interrupt Status +#define I2C_MRIS_RXRIS 0x00000200 // Receive FIFO Request Raw + // Interrupt Status +#define I2C_MRIS_TXRIS 0x00000100 // Transmit Request Raw Interrupt + // Status +#define I2C_MRIS_ARBLOSTRIS 0x00000080 // Arbitration Lost Raw Interrupt + // Status +#define I2C_MRIS_STOPRIS 0x00000040 // STOP Detection Raw Interrupt + // Status +#define I2C_MRIS_STARTRIS 0x00000020 // START Detection Raw Interrupt + // Status +#define I2C_MRIS_NACKRIS 0x00000010 // Address/Data NACK Raw Interrupt + // Status +#define I2C_MRIS_DMATXRIS 0x00000008 // Transmit DMA Raw Interrupt + // Status +#define I2C_MRIS_DMARXRIS 0x00000004 // Receive DMA Raw Interrupt Status +#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt + // Status +#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MMIS register. +// +//****************************************************************************** +#define I2C_MMIS_RXFFMIS 0x00000800 // Receive FIFO Full Interrupt Mask +#define I2C_MMIS_TXFEMIS 0x00000400 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_MMIS_RXMIS 0x00000200 // Receive FIFO Request Interrupt + // Mask +#define I2C_MMIS_TXMIS 0x00000100 // Transmit Request Interrupt Mask +#define I2C_MMIS_ARBLOSTMIS 0x00000080 // Arbitration Lost Interrupt Mask +#define I2C_MMIS_STOPMIS 0x00000040 // STOP Detection Interrupt Mask +#define I2C_MMIS_STARTMIS 0x00000020 // START Detection Interrupt Mask +#define I2C_MMIS_NACKMIS 0x00000010 // Address/Data NACK Interrupt Mask +#define I2C_MMIS_DMATXMIS 0x00000008 // Transmit DMA Interrupt Status +#define I2C_MMIS_DMARXMIS 0x00000004 // Receive DMA Interrupt Status +#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt + // Status +#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MICR register. +// +//****************************************************************************** +#define I2C_MICR_RXFFIC 0x00000800 // Receive FIFO Full Interrupt + // Clear +#define I2C_MICR_TXFEIC 0x00000400 // Transmit FIFO Empty Interrupt + // Clear +#define I2C_MICR_RXIC 0x00000200 // Receive FIFO Request Interrupt + // Clear +#define I2C_MICR_TXIC 0x00000100 // Transmit FIFO Request Interrupt + // Clear +#define I2C_MICR_ARBLOSTIC 0x00000080 // Arbitration Lost Interrupt Clear +#define I2C_MICR_STOPIC 0x00000040 // STOP Detection Interrupt Clear +#define I2C_MICR_STARTIC 0x00000020 // START Detection Interrupt Clear +#define I2C_MICR_NACKIC 0x00000010 // Address/Data NACK Interrupt + // Clear +#define I2C_MICR_DMATXIC 0x00000008 // Transmit DMA Interrupt Clear +#define I2C_MICR_DMARXIC 0x00000004 // Receive DMA Interrupt Clear +#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear +#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCR register. +// +//****************************************************************************** +#define I2C_MCR_MMD 0x00000040 // Multi-master Disable +#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable +#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable +#define I2C_MCR_LPBK 0x00000001 // I2C Loopback +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MCLKOCNT register. +// +//****************************************************************************** +#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count +#define I2C_MCLKOCNT_CNTL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MBMON register. +// +//****************************************************************************** +#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status +#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MBLEN register. +// +//****************************************************************************** +#define I2C_MBLEN_CNTL_M 0x000000FF // I2C Burst Length +#define I2C_MBLEN_CNTL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MBCNT register. +// +//****************************************************************************** +#define I2C_MBCNT_CNTL_M 0x000000FF // I2C Master Burst Count +#define I2C_MBCNT_CNTL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR register. +// +//****************************************************************************** +#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address +#define I2C_SOAR_OAR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SCSR register. +// +//****************************************************************************** +#define I2C_SCSR_ACTDMARX 0x80000000 // DMA RX Active Status +#define I2C_SCSR_ACTDMATX 0x40000000 // DMA TX Active Status +#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write +#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status +#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched +#define I2C_SCSR_FBR 0x00000004 // First Byte Received +#define I2C_SCSR_TREQ 0x00000002 // Transmit Request +#define I2C_SCSR_DA 0x00000001 // Device Active +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SDR register. +// +//****************************************************************************** +#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer +#define I2C_SDR_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SIMR register. +// +//****************************************************************************** +#define I2C_SIMR_IM 0x00000100 // Interrupt Mask +#define I2C_SIMR_TXFEIM 0x00000080 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_SIMR_RXIM 0x00000040 // Receive FIFO Request Interrupt + // Mask +#define I2C_SIMR_TXIM 0x00000020 // Transmit FIFO Request Interrupt + // Mask +#define I2C_SIMR_DMATXIM 0x00000010 // Transmit DMA Interrupt Mask +#define I2C_SIMR_DMARXIM 0x00000008 // Receive DMA Interrupt Mask +#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask +#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask +#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SRIS register. +// +//****************************************************************************** +#define I2C_SRIS_RIS 0x00000100 // Raw Interrupt Status +#define I2C_SRIS_TXFERIS 0x00000080 // Transmit FIFO Empty Raw + // Interrupt Status +#define I2C_SRIS_RXRIS 0x00000040 // Receive FIFO Request Raw + // Interrupt Status +#define I2C_SRIS_TXRIS 0x00000020 // Transmit Request Raw Interrupt + // Status +#define I2C_SRIS_DMATXRIS 0x00000010 // Transmit DMA Raw Interrupt + // Status +#define I2C_SRIS_DMARXRIS 0x00000008 // Receive DMA Raw Interrupt Status +#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt + // Status +#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt + // Status +#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SMIS register. +// +//****************************************************************************** +#define I2C_SMIS_RXFFMIS 0x00000100 // Receive FIFO Full Interrupt Mask +#define I2C_SMIS_TXFEMIS 0x00000080 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_SMIS_RXMIS 0x00000040 // Receive FIFO Request Interrupt + // Mask +#define I2C_SMIS_TXMIS 0x00000020 // Transmit FIFO Request Interrupt + // Mask +#define I2C_SMIS_DMATXMIS 0x00000010 // Transmit DMA Masked Interrupt + // Status +#define I2C_SMIS_DMARXMIS 0x00000008 // Receive DMA Masked Interrupt + // Status +#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt + // Status +#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt + // Status +#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SICR register. +// +//****************************************************************************** +#define I2C_SICR_RXFFIC 0x00000100 // Receive FIFO Full Interrupt Mask +#define I2C_SICR_TXFEIC 0x00000080 // Transmit FIFO Empty Interrupt + // Mask +#define I2C_SICR_RXIC 0x00000040 // Receive Request Interrupt Mask +#define I2C_SICR_TXIC 0x00000020 // Transmit Request Interrupt Mask +#define I2C_SICR_DMATXIC 0x00000010 // Transmit DMA Interrupt Clear +#define I2C_SICR_DMARXIC 0x00000008 // Receive DMA Interrupt Clear +#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear +#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear +#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SOAR2 register. +// +//****************************************************************************** +#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable +#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2 +#define I2C_SOAR2_OAR2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_SACKCTL register. +// +//****************************************************************************** +#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value +#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_FIFODATA register. +// +//****************************************************************************** +#define I2C_FIFODATA_DATA_M 0x000000FF // I2C FIFO Data Byte +#define I2C_FIFODATA_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_FIFOCTL register. +// +//****************************************************************************** +#define I2C_FIFOCTL_RXASGNMT 0x80000000 // RX Control Assignment +#define I2C_FIFOCTL_RXFLUSH 0x40000000 // RX FIFO Flush +#define I2C_FIFOCTL_DMARXENA 0x20000000 // DMA RX Channel Enable +#define I2C_FIFOCTL_RXTRIG_M 0x00070000 // RX FIFO Trigger +#define I2C_FIFOCTL_RXTRIG_S 16 +#define I2C_FIFOCTL_TXASGNMT 0x00008000 // TX Control Assignment +#define I2C_FIFOCTL_TXFLUSH 0x00004000 // TX FIFO Flush +#define I2C_FIFOCTL_DMATXENA 0x00002000 // DMA TX Channel Enable +#define I2C_FIFOCTL_TXTRIG_M 0x00000007 // TX FIFO Trigger +#define I2C_FIFOCTL_TXTRIG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_FIFOSTATUS register. +// +//****************************************************************************** +#define I2C_FIFOSTATUS_RXABVTRIG \ + 0x00040000 // RX FIFO Above Trigger Level + +#define I2C_FIFOSTATUS_RXFF 0x00020000 // RX FIFO Full +#define I2C_FIFOSTATUS_RXFE 0x00010000 // RX FIFO Empty +#define I2C_FIFOSTATUS_TXBLWTRIG \ + 0x00000004 // TX FIFO Below Trigger Level + +#define I2C_FIFOSTATUS_TXFF 0x00000002 // TX FIFO Full +#define I2C_FIFOSTATUS_TXFE 0x00000001 // TX FIFO Empty +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_OBSMUXSEL0 register. +// +//****************************************************************************** +#define I2C_OBSMUXSEL0_LN3_M 0x07000000 // Observation Mux Lane 3 +#define I2C_OBSMUXSEL0_LN3_S 24 +#define I2C_OBSMUXSEL0_LN2_M 0x00070000 // Observation Mux Lane 2 +#define I2C_OBSMUXSEL0_LN2_S 16 +#define I2C_OBSMUXSEL0_LN1_M 0x00000700 // Observation Mux Lane 1 +#define I2C_OBSMUXSEL0_LN1_S 8 +#define I2C_OBSMUXSEL0_LN0_M 0x00000007 // Observation Mux Lane 0 +#define I2C_OBSMUXSEL0_LN0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_OBSMUXSEL1 register. +// +//****************************************************************************** +#define I2C_OBSMUXSEL1_LN7_M 0x07000000 // Observation Mux Lane 7 +#define I2C_OBSMUXSEL1_LN7_S 24 +#define I2C_OBSMUXSEL1_LN6_M 0x00070000 // Observation Mux Lane 6 +#define I2C_OBSMUXSEL1_LN6_S 16 +#define I2C_OBSMUXSEL1_LN5_M 0x00000700 // Observation Mux Lane 5 +#define I2C_OBSMUXSEL1_LN5_S 8 +#define I2C_OBSMUXSEL1_LN4_M 0x00000007 // Observation Mux Lane 4 +#define I2C_OBSMUXSEL1_LN4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_MUXROUTE register. +// +//****************************************************************************** +#define I2C_MUXROUTE_LN7ROUTE_M \ + 0x70000000 // Lane 7 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN7ROUTE_S 28 +#define I2C_MUXROUTE_LN6ROUTE_M \ + 0x07000000 // Lane 6 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN6ROUTE_S 24 +#define I2C_MUXROUTE_LN5ROUTE_M \ + 0x00700000 // Lane 5 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN5ROUTE_S 20 +#define I2C_MUXROUTE_LN4ROUTE_M \ + 0x00070000 // Lane 4 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN4ROUTE_S 16 +#define I2C_MUXROUTE_LN3ROUTE_M \ + 0x00007000 // Lane 3 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN3ROUTE_S 12 +#define I2C_MUXROUTE_LN2ROUTE_M \ + 0x00000700 // Lane 2 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN2ROUTE_S 8 +#define I2C_MUXROUTE_LN1ROUTE_M \ + 0x00000070 // Lane 1 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN1ROUTE_S 4 +#define I2C_MUXROUTE_LN0ROUTE_M \ + 0x00000007 // Lane 0 output is routed to the + // lane pointed to by the offset in + // this bit field + +#define I2C_MUXROUTE_LN0ROUTE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PV register. +// +//****************************************************************************** +#define I2C_PV_MAJOR_M 0x0000FF00 // Major Revision +#define I2C_PV_MAJOR_S 8 +#define I2C_PV_MINOR_M 0x000000FF // Minor Revision +#define I2C_PV_MINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PP register. +// +//****************************************************************************** +#define I2C_PP_HS 0x00000001 // High-Speed Capable +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_PC register. +// +//****************************************************************************** +#define I2C_PC_HS 0x00000001 // High-Speed Capable +//****************************************************************************** +// +// The following are defines for the bit fields in the I2C_O_CC register. +// +//****************************************************************************** + + + +#endif // __HW_I2C_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_ints.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_ints.h new file mode 100644 index 00000000..6b401935 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_ints.h @@ -0,0 +1,117 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +//***************************************************************************** +// +// hw_ints.h - Macros that define the interrupt assignment on CC3200. +// +//***************************************************************************** + +#ifndef __HW_INTS_H__ +#define __HW_INTS_H__ + +//***************************************************************************** +// +// The following are defines for the fault assignments. +// +//***************************************************************************** +#define FAULT_NMI 2 // NMI fault +#define FAULT_HARD 3 // Hard fault +#define FAULT_MPU 4 // MPU fault +#define FAULT_BUS 5 // Bus fault +#define FAULT_USAGE 6 // Usage fault +#define FAULT_SVCALL 11 // SVCall +#define FAULT_DEBUG 12 // Debug monitor +#define FAULT_PENDSV 14 // PendSV +#define FAULT_SYSTICK 15 // System Tick + +//***************************************************************************** +// +// The following are defines for the interrupt assignments. +// +//***************************************************************************** +#define INT_GPIOA0 16 // GPIO Port S0 +#define INT_GPIOA1 17 // GPIO Port S1 +#define INT_GPIOA2 18 // GPIO Port S2 +#define INT_GPIOA3 19 // GPIO Port S3 +#define INT_UARTA0 21 // UART0 Rx and Tx +#define INT_UARTA1 22 // UART1 Rx and Tx +#define INT_I2CA0 24 // I2C controller +#define INT_ADCCH0 30 // ADC Sequence 0 +#define INT_ADCCH1 31 // ADC Sequence 1 +#define INT_ADCCH2 32 // ADC Sequence 2 +#define INT_ADCCH3 33 // ADC Sequence 3 +#define INT_WDT 34 // Watchdog Timer0 +#define INT_TIMERA0A 35 // Timer 0 subtimer A +#define INT_TIMERA0B 36 // Timer 0 subtimer B +#define INT_TIMERA1A 37 // Timer 1 subtimer A +#define INT_TIMERA1B 38 // Timer 1 subtimer B +#define INT_TIMERA2A 39 // Timer 2 subtimer A +#define INT_TIMERA2B 40 // Timer 2 subtimer B +#define INT_FLASH 45 // FLASH Control +#define INT_TIMERA3A 51 // Timer 3 subtimer A +#define INT_TIMERA3B 52 // Timer 3 subtimer B +#define INT_UDMA 62 // uDMA controller +#define INT_UDMAERR 63 // uDMA Error +#define INT_SHA 164 // SHA +#define INT_AES 167 // AES +#define INT_DES 169 // DES +#define INT_MMCHS 175 // SDIO +#define INT_I2S 177 // McAPS +#define INT_CAMERA 179 // Camera +#define INT_NWPIC 187 // Interprocessor communication +#define INT_PRCM 188 // Power, Reset and Clock Module +#define INT_SSPI 191 // Shared SPI +#define INT_GSPI 192 // Generic SPI +#define INT_LSPI 193 // Link SPI + +//***************************************************************************** +// +// The following are defines for the total number of interrupts. +// +//***************************************************************************** +#define NUM_INTERRUPTS 195 //The above number plus 2? + + +//***************************************************************************** +// +// The following are defines for the total number of priority levels. +// +//***************************************************************************** +#define NUM_PRIORITY 8 +#define NUM_PRIORITY_BITS 3 + + +#endif // __HW_INTS_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_mcasp.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_mcasp.h new file mode 100644 index 00000000..c27a0077 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_mcasp.h @@ -0,0 +1,1706 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_MCASP_H__ +#define __HW_MCASP_H__ + +//***************************************************************************** +// +// The following are defines for the MCASP register offsets. +// +//***************************************************************************** +#define MCASP_O_PID 0x00000000 +#define MCASP_O_ESYSCONFIG 0x00000004 // Power Idle SYSCONFIG register. +#define MCASP_O_PFUNC 0x00000010 +#define MCASP_O_PDIR 0x00000014 +#define MCASP_O_PDOUT 0x00000018 +#define MCASP_O_PDSET 0x0000001C // The pin data set register + // (PDSET) is an alias of the pin + // data output register (PDOUT) for + // writes only. Writing a 1 to the + // PDSET bit sets the corresponding + // bit in PDOUT and if PFUNC = 1 + // (GPIO function) and PDIR = 1 + // (output) drives a logic high on + // the pin. +#define MCASP_O_PDIN 0x0000001C // The pin data input register + // (PDIN) holds the I/O pin state of + // each of the McASP pins. PDIN + // allows the actual value of the + // pin to be read regardless of the + // state of PFUNC and PDIR. +#define MCASP_O_PDCLR 0x00000020 // The pin data clear register + // (PDCLR) is an alias of the pin + // data output register (PDOUT) for + // writes only. Writing a 1 to the + // PDCLR bit clears the + // corresponding bit in PDOUT and if + // PFUNC = 1 (GPIO function) and + // PDIR = 1 (output) drives a logic + // low on the pin. +#define MCASP_O_TLGC 0x00000030 // for IODFT +#define MCASP_O_TLMR 0x00000034 // for IODFT +#define MCASP_O_TLEC 0x00000038 // for IODFT +#define MCASP_O_GBLCTL 0x00000044 +#define MCASP_O_AMUTE 0x00000048 +#define MCASP_O_LBCTL 0x0000004C +#define MCASP_O_TXDITCTL 0x00000050 +#define MCASP_O_GBLCTLR 0x00000060 +#define MCASP_O_RXMASK 0x00000064 +#define MCASP_O_RXFMT 0x00000068 +#define MCASP_O_RXFMCTL 0x0000006C +#define MCASP_O_ACLKRCTL 0x00000070 +#define MCASP_O_AHCLKRCTL 0x00000074 +#define MCASP_O_RXTDM 0x00000078 +#define MCASP_O_EVTCTLR 0x0000007C +#define MCASP_O_RXSTAT 0x00000080 +#define MCASP_O_RXTDMSLOT 0x00000084 +#define MCASP_O_RXCLKCHK 0x00000088 +#define MCASP_O_REVTCTL 0x0000008C +#define MCASP_O_GBLCTLX 0x000000A0 +#define MCASP_O_TXMASK 0x000000A4 +#define MCASP_O_TXFMT 0x000000A8 +#define MCASP_O_TXFMCTL 0x000000AC +#define MCASP_O_ACLKXCTL 0x000000B0 +#define MCASP_O_AHCLKXCTL 0x000000B4 +#define MCASP_O_TXTDM 0x000000B8 +#define MCASP_O_EVTCTLX 0x000000BC +#define MCASP_O_TXSTAT 0x000000C0 +#define MCASP_O_TXTDMSLOT 0x000000C4 +#define MCASP_O_TXCLKCHK 0x000000C8 +#define MCASP_O_XEVTCTL 0x000000CC +#define MCASP_O_CLKADJEN 0x000000D0 +#define MCASP_O_DITCSRA0 0x00000100 +#define MCASP_O_DITCSRA1 0x00000104 +#define MCASP_O_DITCSRA2 0x00000108 +#define MCASP_O_DITCSRA3 0x0000010C +#define MCASP_O_DITCSRA4 0x00000110 +#define MCASP_O_DITCSRA5 0x00000114 +#define MCASP_O_DITCSRB0 0x00000118 +#define MCASP_O_DITCSRB1 0x0000011C +#define MCASP_O_DITCSRB2 0x00000120 +#define MCASP_O_DITCSRB3 0x00000124 +#define MCASP_O_DITCSRB4 0x00000128 +#define MCASP_O_DITCSRB5 0x0000012C +#define MCASP_O_DITUDRA0 0x00000130 +#define MCASP_O_DITUDRA1 0x00000134 +#define MCASP_O_DITUDRA2 0x00000138 +#define MCASP_O_DITUDRA3 0x0000013C +#define MCASP_O_DITUDRA4 0x00000140 +#define MCASP_O_DITUDRA5 0x00000144 +#define MCASP_O_DITUDRB0 0x00000148 +#define MCASP_O_DITUDRB1 0x0000014C +#define MCASP_O_DITUDRB2 0x00000150 +#define MCASP_O_DITUDRB3 0x00000154 +#define MCASP_O_DITUDRB4 0x00000158 +#define MCASP_O_DITUDRB5 0x0000015C +#define MCASP_O_XRSRCTL0 0x00000180 +#define MCASP_O_XRSRCTL1 0x00000184 +#define MCASP_O_XRSRCTL2 0x00000188 +#define MCASP_O_XRSRCTL3 0x0000018C +#define MCASP_O_XRSRCTL4 0x00000190 +#define MCASP_O_XRSRCTL5 0x00000194 +#define MCASP_O_XRSRCTL6 0x00000198 +#define MCASP_O_XRSRCTL7 0x0000019C +#define MCASP_O_XRSRCTL8 0x000001A0 +#define MCASP_O_XRSRCTL9 0x000001A4 +#define MCASP_O_XRSRCTL10 0x000001A8 +#define MCASP_O_XRSRCTL11 0x000001AC +#define MCASP_O_XRSRCTL12 0x000001B0 +#define MCASP_O_XRSRCTL13 0x000001B4 +#define MCASP_O_XRSRCTL14 0x000001B8 +#define MCASP_O_XRSRCTL15 0x000001BC +#define MCASP_O_TXBUF0 0x00000200 +#define MCASP_O_TXBUF1 0x00000204 +#define MCASP_O_TXBUF2 0x00000208 +#define MCASP_O_TXBUF3 0x0000020C +#define MCASP_O_TXBUF4 0x00000210 +#define MCASP_O_TXBUF5 0x00000214 +#define MCASP_O_TXBUF6 0x00000218 +#define MCASP_O_TXBUF7 0x0000021C +#define MCASP_O_TXBUF8 0x00000220 +#define MCASP_O_TXBUF9 0x00000224 +#define MCASP_O_TXBUF10 0x00000228 +#define MCASP_O_TXBUF11 0x0000022C +#define MCASP_O_TXBUF12 0x00000230 +#define MCASP_O_TXBUF13 0x00000234 +#define MCASP_O_TXBUF14 0x00000238 +#define MCASP_O_TXBUF15 0x0000023C +#define MCASP_O_RXBUF0 0x00000280 +#define MCASP_O_RXBUF1 0x00000284 +#define MCASP_O_RXBUF2 0x00000288 +#define MCASP_O_RXBUF3 0x0000028C +#define MCASP_O_RXBUF4 0x00000290 +#define MCASP_O_RXBUF5 0x00000294 +#define MCASP_O_RXBUF6 0x00000298 +#define MCASP_O_RXBUF7 0x0000029C +#define MCASP_O_RXBUF8 0x000002A0 +#define MCASP_O_RXBUF9 0x000002A4 +#define MCASP_O_RXBUF10 0x000002A8 +#define MCASP_O_RXBUF11 0x000002AC +#define MCASP_O_RXBUF12 0x000002B0 +#define MCASP_O_RXBUF13 0x000002B4 +#define MCASP_O_RXBUF14 0x000002B8 +#define MCASP_O_RXBUF15 0x000002BC +#define MCASP_0_WFIFOCTL 0x00001000 +#define MCASP_0_WFIFOSTS 0x00001004 +#define MCASP_0_RFIFOCTL 0x00001008 +#define MCASP_0_RFIFOSTS 0x0000100C + + +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PID register. +// +//****************************************************************************** +#define MCASP_PID_SCHEME_M 0xC0000000 +#define MCASP_PID_SCHEME_S 30 +#define MCASP_PID_RESV_M 0x30000000 +#define MCASP_PID_RESV_S 28 +#define MCASP_PID_FUNCTION_M 0x0FFF0000 // McASP +#define MCASP_PID_FUNCTION_S 16 +#define MCASP_PID_RTL_M 0x0000F800 +#define MCASP_PID_RTL_S 11 +#define MCASP_PID_REVMAJOR_M 0x00000700 +#define MCASP_PID_REVMAJOR_S 8 +#define MCASP_PID_CUSTOM_M 0x000000C0 // non-custom +#define MCASP_PID_CUSTOM_S 6 +#define MCASP_PID_REVMINOR_M 0x0000003F +#define MCASP_PID_REVMINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// MCASP_O_ESYSCONFIG register. +// +//****************************************************************************** +#define MCASP_ESYSCONFIG_RSV_M 0xFFFFFFC0 // Reserved as per PDR 3.5 +#define MCASP_ESYSCONFIG_RSV_S 6 +#define MCASP_ESYSCONFIG_OTHER_M \ + 0x0000003C // Reserved for future expansion + +#define MCASP_ESYSCONFIG_OTHER_S 2 +#define MCASP_ESYSCONFIG_IDLE_MODE_M \ + 0x00000003 // Idle Mode + +#define MCASP_ESYSCONFIG_IDLE_MODE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PFUNC register. +// +//****************************************************************************** +#define MCASP_PFUNC_AFSR 0x80000000 // AFSR PFUNC 31 0 1 +#define MCASP_PFUNC_AHCLKR 0x40000000 // AHCLKR PFUNC 30 0 1 +#define MCASP_PFUNC_ACLKR 0x20000000 // ACLKR PFUNC 29 0 1 +#define MCASP_PFUNC_AFSX 0x10000000 // AFSX PFUNC 28 0 1 +#define MCASP_PFUNC_AHCLKX 0x08000000 // AHCLKX PFUNC 27 0 1 +#define MCASP_PFUNC_ACLKX 0x04000000 // ACLKX PFUNC 26 0 1 +#define MCASP_PFUNC_AMUTE 0x02000000 // AMUTE PFUNC 25 0 1 +#define MCASP_PFUNC_RESV1_M 0x01FF0000 // Reserved +#define MCASP_PFUNC_RESV1_S 16 +#define MCASP_PFUNC_AXR15 0x00008000 // AXR PFUNC BIT 15 0 1 +#define MCASP_PFUNC_AXR14 0x00004000 // AXR PFUNC BIT 14 0 1 +#define MCASP_PFUNC_AXR13 0x00002000 // AXR PFUNC BIT 13 0 1 +#define MCASP_PFUNC_AXR12 0x00001000 // AXR PFUNC BIT 12 0 1 +#define MCASP_PFUNC_AXR11 0x00000800 // AXR PFUNC BIT 11 0 1 +#define MCASP_PFUNC_AXR10 0x00000400 // AXR PFUNC BIT 10 0 1 +#define MCASP_PFUNC_AXR9 0x00000200 // AXR PFUNC BIT 9 0 1 +#define MCASP_PFUNC_AXR8 0x00000100 // AXR PFUNC BIT 8 0 1 +#define MCASP_PFUNC_AXR7 0x00000080 // AXR PFUNC BIT 7 0 1 +#define MCASP_PFUNC_AXR6 0x00000040 // AXR PFUNC BIT 6 0 1 +#define MCASP_PFUNC_AXR5 0x00000020 // AXR PFUNC BIT 5 0 1 +#define MCASP_PFUNC_AXR4 0x00000010 // AXR PFUNC BIT 4 0 1 +#define MCASP_PFUNC_AXR3 0x00000008 // AXR PFUNC BIT 3 0 1 +#define MCASP_PFUNC_AXR2 0x00000004 // AXR PFUNC BIT 2 0 1 +#define MCASP_PFUNC_AXR1 0x00000002 // AXR PFUNC BIT 1 0 1 +#define MCASP_PFUNC_AXR0 0x00000001 // AXR PFUNC BIT 0 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PDIR register. +// +//****************************************************************************** +#define MCASP_PDIR_AFSR 0x80000000 // AFSR PDIR 31 0 1 +#define MCASP_PDIR_AHCLKR 0x40000000 // AHCLKR PDIR 30 0 1 +#define MCASP_PDIR_ACLKR 0x20000000 // ACLKR PDIR 29 0 1 +#define MCASP_PDIR_AFSX 0x10000000 // AFSX PDIR 28 0 1 +#define MCASP_PDIR_AHCLKX 0x08000000 // AHCLKX PDIR 27 0 1 +#define MCASP_PDIR_ACLKX 0x04000000 // ACLKX PDIR 26 0 1 +#define MCASP_PDIR_AMUTE 0x02000000 // AMUTE PDIR 25 0 1 +#define MCASP_PDIR_RESV_M 0x01FF0000 // Reserved +#define MCASP_PDIR_RESV_S 16 +#define MCASP_PDIR_AXR15 0x00008000 // AXR PDIR BIT 15 0 1 +#define MCASP_PDIR_AXR14 0x00004000 // AXR PDIR BIT 14 0 1 +#define MCASP_PDIR_AXR13 0x00002000 // AXR PDIR BIT 13 0 1 +#define MCASP_PDIR_AXR12 0x00001000 // AXR PDIR BIT 12 0 1 +#define MCASP_PDIR_AXR11 0x00000800 // AXR PDIR BIT 11 0 1 +#define MCASP_PDIR_AXR10 0x00000400 // AXR PDIR BIT 10 0 1 +#define MCASP_PDIR_AXR9 0x00000200 // AXR PDIR BIT 9 0 1 +#define MCASP_PDIR_AXR8 0x00000100 // AXR PDIR BIT 8 0 1 +#define MCASP_PDIR_AXR7 0x00000080 // AXR PDIR BIT 7 0 1 +#define MCASP_PDIR_AXR6 0x00000040 // AXR PDIR BIT 6 0 1 +#define MCASP_PDIR_AXR5 0x00000020 // AXR PDIR BIT 5 0 1 +#define MCASP_PDIR_AXR4 0x00000010 // AXR PDIR BIT 4 0 1 +#define MCASP_PDIR_AXR3 0x00000008 // AXR PDIR BIT 3 0 1 +#define MCASP_PDIR_AXR2 0x00000004 // AXR PDIR BIT 2 0 1 +#define MCASP_PDIR_AXR1 0x00000002 // AXR PDIR BIT 1 0 1 +#define MCASP_PDIR_AXR0 0x00000001 // AXR PDIR BIT 0 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PDOUT register. +// +//****************************************************************************** +#define MCASP_PDOUT_AFSR 0x80000000 // AFSR PDOUT 31 0 1 +#define MCASP_PDOUT_AHCLKR 0x40000000 // AHCLKR PDOUT 30 0 1 +#define MCASP_PDOUT_ACLKR 0x20000000 // ACLKR PDOUT 29 0 1 +#define MCASP_PDOUT_AFSX 0x10000000 // AFSX PDOUT 28 0 1 +#define MCASP_PDOUT_AHCLKX 0x08000000 // AHCLKX PDOUT 27 0 1 +#define MCASP_PDOUT_ACLKX 0x04000000 // ACLKX PDOUT 26 0 1 +#define MCASP_PDOUT_AMUTE 0x02000000 // AMUTE PDOUT 25 0 1 +#define MCASP_PDOUT_RESV_M 0x01FF0000 // Reserved +#define MCASP_PDOUT_RESV_S 16 +#define MCASP_PDOUT_AXR15 0x00008000 // AXR PDOUT BIT 15 0 1 +#define MCASP_PDOUT_AXR14 0x00004000 // AXR PDOUT BIT 14 0 1 +#define MCASP_PDOUT_AXR13 0x00002000 // AXR PDOUT BIT 13 0 1 +#define MCASP_PDOUT_AXR12 0x00001000 // AXR PDOUT BIT 12 0 1 +#define MCASP_PDOUT_AXR11 0x00000800 // AXR PDOUT BIT 11 0 1 +#define MCASP_PDOUT_AXR10 0x00000400 // AXR PDOUT BIT 10 0 1 +#define MCASP_PDOUT_AXR9 0x00000200 // AXR PDOUT BIT 9 0 1 +#define MCASP_PDOUT_AXR8 0x00000100 // AXR PDOUT BIT 8 0 1 +#define MCASP_PDOUT_AXR7 0x00000080 // AXR PDOUT BIT 7 0 1 +#define MCASP_PDOUT_AXR6 0x00000040 // AXR PDOUT BIT 6 0 1 +#define MCASP_PDOUT_AXR5 0x00000020 // AXR PDOUT BIT 5 0 1 +#define MCASP_PDOUT_AXR4 0x00000010 // AXR PDOUT BIT 4 0 1 +#define MCASP_PDOUT_AXR3 0x00000008 // AXR PDOUT BIT 3 0 1 +#define MCASP_PDOUT_AXR2 0x00000004 // AXR PDOUT BIT 2 0 1 +#define MCASP_PDOUT_AXR1 0x00000002 // AXR PDOUT BIT 1 0 1 +#define MCASP_PDOUT_AXR0 0x00000001 // AXR PDOUT BIT 0 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PDSET register. +// +//****************************************************************************** +#define MCASP_PDSET_AFSR 0x80000000 +#define MCASP_PDSET_AHCLKR 0x40000000 +#define MCASP_PDSET_ACLKR 0x20000000 +#define MCASP_PDSET_AFSX 0x10000000 +#define MCASP_PDSET_AHCLKX 0x08000000 +#define MCASP_PDSET_ACLKX 0x04000000 +#define MCASP_PDSET_AMUTE 0x02000000 +#define MCASP_PDSET_RESV_M 0x01FF0000 // Reserved +#define MCASP_PDSET_RESV_S 16 +#define MCASP_PDSET_AXR15 0x00008000 +#define MCASP_PDSET_AXR14 0x00004000 +#define MCASP_PDSET_AXR13 0x00002000 +#define MCASP_PDSET_AXR12 0x00001000 +#define MCASP_PDSET_AXR11 0x00000800 +#define MCASP_PDSET_AXR10 0x00000400 +#define MCASP_PDSET_AXR9 0x00000200 +#define MCASP_PDSET_AXR8 0x00000100 +#define MCASP_PDSET_AXR7 0x00000080 +#define MCASP_PDSET_AXR6 0x00000040 +#define MCASP_PDSET_AXR5 0x00000020 +#define MCASP_PDSET_AXR4 0x00000010 +#define MCASP_PDSET_AXR3 0x00000008 +#define MCASP_PDSET_AXR2 0x00000004 +#define MCASP_PDSET_AXR1 0x00000002 +#define MCASP_PDSET_AXR0 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PDIN register. +// +//****************************************************************************** +#define MCASP_PDIN_AFSR 0x80000000 +#define MCASP_PDIN_AHCLKR 0x40000000 +#define MCASP_PDIN_ACLKR 0x20000000 +#define MCASP_PDIN_AFSX 0x10000000 +#define MCASP_PDIN_AHCLKX 0x08000000 +#define MCASP_PDIN_ACLKX 0x04000000 +#define MCASP_PDIN_AMUTE 0x02000000 +#define MCASP_PDIN_RESV_M 0x01FF0000 // Reserved +#define MCASP_PDIN_RESV_S 16 +#define MCASP_PDIN_AXR15 0x00008000 +#define MCASP_PDIN_AXR14 0x00004000 +#define MCASP_PDIN_AXR13 0x00002000 +#define MCASP_PDIN_AXR12 0x00001000 +#define MCASP_PDIN_AXR11 0x00000800 +#define MCASP_PDIN_AXR10 0x00000400 +#define MCASP_PDIN_AXR9 0x00000200 +#define MCASP_PDIN_AXR8 0x00000100 +#define MCASP_PDIN_AXR7 0x00000080 +#define MCASP_PDIN_AXR6 0x00000040 +#define MCASP_PDIN_AXR5 0x00000020 +#define MCASP_PDIN_AXR4 0x00000010 +#define MCASP_PDIN_AXR3 0x00000008 +#define MCASP_PDIN_AXR2 0x00000004 +#define MCASP_PDIN_AXR1 0x00000002 +#define MCASP_PDIN_AXR0 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_PDCLR register. +// +//****************************************************************************** +#define MCASP_PDCLR_AFSR 0x80000000 // AFSR PDCLR 31 0 1 +#define MCASP_PDCLR_AHCLKR 0x40000000 // AHCLKR PDCLR 30 0 1 +#define MCASP_PDCLR_ACLKR 0x20000000 // ACLKR PDCLR 29 0 1 +#define MCASP_PDCLR_AFSX 0x10000000 // AFSX PDCLR 28 0 1 +#define MCASP_PDCLR_AHCLKX 0x08000000 // AHCLKX PDCLR 27 0 1 +#define MCASP_PDCLR_ACLKX 0x04000000 // ACLKX PDCLR 26 0 1 +#define MCASP_PDCLR_AMUTE 0x02000000 // AMUTE PDCLR 25 0 1 +#define MCASP_PDCLR_RESV_M 0x01FF0000 // Reserved +#define MCASP_PDCLR_RESV_S 16 +#define MCASP_PDCLR_AXR15 0x00008000 // AXR PDCLR BIT 15 0 1 +#define MCASP_PDCLR_AXR14 0x00004000 // AXR PDCLR BIT 14 0 1 +#define MCASP_PDCLR_AXR13 0x00002000 // AXR PDCLR BIT 13 0 1 +#define MCASP_PDCLR_AXR12 0x00001000 // AXR PDCLR BIT 12 0 1 +#define MCASP_PDCLR_AXR11 0x00000800 // AXR PDCLR BIT 11 0 1 +#define MCASP_PDCLR_AXR10 0x00000400 // AXR PDCLR BIT 10 0 1 +#define MCASP_PDCLR_AXR9 0x00000200 // AXR PDCLR BIT 9 0 1 +#define MCASP_PDCLR_AXR8 0x00000100 // AXR PDCLR BIT 8 0 1 +#define MCASP_PDCLR_AXR7 0x00000080 // AXR PDCLR BIT 7 0 1 +#define MCASP_PDCLR_AXR6 0x00000040 // AXR PDCLR BIT 6 0 1 +#define MCASP_PDCLR_AXR5 0x00000020 // AXR PDCLR BIT 5 0 1 +#define MCASP_PDCLR_AXR4 0x00000010 // AXR PDCLR BIT 4 0 1 +#define MCASP_PDCLR_AXR3 0x00000008 // AXR PDCLR BIT 3 0 1 +#define MCASP_PDCLR_AXR2 0x00000004 // AXR PDCLR BIT 2 0 1 +#define MCASP_PDCLR_AXR1 0x00000002 // AXR PDCLR BIT 1 0 1 +#define MCASP_PDCLR_AXR0 0x00000001 // AXR PDCLR BIT 0 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TLGC register. +// +//****************************************************************************** +#define MCASP_TLGC_RESV_M 0xFFFF0000 // Reserved +#define MCASP_TLGC_RESV_S 16 +#define MCASP_TLGC_MT_M 0x0000C000 // MISR on/off trigger command 0x0 + // 0x1 0x2 0x3 +#define MCASP_TLGC_MT_S 14 +#define MCASP_TLGC_RESV1_M 0x00003E00 // Reserved +#define MCASP_TLGC_RESV1_S 9 +#define MCASP_TLGC_MMS 0x00000100 // Source of MISR input 0 1 +#define MCASP_TLGC_ESEL 0x00000080 // Output enable select 0 1 +#define MCASP_TLGC_TOEN 0x00000040 // Test output enable control. 0 1 +#define MCASP_TLGC_MC_M 0x00000030 // States of MISR 0x0 0x1 0x2 0x3 +#define MCASP_TLGC_MC_S 4 +#define MCASP_TLGC_PC_M 0x0000000E // Pattern code 0x0 0x1 0x2 0x3 0x4 + // 0x5 0x6 0x7 +#define MCASP_TLGC_PC_S 1 +#define MCASP_TLGC_TM 0x00000001 // Tie high; do not write to this + // bit 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TLMR register. +// +//****************************************************************************** +#define MCASP_TLMR_TLMR_M 0xFFFFFFFF // Contains test result signature. +#define MCASP_TLMR_TLMR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TLEC register. +// +//****************************************************************************** +#define MCASP_TLEC_TLEC_M 0xFFFFFFFF // Contains number of cycles during + // which MISR sig will be + // accumulated. +#define MCASP_TLEC_TLEC_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_GBLCTL register. +// +//****************************************************************************** +#define MCASP_GBLCTL_XFRST 0x00001000 // Frame sync generator reset 0 1 +#define MCASP_GBLCTL_XSMRST 0x00000800 // XMT state machine reset 0 1 +#define MCASP_GBLCTL_XSRCLR 0x00000400 // XMT serializer clear 0 1 +#define MCASP_GBLCTL_XHCLKRST 0x00000200 // XMT High Freq. clk Divider 0 1 +#define MCASP_GBLCTL_XCLKRST 0x00000100 // XMT clock divder reset 0 1 +#define MCASP_GBLCTL_RFRST 0x00000010 // Frame sync generator reset 0 1 +#define MCASP_GBLCTL_RSMRST 0x00000008 // RCV state machine reset 0 1 +#define MCASP_GBLCTL_RSRCLR 0x00000004 // RCV serializer clear 0 1 +#define MCASP_GBLCTL_RHCLKRST 0x00000002 // RCV High Freq. clk Divider 0 1 +#define MCASP_GBLCTL_RCLKRST 0x00000001 // RCV clock divder reset 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_AMUTE register. +// +//****************************************************************************** +#define MCASP_AMUTE_XDMAERR 0x00001000 // MUTETXDMAERR occur 0 1 +#define MCASP_AMUTE_RDMAERR 0x00000800 // MUTERXDMAERR occur 0 1 +#define MCASP_AMUTE_XCKFAIL 0x00000400 // XMT bad clock 0 1 +#define MCASP_AMUTE_RCKFAIL 0x00000200 // RCV bad clock 0 1 +#define MCASP_AMUTE_XSYNCERR 0x00000100 // XMT unexpected FS 0 1 +#define MCASP_AMUTE_RSYNCERR 0x00000080 // RCV unexpected FS 0 1 +#define MCASP_AMUTE_XUNDRN 0x00000040 // XMT underrun occurs 0 1 +#define MCASP_AMUTE_ROVRN 0x00000020 // RCV overun occurs 0 1 +#define MCASP_AMUTE_INSTAT 0x00000010 +#define MCASP_AMUTE_INEN 0x00000008 // drive AMUTE active on mute in + // active 0 1 +#define MCASP_AMUTE_INPOL 0x00000004 // Mute input polarity 0 1 +#define MCASP_AMUTE_MUTEN_M 0x00000003 // AMUTE pin enable 0x0 0x1 0x2 +#define MCASP_AMUTE_MUTEN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_LBCTL register. +// +//****************************************************************************** +#define MCASP_LBCTL_IOLBEN 0x00000010 // IO loopback enable 0 1 +#define MCASP_LBCTL_MODE_M 0x0000000C // Loop back clock source generator + // 0x0 0x1 0x2 0x3 +#define MCASP_LBCTL_MODE_S 2 +#define MCASP_LBCTL_ORD 0x00000002 // Loopback order 0 1 +#define MCASP_LBCTL_DLBEN 0x00000001 // Loop back mode 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXDITCTL register. +// +//****************************************************************************** +#define MCASP_TXDITCTL_VB 0x00000008 // Valib bit for odd TDM 0 1 +#define MCASP_TXDITCTL_VA 0x00000004 // Valib bit for even TDM 0 1 +#define MCASP_TXDITCTL_DITEN 0x00000001 // XMT DIT Mode Enable 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_GBLCTLR register. +// +//****************************************************************************** +#define MCASP_GBLCTLR_XFRST 0x00001000 +#define MCASP_GBLCTLR_XSMRST 0x00000800 +#define MCASP_GBLCTLR_XSRCLR 0x00000400 +#define MCASP_GBLCTLR_XHCLKRST 0x00000200 +#define MCASP_GBLCTLR_XCLKRST 0x00000100 +#define MCASP_GBLCTLR_RFRST 0x00000010 // Frame sync generator reset 0 1 +#define MCASP_GBLCTLR_RSMRST 0x00000008 // RCV state machine reset 0 1 +#define MCASP_GBLCTLR_RSRCLR 0x00000004 // RCV serializer clear 0 1 +#define MCASP_GBLCTLR_RHCLKRST 0x00000002 // RCV High Freq. clk Divider 0 1 +#define MCASP_GBLCTLR_RCLKRST 0x00000001 // RCV clock divder reset 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXMASK register. +// +//****************************************************************************** +#define MCASP_RXMASK_RMASK31 0x80000000 // RMASK BIT 31 0 1 +#define MCASP_RXMASK_RMASK30 0x40000000 // RMASK BIT 30 0 1 +#define MCASP_RXMASK_RMASK29 0x20000000 // RMASK BIT 29 0 1 +#define MCASP_RXMASK_RMASK28 0x10000000 // RMASK BIT 28 0 1 +#define MCASP_RXMASK_RMASK27 0x08000000 // RMASK BIT 27 0 1 +#define MCASP_RXMASK_RMASK26 0x04000000 // RMASK BIT 26 0 1 +#define MCASP_RXMASK_RMASK25 0x02000000 // RMASK BIT 25 0 1 +#define MCASP_RXMASK_RMASK24 0x01000000 // RMASK BIT 24 0 1 +#define MCASP_RXMASK_RMASK23 0x00800000 // RMASK BIT 23 0 1 +#define MCASP_RXMASK_RMASK22 0x00400000 // RMASK BIT 22 0 1 +#define MCASP_RXMASK_RMASK21 0x00200000 // RMASK BIT 21 0 1 +#define MCASP_RXMASK_RMASK20 0x00100000 // RMASK BIT 20 0 1 +#define MCASP_RXMASK_RMASK19 0x00080000 // RMASK BIT 19 0 1 +#define MCASP_RXMASK_RMASK18 0x00040000 // RMASK BIT 18 0 1 +#define MCASP_RXMASK_RMASK17 0x00020000 // RMASK BIT 17 0 1 +#define MCASP_RXMASK_RMASK16 0x00010000 // RMASK BIT 16 0 1 +#define MCASP_RXMASK_RMASK15 0x00008000 // RMASK BIT 15 0 1 +#define MCASP_RXMASK_RMASK14 0x00004000 // RMASK BIT 14 0 1 +#define MCASP_RXMASK_RMASK13 0x00002000 // RMASK BIT 13 0 1 +#define MCASP_RXMASK_RMASK12 0x00001000 // RMASK BIT 12 0 1 +#define MCASP_RXMASK_RMASK11 0x00000800 // RMASK BIT 11 0 1 +#define MCASP_RXMASK_RMASK10 0x00000400 // RMASK BIT 10 0 1 +#define MCASP_RXMASK_RMASK9 0x00000200 // RMASK BIT 9 0 1 +#define MCASP_RXMASK_RMASK8 0x00000100 // RMASK BIT 8 0 1 +#define MCASP_RXMASK_RMASK7 0x00000080 // RMASK BIT 7 0 1 +#define MCASP_RXMASK_RMASK6 0x00000040 // RMASK BIT 6 0 1 +#define MCASP_RXMASK_RMASK5 0x00000020 // RMASK BIT 5 0 1 +#define MCASP_RXMASK_RMASK4 0x00000010 // RMASK BIT 4 0 1 +#define MCASP_RXMASK_RMASK3 0x00000008 // RMASK BIT 3 0 1 +#define MCASP_RXMASK_RMASK2 0x00000004 // RMASK BIT 2 0 1 +#define MCASP_RXMASK_RMASK1 0x00000002 // RMASK BIT 1 0 1 +#define MCASP_RXMASK_RMASK0 0x00000001 // RMASK BIT 0 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXFMT register. +// +//****************************************************************************** +#define MCASP_RXFMT_RDATDLY_M 0x00030000 // RCV Frame sync delay 0x0 0 Bit + // delay 0x1 1 Bit delay 0x2 2 Bit + // delay +#define MCASP_RXFMT_RDATDLY_S 16 +#define MCASP_RXFMT_RRVRS 0x00008000 // RCV serial stream bit order 0 1 +#define MCASP_RXFMT_RPAD_M 0x00006000 // Pad value 0x0 0x1 0x2 +#define MCASP_RXFMT_RPAD_S 13 +#define MCASP_RXFMT_RPBIT_M 0x00001F00 // Pad bit position +#define MCASP_RXFMT_RPBIT_S 8 +#define MCASP_RXFMT_RSSZ_M 0x000000F0 // RCV slot Size 0x0 0x1 0x2 0x3 + // 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB + // 0xC 0xD 0xE 0xF +#define MCASP_RXFMT_RSSZ_S 4 +#define MCASP_RXFMT_RBUSEL 0x00000008 // Write to RBUF using CPU/DMA 0 + // DMA port access 1 CPU port Access +#define MCASP_RXFMT_RROT_M 0x00000007 // Right Rotate Value 0x0 0x1 0x2 + // 0x3 0x4 0x5 0x6 0x7 +#define MCASP_RXFMT_RROT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXFMCTL register. +// +//****************************************************************************** +#define MCASP_RXFMCTL_RMOD_M 0x0000FF80 // RCV Frame sync mode +#define MCASP_RXFMCTL_RMOD_S 7 +#define MCASP_RXFMCTL_FRWID 0x00000010 // RCV Frame sync Duration 0 1 +#define MCASP_RXFMCTL_FSRM 0x00000002 // RCV frame sync External 0 1 +#define MCASP_RXFMCTL_FSRP 0x00000001 // RCV Frame sync Polarity 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_ACLKRCTL register. +// +//****************************************************************************** +#define MCASP_ACLKRCTL_BUSY 0x00100000 +#define MCASP_ACLKRCTL_DIVBUSY 0x00080000 +#define MCASP_ACLKRCTL_ADJBUSY 0x00040000 +#define MCASP_ACLKRCTL_CLKRADJ_M \ + 0x00030000 + +#define MCASP_ACLKRCTL_CLKRADJ_S 16 +#define MCASP_ACLKRCTL_CLKRP 0x00000080 // RCV Clock Polarity 0 1 +#define MCASP_ACLKRCTL_CLKRM 0x00000020 // RCV clock source 0 1 +#define MCASP_ACLKRCTL_CLKRDIV_M \ + 0x0000001F // RCV clock devide ratio + +#define MCASP_ACLKRCTL_CLKRDIV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_AHCLKRCTL register. +// +//****************************************************************************** +#define MCASP_AHCLKRCTL_BUSY 0x00100000 +#define MCASP_AHCLKRCTL_DIVBUSY 0x00080000 +#define MCASP_AHCLKRCTL_ADJBUSY 0x00040000 +#define MCASP_AHCLKRCTL_HCLKRADJ_M \ + 0x00030000 + +#define MCASP_AHCLKRCTL_HCLKRADJ_S 16 +#define MCASP_AHCLKRCTL_HCLKRM 0x00008000 // High Freq. RCV clock Source 0 1 +#define MCASP_AHCLKRCTL_HCLKRP 0x00004000 // High Freq. clock Polarity Before + // diviser 0 1 +#define MCASP_AHCLKRCTL_HCLKRDIV_M \ + 0x00000FFF // RCV clock Divide Ratio + +#define MCASP_AHCLKRCTL_HCLKRDIV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXTDM register. +// +//****************************************************************************** +#define MCASP_RXTDM_RTDMS31 0x80000000 // RCV mode during TDM time slot 31 + // 0 1 +#define MCASP_RXTDM_RTDMS30 0x40000000 // RCV mode during TDM time slot 30 + // 0 1 +#define MCASP_RXTDM_RTDMS29 0x20000000 // RCV mode during TDM time slot 29 + // 0 1 +#define MCASP_RXTDM_RTDMS28 0x10000000 // RCV mode during TDM time slot 28 + // 0 1 +#define MCASP_RXTDM_RTDMS27 0x08000000 // RCV mode during TDM time slot 27 + // 0 1 +#define MCASP_RXTDM_RTDMS26 0x04000000 // RCV mode during TDM time slot 26 + // 0 1 +#define MCASP_RXTDM_RTDMS25 0x02000000 // RCV mode during TDM time slot 25 + // 0 1 +#define MCASP_RXTDM_RTDMS24 0x01000000 // RCV mode during TDM time slot 24 + // 0 1 +#define MCASP_RXTDM_RTDMS23 0x00800000 // RCV mode during TDM time slot 23 + // 0 1 +#define MCASP_RXTDM_RTDMS22 0x00400000 // RCV mode during TDM time slot 22 + // 0 1 +#define MCASP_RXTDM_RTDMS21 0x00200000 // RCV mode during TDM time slot 21 + // 0 1 +#define MCASP_RXTDM_RTDMS20 0x00100000 // RCV mode during TDM time slot 20 + // 0 1 +#define MCASP_RXTDM_RTDMS19 0x00080000 // RCV mode during TDM time slot 19 + // 0 1 +#define MCASP_RXTDM_RTDMS18 0x00040000 // RCV mode during TDM time slot 18 + // 0 1 +#define MCASP_RXTDM_RTDMS17 0x00020000 // RCV mode during TDM time slot 17 + // 0 1 +#define MCASP_RXTDM_RTDMS16 0x00010000 // RCV mode during TDM time slot 16 + // 0 1 +#define MCASP_RXTDM_RTDMS15 0x00008000 // RCV mode during TDM time slot 15 + // 0 1 +#define MCASP_RXTDM_RTDMS14 0x00004000 // RCV mode during TDM time slot 14 + // 0 1 +#define MCASP_RXTDM_RTDMS13 0x00002000 // RCV mode during TDM time slot 13 + // 0 1 +#define MCASP_RXTDM_RTDMS12 0x00001000 // RCV mode during TDM time slot 12 + // 0 1 +#define MCASP_RXTDM_RTDMS11 0x00000800 // RCV mode during TDM time slot 11 + // 0 1 +#define MCASP_RXTDM_RTDMS10 0x00000400 // RCV mode during TDM time slot 10 + // 0 1 +#define MCASP_RXTDM_RTDMS9 0x00000200 // RCV mode during TDM time slot 9 + // 0 1 +#define MCASP_RXTDM_RTDMS8 0x00000100 // RCV mode during TDM time slot 8 + // 0 1 +#define MCASP_RXTDM_RTDMS7 0x00000080 // RCV mode during TDM time slot 7 + // 0 1 +#define MCASP_RXTDM_RTDMS6 0x00000040 // RCV mode during TDM time slot 6 + // 0 1 +#define MCASP_RXTDM_RTDMS5 0x00000020 // RCV mode during TDM time slot 5 + // 0 1 +#define MCASP_RXTDM_RTDMS4 0x00000010 // RCV mode during TDM time slot 4 + // 0 1 +#define MCASP_RXTDM_RTDMS3 0x00000008 // RCV mode during TDM time slot 3 + // 0 1 +#define MCASP_RXTDM_RTDMS2 0x00000004 // RCV mode during TDM time slot 2 + // 0 1 +#define MCASP_RXTDM_RTDMS1 0x00000002 // RCV mode during TDM time slot 1 + // 0 1 +#define MCASP_RXTDM_RTDMS0 0x00000001 // RCV mode during TDM time slot 0 + // 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_EVTCTLR register. +// +//****************************************************************************** +#define MCASP_EVTCTLR_RSTAFRM 0x00000080 // RCV Start of Frame Interrupt 0 1 +#define MCASP_EVTCTLR_RDATA 0x00000020 // RCV Data Interrupt 0 1 +#define MCASP_EVTCTLR_RLAST 0x00000010 // RCV Last Slot Interrupt 0 1 +#define MCASP_EVTCTLR_RDMAERR 0x00000008 // RCV DMA Bus Error 0 1 +#define MCASP_EVTCTLR_RCKFAIL 0x00000004 // Bad Clock Interrupt 0 1 +#define MCASP_EVTCTLR_RSYNCERR 0x00000002 // RCV Unexpected FSR Interrupt 0 1 +#define MCASP_EVTCTLR_ROVRN 0x00000001 // RCV Underrun Flag 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXSTAT register. +// +//****************************************************************************** +#define MCASP_RXSTAT_RERR 0x00000100 // RCV Error 0 1 +#define MCASP_RXSTAT_RDMAERR 0x00000080 // RCV DMA bus error 0 1 +#define MCASP_RXSTAT_RSTAFRM 0x00000040 // Start of Frame-RCV 0 1 +#define MCASP_RXSTAT_RDATA 0x00000020 // Data Ready Flag 0 1 +#define MCASP_RXSTAT_RLAST 0x00000010 // Last Slot Interrupt Flag 0 1 +#define MCASP_RXSTAT_RTDMSLOT 0x00000008 // EvenOdd Slot 0 1 +#define MCASP_RXSTAT_RCKFAIL 0x00000004 // Bad Transmit Flag 0 1 +#define MCASP_RXSTAT_RSYNCERR 0x00000002 // Unexpected RCV Frame sync flag 0 + // 1 +#define MCASP_RXSTAT_ROVRN 0x00000001 // RCV Underrun Flag 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXTDMSLOT register. +// +//****************************************************************************** +#define MCASP_RXTDMSLOT_RSLOTCNT_M \ + 0x000003FF // Current RCV time slot count + +#define MCASP_RXTDMSLOT_RSLOTCNT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXCLKCHK register. +// +//****************************************************************************** +#define MCASP_RXCLKCHK_RCNT_M 0xFF000000 // RCV clock count value +#define MCASP_RXCLKCHK_RCNT_S 24 +#define MCASP_RXCLKCHK_RMAX_M 0x00FF0000 // RCV clock maximum boundary +#define MCASP_RXCLKCHK_RMAX_S 16 +#define MCASP_RXCLKCHK_RMIN_M 0x0000FF00 // RCV clock minimum boundary +#define MCASP_RXCLKCHK_RMIN_S 8 +#define MCASP_RXCLKCHK_RPS_M 0x0000000F // RCV clock check prescaler 0x0 + // 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 +#define MCASP_RXCLKCHK_RPS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_REVTCTL register. +// +//****************************************************************************** +#define MCASP_REVTCTL_RDATDMA 0x00000001 // RCV data DMA request 0 Enable + // DMA Transfer 1 Disable DMA + // Transfer +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_GBLCTLX register. +// +//****************************************************************************** +#define MCASP_GBLCTLX_XFRST 0x00001000 // Frame sync generator reset 0 1 +#define MCASP_GBLCTLX_XSMRST 0x00000800 // XMT state machine reset 0 1 +#define MCASP_GBLCTLX_XSRCLR 0x00000400 // XMT serializer clear 0 1 +#define MCASP_GBLCTLX_XHCLKRST 0x00000200 // XMT High Freq. clk Divider 0 1 +#define MCASP_GBLCTLX_XCLKRST 0x00000100 // XMT clock divder reset 0 1 +#define MCASP_GBLCTLX_RFRST 0x00000010 +#define MCASP_GBLCTLX_RSMRST 0x00000008 +#define MCASP_GBLCTLX_RSRCLKR 0x00000004 +#define MCASP_GBLCTLX_RHCLKRST 0x00000002 +#define MCASP_GBLCTLX_RCLKRST 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXMASK register. +// +//****************************************************************************** +#define MCASP_TXMASK_XMASK31 0x80000000 // XMASK BIT 31 0 1 +#define MCASP_TXMASK_XMASK30 0x40000000 // XMASK BIT 30 0 1 +#define MCASP_TXMASK_XMASK29 0x20000000 // XMASK BIT 29 0 1 +#define MCASP_TXMASK_XMASK28 0x10000000 // XMASK BIT 28 0 1 +#define MCASP_TXMASK_XMASK27 0x08000000 // XMASK BIT 27 0 1 +#define MCASP_TXMASK_XMASK26 0x04000000 // XMASK BIT 26 0 1 +#define MCASP_TXMASK_XMASK25 0x02000000 // XMASK BIT 25 0 1 +#define MCASP_TXMASK_XMASK24 0x01000000 // XMASK BIT 24 0 1 +#define MCASP_TXMASK_XMASK23 0x00800000 // XMASK BIT 23 0 1 +#define MCASP_TXMASK_XMASK22 0x00400000 // XMASK BIT 22 0 1 +#define MCASP_TXMASK_XMASK21 0x00200000 // XMASK BIT 21 0 1 +#define MCASP_TXMASK_XMASK20 0x00100000 // XMASK BIT 20 0 1 +#define MCASP_TXMASK_XMASK19 0x00080000 // XMASK BIT 19 0 1 +#define MCASP_TXMASK_XMASK18 0x00040000 // XMASK BIT 18 0 1 +#define MCASP_TXMASK_XMASK17 0x00020000 // XMASK BIT 17 0 1 +#define MCASP_TXMASK_XMASK16 0x00010000 // XMASK BIT 16 0 1 +#define MCASP_TXMASK_XMASK15 0x00008000 // XMASK BIT 15 0 1 +#define MCASP_TXMASK_XMASK14 0x00004000 // XMASK BIT 14 0 1 +#define MCASP_TXMASK_XMASK13 0x00002000 // XMASK BIT 13 0 1 +#define MCASP_TXMASK_XMASK12 0x00001000 // XMASK BIT 12 0 1 +#define MCASP_TXMASK_XMASK11 0x00000800 // XMASK BIT 11 0 1 +#define MCASP_TXMASK_XMASK10 0x00000400 // XMASK BIT 10 0 1 +#define MCASP_TXMASK_XMASK9 0x00000200 // XMASK BIT 9 0 1 +#define MCASP_TXMASK_XMASK8 0x00000100 // XMASK BIT 8 0 1 +#define MCASP_TXMASK_XMASK7 0x00000080 // XMASK BIT 7 0 1 +#define MCASP_TXMASK_XMASK6 0x00000040 // XMASK BIT 6 0 1 +#define MCASP_TXMASK_XMASK5 0x00000020 // XMASK BIT 5 0 1 +#define MCASP_TXMASK_XMASK4 0x00000010 // XMASK BIT 4 0 1 +#define MCASP_TXMASK_XMASK3 0x00000008 // XMASK BIT 3 0 1 +#define MCASP_TXMASK_XMASK2 0x00000004 // XMASK BIT 2 0 1 +#define MCASP_TXMASK_XMASK1 0x00000002 // XMASK BIT 1 0 1 +#define MCASP_TXMASK_XMASK0 0x00000001 // XMASK BIT 0 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXFMT register. +// +//****************************************************************************** +#define MCASP_TXFMT_XDATDLY_M 0x00030000 // XMT Frame sync delay 0x0 0 Bit + // delay 0x1 1 Bit delay 0x2 2 Bit + // delay +#define MCASP_TXFMT_XDATDLY_S 16 +#define MCASP_TXFMT_XRVRS 0x00008000 // XMT serial stream bit order 0 1 +#define MCASP_TXFMT_XPAD_M 0x00006000 // Pad value 0x0 0x1 0x2 +#define MCASP_TXFMT_XPAD_S 13 +#define MCASP_TXFMT_XPBIT_M 0x00001F00 // Pad bit position +#define MCASP_TXFMT_XPBIT_S 8 +#define MCASP_TXFMT_XSSZ_M 0x000000F0 // XMT slot Size 0x0 0x1 0x2 0x3 + // 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB + // 0xC 0xD 0xE 0xF +#define MCASP_TXFMT_XSSZ_S 4 +#define MCASP_TXFMT_XBUSEL 0x00000008 // Write to XBUF using CPU/DMA 0 + // DMA port access 1 CPU port Access +#define MCASP_TXFMT_XROT_M 0x00000007 // Right Rotate Value 0x0 0x1 0x2 + // 0x3 0x4 0x5 0x6 0x7 +#define MCASP_TXFMT_XROT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXFMCTL register. +// +//****************************************************************************** +#define MCASP_TXFMCTL_XMOD_M 0x0000FF80 // XMT Frame sync mode +#define MCASP_TXFMCTL_XMOD_S 7 +#define MCASP_TXFMCTL_FXWID 0x00000010 // XMT Frame sync Duration 0 1 +#define MCASP_TXFMCTL_FSXM 0x00000002 // XMT frame sync External 0 1 +#define MCASP_TXFMCTL_FSXP 0x00000001 // XMT Frame sync Polarity 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_ACLKXCTL register. +// +//****************************************************************************** +#define MCASP_ACLKXCTL_BUSY 0x00100000 +#define MCASP_ACLKXCTL_DIVBUSY 0x00080000 +#define MCASP_ACLKXCTL_ADJBUSY 0x00040000 +#define MCASP_ACLKXCTL_CLKXADJ_M \ + 0x00030000 + +#define MCASP_ACLKXCTL_CLKXADJ_S 16 +#define MCASP_ACLKXCTL_CLKXP 0x00000080 // XMT Clock Polarity 0 1 +#define MCASP_ACLKXCTL_ASYNC 0x00000040 // XMT/RCV operation sync /Async 0 + // 1 +#define MCASP_ACLKXCTL_CLKXM 0x00000020 // XMT clock source 0 1 +#define MCASP_ACLKXCTL_CLKXDIV_M \ + 0x0000001F // XMT clock devide ratio + +#define MCASP_ACLKXCTL_CLKXDIV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_AHCLKXCTL register. +// +//****************************************************************************** +#define MCASP_AHCLKXCTL_BUSY 0x00100000 +#define MCASP_AHCLKXCTL_DIVBUSY 0x00080000 +#define MCASP_AHCLKXCTL_ADJBUSY 0x00040000 +#define MCASP_AHCLKXCTL_HCLKXADJ_M \ + 0x00030000 + +#define MCASP_AHCLKXCTL_HCLKXADJ_S 16 +#define MCASP_AHCLKXCTL_HCLKXM 0x00008000 // High Freq. XMT clock Source 0 1 +#define MCASP_AHCLKXCTL_HCLKXP 0x00004000 // High Freq. clock Polarity Before + // diviser 0 1 +#define MCASP_AHCLKXCTL_HCLKXDIV_M \ + 0x00000FFF // XMT clock Divide Ratio + +#define MCASP_AHCLKXCTL_HCLKXDIV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXTDM register. +// +//****************************************************************************** +#define MCASP_TXTDM_XTDMS31 0x80000000 // XMT mode during TDM time slot 31 + // 0 1 +#define MCASP_TXTDM_XTDMS30 0x40000000 // XMT mode during TDM time slot 30 + // 0 1 +#define MCASP_TXTDM_XTDMS29 0x20000000 // XMT mode during TDM time slot 29 + // 0 1 +#define MCASP_TXTDM_XTDMS28 0x10000000 // XMT mode during TDM time slot 28 + // 0 1 +#define MCASP_TXTDM_XTDMS27 0x08000000 // XMT mode during TDM time slot 27 + // 0 1 +#define MCASP_TXTDM_XTDMS26 0x04000000 // XMT mode during TDM time slot 26 + // 0 1 +#define MCASP_TXTDM_XTDMS25 0x02000000 // XMT mode during TDM time slot 25 + // 0 1 +#define MCASP_TXTDM_XTDMS24 0x01000000 // XMT mode during TDM time slot 24 + // 0 1 +#define MCASP_TXTDM_XTDMS23 0x00800000 // XMT mode during TDM time slot 23 + // 0 1 +#define MCASP_TXTDM_XTDMS22 0x00400000 // XMT mode during TDM time slot 22 + // 0 1 +#define MCASP_TXTDM_XTDMS21 0x00200000 // XMT mode during TDM time slot 21 + // 0 1 +#define MCASP_TXTDM_XTDMS20 0x00100000 // XMT mode during TDM time slot 20 + // 0 1 +#define MCASP_TXTDM_XTDMS19 0x00080000 // XMT mode during TDM time slot 19 + // 0 1 +#define MCASP_TXTDM_XTDMS18 0x00040000 // XMT mode during TDM time slot 18 + // 0 1 +#define MCASP_TXTDM_XTDMS17 0x00020000 // XMT mode during TDM time slot 17 + // 0 1 +#define MCASP_TXTDM_XTDMS16 0x00010000 // XMT mode during TDM time slot 16 + // 0 1 +#define MCASP_TXTDM_XTDMS15 0x00008000 // XMT mode during TDM time slot 15 + // 0 1 +#define MCASP_TXTDM_XTDMS14 0x00004000 // XMT mode during TDM time slot 14 + // 0 1 +#define MCASP_TXTDM_XTDMS13 0x00002000 // XMT mode during TDM time slot 13 + // 0 1 +#define MCASP_TXTDM_XTDMS12 0x00001000 // XMT mode during TDM time slot 12 + // 0 1 +#define MCASP_TXTDM_XTDMS11 0x00000800 // XMT mode during TDM time slot 11 + // 0 1 +#define MCASP_TXTDM_XTDMS10 0x00000400 // XMT mode during TDM time slot 10 + // 0 1 +#define MCASP_TXTDM_XTDMS9 0x00000200 // XMT mode during TDM time slot 9 + // 0 1 +#define MCASP_TXTDM_XTDMS8 0x00000100 // XMT mode during TDM time slot 8 + // 0 1 +#define MCASP_TXTDM_XTDMS7 0x00000080 // XMT mode during TDM time slot 7 + // 0 1 +#define MCASP_TXTDM_XTDMS6 0x00000040 // XMT mode during TDM time slot 6 + // 0 1 +#define MCASP_TXTDM_XTDMS5 0x00000020 // XMT mode during TDM time slot 5 + // 0 1 +#define MCASP_TXTDM_XTDMS4 0x00000010 // XMT mode during TDM time slot 4 + // 0 1 +#define MCASP_TXTDM_XTDMS3 0x00000008 // XMT mode during TDM time slot 3 + // 0 1 +#define MCASP_TXTDM_XTDMS2 0x00000004 // XMT mode during TDM time slot 2 + // 0 1 +#define MCASP_TXTDM_XTDMS1 0x00000002 // XMT mode during TDM time slot 1 + // 0 1 +#define MCASP_TXTDM_XTDMS0 0x00000001 // XMT mode during TDM time slot 0 + // 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_EVTCTLX register. +// +//****************************************************************************** +#define MCASP_EVTCTLX_XSTAFRM 0x00000080 // XMT Start of Frame Interrupt 0 1 +#define MCASP_EVTCTLX_XDATA 0x00000020 // XMT Data Interrupt 0 1 +#define MCASP_EVTCTLX_XLAST 0x00000010 // XMT Last Slot Interrupt 0 1 +#define MCASP_EVTCTLX_XDMAERR 0x00000008 // XMT DMA Bus Error 0 1 +#define MCASP_EVTCTLX_XCKFAIL 0x00000004 // Bad Clock Interrupt 0 1 +#define MCASP_EVTCTLX_XSYNCERR 0x00000002 // XMT Unexpected FSR Interrupt 0 1 +#define MCASP_EVTCTLX_XUNDRN 0x00000001 // XMT Underrun Interrupt 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXSTAT register. +// +//****************************************************************************** +#define MCASP_TXSTAT_XERR 0x00000100 // XMT Error 0 1 +#define MCASP_TXSTAT_XDMAERR 0x00000080 // XMT DMA bus error 0 1 +#define MCASP_TXSTAT_XSTAFRM 0x00000040 // Start of Frame-XMT 0 1 +#define MCASP_TXSTAT_XDATA 0x00000020 // Data Ready Flag 0 1 +#define MCASP_TXSTAT_XLAST 0x00000010 // Last Slot Interrupt Flag 0 1 +#define MCASP_TXSTAT_XTDMSLOT 0x00000008 // EvenOdd Slot 0 1 +#define MCASP_TXSTAT_XCKFAIL 0x00000004 // Bad Transmit Flag 0 1 +#define MCASP_TXSTAT_XSYNCERR 0x00000002 // Unexpected XMT Frame sync flag 0 + // 1 +#define MCASP_TXSTAT_XUNDRN 0x00000001 // XMT Underrun Flag 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXTDMSLOT register. +// +//****************************************************************************** +#define MCASP_TXTDMSLOT_XSLOTCNT_M \ + 0x000003FF // Current XMT time slot count + // during reset the value of this + // register is 0b0101111111 (0x17f) + // and after reset 0 + +#define MCASP_TXTDMSLOT_XSLOTCNT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXCLKCHK register. +// +//****************************************************************************** +#define MCASP_TXCLKCHK_XCNT_M 0xFF000000 // XMT clock count value +#define MCASP_TXCLKCHK_XCNT_S 24 +#define MCASP_TXCLKCHK_XMAX_M 0x00FF0000 // XMT clock maximum boundary +#define MCASP_TXCLKCHK_XMAX_S 16 +#define MCASP_TXCLKCHK_XMIN_M 0x0000FF00 // XMT clock minimum boundary +#define MCASP_TXCLKCHK_XMIN_S 8 +#define MCASP_TXCLKCHK_RESV 0x00000080 // Reserved +#define MCASP_TXCLKCHK_XPS_M 0x0000000F // XMT clock check prescaler 0x0 + // 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 +#define MCASP_TXCLKCHK_XPS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XEVTCTL register. +// +//****************************************************************************** +#define MCASP_XEVTCTL_XDATDMA 0x00000001 // XMT data DMA request 0 Enable + // DMA Transfer 1 Disable DMA + // Transfer +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_CLKADJEN register. +// +//****************************************************************************** +#define MCASP_CLKADJEN_ENABLE 0x00000001 // One-shot clock adjust enable 0 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRA0 register. +// +//****************************************************************************** +#define MCASP_DITCSRA0_DITCSRA0_M \ + 0xFFFFFFFF // Left (Even TDM slot ) Channel + // status + +#define MCASP_DITCSRA0_DITCSRA0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRA1 register. +// +//****************************************************************************** +#define MCASP_DITCSRA1_DITCSRA1_M \ + 0xFFFFFFFF // Left (Even TDM slot ) Channel + // status + +#define MCASP_DITCSRA1_DITCSRA1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRA2 register. +// +//****************************************************************************** +#define MCASP_DITCSRA2_DITCSRA2_M \ + 0xFFFFFFFF // Left (Even TDM slot ) Channel + // status Register + +#define MCASP_DITCSRA2_DITCSRA2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRA3 register. +// +//****************************************************************************** +#define MCASP_DITCSRA3_DITCSRA3_M \ + 0xFFFFFFFF // Left (Even TDM slot ) Channel + // status Register + +#define MCASP_DITCSRA3_DITCSRA3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRA4 register. +// +//****************************************************************************** +#define MCASP_DITCSRA4_DITCSRA4_M \ + 0xFFFFFFFF // Left (Even TDM slot ) Channel + // status + +#define MCASP_DITCSRA4_DITCSRA4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRA5 register. +// +//****************************************************************************** +#define MCASP_DITCSRA5_DITCSRA5_M \ + 0xFFFFFFFF // Left (Even TDM slot ) Channel + // status + +#define MCASP_DITCSRA5_DITCSRA5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRB0 register. +// +//****************************************************************************** +#define MCASP_DITCSRB0_DITCSRB0_M \ + 0xFFFFFFFF // Right (odd TDM slot ) Channel + // status + +#define MCASP_DITCSRB0_DITCSRB0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRB1 register. +// +//****************************************************************************** +#define MCASP_DITCSRB1_DITCSRB1_M \ + 0xFFFFFFFF // Right (odd TDM slot ) Channel + // status + +#define MCASP_DITCSRB1_DITCSRB1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRB2 register. +// +//****************************************************************************** +#define MCASP_DITCSRB2_DITCSRB2_M \ + 0xFFFFFFFF // Right (odd TDM slot ) Channel + // status + +#define MCASP_DITCSRB2_DITCSRB2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRB3 register. +// +//****************************************************************************** +#define MCASP_DITCSRB3_DITCSRB3_M \ + 0xFFFFFFFF // Right (odd TDM slot ) Channel + // status + +#define MCASP_DITCSRB3_DITCSRB3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRB4 register. +// +//****************************************************************************** +#define MCASP_DITCSRB4_DITCSRB4_M \ + 0xFFFFFFFF // Right (odd TDM slot ) Channel + // status + +#define MCASP_DITCSRB4_DITCSRB4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITCSRB5 register. +// +//****************************************************************************** +#define MCASP_DITCSRB5_DITCSRB5_M \ + 0xFFFFFFFF // Right (odd TDM slot ) Channel + // status + +#define MCASP_DITCSRB5_DITCSRB5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRA0 register. +// +//****************************************************************************** +#define MCASP_DITUDRA0_DITUDRA0_M \ + 0xFFFFFFFF // Left (Even TDM slot ) User Data + +#define MCASP_DITUDRA0_DITUDRA0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRA1 register. +// +//****************************************************************************** +#define MCASP_DITUDRA1_DITUDRA1_M \ + 0xFFFFFFFF // Left (Even TDM slot ) User Data + +#define MCASP_DITUDRA1_DITUDRA1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRA2 register. +// +//****************************************************************************** +#define MCASP_DITUDRA2_DITUDRA2_M \ + 0xFFFFFFFF // Left (Even TDM slot ) User Data + +#define MCASP_DITUDRA2_DITUDRA2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRA3 register. +// +//****************************************************************************** +#define MCASP_DITUDRA3_DITUDRA3_M \ + 0xFFFFFFFF // Left (Even TDM slot ) User Data + +#define MCASP_DITUDRA3_DITUDRA3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRA4 register. +// +//****************************************************************************** +#define MCASP_DITUDRA4_DITUDRA4_M \ + 0xFFFFFFFF // Left (Even TDM slot ) User Data + +#define MCASP_DITUDRA4_DITUDRA4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRA5 register. +// +//****************************************************************************** +#define MCASP_DITUDRA5_DITUDRA5_M \ + 0xFFFFFFFF // Left (Even TDM slot ) User Data + +#define MCASP_DITUDRA5_DITUDRA5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRB0 register. +// +//****************************************************************************** +#define MCASP_DITUDRB0_DITUDRB0_M \ + 0xFFFFFFFF // Right (odd TDM slot ) User Data + +#define MCASP_DITUDRB0_DITUDRB0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRB1 register. +// +//****************************************************************************** +#define MCASP_DITUDRB1_DITUDRB1_M \ + 0xFFFFFFFF // Right (odd TDM slot ) User Data + +#define MCASP_DITUDRB1_DITUDRB1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRB2 register. +// +//****************************************************************************** +#define MCASP_DITUDRB2_DITUDRB2_M \ + 0xFFFFFFFF // Right (odd TDM slot ) User Data + +#define MCASP_DITUDRB2_DITUDRB2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRB3 register. +// +//****************************************************************************** +#define MCASP_DITUDRB3_DITUDRB3_M \ + 0xFFFFFFFF // Right (odd TDM slot ) User Data + +#define MCASP_DITUDRB3_DITUDRB3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRB4 register. +// +//****************************************************************************** +#define MCASP_DITUDRB4_DITUDRB4_M \ + 0xFFFFFFFF // Right (odd TDM slot ) User Data + +#define MCASP_DITUDRB4_DITUDRB4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_DITUDRB5 register. +// +//****************************************************************************** +#define MCASP_DITUDRB5_DITUDRB5_M \ + 0xFFFFFFFF // Right (odd TDM slot ) User Data + +#define MCASP_DITUDRB5_DITUDRB5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL0 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL0_RRDY 0x00000020 +#define MCASP_XRSRCTL0_XRDY 0x00000010 +#define MCASP_XRSRCTL0_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL0_DISMOD_S 2 +#define MCASP_XRSRCTL0_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL0_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL1 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL1_RRDY 0x00000020 +#define MCASP_XRSRCTL1_XRDY 0x00000010 +#define MCASP_XRSRCTL1_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL1_DISMOD_S 2 +#define MCASP_XRSRCTL1_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL1_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL2 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL2_RRDY 0x00000020 +#define MCASP_XRSRCTL2_XRDY 0x00000010 +#define MCASP_XRSRCTL2_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL2_DISMOD_S 2 +#define MCASP_XRSRCTL2_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL2_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL3 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL3_RRDY 0x00000020 +#define MCASP_XRSRCTL3_XRDY 0x00000010 +#define MCASP_XRSRCTL3_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL3_DISMOD_S 2 +#define MCASP_XRSRCTL3_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL3_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL4 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL4_RRDY 0x00000020 +#define MCASP_XRSRCTL4_XRDY 0x00000010 +#define MCASP_XRSRCTL4_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL4_DISMOD_S 2 +#define MCASP_XRSRCTL4_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL4_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL5 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL5_RRDY 0x00000020 +#define MCASP_XRSRCTL5_XRDY 0x00000010 +#define MCASP_XRSRCTL5_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL5_DISMOD_S 2 +#define MCASP_XRSRCTL5_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL5_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL6 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL6_RRDY 0x00000020 +#define MCASP_XRSRCTL6_XRDY 0x00000010 +#define MCASP_XRSRCTL6_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL6_DISMOD_S 2 +#define MCASP_XRSRCTL6_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL6_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL7 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL7_RRDY 0x00000020 +#define MCASP_XRSRCTL7_XRDY 0x00000010 +#define MCASP_XRSRCTL7_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL7_DISMOD_S 2 +#define MCASP_XRSRCTL7_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL7_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL8 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL8_RRDY 0x00000020 +#define MCASP_XRSRCTL8_XRDY 0x00000010 +#define MCASP_XRSRCTL8_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL8_DISMOD_S 2 +#define MCASP_XRSRCTL8_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL8_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL9 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL9_RRDY 0x00000020 +#define MCASP_XRSRCTL9_XRDY 0x00000010 +#define MCASP_XRSRCTL9_DISMOD_M 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high +#define MCASP_XRSRCTL9_DISMOD_S 2 +#define MCASP_XRSRCTL9_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL9_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL10 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL10_RRDY 0x00000020 +#define MCASP_XRSRCTL10_XRDY 0x00000010 +#define MCASP_XRSRCTL10_DISMOD_M \ + 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high + +#define MCASP_XRSRCTL10_DISMOD_S 2 +#define MCASP_XRSRCTL10_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL10_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL11 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL11_RRDY 0x00000020 +#define MCASP_XRSRCTL11_XRDY 0x00000010 +#define MCASP_XRSRCTL11_DISMOD_M \ + 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high + +#define MCASP_XRSRCTL11_DISMOD_S 2 +#define MCASP_XRSRCTL11_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL11_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL12 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL12_RRDY 0x00000020 +#define MCASP_XRSRCTL12_XRDY 0x00000010 +#define MCASP_XRSRCTL12_DISMOD_M \ + 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high + +#define MCASP_XRSRCTL12_DISMOD_S 2 +#define MCASP_XRSRCTL12_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL12_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL13 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL13_RRDY 0x00000020 +#define MCASP_XRSRCTL13_XRDY 0x00000010 +#define MCASP_XRSRCTL13_DISMOD_M \ + 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high + +#define MCASP_XRSRCTL13_DISMOD_S 2 +#define MCASP_XRSRCTL13_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL13_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL14 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL14_RRDY 0x00000020 +#define MCASP_XRSRCTL14_XRDY 0x00000010 +#define MCASP_XRSRCTL14_DISMOD_M \ + 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high + +#define MCASP_XRSRCTL14_DISMOD_S 2 +#define MCASP_XRSRCTL14_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL14_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_XRSRCTL15 register. +// +//****************************************************************************** +#define MCASP_XRSRCTL15_RRDY 0x00000020 +#define MCASP_XRSRCTL15_XRDY 0x00000010 +#define MCASP_XRSRCTL15_DISMOD_M \ + 0x0000000C // Serializer drive state 0x0 Tri + // state 0x1 Reserved 0x2 Drive pin + // low 0x3 Drive pin high + +#define MCASP_XRSRCTL15_DISMOD_S 2 +#define MCASP_XRSRCTL15_SRMOD_M 0x00000003 // Serializer Mode 0x0 InActive + // mode 0x1 Transmit mode 0x2 + // Receive mode +#define MCASP_XRSRCTL15_SRMOD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF0 register. +// +//****************************************************************************** +#define MCASP_TXBUF0_XBUF0_M 0xFFFFFFFF // Transmit Buffer 0 +#define MCASP_TXBUF0_XBUF0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF1 register. +// +//****************************************************************************** +#define MCASP_TXBUF1_XBUF1_M 0xFFFFFFFF // Transmit Buffer 1 +#define MCASP_TXBUF1_XBUF1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF2 register. +// +//****************************************************************************** +#define MCASP_TXBUF2_XBUF2_M 0xFFFFFFFF // Transmit Buffer 2 +#define MCASP_TXBUF2_XBUF2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF3 register. +// +//****************************************************************************** +#define MCASP_TXBUF3_XBUF3_M 0xFFFFFFFF // Transmit Buffer 3 +#define MCASP_TXBUF3_XBUF3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF4 register. +// +//****************************************************************************** +#define MCASP_TXBUF4_XBUF4_M 0xFFFFFFFF // Transmit Buffer 4 +#define MCASP_TXBUF4_XBUF4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF5 register. +// +//****************************************************************************** +#define MCASP_TXBUF5_XBUF5_M 0xFFFFFFFF // Transmit Buffer 5 +#define MCASP_TXBUF5_XBUF5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF6 register. +// +//****************************************************************************** +#define MCASP_TXBUF6_XBUF6_M 0xFFFFFFFF // Transmit Buffer 6 +#define MCASP_TXBUF6_XBUF6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF7 register. +// +//****************************************************************************** +#define MCASP_TXBUF7_XBUF7_M 0xFFFFFFFF // Transmit Buffer 7 +#define MCASP_TXBUF7_XBUF7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF8 register. +// +//****************************************************************************** +#define MCASP_TXBUF8_XBUF8_M 0xFFFFFFFF // Transmit Buffer 8 +#define MCASP_TXBUF8_XBUF8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF9 register. +// +//****************************************************************************** +#define MCASP_TXBUF9_XBUF9_M 0xFFFFFFFF // Transmit Buffer 9 +#define MCASP_TXBUF9_XBUF9_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF10 register. +// +//****************************************************************************** +#define MCASP_TXBUF10_XBUF10_M 0xFFFFFFFF // Transmit Buffer 10 +#define MCASP_TXBUF10_XBUF10_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF11 register. +// +//****************************************************************************** +#define MCASP_TXBUF11_XBUF11_M 0xFFFFFFFF // Transmit Buffer 11 +#define MCASP_TXBUF11_XBUF11_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF12 register. +// +//****************************************************************************** +#define MCASP_TXBUF12_XBUF12_M 0xFFFFFFFF // Transmit Buffer 12 +#define MCASP_TXBUF12_XBUF12_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF13 register. +// +//****************************************************************************** +#define MCASP_TXBUF13_XBUF13_M 0xFFFFFFFF // Transmit Buffer 13 +#define MCASP_TXBUF13_XBUF13_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF14 register. +// +//****************************************************************************** +#define MCASP_TXBUF14_XBUF14_M 0xFFFFFFFF // Transmit Buffer 14 +#define MCASP_TXBUF14_XBUF14_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_TXBUF15 register. +// +//****************************************************************************** +#define MCASP_TXBUF15_XBUF15_M 0xFFFFFFFF // Transmit Buffer 15 +#define MCASP_TXBUF15_XBUF15_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF0 register. +// +//****************************************************************************** +#define MCASP_RXBUF0_RBUF0_M 0xFFFFFFFF // Receive Buffer 0 +#define MCASP_RXBUF0_RBUF0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF1 register. +// +//****************************************************************************** +#define MCASP_RXBUF1_RBUF1_M 0xFFFFFFFF // Receive Buffer 1 +#define MCASP_RXBUF1_RBUF1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF2 register. +// +//****************************************************************************** +#define MCASP_RXBUF2_RBUF2_M 0xFFFFFFFF // Receive Buffer 2 +#define MCASP_RXBUF2_RBUF2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF3 register. +// +//****************************************************************************** +#define MCASP_RXBUF3_RBUF3_M 0xFFFFFFFF // Receive Buffer 3 +#define MCASP_RXBUF3_RBUF3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF4 register. +// +//****************************************************************************** +#define MCASP_RXBUF4_RBUF4_M 0xFFFFFFFF // Receive Buffer 4 +#define MCASP_RXBUF4_RBUF4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF5 register. +// +//****************************************************************************** +#define MCASP_RXBUF5_RBUF5_M 0xFFFFFFFF // Receive Buffer 5 +#define MCASP_RXBUF5_RBUF5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF6 register. +// +//****************************************************************************** +#define MCASP_RXBUF6_RBUF6_M 0xFFFFFFFF // Receive Buffer 6 +#define MCASP_RXBUF6_RBUF6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF7 register. +// +//****************************************************************************** +#define MCASP_RXBUF7_RBUF7_M 0xFFFFFFFF // Receive Buffer 7 +#define MCASP_RXBUF7_RBUF7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF8 register. +// +//****************************************************************************** +#define MCASP_RXBUF8_RBUF8_M 0xFFFFFFFF // Receive Buffer 8 +#define MCASP_RXBUF8_RBUF8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF9 register. +// +//****************************************************************************** +#define MCASP_RXBUF9_RBUF9_M 0xFFFFFFFF // Receive Buffer 9 +#define MCASP_RXBUF9_RBUF9_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF10 register. +// +//****************************************************************************** +#define MCASP_RXBUF10_RBUF10_M 0xFFFFFFFF // Receive Buffer 10 +#define MCASP_RXBUF10_RBUF10_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF11 register. +// +//****************************************************************************** +#define MCASP_RXBUF11_RBUF11_M 0xFFFFFFFF // Receive Buffer 11 +#define MCASP_RXBUF11_RBUF11_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF12 register. +// +//****************************************************************************** +#define MCASP_RXBUF12_RBUF12_M 0xFFFFFFFF // Receive Buffer 12 +#define MCASP_RXBUF12_RBUF12_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF13 register. +// +//****************************************************************************** +#define MCASP_RXBUF13_RBUF13_M 0xFFFFFFFF // Receive Buffer 13 +#define MCASP_RXBUF13_RBUF13_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF14 register. +// +//****************************************************************************** +#define MCASP_RXBUF14_RBUF14_M 0xFFFFFFFF // Receive Buffer 14 +#define MCASP_RXBUF14_RBUF14_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCASP_O_RXBUF15 register. +// +//****************************************************************************** +#define MCASP_RXBUF15_RBUF15_M 0xFFFFFFFF // Receive Buffer 15 +#define MCASP_RXBUF15_RBUF15_S 0 + + + +#endif // __HW_MCASP_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_mcspi.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_mcspi.h new file mode 100644 index 00000000..079e4b6b --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_mcspi.h @@ -0,0 +1,1745 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_MCSPI_H__ +#define __HW_MCSPI_H__ + +//***************************************************************************** +// +// The following are defines for the MCSPI register offsets. +// +//***************************************************************************** +#define MCSPI_O_HL_REV 0x00000000 // IP Revision Identifier (X.Y.R) + // Used by software to track + // features bugs and compatibility +#define MCSPI_O_HL_HWINFO 0x00000004 // Information about the IP + // module's hardware configuration + // i.e. typically the module's HDL + // generics (if any). Actual field + // format and encoding is up to the + // module's designer to decide. +#define MCSPI_O_HL_SYSCONFIG 0x00000010 // 0x4402 1010 0x4402 2010 Clock + // management configuration +#define MCSPI_O_REVISION 0x00000100 // 0x4402 1100 0x4402 2100 This + // register contains the hard coded + // RTL revision number. +#define MCSPI_O_SYSCONFIG 0x00000110 // 0x4402 1110 0x4402 2110 This + // register allows controlling + // various parameters of the OCP + // interface. +#define MCSPI_O_SYSSTATUS 0x00000114 // 0x4402 1114 0x4402 2114 This + // register provides status + // information about the module + // excluding the interrupt status + // information +#define MCSPI_O_IRQSTATUS 0x00000118 // 0x4402 1118 0x4402 2118 The + // interrupt status regroups all the + // status of the module internal + // events that can generate an + // interrupt +#define MCSPI_O_IRQENABLE 0x0000011C // 0x4402 111C 0x4402 211C This + // register allows to enable/disable + // the module internal sources of + // interrupt on an event-by-event + // basis. +#define MCSPI_O_WAKEUPENABLE 0x00000120 // 0x4402 1120 0x4402 2120 The + // wakeup enable register allows to + // enable/disable the module + // internal sources of wakeup on + // event-by-event basis. +#define MCSPI_O_SYST 0x00000124 // 0x4402 1124 0x4402 2124 This + // register is used to check the + // correctness of the system + // interconnect either internally to + // peripheral bus or externally to + // device IO pads when the module is + // configured in system test + // (SYSTEST) mode. +#define MCSPI_O_MODULCTRL 0x00000128 // 0x4402 1128 0x4402 2128 This + // register is dedicated to the + // configuration of the serial port + // interface. +#define MCSPI_O_CH0CONF 0x0000012C // 0x4402 112C 0x4402 212C This + // register is dedicated to the + // configuration of the channel 0 +#define MCSPI_O_CH0STAT 0x00000130 // 0x4402 1130 0x4402 2130 This + // register provides status + // information about transmitter and + // receiver registers of channel 0 +#define MCSPI_O_CH0CTRL 0x00000134 // 0x4402 1134 0x4402 2134 This + // register is dedicated to enable + // the channel 0 +#define MCSPI_O_TX0 0x00000138 // 0x4402 1138 0x4402 2138 This + // register contains a single SPI + // word to transmit on the serial + // link what ever SPI word length + // is. +#define MCSPI_O_RX0 0x0000013C // 0x4402 113C 0x4402 213C This + // register contains a single SPI + // word received through the serial + // link what ever SPI word length + // is. +#define MCSPI_O_CH1CONF 0x00000140 // 0x4402 1140 0x4402 2140 This + // register is dedicated to the + // configuration of the channel. +#define MCSPI_O_CH1STAT 0x00000144 // 0x4402 1144 0x4402 2144 This + // register provides status + // information about transmitter and + // receiver registers of channel 1 +#define MCSPI_O_CH1CTRL 0x00000148 // 0x4402 1148 0x4402 2148 This + // register is dedicated to enable + // the channel 1 +#define MCSPI_O_TX1 0x0000014C // 0x4402 114C 0x4402 214C This + // register contains a single SPI + // word to transmit on the serial + // link what ever SPI word length + // is. +#define MCSPI_O_RX1 0x00000150 // 0x4402 1150 0x4402 2150 This + // register contains a single SPI + // word received through the serial + // link what ever SPI word length + // is. +#define MCSPI_O_CH2CONF 0x00000154 // 0x4402 1154 0x4402 2154 This + // register is dedicated to the + // configuration of the channel 2 +#define MCSPI_O_CH2STAT 0x00000158 // 0x4402 1158 0x4402 2158 This + // register provides status + // information about transmitter and + // receiver registers of channel 2 +#define MCSPI_O_CH2CTRL 0x0000015C // 0x4402 115C 0x4402 215C This + // register is dedicated to enable + // the channel 2 +#define MCSPI_O_TX2 0x00000160 // 0x4402 1160 0x4402 2160 This + // register contains a single SPI + // word to transmit on the serial + // link what ever SPI word length + // is. +#define MCSPI_O_RX2 0x00000164 // 0x4402 1164 0x4402 2164 This + // register contains a single SPI + // word received through the serial + // link what ever SPI word length + // is. +#define MCSPI_O_CH3CONF 0x00000168 // 0x4402 1168 0x4402 2168 This + // register is dedicated to the + // configuration of the channel 3 +#define MCSPI_O_CH3STAT 0x0000016C // 0x4402 116C 0x4402 216C This + // register provides status + // information about transmitter and + // receiver registers of channel 3 +#define MCSPI_O_CH3CTRL 0x00000170 // 0x4402 1170 0x4402 2170 This + // register is dedicated to enable + // the channel 3 +#define MCSPI_O_TX3 0x00000174 // 0x4402 1174 0x4402 2174 This + // register contains a single SPI + // word to transmit on the serial + // link what ever SPI word length + // is. +#define MCSPI_O_RX3 0x00000178 // 0x4402 1178 0x4402 2178 This + // register contains a single SPI + // word received through the serial + // link what ever SPI word length + // is. +#define MCSPI_O_XFERLEVEL 0x0000017C // 0x4402 117C 0x4402 217C This + // register provides transfer levels + // needed while using FIFO buffer + // during transfer. +#define MCSPI_O_DAFTX 0x00000180 // 0x4402 1180 0x4402 2180 This + // register contains the SPI words + // to transmit on the serial link + // when FIFO used and DMA address is + // aligned on 256 bit.This register + // is an image of one of MCSPI_TX(i) + // register corresponding to the + // channel which have its FIFO + // enabled. +#define MCSPI_O_DAFRX 0x000001A0 // 0x4402 11A0 0x4402 21A0 This + // register contains the SPI words + // to received on the serial link + // when FIFO used and DMA address is + // aligned on 256 bit.This register + // is an image of one of MCSPI_RX(i) + // register corresponding to the + // channel which have its FIFO + // enabled. + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_HL_REV register. +// +//****************************************************************************** +#define MCSPI_HL_REV_SCHEME_M 0xC0000000 +#define MCSPI_HL_REV_SCHEME_S 30 +#define MCSPI_HL_REV_RSVD_M 0x30000000 // Reserved These bits are + // initialized to zero and writes to + // them are ignored. +#define MCSPI_HL_REV_RSVD_S 28 +#define MCSPI_HL_REV_FUNC_M 0x0FFF0000 // Function indicates a software + // compatible module family. If + // there is no level of software + // compatibility a new Func number + // (and hence REVISION) should be + // assigned. +#define MCSPI_HL_REV_FUNC_S 16 +#define MCSPI_HL_REV_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP + // design owner. RTL follows a + // numbering such as X.Y.R.Z which + // are explained in this table. R + // changes ONLY when: (1) PDS + // uploads occur which may have been + // due to spec changes (2) Bug fixes + // occur (3) Resets to '0' when X or + // Y changes. Design team has an + // internal 'Z' (customer invisible) + // number which increments on every + // drop that happens due to DV and + // RTL updates. Z resets to 0 when R + // increments. +#define MCSPI_HL_REV_R_RTL_S 11 +#define MCSPI_HL_REV_X_MAJOR_M 0x00000700 // Major Revision (X) maintained by + // IP specification owner. X changes + // ONLY when: (1) There is a major + // feature addition. An example + // would be adding Master Mode to + // Utopia Level2. The Func field (or + // Class/Type in old PID format) + // will remain the same. X does NOT + // change due to: (1) Bug fixes (2) + // Change in feature parameters. +#define MCSPI_HL_REV_X_MAJOR_S 8 +#define MCSPI_HL_REV_CUSTOM_M 0x000000C0 +#define MCSPI_HL_REV_CUSTOM_S 6 +#define MCSPI_HL_REV_Y_MINOR_M 0x0000003F // Minor Revision (Y) maintained by + // IP specification owner. Y changes + // ONLY when: (1) Features are + // scaled (up or down). Flexibility + // exists in that this feature + // scalability may either be + // represented in the Y change or a + // specific register in the IP that + // indicates which features are + // exactly available. (2) When + // feature creeps from Is-Not list + // to Is list. But this may not be + // the case once it sees silicon; in + // which case X will change. Y does + // NOT change due to: (1) Bug fixes + // (2) Typos or clarifications (3) + // major functional/feature + // change/addition/deletion. Instead + // these changes may be reflected + // via R S X as applicable. Spec + // owner maintains a + // customer-invisible number 'S' + // which changes due to: (1) + // Typos/clarifications (2) Bug + // documentation. Note that this bug + // is not due to a spec change but + // due to implementation. + // Nevertheless the spec tracks the + // IP bugs. An RTL release (say for + // silicon PG1.1) that occurs due to + // bug fix should document the + // corresponding spec number (X.Y.S) + // in its release notes. +#define MCSPI_HL_REV_Y_MINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_HL_HWINFO register. +// +//****************************************************************************** +#define MCSPI_HL_HWINFO_RETMODE 0x00000040 +#define MCSPI_HL_HWINFO_FFNBYTE_M \ + 0x0000003E + +#define MCSPI_HL_HWINFO_FFNBYTE_S 1 +#define MCSPI_HL_HWINFO_USEFIFO 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// MCSPI_O_HL_SYSCONFIG register. +// +//****************************************************************************** +#define MCSPI_HL_SYSCONFIG_IDLEMODE_M \ + 0x0000000C // Configuration of the local + // target state management mode. By + // definition target can handle + // read/write transaction as long as + // it is out of IDLE state. 0x0 + // Force-idle mode: local target's + // idle state follows (acknowledges) + // the system's idle requests + // unconditionally i.e. regardless + // of the IP module's internal + // requirements.Backup mode for + // debug only. 0x1 No-idle mode: + // local target never enters idle + // state.Backup mode for debug only. + // 0x2 Smart-idle mode: local + // target's idle state eventually + // follows (acknowledges) the + // system's idle requests depending + // on the IP module's internal + // requirements.IP module shall not + // generate (IRQ- or + // DMA-request-related) wakeup + // events. 0x3 "Smart-idle + // wakeup-capable mode: local + // target's idle state eventually + // follows (acknowledges) the + // system's idle requests depending + // on the IP module's internal + // requirements.IP module may + // generate (IRQ- or + // DMA-request-related) wakeup + // events when in idle state.Mode is + // only relevant if the appropriate + // IP module ""swakeup"" output(s) + // is (are) implemented." + +#define MCSPI_HL_SYSCONFIG_IDLEMODE_S 2 +#define MCSPI_HL_SYSCONFIG_FREEEMU \ + 0x00000002 // Sensitivity to emulation (debug) + // suspend input signal. 0 IP module + // is sensitive to emulation suspend + // 1 IP module is not sensitive to + // emulation suspend + +#define MCSPI_HL_SYSCONFIG_SOFTRESET \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_REVISION register. +// +//****************************************************************************** +#define MCSPI_REVISION_REV_M 0x000000FF // IP revision [7:4] Major revision + // [3:0] Minor revision Examples: + // 0x10 for 1.0 0x21 for 2.1 +#define MCSPI_REVISION_REV_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_SYSCONFIG register. +// +//****************************************************************************** +#define MCSPI_SYSCONFIG_CLOCKACTIVITY_M \ + 0x00000300 // Clocks activity during wake up + // mode period 0x0 OCP and + // Functional clocks may be switched + // off. 0x1 OCP clock is maintained. + // Functional clock may be + // switched-off. 0x2 Functional + // clock is maintained. OCP clock + // may be switched-off. 0x3 OCP and + // Functional clocks are maintained. + +#define MCSPI_SYSCONFIG_CLOCKACTIVITY_S 8 +#define MCSPI_SYSCONFIG_SIDLEMODE_M \ + 0x00000018 // Power management 0x0 If an idle + // request is detected the McSPI + // acknowledges it unconditionally + // and goes in Inactive mode. + // Interrupt DMA requests and wake + // up lines are unconditionally + // de-asserted and the module wakeup + // capability is deactivated even if + // the bit + // MCSPI_SYSCONFIG[EnaWakeUp] is + // set. 0x1 If an idle request is + // detected the request is ignored + // and the module does not switch to + // wake up mode and keeps on + // behaving normally. 0x2 If an idle + // request is detected the module + // will switch to idle mode based on + // its internal activity. The wake + // up capability cannot be used. 0x3 + // If an idle request is detected + // the module will switch to idle + // mode based on its internal + // activity and the wake up + // capability can be used if the bit + // MCSPI_SYSCONFIG[EnaWakeUp] is + // set. + +#define MCSPI_SYSCONFIG_SIDLEMODE_S 3 +#define MCSPI_SYSCONFIG_ENAWAKEUP \ + 0x00000004 // WakeUp feature control 0 WakeUp + // capability is disabled 1 WakeUp + // capability is enabled + +#define MCSPI_SYSCONFIG_SOFTRESET \ + 0x00000002 // Software reset. During reads it + // always returns 0. 0 (write) + // Normal mode 1 (write) Set this + // bit to 1 to trigger a module + // reset.The bit is automatically + // reset by the hardware. + +#define MCSPI_SYSCONFIG_AUTOIDLE \ + 0x00000001 // Internal OCP Clock gating + // strategy 0 OCP clock is + // free-running 1 Automatic OCP + // clock gating strategy is applied + // based on the OCP interface + // activity + +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_SYSSTATUS register. +// +//****************************************************************************** +#define MCSPI_SYSSTATUS_RESETDONE \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_IRQSTATUS register. +// +//****************************************************************************** +#define MCSPI_IRQSTATUS_EOW 0x00020000 +#define MCSPI_IRQSTATUS_WKS 0x00010000 +#define MCSPI_IRQSTATUS_RX3_FULL \ + 0x00004000 + +#define MCSPI_IRQSTATUS_TX3_UNDERFLOW \ + 0x00002000 + +#define MCSPI_IRQSTATUS_TX3_EMPTY \ + 0x00001000 + +#define MCSPI_IRQSTATUS_RX2_FULL \ + 0x00000400 + +#define MCSPI_IRQSTATUS_TX2_UNDERFLOW \ + 0x00000200 + +#define MCSPI_IRQSTATUS_TX2_EMPTY \ + 0x00000100 + +#define MCSPI_IRQSTATUS_RX1_FULL \ + 0x00000040 + +#define MCSPI_IRQSTATUS_TX1_UNDERFLOW \ + 0x00000020 + +#define MCSPI_IRQSTATUS_TX1_EMPTY \ + 0x00000010 + +#define MCSPI_IRQSTATUS_RX0_OVERFLOW \ + 0x00000008 + +#define MCSPI_IRQSTATUS_RX0_FULL \ + 0x00000004 + +#define MCSPI_IRQSTATUS_TX0_UNDERFLOW \ + 0x00000002 + +#define MCSPI_IRQSTATUS_TX0_EMPTY \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_IRQENABLE register. +// +//****************************************************************************** +#define MCSPI_IRQENABLE_EOW_ENABLE \ + 0x00020000 // End of Word count Interrupt + // Enable. 0 Interrupt disabled 1 + // Interrupt enabled + +#define MCSPI_IRQENABLE_WKE 0x00010000 // Wake Up event interrupt Enable + // in slave mode when an active + // control signal is detected on the + // SPIEN line programmed in the + // field MCSPI_CH0CONF[SPIENSLV] 0 + // Interrupt disabled 1 Interrupt + // enabled +#define MCSPI_IRQENABLE_RX3_FULL_ENABLE \ + 0x00004000 // Receiver register Full Interrupt + // Enable. Ch 3 0 Interrupt disabled + // 1 Interrupt enabled + +#define MCSPI_IRQENABLE_TX3_UNDERFLOW_ENABLE \ + 0x00002000 // Transmitter register Underflow + // Interrupt Enable. Ch 3 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_TX3_EMPTY_ENABLE \ + 0x00001000 // Transmitter register Empty + // Interrupt Enable. Ch3 0 Interrupt + // disabled 1 Interrupt enabled + +#define MCSPI_IRQENABLE_RX2_FULL_ENABLE \ + 0x00000400 // Receiver register Full Interrupt + // Enable. Ch 2 0 Interrupt disabled + // 1 Interrupt enabled + +#define MCSPI_IRQENABLE_TX2_UNDERFLOW_ENABLE \ + 0x00000200 // Transmitter register Underflow + // Interrupt Enable. Ch 2 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_TX2_EMPTY_ENABLE \ + 0x00000100 // Transmitter register Empty + // Interrupt Enable. Ch 2 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_RX1_FULL_ENABLE \ + 0x00000040 // Receiver register Full Interrupt + // Enable. Ch 1 0 Interrupt disabled + // 1 Interrupt enabled + +#define MCSPI_IRQENABLE_TX1_UNDERFLOW_ENABLE \ + 0x00000020 // Transmitter register Underflow + // Interrupt Enable. Ch 1 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_TX1_EMPTY_ENABLE \ + 0x00000010 // Transmitter register Empty + // Interrupt Enable. Ch 1 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_RX0_OVERFLOW_ENABLE \ + 0x00000008 // Receiver register Overflow + // Interrupt Enable. Ch 0 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_RX0_FULL_ENABLE \ + 0x00000004 // Receiver register Full Interrupt + // Enable. Ch 0 0 Interrupt disabled + // 1 Interrupt enabled + +#define MCSPI_IRQENABLE_TX0_UNDERFLOW_ENABLE \ + 0x00000002 // Transmitter register Underflow + // Interrupt Enable. Ch 0 0 + // Interrupt disabled 1 Interrupt + // enabled + +#define MCSPI_IRQENABLE_TX0_EMPTY_ENABLE \ + 0x00000001 // Transmitter register Empty + // Interrupt Enable. Ch 0 0 + // Interrupt disabled 1 Interrupt + // enabled + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// MCSPI_O_WAKEUPENABLE register. +// +//****************************************************************************** +#define MCSPI_WAKEUPENABLE_WKEN 0x00000001 // WakeUp functionality in slave + // mode when an active control + // signal is detected on the SPIEN + // line programmed in the field + // MCSPI_CH0CONF[SPIENSLV] 0 The + // event is not allowed to wakeup + // the system even if the global + // control bit + // MCSPI_SYSCONF[EnaWakeUp] is set. + // 1 The event is allowed to wakeup + // the system if the global control + // bit MCSPI_SYSCONF[EnaWakeUp] is + // set. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_SYST register. +// +//****************************************************************************** +#define MCSPI_SYST_SSB 0x00000800 // Set status bit 0 No action. + // Writing 0 does not clear already + // set status bits; This bit must be + // cleared prior attempting to clear + // a status bit of the + // register. 1 + // Force to 1 all status bits of + // MCSPI_IRQSTATUS register. Writing + // 1 into this bit sets to 1 all + // status bits contained in the + // register. +#define MCSPI_SYST_SPIENDIR 0x00000400 // Set the direction of the + // SPIEN[3:0] lines and SPICLK line + // 0 output (as in master mode) 1 + // input (as in slave mode) +#define MCSPI_SYST_SPIDATDIR1 0x00000200 // Set the direction of the + // SPIDAT[1] 0 output 1 input +#define MCSPI_SYST_SPIDATDIR0 0x00000100 // Set the direction of the + // SPIDAT[0] 0 output 1 input +#define MCSPI_SYST_WAKD 0x00000080 // SWAKEUP output (signal data + // value of internal signal to + // system). The signal is driven + // high or low according to the + // value written into this register + // bit. 0 The pin is driven low. 1 + // The pin is driven high. +#define MCSPI_SYST_SPICLK 0x00000040 // SPICLK line (signal data value) + // If MCSPI_SYST[SPIENDIR] = 1 + // (input mode direction) this bit + // returns the value on the CLKSPI + // line (high or low) and a write + // into this bit has no effect. If + // MCSPI_SYST[SPIENDIR] = 0 (output + // mode direction) the CLKSPI line + // is driven high or low according + // to the value written into this + // register. +#define MCSPI_SYST_SPIDAT_1 0x00000020 // SPIDAT[1] line (signal data + // value) If MCSPI_SYST[SPIDATDIR1] + // = 0 (output mode direction) the + // SPIDAT[1] line is driven high or + // low according to the value + // written into this register. If + // MCSPI_SYST[SPIDATDIR1] = 1 (input + // mode direction) this bit returns + // the value on the SPIDAT[1] line + // (high or low) and a write into + // this bit has no effect. +#define MCSPI_SYST_SPIDAT_0 0x00000010 // SPIDAT[0] line (signal data + // value) If MCSPI_SYST[SPIDATDIR0] + // = 0 (output mode direction) the + // SPIDAT[0] line is driven high or + // low according to the value + // written into this register. If + // MCSPI_SYST[SPIDATDIR0] = 1 (input + // mode direction) this bit returns + // the value on the SPIDAT[0] line + // (high or low) and a write into + // this bit has no effect. +#define MCSPI_SYST_SPIEN_3 0x00000008 // SPIEN[3] line (signal data + // value) If MCSPI_SYST[SPIENDIR] = + // 0 (output mode direction) the + // SPIENT[3] line is driven high or + // low according to the value + // written into this register. If + // MCSPI_SYST[SPIENDIR] = 1 (input + // mode direction) this bit returns + // the value on the SPIEN[3] line + // (high or low) and a write into + // this bit has no effect. +#define MCSPI_SYST_SPIEN_2 0x00000004 // SPIEN[2] line (signal data + // value) If MCSPI_SYST[SPIENDIR] = + // 0 (output mode direction) the + // SPIENT[2] line is driven high or + // low according to the value + // written into this register. If + // MCSPI_SYST[SPIENDIR] = 1 (input + // mode direction) this bit returns + // the value on the SPIEN[2] line + // (high or low) and a write into + // this bit has no effect. +#define MCSPI_SYST_SPIEN_1 0x00000002 // SPIEN[1] line (signal data + // value) If MCSPI_SYST[SPIENDIR] = + // 0 (output mode direction) the + // SPIENT[1] line is driven high or + // low according to the value + // written into this register. If + // MCSPI_SYST[SPIENDIR] = 1 (input + // mode direction) this bit returns + // the value on the SPIEN[1] line + // (high or low) and a write into + // this bit has no effect. +#define MCSPI_SYST_SPIEN_0 0x00000001 // SPIEN[0] line (signal data + // value) If MCSPI_SYST[SPIENDIR] = + // 0 (output mode direction) the + // SPIENT[0] line is driven high or + // low according to the value + // written into this register. If + // MCSPI_SYST[SPIENDIR] = 1 (input + // mode direction) this bit returns + // the value on the SPIEN[0] line + // (high or low) and a write into + // this bit has no effect. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_MODULCTRL register. +// +//****************************************************************************** +#define MCSPI_MODULCTRL_FDAA 0x00000100 // FIFO DMA Address 256-bit aligned + // This register is used when a FIFO + // is managed by the module and DMA + // connected to the controller + // provides only 256 bit aligned + // address. If this bit is set the + // enabled channel which uses the + // FIFO has its datas managed + // through MCSPI_DAFTX and + // MCSPI_DAFRX registers instead of + // MCSPI_TX(i) and MCSPI_RX(i) + // registers. 0 FIFO data managed by + // MCSPI_TX(i) and MCSPI_RX(i) + // registers. 1 FIFO data managed by + // MCSPI_DAFTX and MCSPI_DAFRX + // registers. +#define MCSPI_MODULCTRL_MOA 0x00000080 // Multiple word ocp access: This + // register can only be used when a + // channel is enabled using a FIFO. + // It allows the system to perform + // multiple SPI word access for a + // single 32-bit OCP word access. + // This is possible for WL < 16. 0 + // Multiple word access disabled 1 + // Multiple word access enabled with + // FIFO +#define MCSPI_MODULCTRL_INITDLY_M \ + 0x00000070 // Initial spi delay for first + // transfer: This register is an + // option only available in SINGLE + // master mode The controller waits + // for a delay to transmit the first + // spi word after channel enabled + // and corresponding TX register + // filled. This Delay is based on + // SPI output frequency clock No + // clock output provided to the + // boundary and chip select is not + // active in 4 pin mode within this + // period. 0x0 No delay for first + // spi transfer. 0x1 The controller + // wait 4 spi bus clock 0x2 The + // controller wait 8 spi bus clock + // 0x3 The controller wait 16 spi + // bus clock 0x4 The controller wait + // 32 spi bus clock + +#define MCSPI_MODULCTRL_INITDLY_S 4 +#define MCSPI_MODULCTRL_SYSTEM_TEST \ + 0x00000008 // Enables the system test mode 0 + // Functional mode 1 System test + // mode (SYSTEST) + +#define MCSPI_MODULCTRL_MS 0x00000004 // Master/ Slave 0 Master - The + // module generates the SPICLK and + // SPIEN[3:0] 1 Slave - The module + // receives the SPICLK and + // SPIEN[3:0] +#define MCSPI_MODULCTRL_PIN34 0x00000002 // Pin mode selection: This + // register is used to configure the + // SPI pin mode in master or slave + // mode. If asserted the controller + // only use SIMOSOMI and SPICLK + // clock pin for spi transfers. 0 + // SPIEN is used as a chip select. 1 + // SPIEN is not used.In this mode + // all related option to chip select + // have no meaning. +#define MCSPI_MODULCTRL_SINGLE 0x00000001 // Single channel / Multi Channel + // (master mode only) 0 More than + // one channel will be used in + // master mode. 1 Only one channel + // will be used in master mode. This + // bit must be set in Force SPIEN + // mode. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH0CONF register. +// +//****************************************************************************** +#define MCSPI_CH0CONF_CLKG 0x20000000 // Clock divider granularity This + // register defines the granularity + // of channel clock divider: power + // of two or one clock cycle + // granularity. When this bit is set + // the register MCSPI_CHCTRL[EXTCLK] + // must be configured to reach a + // maximum of 4096 clock divider + // ratio. Then The clock divider + // ratio is a concatenation of + // MCSPI_CHCONF[CLKD] and + // MCSPI_CHCTRL[EXTCLK] values 0 + // Clock granularity of power of two + // 1 One clock cycle ganularity +#define MCSPI_CH0CONF_FFER 0x10000000 // FIFO enabled for receive:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to receive data. 1 The + // buffer is used to receive data. +#define MCSPI_CH0CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to transmit data. 1 The + // buffer is used to transmit data. +#define MCSPI_CH0CONF_TCS0_M 0x06000000 // Chip Select Time Control This + // 2-bits field defines the number + // of interface clock cycles between + // CS toggling and first or last + // edge of SPI clock. 0x0 0.5 clock + // cycle 0x1 1.5 clock cycle 0x2 2.5 + // clock cycle 0x3 3.5 clock cycle +#define MCSPI_CH0CONF_TCS0_S 25 +#define MCSPI_CH0CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit + // polarity is held to 0 during SPI + // transfer. 1 Start bit polarity is + // held to 1 during SPI transfer. +#define MCSPI_CH0CONF_SBE 0x00800000 // Start bit enable for SPI + // transfer 0 Default SPI transfer + // length as specified by WL bit + // field 1 Start bit D/CX added + // before SPI transfer polarity is + // defined by MCSPI_CH0CONF[SBPOL] +#define MCSPI_CH0CONF_SPIENSLV_M \ + 0x00600000 // Channel 0 only and slave mode + // only: SPI slave select signal + // detection. Reserved bits for + // other cases. 0x0 Detection + // enabled only on SPIEN[0] 0x1 + // Detection enabled only on + // SPIEN[1] 0x2 Detection enabled + // only on SPIEN[2] 0x3 Detection + // enabled only on SPIEN[3] + +#define MCSPI_CH0CONF_SPIENSLV_S 21 +#define MCSPI_CH0CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep + // SPIEN active between SPI words. + // (single channel master mode only) + // 0 Writing 0 into this bit drives + // low the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it high when + // MCSPI_CHCONF(i)[EPOL]=1. 1 + // Writing 1 into this bit drives + // high the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it low when + // MCSPI_CHCONF(i)[EPOL]=1 +#define MCSPI_CH0CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is + // deactivated (recommended for + // single SPI word transfer) 1 Turbo + // is activated to maximize the + // throughput for multi SPI words + // transfer. +#define MCSPI_CH0CONF_IS 0x00040000 // Input Select 0 Data Line0 + // (SPIDAT[0]) selected for + // reception. 1 Data Line1 + // (SPIDAT[1]) selected for + // reception +#define MCSPI_CH0CONF_DPE1 0x00020000 // Transmission Enable for data + // line 1 (SPIDATAGZEN[1]) 0 Data + // Line1 (SPIDAT[1]) selected for + // transmission 1 No transmission on + // Data Line1 (SPIDAT[1]) +#define MCSPI_CH0CONF_DPE0 0x00010000 // Transmission Enable for data + // line 0 (SPIDATAGZEN[0]) 0 Data + // Line0 (SPIDAT[0]) selected for + // transmission 1 No transmission on + // Data Line0 (SPIDAT[0]) +#define MCSPI_CH0CONF_DMAR 0x00008000 // DMA Read request The DMA Read + // request line is asserted when the + // channel is enabled and a new data + // is available in the receive + // register of the channel. The DMA + // Read request line is deasserted + // on read completion of the receive + // register of the channel. 0 DMA + // Read Request disabled 1 DMA Read + // Request enabled +#define MCSPI_CH0CONF_DMAW 0x00004000 // DMA Write request. The DMA Write + // request line is asserted when The + // channel is enabled and the + // transmitter register of the + // channel is empty. The DMA Write + // request line is deasserted on + // load completion of the + // transmitter register of the + // channel. 0 DMA Write Request + // disabled 1 DMA Write Request + // enabled +#define MCSPI_CH0CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 + // Transmit and Receive mode 0x1 + // Receive only mode 0x2 Transmit + // only mode 0x3 Reserved +#define MCSPI_CH0CONF_TRM_S 12 +#define MCSPI_CH0CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved + // 0x01 Reserved 0x02 Reserved 0x03 + // The SPI word is 4-bits long 0x04 + // The SPI word is 5-bits long 0x05 + // The SPI word is 6-bits long 0x06 + // The SPI word is 7-bits long 0x07 + // The SPI word is 8-bits long 0x08 + // The SPI word is 9-bits long 0x09 + // The SPI word is 10-bits long 0x0A + // The SPI word is 11-bits long 0x0B + // The SPI word is 12-bits long 0x0C + // The SPI word is 13-bits long 0x0D + // The SPI word is 14-bits long 0x0E + // The SPI word is 15-bits long 0x0F + // The SPI word is 16-bits long 0x10 + // The SPI word is 17-bits long 0x11 + // The SPI word is 18-bits long 0x12 + // The SPI word is 19-bits long 0x13 + // The SPI word is 20-bits long 0x14 + // The SPI word is 21-bits long 0x15 + // The SPI word is 22-bits long 0x16 + // The SPI word is 23-bits long 0x17 + // The SPI word is 24-bits long 0x18 + // The SPI word is 25-bits long 0x19 + // The SPI word is 26-bits long 0x1A + // The SPI word is 27-bits long 0x1B + // The SPI word is 28-bits long 0x1C + // The SPI word is 29-bits long 0x1D + // The SPI word is 30-bits long 0x1E + // The SPI word is 31-bits long 0x1F + // The SPI word is 32-bits long +#define MCSPI_CH0CONF_WL_S 7 +#define MCSPI_CH0CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held + // high during the active state. 1 + // SPIEN is held low during the + // active state. +#define MCSPI_CH0CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. + // (only when the module is a Master + // SPI device). A programmable clock + // divider divides the SPI reference + // clock (CLKSPIREF) with a 4-bit + // value and results in a new clock + // SPICLK available to shift-in and + // shift-out data. By default the + // clock divider ratio has a power + // of two granularity when + // MCSPI_CHCONF[CLKG] is cleared + // Otherwise this register is the 4 + // LSB bit of a 12-bit register + // concatenated with clock divider + // extension MCSPI_CHCTRL[EXTCLK] + // register.The value description + // below defines the clock ratio + // when MCSPI_CHCONF[CLKG] is set to + // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 + // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 + // 512 0xA 1024 0xB 2048 0xC 4096 + // 0xD 8192 0xE 16384 0xF 32768 +#define MCSPI_CH0CONF_CLKD_S 2 +#define MCSPI_CH0CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held + // high during the active state 1 + // SPICLK is held low during the + // active state +#define MCSPI_CH0CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched + // on odd numbered edges of SPICLK. + // 1 Data are latched on even + // numbered edges of SPICLK. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH0STAT register. +// +//****************************************************************************** +#define MCSPI_CH0STAT_RXFFF 0x00000040 +#define MCSPI_CH0STAT_RXFFE 0x00000020 +#define MCSPI_CH0STAT_TXFFF 0x00000010 +#define MCSPI_CH0STAT_TXFFE 0x00000008 +#define MCSPI_CH0STAT_EOT 0x00000004 +#define MCSPI_CH0STAT_TXS 0x00000002 +#define MCSPI_CH0STAT_RXS 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH0CTRL register. +// +//****************************************************************************** +#define MCSPI_CH0CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This + // register is used to concatenate + // with MCSPI_CHCONF[CLKD] register + // for clock ratio only when + // granularity is one clock cycle + // (MCSPI_CHCONF[CLKG] set to 1). + // Then the max value reached is + // 4096 clock divider ratio. 0x00 + // Clock ratio is CLKD + 1 0x01 + // Clock ratio is CLKD + 1 + 16 0xFF + // Clock ratio is CLKD + 1 + 4080 +#define MCSPI_CH0CTRL_EXTCLK_S 8 +#define MCSPI_CH0CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" + // is not active" 1 "Channel ""i"" + // is active" +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_TX0 register. +// +//****************************************************************************** +#define MCSPI_TX0_TDATA_M 0xFFFFFFFF // Channel 0 Data to transmit +#define MCSPI_TX0_TDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_RX0 register. +// +//****************************************************************************** +#define MCSPI_RX0_RDATA_M 0xFFFFFFFF // Channel 0 Received Data +#define MCSPI_RX0_RDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH1CONF register. +// +//****************************************************************************** +#define MCSPI_CH1CONF_CLKG 0x20000000 // Clock divider granularity This + // register defines the granularity + // of channel clock divider: power + // of two or one clock cycle + // granularity. When this bit is set + // the register MCSPI_CHCTRL[EXTCLK] + // must be configured to reach a + // maximum of 4096 clock divider + // ratio. Then The clock divider + // ratio is a concatenation of + // MCSPI_CHCONF[CLKD] and + // MCSPI_CHCTRL[EXTCLK] values 0 + // Clock granularity of power of two + // 1 One clock cycle ganularity +#define MCSPI_CH1CONF_FFER 0x10000000 // FIFO enabled for receive:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to receive data. 1 The + // buffer is used to receive data. +#define MCSPI_CH1CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to transmit data. 1 The + // buffer is used to transmit data. +#define MCSPI_CH1CONF_TCS1_M 0x06000000 // Chip Select Time Control This + // 2-bits field defines the number + // of interface clock cycles between + // CS toggling and first or last + // edge of SPI clock. 0x0 0.5 clock + // cycle 0x1 1.5 clock cycle 0x2 2.5 + // clock cycle 0x3 3.5 clock cycle +#define MCSPI_CH1CONF_TCS1_S 25 +#define MCSPI_CH1CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit + // polarity is held to 0 during SPI + // transfer. 1 Start bit polarity is + // held to 1 during SPI transfer. +#define MCSPI_CH1CONF_SBE 0x00800000 // Start bit enable for SPI + // transfer 0 Default SPI transfer + // length as specified by WL bit + // field 1 Start bit D/CX added + // before SPI transfer polarity is + // defined by MCSPI_CH1CONF[SBPOL] +#define MCSPI_CH1CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep + // SPIEN active between SPI words. + // (single channel master mode only) + // 0 Writing 0 into this bit drives + // low the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it high when + // MCSPI_CHCONF(i)[EPOL]=1. 1 + // Writing 1 into this bit drives + // high the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it low when + // MCSPI_CHCONF(i)[EPOL]=1 +#define MCSPI_CH1CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is + // deactivated (recommended for + // single SPI word transfer) 1 Turbo + // is activated to maximize the + // throughput for multi SPI words + // transfer. +#define MCSPI_CH1CONF_IS 0x00040000 // Input Select 0 Data Line0 + // (SPIDAT[0]) selected for + // reception. 1 Data Line1 + // (SPIDAT[1]) selected for + // reception +#define MCSPI_CH1CONF_DPE1 0x00020000 // Transmission Enable for data + // line 1 (SPIDATAGZEN[1]) 0 Data + // Line1 (SPIDAT[1]) selected for + // transmission 1 No transmission on + // Data Line1 (SPIDAT[1]) +#define MCSPI_CH1CONF_DPE0 0x00010000 // Transmission Enable for data + // line 0 (SPIDATAGZEN[0]) 0 Data + // Line0 (SPIDAT[0]) selected for + // transmission 1 No transmission on + // Data Line0 (SPIDAT[0]) +#define MCSPI_CH1CONF_DMAR 0x00008000 // DMA Read request The DMA Read + // request line is asserted when the + // channel is enabled and a new data + // is available in the receive + // register of the channel. The DMA + // Read request line is deasserted + // on read completion of the receive + // register of the channel. 0 DMA + // Read Request disabled 1 DMA Read + // Request enabled +#define MCSPI_CH1CONF_DMAW 0x00004000 // DMA Write request. The DMA Write + // request line is asserted when The + // channel is enabled and the + // transmitter register of the + // channel is empty. The DMA Write + // request line is deasserted on + // load completion of the + // transmitter register of the + // channel. 0 DMA Write Request + // disabled 1 DMA Write Request + // enabled +#define MCSPI_CH1CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 + // Transmit and Receive mode 0x1 + // Receive only mode 0x2 Transmit + // only mode 0x3 Reserved +#define MCSPI_CH1CONF_TRM_S 12 +#define MCSPI_CH1CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved + // 0x01 Reserved 0x02 Reserved 0x03 + // The SPI word is 4-bits long 0x04 + // The SPI word is 5-bits long 0x05 + // The SPI word is 6-bits long 0x06 + // The SPI word is 7-bits long 0x07 + // The SPI word is 8-bits long 0x08 + // The SPI word is 9-bits long 0x09 + // The SPI word is 10-bits long 0x0A + // The SPI word is 11-bits long 0x0B + // The SPI word is 12-bits long 0x0C + // The SPI word is 13-bits long 0x0D + // The SPI word is 14-bits long 0x0E + // The SPI word is 15-bits long 0x0F + // The SPI word is 16-bits long 0x10 + // The SPI word is 17-bits long 0x11 + // The SPI word is 18-bits long 0x12 + // The SPI word is 19-bits long 0x13 + // The SPI word is 20-bits long 0x14 + // The SPI word is 21-bits long 0x15 + // The SPI word is 22-bits long 0x16 + // The SPI word is 23-bits long 0x17 + // The SPI word is 24-bits long 0x18 + // The SPI word is 25-bits long 0x19 + // The SPI word is 26-bits long 0x1A + // The SPI word is 27-bits long 0x1B + // The SPI word is 28-bits long 0x1C + // The SPI word is 29-bits long 0x1D + // The SPI word is 30-bits long 0x1E + // The SPI word is 31-bits long 0x1F + // The SPI word is 32-bits long +#define MCSPI_CH1CONF_WL_S 7 +#define MCSPI_CH1CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held + // high during the active state. 1 + // SPIEN is held low during the + // active state. +#define MCSPI_CH1CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. + // (only when the module is a Master + // SPI device). A programmable clock + // divider divides the SPI reference + // clock (CLKSPIREF) with a 4-bit + // value and results in a new clock + // SPICLK available to shift-in and + // shift-out data. By default the + // clock divider ratio has a power + // of two granularity when + // MCSPI_CHCONF[CLKG] is cleared + // Otherwise this register is the 4 + // LSB bit of a 12-bit register + // concatenated with clock divider + // extension MCSPI_CHCTRL[EXTCLK] + // register.The value description + // below defines the clock ratio + // when MCSPI_CHCONF[CLKG] is set to + // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 + // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 + // 512 0xA 1024 0xB 2048 0xC 4096 + // 0xD 8192 0xE 16384 0xF 32768 +#define MCSPI_CH1CONF_CLKD_S 2 +#define MCSPI_CH1CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held + // high during the active state 1 + // SPICLK is held low during the + // active state +#define MCSPI_CH1CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched + // on odd numbered edges of SPICLK. + // 1 Data are latched on even + // numbered edges of SPICLK. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH1STAT register. +// +//****************************************************************************** +#define MCSPI_CH1STAT_RXFFF 0x00000040 +#define MCSPI_CH1STAT_RXFFE 0x00000020 +#define MCSPI_CH1STAT_TXFFF 0x00000010 +#define MCSPI_CH1STAT_TXFFE 0x00000008 +#define MCSPI_CH1STAT_EOT 0x00000004 +#define MCSPI_CH1STAT_TXS 0x00000002 +#define MCSPI_CH1STAT_RXS 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH1CTRL register. +// +//****************************************************************************** +#define MCSPI_CH1CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This + // register is used to concatenate + // with MCSPI_CHCONF[CLKD] register + // for clock ratio only when + // granularity is one clock cycle + // (MCSPI_CHCONF[CLKG] set to 1). + // Then the max value reached is + // 4096 clock divider ratio. 0x00 + // Clock ratio is CLKD + 1 0x01 + // Clock ratio is CLKD + 1 + 16 0xFF + // Clock ratio is CLKD + 1 + 4080 +#define MCSPI_CH1CTRL_EXTCLK_S 8 +#define MCSPI_CH1CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" + // is not active" 1 "Channel ""i"" + // is active" +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_TX1 register. +// +//****************************************************************************** +#define MCSPI_TX1_TDATA_M 0xFFFFFFFF // Channel 1 Data to transmit +#define MCSPI_TX1_TDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_RX1 register. +// +//****************************************************************************** +#define MCSPI_RX1_RDATA_M 0xFFFFFFFF // Channel 1 Received Data +#define MCSPI_RX1_RDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH2CONF register. +// +//****************************************************************************** +#define MCSPI_CH2CONF_CLKG 0x20000000 // Clock divider granularity This + // register defines the granularity + // of channel clock divider: power + // of two or one clock cycle + // granularity. When this bit is set + // the register MCSPI_CHCTRL[EXTCLK] + // must be configured to reach a + // maximum of 4096 clock divider + // ratio. Then The clock divider + // ratio is a concatenation of + // MCSPI_CHCONF[CLKD] and + // MCSPI_CHCTRL[EXTCLK] values 0 + // Clock granularity of power of two + // 1 One clock cycle ganularity +#define MCSPI_CH2CONF_FFER 0x10000000 // FIFO enabled for receive:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to receive data. 1 The + // buffer is used to receive data. +#define MCSPI_CH2CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to transmit data. 1 The + // buffer is used to transmit data. +#define MCSPI_CH2CONF_TCS2_M 0x06000000 // Chip Select Time Control This + // 2-bits field defines the number + // of interface clock cycles between + // CS toggling and first or last + // edge of SPI clock. 0x0 0.5 clock + // cycle 0x1 1.5 clock cycle 0x2 2.5 + // clock cycle 0x3 3.5 clock cycle +#define MCSPI_CH2CONF_TCS2_S 25 +#define MCSPI_CH2CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit + // polarity is held to 0 during SPI + // transfer. 1 Start bit polarity is + // held to 1 during SPI transfer. +#define MCSPI_CH2CONF_SBE 0x00800000 // Start bit enable for SPI + // transfer 0 Default SPI transfer + // length as specified by WL bit + // field 1 Start bit D/CX added + // before SPI transfer polarity is + // defined by MCSPI_CH2CONF[SBPOL] +#define MCSPI_CH2CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep + // SPIEN active between SPI words. + // (single channel master mode only) + // 0 Writing 0 into this bit drives + // low the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it high when + // MCSPI_CHCONF(i)[EPOL]=1. 1 + // Writing 1 into this bit drives + // high the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it low when + // MCSPI_CHCONF(i)[EPOL]=1 +#define MCSPI_CH2CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is + // deactivated (recommended for + // single SPI word transfer) 1 Turbo + // is activated to maximize the + // throughput for multi SPI words + // transfer. +#define MCSPI_CH2CONF_IS 0x00040000 // Input Select 0 Data Line0 + // (SPIDAT[0]) selected for + // reception. 1 Data Line1 + // (SPIDAT[1]) selected for + // reception +#define MCSPI_CH2CONF_DPE1 0x00020000 // Transmission Enable for data + // line 1 (SPIDATAGZEN[1]) 0 Data + // Line1 (SPIDAT[1]) selected for + // transmission 1 No transmission on + // Data Line1 (SPIDAT[1]) +#define MCSPI_CH2CONF_DPE0 0x00010000 // Transmission Enable for data + // line 0 (SPIDATAGZEN[0]) 0 Data + // Line0 (SPIDAT[0]) selected for + // transmission 1 No transmission on + // Data Line0 (SPIDAT[0]) +#define MCSPI_CH2CONF_DMAR 0x00008000 // DMA Read request The DMA Read + // request line is asserted when the + // channel is enabled and a new data + // is available in the receive + // register of the channel. The DMA + // Read request line is deasserted + // on read completion of the receive + // register of the channel. 0 DMA + // Read Request disabled 1 DMA Read + // Request enabled +#define MCSPI_CH2CONF_DMAW 0x00004000 // DMA Write request. The DMA Write + // request line is asserted when The + // channel is enabled and the + // transmitter register of the + // channel is empty. The DMA Write + // request line is deasserted on + // load completion of the + // transmitter register of the + // channel. 0 DMA Write Request + // disabled 1 DMA Write Request + // enabled +#define MCSPI_CH2CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 + // Transmit and Receive mode 0x1 + // Receive only mode 0x2 Transmit + // only mode 0x3 Reserved +#define MCSPI_CH2CONF_TRM_S 12 +#define MCSPI_CH2CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved + // 0x01 Reserved 0x02 Reserved 0x03 + // The SPI word is 4-bits long 0x04 + // The SPI word is 5-bits long 0x05 + // The SPI word is 6-bits long 0x06 + // The SPI word is 7-bits long 0x07 + // The SPI word is 8-bits long 0x08 + // The SPI word is 9-bits long 0x09 + // The SPI word is 10-bits long 0x0A + // The SPI word is 11-bits long 0x0B + // The SPI word is 12-bits long 0x0C + // The SPI word is 13-bits long 0x0D + // The SPI word is 14-bits long 0x0E + // The SPI word is 15-bits long 0x0F + // The SPI word is 16-bits long 0x10 + // The SPI word is 17-bits long 0x11 + // The SPI word is 18-bits long 0x12 + // The SPI word is 19-bits long 0x13 + // The SPI word is 20-bits long 0x14 + // The SPI word is 21-bits long 0x15 + // The SPI word is 22-bits long 0x16 + // The SPI word is 23-bits long 0x17 + // The SPI word is 24-bits long 0x18 + // The SPI word is 25-bits long 0x19 + // The SPI word is 26-bits long 0x1A + // The SPI word is 27-bits long 0x1B + // The SPI word is 28-bits long 0x1C + // The SPI word is 29-bits long 0x1D + // The SPI word is 30-bits long 0x1E + // The SPI word is 31-bits long 0x1F + // The SPI word is 32-bits long +#define MCSPI_CH2CONF_WL_S 7 +#define MCSPI_CH2CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held + // high during the active state. 1 + // SPIEN is held low during the + // active state. +#define MCSPI_CH2CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. + // (only when the module is a Master + // SPI device). A programmable clock + // divider divides the SPI reference + // clock (CLKSPIREF) with a 4-bit + // value and results in a new clock + // SPICLK available to shift-in and + // shift-out data. By default the + // clock divider ratio has a power + // of two granularity when + // MCSPI_CHCONF[CLKG] is cleared + // Otherwise this register is the 4 + // LSB bit of a 12-bit register + // concatenated with clock divider + // extension MCSPI_CHCTRL[EXTCLK] + // register.The value description + // below defines the clock ratio + // when MCSPI_CHCONF[CLKG] is set to + // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 + // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 + // 512 0xA 1024 0xB 2048 0xC 4096 + // 0xD 8192 0xE 16384 0xF 32768 +#define MCSPI_CH2CONF_CLKD_S 2 +#define MCSPI_CH2CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held + // high during the active state 1 + // SPICLK is held low during the + // active state +#define MCSPI_CH2CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched + // on odd numbered edges of SPICLK. + // 1 Data are latched on even + // numbered edges of SPICLK. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH2STAT register. +// +//****************************************************************************** +#define MCSPI_CH2STAT_RXFFF 0x00000040 +#define MCSPI_CH2STAT_RXFFE 0x00000020 +#define MCSPI_CH2STAT_TXFFF 0x00000010 +#define MCSPI_CH2STAT_TXFFE 0x00000008 +#define MCSPI_CH2STAT_EOT 0x00000004 +#define MCSPI_CH2STAT_TXS 0x00000002 +#define MCSPI_CH2STAT_RXS 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH2CTRL register. +// +//****************************************************************************** +#define MCSPI_CH2CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This + // register is used to concatenate + // with MCSPI_CHCONF[CLKD] register + // for clock ratio only when + // granularity is one clock cycle + // (MCSPI_CHCONF[CLKG] set to 1). + // Then the max value reached is + // 4096 clock divider ratio. 0x00 + // Clock ratio is CLKD + 1 0x01 + // Clock ratio is CLKD + 1 + 16 0xFF + // Clock ratio is CLKD + 1 + 4080 +#define MCSPI_CH2CTRL_EXTCLK_S 8 +#define MCSPI_CH2CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" + // is not active" 1 "Channel ""i"" + // is active" +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_TX2 register. +// +//****************************************************************************** +#define MCSPI_TX2_TDATA_M 0xFFFFFFFF // Channel 2 Data to transmit +#define MCSPI_TX2_TDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_RX2 register. +// +//****************************************************************************** +#define MCSPI_RX2_RDATA_M 0xFFFFFFFF // Channel 2 Received Data +#define MCSPI_RX2_RDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH3CONF register. +// +//****************************************************************************** +#define MCSPI_CH3CONF_CLKG 0x20000000 // Clock divider granularity This + // register defines the granularity + // of channel clock divider: power + // of two or one clock cycle + // granularity. When this bit is set + // the register MCSPI_CHCTRL[EXTCLK] + // must be configured to reach a + // maximum of 4096 clock divider + // ratio. Then The clock divider + // ratio is a concatenation of + // MCSPI_CHCONF[CLKD] and + // MCSPI_CHCTRL[EXTCLK] values 0 + // Clock granularity of power of two + // 1 One clock cycle ganularity +#define MCSPI_CH3CONF_FFER 0x10000000 // FIFO enabled for receive:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to receive data. 1 The + // buffer is used to receive data. +#define MCSPI_CH3CONF_FFEW 0x08000000 // FIFO enabled for Transmit:Only + // one channel can have this bit + // field set. 0 The buffer is not + // used to transmit data. 1 The + // buffer is used to transmit data. +#define MCSPI_CH3CONF_TCS3_M 0x06000000 // Chip Select Time Control This + // 2-bits field defines the number + // of interface clock cycles between + // CS toggling and first or last + // edge of SPI clock. 0x0 0.5 clock + // cycle 0x1 1.5 clock cycle 0x2 2.5 + // clock cycle 0x3 3.5 clock cycle +#define MCSPI_CH3CONF_TCS3_S 25 +#define MCSPI_CH3CONF_SBPOL 0x01000000 // Start bit polarity 0 Start bit + // polarity is held to 0 during SPI + // transfer. 1 Start bit polarity is + // held to 1 during SPI transfer. +#define MCSPI_CH3CONF_SBE 0x00800000 // Start bit enable for SPI + // transfer 0 Default SPI transfer + // length as specified by WL bit + // field 1 Start bit D/CX added + // before SPI transfer polarity is + // defined by MCSPI_CH3CONF[SBPOL] +#define MCSPI_CH3CONF_FORCE 0x00100000 // Manual SPIEN assertion to keep + // SPIEN active between SPI words. + // (single channel master mode only) + // 0 Writing 0 into this bit drives + // low the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it high when + // MCSPI_CHCONF(i)[EPOL]=1. 1 + // Writing 1 into this bit drives + // high the SPIEN line when + // MCSPI_CHCONF(i)[EPOL]=0 and + // drives it low when + // MCSPI_CHCONF(i)[EPOL]=1 +#define MCSPI_CH3CONF_TURBO 0x00080000 // Turbo mode 0 Turbo is + // deactivated (recommended for + // single SPI word transfer) 1 Turbo + // is activated to maximize the + // throughput for multi SPI words + // transfer. +#define MCSPI_CH3CONF_IS 0x00040000 // Input Select 0 Data Line0 + // (SPIDAT[0]) selected for + // reception. 1 Data Line1 + // (SPIDAT[1]) selected for + // reception +#define MCSPI_CH3CONF_DPE1 0x00020000 // Transmission Enable for data + // line 1 (SPIDATAGZEN[1]) 0 Data + // Line1 (SPIDAT[1]) selected for + // transmission 1 No transmission on + // Data Line1 (SPIDAT[1]) +#define MCSPI_CH3CONF_DPE0 0x00010000 // Transmission Enable for data + // line 0 (SPIDATAGZEN[0]) 0 Data + // Line0 (SPIDAT[0]) selected for + // transmission 1 No transmission on + // Data Line0 (SPIDAT[0]) +#define MCSPI_CH3CONF_DMAR 0x00008000 // DMA Read request The DMA Read + // request line is asserted when the + // channel is enabled and a new data + // is available in the receive + // register of the channel. The DMA + // Read request line is deasserted + // on read completion of the receive + // register of the channel. 0 DMA + // Read Request disabled 1 DMA Read + // Request enabled +#define MCSPI_CH3CONF_DMAW 0x00004000 // DMA Write request. The DMA Write + // request line is asserted when The + // channel is enabled and the + // transmitter register of the + // channel is empty. The DMA Write + // request line is deasserted on + // load completion of the + // transmitter register of the + // channel. 0 DMA Write Request + // disabled 1 DMA Write Request + // enabled +#define MCSPI_CH3CONF_TRM_M 0x00003000 // Transmit/Receive modes 0x0 + // Transmit and Receive mode 0x1 + // Receive only mode 0x2 Transmit + // only mode 0x3 Reserved +#define MCSPI_CH3CONF_TRM_S 12 +#define MCSPI_CH3CONF_WL_M 0x00000F80 // SPI word length 0x00 Reserved + // 0x01 Reserved 0x02 Reserved 0x03 + // The SPI word is 4-bits long 0x04 + // The SPI word is 5-bits long 0x05 + // The SPI word is 6-bits long 0x06 + // The SPI word is 7-bits long 0x07 + // The SPI word is 8-bits long 0x08 + // The SPI word is 9-bits long 0x09 + // The SPI word is 10-bits long 0x0A + // The SPI word is 11-bits long 0x0B + // The SPI word is 12-bits long 0x0C + // The SPI word is 13-bits long 0x0D + // The SPI word is 14-bits long 0x0E + // The SPI word is 15-bits long 0x0F + // The SPI word is 16-bits long 0x10 + // The SPI word is 17-bits long 0x11 + // The SPI word is 18-bits long 0x12 + // The SPI word is 19-bits long 0x13 + // The SPI word is 20-bits long 0x14 + // The SPI word is 21-bits long 0x15 + // The SPI word is 22-bits long 0x16 + // The SPI word is 23-bits long 0x17 + // The SPI word is 24-bits long 0x18 + // The SPI word is 25-bits long 0x19 + // The SPI word is 26-bits long 0x1A + // The SPI word is 27-bits long 0x1B + // The SPI word is 28-bits long 0x1C + // The SPI word is 29-bits long 0x1D + // The SPI word is 30-bits long 0x1E + // The SPI word is 31-bits long 0x1F + // The SPI word is 32-bits long +#define MCSPI_CH3CONF_WL_S 7 +#define MCSPI_CH3CONF_EPOL 0x00000040 // SPIEN polarity 0 SPIEN is held + // high during the active state. 1 + // SPIEN is held low during the + // active state. +#define MCSPI_CH3CONF_CLKD_M 0x0000003C // Frequency divider for SPICLK. + // (only when the module is a Master + // SPI device). A programmable clock + // divider divides the SPI reference + // clock (CLKSPIREF) with a 4-bit + // value and results in a new clock + // SPICLK available to shift-in and + // shift-out data. By default the + // clock divider ratio has a power + // of two granularity when + // MCSPI_CHCONF[CLKG] is cleared + // Otherwise this register is the 4 + // LSB bit of a 12-bit register + // concatenated with clock divider + // extension MCSPI_CHCTRL[EXTCLK] + // register.The value description + // below defines the clock ratio + // when MCSPI_CHCONF[CLKG] is set to + // 0. 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 + // 0x5 32 0x6 64 0x7 128 0x8 256 0x9 + // 512 0xA 1024 0xB 2048 0xC 4096 + // 0xD 8192 0xE 16384 0xF 32768 +#define MCSPI_CH3CONF_CLKD_S 2 +#define MCSPI_CH3CONF_POL 0x00000002 // SPICLK polarity 0 SPICLK is held + // high during the active state 1 + // SPICLK is held low during the + // active state +#define MCSPI_CH3CONF_PHA 0x00000001 // SPICLK phase 0 Data are latched + // on odd numbered edges of SPICLK. + // 1 Data are latched on even + // numbered edges of SPICLK. +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH3STAT register. +// +//****************************************************************************** +#define MCSPI_CH3STAT_RXFFF 0x00000040 +#define MCSPI_CH3STAT_RXFFE 0x00000020 +#define MCSPI_CH3STAT_TXFFF 0x00000010 +#define MCSPI_CH3STAT_TXFFE 0x00000008 +#define MCSPI_CH3STAT_EOT 0x00000004 +#define MCSPI_CH3STAT_TXS 0x00000002 +#define MCSPI_CH3STAT_RXS 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_CH3CTRL register. +// +//****************************************************************************** +#define MCSPI_CH3CTRL_EXTCLK_M 0x0000FF00 // Clock ratio extension: This + // register is used to concatenate + // with MCSPI_CHCONF[CLKD] register + // for clock ratio only when + // granularity is one clock cycle + // (MCSPI_CHCONF[CLKG] set to 1). + // Then the max value reached is + // 4096 clock divider ratio. 0x00 + // Clock ratio is CLKD + 1 0x01 + // Clock ratio is CLKD + 1 + 16 0xFF + // Clock ratio is CLKD + 1 + 4080 +#define MCSPI_CH3CTRL_EXTCLK_S 8 +#define MCSPI_CH3CTRL_EN 0x00000001 // Channel Enable 0 "Channel ""i"" + // is not active" 1 "Channel ""i"" + // is active" +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_TX3 register. +// +//****************************************************************************** +#define MCSPI_TX3_TDATA_M 0xFFFFFFFF // Channel 3 Data to transmit +#define MCSPI_TX3_TDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_RX3 register. +// +//****************************************************************************** +#define MCSPI_RX3_RDATA_M 0xFFFFFFFF // Channel 3 Received Data +#define MCSPI_RX3_RDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_XFERLEVEL register. +// +//****************************************************************************** +#define MCSPI_XFERLEVEL_WCNT_M 0xFFFF0000 // Spi word counterThis register + // holds the programmable value of + // number of SPI word to be + // transferred on channel which is + // using the FIFO buffer.When + // transfer had started a read back + // in this register returns the + // current SPI word transfer index. + // 0x0000 Counter not used 0x0001 + // one word 0xFFFE 65534 spi word + // 0xFFFF 65535 spi word +#define MCSPI_XFERLEVEL_WCNT_S 16 +#define MCSPI_XFERLEVEL_AFL_M 0x0000FF00 // Buffer Almost Full This register + // holds the programmable almost + // full level value used to + // determine almost full buffer + // condition. If the user wants an + // interrupt or a DMA read request + // to be issued during a receive + // operation when the data buffer + // holds at least n bytes then the + // buffer MCSPI_MODULCTRL[AFL] must + // be set with n-1.The size of this + // register is defined by the + // generic parameter FFNBYTE. 0x00 + // one byte 0x01 2 bytes 0xFE + // 255bytes 0xFF 256bytes +#define MCSPI_XFERLEVEL_AFL_S 8 +#define MCSPI_XFERLEVEL_AEL_M 0x000000FF // Buffer Almost EmptyThis register + // holds the programmable almost + // empty level value used to + // determine almost empty buffer + // condition. If the user wants an + // interrupt or a DMA write request + // to be issued during a transmit + // operation when the data buffer is + // able to receive n bytes then the + // buffer MCSPI_MODULCTRL[AEL] must + // be set with n-1. 0x00 one byte + // 0x01 2 bytes 0xFE 255 bytes 0xFF + // 256bytes +#define MCSPI_XFERLEVEL_AEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_DAFTX register. +// +//****************************************************************************** +#define MCSPI_DAFTX_DAFTDATA_M 0xFFFFFFFF // FIFO Data to transmit with DMA + // 256 bit aligned address. "This + // Register is only is used when + // MCSPI_MODULCTRL[FDAA] is set to + // ""1"" and only one of the + // MCSPI_CH(i)CONF[FFEW] of enabled + // channels is set. If these + // conditions are not respected any + // access to this register return a + // null value." +#define MCSPI_DAFTX_DAFTDATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MCSPI_O_DAFRX register. +// +//****************************************************************************** +#define MCSPI_DAFRX_DAFRDATA_M 0xFFFFFFFF // FIFO Data to transmit with DMA + // 256 bit aligned address. "This + // Register is only is used when + // MCSPI_MODULCTRL[FDAA] is set to + // ""1"" and only one of the + // MCSPI_CH(i)CONF[FFEW] of enabled + // channels is set. If these + // conditions are not respected any + // access to this register return a + // null value." +#define MCSPI_DAFRX_DAFRDATA_S 0 + + + +#endif // __HW_MCSPI_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_memmap.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_memmap.h new file mode 100644 index 00000000..244905dd --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_memmap.h @@ -0,0 +1,84 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_MEMMAP_H__ +#define __HW_MEMMAP_H__ + +//***************************************************************************** +// +// The following are defines for the base address of the memories and +// peripherals on the slave_1 interface. +// +//***************************************************************************** +#define FLASH_BASE 0x01000000 +#define SRAM_BASE 0x20000000 +#define WDT_BASE 0x40000000 +#define GPIOA0_BASE 0x40004000 +#define GPIOA1_BASE 0x40005000 +#define GPIOA2_BASE 0x40006000 +#define GPIOA3_BASE 0x40007000 +#define GPIOA4_BASE 0x40024000 +#define UARTA0_BASE 0x4000C000 +#define UARTA1_BASE 0x4000D000 +#define I2CA0_BASE 0x40020000 +#define TIMERA0_BASE 0x40030000 +#define TIMERA1_BASE 0x40031000 +#define TIMERA2_BASE 0x40032000 +#define TIMERA3_BASE 0x40033000 +#define STACKDIE_CTRL_BASE 0x400F5000 +#define COMMON_REG_BASE 0x400F7000 +#define FLASH_CONTROL_BASE 0x400FD000 +#define SYSTEM_CONTROL_BASE 0x400FE000 +#define UDMA_BASE 0x400FF000 +#define SDHOST_BASE 0x44010000 +#define CAMERA_BASE 0x44018000 +#define I2S_BASE 0x4401C000 +#define SSPI_BASE 0x44020000 +#define GSPI_BASE 0x44021000 +#define LSPI_BASE 0x44022000 +#define ARCM_BASE 0x44025000 +#define APPS_CONFIG_BASE 0x44026000 +#define GPRCM_BASE 0x4402D000 +#define OCP_SHARED_BASE 0x4402E000 +#define ADC_BASE 0x4402E800 +#define HIB1P2_BASE 0x4402F000 +#define HIB3P3_BASE 0x4402F800 +#define DTHE_BASE 0x44030000 +#define SHAMD5_BASE 0x44035000 +#define AES_BASE 0x44037000 +#define DES_BASE 0x44039000 + + +#endif // __HW_MEMMAP_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_mmchs.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_mmchs.h new file mode 100644 index 00000000..3096d13a --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_mmchs.h @@ -0,0 +1,1919 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_MMCHS_H__ +#define __HW_MMCHS_H__ + +//***************************************************************************** +// +// The following are defines for the MMCHS register offsets. +// +//***************************************************************************** +#define MMCHS_O_HL_REV 0x00000000 // IP Revision Identifier (X.Y.R) + // Used by software to track + // features bugs and compatibility +#define MMCHS_O_HL_HWINFO 0x00000004 // Information about the IP + // module's hardware configuration + // i.e. typically the module's HDL + // generics (if any). Actual field + // format and encoding is up to the + // module's designer to decide. +#define MMCHS_O_HL_SYSCONFIG 0x00000010 // Clock management configuration +#define MMCHS_O_SYSCONFIG 0x00000110 // System Configuration Register + // This register allows controlling + // various parameters of the OCP + // interface. +#define MMCHS_O_SYSSTATUS 0x00000114 // System Status Register This + // register provides status + // information about the module + // excluding the interrupt status + // information +#define MMCHS_O_CSRE 0x00000124 // Card status response error This + // register enables the host + // controller to detect card status + // errors of response type R1 R1b + // for all cards and of R5 R5b and + // R6 response for cards types SD or + // SDIO. When a bit MMCHS_CSRE[i] is + // set to 1 if the corresponding bit + // at the same position in the + // response MMCHS_RSP0[i] is set to + // 1 the host controller indicates a + // card error (MMCHS_STAT[CERR]) + // interrupt status to avoid the + // host driver reading the response + // register (MMCHS_RSP0). Note: No + // automatic card error detection + // for autoCMD12 is implemented; the + // host system has to check + // autoCMD12 response register + // (MMCHS_RESP76) for possible card + // errors. +#define MMCHS_O_SYSTEST 0x00000128 // System Test register This + // register is used to control the + // signals that connect to I/O pins + // when the module is configured in + // system test (SYSTEST) mode for + // boundary connectivity + // verification. Note: In SYSTEST + // mode a write into MMCHS_CMD + // register will not start a + // transfer. The buffer behaves as a + // stack accessible only by the + // local host (push and pop + // operations). In this mode the + // Transfer Block Size + // (MMCHS_BLK[BLEN]) and the Blocks + // count for current transfer + // (MMCHS_BLK[NBLK]) are needed to + // generate a Buffer write ready + // interrupt (MMCHS_STAT[BWR]) or a + // Buffer read ready interrupt + // (MMCHS_STAT[BRR]) and DMA + // requests if enabled. +#define MMCHS_O_CON 0x0000012C // Configuration register This + // register is used: - to select the + // functional mode or the SYSTEST + // mode for any card. - to send an + // initialization sequence to any + // card. - to enable the detection + // on DAT[1] of a card interrupt for + // SDIO cards only. and also to + // configure : - specific data and + // command transfers for MMC cards + // only. - the parameters related to + // the card detect and write protect + // input signals. +#define MMCHS_O_PWCNT 0x00000130 // Power counter register This + // register is used to program a mmc + // counter to delay command + // transfers after activating the + // PAD power this value depends on + // PAD characteristics and voltage. +#define MMCHS_O_BLK 0x00000204 // Transfer Length Configuration + // register MMCHS_BLK[BLEN] is the + // block size register. + // MMCHS_BLK[NBLK] is the block + // count register. This register + // shall be used for any card. +#define MMCHS_O_ARG 0x00000208 // Command argument Register This + // register contains command + // argument specified as bit 39-8 of + // Command-Format These registers + // must be initialized prior to + // sending the command itself to the + // card (write action into the + // register MMCHS_CMD register). + // Only exception is for a command + // index specifying stuff bits in + // arguments making a write + // unnecessary. +#define MMCHS_O_CMD 0x0000020C // Command and transfer mode + // register MMCHS_CMD[31:16] = the + // command register MMCHS_CMD[15:0] + // = the transfer mode. This + // register configures the data and + // command transfers. A write into + // the most significant byte send + // the command. A write into + // MMCHS_CMD[15:0] registers during + // data transfer has no effect. This + // register shall be used for any + // card. Note: In SYSTEST mode a + // write into MMCHS_CMD register + // will not start a transfer. +#define MMCHS_O_RSP10 0x00000210 // Command response[31:0] Register + // This 32-bit register holds bits + // positions [31:0] of command + // response type + // R1/R1b/R2/R3/R4/R5/R5b/R6 +#define MMCHS_O_RSP32 0x00000214 // Command response[63:32] Register + // This 32-bit register holds bits + // positions [63:32] of command + // response type R2 +#define MMCHS_O_RSP54 0x00000218 // Command response[95:64] Register + // This 32-bit register holds bits + // positions [95:64] of command + // response type R2 +#define MMCHS_O_RSP76 0x0000021C // Command response[127:96] + // Register This 32-bit register + // holds bits positions [127:96] of + // command response type R2 +#define MMCHS_O_DATA 0x00000220 // Data Register This register is + // the 32-bit entry point of the + // buffer for read or write data + // transfers. The buffer size is + // 32bits x256(1024 bytes). Bytes + // within a word are stored and read + // in little endian format. This + // buffer can be used as two 512 + // byte buffers to transfer data + // efficiently without reducing the + // throughput. Sequential and + // contiguous access is necessary to + // increment the pointer correctly. + // Random or skipped access is not + // allowed. In little endian if the + // local host accesses this register + // byte-wise or 16bit-wise the least + // significant byte (bits [7:0]) + // must always be written/read + // first. The update of the buffer + // address is done on the most + // significant byte write for full + // 32-bit DATA register or on the + // most significant byte of the last + // word of block transfer. Example + // 1: Byte or 16-bit access + // Mbyteen[3:0]=0001 (1-byte) => + // Mbyteen[3:0]=0010 (1-byte) => + // Mbyteen[3:0]=1100 (2-bytes) OK + // Mbyteen[3:0]=0001 (1-byte) => + // Mbyteen[3:0]=0010 (1-byte) => + // Mbyteen[3:0]=0100 (1-byte) OK + // Mbyteen[3:0]=0001 (1-byte) => + // Mbyteen[3:0]=0010 (1-byte) => + // Mbyteen[3:0]=1000 (1-byte) Bad +#define MMCHS_O_PSTATE 0x00000224 // Present state register The Host + // can get status of the Host + // Controller from this 32-bit read + // only register. +#define MMCHS_O_HCTL 0x00000228 // Control register This register + // defines the host controls to set + // power wakeup and transfer + // parameters. MMCHS_HCTL[31:24] = + // Wakeup control MMCHS_HCTL[23:16] + // = Block gap control + // MMCHS_HCTL[15:8] = Power control + // MMCHS_HCTL[7:0] = Host control +#define MMCHS_O_SYSCTL 0x0000022C // SD system control register This + // register defines the system + // controls to set software resets + // clock frequency management and + // data timeout. MMCHS_SYSCTL[31:24] + // = Software resets + // MMCHS_SYSCTL[23:16] = Timeout + // control MMCHS_SYSCTL[15:0] = + // Clock control +#define MMCHS_O_STAT 0x00000230 // Interrupt status register The + // interrupt status regroups all the + // status of the module internal + // events that can generate an + // interrupt. MMCHS_STAT[31:16] = + // Error Interrupt Status + // MMCHS_STAT[15:0] = Normal + // Interrupt Status +#define MMCHS_O_IE 0x00000234 // Interrupt SD enable register + // This register allows to + // enable/disable the module to set + // status bits on an event-by-event + // basis. MMCHS_IE[31:16] = Error + // Interrupt Status Enable + // MMCHS_IE[15:0] = Normal Interrupt + // Status Enable +#define MMCHS_O_ISE 0x00000238 // Interrupt signal enable register + // This register allows to + // enable/disable the module + // internal sources of status on an + // event-by-event basis. + // MMCHS_ISE[31:16] = Error + // Interrupt Signal Enable + // MMCHS_ISE[15:0] = Normal + // Interrupt Signal Enable +#define MMCHS_O_AC12 0x0000023C // Auto CMD12 Error Status Register + // The host driver may determine + // which of the errors cases related + // to Auto CMD12 has occurred by + // checking this MMCHS_AC12 register + // when an Auto CMD12 Error + // interrupt occurs. This register + // is valid only when Auto CMD12 is + // enabled (MMCHS_CMD[ACEN]) and + // Auto CMD12Error (MMCHS_STAT[ACE]) + // is set to 1. Note: These bits are + // automatically reset when starting + // a new adtc command with data. +#define MMCHS_O_CAPA 0x00000240 // Capabilities register This + // register lists the capabilities + // of the MMC/SD/SDIO host + // controller. +#define MMCHS_O_CUR_CAPA 0x00000248 // Maximum current capabilities + // Register This register indicates + // the maximum current capability + // for each voltage. The value is + // meaningful if the voltage support + // is set in the capabilities + // register (MMCHS_CAPA). + // Initialization of this register + // (via a write access to this + // register) depends on the system + // capabilities. The host driver + // shall not modify this register + // after the initilaization. This + // register is only reinitialized by + // a hard reset (via RESETN signal) +#define MMCHS_O_FE 0x00000250 // Force Event Register for Error + // Interrupt status The force Event + // Register is not a physically + // implemented register. Rather it + // is an address at which the Error + // Interrupt Status register can be + // written. The effect of a write to + // this address will be reflected in + // the Error Interrupt Status + // Register if corresponding bit of + // the Error Interrupt Status Enable + // Register is set. +#define MMCHS_O_ADMAES 0x00000254 // ADMA Error Status Register When + // ADMA Error Interrupt is occurred + // the ADMA Error States field in + // this register holds the ADMA + // state and the ADMA System Address + // Register holds the address around + // the error descriptor. For + // recovering the error the Host + // Driver requires the ADMA state to + // identify the error descriptor + // address as follows: ST_STOP: + // Previous location set in the ADMA + // System Address register is the + // error descriptor address ST_FDS: + // Current location set in the ADMA + // System Address register is the + // error descriptor address ST_CADR: + // This sate is never set because do + // not generate ADMA error in this + // state. ST_TFR: Previous location + // set in the ADMA System Address + // register is the error descriptor + // address In case of write + // operation the Host Driver should + // use ACMD22 to get the number of + // written block rather than using + // this information since unwritten + // data may exist in the Host + // Controller. The Host Controller + // generates the ADMA Error + // Interrupt when it detects invalid + // descriptor data (Valid=0) at the + // ST_FDS state. In this case ADMA + // Error State indicates that an + // error occurs at ST_FDS state. The + // Host Driver may find that the + // Valid bit is not set in the error + // descriptor. +#define MMCHS_O_ADMASAL 0x00000258 // ADMA System address Low bits +#define MMCHS_O_REV 0x000002FC // Versions Register This register + // contains the hard coded RTL + // vendor revision number the + // version number of SD + // specification compliancy and a + // slot status bit. MMCHS_REV[31:16] + // = Host controller version + // MMCHS_REV[15:0] = Slot Interrupt + // Status + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_HL_REV register. +// +//****************************************************************************** +#define MMCHS_HL_REV_SCHEME_M 0xC0000000 +#define MMCHS_HL_REV_SCHEME_S 30 +#define MMCHS_HL_REV_FUNC_M 0x0FFF0000 // Function indicates a software + // compatible module family. If + // there is no level of software + // compatibility a new Func number + // (and hence REVISION) should be + // assigned. +#define MMCHS_HL_REV_FUNC_S 16 +#define MMCHS_HL_REV_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP + // design owner. RTL follows a + // numbering such as X.Y.R.Z which + // are explained in this table. R + // changes ONLY when: (1) PDS + // uploads occur which may have been + // due to spec changes (2) Bug fixes + // occur (3) Resets to '0' when X or + // Y changes. Design team has an + // internal 'Z' (customer invisible) + // number which increments on every + // drop that happens due to DV and + // RTL updates. Z resets to 0 when R + // increments. +#define MMCHS_HL_REV_R_RTL_S 11 +#define MMCHS_HL_REV_X_MAJOR_M 0x00000700 // Major Revision (X) maintained by + // IP specification owner. X changes + // ONLY when: (1) There is a major + // feature addition. An example + // would be adding Master Mode to + // Utopia Level2. The Func field (or + // Class/Type in old PID format) + // will remain the same. X does NOT + // change due to: (1) Bug fixes (2) + // Change in feature parameters. +#define MMCHS_HL_REV_X_MAJOR_S 8 +#define MMCHS_HL_REV_CUSTOM_M 0x000000C0 +#define MMCHS_HL_REV_CUSTOM_S 6 +#define MMCHS_HL_REV_Y_MINOR_M 0x0000003F // Minor Revision (Y) maintained by + // IP specification owner. Y changes + // ONLY when: (1) Features are + // scaled (up or down). Flexibility + // exists in that this feature + // scalability may either be + // represented in the Y change or a + // specific register in the IP that + // indicates which features are + // exactly available. (2) When + // feature creeps from Is-Not list + // to Is list. But this may not be + // the case once it sees silicon; in + // which case X will change. Y does + // NOT change due to: (1) Bug fixes + // (2) Typos or clarifications (3) + // major functional/feature + // change/addition/deletion. Instead + // these changes may be reflected + // via R S X as applicable. Spec + // owner maintains a + // customer-invisible number 'S' + // which changes due to: (1) + // Typos/clarifications (2) Bug + // documentation. Note that this bug + // is not due to a spec change but + // due to implementation. + // Nevertheless the spec tracks the + // IP bugs. An RTL release (say for + // silicon PG1.1) that occurs due to + // bug fix should document the + // corresponding spec number (X.Y.S) + // in its release notes. +#define MMCHS_HL_REV_Y_MINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_HL_HWINFO register. +// +//****************************************************************************** +#define MMCHS_HL_HWINFO_RETMODE 0x00000040 +#define MMCHS_HL_HWINFO_MEM_SIZE_M \ + 0x0000003C + +#define MMCHS_HL_HWINFO_MEM_SIZE_S 2 +#define MMCHS_HL_HWINFO_MERGE_MEM \ + 0x00000002 + +#define MMCHS_HL_HWINFO_MADMA_EN \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// MMCHS_O_HL_SYSCONFIG register. +// +//****************************************************************************** +#define MMCHS_HL_SYSCONFIG_STANDBYMODE_M \ + 0x00000030 // Configuration of the local + // initiator state management mode. + // By definition initiator may + // generate read/write transaction + // as long as it is out of STANDBY + // state. 0x0 Force-standby mode: + // local initiator is + // unconditionally placed in standby + // state.Backup mode for debug only. + // 0x1 No-standby mode: local + // initiator is unconditionally + // placed out of standby + // state.Backup mode for debug only. + // 0x2 Smart-standby mode: local + // initiator standby status depends + // on local conditions i.e. the + // module's functional requirement + // from the initiator.IP module + // shall not generate + // (initiator-related) wakeup + // events. 0x3 "Smart-Standby + // wakeup-capable mode: local + // initiator standby status depends + // on local conditions i.e. the + // module's functional requirement + // from the initiator. IP module may + // generate (master-related) wakeup + // events when in standby state.Mode + // is only relevant if the + // appropriate IP module ""mwakeup"" + // output is implemented." + +#define MMCHS_HL_SYSCONFIG_STANDBYMODE_S 4 +#define MMCHS_HL_SYSCONFIG_IDLEMODE_M \ + 0x0000000C // Configuration of the local + // target state management mode. By + // definition target can handle + // read/write transaction as long as + // it is out of IDLE state. 0x0 + // Force-idle mode: local target's + // idle state follows (acknowledges) + // the system's idle requests + // unconditionally i.e. regardless + // of the IP module's internal + // requirements.Backup mode for + // debug only. 0x1 No-idle mode: + // local target never enters idle + // state.Backup mode for debug only. + // 0x2 Smart-idle mode: local + // target's idle state eventually + // follows (acknowledges) the + // system's idle requests depending + // on the IP module's internal + // requirements.IP module shall not + // generate (IRQ- or + // DMA-request-related) wakeup + // events. 0x3 "Smart-idle + // wakeup-capable mode: local + // target's idle state eventually + // follows (acknowledges) the + // system's idle requests depending + // on the IP module's internal + // requirements.IP module may + // generate (IRQ- or + // DMA-request-related) wakeup + // events when in idle state.Mode is + // only relevant if the appropriate + // IP module ""swakeup"" output(s) + // is (are) implemented." + +#define MMCHS_HL_SYSCONFIG_IDLEMODE_S 2 +#define MMCHS_HL_SYSCONFIG_FREEEMU \ + 0x00000002 // Sensitivity to emulation (debug) + // suspend input signal. + // Functionality NOT implemented in + // MMCHS. 0 IP module is sensitive + // to emulation suspend 1 IP module + // is not sensitive to emulation + // suspend + +#define MMCHS_HL_SYSCONFIG_SOFTRESET \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_SYSCONFIG register. +// +//****************************************************************************** +#define MMCHS_SYSCONFIG_STANDBYMODE_M \ + 0x00003000 // Master interface power + // Management standby/wait control. + // The bit field is only useful when + // generic parameter MADMA_EN + // (Master ADMA enable) is set as + // active otherwise it is a read + // only register read a '0'. 0x0 + // Force-standby. Mstandby is forced + // unconditionnaly. 0x1 No-standby. + // Mstandby is never asserted. 0x2 + // Smart-standby mode: local + // initiator standby status depends + // on local conditions i.e. the + // module's functional requirement + // from the initiator.IP module + // shall not generate + // (initiator-related) wakeup + // events. 0x3 Smart-Standby + // wakeup-capable mode: "local + // initiator standby status depends + // on local conditions i.e. the + // module's functional requirement + // from the initiator. IP module may + // generate (master-related) wakeup + // events when in standby state.Mode + // is only relevant if the + // appropriate IP module ""mwakeup"" + // output is implemented." + +#define MMCHS_SYSCONFIG_STANDBYMODE_S 12 +#define MMCHS_SYSCONFIG_CLOCKACTIVITY_M \ + 0x00000300 // Clocks activity during wake up + // mode period. Bit8: OCP interface + // clock Bit9: Functional clock 0x0 + // OCP and Functional clock may be + // switched off. 0x1 OCP clock is + // maintained. Functional clock may + // be switched-off. 0x2 Functional + // clock is maintained. OCP clock + // may be switched-off. 0x3 OCP and + // Functional clocks are maintained. + +#define MMCHS_SYSCONFIG_CLOCKACTIVITY_S 8 +#define MMCHS_SYSCONFIG_SIDLEMODE_M \ + 0x00000018 // Power management 0x0 If an idle + // request is detected the MMCHS + // acknowledges it unconditionally + // and goes in Inactive mode. + // Interrupt and DMA requests are + // unconditionally de-asserted. 0x1 + // If an idle request is detected + // the request is ignored and the + // module keeps on behaving + // normally. 0x2 Smart-idle mode: + // local target's idle state + // eventually follows (acknowledges) + // the system's idle requests + // depending on the IP module's + // internal requirements.IP module + // shall not generate (IRQ- or + // DMA-request-related) wakeup + // events. 0x3 Smart-idle + // wakeup-capable mode: "local + // target's idle state eventually + // follows (acknowledges) the + // system's idle requests depending + // on the IP module's internal + // requirements.IP module may + // generate (IRQ- or + // DMA-request-related) wakeup + // events when in idle state.Mode is + // only relevant if the appropriate + // IP module ""swakeup"" output(s) + // is (are) implemented." + +#define MMCHS_SYSCONFIG_SIDLEMODE_S 3 +#define MMCHS_SYSCONFIG_ENAWAKEUP \ + 0x00000004 // Wakeup feature control 0 Wakeup + // capability is disabled 1 Wakeup + // capability is enabled + +#define MMCHS_SYSCONFIG_SOFTRESET \ + 0x00000002 + +#define MMCHS_SYSCONFIG_AUTOIDLE \ + 0x00000001 // Internal Clock gating strategy 0 + // Clocks are free-running 1 + // Automatic clock gating strategy + // is applied based on the OCP and + // MMC interface activity + +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_SYSSTATUS register. +// +//****************************************************************************** +#define MMCHS_SYSSTATUS_RESETDONE \ + 0x00000001 + +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_CSRE register. +// +//****************************************************************************** +#define MMCHS_CSRE_CSRE_M 0xFFFFFFFF // Card status response error +#define MMCHS_CSRE_CSRE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_SYSTEST register. +// +//****************************************************************************** +#define MMCHS_SYSTEST_OBI 0x00010000 +#define MMCHS_SYSTEST_SDCD 0x00008000 +#define MMCHS_SYSTEST_SDWP 0x00004000 +#define MMCHS_SYSTEST_WAKD 0x00002000 +#define MMCHS_SYSTEST_SSB 0x00001000 +#define MMCHS_SYSTEST_D7D 0x00000800 +#define MMCHS_SYSTEST_D6D 0x00000400 +#define MMCHS_SYSTEST_D5D 0x00000200 +#define MMCHS_SYSTEST_D4D 0x00000100 +#define MMCHS_SYSTEST_D3D 0x00000080 +#define MMCHS_SYSTEST_D2D 0x00000040 +#define MMCHS_SYSTEST_D1D 0x00000020 +#define MMCHS_SYSTEST_D0D 0x00000010 +#define MMCHS_SYSTEST_DDIR 0x00000008 +#define MMCHS_SYSTEST_CDAT 0x00000004 +#define MMCHS_SYSTEST_CDIR 0x00000002 +#define MMCHS_SYSTEST_MCKD 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_CON register. +// +//****************************************************************************** +#define MMCHS_CON_SDMA_LNE 0x00200000 // Slave DMA Level/Edge Request: + // The waveform of the DMA request + // can be configured either edge + // sensitive with early de-assertion + // on first access to MMCHS_DATA + // register or late de-assertion + // request remains active until last + // allowed data written into + // MMCHS_DATA. 0 Slave DMA edge + // sensitive Early DMA de-assertion + // 1 Slave DMA level sensitive Late + // DMA de-assertion +#define MMCHS_CON_DMA_MNS 0x00100000 // DMA Master or Slave selection: + // When this bit is set and the + // controller is configured to use + // the DMA Ocp master interface is + // used to get datas from system + // using ADMA2 procedure (direct + // access to the memory).This option + // is only available if generic + // parameter MADMA_EN is asserted to + // '1'. 0 The controller is slave on + // data transfers with system. 1 The + // controller is master on data + // exchange with system controller + // must be configured as using DMA. +#define MMCHS_CON_DDR 0x00080000 // Dual Data Rate mode: When this + // register is set the controller + // uses both clock edge to emit or + // receive data. Odd bytes are + // transmitted on falling edges and + // even bytes are transmitted on + // rise edges. It only applies on + // Data bytes and CRC Start end bits + // and CRC status are kept full + // cycle. This bit field is only + // meaningful and active for even + // clock divider ratio of + // MMCHS_SYSCTL[CLKD] it is + // insensitive to MMCHS_HCTL[HSPE] + // setting. 0 Standard mode : data + // are transmitted on a single edge + // depending on MMCHS_HCTRL[HSPE]. 1 + // Data Bytes and CRC are + // transmitted on both edge. +#define MMCHS_CON_BOOT_CF0 0x00040000 +#define MMCHS_CON_BOOT_ACK 0x00020000 // Book acknowledge received: When + // this bit is set the controller + // should receive a boot status on + // DAT0 line after next command + // issued. If no status is received + // a data timeout will be generated. + // 0 No acknowledge to be received 1 + // A boot status will be received on + // DAT0 line after issuing a + // command. +#define MMCHS_CON_CLKEXTFREE 0x00010000 // External clock free running: + // This register is used to maintain + // card clock out of transfer + // transaction to enable slave + // module for example to generate a + // synchronous interrupt on DAT[1]. + // The Clock will be maintain only + // if MMCHS_SYSCTL[CEN] is set. 0 + // External card clock is cut off + // outside active transaction + // period. 1 External card clock is + // maintain even out of active + // transaction period only if + // MMCHS_SYSCTL[CEN] is set. +#define MMCHS_CON_PADEN 0x00008000 // Control Power for MMC Lines: + // This register is only useful when + // MMC PADs contain power saving + // mechanism to minimize its leakage + // power. It works as a GPIO that + // directly control the ACTIVE pin + // of PADs. Excepted for DAT[1] the + // signal is also combine outside + // the module with the dedicated + // power control MMCHS_CON[CTPL] + // bit. 0 ADPIDLE module pin is not + // forced it is automatically + // generated by the MMC fsms. 1 + // ADPIDLE module pin is forced to + // active state. +#define MMCHS_CON_OBIE 0x00004000 // Out-of-Band Interrupt Enable MMC + // cards only: This bit enables the + // detection of Out-of-Band + // Interrupt on MMCOBI input pin. + // The usage of the Out-of-Band + // signal (OBI) is optional and + // depends on the system + // integration. 0 Out-of-Band + // interrupt detection disabled 1 + // Out-of-Band interrupt detection + // enabled +#define MMCHS_CON_OBIP 0x00002000 // Out-of-Band Interrupt Polarity + // MMC cards only: This bit selects + // the active level of the + // out-of-band interrupt coming from + // MMC cards. The usage of the + // Out-of-Band signal (OBI) is + // optional and depends on the + // system integration. 0 active high + // level 1 active low level +#define MMCHS_CON_CEATA 0x00001000 // CE-ATA control mode MMC cards + // compliant with CE-ATA:By default + // this bit is set to 0. It is use + // to indicate that next commands + // are considered as specific CE-ATA + // commands that potentially use + // 'command completion' features. 0 + // Standard MMC/SD/SDIO mode. 1 + // CE-ATA mode next commands are + // considered as CE-ATA commands. +#define MMCHS_CON_CTPL 0x00000800 // Control Power for DAT[1] line + // MMC and SD cards: By default this + // bit is set to 0 and the host + // controller automatically disables + // all the input buffers outside of + // a transaction to minimize the + // leakage current. SDIO cards: When + // this bit is set to 1 the host + // controller automatically disables + // all the input buffers except the + // buffer of DAT[1] outside of a + // transaction in order to detect + // asynchronous card interrupt on + // DAT[1] line and minimize the + // leakage current of the buffers. 0 + // Disable all the input buffers + // outside of a transaction. 1 + // Disable all the input buffers + // except the buffer of DAT[1] + // outside of a transaction. +#define MMCHS_CON_DVAL_M 0x00000600 // Debounce filter value All cards + // This register is used to define a + // debounce period to filter the + // card detect input signal (SDCD). + // The usage of the card detect + // input signal (SDCD) is optional + // and depends on the system + // integration and the type of the + // connector housing that + // accommodates the card. 0x0 33 us + // debounce period 0x1 231 us + // debounce period 0x2 1 ms debounce + // period 0x3 84 ms debounce period +#define MMCHS_CON_DVAL_S 9 +#define MMCHS_CON_WPP 0x00000100 // Write protect polarity For SD + // and SDIO cards only This bit + // selects the active level of the + // write protect input signal + // (SDWP). The usage of the write + // protect input signal (SDWP) is + // optional and depends on the + // system integration and the type + // of the connector housing that + // accommodates the card. 0 active + // high level 1 active low level +#define MMCHS_CON_CDP 0x00000080 // Card detect polarity All cards + // This bit selects the active level + // of the card detect input signal + // (SDCD). The usage of the card + // detect input signal (SDCD) is + // optional and depends on the + // system integration and the type + // of the connector housing that + // accommodates the card. 0 active + // high level 1 active low level +#define MMCHS_CON_MIT 0x00000040 // MMC interrupt command Only for + // MMC cards. This bit must be set + // to 1 when the next write access + // to the command register + // (MMCHS_CMD) is for writing a MMC + // interrupt command (CMD40) + // requiring the command timeout + // detection to be disabled for the + // command response. 0 Command + // timeout enabled 1 Command timeout + // disabled +#define MMCHS_CON_DW8 0x00000020 // 8-bit mode MMC select For + // SD/SDIO cards this bit must be + // set to 0. For MMC card this bit + // must be set following a valid + // SWITCH command (CMD6) with the + // correct value and extend CSD + // index written in the argument. + // Prior to this command the MMC + // card configuration register (CSD + // and EXT_CSD) must be verified for + // compliancy with MMC standard + // specification 4.x (see section + // 3.6). 0 1-bit or 4-bit Data width + // (DAT[0] used MMC SD cards) 1 + // 8-bit Data width (DAT[7:0] used + // MMC cards) +#define MMCHS_CON_MODE 0x00000010 // Mode select All cards These bits + // select between Functional mode + // and SYSTEST mode. 0 Functional + // mode. Transfers to the + // MMC/SD/SDIO cards follow the card + // protocol. MMC clock is enabled. + // MMC/SD transfers are operated + // under the control of the CMD + // register. 1 SYSTEST mode The + // signal pins are configured as + // general-purpose input/output and + // the 1024-byte buffer is + // configured as a stack memory + // accessible only by the local host + // or system DMA. The pins retain + // their default type (input output + // or in-out). SYSTEST mode is + // operated under the control of the + // SYSTEST register. +#define MMCHS_CON_STR 0x00000008 // Stream command Only for MMC + // cards. This bit must be set to 1 + // only for the stream data + // transfers (read or write) of the + // adtc commands. Stream read is a + // class 1 command (CMD11: + // READ_DAT_UNTIL_STOP). Stream + // write is a class 3 command + // (CMD20: WRITE_DAT_UNTIL_STOP). 0 + // Block oriented data transfer 1 + // Stream oriented data transfer +#define MMCHS_CON_HR 0x00000004 // Broadcast host response Only for + // MMC cards. This register is used + // to force the host to generate a + // 48-bit response for bc command + // type. "It can be used to + // terminate the interrupt mode by + // generating a CMD40 response by + // the core (see section 4.3 + // ""Interrupt Mode"" in the MMC [1] + // specification). In order to have + // the host response to be generated + // in open drain mode the register + // MMCHS_CON[OD] must be set to 1." + // When MMCHS_CON[CEATA] is set to 1 + // and MMCHS_ARG set to 0x00000000 + // when writing 0x00000000 into + // MMCHS_CMD register the host + // controller performs a 'command + // completion signal disable' token + // i.e. CMD line held to '0' during + // 47 cycles followed by a 1. 0 The + // host does not generate a 48-bit + // response instead of a command. 1 + // The host generates a 48-bit + // response instead of a command or + // a command completion signal + // disable token. +#define MMCHS_CON_INIT 0x00000002 // Send initialization stream All + // cards. When this bit is set to 1 + // and the card is idle an + // initialization sequence is sent + // to the card. "An initialization + // sequence consists of setting the + // CMD line to 1 during 80 clock + // cycles. The initialisation + // sequence is mandatory - but it is + // not required to do it through + // this bit - this bit makes it + // easier. Clock divider + // (MMCHS_SYSCTL[CLKD]) should be + // set to ensure that 80 clock + // periods are greater than 1ms. + // (see section 9.3 ""Power-Up"" in + // the MMC card specification [1] or + // section 6.4 in the SD card + // specification [2])." Note: in + // this mode there is no command + // sent to the card and no response + // is expected 0 The host does not + // send an initialization sequence. + // 1 The host sends an + // initialization sequence. +#define MMCHS_CON_OD 0x00000001 // Card open drain mode. Only for + // MMC cards. This bit must be set + // to 1 for MMC card commands 1 2 3 + // and 40 and if the MMC card bus is + // operating in open-drain mode + // during the response phase to the + // command sent. Typically during + // card identification mode when the + // card is either in idle ready or + // ident state. It is also necessary + // to set this bit to 1 for a + // broadcast host response (see + // Broadcast host response register + // MMCHS_CON[HR]) 0 No Open Drain 1 + // Open Drain or Broadcast host + // response +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_PWCNT register. +// +//****************************************************************************** +#define MMCHS_PWCNT_PWRCNT_M 0x0000FFFF // Power counter register. This + // register is used to introduce a + // delay between the PAD ACTIVE pin + // assertion and the command issued. + // 0x0000 No additional delay added + // 0x0001 TCF delay (card clock + // period) 0x0002 TCF x 2 delay + // (card clock period) 0xFFFE TCF x + // 65534 delay (card clock period) + // 0xFFFF TCF x 65535 delay (card + // clock period) +#define MMCHS_PWCNT_PWRCNT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_BLK register. +// +//****************************************************************************** +#define MMCHS_BLK_NBLK_M 0xFFFF0000 // Blocks count for current + // transfer This register is enabled + // when Block count Enable + // (MMCHS_CMD[BCE]) is set to 1 and + // is valid only for multiple block + // transfers. Setting the block + // count to 0 results no data blocks + // being transferred. Note: The host + // controller decrements the block + // count after each block transfer + // and stops when the count reaches + // zero. This register can be + // accessed only if no transaction + // is executing (i.e after a + // transaction has stopped). Read + // operations during transfers may + // return an invalid value and write + // operation will be ignored. In + // suspend context the number of + // blocks yet to be transferred can + // be determined by reading this + // register. When restoring transfer + // context prior to issuing a Resume + // command The local host shall + // restore the previously saved + // block count. 0x0000 Stop count + // 0x0001 1 block 0x0002 2 blocks + // 0xFFFF 65535 blocks +#define MMCHS_BLK_NBLK_S 16 +#define MMCHS_BLK_BLEN_M 0x00000FFF // Transfer Block Size. This + // register specifies the block size + // for block data transfers. Read + // operations during transfers may + // return an invalid value and write + // operations are ignored. When a + // CMD12 command is issued to stop + // the transfer a read of the BLEN + // field after transfer completion + // (MMCHS_STAT[TC] set to 1) will + // not return the true byte number + // of data length while the stop + // occurs but the value written in + // this register before transfer is + // launched. 0x000 No data transfer + // 0x001 1 byte block length 0x002 2 + // bytes block length 0x003 3 bytes + // block length 0x1FF 511 bytes + // block length 0x200 512 bytes + // block length 0x7FF 2047 bytes + // block length 0x800 2048 bytes + // block length +#define MMCHS_BLK_BLEN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_ARG register. +// +//****************************************************************************** +#define MMCHS_ARG_ARG_M 0xFFFFFFFF // Command argument bits [31:0] +#define MMCHS_ARG_ARG_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_CMD register. +// +//****************************************************************************** +#define MMCHS_CMD_INDX_M 0x3F000000 // Command index Binary encoded + // value from 0 to 63 specifying the + // command number send to card 0x00 + // CMD0 or ACMD0 0x01 CMD1 or ACMD1 + // 0x02 CMD2 or ACMD2 0x03 CMD3 or + // ACMD3 0x04 CMD4 or ACMD4 0x05 + // CMD5 or ACMD5 0x06 CMD6 or ACMD6 + // 0x07 CMD7 or ACMD7 0x08 CMD8 or + // ACMD8 0x09 CMD9 or ACMD9 0x0A + // CMD10 or ACMD10 0x0B CMD11 or + // ACMD11 0x0C CMD12 or ACMD12 0x0D + // CMD13 or ACMD13 0x0E CMD14 or + // ACMD14 0x0F CMD15 or ACMD15 0x10 + // CMD16 or ACMD16 0x11 CMD17 or + // ACMD17 0x12 CMD18 or ACMD18 0x13 + // CMD19 or ACMD19 0x14 CMD20 or + // ACMD20 0x15 CMD21 or ACMD21 0x16 + // CMD22 or ACMD22 0x17 CMD23 or + // ACMD23 0x18 CMD24 or ACMD24 0x19 + // CMD25 or ACMD25 0x1A CMD26 or + // ACMD26 0x1B CMD27 or ACMD27 0x1C + // CMD28 or ACMD28 0x1D CMD29 or + // ACMD29 0x1E CMD30 or ACMD30 0x1F + // CMD31 or ACMD31 0x20 CMD32 or + // ACMD32 0x21 CMD33 or ACMD33 0x22 + // CMD34 or ACMD34 0x23 CMD35 or + // ACMD35 0x24 CMD36 or ACMD36 0x25 + // CMD37 or ACMD37 0x26 CMD38 or + // ACMD38 0x27 CMD39 or ACMD39 0x28 + // CMD40 or ACMD40 0x29 CMD41 or + // ACMD41 0x2A CMD42 or ACMD42 0x2B + // CMD43 or ACMD43 0x2C CMD44 or + // ACMD44 0x2D CMD45 or ACMD45 0x2E + // CMD46 or ACMD46 0x2F CMD47 or + // ACMD47 0x30 CMD48 or ACMD48 0x31 + // CMD49 or ACMD49 0x32 CMD50 or + // ACMD50 0x33 CMD51 or ACMD51 0x34 + // CMD52 or ACMD52 0x35 CMD53 or + // ACMD53 0x36 CMD54 or ACMD54 0x37 + // CMD55 or ACMD55 0x38 CMD56 or + // ACMD56 0x39 CMD57 or ACMD57 0x3A + // CMD58 or ACMD58 0x3B CMD59 or + // ACMD59 0x3C CMD60 or ACMD60 0x3D + // CMD61 or ACMD61 0x3E CMD62 or + // ACMD62 0x3F CMD63 or ACMD63 +#define MMCHS_CMD_INDX_S 24 +#define MMCHS_CMD_CMD_TYPE_M 0x00C00000 // Command type This register + // specifies three types of special + // command: Suspend Resume and + // Abort. These bits shall be set to + // 00b for all other commands. 0x0 + // Others Commands 0x1 "CMD52 for + // writing ""Bus Suspend"" in CCCR" + // 0x2 "CMD52 for writing ""Function + // Select"" in CCCR" 0x3 "Abort + // command CMD12 CMD52 for writing + // "" I/O Abort"" in CCCR" +#define MMCHS_CMD_CMD_TYPE_S 22 +#define MMCHS_CMD_DP 0x00200000 // Data present select This + // register indicates that data is + // present and DAT line shall be + // used. It must be set to 0 in the + // following conditions: - command + // using only CMD line - command + // with no data transfer but using + // busy signal on DAT[0] - Resume + // command 0 Command with no data + // transfer 1 Command with data + // transfer +#define MMCHS_CMD_CICE 0x00100000 // Command Index check enable This + // bit must be set to 1 to enable + // index check on command response + // to compare the index field in the + // response against the index of the + // command. If the index is not the + // same in the response as in the + // command it is reported as a + // command index error + // (MMCHS_STAT[CIE] set to1) Note: + // The register CICE cannot be + // configured for an Auto CMD12 then + // index check is automatically + // checked when this command is + // issued. 0 Index check disable 1 + // Index check enable +#define MMCHS_CMD_CCCE 0x00080000 // Command CRC check enable This + // bit must be set to 1 to enable + // CRC7 check on command response to + // protect the response against + // transmission errors on the bus. + // If an error is detected it is + // reported as a command CRC error + // (MMCHS_STAT[CCRC] set to 1). + // Note: The register CCCE cannot be + // configured for an Auto CMD12 and + // then CRC check is automatically + // checked when this command is + // issued. 0 CRC7 check disable 1 + // CRC7 check enable +#define MMCHS_CMD_RSP_TYPE_M 0x00030000 // Response type This bits defines + // the response type of the command + // 0x0 No response 0x1 Response + // Length 136 bits 0x2 Response + // Length 48 bits 0x3 Response + // Length 48 bits with busy after + // response +#define MMCHS_CMD_RSP_TYPE_S 16 +#define MMCHS_CMD_MSBS 0x00000020 // Multi/Single block select This + // bit must be set to 1 for data + // transfer in case of multi block + // command. For any others command + // this bit shall be set to 0. 0 + // Single block. If this bit is 0 it + // is not necessary to set the + // register MMCHS_BLK[NBLK]. 1 Multi + // block. When Block Count is + // disabled (MMCHS_CMD[BCE] is set + // to 0) in Multiple block transfers + // (MMCHS_CMD[MSBS] is set to 1) the + // module can perform infinite + // transfer. +#define MMCHS_CMD_DDIR 0x00000010 // Data transfer Direction Select + // This bit defines either data + // transfer will be a read or a + // write. 0 Data Write (host to + // card) 1 Data Read (card to host) +#define MMCHS_CMD_ACEN 0x00000004 // Auto CMD12 Enable SD card only. + // When this bit is set to 1 the + // host controller issues a CMD12 + // automatically after the transfer + // completion of the last block. The + // Host Driver shall not set this + // bit to issue commands that do not + // require CMD12 to stop data + // transfer. In particular secure + // commands do not require CMD12. 0 + // Auto CMD12 disable 1 Auto CMD12 + // enable or CCS detection enabled. +#define MMCHS_CMD_BCE 0x00000002 // Block Count Enable Multiple + // block transfers only. This bit is + // used to enable the block count + // register (MMCHS_BLK[NBLK]). When + // Block Count is disabled + // (MMCHS_CMD[BCE] is set to 0) in + // Multiple block transfers + // (MMCHS_CMD[MSBS] is set to 1) the + // module can perform infinite + // transfer. 0 Block count disabled + // for infinite transfer. 1 Block + // count enabled for multiple block + // transfer with known number of + // blocks +#define MMCHS_CMD_DE 0x00000001 // DMA Enable This bit is used to + // enable DMA mode for host data + // access. 0 DMA mode disable 1 DMA + // mode enable +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_RSP10 register. +// +//****************************************************************************** +#define MMCHS_RSP10_RSP1_M 0xFFFF0000 // Command Response [31:16] +#define MMCHS_RSP10_RSP1_S 16 +#define MMCHS_RSP10_RSP0_M 0x0000FFFF // Command Response [15:0] +#define MMCHS_RSP10_RSP0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_RSP32 register. +// +//****************************************************************************** +#define MMCHS_RSP32_RSP3_M 0xFFFF0000 // Command Response [63:48] +#define MMCHS_RSP32_RSP3_S 16 +#define MMCHS_RSP32_RSP2_M 0x0000FFFF // Command Response [47:32] +#define MMCHS_RSP32_RSP2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_RSP54 register. +// +//****************************************************************************** +#define MMCHS_RSP54_RSP5_M 0xFFFF0000 // Command Response [95:80] +#define MMCHS_RSP54_RSP5_S 16 +#define MMCHS_RSP54_RSP4_M 0x0000FFFF // Command Response [79:64] +#define MMCHS_RSP54_RSP4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_RSP76 register. +// +//****************************************************************************** +#define MMCHS_RSP76_RSP7_M 0xFFFF0000 // Command Response [127:112] +#define MMCHS_RSP76_RSP7_S 16 +#define MMCHS_RSP76_RSP6_M 0x0000FFFF // Command Response [111:96] +#define MMCHS_RSP76_RSP6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_DATA register. +// +//****************************************************************************** +#define MMCHS_DATA_DATA_M 0xFFFFFFFF // Data Register [31:0] In + // functional mode (MMCHS_CON[MODE] + // set to the default value 0) A + // read access to this register is + // allowed only when the buffer read + // enable status is set to 1 + // (MMCHS_PSTATE[BRE]) otherwise a + // bad access (MMCHS_STAT[BADA]) is + // signaled. A write access to this + // register is allowed only when the + // buffer write enable status is set + // to 1(MMCHS_STATE[BWE]) otherwise + // a bad access (MMCHS_STAT[BADA]) + // is signaled and the data is not + // written. +#define MMCHS_DATA_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_PSTATE register. +// +//****************************************************************************** +#define MMCHS_PSTATE_CLEV 0x01000000 +#define MMCHS_PSTATE_DLEV_M 0x00F00000 // DAT[3:0] line signal level + // DAT[3] => bit 23 DAT[2] => bit 22 + // DAT[1] => bit 21 DAT[0] => bit 20 + // This status is used to check DAT + // line level to recover from errors + // and for debugging. This is + // especially useful in detecting + // the busy signal level from + // DAT[0]. The value of these + // registers after reset depends on + // the DAT lines level at that time. +#define MMCHS_PSTATE_DLEV_S 20 +#define MMCHS_PSTATE_WP 0x00080000 +#define MMCHS_PSTATE_CDPL 0x00040000 +#define MMCHS_PSTATE_CSS 0x00020000 +#define MMCHS_PSTATE_CINS 0x00010000 +#define MMCHS_PSTATE_BRE 0x00000800 +#define MMCHS_PSTATE_BWE 0x00000400 +#define MMCHS_PSTATE_RTA 0x00000200 +#define MMCHS_PSTATE_WTA 0x00000100 +#define MMCHS_PSTATE_DLA 0x00000004 +#define MMCHS_PSTATE_DATI 0x00000002 +#define MMCHS_PSTATE_CMDI 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_HCTL register. +// +//****************************************************************************** +#define MMCHS_HCTL_OBWE 0x08000000 // Wakeup event enable for + // 'Out-of-Band' Interrupt. This bit + // enables wakeup events for + // 'Out-of-Band' assertion. Wakeup + // is generated if the wakeup + // feature is enabled + // (MMCHS_SYSCONFIG[ENAWAKEUP]). The + // write to this register is ignored + // when MMCHS_CON[OBIE] is not set. + // 0 Disable wakeup on 'Out-of-Band' + // Interrupt 1 Enable wakeup on + // 'Out-of-Band' Interrupt +#define MMCHS_HCTL_REM 0x04000000 // Wakeup event enable on SD card + // removal This bit enables wakeup + // events for card removal + // assertion. Wakeup is generated if + // the wakeup feature is enabled + // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0 + // Disable wakeup on card removal 1 + // Enable wakeup on card removal +#define MMCHS_HCTL_INS 0x02000000 // Wakeup event enable on SD card + // insertion This bit enables wakeup + // events for card insertion + // assertion. Wakeup is generated if + // the wakeup feature is enabled + // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0 + // Disable wakeup on card insertion + // 1 Enable wakeup on card insertion +#define MMCHS_HCTL_IWE 0x01000000 // Wakeup event enable on SD card + // interrupt This bit enables wakeup + // events for card interrupt + // assertion. Wakeup is generated if + // the wakeup feature is enabled + // (MMCHS_SYSCONFIG[ENAWAKEUP]). 0 + // Disable wakeup on card interrupt + // 1 Enable wakeup on card interrupt +#define MMCHS_HCTL_IBG 0x00080000 // Interrupt block at gap This bit + // is valid only in 4-bit mode of + // SDIO card to enable interrupt + // detection in the interrupt cycle + // at block gap for a multiple block + // transfer. For MMC cards and for + // SD card this bit should be set to + // 0. 0 Disable interrupt detection + // at the block gap in 4-bit mode 1 + // Enable interrupt detection at the + // block gap in 4-bit mode +#define MMCHS_HCTL_RWC 0x00040000 // Read wait control The read wait + // function is optional only for + // SDIO cards. If the card supports + // read wait this bit must be + // enabled then requesting a stop at + // block gap (MMCHS_HCTL[SBGR]) + // generates a read wait period + // after the current end of block. + // Be careful if read wait is not + // supported it may cause a conflict + // on DAT line. 0 Disable Read Wait + // Control. Suspend/Resume cannot be + // supported. 1 Enable Read Wait + // Control +#define MMCHS_HCTL_CR 0x00020000 // Continue request This bit is + // used to restart a transaction + // that was stopped by requesting a + // stop at block gap + // (MMCHS_HCTL[SBGR]). Set this bit + // to 1 restarts the transfer. The + // bit is automatically set to 0 by + // the host controller when transfer + // has restarted i.e DAT line is + // active (MMCHS_PSTATE[DLA]) or + // transferring data + // (MMCHS_PSTATE[WTA]). The Stop at + // block gap request must be + // disabled (MMCHS_HCTL[SBGR]=0) + // before setting this bit. 0 No + // affect 1 transfer restart +#define MMCHS_HCTL_SBGR 0x00010000 // Stop at block gap request This + // bit is used to stop executing a + // transaction at the next block + // gap. The transfer can restart + // with a continue request + // (MMHS_HCTL[CR]) or during a + // suspend/resume sequence. In case + // of read transfer the card must + // support read wait control. In + // case of write transfer the host + // driver shall set this bit after + // all block data written. Until the + // transfer completion + // (MMCHS_STAT[TC] set to 1) the + // host driver shall leave this bit + // set to 1. If this bit is set the + // local host shall not write to the + // data register (MMCHS_DATA). 0 + // Transfer mode 1 Stop at block gap +#define MMCHS_HCTL_SDVS_M 0x00000E00 // SD bus voltage select All cards. + // The host driver should set to + // these bits to select the voltage + // level for the card according to + // the voltage supported by the + // system (MMCHS_CAPA[VS18VS30VS33]) + // before starting a transfer. 0x5 + // 1.8V (Typical) 0x6 3.0V (Typical) + // 0x7 3.3V (Typical) +#define MMCHS_HCTL_SDVS_S 9 +#define MMCHS_HCTL_SDBP 0x00000100 // SD bus power Before setting this + // bit the host driver shall select + // the SD bus voltage + // (MMCHS_HCTL[SDVS]). If the host + // controller detects the No card + // state this bit is automatically + // set to 0. If the module is power + // off a write in the command + // register (MMCHS_CMD) will not + // start the transfer. A write to + // this bit has no effect if the + // selected SD bus voltage + // MMCHS_HCTL[SDVS] is not supported + // according to capability register + // (MMCHS_CAPA[VS*]). 0 Power off 1 + // Power on +#define MMCHS_HCTL_CDSS 0x00000080 // Card Detect Signal Selection + // This bit selects source for the + // card detection.When the source + // for the card detection is + // switched the interrupt should be + // disabled during the switching + // period by clearing the Interrupt + // Status/Signal Enable register in + // order to mask unexpected + // interrupt being caused by the + // glitch. The Interrupt + // Status/Signal Enable should be + // disabled during over the period + // of debouncing. 0 SDCD# is + // selected (for normal use) 1 The + // Card Detect Test Level is + // selected (for test purpose) +#define MMCHS_HCTL_CDTL 0x00000040 // Card Detect Test Level: This bit + // is enabled while the Card Detect + // Signal Selection is set to 1 and + // it indicates card inserted or + // not. 0 No Card 1 Card Inserted +#define MMCHS_HCTL_DMAS_M 0x00000018 // DMA Select Mode: One of + // supported DMA modes can be + // selected. The host driver shall + // check support of DMA modes by + // referring the Capabilities + // register. Use of selected DMA is + // determined by DMA Enable of the + // Transfer Mode register. This + // register is only meaningful when + // MADMA_EN is set to 1. When + // MADMA_EN is set to 0 the bit + // field is read only and returned + // value is 0. 0x0 Reserved 0x1 + // Reserved 0x2 32-bit Address ADMA2 + // is selected 0x3 Reserved +#define MMCHS_HCTL_DMAS_S 3 +#define MMCHS_HCTL_HSPE 0x00000004 // High Speed Enable: Before + // setting this bit the Host Driver + // shall check the High Speed + // Support in the Capabilities + // register. If this bit is set to 0 + // (default) the Host Controller + // outputs CMD line and DAT lines at + // the falling edge of the SD Clock. + // If this bit is set to 1 the Host + // Controller outputs CMD line and + // DAT lines at the rising edge of + // the SD Clock.This bit shall not + // be set when dual data rate mode + // is activated in MMCHS_CON[DDR]. 0 + // Normal speed mode 1 High speed + // mode +#define MMCHS_HCTL_DTW 0x00000002 // Data transfer width For MMC card + // this bit must be set following a + // valid SWITCH command (CMD6) with + // the correct value and extend CSD + // index written in the argument. + // Prior to this command the MMC + // card configuration register (CSD + // and EXT_CSD) must be verified for + // compliance with MMC standard + // specification 4.x (see section + // 3.6). This register has no effect + // when the MMC 8-bit mode is + // selected (register MMCHS_CON[DW8] + // set to1 ) For SD/SDIO cards this + // bit must be set following a valid + // SET_BUS_WIDTH command (ACMD6) + // with the value written in bit 1 + // of the argument. Prior to this + // command the SD card configuration + // register (SCR) must be verified + // for the supported bus width by + // the SD card. 0 1-bit Data width + // (DAT[0] used) 1 4-bit Data width + // (DAT[3:0] used) +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_SYSCTL register. +// +//****************************************************************************** +#define MMCHS_SYSCTL_SRD 0x04000000 // Software reset for DAT line This + // bit is set to 1 for reset and + // released to 0 when completed. DAT + // finite state machine in both + // clock domain are also reset. Here + // below are the registers cleared + // by MMCHS_SYSCTL[SRD]: #VALUE! - + // MMCHS_PSTATE: BRE BWE RTA WTA DLA + // and DATI - MMCHS_HCTL: SBGR and + // CR - MMCHS_STAT: BRR BWR BGE and + // TC OCP and MMC buffer data + // management is reinitialized. 0 + // Reset completed 1 Software reset + // for DAT line +#define MMCHS_SYSCTL_SRC 0x02000000 // Software reset for CMD line This + // bit is set to 1 for reset and + // released to 0 when completed. CMD + // finite state machine in both + // clock domain are also reset. Here + // below the registers cleared by + // MMCHS_SYSCTL[SRC]: - + // MMCHS_PSTATE: CMDI - MMCHS_STAT: + // CC OCP and MMC command status + // management is reinitialized. 0 + // Reset completed 1 Software reset + // for CMD line +#define MMCHS_SYSCTL_SRA 0x01000000 // Software reset for all This bit + // is set to 1 for reset and + // released to 0 when completed. + // This reset affects the entire + // host controller except for the + // card detection circuit and + // capabilities registers. 0 Reset + // completed 1 Software reset for + // all the design +#define MMCHS_SYSCTL_DTO_M 0x000F0000 // Data timeout counter value and + // busy timeout. This value + // determines the interval by which + // DAT lines timeouts are detected. + // The host driver needs to set this + // bitfield based on - the maximum + // read access time (NAC) (Refer to + // the SD Specification Part1 + // Physical Layer) - the data read + // access time values (TAAC and + // NSAC) in the card specific data + // register (CSD) of the card - the + // timeout clock base frequency + // (MMCHS_CAPA[TCF]). If the card + // does not respond within the + // specified number of cycles a data + // timeout error occurs + // (MMCHS_STA[DTO]). The + // MMCHS_SYSCTL[DTO] register is + // also used to check busy duration + // to generate busy timeout for + // commands with busy response or + // for busy programming during a + // write command. Timeout on CRC + // status is generated if no CRC + // token is present after a block + // write. 0x0 TCF x 2^13 0x1 TCF x + // 2^14 0xE TCF x 2^27 0xF Reserved +#define MMCHS_SYSCTL_DTO_S 16 +#define MMCHS_SYSCTL_CLKD_M 0x0000FFC0 // Clock frequency select These + // bits define the ratio between a + // reference clock frequency (system + // dependant) and the output clock + // frequency on the CLK pin of + // either the memory card (MMC SD or + // SDIO). 0x000 Clock Ref bypass + // 0x001 Clock Ref bypass 0x002 + // Clock Ref / 2 0x003 Clock Ref / 3 + // 0x3FF Clock Ref / 1023 +#define MMCHS_SYSCTL_CLKD_S 6 +#define MMCHS_SYSCTL_CEN 0x00000004 // Clock enable This bit controls + // if the clock is provided to the + // card or not. 0 The clock is not + // provided to the card . Clock + // frequency can be changed . 1 The + // clock is provided to the card and + // can be automatically gated when + // MMCHS_SYSCONFIG[AUTOIDLE] is set + // to 1 (default value) . The host + // driver shall wait to set this bit + // to 1 until the Internal clock is + // stable (MMCHS_SYSCTL[ICS]). +#define MMCHS_SYSCTL_ICS 0x00000002 +#define MMCHS_SYSCTL_ICE 0x00000001 // Internal clock enable This + // register controls the internal + // clock activity. In very low power + // state the internal clock is + // stopped. Note: The activity of + // the debounce clock (used for + // wakeup events) and the OCP clock + // (used for reads and writes to the + // module register map) are not + // affected by this register. 0 The + // internal clock is stopped (very + // low power state). 1 The internal + // clock oscillates and can be + // automatically gated when + // MMCHS_SYSCONFIG[AUTOIDLE] is set + // to 1 (default value) . +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_STAT register. +// +//****************************************************************************** +#define MMCHS_STAT_BADA 0x20000000 +#define MMCHS_STAT_CERR 0x10000000 +#define MMCHS_STAT_ADMAE 0x02000000 +#define MMCHS_STAT_ACE 0x01000000 +#define MMCHS_STAT_DEB 0x00400000 +#define MMCHS_STAT_DCRC 0x00200000 +#define MMCHS_STAT_DTO 0x00100000 +#define MMCHS_STAT_CIE 0x00080000 +#define MMCHS_STAT_CEB 0x00040000 +#define MMCHS_STAT_CCRC 0x00020000 +#define MMCHS_STAT_CTO 0x00010000 +#define MMCHS_STAT_ERRI 0x00008000 +#define MMCHS_STAT_BSR 0x00000400 +#define MMCHS_STAT_OBI 0x00000200 +#define MMCHS_STAT_CIRQ 0x00000100 +#define MMCHS_STAT_CREM 0x00000080 +#define MMCHS_STAT_CINS 0x00000040 +#define MMCHS_STAT_BRR 0x00000020 +#define MMCHS_STAT_BWR 0x00000010 +#define MMCHS_STAT_DMA 0x00000008 +#define MMCHS_STAT_BGE 0x00000004 +#define MMCHS_STAT_TC 0x00000002 +#define MMCHS_STAT_CC 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_IE register. +// +//****************************************************************************** +#define MMCHS_IE_BADA_ENABLE 0x20000000 // Bad access to data space + // Interrupt Enable 0 Masked 1 + // Enabled +#define MMCHS_IE_CERR_ENABLE 0x10000000 // Card error interrupt Enable 0 + // Masked 1 Enabled +#define MMCHS_IE_ADMAE_ENABLE 0x02000000 // ADMA error Interrupt Enable 0 + // Masked 1 Enabled +#define MMCHS_IE_ACE_ENABLE 0x01000000 // Auto CMD12 error Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_DEB_ENABLE 0x00400000 // Data end bit error Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_DCRC_ENABLE 0x00200000 // Data CRC error Interrupt Enable + // 0 Masked 1 Enabled +#define MMCHS_IE_DTO_ENABLE 0x00100000 // Data timeout error Interrupt + // Enable 0 The data timeout + // detection is deactivated. The + // host controller provides the + // clock to the card until the card + // sends the data or the transfer is + // aborted. 1 The data timeout + // detection is enabled. +#define MMCHS_IE_CIE_ENABLE 0x00080000 // Command index error Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_CEB_ENABLE 0x00040000 // Command end bit error Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_CCRC_ENABLE 0x00020000 // Command CRC error Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_CTO_ENABLE 0x00010000 // Command timeout error Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_NULL 0x00008000 // Fixed to 0 The host driver shall + // control error interrupts using + // the Error Interrupt Signal Enable + // register. Writes to this bit are + // ignored +#define MMCHS_IE_BSR_ENABLE 0x00000400 // Boot status interrupt Enable A + // write to this register when + // MMCHS_CON[BOOT_ACK] is set to 0x0 + // is ignored. 0 Masked 1 Enabled +#define MMCHS_IE_OBI_ENABLE 0x00000200 // Out-of-Band interrupt Enable A + // write to this register when + // MMCHS_CON[OBIE] is set to '0' is + // ignored. 0 Masked 1 Enabled +#define MMCHS_IE_CIRQ_ENABLE 0x00000100 // Card interrupt Enable A clear of + // this bit also clears the + // corresponding status bit. During + // 1-bit mode if the interrupt + // routine doesn't remove the source + // of a card interrupt in the SDIO + // card the status bit is reasserted + // when this bit is set to 1. 0 + // Masked 1 Enabled +#define MMCHS_IE_CREM_ENABLE 0x00000080 // Card removal Interrupt Enable 0 + // Masked 1 Enabled +#define MMCHS_IE_CINS_ENABLE 0x00000040 // Card insertion Interrupt Enable + // 0 Masked 1 Enabled +#define MMCHS_IE_BRR_ENABLE 0x00000020 // Buffer Read Ready Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_BWR_ENABLE 0x00000010 // Buffer Write Ready Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_DMA_ENABLE 0x00000008 // DMA interrupt Enable 0 Masked 1 + // Enabled +#define MMCHS_IE_BGE_ENABLE 0x00000004 // Block Gap Event Interrupt Enable + // 0 Masked 1 Enabled +#define MMCHS_IE_TC_ENABLE 0x00000002 // Transfer completed Interrupt + // Enable 0 Masked 1 Enabled +#define MMCHS_IE_CC_ENABLE 0x00000001 // Command completed Interrupt + // Enable 0 Masked 1 Enabled +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_ISE register. +// +//****************************************************************************** +#define MMCHS_ISE_BADA_SIGEN 0x20000000 // Bad access to data space signal + // status Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CERR_SIGEN 0x10000000 // Card error interrupt signal + // status Enable 0 Masked 1 Enabled +#define MMCHS_ISE_ADMAE_SIGEN 0x02000000 // ADMA error signal status Enable + // 0 Masked 1 Enabled +#define MMCHS_ISE_ACE_SIGEN 0x01000000 // Auto CMD12 error signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_DEB_SIGEN 0x00400000 // Data end bit error signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_DCRC_SIGEN 0x00200000 // Data CRC error signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_DTO_SIGEN 0x00100000 // Data timeout error signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CIE_SIGEN 0x00080000 // Command index error signal + // status Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CEB_SIGEN 0x00040000 // Command end bit error signal + // status Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CCRC_SIGEN 0x00020000 // Command CRC error signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CTO_SIGEN 0x00010000 // Command timeout error signal + // status Enable 0 Masked 1 Enabled +#define MMCHS_ISE_NULL 0x00008000 // Fixed to 0 The host driver shall + // control error interrupts using + // the Error Interrupt Signal Enable + // register. Writes to this bit are + // ignored +#define MMCHS_ISE_BSR_SIGEN 0x00000400 // Boot status signal status + // EnableA write to this register + // when MMCHS_CON[BOOT_ACK] is set + // to 0x0 is ignored. 0 Masked 1 + // Enabled +#define MMCHS_ISE_OBI_SIGEN 0x00000200 // Out-Of-Band Interrupt signal + // status Enable A write to this + // register when MMCHS_CON[OBIE] is + // set to '0' is ignored. 0 Masked 1 + // Enabled +#define MMCHS_ISE_CIRQ_SIGEN 0x00000100 // Card interrupt signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CREM_SIGEN 0x00000080 // Card removal signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CINS_SIGEN 0x00000040 // Card insertion signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_BRR_SIGEN 0x00000020 // Buffer Read Ready signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_BWR_SIGEN 0x00000010 // Buffer Write Ready signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_DMA_SIGEN 0x00000008 // DMA interrupt Signal status + // enable 0 Masked 1 Enabled +#define MMCHS_ISE_BGE_SIGEN 0x00000004 // Black Gap Event signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_TC_SIGEN 0x00000002 // Transfer completed signal status + // Enable 0 Masked 1 Enabled +#define MMCHS_ISE_CC_SIGEN 0x00000001 // Command completed signal status + // Enable 0 Masked 1 Enabled +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_AC12 register. +// +//****************************************************************************** +#define MMCHS_AC12_CNI 0x00000080 +#define MMCHS_AC12_ACIE 0x00000010 +#define MMCHS_AC12_ACEB 0x00000008 +#define MMCHS_AC12_ACCE 0x00000004 +#define MMCHS_AC12_ACTO 0x00000002 +#define MMCHS_AC12_ACNE 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_CAPA register. +// +//****************************************************************************** +#define MMCHS_CAPA_BIT64 0x10000000 +#define MMCHS_CAPA_VS18 0x04000000 +#define MMCHS_CAPA_VS30 0x02000000 +#define MMCHS_CAPA_VS33 0x01000000 +#define MMCHS_CAPA_SRS 0x00800000 +#define MMCHS_CAPA_DS 0x00400000 +#define MMCHS_CAPA_HSS 0x00200000 +#define MMCHS_CAPA_AD2S 0x00080000 +#define MMCHS_CAPA_MBL_M 0x00030000 +#define MMCHS_CAPA_MBL_S 16 +#define MMCHS_CAPA_BCF_M 0x00003F00 +#define MMCHS_CAPA_BCF_S 8 +#define MMCHS_CAPA_TCU 0x00000080 +#define MMCHS_CAPA_TCF_M 0x0000003F +#define MMCHS_CAPA_TCF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_CUR_CAPA register. +// +//****************************************************************************** +#define MMCHS_CUR_CAPA_CUR_1V8_M \ + 0x00FF0000 + +#define MMCHS_CUR_CAPA_CUR_1V8_S 16 +#define MMCHS_CUR_CAPA_CUR_3V0_M \ + 0x0000FF00 + +#define MMCHS_CUR_CAPA_CUR_3V0_S 8 +#define MMCHS_CUR_CAPA_CUR_3V3_M \ + 0x000000FF + +#define MMCHS_CUR_CAPA_CUR_3V3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_FE register. +// +//****************************************************************************** +#define MMCHS_FE_FE_BADA 0x20000000 +#define MMCHS_FE_FE_CERR 0x10000000 +#define MMCHS_FE_FE_ADMAE 0x02000000 +#define MMCHS_FE_FE_ACE 0x01000000 +#define MMCHS_FE_FE_DEB 0x00400000 +#define MMCHS_FE_FE_DCRC 0x00200000 +#define MMCHS_FE_FE_DTO 0x00100000 +#define MMCHS_FE_FE_CIE 0x00080000 +#define MMCHS_FE_FE_CEB 0x00040000 +#define MMCHS_FE_FE_CCRC 0x00020000 +#define MMCHS_FE_FE_CTO 0x00010000 +#define MMCHS_FE_FE_CNI 0x00000080 +#define MMCHS_FE_FE_ACIE 0x00000010 +#define MMCHS_FE_FE_ACEB 0x00000008 +#define MMCHS_FE_FE_ACCE 0x00000004 +#define MMCHS_FE_FE_ACTO 0x00000002 +#define MMCHS_FE_FE_ACNE 0x00000001 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_ADMAES register. +// +//****************************************************************************** +#define MMCHS_ADMAES_LME 0x00000004 // ADMA Length Mismatch Error: (1) + // While Block Count Enable being + // set the total data length + // specified by the Descriptor table + // is different from that specified + // by the Block Count and Block + // Length. (2) Total data length can + // not be divided by the block + // length. 0 No Error 1 Error +#define MMCHS_ADMAES_AES_M 0x00000003 // ADMA Error State his field + // indicates the state of ADMA when + // error is occurred during ADMA + // data transfer. "This field never + // indicates ""10"" because ADMA + // never stops in this state." 0x0 + // ST_STOP (Stop DMA)Contents of + // SYS_SDR register 0x1 ST_STOP + // (Stop DMA)Points the error + // descriptor 0x2 Never set this + // state(Not used) 0x3 ST_TFR + // (Transfer Data)Points the next of + // the error descriptor +#define MMCHS_ADMAES_AES_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_ADMASAL register. +// +//****************************************************************************** +#define MMCHS_ADMASAL_ADMA_A32B_M \ + 0xFFFFFFFF // ADMA System address 32 bits.This + // register holds byte address of + // executing command of the + // Descriptor table. 32-bit Address + // Descriptor uses lower 32-bit of + // this register. At the start of + // ADMA the Host Driver shall set + // start address of the Descriptor + // table. The ADMA increments this + // register address which points to + // next line when every fetching a + // Descriptor line. When the ADMA + // Error Interrupt is generated this + // register shall hold valid + // Descriptor address depending on + // the ADMA state. The Host Driver + // shall program Descriptor Table on + // 32-bit boundary and set 32-bit + // boundary address to this + // register. ADMA2 ignores lower + // 2-bit of this register and + // assumes it to be 00b. + +#define MMCHS_ADMASAL_ADMA_A32B_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the MMCHS_O_REV register. +// +//****************************************************************************** +#define MMCHS_REV_VREV_M 0xFF000000 // Vendor Version Number: IP + // revision [7:4] Major revision + // [3:0] Minor revision Examples: + // 0x10 for 1.0 0x21 for 2.1 +#define MMCHS_REV_VREV_S 24 +#define MMCHS_REV_SREV_M 0x00FF0000 +#define MMCHS_REV_SREV_S 16 +#define MMCHS_REV_SIS 0x00000001 // Slot Interrupt Status This + // status bit indicates the inverted + // state of interrupt signal for the + // module. By a power on reset or by + // setting a software reset for all + // (MMCHS_HCTL[SRA]) the interrupt + // signal shall be de-asserted and + // this status shall read 0. + + + +#endif // __HW_MMCHS_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_nvic.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_nvic.h new file mode 100644 index 00000000..1545f226 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_nvic.h @@ -0,0 +1,1710 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +//***************************************************************************** +// +// hw_nvic.h - Macros used when accessing the NVIC hardware. +// +//***************************************************************************** + +#ifndef __HW_NVIC_H__ +#define __HW_NVIC_H__ + +//***************************************************************************** +// +// The following are defines for the NVIC register addresses. +// +//***************************************************************************** +#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg +#define NVIC_ACTLR 0xE000E008 // Auxiliary Control +#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status + // Register +#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register +#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register +#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg + +#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable +#define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable +#define NVIC_EN2 0xE000E108 // Interrupt 64-95 Set Enable +#define NVIC_EN3 0xE000E10C // Interrupt 96-127 Set Enable +#define NVIC_EN4 0xE000E110 // Interrupt 128-131 Set Enable +#define NVIC_EN5 0xE000E114 // Interrupt 160-191 Set Enable + +#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable +#define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable + +#define NVIC_DIS2 0xE000E188 // Interrupt 64-95 Clear Enable +#define NVIC_DIS3 0xE000E18C // Interrupt 96-127 Clear Enable +#define NVIC_DIS4 0xE000E190 // Interrupt 128-131 Clear Enable +#define NVIC_DIS5 0xE000E194 // Interrupt 160-191 Clear Enable + +#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending +#define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending + +#define NVIC_PEND2 0xE000E208 // Interrupt 64-95 Set Pending +#define NVIC_PEND3 0xE000E20C // Interrupt 96-127 Set Pending +#define NVIC_PEND4 0xE000E210 // Interrupt 128-131 Set Pending +#define NVIC_PEND5 0xE000E214 // Interrupt 160-191 Set Pending + +#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending +#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending + +#define NVIC_UNPEND2 0xE000E288 // Interrupt 64-95 Clear Pending +#define NVIC_UNPEND3 0xE000E28C // Interrupt 96-127 Clear Pending +#define NVIC_UNPEND4 0xE000E290 // Interrupt 128-131 Clear Pending +#define NVIC_UNPEND5 0xE000E294 // Interrupt 160-191 Clear Pending + +#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit +#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit + +#define NVIC_ACTIVE2 0xE000E308 // Interrupt 64-95 Active Bit +#define NVIC_ACTIVE3 0xE000E30C // Interrupt 96-127 Active Bit +#define NVIC_ACTIVE4 0xE000E310 // Interrupt 128-131 Active Bit +#define NVIC_ACTIVE5 0xE000E314 // Interrupt 160-191 Active Bit + +#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority +#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority +#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority +#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority +#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority +#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority +#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority +#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority +#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority +#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority +#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority +#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority +#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority +#define NVIC_PRI13 0xE000E434 // Interrupt 52-53 Priority + +#define NVIC_PRI14 0xE000E438 // Interrupt 56-59 Priority +#define NVIC_PRI15 0xE000E43C // Interrupt 60-63 Priority +#define NVIC_PRI16 0xE000E440 // Interrupt 64-67 Priority +#define NVIC_PRI17 0xE000E444 // Interrupt 68-71 Priority +#define NVIC_PRI18 0xE000E448 // Interrupt 72-75 Priority +#define NVIC_PRI19 0xE000E44C // Interrupt 76-79 Priority +#define NVIC_PRI20 0xE000E450 // Interrupt 80-83 Priority +#define NVIC_PRI21 0xE000E454 // Interrupt 84-87 Priority +#define NVIC_PRI22 0xE000E458 // Interrupt 88-91 Priority +#define NVIC_PRI23 0xE000E45C // Interrupt 92-95 Priority +#define NVIC_PRI24 0xE000E460 // Interrupt 96-99 Priority +#define NVIC_PRI25 0xE000E464 // Interrupt 100-103 Priority +#define NVIC_PRI26 0xE000E468 // Interrupt 104-107 Priority +#define NVIC_PRI27 0xE000E46C // Interrupt 108-111 Priority +#define NVIC_PRI28 0xE000E470 // Interrupt 112-115 Priority +#define NVIC_PRI29 0xE000E474 // Interrupt 116-119 Priority +#define NVIC_PRI30 0xE000E478 // Interrupt 120-123 Priority +#define NVIC_PRI31 0xE000E47C // Interrupt 124-127 Priority +#define NVIC_PRI32 0xE000E480 // Interrupt 128-131 Priority +#define NVIC_PRI33 0xE000E484 // Interrupt 132-135 Priority +#define NVIC_PRI34 0xE000E488 // Interrupt 136-139 Priority +#define NVIC_PRI35 0xE000E48C // Interrupt 140-143 Priority +#define NVIC_PRI36 0xE000E490 // Interrupt 144-147 Priority +#define NVIC_PRI37 0xE000E494 // Interrupt 148-151 Priority +#define NVIC_PRI38 0xE000E498 // Interrupt 152-155 Priority +#define NVIC_PRI39 0xE000E49C // Interrupt 156-159 Priority +#define NVIC_PRI40 0xE000E4A0 // Interrupt 160-163 Priority +#define NVIC_PRI41 0xE000E4A4 // Interrupt 164-167 Priority +#define NVIC_PRI42 0xE000E4A8 // Interrupt 168-171 Priority +#define NVIC_PRI43 0xE000E4AC // Interrupt 172-175 Priority +#define NVIC_PRI44 0xE000E4B0 // Interrupt 176-179 Priority +#define NVIC_PRI45 0xE000E4B4 // Interrupt 180-183 Priority +#define NVIC_PRI46 0xE000E4B8 // Interrupt 184-187 Priority +#define NVIC_PRI47 0xE000E4BC // Interrupt 188-191 Priority +#define NVIC_PRI48 0xE000E4C0 // Interrupt 192-195 Priority + + + +#define NVIC_CPUID 0xE000ED00 // CPU ID Base +#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State +#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset +#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset + // Control +#define NVIC_SYS_CTRL 0xE000ED10 // System Control +#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control +#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 +#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 +#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 +#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State +#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status +#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status +#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register +#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address +#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address +#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type +#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control +#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number +#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address +#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size +#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 +#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size + // Alias 1 +#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 +#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size + // Alias 2 +#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 +#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size + // Alias 3 +#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg +#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select +#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data +#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control +#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_TYPE register. +// +//***************************************************************************** +#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) +#define NVIC_INT_TYPE_LINES_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTLR register. +// +//***************************************************************************** +#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding +#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer +#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple + // Cycle Instructions + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CTRL register. +// +//***************************************************************************** +#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag +#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source +#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable +#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_RELOAD register. +// +//***************************************************************************** +#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value +#define NVIC_ST_RELOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CURRENT +// register. +// +//***************************************************************************** +#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value +#define NVIC_ST_CURRENT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ST_CAL register. +// +//***************************************************************************** +#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock +#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew +#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value +#define NVIC_ST_CAL_ONEMS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN0 register. +// +//***************************************************************************** +#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable +#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable +#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable +#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable +#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable +#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable +#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable +#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable +#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable +#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable +#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable +#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable +#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable +#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable +#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable +#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable +#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable +#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable +#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable +#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable +#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable +#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable +#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable +#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable +#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable +#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable +#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable +#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable +#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable +#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable +#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable +#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable +#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN1 register. +// +//***************************************************************************** +#define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable + +#undef NVIC_EN1_INT_M +#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable + +#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable +#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable +#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable +#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable +#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable +#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable +#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable +#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable +#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable +#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable +#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable +#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable +#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable +#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable +#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable +#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable +#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable +#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable +#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable +#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable +#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable +#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable +#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN2 register. +// +//***************************************************************************** +#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN3 register. +// +//***************************************************************************** +#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_EN4 register. +// +//***************************************************************************** +#define NVIC_EN4_INT_M 0x0000000F // Interrupt Enable + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS0 register. +// +//***************************************************************************** +#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable +#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable +#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable +#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable +#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable +#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable +#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable +#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable +#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable +#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable +#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable +#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable +#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable +#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable +#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable +#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable +#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable +#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable +#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable +#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable +#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable +#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable +#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable +#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable +#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable +#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable +#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable +#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable +#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable +#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable +#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable +#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable +#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS1 register. +// +//***************************************************************************** +#define NVIC_DIS1_INT_M 0x00FFFFFF // Interrupt Disable + +#undef NVIC_DIS1_INT_M +#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable + +#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable +#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable +#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable +#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable +#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable +#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable +#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable +#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable +#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable +#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable +#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable +#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable +#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable +#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable +#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable +#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable +#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable +#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable +#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable +#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable +#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable +#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable +#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable +#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS2 register. +// +//***************************************************************************** +#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS3 register. +// +//***************************************************************************** +#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DIS4 register. +// +//***************************************************************************** +#define NVIC_DIS4_INT_M 0x0000000F // Interrupt Disable + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND0 register. +// +//***************************************************************************** +#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending +#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend +#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend +#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend +#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend +#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend +#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend +#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend +#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend +#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend +#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend +#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend +#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend +#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend +#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend +#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend +#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend +#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend +#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend +#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend +#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend +#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend +#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend +#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend +#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend +#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend +#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend +#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend +#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend +#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend +#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend +#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend +#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND1 register. +// +//***************************************************************************** +#define NVIC_PEND1_INT_M 0x00FFFFFF // Interrupt Set Pending + +#undef NVIC_PEND1_INT_M +#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending + +#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend +#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend +#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend +#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend +#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend +#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend +#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend +#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend +#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend +#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend +#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend +#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend +#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend +#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend +#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend +#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend +#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend +#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend +#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend +#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend +#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend +#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend +#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend +#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND2 register. +// +//***************************************************************************** +#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND3 register. +// +//***************************************************************************** +#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PEND4 register. +// +//***************************************************************************** +#define NVIC_PEND4_INT_M 0x0000000F // Interrupt Set Pending + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND0 register. +// +//***************************************************************************** +#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending +#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend +#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend +#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend +#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend +#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend +#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend +#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend +#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend +#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend +#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend +#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend +#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend +#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend +#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend +#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend +#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend +#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend +#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend +#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend +#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend +#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend +#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend +#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend +#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend +#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend +#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend +#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend +#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend +#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend +#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend +#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend +#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND1 register. +// +//***************************************************************************** +#define NVIC_UNPEND1_INT_M 0x00FFFFFF // Interrupt Clear Pending + +#undef NVIC_UNPEND1_INT_M +#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend +#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend +#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend +#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend +#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend +#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend +#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend +#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend +#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend +#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend +#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend +#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend +#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend +#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend +#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend +#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend +#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend +#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend +#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend +#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend +#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend +#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend +#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend +#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND2 register. +// +//***************************************************************************** +#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND3 register. +// +//***************************************************************************** +#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_UNPEND4 register. +// +//***************************************************************************** +#define NVIC_UNPEND4_INT_M 0x0000000F // Interrupt Clear Pending + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE0 register. +// +//***************************************************************************** +#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active +#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active +#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active +#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active +#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active +#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active +#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active +#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active +#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active +#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active +#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active +#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active +#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active +#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active +#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active +#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active +#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active +#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active +#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active +#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active +#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active +#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active +#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active +#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active +#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active +#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active +#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active +#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active +#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active +#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active +#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active +#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active +#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE1 register. +// +//***************************************************************************** +#define NVIC_ACTIVE1_INT_M 0x00FFFFFF // Interrupt Active + +#undef NVIC_ACTIVE1_INT_M +#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active + +#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active +#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active +#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active +#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active +#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active +#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active +#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active +#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active +#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active +#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active +#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active +#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active +#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active +#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active +#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active +#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active +#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active +#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active +#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active +#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active +#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active +#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active +#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active +#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE2 register. +// +//***************************************************************************** +#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE3 register. +// +//***************************************************************************** +#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_ACTIVE4 register. +// +//***************************************************************************** +#define NVIC_ACTIVE4_INT_M 0x0000000F // Interrupt Active + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI0 register. +// +//***************************************************************************** +#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask +#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask +#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask +#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask +#define NVIC_PRI0_INT3_S 29 +#define NVIC_PRI0_INT2_S 21 +#define NVIC_PRI0_INT1_S 13 +#define NVIC_PRI0_INT0_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI1 register. +// +//***************************************************************************** +#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask +#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask +#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask +#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask +#define NVIC_PRI1_INT7_S 29 +#define NVIC_PRI1_INT6_S 21 +#define NVIC_PRI1_INT5_S 13 +#define NVIC_PRI1_INT4_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI2 register. +// +//***************************************************************************** +#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask +#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask +#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask +#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask +#define NVIC_PRI2_INT11_S 29 +#define NVIC_PRI2_INT10_S 21 +#define NVIC_PRI2_INT9_S 13 +#define NVIC_PRI2_INT8_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI3 register. +// +//***************************************************************************** +#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask +#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask +#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask +#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask +#define NVIC_PRI3_INT15_S 29 +#define NVIC_PRI3_INT14_S 21 +#define NVIC_PRI3_INT13_S 13 +#define NVIC_PRI3_INT12_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI4 register. +// +//***************************************************************************** +#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask +#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask +#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask +#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask +#define NVIC_PRI4_INT19_S 29 +#define NVIC_PRI4_INT18_S 21 +#define NVIC_PRI4_INT17_S 13 +#define NVIC_PRI4_INT16_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI5 register. +// +//***************************************************************************** +#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask +#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask +#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask +#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask +#define NVIC_PRI5_INT23_S 29 +#define NVIC_PRI5_INT22_S 21 +#define NVIC_PRI5_INT21_S 13 +#define NVIC_PRI5_INT20_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI6 register. +// +//***************************************************************************** +#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask +#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask +#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask +#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask +#define NVIC_PRI6_INT27_S 29 +#define NVIC_PRI6_INT26_S 21 +#define NVIC_PRI6_INT25_S 13 +#define NVIC_PRI6_INT24_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI7 register. +// +//***************************************************************************** +#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask +#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask +#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask +#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask +#define NVIC_PRI7_INT31_S 29 +#define NVIC_PRI7_INT30_S 21 +#define NVIC_PRI7_INT29_S 13 +#define NVIC_PRI7_INT28_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI8 register. +// +//***************************************************************************** +#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask +#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask +#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask +#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask +#define NVIC_PRI8_INT35_S 29 +#define NVIC_PRI8_INT34_S 21 +#define NVIC_PRI8_INT33_S 13 +#define NVIC_PRI8_INT32_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI9 register. +// +//***************************************************************************** +#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask +#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask +#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask +#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask +#define NVIC_PRI9_INT39_S 29 +#define NVIC_PRI9_INT38_S 21 +#define NVIC_PRI9_INT37_S 13 +#define NVIC_PRI9_INT36_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI10 register. +// +//***************************************************************************** +#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask +#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask +#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask +#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask +#define NVIC_PRI10_INT43_S 29 +#define NVIC_PRI10_INT42_S 21 +#define NVIC_PRI10_INT41_S 13 +#define NVIC_PRI10_INT40_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI11 register. +// +//***************************************************************************** +#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask +#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask +#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask +#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask +#define NVIC_PRI11_INT47_S 29 +#define NVIC_PRI11_INT46_S 21 +#define NVIC_PRI11_INT45_S 13 +#define NVIC_PRI11_INT44_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI12 register. +// +//***************************************************************************** +#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask +#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask +#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask +#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask +#define NVIC_PRI12_INT51_S 29 +#define NVIC_PRI12_INT50_S 21 +#define NVIC_PRI12_INT49_S 13 +#define NVIC_PRI12_INT48_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI13 register. +// +//***************************************************************************** +#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask +#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask +#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask +#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask +#define NVIC_PRI13_INT55_S 29 +#define NVIC_PRI13_INT54_S 21 +#define NVIC_PRI13_INT53_S 13 +#define NVIC_PRI13_INT52_S 5 + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI14 register. +// +//***************************************************************************** +#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask +#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask +#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask +#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask +#define NVIC_PRI14_INTD_S 29 +#define NVIC_PRI14_INTC_S 21 +#define NVIC_PRI14_INTB_S 13 +#define NVIC_PRI14_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI15 register. +// +//***************************************************************************** +#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask +#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask +#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask +#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask +#define NVIC_PRI15_INTD_S 29 +#define NVIC_PRI15_INTC_S 21 +#define NVIC_PRI15_INTB_S 13 +#define NVIC_PRI15_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI16 register. +// +//***************************************************************************** +#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask +#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask +#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask +#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask +#define NVIC_PRI16_INTD_S 29 +#define NVIC_PRI16_INTC_S 21 +#define NVIC_PRI16_INTB_S 13 +#define NVIC_PRI16_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI17 register. +// +//***************************************************************************** +#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask +#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask +#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask +#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask +#define NVIC_PRI17_INTD_S 29 +#define NVIC_PRI17_INTC_S 21 +#define NVIC_PRI17_INTB_S 13 +#define NVIC_PRI17_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI18 register. +// +//***************************************************************************** +#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask +#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask +#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask +#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask +#define NVIC_PRI18_INTD_S 29 +#define NVIC_PRI18_INTC_S 21 +#define NVIC_PRI18_INTB_S 13 +#define NVIC_PRI18_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI19 register. +// +//***************************************************************************** +#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask +#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask +#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask +#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask +#define NVIC_PRI19_INTD_S 29 +#define NVIC_PRI19_INTC_S 21 +#define NVIC_PRI19_INTB_S 13 +#define NVIC_PRI19_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI20 register. +// +//***************************************************************************** +#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask +#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask +#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask +#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask +#define NVIC_PRI20_INTD_S 29 +#define NVIC_PRI20_INTC_S 21 +#define NVIC_PRI20_INTB_S 13 +#define NVIC_PRI20_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI21 register. +// +//***************************************************************************** +#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask +#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask +#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask +#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask +#define NVIC_PRI21_INTD_S 29 +#define NVIC_PRI21_INTC_S 21 +#define NVIC_PRI21_INTB_S 13 +#define NVIC_PRI21_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI22 register. +// +//***************************************************************************** +#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask +#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask +#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask +#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask +#define NVIC_PRI22_INTD_S 29 +#define NVIC_PRI22_INTC_S 21 +#define NVIC_PRI22_INTB_S 13 +#define NVIC_PRI22_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI23 register. +// +//***************************************************************************** +#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask +#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask +#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask +#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask +#define NVIC_PRI23_INTD_S 29 +#define NVIC_PRI23_INTC_S 21 +#define NVIC_PRI23_INTB_S 13 +#define NVIC_PRI23_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI24 register. +// +//***************************************************************************** +#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask +#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask +#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask +#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask +#define NVIC_PRI24_INTD_S 29 +#define NVIC_PRI24_INTC_S 21 +#define NVIC_PRI24_INTB_S 13 +#define NVIC_PRI24_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI25 register. +// +//***************************************************************************** +#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask +#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask +#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask +#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask +#define NVIC_PRI25_INTD_S 29 +#define NVIC_PRI25_INTC_S 21 +#define NVIC_PRI25_INTB_S 13 +#define NVIC_PRI25_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI26 register. +// +//***************************************************************************** +#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask +#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask +#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask +#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask +#define NVIC_PRI26_INTD_S 29 +#define NVIC_PRI26_INTC_S 21 +#define NVIC_PRI26_INTB_S 13 +#define NVIC_PRI26_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI27 register. +// +//***************************************************************************** +#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask +#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask +#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask +#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask +#define NVIC_PRI27_INTD_S 29 +#define NVIC_PRI27_INTC_S 21 +#define NVIC_PRI27_INTB_S 13 +#define NVIC_PRI27_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI28 register. +// +//***************************************************************************** +#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask +#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask +#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask +#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask +#define NVIC_PRI28_INTD_S 29 +#define NVIC_PRI28_INTC_S 21 +#define NVIC_PRI28_INTB_S 13 +#define NVIC_PRI28_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI29 register. +// +//***************************************************************************** +#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask +#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask +#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask +#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask +#define NVIC_PRI29_INTD_S 29 +#define NVIC_PRI29_INTC_S 21 +#define NVIC_PRI29_INTB_S 13 +#define NVIC_PRI29_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI30 register. +// +//***************************************************************************** +#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask +#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask +#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask +#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask +#define NVIC_PRI30_INTD_S 29 +#define NVIC_PRI30_INTC_S 21 +#define NVIC_PRI30_INTB_S 13 +#define NVIC_PRI30_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI31 register. +// +//***************************************************************************** +#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask +#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask +#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask +#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask +#define NVIC_PRI31_INTD_S 29 +#define NVIC_PRI31_INTC_S 21 +#define NVIC_PRI31_INTB_S 13 +#define NVIC_PRI31_INTA_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_PRI32 register. +// +//***************************************************************************** +#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask +#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask +#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask +#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask +#define NVIC_PRI32_INTD_S 29 +#define NVIC_PRI32_INTC_S 21 +#define NVIC_PRI32_INTB_S 13 +#define NVIC_PRI32_INTA_S 5 + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CPUID register. +// +//***************************************************************************** +#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code +#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM +#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number +#define NVIC_CPUID_CON_M 0x000F0000 // Constant +#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number +#define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor + +#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor + +#define NVIC_CPUID_REV_M 0x0000000F // Revision Number + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_INT_CTRL register. +// +//***************************************************************************** +#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending +#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending +#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending +#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending +#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending +#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling +#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending +#define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number + +#undef NVIC_INT_CTRL_VEC_PEN_M +#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number + +#define NVIC_INT_CTRL_VEC_PEN_NMI \ + 0x00002000 // NMI +#define NVIC_INT_CTRL_VEC_PEN_HARD \ + 0x00003000 // Hard fault +#define NVIC_INT_CTRL_VEC_PEN_MEM \ + 0x00004000 // Memory management fault +#define NVIC_INT_CTRL_VEC_PEN_BUS \ + 0x00005000 // Bus fault +#define NVIC_INT_CTRL_VEC_PEN_USG \ + 0x00006000 // Usage fault +#define NVIC_INT_CTRL_VEC_PEN_SVC \ + 0x0000B000 // SVCall +#define NVIC_INT_CTRL_VEC_PEN_PNDSV \ + 0x0000E000 // PendSV +#define NVIC_INT_CTRL_VEC_PEN_TICK \ + 0x0000F000 // SysTick +#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base +#define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number + +#undef NVIC_INT_CTRL_VEC_ACT_M +#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number + +#define NVIC_INT_CTRL_VEC_PEN_S 12 +#define NVIC_INT_CTRL_VEC_ACT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_VTABLE register. +// +//***************************************************************************** +#define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base +#define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset + +#undef NVIC_VTABLE_OFFSET_M +#define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset + +#define NVIC_VTABLE_OFFSET_S 9 + +#undef NVIC_VTABLE_OFFSET_S +#define NVIC_VTABLE_OFFSET_S 10 + + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_APINT register. +// +//***************************************************************************** +#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key +#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key +#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess +#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping +#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split +#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split +#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split +#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split +#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split +#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split +#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split +#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split +#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request +#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault +#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_CTRL register. +// +//***************************************************************************** +#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending +#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable +#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_CFG_CTRL register. +// +//***************************************************************************** +#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception + // Entry +#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and + // Fault +#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 +#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access +#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger +#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority +#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority +#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority +#define NVIC_SYS_PRI1_USAGE_S 21 +#define NVIC_SYS_PRI1_BUS_S 13 +#define NVIC_SYS_PRI1_MEM_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority +#define NVIC_SYS_PRI2_SVC_S 29 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. +// +//***************************************************************************** +#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority +#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority +#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority +#define NVIC_SYS_PRI3_TICK_S 29 +#define NVIC_SYS_PRI3_PENDSV_S 21 +#define NVIC_SYS_PRI3_DEBUG_S 5 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL +// register. +// +//***************************************************************************** +#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable +#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable +#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable +#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending +#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending +#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending +#define NVIC_SYS_HND_CTRL_USAGEP \ + 0x00001000 // Usage Fault Pending +#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active +#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active +#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active +#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active +#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active +#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active +#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault +#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault +#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault +#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault +#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault +#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage + // Fault +#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid + +#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy + // State Preservation + +#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault +#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault +#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error +#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error +#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error +#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address + // Register Valid + +#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on + // Floating-Point Lazy State + // Preservation + +#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation +#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation +#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation +#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_HFAULT_STAT +// register. +// +//***************************************************************************** +#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event +#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault +#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DEBUG_STAT +// register. +// +//***************************************************************************** +#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted +#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch +#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match +#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction +#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MM_ADDR register. +// +//***************************************************************************** +#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_MM_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_FAULT_ADDR +// register. +// +//***************************************************************************** +#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address +#define NVIC_FAULT_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_TYPE register. +// +//***************************************************************************** +#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions +#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions +#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU +#define NVIC_MPU_TYPE_IREGION_S 16 +#define NVIC_MPU_TYPE_DREGION_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_CTRL register. +// +//***************************************************************************** +#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region +#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults +#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_NUMBER +// register. +// +//***************************************************************************** +#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access +#define NVIC_MPU_NUMBER_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE register. +// +//***************************************************************************** +#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE_ADDR_S 5 +#define NVIC_MPU_BASE_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes +#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access +#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none +#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only +#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw +#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none +#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro +#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable +#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable +#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable +#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable +#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable +#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable +#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable +#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable +#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable +#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable +#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable +#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes +#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes +#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes +#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes +#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes +#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes +#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes +#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes +#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes +#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes +#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes +#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes +#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes +#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes +#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes +#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes +#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes +#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes +#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes +#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes +#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes +#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes +#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes +#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes +#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes +#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes +#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes +#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes +#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE1 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE1_ADDR_S 5 +#define NVIC_MPU_BASE1_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR1_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR1_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR1_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE2 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE2_ADDR_S 5 +#define NVIC_MPU_BASE2_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR2_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR2_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR2_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_BASE3 register. +// +//***************************************************************************** +#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask +#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid +#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number +#define NVIC_MPU_BASE3_ADDR_S 5 +#define NVIC_MPU_BASE3_REGION_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. +// +//***************************************************************************** +#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable +#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege +#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask +#define NVIC_MPU_ATTR3_SHAREABLE \ + 0x00040000 // Shareable +#define NVIC_MPU_ATTR3_CACHEABLE \ + 0x00020000 // Cacheable +#define NVIC_MPU_ATTR3_BUFFRABLE \ + 0x00010000 // Bufferable +#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits +#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask +#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_CTRL register. +// +//***************************************************************************** +#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask +#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key +#define NVIC_DBG_CTRL_S_RESET_ST \ + 0x02000000 // Core has reset since last read +#define NVIC_DBG_CTRL_S_RETIRE_ST \ + 0x01000000 // Core has executed insruction + // since last read +#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up +#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping +#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt +#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available +#define NVIC_DBG_CTRL_C_SNAPSTALL \ + 0x00000020 // Breaks a stalled load/store +#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping +#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core +#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core +#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_XFER register. +// +//***************************************************************************** +#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read +#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register +#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 +#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 +#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 +#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 +#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 +#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 +#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 +#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 +#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 +#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 +#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 +#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 +#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 +#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 +#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 +#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 +#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register +#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP +#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP +#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP +#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_DATA register. +// +//***************************************************************************** +#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache +#define NVIC_DBG_DATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_DBG_INT register. +// +//***************************************************************************** +#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault +#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors +#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error +#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state +#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check +#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error +#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault +#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status +#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset +#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending +#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch + +//***************************************************************************** +// +// The following are defines for the bit fields in the NVIC_SW_TRIG register. +// +//***************************************************************************** +#define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID + +#undef NVIC_SW_TRIG_INTID_M +#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID + +#define NVIC_SW_TRIG_INTID_S 0 + +#endif // __HW_NVIC_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_ocp_shared.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_ocp_shared.h new file mode 100644 index 00000000..a52f6901 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_ocp_shared.h @@ -0,0 +1,3445 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_OCP_SHARED_H__ +#define __HW_OCP_SHARED_H__ + +//***************************************************************************** +// +// The following are defines for the OCP_SHARED register offsets. +// +//***************************************************************************** +#define OCP_SHARED_O_SEMAPHORE1 0x00000000 +#define OCP_SHARED_O_SEMAPHORE2 0x00000004 +#define OCP_SHARED_O_SEMAPHORE3 0x00000008 +#define OCP_SHARED_O_SEMAPHORE4 0x0000000C +#define OCP_SHARED_O_SEMAPHORE5 0x00000010 +#define OCP_SHARED_O_SEMAPHORE6 0x00000014 +#define OCP_SHARED_O_SEMAPHORE7 0x00000018 +#define OCP_SHARED_O_SEMAPHORE8 0x0000001C +#define OCP_SHARED_O_SEMAPHORE9 0x00000020 +#define OCP_SHARED_O_SEMAPHORE10 \ + 0x00000024 + +#define OCP_SHARED_O_SEMAPHORE11 \ + 0x00000028 + +#define OCP_SHARED_O_SEMAPHORE12 \ + 0x0000002C + +#define OCP_SHARED_O_IC_LOCKER_ID \ + 0x00000030 + +#define OCP_SHARED_O_MCU_SEMAPHORE_PEND \ + 0x00000034 + +#define OCP_SHARED_O_WL_SEMAPHORE_PEND \ + 0x00000038 + +#define OCP_SHARED_O_PLATFORM_DETECTION_RD_ONLY \ + 0x0000003C + +#define OCP_SHARED_O_SEMAPHORES_STATUS_RD_ONLY \ + 0x00000040 + +#define OCP_SHARED_O_CC3XX_CONFIG_CTRL \ + 0x00000044 + +#define OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_LSB \ + 0x00000048 + +#define OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_MSB \ + 0x0000004C + +#define OCP_SHARED_O_WLAN_ELP_WAKE_EN \ + 0x00000050 + +#define OCP_SHARED_O_DEVINIT_ROM_START_ADDR \ + 0x00000054 + +#define OCP_SHARED_O_DEVINIT_ROM_END_ADDR \ + 0x00000058 + +#define OCP_SHARED_O_SSBD_SEED 0x0000005C +#define OCP_SHARED_O_SSBD_CHK 0x00000060 +#define OCP_SHARED_O_SSBD_POLY_SEL \ + 0x00000064 + +#define OCP_SHARED_O_SPARE_REG_0 \ + 0x00000068 + +#define OCP_SHARED_O_SPARE_REG_1 \ + 0x0000006C + +#define OCP_SHARED_O_SPARE_REG_2 \ + 0x00000070 + +#define OCP_SHARED_O_SPARE_REG_3 \ + 0x00000074 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_0 \ + 0x000000A0 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_1 \ + 0x000000A4 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_2 \ + 0x000000A8 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_3 \ + 0x000000AC + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_4 \ + 0x000000B0 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_5 \ + 0x000000B4 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_6 \ + 0x000000B8 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_7 \ + 0x000000BC + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_8 \ + 0x000000C0 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_9 \ + 0x000000C4 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_10 \ + 0x000000C8 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_11 \ + 0x000000CC + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_12 \ + 0x000000D0 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_13 \ + 0x000000D4 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_14 \ + 0x000000D8 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_15 \ + 0x000000DC + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_16 \ + 0x000000E0 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_17 \ + 0x000000E4 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_18 \ + 0x000000E8 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_19 \ + 0x000000EC + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_20 \ + 0x000000F0 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_21 \ + 0x000000F4 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_22 \ + 0x000000F8 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_23 \ + 0x000000FC + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_24 \ + 0x00000100 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_25 \ + 0x00000104 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_26 \ + 0x00000108 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_27 \ + 0x0000010C + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_28 \ + 0x00000110 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_29 \ + 0x00000114 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_30 \ + 0x00000118 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_31 \ + 0x0000011C + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_32 \ + 0x00000120 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_33 \ + 0x00000124 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_34 \ + 0x00000128 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_35 \ + 0x0000012C + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_36 \ + 0x00000130 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_37 \ + 0x00000134 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_38 \ + 0x00000138 + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_39 \ + 0x0000013C + +#define OCP_SHARED_O_GPIO_PAD_CONFIG_40 \ + 0x00000140 + +#define OCP_SHARED_O_GPIO_PAD_CMN_CONFIG \ + 0x00000144 // This register provide control to + // GPIO_CC3XXV1 IO PAD. Common + // control signals to all bottom Die + // IO's are controlled via this. + +#define OCP_SHARED_O_D2D_DEV_PAD_CMN_CONFIG \ + 0x00000148 + +#define OCP_SHARED_O_D2D_TOSTACK_PAD_CONF \ + 0x0000014C + +#define OCP_SHARED_O_D2D_MISC_PAD_CONF \ + 0x00000150 + +#define OCP_SHARED_O_SOP_CONF_OVERRIDE \ + 0x00000154 + +#define OCP_SHARED_O_CC3XX_DEBUGSS_STATUS \ + 0x00000158 + +#define OCP_SHARED_O_CC3XX_DEBUGMUX_SEL \ + 0x0000015C + +#define OCP_SHARED_O_ALT_PC_VAL_NW \ + 0x00000160 + +#define OCP_SHARED_O_ALT_PC_VAL_APPS \ + 0x00000164 + +#define OCP_SHARED_O_SPARE_REG_4 \ + 0x00000168 + +#define OCP_SHARED_O_SPARE_REG_5 \ + 0x0000016C + +#define OCP_SHARED_O_SH_SPI_CS_MASK \ + 0x00000170 + +#define OCP_SHARED_O_CC3XX_DEVICE_TYPE \ + 0x00000174 + +#define OCP_SHARED_O_MEM_TOPMUXCTRL_IFORCE \ + 0x00000178 + +#define OCP_SHARED_O_CC3XX_DEV_PACKAGE_DETECT \ + 0x0000017C + +#define OCP_SHARED_O_AUTONMS_SPICLK_SEL \ + 0x00000180 + +#define OCP_SHARED_O_CC3XX_DEV_PADCONF \ + 0x00000184 + +#define OCP_SHARED_O_SPARE_REG_8 \ + 0x00000188 + +#define OCP_SHARED_O_SPARE_REG_6 \ + 0x0000018C + +#define OCP_SHARED_O_SPARE_REG_7 \ + 0x00000190 + +#define OCP_SHARED_O_APPS_WLAN_ORBIT \ + 0x00000194 + +#define OCP_SHARED_O_APPS_WLAN_SCRATCH_PAD \ + 0x00000198 + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE1 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE1_MEM_SEMAPHORE1_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE1_MEM_SEMAPHORE1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE2 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE2_MEM_SEMAPHORE2_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE2_MEM_SEMAPHORE2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE3 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE3_MEM_SEMAPHORE3_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE3_MEM_SEMAPHORE3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE4 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE4_MEM_SEMAPHORE4_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE4_MEM_SEMAPHORE4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE5 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE5_MEM_SEMAPHORE5_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE5_MEM_SEMAPHORE5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE6 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE6_MEM_SEMAPHORE6_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE6_MEM_SEMAPHORE6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE7 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE7_MEM_SEMAPHORE7_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE7_MEM_SEMAPHORE7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE8 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE8_MEM_SEMAPHORE8_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE8_MEM_SEMAPHORE8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE9 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE9_MEM_SEMAPHORE9_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE9_MEM_SEMAPHORE9_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE10 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE10_MEM_SEMAPHORE10_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE10_MEM_SEMAPHORE10_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE11 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE11_MEM_SEMAPHORE11_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE11_MEM_SEMAPHORE11_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORE12 register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORE12_MEM_SEMAPHORE12_M \ + 0x00000003 // General Purpose Semaphore for SW + // Usage. If any of the 2 bits of a + // given register is set to 1, it + // means that the semaphore is + // locked by one of the masters. + // Each bit represents a master IP + // as follows: {WLAN,NWP}. The JTAG + // cannot capture the semaphore but + // it can release it. As a master IP + // reads the semaphore, it will be + // caputed and the masters + // correlating bit will be set to 1 + // (set upon read). As any IP writes + // to this address (independent of + // the written data) the semaphore + // will be set to 2'b00. + +#define OCP_SHARED_SEMAPHORE12_MEM_SEMAPHORE12_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_IC_LOCKER_ID register. +// +//****************************************************************************** +#define OCP_SHARED_IC_LOCKER_ID_MEM_IC_LOCKER_ID_M \ + 0x00000007 // This register is used for + // allowing only one master OCP to + // perform write transactions to the + // OCP slaves. Each bit represents + // an IP in the following format: { + // JTAG,WLAN, NWP mcu}. As any of + // the bits is set to one, the + // correlating IP is preventing the + // other IP's from performing write + // transactions to the slaves. As + // the Inter Connect is locked, the + // only the locking IP can write to + // the register and by that + // releasing the lock. 3'b000 => IC + // is not locked. 3'b001 => IC is + // locked by NWP mcu. 3'b010 => IC + // is locked by WLAN. 3'b100 => IC + // is locked by JTAG. + +#define OCP_SHARED_IC_LOCKER_ID_MEM_IC_LOCKER_ID_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_MCU_SEMAPHORE_PEND register. +// +//****************************************************************************** +#define OCP_SHARED_MCU_SEMAPHORE_PEND_MEM_MCU_SEMAPHORE_PEND_M \ + 0x0000FFFF // This register specifies the + // semaphore for which the NWP mcu + // is waiting to be released. It is + // set to the serial number of a + // given locked semaphore after it + // was read by the NWP mcu. Only + // [11:0] is used. + +#define OCP_SHARED_MCU_SEMAPHORE_PEND_MEM_MCU_SEMAPHORE_PEND_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_WL_SEMAPHORE_PEND register. +// +//****************************************************************************** +#define OCP_SHARED_WL_SEMAPHORE_PEND_MEM_WL_SEMAPHORE_PEND_M \ + 0x0000FFFF // This register specifies the + // semaphore for which the WLAN is + // waiting to be released. It is set + // to the serial number of a given + // locked semaphore after it was + // read by the WLAN. Only [11:0] is + // used. + +#define OCP_SHARED_WL_SEMAPHORE_PEND_MEM_WL_SEMAPHORE_PEND_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_PLATFORM_DETECTION_RD_ONLY register. +// +//****************************************************************************** +#define OCP_SHARED_PLATFORM_DETECTION_RD_ONLY_PLATFORM_DETECTION_M \ + 0x0000FFFF // This information serves the IPs + // for knowing in which platform are + // they integrated at: 0 = CC31XX. + +#define OCP_SHARED_PLATFORM_DETECTION_RD_ONLY_PLATFORM_DETECTION_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SEMAPHORES_STATUS_RD_ONLY register. +// +//****************************************************************************** +#define OCP_SHARED_SEMAPHORES_STATUS_RD_ONLY_SEMAPHORES_STATUS_M \ + 0x00000FFF // Captured/released semaphores + // status for the 12 semaphores. + // Each bit of the 12 bits + // represents a semaphore. 0 => + // Semaphore Free. 1 => Semaphore + // Captured. + +#define OCP_SHARED_SEMAPHORES_STATUS_RD_ONLY_SEMAPHORES_STATUS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_CONFIG_CTRL register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_IC_TO_EN \ + 0x00000010 // This bit is used to enable + // timeout mechanism for top_ocp_ic + // (for debug puropse). When 1 value + // , in case any ocp slave doesn't + // give sresponse within 16 cylcles + // top_ic will give error response + // itself to avoid bus hange. + +#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_ALT_PC_EN_APPS \ + 0x00000008 // 1 bit should be accessible only + // in devinit. This will enable 0x4 + // hack for apps processor + +#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_ALT_PC_EN_NW \ + 0x00000004 // 1 bit, should be accessible only + // in devinit. This will enable 0x4 + // hack for nw processor + +#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_EXTEND_NW_ROM \ + 0x00000002 // When set NW can take over apps + // rom and flash via IDCODE bus. + // Apps will able to access this + // register only during devinit and + // reset value should be 0. + +#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_WLAN_HOST_INTF_SEL \ + 0x00000001 // When this bit is set to 0 WPSI + // host interface wil be selected, + // when this bit is set to 1 , WLAN + // host async bridge will be + // selected. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_LSB register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_LSB_MEM_SHARED_MEM_SEL_LSB_M \ + 0x3FFFFFFF // This register provides memss RAM + // column configuration for column 0 + // to 9. 3 bits are allocated per + // column. This register is required + // to be configured before starting + // RAM access. Changing register + // setting while code is running + // will result into unpredictable + // memory behaviour. Register is + // supported to configured ones + // after core is booted up. 3 bit + // encoding per column is as + // follows: when 000 : WLAN, 001: + // NWP, 010: APPS, 011: PHY, 100: + // OCLA column 0 select: bit [2:0] + // :when 000 -> WLAN,001 -> NWP,010 + // -> APPS, 011 -> PHY, 100 -> OCLA + // column 1 select: bit [5:3] + // :column 2 select: bit [8 : 6]: + // column 3 select : bit [11: 9] + // column 4 select : bit [14:12] + // column 5 select : bit [17:15] + // column 6 select : bit [20:18] + // column 7 select : bit [23:21] + // column 8 select : bit [26:24] + // column 9 select : bit [29:27] + // column 10 select + +#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_LSB_MEM_SHARED_MEM_SEL_LSB_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_MSB register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_MSB_MEM_SHARED_MEM_SEL_MSB_M \ + 0x00000FFF // This register provides memss RAM + // column configuration for column + // 10 to 15. 3 bits are allocated + // per column. This register is + // required to be configured before + // starting RAM access. Changing + // register setting while code is + // running will result into + // unpredictable memory behaviour. + // Register is supported to + // configured ones after core is + // booted up. 3 bit encoding per + // column is as follows: when 000 : + // WLAN, 001: NWP, 010: APPS, 011: + // PHY, 100: OCLA column 11 select : + // bit [2:0] column 12 select : bit + // [5:3] column 13 select : bit [8 : + // 6] column 14 select : + +#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_MSB_MEM_SHARED_MEM_SEL_MSB_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_WLAN_ELP_WAKE_EN register. +// +//****************************************************************************** +#define OCP_SHARED_WLAN_ELP_WAKE_EN_MEM_WLAN_ELP_WAKE_EN \ + 0x00000001 // when '1' : signal will enabled + // ELP power doamin when '0': ELP is + // not powered up. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_DEVINIT_ROM_START_ADDR register. +// +//****************************************************************************** +#define OCP_SHARED_DEVINIT_ROM_START_ADDR_MEM_DEVINIT_ROM_START_ADDR_M \ + 0xFFFFFFFF // 32 bit, Writable only during + // devinit, and whole 32 bit should + // be output of the config register + // module. This register is not used + // , similar register availble in + // GPRCM space. + +#define OCP_SHARED_DEVINIT_ROM_START_ADDR_MEM_DEVINIT_ROM_START_ADDR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_DEVINIT_ROM_END_ADDR register. +// +//****************************************************************************** +#define OCP_SHARED_DEVINIT_ROM_END_ADDR_MEM_DEVINIT_ROM_END_ADDR_M \ + 0xFFFFFFFF // 32 bit, Writable only during + // devinit, and whole 32 bit should + // be output of the config register + // module. + +#define OCP_SHARED_DEVINIT_ROM_END_ADDR_MEM_DEVINIT_ROM_END_ADDR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SSBD_SEED register. +// +//****************************************************************************** +#define OCP_SHARED_SSBD_SEED_MEM_SSBD_SEED_M \ + 0xFFFFFFFF // 32 bit, Writable only during + // devinit, and whole 32 bit should + // be output of the config register + // module. + +#define OCP_SHARED_SSBD_SEED_MEM_SSBD_SEED_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SSBD_CHK register. +// +//****************************************************************************** +#define OCP_SHARED_SSBD_CHK_MEM_SSBD_CHK_M \ + 0xFFFFFFFF // 32 bit, Writable only during + // devinit, and whole 32 bit should + // be output of the config register + // module. + +#define OCP_SHARED_SSBD_CHK_MEM_SSBD_CHK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SSBD_POLY_SEL register. +// +//****************************************************************************** +#define OCP_SHARED_SSBD_POLY_SEL_MEM_SSBD_POLY_SEL_M \ + 0x00000003 // 2 bit, Writable only during + // devinit, and whole 2 bit should + // be output of the config register + // module. + +#define OCP_SHARED_SSBD_POLY_SEL_MEM_SSBD_POLY_SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_0 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_0_MEM_SPARE_REG_0_M \ + 0xFFFFFFFF // Devinit code should look for + // whether corresponding fuse is + // blown and if blown write to the + // 11th bit of this register to + // disable flshtst interface + +#define OCP_SHARED_SPARE_REG_0_MEM_SPARE_REG_0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_1 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_1_MEM_SPARE_REG_1_M \ + 0xFFFFFFFF // NWP Software register + +#define OCP_SHARED_SPARE_REG_1_MEM_SPARE_REG_1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_2 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_2_MEM_SPARE_REG_2_M \ + 0xFFFFFFFF // NWP Software register + +#define OCP_SHARED_SPARE_REG_2_MEM_SPARE_REG_2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_3 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_3_MEM_SPARE_REG_3_M \ + 0xFFFFFFFF // APPS Software register + +#define OCP_SHARED_SPARE_REG_3_MEM_SPARE_REG_3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_0 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_0_MEM_GPIO_PAD_CONFIG_0_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." "For example in + // case of I2C Value gets latched at + // rising edge of RET33.""" """ 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_0_MEM_GPIO_PAD_CONFIG_0_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_1 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_1_MEM_GPIO_PAD_CONFIG_1_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_1_MEM_GPIO_PAD_CONFIG_1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_2 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_2_MEM_GPIO_PAD_CONFIG_2_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_2_MEM_GPIO_PAD_CONFIG_2_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_3 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_3_MEM_GPIO_PAD_CONFIG_3_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_3_MEM_GPIO_PAD_CONFIG_3_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_4 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_4_MEM_GPIO_PAD_CONFIG_4_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_4_MEM_GPIO_PAD_CONFIG_4_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_5 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_5_MEM_GPIO_PAD_CONFIG_5_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_5_MEM_GPIO_PAD_CONFIG_5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_6 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_6_MEM_GPIO_PAD_CONFIG_6_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_6_MEM_GPIO_PAD_CONFIG_6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_7 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_7_MEM_GPIO_PAD_CONFIG_7_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_7_MEM_GPIO_PAD_CONFIG_7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_8 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_8_MEM_GPIO_PAD_CONFIG_8_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_8_MEM_GPIO_PAD_CONFIG_8_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_9 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_9_MEM_GPIO_PAD_CONFIG_9_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_9_MEM_GPIO_PAD_CONFIG_9_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_10 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_10_MEM_GPIO_PAD_CONFIG_10_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_10_MEM_GPIO_PAD_CONFIG_10_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_11 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_11_MEM_GPIO_PAD_CONFIG_11_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_11_MEM_GPIO_PAD_CONFIG_11_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_12 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_12_MEM_GPIO_PAD_CONFIG_12_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_12_MEM_GPIO_PAD_CONFIG_12_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_13 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_13_MEM_GPIO_PAD_CONFIG_13_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_13_MEM_GPIO_PAD_CONFIG_13_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_14 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_14_MEM_GPIO_PAD_CONFIG_14_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_14_MEM_GPIO_PAD_CONFIG_14_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_15 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_15_MEM_GPIO_PAD_CONFIG_15_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_15_MEM_GPIO_PAD_CONFIG_15_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_16 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_16_MEM_GPIO_PAD_CONFIG_16_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_16_MEM_GPIO_PAD_CONFIG_16_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_17 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_17_MEM_GPIO_PAD_CONFIG_17_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_17_MEM_GPIO_PAD_CONFIG_17_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_18 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_18_MEM_GPIO_PAD_CONFIG_18_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_18_MEM_GPIO_PAD_CONFIG_18_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_19 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_19_MEM_GPIO_PAD_CONFIG_19_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_19_MEM_GPIO_PAD_CONFIG_19_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_20 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_20_MEM_GPIO_PAD_CONFIG_20_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_20_MEM_GPIO_PAD_CONFIG_20_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_21 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_21_MEM_GPIO_PAD_CONFIG_21_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_21_MEM_GPIO_PAD_CONFIG_21_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_22 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_22_MEM_GPIO_PAD_CONFIG_22_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_22_MEM_GPIO_PAD_CONFIG_22_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_23 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_23_MEM_GPIO_PAD_CONFIG_23_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_23_MEM_GPIO_PAD_CONFIG_23_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_24 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_24_MEM_GPIO_PAD_CONFIG_24_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_24_MEM_GPIO_PAD_CONFIG_24_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_25 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_25_MEM_GPIO_PAD_CONFIG_25_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_25_MEM_GPIO_PAD_CONFIG_25_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_26 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_26_MEM_GPIO_PAD_CONFIG_26_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_26_MEM_GPIO_PAD_CONFIG_26_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_27 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_27_MEM_GPIO_PAD_CONFIG_27_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_27_MEM_GPIO_PAD_CONFIG_27_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_28 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_28_MEM_GPIO_PAD_CONFIG_28_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_28_MEM_GPIO_PAD_CONFIG_28_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_29 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_29_MEM_GPIO_PAD_CONFIG_29_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_29_MEM_GPIO_PAD_CONFIG_29_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_30 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_30_MEM_GPIO_PAD_CONFIG_30_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_30_MEM_GPIO_PAD_CONFIG_30_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_31 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_31_MEM_GPIO_PAD_CONFIG_31_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_31_MEM_GPIO_PAD_CONFIG_31_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_32 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_32_MEM_GPIO_PAD_CONFIG_32_M \ + 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." it can be used + // for I2C type of peripherals. 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_32_MEM_GPIO_PAD_CONFIG_32_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_33 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_33_MEM_GPIO_PAD_CONFIG_33_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_33_MEM_GPIO_PAD_CONFIG_33_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_34 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_34_MEM_GPIO_PAD_CONFIG_34_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_34_MEM_GPIO_PAD_CONFIG_34_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_35 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_35_MEM_GPIO_PAD_CONFIG_35_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_35_MEM_GPIO_PAD_CONFIG_35_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_36 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_36_MEM_GPIO_PAD_CONFIG_36_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_36_MEM_GPIO_PAD_CONFIG_36_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_37 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_37_MEM_GPIO_PAD_CONFIG_37_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_37_MEM_GPIO_PAD_CONFIG_37_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_38 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_38_MEM_GPIO_PAD_CONFIG_38_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_38_MEM_GPIO_PAD_CONFIG_38_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_39 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_39_MEM_GPIO_PAD_CONFIG_39_M \ + 0x0000003F // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 5 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. IODEN and I8MAEN + // is diesabled for all development + // IO's. These signals are tied to + // logic level '0'. common control + // is implemented for I2MAEN, + // I4MAEN, WKPU, WKPD control . + // refer dev_pad_cmn_config register + // bits. + +#define OCP_SHARED_GPIO_PAD_CONFIG_39_MEM_GPIO_PAD_CONFIG_39_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CONFIG_40 register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CONFIG_40_MEM_GPIO_PAD_CONFIG_40_M \ + 0x0007FFFF // GPIO 0 register: "Bit 0 - 3 is + // used for PAD IO mode selection. + // io_register={ "" 0 => + // """"CONFMODE[0]"""""" "" 1 => + // """"CONFMODE[1]"""""" "" 2 => + // """"CONFMODE[2]"""""" "" 3 => + // """"CONFMODE[3]"""" 4 => + // """"IODEN"""" --> When level ‘1’ + // this disables the PMOS xtors of + // the output stages making them + // open-drain type." "For example in + // case of I2C Value gets latched at + // rising edge of RET33.""" """ 5 => + // """"I2MAEN"""" --> Level ‘1’ + // enables the approx 2mA output + // stage""" """ 6 => """"I4MAEN"""" + // --> Level ‘1’ enables the approx + // 4mA output stage""" """ 7 => + // """"I8MAEN"""" --> Level ‘1’ + // enables the approx 8mA output + // stage. Note: any drive strength + // between 2mA and 14mA can be + // obtained with combination of 2mA + // 4mA and 8mA.""" """ 8 => + // """"IWKPUEN"""" --> 10uA pull up + // (weak strength)""" """ 9 => + // """"IWKPDEN"""" --> 10uA pull + // down (weak strength)""" """ 10 => + // """"IOE_N"""" --> output enable + // value. level ‘0’ enables the IDO + // to PAD path. Else PAD is + // tristated (except for the PU/PD + // which are independent)." "Value + // gets latched at rising edge of + // RET33""" """ 11 =>"""" + // IOE_N_OV"""" --> output enable + // overirde. when bit is set to + // logic '1' IOE_N (bit 4) value + // will control IO IOE_N signal else + // IOE_N is control via selected HW + // logic. strong PULL UP and PULL + // Down control is disabled for all + // IO's. both controls are tied to + // logic level '0'. + +#define OCP_SHARED_GPIO_PAD_CONFIG_40_MEM_GPIO_PAD_CONFIG_40_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_GPIO_PAD_CMN_CONFIG register. +// +//****************************************************************************** +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_D2D_ISO_A_EN \ + 0x00000080 // when '1' enable ISO A control to + // D2D Pads else ISO is disabled. + // For these PADS to be functional + // this signals should be set 0. + +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_D2D_ISO_Y_EN \ + 0x00000040 // when '1' enable ISO Y control to + // D2D Pads else ISO is disabled. + // For these PADS to be functional + // this signals should be set 0. + +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_JTAG_IDIEN \ + 0x00000020 // If level ‘1’ enables the PAD to + // ODI path for JTAG PADS [PAD 23, + // 24, 28, 29]. Else ODI is pulled + // ‘Low’ regardless of PAD level." + // "Value gets latched at rising + // edge of RET33.""" """ + +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTVAL_M \ + 0x00000018 // 00’: hysteriris = 10% of VDDS + // (difference between upper and + // lower threshold of the schmit + // trigger) ‘01’: hysteriris = 20% + // of VDDS (difference between upper + // and lower threshold of the schmit + // trigger) ‘10’: hysteriris = 30% + // of VDDS (difference between upper + // and lower threshold of the schmit + // trigger) ‘11’: hysteriris = 40% + // of VDDS (difference between upper + // and lower threshold of the schmit + // trigger)" """ + +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTVAL_S 3 +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTEN \ + 0x00000004 // If logic ‘0’ there is no + // hysteresis. Set to ‘1’ to enable + // hysteresis. Leave the choice to + // customers""" + +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_IBIASEN \ + 0x00000002 // Normal functional operation set + // this to logic ‘1’ to increase the + // speed of the o/p buffer at the + // cost of 0.2uA static current + // consumption per IO. During IDDQ + // test and during Hibernate this + // would be forced to logic ‘0’. + // Value is not latched at rising + // edge of RET33."" + +#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_IDIEN \ + 0x00000001 // If level ‘1’ enables the PAD to + // ODI path. Else ODI is pulled + // ‘Low’ regardless of PAD level." + // "Value gets latched at rising + // edge of RET33.""" """ + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_D2D_DEV_PAD_CMN_CONFIG register. +// +//****************************************************************************** +#define OCP_SHARED_D2D_DEV_PAD_CMN_CONFIG_MEM_DEV_PAD_CMN_CONF_M \ + 0x0000003F // this register implements common + // IO control to all devement mode + // PADs; these PADs are DEV_PAD33 to + // DEV_PAD39. Bit [1:0] : Drive + // strength control. These 2 bits + // are connected to DEV PAD drive + // strength control. possible drive + // stregnths are 2MA, 4MA and 6 MA + // for the these IO's. bit 0: when + // set to logic value '1' enable 2MA + // drive strength for DEVPAD01 to 07 + // bit 1: when set to logic value + // '1' enable 4MA drive strength for + // DEVPAD01 to 07. bit[3:2] : WK + // PULL UP and PULL down control. + // These 2 bits provide IWKPUEN and + // IWKPDEN control for all DEV IO's. + // bit 2: when set to logic value + // '1' enable WKPU to DEVPAD01 to 07 + // bit 3: when set to logic value + // '1' enable WKPD to DEVPAD01 to + // 07. bit 4: WK PULL control for + // DEV_PKG_DETECT pin. when '1' + // pullup enabled else it is + // disable. bit 5: when set to logic + // value '1' enable 8MA drive + // strength for DEVPAD01 to 07. + +#define OCP_SHARED_D2D_DEV_PAD_CMN_CONFIG_MEM_DEV_PAD_CMN_CONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_D2D_TOSTACK_PAD_CONF register. +// +//****************************************************************************** +#define OCP_SHARED_D2D_TOSTACK_PAD_CONF_MEM_D2D_TOSTACK_PAD_CONF_M \ + 0x1FFFFFFF // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + // this register control OEN2X pin + // of D2D TOSTACK PAD: OEN1X and + // OEN2X decoding is as follows: + // "when ""00"" :" "when ""01"" : + // dirve strength is '1' and output + // buffer enabled." "when ""10"" : + // drive strength is 2 and output + // buffer is disabled." "when ""11"" + // : dirve strength is '3' and + // output buffer enabled." + +#define OCP_SHARED_D2D_TOSTACK_PAD_CONF_MEM_D2D_TOSTACK_PAD_CONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_D2D_MISC_PAD_CONF register. +// +//****************************************************************************** +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_POR_RESET_N \ + 0x00000200 // This register provide OEN2X + // control to D2D PADS OEN/OEN2X + // control. When 0 : Act as input + // buffer else output buffer with + // drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_RESET_N \ + 0x00000100 // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_HCLK \ + 0x00000080 // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TCK \ + 0x00000040 // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TMS \ + 0x00000020 // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TDI \ + 0x00000010 // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_PIOSC \ + 0x00000008 // OEN/OEN2X control. When 0 : Act + // as input buffer else output + // buffer with drive strength 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_SPARE_M \ + 0x00000007 // D2D SPARE PAD OEN/OEN2X control. + // When 0: Act as input buffer else + // output buffer with drive strength + // 2. + +#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_SPARE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SOP_CONF_OVERRIDE register. +// +//****************************************************************************** +#define OCP_SHARED_SOP_CONF_OVERRIDE_MEM_SOP_CONF_OVERRIDE \ + 0x00000001 // when '1' : signal will ovberride + // SoP setting of JTAG PADS. when + // '0': SoP setting will control + // JTAG PADs [ TDI, TDO, TMS, TCK] + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_DEBUGSS_STATUS register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_APPS_MCU_JTAGNSW \ + 0x00000020 // This register contains debug + // subsystem status bits From APPS + // MCU status bit to indicates + // whether serial wire or 4 pins + // jtag select. + +#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_CJTAG_BYPASS_STATUS \ + 0x00000010 // cjtag bypass bit select + +#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_SW_INTERFACE_SEL_STATUS \ + 0x00000008 // serial wire interface bit select + +#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_APPS_TAP_ENABLE_STATUS \ + 0x00000004 // apps tap enable status + +#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_TAPS_ENABLE_STATUS \ + 0x00000002 // tap enable status + +#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_SSBD_UNLOCK \ + 0x00000001 // ssbd unlock status + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_DEBUGMUX_SEL register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_DEBUGMUX_SEL_MEM_CC3XX_DEBUGMUX_SEL_M \ + 0x0000FFFF // debug mux select register. Upper + // 8 bits are used for debug module + // selection. Lower 8 bit [7:0] used + // inside debug module for selecting + // module specific signals. + // Bits[15:8: when set x"00" : GPRCM + // debug bus. When "o1" : SDIO debug + // debug bus when x"02" : + // autonoumous SPI when x"03" : + // TOPIC when x"04": memss when + // x"25": mcu debug bus : APPS debug + // when x"45": mcu debug bus : NWP + // debug when x"65": mcu debug bus : + // AHB2VBUS debug when x"85": mcu + // debug bus : VBUS2HAB debug when + // x"95": mcu debug bus : RCM debug + // when x"A5": mcu debug bus : + // crypto debug when x"06": WLAN + // debug bus when x"07": debugss bus + // when x"08": ADC debug when x"09": + // SDIO PHY debug bus then "others" + // : no debug is selected + +#define OCP_SHARED_CC3XX_DEBUGMUX_SEL_MEM_CC3XX_DEBUGMUX_SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_ALT_PC_VAL_NW register. +// +//****************************************************************************** +#define OCP_SHARED_ALT_PC_VAL_NW_MEM_ALT_PC_VAL_NW_M \ + 0xFFFFFFFF // 32 bit. Program counter value + // for 0x4 address when Alt_pc_en_nw + // is set. + +#define OCP_SHARED_ALT_PC_VAL_NW_MEM_ALT_PC_VAL_NW_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_ALT_PC_VAL_APPS register. +// +//****************************************************************************** +#define OCP_SHARED_ALT_PC_VAL_APPS_MEM_ALT_PC_VAL_APPS_M \ + 0xFFFFFFFF // 32 bit. Program counter value + // for 0x4 address when + // Alt_pc_en_apps is set + +#define OCP_SHARED_ALT_PC_VAL_APPS_MEM_ALT_PC_VAL_APPS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_4 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_4_MEM_SPARE_REG_4_M \ + 0xFFFFFFFE // HW register + +#define OCP_SHARED_SPARE_REG_4_MEM_SPARE_REG_4_S 1 +#define OCP_SHARED_SPARE_REG_4_INVERT_D2D_INTERFACE \ + 0x00000001 // Data to the top die launched at + // negative edge instead of positive + // edge. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_5 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_5_MEM_SPARE_REG_5_M \ + 0xFFFFFFFF // HW register + +#define OCP_SHARED_SPARE_REG_5_MEM_SPARE_REG_5_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SH_SPI_CS_MASK register. +// +//****************************************************************************** +#define OCP_SHARED_SH_SPI_CS_MASK_MEM_SH_SPI_CS_MASK_M \ + 0x0000000F // ( chip select 0 is unmasked + // after reset. When ‘1’ : CS is + // unmasked or else masked. Valid + // configurations are 1000, 0100, + // 0010 or 0001. Any other setting + // can lead to unpredictable + // behavior. + +#define OCP_SHARED_SH_SPI_CS_MASK_MEM_SH_SPI_CS_MASK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_DEVICE_TYPE register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_reserved_M \ + 0x00000060 // reserved bits tied off "00". + +#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_reserved_S 5 +#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_M \ + 0x0000001F // CC3XX Device type information. + +#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_MEM_TOPMUXCTRL_IFORCE register. +// +//****************************************************************************** +#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE1_M \ + 0x000000F0 // [4] 1: switch between + // WLAN_I2C_SCL and + // TOP_GPIO_PORT4_I2C closes 0: + // switch opens [5] 1: switch + // between WLAN_I2C_SCL and + // TOP_VSENSE_PORT closes 0: switch + // opens [6] 1: switch between + // WLAN_I2C_SCL and WLAN_ANA_TP4 + // closes 0: switch opens [7] + // Reserved + +#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE1_S 4 +#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE_M \ + 0x0000000F // [0] 1: switch between + // WLAN_I2C_SDA and + // TOP_GPIO_PORT3_I2C closes 0: + // switch opens [1] 1: switch + // between WLAN_I2C_SDA and + // TOP_IFORCE_PORT closes 0: switch + // opens [2] 1: switch between + // WLAN_I2C_SDA and WLAN_ANA_TP3 + // closes 0: switch opens [3] + // Reserved + +#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_DEV_PACKAGE_DETECT register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_DEV_PACKAGE_DETECT_DEV_PKG_DETECT \ + 0x00000001 // when '0' indicates package type + // is development. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_AUTONMS_SPICLK_SEL register. +// +//****************************************************************************** +#define OCP_SHARED_AUTONMS_SPICLK_SEL_MEM_AUTONOMOUS_BYPASS \ + 0x00000002 // This bit is used to bypass MCPSI + // autonomous mode .if this bit is 1 + // autonomous MCSPI logic will be + // bypassed and it will act as link + // SPI + +#define OCP_SHARED_AUTONMS_SPICLK_SEL_MEM_AUTONMS_SPICLK_SEL \ + 0x00000001 // This bit is used in SPI + // Autonomous mode to switch clock + // from system clock to SPI clk that + // is coming from PAD. When value 1 + // PAD SPI clk is used as system + // clock in LPDS mode by SPI as well + // as autonomous wrapper logic. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_CC3XX_DEV_PADCONF register. +// +//****************************************************************************** +#define OCP_SHARED_CC3XX_DEV_PADCONF_MEM_CC3XX_DEV_PADCONF_M \ + 0x0000FFFF + +#define OCP_SHARED_CC3XX_DEV_PADCONF_MEM_CC3XX_DEV_PADCONF_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_IDMEM_TIM_UPDATE register. +// +//****************************************************************************** +#define OCP_SHARED_IDMEM_TIM_UPDATE_MEM_IDMEM_TIM_UPDATE_M \ + 0xFFFFFFFF + +#define OCP_SHARED_IDMEM_TIM_UPDATE_MEM_IDMEM_TIM_UPDATE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_6 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_6_MEM_SPARE_REG_6_M \ + 0xFFFFFFFF // NWP Software register + +#define OCP_SHARED_SPARE_REG_6_MEM_SPARE_REG_6_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_SPARE_REG_7 register. +// +//****************************************************************************** +#define OCP_SHARED_SPARE_REG_7_MEM_SPARE_REG_7_M \ + 0xFFFFFFFF // NWP Software register + +#define OCP_SHARED_SPARE_REG_7_MEM_SPARE_REG_7_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_APPS_WLAN_ORBIT register. +// +//****************************************************************************** +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_spare_M \ + 0xFFFFFC00 // Spare bit + +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_spare_S 10 +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_status \ + 0x00000200 // A rising edge on this bit + // indicates that the test case + // passes. This bit would be brought + // out on the pin interface during + // ORBIT. + +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_exec \ + 0x00000100 // This register bit is writable by + // the FW and when set to 1 it + // indicates the start of a test + // execution. A failing edge on this + // bit indicates that the test + // execution is complete. This bit + // would be brought out on the pin + // interface during ORBIT. + +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_id_M \ + 0x000000FC // Implies the test case ID that + // needs to run. + +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_id_S 2 +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_halt_proc \ + 0x00000002 // This bit is used to trigger the + // execution of test cases within + // the (ROM based) IP. + +#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_mode \ + 0x00000001 // When this bit is 1 it implies + // ORBIT mode of operation and the + // (ROM based) IP start the + // execution from a test case + // perspective + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// OCP_SHARED_O_APPS_WLAN_SCRATCH_PAD register. +// +//****************************************************************************** +#define OCP_SHARED_APPS_WLAN_SCRATCH_PAD_MEM_APPS_WLAN_SCRATCH_PAD_M \ + 0xFFFFFFFF // scratch pad register. + +#define OCP_SHARED_APPS_WLAN_SCRATCH_PAD_MEM_APPS_WLAN_SCRATCH_PAD_S 0 + + + +#endif // __HW_OCP_SHARED_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_shamd5.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_shamd5.h new file mode 100644 index 00000000..cf6254f5 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_shamd5.h @@ -0,0 +1,1242 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_SHAMD5_H__ +#define __HW_SHAMD5_H__ + +//***************************************************************************** +// +// The following are defines for the SHAMD5_P register offsets. +// +//***************************************************************************** +#define SHAMD5_O_ODIGEST_A 0x00000000 // WRITE: Outer Digest [127:96] for + // MD5 [159:128] for SHA-1 [255:224] + // for SHA-2 / HMAC Key [31:0] for + // HMAC key proc READ: Outer Digest + // [127:96] for MD5 [159:128] for + // SHA-1 [255:224] for SHA-2 +#define SHAMD5_O_ODIGEST_B 0x00000004 // WRITE: Outer Digest [95:64] for + // MD5 [127:96] for SHA-1 [223:192] + // for SHA-2 / HMAC Key [63:32] for + // HMAC key proc READ: Outer Digest + // [95:64] for MD5 [127:96] for + // SHA-1 [223:192] for SHA-2 +#define SHAMD5_O_ODIGEST_C 0x00000008 // WRITE: Outer Digest [63:32] for + // MD5 [95:64] for SHA-1 [191:160] + // for SHA-2 / HMAC Key [95:64] for + // HMAC key proc READ: Outer Digest + // [63:32] for MD5 [95:64] for SHA-1 + // [191:160] for SHA-2 +#define SHAMD5_O_ODIGEST_D 0x0000000C // WRITE: Outer Digest [31:0] for + // MD5 [63:31] for SHA-1 [159:128] + // for SHA-2 / HMAC Key [127:96] for + // HMAC key proc READ: Outer Digest + // [31:0] for MD5 [63:32] for SHA-1 + // [159:128] for SHA-2 +#define SHAMD5_O_ODIGEST_E 0x00000010 // WRITE: Outer Digest [31:0] for + // SHA-1 [127:96] for SHA-2 / HMAC + // Key [159:128] for HMAC key proc + // READ: Outer Digest [31:0] for + // SHA-1 [127:96] for SHA-2 +#define SHAMD5_O_ODIGEST_F 0x00000014 // WRITE: Outer Digest [95:64] for + // SHA-2 / HMAC Key [191:160] for + // HMAC key proc READ: Outer Digest + // [95:64] for SHA-2 +#define SHAMD5_O_ODIGEST_G 0x00000018 // WRITE: Outer Digest [63:32] for + // SHA-2 / HMAC Key [223:192] for + // HMAC key proc READ: Outer Digest + // [63:32] for SHA-2 +#define SHAMD5_O_ODIGEST_H 0x0000001C // WRITE: Outer Digest [31:0] for + // SHA-2 / HMAC Key [255:224] for + // HMAC key proc READ: Outer Digest + // [31:0] for SHA-2 +#define SHAMD5_O_IDIGEST_A 0x00000020 // WRITE: Inner / Initial Digest + // [127:96] for MD5 [159:128] for + // SHA-1 [255:224] for SHA-2 / HMAC + // Key [287:256] for HMAC key proc + // READ: Intermediate / Inner Digest + // [127:96] for MD5 [159:128] for + // SHA-1 [255:224] for SHA-2 / + // Result Digest/MAC [127:96] for + // MD5 [159:128] for SHA-1 [223:192] + // for SHA-2 224 [255:224] for SHA-2 + // 256 +#define SHAMD5_O_IDIGEST_B 0x00000024 // WRITE: Inner / Initial Digest + // [95:64] for MD5 [127:96] for + // SHA-1 [223:192] for SHA-2 / HMAC + // Key [319:288] for HMAC key proc + // READ: Intermediate / Inner Digest + // [95:64] for MD5 [127:96] for + // SHA-1 [223:192] for SHA-2 / + // Result Digest/MAC [95:64] for MD5 + // [127:96] for SHA-1 [191:160] for + // SHA-2 224 [223:192] for SHA-2 256 +#define SHAMD5_O_IDIGEST_C 0x00000028 // WRITE: Inner / Initial Digest + // [63:32] for MD5 [95:64] for SHA-1 + // [191:160] for SHA- 2 / HMAC Key + // [351:320] for HMAC key proc READ: + // Intermediate / Inner Digest + // [63:32] for MD5 [95:64] for SHA-1 + // [191:160] for SHA-2 / Result + // Digest/MAC [63:32] for MD5 + // [95:64] for SHA-1 [159:128] for + // SHA-2 224 [191:160] for SHA-2 256 +#define SHAMD5_O_IDIGEST_D 0x0000002C // WRITE: Inner / Initial Digest + // [31:0] for MD5 [63:32] for SHA-1 + // [159:128] for SHA-2 / HMAC Key + // [383:352] for HMAC key proc READ: + // Intermediate / Inner Digest + // [31:0] for MD5 [63:32] for SHA-1 + // [159:128] for SHA-2 / Result + // Digest/MAC [31:0] for MD5 [63:32] + // for SHA-1 [127:96] for SHA-2 224 + // [159:128] for SHA-2 256 +#define SHAMD5_O_IDIGEST_E 0x00000030 // WRITE: Inner / Initial Digest + // [31:0] for SHA-1 [127:96] for + // SHA-2 / HMAC Key [415:384] for + // HMAC key proc READ: Intermediate + // / Inner Digest [31:0] for SHA-1 + // [127:96] for SHA-2 / Result + // Digest/MAC [31:0] for SHA-1 + // [95:64] for SHA-2 224 [127:96] + // for SHA-2 256 +#define SHAMD5_O_IDIGEST_F 0x00000034 // WRITE: Inner / Initial Digest + // [95:64] for SHA-2 / HMAC Key + // [447:416] for HMAC key proc READ: + // Intermediate / Inner Digest + // [95:64] for SHA-2 / Result + // Digest/MAC [63:32] for SHA-2 224 + // [95:64] for SHA-2 256 +#define SHAMD5_O_IDIGEST_G 0x00000038 // WRITE: Inner / Initial Digest + // [63:32] for SHA-2 / HMAC Key + // [479:448] for HMAC key proc READ: + // Intermediate / Inner Digest + // [63:32] for SHA-2 / Result + // Digest/MAC [31:0] for SHA-2 224 + // [63:32] for SHA-2 256 +#define SHAMD5_O_IDIGEST_H 0x0000003C // WRITE: Inner / Initial Digest + // [31:0] for SHA-2 / HMAC Key + // [511:480] for HMAC key proc READ: + // Intermediate / Inner Digest + // [31:0] for SHA-2 / Result + // Digest/MAC [31:0] for SHA-2 256 +#define SHAMD5_O_DIGEST_COUNT 0x00000040 // WRITE: Initial Digest Count + // ([31:6] only [5:0] assumed 0) + // READ: Result / IntermediateDigest + // Count The initial digest byte + // count for hash/HMAC continue + // operations (HMAC Key Processing = + // 0 and Use Algorithm Constants = + // 0) on the Secure World must be + // written to this register prior to + // starting the operation by writing + // to S_HASH_MODE. When either HMAC + // Key Processing is 1 or Use + // Algorithm Constants is 1 this + // register does not need to be + // written it will be overwritten + // with 64 (1 hash block of key XOR + // ipad) or 0 respectively + // automatically. When starting a + // HMAC operation from pre-computes + // (HMAC Key Processing is 0) then + // the value 64 must be written here + // to compensate for the appended + // key XOR ipad block. Note that the + // value written should always be a + // 64 byte multiple the lower 6 bits + // written are ignored. The updated + // digest byte count (initial digest + // byte count + bytes processed) can + // be read from this register when + // the status register indicates + // that the operation is done or + // suspended due to a context switch + // request or when a Secure World + // context out DMA is requested. In + // Advanced DMA mode when not + // suspended with a partial result + // reading the SHAMD5_DIGEST_COUNT + // register triggers the Hash/HMAC + // Engine to start the next context + // input DMA. Therefore reading the + // SHAMD5_DIGEST_COUNT register + // should always be the last + // context-read action if not + // suspended with a partial result + // (i.e. PartHashReady interrupt not + // pending). +#define SHAMD5_O_MODE 0x00000044 // Register SHAMD5_MODE +#define SHAMD5_O_LENGTH 0x00000048 // WRITE: Block Length / Remaining + // Byte Count (bytes) READ: + // Remaining Byte Count. The value + // programmed MUST be a 64-byte + // multiple if Close Hash is set to + // 0. This register is also the + // trigger to start processing: once + // this register is written the core + // will commence requesting input + // data via DMA or IRQ (if + // programmed length > 0) and start + // processing. The remaining byte + // count for the active operation + // can be read from this register + // when the interrupt status + // register indicates that the + // operation is suspended due to a + // context switch request. +#define SHAMD5_O_DATA0_IN 0x00000080 // Data input message 0 +#define SHAMD5_O_DATA1_IN 0x00000084 // Data input message 1 +#define SHAMD5_O_DATA2_IN 0x00000088 // Data input message 2 +#define SHAMD5_O_DATA3_IN 0x0000008C // Data input message 3 +#define SHAMD5_O_DATA4_IN 0x00000090 // Data input message 4 +#define SHAMD5_O_DATA5_IN 0x00000094 // Data input message 5 +#define SHAMD5_O_DATA6_IN 0x00000098 // Data input message 6 +#define SHAMD5_O_DATA7_IN 0x0000009C // Data input message 7 +#define SHAMD5_O_DATA8_IN 0x000000A0 // Data input message 8 +#define SHAMD5_O_DATA9_IN 0x000000A4 // Data input message 9 +#define SHAMD5_O_DATA10_IN 0x000000A8 // Data input message 10 +#define SHAMD5_O_DATA11_IN 0x000000AC // Data input message 11 +#define SHAMD5_O_DATA12_IN 0x000000B0 // Data input message 12 +#define SHAMD5_O_DATA13_IN 0x000000B4 // Data input message 13 +#define SHAMD5_O_DATA14_IN 0x000000B8 // Data input message 14 +#define SHAMD5_O_DATA15_IN 0x000000BC // Data input message 15 +#define SHAMD5_O_REVISION 0x00000100 // Register SHAMD5_REV +#define SHAMD5_O_SYSCONFIG 0x00000110 // Register SHAMD5_SYSCONFIG +#define SHAMD5_O_SYSSTATUS 0x00000114 // Register SHAMD5_SYSSTATUS +#define SHAMD5_O_IRQSTATUS 0x00000118 // Register SHAMD5_IRQSTATUS +#define SHAMD5_O_IRQENABLE 0x0000011C // Register SHAMD5_IRQENABLE. The + // SHAMD5_IRQENABLE register contains + // an enable bit for each unique + // interrupt for the public side. An + // interrupt is enabled when both + // the global enable in + // SHAMD5_SYSCONFIG (PIT_en) and the + // bit in this register are both set + // to 1. An interrupt that is + // enabled is propagated to the + // SINTREQUEST_P output. Please note + // that the dedicated partial hash + // output (SINTREQUEST_PART_P) is + // not affected by this register it + // is only affected by the global + // enable SHAMD5_SYSCONFIG (PIT_en). +#define SHAMD5_O_HASH512_ODIGEST_A \ + 0x00000200 + +#define SHAMD5_O_HASH512_ODIGEST_B \ + 0x00000204 + +#define SHAMD5_O_HASH512_ODIGEST_C \ + 0x00000208 + +#define SHAMD5_O_HASH512_ODIGEST_D \ + 0x0000020C + +#define SHAMD5_O_HASH512_ODIGEST_E \ + 0x00000210 + +#define SHAMD5_O_HASH512_ODIGEST_F \ + 0x00000214 + +#define SHAMD5_O_HASH512_ODIGEST_G \ + 0x00000218 + +#define SHAMD5_O_HASH512_ODIGEST_H \ + 0x0000021C + +#define SHAMD5_O_HASH512_ODIGEST_I \ + 0x00000220 + +#define SHAMD5_O_HASH512_ODIGEST_J \ + 0x00000224 + +#define SHAMD5_O_HASH512_ODIGEST_K \ + 0x00000228 + +#define SHAMD5_O_HASH512_ODIGEST_L \ + 0x0000022C + +#define SHAMD5_O_HASH512_ODIGEST_M \ + 0x00000230 + +#define SHAMD5_O_HASH512_ODIGEST_N \ + 0x00000234 + +#define SHAMD5_O_HASH512_ODIGEST_O \ + 0x00000238 + +#define SHAMD5_O_HASH512_ODIGEST_P \ + 0x0000023C + +#define SHAMD5_O_HASH512_IDIGEST_A \ + 0x00000240 + +#define SHAMD5_O_HASH512_IDIGEST_B \ + 0x00000244 + +#define SHAMD5_O_HASH512_IDIGEST_C \ + 0x00000248 + +#define SHAMD5_O_HASH512_IDIGEST_D \ + 0x0000024C + +#define SHAMD5_O_HASH512_IDIGEST_E \ + 0x00000250 + +#define SHAMD5_O_HASH512_IDIGEST_F \ + 0x00000254 + +#define SHAMD5_O_HASH512_IDIGEST_G \ + 0x00000258 + +#define SHAMD5_O_HASH512_IDIGEST_H \ + 0x0000025C + +#define SHAMD5_O_HASH512_IDIGEST_I \ + 0x00000260 + +#define SHAMD5_O_HASH512_IDIGEST_J \ + 0x00000264 + +#define SHAMD5_O_HASH512_IDIGEST_K \ + 0x00000268 + +#define SHAMD5_O_HASH512_IDIGEST_L \ + 0x0000026C + +#define SHAMD5_O_HASH512_IDIGEST_M \ + 0x00000270 + +#define SHAMD5_O_HASH512_IDIGEST_N \ + 0x00000274 + +#define SHAMD5_O_HASH512_IDIGEST_O \ + 0x00000278 + +#define SHAMD5_O_HASH512_IDIGEST_P \ + 0x0000027C + +#define SHAMD5_O_HASH512_DIGEST_COUNT \ + 0x00000280 + +#define SHAMD5_O_HASH512_MODE 0x00000284 +#define SHAMD5_O_HASH512_LENGTH 0x00000288 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_A register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_A_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_A_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_B register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_B_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_B_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_C register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_C_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_C_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_D register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_D_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_D_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_E register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_E_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_E_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_F register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_F_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_F_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_G register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_G_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_G_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_H register. +// +//****************************************************************************** +#define SHAMD5_ODIGEST_H_DATA_M 0xFFFFFFFF // data +#define SHAMD5_ODIGEST_H_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_A register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_A_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_A_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_B register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_B_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_B_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_C register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_C_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_C_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_D register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_D_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_D_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_E register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_E_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_E_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_F register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_F_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_F_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_G register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_G_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_G_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_H register. +// +//****************************************************************************** +#define SHAMD5_IDIGEST_H_DATA_M 0xFFFFFFFF // data +#define SHAMD5_IDIGEST_H_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_DIGEST_COUNT register. +// +//****************************************************************************** +#define SHAMD5_DIGEST_COUNT_DATA_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DIGEST_COUNT_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_MODE register. +// +//****************************************************************************** +#define SHAMD5_MODE_HMAC_OUTER_HASH \ + 0x00000080 // The HMAC Outer Hash is performed + // on the hash digest when the inner + // hash hash finished (block length + // exhausted and final hash + // performed if close_hash is 1). + // This bit should normally be set + // together with close_hash to + // finish the inner hash first or + // Block Length should be zero (HMAC + // continue with the just outer hash + // to be done). Auto cleared + // internally when outer hash + // performed. 0 No operation 1 hmac + // processing + +#define SHAMD5_MODE_HMAC_KEY_PROC \ + 0x00000020 // Performs HMAC key processing on + // the 512 bit HMAC key loaded into + // the SHAMD5_IDIGEST_{A to H} and + // SHAMD5_ODIGEST_{A to H} register + // block. Once HMAC key processing + // is finished this bit is + // automatically cleared and the + // resulting Inner and Outer digest + // is available from + // SHAMD5_IDIGEST_{A to H} and + // SHAMD5_ODIGEST_{A to H} + // respectively after which regular + // hash processing (using + // SHAMD5_IDIGEST_{A to H} as initial + // digest) will commence until the + // Block Length is exhausted. 0 No + // operation. 1 Hmac processing. + +#define SHAMD5_MODE_CLOSE_HASH 0x00000010 // Performs the padding the + // hash/HMAC will be 'closed' at the + // end of the block as per + // MD5/SHA-1/SHA-2 specification + // (i.e. appropriate padding is + // added) or no padding is done + // allowing the hash to be continued + // later. However if the hash/HMAC + // is not closed then the Block + // Length MUST be a multiple of 64 + // bytes to ensure correct + // operation. Auto cleared + // internally when hash closed. 0 No + // padding hash computation can be + // contimued. 1 Last packet will be + // padded. +#define SHAMD5_MODE_ALGO_CONSTANT \ + 0x00000008 // The initial digest register will + // be overwritten with the algorithm + // constants for the selected + // algorithm when hashing and the + // initial digest count register + // will be reset to 0. This will + // start a normal hash operation. + // When continuing an existing hash + // or when performing an HMAC + // operation this register must be + // set to 0 and the + // intermediate/inner digest or HMAC + // key and digest count need to be + // written to the context input + // registers prior to writing + // SHAMD5_MODE. Auto cleared + // internally after first block + // processed. 0 Use pre-calculated + // digest (from an other operation) + // 1 Use constants of the selected + // algo. + +#define SHAMD5_MODE_ALGO_M 0x00000006 // These bits select the hash + // algorithm to be used for + // processing: 0x0 md5_128 algorithm + // 0x1 sha1_160 algorithm 0x2 + // sha2_224 algorithm 0x3 sha2_256 + // algorithm +#define SHAMD5_MODE_ALGO_S 1 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_LENGTH register. +// +//****************************************************************************** +#define SHAMD5_LENGTH_DATA_M 0xFFFFFFFF // data +#define SHAMD5_LENGTH_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA0_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA0_IN_DATA0_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA0_IN_DATA0_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA1_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA1_IN_DATA1_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA1_IN_DATA1_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA2_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA2_IN_DATA2_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA2_IN_DATA2_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA3_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA3_IN_DATA3_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA3_IN_DATA3_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA4_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA4_IN_DATA4_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA4_IN_DATA4_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA5_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA5_IN_DATA5_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA5_IN_DATA5_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA6_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA6_IN_DATA6_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA6_IN_DATA6_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA7_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA7_IN_DATA7_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA7_IN_DATA7_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA8_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA8_IN_DATA8_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA8_IN_DATA8_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA9_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA9_IN_DATA9_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA9_IN_DATA9_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA10_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA10_IN_DATA10_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA10_IN_DATA10_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA11_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA11_IN_DATA11_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA11_IN_DATA11_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA12_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA12_IN_DATA12_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA12_IN_DATA12_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA13_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA13_IN_DATA13_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA13_IN_DATA13_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA14_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA14_IN_DATA14_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA14_IN_DATA14_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_DATA15_IN register. +// +//****************************************************************************** +#define SHAMD5_DATA15_IN_DATA15_IN_M \ + 0xFFFFFFFF // data + +#define SHAMD5_DATA15_IN_DATA15_IN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_REVISION register. +// +//****************************************************************************** +#define SHAMD5_REVISION_SCHEME_M 0xC0000000 +#define SHAMD5_REVISION_SCHEME_S 30 +#define SHAMD5_REVISION_FUNC_M 0x0FFF0000 // Function indicates a software + // compatible module family. If + // there is no level of software + // compatibility a new Func number + // (and hence REVISION) should be + // assigned. +#define SHAMD5_REVISION_FUNC_S 16 +#define SHAMD5_REVISION_R_RTL_M 0x0000F800 // RTL Version (R) maintained by IP + // design owner. RTL follows a + // numbering such as X.Y.R.Z which + // are explained in this table. R + // changes ONLY when: (1) PDS + // uploads occur which may have been + // due to spec changes (2) Bug fixes + // occur (3) Resets to '0' when X or + // Y changes. Design team has an + // internal 'Z' (customer invisible) + // number which increments on every + // drop that happens due to DV and + // RTL updates. Z resets to 0 when R + // increments. +#define SHAMD5_REVISION_R_RTL_S 11 +#define SHAMD5_REVISION_X_MAJOR_M \ + 0x00000700 // Major Revision (X) maintained by + // IP specification owner. X changes + // ONLY when: (1) There is a major + // feature addition. An example + // would be adding Master Mode to + // Utopia Level2. The Func field (or + // Class/Type in old PID format) + // will remain the same. X does NOT + // change due to: (1) Bug fixes (2) + // Change in feature parameters. + +#define SHAMD5_REVISION_X_MAJOR_S 8 +#define SHAMD5_REVISION_CUSTOM_M 0x000000C0 +#define SHAMD5_REVISION_CUSTOM_S 6 +#define SHAMD5_REVISION_Y_MINOR_M \ + 0x0000003F // Minor Revision (Y) maintained by + // IP specification owner. Y changes + // ONLY when: (1) Features are + // scaled (up or down). Flexibility + // exists in that this feature + // scalability may either be + // represented in the Y change or a + // specific register in the IP that + // indicates which features are + // exactly available. (2) When + // feature creeps from Is-Not list + // to Is list. But this may not be + // the case once it sees silicon; in + // which case X will change. Y does + // NOT change due to: (1) Bug fixes + // (2) Typos or clarifications (3) + // major functional/feature + // change/addition/deletion. Instead + // these changes may be reflected + // via R S X as applicable. Spec + // owner maintains a + // customer-invisible number 'S' + // which changes due to: (1) + // Typos/clarifications (2) Bug + // documentation. Note that this bug + // is not due to a spec change but + // due to implementation. + // Nevertheless the spec tracks the + // IP bugs. An RTL release (say for + // silicon PG1.1) that occurs due to + // bug fix should document the + // corresponding spec number (X.Y.S) + // in its release notes. + +#define SHAMD5_REVISION_Y_MINOR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_SYSCONFIG register. +// +//****************************************************************************** +#define SHAMD5_SYSCONFIG_PADVANCED \ + 0x00000080 // If set to 1 Advanced mode is + // enabled for the Secure World. If + // set to 0 Legacy mode is enabled + // for the Secure World. + +#define SHAMD5_SYSCONFIG_PCONT_SWT \ + 0x00000040 // Finish all pending data and + // context DMA input requests (but + // will not assert any new requests) + // finish processing all data in the + // module and provide a saved + // context (partial hash result + // updated digest count remaining + // length updated mode information + // where applicable) for the last + // operation that was interrupted so + // that it can be resumed later. + +#define SHAMD5_SYSCONFIG_PDMA_EN 0x00000008 +#define SHAMD5_SYSCONFIG_PIT_EN 0x00000004 +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_SYSSTATUS register. +// +//****************************************************************************** +#define SHAMD5_SYSSTATUS_RESETDONE \ + 0x00000001 // data + +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IRQSTATUS register. +// +//****************************************************************************** +#define SHAMD5_IRQSTATUS_CONTEXT_READY \ + 0x00000008 // indicates that the secure side + // context input registers are + // available for a new context for + // the next packet to be processed. + +#define SHAMD5_IRQSTATUS_PARTHASH_READY \ + 0x00000004 // After a secure side context + // switch request this bit will read + // as 1 indicating that the saved + // context is available from the + // secure side context output + // registers. Note that if the + // context switch request coincides + // with a final hash (when hashing) + // or an outer hash (when doing + // HMAC) that PartHashReady will not + // become active but a regular + // Output Ready will occur instead + // (indicating that the result is + // final and therefore no + // continuation is required). + +#define SHAMD5_IRQSTATUS_INPUT_READY \ + 0x00000002 // indicates that the secure side + // data FIFO is ready to receive the + // next 64 byte data block. + +#define SHAMD5_IRQSTATUS_OUTPUT_READY \ + 0x00000001 // Indicates that a (partial) + // result or saved context is + // available from the secure side + // context output registers. + +//****************************************************************************** +// +// The following are defines for the bit fields in the SHAMD5_O_IRQENABLE register. +// +//****************************************************************************** +#define SHAMD5_IRQENABLE_M_CONTEXT_READY \ + 0x00000008 // mask for context ready + +#define SHAMD5_IRQENABLE_M_PARTHASH_READY \ + 0x00000004 // mask for partial hash + +#define SHAMD5_IRQENABLE_M_INPUT_READY \ + 0x00000002 // mask for input_ready + +#define SHAMD5_IRQENABLE_M_OUTPUT_READY \ + 0x00000001 // mask for output_ready + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_A register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_A_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_A_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_B register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_B_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_B_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_C register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_C_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_C_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_D register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_D_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_D_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_E register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_E_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_E_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_F register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_F_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_F_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_G register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_G_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_G_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_H register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_H_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_H_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_I register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_I_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_I_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_J register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_J_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_J_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_K register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_K_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_K_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_L register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_L_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_L_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_M register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_M_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_M_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_N register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_N_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_N_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_O register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_O_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_O_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_ODIGEST_P register. +// +//****************************************************************************** +#define SHAMD5_HASH512_ODIGEST_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_ODIGEST_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_A register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_A_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_A_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_B register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_B_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_B_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_C register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_C_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_C_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_D register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_D_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_D_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_E register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_E_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_E_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_F register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_F_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_F_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_G register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_G_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_G_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_H register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_H_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_H_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_I register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_I_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_I_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_J register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_J_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_J_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_K register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_K_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_K_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_L register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_L_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_L_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_M register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_M_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_M_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_N register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_N_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_N_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_O register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_O_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_O_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_IDIGEST_P register. +// +//****************************************************************************** +#define SHAMD5_HASH512_IDIGEST_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_IDIGEST_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_DIGEST_COUNT register. +// +//****************************************************************************** +#define SHAMD5_HASH512_DIGEST_COUNT_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_DIGEST_COUNT_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_MODE register. +// +//****************************************************************************** +#define SHAMD5_HASH512_MODE_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_MODE_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// SHAMD5_O_HASH512_LENGTH register. +// +//****************************************************************************** +#define SHAMD5_HASH512_LENGTH_DATA_M \ + 0xFFFFFFFF + +#define SHAMD5_HASH512_LENGTH_DATA_S 0 + + + +#endif // __HW_SHAMD5_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_stack_die_ctrl.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_stack_die_ctrl.h new file mode 100644 index 00000000..eba31e4f --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_stack_die_ctrl.h @@ -0,0 +1,764 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + + +#ifndef __HW_STACK_DIE_CTRL_H__ +#define __HW_STACK_DIE_CTRL_H__ + +//***************************************************************************** +// +// The following are defines for the STACK_DIE_CTRL register offsets. +// +//***************************************************************************** +#define STACK_DIE_CTRL_O_STK_UP_RESET \ + 0x00000000 // Can be written only by Base + // Processor. Writing to this + // register will reset the stack + // processor reset will be + // de-asserted upon clearing this + // register. + +#define STACK_DIE_CTRL_O_SR_MASTER_PRIORITY \ + 0x00000004 // This register defines who among + // base processor and stack + // processor have highest priority + // for Sram Access. Can be written + // only by Base Processor. + +#define STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK2 \ + 0x00000008 // In Spinlock mode this Register + // defines who among base processor + // and stack processor have access + // to Sram Bank2 right now. In + // Handshake mode this Register + // defines who among base processor + // and stack processor have access + // to Sram Bank2 and Bank3 right + // now. Its Clear only register and + // is set by hardware. Lower bit can + // be cleared only by Base Processor + // and Upper bit Cleared only by the + // Stack processor. + +#define STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK2 \ + 0x0000000C // In Spinlock mode whenever Base + // processor wants the access to + // Sram Bank2 it should request for + // it by writing into this register. + // It'll get interrupt whenever it + // is granted. In Handshake mode + // this bit will be set by Stack + // processor. Its a set only bit and + // is cleared by HW when the request + // is granted. + +#define STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK2 \ + 0x00000010 // In Spinlock mode Whenever Stack + // processor wants the access to + // Sram Bank2 it should request for + // it by writing into this register. + // It'll get interrupt whenever it + // is granted. In Handshake mode + // this bit will be set by the Base + // processor. Its a set only bit and + // is cleared by HW when the request + // is granted. + +#define STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK3 \ + 0x00000014 // Register defines who among base + // processor and stack processor + // have access to Sram Bank3 right + // now. Its Clear only register and + // is set by hardware. Lower bit can + // be cleared only by Base Processor + // and Upper bit Cleared only by the + // Stack processor. + +#define STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK3 \ + 0x00000018 // In Spinlock mode whenever Base + // processor wants the access to + // Sram Bank3 it should request for + // it by writing into this register. + // It'll get interrupt whenever it + // is granted. In Handshake mode + // this bit will be set by Stack + // processor. Its a set only bit and + // is cleared by HW when the request + // is granted. + +#define STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK3 \ + 0x0000001C // In Spinlock mode Whenever Stack + // processor wants the access to + // Sram Bank3 it should request for + // it by writing into this register. + // It'll get interrupt whenever it + // is granted. In Handshake mode + // this bit will be set by the Base + // processor. Its a set only bit and + // is cleared by HW when the request + // is granted. + +#define STACK_DIE_CTRL_O_RDSM_CFG_CPU \ + 0x00000020 // Read State Machine timing + // configuration register. Generally + // Bit 4 and 3 will be identical. + // For stacked die always 43 are 0 + // and 6:5 == 1 for 120Mhz. + +#define STACK_DIE_CTRL_O_RDSM_CFG_EE \ + 0x00000024 // Read State Machine timing + // configuration register. Generally + // Bit 4 and 3 will be identical. + // For stacked die always 43 are 0 + // and 6:5 == 1 for 120Mhz. + +#define STACK_DIE_CTRL_O_BASE_UP_IRQ_LOG \ + 0x00000028 // Reading this register Base + // procesor will able to know the + // reason for the interrupt. This is + // clear only register - set by HW + // upon an interrupt to Base + // processor and can be cleared only + // by BASE processor. + +#define STACK_DIE_CTRL_O_STK_UP_IRQ_LOG \ + 0x0000002C // Reading this register Stack + // procesor will able to know the + // reason for the interrupt. This is + // clear only register - set by HW + // upon an interrupt to Stack + // processor and can be cleared only + // by Stack processor. + +#define STACK_DIE_CTRL_O_STK_CLK_EN \ + 0x00000030 // Can be written only by base + // processor. Controls the enable + // pin of the cgcs for the clocks + // going to CM3 dft ctrl block and + // Sram. + +#define STACK_DIE_CTRL_O_SPIN_LOCK_MODE \ + 0x00000034 // Can be written only by the base + // processor. Decides the ram + // sharing mode :: handshake or + // Spinlock mode. + +#define STACK_DIE_CTRL_O_BUS_FAULT_ADDR \ + 0x00000038 // Stores the last bus fault + // address. + +#define STACK_DIE_CTRL_O_BUS_FAULT_CLR \ + 0x0000003C // write only registers on read + // returns 0.W Write 1 to clear the + // bust fault to store the new bus + // fault address + +#define STACK_DIE_CTRL_O_RESET_CAUSE \ + 0x00000040 // Reset cause value captured from + // the ICR_CLKRST block. + +#define STACK_DIE_CTRL_O_WDOG_TIMER_EVENT \ + 0x00000044 // Watchdog timer event value + // captured from the ICR_CLKRST + // block + +#define STACK_DIE_CTRL_O_DMA_REQ \ + 0x00000048 // To send Dma Request to bottom + // die. + +#define STACK_DIE_CTRL_O_SRAM_JUMP_OFFSET_ADDR \ + 0x0000004C // Address offset within SRAM to + // which CM3 should jump after + // reset. + +#define STACK_DIE_CTRL_O_SW_REG1 \ + 0x00000050 // These are sw registers for + // topdie processor and bottom die + // processor to communicate. Both + // can set and read these registers. + // In case of write clash bottom + // die's processor wins and top die + // processor access is ignored. + +#define STACK_DIE_CTRL_O_SW_REG2 \ + 0x00000054 // These are sw registers for + // topdie processor and bottom die + // processor to communicate. Both + // can set and read these registers. + // In case of write clash bottom + // die's processor wins and top die + // processor access is ignored. + +#define STACK_DIE_CTRL_O_FMC_SLEEP_CTL \ + 0x00000058 // By posting the request Flash can + // be put into low-power mode + // (Sleep) without powering down the + // Flash. Earlier (in Garnet) this + // was fully h/w controlled and the + // control for this was coming from + // SysCtl while entering into Cortex + // Deep-sleep mode. But for our + // device the D2D i/f doesnt support + // this. The Firmware has to program + // the register in the top-die for + // entering into this mode and wait + // for an interrupt. + +#define STACK_DIE_CTRL_O_MISC_CTL \ + 0x0000005C // Miscellanious control register. + +#define STACK_DIE_CTRL_O_SW_DFT_CTL \ + 0x000000FC // DFT control and status bits + +#define STACK_DIE_CTRL_O_PADN_CTL_0 \ + 0x00000100 // Mainly for For controlling the + // pads OEN pins. There are total 60 + // pads and hence 60 control registe + // i.e n value varies from 0 to 59. + // Here is the mapping for the + // pad_ctl register number and the + // functionality : 0 D2DPAD_DMAREQ1 + // 1 D2DPAD_DMAREQ0 2 + // D2DPAD_INT2BASE 3 D2DPAD_PIOSC 4 + // D2DPAD_RST_N 5 D2DPAD_POR_RST_N 6 + // D2DPAD_HCLK 7 D2DPAD_JTAG_TDO 8 + // D2DPAD_JTAG_TCK 9 D2DPAD_JTAG_TMS + // 10 D2DPAD_JTAG_TDI 11-27 + // D2DPAD_FROMSTACK[D2D_FROMSTACK_SIZE + // -1:0] 28-56 D2DPAD_TOSTACK + // [D2D_TOSTACK_SIZE -1:0] 57-59 + // D2DPAD_SPARE [D2D_SPARE_PAD_SIZE + // -1:0] 0:00 + + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_UP_RESET register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_UP_RESET_UP_RESET \ + 0x00000001 // 1 :Assert Reset 0 : Deassert the + // Reset + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_SR_MASTER_PRIORITY register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_SR_MASTER_PRIORITY_PRIORITY_M \ + 0x00000003 // 00 : Equal Priority 01 : Stack + // Processor have priority 10 : Base + // Processor have priority 11 : + // Unused + +#define STACK_DIE_CTRL_SR_MASTER_PRIORITY_PRIORITY_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK2 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK2_STK_UP_ACCSS \ + 0x00000002 // Stack Processor should clear it + // when it is done with the sram + // bank usage. Set by HW It is set + // when Stack Processor is granted + // the access to this bank + +#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK2_BASE_UP_ACCSS \ + 0x00000001 // Base Processor should clear it + // when it is done wth the sram + // usage. Set by HW It is set when + // Base Processor is granted the + // access to this bank + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK2 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_BASE_UP_ACC_REQ_BK2_ACCSS_REQ \ + 0x00000001 // Base Processor will set when + // Sram access is needed in Spin + // Lock mode. In Handshake mode + // Stack Processor will set to + // inform Base Processor that it is + // done with the processing of data + // in SRAM and is now ready to use + // by the base processor. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK2 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_UP_ACC_REQ_BK2_ACCSS_REQ \ + 0x00000001 // Stack Processor will set when + // Sram access is needed in Spin + // Lock mode. In Handshake mode Base + // Processor will set to inform + // Stack Processor to start + // processing the data in the Ram. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK3 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK3_STK_UP_ACCSS \ + 0x00000002 // Stack Processor should clear it + // when it is done with the sram + // bank usage. Set by HW It is set + // when Stack Processor is granted + // the access to this bank. + +#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK3_BASE_UP_ACCSS \ + 0x00000001 // Base Processor should clear it + // when it is done wth the sram + // usage. Set by HW it is set when + // Base Processor is granted the + // access to this bank. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK3 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_BASE_UP_ACC_REQ_BK3_ACCSS_REQ \ + 0x00000001 // Base Processor will set when + // Sram access is needed in Spin + // Lock mode. Not used in handshake + // mode. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK3 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_UP_ACC_REQ_BK3_ACCSS_REQ \ + 0x00000001 // Stack Processor will set when + // Sram access is needed in Spin + // Lock mode. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_RDSM_CFG_CPU register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_PULSE_WIDTH_M \ + 0x000000C0 // Bank Clock Hi Time 00 : HCLK + // pulse 01 : 1 cycle of HCLK 10 : + // 1.5 cycles of HCLK 11 : 2 cycles + // of HCLK + +#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_PULSE_WIDTH_S 6 +#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_SENSE \ + 0x00000020 // FLCLK 0 : indicates flash clock + // rise aligns on HCLK rise 1 : + // indicates flash clock rise aligns + // on HCLK fall + +#define STACK_DIE_CTRL_RDSM_CFG_CPU_PIPELINE_FLDATA \ + 0x00000010 // 0 : Always register flash rdata + // before sending to CPU 1 : Drive + // Flash rdata directly out on MISS + // (Both ICODE / DCODE) + +#define STACK_DIE_CTRL_RDSM_CFG_CPU_READ_WAIT_STATE_M \ + 0x0000000F // Number of wait states inserted + +#define STACK_DIE_CTRL_RDSM_CFG_CPU_READ_WAIT_STATE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_RDSM_CFG_EE register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_PULSE_WIDTH_M \ + 0x000000C0 // Bank Clock Hi Time 00 : HCLK + // pulse 01 : 1 cycle of HCLK 10 : + // 1.5 cycles of HCLK 11 : 2 cycles + // of HCLK + +#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_PULSE_WIDTH_S 6 +#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_SENSE \ + 0x00000020 // FLCLK 0 : indicates flash clock + // rise aligns on HCLK rise 1 : + // indicates flash clock rise aligns + // on HCLK fall + +#define STACK_DIE_CTRL_RDSM_CFG_EE_PIPELINE_FLDATA \ + 0x00000010 // 0 : Always register flash rdata + // before sending to CPU 1 : Drive + // Flash rdata directly out on MISS + // (Both ICODE / DCODE) + +#define STACK_DIE_CTRL_RDSM_CFG_EE_READ_WAIT_STATE_M \ + 0x0000000F // Number of wait states inserted + +#define STACK_DIE_CTRL_RDSM_CFG_EE_READ_WAIT_STATE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_BASE_UP_IRQ_LOG register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK3_REL \ + 0x00000010 // Set when Relinquish Interrupt + // sent to Base processor for Bank3. + +#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK2_RELEASE \ + 0x00000008 // Set when Relinquish Interrupt + // sent to Base processor for Bank2. + +#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK3_GRANT \ + 0x00000004 // Set when Bank3 is granted to + // Base processor. + +#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK2_GRANT \ + 0x00000002 // Set when Bank2 is granted to + // BAse processor. + +#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_INVAL_ACCSS \ + 0x00000001 // Set when there Base processor do + // an Invalid access to Sram. Ex : + // Accessing the bank which is not + // granted for BAse processor. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_UP_IRQ_LOG register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK3_REL \ + 0x00000008 // Set when Relinquish Interrupt + // sent to Stack processor for + // Bank3. + +#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK2_REL \ + 0x00000004 // Set when Relinquish Interrupt + // sent to Stack processor for + // Bank2. + +#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK3_GRANT \ + 0x00000002 // Set when Bank3 is granted to + // Stack processor. + +#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK2_GRANT \ + 0x00000001 // Set when Bank2 is granted to + // Stack processor. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_STK_CLK_EN register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_STK_CLK_EN_SR_CLK \ + 0x00000004 // Enable the clock going to sram. + +#define STACK_DIE_CTRL_STK_CLK_EN_DFT_CTRL_CLK \ + 0x00000002 // Enable the clock going to dft + // control block + +#define STACK_DIE_CTRL_STK_CLK_EN_STK_UP_CLK \ + 0x00000001 // Enable the clock going to Cm3 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_SPIN_LOCK_MODE register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_SPIN_LOCK_MODE_MODE \ + 0x00000001 // 0 : Handshake Mode 1 : Spinlock + // mode. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_BUS_FAULT_ADDR register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_BUS_FAULT_ADDR_ADDRESS_M \ + 0xFFFFFFFF // Fault Address + +#define STACK_DIE_CTRL_BUS_FAULT_ADDR_ADDRESS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_BUS_FAULT_CLR register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_BUS_FAULT_CLR_CLEAR \ + 0x00000001 // When set it'll clear the bust + // fault address register to store + // the new bus fault address + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_RESET_CAUSE register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_RESET_CAUSE_RST_CAUSE_M \ + 0xFFFFFFFF + +#define STACK_DIE_CTRL_RESET_CAUSE_RST_CAUSE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_WDOG_TIMER_EVENT register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_WDOG_TIMER_EVENT_WDOG_TMR_EVNT_M \ + 0xFFFFFFFF + +#define STACK_DIE_CTRL_WDOG_TIMER_EVENT_WDOG_TMR_EVNT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_DMA_REQ register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_DMA_REQ_DMAREQ1 \ + 0x00000002 // Generate DMAREQ1 on setting this + // bit. + +#define STACK_DIE_CTRL_DMA_REQ_DMAREQ0 \ + 0x00000001 // Generate DMAREQ0 on setting this + // bit. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_SRAM_JUMP_OFFSET_ADDR register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_SRAM_JUMP_OFFSET_ADDR_ADDR_M \ + 0xFFFFFFFF + +#define STACK_DIE_CTRL_SRAM_JUMP_OFFSET_ADDR_ADDR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_SW_REG1 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_SW_REG1_NEWBITFIELD1_M \ + 0xFFFFFFFF + +#define STACK_DIE_CTRL_SW_REG1_NEWBITFIELD1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_SW_REG2 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_SW_REG2_NEWBITFIELD1_M \ + 0xFFFFFFFF + +#define STACK_DIE_CTRL_SW_REG2_NEWBITFIELD1_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_FMC_SLEEP_CTL register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_FMC_SLEEP_CTL_FMC_LPM_ACK \ + 0x00000002 // captures the status of of + // fmc_lpm_ack + +#define STACK_DIE_CTRL_FMC_SLEEP_CTL_FMC_LPM_REQ \ + 0x00000001 // When set assert + // iflpe2fmc_lpm_req to FMC. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_MISC_CTL register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_MISC_CTL_WDOG_RESET \ + 0x00000080 // 1 : will reset the async wdog + // timer runing on piosc clock + +#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ2 \ + 0x00000020 // Setting this Will send to + // interttupt to CM3 + +#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ1 \ + 0x00000010 // Setting this Will send to + // interttupt to CM3 + +#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ0 \ + 0x00000008 // Setting this Will send to + // interttupt to CM3 + +#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK3 \ + 0x00000004 // While testing Flash Setting this + // bit will Control the + // CE/STR/AIN/CLKIN going to flash + // banks 12 and 3. 0 : Control + // signals coming from FMC for Bank + // 3 goes to Bank3 1 : Control + // signals coming from FMC for Bank + // 0 goes to Bank2 + +#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK2 \ + 0x00000002 // While testing Flash Setting this + // bit will Control the + // CE/STR/AIN/CLKIN going to flash + // banks 12 and 3. 0 : Control + // signals coming from FMC for Bank + // 2 goes to Bank2 1 : Control + // signals coming from FMC for Bank + // 0 goes to Bank2 + +#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK1 \ + 0x00000001 // While testing Flash Setting this + // bit will Control the + // CE/STR/AIN/CLKIN going to flash + // banks 12 and 3. 0 : Control + // signals coming from FMC for Bank + // 1 goes to Bank1 1 : Control + // signals coming from FMC for Bank + // 0 goes to Bank1 + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_SW_DFT_CTL register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_SW_DFT_CTL_FL_CTRL_OWNS \ + 0x20000000 // when set to '1' all flash + // control signals switch over to + // CM3 control when '0' it is under + // the D2D interface control + +#define STACK_DIE_CTRL_SW_DFT_CTL_SWIF_CPU_READ \ + 0x10000000 // 1 indicates in SWIF mode the + // control signals to flash are from + // FMC CPU read controls the clock + // and address. that is one can give + // address via FMC and read through + // IDMEM. + +#define STACK_DIE_CTRL_SW_DFT_CTL_CPU_DONE \ + 0x00800000 // 'CPU Done' bit for PBIST. Write + // '1' to indicate test done. + +#define STACK_DIE_CTRL_SW_DFT_CTL_CPU_FAIL \ + 0x00400000 // 'CPU Fail' bit for PBIST. Write + // '1' to indicate test failed. + +#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK4_OWNS \ + 0x00001000 // when set to '1' flash bank 4 + // (EEPROM) is owned by the CM3for + // reads over DCODE bus. When '0' + // access control given to D2D + // interface. + +#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK3_OWNS \ + 0x00000800 // when set to '1' flash bank 3 is + // owned by the CM3for reads over + // DCODE bus. When '0' access + // control given to D2D interface. + +#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK2_OWNS \ + 0x00000400 // when set to '1' flash bank 2 is + // owned by the CM3for reads over + // DCODE bus. When '0' access + // control given to D2D interface. + +#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK1_OWNS \ + 0x00000200 // when set to '1' flash bank 1 is + // owned by the CM3for reads over + // DCODE bus. When '0' access + // control given to D2D interface. + +#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK0_OWNS \ + 0x00000100 // when set to '1' flash bank 0 is + // owned by the CM3 for reads over + // DCODE bus. When '0' access + // control given to D2D interface. + +//****************************************************************************** +// +// The following are defines for the bit fields in the +// STACK_DIE_CTRL_O_PADN_CTL_0 register. +// +//****************************************************************************** +#define STACK_DIE_CTRL_PADN_CTL_0_SPARE_PAD_DOUT \ + 0x00000008 // This bit is valid for only the + // spare pads ie for n=57 to 59. + // value to drive at the output of + // the pad + +#define STACK_DIE_CTRL_PADN_CTL_0_SPARE_PAD_DIN \ + 0x00000004 // This bit is valid for only the + // spare pads ie for n=57 to 59. + // captures the 'Y' pin of the pad + // which is the data being driven + // into the die + +#define STACK_DIE_CTRL_PADN_CTL_0_OEN2X \ + 0x00000002 // OEN2X control when '1' enables + // the output with 1x. Total drive + // strength is decided bu oen1x + // setting + oen2x setting. + +#define STACK_DIE_CTRL_PADN_CTL_0_OEN1X \ + 0x00000001 // OEN1X control when '1' enables + // the output with 1x . Total drive + // strength is decided bu oen1x + // setting + oen2x setting. + + + + +#endif // __HW_STACK_DIE_CTRL_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_timer.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_timer.h new file mode 100644 index 00000000..b6844ec6 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_timer.h @@ -0,0 +1,778 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +//***************************************************************************** +// +// hw_timer.h - Defines and macros used when accessing the timer. +// +//***************************************************************************** + +//##### INTERNAL BEGIN ##### +// +// This is an auto-generated file. Do not edit by hand. +// Created by version 6779 of DriverLib. +// +//##### INTERNAL END ##### + +#ifndef __HW_TIMER_H__ +#define __HW_TIMER_H__ + +//***************************************************************************** +// +// The following are defines for the Timer register offsets. +// +//***************************************************************************** +#define TIMER_O_CFG 0x00000000 // GPTM Configuration +#define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode +#define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode +#define TIMER_O_CTL 0x0000000C // GPTM Control +//##### GARNET BEGIN ##### +#define TIMER_O_SYNC 0x00000010 // GPTM Synchronize +//##### GARNET END ##### +#define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask +#define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status +#define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status +#define TIMER_O_ICR 0x00000024 // GPTM Interrupt Clear +#define TIMER_O_TAILR 0x00000028 // GPTM Timer A Interval Load +#define TIMER_O_TBILR 0x0000002C // GPTM Timer B Interval Load +#define TIMER_O_TAMATCHR 0x00000030 // GPTM Timer A Match +#define TIMER_O_TBMATCHR 0x00000034 // GPTM Timer B Match +#define TIMER_O_TAPR 0x00000038 // GPTM Timer A Prescale +#define TIMER_O_TBPR 0x0000003C // GPTM Timer B Prescale +#define TIMER_O_TAPMR 0x00000040 // GPTM TimerA Prescale Match +#define TIMER_O_TBPMR 0x00000044 // GPTM TimerB Prescale Match +#define TIMER_O_TAR 0x00000048 // GPTM Timer A +#define TIMER_O_TBR 0x0000004C // GPTM Timer B +#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value +#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value +#define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide +#define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot +#define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot +#define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value +#define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value +#define TIMER_O_DMAEV 0x0000006C // GPTM DMA Event +#define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties + + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CFG register. +// +//***************************************************************************** +#define TIMER_CFG_M 0x00000007 // GPTM Configuration +#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration +#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC) + // counter configuration +#define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration. The + // function is controlled by bits + // 1:0 of GPTMTAMR and GPTMTBMR + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy + // Operation +#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register + // Update +#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt + // Enable +#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write +//##### GARNET END ##### +#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode +#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger +#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt + // Enable +#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction +#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode + // Select +#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode +#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode +#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode +#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode +#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy + // Operation +#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register + // Update +#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt + // Enable +#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write +//##### GARNET END ##### +#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode +#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger +#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt + // Enable +#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction +#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode + // Select +#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode +#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode +#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode +#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode +#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_CTL register. +// +//***************************************************************************** +#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level +#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger + // Enable +#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode +#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge +#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge +#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges +#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable +#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable +#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level +#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger + // Enable +#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Enable +#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode +#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge +#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge +#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges +#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable +#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable +//##### GARNET BEGIN ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_SYNC register. +// +//***************************************************************************** +#define TIMER_SYNC_SYNC11_M 0x00C00000 // Synchronize GPTM Timer 11 +#define TIMER_SYNC_SYNC11_TA 0x00400000 // A timeout event for Timer A of + // GPTM11 is triggered +#define TIMER_SYNC_SYNC11_TB 0x00800000 // A timeout event for Timer B of + // GPTM11 is triggered +#define TIMER_SYNC_SYNC11_TATB 0x00C00000 // A timeout event for both Timer A + // and Timer B of GPTM11 is + // triggered +#define TIMER_SYNC_SYNC10_M 0x00300000 // Synchronize GPTM Timer 10 +#define TIMER_SYNC_SYNC10_TA 0x00100000 // A timeout event for Timer A of + // GPTM10 is triggered +#define TIMER_SYNC_SYNC10_TB 0x00200000 // A timeout event for Timer B of + // GPTM10 is triggered +#define TIMER_SYNC_SYNC10_TATB 0x00300000 // A timeout event for both Timer A + // and Timer B of GPTM10 is + // triggered +#define TIMER_SYNC_SYNC9_M 0x000C0000 // Synchronize GPTM Timer 9 +#define TIMER_SYNC_SYNC9_TA 0x00040000 // A timeout event for Timer A of + // GPTM9 is triggered +#define TIMER_SYNC_SYNC9_TB 0x00080000 // A timeout event for Timer B of + // GPTM9 is triggered +#define TIMER_SYNC_SYNC9_TATB 0x000C0000 // A timeout event for both Timer A + // and Timer B of GPTM9 is + // triggered +#define TIMER_SYNC_SYNC8_M 0x00030000 // Synchronize GPTM Timer 8 +#define TIMER_SYNC_SYNC8_TA 0x00010000 // A timeout event for Timer A of + // GPTM8 is triggered +#define TIMER_SYNC_SYNC8_TB 0x00020000 // A timeout event for Timer B of + // GPTM8 is triggered +#define TIMER_SYNC_SYNC8_TATB 0x00030000 // A timeout event for both Timer A + // and Timer B of GPTM8 is + // triggered +#define TIMER_SYNC_SYNC7_M 0x0000C000 // Synchronize GPTM Timer 7 +#define TIMER_SYNC_SYNC7_TA 0x00004000 // A timeout event for Timer A of + // GPTM7 is triggered +#define TIMER_SYNC_SYNC7_TB 0x00008000 // A timeout event for Timer B of + // GPTM7 is triggered +#define TIMER_SYNC_SYNC7_TATB 0x0000C000 // A timeout event for both Timer A + // and Timer B of GPTM7 is + // triggered +#define TIMER_SYNC_SYNC6_M 0x00003000 // Synchronize GPTM Timer 6 +#define TIMER_SYNC_SYNC6_TA 0x00001000 // A timeout event for Timer A of + // GPTM6 is triggered +#define TIMER_SYNC_SYNC6_TB 0x00002000 // A timeout event for Timer B of + // GPTM6 is triggered +#define TIMER_SYNC_SYNC6_TATB 0x00003000 // A timeout event for both Timer A + // and Timer B of GPTM6 is + // triggered +#define TIMER_SYNC_SYNC5_M 0x00000C00 // Synchronize GPTM Timer 5 +#define TIMER_SYNC_SYNC5_TA 0x00000400 // A timeout event for Timer A of + // GPTM5 is triggered +#define TIMER_SYNC_SYNC5_TB 0x00000800 // A timeout event for Timer B of + // GPTM5 is triggered +#define TIMER_SYNC_SYNC5_TATB 0x00000C00 // A timeout event for both Timer A + // and Timer B of GPTM5 is + // triggered +#define TIMER_SYNC_SYNC4_M 0x00000300 // Synchronize GPTM Timer 4 +#define TIMER_SYNC_SYNC4_TA 0x00000100 // A timeout event for Timer A of + // GPTM4 is triggered +#define TIMER_SYNC_SYNC4_TB 0x00000200 // A timeout event for Timer B of + // GPTM4 is triggered +#define TIMER_SYNC_SYNC4_TATB 0x00000300 // A timeout event for both Timer A + // and Timer B of GPTM4 is + // triggered +#define TIMER_SYNC_SYNC3_M 0x000000C0 // Synchronize GPTM Timer 3 +#define TIMER_SYNC_SYNC3_TA 0x00000040 // A timeout event for Timer A of + // GPTM3 is triggered +#define TIMER_SYNC_SYNC3_TB 0x00000080 // A timeout event for Timer B of + // GPTM3 is triggered +#define TIMER_SYNC_SYNC3_TATB 0x000000C0 // A timeout event for both Timer A + // and Timer B of GPTM3 is + // triggered +#define TIMER_SYNC_SYNC2_M 0x00000030 // Synchronize GPTM Timer 2 +#define TIMER_SYNC_SYNC2_TA 0x00000010 // A timeout event for Timer A of + // GPTM2 is triggered +#define TIMER_SYNC_SYNC2_TB 0x00000020 // A timeout event for Timer B of + // GPTM2 is triggered +#define TIMER_SYNC_SYNC2_TATB 0x00000030 // A timeout event for both Timer A + // and Timer B of GPTM2 is + // triggered +#define TIMER_SYNC_SYNC1_M 0x0000000C // Synchronize GPTM Timer 1 +#define TIMER_SYNC_SYNC1_TA 0x00000004 // A timeout event for Timer A of + // GPTM1 is triggered +#define TIMER_SYNC_SYNC1_TB 0x00000008 // A timeout event for Timer B of + // GPTM1 is triggered +#define TIMER_SYNC_SYNC1_TATB 0x0000000C // A timeout event for both Timer A + // and Timer B of GPTM1 is + // triggered +#define TIMER_SYNC_SYNC0_M 0x00000003 // Synchronize GPTM Timer 0 +#define TIMER_SYNC_SYNC0_TA 0x00000001 // A timeout event for Timer A of + // GPTM0 is triggered +#define TIMER_SYNC_SYNC0_TB 0x00000002 // A timeout event for Timer B of + // GPTM0 is triggered +#define TIMER_SYNC_SYNC0_TATB 0x00000003 // A timeout event for both Timer A + // and Timer B of GPTM0 is + // triggered +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_IMR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_IMR_WUEIM 0x00010000 // 32/64-Bit GPTM Write Update + // Error Interrupt Mask +//##### GARNET END ##### +#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Mode Match + // Interrupt Mask +#define TIMER_IMR_CBEIM 0x00000400 // GPTM Capture B Event Interrupt + // Mask +#define TIMER_IMR_CBMIM 0x00000200 // GPTM Capture B Match Interrupt + // Mask +#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt + // Mask +#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Mode Match + // Interrupt Mask +#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask +#define TIMER_IMR_CAEIM 0x00000004 // GPTM Capture A Event Interrupt + // Mask +#define TIMER_IMR_CAMIM 0x00000002 // GPTM Capture A Match Interrupt + // Mask +#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt + // Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_RIS register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_RIS_WUERIS 0x00010000 // 32/64-Bit GPTM Write Update + // Error Raw Interrupt Status +//##### GARNET END ##### +#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Mode Match Raw + // Interrupt +#define TIMER_RIS_CBERIS 0x00000400 // GPTM Capture B Event Raw + // Interrupt +#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Capture B Match Raw + // Interrupt +#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw + // Interrupt +#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Mode Match Raw + // Interrupt +#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt +#define TIMER_RIS_CAERIS 0x00000004 // GPTM Capture A Event Raw + // Interrupt +#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Capture A Match Raw + // Interrupt +#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_MIS register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_MIS_WUEMIS 0x00010000 // 32/64-Bit GPTM Write Update + // Error Masked Interrupt Status +//##### GARNET END ##### +#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Mode Match Masked + // Interrupt +#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Capture B Event Masked + // Interrupt +#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Capture B Match Masked + // Interrupt +#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked + // Interrupt +#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Mode Match Masked + // Interrupt +#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt +#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Capture A Event Masked + // Interrupt +#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Capture A Match Masked + // Interrupt +#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_ICR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit GPTM Write Update + // Error Interrupt Clear +//##### GARNET END ##### +#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Mode Match + // Interrupt Clear +#define TIMER_ICR_CBECINT 0x00000400 // GPTM Capture B Event Interrupt + // Clear +#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Capture B Match Interrupt + // Clear +#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt + // Clear +#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Mode Match + // Interrupt Clear +#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear +#define TIMER_ICR_CAECINT 0x00000004 // GPTM Capture A Event Interrupt + // Clear +#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Capture A Match Interrupt + // Clear +#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw + // Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAILR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load + // Register +//##### GARNET END ##### +#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM Timer A Interval Load + // Register High +#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM Timer A Interval Load + // Register Low +#define TIMER_TAILR_TAILRH_S 16 +#define TIMER_TAILR_TAILRL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TAILR_S 0 +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBILR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load + // Register +//##### GARNET END ##### +#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM Timer B Interval Load + // Register +#define TIMER_TBILR_TBILRL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TBILR_S 0 +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAMATCHR +// register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register +//##### GARNET END ##### +#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM Timer A Match Register High +#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM Timer A Match Register Low +#define TIMER_TAMATCHR_TAMRH_S 16 +#define TIMER_TAMATCHR_TAMRL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TAMATCHR_TAMR_S 0 +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBMATCHR +// register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register +//##### GARNET END ##### +#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM Timer B Match Register Low +//##### GARNET BEGIN ##### +#define TIMER_TBMATCHR_TBMR_S 0 +//##### GARNET END ##### +#define TIMER_TBMATCHR_TBMRL_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte +//##### GARNET END ##### +#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale +//##### GARNET BEGIN ##### +#define TIMER_TAPR_TAPSRH_S 8 +//##### GARNET END ##### +#define TIMER_TAPR_TAPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte +//##### GARNET END ##### +#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale +//##### GARNET BEGIN ##### +#define TIMER_TBPR_TBPSRH_S 8 +//##### GARNET END ##### +#define TIMER_TBPR_TBPSR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPMR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High + // Byte +//##### GARNET END ##### +#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match +//##### GARNET BEGIN ##### +#define TIMER_TAPMR_TAPSMRH_S 8 +//##### GARNET END ##### +#define TIMER_TAPMR_TAPSMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPMR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High + // Byte +//##### GARNET END ##### +#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match +//##### GARNET BEGIN ##### +#define TIMER_TBPMR_TBPSMRH_S 8 +//##### GARNET END ##### +#define TIMER_TBPMR_TBPSMR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register +//##### GARNET END ##### +#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM Timer A Register High +#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM Timer A Register Low +#define TIMER_TAR_TARH_S 16 +#define TIMER_TAR_TARL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TAR_S 0 +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBR register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register +//##### GARNET END ##### +#define TIMER_TBR_TBRL_M 0x00FFFFFF // GPTM Timer B +#define TIMER_TBR_TBRL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TBR_S 0 +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAV register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value +//##### GARNET END ##### +#define TIMER_TAV_TAVH_M 0xFFFF0000 // GPTM Timer A Value High +#define TIMER_TAV_TAVL_M 0x0000FFFF // GPTM Timer A Register Low +#define TIMER_TAV_TAVH_S 16 +#define TIMER_TAV_TAVL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TAV_S 0 +//##### GARNET END ##### + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBV register. +// +//***************************************************************************** +//##### GARNET BEGIN ##### +#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value +//##### GARNET END ##### +#define TIMER_TBV_TBVL_M 0x0000FFFF // GPTM Timer B Register +#define TIMER_TBV_TBVL_S 0 +//##### GARNET BEGIN ##### +#define TIMER_TBV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_RTCPD register. +// +//***************************************************************************** +#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value +#define TIMER_RTCPD_RTCPD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPS register. +// +//***************************************************************************** +#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot +#define TIMER_TAPS_PSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPS register. +// +//***************************************************************************** +#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value +#define TIMER_TBPS_PSS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TAPV register. +// +//***************************************************************************** +#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value +#define TIMER_TAPV_PSV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_TBPV register. +// +//***************************************************************************** +#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value +#define TIMER_TBPV_PSV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the TIMER_O_PP register. +// +//***************************************************************************** +#define TIMER_PP_SYNCCNT 0x00000020 // Synchronize Start +#define TIMER_PP_CHAIN 0x00000010 // Chain with Other Timers +#define TIMER_PP_SIZE_M 0x0000000F // Count Size +#define TIMER_PP_SIZE__0 0x00000000 // Timer A and Timer B counters are + // 16 bits each with an 8-bit + // prescale counter +#define TIMER_PP_SIZE__1 0x00000001 // Timer A and Timer B counters are + // 32 bits each with an 16-bit + // prescale counter +//##### GARNET END ##### + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_CFG +// register. +// +//***************************************************************************** +#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_CTL +// register. +// +//***************************************************************************** +#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask +#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_RIS +// register. +// +//***************************************************************************** +#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status +#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status +#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat +#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status +#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status +#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status +#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_TAILR +// register. +// +//***************************************************************************** +#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode +#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_TBILR +// register. +// +//***************************************************************************** +#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// TIMER_O_TAMATCHR register. +// +//***************************************************************************** +#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode +#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// TIMER_O_TBMATCHR register. +// +//***************************************************************************** +#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_TAR +// register. +// +//***************************************************************************** +#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode +#define TIMER_TAR_TARL 0x0000FFFF // TimerA value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_O_TBR +// register. +// +//***************************************************************************** +#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value + +//***************************************************************************** +// +// The following are deprecated defines for the reset values of the timer +// registers. +// +//***************************************************************************** +#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV +#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV +#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV +#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV +#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV +#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV +#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV +#define TIMER_RV_CFG 0x00000000 // Configuration register RV +#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV +#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV +#define TIMER_RV_CTL 0x00000000 // Control register RV +#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV +#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV +#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV +#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV +#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV +#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV +#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TnMR +// register. +// +//***************************************************************************** +#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select +#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time +#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask +#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot +#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic +#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TnPR +// register. +// +//***************************************************************************** +#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the TIMER_TnPMR +// register. +// +//***************************************************************************** +#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value + +#endif + +#endif // __HW_TIMER_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_types.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_types.h new file mode 100644 index 00000000..d7a6ab4f --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_types.h @@ -0,0 +1,76 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_TYPES_H__ +#define __HW_TYPES_H__ + +//***************************************************************************** +// +// Define a boolean type, and values for true and false. +// +//***************************************************************************** +typedef unsigned char tBoolean; + +#ifndef true +#define true 1 +#endif + +#ifndef false +#define false 0 +#endif + +//***************************************************************************** +// +// Macros for hardware access, both direct and via the bit-band region. +// +//***************************************************************************** +#define HWREG(x) \ + (*((volatile unsigned long *)(x))) +#define HWREGH(x) \ + (*((volatile unsigned short *)(x))) +#define HWREGB(x) \ + (*((volatile unsigned char *)(x))) +#define HWREGBITW(x, b) \ + HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITH(x, b) \ + HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) +#define HWREGBITB(x, b) \ + HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ + (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) + + +#endif // __HW_TYPES_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_uart.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_uart.h new file mode 100644 index 00000000..ae50ac38 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_uart.h @@ -0,0 +1,417 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_UART_H__ +#define __HW_UART_H__ + +//***************************************************************************** +// +// The following are defines for the UART register offsets. +// +//***************************************************************************** +#define UART_O_DR 0x00000000 +#define UART_O_RSR 0x00000004 +#define UART_O_ECR 0x00000004 +#define UART_O_FR 0x00000018 +#define UART_O_ILPR 0x00000020 +#define UART_O_IBRD 0x00000024 +#define UART_O_FBRD 0x00000028 +#define UART_O_LCRH 0x0000002C +#define UART_O_CTL 0x00000030 +#define UART_O_IFLS 0x00000034 +#define UART_O_IM 0x00000038 +#define UART_O_RIS 0x0000003C +#define UART_O_MIS 0x00000040 +#define UART_O_ICR 0x00000044 +#define UART_O_DMACTL 0x00000048 +#define UART_O_LCTL 0x00000090 +#define UART_O_LSS 0x00000094 +#define UART_O_LTIM 0x00000098 +#define UART_O_9BITADDR 0x000000A4 +#define UART_O_9BITAMASK 0x000000A8 +#define UART_O_PP 0x00000FC0 +#define UART_O_CC 0x00000FC8 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DR register. +// +//****************************************************************************** +#define UART_DR_OE 0x00000800 // UART Overrun Error +#define UART_DR_BE 0x00000400 // UART Break Error +#define UART_DR_PE 0x00000200 // UART Parity Error +#define UART_DR_FE 0x00000100 // UART Framing Error +#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received +#define UART_DR_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_RSR register. +// +//****************************************************************************** +#define UART_RSR_OE 0x00000008 // UART Overrun Error +#define UART_RSR_BE 0x00000004 // UART Break Error +#define UART_RSR_PE 0x00000002 // UART Parity Error +#define UART_RSR_FE 0x00000001 // UART Framing Error +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ECR register. +// +//****************************************************************************** +#define UART_ECR_DATA_M 0x000000FF // Error Clear +#define UART_ECR_DATA_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_FR register. +// +//****************************************************************************** +#define UART_FR_RI 0x00000100 // Ring Indicator +#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty +#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full +#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full +#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty +#define UART_FR_BUSY 0x00000008 // UART Busy +#define UART_FR_DCD 0x00000004 // Data Carrier Detect +#define UART_FR_DSR 0x00000002 // Data Set Ready +#define UART_FR_CTS 0x00000001 // Clear To Send +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ILPR register. +// +//****************************************************************************** +#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor +#define UART_ILPR_ILPDVSR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IBRD register. +// +//****************************************************************************** +#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor +#define UART_IBRD_DIVINT_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_FBRD register. +// +//****************************************************************************** +#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor +#define UART_FBRD_DIVFRAC_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LCRH register. +// +//****************************************************************************** +#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select +#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length 0x00000000 : + // UART_LCRH_WLEN_5 : 5 bits + // (default) 0x00000020 : + // UART_LCRH_WLEN_6 : 6 bits + // 0x00000040 : UART_LCRH_WLEN_7 : 7 + // bits 0x00000060 : + // UART_LCRH_WLEN_8 : 8 bits +#define UART_LCRH_WLEN_S 5 +#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs +#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select +#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select +#define UART_LCRH_PEN 0x00000002 // UART Parity Enable +#define UART_LCRH_BRK 0x00000001 // UART Send Break +#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length +#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) +#define UART_LCRH_WLEN_6 0x00000020 // 6 bits +#define UART_LCRH_WLEN_7 0x00000040 // 7 bits +#define UART_LCRH_WLEN_8 0x00000060 // 8 bits +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_CTL register. +// +//****************************************************************************** +#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send +#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send +#define UART_CTL_RI 0x00002000 // Ring Indicator +#define UART_CTL_DCD 0x00001000 // Data Carrier Detect +#define UART_CTL_RTS 0x00000800 // Request to Send +#define UART_CTL_DTR 0x00000400 // Data Terminal Ready +#define UART_CTL_RXE 0x00000200 // UART Receive Enable +#define UART_CTL_TXE 0x00000100 // UART Transmit Enable +#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable +#define UART_CTL_LIN 0x00000040 // LIN Mode Enable +#define UART_CTL_HSE 0x00000020 // High-Speed Enable +#define UART_CTL_EOT 0x00000010 // End of Transmission +#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support +#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode +#define UART_CTL_SIREN 0x00000002 // UART SIR Enable +#define UART_CTL_UARTEN 0x00000001 // UART Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IFLS register. +// +//****************************************************************************** +#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO + // Level Select +#define UART_IFLS_RX_S 3 +#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO + // Level Select +#define UART_IFLS_TX_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_IM register. +// +//****************************************************************************** +#define UART_IM_DMATXIM 0x00020000 // Transmit DMA Interrupt Mask +#define UART_IM_DMARXIM 0x00010000 // Receive DMA Interrupt Mask +#define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask +#define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask +#define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt + // Mask +#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask +#define UART_IM_EOTIM 0x00000800 // End of Transmission Interrupt + // Mask +#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt + // Mask +#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask +#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask +#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt + // Mask +#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt + // Mask +#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask +#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask +#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem + // Interrupt Mask +#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem + // Interrupt Mask +#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem + // Interrupt Mask +#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem + // Interrupt Mask +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_RIS register. +// +//****************************************************************************** +#define UART_RIS_DMATXRIS 0x00020000 // Transmit DMA Raw Interrupt + // Status +#define UART_RIS_DMARXRIS 0x00010000 // Receive DMA Raw Interrupt Status +#define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt + // Status +#define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt + // Status +#define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw + // Interrupt Status +#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status +#define UART_RIS_EOTRIS 0x00000800 // End of Transmission Raw + // Interrupt Status +#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt + // Status +#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt + // Status +#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt + // Status +#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt + // Status +#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw + // Interrupt Status +#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt + // Status +#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt + // Status +#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw + // Interrupt Status +#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem + // Raw Interrupt Status +#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw + // Interrupt Status +#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw + // Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_MIS register. +// +//****************************************************************************** +#define UART_MIS_DMATXMIS 0x00020000 // Transmit DMA Masked Interrupt + // Status +#define UART_MIS_DMARXMIS 0x00010000 // Receive DMA Masked Interrupt + // Status +#define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt + // Status +#define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt + // Status +#define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked + // Interrupt Status +#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt + // Status +#define UART_MIS_EOTMIS 0x00000800 // End of Transmission Masked + // Interrupt Status +#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked + // Interrupt Status +#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked + // Interrupt Status +#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked + // Interrupt Status +#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked + // Interrupt Status +#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked + // Interrupt Status +#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt + // Status +#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt + // Status +#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked + // Interrupt Status +#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem + // Masked Interrupt Status +#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked + // Interrupt Status +#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked + // Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_ICR register. +// +//****************************************************************************** +#define UART_ICR_DMATXIC 0x00020000 // Transmit DMA Interrupt Clear +#define UART_ICR_DMARXIC 0x00010000 // Receive DMA Interrupt Clear +#define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear +#define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear +#define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt + // Clear +#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear +#define UART_ICR_EOTIC 0x00000800 // End of Transmission Interrupt + // Clear +#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear +#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear +#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear +#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear +#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear +#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear +#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear +#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem + // Interrupt Clear +#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem + // Interrupt Clear +#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem + // Interrupt Clear +#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem + // Interrupt Clear +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_DMACTL register. +// +//****************************************************************************** +#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error +#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable +#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LCTL register. +// +//****************************************************************************** +#define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length 0x00000000 : + // UART_LCTL_BLEN_13T : Sync break + // length is 13T bits (default) + // 0x00000010 : UART_LCTL_BLEN_14T : + // Sync break length is 14T bits + // 0x00000020 : UART_LCTL_BLEN_15T : + // Sync break length is 15T bits + // 0x00000030 : UART_LCTL_BLEN_16T : + // Sync break length is 16T bits +#define UART_LCTL_BLEN_S 4 +#define UART_LCTL_MASTER 0x00000001 // LIN Master Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LSS register. +// +//****************************************************************************** +#define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot +#define UART_LSS_TSS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_LTIM register. +// +//****************************************************************************** +#define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value +#define UART_LTIM_TIMER_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// UART_O_9BITADDR register. +// +//****************************************************************************** +#define UART_9BITADDR_9BITEN \ + 0x00008000 // Enable 9-Bit Mode + +#define UART_9BITADDR_ADDR_M \ + 0x000000FF // Self Address for 9-Bit Mode + +#define UART_9BITADDR_ADDR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// UART_O_9BITAMASK register. +// +//****************************************************************************** +#define UART_9BITAMASK_RANGE_M \ + 0x0000FF00 // Self Address Range for 9-Bit + // Mode + +#define UART_9BITAMASK_RANGE_S 8 +#define UART_9BITAMASK_MASK_M \ + 0x000000FF // Self Address Mask for 9-Bit Mode + +#define UART_9BITAMASK_MASK_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_PP register. +// +//****************************************************************************** +#define UART_PP_MSE 0x00000008 // Modem Support Extended +#define UART_PP_MS 0x00000004 // Modem Support +#define UART_PP_NB 0x00000002 // 9-Bit Support +#define UART_PP_SC 0x00000001 // Smart Card Support +//****************************************************************************** +// +// The following are defines for the bit fields in the UART_O_CC register. +// +//****************************************************************************** +#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source + // 0x00000005 : UART_CC_CS_PIOSC : + // PIOSC 0x00000000 : + // UART_CC_CS_SYSCLK : The system + // clock (default) +#define UART_CC_CS_S 0 + + + +#endif // __HW_UART_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_udma.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_udma.h new file mode 100644 index 00000000..9a495bae --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_udma.h @@ -0,0 +1,336 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_UDMA_H__ +#define __HW_UDMA_H__ + +//***************************************************************************** +// +// The following are defines for the UDMA register offsets. +// +//***************************************************************************** +#define UDMA_O_STAT 0x00000000 +#define UDMA_O_CFG 0x00000004 +#define UDMA_O_CTLBASE 0x00000008 +#define UDMA_O_ALTBASE 0x0000000C +#define UDMA_O_WAITSTAT 0x00000010 +#define UDMA_O_SWREQ 0x00000014 +#define UDMA_O_USEBURSTSET 0x00000018 +#define UDMA_O_USEBURSTCLR 0x0000001C +#define UDMA_O_REQMASKSET 0x00000020 +#define UDMA_O_REQMASKCLR 0x00000024 +#define UDMA_O_ENASET 0x00000028 +#define UDMA_O_ENACLR 0x0000002C +#define UDMA_O_ALTSET 0x00000030 +#define UDMA_O_ALTCLR 0x00000034 +#define UDMA_O_PRIOSET 0x00000038 +#define UDMA_O_PRIOCLR 0x0000003C +#define UDMA_O_ERRCLR 0x0000004C +#define UDMA_O_CHASGN 0x00000500 +#define UDMA_O_CHIS 0x00000504 +#define UDMA_O_CHMAP0 0x00000510 +#define UDMA_O_CHMAP1 0x00000514 +#define UDMA_O_CHMAP2 0x00000518 +#define UDMA_O_CHMAP3 0x0000051C +#define UDMA_O_PV 0x00000FB0 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_STAT register. +// +//****************************************************************************** +#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1 +#define UDMA_STAT_DMACHANS_S 16 +#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status + // 0x00000090 : UDMA_STAT_STATE_DONE + // : Done 0x00000000 : + // UDMA_STAT_STATE_IDLE : Idle + // 0x00000010 : + // UDMA_STAT_STATE_RD_CTRL : Reading + // channel controller data + // 0x00000030 : + // UDMA_STAT_STATE_RD_DSTENDP : + // Reading destination end pointer + // 0x00000040 : + // UDMA_STAT_STATE_RD_SRCDAT : + // Reading source data 0x00000020 : + // UDMA_STAT_STATE_RD_SRCENDP : + // Reading source end pointer + // 0x00000080 : + // UDMA_STAT_STATE_STALL : Stalled + // 0x000000A0 : + // UDMA_STAT_STATE_UNDEF : Undefined + // 0x00000060 : UDMA_STAT_STATE_WAIT + // : Waiting for uDMA request to + // clear 0x00000070 : + // UDMA_STAT_STATE_WR_CTRL : Writing + // channel controller data + // 0x00000050 : + // UDMA_STAT_STATE_WR_DSTDAT : + // Writing destination data +#define UDMA_STAT_STATE_S 4 +#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CFG register. +// +//****************************************************************************** +#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CTLBASE register. +// +//****************************************************************************** +#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address +#define UDMA_CTLBASE_ADDR_S 10 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_ALTBASE register. +// +//****************************************************************************** +#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address + // Pointer +#define UDMA_ALTBASE_ADDR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_WAITSTAT register. +// +//****************************************************************************** +#define UDMA_WAITSTAT_WAITREQ_M \ + 0xFFFFFFFF // Channel [n] Wait Status + +#define UDMA_WAITSTAT_WAITREQ_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_SWREQ register. +// +//****************************************************************************** +#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request +#define UDMA_SWREQ_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// UDMA_O_USEBURSTSET register. +// +//****************************************************************************** +#define UDMA_USEBURSTSET_SET_M \ + 0xFFFFFFFF // Channel [n] Useburst Set + +#define UDMA_USEBURSTSET_SET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the +// UDMA_O_USEBURSTCLR register. +// +//****************************************************************************** +#define UDMA_USEBURSTCLR_CLR_M \ + 0xFFFFFFFF // Channel [n] Useburst Clear + +#define UDMA_USEBURSTCLR_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_REQMASKSET register. +// +//****************************************************************************** +#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set +#define UDMA_REQMASKSET_SET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_REQMASKCLR register. +// +//****************************************************************************** +#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear +#define UDMA_REQMASKCLR_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_ENASET register. +// +//****************************************************************************** +#define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set +#define UDMA_ENASET_CHENSET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_ENACLR register. +// +//****************************************************************************** +#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear +#define UDMA_ENACLR_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_ALTSET register. +// +//****************************************************************************** +#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set +#define UDMA_ALTSET_SET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_ALTCLR register. +// +//****************************************************************************** +#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear +#define UDMA_ALTCLR_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_PRIOSET register. +// +//****************************************************************************** +#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set +#define UDMA_PRIOSET_SET_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_PRIOCLR register. +// +//****************************************************************************** +#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear +#define UDMA_PRIOCLR_CLR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_ERRCLR register. +// +//****************************************************************************** +#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHASGN register. +// +//****************************************************************************** +#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select +#define UDMA_CHASGN_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHIS register. +// +//****************************************************************************** +#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status +#define UDMA_CHIS_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHMAP0 register. +// +//****************************************************************************** +#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select +#define UDMA_CHMAP0_CH7SEL_S 28 +#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select +#define UDMA_CHMAP0_CH6SEL_S 24 +#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select +#define UDMA_CHMAP0_CH5SEL_S 20 +#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select +#define UDMA_CHMAP0_CH4SEL_S 16 +#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select +#define UDMA_CHMAP0_CH3SEL_S 12 +#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select +#define UDMA_CHMAP0_CH2SEL_S 8 +#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select +#define UDMA_CHMAP0_CH1SEL_S 4 +#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select +#define UDMA_CHMAP0_CH0SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHMAP1 register. +// +//****************************************************************************** +#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select +#define UDMA_CHMAP1_CH15SEL_S 28 +#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select +#define UDMA_CHMAP1_CH14SEL_S 24 +#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select +#define UDMA_CHMAP1_CH13SEL_S 20 +#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select +#define UDMA_CHMAP1_CH12SEL_S 16 +#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select +#define UDMA_CHMAP1_CH11SEL_S 12 +#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select +#define UDMA_CHMAP1_CH10SEL_S 8 +#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select +#define UDMA_CHMAP1_CH9SEL_S 4 +#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select +#define UDMA_CHMAP1_CH8SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHMAP2 register. +// +//****************************************************************************** +#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select +#define UDMA_CHMAP2_CH23SEL_S 28 +#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select +#define UDMA_CHMAP2_CH22SEL_S 24 +#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select +#define UDMA_CHMAP2_CH21SEL_S 20 +#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select +#define UDMA_CHMAP2_CH20SEL_S 16 +#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select +#define UDMA_CHMAP2_CH19SEL_S 12 +#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select +#define UDMA_CHMAP2_CH18SEL_S 8 +#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select +#define UDMA_CHMAP2_CH17SEL_S 4 +#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select +#define UDMA_CHMAP2_CH16SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_CHMAP3 register. +// +//****************************************************************************** +#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select +#define UDMA_CHMAP3_CH31SEL_S 28 +#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select +#define UDMA_CHMAP3_CH30SEL_S 24 +#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select +#define UDMA_CHMAP3_CH29SEL_S 20 +#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select +#define UDMA_CHMAP3_CH28SEL_S 16 +#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select +#define UDMA_CHMAP3_CH27SEL_S 12 +#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select +#define UDMA_CHMAP3_CH26SEL_S 8 +#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select +#define UDMA_CHMAP3_CH25SEL_S 4 +#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select +#define UDMA_CHMAP3_CH24SEL_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the UDMA_O_PV register. +// +//****************************************************************************** +#define UDMA_PV_MAJOR_M 0x0000FF00 // Major Revision +#define UDMA_PV_MAJOR_S 8 +#define UDMA_PV_MINOR_M 0x000000FF // Minor Revision +#define UDMA_PV_MINOR_S 0 + + + +#endif // __HW_UDMA_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_wdt.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_wdt.h new file mode 100644 index 00000000..00b14acb --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CCWare/inc/hw_wdt.h @@ -0,0 +1,131 @@ +//***************************************************************************** +// +// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//***************************************************************************** + +#ifndef __HW_WDT_H__ +#define __HW_WDT_H__ + +//***************************************************************************** +// +// The following are defines for the WDT register offsets. +// +//***************************************************************************** +#define WDT_O_LOAD 0x00000000 +#define WDT_O_VALUE 0x00000004 +#define WDT_O_CTL 0x00000008 +#define WDT_O_ICR 0x0000000C +#define WDT_O_RIS 0x00000010 +#define WDT_O_MIS 0x00000014 +#define WDT_O_TEST 0x00000418 +#define WDT_O_LOCK 0x00000C00 + + + +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOAD register. +// +//****************************************************************************** +#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value +#define WDT_LOAD_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_VALUE register. +// +//****************************************************************************** +#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value +#define WDT_VALUE_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_CTL register. +// +//****************************************************************************** +#define WDT_CTL_WRC 0x80000000 // Write Complete +#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type +#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable. This bit + // is not used in cc3xx, WDOG shall + // always generate RESET to system + // irrespective of this bit setting. +#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_ICR register. +// +//****************************************************************************** +#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear +#define WDT_ICR_S 0 +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_RIS register. +// +//****************************************************************************** +#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_MIS register. +// +//****************************************************************************** +#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_TEST register. +// +//****************************************************************************** +#define WDT_TEST_STALL_EN_M 0x00000C00 // Watchdog stall enable +#define WDT_TEST_STALL_EN_S 10 +#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable +//****************************************************************************** +// +// The following are defines for the bit fields in the WDT_O_LOCK register. +// +//****************************************************************************** +#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock +#define WDT_LOCK_S 0 +#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked +#define WDT_LOCK_LOCKED 0x00000001 // Locked +#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer + +//***************************************************************************** +// +// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and +// WDT_MIS registers. +// +//***************************************************************************** +#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired + + + + + +#endif // __HW_WDT_H__ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CMSIS/TI/TICC3200/cc3200.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CMSIS/TI/TICC3200/cc3200.h new file mode 100644 index 00000000..d9a3c1cc --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/ext/CMSIS/TI/TICC3200/cc3200.h @@ -0,0 +1,118 @@ + + +#ifndef __CC3200_H +#define __CC3200_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +#define __CM4_REV 0x0001U /*!< Core revision r0p1 */ +#define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ +#define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /*!< FPU present */ + +typedef enum +{ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ +/****** STM32 specific Interrupt Numbers **********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ + TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ + RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ + FLASH_IRQn = 4, /*!< FLASH global Interrupt */ + RCC_IRQn = 5, /*!< RCC global Interrupt */ + EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ + EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ + EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ + EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ + EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ + DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ + DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ + DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ + DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ + DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ + DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ + DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ + ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ + CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ + CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ + CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ + TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ + TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ + TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ + TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ + TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ + I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ + I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ + I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ + I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ + SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ + USART1_IRQn = 37, /*!< USART1 global Interrupt */ + USART2_IRQn = 38, /*!< USART2 global Interrupt */ + USART3_IRQn = 39, /*!< USART3 global Interrupt */ + EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ + RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ + OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ + TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ + TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ + TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ + TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ + DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ + FSMC_IRQn = 48, /*!< FSMC global Interrupt */ + SDIO_IRQn = 49, /*!< SDIO global Interrupt */ + TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ + SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ + UART4_IRQn = 52, /*!< UART4 global Interrupt */ + UART5_IRQn = 53, /*!< UART5 global Interrupt */ + TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ + TIM7_IRQn = 55, /*!< TIM7 global interrupt */ + DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ + DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ + DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ + DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ + DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ + ETH_IRQn = 61, /*!< Ethernet global Interrupt */ + ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ + CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ + CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ + CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ + OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ + DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ + DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ + DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ + USART6_IRQn = 71, /*!< USART6 global interrupt */ + I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ + OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ + OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ + OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ + OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ + DCMI_IRQn = 78, /*!< DCMI global interrupt */ + HASH_RNG_IRQn = 80, /*!< Hash and RNG global interrupt */ + FPU_IRQn = 81 /*!< FPU global interrupt */ + +} IRQn_Type; + + +#include "core_cm4.h" + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif // __CC3200_H \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/startup/ARMCMx/devices/TICC3200/cmparams.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/startup/ARMCMx/devices/TICC3200/cmparams.h new file mode 100644 index 00000000..a98242b1 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/common/startup/ARMCMx/devices/TICC3200/cmparams.h @@ -0,0 +1,119 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/** + * @file CC3200/cmparams.h + * @brief ARM Cortex-M4 parameters for the CC3200. + * + * @defgroup ARMCMx_CC3200 CC3200 Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M4 specific parameters for the + * CC3200 platform. + * @{ + */ + +#ifndef CMPARAMS_H +#define CMPARAMS_H + +/* Defines required for correct CMSIS header functioning */ +#define __MPU_PRESENT 1 /**< MPU present */ +#define __NVIC_PRIO_BITS 3 /**< Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 1 /**< Use different SysTick Config */ +#define __FPU_PRESENT 1 /**< FPU present */ + +/* The following two defines are needed by ChibiOS */ +#define SVCall_IRQn -5 +#define PendSV_IRQn -3 + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL 4 + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU 1 + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +/** + * @brief Number of interrupt vectors. + * @note This number does not include the 16 system vectors and must be + * rounded to a multiple of 8. + */ +#define CORTEX_NUM_VECTORS 184 + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +// /* If the device type is not externally defined, for example from the Makefile, +// then a file named board.h is included. This file must contain a device +// definition compatible with the vendor include file.*/ +// #if !defined(STM32F405xx) && !defined(STM32F415xx) && \ +// !defined(STM32F407xx) && !defined(STM32F417xx) && \ +// !defined(STM32F427xx) && !defined(STM32F437xx) && \ +// !defined(STM32F429xx) && !defined(STM32F439xx) && \ +// !defined(STM32F401xC) && !defined(STM32F401xE) && \ +// !defined(STM32F410Cx) && !defined(STM32F410Rx) && \ +// !defined(STM32F411xE) && !defined(STM32F446xx) && \ +// !defined(STM32F469xx) && !defined(STM32F479xx) +#include "board.h" +// #endif + +typedef int IRQn_Type; + +#include "core_cm4.h" + +/* Including the device CMSIS header. Note, we are not using the definitions + from this header because we need this file to be usable also from + assembler source files. We verify that the info matches instead.*/ +//#include "cc3200.h" + + +/* Including the CCWare peripheral headers.*/ +#include "asmdefs.h" +#include "hw_adc.h" +#include "hw_aes.h" +#include "hw_apps_config.h" +#include "hw_apps_rcm.h" +#include "hw_camera.h" +#include "hw_common_reg.h" +#include "hw_des.h" +#include "hw_dthe.h" +#include "hw_flash_ctrl.h" +#include "hw_gpio.h" +#include "hw_gprcm.h" +#include "hw_hib1p2.h" +#include "hw_hib3p3.h" +#include "hw_i2c.h" +#include "hw_ints.h" +#include "hw_mcasp.h" +#include "hw_mcspi.h" +#include "hw_memmap.h" +#include "hw_mmchs.h" +#include "hw_nvic.h" +#include "hw_ocp_shared.h" +#include "hw_shamd5.h" +#include "hw_stack_die_ctrl.h" +#include "hw_timer.h" +#include "hw_types.h" +#include "hw_uart.h" +#include "hw_udma.h" +#include "hw_wdt.h" + +#if CORTEX_NUM_VECTORS != ((((NUM_INTERRUPTS - 16) + 7) / 8) * 8) +#error "CCWare NUM_INTERRUPTS mismatch" +#endif + +#endif /* !defined(_FROM_ASM_) */ + +#endif /* CMPARAMS_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/dummy_includes/hal_community.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/dummy_includes/hal_community.h new file mode 100644 index 00000000..27cb0645 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/dummy_includes/hal_community.h @@ -0,0 +1,19 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef HAL_COMMUNITY_H +#define HAL_COMMUNITY_H + +#ifdef __cplusplus +extern "C" { +#endif + + void halCommunityInit(void); + +#ifdef __cplusplus +} +#endif + +#endif // HAL_COMMUNITY_H diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/hal_nf_community.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/hal_nf_community.h new file mode 100644 index 00000000..d2ae9bd3 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/hal_nf_community.h @@ -0,0 +1,95 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef HAL_NF_COMMUNITY_H +#define HAL_NF_COMMUNITY_H + + +// these are for error checks on the configuration header files +#if !defined(HAL_USE_STM32_FLASH) +#define HAL_USE_STM32_FLASH FALSE +#endif + +#if !defined(HAL_USE_STM32_CRC) +// the default for this driver is to be included +#define HAL_USE_STM32_CRC TRUE +#endif + +#if !defined(HAL_USE_STM32_RNG) +// the default for this driver is to be included +#define HAL_USE_STM32_RNG TRUE +#endif + +#if !defined(HAL_USE_FSMC) +#define HAL_USE_FSMC FALSE +#endif + +#if !defined(HAL_USE_STM32_ONEWIRE) +// the default for this driver is NOT to be included +#define HAL_USE_STM32_ONEWIRE FALSE +#endif + +#if !defined(HAL_USE_STM32_USB_MSD) +// the default for this driver is NOT to be included +#define HAL_USE_STM32_USB_MSD FALSE +#endif + +#if !defined(HAL_USE_STM32_QSPI) +// the default for this driver is NOT to be included +#define HAL_USE_STM32_QSPI FALSE +#endif + +// Abstract interfaces + +// Shared headers +// #include "hal_nnnn.h" + +// Normal drivers +#include +#include +#include +#include +#include +#include + +// Complex drivers +// #include "hal_nnnn.h" + +/////////////////////////////////////////////////////////////////////////////// +// Driver constants. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver pre-compile time settings. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Derived constants and error checks. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver data structures and types. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver macros. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// External declarations. // +/////////////////////////////////////////////////////////////////////////////// + +#ifdef __cplusplus +extern "C" { +#endif + + void halCommunityInit(void); + +#ifdef __cplusplus +} +#endif + +#endif // HAL_NF_COMMUNITY_H + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_crc/hal_stm32_crc.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_crc/hal_stm32_crc.h new file mode 100644 index 00000000..bfbc7c3d --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_crc/hal_stm32_crc.h @@ -0,0 +1,74 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef HAL_STM32_CRC_H +#define HAL_STM32_CRC_H + +#if (HAL_USE_STM32_CRC == TRUE) + +/////////////////////////////////////////////////////////////////////////////// +// Driver constants. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver pre-compile time settings. // +/////////////////////////////////////////////////////////////////////////////// + +// Enables the crcAcquireModule() and crcReleaseModule() APIs. +// Disabling this option saves both code and data space. +#if !defined(CRC_USE_MUTUAL_EXCLUSION) +#define CRC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/////////////////////////////////////////////////////////////////////////////// +// Derived constants and error checks. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver data structures and types. // +/////////////////////////////////////////////////////////////////////////////// + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + CRC_UNINIT, // Not initialized + CRC_STOP, // Stopped + CRC_READY, // Ready + CRC_ACTIVE // Calculating CRC +} crcState; + +#include "crc_lld.h" + +/////////////////////////////////////////////////////////////////////////////// +// Driver macros. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// External declarations. // +/////////////////////////////////////////////////////////////////////////////// + +#ifdef __cplusplus +extern "C" { +#endif + + void crcInit(void); + void crcStart(const crcConfig *config); + void crcStop(); + void crcReset(); + uint32_t crcCompute(const void* buffer, int size, uint32_t initialCrc); + +#if (CRC_USE_MUTUAL_EXCLUSION == TRUE) + void crcAquireModule(); + void crcReleaseModule(); +#endif + +#ifdef __cplusplus +} +#endif + +#endif // HAL_USE_STM32_CRC + +#endif // HAL_STM32_CRC_H diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_flash/hal_stm32_flash.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_flash/hal_stm32_flash.h new file mode 100644 index 00000000..a5eafabb --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_flash/hal_stm32_flash.h @@ -0,0 +1,56 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef HAL_ST_FLASH_H +#define HAL_ST_FLASH_H + +#if (HAL_USE_STM32_FLASH == TRUE) + +#include "flash_lld.h" + +/////////////////////////////////////////////////////////////////////////////// +// Driver constants. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver pre-compile time settings. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Derived constants and error checks. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver data structures and types. // +/////////////////////////////////////////////////////////////////////////////// +#define FLASH_ERASED_WORD 0x0FFFFFFFFU + +/////////////////////////////////////////////////////////////////////////////// +// Driver macros. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// External declarations. // +/////////////////////////////////////////////////////////////////////////////// + +#ifdef __cplusplus +extern "C" { +#endif + + void stm32FlashInit(void); + void stm32FlashObjectInit(SMT32FlashDriver* flash); + void stm32FlashReadBytes(uint32_t startAddress, uint32_t length, uint8_t* buffer); + int stm32FlashWrite(uint32_t startAddress, uint32_t length, const uint8_t* buffer); + int stm32FlashIsErased(uint32_t startAddress, uint32_t length); + int stm32FlashErase(uint32_t address); + +#ifdef __cplusplus +} +#endif + +#endif // HAL_USE_STM32_FLASH + +#endif // HAL_ST_FLASH_H + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_fsmc/hal_stm32_fsmc.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_fsmc/hal_stm32_fsmc.h new file mode 100644 index 00000000..ff94d9cf --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_fsmc/hal_stm32_fsmc.h @@ -0,0 +1,335 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2014 Uladzimir Pylinsky aka barthess +// See LICENSE file in the project root for full license information. +// + +#ifndef HAL_FSMC_H_ +#define HAL_FSMC_H_ + +#if (HAL_USE_FSMC == TRUE) + +/////////////////////////////////////////////////////////////////////////////// +// Driver constants. // +/////////////////////////////////////////////////////////////////////////////// + +// (Re)define if needed base address constants supplied in ST's CMSIS +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) || \ + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) + #if !defined(FSMC_Bank1_R_BASE) + #define FSMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) + #endif + #if !defined(FSMC_Bank1E_R_BASE) + #define FSMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) + #endif + #if !defined(FSMC_Bank2_R_BASE) + #define FSMC_Bank2_R_BASE (FMC_R_BASE + 0x0060) + #endif + #if !defined(FSMC_Bank3_R_BASE) + #define FSMC_Bank3_R_BASE (FMC_R_BASE + 0x0080) + #endif + #if !defined(FSMC_Bank4_R_BASE) + #define FSMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0) + #endif + #if !defined(FSMC_Bank5_R_BASE) + #define FSMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140) + #endif +#else + #if !defined(FSMC_Bank1_R_BASE) + #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) + #endif + #if !defined(FSMC_Bank1E_R_BASE) + #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) + #endif + #if !defined(FSMC_Bank2_R_BASE) + #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) + #endif + #if !defined(FSMC_Bank3_R_BASE) + #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) + #endif + #if !defined(FSMC_Bank4_R_BASE) + #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) + #endif +#endif + +/* + * Base bank mappings + */ +#define FSMC_Bank1_MAP_BASE ((uint32_t) 0x60000000) +#define FSMC_Bank2_MAP_BASE ((uint32_t) 0x70000000) +#define FSMC_Bank3_MAP_BASE ((uint32_t) 0x80000000) +#define FSMC_Bank4_MAP_BASE ((uint32_t) 0x90000000) +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) || \ + defined(STM32F7)) + #define FSMC_Bank5_MAP_BASE ((uint32_t) 0xC0000000) + #define FSMC_Bank6_MAP_BASE ((uint32_t) 0xD0000000) +#endif + +/* + * Subbunks of bank1 + */ +#define FSMC_SUBBUNK_OFFSET (1024 * 1024 * 64) +#define FSMC_Bank1_1_MAP (FSMC_Bank1_MAP_BASE) +#define FSMC_Bank1_2_MAP (FSMC_Bank1_1_MAP + FSMC_SUBBUNK_OFFSET) +#define FSMC_Bank1_3_MAP (FSMC_Bank1_2_MAP + FSMC_SUBBUNK_OFFSET) +#define FSMC_Bank1_4_MAP (FSMC_Bank1_3_MAP + FSMC_SUBBUNK_OFFSET) + +/* + * Bank 2 (NAND) + */ +#define FSMC_Bank2_MAP_COMMON (FSMC_Bank2_MAP_BASE + 0) +#define FSMC_Bank2_MAP_ATTR (FSMC_Bank2_MAP_BASE + 0x8000000) + +#define FSMC_Bank2_MAP_COMMON_DATA (FSMC_Bank2_MAP_COMMON + 0) +#define FSMC_Bank2_MAP_COMMON_CMD (FSMC_Bank2_MAP_COMMON + 0x10000) +#define FSMC_Bank2_MAP_COMMON_ADDR (FSMC_Bank2_MAP_COMMON + 0x20000) + +#define FSMC_Bank2_MAP_ATTR_DATA (FSMC_Bank2_MAP_ATTR + 0) +#define FSMC_Bank2_MAP_ATTR_CMD (FSMC_Bank2_MAP_ATTR + 0x10000) +#define FSMC_Bank2_MAP_ATTR_ADDR (FSMC_Bank2_MAP_ATTR + 0x20000) + +/* + * Bank 3 (NAND) + */ +#define FSMC_Bank3_MAP_COMMON (FSMC_Bank3_MAP_BASE + 0) +#define FSMC_Bank3_MAP_ATTR (FSMC_Bank3_MAP_BASE + 0x8000000) + +#define FSMC_Bank3_MAP_COMMON_DATA (FSMC_Bank3_MAP_COMMON + 0) +#define FSMC_Bank3_MAP_COMMON_CMD (FSMC_Bank3_MAP_COMMON + 0x10000) +#define FSMC_Bank3_MAP_COMMON_ADDR (FSMC_Bank3_MAP_COMMON + 0x20000) + +#define FSMC_Bank3_MAP_ATTR_DATA (FSMC_Bank3_MAP_ATTR + 0) +#define FSMC_Bank3_MAP_ATTR_CMD (FSMC_Bank3_MAP_ATTR + 0x10000) +#define FSMC_Bank3_MAP_ATTR_ADDR (FSMC_Bank3_MAP_ATTR + 0x20000) + +/* + * Bank 4 (PC card) + */ +#define FSMC_Bank4_MAP_COMMON (FSMC_Bank4_MAP_BASE + 0) +#define FSMC_Bank4_MAP_ATTR (FSMC_Bank4_MAP_BASE + 0x8000000) +#define FSMC_Bank4_MAP_IO (FSMC_Bank4_MAP_BASE + 0xC000000) + +/* + * More convenient typedefs than CMSIS has + */ +typedef struct { + __IO uint32_t PCR; /**< NAND Flash control */ + __IO uint32_t SR; /**< NAND Flash FIFO status and interrupt */ + __IO uint32_t PMEM; /**< NAND Flash Common memory space timing */ + __IO uint32_t PATT; /**< NAND Flash Attribute memory space timing */ + uint32_t RESERVED0; /**< Reserved, 0x70 */ + __IO uint32_t ECCR; /**< NAND Flash ECC result registers */ +} FSMC_NAND_TypeDef; + +typedef struct { + __IO uint32_t PCR; /**< PC Card control */ + __IO uint32_t SR; /**< PC Card FIFO status and interrupt */ + __IO uint32_t PMEM; /**< PC Card Common memory space timing */ + __IO uint32_t PATT; /**< PC Card Attribute memory space timing */ + __IO uint32_t PIO; /**< PC Card I/O space timing */ +} FSMC_PCCard_TypeDef; + +typedef struct { + __IO uint32_t BCR; /**< SRAM/NOR chip-select control registers */ + __IO uint32_t BTR; /**< SRAM/NOR chip-select timing registers */ + uint32_t RESERVED[63]; /**< Reserved */ + __IO uint32_t BWTR; /**< SRAM/NOR write timing registers */ +} FSMC_SRAM_NOR_TypeDef; + +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) || \ + defined(STM32F7)) + +typedef struct { + __IO uint32_t SDCR1; /**< SDRAM control register (bank 1) */ + __IO uint32_t SDCR2; /**< SDRAM control register (bank 2) */ + __IO uint32_t SDTR1; /**< SDRAM timing register (bank 1) */ + __IO uint32_t SDTR2; /**< SDRAM timing register (bank 2) */ + __IO uint32_t SDCMR; /**< SDRAM comand mode register */ + __IO uint32_t SDRTR; /**< SDRAM refresh timer register */ + __IO uint32_t SDSR; /**< SDRAM status register */ +} FSMC_SDRAM_TypeDef; + +#endif + +/** + * @brief PCR register + */ +#define FSMC_PCR_PWAITEN ((uint32_t)1 << 1) +#define FSMC_PCR_PBKEN ((uint32_t)1 << 2) +#define FSMC_PCR_PTYP ((uint32_t)1 << 3) +#define FSMC_PCR_PWID_8 ((uint32_t)0 << 4) +#define FSMC_PCR_PWID_16 ((uint32_t)1 << 4) +#define FSMC_PCR_PWID_RESERVED1 ((uint32_t)2 << 4) +#define FSMC_PCR_PWID_RESERVED2 ((uint32_t)3 << 4) +#define FSMC_PCR_PWID_MASK ((uint32_t)3 << 4) +#define FSMC_PCR_ECCEN ((uint32_t)1 << 6) +#define FSMC_PCR_PTYP_PCCARD 0 +#define FSMC_PCR_PTYP_NAND FSMC_PCR_PTYP + +/** + * @brief SR register + */ +#define FSMC_SR_IRS ((uint8_t)0x01) +#define FSMC_SR_ILS ((uint8_t)0x02) +#define FSMC_SR_IFS ((uint8_t)0x04) +#define FSMC_SR_IREN ((uint8_t)0x08) +#define FSMC_SR_ILEN ((uint8_t)0x10) +#define FSMC_SR_IFEN ((uint8_t)0x20) +#define FSMC_SR_FEMPT ((uint8_t)0x40) +#define FSMC_SR_ISR_MASK (FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS) + +/** + * @brief BCR register + */ +#define FSMC_BCR_MBKEN ((uint32_t)1 << 0) +#define FSMC_BCR_MUXEN ((uint32_t)1 << 1) +#define FSMC_BCR_MTYP_SRAM ((uint32_t)0 << 2) +#define FSMC_BCR_MTYP_PSRAM ((uint32_t)1 << 2) +#define FSMC_BCR_MTYP_NOR_NAND ((uint32_t)2 << 2) +#define FSMC_BCR_MTYP_RESERVED ((uint32_t)3 << 2) +#define FSMC_BCR_MWID_8 ((uint32_t)0 << 4) +#define FSMC_BCR_MWID_16 ((uint32_t)1 << 4) +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) || \ + defined(STM32F7)) +#define FSMC_BCR_MWID_32 ((uint32_t)2 << 4) +#else +#define FSMC_BCR_MWID_RESERVED1 ((uint32_t)2 << 4) +#endif +#define FSMC_BCR_MWID_RESERVED2 ((uint32_t)3 << 4) +#define FSMC_BCR_FACCEN ((uint32_t)1 << 6) +#define FSMC_BCR_BURSTEN ((uint32_t)1 << 8) +#define FSMC_BCR_WAITPOL ((uint32_t)1 << 9) +#define FSMC_BCR_WRAPMOD ((uint32_t)1 << 10) +#define FSMC_BCR_WAITCFG ((uint32_t)1 << 11) +#define FSMC_BCR_WREN ((uint32_t)1 << 12) +#define FSMC_BCR_WAITEN ((uint32_t)1 << 13) +#define FSMC_BCR_EXTMOD ((uint32_t)1 << 14) +#define FSMC_BCR_ASYNCWAIT ((uint32_t)1 << 15) +#define FSMC_BCR_CBURSTRW ((uint32_t)1 << 19) +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) || \ + defined(STM32F7)) +#define FSMC_BCR_CCLKEN ((uint32_t)1 << 20) +#endif +#if (defined(STM32F7)) +#define FSMC_BCR_WFDIS ((uint32_t)1 << 21) +#endif + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief FSMC driver enable switch. + * @details If set to @p TRUE the support for FSMC is included. + */ +#if !defined(STM32_FSMC_USE_FSMC1) +#define STM32_FSMC_USE_FSMC1 FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ +#if !STM32_FSMC_USE_FSMC1 +#error "FSMC driver activated but no FSMC peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an FSMC driver. + */ +typedef struct FSMCDriver FSMCDriver; + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + FSMC_UNINIT = 0, /**< Not initialized. */ + FSMC_STOP = 1, /**< Stopped. */ + FSMC_READY = 2, /**< Ready. */ +} fsmcstate_t; + +/** + * @brief Structure representing an FSMC driver. + */ +struct FSMCDriver { + /** + * @brief Driver state. + */ + fsmcstate_t state; + /* End of the mandatory fields.*/ + +#if STM32_SRAM_USE_FSMC_SRAM1 + FSMC_SRAM_NOR_TypeDef *sram1; +#endif +#if STM32_SRAM_USE_FSMC_SRAM2 + FSMC_SRAM_NOR_TypeDef *sram2; +#endif +#if STM32_SRAM_USE_FSMC_SRAM3 + FSMC_SRAM_NOR_TypeDef *sram3; +#endif +#if STM32_SRAM_USE_FSMC_SRAM4 + FSMC_SRAM_NOR_TypeDef *sram4; +#endif +#if STM32_NAND_USE_FSMC_NAND1 + FSMC_NAND_TypeDef *nand1; +#endif +#if STM32_NAND_USE_FSMC_NAND2 + FSMC_NAND_TypeDef *nand2; +#endif +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) || \ + defined(STM32F7)) + #if STM32_USE_FSMC_SDRAM + FSMC_SDRAM_TypeDef *sdram; + #endif +#endif +}; + +/////////////////////////////////////////////////////////////////////////////// +// Driver macros. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// External declarations. // +/////////////////////////////////////////////////////////////////////////////// + +#if STM32_FSMC_USE_FSMC1 && !defined(__DOXYGEN__) +extern FSMCDriver FSMCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void stm32FsmcInit(void); + void fsmc_start(FSMCDriver *fsmcp); + void fsmc_stop(FSMCDriver *fsmcp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_FSMC */ + +#endif /* HAL_FSMC_H_ */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_onewire/hal_stm32_onewire.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_onewire/hal_stm32_onewire.h new file mode 100644 index 00000000..d56c33c5 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_onewire/hal_stm32_onewire.h @@ -0,0 +1,117 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef HAL_STM32_ONEWIRE_H +#define HAL_STM32_ONEWIRE_H + +#if (HAL_USE_STM32_ONEWIRE == TRUE) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +// memory commands // +#define WR_SCRPAD 0x0F /* write scratchpad */ +#define RD_SCRPAD 0xAA /* read scratchpad */ +#define COPY_SCRPAD 0x55 /* copy scratchpad */ +#define RD_MEMORY 0xF0 /* read memory */ +#define RD_MEMORY_CRC 0xA5 /* read memory with CRC */ +#define CLEAR_MEMORY 0x3C /* clear memory */ +#define SKIP_ROM 0xCC /* skip ROM */ + +/* ROM commands */ +#define READ_ROM 0x33 /* read ROM */ +#define MATCH_ROM 0x55 /* match ROM */ +#define SEARCH_ROM 0xF0 /* search ROM */ +#define COND_SEARCH_ROM 0xEC /* conditional search ROM */ + +// General command defines +#define READ_MEMORY_PSW_COMMAND 0x69 + +#define MAX_PORTNUM 16 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ + +/** + * @brief Enables the @p oneWireAcquireBus() and @p oneWireReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ONEWIRE_USE_MUTUAL_EXCLUSION) +#define ONEWIRE_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +// forward declarations +typedef struct ONEWIREDriver ONEWIREDriver; + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + ONEWIRE_UNINIT, /* Not initialized. */ + ONEWIRE_STOP, /* Stopped. */ + ONEWIRE_READY, /* Ready. */ + ONEWIRE_ACTIVE /* Generating random number. */ +} oneWireState; + +#include + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void oneWireInit(void); + void oneWireStart(void); + void oneWireStop(void); + uint8_t oneWireTouchReset(void); + bool oneWireTouchBit(bool sendbit); + uint8_t oneWireTouchByte(uint8_t sendbyte); + uint8_t oneWireWriteByte(uint8_t sendbyte); + uint8_t oneWireReadByte(void); + void oneWireSerialNum(uint8_t* serialnum_buf, uint8_t do_read); + uint8_t oneWireAccess(void); + uint8_t oneWireBlock(uint8_t doReset, uint8_t* tran_buf, uint8_t tran_len); + uint8_t oneWireWriteMemory(uint8_t* buf, uint32_t ln, uint32_t adr); + uint8_t oneWireCopyScratchpad(uint32_t ln, uint32_t adr); + uint8_t oneWireWriteScratchpad(uint8_t* buf, uint32_t ln, uint32_t adr); + uint8_t oneWireReadPage(uint32_t start_pg, uint8_t* finalbuf); + uint8_t oneWireReadPageCRCEE77(uint32_t page, uint8_t *buff); + bool oneWireFindFirst (bool doReset, bool alarmOnly); + bool oneWireFindNext (bool doReset, bool alarmOnly); + + +#if ONEWIRE_USE_MUTUAL_EXCLUSION == TRUE + void oneWireAcquireModule(void); + void oneWireReleaseModule(void); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_STM32_ONEWIRE */ + +#endif /* HAL_STM32_ONEWIRE_H_ */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_qspi/hal_stm32_qspi.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_qspi/hal_stm32_qspi.h new file mode 100644 index 00000000..0b9e40cf --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_qspi/hal_stm32_qspi.h @@ -0,0 +1,75 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef HAL_STM32_QSPI_H +#define HAL_STM32_QSPI_H + +#if (HAL_USE_STM32_QSPI == TRUE) +#if defined(STM32F0xx_MCUCONF) +#error "CAN'T ENABLE QSPI FOR STM32F0 series" +#endif + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ + +/** + * @brief Enables the @p qspiAcquireBus() and @p qspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +// #if !defined(QSPI_USE_MUTUAL_EXCLUSION) +// #define QSPI_USE_MUTUAL_EXCLUSION TRUE +// #endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +#include "qspi_lld.h" + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/* QSPI Error codes */ +#define QSPI_OK ((uint8_t)0x00) +#define QSPI_ERROR ((uint8_t)0x01) +#define QSPI_BUSY ((uint8_t)0x02) +#define QSPI_NOT_SUPPORTED ((uint8_t)0x04) +#define QSPI_SUSPENDED ((uint8_t)0x08) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + + void qspiInit(void); + void qspiStart(QSPI_HandleTypeDef* qspip); + void qspiStop(QSPI_HandleTypeDef* qspi); + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_STM32_QSPI */ + +#endif /* HAL_STM32_QSPI_H_ */ + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_rng/hal_stm32_rng.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_rng/hal_stm32_rng.h new file mode 100644 index 00000000..3c3f01b8 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/include/stm32_rng/hal_stm32_rng.h @@ -0,0 +1,87 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef HAL_STM32_RNG_H +#define HAL_STM32_RNG_H + +#if (HAL_USE_STM32_RNG == TRUE) + +#if defined(STM32F0xx_MCUCONF) +#error "CAN'T ENABLE RNG FOR STM32F0 series" +#endif + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ + +/** + * @brief Enables the @p rngAcquireBus() and @p rngReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(RNG_USE_MUTUAL_EXCLUSION) +#define RNG_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + RNG_UNINIT, /* Not initialized. */ + RNG_STOP, /* Stopped. */ + RNG_READY, /* Ready. */ + RNG_ACTIVE /* Generating random number. */ +} rngState; + +#include "rng_lld.h" + + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + + void rngInit(void); + void rngStart(void); + void rngStop(void); + uint32_t rngGenerateRandomNumber(void); + uint32_t rngGetLastRandomNumber(void); + +#if RNG_USE_MUTUAL_EXCLUSION == TRUE + void rngAcquireModule(void); + void rngReleaseModule(void); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_STM32_RNG */ + +#endif /* HAL_STM32_RNG_H_ */ + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/CRCv1/README.md b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/CRCv1/README.md new file mode 100644 index 00000000..c5a99c90 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/CRCv1/README.md @@ -0,0 +1,8 @@ +# CRC v1 + +This driver supports all STM32 series. +The low level driver code is taken or heavily inspired in the STCube MX HAL drivers from STMicroelectronics. +The ChibiOS driver follows the 'standard' template driver model. + +**NOTE:** unlike all the other drivers and because all SMT32 chips (until now) have a CRC unit, the default for this driver is to be included. +If for some reason the developer chooses NOT to include support, they have to add `#define HAL_USE_STM32_CRC == FALSE` preferably in the file halconf_nf.h. diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/CRCv1/crc_lld.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/CRCv1/crc_lld.c new file mode 100644 index 00000000..816587a1 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/CRCv1/crc_lld.c @@ -0,0 +1,331 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2016 STMicroelectronics. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////// +// This driver has been tested with the following STM32 series: F0 +/////////////////////////////////////////////////////////////////////////////// + + +// The reversed CRC32 calculation is an extra step required for F1, L1, F2 and F4 units series. +// Others have different configurations and polynomial coefficients. + + +#include +#include + +#if (HAL_USE_STM32_CRC == TRUE) + +/////////////////////////////////////////////////////////////////////////////// +// Driver local definitions. // +/////////////////////////////////////////////////////////////////////////////// + +#if (STM32_CRC_PROGRAMMABLE == TRUE) || \ + defined(STM32F7XX) || defined(STM32L0XX) || defined(STM32H7XX) + +// CRC default configuration. +static const crcConfig defaultConfig = { + + .CRCLength = CRC_POLYLENGTH_32B, + .GeneratingPolynomial = DEFAULT_CRC32_POLY, + .InputDataFormat = CRC_INPUTDATA_FORMAT_BYTES, + .InputDataInversionMode = CRC_INPUTDATA_INVERSION_NONE, + .OutputDataInversionMode = CRC_OUTPUTDATA_INVERSION_DISABLE +}; +#endif + +/////////////////////////////////////////////////////////////////////////////// +// Driver exported variables. // +/////////////////////////////////////////////////////////////////////////////// +CRCDriver CRCD1; + +/////////////////////////////////////////////////////////////////////////////// +// Driver local variables and types. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver local functions. // +/////////////////////////////////////////////////////////////////////////////// + + +/////////////////////////////////////////////////////////////////////////////// +// Driver exported functions. // +/////////////////////////////////////////////////////////////////////////////// + +void crc_lld_init(void) { + + CRCD1.State = CRC_STOP; + CRCD1.Config = NULL; + + #if (CRC_USE_MUTUAL_EXCLUSION == TRUE) + osalMutexObjectInit(&CRCD1.Lock); + #endif + + CRCD1.Instance = CRC; +} + +void crc_lld_start(const crcConfig *config) { + + // enable peripheral + rccEnableCRC(FALSE); + +#if (STM32_CRC_PROGRAMMABLE == TRUE) || \ + defined(STM32F7XX) || defined(STM32L0XX) || defined(STM32H7XX) + + // set configuration, if supplied + if (config == NULL) + { + CRCD1.Config = &defaultConfig; + } + else + { + CRCD1.Config = config; + } + +#else + osalDbgAssert(config == NULL, "CRC peripheral doesn't support configuration"); +#endif + +#if (STM32_CRC_PROGRAMMABLE == TRUE) || \ + defined(STM32F7XX) || defined(STM32L0XX) || defined(STM32H7XX) + + WRITE_REG(CRCD1.Instance->INIT, DEFAULT_CRC_INITVALUE); + + // set generating polynomial + WRITE_REG(CRCD1.Instance->POL, CRCD1.Config->GeneratingPolynomial); + + CRCD1.Instance->CR = 0; + + // set generating polynomial size + MODIFY_REG(CRCD1.Instance->CR, CRC_CR_POLYSIZE, CRCD1.Config->CRCLength); + + // set input data inversion mode + MODIFY_REG(CRCD1.Instance->CR, CRC_CR_REV_IN, CRCD1.Config->OutputDataInversionMode); + + // set output data inversion mode + MODIFY_REG(CRCD1.Instance->CR, CRC_CR_REV_OUT, CRCD1.Config->OutputDataInversionMode); + +#endif + + // driver is ready + CRCD1.State = CRC_READY; +} + +void crc_lld_stop() { + + // disable peripheral + rccDisableCRC(); + + // driver is stopped + CRCD1.State = CRC_STOP; +} + +void crc_lld_reset() { + + CRCD1.Instance->CR |= CRC_CR_RESET; +} + +uint32_t crc_lld_compute(const void* buffer, int size, uint32_t initialCrc) { + + int32_t index = 0U; + uint32_t arg1; + uint32_t crc = 0; + + // anything to do here? + if(size == 0) + { + return initialCrc; + } + + // get pointer to buffer + uint8_t* ptr = (uint8_t*)buffer; + +#if defined(STM32F1XX) || defined(STM32L1XX) || defined(STM32F2XX) || defined(STM32F4XX) + uint32_t size_remainder = 0; + + // need to reset CRC peripheral if: + // - CRC initial value is 0 + // - the initial CRC is NOT already loaded in the calculation register + if(initialCrc == 0 || (CRCD1.Instance->DR != initialCrc)) + { + // Reset CRC Calculation Unit + crc_lld_reset(); + + // CRC calculation unit is initiated with 0xFFFFFFFF which is not a initial value for our CRC calculation + // feeding 0xFFFFFFFF to the calculation unit will set the register to 0x00000000 + while(CRCD1.Instance->DR != 0x0) + { + CRCD1.Instance->DR = CRCD1.Instance->DR; + } + } + + if(initialCrc != 0 && CRCD1.Instance->DR != initialCrc) + { + // we have an initial value for CRC calculation and that is not loaded in the CRC calculation register + // load calculation register with REVERSE initial CRC32 value (because of STM32F4 shift order) + CRCD1.Instance->DR = crc_lld_reverseCRC32(initialCrc); + } + + // set variable to hold how many bytes remain after processing the buffer in steps of 4 bytes + size_remainder = size & 3; + + // we'll be reading the buffer in steps of 4 bytes, so the size must be recalculated accordingly + size = size >> 2; + + // feed data into the CRC calculator + for(index = 0U; index < size; index++) + { + // take the next 4 bytes as if they were a UINT32 + // because the CRC calculation unit expects the bytes in reverse order, reverse the byte order first + arg1 = __REV(*(uint32_t*)(ptr)); + + // feed the bytes to the CRC + CRCD1.Instance->DR = arg1; + + // copy to return value + crc = (uint32_t)CRCD1.Instance->DR; + + // increase pointer by 4 to the next position + // !! we are reading UINT32 from a UINT8 pointer!! + ptr +=4; + } + + // compute CRC for remaining bytes, if any + while(size_remainder--) + { + crc = crc_lld_fastCRC32(crc, *(uint8_t*)(ptr++)); + } + +#else + uint16_t* ptr16 = (uint16_t*)buffer; + + // need to reset CRC peripheral if: + // - CRC initial value is 0 + // - the initial CRC is NOT already loaded in the calculation register + if(initialCrc != DEFAULT_CRC_INITVALUE || (CRCD1.Instance->DR != initialCrc)) + { + // Reset CRC Calculation Unit + crc_lld_reset(); + + #if (STM32_CRC_PROGRAMMABLE == TRUE) || \ + defined(STM32F7XX) || defined(STM32L0XX) || defined(STM32H7XX) + // set initial CRC value + WRITE_REG(CRCD1.Instance->INIT, initialCrc); + #endif + } + + switch (CRCD1.Config->InputDataFormat) + { + case CRC_INPUTDATA_FORMAT_WORDS: + // Enter 32-bit input data to the CRC calculator + for(index = 0; index < size; index++) + { + arg1 = ((uint32_t*)buffer)[index]; + CRCD1.Instance->DR = arg1; + } + break; + + case CRC_INPUTDATA_FORMAT_BYTES: + // Specific 8-bit input data handling + + /* Processing time optimization: 4 bytes are entered in a row with a single word write, + * last bytes must be carefully fed to the CRC calculator to ensure a correct type + * handling by the IP */ + for(index = 0; index < (size / 4); index++) + { + CRCD1.Instance->DR = (uint32_t)(((uint32_t)(ptr[4*index])<<24) | ((uint32_t)(ptr[4*index + 1])<<16) | ((uint32_t)(ptr[4*index + 2])<<8) | (uint32_t)(ptr[4*index + 3])); + } + + // last bytes specific handling + if((size % 4) != 0) + { + if(size % 4 == 1) + { + CRCD1.Instance->DR = ptr[4*index]; + } + if(size % 4 == 2) + { + CRCD1.Instance->DR = (uint16_t)((uint16_t)((uint16_t)(ptr[4*index])<<8) | (uint16_t)(ptr[4*index + 1])); + } + if(size % 4 == 3) + { + CRCD1.Instance->DR = (uint16_t)((uint16_t)((uint16_t)(ptr[4*index])<<8) | (uint16_t)(ptr[4*index + 1])); + CRCD1.Instance->DR = ptr[4*index + 2]; + } + } + break; + + case CRC_INPUTDATA_FORMAT_HALFWORDS: + // Specific 16-bit input data handling + + /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, + * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure + * a correct type handling by the IP */ + for(index = 0; index < (size / 2); index++) + { + CRCD1.Instance->DR = (((uint32_t)(ptr16[2*index])<<16) | (uint32_t)(ptr16[2*index + 1])); + } + if((size % 2) != 0) + { + CRCD1.Instance->DR = ptr16[2*index]; + } + break; + } + + crc = CRCD1.Instance->DR; + +#endif + + // Return the CRC computed value + return crc; +} + +#if (CRC_USE_MUTUAL_EXCLUSION == TRUE) + +void crc_lld_aquire() { + osalMutexLock(&CRCD1.Lock); +} + +void crc_lld_release() { + osalMutexUnlock(&CRCD1.Lock); +} + +#endif + +uint32_t crc_lld_reverseCRC32(uint32_t targetCRC) +{ + // nibble lookup table for _REVERSE_ CRC32 polynomial 0x4C11DB7 + static const uint32_t crc32NibbleTable[16] = + { + 0x00000000, 0xB2B4BCB6, 0x61A864DB, 0xD31CD86D, 0xC350C9B6, 0x71E47500, 0xA2F8AD6D, 0x104C11DB, + 0x82608EDB, 0x30D4326D, 0xE3C8EA00, 0x517C56B6, 0x4130476D, 0xF384FBDB, 0x209823B6, 0x922C9F00 + }; + + uint8_t counter = 8; + + while(counter--) + { + targetCRC = (targetCRC >> 4) ^ crc32NibbleTable[targetCRC & 0x0F]; + } + + return targetCRC; +} + +uint32_t crc_lld_fastCRC32(uint32_t initialCrc, uint8_t data) +{ + // nibble lookup table for CRC32 polynomial 0x4C11DB7 + static const uint32_t crc32NibbleTable[16] = + { + 0x00000000, 0x04C11DB7, 0x09823B6E, 0x0D4326D9, 0x130476DC, 0x17C56B6B, 0x1A864DB2, 0x1E475005, + 0x2608EDB8, 0x22C9F00F, 0x2F8AD6D6, 0x2B4BCB61, 0x350C9B64, 0x31CD86D3, 0x3C8EA00A, 0x384FBDBD + }; + + initialCrc = crc32NibbleTable[(initialCrc >> 28) ^ (data >> 4)] ^ (initialCrc << 4) ; + initialCrc = crc32NibbleTable[(initialCrc >> 28) ^ (data & 0xF)] ^ (initialCrc << 4) ; + + return initialCrc; +} + +#endif diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/CRCv1/crc_lld.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/CRCv1/crc_lld.h new file mode 100644 index 00000000..e7449b53 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/CRCv1/crc_lld.h @@ -0,0 +1,182 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef CRC_LLD_H +#define CRC_LLD_H + +#include "stm32_registry.h" +#include +#include + +#if (HAL_USE_STM32_CRC == TRUE) + +/////////////////////////////////////////////////////////////////////////////// +// Driver constants. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver pre-compile time settings. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Derived constants and error checks. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver data structures and types. // +/////////////////////////////////////////////////////////////////////////////// + +// Driver configuration structure. +typedef struct crcConfig { + + // indicates CRC length + uint32_t CRCLength; + + // 7, 8, 16 or 32-bit long value for a polynomial degree + uint32_t GeneratingPolynomial; + + // Input data format + uint32_t InputDataFormat; + + // The final XOR value + uint32_t FinalValue; + + // Specifies input data inversion mode + bool InputDataInversionMode; + + // Specifies output data (i.e. CRC) inversion mode + bool OutputDataInversionMode; + +} crcConfig; + +typedef struct CRCDriver { + + CRC_TypeDef *Instance; //Register base address + + // Driver state. + crcState State; + + // Current configuration data. + const crcConfig *Config; + +#if CRC_USE_MUTUAL_EXCLUSION + // Mutex protecting the peripheral + mutex_t Lock; +#endif // CRC_USE_MUTUAL_EXCLUSION + +} CRCDriver; + + +// From STMicroelectronics Cube HAL +/////////////////////////////////////////// + +#if defined(STM32L0XX) +// this series uses different names for the buses + +#define rccEnableCRC(lp) rccEnableAHB(RCC_AHBENR_CRCEN, lp) +#define rccDisableCRC() rccDisableAHB(RCC_AHBENR_CRCEN) +#define rccResetCRC() rccResetAHB(RCC_AHB1RSTR_CRCRST) + +#endif + +/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial + * @{ + */ +#define DEFAULT_CRC32_POLY 0x04C11DB7U + +/** @defgroup CRC_Default_InitValue Default CRC computation initialization value + * @{ + */ +#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU + +/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used + * @{ + */ +#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) +#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) + +/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used + * @{ + */ +#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) +#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) + +/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP + * @{ + */ +#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000U) +#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0) +#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1) +#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE) + +/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions + * @{ + */ +#define HAL_CRC_LENGTH_32B 32U +#define HAL_CRC_LENGTH_16B 16U +#define HAL_CRC_LENGTH_8B 8U +#define HAL_CRC_LENGTH_7B 7U + +/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but + * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set + * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for + * the CRC APIs to provide a correct result */ +#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000U) +#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001U) +#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002U) +#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003U) + +/** @defgroup CRCEx_Input_Data_Inversion CRC Extended input data inversion modes + * @{ + */ +#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000U) +#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0) +#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1) +#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN) + +/** @defgroup CRCEx_Output_Data_Inversion CRC Extended output data inversion modes + * @{ + */ +#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000U) +#define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT) + +/////////////////////////////////////////// + + +/////////////////////////////////////////////////////////////////////////////// +// Driver macros. // +/////////////////////////////////////////////////////////////////////////////// + +// From STMicroelectronics Cube HAL + +/////////////////////////////////////////////////////////////////////////////// +// External declarations. // +/////////////////////////////////////////////////////////////////////////////// + +#ifdef __cplusplus +extern "C" { +#endif + + void crc_lld_init(void); + void crc_lld_start(const crcConfig *config); + void crc_lld_stop(); + void crc_lld_reset(); + uint32_t crc_lld_compute(const void* buffer, int size, uint32_t initialCrc); + +#if (CRC_USE_MUTUAL_EXCLUSION == TRUE) + void crc_lld_aquire(); + void crc_lld_release(); +#endif + +uint32_t crc_lld_reverseCRC32(uint32_t targetCRC); +uint32_t crc_lld_fastCRC32(uint32_t initialCrc, uint8_t data); + +#ifdef __cplusplus +} +#endif + +#endif // HAL_USE_STM32_CRC + +#endif // CRC_LLD_H diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv1/README.md b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv1/README.md new file mode 100644 index 00000000..e15983aa --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv1/README.md @@ -0,0 +1,4 @@ +# Flash driver V1 + +This driver supports F0 series. +The low level driver code is taken or heavily inspired in the STCube MX HAL drivers from STMicroelectronics. diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv1/flash_lld.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv1/flash_lld.c new file mode 100644 index 00000000..08196953 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv1/flash_lld.c @@ -0,0 +1,227 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2016 STMicroelectronics. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////// +// This driver has been tested with the following STM32 series: F0 +/////////////////////////////////////////////////////////////////////////////// + +#include +#include + +#if (HAL_USE_STM32_FLASH == TRUE) + +/////////////////////////////////////////////////////////////////////////////// +// Driver local definitions. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver exported variables. // +/////////////////////////////////////////////////////////////////////////////// +SMT32FlashDriver STM32FLASH; + +/////////////////////////////////////////////////////////////////////////////// +// Driver local variables and types. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver local functions. // +/////////////////////////////////////////////////////////////////////////////// + +// Unlock the FLASH control register access +bool HAL_FLASH_Unlock(void) +{ + bool status = true; + + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + // Authorize the FLASH Registers access + WRITE_REG(FLASH->KEYR, FLASH_KEY1); + WRITE_REG(FLASH->KEYR, FLASH_KEY2); + + // Verify Flash is unlocked + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + status = false; + } + } + + return status; +} + +// Locks the FLASH control register access +bool HAL_FLASH_Lock(void) +{ + // Set the LOCK Bit to lock the FLASH Registers access + SET_BIT(FLASH->CR, FLASH_CR_LOCK); + + return true; +} + +bool FLASH_WaitForLastOperation(uint32_t timeout) +{ + (void)timeout; + + bool success = true; + + // Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + // Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set + // no need to overload this with a timeout workflow as the watchdog will quick-in if execution gets stuck + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)); + + // Check FLASH End of Operation flag + if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) ) + { + // Clear FLASH End of Operation pending bit + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } + + if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || + __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGERR)) + { + // at this point we don't care about the details of the programming error + success = false; + } + + return success; +} + +/////////////////////////////////////////////////////////////////////////////// +// Driver exported functions. // +/////////////////////////////////////////////////////////////////////////////// + +void flash_lld_init() +{ + stm32FlashObjectInit(&STM32FLASH); +} + +void flash_lld_readBytes(uint32_t startAddress, uint32_t length, uint8_t* buffer) +{ + + __IO uint8_t* cursor = (__IO uint8_t*)startAddress; + __IO uint8_t* endAddress = (__IO uint8_t*)(startAddress + length); + + // copy contents from flash to buffer starting from the start address + while(cursor < endAddress) + { + *buffer++ = *cursor++; + } +} + +int flash_lld_write(uint32_t startAddress, uint32_t length, const uint8_t* buffer) +{ + bool success = true; + + __IO uint8_t* cursor = (__IO uint8_t*)startAddress; + __IO uint8_t* endAddress = (__IO uint8_t*)(startAddress + length); + + // unlock the FLASH + if(HAL_FLASH_Unlock()) + { + // Clear pending flags (if any) + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); + + while(cursor < endAddress) + { + // proceed to program the flash by setting the PG Bit + SET_BIT(FLASH->CR, FLASH_CR_PG); + + // if buffer has enough data, program half-words (16 bits) in a single operation to speed up things + // NOTE: assuming that the supply voltage is able to cope with half-word programming + if((endAddress - cursor) >= 2) + { + *(__IO uint16_t*)cursor = *((uint16_t*)buffer); + + // update flash and buffer pointers by the 'extra' byte that was programmed + cursor += 2; + buffer += 2; + } + else + { + // program single byte + *(__IO uint8_t*)cursor = *buffer; + + // update flash pointer by the 'extra' byte that was programmed + cursor += 2; + } + + // wait for any flash operation to be completed + // timeout set to 0 on purpose + // watchdog will quick-in if execution gets stuck + success = FLASH_WaitForLastOperation(0); + + if(!success) + { + // quit on failure + break; + } + } + + // after the program operation is completed disable the PG Bit + CLEAR_BIT(FLASH->CR, FLASH_CR_PG); + + // lock the FLASH + HAL_FLASH_Lock(); + } + + return success; +} + +int flash_lld_isErased(uint32_t startAddress, uint32_t length) +{ + __IO uint32_t* cursor = (__IO uint32_t*)startAddress; + __IO uint32_t* endAddress = (__IO uint32_t*)(startAddress + length); + + // an erased flash address has to read FLASH_ERASED_WORD + // OK to check by word (32 bits) because the erase is performed by 'page' whose size is word multiple + while(cursor < endAddress) + { + if(*cursor++ != FLASH_ERASED_WORD) + { + // found an address with something other than FLASH_ERASED_WORD!! + return false; + } + } + + // reached here so the segment must be erased + return true; +} + +uint8_t flash_lld_getSector(uint32_t address) +{ + return (address - FLASH_BASE) / F0_SERIES_SECTOR_SIZE; +} + +int flash_lld_erase(uint32_t address) +{ + bool success = true; + + //unlock the FLASH + if(HAL_FLASH_Unlock()) + { + // Clear pending flags (if any) + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); + + // erase the page + SET_BIT(FLASH->CR, FLASH_CR_PER); + WRITE_REG(FLASH->AR, address); + SET_BIT(FLASH->CR, FLASH_CR_STRT); + + // wait for any flash operation to be completed + // watchdog will quick-in if execution gets stuck + success = FLASH_WaitForLastOperation(0); + + // after erase operation completed disable the PER Bit + CLEAR_BIT(FLASH->CR, FLASH_CR_PER); + + // lock the FLASH + HAL_FLASH_Lock(); + } + + return success; +} + +#endif diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv1/flash_lld.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv1/flash_lld.h new file mode 100644 index 00000000..8bcce8b4 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv1/flash_lld.h @@ -0,0 +1,91 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef FLASH_LLD_H +#define FLASH_LLD_H + +#include "stm32_registry.h" +#include + +#if (HAL_USE_STM32_FLASH == TRUE) + +/////////////////////////////////////////////////////////////////////////////// +// Driver constants. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver pre-compile time settings. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Derived constants and error checks. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver data structures and types. // +/////////////////////////////////////////////////////////////////////////////// + +// From STMicroelectronics Cube HAL +// HAL Status structures definition +typedef struct SMT32FlashDriver { + + // pointer to the FLASH Registers + FLASH_TypeDef *flash; + +}SMT32FlashDriver; + +/////////////////////////////////////////////////////////////////////////////// +// Driver macros. // +/////////////////////////////////////////////////////////////////////////////// + +// From STMicroelectronics Cube HAL +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET) + +#define FLASH_FLAG_BSY FLASH_SR_BSY //!< FLASH Busy flag +#define FLASH_FLAG_PGERR FLASH_SR_PGERR //!< FLASH Programming error flag +#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR //!< FLASH Write protected error flag +#define FLASH_FLAG_EOP FLASH_SR_EOP //!< FLASH End of Operation flag + +#define FLASH_FLAG_ALL_ERRORS ( FLASH_FLAG_WRPERR | FLASH_FLAG_PGERR ) + +// FLASH_Program_Parallelism FLASH Program Parallelism +#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000U) +#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100U) +#define FLASH_PSIZE_WORD ((uint32_t)0x00000200U) +#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300U) +#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFFU) + +#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__))) +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__)) + +#define F0_SERIES_SECTOR_SIZE ((uint32_t)0x00001000U) + +/////////////////////////////////////////////////////////////////////////////// +// External declarations. // +/////////////////////////////////////////////////////////////////////////////// + +#if STM32FLASH_USE_FLASH +SMT32FlashDriver STM32FLASH; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + + void flash_lld_init(); + void flash_lld_readBytes(uint32_t startAddress, uint32_t length, uint8_t* buffer); + int flash_lld_write(uint32_t startAddress, uint32_t length, const uint8_t* buffer); + int flash_lld_isErased(uint32_t startAddress, uint32_t length); + int flash_lld_erase(uint32_t address); + uint8_t flash_lld_getSector(uint32_t address); + +#ifdef __cplusplus +} +#endif + +#endif // HAL_USE_STM32_FLASH + +#endif // FLASH_LLD_H diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv2/README.md b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv2/README.md new file mode 100644 index 00000000..e450e52d --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv2/README.md @@ -0,0 +1,4 @@ +# Flash driver V2 + +This driver supports F4 and F7 series. +The low level driver code is taken or heavily inspired in the STCube MX HAL drivers from STMicroelectronics. diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv2/flash_lld.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv2/flash_lld.c new file mode 100644 index 00000000..1163a36a --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv2/flash_lld.c @@ -0,0 +1,396 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2016 STMicroelectronics. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////// +// This driver has been tested with the following STM32 series: F4 +/////////////////////////////////////////////////////////////////////////////// + +#include +#include + +#if (HAL_USE_STM32_FLASH == TRUE) + +/////////////////////////////////////////////////////////////////////////////// +// Driver local definitions. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver exported variables. // +/////////////////////////////////////////////////////////////////////////////// +SMT32FlashDriver STM32FLASH; + +/////////////////////////////////////////////////////////////////////////////// +// Driver local variables and types. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver local functions. // +/////////////////////////////////////////////////////////////////////////////// + +// Unlock the FLASH control register access +bool HAL_FLASH_Unlock(void) +{ + if((FLASH->CR & FLASH_CR_LOCK) != RESET) + { + // Authorize the FLASH Registers access + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + } + else + { + return false; + } + + return true; +} + +// Locks the FLASH control register access +void HAL_FLASH_Lock(void) +{ + // Set the LOCK Bit to lock the FLASH Registers access + FLASH->CR |= FLASH_CR_LOCK; +} + +bool FLASH_WaitForLastOperation(uint32_t timeout) +{ + // Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + // Even if the FLASH operation fails, the BUSY flag will be reset and an error + // flag will be set + + systime_t start = chVTGetSystemTime(); + systime_t end = start + TIME_MS2I(timeout); + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) + { + // do nothing until the timeout expires + if(chVTIsSystemTimeWithin(start, end)) + { + __NOP(); + } + else + { + return false; + } + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET) + { + return false; + } + + // Check FLASH End of Operation flag + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) + { + // Clear FLASH End of Operation pending bit + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } + + // If there is no error flag set + return true; +} + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) ||\ + defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F401xC) ||\ + defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ + defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) + +void FLASH_FlushCaches(void) +{ + // Flush instruction cache + if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN)!= RESET) + { + // Disable instruction cache + __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); + // Reset instruction cache + __HAL_FLASH_INSTRUCTION_CACHE_RESET(); + // Enable instruction cache + __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); + } + + // Flush data cache + if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) + { + // Disable data cache + __HAL_FLASH_DATA_CACHE_DISABLE(); + // Reset data cache + __HAL_FLASH_DATA_CACHE_RESET(); + // Enable data cache + __HAL_FLASH_DATA_CACHE_ENABLE(); + } +} +#endif // define STM32F4xxxx + +/////////////////////////////////////////////////////////////////////////////// +// Driver exported functions. // +/////////////////////////////////////////////////////////////////////////////// + +void flash_lld_init() { + stm32FlashObjectInit(&STM32FLASH); +} + +void flash_lld_readBytes(uint32_t startAddress, uint32_t length, uint8_t* buffer) { + + __IO uint8_t* cursor = (__IO uint8_t*)startAddress; + __IO uint8_t* endAddress = (__IO uint8_t*)(startAddress + length); + + // copy contents from flash to buffer starting from the start address + while(cursor < endAddress) + { + *buffer++ = *cursor++; + } +} + +int flash_lld_write(uint32_t startAddress, uint32_t length, const uint8_t* buffer) { + + __IO uint8_t* cursor = (__IO uint8_t*)startAddress; + __IO uint8_t* endAddress = (__IO uint8_t*)(startAddress + length); + + // default to false + bool success = false; + + // unlock the FLASH + if(HAL_FLASH_Unlock()) + { + // Clear pending flags (if any) + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); + + while(cursor < endAddress) + { + // if buffer has enough data, program half-words (16 bits) in a single operation to speed up things + // NOTE: assuming that the supply voltage is able to cope with half-word programming + if((endAddress - cursor) >= 2) + { + // clear the program size mask + FLASH->CR &= CR_PSIZE_MASK; + // set the size of of the programming word to HALF WORD + FLASH->CR |= FLASH_PSIZE_HALF_WORD; + // proceed to program the flash by setting the PG Bit + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint16_t*)cursor = *((uint16_t*)buffer); + +#if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F745xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F722xx) || \ + defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx) + + // Data synchronous Barrier, forcing the CPU to respect the sequence of instruction without optimization + __DSB(); +#endif + // update flash and buffer pointers by the 'extra' byte that was programmed + cursor += 2; + buffer += 2; + } + else + { + // program single byte + + // clear the program size mask + FLASH->CR &= CR_PSIZE_MASK; + // set the size of of the programming word to BYTE + FLASH->CR |= FLASH_PSIZE_BYTE; + // proceed to program the flash by setting the PG Bit + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint8_t*)cursor = *buffer; + +#if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F745xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F722xx) || \ + defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx) + + // Data synchronous Barrier, forcing the CPU to respect the sequence of instruction without optimization + __DSB(); +#endif + + // update flash pointer by the 'extra' byte that was programmed + cursor += 2; + } + + // wait 500ms for any flash operation to be completed + success = FLASH_WaitForLastOperation(500); + + if(!success) + { + // quit on failure + break; + } + } + + // after the program operation is completed disable the PG Bit + FLASH->CR &= (~FLASH_CR_PG); + + // lock the FLASH + HAL_FLASH_Lock(); + } + + return success; +} + +int flash_lld_isErased(uint32_t startAddress, uint32_t length) { + + __IO uint32_t* cursor = (__IO uint32_t*)startAddress; + __IO uint32_t* endAddress = (__IO uint32_t*)(startAddress + length); + + // an erased flash address has to read FLASH_ERASED_WORD + // OK to check by word (32 bits) because the erase is performed by 'page' whose size is word multiple + while(cursor < endAddress) + { + if(*cursor++ != FLASH_ERASED_WORD) + { + // found an address with something other than FLASH_ERASED_WORD!! + return false; + } + } + + // reached here so the segment must be erased + return true; +} + +uint8_t flash_lld_getSector(uint32_t address) +{ + uint8_t sector = 0; + + if((address < ADDR_FLASH_SECTOR_1) && (address >= ADDR_FLASH_SECTOR_0)) + { + sector = FLASH_SECTOR_0; + } + else if((address < ADDR_FLASH_SECTOR_2) && (address >= ADDR_FLASH_SECTOR_1)) + { + sector = FLASH_SECTOR_1; + } + else if((address < ADDR_FLASH_SECTOR_3) && (address >= ADDR_FLASH_SECTOR_2)) + { + sector = FLASH_SECTOR_2; + } + else if((address < ADDR_FLASH_SECTOR_4) && (address >= ADDR_FLASH_SECTOR_3)) + { + sector = FLASH_SECTOR_3; + } + +// need to wrap the else ifs below because not all target devices have all the sectors defined +#if defined(FLASH_SECTOR_4) + else if((address < ADDR_FLASH_SECTOR_5) && (address >= ADDR_FLASH_SECTOR_4)) + { + sector = FLASH_SECTOR_4; + } +#endif +#if defined(FLASH_SECTOR_5) + else if((address < ADDR_FLASH_SECTOR_6) && (address >= ADDR_FLASH_SECTOR_5)) + { + sector = FLASH_SECTOR_5; + } +#endif +#if defined(FLASH_SECTOR_6) + else if((address < ADDR_FLASH_SECTOR_7) && (address >= ADDR_FLASH_SECTOR_6)) + { + sector = FLASH_SECTOR_6; + } +#endif +// the next one is for devices that have FLASH sector 8 defined (see next one for devices WITHOUT sector 8) +#if defined(FLASH_SECTOR_7) && defined(FLASH_SECTOR_8) + else if((address < ADDR_FLASH_SECTOR_8) && (address >= ADDR_FLASH_SECTOR_7)) + { + sector = FLASH_SECTOR_7; + } +#endif +// this next one needs to be here for devices that don't have FLASH sector 8 +#if defined(FLASH_SECTOR_7) && !defined(FLASH_SECTOR_8) + else if(address >= ADDR_FLASH_SECTOR_7) + { + sector = FLASH_SECTOR_7; + } +#endif +#if defined(FLASH_SECTOR_8) + else if((address < ADDR_FLASH_SECTOR_9) && (address >= ADDR_FLASH_SECTOR_8)) + { + sector = FLASH_SECTOR_8; + } +#endif +#if defined(FLASH_SECTOR_9) + else if((address < ADDR_FLASH_SECTOR_10) && (address >= ADDR_FLASH_SECTOR_9)) + { + sector = FLASH_SECTOR_9; + } +#endif +#if defined(FLASH_SECTOR_10) + else if((address < ADDR_FLASH_SECTOR_11) && (address >= ADDR_FLASH_SECTOR_10)) + { + sector = FLASH_SECTOR_10; + } +#endif + else /* (address < FLASH_END_ADDR) && (address >= ADDR_FLASH_SECTOR_11) */ + { + sector = FLASH_SECTOR_11; + } + + return sector; +} + +int flash_lld_erase(uint32_t address) { + + // default to false + bool success = false; + + // unlock the FLASH + if(HAL_FLASH_Unlock()) + { + // Clear pending flags (if any) + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); + + // get the sector number to erase + uint8_t sectorNumber = flash_lld_getSector(address); + + // Need to add offset of 4 when sector higher than FLASH_SECTOR_11 + if(sectorNumber > FLASH_SECTOR_11) + { + sectorNumber += 4U; + } + + // If the previous operation is completed, proceed to erase the sector + CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); + SET_BIT(FLASH->CR, FLASH_PSIZE_HALF_WORD); + CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); + FLASH->CR |= FLASH_CR_SER | (sectorNumber << POSITION_VAL(FLASH_CR_SNB)); + + // start erase operation + FLASH->CR |= FLASH_CR_STRT; + +#if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F745xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F722xx) || \ + defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx) + + // Data synchronous Barrier, forcing the CPU to respect the sequence of instruction without optimization + __DSB(); +#endif + + // wait 500ms for any flash operation to be completed + success = FLASH_WaitForLastOperation(2000); + + // after erase operation completed disable the SER and SNB Bits + CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB)); + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) ||\ + defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F401xC) ||\ + defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ + defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) + + // Flush the caches to be sure of the data consistency + FLASH_FlushCaches(); +#endif + + // lock the FLASH + HAL_FLASH_Lock(); + } + + return success; +} + +#endif diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv2/flash_lld.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv2/flash_lld.h new file mode 100644 index 00000000..06c27d18 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv2/flash_lld.h @@ -0,0 +1,451 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2016 STMicroelectronics. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef FLASH_LLD_H +#define FLASH_LLD_H + +#include "stm32_registry.h" +#include + +#if (HAL_USE_STM32_FLASH == TRUE) + +/////////////////////////////////////////////////////////////////////////////// +// Driver constants. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver pre-compile time settings. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Derived constants and error checks. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver data structures and types. // +/////////////////////////////////////////////////////////////////////////////// + +// From STMicroelectronics Cube HAL +// HAL Status structures definition + +typedef struct SMT32FlashDriver { + + // pointer to the FLASH Registers + FLASH_TypeDef *flash; + +}SMT32FlashDriver; + +/////////////////////////////////////////////////////////////////////////////// +// Driver macros. // +/////////////////////////////////////////////////////////////////////////////// + +// From STMicroelectronics Cube HAL +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#ifndef HAL_IS_BIT_SET +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET) +#endif +#define FLASH_KEY1 ((uint32_t)0x45670123U) +#define FLASH_KEY2 ((uint32_t)0xCDEF89ABU) +#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU) +#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7FU) +#define SECTOR_MASK ((uint32_t)0xFFFFFF07) + +// FLASH_Error_Code FLASH Error Code +#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_FLASH_ERROR_ERS ((uint32_t)0x00000002U) /*!< Programming Sequence error */ +#define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004U) /*!< Programming Parallelism error */ +#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008U) /*!< Programming Alignment error */ +#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010U) /*!< Write protection error */ +#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020U) /*!< Operation Error */ +#define HAL_FLASH_ERROR_RD ((uint32_t)0x00000040U) /*!< Read Protection Error */ + +// FLASH_Program_Parallelism FLASH Program Parallelism +#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000U) +#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100U) +#define FLASH_PSIZE_WORD ((uint32_t)0x00000200U) +#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300U) +#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFFU) + +//---------------------------------- STM32F4xx ------------------------------// +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) ||\ + defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ + defined(STM32F401xC) ||\ + defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ + defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) + +#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_OPERR FLASH_SR_SOP /*!< FLASH operation Error flag */ +#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */ +#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */ +#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming Sequence error flag */ +#if defined(FLASH_SR_RDERR) +#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< Read Protection error flag (PCROP) */ +#endif /* FLASH_SR_RDERR */ +#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ + +#if defined(FLASH_SR_RDERR) +#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR) + +#else +#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR ) + +#endif // FLASH_SR_RDERR + + +//---------------------------------- STM32F7xx ------------------------------// +#elif defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F745xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F722xx) || \ + defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx) + +#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH operation Error flag */ +#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */ +#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */ +#define FLASH_FLAG_ERSERR FLASH_SR_ERSERR /*!< FLASH Erasing Sequence error flag */ +#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ + +#if defined (FLASH_OPTCR2_PCROP) +#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH Read protection error flag */ +#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR | FLASH_FLAG_RDERR) +#else +#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR) +#endif /* FLASH_OPTCR2_PCROP */ + +#endif + +#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__))) +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__)) + +// FLASHEx_Sectors FLASH Sectors +/*-------------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx ------------------------------------*/ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ + defined(STM32F469xx) || defined(STM32F479xx) + +#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ +#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ +#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */ +#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */ +#define FLASH_SECTOR_4 ((uint32_t)4U) /*!< Sector Number 4 */ +#define FLASH_SECTOR_5 ((uint32_t)5U) /*!< Sector Number 5 */ +#define FLASH_SECTOR_6 ((uint32_t)6U) /*!< Sector Number 6 */ +#define FLASH_SECTOR_7 ((uint32_t)7U) /*!< Sector Number 7 */ +#define FLASH_SECTOR_8 ((uint32_t)8U) /*!< Sector Number 8 */ +#define FLASH_SECTOR_9 ((uint32_t)9U) /*!< Sector Number 9 */ +#define FLASH_SECTOR_10 ((uint32_t)10U) /*!< Sector Number 10 */ +#define FLASH_SECTOR_11 ((uint32_t)11U) /*!< Sector Number 11 */ +#define FLASH_SECTOR_12 ((uint32_t)12U) /*!< Sector Number 12 */ +#define FLASH_SECTOR_13 ((uint32_t)13U) /*!< Sector Number 13 */ +#define FLASH_SECTOR_14 ((uint32_t)14U) /*!< Sector Number 14 */ +#define FLASH_SECTOR_15 ((uint32_t)15U) /*!< Sector Number 15 */ +#define FLASH_SECTOR_16 ((uint32_t)16U) /*!< Sector Number 16 */ +#define FLASH_SECTOR_17 ((uint32_t)17U) /*!< Sector Number 17 */ +#define FLASH_SECTOR_18 ((uint32_t)18U) /*!< Sector Number 18 */ +#define FLASH_SECTOR_19 ((uint32_t)19U) /*!< Sector Number 19 */ +#define FLASH_SECTOR_20 ((uint32_t)20U) /*!< Sector Number 20 */ +#define FLASH_SECTOR_21 ((uint32_t)21U) /*!< Sector Number 21 */ +#define FLASH_SECTOR_22 ((uint32_t)22U) /*!< Sector Number 22 */ +#define FLASH_SECTOR_23 ((uint32_t)23U) /*!< Sector Number 23 */ + +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbyte */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbyte */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbyte */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbyte */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbyte */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08080000) /* Base @ of Sector 8, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x080A0000) /* Base @ of Sector 9, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x080C0000) /* Base @ of Sector 10, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x080E0000) /* Base @ of Sector 11, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_12 ((uint32_t)0x08100000) /* Base @ of Sector 12, 16 Kbyte */ +#define ADDR_FLASH_SECTOR_13 ((uint32_t)0x08104000) /* Base @ of Sector 13, 16 Kbyte */ +#define ADDR_FLASH_SECTOR_14 ((uint32_t)0x08108000) /* Base @ of Sector 14, 16 Kbyte */ +#define ADDR_FLASH_SECTOR_15 ((uint32_t)0x0810C000) /* Base @ of Sector 15, 16 Kbyte */ +#define ADDR_FLASH_SECTOR_16 ((uint32_t)0x08110000) /* Base @ of Sector 16, 64 Kbyte */ +#define ADDR_FLASH_SECTOR_17 ((uint32_t)0x08120000) /* Base @ of Sector 17, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_18 ((uint32_t)0x08140000) /* Base @ of Sector 18, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_19 ((uint32_t)0x08160000) /* Base @ of Sector 19, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_20 ((uint32_t)0x08180000) /* Base @ of Sector 20, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_21 ((uint32_t)0x081A0000) /* Base @ of Sector 21, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_22 ((uint32_t)0x081C0000) /* Base @ of Sector 22, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_23 ((uint32_t)0x081E0000) /* Base @ of Sector 23, 128 Kbyte */ + +#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */ +/*-----------------------------------------------------------------------------------------------------*/ + +/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\ + defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) +#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ +#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ +#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */ +#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */ +#define FLASH_SECTOR_4 ((uint32_t)4U) /*!< Sector Number 4 */ +#define FLASH_SECTOR_5 ((uint32_t)5U) /*!< Sector Number 5 */ +#define FLASH_SECTOR_6 ((uint32_t)6U) /*!< Sector Number 6 */ +#define FLASH_SECTOR_7 ((uint32_t)7U) /*!< Sector Number 7 */ +#define FLASH_SECTOR_8 ((uint32_t)8U) /*!< Sector Number 8 */ +#define FLASH_SECTOR_9 ((uint32_t)9U) /*!< Sector Number 9 */ +#define FLASH_SECTOR_10 ((uint32_t)10U) /*!< Sector Number 10 */ +#define FLASH_SECTOR_11 ((uint32_t)11U) /*!< Sector Number 11 */ + +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08080000) /* Base @ of Sector 8, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x080A0000) /* Base @ of Sector 9, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x080C0000) /* Base @ of Sector 10, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x080E0000) /* Base @ of Sector 11, 128 Kbytes */ + +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ +/*-----------------------------------------------------------------------------------------------------*/ + +/*--------------------------------------------- STM32F401xC -------------------------------------------*/ +#if defined(STM32F401xC) + +#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ +#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ +#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */ +#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */ +#define FLASH_SECTOR_4 ((uint32_t)4U) /*!< Sector Number 4 */ +#define FLASH_SECTOR_5 ((uint32_t)5U) /*!< Sector Number 5 */ + +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */ + +#endif /* STM32F401xC */ +/*-----------------------------------------------------------------------------------------------------*/ + +/*--------------------------------------------- STM32F410xx -------------------------------------------*/ +#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ +#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ +#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */ +#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */ +#define FLASH_SECTOR_4 ((uint32_t)4U) /*!< Sector Number 4 */ +#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ +/*-----------------------------------------------------------------------------------------------------*/ + +/*---------------------------------- STM32F401xE/STM32F411xE/STM32F446xx ------------------------------*/ +#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) + +#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ +#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ +#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */ +#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */ +#define FLASH_SECTOR_4 ((uint32_t)4U) /*!< Sector Number 4 */ +#define FLASH_SECTOR_5 ((uint32_t)5U) /*!< Sector Number 5 */ +#define FLASH_SECTOR_6 ((uint32_t)6U) /*!< Sector Number 6 */ +#define FLASH_SECTOR_7 ((uint32_t)7U) /*!< Sector Number 7 */ + +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbyte */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbyte */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbyte */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbyte */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbyte */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbyte */ + +#endif /* STM32F401xE || STM32F411xE || STM32F446xx */ +/*-----------------------------------------------------------------------------------------------------*/ + +/*---------------------------------- STM32F7xx ------------------------------*/ +#if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F745xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F722xx) || \ + defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx) + +#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ +#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ +#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */ +#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */ +#define FLASH_SECTOR_4 ((uint32_t)4U) /*!< Sector Number 4 */ +#define FLASH_SECTOR_5 ((uint32_t)5U) /*!< Sector Number 5 */ +#define FLASH_SECTOR_6 ((uint32_t)6U) /*!< Sector Number 6 */ +#define FLASH_SECTOR_7 ((uint32_t)7U) /*!< Sector Number 7 */ + +#if (FLASH_SECTOR_TOTAL == 24) +#define FLASH_SECTOR_8 ((uint32_t)8U) /*!< Sector Number 8 */ +#define FLASH_SECTOR_9 ((uint32_t)9U) /*!< Sector Number 9 */ +#define FLASH_SECTOR_10 ((uint32_t)10U) /*!< Sector Number 10 */ +#define FLASH_SECTOR_11 ((uint32_t)11U) /*!< Sector Number 11 */ +#define FLASH_SECTOR_12 ((uint32_t)12U) /*!< Sector Number 12 */ +#define FLASH_SECTOR_13 ((uint32_t)13U) /*!< Sector Number 13 */ +#define FLASH_SECTOR_14 ((uint32_t)14U) /*!< Sector Number 14 */ +#define FLASH_SECTOR_15 ((uint32_t)15U) /*!< Sector Number 15 */ +#define FLASH_SECTOR_16 ((uint32_t)16U) /*!< Sector Number 16 */ +#define FLASH_SECTOR_17 ((uint32_t)17U) /*!< Sector Number 17 */ +#define FLASH_SECTOR_18 ((uint32_t)18U) /*!< Sector Number 18 */ +#define FLASH_SECTOR_19 ((uint32_t)19U) /*!< Sector Number 19 */ +#define FLASH_SECTOR_20 ((uint32_t)20U) /*!< Sector Number 20 */ +#define FLASH_SECTOR_21 ((uint32_t)21U) /*!< Sector Number 21 */ +#define FLASH_SECTOR_22 ((uint32_t)22U) /*!< Sector Number 22 */ +#define FLASH_SECTOR_23 ((uint32_t)23U) /*!< Sector Number 23 */ +#else +// need to define here a 'dummy'' SECTOR_11, for F7 series this required when FLASH_SECTOR_TOTAL is 8 +#define FLASH_SECTOR_11 ((uint32_t)11U) /*!< Sector Number 11 */ +#endif /* FLASH_SECTOR_TOTAL == 24 */ + +// the following is assuming DUAL BANK is not used +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base address of Sector 0, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08008000) /* Base address of Sector 1, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08010000) /* Base address of Sector 2, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x08018000) /* Base address of Sector 3, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08020000) /* Base address of Sector 4, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08040000) /* Base address of Sector 5, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08080000) /* Base address of Sector 6, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x080C0000) /* Base address of Sector 7, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08100000) /* Base address of Sector 8, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x08140000) /* Base address of Sector 9, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x08180000) /* Base address of Sector 10, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x081C0000) /* Base address of Sector 11, 256 Kbytes */ + +#endif // efined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F745xx) || defined(STM32F767xx) || .... etc + + +///////////////// +// sector address +///////////////// + +#if defined(STM32F746xx) || defined(STM32F745xx) + +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base address of Sector 0, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08008000) /* Base address of Sector 1, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08010000) /* Base address of Sector 2, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x08018000) /* Base address of Sector 3, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08020000) /* Base address of Sector 4, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08040000) /* Base address of Sector 5, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08080000) /* Base address of Sector 6, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x080C0000) /* Base address of Sector 7, 256 Kbytes */ + +#elif defined(STM32F767xx) + +// this is assuming that we DO NOT work with dual bank +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base address of Sector 0, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08008000) /* Base address of Sector 1, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08010000) /* Base address of Sector 2, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x08018000) /* Base address of Sector 3, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08020000) /* Base address of Sector 4, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08040000) /* Base address of Sector 5, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08080000) /* Base address of Sector 6, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x080C0000) /* Base address of Sector 7, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08100000) /* Base address of Sector 8, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x08140000) /* Base address of Sector 9, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x08180000) /* Base address of Sector 10, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x081C0000) /* Base address of Sector 11, 256 Kbytes */ + +#elif defined(STM32F769xx) + +// this is assuming that we DO NOT work with dual bank +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 32 Kbyte */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08008000) /* Base @ of Sector 1, 32 Kbyte */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08010000) /* Base @ of Sector 2, 32 Kbyte */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x08018000) /* Base @ of Sector 3, 32 Kbyte */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08020000) /* Base @ of Sector 4, 128 Kbyte */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08040000) /* Base @ of Sector 5, 256 Kbyte */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08080000) /* Base @ of Sector 6, 256 Kbyte */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x080C0000) /* Base @ of Sector 7, 256 Kbyte */ +#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08100000) /* Base @ of Sector 8, 256 Kbyte */ +#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x08140000) /* Base @ of Sector 9, 256 Kbyte */ +#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x08180000) /* Base @ of Sector 10, 256 Kbyte */ +#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x081C0000) /* Base @ of Sector 11, 256 Kbyte */ + +#elif defined(STM32F722xx) + +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base address of Sector 0, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08008000) /* Base address of Sector 1, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08010000) /* Base address of Sector 2, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x08018000) /* Base address of Sector 3, 32 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08020000) /* Base address of Sector 4, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08040000) /* Base address of Sector 5, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08080000) /* Base address of Sector 6, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x080C0000) /* Base address of Sector 7, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_8 ((uint32_t)0x08100000) /* Base address of Sector 8, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_9 ((uint32_t)0x08140000) /* Base address of Sector 9, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_10 ((uint32_t)0x08180000) /* Base address of Sector 10, 256 Kbytes */ +#define ADDR_FLASH_SECTOR_11 ((uint32_t)0x081C0000) /* Base address of Sector 11, 256 Kbytes */ + +#elif defined(STM32F723xx) + +#define ADDR_FLASH_SECTOR_0 ((uint32_t)0x08000000) /* Base @ of Sector 0, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_1 ((uint32_t)0x08004000) /* Base @ of Sector 1, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_2 ((uint32_t)0x08008000) /* Base @ of Sector 2, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_3 ((uint32_t)0x0800C000) /* Base @ of Sector 3, 16 Kbytes */ +#define ADDR_FLASH_SECTOR_4 ((uint32_t)0x08010000) /* Base @ of Sector 4, 64 Kbytes */ +#define ADDR_FLASH_SECTOR_5 ((uint32_t)0x08020000) /* Base @ of Sector 5, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_6 ((uint32_t)0x08040000) /* Base @ of Sector 6, 128 Kbytes */ +#define ADDR_FLASH_SECTOR_7 ((uint32_t)0x08060000) /* Base @ of Sector 7, 128 Kbytes */ + +#endif + +// sanity check for definition of flash sector, sector0 exists on any target, so we are good checking for its definition +#ifndef ADDR_FLASH_SECTOR_0 +#error >>THE SECTORS ADDRESSES FOR THE TARGET BOARD HAVE NOT BEEN DEFINED, PLEASE ADD THOSE ABOVE AT THE APPROPRIATE LOCATION AND SUBMIT A PR<< +#endif + + +// END of sector address + + +#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_ICEN) +#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_ICEN)) + +#define __HAL_FLASH_DATA_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_DCEN)) +#define __HAL_FLASH_DATA_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_DCEN) +#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST; \ + FLASH->ACR &= ~FLASH_ACR_ICRST; \ + }while(0U) +#define __HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST; \ + FLASH->ACR &= ~FLASH_ACR_DCRST; \ + }while(0U) + +/////////////////////////////////////////////////////////////////////////////// +// External declarations. // +/////////////////////////////////////////////////////////////////////////////// + +#if STM32FLASH_USE_FLASH +SMT32FlashDriver STM32FLASH; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + bool HAL_FLASH_Unlock(void); + void HAL_FLASH_Lock(void); + bool FLASH_WaitForLastOperation(uint32_t timeout); + + void flash_lld_init(); + void flash_lld_readBytes(uint32_t startAddress, uint32_t length, uint8_t* buffer); + int flash_lld_write(uint32_t startAddress, uint32_t length, const uint8_t* buffer); + int flash_lld_isErased(uint32_t startAddress, uint32_t length); + int flash_lld_erase(uint32_t address); + uint8_t flash_lld_getSector(uint32_t address); + +#ifdef __cplusplus +} +#endif + +#endif // HAL_USE_STM32_FLASH + +#endif // FLASH_LLD_H diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv3/README.md b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv3/README.md new file mode 100644 index 00000000..a5d81d13 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv3/README.md @@ -0,0 +1,4 @@ +# Flash driver V3 + +This driver supports L0 series. +The low level driver code is taken or heavily inspired in the STCube MX HAL drivers from STMicroelectronics. diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv3/flash_lld.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv3/flash_lld.c new file mode 100644 index 00000000..199df17b --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv3/flash_lld.c @@ -0,0 +1,236 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) 2016 STMicroelectronics. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////// +// This driver has been tested with the following STM32 series: F0 +/////////////////////////////////////////////////////////////////////////////// + +#include +#include + +#if (HAL_USE_STM32_FLASH == TRUE) + +/////////////////////////////////////////////////////////////////////////////// +// Driver local definitions. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver exported variables. // +/////////////////////////////////////////////////////////////////////////////// +SMT32FlashDriver STM32FLASH; + +/////////////////////////////////////////////////////////////////////////////// +// Driver local variables and types. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver local functions. // +/////////////////////////////////////////////////////////////////////////////// + +// Unlock the FLASH control register access +bool HAL_FLASH_Unlock(void) +{ + // Unlocking FLASH_PECR register access + if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK)) + { + WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1); + WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2); + } + + if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PRGLOCK)) + { + // Unlocking the program memory access + WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY1); + WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY2); + } + + return true; +} + +// Locks the FLASH control register access +bool HAL_FLASH_Lock(void) +{ + // Set the PRGLOCK Bit to lock the FLASH Registers access + SET_BIT(FLASH->PECR, FLASH_PECR_PRGLOCK); + + // Set the PELOCK Bit to lock the PECR Register access + SET_BIT(FLASH->PECR, FLASH_PECR_PELOCK); + + return true; +} + +// Wait for a FLASH operation to complete. +bool FLASH_WaitForLastOperation(uint32_t timeout) +{ + (void)timeout; + + // Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + // Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set + // no need to overload this with a timeout workflow as the watchdog will quick-in if execution gets stuck + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)); + + // Check FLASH End of Operation flag + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) + { + // Clear FLASH End of Operation pending bit + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } + + if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || + __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) || + __HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) || + __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || + __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) || + __HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR) || + __HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) ) + { + return false; + } + + // There is no error flag set + return true; +} + +/////////////////////////////////////////////////////////////////////////////// +// Driver exported functions. // +/////////////////////////////////////////////////////////////////////////////// + +void flash_lld_init() +{ + stm32FlashObjectInit(&STM32FLASH); +} + +void flash_lld_readBytes(uint32_t startAddress, uint32_t length, uint8_t* buffer) +{ + + __IO uint8_t* cursor = (__IO uint8_t*)startAddress; + __IO uint8_t* endAddress = (__IO uint8_t*)(startAddress + length); + + // copy contents from flash to buffer starting from the start address + while(cursor < endAddress) + { + *buffer++ = *cursor++; + } +} + +int flash_lld_write(uint32_t startAddress, uint32_t length, const uint8_t* buffer) +{ + bool success = true; + + __IO uint8_t* cursor = (__IO uint8_t*)startAddress; + __IO uint8_t* endAddress = (__IO uint8_t*)(startAddress + length); + + // unlock the FLASH + if(HAL_FLASH_Unlock()) + { + // Clear pending flags (if any) + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); + + while(cursor < endAddress) + { + // if buffer has enough data, program words (32 bits) in a single operation to speed up things + // NOTE: assuming that the supply voltage is able to cope with half-word programming + if((endAddress - cursor) >= 4) + { + *(__IO uint32_t*)cursor = *((uint32_t*)buffer); + + //*(__IO uint32_t*)cursor = 0xBEEFBEEF; + + // update flash and buffer pointers by the 'extra' byte that was programmed + cursor += 4; + buffer += 4; + } + else + { + // can only program words + // TODO add error code? + success = false; + break; + } + + // wait for any flash operation to be completed + // timeout set to 0 on purpose + // watchdog will quick-in if execution gets stuck + success = FLASH_WaitForLastOperation(0); + + if(!success) + { + // quit on failure + break; + } + } + + // lock the FLASH + HAL_FLASH_Lock(); + } + + // done here + return success; +} + +int flash_lld_isErased(uint32_t startAddress, uint32_t length) +{ + __IO uint32_t* cursor = (__IO uint32_t*)startAddress; + __IO uint32_t* endAddress = (__IO uint32_t*)(startAddress + length); + + // an erased flash address has to read FLASH_ERASED_WORD + // OK to check by word (32 bits) because the erase is performed by 'page' whose size is word multiple + while(cursor < endAddress) + { + if(*cursor++ != FLASH_ERASED_WORD) + { + // found an address with something other than FLASH_ERASED_WORD!! + return false; + } + } + + // reached here so the segment must be erased + return true; +} + +uint8_t flash_lld_getSector(uint32_t address) +{ + return (address - FLASH_BASE) / FLASH_PAGE_SIZE; +} + +int flash_lld_erase(uint32_t address) +{ + bool success = true; + + // unlock the FLASH + if(HAL_FLASH_Unlock()) + { + // Clear pending flags (if any) + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); + + // erase the page + + // Set the ERASE bit + SET_BIT(FLASH->PECR, FLASH_PECR_ERASE); + + // Set PROG bit + SET_BIT(FLASH->PECR, FLASH_PECR_PROG); + + // Write 00000000h to the first word of the program page to erase + *(__IO uint32_t *)(uint32_t)(address & ~(FLASH_PAGE_SIZE - 1)) = 0x00000000; + + // wait for any flash operation to be completed + // watchdog will quick-in if execution gets stuck + success = FLASH_WaitForLastOperation(0); + + // If the erase operation is completed, disable the ERASE Bit + CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); + CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); + + // lock the FLASH + HAL_FLASH_Lock(); + } + + return success; +} + +#endif diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv3/flash_lld.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv3/flash_lld.h new file mode 100644 index 00000000..475aae08 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FLASHv3/flash_lld.h @@ -0,0 +1,152 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef FLASH_LLD_H +#define FLASH_LLD_H + +#include "stm32_registry.h" +#include + +#if (HAL_USE_STM32_FLASH == TRUE) + +/////////////////////////////////////////////////////////////////////////////// +// Driver constants. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver pre-compile time settings. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Derived constants and error checks. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver data structures and types. // +/////////////////////////////////////////////////////////////////////////////// + +// From STMicroelectronics Cube HAL +// HAL Status structures definition +typedef struct SMT32FlashDriver { + + // pointer to the FLASH Registers + FLASH_TypeDef *flash; + +}SMT32FlashDriver; + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, + HAL_TIMEOUT = 0x03U +} HAL_StatusTypeDef; + +/////////////////////////////////////////////////////////////////////////////// +// Driver macros. // +/////////////////////////////////////////////////////////////////////////////// + +// From STMicroelectronics Cube HAL +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET) + +#define FLASH_PEKEY1 ((uint32_t)0x89ABCDEFU) /*!< Flash program erase key1 */ +#define FLASH_PEKEY2 ((uint32_t)0x02030405U) /*!< Flash program erase key: used with FLASH_PEKEY2 + to unlock the write access to the FLASH_PECR register and + data EEPROM */ + +#define FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBFU) /*!< Flash program memory key1 */ +#define FLASH_PRGKEY2 ((uint32_t)0x13141516U) /*!< Flash program memory key2: used with FLASH_PRGKEY2 + to unlock the program memory */ +#define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */ +#define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE + +#define FLASH_SIZE (uint32_t)((*((uint32_t *)FLASHSIZE_BASE)&0xFFFF) * 1024U) +#define FLASH_PAGE_SIZE ((uint32_t)128U) /*!< FLASH Page Size in bytes */ + +#define FLASH_FLAG_ALL_ERRORS ( FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \ + FLASH_FLAG_OPTVERR | FLASH_FLAG_RDERR | FLASH_FLAG_FWWERR | \ + FLASH_FLAG_NOTZEROERR ) + +/** + * @brief Get the specified FLASH flag status. + * @param __FLAG__ specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg @ref FLASH_FLAG_BSY FLASH Busy flag + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_ENDHV FLASH End of High Voltage flag + * @arg @ref FLASH_FLAG_READY FLASH Ready flag after low power mode + * @arg @ref FLASH_FLAG_PGAERR FLASH Programming Alignment error flag + * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag + * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag (not valid with STM32L031xx/STM32L041xx) + * @arg @ref FLASH_FLAG_RDERR FLASH Read protected error flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg @ref FLASH_FLAG_FWWERR FLASH Fetch While Write Error flag + * @arg @ref FLASH_FLAG_NOTZEROERR Not Zero area error flag + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear the specified FLASH flag. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag + * @arg @ref FLASH_FLAG_PGAERR FLASH Programming Alignment error flag + * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag + * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag (not valid with STM32L031xx/STM32L041xx) + * @arg @ref FLASH_FLAG_RDERR FLASH Read protected error flag + * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag + * @arg @ref FLASH_FLAG_FWWERR FLASH Fetch While Write Error flag + * @arg @ref FLASH_FLAG_NOTZEROERR Not Zero area error flag + * @retval none + */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__)) + +/** @defgroup FLASH_Flags FLASH Flags + * @{ + */ + +#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ +#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */ +#define FLASH_FLAG_ENDHV FLASH_SR_HVOFF /*!< FLASH End of High Voltage flag */ +#define FLASH_FLAG_READY FLASH_SR_READY /*!< FLASH Ready flag after low power mode */ +#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */ +#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */ +#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option Validity error flag */ +#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH Read protected error flag */ +#define FLASH_FLAG_FWWERR FLASH_SR_FWWERR /*!< FLASH Write or Errase operation aborted */ +#define FLASH_FLAG_NOTZEROERR FLASH_SR_NOTZEROERR /*!< FLASH Read protected error flag */ + +/////////////////////////////////////////////////////////////////////////////// +// External declarations. // +/////////////////////////////////////////////////////////////////////////////// + +#if STM32FLASH_USE_FLASH +SMT32FlashDriver STM32FLASH; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + + void flash_lld_init(); + void flash_lld_readBytes(uint32_t startAddress, uint32_t length, uint8_t* buffer); + int flash_lld_write(uint32_t startAddress, uint32_t length, const uint8_t* buffer); + int flash_lld_isErased(uint32_t startAddress, uint32_t length); + int flash_lld_erase(uint32_t address); + uint8_t flash_lld_getSector(uint32_t address); + +#ifdef __cplusplus +} +#endif + +#endif // HAL_USE_STM32_FLASH + +#endif // FLASH_LLD_H diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/README.md b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/README.md new file mode 100644 index 00000000..2324fcee --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/README.md @@ -0,0 +1,4 @@ +# External flexible memory controller (FSMC) driver V1 + +This driver supports F4 and F7 series. +The low level driver code is taken from or heavily inspired in the ChibiOS community contribution repository. diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_nand_lld.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_nand_lld.c new file mode 100644 index 00000000..ac2ac802 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_nand_lld.c @@ -0,0 +1,475 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2014 Uladzimir Pylinsky aka barthess +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#if (HAL_USE_NAND == TRUE) + +/////////////////////////////////////////////////////////////////////////////// +// Driver local definitions. // +/////////////////////////////////////////////////////////////////////////////// +#define NAND_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_NAND_DMA_STREAM, \ + STM32_FSMC_DMA_CHN) + +// Bus width of NAND IC. +// Must be 8 or 16 +#if ! defined(STM32_NAND_BUS_WIDTH) +#define STM32_NAND_BUS_WIDTH 8 +#endif + +// DMA transaction width on AHB bus in bytes +#define AHB_TRANSACTION_WIDTH 2 + +/////////////////////////////////////////////////////////////////////////////// +// Driver exported variables. // +/////////////////////////////////////////////////////////////////////////////// + +// NAND1 driver identifier. +#if STM32_NAND_USE_FSMC_NAND1 +NANDDriver NANDD1; +#endif + +// NAND2 driver identifier. +#if STM32_NAND_USE_FSMC_NAND2 +NANDDriver NANDD2; +#endif + +/////////////////////////////////////////////////////////////////////////////// +// Driver local variables and types. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver local functions. // +/////////////////////////////////////////////////////////////////////////////// + +// Helper function. +static void align_check(const void *ptr, uint32_t len) { + osalDbgCheck((((uint32_t)ptr % AHB_TRANSACTION_WIDTH) == 0) && + ((len % AHB_TRANSACTION_WIDTH) == 0) && + (len >= AHB_TRANSACTION_WIDTH)); + (void)ptr; + (void)len; +} + +// Work around errata in STM32's FSMC core. +// Constant output clock (if enabled) disappears when CLKDIV value +// sets to 1 (FMC_CLK period = 2 × HCLK periods) AND 8-bit async +// transaction generated on AHB. This workaround eliminates 8-bit +// transactions on bus when you use 8-bit memory. It suitable only +// for 8-bit memory (i.e. PWID bits in PCR register must be set +// to 8-bit mode). +static void set_16bit_bus(NANDDriver *nandp) { +#if STM32_NAND_BUS_WIDTH + nandp->nand->PCR |= FSMC_PCR_PWID_16; +#else + (void)nandp; +#endif +} + +static void set_8bit_bus(NANDDriver *nandp) { +#if STM32_NAND_BUS_WIDTH + nandp->nand->PCR &= ~FSMC_PCR_PWID_16; +#else + (void)nandp; +#endif +} + +// Wakes up the waiting thread. +// nandp pointer to the @p NANDDriver object +// msg wakeup message +static void wakeup_isr(NANDDriver *nandp) { + + osalDbgCheck(nandp->thread != NULL); + osalThreadResumeI(&nandp->thread, MSG_OK); +} + +// Put calling thread in suspend and switch driver state +// nandp pointer to the @p NANDDriver object +static void nand_lld_suspend_thread(NANDDriver *nandp) { + + osalThreadSuspendS(&nandp->thread); +} + +// Caclulate ECCPS register value +// nandp pointer to the @p NANDDriver object +static uint32_t calc_eccps(NANDDriver *nandp) { + + uint32_t i = 0; + uint32_t eccps = nandp->config->page_data_size; + + eccps = eccps >> 9; + while (eccps > 0){ + i++; + eccps >>= 1; + } + + return i << 17; +} + +/////////////////////////////////////////////////////////////////////////////// +// Driver local variables and types. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver local functions. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver interrupt handlers. // +/////////////////////////////////////////////////////////////////////////////// + +// Enable interrupts from NAND +// nandp pointer to the @p NANDDriver object +static void nand_ready_isr_enable(NANDDriver *nandp) { + + nandp->nand->SR &= ~(FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS | + FSMC_SR_ILEN | FSMC_SR_IFEN); + nandp->nand->SR |= FSMC_SR_IREN; +} + +// Disable interrupts from NAND +// nandp pointer to the @p NANDDriver object +static void nand_ready_isr_disable(NANDDriver *nandp) { + + nandp->nand->SR &= ~FSMC_SR_IREN; +} + +// Ready interrupt handler +// nandp pointer to the @p NANDDriver object +static void nand_isr_handler(NANDDriver *nandp) { + + osalSysLockFromISR(); + + osalDbgCheck(nandp->nand->SR & FSMC_SR_IRS); // spurious interrupt happened + nandp->nand->SR &= ~FSMC_SR_IRS; + + switch (nandp->state){ + case NAND_READ: + nandp->state = NAND_DMA_RX; + dmaStartMemCopy(nandp->dma, nandp->dmamode, nandp->map_data, nandp->rxdata, + nandp->datalen/AHB_TRANSACTION_WIDTH); + // thread will be waked up from DMA ISR + break; + + case NAND_ERASE: // NAND reports about erase finish + case NAND_PROGRAM: // NAND reports about page programming finish + case NAND_RESET: // NAND reports about finished reset recover + nandp->state = NAND_READY; + wakeup_isr(nandp); + break; + + default: + osalSysHalt("Unhandled case"); + break; + } + osalSysUnlockFromISR(); +} + +// DMA RX end IRQ handler. +// nandp pointer to the @p NANDDriver object +// flags pre-shifted content of the ISR register +static void nand_lld_serve_transfer_end_irq(NANDDriver *nandp, uint32_t flags) { + // DMA errors handling. +#if defined(STM32_NAND_DMA_ERROR_HOOK) + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + STM32_NAND_DMA_ERROR_HOOK(nandp); + } +#else + (void)flags; +#endif + + osalSysLockFromISR(); + + dmaStreamDisable(nandp->dma); + + switch (nandp->state){ + case NAND_DMA_TX: + nandp->state = NAND_PROGRAM; + nandp->map_cmd[0] = NAND_CMD_PAGEPROG; + // thread will be woken up from ready_isr() + break; + + case NAND_DMA_RX: + nandp->state = NAND_READY; + nandp->rxdata = NULL; + nandp->datalen = 0; + wakeup_isr(nandp); + break; + + default: + osalSysHalt("Unhandled case"); + break; + } + + osalSysUnlockFromISR(); +} + +/////////////////////////////////////////////////////////////////////////////// +// Driver exported functions. // +/////////////////////////////////////////////////////////////////////////////// + +// Low level NAND driver initialization. +void fsmcNandInit(void) { + + stm32FsmcInit(); + +#if STM32_NAND_USE_FSMC_NAND1 + // Driver initialization. + nandObjectInit(&NANDD1); + NANDD1.rxdata = NULL; + NANDD1.datalen = 0; + NANDD1.thread = NULL; + NANDD1.dma = STM32_DMA_STREAM(STM32_NAND_DMA_STREAM); + NANDD1.nand = FSMCD1.nand1; + NANDD1.map_data = (void *)FSMC_Bank2_MAP_COMMON_DATA; + NANDD1.map_cmd = (uint16_t *)FSMC_Bank2_MAP_COMMON_CMD; + NANDD1.map_addr = (uint16_t *)FSMC_Bank2_MAP_COMMON_ADDR; + NANDD1.bb_map = NULL; +#endif // STM32_NAND_USE_FSMC_NAND1 + +#if STM32_NAND_USE_FSMC_NAND2 + // Driver initialization. + nandObjectInit(&NANDD2); + NANDD2.rxdata = NULL; + NANDD2.datalen = 0; + NANDD2.thread = NULL; + NANDD2.dma = STM32_DMA_STREAM(STM32_NAND_DMA_STREAM); + NANDD2.nand = FSMCD1.nand2; + NANDD2.map_data = (void *)FSMC_Bank3_MAP_COMMON_DATA; + NANDD2.map_cmd = (uint16_t *)FSMC_Bank3_MAP_COMMON_CMD; + NANDD2.map_addr = (uint16_t *)FSMC_Bank3_MAP_COMMON_ADDR; + NANDD2.bb_map = NULL; +#endif // STM32_NAND_USE_FSMC_NAND2 +} + +// Configures and activates the NAND peripheral. +// nandp pointer to the @p NANDDriver object +void fsmcNandStart(NANDDriver *nandp) { + + bool b; + uint32_t dmasize; + uint32_t pcr_bus_width; + + if (FSMCD1.state == FSMC_STOP) + fsmc_start(&FSMCD1); + + if (nandp->state == NAND_STOP) { + b = dmaStreamAllocate(nandp->dma, + STM32_EMC_FSMC1_IRQ_PRIORITY, + (stm32_dmaisr_t)nand_lld_serve_transfer_end_irq, + (void *)nandp); + osalDbgAssert(!b, "stream already allocated"); + +#if AHB_TRANSACTION_WIDTH == 4 + dmasize = STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD; +#elif AHB_TRANSACTION_WIDTH == 2 + dmasize = STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; +#elif AHB_TRANSACTION_WIDTH == 1 + dmasize = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; +#else +#error "Incorrect AHB_TRANSACTION_WIDTH" +#endif + + nandp->dmamode = STM32_DMA_CR_CHSEL(NAND_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_NAND_NAND1_DMA_PRIORITY) | + dmasize | + STM32_DMA_CR_DMEIE | + STM32_DMA_CR_TEIE | + STM32_DMA_CR_TCIE; + +#if STM32_NAND_BUS_WIDTH == 8 + pcr_bus_width = FSMC_PCR_PWID_8; +#elif STM32_NAND_BUS_WIDTH == 16 + pcr_bus_width = FSMC_PCR_PWID_16; +#else +#error "Bus width must be 8 or 16 bits" +#endif + nandp->nand->PCR = pcr_bus_width | calc_eccps(nandp) | + FSMC_PCR_PTYP_NAND | FSMC_PCR_PBKEN; + nandp->nand->PMEM = nandp->config->pmem; + nandp->nand->PATT = nandp->config->pmem; + nandp->isr_handler = nand_isr_handler; + nand_ready_isr_enable(nandp); + } +} + +// Deactivates the NAND peripheral. +// nandp pointer to the @p NANDDriver object +void fsmcNandStop(NANDDriver *nandp) { + + if (nandp->state == NAND_READY) { + dmaStreamRelease(nandp->dma); + nandp->nand->PCR &= ~FSMC_PCR_PBKEN; + nand_ready_isr_disable(nandp); + nandp->isr_handler = NULL; + } +} + +// Read data from NAND. +// nandp pointer to the @p NANDDriver object +// data pointer to data buffer +// datalen size of data buffer in bytes +// addr pointer to address buffer +// addrlen length of address +// ecc pointer to store computed ECC. Ignored when NULL. +void nand_lld_read_data(NANDDriver *nandp, uint16_t *data, size_t datalen, + uint8_t *addr, size_t addrlen, uint32_t *ecc){ + + align_check(data, datalen); + + nandp->state = NAND_READ; + nandp->rxdata = data; + nandp->datalen = datalen; + + set_16bit_bus(nandp); + nand_lld_write_cmd(nandp, NAND_CMD_READ0); + nand_lld_write_addr(nandp, addr, addrlen); + osalSysLock(); + nand_lld_write_cmd(nandp, NAND_CMD_READ0_CONFIRM); + set_8bit_bus(nandp); + + // Here NAND asserts busy signal and starts transferring from memory + // array to page buffer. After the end of transmission ready_isr functions + // starts DMA transfer from page buffer to MCU's RAM. + osalDbgAssert((nandp->nand->PCR & FSMC_PCR_ECCEN) == 0, + "State machine broken. ECCEN must be previously disabled."); + + if (NULL != ecc){ + nandp->nand->PCR |= FSMC_PCR_ECCEN; + } + + nand_lld_suspend_thread(nandp); + osalSysUnlock(); + + // thread was woken up from DMA ISR + if (NULL != ecc){ + while (! (nandp->nand->SR & FSMC_SR_FEMPT)) + ; + *ecc = nandp->nand->ECCR; + nandp->nand->PCR &= ~FSMC_PCR_ECCEN; + } +} + +// Write data to NAND. +// nandp pointer to the @p NANDDriver object +// data buffer with data to be written +// datalen size of data buffer in bytes +// addr pointer to address buffer +// addrlen length of address +// ecc pointer to store computed ECC. Ignored when NULL. +// The operation status reported by NAND IC (0x70 command). +uint8_t nand_lld_write_data(NANDDriver *nandp, const uint16_t *data, + size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc) { + + align_check(data, datalen); + + nandp->state = NAND_WRITE; + + set_16bit_bus(nandp); + nand_lld_write_cmd(nandp, NAND_CMD_WRITE); + osalSysLock(); + nand_lld_write_addr(nandp, addr, addrlen); + set_8bit_bus(nandp); + + // Now start DMA transfer to NAND buffer and put thread in sleep state. + // Tread will be woken up from ready ISR. + nandp->state = NAND_DMA_TX; + osalDbgAssert((nandp->nand->PCR & FSMC_PCR_ECCEN) == 0, + "State machine broken. ECCEN must be previously disabled."); + + if (NULL != ecc){ + nandp->nand->PCR |= FSMC_PCR_ECCEN; + } + + dmaStartMemCopy(nandp->dma, nandp->dmamode, data, nandp->map_data, + datalen/AHB_TRANSACTION_WIDTH); + + nand_lld_suspend_thread(nandp); + osalSysUnlock(); + + if (NULL != ecc){ + while (! (nandp->nand->SR & FSMC_SR_FEMPT)) + ; + *ecc = nandp->nand->ECCR; + nandp->nand->PCR &= ~FSMC_PCR_ECCEN; + } + + return nand_lld_read_status(nandp); +} + +// Soft reset NAND device. +// nandp pointer to the @p NANDDriver object +void nand_lld_reset(NANDDriver *nandp) { + + nandp->state = NAND_RESET; + + set_16bit_bus(nandp); + nand_lld_write_cmd(nandp, NAND_CMD_RESET); + set_8bit_bus(nandp); + + osalSysLock(); + nand_lld_suspend_thread(nandp); + osalSysUnlock(); +} + +// Erase block. +// nandp pointer to the @p NANDDriver object +// addr pointer to address buffer +// addrlen length of address +// return The operation status reported by NAND IC (0x70 command). +uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen) { + + nandp->state = NAND_ERASE; + + set_16bit_bus(nandp); + nand_lld_write_cmd(nandp, NAND_CMD_ERASE); + nand_lld_write_addr(nandp, addr, addrlen); + osalSysLock(); + nand_lld_write_cmd(nandp, NAND_CMD_ERASE_CONFIRM); + set_8bit_bus(nandp); + + nand_lld_suspend_thread(nandp); + osalSysUnlock(); + + return nand_lld_read_status(nandp); +} + +// Send addres to NAND. +// nandp pointer to the @p NANDDriver object +// len length of address array +// addr pointer to address array +void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len) { + size_t i = 0; + + for (i=0; imap_addr[i] = addr[i]; +} + +// Send command to NAND. +// nandp pointer to the @p NANDDriver object +// cmd command value +void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd) { + nandp->map_cmd[0] = cmd; +} + +// Read status byte from NAND. +// nandp pointer to the @p NANDDriver object +// return Status byte. +uint8_t nand_lld_read_status(NANDDriver *nandp) { + + uint16_t status; + + set_16bit_bus(nandp); + nand_lld_write_cmd(nandp, NAND_CMD_STATUS); + set_8bit_bus(nandp); + status = nandp->map_data[0]; + + return status & 0xFF; +} + +#endif // HAL_USE_NAND diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_nand_lld.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_nand_lld.h new file mode 100644 index 00000000..74f5a52b --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_nand_lld.h @@ -0,0 +1,219 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2014 Uladzimir Pylinsky aka barthess +// See LICENSE file in the project root for full license information. +// + +#ifndef HAL_NAND_LLD_H_ +#define HAL_NAND_LLD_H_ + +#include "hal_stm32_fsmc" +#include + +#if (HAL_USE_NAND == TRUE) + +/////////////////////////////////////////////////////////////////////////////// +// Driver constants. // +/////////////////////////////////////////////////////////////////////////////// +#define NAND_MIN_PAGE_SIZE 256 +#define NAND_MAX_PAGE_SIZE 8192 + +/////////////////////////////////////////////////////////////////////////////// +// Driver pre-compile time settings. // +/////////////////////////////////////////////////////////////////////////////// + +// Configuration options + +// FSMC1 interrupt priority level setting. +#if !defined(STM32_EMC_FSMC1_IRQ_PRIORITY) +#define STM32_EMC_FSMC1_IRQ_PRIORITY 10 +#endif + +// NAND driver enable switch. +// If set to @p TRUE the support for NAND1 is included. + +#if !defined(STM32_NAND_USE_NAND1) +#define STM32_NAND_USE_NAND1 FALSE +#endif + +// NAND driver enable switch. +// If set to @p TRUE the support for NAND2 is included. +#if !defined(STM32_NAND_USE_NAND2) +#define STM32_NAND_USE_NAND2 FALSE +#endif + +// NAND DMA error hook. +// The default action for DMA errors is a system halt because DMA +// error can only happen because programming errors. +#if !defined(STM32_NAND_DMA_ERROR_HOOK) +#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") +#endif + +// NAND interrupt enable switch. +// If set to @p TRUE the support for internal FSMC interrupt included. +#if !defined(STM32_NAND_USE_INT) +#define STM32_NAND_USE_INT FALSE +#endif + +// NAND1 DMA priority (0..3|lowest..highest). +#if !defined(STM32_NAND_NAND1_DMA_PRIORITY) +#define STM32_NAND_NAND1_DMA_PRIORITY 0 +#endif + +// NAND2 DMA priority (0..3|lowest..highest). +#if !defined(STM32_NAND_NAND2_DMA_PRIORITY) +#define STM32_NAND_NAND2_DMA_PRIORITY 0 +#endif + +// DMA stream used for NAND operations. +// This option is only available on platforms with enhanced DMA. +#if !defined(STM32_NAND_DMA_STREAM) +#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#endif + +/////////////////////////////////////////////////////////////////////////////// +// Derived constants and error checks. // +/////////////////////////////////////////////////////////////////////////////// + +#if !STM32_NAND_USE_FSMC_NAND1 && !STM32_NAND_USE_FSMC_NAND2 +#error "NAND driver activated but no NAND peripheral assigned" +#endif + +#if (STM32_NAND_USE_FSMC_NAND2 || STM32_NAND_USE_FSMC_NAND1) && !STM32_HAS_FSMC +#error "FSMC not present in the selected device" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/////////////////////////////////////////////////////////////////////////////// +// Driver data structures and types. // +/////////////////////////////////////////////////////////////////////////////// + +// Type of a structure representing an NAND driver. +typedef struct NANDDriver NANDDriver; + +// Type of interrupt handler function. +typedef void (*nandisrhandler_t)(NANDDriver *nandp); + +// Driver configuration structure. +// It could be empty on some architectures. +typedef struct { + // Number of erase blocks in NAND device. + uint32_t blocks; + + // Number of data bytes in page. + uint32_t page_data_size; + + // Number of spare bytes in page. + uint32_t page_spare_size; + + // Number of pages in block. + uint32_t pages_per_block; + + // Number of write cycles for row addressing. + uint8_t rowcycles; + + // Number of write cycles for column addressing. + uint8_t colcycles; + + // End of the mandatory fields. + // Number of wait cycles. This value will be used both for + // PMEM and PATTR registers + // For proper calculation procedure please look at AN2784 document from STMicroelectronics + uint32_t pmem; + +} NANDConfig; + +// Structure representing an NAND driver. +struct NANDDriver { + // Driver state. + nandstate_t state; + + // Current configuration data. + const NANDConfig *config; + + // Array to store bad block map. +#if NAND_USE_MUTUAL_EXCLUSION +#if CH_CFG_USE_MUTEXES + // Mutex protecting the bus. + mutex_t mutex; +#elif CH_CFG_USE_SEMAPHORES + semaphore_t semaphore; +#endif +#endif // NAND_USE_MUTUAL_EXCLUSION + // End of the mandatory fields. + + // Function enabling interrupts from FSMC. + nandisrhandler_t isr_handler; + + // Pointer to current transaction buffer. + void *rxdata; + + // Current transaction length in bytes. + size_t datalen; + + // DMA mode bit mask. + uint32_t dmamode; + + // DMA channel. + const stm32_dma_stream_t *dma; + + // Thread waiting for I/O completion. + thread_t *thread; + + // Pointer to the FSMC NAND registers block. + FSMC_NAND_TypeDef *nand; + + // Memory mapping for data. + uint16_t *map_data; + + // Memory mapping for commands. + uint16_t *map_cmd; + + // Memory mapping for addresses. + uint16_t *map_addr; + +}; + +/////////////////////////////////////////////////////////////////////////////// +// Driver macros. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// External declarations. // +/////////////////////////////////////////////////////////////////////////////// + +#if STM32_NAND_USE_FSMC_NAND1 +extern NANDDriver NANDD1; +#endif + +#if STM32_NAND_USE_FSMC_NAND2 +extern NANDDriver NANDD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + + void fsmcNandInit(void); + void fsmcNandStart(NANDDriver *nandp); + void fsmcNandStop(NANDDriver *nandp); + uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen); + void nand_lld_read_data(NANDDriver *nandp, uint16_t *data, + size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); + void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len); + void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd); + uint8_t nand_lld_write_data(NANDDriver *nandp, const uint16_t *data, + size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); + uint8_t nand_lld_read_status(NANDDriver *nandp); + void nand_lld_reset(NANDDriver *nandp); + +#ifdef __cplusplus +} +#endif + +#endif // HAL_USE_NAND + +#endif // HAL_NAND_LLD_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram_lld.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram_lld.c new file mode 100644 index 00000000..8efa372e --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram_lld.c @@ -0,0 +1,168 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2014 Uladzimir Pylinsky aka barthess and Nick Klimov aka progfin +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) || \ + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) + +#if (STM32_USE_FSMC_SDRAM == TRUE) + +#include "fsmc_sdram_lld.h" + +/////////////////////////////////////////////////////////////////////////////// +// Driver local definitions. // +/////////////////////////////////////////////////////////////////////////////// + +// FMC_Command_Mode +#define FMCCM_NORMAL ((uint32_t)0x00000000) +#define FMCCM_CLK_ENABLED ((uint32_t)0x00000001) +#define FMCCM_PALL ((uint32_t)0x00000002) +#define FMCCM_AUTO_REFRESH ((uint32_t)0x00000003) +#define FMCCM_LOAD_MODE ((uint32_t)0x00000004) +#define FMCCM_SELFREFRESH ((uint32_t)0x00000005) +#define FMCCM_POWER_DOWN ((uint32_t)0x00000006) + +/////////////////////////////////////////////////////////////////////////////// +// Driver exported variables. // +/////////////////////////////////////////////////////////////////////////////// +// SDRAM driver identifier. +SDRAMDriver SDRAMD; + +/////////////////////////////////////////////////////////////////////////////// +// Driver local variables and types. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver local functions. // +/////////////////////////////////////////////////////////////////////////////// + +// Wait until the SDRAM controller is ready. +static void _sdram_wait_ready(void) { + // Wait until the SDRAM controller is ready + while (SDRAMD.sdram->SDSR & FMC_SDSR_BUSY); +} + +// Executes the SDRAM memory initialization sequence. +// cfgp pointer to the @p SDRAMConfig object +static void _sdram_init_sequence(const SDRAMConfig *cfgp) { + + uint32_t command_target = 0; + +#if STM32_SDRAM_USE_FSMC_SDRAM1 + command_target |= FMC_SDCMR_CTB1; +#endif +#if STM32_SDRAM_USE_FSMC_SDRAM2 + command_target |= FMC_SDCMR_CTB2; +#endif + + // Step 3: Configure a clock configuration enable command. + _sdram_wait_ready(); + SDRAMD.sdram->SDCMR = FMCCM_CLK_ENABLED | command_target; + + // Step 4: Insert delay (tipically 100uS). + osalThreadSleepMilliseconds(1); + + // Step 5: Configure a PALL (precharge all) command. + _sdram_wait_ready(); + SDRAMD.sdram->SDCMR = FMCCM_PALL | command_target; + + // Step 6.1: Configure a Auto-Refresh command: send the first command. + _sdram_wait_ready(); + SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target | + (cfgp->sdcmr & FMC_SDCMR_NRFS); + + // Step 6.2: Send the second command. + _sdram_wait_ready(); + SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target | + (cfgp->sdcmr & FMC_SDCMR_NRFS); + + // Step 7: Program the external memory mode register. + _sdram_wait_ready(); + SDRAMD.sdram->SDCMR = FMCCM_LOAD_MODE | command_target | + (cfgp->sdcmr & FMC_SDCMR_MRD); + + // Step 8: Set clock. + _sdram_wait_ready(); + SDRAMD.sdram->SDRTR = cfgp->sdrtr & FMC_SDRTR_COUNT; + + _sdram_wait_ready(); +} + +/////////////////////////////////////////////////////////////////////////////// +// Driver interrupt handlers. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver exported functions. // +/////////////////////////////////////////////////////////////////////////////// + +// Low level SDRAM driver initialization. + +void fsmcSdramInit(void) { + + stm32FsmcInit(); + + SDRAMD.sdram = FSMCD1.sdram; + SDRAMD.state = SDRAM_STOP; +} + +// Configures and activates the SDRAM peripheral. +// sdramp pointer to the @p SDRAMDriver object +// cfgp pointer to the @p SDRAMConfig object +void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) { + + if (FSMCD1.state == FSMC_STOP) + fsmc_start(&FSMCD1); + + osalDbgAssert((sdramp->state == SDRAM_STOP) || (sdramp->state == SDRAM_READY), + "SDRAM. Invalid state."); + + if (sdramp->state == SDRAM_STOP) { + + // Even if you need only bank2 you must properly set up SDCR and SDTR + // regitsters for bank1 too. Both banks will be tuned equally assuming + // connected memory ICs are equal. + sdramp->sdram->SDCR1 = cfgp->sdcr; + sdramp->sdram->SDTR1 = cfgp->sdtr; + sdramp->sdram->SDCR2 = cfgp->sdcr; + sdramp->sdram->SDTR2 = cfgp->sdtr; + + _sdram_init_sequence(cfgp); + + sdramp->state = SDRAM_READY; + } +} + +// Deactivates the SDRAM peripheral. +// sdramp pointer to the @p SDRAMDriver object +void fsmcSdramStop(SDRAMDriver *sdramp) { + + uint32_t command_target = 0; + +#if STM32_SDRAM_USE_FSMC_SDRAM1 + command_target |= FMC_SDCMR_CTB1; +#endif +#if STM32_SDRAM_USE_FSMC_SDRAM2 + command_target |= FMC_SDCMR_CTB2; +#endif + + if (sdramp->state == SDRAM_READY) { + SDRAMD.sdram->SDCMR = FMCCM_POWER_DOWN | command_target; + sdramp->state = SDRAM_STOP; + } +} + +#endif // STM32_USE_FSMC_SDRAM + +#endif //STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx / STM32F469xx / STM32F479xx / STM32F745xx / STM32F746xx + // STM32F756xx / STM32F767xx / STM32F769xx / STM32F777xx / STM32F779xx diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram_lld.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram_lld.h new file mode 100644 index 00000000..20fe8587 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sdram_lld.h @@ -0,0 +1,133 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2014 Uladzimir Pylinsky aka barthess and Nick Klimov aka progfin +// See LICENSE file in the project root for full license information. +// + +#ifndef HAL_FMC_SDRAM_H_ +#define HAL_FMC_SDRAM_H_ + +#include + +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) || \ + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) + +#include "hal_stm32_fsmc.h" + +#if (STM32_USE_FSMC_SDRAM == TRUE) + +/////////////////////////////////////////////////////////////////////////////// +// Driver constants. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver pre-compile time settings. // +/////////////////////////////////////////////////////////////////////////////// +// Configuration options + +// SDRAM driver enable switch. +// If set to @p TRUE the support for SDRAM1 is included. +#if !defined(STM32_SDRAM_USE_FSMC_SDRAM1) +#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE +#else +#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE +#endif + +// SDRAM driver enable switch. +// If set to @p TRUE the support for SDRAM2 is included. +#if !defined(STM32_SDRAM_USE_FSMC_SDRAM2) +#define STM32_SDRAM_USE_FSMC_SDRAM2 FALSE +#else +#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE +#endif + +/////////////////////////////////////////////////////////////////////////////// +// Derived constants and error checks. // +/////////////////////////////////////////////////////////////////////////////// + +#if !STM32_SDRAM_USE_FSMC_SDRAM1 && !STM32_SDRAM_USE_FSMC_SDRAM2 +#error "SDRAM driver activated but no SDRAM peripheral assigned" +#endif + +#if (STM32_SDRAM_USE_FSMC_SDRAM1 || STM32_SDRAM_USE_FSMC_SDRAM2) && !STM32_HAS_FSMC +#error "FMC not present in the selected device" +#endif + +/////////////////////////////////////////////////////////////////////////////// +// Driver data structures and types. // +/////////////////////////////////////////////////////////////////////////////// + +// Driver state machine possible states. +typedef enum +{ + SDRAM_UNINIT = 0, //*< Not initialized. + SDRAM_STOP = 1, //*< Stopped. + SDRAM_READY = 2, //*< Ready. +} sdramstate_t; + +// Type of a structure representing an SDRAM driver. +typedef struct SDRAMDriver SDRAMDriver; + +// Driver configuration structure. +// It could be empty on some architectures. +typedef struct { + // SDRAM control register. + // Its value will be used for both banks. + uint32_t sdcr; + + // SDRAM timing register. + // Its value will be used for both banks. + uint32_t sdtr; + + // SDRAM command mode register. + // Only its MRD and NRFS bits will be used. + uint32_t sdcmr; + + // SDRAM refresh timer register. + // Only its COUNT bits will be used. + uint32_t sdrtr; + +} SDRAMConfig; + +// Structure representing an SDRAM driver. +struct SDRAMDriver { + // Driver state. + sdramstate_t state; + + // Pointer to the FMC SDRAM registers block. + FSMC_SDRAM_TypeDef *sdram; +}; + +/////////////////////////////////////////////////////////////////////////////// +// Driver macros. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// External declarations. // +/////////////////////////////////////////////////////////////////////////////// + +extern SDRAMDriver SDRAMD; + +#ifdef __cplusplus +extern "C" { +#endif + + void fsmcSdramInit(void); + void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp); + void fsmcSdramStop(SDRAMDriver *sdramp); + +#ifdef __cplusplus +} +#endif + +#endif // STM32_USE_FSMC_SDRAM + +#endif //STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx / STM32F469xx / STM32F479xx / STM32F745xx / STM32F746xx + // STM32F756xx / STM32F767xx / STM32F769xx / STM32F777xx / STM32F779xx + +#endif // HAL_FMC_SDRAM_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram_lld.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram_lld.c new file mode 100644 index 00000000..436759c7 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram_lld.c @@ -0,0 +1,123 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2014 Uladzimir Pylinsky aka barthess +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include "fsmc_sram_lld.h" + +#if (STM32_USE_FSMC_SRAM == TRUE) + +/////////////////////////////////////////////////////////////////////////////// +// Driver local definitions. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver exported variables. // +/////////////////////////////////////////////////////////////////////////////// +// SRAM1 driver identifier. +#if STM32_SRAM_USE_FSMC_SRAM1 +SRAMDriver SRAMD1; +#endif + +// SRAM2 driver identifier. +#if STM32_SRAM_USE_FSMC_SRAM2 +SRAMDriver SRAMD2; +#endif + +// SRAM3 driver identifier. +#if STM32_SRAM_USE_FSMC_SRAM3 +SRAMDriver SRAMD3; +#endif + +// SRAM4 driver identifier. +#if STM32_SRAM_USE_FSMC_SRAM4 +SRAMDriver SRAMD4; +#endif + +/////////////////////////////////////////////////////////////////////////////// +// Driver local variables and types. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver local functions. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver interrupt handlers. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver exported functions. // +/////////////////////////////////////////////////////////////////////////////// + +// Low level SRAM driver initialization. +void fsmcSramInit(void) { + + stm32FsmcInit(); + +#if STM32_SRAM_USE_FSMC_SRAM1 + SRAMD1.sram = FSMCD1.sram1; + SRAMD1.state = SRAM_STOP; +#endif /* STM32_SRAM_USE_FSMC_SRAM1 */ + +#if STM32_SRAM_USE_FSMC_SRAM2 + SRAMD2.sram = FSMCD1.sram2; + SRAMD2.state = SRAM_STOP; +#endif /* STM32_SRAM_USE_FSMC_SRAM2 */ + +#if STM32_SRAM_USE_FSMC_SRAM3 + SRAMD3.sram = FSMCD1.sram3; + SRAMD3.state = SRAM_STOP; +#endif /* STM32_SRAM_USE_FSMC_SRAM3 */ + +#if STM32_SRAM_USE_FSMC_SRAM4 + SRAMD4.sram = FSMCD1.sram4; + SRAMD4.state = SRAM_STOP; +#endif /* STM32_SRAM_USE_FSMC_SRAM4 */ +} + +// Configures and activates the SRAM peripheral. +// sramp pointer to the @p SRAMDriver object +// cfgp pointer to the @p SRAMConfig object +void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp) { + + if (FSMCD1.state == FSMC_STOP) + fsmc_start(&FSMCD1); + + osalDbgAssert((sramp->state == SRAM_STOP) || (sramp->state == SRAM_READY), + "invalid state"); + + if (sramp->state == SRAM_STOP) { + sramp->sram->BTR = cfgp->btr; + sramp->sram->BWTR = cfgp->bwtr; + sramp->sram->BCR = cfgp->bcr | FSMC_BCR_MBKEN; + sramp->state = SRAM_READY; + } +} + +// Deactivates the SRAM peripheral. +// sramp pointer to the @p SRAMDriver object +void fsmcSramStop(SRAMDriver *sramp) { + + if (sramp->state == SRAM_READY) { + uint32_t mask = FSMC_BCR_MBKEN; + +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) || \ + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) + mask |= FSMC_BCR_CCLKEN; +#endif + + sramp->sram->BCR &= ~mask; + sramp->state = SRAM_STOP; + } +} + +#endif // STM32_USE_FSMC_SRAM */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram_lld.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram_lld.h new file mode 100644 index 00000000..1d10d377 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/FSMCv1/fsmc_sram_lld.h @@ -0,0 +1,131 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2014 Uladzimir Pylinsky aka barthess +// See LICENSE file in the project root for full license information. +// + +#ifndef HAL_FSMC_SRAM_H_ +#define HAL_FSMC_SRAM_H_ + +#include "hal_stm32_fsmc.h" +#include + +#if (STM32_USE_FSMC_SRAM == TRUE) + +/////////////////////////////////////////////////////////////////////////////// +// Driver constants. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver pre-compile time settings. // +/////////////////////////////////////////////////////////////////////////////// + +// SRAM driver enable switch. +// If set to @p TRUE the support for SRAM1 is included. +#if !defined(STM32_SRAM_USE_FSMC_SRAM1) +#define STM32_SRAM_USE_FSMC_SRAM1 FALSE +#endif + +// SRAM driver enable switch. +// If set to @p TRUE the support for SRAM2 is included. +#if !defined(STM32_SRAM_USE_FSMC_SRAM2) +#define STM32_SRAM_USE_FSMC_SRAM2 FALSE +#endif + +// SRAM driver enable switch. +// If set to @p TRUE the support for SRAM3 is included. +#if !defined(STM32_SRAM_USE_FSMC_SRAM3) +#define STM32_SRAM_USE_FSMC_SRAM3 FALSE +#endif + +// SRAM driver enable switch. +// If set to @p TRUE the support for SRAM4 is included. +#if !defined(STM32_SRAM_USE_FSMC_SRAM4) +#define STM32_SRAM_USE_FSMC_SRAM4 FALSE +#endif + +/////////////////////////////////////////////////////////////////////////////// +// Derived constants and error checks. // +/////////////////////////////////////////////////////////////////////////////// + +#if !STM32_SRAM_USE_FSMC_SRAM1 && !STM32_SRAM_USE_FSMC_SRAM2 && \ + !STM32_SRAM_USE_FSMC_SRAM3 && !STM32_SRAM_USE_FSMC_SRAM4 +#error "SRAM driver activated but no SRAM peripheral assigned" +#endif + +#if (STM32_SRAM_USE_FSMC_SRAM1 || STM32_SRAM_USE_FSMC_SRAM2 || \ + STM32_SRAM_USE_FSMC_SRAM3 || STM32_SRAM_USE_FSMC_SRAM4) && !STM32_HAS_FSMC +#error "FSMC not present in the selected device" +#endif + +/////////////////////////////////////////////////////////////////////////////// +// Driver data structures and types. // +/////////////////////////////////////////////////////////////////////////////// + +// Driver state machine possible states. +typedef enum { + SRAM_UNINIT = 0, // Not initialized + SRAM_STOP = 1, // Stopped + SRAM_READY = 2, // Ready +} sramstate_t; + +// Type of a structure representing an NAND driver. +typedef struct SRAMDriver SRAMDriver; + +// Driver configuration structure. +// It could be empty on some architectures. +// Some bits in BCR register will be forced by driver. +typedef struct { + uint32_t bcr; + uint32_t btr; + uint32_t bwtr; +} SRAMConfig; + +// Structure representing an NAND driver. +struct SRAMDriver { + // Driver state + sramstate_t state; + + // Pointer to the FSMC SRAM registers block. + FSMC_SRAM_NOR_TypeDef *sram; +}; + +/////////////////////////////////////////////////////////////////////////////// +// Driver macros. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// External declarations. // +/////////////////////////////////////////////////////////////////////////////// + +#if STM32_SRAM_USE_FSMC_SRAM1 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD1; +#endif + +#if STM32_SRAM_USE_FSMC_SRAM2 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD2; +#endif + +#if STM32_SRAM_USE_FSMC_SRAM3 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD3; +#endif + +#if STM32_SRAM_USE_FSMC_SRAM4 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + + void fsmcSramInit(void); + void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp); + void fsmcSramStop(SRAMDriver *sramp); + +#ifdef __cplusplus +} +#endif + +#endif // STM32_USE_FSMC_SRAM + +#endif // HAL_FSMC_SRAM_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/ONEWIREv1/README.md b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/ONEWIREv1/README.md new file mode 100644 index 00000000..103714ee --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/ONEWIREv1/README.md @@ -0,0 +1,4 @@ +# 1-Wire v1 + +This driver supports all STM32 series. +The low level driver code is taken or heavily inspired in the 1-Wire SDK from MAXIM Semiconductors. diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/ONEWIREv1/onewire_lld.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/ONEWIREv1/onewire_lld.c new file mode 100644 index 00000000..8def10f5 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/ONEWIREv1/onewire_lld.c @@ -0,0 +1,320 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2016 STMicroelectronics. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#include +#include + +#if (HAL_USE_STM32_ONEWIRE == TRUE) + +#include +#include + +#if !NF_ONEWIRE_STM32_UART_USE_USART1 && !NF_ONEWIRE_STM32_UART_USE_USART2 && \ + !NF_ONEWIRE_STM32_UART_USE_USART3 && !NF_ONEWIRE_STM32_UART_USE_USART4 && \ + !NF_ONEWIRE_STM32_UART_USE_USART5 && !NF_ONEWIRE_STM32_UART_USE_USART6 && \ + !NF_ONEWIRE_STM32_UART_USE_USART7 && !NF_ONEWIRE_STM32_UART_USE_USART8 + +#error "1-Wire driver activated but no USART/UART peripheral assigned. Make sure to assign it @ target_nf_devices_onewire_config.h" +#endif + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief ONEWIRED1 driver identifier.*/ +ONEWIREDriver ONEWIRED1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +void uartSetSpeed(uint32_t speed) +{ + // stop UART, better do this before changing configuration + uartStop(ONEWIRED1.UartDriver); + + // default UART config + ONEWIRED1.UartConfig.speed = speed; + + uartStart(ONEWIRED1.UartDriver, &ONEWIRED1.UartConfig); +} + + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +static void TxEnd(UARTDriver *uartp) +{ + (void) uartp; + + //NATIVE_INTERRUPT_START + + //chSysLockFromISR(); + chBSemSignalI(&ONEWIRED1.TxCompleted); + // chSysUnlockFromISR(); + + //NATIVE_INTERRUPT_END +} + +static void RxEnd(UARTDriver *uartp) +{ + (void) uartp; + + //NATIVE_INTERRUPT_START + + // chSysLockFromISR(); + chBSemSignalI(&ONEWIRED1.RxCompleted); + // chSysUnlockFromISR(); + + // NATIVE_INTERRUPT_END +} + +static void RxErr(UARTDriver *uartp, uartflags_t e) +{ + (void) uartp; + (void) e; +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ONEWIRE driver initialization. + * + * @notapi + */ +void oneWire_lld_init(void) { + + ONEWIRED1.State = ONEWIRE_STOP; + + // reset UART config + memset(&ONEWIRED1.UartConfig, 0, sizeof(ONEWIRED1.UartConfig)); + + // set callbacks + ONEWIRED1.UartConfig.txend1_cb = TxEnd; + ONEWIRED1.UartConfig.rxend_cb = RxEnd; + ONEWIRED1.UartConfig.rxerr_cb = RxErr; + + // UART config + // half duplex mode + ONEWIRED1.UartConfig.cr3 = USART_CR3_HDSEL; + + #if (ONEWIRE_USE_MUTUAL_EXCLUSION == TRUE) + osalMutexObjectInit(&ONEWIRED1.Lock); + #endif + +} + +void oneWire_lld_start() { + + // set UART according to target config + // configure UART pins + // set buffers +#if NF_ONEWIRE_STM32_UART_USE_USART1 + ConfigPins_UART1(); + ONEWIRED1.UartDriver = &UARTD1; + ONEWIRED1.TxBuffer = Uart1_TxBuffer; + ONEWIRED1.RxBuffer = Uart1_RxBuffer; +#endif +#if NF_ONEWIRE_STM32_UART_USE_USART2 + ConfigPins_UART2(); + ONEWIRED1.UartDriver = &UARTD2; + ONEWIRED1.TxBuffer = Uart2_TxBuffer; + ONEWIRED1.RxBuffer = Uart2_RxBuffer; +#endif +#if NF_ONEWIRE_STM32_UART_USE_USART3 + ConfigPins_UART3(); + ONEWIRED1.UartDriver = &UARTD3; + ONEWIRED1.TxBuffer = Uart3_TxBuffer; + ONEWIRED1.RxBuffer = Uart3_RxBuffer; +#endif +#if NF_ONEWIRE_STM32_UART_USE_USART4 + ConfigPins_UART4(); + ONEWIRED1.UartDriver = &UARTD4; + ONEWIRED1.TxBuffer = Uart4_TxBuffer; + ONEWIRED1.RxBuffer = Uart4_RxBuffer; +#endif +#if NF_ONEWIRE_STM32_UART_USE_USART5 + ConfigPins_UART5(); + ONEWIRED1.UartDriver = &UARTD5; + ONEWIRED1.TxBuffer = Uart5_TxBuffer; + ONEWIRED1.RxBuffer = Uart5_RxBuffer; +#endif +#if NF_ONEWIRE_STM32_UART_USE_USART6 + ConfigPins_UART6(); + ONEWIRED1.UartDriver = &UARTD6; + ONEWIRED1.TxBuffer = Uart6_TxBuffer; + ONEWIRED1.RxBuffer = Uart6_RxBuffer; +#endif +#if NF_ONEWIRE_STM32_UART_USE_USART7 + ConfigPins_UART7(); + ONEWIRED1.UartDriver = &UARTD7; + ONEWIRED1.TxBuffer = Uart7_TxBuffer; + ONEWIRED1.RxBuffer = Uart7_RxBuffer; +#endif +#if NF_ONEWIRE_STM32_UART_USE_USART8 + ConfigPins_UART8(); + ONEWIRED1.UartDriver = &UARTD8; + ONEWIRED1.TxBuffer = Uart8_TxBuffer; + ONEWIRED1.RxBuffer = Uart8_RxBuffer; +#endif + + uartSetSpeed(9600); + + // driver is ready + ONEWIRED1.State = ONEWIRE_READY; +} + +void oneWire_lld_stop() { + + // stop UART + uartStop(ONEWIRED1.UartDriver); + + // driver is stopped + ONEWIRED1.State = ONEWIRE_STOP; +} + +uint8_t oneWire_lld_TouchReset(void) +{ + ONEWIRED1.TxBuffer[0] = 0xf0; + ONEWIRED1.RxBuffer[0] = 0; + + // flush DMA buffer to ensure cache coherency + // (only required for Cortex-M7) + cacheBufferFlush(&ONEWIRED1.TxBuffer[0], 1); + + // set UART baud rate to 9600bps (required to send the RESET condition to the 1-Wire bus) + uartSetSpeed(9600); + + chBSemReset(&ONEWIRED1.TxCompleted, TRUE); + chBSemReset(&ONEWIRED1.RxCompleted, TRUE); + uartStartReceive (ONEWIRED1.UartDriver, 1 , &ONEWIRED1.RxBuffer[0]); + uartStartSend (ONEWIRED1.UartDriver, 1, &ONEWIRED1.TxBuffer[0]); + chThdSleepMilliseconds(10); + chBSemWait (&ONEWIRED1.TxCompleted); + chBSemWait (&ONEWIRED1.RxCompleted); + + // invalidate cache over read buffer to ensure that content from DMA is read + // (only required for Cortex-M7) + cacheBufferInvalidate(&ONEWIRED1.RxBuffer[0], 1); + + // set UART baud rate to 115200bps (normal comm is performed at this baud rate) + uartSetSpeed(115200); + + // check for presence pulse + return (ONEWIRED1.TxBuffer[0] != ONEWIRED1.RxBuffer[0]); +} + +bool oneWire_lld_TouchBit(bool sendbit) +{ + // need to send 1-Wire write 1 or 0 according to sendbit + ONEWIRED1.TxBuffer[0] = sendbit ? IWIRE_WR1 : IWIRE_WR0; + + // flush DMA buffer to ensure cache coherency + // (only required for Cortex-M7) + cacheBufferFlush(&ONEWIRED1.TxBuffer[0], 1); + + chBSemReset(&ONEWIRED1.RxCompleted, TRUE); + chBSemReset(&ONEWIRED1.TxCompleted, TRUE); + uartStartReceive (ONEWIRED1.UartDriver, 1 , &ONEWIRED1.RxBuffer[0]); + uartStartSend(ONEWIRED1.UartDriver, 1, &ONEWIRED1.TxBuffer[0]); + chThdSleepMilliseconds(0.1); + chBSemWait (&ONEWIRED1.TxCompleted); + chBSemWait (&ONEWIRED1.RxCompleted); + + // invalidate cache over read buffer to ensure that content from DMA is read + // (only required for Cortex-M7) + cacheBufferInvalidate(&ONEWIRED1.RxBuffer[0], 1); + + // interpret 1-Wire reply + return (ONEWIRED1.RxBuffer[0] == 0xff); +} + +uint8_t oneWire_lld_TouchByte(uint8_t sendbyte) +{ + uint8_t send_mask = 0x01, result = 0; + uint8_t i = 0; + + // send byte + while (send_mask) + { + if (sendbyte & send_mask) + { + // if transmit bit is 1 + ONEWIRED1.TxBuffer[i] = IWIRE_WR1; + } + else + { + // if transmit bit is 0 + ONEWIRED1.TxBuffer[i] = IWIRE_WR0; + } + + i++; + + // rotates the position mask transmit bit + send_mask<<=1; + }; + + + // flush DMA buffer to ensure cache coherency + // (only required for Cortex-M7) + cacheBufferFlush(&ONEWIRED1.TxBuffer[0], 8); + + chBSemReset(&ONEWIRED1.RxCompleted, TRUE); + chBSemReset(&ONEWIRED1.TxCompleted, TRUE); + uartStartReceive (ONEWIRED1.UartDriver, 8 , &ONEWIRED1.RxBuffer[0]); + uartStartSend (ONEWIRED1.UartDriver, 8, &ONEWIRED1.TxBuffer[0]); + chThdSleepMilliseconds(0.1); + chBSemWait (&ONEWIRED1.TxCompleted); + chBSemWait (&ONEWIRED1.RxCompleted); + + // invalidate cache over read buffer to ensure that content from DMA is read + // (only required for Cortex-M7) + cacheBufferInvalidate(&ONEWIRED1.RxBuffer[0], 8); + + // reset send mask to interpret the reply + send_mask = 0x01; + + for (uint32_t i = 0; i < 8; i++) + { + if (ONEWIRED1.RxBuffer[i] == 0xff) + { + result |= send_mask; + } + + send_mask<<=1; + } + + return result; +} + +#if (ONEWIRE_USE_MUTUAL_EXCLUSION == TRUE) + +void oneWire_lld_aquire() +{ + osalMutexLock(&ONEWIRED1.Lock); +} + +void oneWire_lld_release() +{ + osalMutexUnlock(&ONEWIRED1.Lock); +} + +#endif + +#endif /* HAL_USE_STM32_ONEWIRE */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/ONEWIREv1/onewire_lld.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/ONEWIREv1/onewire_lld.h new file mode 100644 index 00000000..270c3d32 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/ONEWIREv1/onewire_lld.h @@ -0,0 +1,138 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2016 STMicroelectronics. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef ONEWIRE_LLD_H +#define ONEWIRE_LLD_H + +#if (HAL_USE_STM32_ONEWIRE == TRUE) + +#include "hal_uart_lld.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +//character to send on the UART to mimic 1-Wire bus signals +#define IWIRE_WR0 0x00 // 1-Wire write 0 time slot +#define IWIRE_WR1 0xFF // 1-Wire write 1 time slot +#define IWIRE_RD 0xFF // 1-Wire read time slot + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Structure representing an ONEWIRE driver. + */ +typedef struct ONEWIREDriver { + // UART to use for 1-Wire comm + UARTDriver* UartDriver; + + // UART config struct + UARTConfig UartConfig; + + // Driver state. + oneWireState State; + + // TX buffer + uint8_t* TxBuffer; + + // RX buffer + uint8_t* RxBuffer; + + // semaphore for Tx operation completed + binary_semaphore_t TxCompleted; + + // semaphore for Rx operation completed + binary_semaphore_t RxCompleted; + + +#if ONEWIRE_USE_MUTUAL_EXCLUSION + // Mutex protecting the peripheral + mutex_t Lock; +#endif // ONEWIRE_USE_MUTUAL_EXCLUSION + +} ONEWIREDriver; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void oneWire_lld_init(void); + void oneWire_lld_start(void); + void oneWire_lld_stop(void); + void oneWire_lld_UART9600(void); + void oneWire_lld_UART115200(void); + uint8_t oneWire_lld_TouchReset(void); + bool oneWire_lld_TouchBit(bool sendbit); + uint8_t oneWire_lld_TouchByte(uint8_t sendbyte); + +#if (ONEWIRE_USE_MUTUAL_EXCLUSION == TRUE) + + void oneWire_lld_aquire(); + void oneWire_lld_release(); + +#endif + + void ConfigPins_UART1(void); + void ConfigPins_UART2(void); + void ConfigPins_UART3(void); + void ConfigPins_UART4(void); + void ConfigPins_UART5(void); + void ConfigPins_UART6(void); + void ConfigPins_UART7(void); + void ConfigPins_UART8(void); + + ///////////////////////////////////// + // UART Tx buffers // + // these live in the target folder // + ///////////////////////////////////// + extern uint8_t Uart1_TxBuffer[]; + extern uint8_t Uart2_TxBuffer[]; + extern uint8_t Uart3_TxBuffer[]; + extern uint8_t Uart4_TxBuffer[]; + extern uint8_t Uart5_TxBuffer[]; + extern uint8_t Uart6_TxBuffer[]; + extern uint8_t Uart7_TxBuffer[]; + extern uint8_t Uart8_TxBuffer[]; + + ///////////////////////////////////// + // UART Rx buffers // + // these live in the target folder // + ///////////////////////////////////// + extern uint8_t Uart1_RxBuffer[]; + extern uint8_t Uart2_RxBuffer[]; + extern uint8_t Uart3_RxBuffer[]; + extern uint8_t Uart4_RxBuffer[]; + extern uint8_t Uart5_RxBuffer[]; + extern uint8_t Uart6_RxBuffer[]; + extern uint8_t Uart7_RxBuffer[]; + extern uint8_t Uart8_RxBuffer[]; + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_STM32_ONEWIRE */ + +#endif /* ONEWIRE_LLD_H */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/QSPIv1/README.md b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/QSPIv1/README.md new file mode 100644 index 00000000..29f0f78b --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/QSPIv1/README.md @@ -0,0 +1,5 @@ +# QSPI v1 + +This driver supports all STM32 series. +The low level driver code is taken or heavily inspired in the STCube MX HAL drivers from STMicroelectronics. +The ChibiOS driver follows the 'standard' template driver model. diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/QSPIv1/qspi_lld.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/QSPIv1/qspi_lld.c new file mode 100644 index 00000000..58d1e908 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/QSPIv1/qspi_lld.c @@ -0,0 +1,98 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) 2016 STMicroelectronics. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//possible help: +// https://github.com/xpacks/stm32f7-hal/blob/xpack/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c + +#include +#include + +#if (HAL_USE_STM32_QSPI == TRUE) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief QSPID1 driver identifier.*/ +QSPI_HandleTypeDef QSPID1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level QSPI driver initialization. + * + * @notapi + */ +void qspi_lld_init() +{ + +} + +void qspi_lld_start(QSPI_HandleTypeDef* qspi) +{ + QSPI_CLK_ENABLE(); + QSPI_FORCE_RESET(); + QSPI_RELEASE_RESET(); + + nvicEnableVector(STM32_QUADSPI1_NUMBER, STM32_QSPI_QUADSPI1_IRQ_PRIORITY); + + qspi->Instance = QUADSPI; + + qspi->State = HAL_QSPI_STATE_RESET; + + // driver is ready + qspi->State = HAL_QSPI_STATE_READY; +} + +void qspi_lld_stop(QSPI_HandleTypeDef* qspi) +{ + /* If in ready state then disables the QUADSPI clock.*/ + if (qspi->State == HAL_QSPI_STATE_READY) + { + /* WSPI disable.*/ + qspi->Instance->CR = 0U; + + // /* Releasing the DMA.*/ + // dmaStreamFreeI(wspip->dma); + // wspip->dma = NULL; + + /* Stopping involved clocks.*/ + rccDisableQUADSPI1(); + } + + // driver is stopped + qspi->State = HAL_QSPI_STATE_RESET; +} + +// QSPI interrupt handler, following ChibiOS style +OSAL_IRQ_HANDLER(STM32_QUADSPI1_HANDLER) { + + OSAL_IRQ_PROLOGUE(); + + HAL_QSPI_IRQHandler(&QSPID1); + + OSAL_IRQ_EPILOGUE(); +} + +#endif /* HAL_USE_STM32_QSPI */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/QSPIv1/qspi_lld.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/QSPIv1/qspi_lld.h new file mode 100644 index 00000000..cb4ab3bd --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/QSPIv1/qspi_lld.h @@ -0,0 +1,72 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) 2016 STMicroelectronics. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//Help: https://github.com/xpacks/stm32f7-hal/blob/xpack/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h + +#ifndef QSPI_LLD_H +#define QSPI_LLD_H + +#include + +#if defined(STM32F4XX) +#include +#endif +#if defined(STM32F7XX) +#include +#endif + +#if (HAL_USE_STM32_QSPI == TRUE) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief QUADSPI1 interrupt priority level setting. + */ +#if !defined(STM32_QSPI_QUADSPI1_IRQ_PRIORITY) +#define STM32_QSPI_QUADSPI1_IRQ_PRIORITY 10 +#endif + +#define QSPI_CLK_ENABLE() __HAL_RCC_QSPI_CLK_ENABLE() +#define QSPI_CLK_DISABLE() __HAL_RCC_QSPI_CLK_DISABLE() +#define QSPI_FORCE_RESET() __HAL_RCC_QSPI_FORCE_RESET() +#define QSPI_RELEASE_RESET() __HAL_RCC_QSPI_RELEASE_RESET() + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern QSPI_HandleTypeDef QSPID1; + +#ifdef __cplusplus +extern "C" { +#endif + + void qspi_lld_init(void); + void qspi_lld_start(QSPI_HandleTypeDef* qspip); + void qspi_lld_stop(QSPI_HandleTypeDef* qspi); + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_STM32_QSPI */ + +#endif /* QSPI_LLD_H */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/RNGv1/README.md b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/RNGv1/README.md new file mode 100644 index 00000000..fe86a3e1 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/RNGv1/README.md @@ -0,0 +1,8 @@ +# RNG v1 + +This driver supports all STM32 series except for the STM32F0 series. +The low level driver code is taken or heavily inspired in the STCube MX HAL drivers from STMicroelectronics. +The ChibiOS driver follows the 'standard' template driver model. + +**NOTE:** unlike all the other drivers and because most SMT32 chips (**Except the STM32F0 series**) have a RNG unit, the default for this driver is to be included. +If for some reason the developer chooses NOT to include support, they have to add `#define HAL_USE_STM32_RNG == FALSE` preferably in the file halconf_nf.h. diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/RNGv1/rng_lld.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/RNGv1/rng_lld.c new file mode 100644 index 00000000..33a3b532 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/RNGv1/rng_lld.c @@ -0,0 +1,128 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2016 STMicroelectronics. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +//possible help: +// https://github.com/xpacks/stm32f7-hal/blob/xpack/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rng.c +// https://github.com/ChibiOS/ChibiOS-Contrib/blob/master/os/hal/src/hal_rng.c + +#include +#include + +#if (HAL_USE_STM32_RNG == TRUE) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief RNGD1 driver identifier.*/ +RNGDriver RNGD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +#define RNG_TIMEOUT_VALUE 200 + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level RNG driver initialization. + * + * @notapi + */ +void rng_lld_init(void) { + RNGD1.State = RNG_STOP; + + #if (RNG_USE_MUTUAL_EXCLUSION == TRUE) + osalMutexObjectInit(&RNGD1.Lock); + #endif + + RNGD1.Instance = RNG; +} + + +void rng_lld_start() { + + rccEnableRNG(FALSE) + + // Enables the RNG peripheral. + __RNG_ENABLE(RNGD1); + + // driver is ready + RNGD1.State = RNG_READY; +} + + +void rng_lld_stop() { + + /* Disable the RNG Peripheral */ + CLEAR_BIT(RNGD1.Instance->CR, RNG_CR_IE | RNG_CR_RNGEN); + + /* Clear RNG interrupt status flags */ + CLEAR_BIT(RNGD1.Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS); + + rccDisableRNG(); + + // driver is stopped + RNGD1.State = RNG_STOP; +} + + +uint32_t rng_lld_GenerateRandomNumber() { + systime_t start = chVTGetSystemTime(); + systime_t end = start + TIME_MS2I(RNG_TIMEOUT_VALUE); + + + /* Check if data register contains valid random data */ + while(__RNG_GET_FLAG(RNGD1, RNG_FLAG_DRDY) == RESET) + { + if(!chVTIsSystemTimeWithin(start, end)) + { + return 0; + } + + } + + /* Get a 32bit Random number */ + RNGD1.RandomNumber = RNGD1.Instance->DR; + + return RNGD1.RandomNumber; +} + + +uint32_t rng_lld_GetLastRandomNumber() { + return RNGD1.RandomNumber; +} + + +#if (RNG_USE_MUTUAL_EXCLUSION == TRUE) + +void rng_lld_aquire() { + osalMutexLock(&RNGD1.Lock); +} + +void rng_lld_release() { + osalMutexUnlock(&RNGD1.Lock); +} + +#endif + +#endif /* HAL_USE_STM32_RNG */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/RNGv1/rng_lld.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/RNGv1/rng_lld.h new file mode 100644 index 00000000..a7b9d892 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/STM32/LLD/RNGv1/rng_lld.h @@ -0,0 +1,126 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2016 STMicroelectronics. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +//Help: https://github.com/xpacks/stm32f7-hal/blob/xpack/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rng.h + +#ifndef RNG_LLD_H +#define RNG_LLD_H + +#include "stm32_registry.h" +#include +#include + +#if (HAL_USE_STM32_RNG == TRUE) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +// RNG Flag definitions +#define RNG_FLAG_DRDY RNG_SR_DRDY /*!< Data ready */ +#define RNG_FLAG_CECS RNG_SR_CECS /*!< Clock error current status */ +#define RNG_FLAG_SECS RNG_SR_SECS /*!< Seed error current status */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Structure representing an RNG driver. + */ +typedef struct RNGDriver { + //Register base address + RNG_TypeDef *Instance; + + // Driver state. + rngState State; + + // Last Generated random number. + uint32_t RandomNumber; + +#if RNG_USE_MUTUAL_EXCLUSION + // Mutex protecting the peripheral + mutex_t Lock; +#endif // RNG_USE_MUTUAL_EXCLUSION + +} RNGDriver; + +// From STMicroelectronics Cube HAL +///////////////////////////////////////////////////////////// + +#if defined(STM32L0XX) +// this series uses different names for the buses + +#define rccEnableRNG(lp) rccEnableAPB2(RCC_AHBENR_RNGEN, lp) +#define rccDisableRNG() rccDisableAPB2(RCC_AHBENR_RNGEN) + +#else + +#define rccEnableRNG(lp) rccEnableAHB2(RCC_AHB2ENR_RNGEN, lp) +#define rccDisableRNG() rccDisableAHB2(RCC_AHB2ENR_RNGEN) + +#endif + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +// Enables the RNG peripheral. +#define __RNG_ENABLE(__HANDLE__) ((__HANDLE__).Instance->CR |= RNG_CR_RNGEN) + +// Disables the RNG peripheral. +#define __RNG_DISABLE(__HANDLE__) ((__HANDLE__).Instance->CR &= ~RNG_CR_RNGEN) + +// Check the selected RNG flag status. +// This parameter can be one of the following values: +// @arg RNG_FLAG_DRDY: Data ready +// @arg RNG_FLAG_CECS: Clock error current status +// @arg RNG_FLAG_SECS: Seed error current status +#define __RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__).Instance->SR & (__FLAG__)) == (__FLAG__)) + + + // Clears the selected RNG flag status. + // WARNING: This is a dummy macro for HAL code alignment, + // flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only. +#define __RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void rng_lld_init(void); + void rng_lld_start(void); + void rng_lld_stop(void); + uint32_t rng_lld_GenerateRandomNumber(void); + uint32_t rng_lld_GetLastRandomNumber(void); + +#if (RNG_USE_MUTUAL_EXCLUSION == TRUE) + + void rng_lld_aquire(); + void rng_lld_release(); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_STM32_RNG */ + +#endif /* RNG_LLD_H */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPIO/hal_pal_lld.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPIO/hal_pal_lld.c new file mode 100644 index 00000000..6349b509 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPIO/hal_pal_lld.c @@ -0,0 +1,432 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/** + * @file GPIO/hal_pal_lld.c + * @brief TICC3200 PAL subsystem low level driver. + * + * @addtogroup PAL + * @{ + */ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#if TICC3200_HAS_GPIOA || defined(__DOXYGEN__) +#define GPIOA_BIT (1 << 0) +#if TICC3200_GPIO_GPIOA_USE_AHB && defined(TM4C123x) +#define GPIOA_AHB_BIT (1 << 0) +#else +#define GPIOA_AHB_BIT 0 +#endif +#else +#define GPIOA_BIT 0 +#define GPIOA_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOB || defined(__DOXYGEN__) +#define GPIOB_BIT (1 << 1) +#if TICC3200_GPIO_GPIOB_USE_AHB && defined(TM4C123x) +#define GPIOB_AHB_BIT (1 << 1) +#else +#define GPIOB_AHB_BIT 0 +#endif +#else +#define GPIOB_BIT 0 +#define GPIOB_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOC || defined(__DOXYGEN__) +#define GPIOC_BIT (1 << 2) +#if TICC3200_GPIO_GPIOC_USE_AHB && defined(TM4C123x) +#define GPIOC_AHB_BIT (1 << 2) +#else +#define GPIOC_AHB_BIT 0 +#endif +#else +#define GPIOC_BIT 0 +#define GPIOC_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOD || defined(__DOXYGEN__) +#define GPIOD_BIT (1 << 3) +#if TICC3200_GPIO_GPIOD_USE_AHB && defined(TM4C123x) +#define GPIOD_AHB_BIT (1 << 3) +#else +#define GPIOD_AHB_BIT 0 +#endif +#else +#define GPIOD_BIT 0 +#define GPIOD_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOE || defined(__DOXYGEN__) +#define GPIOE_BIT (1 << 4) +#if TICC3200_GPIO_GPIOE_USE_AHB && defined(TM4C123x) +#define GPIOE_AHB_BIT (1 << 4) +#else +#define GPIOE_AHB_BIT 0 +#endif +#else +#define GPIOE_BIT 0 +#define GPIOE_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOF || defined(__DOXYGEN__) +#define GPIOF_BIT (1 << 5) +#if TICC3200_GPIO_GPIOF_USE_AHB && defined(TM4C123x) +#define GPIOF_AHB_BIT (1 << 5) +#else +#define GPIOF_AHB_BIT 0 +#endif +#else +#define GPIOF_BIT 0 +#define GPIOF_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOG || defined(__DOXYGEN__) +#define GPIOG_BIT (1 << 6) +#if TICC3200_GPIO_GPIOG_USE_AHB && defined(TM4C123x) +#define GPIOG_AHB_BIT (1 << 6) +#else +#define GPIOG_AHB_BIT 0 +#endif +#else +#define GPIOG_BIT 0 +#define GPIOG_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOH || defined(__DOXYGEN__) +#define GPIOH_BIT (1 << 7) +#if TICC3200_GPIO_GPIOH_USE_AHB && defined(TM4C123x) +#define GPIOH_AHB_BIT (1 << 7) +#else +#define GPIOH_AHB_BIT 0 +#endif +#else +#define GPIOH_BIT 0 +#define GPIOH_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOJ || defined(__DOXYGEN__) +#define GPIOJ_BIT (1 << 8) +#if TICC3200_GPIO_GPIOJ_USE_AHB && defined(TM4C123x) +#define GPIOJ_AHB_BIT (1 << 8) +#else +#define GPIOJ_AHB_BIT 0 +#endif +#else +#define GPIOJ_BIT 0 +#define GPIOJ_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOK || defined(__DOXYGEN__) +#define GPIOK_BIT (1 << 9) +#define GPIOK_AHB_BIT (1 << 9) +#else +#define GPIOK_BIT 0 +#define GPIOK_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOL || defined(__DOXYGEN__) +#define GPIOL_BIT (1 << 10) +#define GPIOL_AHB_BIT (1 << 10) +#else +#define GPIOL_BIT 0 +#define GPIOL_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOM || defined(__DOXYGEN__) +#define GPIOM_BIT (1 << 11) +#define GPIOM_AHB_BIT (1 << 11) +#else +#define GPIOM_BIT 0 +#define GPIOM_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPION || defined(__DOXYGEN__) +#define GPION_BIT (1 << 12) +#define GPION_AHB_BIT (1 << 12) +#else +#define GPION_BIT 0 +#define GPION_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOP || defined(__DOXYGEN__) +#define GPIOP_BIT (1 << 13) +#define GPIOP_AHB_BIT (1 << 13) +#else +#define GPIOP_BIT 0 +#define GPIOP_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOQ || defined(__DOXYGEN__) +#define GPIOQ_BIT (1 << 14) +#define GPIOQ_AHB_BIT (1 << 14) +#else +#define GPIOQ_BIT 0 +#define GPIOQ_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOR || defined(__DOXYGEN__) +#define GPIOR_BIT (1 << 15) +#define GPIOR_AHB_BIT (1 << 15) +#else +#define GPIOR_BIT 0 +#define GPIOR_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOS || defined(__DOXYGEN__) +#define GPIOS_BIT (1 << 16) +#define GPIOS_AHB_BIT (1 << 16) +#else +#define GPIOS_BIT 0 +#define GPIOS_AHB_BIT 0 +#endif + +#if TICC3200_HAS_GPIOT || defined(__DOXYGEN__) +#define GPIOT_BIT (1 << 17) +#define GPIOT_AHB_BIT (1 << 17) +#else +#define GPIOT_BIT 0 +#define GPIOT_AHB_BIT 0 +#endif + +#define RCGCGPIO_MASK (GPIOA_BIT | GPIOB_BIT | GPIOC_BIT | GPIOD_BIT | \ + GPIOE_BIT | GPIOF_BIT | GPIOG_BIT | GPIOH_BIT | \ + GPIOJ_BIT | GPIOK_BIT | GPIOL_BIT | GPIOM_BIT | \ + GPION_BIT | GPIOP_BIT | GPIOQ_BIT | GPIOR_BIT | \ + GPIOS_BIT | GPIOR_BIT) + +#define GPIOHBCTL_MASK (GPIOA_AHB_BIT | GPIOB_AHB_BIT | GPIOC_AHB_BIT | \ + GPIOD_AHB_BIT | GPIOE_AHB_BIT | GPIOF_AHB_BIT | \ + GPIOG_AHB_BIT | GPIOH_AHB_BIT | GPIOJ_AHB_BIT | \ + GPIOK_AHB_BIT | GPIOL_AHB_BIT | GPIOM_AHB_BIT | \ + GPION_AHB_BIT | GPIOP_AHB_BIT | GPIOQ_AHB_BIT | \ + GPIOR_AHB_BIT | GPIOS_AHB_BIT | GPIOT_AHB_BIT) + +#define GPIOC_JTAG_MASK (0x0F) +#define GPIOD_NMI_MASK (0x80) +#define GPIOF_NMI_MASK (0x01) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Initializes the port with the port configuration. + * + * @param[in] port the port identifier + * @param[in] config the port configuration + */ +static void gpio_init(ioportid_t port, const tiva_gpio_setup_t *config) +{ + HWREG(port + GPIO_O_DATA) = config->data; + HWREG(port + GPIO_O_DIR) = config->dir; + HWREG(port + GPIO_O_AFSEL) = config->afsel; + HWREG(port + GPIO_O_DR2R) = config->dr2r; + HWREG(port + GPIO_O_DR4R) = config->dr4r; + HWREG(port + GPIO_O_DR8R) = config->dr8r; + HWREG(port + GPIO_O_ODR) = config->odr; + HWREG(port + GPIO_O_PUR) = config->pur; + HWREG(port + GPIO_O_PDR) = config->pdr; + HWREG(port + GPIO_O_SLR) = config->slr; + HWREG(port + GPIO_O_DEN) = config->den; + HWREG(port + GPIO_O_AMSEL) = config->amsel; + HWREG(port + GPIO_O_PCTL) = config->pctl; +} + +/** + * @brief Unlocks the masked pins of the GPIO peripheral. + * @note This function is only useful for PORTC0-3, PORTD7 and PORTF0. + * + * @param[in] port the port identifier + * @param[in] mask the pin mask + */ +static void gpio_unlock(ioportid_t port, ioportmask_t mask) +{ + + HWREG(port + GPIO_O_LOCK) = GPIO_LOCK_KEY; + HWREG(port + GPIO_O_CR) = mask; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Tiva I/O ports configuration. + * @details Ports A-F (G, H, J, K, L, M, N, P, Q, R, S, T) clocks enabled. + * + * @param[in] config the Tiva ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) +{ + /* + * Enables all GPIO clocks. + */ + HWREG(SYSCTL_RCGCGPIO) = RCGCGPIO_MASK; +#if defined(TM4C123x) + HWREG(SYSCTL_GPIOHBCTL) = GPIOHBCTL_MASK; +#endif + + /* Wait until all GPIO modules are ready */ + while (!((HWREG(SYSCTL_PRGPIO) & RCGCGPIO_MASK) == RCGCGPIO_MASK)) + ; + +#if TICC3200_HAS_GPIOA + gpio_init(GPIOA, &config->PAData); +#endif +#if TICC3200_HAS_GPIOB + gpio_init(GPIOB, &config->PBData); +#endif +#if TICC3200_HAS_GPIOC + /* Unlock JTAG pins.*/ + gpio_unlock(GPIOC, GPIOC_JTAG_MASK); + gpio_init(GPIOC, &config->PCData); +#endif +#if TICC3200_HAS_GPIOD + /* Unlock NMI pin.*/ + gpio_unlock(GPIOD, GPIOD_NMI_MASK); + gpio_init(GPIOD, &config->PDData); +#endif +#if TICC3200_HAS_GPIOE + gpio_init(GPIOE, &config->PEData); +#endif +#if TICC3200_HAS_GPIOF + /* Unlock NMI pin.*/ + gpio_unlock(GPIOF, GPIOF_NMI_MASK); + gpio_init(GPIOF, &config->PFData); +#endif +#if TICC3200_HAS_GPIOG || defined(__DOXYGEN__) + gpio_init(GPIOG, &config->PGData); +#endif +#if TICC3200_HAS_GPIOH || defined(__DOXYGEN__) + gpio_init(GPIOH, &config->PHData); +#endif +#if TICC3200_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_init(GPIOJ, &config->PJData); +#endif +#if TICC3200_HAS_GPIOK || defined(__DOXYGEN__) + gpio_init(GPIOK, &config->PKData); +#endif +#if TICC3200_HAS_GPIOL || defined(__DOXYGEN__) + gpio_init(GPIOL, &config->PLData); +#endif +#if TICC3200_HAS_GPIOM || defined(__DOXYGEN__) + gpio_init(GPIOM, &config->PMData); +#endif +#if TICC3200_HAS_GPION || defined(__DOXYGEN__) + gpio_init(GPION, &config->PNData); +#endif +#if TICC3200_HAS_GPIOP || defined(__DOXYGEN__) + gpio_init(GPIOP, &config->PPData); +#endif +#if TICC3200_HAS_GPIOQ || defined(__DOXYGEN__) + gpio_init(GPIOQ, &config->PQData); +#endif +#if TICC3200_HAS_GPIOR || defined(__DOXYGEN__) + gpio_init(GPIOR, &config->PRData); +#endif +#if TICC3200_HAS_GPIOS || defined(__DOXYGEN__) + gpio_init(GPIOS, &config->PSData); +#endif +#if TICC3200_HAS_GPIOT || defined(__DOXYGEN__) + gpio_init(GPIOT, &config->PTData); +#endif +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode) +{ + uint32_t dir = (mode & PAL_TICC3200_DIR_MASK) >> 0; + uint32_t afsel = (mode & PAL_TICC3200_AFSEL_MASK) >> 1; + uint32_t dr2r = (mode & PAL_TICC3200_DR2R_MASK) >> 2; + uint32_t dr4r = (mode & PAL_TICC3200_DR4R_MASK) >> 3; + uint32_t dr8r = (mode & PAL_TICC3200_DR8R_MASK) >> 4; + uint32_t odr = (mode & PAL_TICC3200_ODR_MASK) >> 5; + uint32_t pur = (mode & PAL_TICC3200_PUR_MASK) >> 6; + uint32_t pdr = (mode & PAL_TICC3200_PDR_MASK) >> 7; + uint32_t slr = (mode & PAL_TICC3200_SLR_MASK) >> 8; + uint32_t den = (mode & PAL_TICC3200_DEN_MASK) >> 9; + uint32_t amsel = (mode & PAL_TICC3200_AMSEL_MASK) >> 10; + uint32_t pctl = (mode & PAL_TICC3200_PCTL_MASK) >> 11; + uint32_t bit = 0; + + while(TRUE) { + uint32_t pctl_mask = (7 << (4 * bit)); + uint32_t bit_mask = (1 << bit); + + if ((mask & 1) != 0) { + HWREG(port + GPIO_O_DIR) = (HWREG(port + GPIO_O_DIR) & ~bit_mask) | dir; + HWREG(port + GPIO_O_AFSEL) = (HWREG(port + GPIO_O_AFSEL) & ~bit_mask) | afsel; + HWREG(port + GPIO_O_DR2R) = (HWREG(port + GPIO_O_DR2R) & ~bit_mask) | dr2r; + HWREG(port + GPIO_O_DR4R) = (HWREG(port + GPIO_O_DR4R) & ~bit_mask) | dr4r; + HWREG(port + GPIO_O_DR8R) = (HWREG(port + GPIO_O_DR8R) & ~bit_mask) | dr8r; + HWREG(port + GPIO_O_ODR) = (HWREG(port + GPIO_O_ODR) & ~bit_mask) | odr; + HWREG(port + GPIO_O_PUR) = (HWREG(port + GPIO_O_PUR) & ~bit_mask) | pur; + HWREG(port + GPIO_O_PDR) = (HWREG(port + GPIO_O_PDR) & ~bit_mask) | pdr; + HWREG(port + GPIO_O_SLR) = (HWREG(port + GPIO_O_SLR) & ~bit_mask) | slr; + HWREG(port + GPIO_O_DEN) = (HWREG(port + GPIO_O_DEN) & ~bit_mask) | den; + HWREG(port + GPIO_O_AMSEL) = (HWREG(port + GPIO_O_AMSEL) & ~bit_mask) | amsel; + HWREG(port + GPIO_O_PCTL) = (HWREG(port + GPIO_O_PCTL) & ~pctl_mask) | pctl; + } + + mask >>= 1; + if (!mask) { + return; + } + + dir <<= 1; + afsel <<= 1; + dr2r <<= 1; + dr4r <<= 1; + dr8r <<= 1; + odr <<= 1; + pur <<= 1; + pdr <<= 1; + slr <<= 1; + den <<= 1; + amsel <<= 1; + pctl <<= 4; + + bit++; + } +} + +#endif /* HAL_USE_PAL */ + +/** + * @} + */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPIO/hal_pal_lld.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPIO/hal_pal_lld.h new file mode 100644 index 00000000..f73d22fb --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPIO/hal_pal_lld.h @@ -0,0 +1,806 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/** + * @file GPIO/hal_pal_lld.h + * @brief TICC3200 PAL subsystem low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef HAL_PAL_LLD_H +#define HAL_PAL_LLD_H + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_RESET +#undef PAL_MODE_UNCONNECTED +#undef PAL_MODE_INPUT +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_OUTPUT_PUSHPULL +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/** + * @name TICC3200 specific I/O mode flags + * @{ + */ +#define PAL_TICC3200_DIR_MASK (1 << 0) +#define PAL_TICC3200_DIR_INPUT (0 << 0) +#define PAL_TICC3200_DIR_OUTPUT (1 << 0) + +#define PAL_TICC3200_AFSEL_MASK (1 << 1) +#define PAL_TICC3200_AFSEL_GPIO (0 << 1) +#define PAL_TICC3200_AFSEL_ALTERNATE (1 << 1) + +#define PAL_TICC3200_DR2R_MASK (1 << 2) +#define PAL_TICC3200_DR2R_DISABLE (0 << 2) +#define PAL_TICC3200_DR2R_ENABLE (1 << 2) + +#define PAL_TICC3200_DR4R_MASK (1 << 3) +#define PAL_TICC3200_DR4R_DISABLE (0 << 3) +#define PAL_TICC3200_DR4R_ENABLE (1 << 3) + +#define PAL_TICC3200_DR8R_MASK (1 << 4) +#define PAL_TICC3200_DR8R_DISABLE (0 << 4) +#define PAL_TICC3200_DR8R_ENABLE (1 << 4) + +#define PAL_TICC3200_ODR_MASK (1 << 5) +#define PAL_TICC3200_ODR_PUSHPULL (0 << 5) +#define PAL_TICC3200_ODR_OPENDRAIN (1 << 5) + +#define PAL_TICC3200_PUR_MASK (1 << 6) +#define PAL_TICC3200_PUR_DISABLE (0 << 6) +#define PAL_TICC3200_PUR_ENABLE (1 << 6) + +#define PAL_TICC3200_PDR_MASK (1 << 7) +#define PAL_TICC3200_PDR_DISABLE (0 << 7) +#define PAL_TICC3200_PDR_ENABLE (1 << 7) + +#define PAL_TICC3200_SLR_MASK (1 << 8) +#define PAL_TICC3200_SLR_DISABLE (0 << 8) +#define PAL_TICC3200_SLR_ENABLE (1 << 8) + +#define PAL_TICC3200_DEN_MASK (1 << 9) +#define PAL_TICC3200_DEN_DISABLE (0 << 9) +#define PAL_TICC3200_DEN_ENABLE (1 << 9) + +#define PAL_TICC3200_AMSEL_MASK (1 << 10) +#define PAL_TICC3200_AMSEL_DISABLE (0 << 10) +#define PAL_TICC3200_AMSEL_ENABLE (1 << 10) + +#define PAL_TICC3200_PCTL_MASK (7 << 11) +#define PAL_TICC3200_PCTL(n) ((n) << 11) + +/** + * @brief Alternate function. + * + * @param[in] n alternate function selector + */ +#define PAL_MODE_ALTERNATE(n) (PAL_TICC3200_AFSEL_ALTERNATE | \ + PAL_TICC3200_PCTL(n)) +/** @} */ + +/** + * @name Standard I/O mode flags + * @{ + */ +/** + * @brief This mode is implemented as input. + */ +#define PAL_MODE_RESET PAL_MODE_INPUT + +/** + * @brief This mode is implemented as input with pull-up. + */ +#define PAL_MODE_UNCONNECTED PAL_MODE_INPUT_PULLUP + +/** + * @brief Regular input high-Z pad. + */ +#define PAL_MODE_INPUT (PAL_TICC3200_DEN_ENABLE | \ + PAL_TICC3200_DIR_INPUT) + +/** + * @brief Input pad with weak pull up resistor. + */ +#define PAL_MODE_INPUT_PULLUP (PAL_TICC3200_DIR_INPUT | \ + PAL_TICC3200_PUR_ENABLE | \ + PAL_TICC3200_DEN_ENABLE) + +/** + * @brief Input pad with weak pull down resistor. + */ +#define PAL_MODE_INPUT_PULLDOWN (PAL_TICC3200_DIR_INPUT | \ + PAL_TICC3200_PDR_ENABLE | \ + PAL_TICC3200_DEN_ENABLE) + +/** + * @brief Analog input mode. + */ +#define PAL_MODE_INPUT_ANALOG (PAL_TICC3200_DEN_DISABLE | \ + PAL_TICC3200_AMSEL_ENABLE) + +/** + * @brief Push-pull output pad. + */ +#define PAL_MODE_OUTPUT_PUSHPULL (PAL_TICC3200_DIR_OUTPUT | \ + PAL_TICC3200_DR2R_ENABLE | \ + PAL_TICC3200_ODR_PUSHPULL | \ + PAL_TICC3200_DEN_ENABLE) + +/** + * @brief Open-drain output pad. + */ +#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_TICC3200_DIR_OUTPUT | \ + PAL_TICC3200_DR2R_ENABLE | \ + PAL_TICC3200_ODR_OPENDRAIN | \ + PAL_TICC3200_DEN_ENABLE) +/** @} */ + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @name Port related definitions + * @{ + */ +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 8 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFF) +/** @} */ + +/** + * @name Line handling macros + * @{ + */ +/** + * @brief Forms a line identifier. + * @details A port/pad pair are encoded into an @p ioline_t type. The encoding + * of this type is platform-dependent. + * @note In this driver the pad number is encoded in the lower 4 bits of + * the GPIO address which are guaranteed to be zero. + */ +#define PAL_LINE(port, pad) \ + ((ioline_t)((uint32_t)(port)) | ((uint32_t)(pad))) + +/** + * @brief Decodes a port identifier from a line identifier. + */ +#define PAL_PORT(line) \ + ((ioportid_t)(((uint32_t)(line)) & 0xFFFFFFF0U)) + +/** + * @brief Decodes a pad identifier from a line identifier. + */ +#define PAL_PAD(line) \ + ((uint32_t)((uint32_t)(line) & 0x0000000FU)) + +/** + * @brief Value identifying an invalid line. + */ +#define PAL_NOLINE 0U +/** @} */ + +/** + * @brief GPIO port setup info. + */ +typedef struct +{ + /** @brief Initial value for DATA register.*/ + uint32_t data; + /** @brief Initial value for DIR register.*/ + uint32_t dir; + /** @brief Initial value for AFSEL register.*/ + uint32_t afsel; + /** @brief Initial value for DR2R register.*/ + uint32_t dr2r; + /** @brief Initial value for DR4R register.*/ + uint32_t dr4r; + /** @brief Initial value for DR8R register.*/ + uint32_t dr8r; + /** @brief Initial value for ODR register.*/ + uint32_t odr; + /** @brief Initial value for PUR register.*/ + uint32_t pur; + /** @brief Initial value for PDR register.*/ + uint32_t pdr; + /** @brief Initial value for SLR register.*/ + uint32_t slr; + /** @brief Initial value for DEN register.*/ + uint32_t den; + /** @brief Initial value for AMSEL register.*/ + uint32_t amsel; + /** @brief Initial value for PCTL register.*/ + uint32_t pctl; +} tiva_gpio_setup_t; + +/** + * @brief Tiva GPIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct +{ + /** @brief GPIO port A setup data.*/ + tiva_gpio_setup_t PAData; + /** @brief GPIO port B setup data.*/ + tiva_gpio_setup_t PBData; + /** @brief GPIO port C setup data.*/ + tiva_gpio_setup_t PCData; + /** @brief GPIO port D setup data.*/ + tiva_gpio_setup_t PDData; + /** @brief GPIO port E setup data.*/ + tiva_gpio_setup_t PEData; + /** @brief GPIO port F setup data.*/ + tiva_gpio_setup_t PFData; +#if TICC3200_HAS_GPIOG || defined(__DOXYGEN__) + /** @brief GPIO port G setup data.*/ + tiva_gpio_setup_t PGData; +#endif +#if TICC3200_HAS_GPIOH || defined(__DOXYGEN__) + /** @brief GPIO port H setup data.*/ + tiva_gpio_setup_t PHData; +#endif +#if TICC3200_HAS_GPIOJ || defined(__DOXYGEN__) + /** @brief GPIO port J setup data.*/ + tiva_gpio_setup_t PJData; +#endif +#if TICC3200_HAS_GPIOK || defined(__DOXYGEN__) + /** @brief GPIO port K setup data.*/ + tiva_gpio_setup_t PKData; +#endif +#if TICC3200_HAS_GPIOL || defined(__DOXYGEN__) + /** @brief GPIO port L setup data.*/ + tiva_gpio_setup_t PLData; +#endif +#if TICC3200_HAS_GPIOM || defined(__DOXYGEN__) + /** @brief GPIO port M setup data.*/ + tiva_gpio_setup_t PMData; +#endif +#if TICC3200_HAS_GPION || defined(__DOXYGEN__) + /** @brief GPIO port N setup data.*/ + tiva_gpio_setup_t PNData; +#endif +#if TICC3200_HAS_GPIOP || defined(__DOXYGEN__) + /** @brief GPIO port P setup data.*/ + tiva_gpio_setup_t PPData; +#endif +#if TICC3200_HAS_GPIOQ || defined(__DOXYGEN__) + /** @brief GPIO port Q setup data.*/ + tiva_gpio_setup_t PQData; +#endif +#if TICC3200_HAS_GPIOR || defined(__DOXYGEN__) + /** @brief GPIO port R setup data.*/ + tiva_gpio_setup_t PRData; +#endif +#if TICC3200_HAS_GPIOS || defined(__DOXYGEN__) + /** @brief GPIO port S setup data.*/ + tiva_gpio_setup_t PSData; +#endif +#if TICC3200_HAS_GPIOT || defined(__DOXYGEN__) + /** @brief GPIO port T setup data.*/ + tiva_gpio_setup_t PTData; +#endif +} PALConfig; + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Type of an I/O line. + */ +typedef uint32_t ioline_t; + +/** + * @brief Port Identifier. + */ +typedef uint32_t ioportid_t; + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +#if defined(TM4C123x) + +/** + * @brief GPIOA AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOA. When set + * to @p FALSE the APB bus is used to access GPIOA. + */ +#if !defined(TICC3200_GPIO_GPIOA_USE_AHB) || defined(__DOXYGEN__) +#define TICC3200_GPIO_GPIOA_USE_AHB TRUE +#endif + +/** + * @brief GPIOB AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOB. When set + * to @p FALSE the APB bus is used to access GPIOB. + */ +#if !defined(TICC3200_GPIO_GPIOB_USE_AHB) || defined(__DOXYGEN__) +#define TICC3200_GPIO_GPIOB_USE_AHB TRUE +#endif + +/** + * @brief GPIOC AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOC. When set + * to @p FALSE the APB bus is used to access GPIOC. + */ +#if !defined(TICC3200_GPIO_GPIOC_USE_AHB) || defined(__DOXYGEN__) +#define TICC3200_GPIO_GPIOC_USE_AHB TRUE +#endif + +/** + * @brief GPIOD AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOD. When set + * to @p FALSE the APB bus is used to access GPIOD. + */ +#if !defined(TICC3200_GPIO_GPIOD_USE_AHB) || defined(__DOXYGEN__) +#define TICC3200_GPIO_GPIOD_USE_AHB TRUE +#endif + +/** + * @brief GPIOE AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOE. When set + * to @p FALSE the APB bus is used to access GPIOE. + */ +#if !defined(TICC3200_GPIO_GPIOE_USE_AHB) || defined(__DOXYGEN__) +#define TICC3200_GPIO_GPIOE_USE_AHB TRUE +#endif + +/** + * @brief GPIOF AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOF. When set + * to @p FALSE the APB bus is used to access GPIOF. + */ +#if !defined(TICC3200_GPIO_GPIOF_USE_AHB) || defined(__DOXYGEN__) +#define TICC3200_GPIO_GPIOF_USE_AHB TRUE +#endif + +/** + * @brief GPIOG AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOG. When set + * to @p FALSE the APB bus is used to access GPIOG. + */ +#if !defined(TICC3200_GPIO_GPIOG_USE_AHB) || defined(__DOXYGEN__) +#define TICC3200_GPIO_GPIOG_USE_AHB TRUE +#endif + +/** + * @brief GPIOH AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOH. When set + * to @p FALSE the APB bus is used to access GPIOH. + */ +#if !defined(TICC3200_GPIO_GPIOH_USE_AHB) || defined(__DOXYGEN__) +#define TICC3200_GPIO_GPIOH_USE_AHB TRUE +#endif + +/** + * @brief GPIOJ AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOJ. When set + * to @p FALSE the APB bus is used to access GPIOJ. + */ +#if !defined(TICC3200_GPIO_GPIOJ_USE_AHB) || defined(__DOXYGEN__) +#define TICC3200_GPIO_GPIOJ_USE_AHB TRUE +#endif + +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if TICC3200_GPIO_GPIOA_USE_AHB && defined(TM4C123x) +#define GPIOA GPIO_PORTA_AHB_BASE +#else +#define GPIOA GPIO_PORTA_BASE +#endif + +#if TICC3200_GPIO_GPIOB_USE_AHB && defined(TM4C123x) +#define GPIOB GPIO_PORTB_AHB_BASE +#else +#define GPIOB GPIO_PORTB_BASE +#endif + +#if TICC3200_GPIO_GPIOC_USE_AHB && defined(TM4C123x) +#define GPIOC GPIO_PORTC_AHB_BASE +#else +#define GPIOC GPIO_PORTC_BASE +#endif + +#if TICC3200_GPIO_GPIOD_USE_AHB && defined(TM4C123x) +#define GPIOD GPIO_PORTD_AHB_BASE +#else +#define GPIOD GPIO_PORTD_BASE +#endif + +#if TICC3200_GPIO_GPIOE_USE_AHB && defined(TM4C123x) +#define GPIOE GPIO_PORTE_AHB_BASE +#else +#define GPIOE GPIO_PORTE_BASE +#endif + +#if TICC3200_GPIO_GPIOF_USE_AHB && defined(TM4C123x) +#define GPIOF GPIO_PORTF_AHB_BASE +#else +#define GPIOF GPIO_PORTF_BASE +#endif + +#if TICC3200_GPIO_GPIOG_USE_AHB && defined(TM4C123x) +#define GPIOG GPIO_PORTG_AHB_BASE +#else +#define GPIOG GPIO_PORTG_BASE +#endif + +#if TICC3200_GPIO_GPIOH_USE_AHB && defined(TM4C123x) +#define GPIOH GPIO_PORTH_AHB_BASE +#else +#define GPIOH GPIO_PORTH_BASE +#endif + +#if TICC3200_GPIO_GPIOJ_USE_AHB && defined(TM4C123x) +#define GPIOJ GPIO_PORTJ_AHB_BASE +#else +#define GPIOJ GPIO_PORTJ_BASE +#endif + +#define GPIOK GPIO_PORTK_BASE +#define GPIOL GPIO_PORTL_BASE +#define GPIOM GPIO_PORTM_BASE +#define GPION GPIO_PORTN_BASE +#define GPIOP GPIO_PORTP_BASE +#define GPIOQ GPIO_PORTQ_BASE +#define GPIOR GPIO_PORTR_BASE +#define GPIOS GPIO_PORTS_BASE +#define GPIOT GPIO_PORTT_BASE + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief GPIO port A identifier. + */ +#define IOPORT1 GPIOA + +/** + * @brief GPIO port B identifier. + */ +#define IOPORT2 GPIOB + +/** + * @brief GPIO port C identifier. + */ +#define IOPORT3 GPIOC + +/** + * @brief GPIO port D identifier. + */ +#define IOPORT4 GPIOD + +/** + * @brief GPIO port E identifier. + */ +#define IOPORT5 GPIOE + +/** + * @brief GPIO port F identifier. + */ +#define IOPORT6 GPIOF + +/** + * @brief GPIO port G identifier. + */ +#if TICC3200_HAS_GPIOG || defined(__DOXYGEN__) +#define IOPORT7 GPIOG +#endif + +/** + * @brief GPIO port H identifier. + */ +#if TICC3200_HAS_GPIOH || defined(__DOXYGEN__) +#define IOPORT8 GPIOH +#endif + +/** + * @brief GPIO port J identifier. + */ +#if TICC3200_HAS_GPIOJ || defined(__DOXYGEN__) +#define IOPORT9 GPIOJ +#endif + +/** + * @brief GPIO port K identifier. + */ +#if TICC3200_HAS_GPIOK || defined(__DOXYGEN__) +#define IOPORT10 GPIOK +#endif + +/** + * @brief GPIO port L identifier. + */ +#if TICC3200_HAS_GPIOL || defined(__DOXYGEN__) +#define IOPORT11 GPIOL +#endif + +/** + * @brief GPIO port M identifier. + */ +#if TICC3200_HAS_GPIOM || defined(__DOXYGEN__) +#define IOPORT12 GPIOM +#endif + +/** + * @brief GPIO port N identifier. + */ +#if TICC3200_HAS_GPION || defined(__DOXYGEN__) +#define IOPORT13 GPION +#endif + +/** + * @brief GPIO port P identifier. + */ +#if TICC3200_HAS_GPIOP || defined(__DOXYGEN__) +#define IOPORT14 GPIOP +#endif + +/** + * @brief GPIO port Q identifier. + */ +#if TICC3200_HAS_GPIOQ || defined(__DOXYGEN__) +#define IOPORT15 GPIOQ +#endif + +/** + * @brief GPIO port R identifier. + */ +#if TICC3200_HAS_GPIOR || defined(__DOXYGEN__) +#define IOPORT16 GPIOR +#endif + +/** + * @brief GPIO port S identifier. + */ +#if TICC3200_HAS_GPIOS || defined(__DOXYGEN__) +#define IOPORT17 GPIOS +#endif + +/** + * @brief GPIO port T identifier. + */ +#if TICC3200_HAS_GPIOT || defined(__DOXYGEN__) +#define IOPORT18 GPIOT +#endif + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) (HWREG((port) + GPIO_O_GPIO_DATA + (0xff << 2))) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) pal_lld_readport(port) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) (HWREG((port) + GPIO_O_GPIO_DATA + (0xff << 2)) = (bits)) + +/** + * @brief Sets a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) (HWREG((port) + (GPIO_O_GPIO_DATA + (bits << 2))) = 0xFF) + +/** + * @brief Clears a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) (HWREG((port) + (GPIO_O_GPIO_DATA + (bits << 2))) = 0) + +/** + * @brief Reads a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @return The group logical states. + * + * @notapi + */ +#define pal_lld_readgroup(port, mask, offset) \ + (HWREG((port) + (GPIO_O_GPIO_DATA + (((mask) << (offset)) << 2)))) + +/** + * @brief Writes a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group width + * are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) \ + (HWREG((port) + (GPIO_O_GPIO_DATA + (((mask) << (offset)) << 2))) = (bits)) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Reads a logical state from an I/O pad. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @return The logical state. + * @retval PAL_LOW low logical state. + * @retval PAL_HIGH high logical state. + * + * @notapi + */ +#define pal_lld_readpad(port, pad) (HWREG((port) + (GPIO_O_GPIO_DATA + ((1 << (pad)) << 2)))) + +/** + * @brief Writes a logical state on an output pad. + * @note This function is not meant to be invoked directly by the + * application code. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) \ + (HWREG((port) + (GPIO_O_GPIO_DATA + ((1 << (pad)) << 2))) = (bit)) + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_setpad(port, pad) \ + (HWREG((port) + (GPIO_O_GPIO_DATA + ((1 << (pad)) << 2))) = 1 << (pad)) + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_clearpad(port, pad) \ + (HWREG((port) + (GPIO_O_GPIO_DATA + ((1 << (pad)) << 2))) = 0) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern const PALConfig pal_default_config; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* HAL_PAL_LLD_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPTM/hal_st_lld.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPTM/hal_st_lld.c new file mode 100644 index 00000000..06b2f946 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPTM/hal_st_lld.c @@ -0,0 +1,244 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/** + * @file GPTM/hal_st_lld.c + * @brief ST Driver subsystem low level driver code. + * + * @addtogroup ST + * @{ + */ + +#include "hal.h" + +#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING + +#if (TICC3200_ST_USE_WIDE_TIMER == TRUE) + +#if TICC3200_ST_TIMER_NUMBER == 0 +#define ST_HANDLER TICC3200_WGPT0A_HANDLER +#define ST_NUMBER TICC3200_WGPT0A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 0)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 0))) + +#elif TICC3200_ST_TIMER_NUMBER == 1 +#define ST_HANDLER TICC3200_WGPT1A_HANDLER +#define ST_NUMBER TICC3200_WGPT1A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 1)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 1))) + +#elif TICC3200_ST_TIMER_NUMBER == 2 +#define ST_HANDLER TICC3200_WGPT2A_HANDLER +#define ST_NUMBER TICC3200_WGPT2A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 2)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 2))) + +#elif TICC3200_ST_TIMER_NUMBER == 3 +#define ST_HANDLER TICC3200_WGPT3A_HANDLER +#define ST_NUMBER TICC3200_WGPT3A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 3)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 3))) + +#elif TICC3200_ST_TIMER_NUMBER == 4 +#define ST_HANDLER TICC3200_WGPT4A_HANDLER +#define ST_NUMBER TICC3200_WGPT4A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 4)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 4))) + +#elif TICC3200_ST_TIMER_NUMBER == 5 +#define ST_HANDLER TICC3200_WGPT5A_HANDLER +#define ST_NUMBER TICC3200_WGPT5A_NUMBER +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 5)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 5))) + +#else +#error "TICC3200_ST_USE_TIMER specifies an unsupported timer" +#endif + +#if (ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1 > 0xFFFF +#error "the selected ST frequency is not obtainable because TIM timer prescaler limits" +#endif + +#elif (TICC3200_ST_USE_WIDE_TIMER == FALSE) + +#if TICC3200_ST_TIMER_NUMBER == 0 +#define ST_HANDLER TICC3200_GPT0A_HANDLER +#define ST_NUMBER TICC3200_GPT0A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 0)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 0))) + +#elif TICC3200_ST_TIMER_NUMBER == 1 +#define ST_HANDLER TICC3200_GPT1A_HANDLER +#define ST_NUMBER TICC3200_GPT1A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 1)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 1))) + +#elif TICC3200_ST_TIMER_NUMBER == 2 +#define ST_HANDLER TICC3200_GPT2A_HANDLER +#define ST_NUMBER TICC3200_GPT2A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 2)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 2))) + +#elif TICC3200_ST_TIMER_NUMBER == 3 +#define ST_HANDLER TICC3200_GPT3A_HANDLER +#define ST_NUMBER TICC3200_GPT3A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 3)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 3))) + +#elif TICC3200_ST_TIMER_NUMBER == 4 +#define ST_HANDLER TICC3200_GPT4A_HANDLER +#define ST_NUMBER TICC3200_GPT4A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 4)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 4))) + +#elif TICC3200_ST_TIMER_NUMBER == 5 +#define ST_HANDLER TICC3200_GPT5A_HANDLER +#define ST_NUMBER TICC3200_GPT5A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 5)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 5))) + +#else +#error "TICC3200_ST_USE_TIMER specifies an unsupported timer" +#endif + +#if (TICC3200_SYSCLK / OSAL_ST_FREQUENCY) - 1 > 0xFF +#error "the selected ST frequency is not obtainable because TIM timer prescaler limits" +#endif + +#endif + +#if TICC3200_SYSCLK % OSAL_ST_FREQUENCY != 0 +#error "the selected ST frequency is not obtainable because integer rounding" +#endif + +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__) +/** + * @brief System Timer vector. + * @details This interrupt is used for system tick in periodic mode. + * + * @isr + */ +OSAL_IRQ_HANDLER(SysTick_Handler) +{ + OSAL_IRQ_PROLOGUE(); + + osalSysLockFromISR(); + osalOsTimerHandlerI(); + osalSysUnlockFromISR(); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ + +#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__) +/** + * @brief GPT interrupt handler. + * @details This interrupt is used for system tick in free running mode. + * + * @isr + */ +OSAL_IRQ_HANDLER(ST_HANDLER) +{ + uint32_t mis; + + OSAL_IRQ_PROLOGUE(); + + mis = HWREG(TICC3200_ST_TIM + TIMER_O_MIS); + HWREG(TICC3200_ST_TIM + TIMER_O_ICR) = mis; + + if (mis & TIMER_IMR_TAMIM) { + osalSysLockFromISR(); + osalOsTimerHandlerI(); + osalSysUnlockFromISR(); + } + + OSAL_IRQ_EPILOGUE(); +} +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ST driver initialization. + * + * @notapi + */ +void st_lld_init(void) +{ +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING + /* Free running counter mode.*/ + + /* Enabling timer clock.*/ + ST_ENABLE_CLOCK(); + + /* Wait until timer peripheral is ready */ + ST_WAIT_CLOCK(); + + /* Initializing the counter in free running down mode.*/ + HWREG(TICC3200_ST_TIM + TIMER_O_CTL) = 0; + HWREG(TICC3200_ST_TIM + TIMER_O_CFG) = TIMER_CFG_16_BIT; /* Timer split mode */ + HWREG(TICC3200_ST_TIM + TIMER_O_TAMR) = ( + TIMER_TAMR_TAMR_PERIOD | /* Periodic mode */ + TIMER_TAMR_TAMIE | /* Match interrupt enable */ + TIMER_TAMR_TASNAPS); /* Snapshot mode */ + + HWREG(TICC3200_ST_TIM + TIMER_O_TAPR) = (TICC3200_SYSCLK / OSAL_ST_FREQUENCY) - 1; + HWREG(TICC3200_ST_TIM + TIMER_O_CTL) = ( + TIMER_CTL_TAEN | /* Timer A enable */ + TIMER_CTL_TASTALL); /* Timer A stall when paused */ + + /* IRQ enabled.*/ + nvicEnableVector(ST_NUMBER, TICC3200_ST_IRQ_PRIORITY); +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ + +#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC + /* Periodic systick mode, the Cortex-Mx internal systick timer is used + in this mode.*/ + SysTick->LOAD = (TICC3200_SYSCLK / OSAL_ST_FREQUENCY) - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; + + /* IRQ enabled.*/ + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, TICC3200_ST_IRQ_PRIORITY); +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ +} + +#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */ + +/** + * @} + */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPTM/hal_st_lld.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPTM/hal_st_lld.h new file mode 100644 index 00000000..013211d1 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/GPTM/hal_st_lld.h @@ -0,0 +1,199 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/** + * @file GPTM/hal_st_lld.h + * @brief ST Driver subsystem low level driver header. + * @details This header is designed to be include-able without having to + * include other files from the HAL. + * + * @addtogroup ST + * @{ + */ + +#ifndef HAL_ST_LLD_H +#define HAL_ST_LLD_H + +#include "mcuconf.h" +#include "ticc3200_registry.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ + +/** + * @brief SysTick timer IRQ priority. + */ +#if !defined(TICC3200_ST_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TICC3200_ST_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPTx unit (by number) to be used for free running operations. + * @note You must select a 32 bits timer if a 32 bits @p systick_t type + * is required. + */ +#if !defined(TICC3200_ST_TIMER_NUMBER) || defined(__DOXYGEN__) +#define TICC3200_ST_TIMER_NUMBER 0 +#endif + +/** + * @brief When set to @p TRUE a wide timer is used. When set to @p FALSE a + * normal timer is used. + */ +#if !defined(TICC3200_ST_USE_WIDE_TIMER) || defined(__DOXYGEN__) +#define TICC3200_ST_USE_WIDE_TIMER TRUE +#endif + +/** + * @} + */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if TICC3200_ST_TIMER_NUMBER == 0 +#if !TICC3200_HAS_GPT0 +#error "GPT0 not present" +#endif +#define TICC3200_ST_TIM TIMERA0_BASE + +#elif TICC3200_ST_TIMER_NUMBER == 1 +#if !TICC3200_HAS_GPT1 +#error "GPT1 not present" +#endif +#define TICC3200_ST_TIM TIMERA1_BASE + +#elif TICC3200_ST_TIMER_NUMBER == 2 +#if !TICC3200_HAS_GPT2 +#error "GPT2 not present" +#endif +#define TICC3200_ST_TIM TIMERA2_BASE + +#elif TICC3200_ST_TIMER_NUMBER == 3 +#if !TICC3200_HAS_GPT3 +#error "GPT3 not present" +#endif +#define TICC3200_ST_TIM TIMERA3_BASE + +#else +#error "TICC3200_ST_TIMER_NUMBER specifies an unsupported timer" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void st_lld_init(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Driver inline functions. */ +/*===========================================================================*/ + +/** + * @brief Returns the time counter value. + * + * @return The counter value. + * + * @notapi + */ +static inline systime_t st_lld_get_counter(void) +{ + return (systime_t) (((systime_t) 0xffffffff) - HWREG(TICC3200_ST_TIM + TIMER_O_TAV)); +} + +/** + * @brief Starts the alarm. + * @note Makes sure that no spurious alarms are triggered after + * this call. + * + * @param[in] time the time to be set for the first alarm + * + * @notapi + */ +static inline void st_lld_start_alarm(systime_t time) +{ + HWREG(TICC3200_ST_TIM + TIMER_O_TAMATCHR) = (systime_t) (((systime_t) 0xffffffff) - time); + HWREG(TICC3200_ST_TIM + TIMER_O_ICR) = HWREG(TICC3200_ST_TIM + TIMER_O_MIS); + HWREG(TICC3200_ST_TIM + TIMER_O_IMR) = TIMER_IMR_TAMIM; +} + +/** + * @brief Stops the alarm interrupt. + * + * @notapi + */ +static inline void st_lld_stop_alarm(void) +{ + HWREG(TICC3200_ST_TIM + TIMER_O_IMR) = 0; +} + +/** + * @brief Sets the alarm time. + * + * @param[in] time the time to be set for the next alarm + * + * @notapi + */ +static inline void st_lld_set_alarm(systime_t time) +{ + HWREG(TICC3200_ST_TIM + TIMER_O_TAMATCHR) = (systime_t) (((systime_t) 0xffffffff) - time); +} + +/** + * @brief Returns the current alarm time. + * + * @return The currently set alarm time. + * + * @notapi + */ +static inline systime_t st_lld_get_alarm(void) +{ + return (systime_t) (((systime_t)0xffffffff) - HWREG(TICC3200_ST_TIM + TIMER_O_TAMATCHR)); +} + +/** + * @brief Determines if the alarm is active. + * + * @return The alarm status. + * @retval false if the alarm is not active. + * @retval true is the alarm is active + * + * @notapi + */ +static inline bool st_lld_is_alarm_active(void) +{ + return (bool) ((HWREG(TICC3200_ST_TIM + TIMER_O_IMR) & TIMER_IMR_TAMIM) !=0); +} + +#endif /* HAL_ST_LLD_H */ + +/** + * @} + */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/RTC/hal_rtc_lld.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/RTC/hal_rtc_lld.h new file mode 100644 index 00000000..8ead7b02 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/RTC/hal_rtc_lld.h @@ -0,0 +1,188 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file RTCv1/hal_rtc_lld.h + * @brief TCC3200 RTC subsystem low level driver header. + * + * @addtogroup RTC + * @{ + */ + +#ifndef HAL_RTC_LLD_H +#define HAL_RTC_LLD_H + +#if HAL_USE_RTC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Implementation capabilities + */ +/** + * @brief This RTC implementation supports callbacks. + */ +#define RTC_SUPPORTS_CALLBACKS TRUE + +/** + * @brief One alarm comparator available. + */ +#define RTC_ALARMS 1 + +/** + * @brief Presence of a local persistent storage. + */ +#define RTC_HAS_STORAGE FALSE +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/* + * RTC driver system settings. + */ +#define TICC3200_RTC_IRQ_PRIORITY 15 +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if HAL_USE_RTC && !TICC3200_HAS_RTC +#error "RTC not present in the selected device" +#endif + +#if TICC3200_RTCCLK == 0 +#error "RTC clock not enabled" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief FileStream specific methods. + */ +#define _rtc_driver_methods \ + _file_stream_methods + +/** + * @brief Type of a structure representing an RTC alarm time stamp. + */ +typedef struct RTCAlarm RTCAlarm; + +/** + * @brief Type of an RTC alarm. + * @details Meaningful on platforms with more than 1 alarm comparator. + */ +typedef uint32_t rtcalarm_t; + +/** + * @brief Type of an RTC event. + */ +typedef enum { + RTC_EVENT_SECOND = 0, /** Triggered every second. */ + RTC_EVENT_ALARM = 1, /** Triggered on alarm. */ + RTC_EVENT_OVERFLOW = 2 /** Triggered on counter overflow. */ +} rtcevent_t; + +/** + * @brief Type of a generic RTC callback. + */ +typedef void (*rtccb_t)(RTCDriver *rtcp, rtcevent_t event); + +/** + * @brief Structure representing an RTC alarm time stamp. + */ +struct RTCAlarm { + /** + * @brief Seconds since UNIX epoch. + */ + uint32_t tv_sec; +}; + +#if RTC_HAS_STORAGE || defined(__DOXYGEN__) +/** + * @extends FileStream + * + * @brief @p RTCDriver virtual methods table. + */ +struct RTCDriverVMT { + _rtc_driver_methods +}; +#endif + +/** + * @brief Structure representing an RTC driver. + */ +struct RTCDriver{ +#if RTC_HAS_STORAGE || defined(__DOXYGEN__) + /** + * @brief Virtual Methods Table. + */ + const struct RTCDriverVMT *vmt; +#endif + /** + * @brief Pointer to the RTC registers block. + */ + RTC_TypeDef *rtc; + /** + * @brief Callback pointer. + */ + rtccb_t callback; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern RTCDriver RTCD1; +#if RTC_HAS_STORAGE +extern struct RTCDriverVMT _rtc_lld_vmt; +#endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void rtc_lld_set_prescaler(void); + void rtc_lld_init(void); + void rtc_lld_set_time(RTCDriver *rtcp, const RTCDateTime *timespec); + void rtc_lld_get_time(RTCDriver *rtcp, RTCDateTime *timespec); + void rtc_lld_set_alarm(RTCDriver *rtcp, + rtcalarm_t alarm_number, + const RTCAlarm *alarmspec); + void rtc_lld_get_alarm(RTCDriver *rtcp, + rtcalarm_t alarm_number, + RTCAlarm *alarmspec); + void rtc_lld_set_callback(RTCDriver *rtcp, rtccb_t callback); + void rtcSTM32GetSecMsec(RTCDriver *rtcp, uint32_t *tv_sec, uint32_t *tv_msec); + void rtcSTM32SetSec(RTCDriver *rtcp, uint32_t tv_sec); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_RTC */ + +#endif /* HAL_RTC_LLD_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/UART/hal_serial_lld.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/UART/hal_serial_lld.h new file mode 100644 index 00000000..5c976131 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/LLD/UART/hal_serial_lld.h @@ -0,0 +1,437 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/** + * @file UART/hal_serial_lld.h + * @brief TICC3200 low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef HAL_SERIAL_LLD_H +#define HAL_SERIAL_LLD_H + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Advanced buffering support switch. + * @details This constants enables the advanced buffering support in the + * low level driver, the queue buffer is no more part of the + * @p SerialDriver structure, each driver can have a different + * queue size. + */ +#define SERIAL_ADVANCED_BUFFERING_SUPPORT TRUE + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief UART0 driver enable switch. + * @details If set to @p TRUE the support for UART0 is included. + * @note The default is @p TRUE. + */ +#if !defined(TICC3200_SERIAL_USE_UART0) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_USE_UART0 FALSE +#endif + +/** + * @brief UART1 driver enable switch. + * @details If set to @p TRUE the support for UART1 is included. + * @note The default is @p FALSE . + */ +#if !defined(TICC3200_SERIAL_USE_UART1) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_USE_UART1 FALSE +#endif + +/** + * @brief UART2 driver enable switch. + * @details If set to @p TRUE the support for UART2 is included. + * @note The default is @p FALSE . + */ +#if !defined(TICC3200_SERIAL_USE_UART2) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_USE_UART2 FALSE +#endif + +/** + * @brief UART3 driver enable switch. + * @details If set to @p TRUE the support for UART3 is included. + * @note The default is @p FALSE . + */ +#if !defined(TICC3200_SERIAL_USE_UART3) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_USE_UART3 FALSE +#endif + +/** + * @brief UART4 driver enable switch. + * @details If set to @p TRUE the support for UART4 is included. + * @note The default is @p FALSE . + */ +#if !defined(TICC3200_SERIAL_USE_UART4) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_USE_UART4 FALSE +#endif + +/** + * @brief UART5 driver enable switch. + * @details If set to @p TRUE the support for UART5 is included. + * @note The default is @p FALSE . + */ +#if !defined(TICC3200_SERIAL_USE_UART5) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_USE_UART5 FALSE +#endif + +/** + * @brief UART6 driver enable switch. + * @details If set to @p TRUE the support for UART6 is included. + * @note The default is @p FALSE . + */ +#if !defined(TICC3200_SERIAL_USE_UART6) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_USE_UART6 FALSE +#endif + +/** + * @brief UART7 driver enable switch. + * @details If set to @p TRUE the support for UART7 is included. + * @note The default is @p FALSE . + */ +#if !defined(TICC3200_SERIAL_USE_UART7) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_USE_UART7 FALSE +#endif + +/** + * @brief UART0 interrupt priority level setting. + */ +#if !defined(TICC3200_SERIAL_UART0_PRIORITY) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART0_PRIORITY 5 +#endif + +/** + * @brief UART1 interrupt priority level setting. + */ +#if !defined(TICC3200_SERIAL_UART1_PRIORITY) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART1_PRIORITY 5 +#endif + +/** + * @brief UART2 interrupt priority level setting. + */ +#if !defined(TICC3200_SERIAL_UART2_PRIORITY) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART2_PRIORITY 5 +#endif + +/** + * @brief UART3 interrupt priority level setting. + */ +#if !defined(TICC3200_SERIAL_UART3_PRIORITY) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART3_PRIORITY 5 +#endif + +/** + * @brief UART4 interrupt priority level setting. + */ +#if !defined(TICC3200_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART4_PRIORITY 5 +#endif + +/** + * @brief UART5 interrupt priority level setting. + */ +#if !defined(TICC3200_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART5_PRIORITY 5 +#endif + +/** + * @brief UART6 interrupt priority level setting. + */ +#if !defined(TICC3200_SERIAL_UART6_PRIORITY) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART6_PRIORITY 5 +#endif + +/** + * @brief UART7 interrupt priority level setting. + */ +#if !defined(TICC3200_SERIAL_UART7_PRIORITY) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART7_PRIORITY 5 +#endif + +/** + * @brief Input buffer size for UART0. + */ +#if !defined(TICC3200_SERIAL_UART0_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART0_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART0. + */ +#if !defined(TICC3200_SERIAL_UART0_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART0_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for UART1. + */ +#if !defined(TICC3200_SERIAL_UART1_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART1_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART1. + */ +#if !defined(TICC3200_SERIAL_UART1_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART1_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for UART2. + */ +#if !defined(TICC3200_SERIAL_UART2_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART2_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART2. + */ +#if !defined(TICC3200_SERIAL_UART2_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART2_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for UART3. + */ +#if !defined(TICC3200_SERIAL_UART3_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART3_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART3. + */ +#if !defined(TICC3200_SERIAL_UART3_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART3_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for UART4. + */ +#if !defined(TICC3200_SERIAL_UART4_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART4_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART4. + */ +#if !defined(TICC3200_SERIAL_UART4_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART4_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for UART5. + */ +#if !defined(TICC3200_SERIAL_UART5_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART5_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART5. + */ +#if !defined(TICC3200_SERIAL_UART5_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART5_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for UART6. + */ +#if !defined(TICC3200_SERIAL_UART6_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART6_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART6. + */ +#if !defined(TICC3200_SERIAL_UART6_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART6_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Input buffer size for UART7. + */ +#if !defined(TICC3200_SERIAL_UART7_IN_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART7_IN_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif + +/** + * @brief Output buffer size for UART7. + */ +#if !defined(TICC3200_SERIAL_UART7_OUT_BUF_SIZE) || defined(__DOXYGEN__) +#define TICC3200_SERIAL_UART7_OUT_BUF_SIZE SERIAL_BUFFERS_SIZE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !TICC3200_SERIAL_USE_UART0 && !TICC3200_SERIAL_USE_UART1 && \ + !TICC3200_SERIAL_USE_UART2 && !TICC3200_SERIAL_USE_UART3 && \ + !TICC3200_SERIAL_USE_UART4 && !TICC3200_SERIAL_USE_UART5 && \ + !TICC3200_SERIAL_USE_UART6 && !TICC3200_SERIAL_USE_UART7 +#error "SERIAL driver activated but no UART peripheral assigned" +#endif + +#if TICC3200_SERIAL_USE_UART0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TICC3200_SERIAL_UART0_PRIORITY) +#error "Invalid IRQ priority assigned to UART0" +#endif + +#if TICC3200_SERIAL_USE_UART1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TICC3200_SERIAL_UART1_PRIORITY) +#error "Invalid IRQ priority assigned to UART1" +#endif + +#if TICC3200_SERIAL_USE_UART2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TICC3200_SERIAL_UART2_PRIORITY) +#error "Invalid IRQ priority assigned to UART2" +#endif + +#if TICC3200_SERIAL_USE_UART3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TICC3200_SERIAL_UART3_PRIORITY) +#error "Invalid IRQ priority assigned to UART3" +#endif + +#if TICC3200_SERIAL_USE_UART4 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TICC3200_SERIAL_UART4_PRIORITY) +#error "Invalid IRQ priority assigned to UART4" +#endif + +#if TICC3200_SERIAL_USE_UART5 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TICC3200_SERIAL_UART5_PRIORITY) +#error "Invalid IRQ priority assigned to UART5" +#endif + +#if TICC3200_SERIAL_USE_UART6 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TICC3200_SERIAL_UART6_PRIORITY) +#error "Invalid IRQ priority assigned to UART6" +#endif + +#if TICC3200_SERIAL_USE_UART7 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TICC3200_SERIAL_UART7_PRIORITY) +#error "Invalid IRQ priority assigned to UART7" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Tiva Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + * @note This structure content is architecture dependent, each driver + * implementation defines its own version and the custom static + * initializers. + */ +typedef struct { + /** + * @brief Bit rate. + */ + uint32_t speed; + /* End of the mandatory fields. */ + /** + * @brief Initialization value for the CTL register. + */ + uint16_t ctl; + /** + * @brief Initialization value for the LCRH register. + */ + uint8_t lcrh; + /** + * @brief Initialization value for the IFLS register. + */ + uint8_t ifls; + /** + * @brief Initialization value for the CC register. + */ + uint8_t cc; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + input_queue_t iqueue; \ + /* Output queue.*/ \ + output_queue_t oqueue; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the USART registers block.*/ \ + uint32_t uart; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if TICC3200_SERIAL_USE_UART0 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif + +#if TICC3200_SERIAL_USE_UART1 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif + +#if TICC3200_SERIAL_USE_UART2 && !defined(__DOXYGEN__) +extern SerialDriver SD3; +#endif + +#if TICC3200_SERIAL_USE_UART3 && !defined(__DOXYGEN__) +extern SerialDriver SD4; +#endif + +#if TICC3200_SERIAL_USE_UART4 && !defined(__DOXYGEN__) +extern SerialDriver SD5; +#endif + +#if TICC3200_SERIAL_USE_UART5 && !defined(__DOXYGEN__) +extern SerialDriver SD6; +#endif + +#if TICC3200_SERIAL_USE_UART6 && !defined(__DOXYGEN__) +extern SerialDriver SD7; +#endif + +#if TICC3200_SERIAL_USE_UART7 && !defined(__DOXYGEN__) +extern SerialDriver SD8; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* HAL_SERIAL_LLD_H */ + +/** @} */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/hal_lld.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/hal_lld.c new file mode 100644 index 00000000..c9633519 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/hal_lld.c @@ -0,0 +1,131 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/** + * @file TI/TICC3200/hal_lld.c + * @brief TI CC3200 HAL Driver subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) +{ +} + +/** + * @brief CC3200 clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h and + * @p mcuconf.h. + * @note This function should be invoked just after the system reset. + * + * @special + */ +void ti3200_clock_init(void) +{ + uint32_t rcc, rcc2, i; + + /* 1. Bypass the PLL and system clock divider by setting the BYPASS bit and + * clearing the USESYSDIV bit in the RCC register, thereby configuring the + * microcontroller to run off a "raw" clock source and allowing for the new + * PLL configuration to be validated before switching the system clock to the + * PLL. */ + /* read */ + + rcc = HWREG(SYSCTL_RCC); + rcc2 = HWREG(SYSCTL_RCC2); + + /* modify */ + rcc |= SYSCTL_RCC_BYPASS; + rcc &= ~SYSCTL_RCC_USESYSDIV; + rcc2 |= SYSCTL_RCC2_BYPASS2 | SYSCTL_RCC2_USERCC2; + + /* write */ + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; + + /* 2 Select the crystal value (XTAL) and oscillator source (OSCSRC), and + * clear the PWRDN bit in RCC and RCC2. Setting the XTAL field automatically + * pulls valid PLL configuration data for the appropriate crystal, and + * clearing the PWRDN bit powers and enables the PLL and its output. */ + /* modify */ + rcc &= ~(SYSCTL_RCC_OSCSRC_M | SYSCTL_RCC_XTAL_M | SYSCTL_RCC_PWRDN | SYSCTL_RCC_MOSCDIS); + rcc |= ((TIVA_XTAL | TIVA_OSCSRC | TIVA_MOSCDIS) & (SYSCTL_RCC_XTAL_M | SYSCTL_RCC_OSCSRC_M | SYSCTL_RCC_MOSCDIS)); + rcc2 &= ~(SYSCTL_RCC2_OSCSRC2_M | SYSCTL_RCC2_PWRDN2); + rcc2 |= ((TIVA_OSCSRC | TIVA_DIV400) & (SYSCTL_RCC2_OSCSRC2_M | SYSCTL_RCC2_DIV400)); + + /* write */ + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; + for(i = 100000; i; i--); + + /* 3. Select the desired system divider (SYSDIV) in RCC and RCC2 and set the + * USESYSDIV bit in RCC. The SYSDIV field determines the system frequency for + * the microcontroller. */ + /* modify */ + rcc &= ~SYSCTL_RCC_SYSDIV_M; + rcc |= (TIVA_SYSDIV & SYSCTL_RCC_SYSDIV_M) | SYSCTL_RCC_USESYSDIV; + rcc2 &= ~(SYSCTL_RCC2_SYSDIV2_M | SYSCTL_RCC2_SYSDIV2LSB); + rcc2 |= ((TIVA_SYSDIV2 | TIVA_SYSDIV2LSB) & (SYSCTL_RCC2_SYSDIV2_M | SYSCTL_RCC2_SYSDIV2LSB)); + + /* write */ + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; + + /* 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw + * Interrupt Status (RIS) register. */ + while ((HWREG(SYSCTL_RIS) & SYSCTL_RIS_PLLLRIS) == 0); + + /* 5. Enable use of the PLL by clearing the BYPASS bit in RCC and RCC2. */ + rcc &= ~SYSCTL_RCC_BYPASS; + rcc2 &= ~SYSCTL_RCC2_BYPASS2; + rcc |= (TIVA_BYPASS_VALUE << 11); + rcc2 |= (TIVA_BYPASS_VALUE << 11); + HWREG(SYSCTL_RCC) = rcc; + HWREG(SYSCTL_RCC2) = rcc2; + +#if HAL_USE_PWM + HWREG(SYSCTL_RCC) |= TIVA_PWM_FIELDS; +#endif + +#if defined(TICC3200_UDMA_REQUIRED) + udmaInit(); +#endif +} + +/** + * @} + */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/hal_lld.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/hal_lld.h new file mode 100644 index 00000000..d2122366 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/hal_lld.h @@ -0,0 +1,234 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/** + * @file TI/TICC3200/hal_lld.h + * @brief TI CC3200 HAL subsystem low level driver header. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - TODO: add required macros + * + * @addtogroup HAL + * @{ + */ + +#ifndef HAL_LLD_H +#define HAL_LLD_H + +#include "ticc3200_registry.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Platform identification + * @{ + */ + +#define PLATFORM_NAME "TI CC3200" + +/** + * @} + */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ + +#if !defined(TICC3200_OSCSRC) +#define TICC3200_OSCSRC SYSCTL_RCC2_OSCSRC2_MO +#endif + +#if !defined(TICC3200_MOSC_ENABLE) +#define TICC3200_MOSC_ENABLE TRUE +#endif + +#if !defined(TICC3200_DIV400_VALUE) +#define TICC3200_DIV400_VALUE 1 +#endif + +#if !defined(TICC3200_SYSDIV_VALUE) +#define TICC3200_SYSDIV_VALUE 2 +#endif + +#if !defined(TICC3200_USESYSDIV_ENABLE) +#define TICC3200_USESYSDIV_ENABLE FALSE +#endif + +#if !defined(TICC3200_SYSDIV2LSB_ENABLE) +#define TICC3200_SYSDIV2LSB_ENABLE FALSE +#endif + +#if !defined(TICC3200_BYPASS_VALUE) +#define TICC3200_BYPASS_VALUE 0 +#endif + +/** + * @} + */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(TICC3200_MCUCONF) +#error "Using a wrong mcuconf.h file, TICC3200_MCUCONF not defined" +#endif + +/* + * Oscillator-related checks. + */ +#if !(TICC3200_OSCSRC == SYSCTL_RCC2_OSCSRC2_MO) && \ + !(TICC3200_OSCSRC == SYSCTL_RCC2_OSCSRC2_IO) && \ + !(TICC3200_OSCSRC == SYSCTL_RCC2_OSCSRC2_IO4) && \ + !(TICC3200_OSCSRC == SYSCTL_RCC2_OSCSRC2_30) && \ + !(TICC3200_OSCSRC == SYSCTL_RCC2_OSCSRC2_32) +#error "Invalid value for TICC3200_OSCSRC defined" +#endif + +// #if TICC3200_XTAL_VALUE == 4000000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_4MHZ +// #elif TICC3200_XTAL_VALUE == 4096000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_4_09MHZ +// #elif TICC3200_XTAL_VALUE == 4915200 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_4_91MHZ +// #elif TICC3200_XTAL_VALUE == 5000000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_5MHZ +// #elif TICC3200_XTAL_VALUE == 5120000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_5_12MHZ +// #elif TICC3200_XTAL_VALUE == 6000000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_6MHZ +// #elif TICC3200_XTAL_VALUE == 6144000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_6_14MHZ +// #elif TICC3200_XTAL_VALUE == 7372800 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_7_37MHZ +// #elif TICC3200_XTAL_VALUE == 8000000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_8MHZ +// #elif TICC3200_XTAL_VALUE == 8192000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_8_19MHZ +// #elif TICC3200_XTAL_VALUE == 10000000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_10MHZ +// #elif TICC3200_XTAL_VALUE == 12000000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_12MHZ +// #elif TICC3200_XTAL_VALUE == 12288000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_12_2MHZ +// #elif TICC3200_XTAL_VALUE == 13560000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_13_5MHZ +// #elif TICC3200_XTAL_VALUE == 14318180 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_14_3MHZ +// #elif TICC3200_XTAL_VALUE == 16000000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_16MHZ +// #elif TICC3200_XTAL_VALUE == 16384000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_16_3MHZ +// #elif TICC3200_XTAL_VALUE == 18000000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_18MHZ +// #elif TICC3200_XTAL_VALUE == 20000000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_20MHZ +// #elif TICC3200_XTAL_VALUE == 24000000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_24MHZ +// #elif TICC3200_XTAL_VALUE == 25000000 +// #define TICC3200_XTAL_ SYSCTL_RCC_XTAL_25MHZ +// #else +// #error "Invalid value for TICC3200_XTAL_VALUE defined" +// #endif + +// #if TICC3200_MOSC_ENABLE == TRUE +// #define TICC3200_MOSCDIS (0 << 0) +// #define TICC3200_XTAL TICC3200_XTAL_ +// #elif TICC3200_MOSC_ENABLE == FALSE +// #define TICC3200_MOSCDIS (1 << 0) +// #define TICC3200_XTAL 0 +// #else +// #error "Invalid value for TICC3200_MOSC_ENABLE defined" +// #endif + +// #if TICC3200_DIV400_VALUE == 1 +// #define TICC3200_DIV400 (1 << 30) +// #elif TICC3200_DIV400_VALUE == 0 +// #define TICC3200_DIV400 (0 << 30) +// #else +// #error "Invalid value for TICC3200_DIV400_VALUE defined" +// #endif + +// #if (TICC3200_SYSDIV_VALUE >= 0x02) && (TICC3200_SYSDIV_VALUE <= 0x3f) +// #define TICC3200_SYSDIV (TICC3200_SYSDIV_VALUE << 23) +// #define TICC3200_SYSDIV2 (TICC3200_SYSDIV_VALUE << 23) +// #else +// #error "Invalid value for TICC3200_SYSDIV_VALUE defined" +// #endif + +// #if TICC3200_USESYSDIV_ENABLE == TRUE +// #define TICC3200_USESYSDIV (1 << 22) +// #elif TICC3200_USESYSDIV_ENABLE == FALSE +// #define TICC3200_USESYSDIV (0 << 22) +// #else +// #error "Invalid value for TICC3200_USESYSDIV_ENABLE defined" +// #endif + +// #if TICC3200_SYSDIV2LSB_ENABLE == TRUE +// #define TICC3200_SYSDIV2LSB (1 << 22) +// #elif TICC3200_SYSDIV2LSB_ENABLE == FALSE +// #define TICC3200_SYSDIV2LSB (0 << 22) +// #else +// #error "Invalid value for TICC3200_SYSDIV2LSB_ENABLE defined" +// #endif + +// #if TICC3200_BYPASS_VALUE == 1 +// #define TICC3200_SRC 16000000 +// #elif TICC3200_BYPASS_VALUE == 0 +// #define TICC3200_SRC (200000000 + (TICC3200_DIV400_VALUE * 200000000)) +// #else +// #error "Invalid value for TICC3200_BYPASS_VALUE defined" +// #endif + +// #if (TICC3200_OSCSRC == TICC3200_RCC_OSCSRC_MOSC) && (TICC3200_MOSC_ENABLE == FALSE) +// #error "Main Oscillator selected but not enabled" +// #endif + +/* + * System Clock calculation + */ +#define TICC3200_SYSCLK (TICC3200_SRC / (((TICC3200_SYSDIV_VALUE << TICC3200_DIV400_VALUE /*& TICC3200_BYPASS_VALUE*/) | (TICC3200_SYSDIV2LSB >> 22)) + 1)) + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* Various helpers.*/ +#include "nvic.h" +#include "ticc3200_isr.h" +// #include "TICC3200_udma.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void ti3200_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_LLD_H */ + +/** + * @} + */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/ticc3200_isr.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/ticc3200_isr.h new file mode 100644 index 00000000..889551d8 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/ticc3200_isr.h @@ -0,0 +1,40 @@ + +/** + * @file TICC3200/ticc3200_isr.h + * @brief TICC3200 ISR remapper driver header. + * + * @addtogroup TICC3200_ISR + * @{ + */ + +#ifndef _TICC3200_ISR_H_ +#define _TICC3200_ISR_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name ISR names and numbers remapping + * @{ + */ + +// /* UDMA units.*/ +// #define TICC3200_UDMA_SW_HANDLER VectorF8 +// #define TICC3200_UDMA_ERR_HANDLER VectorFC + +// #define TICC3200_UDMA_SW_NUMBER 46 +// #define TICC3200_UDMA_ERR_NUMBER 47 + +/* GPIO units.*/ +#define TICC3200_GPIOA_HANDLER INT_GPIOA0 +#define TICC3200_GPIOB_HANDLER INT_GPIOA1 +#define TICC3200_GPIOC_HANDLER INT_GPIOA2 +#define TICC3200_GPIOD_HANDLER INT_GPIOA3 + +#define TICC3200_GPIOA_NUMBER 0 +#define TICC3200_GPIOB_NUMBER 1 +#define TICC3200_GPIOC_NUMBER 2 +#define TICC3200_GPIOD_NUMBER 3 + +#endif // _TICC3200_ISR_H_ \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/ticc3200_registry.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/ticc3200_registry.h new file mode 100644 index 00000000..0f974458 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/ports/TI/TICC3200/ticc3200_registry.h @@ -0,0 +1,31 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/** + * @file TICC3200/TICC3200_registry.h + * @brief TICC3200 capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _TICC3200_REGISTRY_H_ +#define _TICC3200_REGISTRY_H_ + +#define TICC3200_HAS_GPIOA TRUE +#define TICC3200_HAS_GPIOB TRUE +#define TICC3200_HAS_GPIOC TRUE + +#define TICC3200_HAS_GPT0 TRUE +#define TICC3200_HAS_GPT1 TRUE +#define TICC3200_HAS_GPT2 TRUE +#define TICC3200_HAS_GPT3 TRUE + +#define TICC3200_HAS_UART0 TRUE +#define TICC3200_HAS_UART1 TRUE + +#define TICC3200_HAS_RTC TRUE + +#endif // _TICC3200_REGISTRY_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/hal_community.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/hal_community.c new file mode 100644 index 00000000..20bed282 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/hal_community.c @@ -0,0 +1,68 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +/////////////////////////////////////////////////////////////////////////////// +// Driver local definitions. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver exported variables. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver local variables and types. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver local functions. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver exported functions. // +/////////////////////////////////////////////////////////////////////////////// + +// HAL initialization (community part). +void halCommunityInit(void) { + +/////////////////////////////// +// from ChibiOS-Contrib repo // +/////////////////////////////// + +#if (HAL_USE_USBH == TRUE) + usbhInit(); +#endif + +/////////////////////////// +// nanoFramework overlay // +/////////////////////////// + +#if (HAL_USE_STM32_FLASH == TRUE) + stm32FlashInit(); +#endif + +#if (HAL_USE_STM32_CRC == TRUE) + crcInit(); +#endif + +#if (HAL_USE_STM32_RNG == TRUE) + rngInit(); +#endif + +#if HAL_USE_FSMC + stm32FsmcInit(); +#endif + +#if (HAL_USE_STM32_ONEWIRE == TRUE) + oneWireInit(); +#endif + +#if (HAL_USE_STM32_QSPI == TRUE) + qspiInit(); +#endif + +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_crc/hal_stm32_crc.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_crc/hal_stm32_crc.c new file mode 100644 index 00000000..0ba165f3 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_crc/hal_stm32_crc.c @@ -0,0 +1,85 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +// This driver is slightly different from the usual ChibiOS drivers because the calls don't require an instance of the driver. +// The reason for this is that the hardware only has a single instance of the peripheral +// so there is no point on wasting memory with calling functions with dummy arguments. + + +#include +#include + +#if (HAL_USE_STM32_CRC == TRUE) + +/////////////////////////////////////////////////////////////////////////////// +// Driver local definitions. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver exported variables. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver local variables and types. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver local functions. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver exported functions. // +/////////////////////////////////////////////////////////////////////////////// + +// Initializes the CRC Driver +void crcInit(void) { + crc_lld_init(); +} + +// Configures and activates the CRC peripheral +void crcStart(const crcConfig *config) { + + // better lock this to setup the driver and start the peripheral + osalSysLock(); + + crc_lld_start(config); + + osalSysUnlock(); +} + +// Deactivates the CRC peripheral +void crcStop() { + + // better lock this to stop the peripheral + osalSysLock(); + + crc_lld_stop(); + + osalSysUnlock(); +} + +// Resets the current CRC calculation +void crcReset() { + osalSysLock(); + crc_lld_reset(); + osalSysUnlock(); +} + +uint32_t crcCompute(const void* buffer, int size, uint32_t initialCrc) { + + return crc_lld_compute(buffer, size, initialCrc); +} + +void crcAquireModule() { + + crc_lld_aquire(); +} + +void crcReleaseModule() { + + crc_lld_release(); +} + +#endif diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_flash/hal_stm32_flash.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_flash/hal_stm32_flash.c new file mode 100644 index 00000000..b4ccb743 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_flash/hal_stm32_flash.c @@ -0,0 +1,70 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "hal.h" +#include + +#if (HAL_USE_STM32_FLASH == TRUE) + +/////////////////////////////////////////////////////////////////////////////// +// Driver local definitions. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver exported variables. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver local variables and types. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver local functions. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver exported functions. // +/////////////////////////////////////////////////////////////////////////////// + +void stm32FlashInit(void) { + flash_lld_init(); +} + +void stm32FlashObjectInit(SMT32FlashDriver* flash) { + (void)flash; +} + + +void stm32FlashReadBytes(uint32_t startAddress, uint32_t length, uint8_t* buffer) { + osalDbgCheck((startAddress > FLASH_BASE) && (length > 0U) && (buffer != NULL)); + + flash_lld_readBytes(startAddress, length, buffer); +} + +int stm32FlashWrite(uint32_t startAddress, uint32_t length, const uint8_t* buffer) { + osalDbgCheck((startAddress > FLASH_BASE) && (length > 0U) && (buffer != NULL)); + + return flash_lld_write(startAddress, length, buffer); +} + +int stm32FlashIsErased(uint32_t startAddress, uint32_t length) { + osalDbgCheck((startAddress > FLASH_BASE) && (length > 0U)); + + return flash_lld_isErased(startAddress, length); +} + +int stm32FlashErase(uint32_t address) { + osalDbgCheck(address > FLASH_BASE); + + return flash_lld_erase(address); +} + +uint8_t stm32FlashGetSector(uint32_t address) { + return flash_lld_getSector(address); +} + + +#endif + diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_fsmc/hal_stm32_fsmc.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_fsmc/hal_stm32_fsmc.c new file mode 100644 index 00000000..82b85d86 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_fsmc/hal_stm32_fsmc.c @@ -0,0 +1,149 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2014 Uladzimir Pylinsky aka barthess +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include "hal_stm32_fsmc.h" + +#if (HAL_USE_FSMC == TRUE) +/////////////////////////////////////////////////////////////////////////////// +// Driver local definitions. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver exported variables. // +/////////////////////////////////////////////////////////////////////////////// + +/** + * @brief FSMC1 driver identifier. + */ +#if STM32_FSMC_USE_FSMC1 +FSMCDriver FSMCD1; +#endif + +/////////////////////////////////////////////////////////////////////////////// +// Driver local variables and types. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver local functions. // +/////////////////////////////////////////////////////////////////////////////// + +/////////////////////////////////////////////////////////////////////////////// +// Driver exported functions. // +/////////////////////////////////////////////////////////////////////////////// + +// Low level FSMC driver initialization. +void stm32FsmcInit(void) { + + if (FSMCD1.state == FSMC_UNINIT) { + FSMCD1.state = FSMC_STOP; + +#if STM32_SRAM_USE_FSMC_SRAM1 + FSMCD1.sram1 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE); +#endif + +#if STM32_SRAM_USE_FSMC_SRAM2 + FSMCD1.sram2 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8); +#endif + +#if STM32_SRAM_USE_FSMC_SRAM3 + FSMCD1.sram3 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 2); +#endif + +#if STM32_SRAM_USE_FSMC_SRAM4 + FSMCD1.sram4 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 3); +#endif + +#if STM32_NAND_USE_FSMC_NAND1 + FSMCD1.nand1 = (FSMC_NAND_TypeDef *)FSMC_Bank2_R_BASE; +#endif + +#if STM32_NAND_USE_FSMC_NAND2 + FSMCD1.nand2 = (FSMC_NAND_TypeDef *)FSMC_Bank3_R_BASE; +#endif + +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) || \ + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) + #if STM32_USE_FSMC_SDRAM + FSMCD1.sdram = (FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE; + #endif +#endif + } +} + +// Configures and activates the FSMC peripheral. +// fsmcp pointer to the @p FSMCDriver object +void fsmc_start(FSMCDriver *fsmcp) { + + osalDbgAssert((fsmcp->state == FSMC_STOP) || (fsmcp->state == FSMC_READY), + "invalid state"); + + if (fsmcp->state == FSMC_STOP) { + /* Enables the peripheral.*/ +#if STM32_FSMC_USE_FSMC1 + if (&FSMCD1 == fsmcp) { +#ifdef rccResetFSMC + rccResetFSMC(); +#endif + rccEnableFSMC(FALSE); +#if HAL_USE_NAND + nvicEnableVector(STM32_FSMC_NUMBER, STM32_FSMC_FSMC1_IRQ_PRIORITY); +#endif + } +#endif /* STM32_FSMC_USE_FSMC1 */ + + fsmcp->state = FSMC_READY; + } +} + +// Deactivates the FSMC peripheral. +// emcp pointer to the @p FSMCDriver object +void fsmc_stop(FSMCDriver *fsmcp) { + + if (fsmcp->state == FSMC_READY) { + /* Resets the peripheral.*/ +#ifdef rccResetFSMC + rccResetFSMC(); +#endif + + /* Disables the peripheral.*/ +#if STM32_FSMC_USE_FSMC1 + if (&FSMCD1 == fsmcp) { +#if HAL_USE_NAND + nvicDisableVector(STM32_FSMC_NUMBER); +#endif + rccDisableFSMC(); + } +#endif /* STM32_FSMC_USE_FSMC1 */ + + fsmcp->state = FSMC_STOP; + } +} + +// FSMC shared interrupt handler. +CH_IRQ_HANDLER(STM32_FSMC_HANDLER) { + + CH_IRQ_PROLOGUE(); +#if STM32_NAND_USE_FSMC_NAND1 + if (FSMCD1.nand1->SR & FSMC_SR_ISR_MASK) { + NANDD1.isr_handler(&NANDD1); + } +#endif +#if STM32_NAND_USE_FSMC_NAND2 + if (FSMCD1.nand2->SR & FSMC_SR_ISR_MASK) { + NANDD2.isr_handler(&NANDD2); + } +#endif + CH_IRQ_EPILOGUE(); +} + +#endif /* HAL_USE_FSMC */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_onewire/hal_stm32_onewire.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_onewire/hal_stm32_onewire.c new file mode 100644 index 00000000..6df9df43 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_onewire/hal_stm32_onewire.c @@ -0,0 +1,1033 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/* + * Hardware Abstraction Layer for ONEWIRE Unit + */ +#include +#include + +#if (HAL_USE_STM32_ONEWIRE == TRUE) + +#include + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define PAGE_LENGTH 64 +#define PAGE_LENGTH_HYGRO 32 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +uint32_t utilcrc16 = 0; +uint8_t utilcrc8; + +// local variables for this module to hold search state information + +uint8_t LastDiscrepancy; +uint8_t LastFamilyDiscrepancy; +uint8_t LastDevice; + +uint8_t SerialNum[8]; + +#if ONEWIRE_CRC8_TABLE + +static const uint8_t dscrc_table[] = { + 0, 94,188,226, 97, 63,221,131,194,156,126, 32,163,253, 31, 65, + 157,195, 33,127,252,162, 64, 30, 95, 1,227,189, 62, 96,130,220, + 35,125,159,193, 66, 28,254,160,225,191, 93, 3,128,222, 60, 98, + 190,224, 2, 92,223,129, 99, 61,124, 34,192,158, 29, 67,161,255, + 70, 24,250,164, 39,121,155,197,132,218, 56,102,229,187, 89, 7, + 219,133,103, 57,186,228, 6, 88, 25, 71,165,251,120, 38,196,154, + 101, 59,217,135, 4, 90,184,230,167,249, 27, 69,198,152,122, 36, + 248,166, 68, 26,153,199, 37,123, 58,100,134,216, 91, 5,231,185, + 140,210, 48,110,237,179, 81, 15, 78, 16,242,172, 47,113,147,205, + 17, 79,173,243,112, 46,204,146,211,141,111, 49,178,236, 14, 80, + 175,241, 19, 77,206,144,114, 44,109, 51,209,143, 12, 82,176,238, + 50,108,142,208, 83, 13,239,177,240,174, 76, 18,145,207, 45,115, + 202,148,118, 40,171,245, 23, 73, 8, 86,180,234,105, 55,213,139, + 87, 9,235,181, 54,104,138,212,149,203, 41,119,244,170, 72, 22, + 233,183, 85, 11,136,214, 52,106, 43,117,151,201, 74, 20,246,168, + 116, 42,200,150, 21, 75,169,247,182,232, 10, 84,215,137,107, 53}; + +#endif // ONEWIRE_CRC8_TABLE + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + + +// Initializes the ONEWIRE Driver +void oneWireInit(void) { + oneWire_lld_init(); +} + +// Configures and activates the CRC peripheral +void oneWireStart() { + + // better lock this to setup the driver and start the peripheral + osalSysLock(); + + oneWire_lld_start(); + + osalSysUnlock(); +} + +// Deactivates the ONEWIRE peripheral +void oneWireStop() { + + // better lock this to stop the peripheral + osalSysLock(); + + oneWire_lld_stop(); + + osalSysUnlock(); +} + + +#if (ONEWIRE_USE_MUTUAL_EXCLUSION == TRUE) + +void oneWireAcquireModule() { + + oneWire_lld_aquire(); +} + +void oneWireReleaseModule() { + + oneWire_lld_release(); +} + +#endif /* ONEWIRE_USE_MUTUAL_EXCLUSION == TRUE */ + +// Calculate a new CRC16 from the input data short. Return the current +// CRC16 and also update the global variable CRC16. +uint32_t docrc16(uint32_t cdata) +{ + uint8_t oddparity[] = { 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0 }; + + cdata = (cdata ^ (utilcrc16 & 0xff)) & 0xff; + utilcrc16 >>= 8; + + if ((oddparity[(cdata & 0xf)] ^ oddparity[(cdata >> 4)]) == 1) + { + utilcrc16 ^= 0xC001; + } + + cdata <<= 6; + utilcrc16 ^= cdata; + cdata <<= 1; + utilcrc16 ^= cdata; + + return utilcrc16; +} + +// Reset CRC16 to the value passed in +void setcrc16(uint32_t reset) +{ + utilcrc16 = reset; +} + +#if ONEWIRE_CRC8_TABLE + +// compute CRC8 using lookup table (FLASH expensive) + +uint8_t doCrc8(uint8_t oldCrc, uint8_t x) +{ + return dscrc_table[oldCrc ^ x]; +} + +#else + +// compute CRC8 using running algorith (slower but saves FLASH) + +uint8_t doCrc8(uint8_t oldCrc, uint8_t x) +{ + uint8_t crc = oldCrc; + + for (uint8_t i = 8; i; i--) + { + uint8_t mix = (crc ^ x) & 0x01; + crc >>= 1; + if (mix) crc ^= 0x8C; + x >>= 1; + } + + return crc; +} + +#endif // ONEWIRE_CRC8_TABLE + + +/******************************************************************************* +** NAME: oneWireTouchReset ************************************************* +******************************************************************************** + +DESCRIPTION: +Reset all of the devices on the 1-Wire Net and return the result. + +USAGE EXAMPLES: + +AUTHOR: jassimoes + +COMMENTS: +-------------------------------------------------------------------------- + + Returns: TRUE(1): presense pulse(s) detected, device(s) reset + FALSE(0): no presense pulses detected + +*******************************************************************************/ +uint8_t oneWireTouchReset(void) +{ + return oneWire_lld_TouchReset(); +} + +/******************************************************************************* +** NAME: oneWireTouchBit *************************************************** +******************************************************************************** + +DESCRIPTION: + * Send 1 bit of communication to the 1-Wire Net and return the + * result 1 bit read from the 1-Wire Net. The parameter 'sendbit' + * least significant bit is used and the least significant bit + * of the result is the return bit. + * @return a SMALLINT with 0 bit read from sendbit or 1 bit read fromsendbit + * @param sendbit the least significant bit is the bit to send + +USAGE EXAMPLES: + +AUTHOR: jassimoes + +COMMENTS: + +*******************************************************************************/ +bool oneWireTouchBit(bool sendbit) +{ + return oneWire_lld_TouchBit(sendbit); +} + +/******************************************************************************* +** NAME: oneWireTouchByte ************************************************** +******************************************************************************** + +DESCRIPTION: + // Send 8 bits of communication to the 1-Wire Net and return the + // result 8 bits read from the 1-Wire Net. The parameter 'sendbyte' + // least significant 8 bits are used and the least significant 8 bits + // of the result is the return byte. + // + // 'sendbyte' - 8 bits to send (least significant byte) + // + // Returns: 8 bits read from sendbyte + +USAGE EXAMPLES: + +AUTHOR: jassimoes + +COMMENTS: + +*******************************************************************************/ +uint8_t oneWireTouchByte(uint8_t sendbyte) +{ + return oneWire_lld_TouchByte(sendbyte); +} + +/******************************************************************************* +** NAME: oneWireWriteByte ************************************************** +******************************************************************************** + +DESCRIPTION: + // Send 8 bits of communication to the 1-Wire Net and verify that the + // 8 bits read from the 1-Wire Net is the same (write operation). + // The parameter 'sendbyte' least significant 8 bits are used. + // + // 'sendbyte' - 8 bits to send (least significant byte) + // + // Returns: TRUE: bytes written and echo was the same + // FALSE: echo was not the same + +USAGE EXAMPLES: + +AUTHOR: jassimoes + +COMMENTS: + +*******************************************************************************/ +uint8_t oneWireWriteByte(uint8_t sendbyte) +{ + return (oneWireTouchByte(sendbyte) == sendbyte) ? TRUE : FALSE; +} + +/******************************************************************************* +** NAME: oneWireReadByte *************************************************** +******************************************************************************** + +DESCRIPTION: + // Send 8 bits of read communication to the 1-Wire Net and and return the + // result 8 bits read from the 1-Wire Net. + // + // Returns: 8 bytes read from 1-Wire Net + +USAGE EXAMPLES: + +AUTHOR: jassimoes + +COMMENTS: + +*******************************************************************************/ +uint8_t oneWireReadByte(void) +{ + return oneWireTouchByte(0xFF); +} + +/******************************************************************************* +** NAME: oneWireSerialNum ************************************************** +******************************************************************************** + +DESCRIPTION: + // The 'oneWireSerialNum' function either reads or sets the SerialNum buffer + // that is used in the search functions 'owFirst' and 'owNext'. + // This function contains two parameters, 'serialnum_buf' is a pointer + // to a buffer provided by the caller. 'serialnum_buf' should point to + // an array of 8 unsigned chars. The second parameter is a flag called + // 'do_read' that is TRUE (1) if the operation is to read and FALSE + // (0) if the operation is to set the internal SerialNum buffer from + // the data in the provided buffer. + // + // 'serialnum_buf' - buffer to that contains the serial number to set + // when do_read = FALSE (0) and buffer to get the serial + // number when do_read = TRUE (1). + // 'do_read' - flag to indicate reading (1) or setting (0) the current + // serial number. + // + +USAGE EXAMPLES: + +AUTHOR: jassimoes + +COMMENTS: + +*******************************************************************************/ +void oneWireSerialNum(uint8_t* serialnum_buf, uint8_t do_read) +{ + uint8_t i; + + //-------------------------------------------------// + // read the internal buffer and place in 'serialnum_buf' + if (do_read) + { + for (i = 0; i < 8; i++) + { + serialnum_buf[i] = SerialNum[i]; + } + } + // set the internal buffer from the data in 'serialnum_buf' + else + { + for (i = 0; i < 8; i++) + { + SerialNum[i] = serialnum_buf[i]; + } + } +} + +/******************************************************************************* +** NAME: oneWireAccess ***************************************************** +******************************************************************************** + +DESCRIPTION: + //-------------------------------------------------------------------------- + // The 'owAccess' function resets the 1-Wire and sends a MATCH Serial + // Number command followed by the current SerialNum code. After this + // function is complete the 1-Wire device is ready to accept device-specific + // commands. + // + // Returns: TRUE (1) : reset indicates present and device is ready + // for commands. + // FALSE (0): reset does not indicate presence or echos 'writes' + // are not correct. + // + +USAGE EXAMPLES: + +AUTHOR: jassimoes + +COMMENTS: + +*******************************************************************************/ +uint8_t oneWireAccess(void) +{ + uint8_t sendpacket[9]; + uint8_t i; + + // + //-------------------------------------------------// + // reset the 1-wire + if (oneWireTouchReset()) + { + // create a buffer to use with block function + // match Serial Number command 0x55 + sendpacket[0] = MATCH_ROM; + // Serial Number + for (i = 1; i < 9; i++) + { + sendpacket[i] = SerialNum[i-1]; + } + + // send/recieve the transfer buffer + if (oneWireBlock(FALSE, sendpacket, 9)) + { + // verify that the echo of the writes was correct + for (i = 1; i < 9; i++) + { + if (sendpacket[i] != SerialNum[i-1]) + { + return FALSE; + } + } + + if (sendpacket[0] != MATCH_ROM) + { + //OWERROR(//OWERROR_WRITE_VERIFY_FAILED); + return FALSE; + } + else + { + return TRUE; + } + } + } + + // reset or match echo failed + return FALSE; +} + +/******************************************************************************* +** NAME: oneWireBlock ****************************************************** +******************************************************************************** + +DESCRIPTION: + // The 'oneWireBlock' transfers a block of data to and from the + // 1-Wire Net with an optional reset at the begining of communication. + // The result is returned in the same buffer. + // + // 'doReset' - cause a oneWireTouchReset to occure at the begining of + // communication TRUE(1) or not FALSE(0) + // 'tran_buf' - pointer to a block of unsigned + // chars of length 'TranferLength' that will be sent + // to the 1-Wire Net + // 'tran_len' - length in bytes to transfer + // Supported devices: all + // + // Returns: TRUE (1) : The optional reset returned a valid + // presence (doReset == TRUE) or there + // was no reset required. + // FALSE (0): The reset did not return a valid prsence + // (doReset == TRUE). + // + // The maximum tran_len is 160 + +USAGE EXAMPLES: + +AUTHOR: jassimoes + +COMMENTS: + +*******************************************************************************/ +uint8_t oneWireBlock(uint8_t doReset, uint8_t* tran_buf, uint8_t tran_len) +{ + uint8_t i; + // + //-------------------------------------------------// + // check for a block too big + if (tran_len > 160) + { + // error: BLOCK TOO BIG + return FALSE; + } + + // check if need to do a owTouchReset first + if (doReset) + { + if (!oneWireTouchReset()) + { + // error: NO DEVICES ON NET + return FALSE; + } + } + + // send and receive the buffer + for (i = 0; i < tran_len; i++) + { + tran_buf[i] = oneWireTouchByte(tran_buf[i]); + } + + return TRUE; +} + +/******************************************************************************* +** NAME: oneWireWriteMemory ************************************************** +******************************************************************************** + +DESCRIPTION: +write block of memory to iButton memory + +USAGE EXAMPLES: + +AUTHOR: jassimoes + +COMMENTS: + +*******************************************************************************/ +uint8_t oneWireWriteMemory(uint8_t* buf, uint32_t ln, uint32_t adr) +{ + //-------------------------------------------------// + // write to scratch and then copy + if (oneWireWriteScratchpad(buf, ln, adr)) + return oneWireCopyScratchpad(ln, adr); + + // end function + return FALSE; +} + +/******************************************************************************* +** NAME: oneWireCopyScratchpad *********************************************** +******************************************************************************** + +DESCRIPTION: +copy scratchpad contempts + +USAGE EXAMPLES: + +AUTHOR: jassimoes + +COMMENTS: +Only valid for DS1921G,H,Z + +*******************************************************************************/ +uint8_t oneWireCopyScratchpad(uint32_t ln, uint32_t adr) +{ + // local variables + uint8_t i; + uint8_t pbuf[15]; + + //-------------------------------------------------// + // check for presence indicator + if (oneWireAccess()) + { + // construct a packet to send + pbuf[0] = COPY_SCRPAD; // copy scratch command + pbuf[1] = (adr & 0xFF); // address 1 + pbuf[2] = ((adr >> 8) & 0xFF); // address 2 + pbuf[3] = (adr + ln - 1) & 0x1F; // offset + for (i = 0; i <= 9; i++) + pbuf[4 + i] = 0xFF; // result of copy + // perform the block + if (oneWireBlock(FALSE, pbuf, 14)) { + if ((pbuf[13] == 0x55) || (pbuf[13] == 0xAA)) + return TRUE; + } + } + + // end function + return FALSE; +} + +/******************************************************************************* +** NAME: oneWireWriteScratchpad ********************************************** +******************************************************************************** + +DESCRIPTION: +copy scratchpad contempts + +USAGE EXAMPLES: + +AUTHOR: jassimoes + +COMMENTS: +Only valid for DS1921G,H,Z + +*******************************************************************************/ +uint8_t oneWireWriteScratchpad(uint8_t* buf, uint32_t ln, uint32_t adr) +{ + uint8_t i; + uint8_t pbuf[40]; + + //-------------------------------------------------// + // check for presence indicator + if (oneWireAccess()) + { + // construct a packet to send + pbuf[0] = WR_SCRPAD; // write scratch command + pbuf[1] = (adr & 0xFF); // address 1 + pbuf[2] = ((adr >> 8) & 0xFF); // address 2 + + // the write bytes + for (i = 0; i < ln; i++) + pbuf[3 + i] = (uint8_t)(buf[i]); // data + + // perform the block + if (!oneWireBlock(FALSE, pbuf, ln+3)) + return FALSE; + + // Now read back the scratch + if (oneWireAccess()) { + // construct a packet to send + pbuf[0] = RD_SCRPAD; // read scratch command + pbuf[1] = 0xFF; // address 1 + pbuf[2] = 0xFF; // address 2 + pbuf[3] = 0xFF; // offset + + // the write bytes + for (i = 0; i < ln; i++) + pbuf[4 + i] = 0xFF; // data + + // perform the block + if (!oneWireBlock(FALSE, pbuf, ln+4)) + return FALSE; + + // read address 1 + if (pbuf[1] != (adr & 0xFF)) + return FALSE; + // read address 2 + if (pbuf[2] != ((adr >> 8) & 0xFF)) + return FALSE; + // read the offset + if (pbuf[3] != ((adr + ln - 1) & 0x1F)) + return FALSE; + // read and compare the contents + for (i = 0; i < ln; i++) { + if (pbuf[4 + i] != buf[i]) + return FALSE; + } + // success + return TRUE; + } + } + + // end function + return FALSE; + +} + +/******************************************************************************* +** NAME: oneWireReadPage ***************************************************** +******************************************************************************** + +DESCRIPTION +read memory page + +USAGE EXAMPLES: + +AUTHOR: jassimoes + +COMMENTS: +Only valid for DS1921G,H,Z +Simplification of addressing using SKIP ROM + +*******************************************************************************/ +uint8_t oneWireReadPage(uint32_t start_pg, uint8_t* finalbuf) +{ + uint32_t lastcrc16; + uint32_t len,i; + + // create a packet to read a page + len = 0; + setcrc16(0x0); + // skip ROM + finalbuf[len++] = SKIP_ROM; + // read memory with crc command + finalbuf[len] = RD_MEMORY_CRC; + docrc16(finalbuf[len++]); + + // address + finalbuf[len] = (uint8_t)((start_pg << 5) & 0xFF); + docrc16(finalbuf[len++]); + finalbuf[len] = (uint8_t)(start_pg >> 3); + docrc16(finalbuf[len++]); + + // set 32 reads for data and 2 for crc + for (i = 0; i < 34; i++) + { + finalbuf[len++] = 0xFF; + } + // send the bytes + if (oneWireBlock(TRUE , finalbuf, len)) + { + // calculate the CRC over the last 34 bytes + for (i = 0; i < 34; i++) + { + lastcrc16 = docrc16(finalbuf[len - 34 + i]); + } + // check crc + if (lastcrc16 == 0xB001) + { + // copy the data into the buffer without the command and parameters + for (i = 0; i < 32; i++) + { + finalbuf[i] = finalbuf[i + 4]; + } + } + else + { + return FALSE; + } + } + else + { + return FALSE; + } + + // end function + return TRUE; +} + +/******************************************************************************* +** NAME: oneWireReadPageCRCEE77 ********************************************** +******************************************************************************** + +DESCRIPTION + Read a complete memory page with CRC verification provided by the + device. Not supported by all devices. See the method + 'hasPageAutoCRCEE()'. + + bank to tell what memory bank of the ibutton to use. + portnum the port number of the port being used for the + 1-Wire Network. + SNum the serial number for the part. + psw 8 byte password + page the page to read + rd_cont if 'true' then device read is continued without + re-selecting. This can only be used if the new + read() continious where the last one led off + and it is inside a 'beginExclusive/endExclusive' + block. + buff byte array containing data that was read + + @return - returns '0' if the read page wasn't completed. + '1' if the operation is complete. + + +USAGE EXAMPLES: + +AUTHOR: jassimoes + +COMMENTS: + +*******************************************************************************/ +uint8_t oneWireReadPageCRCEE77(uint32_t page, uint8_t *buff) +{ + uint8_t i, send_len=0, lsCRC16; + uint8_t raw_buf[15]; + uint32_t str_add; + uint32_t lastcrc16; + + // select the device + if (!oneWireAccess()) + { + return FALSE; + } + + // command, address, offset, password (except last byte) + raw_buf[send_len++] = READ_MEMORY_PSW_COMMAND; + if(SerialNum[0] == 0x37) + { + str_add = page * PAGE_LENGTH; + } + else + { + str_add = page * PAGE_LENGTH_HYGRO; + } + raw_buf[send_len++] = str_add & 0xFF; + raw_buf[send_len++] = ((str_add & 0xFFFF) >> 8) & 0xFF; + + // calculate the CRC16 + setcrc16(0); + for(i = 0; i < send_len; i++) + lastcrc16 = docrc16(raw_buf[i]); + + for (i = 0; i < 8; i++) + raw_buf[send_len++] = 0xFF; + + + if(SerialNum[0] == 0x37) + { + // send block (check copy indication complete) + if(!oneWireBlock(FALSE,(uint8_t*)raw_buf,(send_len-1))) + { + return FALSE; + } + + } + else + { + if(!oneWireBlock(FALSE,(uint8_t*)raw_buf,send_len)) + { + return FALSE; + } + } + + // set the read bytes + if(SerialNum[0] == 0x37) + { + + for (i = 0; i < PAGE_LENGTH; i++) + buff[i] = 0xFF; + } + else + { + for(i=0; i 0) + { + // all connected devices reply with 0 or 1 + // write bit to perform search + outBit = attempt >> 1; + } + else + { + if (romBitIndex < LastDiscrepancy) + { + outBit = ((SerialNum[romByteIndex] & bitMask) > 0); + } + else + { + // set to 1 if it's the same, otherwise 0 + outBit = (romBitIndex == LastDiscrepancy); + } + + // on 0 record position on bitMask + if (outBit == 0) + { + discrepMarker = romBitIndex; + } + } + + // isolate bit in ROM[n] with bitMask + if (outBit == 1) + { + SerialNum[romByteIndex] |= bitMask; + } + else + { + SerialNum[romByteIndex] &= ~bitMask; + } + + // ROM search write + oneWireTouchBit(outBit); + + romBitIndex++; + + bitMask = bitMask << 1; + + // if the mask has reached 0 then go for a new ROM + if (bitMask == 0) + { + // reset mask and perform CRC8 + lastcrc8 = doCrc8(lastcrc8, SerialNum[romByteIndex]); + + romByteIndex++; + bitMask++; + } + } + + } + while (romByteIndex < 8); // loop until we have all ROM bytes + + if ((romBitIndex < 65) || (lastcrc8 != 0)) + { + // search was unsuccessful reset the last discrepancy + LastDiscrepancy = 0; + } + else + { + // search was successful: set last discrepancy, device and result + LastDiscrepancy = discrepMarker; + LastDevice = (LastDiscrepancy == 0); + + // search isn't completed there are more devices present in the bus + result = TRUE; + } + + return result; +} + +#endif /* HAL_USE_STM32_ONEWIRE */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_qspi/hal_stm32_qspi.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_qspi/hal_stm32_qspi.c new file mode 100644 index 00000000..232e3278 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_qspi/hal_stm32_qspi.c @@ -0,0 +1,63 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/* + * Hardware Abstraction Layer for QSPI + */ +#include +#include + +#if (HAL_USE_STM32_QSPI == TRUE) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + + +// Initializes the QSPI Driver +void qspiInit() +{ + qspi_lld_init(); +} + +// Configures and activates the QSPI peripheral +void qspiStart(QSPI_HandleTypeDef* qspi) +{ + // better lock this to setup the driver and start the peripheral + osalSysLock(); + + qspi_lld_start(qspi); + + osalSysUnlock(); +} + +// Deactivates the QSPI peripheral +void qspiStop(QSPI_HandleTypeDef* qspi) +{ + // better lock this to stop the peripheral + osalSysLock(); + + qspi_lld_stop(qspi); + + osalSysUnlock(); +} + +#endif /* HAL_USE_STM32_QSPI */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_rng/hal_stm32_rng.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_rng/hal_stm32_rng.c new file mode 100644 index 00000000..6a4ed5b8 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/os/hal/src/stm32_rng/hal_stm32_rng.c @@ -0,0 +1,94 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/* + * Hardware Abstraction Layer for RNG Unit + */ +#include +#include + +#if (HAL_USE_STM32_RNG == TRUE) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + + +// Initializes the RNG Driver +void rngInit(void) { + rng_lld_init(); +} + +// Configures and activates the CRC peripheral +void rngStart() { + + // better lock this to setup the driver and start the peripheral + osalSysLock(); + + rng_lld_start(); + + osalSysUnlock(); +} + +// Deactivates the RNG peripheral +void rngStop() { + + // better lock this to stop the peripheral + osalSysLock(); + + rng_lld_stop(); + + osalSysUnlock(); +} + + +#if (RNG_USE_MUTUAL_EXCLUSION == TRUE) + +void rngAquireModule() { + + rng_lld_aquire(); +} + +void rngReleaseModule() { + + rng_lld_release(); +} + +#endif /* RNG_USE_MUTUAL_EXCLUSION == TRUE */ + + +uint32_t rngGenerateRandomNumber() { + uint32_t randomNumber; + osalSysLock(); + randomNumber = rng_lld_GenerateRandomNumber(); + osalSysUnlock(); + return randomNumber; +} + +uint32_t rngGetLastRandomNumber() { + uint32_t randomNumber; + osalSysLock(); + randomNumber = rng_lld_GetLastRandomNumber(); + osalSysUnlock(); + return randomNumber; +} + +#endif /* HAL_USE_STM32_RNG */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/stm32-internal-flash-driver.md b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/stm32-internal-flash-driver.md new file mode 100644 index 00000000..39500086 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/nf-overlay/stm32-internal-flash-driver.md @@ -0,0 +1,31 @@ +# Driver for SMT32 internal flash + +This driver enables **nanoFramework** to access the internal flash for STM32 parts taking care of the low level details and implementation specifics. + +In order to enable/use it the developer has to set HAL_USE_STM32_FLASH to TRUE on the halconf_nf.h provided in the reference implementations. +_Note: to enable the driver the developer has to also enable the HAL_USE_COMMUNITY 'master switch' on that same file._ + +There are currently two versions of the driver: +- FLASHv1: suitable for F0 series +- FLASHv2: suitable for F4 series + + +The functions provided by driver are: +- ```void stm32FlashReadBytes(uint32_t startAddress, uint32_t length, uint8_t* buffer)``` + - startAddress: the flash start address from where to read data + - length: how many bytes to be read from the flash + - buffer: pointer to the buffer where to read the flash data + +- ```int stm32FlashWrite(uint32_t startAddress, uint32_t length, const uint8_t* buffer)``` + - startAddress: the flash start address where to write data to + - length: how many bytes to be written to the flash + - buffer: pointer to the buffer whit the data to be written to the flash + +- ```int stm32FlashIsErased(uint32_t startAddress, uint32_t length)``` + - startAddress: the flash start address to check if it's erased + - length: length of the flash segment to check if it's erased + +- ```int stm32FlashErase(uint32_t address)``` + - address: the flash address belonging to the segment to be erased (this can be a block or a page depending on the flash organization of the target series) + +The driver performs basic and trivial checks on the arguments passed. diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/spiffs/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/spiffs/CMakeLists.txt new file mode 100644 index 00000000..f868eac1 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/spiffs/CMakeLists.txt @@ -0,0 +1,14 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# include SPIFFS sources, if feature is enabled +if(NF_FEATURE_USE_SPIFFS) + list(APPEND TARGET_CHIBIOS_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/hal_spiffs.c") + list(APPEND TARGET_CHIBIOS_COMMON_INCLUDE_DIRS "${CMAKE_CURRENT_SOURCE_DIR}") +endif() + +# make var global +set(TARGET_CHIBIOS_COMMON_SOURCES ${TARGET_CHIBIOS_COMMON_SOURCES} CACHE INTERNAL "make global") +set(TARGET_CHIBIOS_COMMON_INCLUDE_DIRS ${TARGET_CHIBIOS_COMMON_INCLUDE_DIRS} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/spiffs/hal_spiffs.c b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/spiffs/hal_spiffs.c new file mode 100644 index 00000000..e6108a7e --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/spiffs/hal_spiffs.c @@ -0,0 +1,141 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include + +extern s32_t hal_spiffs_erase(u32_t addr, u32_t size); +extern s32_t hal_spiffs_read(u32_t addr, u32_t size, u8_t *dst); +extern s32_t hal_spiffs_write(u32_t addr, u32_t size, u8_t *src); + +extern uint8_t target_spiffs_init(); + +mutex_t spiffs_mutex; + +spiffs fs; +spiffs_config spiffs_cfg; +bool spiffsFileSystemReady; + +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t spiffs_work_buffer[SPIFFS_WORK_BUFFER_SIZE]; + +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t spiffs_fd_space[SPIFFS_FILE_DESCRIPTORS_SPACE]; + +#if defined(__GNUC__) +__attribute__((aligned (32))) +#endif +uint8_t spiffs_cache[SPIFFS_CACHE_SIZE]; + +// initialization of SPIFFS: configurations, data structures, drivers and lock +uint8_t hal_spiffs_config() +{ + uint8_t mountResult; + + // low level hardware and drivers initializations + target_spiffs_init(); + + osalMutexObjectInit(&spiffs_mutex); + + // setup SPIFFS configurations + spiffs_cfg.phys_size = SPIFFS_TOTAL_SIZE; + spiffs_cfg.phys_addr = 0; + spiffs_cfg.phys_erase_block = SPIFFS_ERASE_BLOCK_SIZE; + spiffs_cfg.log_block_size = SPIFFS_LOGICAL_BLOCK_SIZE; + spiffs_cfg.log_page_size = SPIFFS_LOGICAL_PAGE_SIZE; + + // setup pointers to HAL functions + spiffs_cfg.hal_erase_f = hal_spiffs_erase; + spiffs_cfg.hal_read_f = hal_spiffs_read; + spiffs_cfg.hal_write_f = hal_spiffs_write; + + mountResult = SPIFFS_mount(&fs, + &spiffs_cfg, + spiffs_work_buffer, + spiffs_fd_space, + SPIFFS_FILE_DESCRIPTORS_SPACE, + spiffs_cache, + SPIFFS_CACHE_SIZE, + 0); + + if( mountResult != SPIFFS_OK && + SPIFFS_errno(&fs) == SPIFFS_ERR_NOT_A_FS) + { + // looks like SPIFFS is not formated + + // need to unmount 1st + SPIFFS_unmount(&fs); + + // now format + if (SPIFFS_format(&fs) != SPIFFS_OK) + { + return -1; + } + + // finally try mounting it again + mountResult = SPIFFS_mount(&fs, + &spiffs_cfg, + spiffs_work_buffer, + spiffs_fd_space, + SPIFFS_FILE_DESCRIPTORS_SPACE, + spiffs_cache, + SPIFFS_CACHE_SIZE, + 0); + } + + #if !defined(BUILD_RTM) + + ASSERT(mountResult == SPIFFS_OK) + + #endif + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + // // code block to assist testing SPIFFS + // char writeBuf[] = {"Hello! if you get this message, congratulations, that's because SPIFFS is working on your device!!"}; + // char readBuf[sizeof(writeBuf)]; + + // spiffs_file fd = SPIFFS_open(&fs, "file1.txt", SPIFFS_CREAT | SPIFFS_TRUNC | SPIFFS_RDWR, 0); + // if (SPIFFS_write(&fs, fd, writeBuf, sizeof(writeBuf)) < 0) + // { + // return -1; + // } + + // SPIFFS_close(&fs, fd); + // fd = SPIFFS_open(&fs, "file1.txt", SPIFFS_RDWR, 0); + // if (SPIFFS_read(&fs, fd, readBuf, sizeof(readBuf)) < 0) + // { + // return -1; + // } + + // SPIFFS_close(&fs, fd); + + // uint32_t total = 0; + // uint32_t used_space = 0; + // SPIFFS_info(&fs, &total, &used_space); + ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + + + // mirror SPIFFS mount result into global flag + spiffsFileSystemReady = (mountResult == SPIFFS_OK); + + return mountResult; +} + +void hal_spiffs_lock() +{ + osalMutexLock(&spiffs_mutex); +} + +void hal_spiffs_unlock() +{ + osalMutexUnlock(&spiffs_mutex); +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/spiffs/hal_spiffs.h b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/spiffs/hal_spiffs.h new file mode 100644 index 00000000..1b8d23cb --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/ChibiOS/spiffs/hal_spiffs.h @@ -0,0 +1,28 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef HAL_SPIFFS_H_ +#define HAL_SPIFFS_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SPIFFS_SUCCESS (0) +#define SPIFFS_ERROR (-1) + +extern spiffs fs; +extern spiffs_config spiffs_cfg; +extern bool spiffsFileSystemReady; + +uint8_t hal_spiffs_config(); + +#ifdef __cplusplus +} +#endif + +#endif // HAL_SPIFFS_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/LwIP/arch/cc.h b/source/native/nf-interpreter/targets/CMSIS-OS/LwIP/arch/cc.h new file mode 100644 index 00000000..e03ee9e8 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/LwIP/arch/cc.h @@ -0,0 +1,93 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + * **** This file incorporates work covered by the following copyright and **** + * **** permission notice: **** + * + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef __CC_H__ +#define __CC_H__ + +// need to declare this here instead of adding an include because debug_printf is declared in nanoHAL.h which is a C++ header +extern void debug_printf(const char* format, ...); + +/* Use errno provided by system. */ +#define LWIP_ERRNO_INCLUDE + +typedef int sys_prot_t; + +/** + * @brief Use system provided struct timeval by default. + */ +#ifndef LWIP_TIMEVAL_PRIVATE +#define LWIP_TIMEVAL_PRIVATE 0 +#include +#endif + +/** + * @brief Use a no-op diagnostic output macro by default. + */ +#if !defined(LWIP_PLATFORM_DIAG) +#define LWIP_PLATFORM_DIAG(x) do {debug_printf x;} while(0) + +#endif + +/** + * @brief Halt the system on lwIP assert failure by default. + */ +#if !defined(LWIP_PLATFORM_ASSERT) +#define LWIP_PLATFORM_ASSERT(x) __asm volatile("BKPT #0\n"); +#endif + +/** + * @brief The NETIF API is required by lwipthread. + */ +#ifdef LWIP_NETIF_API +#undef LWIP_NETIF_API +#endif +#define LWIP_NETIF_API 1 + +#endif /* __CC_H__ */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/LwIP/arch/perf.h b/source/native/nf-interpreter/targets/CMSIS-OS/LwIP/arch/perf.h new file mode 100644 index 00000000..dc786cad --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/LwIP/arch/perf.h @@ -0,0 +1,57 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + * **** This file incorporates work covered by the following copyright and **** + * **** permission notice: **** + * + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#ifndef __PERF_H__ +#define __PERF_H__ + +#define PERF_START +#define PERF_STOP(x) + +#endif /* __PERF_H__ */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/LwIP/arch/sys_arch.h b/source/native/nf-interpreter/targets/CMSIS-OS/LwIP/arch/sys_arch.h new file mode 100644 index 00000000..c79c5b5d --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/LwIP/arch/sys_arch.h @@ -0,0 +1,85 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + * **** This file incorporates work covered by the following copyright and **** + * **** permission notice: **** + * + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include + +#ifndef __SYS_ARCH_H__ +#define __SYS_ARCH_H__ + +#define SYS_MBOX_NULL (osMessageQId)0 +#define SYS_SEM_NULL (osSemaphoreId)0 +#define SYS_THREAD_NULL (thread_t *)0 + +typedef osSemaphoreId sys_sem_t; +typedef osSemaphoreId sys_mutex_t; +typedef osMessageQId sys_mbox_t; +typedef osThreadId sys_thread_t; + +// typedef struct _sys_arch_state_t +// { +// // Task creation data. +// char cTaskName[configMAX_TASK_NAME_LEN]; +// unsigned short nStackDepth; +// unsigned short nTaskCount; +// } sys_arch_state_t; + +/* let sys.h use binary semaphores for mutexes */ +#define LWIP_COMPAT_MUTEX 1 + +#if LWIP_NETCONN_SEM_PER_THREAD +sys_sem_t* sys_arch_netconn_sem_get(void); +void sys_arch_netconn_sem_alloc(void); +void sys_arch_netconn_sem_free(void); +#define LWIP_NETCONN_THREAD_SEM_GET() sys_arch_netconn_sem_get() +#define LWIP_NETCONN_THREAD_SEM_ALLOC() sys_arch_netconn_sem_alloc() +#define LWIP_NETCONN_THREAD_SEM_FREE() sys_arch_netconn_sem_free() +#endif // LWIP_NETCONN_SEM_PER_THREAD + +#endif /* __SYS_ARCH_H__ */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/LwIP/nf_api_msg.c b/source/native/nf-interpreter/targets/CMSIS-OS/LwIP/nf_api_msg.c new file mode 100644 index 00000000..b9ac0cfd --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/LwIP/nf_api_msg.c @@ -0,0 +1,1954 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2001-2004 Swedish Institute of Computer Science. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +// from the original source code file +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// 3. The name of the author may not be used to endorse or promote products +// derived from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED +// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT +// SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +// OF SUCH DAMAGE. +// +// This file is part of the lwIP TCP/IP stack. +// +// Author: Adam Dunkels + + +#include +#include "lwip/opt.h" + +#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/priv/api_msg.h" + +#include "lwip/ip.h" +#include "lwip/ip_addr.h" +#include "lwip/udp.h" +#include "lwip/tcp.h" +#include "lwip/raw.h" + +#include "lwip/memp.h" +#include "lwip/igmp.h" +#include "lwip/dns.h" +#include "lwip/mld6.h" +#include "lwip/priv/tcpip_priv.h" + +#include + +/* netconns are polled once per second (e.g. continue write on memory error) */ +#define NETCONN_TCP_POLL_INTERVAL 2 + +#define SET_NONBLOCKING_CONNECT(conn, val) do { if (val) { \ + (conn)->flags |= NETCONN_FLAG_IN_NONBLOCKING_CONNECT; \ +} else { \ + (conn)->flags &= ~ NETCONN_FLAG_IN_NONBLOCKING_CONNECT; }} while(0) +#define IN_NONBLOCKING_CONNECT(conn) (((conn)->flags & NETCONN_FLAG_IN_NONBLOCKING_CONNECT) != 0) + +/* forward declarations */ +#if LWIP_TCP +#if LWIP_TCPIP_CORE_LOCKING +#define WRITE_DELAYED , 1 +#define WRITE_DELAYED_PARAM , u8_t delayed +#else /* LWIP_TCPIP_CORE_LOCKING */ +#define WRITE_DELAYED +#define WRITE_DELAYED_PARAM +#endif /* LWIP_TCPIP_CORE_LOCKING */ +static err_t lwip_netconn_do_writemore(struct netconn *conn WRITE_DELAYED_PARAM); +static err_t lwip_netconn_do_close_internal(struct netconn *conn WRITE_DELAYED_PARAM); +#endif + +#if LWIP_TCPIP_CORE_LOCKING +#define TCPIP_APIMSG_ACK(m) NETCONN_SET_SAFE_ERR((m)->conn, (m)->err) +#else /* LWIP_TCPIP_CORE_LOCKING */ +#define TCPIP_APIMSG_ACK(m) do { NETCONN_SET_SAFE_ERR((m)->conn, (m)->err); sys_sem_signal(LWIP_API_MSG_SEM(m)); } while(0) +#endif /* LWIP_TCPIP_CORE_LOCKING */ + +#if LWIP_TCP +u8_t netconn_aborted; +#endif /* LWIP_TCP */ + +#if LWIP_RAW +/** + * Receive callback function for RAW netconns. + * Doesn't 'eat' the packet, only copies it and sends it to + * conn->recvmbox + * + * @see raw.h (struct raw_pcb.recv) for parameters and return value + */ +static u8_t +recv_raw(void *arg, struct raw_pcb *pcb, struct pbuf *p, + const ip_addr_t *addr) +{ + struct pbuf *q; + struct netbuf *buf; + struct netconn *conn; + + LWIP_UNUSED_ARG(addr); + conn = (struct netconn *)arg; + + if ((conn != NULL) && sys_mbox_valid(&conn->recvmbox)) { +#if LWIP_SO_RCVBUF + int recv_avail; + SYS_ARCH_GET(conn->recv_avail, recv_avail); + if ((recv_avail + (int)(p->tot_len)) > conn->recv_bufsize) { + return 0; + } +#endif /* LWIP_SO_RCVBUF */ + /* copy the whole packet into new pbufs */ + q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM); + if (q != NULL) { + if (pbuf_copy(q, p) != ERR_OK) { + pbuf_free(q); + q = NULL; + } + } + + if (q != NULL) { + u16_t len; + buf = (struct netbuf *)memp_malloc(MEMP_NETBUF); + if (buf == NULL) { + pbuf_free(q); + return 0; + } + + buf->p = q; + buf->ptr = q; + ip_addr_copy(buf->addr, *ip_current_src_addr()); + buf->port = pcb->protocol; + + len = q->tot_len; + if (sys_mbox_trypost(&conn->recvmbox, buf) != ERR_OK) { + netbuf_delete(buf); + return 0; + } else { +#if LWIP_SO_RCVBUF + SYS_ARCH_INC(conn->recv_avail, len); +#endif /* LWIP_SO_RCVBUF */ + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, len); + } + } + } + + return 0; /* do not eat the packet */ +} +#endif /* LWIP_RAW*/ + +#if LWIP_UDP +/** + * Receive callback function for UDP netconns. + * Posts the packet to conn->recvmbox or deletes it on memory error. + * + * @see udp.h (struct udp_pcb.recv) for parameters + */ +static void +recv_udp(void *arg, struct udp_pcb *pcb, struct pbuf *p, + const ip_addr_t *addr, u16_t port) +{ + struct netbuf *buf; + struct netconn *conn; + u16_t len; +#if LWIP_SO_RCVBUF + int recv_avail; +#endif /* LWIP_SO_RCVBUF */ + + LWIP_UNUSED_ARG(pcb); /* only used for asserts... */ + LWIP_ASSERT("recv_udp must have a pcb argument", pcb != NULL); + LWIP_ASSERT("recv_udp must have an argument", arg != NULL); + conn = (struct netconn *)arg; + + if (conn == NULL) { + pbuf_free(p); + return; + } + + LWIP_ASSERT("recv_udp: recv for wrong pcb!", conn->pcb.udp == pcb); + +#if LWIP_SO_RCVBUF + SYS_ARCH_GET(conn->recv_avail, recv_avail); + if (!sys_mbox_valid(&conn->recvmbox) || + ((recv_avail + (int)(p->tot_len)) > conn->recv_bufsize)) { +#else /* LWIP_SO_RCVBUF */ + if (!sys_mbox_valid(&conn->recvmbox)) { +#endif /* LWIP_SO_RCVBUF */ + pbuf_free(p); + return; + } + + buf = (struct netbuf *)memp_malloc(MEMP_NETBUF); + if (buf == NULL) { + pbuf_free(p); + return; + } else { + buf->p = p; + buf->ptr = p; + ip_addr_set(&buf->addr, addr); + buf->port = port; +#if LWIP_NETBUF_RECVINFO + { + /* get the UDP header - always in the first pbuf, ensured by udp_input */ + const struct udp_hdr* udphdr = (const struct udp_hdr*)ip_next_header_ptr(); +#if LWIP_CHECKSUM_ON_COPY + buf->flags = NETBUF_FLAG_DESTADDR; +#endif /* LWIP_CHECKSUM_ON_COPY */ + ip_addr_set(&buf->toaddr, ip_current_dest_addr()); + buf->toport_chksum = udphdr->dest; + } +#endif /* LWIP_NETBUF_RECVINFO */ + } + + len = p->tot_len; + if (sys_mbox_trypost(&conn->recvmbox, buf) != ERR_OK) { + netbuf_delete(buf); + return; + } else { +#if LWIP_SO_RCVBUF + SYS_ARCH_INC(conn->recv_avail, len); +#endif /* LWIP_SO_RCVBUF */ + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, len); + } +} +#endif /* LWIP_UDP */ + +#if LWIP_TCP +/** + * Receive callback function for TCP netconns. + * Posts the packet to conn->recvmbox, but doesn't delete it on errors. + * + * @see tcp.h (struct tcp_pcb.recv) for parameters and return value + */ +static err_t +recv_tcp(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) +{ + struct netconn *conn; + u16_t len; + + LWIP_UNUSED_ARG(pcb); + LWIP_ASSERT("recv_tcp must have a pcb argument", pcb != NULL); + LWIP_ASSERT("recv_tcp must have an argument", arg != NULL); + conn = (struct netconn *)arg; + + if (conn == NULL) { + return ERR_VAL; + } + LWIP_ASSERT("recv_tcp: recv for wrong pcb!", conn->pcb.tcp == pcb); + + if (!sys_mbox_valid(&conn->recvmbox)) { + /* recvmbox already deleted */ + if (p != NULL) { + tcp_recved(pcb, p->tot_len); + pbuf_free(p); + } + return ERR_OK; + } + /* Unlike for UDP or RAW pcbs, don't check for available space + using recv_avail since that could break the connection + (data is already ACKed) */ + + /* don't overwrite fatal errors! */ + if (err != ERR_OK) { + NETCONN_SET_SAFE_ERR(conn, err); + } + + if (p != NULL) { + len = p->tot_len; + } else { + len = 0; + } + + if (sys_mbox_trypost(&conn->recvmbox, p) != ERR_OK) { + /* don't deallocate p: it is presented to us later again from tcp_fasttmr! */ + return ERR_MEM; + } else { +#if LWIP_SO_RCVBUF + SYS_ARCH_INC(conn->recv_avail, len); +#endif /* LWIP_SO_RCVBUF */ + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, len); + } + + return ERR_OK; +} + +/** + * Poll callback function for TCP netconns. + * Wakes up an application thread that waits for a connection to close + * or data to be sent. The application thread then takes the + * appropriate action to go on. + * + * Signals the conn->sem. + * netconn_close waits for conn->sem if closing failed. + * + * @see tcp.h (struct tcp_pcb.poll) for parameters and return value + */ +static err_t +poll_tcp(void *arg, struct tcp_pcb *pcb) +{ + struct netconn *conn = (struct netconn *)arg; + + LWIP_UNUSED_ARG(pcb); + LWIP_ASSERT("conn != NULL", (conn != NULL)); + + if (conn->state == NETCONN_WRITE) { + lwip_netconn_do_writemore(conn WRITE_DELAYED); + } else if (conn->state == NETCONN_CLOSE) { +#if !LWIP_SO_SNDTIMEO && !LWIP_SO_LINGER + if (conn->current_msg && conn->current_msg->msg.sd.polls_left) { + conn->current_msg->msg.sd.polls_left--; + } +#endif /* !LWIP_SO_SNDTIMEO && !LWIP_SO_LINGER */ + lwip_netconn_do_close_internal(conn WRITE_DELAYED); + } + /* @todo: implement connect timeout here? */ + + /* Did a nonblocking write fail before? Then check available write-space. */ + if (conn->flags & NETCONN_FLAG_CHECK_WRITESPACE) { + /* If the queued byte- or pbuf-count drops below the configured low-water limit, + let select mark this pcb as writable again. */ + if ((conn->pcb.tcp != NULL) && (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) && + (tcp_sndqueuelen(conn->pcb.tcp) < TCP_SNDQUEUELOWAT)) { + conn->flags &= ~NETCONN_FLAG_CHECK_WRITESPACE; + API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0); + } + } + + return ERR_OK; +} + +/** + * Sent callback function for TCP netconns. + * Signals the conn->sem and calls API_EVENT. + * netconn_write waits for conn->sem if send buffer is low. + * + * @see tcp.h (struct tcp_pcb.sent) for parameters and return value + */ +static err_t +sent_tcp(void *arg, struct tcp_pcb *pcb, u16_t len) +{ + struct netconn *conn = (struct netconn *)arg; + + LWIP_UNUSED_ARG(pcb); + LWIP_ASSERT("conn != NULL", (conn != NULL)); + + if (conn) { + if (conn->state == NETCONN_WRITE) { + lwip_netconn_do_writemore(conn WRITE_DELAYED); + } else if (conn->state == NETCONN_CLOSE) { + lwip_netconn_do_close_internal(conn WRITE_DELAYED); + } + + /* If the queued byte- or pbuf-count drops below the configured low-water limit, + let select mark this pcb as writable again. */ + if ((conn->pcb.tcp != NULL) && (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) && + (tcp_sndqueuelen(conn->pcb.tcp) < TCP_SNDQUEUELOWAT)) { + conn->flags &= ~NETCONN_FLAG_CHECK_WRITESPACE; + API_EVENT(conn, NETCONN_EVT_SENDPLUS, len); + } + } + + return ERR_OK; +} + +/** + * Error callback function for TCP netconns. + * Signals conn->sem, posts to all conn mboxes and calls API_EVENT. + * The application thread has then to decide what to do. + * + * @see tcp.h (struct tcp_pcb.err) for parameters + */ +static void +err_tcp(void *arg, err_t err) +{ + struct netconn *conn; + enum netconn_state old_state; + + conn = (struct netconn *)arg; + LWIP_ASSERT("conn != NULL", (conn != NULL)); + + conn->pcb.tcp = NULL; + + /* reset conn->state now before waking up other threads */ + old_state = conn->state; + conn->state = NETCONN_NONE; + + if (old_state == NETCONN_CLOSE) { + /* RST during close: let close return success & dealloc the netconn */ + err = ERR_OK; + NETCONN_SET_SAFE_ERR(conn, ERR_OK); + } else { + /* no check since this is always fatal! */ + SYS_ARCH_SET(conn->last_err, err); + } + + /* @todo: the type of NETCONN_EVT created should depend on 'old_state' */ + + /* Notify the user layer about a connection error. Used to signal select. */ + API_EVENT(conn, NETCONN_EVT_ERROR, 0); + /* Try to release selects pending on 'read' or 'write', too. + They will get an error if they actually try to read or write. */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); + API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0); + + /* pass NULL-message to recvmbox to wake up pending recv */ + if (sys_mbox_valid(&conn->recvmbox)) { + /* use trypost to prevent deadlock */ + sys_mbox_trypost(&conn->recvmbox, NULL); + } + /* pass NULL-message to acceptmbox to wake up pending accept */ + if (sys_mbox_valid(&conn->acceptmbox)) { + /* use trypost to preven deadlock */ + sys_mbox_trypost(&conn->acceptmbox, NULL); + } + + if ((old_state == NETCONN_WRITE) || (old_state == NETCONN_CLOSE) || + (old_state == NETCONN_CONNECT)) { + /* calling lwip_netconn_do_writemore/lwip_netconn_do_close_internal is not necessary + since the pcb has already been deleted! */ + int was_nonblocking_connect = IN_NONBLOCKING_CONNECT(conn); + SET_NONBLOCKING_CONNECT(conn, 0); + + if (!was_nonblocking_connect) { + sys_sem_t* op_completed_sem; + /* set error return code */ + LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL); + conn->current_msg->err = err; + op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg); + LWIP_ASSERT("inavlid op_completed_sem", sys_sem_valid(op_completed_sem)); + conn->current_msg = NULL; + /* wake up the waiting task */ + NETCONN_SET_SAFE_ERR(conn, err); + sys_sem_signal(op_completed_sem); + } + } else { + LWIP_ASSERT("conn->current_msg == NULL", conn->current_msg == NULL); + } +} + +/** + * Setup a tcp_pcb with the correct callback function pointers + * and their arguments. + * + * @param conn the TCP netconn to setup + */ +static void +setup_tcp(struct netconn *conn) +{ + struct tcp_pcb *pcb; + + pcb = conn->pcb.tcp; + tcp_arg(pcb, conn); + tcp_recv(pcb, recv_tcp); + tcp_sent(pcb, sent_tcp); + tcp_poll(pcb, poll_tcp, NETCONN_TCP_POLL_INTERVAL); + tcp_err(pcb, err_tcp); +} + +/** + * Accept callback function for TCP netconns. + * Allocates a new netconn and posts that to conn->acceptmbox. + * + * @see tcp.h (struct tcp_pcb_listen.accept) for parameters and return value + */ +static err_t +accept_function(void *arg, struct tcp_pcb *newpcb, err_t err) +{ + struct netconn *newconn; + struct netconn *conn = (struct netconn *)arg; + + if (conn == NULL) { + return ERR_VAL; + } + if (!sys_mbox_valid(&conn->acceptmbox)) { + LWIP_DEBUGF(API_MSG_DEBUG, ("accept_function: acceptmbox already deleted\n")); + return ERR_VAL; + } + + if (newpcb == NULL) { + /* out-of-pcbs during connect: pass on this error to the application */ + if (sys_mbox_trypost(&conn->acceptmbox, &netconn_aborted) == ERR_OK) { + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); + } + return ERR_VAL; + } + + LWIP_DEBUGF(API_MSG_DEBUG, ("accept_function: newpcb->tate: %s\n", tcp_debug_state_str(newpcb->state))); + + /* We have to set the callback here even though + * the new socket is unknown. newconn->socket is marked as -1. */ + newconn = netconn_alloc(conn->type, conn->callback); + if (newconn == NULL) { + /* outof netconns: pass on this error to the application */ + if (sys_mbox_trypost(&conn->acceptmbox, &netconn_aborted) == ERR_OK) { + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); + } + return ERR_MEM; + } + newconn->pcb.tcp = newpcb; + setup_tcp(newconn); + /* no protection: when creating the pcb, the netconn is not yet known + to the application thread */ + newconn->last_err = err; + + /* handle backlog counter */ + tcp_backlog_delayed(newpcb); + + if (sys_mbox_trypost(&conn->acceptmbox, newconn) != ERR_OK) { + /* When returning != ERR_OK, the pcb is aborted in tcp_process(), + so do nothing here! */ + /* remove all references to this netconn from the pcb */ + struct tcp_pcb* pcb = newconn->pcb.tcp; + tcp_arg(pcb, NULL); + tcp_recv(pcb, NULL); + tcp_sent(pcb, NULL); + tcp_poll(pcb, NULL, 0); + tcp_err(pcb, NULL); + /* remove reference from to the pcb from this netconn */ + newconn->pcb.tcp = NULL; + /* no need to drain since we know the recvmbox is empty. */ + sys_mbox_free(&newconn->recvmbox); + sys_mbox_set_invalid(&newconn->recvmbox); + netconn_free(newconn); + return ERR_MEM; + } else { + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); + } + + return ERR_OK; +} +#endif /* LWIP_TCP */ + +/** + * Create a new pcb of a specific type. + * Called from lwip_netconn_do_newconn(). + * + * @param msg the api_msg_msg describing the connection type + */ +static void +pcb_new(struct api_msg *msg) +{ + enum lwip_ip_addr_type iptype = IPADDR_TYPE_V4; + + LWIP_ASSERT("pcb_new: pcb already allocated", msg->conn->pcb.tcp == NULL); + +#if LWIP_IPV6 && LWIP_IPV4 + /* IPv6: Dual-stack by default, unless netconn_set_ipv6only() is called */ + if(NETCONNTYPE_ISIPV6(netconn_type(msg->conn))) { + iptype = IPADDR_TYPE_ANY; + } +#endif + + /* Allocate a PCB for this connection */ + switch(NETCONNTYPE_GROUP(msg->conn->type)) { +#if LWIP_RAW + case NETCONN_RAW: + msg->conn->pcb.raw = raw_new_ip_type(iptype, msg->msg.n.proto); + if (msg->conn->pcb.raw != NULL) { +#if LWIP_IPV6 + /* ICMPv6 packets should always have checksum calculated by the stack as per RFC 3542 chapter 3.1 */ + if (NETCONNTYPE_ISIPV6(msg->conn->type) && msg->conn->pcb.raw->protocol == IP6_NEXTH_ICMP6) { + msg->conn->pcb.raw->chksum_reqd = 1; + msg->conn->pcb.raw->chksum_offset = 2; + } +#endif /* LWIP_IPV6 */ + raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn); + } + break; +#endif /* LWIP_RAW */ +#if LWIP_UDP + case NETCONN_UDP: + msg->conn->pcb.udp = udp_new_ip_type(iptype); + if (msg->conn->pcb.udp != NULL) { +#if LWIP_UDPLITE + if (NETCONNTYPE_ISUDPLITE(msg->conn->type)) { + udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE); + } +#endif /* LWIP_UDPLITE */ + if (NETCONNTYPE_ISUDPNOCHKSUM(msg->conn->type)) { + udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM); + } + udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); + } + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + msg->conn->pcb.tcp = tcp_new_ip_type(iptype); + if (msg->conn->pcb.tcp != NULL) { + setup_tcp(msg->conn); + } + break; +#endif /* LWIP_TCP */ + default: + /* Unsupported netconn type, e.g. protocol disabled */ + msg->err = ERR_VAL; + return; + } + if (msg->conn->pcb.ip == NULL) { + msg->err = ERR_MEM; + } +} + +/** + * Create a new pcb of a specific type inside a netconn. + * Called from netconn_new_with_proto_and_callback. + * + * @param m the api_msg_msg describing the connection type + */ +void +lwip_netconn_do_newconn(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + + msg->err = ERR_OK; + if (msg->conn->pcb.tcp == NULL) { + pcb_new(msg); + } + /* Else? This "new" connection already has a PCB allocated. */ + /* Is this an error condition? Should it be deleted? */ + /* We currently just are happy and return. */ + + TCPIP_APIMSG_ACK(msg); +} + +/** + * Create a new netconn (of a specific type) that has a callback function. + * The corresponding pcb is NOT created! + * + * @param t the type of 'connection' to create (@see enum netconn_type) + * @param callback a function to call on status changes (RX available, TX'ed) + * @return a newly allocated struct netconn or + * NULL on memory error + */ +struct netconn* +netconn_alloc(enum netconn_type t, netconn_callback callback) +{ + struct netconn *conn; + int size; + + conn = (struct netconn *)memp_malloc(MEMP_NETCONN); + if (conn == NULL) { + return NULL; + } + + conn->last_err = ERR_OK; + conn->type = t; + conn->pcb.tcp = NULL; + + /* If all sizes are the same, every compiler should optimize this switch to nothing */ + switch(NETCONNTYPE_GROUP(t)) { +#if LWIP_RAW + case NETCONN_RAW: + size = DEFAULT_RAW_RECVMBOX_SIZE; + break; +#endif /* LWIP_RAW */ +#if LWIP_UDP + case NETCONN_UDP: + size = DEFAULT_UDP_RECVMBOX_SIZE; + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + size = DEFAULT_TCP_RECVMBOX_SIZE; + break; +#endif /* LWIP_TCP */ + default: + LWIP_ASSERT("netconn_alloc: undefined netconn_type", 0); + goto free_and_return; + } + + if (sys_mbox_new(&conn->recvmbox, size) != ERR_OK) { + goto free_and_return; + } +#if !LWIP_NETCONN_SEM_PER_THREAD + if (sys_sem_new(&conn->op_completed, 0) != ERR_OK) { + sys_mbox_free(&conn->recvmbox); + goto free_and_return; + } +#endif + +#if LWIP_TCP + sys_mbox_set_invalid(&conn->acceptmbox); +#endif + conn->state = NETCONN_NONE; +#if LWIP_SOCKET + /* initialize socket to -1 since 0 is a valid socket */ + conn->socket = -1; +#endif /* LWIP_SOCKET */ + conn->callback = callback; +#if LWIP_TCP + conn->current_msg = NULL; + conn->write_offset = 0; +#endif /* LWIP_TCP */ +#if LWIP_SO_SNDTIMEO + conn->send_timeout = 0; +#endif /* LWIP_SO_SNDTIMEO */ +#if LWIP_SO_RCVTIMEO + conn->recv_timeout = 0; +#endif /* LWIP_SO_RCVTIMEO */ +#if LWIP_SO_RCVBUF + conn->recv_bufsize = RECV_BUFSIZE_DEFAULT; + conn->recv_avail = 0; +#endif /* LWIP_SO_RCVBUF */ +#if LWIP_SO_LINGER + conn->linger = -1; +#endif /* LWIP_SO_LINGER */ + conn->flags = 0; + return conn; +free_and_return: + memp_free(MEMP_NETCONN, conn); + return NULL; +} + +/** + * Delete a netconn and all its resources. + * The pcb is NOT freed (since we might not be in the right thread context do this). + * + * @param conn the netconn to free + */ +void +netconn_free(struct netconn *conn) +{ + LWIP_ASSERT("PCB must be deallocated outside this function", conn->pcb.tcp == NULL); + LWIP_ASSERT("recvmbox must be deallocated before calling this function", + !sys_mbox_valid(&conn->recvmbox)); +#if LWIP_TCP + LWIP_ASSERT("acceptmbox must be deallocated before calling this function", + !sys_mbox_valid(&conn->acceptmbox)); +#endif /* LWIP_TCP */ + +#if !LWIP_NETCONN_SEM_PER_THREAD + sys_sem_free(&conn->op_completed); + sys_sem_set_invalid(&conn->op_completed); +#endif + + memp_free(MEMP_NETCONN, conn); +} + +/** + * Delete rcvmbox and acceptmbox of a netconn and free the left-over data in + * these mboxes + * + * @param conn the netconn to free + * @bytes_drained bytes drained from recvmbox + * @accepts_drained pending connections drained from acceptmbox + */ +static void +netconn_drain(struct netconn *conn) +{ + void *mem; +#if LWIP_TCP + struct pbuf *p; +#endif /* LWIP_TCP */ + + /* This runs in tcpip_thread, so we don't need to lock against rx packets */ + + /* Delete and drain the recvmbox. */ + if (sys_mbox_valid(&conn->recvmbox)) { + while (sys_mbox_tryfetch(&conn->recvmbox, &mem) != SYS_MBOX_EMPTY) { +#if LWIP_TCP + if (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP) { + if (mem != NULL) { + p = (struct pbuf*)mem; + /* pcb might be set to NULL already by err_tcp() */ + if (conn->pcb.tcp != NULL) { + tcp_recved(conn->pcb.tcp, p->tot_len); + } + pbuf_free(p); + } + } else +#endif /* LWIP_TCP */ + { + netbuf_delete((struct netbuf *)mem); + } + } + sys_mbox_free(&conn->recvmbox); + sys_mbox_set_invalid(&conn->recvmbox); + } + + /* Delete and drain the acceptmbox. */ +#if LWIP_TCP + if (sys_mbox_valid(&conn->acceptmbox)) { + while (sys_mbox_tryfetch(&conn->acceptmbox, &mem) != SYS_MBOX_EMPTY) { + if (mem != &netconn_aborted) { + struct netconn *newconn = (struct netconn *)mem; + /* Only tcp pcbs have an acceptmbox, so no need to check conn->type */ + /* pcb might be set to NULL already by err_tcp() */ + /* drain recvmbox */ + netconn_drain(newconn); + if (newconn->pcb.tcp != NULL) { + tcp_abort(newconn->pcb.tcp); + newconn->pcb.tcp = NULL; + } + netconn_free(newconn); + } + } + sys_mbox_free(&conn->acceptmbox); + sys_mbox_set_invalid(&conn->acceptmbox); + } +#endif /* LWIP_TCP */ +} + +#if LWIP_TCP +/** + * Internal helper function to close a TCP netconn: since this sometimes + * doesn't work at the first attempt, this function is called from multiple + * places. + * + * @param conn the TCP netconn to close + */ +static err_t +lwip_netconn_do_close_internal(struct netconn *conn WRITE_DELAYED_PARAM) +{ + err_t err; + u8_t shut, shut_rx, shut_tx, close; + u8_t close_finished = 0; + struct tcp_pcb* tpcb; +#if LWIP_SO_LINGER + u8_t linger_wait_required = 0; +#endif /* LWIP_SO_LINGER */ + + LWIP_ASSERT("invalid conn", (conn != NULL)); + LWIP_ASSERT("this is for tcp netconns only", (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP)); + LWIP_ASSERT("conn must be in state NETCONN_CLOSE", (conn->state == NETCONN_CLOSE)); + LWIP_ASSERT("pcb already closed", (conn->pcb.tcp != NULL)); + LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL); + + tpcb = conn->pcb.tcp; + shut = conn->current_msg->msg.sd.shut; + shut_rx = shut & NETCONN_SHUT_RD; + shut_tx = shut & NETCONN_SHUT_WR; + /* shutting down both ends is the same as closing + (also if RD or WR side was shut down before already) */ + if (shut == NETCONN_SHUT_RDWR) { + close = 1; + } else if (shut_rx && + ((tpcb->state == FIN_WAIT_1) || + (tpcb->state == FIN_WAIT_2) || + (tpcb->state == CLOSING))) { + close = 1; + } else if (shut_tx && ((tpcb->flags & TF_RXCLOSED) != 0)) { + close = 1; + } else { + close = 0; + } + + /* Set back some callback pointers */ + if (close) { + tcp_arg(tpcb, NULL); + } + if (tpcb->state == LISTEN) { + tcp_accept(tpcb, NULL); + } else { + /* some callbacks have to be reset if tcp_close is not successful */ + if (shut_rx) { + tcp_recv(tpcb, NULL); + tcp_accept(tpcb, NULL); + } + if (shut_tx) { + tcp_sent(tpcb, NULL); + } + if (close) { + tcp_poll(tpcb, NULL, 0); + tcp_err(tpcb, NULL); + } + } + /* Try to close the connection */ + if (close) { +#if LWIP_SO_LINGER + /* check linger possibilites before calling tcp_close */ + err = ERR_OK; + /* linger enabled/required at all? (i.e. is there untransmitted data left?) */ + if ((conn->linger >= 0) && (conn->pcb.tcp->unsent || conn->pcb.tcp->unacked)) { + if ((conn->linger == 0)) { + /* data left but linger prevents waiting */ + tcp_abort(tpcb); + tpcb = NULL; + } else if (conn->linger > 0) { + /* data left and linger says we should wait */ + if (netconn_is_nonblocking(conn)) { + /* data left on a nonblocking netconn -> cannot linger */ + err = ERR_WOULDBLOCK; + } else if ((s32_t)(sys_now() - conn->current_msg->msg.sd.time_started) >= + (conn->linger * 1000)) { + /* data left but linger timeout has expired (this happens on further + calls to this function through poll_tcp */ + tcp_abort(tpcb); + tpcb = NULL; + } else { + /* data left -> need to wait for ACK after successful close */ + linger_wait_required = 1; + } + } + } + if ((err == ERR_OK) && (tpcb != NULL)) +#endif /* LWIP_SO_LINGER */ + { + err = tcp_close(tpcb); + } + } else { + err = tcp_shutdown(tpcb, shut_rx, shut_tx); + } + if (err == ERR_OK) { + close_finished = 1; +#if LWIP_SO_LINGER + if (linger_wait_required) { + /* wait for ACK of all unsent/unacked data by just getting called again */ + close_finished = 0; + err = ERR_INPROGRESS; + } +#endif /* LWIP_SO_LINGER */ + } else { + if (err == ERR_MEM) { + /* Closing failed because of memory shortage, try again later. Even for + nonblocking netconns, we have to wait since no standard socket application + is prepared for close failing because of resource shortage. + Check the timeout: this is kind of an lwip addition to the standard sockets: + we wait for some time when failing to allocate a segment for the FIN */ +#if LWIP_SO_SNDTIMEO || LWIP_SO_LINGER + s32_t close_timeout = LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT; +#if LWIP_SO_SNDTIMEO + if (conn->send_timeout > 0) { + close_timeout = conn->send_timeout; + } +#endif /* LWIP_SO_SNDTIMEO */ +#if LWIP_SO_LINGER + if (conn->linger >= 0) { + /* use linger timeout (seconds) */ + close_timeout = conn->linger * 1000U; + } +#endif + if ((s32_t)(sys_now() - conn->current_msg->msg.sd.time_started) >= close_timeout) { +#else /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ + if (conn->current_msg->msg.sd.polls_left == 0) { +#endif /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ + close_finished = 1; + if (close) { + /* in this case, we want to RST the connection */ + tcp_abort(tpcb); + err = ERR_OK; + } + } + } else { + /* Closing failed for a non-memory error: give up */ + close_finished = 1; + } + } + if (close_finished) { + /* Closing done (succeeded, non-memory error, nonblocking error or timeout) */ + sys_sem_t* op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg); + conn->current_msg->err = err; + conn->current_msg = NULL; + conn->state = NETCONN_NONE; + if (err == ERR_OK) { + if (close) { + /* Set back some callback pointers as conn is going away */ + conn->pcb.tcp = NULL; + /* Trigger select() in socket layer. Make sure everybody notices activity + on the connection, error first! */ + API_EVENT(conn, NETCONN_EVT_ERROR, 0); + } + if (shut_rx) { + API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); + } + if (shut_tx) { + API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0); + } + } + NETCONN_SET_SAFE_ERR(conn, err); +#if LWIP_TCPIP_CORE_LOCKING + if (delayed) +#endif + { + /* wake up the application task */ + sys_sem_signal(op_completed_sem); + } + return ERR_OK; + } + if (!close_finished) { + /* Closing failed and we want to wait: restore some of the callbacks */ + /* Closing of listen pcb will never fail! */ + LWIP_ASSERT("Closing a listen pcb may not fail!", (tpcb->state != LISTEN)); + if (shut_tx) { + tcp_sent(tpcb, sent_tcp); + } + /* when waiting for close, set up poll interval to 500ms */ + tcp_poll(tpcb, poll_tcp, 1); + tcp_err(tpcb, err_tcp); + tcp_arg(tpcb, conn); + /* don't restore recv callback: we don't want to receive any more data */ + } + /* If closing didn't succeed, we get called again either + from poll_tcp or from sent_tcp */ + LWIP_ASSERT("err != ERR_OK", err != ERR_OK); + return err; +} +#endif /* LWIP_TCP */ + +/** + * Delete the pcb inside a netconn. + * Called from netconn_delete. + * + * @param m the api_msg_msg pointing to the connection + */ +void +lwip_netconn_do_delconn(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + + enum netconn_state state = msg->conn->state; + LWIP_ASSERT("netconn state error", /* this only happens for TCP netconns */ + (state == NETCONN_NONE) || (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP)); +#if LWIP_NETCONN_FULLDUPLEX + /* In full duplex mode, blocking write/connect is aborted with ERR_CLSD */ + if (state != NETCONN_NONE) { + if ((state == NETCONN_WRITE) || + ((state == NETCONN_CONNECT) && !IN_NONBLOCKING_CONNECT(msg->conn))) { + /* close requested, abort running write/connect */ + sys_sem_t* op_completed_sem; + LWIP_ASSERT("msg->conn->current_msg != NULL", msg->conn->current_msg != NULL); + op_completed_sem = LWIP_API_MSG_SEM(msg->conn->current_msg); + msg->conn->current_msg->err = ERR_CLSD; + msg->conn->current_msg = NULL; + msg->conn->write_offset = 0; + msg->conn->state = NETCONN_NONE; + NETCONN_SET_SAFE_ERR(msg->conn, ERR_CLSD); + sys_sem_signal(op_completed_sem); + } + } +#else /* LWIP_NETCONN_FULLDUPLEX */ + if (((state != NETCONN_NONE) && + (state != NETCONN_LISTEN) && + (state != NETCONN_CONNECT)) || + ((state == NETCONN_CONNECT) && !IN_NONBLOCKING_CONNECT(msg->conn))) { + /* This means either a blocking write or blocking connect is running + (nonblocking write returns and sets state to NONE) */ + msg->err = ERR_INPROGRESS; + } else +#endif /* LWIP_NETCONN_FULLDUPLEX */ + { + LWIP_ASSERT("blocking connect in progress", + (state != NETCONN_CONNECT) || IN_NONBLOCKING_CONNECT(msg->conn)); + msg->err = ERR_OK; + /* Drain and delete mboxes */ + netconn_drain(msg->conn); + + if (msg->conn->pcb.tcp != NULL) { + + switch (NETCONNTYPE_GROUP(msg->conn->type)) { +#if LWIP_RAW + case NETCONN_RAW: + raw_remove(msg->conn->pcb.raw); + break; +#endif /* LWIP_RAW */ +#if LWIP_UDP + case NETCONN_UDP: + msg->conn->pcb.udp->recv_arg = NULL; + udp_remove(msg->conn->pcb.udp); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL && + msg->conn->write_offset == 0); + msg->conn->state = NETCONN_CLOSE; + msg->msg.sd.shut = NETCONN_SHUT_RDWR; + msg->conn->current_msg = msg; +#if LWIP_TCPIP_CORE_LOCKING + if (lwip_netconn_do_close_internal(msg->conn, 0) != ERR_OK) { + LWIP_ASSERT("state!", msg->conn->state == NETCONN_CLOSE); + UNLOCK_TCPIP_CORE(); + sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0); + LOCK_TCPIP_CORE(); + LWIP_ASSERT("state!", msg->conn->state == NETCONN_NONE); + } +#else /* LWIP_TCPIP_CORE_LOCKING */ + lwip_netconn_do_close_internal(msg->conn); +#endif /* LWIP_TCPIP_CORE_LOCKING */ + /* API_EVENT is called inside lwip_netconn_do_close_internal, before releasing + the application thread, so we can return at this point! */ + return; +#endif /* LWIP_TCP */ + default: + break; + } + msg->conn->pcb.tcp = NULL; + } + /* tcp netconns don't come here! */ + + /* @todo: this lets select make the socket readable and writable, + which is wrong! errfd instead? */ + API_EVENT(msg->conn, NETCONN_EVT_RCVPLUS, 0); + API_EVENT(msg->conn, NETCONN_EVT_SENDPLUS, 0); + } + if (sys_sem_valid(LWIP_API_MSG_SEM(msg))) { + TCPIP_APIMSG_ACK(msg); + } +} + +/** + * Bind a pcb contained in a netconn + * Called from netconn_bind. + * + * @param m the api_msg_msg pointing to the connection and containing + * the IP address and port to bind to + */ +void +lwip_netconn_do_bind(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + + if (ERR_IS_FATAL(msg->conn->last_err)) { + msg->err = msg->conn->last_err; + } else { + msg->err = ERR_VAL; + if (msg->conn->pcb.tcp != NULL) { + switch (NETCONNTYPE_GROUP(msg->conn->type)) { +#if LWIP_RAW + case NETCONN_RAW: + msg->err = raw_bind(msg->conn->pcb.raw, API_EXPR_REF(msg->msg.bc.ipaddr)); + break; +#endif /* LWIP_RAW */ +#if LWIP_UDP + case NETCONN_UDP: + msg->err = udp_bind(msg->conn->pcb.udp, API_EXPR_REF(msg->msg.bc.ipaddr), msg->msg.bc.port); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + msg->err = tcp_bind(msg->conn->pcb.tcp, API_EXPR_REF(msg->msg.bc.ipaddr), msg->msg.bc.port); + break; +#endif /* LWIP_TCP */ + default: + break; + } + } + } + TCPIP_APIMSG_ACK(msg); +} + +#if LWIP_TCP +/** + * TCP callback function if a connection (opened by tcp_connect/lwip_netconn_do_connect) has + * been established (or reset by the remote host). + * + * @see tcp.h (struct tcp_pcb.connected) for parameters and return values + */ +static err_t +lwip_netconn_do_connected(void *arg, struct tcp_pcb *pcb, err_t err) +{ + struct netconn *conn; + int was_blocking; + sys_sem_t* op_completed_sem = NULL; + + LWIP_UNUSED_ARG(pcb); + + conn = (struct netconn *)arg; + + if (conn == NULL) { + return ERR_VAL; + } + + LWIP_ASSERT("conn->state == NETCONN_CONNECT", conn->state == NETCONN_CONNECT); + LWIP_ASSERT("(conn->current_msg != NULL) || conn->in_non_blocking_connect", + (conn->current_msg != NULL) || IN_NONBLOCKING_CONNECT(conn)); + + if (conn->current_msg != NULL) { + conn->current_msg->err = err; + op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg); + } + if ((NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP) && (err == ERR_OK)) { + setup_tcp(conn); + } + was_blocking = !IN_NONBLOCKING_CONNECT(conn); + SET_NONBLOCKING_CONNECT(conn, 0); + LWIP_ASSERT("blocking connect state error", + (was_blocking && op_completed_sem != NULL) || + (!was_blocking && op_completed_sem == NULL)); + conn->current_msg = NULL; + conn->state = NETCONN_NONE; + NETCONN_SET_SAFE_ERR(conn, ERR_OK); + API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0); + + if (was_blocking) { + sys_sem_signal(op_completed_sem); + } + return ERR_OK; +} +#endif /* LWIP_TCP */ + +/** + * Connect a pcb contained inside a netconn + * Called from netconn_connect. + * + * @param m the api_msg_msg pointing to the connection and containing + * the IP address and port to connect to + */ +void +lwip_netconn_do_connect(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + + if (msg->conn->pcb.tcp == NULL) { + /* This may happen when calling netconn_connect() a second time */ + msg->err = ERR_CLSD; + } else { + switch (NETCONNTYPE_GROUP(msg->conn->type)) { +#if LWIP_RAW + case NETCONN_RAW: + msg->err = raw_connect(msg->conn->pcb.raw, API_EXPR_REF(msg->msg.bc.ipaddr)); + break; +#endif /* LWIP_RAW */ +#if LWIP_UDP + case NETCONN_UDP: + msg->err = udp_connect(msg->conn->pcb.udp, API_EXPR_REF(msg->msg.bc.ipaddr), msg->msg.bc.port); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + /* Prevent connect while doing any other action. */ + if (msg->conn->state == NETCONN_CONNECT) { + msg->err = ERR_ALREADY; + } else if (msg->conn->state != NETCONN_NONE) { + msg->err = ERR_ISCONN; + } else { + setup_tcp(msg->conn); + msg->err = tcp_connect(msg->conn->pcb.tcp, API_EXPR_REF(msg->msg.bc.ipaddr), + msg->msg.bc.port, lwip_netconn_do_connected); + if (msg->err == ERR_OK) { + u8_t non_blocking = netconn_is_nonblocking(msg->conn); + msg->conn->state = NETCONN_CONNECT; + SET_NONBLOCKING_CONNECT(msg->conn, non_blocking); + if (non_blocking) { + msg->err = ERR_INPROGRESS; + } else { + msg->conn->current_msg = msg; + /* sys_sem_signal() is called from lwip_netconn_do_connected (or err_tcp()), + when the connection is established! */ +#if LWIP_TCPIP_CORE_LOCKING + LWIP_ASSERT("state!", msg->conn->state == NETCONN_CONNECT); + UNLOCK_TCPIP_CORE(); + sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0); + LOCK_TCPIP_CORE(); + LWIP_ASSERT("state!", msg->conn->state != NETCONN_CONNECT); +#endif /* LWIP_TCPIP_CORE_LOCKING */ + return; + } + } + } + break; +#endif /* LWIP_TCP */ + default: + LWIP_ERROR("Invalid netconn type", 0, do{ msg->err = ERR_VAL; }while(0)); + break; + } + } + /* For all other protocols, netconn_connect() calls TCPIP_APIMSG(), + so use TCPIP_APIMSG_ACK() here. */ + TCPIP_APIMSG_ACK(msg); +} + +/** + * Disconnect a pcb contained inside a netconn + * Only used for UDP netconns. + * Called from netconn_disconnect. + * + * @param m the api_msg_msg pointing to the connection to disconnect + */ +void +lwip_netconn_do_disconnect(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + +#if LWIP_UDP + if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_UDP) { + udp_disconnect(msg->conn->pcb.udp); + msg->err = ERR_OK; + } else +#endif /* LWIP_UDP */ + { + msg->err = ERR_VAL; + } + TCPIP_APIMSG_ACK(msg); +} + +#if LWIP_TCP +/** + * Set a TCP pcb contained in a netconn into listen mode + * Called from netconn_listen. + * + * @param m the api_msg_msg pointing to the connection + */ +void +lwip_netconn_do_listen(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + + if (ERR_IS_FATAL(msg->conn->last_err)) { + msg->err = msg->conn->last_err; + } else { + msg->err = ERR_CONN; + if (msg->conn->pcb.tcp != NULL) { + if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) { + if (msg->conn->state == NETCONN_NONE) { + struct tcp_pcb* lpcb; + if (msg->conn->pcb.tcp->state != CLOSED) { + /* connection is not closed, cannot listen */ + msg->err = ERR_VAL; + } else { + err_t err; + u8_t backlog; +#if TCP_LISTEN_BACKLOG + backlog = msg->msg.lb.backlog; +#else /* TCP_LISTEN_BACKLOG */ + backlog = TCP_DEFAULT_LISTEN_BACKLOG; +#endif /* TCP_LISTEN_BACKLOG */ +#if LWIP_IPV4 && LWIP_IPV6 + /* "Socket API like" dual-stack support: If IP to listen to is IP6_ADDR_ANY, + * and NETCONN_FLAG_IPV6_V6ONLY is NOT set, use IP_ANY_TYPE to listen + */ + if (ip_addr_cmp(&msg->conn->pcb.ip->local_ip, IP6_ADDR_ANY) && + (netconn_get_ipv6only(msg->conn) == 0)) { + /* change PCB type to IPADDR_TYPE_ANY */ + IP_SET_TYPE_VAL(msg->conn->pcb.tcp->local_ip, IPADDR_TYPE_ANY); + IP_SET_TYPE_VAL(msg->conn->pcb.tcp->remote_ip, IPADDR_TYPE_ANY); + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + + lpcb = tcp_listen_with_backlog_and_err(msg->conn->pcb.tcp, backlog, &err); + + if (lpcb == NULL) { + /* in this case, the old pcb is still allocated */ + msg->err = err; + } else { + /* delete the recvmbox and allocate the acceptmbox */ + if (sys_mbox_valid(&msg->conn->recvmbox)) { + /** @todo: should we drain the recvmbox here? */ + sys_mbox_free(&msg->conn->recvmbox); + sys_mbox_set_invalid(&msg->conn->recvmbox); + } + msg->err = ERR_OK; + if (!sys_mbox_valid(&msg->conn->acceptmbox)) { + msg->err = sys_mbox_new(&msg->conn->acceptmbox, DEFAULT_ACCEPTMBOX_SIZE); + } + if (msg->err == ERR_OK) { + msg->conn->state = NETCONN_LISTEN; + msg->conn->pcb.tcp = lpcb; + tcp_arg(msg->conn->pcb.tcp, msg->conn); + tcp_accept(msg->conn->pcb.tcp, accept_function); + } else { + /* since the old pcb is already deallocated, free lpcb now */ + tcp_close(lpcb); + msg->conn->pcb.tcp = NULL; + } + } + } + } else if (msg->conn->state == NETCONN_LISTEN) { + /* already listening, allow updating of the backlog */ + msg->err = ERR_OK; + tcp_backlog_set(msg->conn->pcb.tcp, msg->msg.lb.backlog); + } + } else { + msg->err = ERR_ARG; + } + } + } + TCPIP_APIMSG_ACK(msg); +} +#endif /* LWIP_TCP */ + +/** + * Send some data on a RAW or UDP pcb contained in a netconn + * Called from netconn_send + * + * @param m the api_msg_msg pointing to the connection + */ +void +lwip_netconn_do_send(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + + if (ERR_IS_FATAL(msg->conn->last_err)) { + msg->err = msg->conn->last_err; + } else { + msg->err = ERR_CONN; + if (msg->conn->pcb.tcp != NULL) { + switch (NETCONNTYPE_GROUP(msg->conn->type)) { +#if LWIP_RAW + case NETCONN_RAW: + if (ip_addr_isany(&msg->msg.b->addr) || IP_IS_ANY_TYPE_VAL(msg->msg.b->addr)) { + msg->err = raw_send(msg->conn->pcb.raw, msg->msg.b->p); + } else { + msg->err = raw_sendto(msg->conn->pcb.raw, msg->msg.b->p, &msg->msg.b->addr); + } + break; +#endif +#if LWIP_UDP + case NETCONN_UDP: +#if LWIP_CHECKSUM_ON_COPY + if (ip_addr_isany(&msg->msg.b->addr) || IP_IS_ANY_TYPE_VAL(msg->msg.b->addr)) { + msg->err = udp_send_chksum(msg->conn->pcb.udp, msg->msg.b->p, + msg->msg.b->flags & NETBUF_FLAG_CHKSUM, msg->msg.b->toport_chksum); + } else { + msg->err = udp_sendto_chksum(msg->conn->pcb.udp, msg->msg.b->p, + &msg->msg.b->addr, msg->msg.b->port, + msg->msg.b->flags & NETBUF_FLAG_CHKSUM, msg->msg.b->toport_chksum); + } +#else /* LWIP_CHECKSUM_ON_COPY */ + if (ip_addr_isany_val(msg->msg.b->addr) || IP_IS_ANY_TYPE_VAL(msg->msg.b->addr)) { + msg->err = udp_send(msg->conn->pcb.udp, msg->msg.b->p); + } else { + msg->err = udp_sendto(msg->conn->pcb.udp, msg->msg.b->p, &msg->msg.b->addr, msg->msg.b->port); + } +#endif /* LWIP_CHECKSUM_ON_COPY */ + break; +#endif /* LWIP_UDP */ + default: + break; + } + } + } + TCPIP_APIMSG_ACK(msg); +} + +#if LWIP_TCP +/** + * Indicate data has been received from a TCP pcb contained in a netconn + * Called from netconn_recv + * + * @param m the api_msg_msg pointing to the connection + */ +void +lwip_netconn_do_recv(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + + msg->err = ERR_OK; + if (msg->conn->pcb.tcp != NULL) { + if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) { + u32_t remaining = msg->msg.r.len; + do { + u16_t recved = (remaining > 0xffff) ? 0xffff : (u16_t)remaining; + tcp_recved(msg->conn->pcb.tcp, recved); + remaining -= recved; + } while (remaining != 0); + } + } + TCPIP_APIMSG_ACK(msg); +} + +#if TCP_LISTEN_BACKLOG +/** Indicate that a TCP pcb has been accepted + * Called from netconn_accept + * + * @param m the api_msg_msg pointing to the connection + */ +void +lwip_netconn_do_accepted(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + + msg->err = ERR_OK; + if (msg->conn->pcb.tcp != NULL) { + if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) { + tcp_backlog_accepted(msg->conn->pcb.tcp); + } + } + TCPIP_APIMSG_ACK(msg); +} +#endif /* TCP_LISTEN_BACKLOG */ + +/** + * See if more data needs to be written from a previous call to netconn_write. + * Called initially from lwip_netconn_do_write. If the first call can't send all data + * (because of low memory or empty send-buffer), this function is called again + * from sent_tcp() or poll_tcp() to send more data. If all data is sent, the + * blocking application thread (waiting in netconn_write) is released. + * + * @param conn netconn (that is currently in state NETCONN_WRITE) to process + * @return ERR_OK + * ERR_MEM if LWIP_TCPIP_CORE_LOCKING=1 and sending hasn't yet finished + */ +static err_t +lwip_netconn_do_writemore(struct netconn *conn WRITE_DELAYED_PARAM) +{ + err_t err; + const void *dataptr; + u16_t len, available; + u8_t write_finished = 0; + size_t diff; + u8_t dontblock; + u8_t apiflags; + + LWIP_ASSERT("conn != NULL", conn != NULL); + LWIP_ASSERT("conn->state == NETCONN_WRITE", (conn->state == NETCONN_WRITE)); + LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL); + LWIP_ASSERT("conn->pcb.tcp != NULL", conn->pcb.tcp != NULL); + LWIP_ASSERT("conn->write_offset < conn->current_msg->msg.w.len", + conn->write_offset < conn->current_msg->msg.w.len); + + apiflags = conn->current_msg->msg.w.apiflags; + dontblock = netconn_is_nonblocking(conn) || (apiflags & NETCONN_DONTBLOCK); + +#if LWIP_SO_SNDTIMEO + if ((conn->send_timeout != 0) && + ((s32_t)(sys_now() - conn->current_msg->msg.w.time_started) >= conn->send_timeout)) { + write_finished = 1; + if (conn->write_offset == 0) { + /* nothing has been written */ + err = ERR_WOULDBLOCK; + conn->current_msg->msg.w.len = 0; + } else { + /* partial write */ + err = ERR_OK; + conn->current_msg->msg.w.len = conn->write_offset; + conn->write_offset = 0; + } + } else +#endif /* LWIP_SO_SNDTIMEO */ + { + dataptr = (const u8_t*)conn->current_msg->msg.w.dataptr + conn->write_offset; + diff = conn->current_msg->msg.w.len - conn->write_offset; + if (diff > 0xffffUL) { /* max_u16_t */ + len = 0xffff; + apiflags |= TCP_WRITE_FLAG_MORE; + } else { + len = (u16_t)diff; + } + available = tcp_sndbuf(conn->pcb.tcp); + if (available < len) { + /* don't try to write more than sendbuf */ + len = available; + if (dontblock) { + if (!len) { + err = ERR_WOULDBLOCK; + goto err_mem; + } + } else { + apiflags |= TCP_WRITE_FLAG_MORE; + } + } + LWIP_ASSERT("lwip_netconn_do_writemore: invalid length!", ((conn->write_offset + len) <= conn->current_msg->msg.w.len)); + err = tcp_write(conn->pcb.tcp, dataptr, len, apiflags); + /* if OK or memory error, check available space */ + if ((err == ERR_OK) || (err == ERR_MEM)) { +err_mem: + if (dontblock && (len < conn->current_msg->msg.w.len)) { + /* non-blocking write did not write everything: mark the pcb non-writable + and let poll_tcp check writable space to mark the pcb writable again */ + API_EVENT(conn, NETCONN_EVT_SENDMINUS, len); + conn->flags |= NETCONN_FLAG_CHECK_WRITESPACE; + } else if ((tcp_sndbuf(conn->pcb.tcp) <= TCP_SNDLOWAT) || + (tcp_sndqueuelen(conn->pcb.tcp) >= TCP_SNDQUEUELOWAT)) { + /* The queued byte- or pbuf-count exceeds the configured low-water limit, + let select mark this pcb as non-writable. */ + API_EVENT(conn, NETCONN_EVT_SENDMINUS, len); + } + } + + if (err == ERR_OK) { + err_t out_err; + conn->write_offset += len; + if ((conn->write_offset == conn->current_msg->msg.w.len) || dontblock) { + /* return sent length */ + conn->current_msg->msg.w.len = conn->write_offset; + /* everything was written */ + write_finished = 1; + } + out_err = tcp_output(conn->pcb.tcp); + if (ERR_IS_FATAL(out_err) || (out_err == ERR_RTE)) { + /* If tcp_output fails with fatal error or no route is found, + don't try writing any more but return the error + to the application thread. */ + err = out_err; + write_finished = 1; + conn->current_msg->msg.w.len = 0; + } + } else if (err == ERR_MEM) { + /* If ERR_MEM, we wait for sent_tcp or poll_tcp to be called. + For blocking sockets, we do NOT return to the application + thread, since ERR_MEM is only a temporary error! Non-blocking + will remain non-writable until sent_tcp/poll_tcp is called */ + + /* tcp_write returned ERR_MEM, try tcp_output anyway */ + err_t out_err = tcp_output(conn->pcb.tcp); + if (ERR_IS_FATAL(out_err) || (out_err == ERR_RTE)) { + /* If tcp_output fails with fatal error or no route is found, + don't try writing any more but return the error + to the application thread. */ + err = out_err; + write_finished = 1; + conn->current_msg->msg.w.len = 0; + } else if (dontblock) { + /* non-blocking write is done on ERR_MEM */ + err = ERR_WOULDBLOCK; + write_finished = 1; + conn->current_msg->msg.w.len = 0; + } + } else { + /* On errors != ERR_MEM, we don't try writing any more but return + the error to the application thread. */ + write_finished = 1; + conn->current_msg->msg.w.len = 0; + } + } + if (write_finished) { + /* everything was written: set back connection state + and back to application task */ + sys_sem_t* op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg); + conn->current_msg->err = err; + conn->current_msg = NULL; + conn->write_offset = 0; + conn->state = NETCONN_NONE; + NETCONN_SET_SAFE_ERR(conn, err); +#if LWIP_TCPIP_CORE_LOCKING + if (delayed) +#endif + { + sys_sem_signal(op_completed_sem); + } + } +#if LWIP_TCPIP_CORE_LOCKING + else { + return ERR_MEM; + } +#endif + return ERR_OK; +} +#endif /* LWIP_TCP */ + +/** + * Send some data on a TCP pcb contained in a netconn + * Called from netconn_write + * + * @param m the api_msg_msg pointing to the connection + */ +void +lwip_netconn_do_write(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + + if (ERR_IS_FATAL(msg->conn->last_err)) { + msg->err = msg->conn->last_err; + } else { + if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) { +#if LWIP_TCP + if (msg->conn->state != NETCONN_NONE) { + /* netconn is connecting, closing or in blocking write */ + msg->err = ERR_INPROGRESS; + } else if (msg->conn->pcb.tcp != NULL) { + msg->conn->state = NETCONN_WRITE; + /* set all the variables used by lwip_netconn_do_writemore */ + LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL && + msg->conn->write_offset == 0); + LWIP_ASSERT("msg->msg.w.len != 0", msg->msg.w.len != 0); + msg->conn->current_msg = msg; + msg->conn->write_offset = 0; +#if LWIP_TCPIP_CORE_LOCKING + if (lwip_netconn_do_writemore(msg->conn, 0) != ERR_OK) { + LWIP_ASSERT("state!", msg->conn->state == NETCONN_WRITE); + UNLOCK_TCPIP_CORE(); + sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0); + LOCK_TCPIP_CORE(); + LWIP_ASSERT("state!", msg->conn->state != NETCONN_WRITE); + } +#else /* LWIP_TCPIP_CORE_LOCKING */ + lwip_netconn_do_writemore(msg->conn); +#endif /* LWIP_TCPIP_CORE_LOCKING */ + /* for both cases: if lwip_netconn_do_writemore was called, don't ACK the APIMSG + since lwip_netconn_do_writemore ACKs it! */ + return; + } else { + msg->err = ERR_CONN; + } +#else /* LWIP_TCP */ + msg->err = ERR_VAL; +#endif /* LWIP_TCP */ +#if (LWIP_UDP || LWIP_RAW) + } else { + msg->err = ERR_VAL; +#endif /* (LWIP_UDP || LWIP_RAW) */ + } + } + TCPIP_APIMSG_ACK(msg); +} + +/** + * Return a connection's local or remote address + * Called from netconn_getaddr + * + * @param m the api_msg_msg pointing to the connection + */ +void +lwip_netconn_do_getaddr(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + + if (msg->conn->pcb.ip != NULL) { + if (msg->msg.ad.local) { + ip_addr_copy(API_EXPR_DEREF(msg->msg.ad.ipaddr), + msg->conn->pcb.ip->local_ip); + } else { + ip_addr_copy(API_EXPR_DEREF(msg->msg.ad.ipaddr), + msg->conn->pcb.ip->remote_ip); + } + + msg->err = ERR_OK; + switch (NETCONNTYPE_GROUP(msg->conn->type)) { +#if LWIP_RAW + case NETCONN_RAW: + if (msg->msg.ad.local) { + API_EXPR_DEREF(msg->msg.ad.port) = msg->conn->pcb.raw->protocol; + } else { + /* return an error as connecting is only a helper for upper layers */ + msg->err = ERR_CONN; + } + break; +#endif /* LWIP_RAW */ +#if LWIP_UDP + case NETCONN_UDP: + if (msg->msg.ad.local) { + API_EXPR_DEREF(msg->msg.ad.port) = msg->conn->pcb.udp->local_port; + } else { + if ((msg->conn->pcb.udp->flags & UDP_FLAGS_CONNECTED) == 0) { + msg->err = ERR_CONN; + } else { + API_EXPR_DEREF(msg->msg.ad.port) = msg->conn->pcb.udp->remote_port; + } + } + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + if ((msg->msg.ad.local == 0) && + ((msg->conn->pcb.tcp->state == CLOSED) || (msg->conn->pcb.tcp->state == LISTEN))) { + /* pcb is not connected and remote name is requested */ + msg->err = ERR_CONN; + } else { + API_EXPR_DEREF(msg->msg.ad.port) = (msg->msg.ad.local ? msg->conn->pcb.tcp->local_port : msg->conn->pcb.tcp->remote_port); + } + break; +#endif /* LWIP_TCP */ + default: + LWIP_ASSERT("invalid netconn_type", 0); + break; + } + } else { + msg->err = ERR_CONN; + } + TCPIP_APIMSG_ACK(msg); +} + +/** + * Close or half-shutdown a TCP pcb contained in a netconn + * Called from netconn_close + * In contrast to closing sockets, the netconn is not deallocated. + * + * @param m the api_msg_msg pointing to the connection + */ +void +lwip_netconn_do_close(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + +#if LWIP_TCP + enum netconn_state state = msg->conn->state; + /* First check if this is a TCP netconn and if it is in a correct state + (LISTEN doesn't support half shutdown) */ + if ((msg->conn->pcb.tcp != NULL) && + (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) && + ((msg->msg.sd.shut == NETCONN_SHUT_RDWR) || (state != NETCONN_LISTEN))) { + /* Check if we are in a connected state */ + if (state == NETCONN_CONNECT) { + /* TCP connect in progress: cannot shutdown */ + msg->err = ERR_CONN; + } else if (state == NETCONN_WRITE) { +#if LWIP_NETCONN_FULLDUPLEX + if (msg->msg.sd.shut & NETCONN_SHUT_WR) { + /* close requested, abort running write */ + sys_sem_t* write_completed_sem; + LWIP_ASSERT("msg->conn->current_msg != NULL", msg->conn->current_msg != NULL); + write_completed_sem = LWIP_API_MSG_SEM(msg->conn->current_msg); + msg->conn->current_msg->err = ERR_CLSD; + msg->conn->current_msg = NULL; + msg->conn->write_offset = 0; + msg->conn->state = NETCONN_NONE; + state = NETCONN_NONE; + NETCONN_SET_SAFE_ERR(msg->conn, ERR_CLSD); + sys_sem_signal(write_completed_sem); + } else { + LWIP_ASSERT("msg->msg.sd.shut == NETCONN_SHUT_RD", msg->msg.sd.shut == NETCONN_SHUT_RD); + /* In this case, let the write continue and do not interfere with + conn->current_msg or conn->state! */ + msg->err = tcp_shutdown(msg->conn->pcb.tcp, 1, 0); + } + } + if (state == NETCONN_NONE) { +#else /* LWIP_NETCONN_FULLDUPLEX */ + msg->err = ERR_INPROGRESS; + } else { +#endif /* LWIP_NETCONN_FULLDUPLEX */ + if (msg->msg.sd.shut & NETCONN_SHUT_RD) { + /* Drain and delete mboxes */ + netconn_drain(msg->conn); + } + LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL && + msg->conn->write_offset == 0); + msg->conn->state = NETCONN_CLOSE; + msg->conn->current_msg = msg; +#if LWIP_TCPIP_CORE_LOCKING + if (lwip_netconn_do_close_internal(msg->conn, 0) != ERR_OK) { + LWIP_ASSERT("state!", msg->conn->state == NETCONN_CLOSE); + UNLOCK_TCPIP_CORE(); + sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0); + LOCK_TCPIP_CORE(); + LWIP_ASSERT("state!", msg->conn->state == NETCONN_NONE); + } +#else /* LWIP_TCPIP_CORE_LOCKING */ + lwip_netconn_do_close_internal(msg->conn); +#endif /* LWIP_TCPIP_CORE_LOCKING */ + /* for tcp netconns, lwip_netconn_do_close_internal ACKs the message */ + return; + } + } else +#endif /* LWIP_TCP */ + { + msg->err = ERR_CONN; + } + TCPIP_APIMSG_ACK(msg); +} + +#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) +/** + * Join multicast groups for UDP netconns. + * Called from netconn_join_leave_group + * + * @param m the api_msg_msg pointing to the connection + */ +void +lwip_netconn_do_join_leave_group(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + + if (ERR_IS_FATAL(msg->conn->last_err)) { + msg->err = msg->conn->last_err; + } else { + if (msg->conn->pcb.tcp != NULL) { + if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_UDP) { +#if LWIP_UDP +#if LWIP_IPV6 && LWIP_IPV6_MLD + if (NETCONNTYPE_ISIPV6(msg->conn->type)) { + if (msg->msg.jl.join_or_leave == NETCONN_JOIN) { + msg->err = mld6_joingroup(ip_2_ip6(API_EXPR_REF(msg->msg.jl.netif_addr)), + ip_2_ip6(API_EXPR_REF(msg->msg.jl.multiaddr))); + } else { + msg->err = mld6_leavegroup(ip_2_ip6(API_EXPR_REF(msg->msg.jl.netif_addr)), + ip_2_ip6(API_EXPR_REF(msg->msg.jl.multiaddr))); + } + } + else +#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */ + { +#if LWIP_IGMP + if (msg->msg.jl.join_or_leave == NETCONN_JOIN) { + msg->err = igmp_joingroup(ip_2_ip4(API_EXPR_REF(msg->msg.jl.netif_addr)), + ip_2_ip4(API_EXPR_REF(msg->msg.jl.multiaddr))); + } else { + msg->err = igmp_leavegroup(ip_2_ip4(API_EXPR_REF(msg->msg.jl.netif_addr)), + ip_2_ip4(API_EXPR_REF(msg->msg.jl.multiaddr))); + } +#endif /* LWIP_IGMP */ + } +#endif /* LWIP_UDP */ +#if (LWIP_TCP || LWIP_RAW) + } else { + msg->err = ERR_VAL; +#endif /* (LWIP_TCP || LWIP_RAW) */ + } + } else { + msg->err = ERR_CONN; + } + } + TCPIP_APIMSG_ACK(msg); +} +#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */ + +#if LWIP_DNS +/** + * Callback function that is called when DNS name is resolved + * (or on timeout). A waiting application thread is waked up by + * signaling the semaphore. + */ +static void +lwip_netconn_do_dns_found(const char *name, const ip_addr_t *ipaddr, void *arg) +{ + struct dns_api_msg *msg = (struct dns_api_msg*)arg; + + /* we trust the internal implementation to be correct :-) */ + LWIP_UNUSED_ARG(name); + + if (ipaddr == NULL) { + /* timeout or memory error */ + API_EXPR_DEREF(msg->err) = ERR_VAL; + } else { + /* address was resolved */ + API_EXPR_DEREF(msg->err) = ERR_OK; + API_EXPR_DEREF(msg->addr) = *ipaddr; + } + /* wake up the application task waiting in netconn_gethostbyname */ + sys_sem_signal(API_EXPR_REF_SEM(msg->sem)); + + // [NF_CHANGE] + sys_signal_sock_event(); + // [END_NF_CHANGE] +} + +/** + * Execute a DNS query + * Called from netconn_gethostbyname + * + * @param arg the dns_api_msg pointing to the query + */ +void +lwip_netconn_do_gethostbyname(void *arg) +{ + struct dns_api_msg *msg = (struct dns_api_msg*)arg; + u8_t addrtype = +#if LWIP_IPV4 && LWIP_IPV6 + msg->dns_addrtype; +#else + LWIP_DNS_ADDRTYPE_DEFAULT; +#endif + + API_EXPR_DEREF(msg->err) = dns_gethostbyname_addrtype(msg->name, + API_EXPR_REF(msg->addr), lwip_netconn_do_dns_found, msg, addrtype); + if (API_EXPR_DEREF(msg->err) != ERR_INPROGRESS) { + /* on error or immediate success, wake up the application + * task waiting in netconn_gethostbyname */ + sys_sem_signal(API_EXPR_REF_SEM(msg->sem)); + } +} +#endif /* LWIP_DNS */ + +#endif /* LWIP_NETCONN */ \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/LwIP/nf_sockets.c b/source/native/nf-interpreter/targets/CMSIS-OS/LwIP/nf_sockets.c new file mode 100644 index 00000000..4dc0c28a --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/LwIP/nf_sockets.c @@ -0,0 +1,2868 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2001-2004 Swedish Institute of Computer Science. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +// from the original source code file +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// 3. The name of the author may not be used to endorse or promote products +// derived from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED +// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT +// SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +// OF SUCH DAMAGE. +// +// This file is part of the lwIP TCP/IP stack. +// +// Author: Adam Dunkels +// Improved by Marc Boucher and David Haas + + +#include +#include "lwip/opt.h" + +#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/sockets.h" +#include "lwip/api.h" +#include "lwip/sys.h" +#include "lwip/igmp.h" +#include "lwip/inet.h" +#include "lwip/tcp.h" +#include "lwip/raw.h" +#include "lwip/udp.h" +#include "lwip/memp.h" +#include "lwip/pbuf.h" +#include "lwip/priv/tcpip_priv.h" +#if LWIP_CHECKSUM_ON_COPY +#include "lwip/inet_chksum.h" +#endif + +#include + +/* If the netconn API is not required publicly, then we include the necessary + files here to get the implementation */ +#if !LWIP_NETCONN +#undef LWIP_NETCONN +#define LWIP_NETCONN 1 +#include "api_msg.c" +#include "api_lib.c" +#include "netbuf.c" +#undef LWIP_NETCONN +#define LWIP_NETCONN 0 +#endif + +#if LWIP_IPV4 +#define IP4ADDR_PORT_TO_SOCKADDR(sin, ipaddr, port) do { \ + (sin)->sin_len = sizeof(struct sockaddr_in); \ + (sin)->sin_family = AF_INET; \ + (sin)->sin_port = lwip_htons((port)); \ + inet_addr_from_ip4addr(&(sin)->sin_addr, ipaddr); \ + memset((sin)->sin_zero, 0, SIN_ZERO_LEN); }while(0) +#define SOCKADDR4_TO_IP4ADDR_PORT(sin, ipaddr, port) do { \ + inet_addr_to_ip4addr(ip_2_ip4(ipaddr), &((sin)->sin_addr)); \ + (port) = lwip_ntohs((sin)->sin_port); }while(0) +#endif /* LWIP_IPV4 */ + +#if LWIP_IPV6 +#define IP6ADDR_PORT_TO_SOCKADDR(sin6, ipaddr, port) do { \ + (sin6)->sin6_len = sizeof(struct sockaddr_in6); \ + (sin6)->sin6_family = AF_INET6; \ + (sin6)->sin6_port = lwip_htons((port)); \ + (sin6)->sin6_flowinfo = 0; \ + inet6_addr_from_ip6addr(&(sin6)->sin6_addr, ipaddr); \ + (sin6)->sin6_scope_id = 0; }while(0) +#define SOCKADDR6_TO_IP6ADDR_PORT(sin6, ipaddr, port) do { \ + inet6_addr_to_ip6addr(ip_2_ip6(ipaddr), &((sin6)->sin6_addr)); \ + (port) = lwip_ntohs((sin6)->sin6_port); }while(0) +#endif /* LWIP_IPV6 */ + +#if LWIP_IPV4 && LWIP_IPV6 +static void sockaddr_to_ipaddr_port(const struct sockaddr* sockaddr, ip_addr_t* ipaddr, u16_t* port); + +#define IS_SOCK_ADDR_LEN_VALID(namelen) (((namelen) == sizeof(struct sockaddr_in)) || \ + ((namelen) == sizeof(struct sockaddr_in6))) +#define IS_SOCK_ADDR_TYPE_VALID(name) (((name)->sa_family == AF_INET) || \ + ((name)->sa_family == AF_INET6)) +#define SOCK_ADDR_TYPE_MATCH(name, sock) \ + ((((name)->sa_family == AF_INET) && !(NETCONNTYPE_ISIPV6((sock)->conn->type))) || \ + (((name)->sa_family == AF_INET6) && (NETCONNTYPE_ISIPV6((sock)->conn->type)))) +#define IPADDR_PORT_TO_SOCKADDR(sockaddr, ipaddr, port) do { \ + if (IP_IS_V6(ipaddr)) { \ + IP6ADDR_PORT_TO_SOCKADDR((struct sockaddr_in6*)(void*)(sockaddr), ip_2_ip6(ipaddr), port); \ + } else { \ + IP4ADDR_PORT_TO_SOCKADDR((struct sockaddr_in*)(void*)(sockaddr), ip_2_ip4(ipaddr), port); \ + } } while(0) +#define SOCKADDR_TO_IPADDR_PORT(sockaddr, ipaddr, port) sockaddr_to_ipaddr_port(sockaddr, ipaddr, &(port)) +#define DOMAIN_TO_NETCONN_TYPE(domain, type) (((domain) == AF_INET) ? \ + (type) : (enum netconn_type)((type) | NETCONN_TYPE_IPV6)) +#elif LWIP_IPV6 /* LWIP_IPV4 && LWIP_IPV6 */ +#define IS_SOCK_ADDR_LEN_VALID(namelen) ((namelen) == sizeof(struct sockaddr_in6)) +#define IS_SOCK_ADDR_TYPE_VALID(name) ((name)->sa_family == AF_INET6) +#define SOCK_ADDR_TYPE_MATCH(name, sock) 1 +#define IPADDR_PORT_TO_SOCKADDR(sockaddr, ipaddr, port) \ + IP6ADDR_PORT_TO_SOCKADDR((struct sockaddr_in6*)(void*)(sockaddr), ip_2_ip6(ipaddr), port) +#define SOCKADDR_TO_IPADDR_PORT(sockaddr, ipaddr, port) \ + SOCKADDR6_TO_IP6ADDR_PORT((const struct sockaddr_in6*)(const void*)(sockaddr), ipaddr, port) +#define DOMAIN_TO_NETCONN_TYPE(domain, netconn_type) (netconn_type) +#else /*-> LWIP_IPV4: LWIP_IPV4 && LWIP_IPV6 */ +#define IS_SOCK_ADDR_LEN_VALID(namelen) ((namelen) == sizeof(struct sockaddr_in)) +#define IS_SOCK_ADDR_TYPE_VALID(name) ((name)->sa_family == AF_INET) +#define SOCK_ADDR_TYPE_MATCH(name, sock) 1 +#define IPADDR_PORT_TO_SOCKADDR(sockaddr, ipaddr, port) \ + IP4ADDR_PORT_TO_SOCKADDR((struct sockaddr_in*)(void*)(sockaddr), ip_2_ip4(ipaddr), port) +#define SOCKADDR_TO_IPADDR_PORT(sockaddr, ipaddr, port) \ + SOCKADDR4_TO_IP4ADDR_PORT((const struct sockaddr_in*)(const void*)(sockaddr), ipaddr, port) +#define DOMAIN_TO_NETCONN_TYPE(domain, netconn_type) (netconn_type) +#endif /* LWIP_IPV6 */ + +#define IS_SOCK_ADDR_TYPE_VALID_OR_UNSPEC(name) (((name)->sa_family == AF_UNSPEC) || \ + IS_SOCK_ADDR_TYPE_VALID(name)) +#define SOCK_ADDR_TYPE_MATCH_OR_UNSPEC(name, sock) (((name)->sa_family == AF_UNSPEC) || \ + SOCK_ADDR_TYPE_MATCH(name, sock)) +#define IS_SOCK_ADDR_ALIGNED(name) ((((mem_ptr_t)(name)) % 4) == 0) + + +#define LWIP_SOCKOPT_CHECK_OPTLEN(optlen, opttype) do { if ((optlen) < sizeof(opttype)) { return EINVAL; }}while(0) +#define LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, opttype) do { \ + LWIP_SOCKOPT_CHECK_OPTLEN(optlen, opttype); \ + if ((sock)->conn == NULL) { return EINVAL; } }while(0) +#define LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, opttype) do { \ + LWIP_SOCKOPT_CHECK_OPTLEN(optlen, opttype); \ + if (((sock)->conn == NULL) || ((sock)->conn->pcb.tcp == NULL)) { return EINVAL; } }while(0) +#define LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, opttype, netconntype) do { \ + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, opttype); \ + if (NETCONNTYPE_GROUP(netconn_type((sock)->conn)) != netconntype) { return ENOPROTOOPT; } }while(0) + + +#define LWIP_SETGETSOCKOPT_DATA_VAR_REF(name) API_VAR_REF(name) +#define LWIP_SETGETSOCKOPT_DATA_VAR_DECLARE(name) API_VAR_DECLARE(struct lwip_setgetsockopt_data, name) +#define LWIP_SETGETSOCKOPT_DATA_VAR_FREE(name) API_VAR_FREE(MEMP_SOCKET_SETGETSOCKOPT_DATA, name) +#if LWIP_MPU_COMPATIBLE +#define LWIP_SETGETSOCKOPT_DATA_VAR_ALLOC(name, sock) do { \ + name = (struct lwip_setgetsockopt_data *)memp_malloc(MEMP_SOCKET_SETGETSOCKOPT_DATA); \ + if (name == NULL) { \ + sock_set_errno(sock, ENOMEM); \ + return -1; \ + } }while(0) +#else /* LWIP_MPU_COMPATIBLE */ +#define LWIP_SETGETSOCKOPT_DATA_VAR_ALLOC(name, sock) +#endif /* LWIP_MPU_COMPATIBLE */ + +#if LWIP_SO_SNDRCVTIMEO_NONSTANDARD +#define LWIP_SO_SNDRCVTIMEO_OPTTYPE int +#define LWIP_SO_SNDRCVTIMEO_SET(optval, val) (*(int *)(optval) = (val)) +#define LWIP_SO_SNDRCVTIMEO_GET_MS(optval) ((s32_t)*(const int*)(optval)) +#else +#define LWIP_SO_SNDRCVTIMEO_OPTTYPE struct timeval +#define LWIP_SO_SNDRCVTIMEO_SET(optval, val) do { \ + s32_t loc = (val); \ + ((struct timeval *)(optval))->tv_sec = (loc) / 1000U; \ + ((struct timeval *)(optval))->tv_usec = ((loc) % 1000U) * 1000U; }while(0) +#define LWIP_SO_SNDRCVTIMEO_GET_MS(optval) ((((const struct timeval *)(optval))->tv_sec * 1000U) + (((const struct timeval *)(optval))->tv_usec / 1000U)) +#endif + +#define NUM_SOCKETS MEMP_NUM_NETCONN + +/** This is overridable for the rare case where more than 255 threads + * select on the same socket... + */ +#ifndef SELWAIT_T +#define SELWAIT_T u8_t +#endif + +/** Contains all internal pointers and states used for a socket */ +struct lwip_sock { + /** sockets currently are built on netconns, each socket has one netconn */ + struct netconn *conn; + /** data that was left from the previous read */ + void *lastdata; + /** offset in the data that was left from the previous read */ + u16_t lastoffset; + /** number of times data was received, set by event_callback(), + tested by the receive and select functions */ + s16_t rcvevent; + /** number of times data was ACKed (free send buffer), set by event_callback(), + tested by select */ + u16_t sendevent; + /** error happened for this socket, set by event_callback(), tested by select */ + u16_t errevent; + /** last error that occurred on this socket (in fact, all our errnos fit into an u8_t) */ + u8_t err; + /** counter of how many threads are waiting for this socket using select */ + SELWAIT_T select_waiting; +}; + +#if LWIP_NETCONN_SEM_PER_THREAD +#define SELECT_SEM_T sys_sem_t* +#define SELECT_SEM_PTR(sem) (sem) +#else /* LWIP_NETCONN_SEM_PER_THREAD */ +#define SELECT_SEM_T sys_sem_t +#define SELECT_SEM_PTR(sem) (&(sem)) +#endif /* LWIP_NETCONN_SEM_PER_THREAD */ + +/** Description for a task waiting in select */ +struct lwip_select_cb { + /** Pointer to the next waiting task */ + struct lwip_select_cb *next; + /** Pointer to the previous waiting task */ + struct lwip_select_cb *prev; + /** readset passed to select */ + fd_set *readset; + /** writeset passed to select */ + fd_set *writeset; + /** unimplemented: exceptset passed to select */ + fd_set *exceptset; + /** don't signal the same semaphore twice: set to 1 when signalled */ + int sem_signalled; + /** semaphore to wake up a task waiting for select */ + SELECT_SEM_T sem; +}; + +/** A struct sockaddr replacement that has the same alignment as sockaddr_in/ + * sockaddr_in6 if instantiated. + */ +union sockaddr_aligned { + struct sockaddr sa; +#if LWIP_IPV6 + struct sockaddr_in6 sin6; +#endif /* LWIP_IPV6 */ +#if LWIP_IPV4 + struct sockaddr_in sin; +#endif /* LWIP_IPV4 */ +}; + +#if LWIP_IGMP +/* Define the number of IPv4 multicast memberships, default is one per socket */ +#ifndef LWIP_SOCKET_MAX_MEMBERSHIPS +#define LWIP_SOCKET_MAX_MEMBERSHIPS NUM_SOCKETS +#endif + +/* This is to keep track of IP_ADD_MEMBERSHIP calls to drop the membership when + a socket is closed */ +struct lwip_socket_multicast_pair { + /** the socket */ + struct lwip_sock* sock; + /** the interface address */ + ip4_addr_t if_addr; + /** the group address */ + ip4_addr_t multi_addr; +}; + +struct lwip_socket_multicast_pair socket_ipv4_multicast_memberships[LWIP_SOCKET_MAX_MEMBERSHIPS]; + +static int lwip_socket_register_membership(int s, const ip4_addr_t *if_addr, const ip4_addr_t *multi_addr); +static void lwip_socket_unregister_membership(int s, const ip4_addr_t *if_addr, const ip4_addr_t *multi_addr); +static void lwip_socket_drop_registered_memberships(int s); +#endif /* LWIP_IGMP */ + +/** The global array of available sockets */ +static struct lwip_sock sockets[NUM_SOCKETS]; +/** The global list of tasks waiting for select */ +static struct lwip_select_cb *select_cb_list; +/** This counter is increased from lwip_select when the list is changed + and checked in event_callback to see if it has changed. */ +static volatile int select_cb_ctr; + +#if LWIP_SOCKET_SET_ERRNO +#ifndef set_errno +#define set_errno(err) do { if (err) { errno = (err); } } while(0) +#endif +#else /* LWIP_SOCKET_SET_ERRNO */ +#define set_errno(err) +#endif /* LWIP_SOCKET_SET_ERRNO */ + +#define sock_set_errno(sk, e) do { \ + const int sockerr = (e); \ + sk->err = (u8_t)sockerr; \ + set_errno(sockerr); \ +} while (0) + +/* Forward declaration of some functions */ +static void event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len); +#if !LWIP_TCPIP_CORE_LOCKING +static void lwip_getsockopt_callback(void *arg); +static void lwip_setsockopt_callback(void *arg); +#endif +static u8_t lwip_getsockopt_impl(int s, int level, int optname, void *optval, socklen_t *optlen); +static u8_t lwip_setsockopt_impl(int s, int level, int optname, const void *optval, socklen_t optlen); + +#if LWIP_IPV4 && LWIP_IPV6 +static void +sockaddr_to_ipaddr_port(const struct sockaddr* sockaddr, ip_addr_t* ipaddr, u16_t* port) +{ + if ((sockaddr->sa_family) == AF_INET6) { + SOCKADDR6_TO_IP6ADDR_PORT((const struct sockaddr_in6*)(const void*)(sockaddr), ipaddr, *port); + ipaddr->type = IPADDR_TYPE_V6; + } else { + SOCKADDR4_TO_IP4ADDR_PORT((const struct sockaddr_in*)(const void*)(sockaddr), ipaddr, *port); + ipaddr->type = IPADDR_TYPE_V4; + } +} +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + +/** LWIP_NETCONN_SEM_PER_THREAD==1: initialize thread-local semaphore */ +void +lwip_socket_thread_init(void) +{ + netconn_thread_init(); +} + +/** LWIP_NETCONN_SEM_PER_THREAD==1: destroy thread-local semaphore */ +void +lwip_socket_thread_cleanup(void) +{ + netconn_thread_cleanup(); +} + +/** + * Map a externally used socket index to the internal socket representation. + * + * @param s externally used socket index + * @return struct lwip_sock for the socket or NULL if not found + */ +static struct lwip_sock * +get_socket(int s) +{ + struct lwip_sock *sock; + + s -= LWIP_SOCKET_OFFSET; + + if ((s < 0) || (s >= NUM_SOCKETS)) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): invalid\n", s + LWIP_SOCKET_OFFSET)); + set_errno(EBADF); + return NULL; + } + + sock = &sockets[s]; + + if (!sock->conn) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): not active\n", s + LWIP_SOCKET_OFFSET)); + set_errno(EBADF); + return NULL; + } + + return sock; +} + +/** + * Same as get_socket but doesn't set errno + * + * @param s externally used socket index + * @return struct lwip_sock for the socket or NULL if not found + */ +static struct lwip_sock * +tryget_socket(int s) +{ + s -= LWIP_SOCKET_OFFSET; + if ((s < 0) || (s >= NUM_SOCKETS)) { + return NULL; + } + if (!sockets[s].conn) { + return NULL; + } + return &sockets[s]; +} + +/** + * Allocate a new socket for a given netconn. + * + * @param newconn the netconn for which to allocate a socket + * @param accepted 1 if socket has been created by accept(), + * 0 if socket has been created by socket() + * @return the index of the new socket; -1 on error + */ +static int +alloc_socket(struct netconn *newconn, int accepted) +{ + int i; + SYS_ARCH_DECL_PROTECT(lev); + + /* allocate a new socket identifier */ + for (i = 0; i < NUM_SOCKETS; ++i) { + /* Protect socket array */ + SYS_ARCH_PROTECT(lev); + if (!sockets[i].conn && (sockets[i].select_waiting == 0)) { + sockets[i].conn = newconn; + /* The socket is not yet known to anyone, so no need to protect + after having marked it as used. */ + SYS_ARCH_UNPROTECT(lev); + sockets[i].lastdata = NULL; + sockets[i].lastoffset = 0; + sockets[i].rcvevent = 0; + /* TCP sendbuf is empty, but the socket is not yet writable until connected + * (unless it has been created by accept()). */ + sockets[i].sendevent = (NETCONNTYPE_GROUP(newconn->type) == NETCONN_TCP ? (accepted != 0) : 1); + sockets[i].errevent = 0; + sockets[i].err = 0; + return i + LWIP_SOCKET_OFFSET; + } + SYS_ARCH_UNPROTECT(lev); + } + return -1; +} + +/** Free a socket. The socket's netconn must have been + * delete before! + * + * @param sock the socket to free + * @param is_tcp != 0 for TCP sockets, used to free lastdata + */ +static void +free_socket(struct lwip_sock *sock, int is_tcp) +{ + void *lastdata; + + lastdata = sock->lastdata; + sock->lastdata = NULL; + sock->lastoffset = 0; + sock->err = 0; + + /* Protect socket array */ + SYS_ARCH_SET(sock->conn, NULL); + /* don't use 'sock' after this line, as another task might have allocated it */ + + if (lastdata != NULL) { + if (is_tcp) { + pbuf_free((struct pbuf *)lastdata); + } else { + netbuf_delete((struct netbuf *)lastdata); + } + } +} + +/* Below this, the well-known socket functions are implemented. + * Use google.com or opengroup.org to get a good description :-) + * + * Exceptions are documented! + */ + +int +lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen) +{ + struct lwip_sock *sock, *nsock; + struct netconn *newconn; + ip_addr_t naddr; + u16_t port = 0; + int newsock; + err_t err; + SYS_ARCH_DECL_PROTECT(lev); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d)...\n", s)); + sock = get_socket(s); + if (!sock) { + return -1; + } + + if (netconn_is_nonblocking(sock->conn) && (sock->rcvevent <= 0)) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d): returning EWOULDBLOCK\n", s)); + set_errno(EWOULDBLOCK); + return -1; + } + + /* wait for a new connection */ + err = netconn_accept(sock->conn, &newconn); + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d): netconn_acept failed, err=%d\n", s, err)); + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) { + sock_set_errno(sock, EOPNOTSUPP); + } else if (err == ERR_CLSD) { + sock_set_errno(sock, EINVAL); + } else { + sock_set_errno(sock, err_to_errno(err)); + } + return -1; + } + LWIP_ASSERT("newconn != NULL", newconn != NULL); + + newsock = alloc_socket(newconn, 1); + if (newsock == -1) { + netconn_delete(newconn); + sock_set_errno(sock, ENFILE); + return -1; + } + LWIP_ASSERT("invalid socket index", (newsock >= LWIP_SOCKET_OFFSET) && (newsock < NUM_SOCKETS + LWIP_SOCKET_OFFSET)); + LWIP_ASSERT("newconn->callback == event_callback", newconn->callback == event_callback); + nsock = &sockets[newsock - LWIP_SOCKET_OFFSET]; + + /* See event_callback: If data comes in right away after an accept, even + * though the server task might not have created a new socket yet. + * In that case, newconn->socket is counted down (newconn->socket--), + * so nsock->rcvevent is >= 1 here! + */ + SYS_ARCH_PROTECT(lev); + nsock->rcvevent += (s16_t)(-1 - newconn->socket); + newconn->socket = newsock; + SYS_ARCH_UNPROTECT(lev); + + /* Note that POSIX only requires us to check addr is non-NULL. addrlen must + * not be NULL if addr is valid. + */ + if (addr != NULL) { + union sockaddr_aligned tempaddr; + /* get the IP address and port of the remote host */ + err = netconn_peer(newconn, &naddr, &port); + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d): netconn_peer failed, err=%d\n", s, err)); + netconn_delete(newconn); + free_socket(nsock, 1); + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + LWIP_ASSERT("addr valid but addrlen NULL", addrlen != NULL); + + IPADDR_PORT_TO_SOCKADDR(&tempaddr, &naddr, port); + if (*addrlen > tempaddr.sa.sa_len) { + *addrlen = tempaddr.sa.sa_len; + } + MEMCPY(addr, &tempaddr, *addrlen); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d addr=", s, newsock)); + ip_addr_debug_print_val(SOCKETS_DEBUG, naddr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F"\n", port)); + } else { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d", s, newsock)); + } + + // [NF_CHANGE] - Signal the CLR that a socket event has occured + // TODO: We may want to investigate other ways to signal + // the CLR (maybe based on which socket received the + // event). + if(nsock->rcvevent > 0 ) { + sys_signal_sock_event(); + } + //[END_NF_CHANGE] + + sock_set_errno(sock, 0); + return newsock; +} + +int +lwip_bind(int s, const struct sockaddr *name, socklen_t namelen) +{ + struct lwip_sock *sock; + ip_addr_t local_addr; + u16_t local_port; + err_t err; + + sock = get_socket(s); + if (!sock) { + return -1; + } + + if (!SOCK_ADDR_TYPE_MATCH(name, sock)) { + /* sockaddr does not match socket type (IPv4/IPv6) */ + sock_set_errno(sock, err_to_errno(ERR_VAL)); + return -1; + } + + /* check size, family and alignment of 'name' */ + LWIP_ERROR("lwip_bind: invalid address", (IS_SOCK_ADDR_LEN_VALID(namelen) && + IS_SOCK_ADDR_TYPE_VALID(name) && IS_SOCK_ADDR_ALIGNED(name)), + sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;); + LWIP_UNUSED_ARG(namelen); + + SOCKADDR_TO_IPADDR_PORT(name, &local_addr, local_port); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d, addr=", s)); + ip_addr_debug_print_val(SOCKETS_DEBUG, local_addr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", local_port)); + +#if LWIP_IPV4 && LWIP_IPV6 + /* Dual-stack: Unmap IPv4 mapped IPv6 addresses */ + if (IP_IS_V6_VAL(local_addr) && ip6_addr_isipv4mappedipv6(ip_2_ip6(&local_addr))) { + unmap_ipv4_mapped_ipv6(ip_2_ip4(&local_addr), ip_2_ip6(&local_addr)); + IP_SET_TYPE_VAL(local_addr, IPADDR_TYPE_V4); + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + + err = netconn_bind(sock->conn, &local_addr, local_port); + + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) failed, err=%d\n", s, err)); + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) succeeded\n", s)); + sock_set_errno(sock, 0); + return 0; +} + +int +lwip_close(int s) +{ + struct lwip_sock *sock; + int is_tcp = 0; + err_t err; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_close(%d)\n", s)); + + sock = get_socket(s); + if (!sock) { + return -1; + } + + if (sock->conn != NULL) { + is_tcp = NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP; + } else { + LWIP_ASSERT("sock->lastdata == NULL", sock->lastdata == NULL); + } + +#if LWIP_IGMP + /* drop all possibly joined IGMP memberships */ + lwip_socket_drop_registered_memberships(s); +#endif /* LWIP_IGMP */ + + err = netconn_delete(sock->conn); + if (err != ERR_OK) { + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + + free_socket(sock, is_tcp); + set_errno(0); + return 0; +} + +int +lwip_connect(int s, const struct sockaddr *name, socklen_t namelen) +{ + struct lwip_sock *sock; + err_t err; + + sock = get_socket(s); + if (!sock) { + return -1; + } + + if (!SOCK_ADDR_TYPE_MATCH_OR_UNSPEC(name, sock)) { + /* sockaddr does not match socket type (IPv4/IPv6) */ + sock_set_errno(sock, err_to_errno(ERR_VAL)); + return -1; + } + + LWIP_UNUSED_ARG(namelen); + if (name->sa_family == AF_UNSPEC) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, AF_UNSPEC)\n", s)); + err = netconn_disconnect(sock->conn); + } else { + ip_addr_t remote_addr; + u16_t remote_port; + + /* check size, family and alignment of 'name' */ + LWIP_ERROR("lwip_connect: invalid address", IS_SOCK_ADDR_LEN_VALID(namelen) && + IS_SOCK_ADDR_TYPE_VALID_OR_UNSPEC(name) && IS_SOCK_ADDR_ALIGNED(name), + sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;); + + SOCKADDR_TO_IPADDR_PORT(name, &remote_addr, remote_port); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, addr=", s)); + ip_addr_debug_print_val(SOCKETS_DEBUG, remote_addr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", remote_port)); + +#if LWIP_IPV4 && LWIP_IPV6 + /* Dual-stack: Unmap IPv4 mapped IPv6 addresses */ + if (IP_IS_V6_VAL(remote_addr) && ip6_addr_isipv4mappedipv6(ip_2_ip6(&remote_addr))) { + unmap_ipv4_mapped_ipv6(ip_2_ip4(&remote_addr), ip_2_ip6(&remote_addr)); + IP_SET_TYPE_VAL(remote_addr, IPADDR_TYPE_V4); + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + + err = netconn_connect(sock->conn, &remote_addr, remote_port); + } + + if (err == ERR_INPROGRESS) + { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) operation in progress\n", s)); + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) failed, err=%d\n", s, err)); + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) succeeded\n", s)); + sock_set_errno(sock, 0); + return 0; +} + +/** + * Set a socket into listen mode. + * The socket may not have been used for another connection previously. + * + * @param s the socket to set to listening mode + * @param backlog (ATTENTION: needs TCP_LISTEN_BACKLOG=1) + * @return 0 on success, non-zero on failure + */ +int +lwip_listen(int s, int backlog) +{ + struct lwip_sock *sock; + err_t err; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d, backlog=%d)\n", s, backlog)); + + sock = get_socket(s); + if (!sock) { + return -1; + } + + /* limit the "backlog" parameter to fit in an u8_t */ + backlog = LWIP_MIN(LWIP_MAX(backlog, 0), 0xff); + + err = netconn_listen_with_backlog(sock->conn, (u8_t)backlog); + + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d) failed, err=%d\n", s, err)); + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) { + sock_set_errno(sock, EOPNOTSUPP); + return -1; + } + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + + sock_set_errno(sock, 0); + return 0; +} + +int +lwip_recvfrom(int s, void *mem, size_t len, int flags, + struct sockaddr *from, socklen_t *fromlen) +{ + struct lwip_sock *sock; + void *buf = NULL; + struct pbuf *p; + u16_t buflen, copylen; + int off = 0; + u8_t done = 0; + err_t err; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d, %p, %"SZT_F", 0x%x, ..)\n", s, mem, len, flags)); + sock = get_socket(s); + if (!sock) { + return -1; + } + + do { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: top while sock->lastdata=%p\n", sock->lastdata)); + /* Check if there is data left from the last recv operation. */ + if (sock->lastdata) { + buf = sock->lastdata; + } else { + /* If this is non-blocking call, then check first */ + if (((flags & MSG_DONTWAIT) || netconn_is_nonblocking(sock->conn)) && + (sock->rcvevent <= 0)) { + if (off > 0) { + /* already received data, return that */ + sock_set_errno(sock, 0); + return off; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): returning EWOULDBLOCK\n", s)); + set_errno(EWOULDBLOCK); + return -1; + } + + /* No data was left from the previous operation, so we try to get + some from the network. */ + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { + err = netconn_recv_tcp_pbuf(sock->conn, (struct pbuf **)&buf); + } else { + err = netconn_recv(sock->conn, (struct netbuf **)&buf); + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: netconn_recv err=%d, netbuf=%p\n", + err, buf)); + + if (err != ERR_OK) { + if (off > 0) { + if (err == ERR_CLSD) { + /* closed but already received data, ensure select gets the FIN, too */ + event_callback(sock->conn, NETCONN_EVT_RCVPLUS, 0); + } + /* already received data, return that */ + sock_set_errno(sock, 0); + return off; + } + /* We should really do some error checking here. */ + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): buf == NULL, error is \"%s\"!\n", + s, lwip_strerr(err))); + sock_set_errno(sock, err_to_errno(err)); + if (err == ERR_CLSD) { + return 0; + } else { + return -1; + } + } + LWIP_ASSERT("buf != NULL", buf != NULL); + sock->lastdata = buf; + } + + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { + p = (struct pbuf *)buf; + } else { + p = ((struct netbuf *)buf)->p; + } + buflen = p->tot_len; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: buflen=%"U16_F" len=%"SZT_F" off=%d sock->lastoffset=%"U16_F"\n", + buflen, len, off, sock->lastoffset)); + + buflen -= sock->lastoffset; + + if (len > buflen) { + copylen = buflen; + } else { + copylen = (u16_t)len; + } + + /* copy the contents of the received buffer into + the supplied memory pointer mem */ + pbuf_copy_partial(p, (u8_t*)mem + off, copylen, sock->lastoffset); + + off += copylen; + + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { + LWIP_ASSERT("invalid copylen, len would underflow", len >= copylen); + len -= copylen; + if ((len <= 0) || + (p->flags & PBUF_FLAG_PUSH) || + (sock->rcvevent <= 0) || + ((flags & MSG_PEEK) != 0)) { + done = 1; + } + } else { + done = 1; + } + + /* Check to see from where the data was.*/ + if (done) { +#if !SOCKETS_DEBUG + if (from && fromlen) +#endif /* !SOCKETS_DEBUG */ + { + u16_t port; + ip_addr_t tmpaddr; + ip_addr_t *fromaddr; + union sockaddr_aligned saddr; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s)); + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { + fromaddr = &tmpaddr; + netconn_getaddr(sock->conn, fromaddr, &port, 0); + } else { + port = netbuf_fromport((struct netbuf *)buf); + fromaddr = netbuf_fromaddr((struct netbuf *)buf); + } + +#if LWIP_IPV4 && LWIP_IPV6 + /* Dual-stack: Map IPv4 addresses to IPv4 mapped IPv6 */ + if (NETCONNTYPE_ISIPV6(netconn_type(sock->conn)) && IP_IS_V4(fromaddr)) { + ip4_2_ipv4_mapped_ipv6(ip_2_ip6(fromaddr), ip_2_ip4(fromaddr)); + IP_SET_TYPE(fromaddr, IPADDR_TYPE_V6); + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + + IPADDR_PORT_TO_SOCKADDR(&saddr, fromaddr, port); + ip_addr_debug_print(SOCKETS_DEBUG, fromaddr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F" len=%d\n", port, off)); +#if SOCKETS_DEBUG + if (from && fromlen) +#endif /* SOCKETS_DEBUG */ + { + if (*fromlen > saddr.sa.sa_len) { + *fromlen = saddr.sa.sa_len; + } + MEMCPY(from, &saddr, *fromlen); + } + } + } + + /* If we don't peek the incoming message... */ + if ((flags & MSG_PEEK) == 0) { + /* If this is a TCP socket, check if there is data left in the + buffer. If so, it should be saved in the sock structure for next + time around. */ + if ((NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) && (buflen - copylen > 0)) { + sock->lastdata = buf; + sock->lastoffset += copylen; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: lastdata now netbuf=%p\n", buf)); + } else { + sock->lastdata = NULL; + sock->lastoffset = 0; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: deleting netbuf=%p\n", buf)); + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { + pbuf_free((struct pbuf *)buf); + } else { + netbuf_delete((struct netbuf *)buf); + } + buf = NULL; + } + } + } while (!done); + + sock_set_errno(sock, 0); + return off; +} + +int +lwip_read(int s, void *mem, size_t len) +{ + return lwip_recvfrom(s, mem, len, 0, NULL, NULL); +} + +int +lwip_recv(int s, void *mem, size_t len, int flags) +{ + return lwip_recvfrom(s, mem, len, flags, NULL, NULL); +} + +int +lwip_send(int s, const void *data, size_t size, int flags) +{ + struct lwip_sock *sock; + err_t err; + u8_t write_flags; + size_t written; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d, data=%p, size=%"SZT_F", flags=0x%x)\n", + s, data, size, flags)); + + sock = get_socket(s); + if (!sock) { + return -1; + } + + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) { +#if (LWIP_UDP || LWIP_RAW) + return lwip_sendto(s, data, size, flags, NULL, 0); +#else /* (LWIP_UDP || LWIP_RAW) */ + sock_set_errno(sock, err_to_errno(ERR_ARG)); + return -1; +#endif /* (LWIP_UDP || LWIP_RAW) */ + } + + write_flags = NETCONN_COPY | + ((flags & MSG_MORE) ? NETCONN_MORE : 0) | + ((flags & MSG_DONTWAIT) ? NETCONN_DONTBLOCK : 0); + written = 0; + err = netconn_write_partly(sock->conn, data, size, write_flags, &written); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) err=%d written=%"SZT_F"\n", s, err, written)); + sock_set_errno(sock, err_to_errno(err)); + return (err == ERR_OK ? (int)written : -1); +} + +int +lwip_sendmsg(int s, const struct msghdr *msg, int flags) +{ + struct lwip_sock *sock; + int i; +#if LWIP_TCP + u8_t write_flags; + size_t written; +#endif + int size = 0; + err_t err = ERR_OK; + + sock = get_socket(s); + if (!sock) { + return -1; + } + + LWIP_ERROR("lwip_sendmsg: invalid msghdr", msg != NULL, + sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;); + + LWIP_UNUSED_ARG(msg->msg_control); + LWIP_UNUSED_ARG(msg->msg_controllen); + LWIP_UNUSED_ARG(msg->msg_flags); + LWIP_ERROR("lwip_sendmsg: invalid msghdr iov", (msg->msg_iov != NULL && msg->msg_iovlen != 0), + sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;); + + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { +#if LWIP_TCP + write_flags = NETCONN_COPY | + ((flags & MSG_MORE) ? NETCONN_MORE : 0) | + ((flags & MSG_DONTWAIT) ? NETCONN_DONTBLOCK : 0); + + for (i = 0; i < msg->msg_iovlen; i++) { + u8_t apiflags = write_flags; + if (i + 1 < msg->msg_iovlen) { + apiflags |= NETCONN_MORE; + } + written = 0; + err = netconn_write_partly(sock->conn, msg->msg_iov[i].iov_base, msg->msg_iov[i].iov_len, write_flags, &written); + if (err == ERR_OK) { + size += written; + /* check that the entire IO vector was accepected, if not return a partial write */ + if (written != msg->msg_iov[i].iov_len) + break; + } + /* none of this IO vector was accepted, but previous was, return partial write and conceal ERR_WOULDBLOCK */ + else if (err == ERR_WOULDBLOCK && size > 0) { + err = ERR_OK; + /* let ERR_WOULDBLOCK persist on the netconn since we are returning ERR_OK */ + break; + } else { + size = -1; + break; + } + } + sock_set_errno(sock, err_to_errno(err)); + return size; +#else /* LWIP_TCP */ + sock_set_errno(sock, err_to_errno(ERR_ARG)); + return -1; +#endif /* LWIP_TCP */ + } + /* else, UDP and RAW NETCONNs */ +#if LWIP_UDP || LWIP_RAW + { + struct netbuf *chain_buf; + + LWIP_UNUSED_ARG(flags); + LWIP_ERROR("lwip_sendmsg: invalid msghdr name", (((msg->msg_name == NULL) && (msg->msg_namelen == 0)) || + IS_SOCK_ADDR_LEN_VALID(msg->msg_namelen)) , + sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;); + + /* initialize chain buffer with destination */ + chain_buf = netbuf_new(); + if (!chain_buf) { + sock_set_errno(sock, err_to_errno(ERR_MEM)); + return -1; + } + if (msg->msg_name) { + u16_t remote_port; + SOCKADDR_TO_IPADDR_PORT((const struct sockaddr *)msg->msg_name, &chain_buf->addr, remote_port); + netbuf_fromport(chain_buf) = remote_port; + } +#if LWIP_NETIF_TX_SINGLE_PBUF + for (i = 0; i < msg->msg_iovlen; i++) { + size += msg->msg_iov[i].iov_len; + } + /* Allocate a new netbuf and copy the data into it. */ + if (netbuf_alloc(chain_buf, (u16_t)size) == NULL) { + err = ERR_MEM; + } else { + /* flatten the IO vectors */ + size_t offset = 0; + for (i = 0; i < msg->msg_iovlen; i++) { + MEMCPY(&((u8_t*)chain_buf->p->payload)[offset], msg->msg_iov[i].iov_base, msg->msg_iov[i].iov_len); + offset += msg->msg_iov[i].iov_len; + } +#if LWIP_CHECKSUM_ON_COPY + { + /* This can be improved by using LWIP_CHKSUM_COPY() and aggregating the checksum for each IO vector */ + u16_t chksum = ~inet_chksum_pbuf(chain_buf->p); + netbuf_set_chksum(chain_buf, chksum); + } +#endif /* LWIP_CHECKSUM_ON_COPY */ + err = ERR_OK; + } +#else /* LWIP_NETIF_TX_SINGLE_PBUF */ + /* create a chained netbuf from the IO vectors. NOTE: we assemble a pbuf chain + manually to avoid having to allocate, chain, and delete a netbuf for each iov */ + for (i = 0; i < msg->msg_iovlen; i++) { + struct pbuf *p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF); + if (p == NULL) { + err = ERR_MEM; /* let netbuf_delete() cleanup chain_buf */ + break; + } + p->payload = msg->msg_iov[i].iov_base; + LWIP_ASSERT("iov_len < u16_t", msg->msg_iov[i].iov_len <= 0xFFFF); + p->len = p->tot_len = (u16_t)msg->msg_iov[i].iov_len; + /* netbuf empty, add new pbuf */ + if (chain_buf->p == NULL) { + chain_buf->p = chain_buf->ptr = p; + /* add pbuf to existing pbuf chain */ + } else { + pbuf_cat(chain_buf->p, p); + } + } + /* save size of total chain */ + if (err == ERR_OK) { + size = netbuf_len(chain_buf); + } +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + + if (err == ERR_OK) { +#if LWIP_IPV4 && LWIP_IPV6 + /* Dual-stack: Unmap IPv4 mapped IPv6 addresses */ + if (IP_IS_V6_VAL(chain_buf->addr) && ip6_addr_isipv4mappedipv6(ip_2_ip6(&chain_buf->addr))) { + unmap_ipv4_mapped_ipv6(ip_2_ip4(&chain_buf->addr), ip_2_ip6(&chain_buf->addr)); + IP_SET_TYPE_VAL(chain_buf->addr, IPADDR_TYPE_V4); + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + + /* send the data */ + err = netconn_send(sock->conn, chain_buf); + } + + /* deallocated the buffer */ + netbuf_delete(chain_buf); + + sock_set_errno(sock, err_to_errno(err)); + return (err == ERR_OK ? size : -1); + } +#else /* LWIP_UDP || LWIP_RAW */ + sock_set_errno(sock, err_to_errno(ERR_ARG)); + return -1; +#endif /* LWIP_UDP || LWIP_RAW */ +} + +int +lwip_sendto(int s, const void *data, size_t size, int flags, + const struct sockaddr *to, socklen_t tolen) +{ + struct lwip_sock *sock; + err_t err; + u16_t short_size; + u16_t remote_port; + struct netbuf buf; + + sock = get_socket(s); + if (!sock) { + return -1; + } + + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { +#if LWIP_TCP + return lwip_send(s, data, size, flags); +#else /* LWIP_TCP */ + LWIP_UNUSED_ARG(flags); + sock_set_errno(sock, err_to_errno(ERR_ARG)); + return -1; +#endif /* LWIP_TCP */ + } + + /* @todo: split into multiple sendto's? */ + LWIP_ASSERT("lwip_sendto: size must fit in u16_t", size <= 0xffff); + short_size = (u16_t)size; + LWIP_ERROR("lwip_sendto: invalid address", (((to == NULL) && (tolen == 0)) || + (IS_SOCK_ADDR_LEN_VALID(tolen) && + IS_SOCK_ADDR_TYPE_VALID(to) && IS_SOCK_ADDR_ALIGNED(to))), + sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;); + LWIP_UNUSED_ARG(tolen); + + /* initialize a buffer */ + buf.p = buf.ptr = NULL; +#if LWIP_CHECKSUM_ON_COPY + buf.flags = 0; +#endif /* LWIP_CHECKSUM_ON_COPY */ + if (to) { + SOCKADDR_TO_IPADDR_PORT(to, &buf.addr, remote_port); + } else { + remote_port = 0; + ip_addr_set_any(NETCONNTYPE_ISIPV6(netconn_type(sock->conn)), &buf.addr); + } + netbuf_fromport(&buf) = remote_port; + + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_sendto(%d, data=%p, short_size=%"U16_F", flags=0x%x to=", + s, data, short_size, flags)); + ip_addr_debug_print(SOCKETS_DEBUG, &buf.addr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F"\n", remote_port)); + + /* make the buffer point to the data that should be sent */ +#if LWIP_NETIF_TX_SINGLE_PBUF + /* Allocate a new netbuf and copy the data into it. */ + if (netbuf_alloc(&buf, short_size) == NULL) { + err = ERR_MEM; + } else { +#if LWIP_CHECKSUM_ON_COPY + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_RAW) { + u16_t chksum = LWIP_CHKSUM_COPY(buf.p->payload, data, short_size); + netbuf_set_chksum(&buf, chksum); + } else +#endif /* LWIP_CHECKSUM_ON_COPY */ + { + MEMCPY(buf.p->payload, data, short_size); + } + err = ERR_OK; + } +#else /* LWIP_NETIF_TX_SINGLE_PBUF */ + err = netbuf_ref(&buf, data, short_size); +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + if (err == ERR_OK) { +#if LWIP_IPV4 && LWIP_IPV6 + /* Dual-stack: Unmap IPv4 mapped IPv6 addresses */ + if (IP_IS_V6_VAL(buf.addr) && ip6_addr_isipv4mappedipv6(ip_2_ip6(&buf.addr))) { + unmap_ipv4_mapped_ipv6(ip_2_ip4(&buf.addr), ip_2_ip6(&buf.addr)); + IP_SET_TYPE_VAL(buf.addr, IPADDR_TYPE_V4); + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + + /* send the data */ + err = netconn_send(sock->conn, &buf); + } + + /* deallocated the buffer */ + netbuf_free(&buf); + + sock_set_errno(sock, err_to_errno(err)); + return (err == ERR_OK ? short_size : -1); +} + +int +lwip_socket(int domain, int type, int protocol) +{ + struct netconn *conn; + int i; + + LWIP_UNUSED_ARG(domain); /* @todo: check this */ + + /* create a netconn */ + switch (type) { + case SOCK_RAW: + conn = netconn_new_with_proto_and_callback(DOMAIN_TO_NETCONN_TYPE(domain, NETCONN_RAW), + (u8_t)protocol, event_callback); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_RAW, %d) = ", + domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); + break; + case SOCK_DGRAM: + conn = netconn_new_with_callback(DOMAIN_TO_NETCONN_TYPE(domain, + ((protocol == IPPROTO_UDPLITE) ? NETCONN_UDPLITE : NETCONN_UDP)) , + event_callback); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_DGRAM, %d) = ", + domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); + break; + case SOCK_STREAM: + conn = netconn_new_with_callback(DOMAIN_TO_NETCONN_TYPE(domain, NETCONN_TCP), event_callback); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_STREAM, %d) = ", + domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%d, %d/UNKNOWN, %d) = -1\n", + domain, type, protocol)); + set_errno(EINVAL); + return -1; + } + + if (!conn) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("-1 / ENOBUFS (could not create netconn)\n")); + set_errno(ENOBUFS); + return -1; + } + + i = alloc_socket(conn, 0); + + if (i == -1) { + netconn_delete(conn); + set_errno(ENFILE); + return -1; + } + conn->socket = i; + LWIP_DEBUGF(SOCKETS_DEBUG, ("%d\n", i)); + set_errno(0); + return i; +} + +int +lwip_write(int s, const void *data, size_t size) +{ + return lwip_send(s, data, size, 0); +} + +int +lwip_writev(int s, const struct iovec *iov, int iovcnt) +{ + struct msghdr msg; + + msg.msg_name = NULL; + msg.msg_namelen = 0; + /* Hack: we have to cast via number to cast from 'const' pointer to non-const. + Blame the opengroup standard for this inconsistency. */ + msg.msg_iov = LWIP_CONST_CAST(struct iovec *, iov); + msg.msg_iovlen = iovcnt; + msg.msg_control = NULL; + msg.msg_controllen = 0; + msg.msg_flags = 0; + return lwip_sendmsg(s, &msg, 0); +} + +/** + * Go through the readset and writeset lists and see which socket of the sockets + * set in the sets has events. On return, readset, writeset and exceptset have + * the sockets enabled that had events. + * + * @param maxfdp1 the highest socket index in the sets + * @param readset_in set of sockets to check for read events + * @param writeset_in set of sockets to check for write events + * @param exceptset_in set of sockets to check for error events + * @param readset_out set of sockets that had read events + * @param writeset_out set of sockets that had write events + * @param exceptset_out set os sockets that had error events + * @return number of sockets that had events (read/write/exception) (>= 0) + */ +static int +lwip_selscan(int maxfdp1, fd_set *readset_in, fd_set *writeset_in, fd_set *exceptset_in, + fd_set *readset_out, fd_set *writeset_out, fd_set *exceptset_out) +{ + int i, nready = 0; + fd_set lreadset, lwriteset, lexceptset; + struct lwip_sock *sock; + SYS_ARCH_DECL_PROTECT(lev); + + FD_ZERO(&lreadset); + FD_ZERO(&lwriteset); + FD_ZERO(&lexceptset); + + /* Go through each socket in each list to count number of sockets which + currently match */ + for (i = LWIP_SOCKET_OFFSET; i < maxfdp1; i++) { + /* if this FD is not in the set, continue */ + if (!(readset_in && FD_ISSET(i, readset_in)) && + !(writeset_in && FD_ISSET(i, writeset_in)) && + !(exceptset_in && FD_ISSET(i, exceptset_in))) { + continue; + } + /* First get the socket's status (protected)... */ + SYS_ARCH_PROTECT(lev); + sock = tryget_socket(i); + if (sock != NULL) { + void* lastdata = sock->lastdata; + s16_t rcvevent = sock->rcvevent; + u16_t sendevent = sock->sendevent; + u16_t errevent = sock->errevent; + SYS_ARCH_UNPROTECT(lev); + + /* ... then examine it: */ + /* See if netconn of this socket is ready for read */ + if (readset_in && FD_ISSET(i, readset_in) && ((lastdata != NULL) || (rcvevent > 0))) { + FD_SET(i, &lreadset); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for reading\n", i)); + nready++; + } + /* See if netconn of this socket is ready for write */ + if (writeset_in && FD_ISSET(i, writeset_in) && (sendevent != 0)) { + FD_SET(i, &lwriteset); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for writing\n", i)); + nready++; + } + /* See if netconn of this socket had an error */ + if (exceptset_in && FD_ISSET(i, exceptset_in) && (errevent != 0)) { + FD_SET(i, &lexceptset); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for exception\n", i)); + nready++; + } + } else { + SYS_ARCH_UNPROTECT(lev); + /* continue on to next FD in list */ + } + } + /* copy local sets to the ones provided as arguments */ + *readset_out = lreadset; + *writeset_out = lwriteset; + *exceptset_out = lexceptset; + + LWIP_ASSERT("nready >= 0", nready >= 0); + return nready; +} + +int +lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset, + struct timeval *timeout) +{ + u32_t waitres = 0; + int nready; + fd_set lreadset, lwriteset, lexceptset; + u32_t msectimeout; + struct lwip_select_cb select_cb; + int i; + int maxfdp2; +#if LWIP_NETCONN_SEM_PER_THREAD + int waited = 0; +#endif + SYS_ARCH_DECL_PROTECT(lev); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select(%d, %p, %p, %p, tvsec=%"S32_F" tvusec=%"S32_F")\n", + maxfdp1, (void *)readset, (void *) writeset, (void *) exceptset, + timeout ? (s32_t)timeout->tv_sec : (s32_t)-1, + timeout ? (s32_t)timeout->tv_usec : (s32_t)-1)); + + /* Go through each socket in each list to count number of sockets which + currently match */ + nready = lwip_selscan(maxfdp1, readset, writeset, exceptset, &lreadset, &lwriteset, &lexceptset); + + /* If we don't have any current events, then suspend if we are supposed to */ + if (!nready) { + if (timeout && timeout->tv_sec == 0 && timeout->tv_usec == 0) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: no timeout, returning 0\n")); + /* This is OK as the local fdsets are empty and nready is zero, + or we would have returned earlier. */ + goto return_copy_fdsets; + } + + /* None ready: add our semaphore to list: + We don't actually need any dynamic memory. Our entry on the + list is only valid while we are in this function, so it's ok + to use local variables. */ + + select_cb.next = NULL; + select_cb.prev = NULL; + select_cb.readset = readset; + select_cb.writeset = writeset; + select_cb.exceptset = exceptset; + select_cb.sem_signalled = 0; +#if LWIP_NETCONN_SEM_PER_THREAD + select_cb.sem = LWIP_NETCONN_THREAD_SEM_GET(); +#else /* LWIP_NETCONN_SEM_PER_THREAD */ + if (sys_sem_new(&select_cb.sem, 0) != ERR_OK) { + /* failed to create semaphore */ + set_errno(ENOMEM); + return -1; + } +#endif /* LWIP_NETCONN_SEM_PER_THREAD */ + + /* Protect the select_cb_list */ + SYS_ARCH_PROTECT(lev); + + /* Put this select_cb on top of list */ + select_cb.next = select_cb_list; + if (select_cb_list != NULL) { + select_cb_list->prev = &select_cb; + } + select_cb_list = &select_cb; + /* Increasing this counter tells event_callback that the list has changed. */ + select_cb_ctr++; + + /* Now we can safely unprotect */ + SYS_ARCH_UNPROTECT(lev); + + /* Increase select_waiting for each socket we are interested in */ + maxfdp2 = maxfdp1; + for (i = LWIP_SOCKET_OFFSET; i < maxfdp1; i++) { + if ((readset && FD_ISSET(i, readset)) || + (writeset && FD_ISSET(i, writeset)) || + (exceptset && FD_ISSET(i, exceptset))) { + struct lwip_sock *sock; + SYS_ARCH_PROTECT(lev); + sock = tryget_socket(i); + if (sock != NULL) { + sock->select_waiting++; + LWIP_ASSERT("sock->select_waiting > 0", sock->select_waiting > 0); + } else { + /* Not a valid socket */ + nready = -1; + maxfdp2 = i; + SYS_ARCH_UNPROTECT(lev); + break; + } + SYS_ARCH_UNPROTECT(lev); + } + } + + if (nready >= 0) { + /* Call lwip_selscan again: there could have been events between + the last scan (without us on the list) and putting us on the list! */ + nready = lwip_selscan(maxfdp1, readset, writeset, exceptset, &lreadset, &lwriteset, &lexceptset); + if (!nready) { + /* Still none ready, just wait to be woken */ + if (timeout == 0) { + /* Wait forever */ + msectimeout = 0; + } else { + msectimeout = ((timeout->tv_sec * 1000) + ((timeout->tv_usec + 500)/1000)); + if (msectimeout == 0) { + /* Wait 1ms at least (0 means wait forever) */ + msectimeout = 1; + } + } + + waitres = sys_arch_sem_wait(SELECT_SEM_PTR(select_cb.sem), msectimeout); +#if LWIP_NETCONN_SEM_PER_THREAD + waited = 1; +#endif + } + } + + /* Decrease select_waiting for each socket we are interested in */ + for (i = LWIP_SOCKET_OFFSET; i < maxfdp2; i++) { + if ((readset && FD_ISSET(i, readset)) || + (writeset && FD_ISSET(i, writeset)) || + (exceptset && FD_ISSET(i, exceptset))) { + struct lwip_sock *sock; + SYS_ARCH_PROTECT(lev); + sock = tryget_socket(i); + if (sock != NULL) { + /* for now, handle select_waiting==0... */ + LWIP_ASSERT("sock->select_waiting > 0", sock->select_waiting > 0); + if (sock->select_waiting > 0) { + sock->select_waiting--; + } + } else { + /* Not a valid socket */ + nready = -1; + } + SYS_ARCH_UNPROTECT(lev); + } + } + /* Take us off the list */ + SYS_ARCH_PROTECT(lev); + if (select_cb.next != NULL) { + select_cb.next->prev = select_cb.prev; + } + if (select_cb_list == &select_cb) { + LWIP_ASSERT("select_cb.prev == NULL", select_cb.prev == NULL); + select_cb_list = select_cb.next; + } else { + LWIP_ASSERT("select_cb.prev != NULL", select_cb.prev != NULL); + select_cb.prev->next = select_cb.next; + } + /* Increasing this counter tells event_callback that the list has changed. */ + select_cb_ctr++; + SYS_ARCH_UNPROTECT(lev); + +#if LWIP_NETCONN_SEM_PER_THREAD + if (select_cb.sem_signalled && (!waited || (waitres == SYS_ARCH_TIMEOUT))) { + /* don't leave the thread-local semaphore signalled */ + sys_arch_sem_wait(select_cb.sem, 1); + } +#else /* LWIP_NETCONN_SEM_PER_THREAD */ + sys_sem_free(&select_cb.sem); +#endif /* LWIP_NETCONN_SEM_PER_THREAD */ + + if (nready < 0) { + /* This happens when a socket got closed while waiting */ + set_errno(EBADF); + return -1; + } + + if (waitres == SYS_ARCH_TIMEOUT) { + /* Timeout */ + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: timeout expired\n")); + /* This is OK as the local fdsets are empty and nready is zero, + or we would have returned earlier. */ + goto return_copy_fdsets; + } + + /* See what's set */ + nready = lwip_selscan(maxfdp1, readset, writeset, exceptset, &lreadset, &lwriteset, &lexceptset); + } + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: nready=%d\n", nready)); +return_copy_fdsets: + set_errno(0); + if (readset) { + *readset = lreadset; + } + if (writeset) { + *writeset = lwriteset; + } + if (exceptset) { + *exceptset = lexceptset; + } + return nready; +} + +/** + * Callback registered in the netconn layer for each socket-netconn. + * Processes recvevent (data available) and wakes up tasks waiting for select. + */ +static void +event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len) +{ + int s; + struct lwip_sock *sock; + struct lwip_select_cb *scb; + int last_select_cb_ctr; + SYS_ARCH_DECL_PROTECT(lev); + + LWIP_UNUSED_ARG(len); + + /* Get socket */ + if (conn) { + s = conn->socket; + if (s < 0) { + /* Data comes in right away after an accept, even though + * the server task might not have created a new socket yet. + * Just count down (or up) if that's the case and we + * will use the data later. Note that only receive events + * can happen before the new socket is set up. */ + SYS_ARCH_PROTECT(lev); + if (conn->socket < 0) { + if (evt == NETCONN_EVT_RCVPLUS) { + conn->socket--; + } + SYS_ARCH_UNPROTECT(lev); + return; + } + s = conn->socket; + SYS_ARCH_UNPROTECT(lev); + } + + sock = get_socket(s); + if (!sock) { + return; + } + } else { + return; + } + + SYS_ARCH_PROTECT(lev); + /* Set event as required */ + switch (evt) { + case NETCONN_EVT_RCVPLUS: + sock->rcvevent++; + break; + case NETCONN_EVT_RCVMINUS: + sock->rcvevent--; + break; + case NETCONN_EVT_SENDPLUS: + sock->sendevent = 1; + break; + case NETCONN_EVT_SENDMINUS: + sock->sendevent = 0; + break; + case NETCONN_EVT_ERROR: + sock->errevent = 1; + break; + default: + LWIP_ASSERT("unknown event", 0); + break; + } + + if (sock->select_waiting == 0) { + /* noone is waiting for this socket, no need to check select_cb_list */ + SYS_ARCH_UNPROTECT(lev); + + // [NF_CHANGE] - Signal the CLR that a socket event has occured + // TODO: We may want to investigate other ways to signal + // the CLR (maybe based on which socket received the + // event). + sys_signal_sock_event(); + //[END_NF_CHANGE] + + return; + } + + /* Now decide if anyone is waiting for this socket */ + /* NOTE: This code goes through the select_cb_list list multiple times + ONLY IF a select was actually waiting. We go through the list the number + of waiting select calls + 1. This list is expected to be small. */ + + /* At this point, SYS_ARCH is still protected! */ +again: + for (scb = select_cb_list; scb != NULL; scb = scb->next) { + /* remember the state of select_cb_list to detect changes */ + last_select_cb_ctr = select_cb_ctr; + if (scb->sem_signalled == 0) { + /* semaphore not signalled yet */ + int do_signal = 0; + /* Test this select call for our socket */ + if (sock->rcvevent > 0) { + if (scb->readset && FD_ISSET(s, scb->readset)) { + do_signal = 1; + } + } + if (sock->sendevent != 0) { + if (!do_signal && scb->writeset && FD_ISSET(s, scb->writeset)) { + do_signal = 1; + } + } + if (sock->errevent != 0) { + if (!do_signal && scb->exceptset && FD_ISSET(s, scb->exceptset)) { + do_signal = 1; + } + } + if (do_signal) { + scb->sem_signalled = 1; + /* Don't call SYS_ARCH_UNPROTECT() before signaling the semaphore, as this might + lead to the select thread taking itself off the list, invalidating the semaphore. */ + /* CHIBIOS FIX: specific variant of this call to be called from within + a lock.*/ +#if !SYS_LIGHTWEIGHT_PROT + sys_sem_signal(&scb->sem); +#else + #if LWIP_NETCONN_SEM_PER_THREAD + sys_sem_signal_S(scb->sem); + #else + sys_sem_signal_S(&scb->sem); + #endif + +#endif + } + } + /* unlock interrupts with each step */ + SYS_ARCH_UNPROTECT(lev); + /* this makes sure interrupt protection time is short */ + SYS_ARCH_PROTECT(lev); + if (last_select_cb_ctr != select_cb_ctr) { + /* someone has changed select_cb_list, restart at the beginning */ + goto again; + } + } + SYS_ARCH_UNPROTECT(lev); + + // [NF_CHANGE] - Signal the CLR that a socket event has occurred + // TODO: We may want to investigate other ways to signal + // the CLR (maybe based on which socket received the + // event). + sys_signal_sock_event(); + //[END_NF_CHANGE] +} + +/** + * Close one end of a full-duplex connection. + */ +int +lwip_shutdown(int s, int how) +{ + struct lwip_sock *sock; + err_t err; + u8_t shut_rx = 0, shut_tx = 0; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_shutdown(%d, how=%d)\n", s, how)); + + sock = get_socket(s); + if (!sock) { + return -1; + } + + if (sock->conn != NULL) { + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) { + sock_set_errno(sock, EOPNOTSUPP); + return -1; + } + } else { + sock_set_errno(sock, ENOTCONN); + return -1; + } + + if (how == SHUT_RD) { + shut_rx = 1; + } else if (how == SHUT_WR) { + shut_tx = 1; + } else if (how == SHUT_RDWR) { + shut_rx = 1; + shut_tx = 1; + } else { + sock_set_errno(sock, EINVAL); + return -1; + } + err = netconn_shutdown(sock->conn, shut_rx, shut_tx); + + sock_set_errno(sock, err_to_errno(err)); + return (err == ERR_OK ? 0 : -1); +} + +static int +lwip_getaddrname(int s, struct sockaddr *name, socklen_t *namelen, u8_t local) +{ + struct lwip_sock *sock; + union sockaddr_aligned saddr; + ip_addr_t naddr; + u16_t port; + err_t err; + + sock = get_socket(s); + if (!sock) { + return -1; + } + + /* get the IP address and port */ + err = netconn_getaddr(sock->conn, &naddr, &port, local); + if (err != ERR_OK) { + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + +#if LWIP_IPV4 && LWIP_IPV6 + /* Dual-stack: Map IPv4 addresses to IPv4 mapped IPv6 */ + if (NETCONNTYPE_ISIPV6(netconn_type(sock->conn)) && + IP_IS_V4_VAL(naddr)) { + ip4_2_ipv4_mapped_ipv6(ip_2_ip6(&naddr), ip_2_ip4(&naddr)); + IP_SET_TYPE_VAL(naddr, IPADDR_TYPE_V6); + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + + IPADDR_PORT_TO_SOCKADDR(&saddr, &naddr, port); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getaddrname(%d, addr=", s)); + ip_addr_debug_print_val(SOCKETS_DEBUG, naddr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", port)); + + if (*namelen > saddr.sa.sa_len) { + *namelen = saddr.sa.sa_len; + } + MEMCPY(name, &saddr, *namelen); + + sock_set_errno(sock, 0); + return 0; +} + +int +lwip_getpeername(int s, struct sockaddr *name, socklen_t *namelen) +{ + return lwip_getaddrname(s, name, namelen, 0); +} + +int +lwip_getsockname(int s, struct sockaddr *name, socklen_t *namelen) +{ + return lwip_getaddrname(s, name, namelen, 1); +} + +int +lwip_getsockopt(int s, int level, int optname, void *optval, socklen_t *optlen) +{ + u8_t err; + struct lwip_sock *sock = get_socket(s); +#if !LWIP_TCPIP_CORE_LOCKING + LWIP_SETGETSOCKOPT_DATA_VAR_DECLARE(data); +#endif /* !LWIP_TCPIP_CORE_LOCKING */ + + if (!sock) { + return -1; + } + + if ((NULL == optval) || (NULL == optlen)) { + sock_set_errno(sock, EFAULT); + return -1; + } + +#if LWIP_TCPIP_CORE_LOCKING + /* core-locking can just call the -impl function */ + LOCK_TCPIP_CORE(); + err = lwip_getsockopt_impl(s, level, optname, optval, optlen); + UNLOCK_TCPIP_CORE(); + +#else /* LWIP_TCPIP_CORE_LOCKING */ + +#if LWIP_MPU_COMPATIBLE + /* MPU_COMPATIBLE copies the optval data, so check for max size here */ + if (*optlen > LWIP_SETGETSOCKOPT_MAXOPTLEN) { + sock_set_errno(sock, ENOBUFS); + return -1; + } +#endif /* LWIP_MPU_COMPATIBLE */ + + LWIP_SETGETSOCKOPT_DATA_VAR_ALLOC(data, sock); + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).s = s; + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).level = level; + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optname = optname; + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optlen = *optlen; +#if !LWIP_MPU_COMPATIBLE + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optval.p = optval; +#endif /* !LWIP_MPU_COMPATIBLE */ + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).err = 0; +#if LWIP_NETCONN_SEM_PER_THREAD + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem = LWIP_NETCONN_THREAD_SEM_GET(); +#else + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem = &sock->conn->op_completed; +#endif + err = tcpip_callback(lwip_getsockopt_callback, &LWIP_SETGETSOCKOPT_DATA_VAR_REF(data)); + if (err != ERR_OK) { + LWIP_SETGETSOCKOPT_DATA_VAR_FREE(data); + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + sys_arch_sem_wait((sys_sem_t*)(LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem), 0); + + /* write back optlen and optval */ + *optlen = LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optlen; +#if LWIP_MPU_COMPATIBLE + MEMCPY(optval, LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optval, + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optlen); +#endif /* LWIP_MPU_COMPATIBLE */ + + /* maybe lwip_getsockopt_internal has changed err */ + err = LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).err; + LWIP_SETGETSOCKOPT_DATA_VAR_FREE(data); +#endif /* LWIP_TCPIP_CORE_LOCKING */ + + sock_set_errno(sock, err); + return err ? -1 : 0; +} + +#if !LWIP_TCPIP_CORE_LOCKING +/** lwip_getsockopt_callback: only used without CORE_LOCKING + * to get into the tcpip_thread + */ +static void +lwip_getsockopt_callback(void *arg) +{ + struct lwip_setgetsockopt_data *data; + LWIP_ASSERT("arg != NULL", arg != NULL); + data = (struct lwip_setgetsockopt_data*)arg; + + data->err = lwip_getsockopt_impl(data->s, data->level, data->optname, +#if LWIP_MPU_COMPATIBLE + data->optval, +#else /* LWIP_MPU_COMPATIBLE */ + data->optval.p, +#endif /* LWIP_MPU_COMPATIBLE */ + &data->optlen); + + sys_sem_signal((sys_sem_t*)(data->completed_sem)); +} +#endif /* LWIP_TCPIP_CORE_LOCKING */ + +/** lwip_getsockopt_impl: the actual implementation of getsockopt: + * same argument as lwip_getsockopt, either called directly or through callback + */ +static u8_t +lwip_getsockopt_impl(int s, int level, int optname, void *optval, socklen_t *optlen) +{ + u8_t err = 0; + struct lwip_sock *sock = tryget_socket(s); + if (!sock) { + return EBADF; + } + + switch (level) { + +/* Level: SOL_SOCKET */ + case SOL_SOCKET: + switch (optname) { + +#if LWIP_TCP + case SO_ACCEPTCONN: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, int); + if (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_TCP) { + return ENOPROTOOPT; + } + if ((sock->conn->pcb.tcp != NULL) && (sock->conn->pcb.tcp->state == LISTEN)) { + *(int*)optval = 1; + } else { + *(int*)optval = 0; + } + break; +#endif /* LWIP_TCP */ + + /* The option flags */ + case SO_BROADCAST: + case SO_KEEPALIVE: +#if SO_REUSE + case SO_REUSEADDR: +#endif /* SO_REUSE */ + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, int); + *(int*)optval = ip_get_option(sock->conn->pcb.ip, optname); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, optname=0x%x, ..) = %s\n", + s, optname, (*(int*)optval?"on":"off"))); + break; + + case SO_TYPE: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, int); + switch (NETCONNTYPE_GROUP(netconn_type(sock->conn))) { + case NETCONN_RAW: + *(int*)optval = SOCK_RAW; + break; + case NETCONN_TCP: + *(int*)optval = SOCK_STREAM; + break; + case NETCONN_UDP: + *(int*)optval = SOCK_DGRAM; + break; + default: /* unrecognized socket type */ + *(int*)optval = netconn_type(sock->conn); + LWIP_DEBUGF(SOCKETS_DEBUG, + ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE): unrecognized socket type %d\n", + s, *(int *)optval)); + } /* switch (netconn_type(sock->conn)) */ + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE) = %d\n", + s, *(int *)optval)); + break; + + case SO_ERROR: + LWIP_SOCKOPT_CHECK_OPTLEN(*optlen, int); + /* only overwrite ERR_OK or temporary errors */ + if (((sock->err == 0) || (sock->err == EINPROGRESS)) && (sock->conn != NULL)) { + sock_set_errno(sock, err_to_errno(sock->conn->last_err)); + } + *(int *)optval = (sock->err == 0xFF ? (int)-1 : (int)sock->err); + sock->err = 0; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_ERROR) = %d\n", + s, *(int *)optval)); + break; + +#if LWIP_SO_SNDTIMEO + case SO_SNDTIMEO: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, LWIP_SO_SNDRCVTIMEO_OPTTYPE); + LWIP_SO_SNDRCVTIMEO_SET(optval, netconn_get_sendtimeout(sock->conn)); + break; +#endif /* LWIP_SO_SNDTIMEO */ +#if LWIP_SO_RCVTIMEO + case SO_RCVTIMEO: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, LWIP_SO_SNDRCVTIMEO_OPTTYPE); + LWIP_SO_SNDRCVTIMEO_SET(optval, netconn_get_recvtimeout(sock->conn)); + break; +#endif /* LWIP_SO_RCVTIMEO */ +#if LWIP_SO_RCVBUF + case SO_RCVBUF: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, int); + *(int *)optval = netconn_get_recvbufsize(sock->conn); + break; +#endif /* LWIP_SO_RCVBUF */ +#if LWIP_SO_LINGER + case SO_LINGER: + { + s16_t conn_linger; + struct linger* linger = (struct linger*)optval; + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, struct linger); + conn_linger = sock->conn->linger; + if (conn_linger >= 0) { + linger->l_onoff = 1; + linger->l_linger = (int)conn_linger; + } else { + linger->l_onoff = 0; + linger->l_linger = 0; + } + } + break; +#endif /* LWIP_SO_LINGER */ +#if LWIP_UDP + case SO_NO_CHECK: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, *optlen, int, NETCONN_UDP); +#if LWIP_UDPLITE + if ((udp_flags(sock->conn->pcb.udp) & UDP_FLAGS_UDPLITE) != 0) { + /* this flag is only available for UDP, not for UDP lite */ + return EAFNOSUPPORT; + } +#endif /* LWIP_UDPLITE */ + *(int*)optval = (udp_flags(sock->conn->pcb.udp) & UDP_FLAGS_NOCHKSUM) ? 1 : 0; + break; +#endif /* LWIP_UDP*/ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; + +/* Level: IPPROTO_IP */ + case IPPROTO_IP: + switch (optname) { + case IP_TTL: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, int); + *(int*)optval = sock->conn->pcb.ip->ttl; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TTL) = %d\n", + s, *(int *)optval)); + break; + case IP_TOS: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, int); + *(int*)optval = sock->conn->pcb.ip->tos; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TOS) = %d\n", + s, *(int *)optval)); + break; +#if LWIP_MULTICAST_TX_OPTIONS + case IP_MULTICAST_TTL: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, u8_t); + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_UDP) { + return ENOPROTOOPT; + } + *(u8_t*)optval = udp_get_multicast_ttl(sock->conn->pcb.udp); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_TTL) = %d\n", + s, *(int *)optval)); + break; + case IP_MULTICAST_IF: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, struct in_addr); + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_UDP) { + return ENOPROTOOPT; + } + inet_addr_from_ip4addr((struct in_addr*)optval, udp_get_multicast_netif_addr(sock->conn->pcb.udp)); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_IF) = 0x%"X32_F"\n", + s, *(u32_t *)optval)); + break; + case IP_MULTICAST_LOOP: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, u8_t); + if ((sock->conn->pcb.udp->flags & UDP_FLAGS_MULTICAST_LOOP) != 0) { + *(u8_t*)optval = 1; + } else { + *(u8_t*)optval = 0; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_LOOP) = %d\n", + s, *(int *)optval)); + break; +#endif /* LWIP_MULTICAST_TX_OPTIONS */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; + +#if LWIP_TCP +/* Level: IPPROTO_TCP */ + case IPPROTO_TCP: + /* Special case: all IPPROTO_TCP option take an int */ + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, *optlen, int, NETCONN_TCP); + if (sock->conn->pcb.tcp->state == LISTEN) { + return EINVAL; + } + switch (optname) { + case TCP_NODELAY: + *(int*)optval = tcp_nagle_disabled(sock->conn->pcb.tcp); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_NODELAY) = %s\n", + s, (*(int*)optval)?"on":"off") ); + break; + case TCP_KEEPALIVE: + *(int*)optval = (int)sock->conn->pcb.tcp->keep_idle; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) = %d\n", + s, *(int *)optval)); + break; + +#if LWIP_TCP_KEEPALIVE + case TCP_KEEPIDLE: + *(int*)optval = (int)(sock->conn->pcb.tcp->keep_idle/1000); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_KEEPIDLE) = %d\n", + s, *(int *)optval)); + break; + case TCP_KEEPINTVL: + *(int*)optval = (int)(sock->conn->pcb.tcp->keep_intvl/1000); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_KEEPINTVL) = %d\n", + s, *(int *)optval)); + break; + case TCP_KEEPCNT: + *(int*)optval = (int)sock->conn->pcb.tcp->keep_cnt; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_KEEPCNT) = %d\n", + s, *(int *)optval)); + break; +#endif /* LWIP_TCP_KEEPALIVE */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; +#endif /* LWIP_TCP */ + +#if LWIP_IPV6 +/* Level: IPPROTO_IPV6 */ + case IPPROTO_IPV6: + switch (optname) { + case IPV6_V6ONLY: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, int); + *(int*)optval = (netconn_get_ipv6only(sock->conn) ? 1 : 0); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IPV6, IPV6_V6ONLY) = %d\n", + s, *(int *)optval)); + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IPV6, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; +#endif /* LWIP_IPV6 */ + +#if LWIP_UDP && LWIP_UDPLITE + /* Level: IPPROTO_UDPLITE */ + case IPPROTO_UDPLITE: + /* Special case: all IPPROTO_UDPLITE option take an int */ + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, int); + /* If this is no UDP lite socket, ignore any options. */ + if (!NETCONNTYPE_ISUDPLITE(netconn_type(sock->conn))) { + return ENOPROTOOPT; + } + switch (optname) { + case UDPLITE_SEND_CSCOV: + *(int*)optval = sock->conn->pcb.udp->chksum_len_tx; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UDPLITE_SEND_CSCOV) = %d\n", + s, (*(int*)optval)) ); + break; + case UDPLITE_RECV_CSCOV: + *(int*)optval = sock->conn->pcb.udp->chksum_len_rx; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UDPLITE_RECV_CSCOV) = %d\n", + s, (*(int*)optval)) ); + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; +#endif /* LWIP_UDP */ + /* Level: IPPROTO_RAW */ + case IPPROTO_RAW: + switch (optname) { +#if LWIP_IPV6 && LWIP_RAW + case IPV6_CHECKSUM: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, *optlen, int, NETCONN_RAW); + if (sock->conn->pcb.raw->chksum_reqd == 0) { + *(int *)optval = -1; + } else { + *(int *)optval = sock->conn->pcb.raw->chksum_offset; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_RAW, IPV6_CHECKSUM) = %d\n", + s, (*(int*)optval)) ); + break; +#endif /* LWIP_IPV6 && LWIP_RAW */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_RAW, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", + s, level, optname)); + err = ENOPROTOOPT; + break; + } /* switch (level) */ + + return err; +} + +int +lwip_setsockopt(int s, int level, int optname, const void *optval, socklen_t optlen) +{ + u8_t err = 0; + struct lwip_sock *sock = get_socket(s); +#if !LWIP_TCPIP_CORE_LOCKING + LWIP_SETGETSOCKOPT_DATA_VAR_DECLARE(data); +#endif /* !LWIP_TCPIP_CORE_LOCKING */ + + if (!sock) { + return -1; + } + + if (NULL == optval) { + sock_set_errno(sock, EFAULT); + return -1; + } + +#if LWIP_TCPIP_CORE_LOCKING + /* core-locking can just call the -impl function */ + LOCK_TCPIP_CORE(); + err = lwip_setsockopt_impl(s, level, optname, optval, optlen); + UNLOCK_TCPIP_CORE(); + +#else /* LWIP_TCPIP_CORE_LOCKING */ + +#if LWIP_MPU_COMPATIBLE + /* MPU_COMPATIBLE copies the optval data, so check for max size here */ + if (optlen > LWIP_SETGETSOCKOPT_MAXOPTLEN) { + sock_set_errno(sock, ENOBUFS); + return -1; + } +#endif /* LWIP_MPU_COMPATIBLE */ + + LWIP_SETGETSOCKOPT_DATA_VAR_ALLOC(data, sock); + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).s = s; + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).level = level; + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optname = optname; + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optlen = optlen; +#if LWIP_MPU_COMPATIBLE + MEMCPY(LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optval, optval, optlen); +#else /* LWIP_MPU_COMPATIBLE */ + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optval.pc = (const void*)optval; +#endif /* LWIP_MPU_COMPATIBLE */ + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).err = 0; +#if LWIP_NETCONN_SEM_PER_THREAD + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem = LWIP_NETCONN_THREAD_SEM_GET(); +#else + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem = &sock->conn->op_completed; +#endif + err = tcpip_callback(lwip_setsockopt_callback, &LWIP_SETGETSOCKOPT_DATA_VAR_REF(data)); + if (err != ERR_OK) { + LWIP_SETGETSOCKOPT_DATA_VAR_FREE(data); + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + sys_arch_sem_wait((sys_sem_t*)(LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem), 0); + + /* maybe lwip_getsockopt_internal has changed err */ + err = LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).err; + LWIP_SETGETSOCKOPT_DATA_VAR_FREE(data); +#endif /* LWIP_TCPIP_CORE_LOCKING */ + + sock_set_errno(sock, err); + return err ? -1 : 0; +} + +#if !LWIP_TCPIP_CORE_LOCKING +/** lwip_setsockopt_callback: only used without CORE_LOCKING + * to get into the tcpip_thread + */ +static void +lwip_setsockopt_callback(void *arg) +{ + struct lwip_setgetsockopt_data *data; + LWIP_ASSERT("arg != NULL", arg != NULL); + data = (struct lwip_setgetsockopt_data*)arg; + + data->err = lwip_setsockopt_impl(data->s, data->level, data->optname, +#if LWIP_MPU_COMPATIBLE + data->optval, +#else /* LWIP_MPU_COMPATIBLE */ + data->optval.pc, +#endif /* LWIP_MPU_COMPATIBLE */ + data->optlen); + + sys_sem_signal((sys_sem_t*)(data->completed_sem)); +} +#endif /* LWIP_TCPIP_CORE_LOCKING */ + +/** lwip_setsockopt_impl: the actual implementation of setsockopt: + * same argument as lwip_setsockopt, either called directly or through callback + */ +static u8_t +lwip_setsockopt_impl(int s, int level, int optname, const void *optval, socklen_t optlen) +{ + u8_t err = 0; + struct lwip_sock *sock = tryget_socket(s); + if (!sock) { + return EBADF; + } + + switch (level) { + +/* Level: SOL_SOCKET */ + case SOL_SOCKET: + switch (optname) { + + /* SO_ACCEPTCONN is get-only */ + + /* The option flags */ + case SO_BROADCAST: + case SO_KEEPALIVE: +#if SO_REUSE + case SO_REUSEADDR: +#endif /* SO_REUSE */ + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, int); + if (*(const int*)optval) { + ip_set_option(sock->conn->pcb.ip, optname); + } else { + ip_reset_option(sock->conn->pcb.ip, optname); + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, optname=0x%x, ..) -> %s\n", + s, optname, (*(const int*)optval?"on":"off"))); + break; + + /* SO_TYPE is get-only */ + /* SO_ERROR is get-only */ + +#if LWIP_SO_SNDTIMEO + case SO_SNDTIMEO: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, LWIP_SO_SNDRCVTIMEO_OPTTYPE); + netconn_set_sendtimeout(sock->conn, LWIP_SO_SNDRCVTIMEO_GET_MS(optval)); + break; +#endif /* LWIP_SO_SNDTIMEO */ +#if LWIP_SO_RCVTIMEO + case SO_RCVTIMEO: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, LWIP_SO_SNDRCVTIMEO_OPTTYPE); + netconn_set_recvtimeout(sock->conn, (int)LWIP_SO_SNDRCVTIMEO_GET_MS(optval)); + break; +#endif /* LWIP_SO_RCVTIMEO */ +#if LWIP_SO_RCVBUF + case SO_RCVBUF: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, int); + netconn_set_recvbufsize(sock->conn, *(const int*)optval); + break; +#endif /* LWIP_SO_RCVBUF */ +#if LWIP_SO_LINGER + case SO_LINGER: + { + const struct linger* linger = (const struct linger*)optval; + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, struct linger); + if (linger->l_onoff) { + int lingersec = linger->l_linger; + if (lingersec < 0) { + return EINVAL; + } + if (lingersec > 0xFFFF) { + lingersec = 0xFFFF; + } + sock->conn->linger = (s16_t)lingersec; + } else { + sock->conn->linger = -1; + } + } + break; +#endif /* LWIP_SO_LINGER */ +#if LWIP_UDP + case SO_NO_CHECK: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, int, NETCONN_UDP); +#if LWIP_UDPLITE + if ((udp_flags(sock->conn->pcb.udp) & UDP_FLAGS_UDPLITE) != 0) { + /* this flag is only available for UDP, not for UDP lite */ + return EAFNOSUPPORT; + } +#endif /* LWIP_UDPLITE */ + if (*(const int*)optval) { + udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) | UDP_FLAGS_NOCHKSUM); + } else { + udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) & ~UDP_FLAGS_NOCHKSUM); + } + break; +#endif /* LWIP_UDP */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; + +/* Level: IPPROTO_IP */ + case IPPROTO_IP: + switch (optname) { + case IP_TTL: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, int); + sock->conn->pcb.ip->ttl = (u8_t)(*(const int*)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TTL, ..) -> %d\n", + s, sock->conn->pcb.ip->ttl)); + break; + case IP_TOS: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, int); + sock->conn->pcb.ip->tos = (u8_t)(*(const int*)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TOS, ..)-> %d\n", + s, sock->conn->pcb.ip->tos)); + break; +#if LWIP_MULTICAST_TX_OPTIONS + case IP_MULTICAST_TTL: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, u8_t, NETCONN_UDP); + udp_set_multicast_ttl(sock->conn->pcb.udp, (u8_t)(*(const u8_t*)optval)); + break; + case IP_MULTICAST_IF: + { + ip4_addr_t if_addr; + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, struct in_addr, NETCONN_UDP); + inet_addr_to_ip4addr(&if_addr, (const struct in_addr*)optval); + udp_set_multicast_netif_addr(sock->conn->pcb.udp, &if_addr); + } + break; + case IP_MULTICAST_LOOP: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, u8_t, NETCONN_UDP); + if (*(const u8_t*)optval) { + udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) | UDP_FLAGS_MULTICAST_LOOP); + } else { + udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) & ~UDP_FLAGS_MULTICAST_LOOP); + } + break; +#endif /* LWIP_MULTICAST_TX_OPTIONS */ +#if LWIP_IGMP + case IP_ADD_MEMBERSHIP: + case IP_DROP_MEMBERSHIP: + { + /* If this is a TCP or a RAW socket, ignore these options. */ + /* @todo: assign membership to this socket so that it is dropped when closing the socket */ + err_t igmp_err; + const struct ip_mreq *imr = (const struct ip_mreq *)optval; + ip4_addr_t if_addr; + ip4_addr_t multi_addr; + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, struct ip_mreq, NETCONN_UDP); + inet_addr_to_ip4addr(&if_addr, &imr->imr_interface); + inet_addr_to_ip4addr(&multi_addr, &imr->imr_multiaddr); + if (optname == IP_ADD_MEMBERSHIP) { + if (!lwip_socket_register_membership(s, &if_addr, &multi_addr)) { + /* cannot track membership (out of memory) */ + err = ENOMEM; + igmp_err = ERR_OK; + } else { + igmp_err = igmp_joingroup(&if_addr, &multi_addr); + } + } else { + igmp_err = igmp_leavegroup(&if_addr, &multi_addr); + lwip_socket_unregister_membership(s, &if_addr, &multi_addr); + } + if (igmp_err != ERR_OK) { + err = EADDRNOTAVAIL; + } + } + break; +#endif /* LWIP_IGMP */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; + +#if LWIP_TCP +/* Level: IPPROTO_TCP */ + case IPPROTO_TCP: + /* Special case: all IPPROTO_TCP option take an int */ + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, int, NETCONN_TCP); + if (sock->conn->pcb.tcp->state == LISTEN) { + return EINVAL; + } + switch (optname) { + case TCP_NODELAY: + if (*(const int*)optval) { + tcp_nagle_disable(sock->conn->pcb.tcp); + } else { + tcp_nagle_enable(sock->conn->pcb.tcp); + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_NODELAY) -> %s\n", + s, (*(const int *)optval)?"on":"off") ); + break; + case TCP_KEEPALIVE: + sock->conn->pcb.tcp->keep_idle = (u32_t)(*(const int*)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) -> %"U32_F"\n", + s, sock->conn->pcb.tcp->keep_idle)); + break; + +#if LWIP_TCP_KEEPALIVE + case TCP_KEEPIDLE: + sock->conn->pcb.tcp->keep_idle = 1000*(u32_t)(*(const int*)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPIDLE) -> %"U32_F"\n", + s, sock->conn->pcb.tcp->keep_idle)); + break; + case TCP_KEEPINTVL: + sock->conn->pcb.tcp->keep_intvl = 1000*(u32_t)(*(const int*)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPINTVL) -> %"U32_F"\n", + s, sock->conn->pcb.tcp->keep_intvl)); + break; + case TCP_KEEPCNT: + sock->conn->pcb.tcp->keep_cnt = (u32_t)(*(const int*)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPCNT) -> %"U32_F"\n", + s, sock->conn->pcb.tcp->keep_cnt)); + break; +#endif /* LWIP_TCP_KEEPALIVE */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; +#endif /* LWIP_TCP*/ + +#if LWIP_IPV6 +/* Level: IPPROTO_IPV6 */ + case IPPROTO_IPV6: + switch (optname) { + case IPV6_V6ONLY: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, int, NETCONN_TCP); + if (*(const int*)optval) { + netconn_set_ipv6only(sock->conn, 1); + } else { + netconn_set_ipv6only(sock->conn, 0); + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IPV6, IPV6_V6ONLY, ..) -> %d\n", + s, (netconn_get_ipv6only(sock->conn) ? 1 : 0))); + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IPV6, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; +#endif /* LWIP_IPV6 */ + +#if LWIP_UDP && LWIP_UDPLITE + /* Level: IPPROTO_UDPLITE */ + case IPPROTO_UDPLITE: + /* Special case: all IPPROTO_UDPLITE option take an int */ + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, int); + /* If this is no UDP lite socket, ignore any options. */ + if (!NETCONNTYPE_ISUDPLITE(netconn_type(sock->conn))) { + return ENOPROTOOPT; + } + switch (optname) { + case UDPLITE_SEND_CSCOV: + if ((*(const int*)optval != 0) && ((*(const int*)optval < 8) || (*(const int*)optval > 0xffff))) { + /* don't allow illegal values! */ + sock->conn->pcb.udp->chksum_len_tx = 8; + } else { + sock->conn->pcb.udp->chksum_len_tx = (u16_t)*(const int*)optval; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UDPLITE_SEND_CSCOV) -> %d\n", + s, (*(const int*)optval)) ); + break; + case UDPLITE_RECV_CSCOV: + if ((*(const int*)optval != 0) && ((*(const int*)optval < 8) || (*(const int*)optval > 0xffff))) { + /* don't allow illegal values! */ + sock->conn->pcb.udp->chksum_len_rx = 8; + } else { + sock->conn->pcb.udp->chksum_len_rx = (u16_t)*(const int*)optval; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UDPLITE_RECV_CSCOV) -> %d\n", + s, (*(const int*)optval)) ); + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; +#endif /* LWIP_UDP */ + /* Level: IPPROTO_RAW */ + case IPPROTO_RAW: + switch (optname) { +#if LWIP_IPV6 && LWIP_RAW + case IPV6_CHECKSUM: + /* It should not be possible to disable the checksum generation with ICMPv6 + * as per RFC 3542 chapter 3.1 */ + if(sock->conn->pcb.raw->protocol == IPPROTO_ICMPV6) { + return EINVAL; + } + + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, int, NETCONN_RAW); + if (*(const int *)optval < 0) { + sock->conn->pcb.raw->chksum_reqd = 0; + } else if (*(const int *)optval & 1) { + /* Per RFC3542, odd offsets are not allowed */ + return EINVAL; + } else { + sock->conn->pcb.raw->chksum_reqd = 1; + sock->conn->pcb.raw->chksum_offset = (u16_t)*(const int *)optval; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_RAW, IPV6_CHECKSUM, ..) -> %d\n", + s, sock->conn->pcb.raw->chksum_reqd)); + break; +#endif /* LWIP_IPV6 && LWIP_RAW */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_RAW, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", + s, level, optname)); + err = ENOPROTOOPT; + break; + } /* switch (level) */ + + return err; +} + +int +lwip_ioctl(int s, long cmd, void *argp) +{ + struct lwip_sock *sock = get_socket(s); + u8_t val; +#if LWIP_SO_RCVBUF + u16_t buflen = 0; + int recv_avail; +#endif /* LWIP_SO_RCVBUF */ + + if (!sock) { + return -1; + } + + switch (cmd) { +#if LWIP_SO_RCVBUF || LWIP_FIONREAD_LINUXMODE + case FIONREAD: + if (!argp) { + sock_set_errno(sock, EINVAL); + return -1; + } +#if LWIP_FIONREAD_LINUXMODE + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) { + struct pbuf *p; + if (sock->lastdata) { + p = ((struct netbuf *)sock->lastdata)->p; + *((int*)argp) = p->tot_len - sock->lastoffset; + } else { + struct netbuf *rxbuf; + err_t err; + if (sock->rcvevent <= 0) { + *((int*)argp) = 0; + } else { + err = netconn_recv(sock->conn, &rxbuf); + if (err != ERR_OK) { + *((int*)argp) = 0; + } else { + sock->lastdata = rxbuf; + sock->lastoffset = 0; + *((int*)argp) = rxbuf->p->tot_len; + } + } + } + return 0; + } +#endif /* LWIP_FIONREAD_LINUXMODE */ + +#if LWIP_SO_RCVBUF + /* we come here if either LWIP_FIONREAD_LINUXMODE==0 or this is a TCP socket */ + SYS_ARCH_GET(sock->conn->recv_avail, recv_avail); + if (recv_avail < 0) { + recv_avail = 0; + } + *((int*)argp) = recv_avail; + + /* Check if there is data left from the last recv operation. /maq 041215 */ + if (sock->lastdata) { + struct pbuf *p = (struct pbuf *)sock->lastdata; + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) { + p = ((struct netbuf *)p)->p; + } + buflen = p->tot_len; + buflen -= sock->lastoffset; + + *((int*)argp) += buflen; + } + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONREAD, %p) = %"U16_F"\n", s, argp, *((u16_t*)argp))); + sock_set_errno(sock, 0); + return 0; +#else /* LWIP_SO_RCVBUF */ + break; +#endif /* LWIP_SO_RCVBUF */ +#endif /* LWIP_SO_RCVBUF || LWIP_FIONREAD_LINUXMODE */ + + case (long)FIONBIO: + val = 0; + if (argp && *(u32_t*)argp) { + val = 1; + } + netconn_set_nonblocking(sock->conn, val); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONBIO, %d)\n", s, val)); + sock_set_errno(sock, 0); + return 0; + + default: + break; + } /* switch (cmd) */ + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, UNIMPL: 0x%lx, %p)\n", s, cmd, argp)); + sock_set_errno(sock, ENOSYS); /* not yet implemented */ + return -1; +} + +/** A minimal implementation of fcntl. + * Currently only the commands F_GETFL and F_SETFL are implemented. + * Only the flag O_NONBLOCK is implemented. + */ +int +lwip_fcntl(int s, int cmd, int val) +{ + struct lwip_sock *sock = get_socket(s); + int ret = -1; + + if (!sock) { + return -1; + } + + switch (cmd) { + case F_GETFL: + ret = netconn_is_nonblocking(sock->conn) ? O_NONBLOCK : 0; + sock_set_errno(sock, 0); + break; + case F_SETFL: + if ((val & ~O_NONBLOCK) == 0) { + /* only O_NONBLOCK, all other bits are zero */ + netconn_set_nonblocking(sock->conn, val & O_NONBLOCK); + ret = 0; + sock_set_errno(sock, 0); + } else { + sock_set_errno(sock, ENOSYS); /* not yet implemented */ + } + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_fcntl(%d, UNIMPL: %d, %d)\n", s, cmd, val)); + sock_set_errno(sock, ENOSYS); /* not yet implemented */ + break; + } + return ret; +} + +#if LWIP_IGMP +/** Register a new IGMP membership. On socket close, the membership is dropped automatically. + * + * ATTENTION: this function is called from tcpip_thread (or under CORE_LOCK). + * + * @return 1 on success, 0 on failure + */ +static int +lwip_socket_register_membership(int s, const ip4_addr_t *if_addr, const ip4_addr_t *multi_addr) +{ + struct lwip_sock *sock = get_socket(s); + int i; + + if (!sock) { + return 0; + } + + for (i = 0; i < LWIP_SOCKET_MAX_MEMBERSHIPS; i++) { + if (socket_ipv4_multicast_memberships[i].sock == NULL) { + socket_ipv4_multicast_memberships[i].sock = sock; + ip4_addr_copy(socket_ipv4_multicast_memberships[i].if_addr, *if_addr); + ip4_addr_copy(socket_ipv4_multicast_memberships[i].multi_addr, *multi_addr); + return 1; + } + } + return 0; +} + +/** Unregister a previously registered membership. This prevents dropping the membership + * on socket close. + * + * ATTENTION: this function is called from tcpip_thread (or under CORE_LOCK). + */ +static void +lwip_socket_unregister_membership(int s, const ip4_addr_t *if_addr, const ip4_addr_t *multi_addr) +{ + struct lwip_sock *sock = get_socket(s); + int i; + + if (!sock) { + return; + } + + for (i = 0; i < LWIP_SOCKET_MAX_MEMBERSHIPS; i++) { + if ((socket_ipv4_multicast_memberships[i].sock == sock) && + ip4_addr_cmp(&socket_ipv4_multicast_memberships[i].if_addr, if_addr) && + ip4_addr_cmp(&socket_ipv4_multicast_memberships[i].multi_addr, multi_addr)) { + socket_ipv4_multicast_memberships[i].sock = NULL; + ip4_addr_set_zero(&socket_ipv4_multicast_memberships[i].if_addr); + ip4_addr_set_zero(&socket_ipv4_multicast_memberships[i].multi_addr); + return; + } + } +} + +/** Drop all memberships of a socket that were not dropped explicitly via setsockopt. + * + * ATTENTION: this function is NOT called from tcpip_thread (or under CORE_LOCK). + */ +static void +lwip_socket_drop_registered_memberships(int s) +{ + struct lwip_sock *sock = get_socket(s); + int i; + + if (!sock) { + return; + } + + for (i = 0; i < LWIP_SOCKET_MAX_MEMBERSHIPS; i++) { + if (socket_ipv4_multicast_memberships[i].sock == sock) { + ip_addr_t multi_addr, if_addr; + ip_addr_copy_from_ip4(multi_addr, socket_ipv4_multicast_memberships[i].multi_addr); + ip_addr_copy_from_ip4(if_addr, socket_ipv4_multicast_memberships[i].if_addr); + socket_ipv4_multicast_memberships[i].sock = NULL; + ip4_addr_set_zero(&socket_ipv4_multicast_memberships[i].if_addr); + ip4_addr_set_zero(&socket_ipv4_multicast_memberships[i].multi_addr); + + netconn_join_leave_group(sock->conn, &multi_addr, &if_addr, NETCONN_LEAVE); + } + } +} +#endif /* LWIP_IGMP */ + +// get last socket error +// lwIP is clearly missing an API to get the last error from a socket +uint32_t lwip_socket_get_err(int s) +{ + struct lwip_sock *sock = get_socket(s); + return sock->err; +} + +#endif /* LWIP_SOCKET */ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/LwIP/nf_sys_arch.c b/source/native/nf-interpreter/targets/CMSIS-OS/LwIP/nf_sys_arch.c new file mode 100644 index 00000000..86169cb8 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/LwIP/nf_sys_arch.c @@ -0,0 +1,368 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2001-2004 Swedish Institute of Computer Science. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +// from the original source code file +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// +// 1. Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// 2. Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// 3. The name of the author may not be used to endorse or promote products +// derived from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED +// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT +// SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +// OF SUCH DAMAGE. +// +// This file is part of the lwIP TCP/IP stack. +// +// Author: Adam Dunkels + +// see http://lwip.wikia.com/wiki/Porting_for_an_OS for instructions + +#include +#include + +#include "lwip/opt.h" +#include "lwip/mem.h" +#include "lwip/sys.h" +#include "lwip/stats.h" +#include "lwip/api.h" + +#include "arch/cc.h" +#include "arch/sys_arch.h" + +osMutexId lwip_sys_mutex; +osMutexDef(lwip_sys_mutex); + +void sys_init(void) +{ + lwip_sys_mutex = osMutexCreate(osMutex(lwip_sys_mutex)); +} + +// Creates a new semaphore. The "count" argument specifies +// the initial state of the semaphore. +err_t sys_sem_new(sys_sem_t *sem, u8_t count) +{ + osSemaphoreDef(SEM); + + *sem = osSemaphoreCreate (osSemaphore(SEM), 1); + + if(*sem == NULL) + { + #if SYS_STATS + ++lwip_stats.sys.sem.err; + #endif /* SYS_STATS */ + return ERR_MEM; + } + + if(count == 0) // Means it can't be taken + { + osSemaphoreWait(*sem,0); + } + + #if SYS_STATS + ++lwip_stats.sys.sem.used; + + if (lwip_stats.sys.sem.max < lwip_stats.sys.sem.used) + { + lwip_stats.sys.sem.max = lwip_stats.sys.sem.used; + } + #endif /* SYS_STATS */ + + return ERR_OK; +} + +// Deallocates a semaphore +void sys_sem_free(sys_sem_t *sem) +{ + #if SYS_STATS + --lwip_stats.sys.sem.used; + #endif /* SYS_STATS */ + + osSemaphoreDelete(*sem); +} + +// Signals a semaphore +void sys_sem_signal(sys_sem_t *sem) +{ + osSemaphoreRelease(*sem); +} + +/* + Blocks the thread while waiting for the semaphore to be + signaled. If the "timeout" argument is non-zero, the thread should + only be blocked for the specified time (measured in + milliseconds). + + If the timeout argument is non-zero, the return value is the number of + milliseconds spent waiting for the semaphore to be signaled. If the + semaphore wasn't signaled within the specified time, the return value is + SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore + (i.e., it was already signaled), the function may return zero. + + Notice that lwIP implements a function with a similar name, + sys_sem_wait(), that uses the sys_arch_sem_wait() function. +*/ +u32_t sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout) +{ + uint32_t starttime = osKernelSysTick(); + + if(timeout != 0) + { + if(osSemaphoreWait (*sem, timeout) == osOK) + { + return (osKernelSysTick() - starttime); + } + else + { + return SYS_ARCH_TIMEOUT; + } + } + else + { + while(osSemaphoreWait (*sem, osWaitForever) != osOK); + return (osKernelSysTick() - starttime); + } +} + +int sys_sem_valid(sys_sem_t *sem) +{ + if (*sem == SYS_SEM_NULL) + return 0; + else + return 1; +} + +void sys_sem_set_invalid(sys_sem_t *sem) +{ + *sem = SYS_SEM_NULL; +} + +// Creates an empty mailbox. +///////////////////////////////////////////////////////// +// NEEDS strong implementation at platform level +///////////////////////////////////////////////////////// +__nfweak err_t sys_mbox_new(sys_mbox_t *mbox, int size) +{ + (void)mbox; + (void)size; + + // breaks execution to ensure developer is aware that this function needs a strong implementation at platform level + __asm volatile("BKPT #0\n"); + + return ERR_OK; +} + +/* + Deallocates a mailbox. If there are messages still present in the + mailbox when the mailbox is deallocated, it is an indication of a + programming error in lwIP and the developer should be notified. +*/ +///////////////////////////////////////////////////////// +// NEEDS strong implementation at platform level +///////////////////////////////////////////////////////// +__nfweak void sys_mbox_free(sys_mbox_t *mbox) +{ + (void)mbox; + + // breaks execution to ensure developer is aware that this function needs a strong implementation at platform level + __asm volatile("BKPT #0\n"); +} + +// Posts the "msg" to the mailbox. +void sys_mbox_post(sys_mbox_t *mbox, void *data) +{ + while(osMessagePut(*mbox, (uint32_t)data, osWaitForever) != osOK); +} + +// Try to post the "msg" to the mailbox. +err_t sys_mbox_trypost(sys_mbox_t *mbox, void *msg) +{ + err_t result; + + if ( osMessagePut(*mbox, (uint32_t)msg, 0) == osOK) + { + result = ERR_OK; + } + else + { + // could not post, queue must be full + result = ERR_MEM; + + #if SYS_STATS + lwip_stats.sys.mbox.err++; + #endif /* SYS_STATS */ + + } + + return result; +} + +/* + Blocks the thread until a message arrives in the mailbox, but does + not block the thread longer than "timeout" milliseconds (similar to + the sys_arch_sem_wait() function). The "msg" argument is a result + parameter that is set by the function (i.e., by doing "*msg = + ptr"). The "msg" parameter maybe NULL to indicate that the message + should be dropped. + + The return values are the same as for the sys_arch_sem_wait() function: + Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a + timeout. + + Note that a function with a similar name, sys_mbox_fetch(), is + implemented by lwIP. +*/ +u32_t sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout) +{ + osEvent event; + uint32_t starttime = osKernelSysTick();; + + if(timeout != 0) + { + event = osMessageGet (*mbox, timeout); + + if(event.status == osEventMessage) + { + *msg = (void *)event.value.v; + return (osKernelSysTick() - starttime); + } + else + { + return SYS_ARCH_TIMEOUT; + } + } + else + { + event = osMessageGet (*mbox, osWaitForever); + *msg = (void *)event.value.v; + return (osKernelSysTick() - starttime); + } +} + +/* + Similar to sys_arch_mbox_fetch, but if message is not ready immediately, we'll + return with SYS_MBOX_EMPTY. On success, 0 is returned. +*/ +u32_t sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg) +{ + osEvent event; + + event = osMessageGet (*mbox, 0); + + if(event.status == osEventMessage) + { + *msg = (void *)event.value.v; + return ERR_OK; + } + else + { + return SYS_MBOX_EMPTY; + } +} + +int sys_mbox_valid(sys_mbox_t *mbox) +{ + if (*mbox == SYS_MBOX_NULL) + { + return 0; + } + else + { + return 1; + } +} + +void sys_mbox_set_invalid(sys_mbox_t *mbox) +{ + *mbox = SYS_MBOX_NULL; +} + +sys_thread_t sys_thread_new(const char *name, lwip_thread_fn thread, void *arg, int stacksize, int prio) +{ + const osThreadDef_t os_thread_def = { (os_pthread)thread, (osPriority)prio, stacksize, (char *)name }; + sys_thread_t newThread = osThreadCreate(&os_thread_def, arg); + + netconn_thread_init(); + + return newThread; +} + +sys_prot_t sys_arch_protect(void) +{ + osMutexWait(lwip_sys_mutex, osWaitForever); + return (sys_prot_t)1; +} + +void sys_arch_unprotect(sys_prot_t pval) +{ + (void) pval; + osMutexRelease(lwip_sys_mutex); +} + +#if LWIP_NETCONN_SEM_PER_THREAD + +///////////////////////////////////////////////////////// +// NEEDS to be implementated at platform level +// CMSIS RTOS API doesn't have a decent API to tackle +///////////////////////////////////////////////////////// + +// sys_sem_t* sys_arch_netconn_sem_get(void) +// { +// return 0; +// } + +// void sys_arch_netconn_sem_alloc(void) +// { +// } + +// void sys_arch_netconn_sem_free(void) +// { +// } + +#endif // LWIP_NETCONN_SEM_PER_THREAD + + +//////////////////////////////////////////////////// +// nanoFramework "hack" extending LwIP original code +// with this callback here we don't need any reference to CLR nor need to include any nanoFramework headers here +void (*signal_sock_functionPtr)() = 0; + +void set_signal_sock_function( void (*funcPtr)() ) +{ + signal_sock_functionPtr = funcPtr; +} + +void sys_signal_sock_event() +{ + if ( signal_sock_functionPtr != 0 ) + signal_sock_functionPtr(); +} + +//////////////////////////////////////////////////// + +///////////////////////////////////////////////////////// +// NEEDS strong implementation at platform level +///////////////////////////////////////////////////////// +__nfweak u32_t sys_now(void) +{ + + // breaks execution to ensure developer is aware that this function needs a strong implementation at platform level + __asm volatile("BKPT #0\n"); + + return 0; +} diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/common/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/common/CMakeLists.txt new file mode 100644 index 00000000..b0df1bf2 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/common/CMakeLists.txt @@ -0,0 +1,16 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append target CMSIS-OS common source files + +# if SWO opting add source file +if(SWO_OUTPUT_OPTION) + list(APPEND TARGET_CMSIS_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/swo.cpp") +endif() + +list(APPEND TARGET_CMSIS_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/syscalls.c") + +# make var global +set(TARGET_CMSIS_COMMON_SOURCES ${TARGET_CMSIS_COMMON_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/common/Include/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/common/Include/CMakeLists.txt new file mode 100644 index 00000000..c6747eaa --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/common/Include/CMakeLists.txt @@ -0,0 +1,13 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/swo.h.in" +"${CMAKE_CURRENT_BINARY_DIR}/swo.h" @ONLY) + +# append include directory for target CMSIS, need this to be the binary dir because the header is a config file +list(APPEND TARGET_CMSIS_COMMON_INCLUDE_DIRS ${CMAKE_CURRENT_BINARY_DIR}) + +# make var global +set(TARGET_CMSIS_COMMON_INCLUDE_DIRS ${TARGET_CMSIS_COMMON_INCLUDE_DIRS} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/common/Include/swo.h.in b/source/native/nf-interpreter/targets/CMSIS-OS/common/Include/swo.h.in new file mode 100644 index 00000000..5629a8d3 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/common/Include/swo.h.in @@ -0,0 +1,35 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef SWO_H_ +#define SWO_H_ + + +#define SWO_OUTPUT @SWO_OUTPUT_OPTION@ + + +#if (SWO_OUTPUT == TRUE) + +#ifdef __cplusplus +extern "C" { +#endif + + void SwoInit(); + void SwoPrintChar(char c); + void SwoPrintString(const char *s); + +#ifdef __cplusplus +} +#endif + +#endif //(SWO_OUTPUT == TRUE) + + +#endif // SWO_H_ diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/common/swo.cpp b/source/native/nf-interpreter/targets/CMSIS-OS/common/swo.cpp new file mode 100644 index 00000000..b0b62004 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/common/swo.cpp @@ -0,0 +1,107 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include "nanoCLR_Types.h" + +#if (__CORTEX_M == 0) + #error "ITM port is not available on Cortex-M0(+) cores. Need to set CMake option SWO_OUTPUT to OFF." +#else + +extern "C" void SwoInit() +{ + // set SWO pin (PB3) to alternate mode (0 == the status after RESET) + // in case it's being set to a different function in board config + palSetPadMode(GPIOB, 0x03, PAL_MODE_ALTERNATE(0) ); + + // enable trace in core debug register + CoreDebug->DEMCR = CoreDebug_DEMCR_TRCENA_Msk; + + // enable trace pins with async trace + DBGMCU->CR |= DBGMCU_CR_TRACE_IOEN | ~DBGMCU_CR_TRACE_MODE; + + // default speed for ST-Link is 2000kHz + uint32_t swoSpeed = 2000000; + uint32_t swoPrescaler = (STM32_SYSCLK / swoSpeed) + 1; + + // Write the TPIU Current Port Size Register to the desired value (default is 0x1 for a 1-bit port size) + TPI->CSPSR = 1; + // Write TPIU Formatter and Flush Control Register + TPI->FFCR = 0x100; + // Write the TPIU Select Pin Protocol to select the sync or async mode. Example: 0x2 for async NRZ mode (UART like) + TPI->SPPR = 2; + + // Write clock prescaler + TPI->ACPR = swoPrescaler; + + // unlock Write Access to the ITM registers + ITM->LAR = 0xC5ACCE55; + + // core debug: + // Trace bus ID for TPIU + // enable events + // enable sync packets + // time stamp enable + // trace main enable + ITM->TCR = ITM_TCR_TraceBusID_Msk | ITM_TCR_SWOENA_Msk | ITM_TCR_SYNCENA_Msk | ITM_TCR_ITMENA_Msk; /* ITM Trace Control Register */ + + // enable stimulus port 0 + // we are not using any other port right now + ITM->TER |= 1; + ITM->TPR = ITM_TPR_PRIVMASK_Msk; +} + +extern "C" void SwoPrintChar(char c) +{ + ITM_SendChar(c); +} + +extern "C" void SwoPrintString(const char *s) +{ + // print char until terminator is found + while(*s) + { + SwoPrintChar(*s++); + } +} + +// this function is heavily based in the CMSIS ITM_SendChar +// but with small performance improvements as we are sending a string not individual chars +__STATIC_INLINE uint32_t GenericPort_Write_CMSIS(int portNum, const char* data, size_t size) +{ + (void)portNum; + + char* p = (char*)data; + uint32_t counter = 0; + + // check if ITM port is enabled before start sending + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while(*p != '\0' || counter < size) + { + // wait until TX buffer is available + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + + ITM->PORT[0U].u8 = (uint8_t)*p++; + + counter++; + } + } + + return counter; +} + +uint32_t GenericPort_Write(int portNum, const char* data, size_t size) +{ + return GenericPort_Write_CMSIS(portNum, data, size); +} + +#endif // (__CORTEX_M == 0) diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/common/syscalls.c b/source/native/nf-interpreter/targets/CMSIS-OS/common/syscalls.c new file mode 100644 index 00000000..d53b7517 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/common/syscalls.c @@ -0,0 +1,64 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +// these are stubs to keep the linker happy when these are pulled in + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * _gettimeofday primitive (Stub function) + * */ + +/* + * Structure used in select() call, taken from the BSD file sys/time.h. + */ +struct timeval { + long tv_sec; /* seconds */ + long tv_usec; /* and microseconds */ +}; + +struct timezone { + int tz_minuteswest; /* minutes west of Greenwich */ + int tz_dsttime; /* type of dst correction */ +}; + +int _gettimeofday (struct timeval * tp, struct timezone * tzp) +{ + (void)tp; + + /* Return fixed data for the timezone. */ + if (tzp) + { + tzp->tz_minuteswest = 0; + tzp->tz_dsttime = 0; + } + + return 0; +} + +extern void _exit(int status) +{ + (void)status; + + for (;;); +} + +extern void _kill(int pid, int sig) +{ + (void) pid; + (void) sig; + return; +} + +extern int _getpid(void) +{ + return -1; +} + +#ifdef __cplusplus +} +#endif diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/nanoBooter/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/nanoBooter/CMakeLists.txt new file mode 100644 index 00000000..0753c7f3 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/nanoBooter/CMakeLists.txt @@ -0,0 +1,18 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append target CMSIS-OS nanoBooter source files +# list(APPEND TARGET_CMSIS_NANOBOOTER_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_ReceiverThread.c") + +# PAL source files +list(APPEND TARGET_CMSIS_NANOBOOTER_SOURCES "${PROJECT_SOURCE_DIR}/src/PAL/BlockStorage/nanoPAL_BlockStorage.c") + +# make var global +set(TARGET_CMSIS_NANOBOOTER_SOURCES ${TARGET_CMSIS_NANOBOOTER_SOURCES} CACHE INTERNAL "make global") + +# appendtarget CMSIS-OS nanoBooter include directory +list(APPEND TARGET_CMSIS_NANOBOOTER_INCLUDE_DIRS "${CMAKE_CURRENT_SOURCE_DIR}") +# make var global +set(TARGET_CMSIS_NANOBOOTER_INCLUDE_DIRS ${TARGET_CMSIS_NANOBOOTER_INCLUDE_DIRS} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/CMSIS-OS/nanoCLR/CMakeLists.txt b/source/native/nf-interpreter/targets/CMSIS-OS/nanoCLR/CMakeLists.txt new file mode 100644 index 00000000..4bbd6432 --- /dev/null +++ b/source/native/nf-interpreter/targets/CMSIS-OS/nanoCLR/CMakeLists.txt @@ -0,0 +1,16 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append target CMSIS-OS nanoCLR source files +# list(APPEND TARGET_CMSIS_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR_dat.s) + +# make var global +set(TARGET_CMSIS_NANOCLR_SOURCES ${TARGET_CMSIS_NANOCLR_SOURCES} CACHE INTERNAL "make global") + + +# append target CMSIS-OS nanoCLR include directory +list(APPEND TARGET_CMSIS_NANOCLR_INCLUDE_DIRS "${CMAKE_CURRENT_SOURCE_DIR}") +# make var global +set(TARGET_CMSIS_NANOCLR_INCLUDE_DIRS ${TARGET_CMSIS_NANOCLR_INCLUDE_DIRS} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/CMakeLists.txt b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/CMakeLists.txt new file mode 100644 index 00000000..ca780615 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/CMakeLists.txt @@ -0,0 +1,107 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# if mbed TLS is enabled add it to the build +if(USE_SECURITY_MBEDTLS_OPTION) + + # check if MBEDTLS_SOURCE was specified or if it's empty (default is empty) + set(NO_MBEDTLS_SOURCE TRUE) + + if(MBEDTLS_SOURCE) + if(NOT "${MBEDTLS_SOURCE}" STREQUAL "") + set(NO_MBEDTLS_SOURCE FALSE) + endif() + endif() + + # set options for mbed TLS + option(ENABLE_TESTING "no testing when building mbed TLS." OFF) + + if(NO_MBEDTLS_SOURCE) + # no mbed TLS source specified, download it from it's repo + + # check for Git (needed here for advanced warning to user if it's not installed) + find_package(Git) + + # check if Git was found, if not report to user and abort + if(NOT GIT_EXECUTABLE) + message(FATAL_ERROR "error: could not find Git, make sure you have it installed.") + endif() + + # set tag for currently supported version + set(MBEDTLS_GIT_TAG "mbedtls-2.16.3") + + # need to setup a separate CMake project to download the code from the GitHub repository + # otherwise it won't be available before the actual build step + configure_file("${PROJECT_SOURCE_DIR}/CMake/mbedTLS.CMakeLists.cmake.in" + "${CMAKE_BINARY_DIR}/mbedTLS_Download/CMakeLists.txt") + + # setup CMake project for mbedTLS download + execute_process(COMMAND ${CMAKE_COMMAND} -G "${CMAKE_GENERATOR}" . + RESULT_VARIABLE result + WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/mbedTLS_Download") + + # run build on mbedTLS download CMake project to perform the download + execute_process(COMMAND ${CMAKE_COMMAND} --build . + RESULT_VARIABLE result + WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/mbedTLS_Download") + + # add mbedTLS as external project + ExternalProject_Add( + mbedTLS + PREFIX mbedTLS + SOURCE_DIR ${CMAKE_BINARY_DIR}/mbedTLS_Source + GIT_REPOSITORY https://github.com/nanoframework/mbedtls + GIT_TAG ${MBEDTLS_GIT_TAG} # target specified branch + GIT_SHALLOW 1 # download only the tip of the branch, not the complete history + TIMEOUT 10 + LOG_DOWNLOAD 1 + + # Disable all other steps + CONFIGURE_COMMAND "" + BUILD_COMMAND "" + INSTALL_COMMAND "" + ) + + else() + # mbedTLS source was specified + + # sanity check is source path exists + if(EXISTS "${MBEDTLS_SOURCE}/") + + # check if we already have the sources, no need to copy again + if(NOT EXISTS "${CMAKE_BINARY_DIR}/mbedTLS_Source") + message(STATUS "mbedTLS source from: ${MBEDTLS_SOURCE}") + file(COPY "${MBEDTLS_SOURCE}/" DESTINATION "${CMAKE_BINARY_DIR}/mbedTLS_Source") + else() + message(STATUS "Using local cache of mbedTLS source from ${MBEDTLS_SOURCE}") + endif() + + set(MBEDTLS_INCLUDE_DIR ${CMAKE_BINARY_DIR}/mbedTLS_Source/include) + else() + message(FATAL_ERROR "Couldn't find mbedTLS source at ${MBEDTLS_SOURCE}/") + endif() + + # add mbedTLS as external project + ExternalProject_Add( + mbedTLS + PREFIX mbedTLS + SOURCE_DIR ${CMAKE_BINARY_DIR}/mbedTLS_Source + + # Disable all other steps + CONFIGURE_COMMAND "" + BUILD_COMMAND "" + INSTALL_COMMAND "" + ) + + endif() + + # get source dir for mbedTLS CMake project + ExternalProject_Get_Property(mbedTLS SOURCE_DIR) + + set(mbedTLS_INCLUDE_DIRS "${CMAKE_SOURCE_DIR}/3rdparty/humblelogging/include") + set(mbedTLS_LIBRARIES "${CMAKE_SHARED_LIBRARY_PREFIX}mbedTLS${CMAKE_SHARED_LIBRARY_SUFFIX}") + include_directories(${mbedTLS_INCLUDE_DIRS}) + +endif() diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/CMakeLists.txt b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/CMakeLists.txt new file mode 100644 index 00000000..85b526f2 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/CMakeLists.txt @@ -0,0 +1,301 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +ENABLE_LANGUAGE(ASM) + +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/target_common.h" @ONLY) + +configure_file("${CMAKE_SOURCE_DIR}/CMake/ESP32_target_os.h.in" + "${CMAKE_BINARY_DIR}/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_os.h" @ONLY) + +set(NANOCLR_PROJECT_NAME "nanoCLR") + +find_package(WireProtocol REQUIRED) + +# packages for nanoFramework libraries +# mandatory +find_package(NF_CoreCLR REQUIRED) + +####################################### +# optional + +# nF feature: debugger +if(NF_FEATURE_DEBUGGER) + find_package(NF_Debugger REQUIRED) + find_package(NF_Diagnostics REQUIRED) +endif() + +# nF feature: Networking Stack, LWIP included in IDF libs +if(USE_NETWORKING_OPTION) + find_package(NF_NETWORKING REQUIRED) +endif() + +# RTC (real time clock) (default is OFF so RTC is NOT included) +option(NF_FEATURE_RTC "option to use hardware RTC") +if(NF_FEATURE_RTC) + set(HAL_USE_RTC_OPTION TRUE CACHE INTERNAL "NF feature RTC") +else() + set(HAL_USE_RTC_OPTION FALSE CACHE INTERNAL "NF feature RTC") +endif() + +# security provider is mbedTLS +if(USE_SECURITY_MBEDTLS_OPTION) + find_package(mbedTLS REQUIRED) +endif() + +####################################### + +add_subdirectory("common") +add_subdirectory("Lwip") # lwip must be before IDF +add_subdirectory("IDF") +add_subdirectory("Network") +add_subdirectory("nanoCLR") + +# mbed TLS requires a config file +if(USE_SECURITY_MBEDTLS_OPTION) + # this seems to be only option to properly set a compiler define through the command line that needs to be a string literal + file(TO_CMAKE_PATH "${PROJECT_SOURCE_DIR}/src/PAL/COM/sockets/ssl/mbedTLS/nf_mbedtls_config.h" MBED_CONFILE) + SET(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -DMBEDTLS_CONFIG_FILE=\"<${MBED_CONFILE}>\"") + SET(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -DMBEDTLS_CONFIG_FILE=\"<${MBED_CONFILE}>\"") +endif() + +# Build the networking components as a separate library +# This is done this way to stop "Createprocess: file no found" errors in linker when object input file is greater than 32k +if(USE_NETWORKING_OPTION) + add_library(NetworkLib STATIC ${NF_Networking_SOURCES} ${TARGET_ESP32_NETWORK_SOURCES} ${TARGET_LWIP_SOURCES} ${mbedTLS_SOURCES} ) +endif() + +# add dependency for security provider mbedTLS +if(USE_SECURITY_MBEDTLS_OPTION) + add_dependencies(NetworkLib mbedTLS) +endif() + +####################### +# nanoCLR executable + +add_executable( + # executables for project, project sources + ${NANOCLR_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + "${CMAKE_CURRENT_SOURCE_DIR}/target_BlockStorage.c" + + ${COMMON_PROJECT_SOURCES} + ${TARGET_ESP32_COMMON_SOURCES} + + ${NANOCLR_PROJECT_SOURCES} + + ${TARGET_ESP32_NANOCLR_SOURCES} + + ${WireProtocol_SOURCES} + + # sources for nanoFramework libraries + ${NF_CoreCLR_SOURCES} + ${NF_Debugger_SOURCES} + ${NF_Diagnostics_SOURCES} + + # # sources for nanoFramework APIs + ${TARGET_NANO_APIS_SOURCES} +) + +# Add link flags +set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS " -Wl,--start-group ") + +if(USE_SECURITY_MBEDTLS_OPTION) + add_dependencies(${NANOCLR_PROJECT_NAME}.elf NetworkLib) +endif() + +#message( "project libs:${PROJECT_LINK_LIBS} " ) +set(LIBPATHSAVE "") +foreach( IDF_libraries ${PROJECT_LINK_LIBS} ) + + get_filename_component( LIBNAME ${IDF_libraries} NAME_WE ) + get_filename_component( LIBPATH ${IDF_libraries} DIRECTORY ) + + string( SUBSTRING ${LIBNAME} 3 -1 LIBSHORT ) + + if( NOT "${LIBPATHSAVE}" STREQUAL ${LIBPATH} ) + set(LIBPATHSAVE ${LIBPATH}) + set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS " -L${LIBPATH} " ) + endif() + + # Add psram workarounds for newlib + if( "${LIBSHORT}" STREQUAL "newlib" ) + set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS " ${ESP32_IDF_PATH}/components/newlib/lib/libc-psram-workaround.a " ) + set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS " ${ESP32_IDF_PATH}/components/newlib/lib/libm-psram-workaround.a " ) + endif() + + set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS " -l${LIBSHORT} " ) + + if( "${LIBSHORT}" STREQUAL "app_update" ) + set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS " -u esp_app_desc " ) + endif() + + if( "${LIBSHORT}" STREQUAL "bt" ) + set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS " -L${ESP32_IDF_PATH}/components/bt/lib -lbtdm_app " ) + endif() + + # Add options into LINK_FLAGS in same position as IDF link + if( "${LIBSHORT}" STREQUAL "cxx" ) + # Cxx Library needs an undefine + set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS " -u __cxa_guard_dummy -u __cxx_fatal_exception " ) + endif() + + if( "${LIBSHORT}" STREQUAL "esp32" ) + set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS " ${ESP32_IDF_PATH}/components/esp32/libhal.a " ) + set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS " -L ${ESP32_IDF_PATH}/components/esp32/lib -lcore -lrtc -lnet80211 -lpp -lwpa -lsmartconfig -lcoexist -lwps -lwpa2 -lespnow -lphy -lmesh") + + set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS " -L ${CMAKE_CURRENT_SOURCE_DIR} -T esp32_out.ld ") + set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS " -L ${ESP32_IDF_PATH}/components/esp32/ld -u ld_include_panic_highint_hdl -T esp32.project.ld -T esp32.rom.ld -T esp32.peripherals.ld -T esp32.rom.libgcc.ld ") + endif() + + + if( "${LIBSHORT}" STREQUAL "freertos" ) + # Cxx Library needs an undefine + set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS " -Wl,--undefined=uxTopUsedPriority " ) + endif() + +endforeach( IDF_libraries ) + + +if(USE_NETWORKING_OPTION) + set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS " -L${CMAKE_CURRENT_BINARY_DIR} -lNetworkLib " ) +endif() + +set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS " -lgcc -lstdc++ -lgcov -Wl,--end-group -Wl,-EL ") + +# include common directories +include_directories( + ${CMAKE_CURRENT_BINARY_DIR} + ${CMAKE_CURRENT_SOURCE_DIR} + ${CMAKE_CURRENT_SOURCE_DIR}/include + ${CMAKE_CURRENT_SOURCE_DIR}/common + ${PROJECT_SOURCE_DIR}/src/CLR/Core + ${PROJECT_SOURCE_DIR}/src/CLR/Include + ${PROJECT_SOURCE_DIR}/src/CLR/Debugger + ${PROJECT_SOURCE_DIR}/src/HAL/Include + ${PROJECT_SOURCE_DIR}/src/PAL/Include + ${PROJECT_SOURCE_DIR}/src/CLR/Runtime.Native + + ${PROJECT_SOURCE_DIR}/src/PAL/COM/sockets/ssl + + ${WireProtocol_INCLUDE_DIRS} + + ${TARGET_ESP32_IDF_INCLUDES} +) + +# include directories for nanoCLR +target_include_directories(${NANOCLR_PROJECT_NAME}.elf PUBLIC + ${CMAKE_CURRENT_BINARY_DIR}/nanoCLR + ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR + + # directories for nanoFramework libraries + ${NF_CoreCLR_INCLUDE_DIRS} + ${NF_Debugger_INCLUDE_DIRS} + ${NF_Networking_INCLUDE_DIRS} + + # includes for nanoFramework APIs + ${TARGET_NANO_APIS_INCLUDES} +) + +# Set Includes & compile definition for Network library +if(USE_NETWORKING_OPTION) + target_include_directories(NetworkLib PUBLIC + ${CMAKE_CURRENT_BINARY_DIR}/nanoCLR + ${NF_CoreCLR_INCLUDE_DIRS} + ${NF_Networking_INCLUDE_DIRS} + ${mbedTLS_INCLUDE_DIRS} + ) + + target_compile_definitions(NetworkLib PUBLIC "-DPLATFORM_ESP32 " ) + set (EXTRA_LIBS ${EXTRA_LIBS} NetworkLib) + target_link_libraries(${NANOCLR_PROJECT_NAME}.elf ${EXTRA_LIBS}) + SET( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${GCC_COVERAGE_COMPILE_FLAGS}" ) + + # Inhibit warnings so we can compile 3rd party code (Lwip) + set_target_properties(NetworkLib PROPERTIES COMPILE_FLAGS " -w " ) +endif() + +# set platform for NanoClr +target_compile_definitions(${NANOCLR_PROJECT_NAME}.elf PUBLIC "-DPLATFORM_ESP32 " ) + +# build types that have debugging capabilities AND are NOT RTM have to have the define 'NANOCLR_ENABLE_SOURCELEVELDEBUGGING' +if((NOT NF_BUILD_RTM) OR NF_FEATURE_DEBUGGER) + target_compile_definitions(${NANOCLR_PROJECT_NAME}.elf PUBLIC "-DNANOCLR_ENABLE_SOURCELEVELDEBUGGING ") +endif() + +# set compiler definition for using Application Domains feature +if(NF_FEATURE_USE_APPDOMAINS) + target_compile_definitions(${NANOCLR_PROJECT_NAME}.elf PUBLIC -DNANOCLR_USE_APPDOMAINS) +endif() + +# set compiler definition for implementing (or not) CRC32 in Wire Protocol +if(NF_WP_IMPLEMENTS_CRC32) + target_compile_definitions(${NANOCLR_PROJECT_NAME}.elf PUBLIC -DWP_IMPLEMENTS_CRC32) +endif() + +# set compiler definition regarding inclusion of trace messages and checks on CLR +if(NF_PLATFORM_NO_CLR_TRACE) + target_compile_definitions(${TARGET} PUBLIC -DPLATFORM_NO_CLR_TRACE=1) +endif() + +# set compiler definition regarding CLR IL inlining +if(NF_CLR_NO_IL_INLINE) + target_compile_definitions(${TARGET} PUBLIC -DNANOCLR_NO_IL_INLINE=1) +endif() + +# set extra linker flags for DEBUG +set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS_DEBUG "") + +# set extra linker flags for RELEASE +#set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS_RELEASE " -flto ") + +# add linker flags set with traditional CMAKE_EXE_LINKER_FLAGS +set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ${CMAKE_EXE_LINKER_FLAGS}) + +# add linker flags to generate map file +set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS " -Wl,-Map=${PROJECT_BINARY_DIR}/${NANOCLR_PROJECT_NAME}.map") +# Verbose linking, uncomment to enable +#set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS " -Wl,--verbose ") + +# add dependency for networking +if(USE_SECURITY_MBEDTLS_OPTION) + add_dependencies(${NANOCLR_PROJECT_NAME}.elf NetworkLib) +endif() + +# Create bin file from elf +set(GEN_ESP32_BIN_PATH ${EXECUTABLE_OUTPUT_PATH} ) +set(NANOCLR_BIN_FILE ${GEN_ESP32_BIN_PATH}/${NANOCLR_PROJECT_NAME}.bin) +set(ESPTOOL_PY_FILE ${ESP32_IDF_PATH}/components/esptool_py/esptool/esptool.py ) +set(ESPTOOL_PY_FLAGS "--chip esp32 elf2image --flash_mode \"dio\" --flash_freq \"40m\" --flash_size \"4MB\" " ) +set(GEN_ESP32PART_PY_FILE ${ESP32_IDF_PATH}/components/partition_table/gen_esp32part.py ) + +add_custom_command( TARGET ${NANOCLR_PROJECT_NAME}.elf POST_BUILD + COMMAND ${ESPTOOL_PY_FILE} ${ESPTOOL_PY_FLAGS} -o ${NANOCLR_BIN_FILE} ${EXECUTABLE_OUTPUT_PATH}/${NANOCLR_PROJECT_NAME}.elf + COMMENT "Generate nanoClr BIN file for deployment" ) + +# # Create partition table +add_custom_command( TARGET ${NANOCLR_PROJECT_NAME}.elf POST_BUILD + COMMAND ${GEN_ESP32PART_PY_FILE} --verify ${PROJECT_SOURCE_DIR}/targets/FreeRTOS_ESP32/ESP32_WROOM_32/IDF/partitions_nanoclr_16mb.csv ${GEN_ESP32_BIN_PATH}/partitions_16mb.bin + COMMAND ${GEN_ESP32PART_PY_FILE} --verify ${PROJECT_SOURCE_DIR}/targets/FreeRTOS_ESP32/ESP32_WROOM_32/IDF/partitions_nanoclr_8mb.csv ${GEN_ESP32_BIN_PATH}/partitions_8mb.bin + COMMAND ${GEN_ESP32PART_PY_FILE} --verify ${PROJECT_SOURCE_DIR}/targets/FreeRTOS_ESP32/ESP32_WROOM_32/IDF/partitions_nanoclr_4mb.csv ${GEN_ESP32_BIN_PATH}/partitions_4mb.bin + COMMAND ${GEN_ESP32PART_PY_FILE} --verify ${PROJECT_SOURCE_DIR}/targets/FreeRTOS_ESP32/ESP32_WROOM_32/IDF/partitions_nanoclr_2mb.csv ${GEN_ESP32_BIN_PATH}/partitions_2mb.bin + COMMENT "Generate Esp32 Partition tables for 2MB, 4MB, 8MB and 16MB flash" ) + +# list partition table +add_custom_command( TARGET ${NANOCLR_PROJECT_NAME}.elf POST_BUILD + COMMAND ${GEN_ESP32PART_PY_FILE} ${GEN_ESP32_BIN_PATH}/partitions_4mb.bin + COMMENT "List flash 4Mb Esp32 Partition tables" ) + +#message("CMAKE_CXX_FLAGS:${CMAKE_CXX_FLAGS}" ) +#message("CMAKE_EXE_LINKER_FLAGS:${CMAKE_EXE_LINKER_FLAGS}" ) +#message("CMAKE_EXE_LINKER_FLAGS_DEBUG:${CMAKE_EXE_LINKER_FLAGS_DEBUG}" ) +#message("CMAKE_EXE_LINKER_FLAGS_DEBUG_INIT:${CMAKE_EXE_LINKER_FLAGS_DEBUG_INIT}" ) +#message("CMAKE_CXX_LINK_EXECUTABLE:${CMAKE_CXX_LINK_EXECUTABLE}" ) +#message("CMAKE_C_LINK_EXECUTABLE:${CMAKE_C_LINK_EXECUTABLE}" ) +#message("FLAGS:${FLAGS}" ) diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/CopyLibs.cmd b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/CopyLibs.cmd new file mode 100644 index 00000000..c262f6e3 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/CopyLibs.cmd @@ -0,0 +1,89 @@ +echo off + +SET idfVer=3.3 +SET targetDir=c:\Esp32_tools\libs-v%idfVer% + +echo Copy IDF libraries to %targetDir% + +rmdir /S /Q %targetDir% +mkdir %targetDir% + + +copy /Y build\bootloader\bootloader.bin %targetDir% + +copy /Y build\app_trace\libapp_trace.a %targetDir% +copy /Y build\app_update\libapp_update.a %targetDir% +copy /Y build\asio\libasio.a %targetDir% +copy /Y build\aws_iot\libaws_iot.a %targetDir% +copy /Y build\bootloader\bootloader_support\libbootloader_support.a %targetDir% + +copy /Y build\bt\libbt.a %targetDir% + +copy /Y build\coap\libcoap.a %targetDir% +copy /Y build\console\libconsole.a %targetDir% + +copy /Y build\cxx\libcxx.a %targetDir% +copy /Y build\driver\libdriver.a %targetDir% +copy /Y build\efuse\libefuse.a %targetDir% +copy /Y build\esp-tls\libesp-tls.a %targetDir% +copy /Y build\esp32\libesp32.a %targetDir% + +copy /Y build\esp_adc_cal\libesp_adc_cal.a %targetDir% +copy /Y build\esp_event\libesp_event.a %targetDir% + +copy /Y build\esp_http_client\libesp_http_client.a %targetDir% +copy /Y build\esp_http_server\libesp_http_server.a %targetDir% + +copy /Y build\esp_https_ota\libesp_https_ota.a %targetDir% +copy /Y build\esp_https_server\libesp_https_server.a %targetDir% +copy /Y build\esp_ringbuf\libesp_ringbuf.a %targetDir% +copy /Y build\espcoredump\libespcoredump.a %targetDir% +copy /Y build\ethernet\libethernet.a %targetDir% +copy /Y build\expat\libexpat.a %targetDir% +copy /Y build\fatfs\libfatfs.a %targetDir% +copy /Y build\freemodbus\libfreemodbus.a %targetDir% +copy /Y build\freertos\libfreertos.a %targetDir% +copy /Y build\heap\libheap.a %targetDir% +copy /Y build\idf_test\libidf_test.a %targetDir% +copy /Y build\jsmn\libjsmn.a %targetDir% +copy /Y build\json\libjson.a %targetDir% +copy /Y build\libsodium\liblibsodium.a %targetDir% +copy /Y build\log\liblog.a %targetDir% + +copy /Y build\main\libmain.a %targetDir% +copy /Y build\lwip\liblwip.a %targetDir% +copy /Y build\mbedtls\libmbedtls.a %targetDir% +copy /Y build\mdns\libmdns.a %targetDir% +copy /Y build\micro-ecc\libmicro-ecc.a %targetDir% +copy /Y build\mqtt\libmqtt.a %targetDir% + +copy /Y build\newlib\libnewlib.a %targetDir% + +copy /Y build\nghttp\libnghttp.a %targetDir% +copy /Y build\nvs_flash\libnvs_flash.a %targetDir% +copy /Y build\openssl\libopenssl.a %targetDir% + +copy /Y build\protobuf-c\libprotobuf-c.a %targetDir% +copy /Y build\protocomm\libprotocomm.a %targetDir% +copy /Y build\pthread\libpthread.a %targetDir% +copy /Y build\sdmmc\libsdmmc.a %targetDir% +copy /Y build\smartconfig_ack\libsmartconfig_ack.a %targetDir% +copy /Y build\soc\libsoc.a %targetDir% +copy /Y build\spi_flash\libspi_flash.a %targetDir% +copy /Y build\spiffs\libspiffs.a %targetDir% + +copy /Y build\tcp_transport\libtcp_transport.a %targetDir% +copy /Y build\tcpip_adapter\libtcpip_adapter.a %targetDir% +copy /Y build\ulp\libulp.a %targetDir% +copy /Y build\unity\libunity.a %targetDir% +copy /Y build\vfs\libvfs.a %targetDir% +copy /Y build\wear_levelling\libwear_levelling.a %targetDir% +copy /Y build\wifi_provisioning\libwifi_provisioning.a %targetDir% +copy /Y build\wpa_supplicant\libwpa_supplicant.a %targetDir% +copy /Y build\xtensa-debug-module\libxtensa-debug-module.a %targetDir% + + + + + + diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/IDF/CMakeLists.txt b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/IDF/CMakeLists.txt new file mode 100644 index 00000000..957e1e68 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/IDF/CMakeLists.txt @@ -0,0 +1,380 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + + +list(APPEND COMPONENT_PATH "${ESP32_IDF_PATH}/components") +#append ESP32 IDF include paths + +list(APPEND IDF_SDKCONFIG "${ESP32_IDF_PATH}/examples/get-started/blink/build/include") + +list(APPEND TARGET_ESP32_IDF_INCLUDES "${CMAKE_CURRENT_SOURCE_DIR}") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/tcpip_adapter/include") + +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/lwip/lwip/src/include/lwip") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/lwip/include/lwip/port") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/lwip/lwip/src") + +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/lwip/lwip/src/include/posix") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/lwip/include/apps") + + +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/newlib/platform_include") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/driver/include") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/driver/include/driver") + +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/esp32/include") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/esp32/include/rom") + +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/esp_event/include") + +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/spi_flash/include") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/nvs_flash/include") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/Log/include") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/Ethernet/include") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/wpa_supplicant/include") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/wpa_supplicant/port/include") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/freertos/include") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/freertos/include/freertos") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/soc/include") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/soc/esp32/include") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/heap/include") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/app_trace/include") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/bt/include") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/wear_levelling/include") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/esp_ringbuf/include") + +# list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/mbedtls/port/include" "${COMPONENT_PATH}/mbedtls/mbedtls/include" ) + +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/nghttp/port/include") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/nghttp/nghttp2/lib/includes") + +# list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/openssl/include") + +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/app_update/include") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/vfs/include") + +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/micro-ecc/micro-ecc") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/xtensa-debug-module/include") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/ulp/include") + +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/ulp/include") + +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/spiffs/include") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/fatfs/src") + +#sdkconfig reference +list(APPEND TARGET_ESP32_IDF_INCLUDES "${ESP32_IDF_PATH}/examples/get-started/blink/build/include") + + +list( APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/bootloader_support/include" ) +list( APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/bootloader_support/include" ) + +set( IDF_EXAMPLE_BASE "${ESP32_IDF_PATH}/examples/get-started/blink/build" CACHE INTERNAL "make global") +set( IDF_NANOFRAMEWORK_BASE "${ESP32_IDF_PATH}/examples/get-started/blink/build" CACHE INTERNAL "make global") + +# library paths for Example project +set( PROJECT_LINK_LIBS "" ) + +# find_library( LIB_APPTRACE_PATH +# NAMES libapp_trace.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/app_trace" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_APPTRACE_PATH}) + +# find_library( LIB_APPUPDATE_PATH +# NAMES libapp_update.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/app_update" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_APPUPDATE_PATH}) + +# find_library( LIB_AWS_IOT_PATH +# NAMES libaws_iot.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/aws_iot" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_AWS_IOT_PATH}) + +# find_library( LIB_BOOTLOADER_SUPPORT_PATH +# NAMES libbootloader_support.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/bootloader_support" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_BOOTLOADER_SUPPORT_PATH}) + +# find_library( LIB_BT_PATH +# NAMES libbt.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/bt" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_BT_PATH}) + +# find_library( LIB_COAP_PATH +# NAMES libcoap.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/coap" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_COAP_PATH}) + +# find_library( LIB_CONSOLE_PATH +# NAMES libconsole.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/console" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_CONSOLE_PATH}) + +# find_library( LIB_CXX_PATH +# NAMES libcxx.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/cxx" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_CXX_PATH}) + +# find_library( LIB_DRIVER_PATH +# NAMES libdriver.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/driver" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_DRIVER_PATH}) + +# find_library( LIB_ESP32_PATH +# NAMES libesp32.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/esp32" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_ESP32_PATH}) + +# find_library( LIB_ETHERNET_PATH +# NAMES libethernet.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/ethernet" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_ETHERNET_PATH}) + +# find_library( LIB_EXPAT_PATH +# NAMES libexpat.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/expat" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_EXPAT_PATH}) + +# find_library( LIB_FATFS_PATH +# NAMES libfatfs.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/fatfs" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_FATFS_PATH}) + +# find_library( LIB_FREERTOS_PATH +# NAMES libfreertos.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/freertos" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_FREERTOS_PATH}) + +# find_library( LIB_HEAP_PATH +# NAMES libheap.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/heap" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_HEAP_PATH}) + +# find_library( LIB_JSMN_PATH +# NAMES libjsmn.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/jsmn" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_JSMN_PATH}) + +# find_library( LIB_JSON_PATH +# NAMES libjson.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/json" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_JSON_PATH}) + +# find_library( LIB_SODIUM_PATH +# NAMES liblibsodium.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/libsodium" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_SODIUM_PATH}) + +# find_library( LIB_LOG_PATH +# NAMES liblog.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/log" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_LOG_PATH}) + +# find_library( LIB_LWIP_PATH +# NAMES liblwip.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/lwip" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_LWIP_PATH}) + +# find_library( LIB_MBEDTLS_PATH +# NAMES libmbedtls.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/mbedtls" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_MBEDTLS_PATH}) + +# find_library( LIB_MDNS_PATH +# NAMES libmdns.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/mdns" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_MDNS_PATH}) + +# find_library( LIB_MICROECC_PATH +# NAMES libmicro-ecc.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/micro-ecc" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_MICROECC_PATH}) + +# find_library( LIB_NEWLIB_PATH +# NAMES libnewlib.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/newlib" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_NEWLIB_PATH}) + +# find_library( LIB_NGHTTP_PATH +# NAMES libnghttp.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/nghttp" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_NGHTTP_PATH}) + +# find_library( LIB_NVSFLASH_PATH +# NAMES libnvs_flash.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/nvs_flash" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_NVSFLASH_PATH}) + +# find_library( LIB_OPENSSL_PATH +# NAMES libopenssl.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/openssl" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_OPENSSL_PATH}) + +# find_library( LIB_SDMMC_PATH +# NAMES libsdmmc.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/sdmmc" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_SDMMC_PATH}) + +# find_library( LIB_SOC_PATH +# NAMES libsoc.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/soc" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_SOC_PATH}) + +# find_library( LIB_SPIFLASH_PATH +# NAMES libspi_flash.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/spi_flash" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_SPIFLASH_PATH}) + +# find_library( LIB_TCPIPADAPTER_PATH +# NAMES libtcpip_adapter.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/tcpip_adapter" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_TCPIPADAPTER_PATH}) + +# find_library( LIB_ULP_PATH +# NAMES libulp.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/ulp" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_ULP_PATH}) + +# find_library( LIB_VFS_PATH +# NAMES libvfs.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/vfs" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_VFS_PATH}) + +# find_library( LIB_WEAR_PATH +# NAMES libwear_levelling.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/wear_levelling" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_WEAR_PATH}) + +# find_library( LIB_WPA_PATH +# NAMES libwpa_supplicant.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/wpa_supplicant" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_WPA_PATH}) + +# find_library( LIB_PTHREAD_PATH +# NAMES libpthread.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/pthread" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_PTHREAD_PATH}) + + +# find_library( LIB_DEBUG_PATH +# NAMES libxtensa-debug-module.a +# HINTS "${IDF_NANOFRAMEWORK_BASE}/xtensa-debug-module" +# NO_CMAKE_FIND_ROOT_PATH ) +# list(APPEND PROJECT_LINK_LIBS ${LIB_DEBUG_PATH}) + + +# Path to pre compiled Libs + +set( DIRECT_LINK_LIBS "" ) +set( DIRECT_LINK_PATH "${ESP32_LIBS_PATH}" ) +#message( "direct link path:${DIRECT_LINK_PATH}") + +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libapp_trace.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libapp_update.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libasio.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libaws_iot.a) +#list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libbootloader_support.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libbt.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libcoap.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libconsole.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libcxx.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libdriver.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libefuse.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libesp-tls.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libesp32.a) + +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libesp_adc_cal.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libesp_event.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libesp_http_client.a) + +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libesp_http_server.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libesp_https_ota.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libesp_https_server.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libesp_ringbuf.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libespcoredump.a) + +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libethernet.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libexpat.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libfatfs.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libfreemodbus.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libfreertos.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libheap.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libidf_test.a ) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libjsmn.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libjson.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/liblibsodium.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/liblog.a) +# list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libmbedtls.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libmdns.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libmicro-ecc.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libmqtt.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libnewlib.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libnghttp.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libnvs_flash.a) +# list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libopenssl.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libprotobuf-c.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libprotocomm.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libpthread.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libsdmmc.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libsmartconfig_ack.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libsoc.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libspi_flash.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libspiffs.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libtcp_transport.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libtcpip_adapter.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libulp.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libunity.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libvfs.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libwear_levelling.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libwifi_provisioning.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libwpa_supplicant.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libxtensa-debug-module.a) +list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/libbootloader_support.a) + +# Lwip lib is built separately +#list(APPEND DIRECT_LINK_LIBS ${DIRECT_LINK_PATH}/liblwip.a) + +set(PROJECT_LINK_LIBS ${DIRECT_LINK_LIBS}) + +set(TARGET_ESP32_IDF_INCLUDES ${TARGET_ESP32_IDF_INCLUDES} CACHE INTERNAL "make global") +set(PROJECT_LINK_LIBS ${PROJECT_LINK_LIBS} CACHE INTERNAL "make global") +#set(DIRECT_LINK_LIBS ${DIRECT_LINK_LIBS} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/IDF/partitions_nanoclr_16mb.csv b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/IDF/partitions_nanoclr_16mb.csv new file mode 100644 index 00000000..872173bf --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/IDF/partitions_nanoclr_16mb.csv @@ -0,0 +1,13 @@ +# Name, Type, SubType, Offset, Size +# Note: if you change the phy_init or app partition offset, make sure to change the offset in Kconfig.projbuild +############################################################################################################################### +# if you change the partitions here, make sure to update the BlockRegions array in the device BlockStorage configuration file # +############################################################################################################################### +nvs, data, nvs, 0x9000, 0x6000, +phy_init, data, phy, 0xf000, 0x1000, +# Factory area for NanoCLR - 1536KB +factory, 0, 0, 0x10000, 0x180000, +# Deployment area for Managed code 1769K +deploy, data, 0x84, 0x190000, 0x1B0000, +# Config data for Network, Wireless, certificates, user data 2MB +config, data, spiffs, 0x340000, 0x200000, diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/IDF/partitions_nanoclr_2mb.csv b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/IDF/partitions_nanoclr_2mb.csv new file mode 100644 index 00000000..5008399e --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/IDF/partitions_nanoclr_2mb.csv @@ -0,0 +1,13 @@ +# Name, Type, SubType, Offset, Size +# Note: if you change the phy_init or app partition offset, make sure to change the offset in Kconfig.projbuild +############################################################################################################################### +# if you change the partitions here, make sure to update the BlockRegions array in the device BlockStorage configuration file # +############################################################################################################################### +nvs, data, nvs, 0x9000, 0x4000, +phy_init, data, phy, 0xf000, 0x1000, +# Factory area for NanoCLR - 1088KB +factory, 0, 0, 0x10000, 0x110000, +# Deployment area for Managed code 393K +deploy, data, 0x84, 0x120000, 0x60000, +# Config data for Network, Wireless, certificates, user data 64K +config, data, spiffs, 0x180000, 0x10000, diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/IDF/partitions_nanoclr_4mb.csv b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/IDF/partitions_nanoclr_4mb.csv new file mode 100644 index 00000000..3bcfdd51 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/IDF/partitions_nanoclr_4mb.csv @@ -0,0 +1,13 @@ +# Name, Type, SubType, Offset, Size +# Note: if you change the phy_init or app partition offset, make sure to change the offset in Kconfig.projbuild +############################################################################################################################### +# if you change the partitions here, make sure to update the BlockRegions array in the device BlockStorage configuration file # +############################################################################################################################### +nvs, data, nvs, 0x9000, 0x6000, +phy_init, data, phy, 0xf000, 0x1000, +# Factory area for NanoCLR - 1536KB +factory, 0, 0, 0x10000, 0x180000, +# Deployment area for Managed code 1769K +deploy, data, 0x84, 0x190000, 0x1B0000, +# Config data for Network, Wireless, certificates, user data 256K +config, data, spiffs, 0x340000, 0x40000, diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/IDF/partitions_nanoclr_8mb.csv b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/IDF/partitions_nanoclr_8mb.csv new file mode 100644 index 00000000..8814230f --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/IDF/partitions_nanoclr_8mb.csv @@ -0,0 +1,13 @@ +# Name, Type, SubType, Offset, Size +# Note: if you change the phy_init or app partition offset, make sure to change the offset in Kconfig.projbuild +############################################################################################################################### +# if you change the partitions here, make sure to update the BlockRegions array in the device BlockStorage configuration file # +############################################################################################################################### +nvs, data, nvs, 0x9000, 0x6000, +phy_init, data, phy, 0xf000, 0x1000, +# Factory area for NanoCLR - 1536KB +factory, 0, 0, 0x10000, 0x180000, +# Deployment area for Managed code 1769K +deploy, data, 0x84, 0x190000, 0x1B0000, +# Config data for Network, Wireless, certificates, user data 1Mb +config, data, spiffs, 0x340000, 0x100000, diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/CLR_Startup_Thread.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/CLR_Startup_Thread.h new file mode 100644 index 00000000..3c394ef4 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/CLR_Startup_Thread.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _CLRSTARTUPTHREAD_ +#define _CLRSTARTUPTHREAD_ + +// declaration of RTOS thread +void CLRStartupThread(void const * argument); + +#endif //_CLRSTARTUPTHREAD_ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/Esp32_DeviceMapping.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/Esp32_DeviceMapping.h new file mode 100644 index 00000000..c3eacf54 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/Esp32_DeviceMapping.h @@ -0,0 +1,36 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +// +// Header file for ESP32 device pin mnapping +// + +#ifndef _ESP32_DEVICEMAPPING_ +#define _ESP32_DEVICEMAPPING_ + +// Default I2C gpio pins +#define I2C1_DATA 18 +#define I2C1_CLOCK 19 +#define I2C2_DATA 25 +#define I2C2_CLOCK 26 + +enum Esp32_MapDeviceType +{ + DEV_TYPE_GPIO, + DEV_TYPE_SPI, + DEV_TYPE_I2C, + DEV_TYPE_SERIAL, + DEV_TYPE_LED_PWM, + DEV_TYPE_ADC, + DEV_TYPE_DAC, + DEV_TYPE_MAX, +}; + +int Esp32_GetMappedDevicePins(Esp32_MapDeviceType DevType, int DevNumber, int PinIndex); +int Esp32_GetMappedDevicePinsWithFunction(uint32_t alternateFunction); + +void Esp32_SetMappedDevicePins( uint8_t pin, int32_t alternateFunction ); + +#endif //_ESP32_DEVICEMAPPING_ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/LaunchCLR.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/LaunchCLR.h new file mode 100644 index 00000000..15e319ef --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/LaunchCLR.h @@ -0,0 +1,13 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _LAUNCHCLR_H_ +#define _LAUNCHCLR_H_ + +void LaunchCLR(uint32_t address); +bool CheckValidCLRImage(uint32_t address); + +#endif //_LAUNCHCLR_H_ + diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/TargetPAL_BlockStorage.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/TargetPAL_BlockStorage.h new file mode 100644 index 00000000..805c2e32 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/TargetPAL_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_PAL_BLOCKSTORAGE_H_ +#define _TARGET_PAL_BLOCKSTORAGE_H_ 1 + +#include + +#endif // _TARGET_PAL_BLOCKSTORAGE_H_ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/Target_BlockStorage_Esp32FlashDriver.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/Target_BlockStorage_Esp32FlashDriver.h new file mode 100644 index 00000000..4fa13281 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/Target_BlockStorage_Esp32FlashDriver.h @@ -0,0 +1,32 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_ESP32FLASH_DRIVER_H_ +#define _TARGET_ESP32FLASH_DRIVER_H_ 1 + +#include +#include + +#include + + +//!< .NanoFramework deploy partition +#define ESP_PARTITION_SUBTYPE_DATA_NANOCLR (esp_partition_subtype_t)0x84 +//--// + +bool Esp32FlashDriver_InitializeDevice(void*); +bool Esp32FlashDriver_UninitializeDevice(void*); +DeviceBlockInfo* Esp32FlashDriver_GetDeviceInfo(void*); +bool Esp32FlashDriver_Read(void*, ByteAddress startAddress, unsigned int numBytes, unsigned char* buffer); +bool Esp32FlashDriver_Write(void*, ByteAddress startAddress, unsigned int numBytes, unsigned char* buffer, bool readModifyWrite); +bool Esp32FlashDriver_IsBlockErased(void*, ByteAddress blockAddress, unsigned int length); +bool Esp32FlashDriver_EraseBlock(void*, ByteAddress address); +void Esp32FlashDriver_SetPowerState(void*, unsigned int state); +bool Esp32FlashDriver_GetMemoryMappedAddress(void*, unsigned int blockRegionIndex, unsigned int blockRangeIndex, unsigned int* address); + +extern const DRAM_ATTR esp_partition_t * g_pFlashDriver_partition; +extern const void * g_esp32_flash_start_ptr; + +#endif //_TARGET_ESP32FLASH_DRIVER_H_ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/Target_Windows_Storage.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/Target_Windows_Storage.h new file mode 100644 index 00000000..888c34fe --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/Target_Windows_Storage.h @@ -0,0 +1,9 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_WINDOWS_STORAGE_H_ +#define _TARGET_WINDOWS_STORAGE_H_ 1 + +#endif //_TARGET_WINDOWS_STORAGE_H_ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/WireProtocol_ReceiverThread.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/WireProtocol_ReceiverThread.h new file mode 100644 index 00000000..c6b75c3e --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/WireProtocol_ReceiverThread.h @@ -0,0 +1,13 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIREPROTOCOL_RECEIVERTHREAD_H_ +#define _WIREPROTOCOL_RECEIVERTHREAD_H_ + +// declaration of RTOS thread +void ReceiverThread(void const * argument); + +#endif //_WIREPROTOCOL_RECEIVERTHREAD_H_ + diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/esp32_os.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/esp32_os.h new file mode 100644 index 00000000..0dfba6f5 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/esp32_os.h @@ -0,0 +1,46 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _ESP32_OS_H_ +#define _ESP32_OS_H_ + +#include +#include +#include +#include + +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "freertos/timers.h" +#include "freertos/event_groups.h" +#include "esp_system.h" +#include "esp_attr.h" +#include "esp_log.h" +#include "task.h" +#include "nvs_flash.h" + +// TODO ONly with network +#include "esp_wifi.h" +#include "esp_wpa2.h" +#include "esp_eth.h" +#include "esp_event_loop.h" + +#include "esp_timer.h" + +#include "spi_master.h" +#include "gpio.h" +#include "i2c.h" +#include "uart.h" +#include "ledc.h" +#include "adc.h" +#include "dac.h" +#include "timer.h" +#include "esp_spiffs.h" +#include "pcnt.h" + +// Uncomment to support Ethernet +//#define ESP32_ETHERNET_SUPPORT 1 + +#endif // _ESP32_OS_H_ \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/platform_target_capabilities.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/platform_target_capabilities.h new file mode 100644 index 00000000..e96158da --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/platform_target_capabilities.h @@ -0,0 +1,25 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _PLATFORM_TARGET_CAPABILITIES_H_ +#define _PLATFORM_TARGET_CAPABILITIES_H_ 1 + +/////////////////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH nanoFramework.Tools.Debugger.Esp32.TargetCapabilities (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////////////////////// + +#ifdef __cplusplus +extern "C" { +#endif + +// this platform doesn't have any declared capabilities + +// the targets of this platform don't have any declared capabilities + +#ifdef __cplusplus +} +#endif + +#endif //_PLATFORM_TARGET_CAPABILITIES_H_ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/targetHAL.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/targetHAL.h new file mode 100644 index 00000000..d7726299 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/targetHAL.h @@ -0,0 +1,77 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_HAL_H_ +#define _TARGET_HAL_H_ + +#include +#include + +// global mutex protecting the internal state of the interpreter, including event flags +extern portMUX_TYPE globalLockMutex; +#define GLOBAL_LOCK() portENTER_CRITICAL(&globalLockMutex); +#define GLOBAL_UNLOCK() portEXIT_CRITICAL(&globalLockMutex); + +// platform dependent delay +#define PLATFORM_DELAY(milliSecs) vTaskDelay(milliSecs); + +// Definitions for Sockets/Network +#define GLOBAL_LOCK_SOCKETS(x) + +#define PLATFORM_DEPENDENT__SOCKETS_MAX_COUNT 16 + +#define LPCSTR const char* + + +// these macros are to be used at entry/exit of native interrupt handlers +#define NATIVE_INTERRUPT_START SystemState_SetNoLock( SYSTEM_STATE_ISR ); \ + SystemState_SetNoLock( SYSTEM_STATE_NO_CONTINUATIONS ); +#define NATIVE_INTERRUPT_END SystemState_ClearNoLock( SYSTEM_STATE_NO_CONTINUATIONS ); \ + SystemState_ClearNoLock( SYSTEM_STATE_ISR ); + + +// TODO: Doesn't seem to be defined anywhere, used clr corlib math +#define INT32 int32_t +#define TRUE true +#define FALSE false + +#if !defined(BUILD_RTM) + +#define HARD_BREAKPOINT() HARD_Breakpoint() + +// #if defined(_DEBUG) +// #define DEBUG_HARD_BREAKPOINT() HARD_Breakpoint() +// #else +// #define DEBUG_HARD_BREAKPOINT() +// #endif + +// #else + +// #define HARD_BREAKPOINT() +// #define DEBUG_HARD_BREAKPOINT() + +#endif // !defined(BUILD_RTM) + +#define NANOCLR_STOP() HARD_BREAKPOINT() + + +///////////////////////////////////////////////////////////////////////////////////////////////////// +// DEBUGGER HELPER // +// The line below is meant to be used as helper on checking that the execution engine is running. // +// This can be inferred by checking if Events_WaitForEvents loop is running. // +// The implementation should is to be provided by each target at target_common.h.in // +//////////////////////////////////////////////////////////////////////////////////////////////////// +#if defined(BUILD_RTM) + #define EVENTS_HEART_BEAT +#else + #ifndef EVENTS_HEART_BEAT + #define EVENTS_HEART_BEAT __asm__ __volatile__ ("nop") + #endif // EVENTS_HEART_BEAT +#endif + +extern int HeapBegin; +extern int HeapEnd; + +#endif //_TARGET_HAL_H_ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/targetHAL_Power.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/targetHAL_Power.h new file mode 100644 index 00000000..93af4528 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/targetHAL_Power.h @@ -0,0 +1,21 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_HAL_POWER_H_ +#define _TARGET_HAL_POWER_H_ 1 + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef __cplusplus +} +#endif + +#endif //_TARGET_HAL_POWER_H_ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/targetHAL_Time.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/targetHAL_Time.h new file mode 100644 index 00000000..e66b86ce --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/targetHAL_Time.h @@ -0,0 +1,17 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_HAL_TIME_H_ +#define _TARGET_HAL_TIME_H_ 1 + +#include +#include + +#include + +#define HAL_Time_CurrentSysTicks xTaskGetTickCount +#define ESP32_TICKS_PER_MS(x) ((x * (uint64_t)configTICK_RATE_HZ) / 1000) + +#endif //_TARGET_HAL_TIME_H_ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/targetPAL.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/targetPAL.h new file mode 100644 index 00000000..42d1f494 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/targetPAL.h @@ -0,0 +1,11 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_H_ +#define _TARGETPAL_H_ + + + +#endif // _TARGETPAL_H_ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/targetPAL_Time.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/targetPAL_Time.h new file mode 100644 index 00000000..e8383973 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Include/targetPAL_Time.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_PAL_TIME_H_ +#define _TARGET_PAL_TIME_H_ 1 + +#include + + +#endif //_TARGET_PAL_TIME_H_ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Lwip/CMakeLists.txt b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Lwip/CMakeLists.txt new file mode 100644 index 00000000..e5a99638 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Lwip/CMakeLists.txt @@ -0,0 +1,50 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# We build Lwip library from sources so as to include patches required for nanoFramework + +list(APPEND COMPONENT_PATH "${ESP32_IDF_PATH}/components") + +# Add current source path for lwipopts.h and sdkconfig.h +list(APPEND TARGET_ESP32_IDF_INCLUDES "${CMAKE_CURRENT_SOURCE_DIR}") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/lwip/lwip/src/include") +list(APPEND TARGET_ESP32_IDF_INCLUDES "${COMPONENT_PATH}/lwip/port/esp32/include") + + + +# Lwip Library +list( APPEND TARGET_LWIP_API_SOURCES "${COMPONENT_PATH}/lwip/lwip/src/api/api_lib.c" ) +list( APPEND TARGET_LWIP_API_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nf_api_msg.c" ) +list( APPEND TARGET_LWIP_API_SOURCES "${COMPONENT_PATH}/lwip/lwip/src/api/err.c" ) +list( APPEND TARGET_LWIP_API_SOURCES "${COMPONENT_PATH}/lwip/lwip/src/api/netbuf.c" ) +list( APPEND TARGET_LWIP_API_SOURCES "${COMPONENT_PATH}/lwip/lwip/src/api/netdb.c" ) +list( APPEND TARGET_LWIP_API_SOURCES "${COMPONENT_PATH}/lwip/lwip/src/api/netifapi.c" ) +list( APPEND TARGET_LWIP_API_SOURCES "${COMPONENT_PATH}/lwip/lwip/src/netif/ppp/pppapi.c" ) +list( APPEND TARGET_LWIP_API_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nf_sockets.c" ) +list( APPEND TARGET_LWIP_API_SOURCES "${COMPONENT_PATH}/lwip/lwip/src/api/tcpip.c" ) + +file( GLOB TARGET_LWIP_APPS1_SOURCES "${COMPONENT_PATH}/lwip/lwip/src/apps/*.c" ) +file( GLOB TARGET_LWIP_APPS2_SOURCES "${COMPONENT_PATH}/lwip/lwip/src/apps/sntp/*.c" ) +file( GLOB TARGET_LWIP_APPS3_SOURCES "${COMPONENT_PATH}/lwip/lwip/src/apps/ping/*.c" ) +file( GLOB TARGET_LWIP_APPS4_SOURCES "${COMPONENT_PATH}/lwip/apps/dhcpserver/dhcpserver.c" ) +file( GLOB TARGET_LWIP_CORE_SOURCES "${COMPONENT_PATH}/lwip/lwip/src/core/*.c" ) +file( GLOB TARGET_LWIP_CORE_IP4_SOURCES "${COMPONENT_PATH}/lwip/lwip/src/core/ipv4/*.c" ) +file( GLOB TARGET_LWIP_CORE_IP6_SOURCES "${COMPONENT_PATH}/lwip/lwip/src/core/ipv6/*.c" ) +file( GLOB TARGET_LWIP_NETIF_SOURCES "${COMPONENT_PATH}/lwip/lwip/src/netif/*.c" ) + +list(APPEND TARGET_LWIP_PORT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nf_sys_arch.c" ) +list(APPEND TARGET_LWIP_PORT_SOURCES "${COMPONENT_PATH}/lwip/port/esp32/netif/ethernetif.c" ) +list(APPEND TARGET_LWIP_PORT_SOURCES "${COMPONENT_PATH}/lwip/port/esp32/netif/wlanif.c" ) +list(APPEND TARGET_LWIP_PORT_SOURCES "${COMPONENT_PATH}/lwip/port/esp32/debug/lwip_debug.c" ) +list(APPEND TARGET_LWIP_PORT_SOURCES "${COMPONENT_PATH}/lwip/port/esp32/vfs_lwip.c" ) + +list(APPEND TARGET_LWIP_SOURCES ${TARGET_LWIP_API_SOURCES} ${TARGET_LWIP_APPS1_SOURCES} ${TARGET_LWIP_APPS2_SOURCES} ${TARGET_LWIP_APPS3_SOURCES} ${TARGET_LWIP_APPS4_SOURCES} ${TARGET_LWIP_CORE_SOURCES} ${TARGET_LWIP_CORE_IP4_SOURCES} ${TARGET_LWIP_CORE_IP6_SOURCES} ${TARGET_LWIP_NETIF_SOURCES} ${TARGET_LWIP_PORT_SOURCES} ) +#list( APPEND CMAKE_C_FLAGS " -Wno-address -Wno-unused-variable -Wno-unused-but-set-variable " ) +#add_library( lwip STATIC ${TARGET_LWIP_SOURCES} ) +#target_include_directories( lwip PUBLIC ${TARGET_ESP32_IDF_INCLUDES} ) + +# make var global +set(TARGET_LWIP_SOURCES ${TARGET_LWIP_SOURCES} CACHE INTERNAL "make global") +set(TARGET_ESP32_IDF_INCLUDES ${TARGET_ESP32_IDF_INCLUDES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Lwip/asdkconfig.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Lwip/asdkconfig.h new file mode 100644 index 00000000..de06e3dd --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Lwip/asdkconfig.h @@ -0,0 +1,203 @@ +/* + * + * Automatically generated file; DO NOT EDIT. + * Espressif IoT Development Framework Configuration + * + */ +#define CONFIG_ESP32_PHY_MAX_TX_POWER 20 +#define CONFIG_TRACEMEM_RESERVE_DRAM 0x0 +#define CONFIG_FREERTOS_MAX_TASK_NAME_LEN 16 +#define CONFIG_FATFS_LFN_NONE 1 +#define CONFIG_TCP_RECVMBOX_SIZE 6 +#define CONFIG_FATFS_CODEPAGE_437 1 +#define CONFIG_LWIP_ETHARP_TRUST_IP_MAC 1 +#define CONFIG_TCP_WND_DEFAULT 5744 +#define CONFIG_SPIFFS_USE_MAGIC_LENGTH 1 +#define CONFIG_IPC_TASK_STACK_SIZE 1024 +#define CONFIG_FATFS_PER_FILE_CACHE 1 +#define CONFIG_ESPTOOLPY_FLASHFREQ "40m" +#define CONFIG_BLINK_GPIO 5 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_RSA 1 +#define CONFIG_UDP_RECVMBOX_SIZE 6 +#define CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE 0 +#define CONFIG_MBEDTLS_AES_C 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED 1 +#define CONFIG_MBEDTLS_GCM_C 1 +#define CONFIG_ESPTOOLPY_FLASHSIZE "2MB" +#define CONFIG_HEAP_POISONING_DISABLED 1 +#define CONFIG_SPIFFS_CACHE_WR 1 +#define CONFIG_BROWNOUT_DET_LVL_SEL_0 1 +#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER 1 +#define CONFIG_SPIFFS_CACHE 1 +#define CONFIG_INT_WDT 1 +#define CONFIG_MBEDTLS_SSL_PROTO_TLS1 1 +#define CONFIG_MBEDTLS_ECDSA_C 1 +#define CONFIG_ESPTOOLPY_FLASHFREQ_40M 1 +#define CONFIG_LOG_BOOTLOADER_LEVEL_INFO 1 +#define CONFIG_ESPTOOLPY_FLASHSIZE_2MB 1 +#define CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE 0 +#define CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS 1 +#define CONFIG_MBEDTLS_ECDH_C 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE 1 +#define CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM 10 +#define CONFIG_MBEDTLS_SSL_ALPN 1 +#define CONFIG_MBEDTLS_PEM_WRITE_C 1 +#define CONFIG_LOG_DEFAULT_LEVEL_INFO 1 +#define CONFIG_BT_RESERVE_DRAM 0x0 +#define CONFIG_FATFS_FS_LOCK 0 +#define CONFIG_IP_LOST_TIMER_INTERVAL 120 +#define CONFIG_ESP32_PANIC_PRINT_REBOOT 1 +#define CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED 1 +#define CONFIG_CONSOLE_UART_BAUDRATE 115200 +#define CONFIG_LWIP_MAX_SOCKETS 10 +#define CONFIG_LWIP_NETIF_LOOPBACK 1 +#define CONFIG_EMAC_TASK_PRIORITY 20 +#define CONFIG_TIMER_TASK_STACK_DEPTH 2048 +#define CONFIG_TCP_MSS 1436 +#define CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED 1 +#define CONFIG_FATFS_CODEPAGE 437 +#define CONFIG_ESP32_DEFAULT_CPU_FREQ_160 1 +#define CONFIG_ULP_COPROC_RESERVE_MEM 0 +#define CONFIG_LWIP_MAX_UDP_PCBS 16 +#define CONFIG_ESPTOOLPY_BAUD 115200 +#define CONFIG_INT_WDT_CHECK_CPU1 1 +#define CONFIG_FLASHMODE_DIO 1 +#define CONFIG_ESPTOOLPY_AFTER_RESET 1 +#define CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED 1 +#define CONFIG_LWIP_DHCPS_MAX_STATION_NUM 8 +#define CONFIG_TOOLPREFIX "xtensa-esp32-elf-" +#define CONFIG_MBEDTLS_ECP_C 1 +#define CONFIG_FREERTOS_IDLE_TASK_STACKSIZE 1024 +#define CONFIG_MBEDTLS_RC4_DISABLED 1 +#define CONFIG_CONSOLE_UART_NUM 0 +#define CONFIG_ESP32_APPTRACE_LOCK_ENABLE 1 +#define CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC 1 +#define CONFIG_ESPTOOLPY_BAUD_115200B 1 +#define CONFIG_TCP_OVERSIZE_MSS 1 +#define CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS 1 +#define CONFIG_CONSOLE_UART_DEFAULT 1 +#define CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN 16384 +#define CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS 4 +#define CONFIG_ESPTOOLPY_FLASHSIZE_DETECT 1 +#define CONFIG_TIMER_TASK_STACK_SIZE 3584 +#define CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE 1 +#define CONFIG_MBEDTLS_X509_CRL_PARSE_C 1 +#define CONFIG_LWIP_DHCPS_LEASE_UNIT 60 +#define CONFIG_SPIFFS_USE_MAGIC 1 +#define CONFIG_TCPIP_TASK_STACK_SIZE 2048 +#define CONFIG_MAIN_TASK_STACK_SIZE 3584 +#define CONFIG_SPIFFS_PAGE_CHECK 1 +#define CONFIG_LWIP_MAX_ACTIVE_TCP 16 +#define CONFIG_INT_WDT_TIMEOUT_MS 300 +#define CONFIG_ESPTOOLPY_FLASHMODE "dio" +#define CONFIG_NEWLIB_STDIN_LINE_ENDING_CR 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA 1 +#define CONFIG_ESPTOOLPY_BEFORE "default_reset" +#define CONFIG_LOG_DEFAULT_LEVEL 3 +#define CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION 1 +#define CONFIG_TIMER_QUEUE_LENGTH 10 +#define CONFIG_MAKE_WARN_UNDEFINED_VARIABLES 1 +#define CONFIG_FATFS_TIMEOUT_MS 10000 +#define CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM 32 +#define CONFIG_MBEDTLS_CCM_C 1 +#define CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER 20 +#define CONFIG_ESP32_RTC_CLK_CAL_CYCLES 1024 +#define CONFIG_ESP32_WIFI_TX_BA_WIN 6 +#define CONFIG_ESP32_WIFI_NVS_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED 1 +#define CONFIG_LIBSODIUM_USE_MBEDTLS_SHA 1 +#define CONFIG_DMA_RX_BUF_NUM 10 +#define CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED 1 +#define CONFIG_TCP_SYNMAXRTX 6 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA 1 +#define CONFIG_PYTHON "python" +#define CONFIG_MBEDTLS_ECP_NIST_OPTIM 1 +#define CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1 1 +#define CONFIG_ESPTOOLPY_COMPRESSED 1 +#define CONFIG_PARTITION_TABLE_FILENAME "partitions_singleapp.csv" +#define CONFIG_TCP_SND_BUF_DEFAULT 5744 +#define CONFIG_LWIP_DHCP_MAX_NTP_SERVERS 1 +#define CONFIG_TCP_MSL 60000 +#define CONFIG_MBEDTLS_SSL_PROTO_TLS1_1 1 +#define CONFIG_LWIP_SO_REUSE_RXTOALL 1 +#define CONFIG_PARTITION_TABLE_SINGLE_APP 1 +#define CONFIG_ESP32_WIFI_RX_BA_WIN 6 +#define CONFIG_MBEDTLS_X509_CSR_PARSE_C 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA 1 +#define CONFIG_LWIP_DHCP_DOES_ARP_CHECK 1 +#define CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE 2048 +#define CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY 2000 +#define CONFIG_BROWNOUT_DET_LVL 0 +#define CONFIG_MBEDTLS_PEM_PARSE_C 1 +#define CONFIG_SPIFFS_GC_MAX_RUNS 10 +#define CONFIG_ESP32_APPTRACE_DEST_NONE 1 +#define CONFIG_PARTITION_TABLE_CUSTOM_APP_BIN_OFFSET 0x10000 +#define CONFIG_MBEDTLS_SSL_PROTO_TLS1_2 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA 1 +#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM 32 +#define CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED 1 +#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 160 +#define CONFIG_MBEDTLS_HARDWARE_AES 1 +#define CONFIG_FREERTOS_HZ 100 +#define CONFIG_LOG_COLORS 1 +#define CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE 1 +#define CONFIG_STACK_CHECK_NONE 1 +#define CONFIG_FREERTOS_ASSERT_FAIL_ABORT 1 +#define CONFIG_BROWNOUT_DET 1 +#define CONFIG_ESP32_XTAL_FREQ 40 +#define CONFIG_MONITOR_BAUD_115200B 1 +#define CONFIG_LOG_BOOTLOADER_LEVEL 3 +#define CONFIG_MBEDTLS_TLS_ENABLED 1 +#define CONFIG_LWIP_MAX_RAW_PCBS 16 +#define CONFIG_MBEDTLS_SSL_SESSION_TICKETS 1 +#define CONFIG_SPIFFS_MAX_PARTITIONS 3 +#define CONFIG_MBEDTLS_SSL_RENEGOTIATION 1 +#define CONFIG_ESPTOOLPY_BEFORE_RESET 1 +#define CONFIG_ESPTOOLPY_BAUD_OTHER_VAL 115200 +#define CONFIG_SPIFFS_OBJ_NAME_LEN 32 +#define CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT 5 +#define CONFIG_TCPIP_RECVMBOX_SIZE 32 +#define CONFIG_TCP_MAXRTX 12 +#define CONFIG_ESPTOOLPY_AFTER "hard_reset" +#define CONFIG_LWIP_SO_REUSE 1 +#define CONFIG_ESP32_XTAL_FREQ_40 1 +#define CONFIG_DMA_TX_BUF_NUM 10 +#define CONFIG_LWIP_MAX_LISTENING_TCP 16 +#define CONFIG_FREERTOS_INTERRUPT_BACKTRACE 1 +#define CONFIG_WL_SECTOR_SIZE 4096 +#define CONFIG_ESP32_DEBUG_OCDAWARE 1 +#define CONFIG_TIMER_TASK_PRIORITY 1 +#define CONFIG_MBEDTLS_TLS_CLIENT 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED 1 +#define CONFIG_MONITOR_BAUD 115200 +#define CONFIG_FREERTOS_CORETIMER_0 1 +#define CONFIG_PARTITION_TABLE_CUSTOM_FILENAME "partitions.csv" +#define CONFIG_MBEDTLS_HAVE_TIME 1 +#define CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY 1 +#define CONFIG_TCP_QUEUE_OOSEQ 1 +#define CONFIG_MBEDTLS_TLS_SERVER 1 +#define CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT 1 +#define CONFIG_FREERTOS_ISR_STACKSIZE 1536 +#define CONFIG_OPENSSL_ASSERT_DO_NOTHING 1 +#define CONFIG_WL_SECTOR_SIZE_4096 1 +#define CONFIG_OPTIMIZATION_LEVEL_DEBUG 1 +#define CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED 1 +#define CONFIG_BOOTLOADER_VDDSDIO_BOOST 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA 1 +#define CONFIG_SYSTEM_EVENT_QUEUE_SIZE 32 +#define CONFIG_ESP32_WIFI_TX_BUFFER_TYPE 1 +#define CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED 1 +#define CONFIG_LWIP_LOOPBACK_MAX_PBUFS 8 +#define CONFIG_APP_OFFSET 0x10000 +#define CONFIG_MEMMAP_SMP 1 +#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED 1 +#define CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT 3072 +#define CONFIG_MONITOR_BAUD_OTHER_VAL 115200 +#define CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF 1 +#define CONFIG_ESPTOOLPY_PORT "/dev/ttyUSB0" +#define CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS 1 diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Lwip/lwipopts.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Lwip/lwipopts.h new file mode 100644 index 00000000..509e512c --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Lwip/lwipopts.h @@ -0,0 +1,860 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Simon Goldschmidt + * + */ +#ifndef __LWIPOPTS_H__ +#define __LWIPOPTS_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "esp_task.h" +#include "esp_system.h" +#include "sdkconfig.h" + +#include "netif/dhcp_state.h" + +#include +#include + +/* Enable all Espressif-only options */ + +/* + ----------------------------------------------- + ---------- Platform specific locking ---------- + ----------------------------------------------- +*/ +/** + * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain + * critical regions during buffer allocation, deallocation and memory + * allocation and deallocation. + */ +#define SYS_LIGHTWEIGHT_PROT 1 + +/** + * MEMCPY: override this if you have a faster implementation at hand than the + * one included in your C library + */ +#define MEMCPY(dst,src,len) memcpy(dst,src,len) + +/** + * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a + * call to memcpy() if the length is known at compile time and is small. + */ +#define SMEMCPY(dst,src,len) memcpy(dst,src,len) + +#define LWIP_RAND esp_random + +/* + ------------------------------------ + ---------- Memory options ---------- + ------------------------------------ +*/ +/** + * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library + * instead of the lwip internal allocator. Can save code size if you + * already use it. + */ +#define MEM_LIBC_MALLOC 1 + +/** +* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator. +* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution +* speed and usage from interrupts! +*/ +#define MEMP_MEM_MALLOC 1 + +/** + * MEM_ALIGNMENT: should be set to the alignment of the CPU + * 4 byte alignment -> #define MEM_ALIGNMENT 4 + * 2 byte alignment -> #define MEM_ALIGNMENT 2 + */ +#define MEM_ALIGNMENT 4 + +/* + ------------------------------------------------ + ---------- Internal Memory Pool Sizes ---------- + ------------------------------------------------ +*/ + +/** + * MEMP_NUM_NETCONN: the number of struct netconns. + * (only needed if you use the sequential API, like api_lib.c) + */ +#define MEMP_NUM_NETCONN CONFIG_LWIP_MAX_SOCKETS + +/** + * MEMP_NUM_RAW_PCB: Number of raw connection PCBs + * (requires the LWIP_RAW option) + */ +#define MEMP_NUM_RAW_PCB CONFIG_LWIP_MAX_RAW_PCBS + +/** + * MEMP_NUM_TCP_PCB: the number of simultaneously active TCP connections. + * (requires the LWIP_TCP option) + */ +#define MEMP_NUM_TCP_PCB CONFIG_LWIP_MAX_ACTIVE_TCP + +/** + * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections. + * (requires the LWIP_TCP option) + */ +#define MEMP_NUM_TCP_PCB_LISTEN CONFIG_LWIP_MAX_LISTENING_TCP + +/** + * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + * per active UDP "connection". + * (requires the LWIP_UDP option) + */ +#define MEMP_NUM_UDP_PCB CONFIG_LWIP_MAX_UDP_PCBS + +/* + -------------------------------- + ---------- ARP options ------- + -------------------------------- +*/ +/** + * ARP_QUEUEING==1: Multiple outgoing packets are queued during hardware address + * resolution. By default, only the most recent packet is queued per IP address. + * This is sufficient for most protocols and mainly reduces TCP connection + * startup time. Set this to 1 if you know your application sends more than one + * packet in a row to an IP address that is not in the ARP cache. + */ +#define ARP_QUEUEING 1 + +/* + -------------------------------- + ---------- IP options ---------- + -------------------------------- +*/ +/** + * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that + * this option does not affect outgoing packet sizes, which can be controlled + * via IP_FRAG. + */ +#define IP_REASSEMBLY CONFIG_LWIP_IP_REASSEMBLY + +/** + * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note + * that this option does not affect incoming packet sizes, which can be + * controlled via IP_REASSEMBLY. + */ +#define IP_FRAG CONFIG_LWIP_IP_FRAG + +/** + * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally) + * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived + * in this time, the whole packet is discarded. + */ +#define IP_REASS_MAXAGE 3 + +/** + * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled. + * Since the received pbufs are enqueued, be sure to configure + * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive + * packets even if the maximum amount of fragments is enqueued for reassembly! + */ +#define IP_REASS_MAX_PBUFS 10 + +/* + ---------------------------------- + ---------- ICMP options ---------- + ---------------------------------- +*/ + +#define LWIP_BROADCAST_PING CONFIG_LWIP_BROADCAST_PING + +#define LWIP_MULTICAST_PING CONFIG_LWIP_MULTICAST_PING + +/* + --------------------------------- + ---------- RAW options ---------- + --------------------------------- +*/ +/** + * LWIP_RAW==1: Enable application layer to hook into the IP layer itself. + */ +#define LWIP_RAW 1 + +/* + ---------------------------------- + ---------- DHCP options ---------- + ---------------------------------- +*/ +/** + * LWIP_DHCP==1: Enable DHCP module. + */ +#define LWIP_DHCP 1 + +#define DHCP_MAXRTX 0 + +/** + * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address. + */ +#define DHCP_DOES_ARP_CHECK CONFIG_LWIP_DHCP_DOES_ARP_CHECK + + +/** + * CONFIG_LWIP_DHCP_RESTORE_LAST_IP==1: Last valid IP address obtained from DHCP server + * is restored after reset/power-up. + */ +#if CONFIG_LWIP_DHCP_RESTORE_LAST_IP + +#define LWIP_DHCP_IP_ADDR_RESTORE() dhcp_ip_addr_restore(netif) +#define LWIP_DHCP_IP_ADDR_STORE() dhcp_ip_addr_store(netif) +#define LWIP_DHCP_IP_ADDR_ERASE() dhcp_ip_addr_erase(esp_netif[tcpip_if]) + +#endif + +/* + ------------------------------------ + ---------- AUTOIP options ---------- + ------------------------------------ +*/ +#ifdef CONFIG_LWIP_AUTOIP +#define LWIP_AUTOIP 1 + +/** +* LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on +* the same interface at the same time. +*/ +#define LWIP_DHCP_AUTOIP_COOP 1 + +/** +* LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes +* that should be sent before falling back on AUTOIP. This can be set +* as low as 1 to get an AutoIP address very quickly, but you should +* be prepared to handle a changing IP address when DHCP overrides +* AutoIP. +*/ +#define LWIP_DHCP_AUTOIP_COOP_TRIES CONFIG_LWIP_AUTOIP_TRIES + +#define LWIP_AUTOIP_MAX_CONFLICTS CONFIG_LWIP_AUTOIP_MAX_CONFLICTS + +#define LWIP_AUTOIP_RATE_LIMIT_INTERVAL CONFIG_LWIP_AUTOIP_RATE_LIMIT_INTERVAL + +#endif /* CONFIG_LWIP_AUTOIP */ + +/* + ---------------------------------- + ---------- SNMP options ---------- + ---------------------------------- +*/ +/* + ---------------------------------- + ---------- IGMP options ---------- + ---------------------------------- +*/ +/** + * LWIP_IGMP==1: Turn on IGMP module. + */ +#define LWIP_IGMP 1 + +/* + ---------------------------------- + ---------- DNS options ----------- + ---------------------------------- +*/ +/** + * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS + * transport. + */ +#define LWIP_DNS 1 + +#define DNS_MAX_SERVERS 3 +#define DNS_FALLBACK_SERVER_INDEX (DNS_MAX_SERVERS - 1) + +/* + --------------------------------- + ---------- UDP options ---------- + --------------------------------- +*/ +/* + --------------------------------- + ---------- TCP options ---------- + --------------------------------- +*/ + + +/** + * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order. + * Define to 0 if your device is low on memory. + */ +#define TCP_QUEUE_OOSEQ CONFIG_TCP_QUEUE_OOSEQ + +/** + * ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES==1: Keep TCP connection when IP changed + * scenario happens: 192.168.0.2 -> 0.0.0.0 -> 192.168.0.2 or 192.168.0.2 -> 0.0.0.0 + */ + +#define ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES +/* + * LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all + * events (accept, sent, etc) that happen in the system. + * LWIP_CALLBACK_API==1: The PCB callback function is called directly + * for the event. This is the default. +*/ +#define TCP_MSS CONFIG_TCP_MSS + +/** + * TCP_MSL: The maximum segment lifetime in milliseconds + */ +#define TCP_MSL CONFIG_TCP_MSL + +/** + * TCP_MAXRTX: Maximum number of retransmissions of data segments. + */ +#define TCP_MAXRTX CONFIG_TCP_MAXRTX + +/** + * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments. + */ +#define TCP_SYNMAXRTX CONFIG_TCP_SYNMAXRTX + +/** + * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb. + */ +#define TCP_LISTEN_BACKLOG 1 + + +/** + * TCP_OVERSIZE: The maximum number of bytes that tcp_write may + * allocate ahead of time + */ +#ifdef CONFIG_TCP_OVERSIZE_MSS +#define TCP_OVERSIZE TCP_MSS +#endif +#ifdef CONFIG_TCP_OVERSIZE_QUARTER_MSS +#define TCP_OVERSIZE (TCP_MSS/4) +#endif +#ifdef CONFIG_TCP_OVERSIZE_DISABLE +#define TCP_OVERSIZE 0 +#endif +#ifndef TCP_OVERSIZE +#error "One of CONFIG_TCP_OVERSIZE_xxx options should be set by sdkconfig" +#endif + +/** + * LWIP_WND_SCALE and TCP_RCV_SCALE: + * Set LWIP_WND_SCALE to 1 to enable window scaling. + * Set TCP_RCV_SCALE to the desired scaling factor (shift count in the + * range of [0..14]). + * When LWIP_WND_SCALE is enabled but TCP_RCV_SCALE is 0, we can use a large + * send window while having a small receive window only. + */ +#ifdef CONFIG_LWIP_WND_SCALE +#define LWIP_WND_SCALE 1 +#define TCP_RCV_SCALE CONFIG_TCP_RCV_SCALE +#endif + +/* + ---------------------------------- + ---------- Pbuf options ---------- + ---------------------------------- +*/ + +/* + ------------------------------------------------ + ---------- Network Interfaces options ---------- + ------------------------------------------------ +*/ + +/** + * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname + * field. + */ +#define LWIP_NETIF_HOSTNAME 1 + +/** + * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data + * to be sent into one single pbuf. This is for compatibility with DMA-enabled + * MACs that do not support scatter-gather. + * Beware that this might involve CPU-memcpy before transmitting that would not + * be needed without this flag! Use this only if you need to! + * + * @todo: TCP and IP-frag do not work with this, yet: + */ +#define LWIP_NETIF_TX_SINGLE_PBUF 1 + +/* + ------------------------------------ + ---------- LOOPIF options ---------- + ------------------------------------ +*/ +#ifdef CONFIG_LWIP_NETIF_LOOPBACK +/** + * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP + * address equal to the netif IP address, looping them back up the stack. + */ +#define LWIP_NETIF_LOOPBACK 1 + +/** + * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback + * sending for each netif (0 = disabled) + */ +#define LWIP_LOOPBACK_MAX_PBUFS CONFIG_LWIP_LOOPBACK_MAX_PBUFS +#endif + +/* + ------------------------------------ + ---------- SLIPIF options ---------- + ------------------------------------ +*/ + +/* + ------------------------------------ + ---------- Thread options ---------- + ------------------------------------ +*/ +/** + * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread. + */ +#define TCPIP_THREAD_NAME "tiT" + +/** + * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#define TCPIP_THREAD_STACKSIZE ESP_TASK_TCPIP_STACK + +/** + * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#define TCPIP_THREAD_PRIO ESP_TASK_TCPIP_PRIO + +/** + * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when tcpip_init is called. + */ +#define TCPIP_MBOX_SIZE CONFIG_TCPIP_RECVMBOX_SIZE + +/** + * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#define DEFAULT_UDP_RECVMBOX_SIZE CONFIG_UDP_RECVMBOX_SIZE + +/** + * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#define DEFAULT_TCP_RECVMBOX_SIZE CONFIG_TCP_RECVMBOX_SIZE + +/** + * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections. + * The queue size value itself is platform-dependent, but is passed to + * sys_mbox_new() when the acceptmbox is created. + */ +#define DEFAULT_ACCEPTMBOX_SIZE 6 + +/** + * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread. + * The stack size value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#define DEFAULT_THREAD_STACKSIZE TCPIP_THREAD_STACKSIZE + +/** + * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread. + * The priority value itself is platform-dependent, but is passed to + * sys_thread_new() when the thread is created. + */ +#define DEFAULT_THREAD_PRIO TCPIP_THREAD_PRIO + +/** + * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a + * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed + * to sys_mbox_new() when the recvmbox is created. + */ +#define DEFAULT_RAW_RECVMBOX_SIZE 6 + +/* + ---------------------------------------------- + ---------- Sequential layer options ---------- + ---------------------------------------------- +*/ +/** + * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!) + * Don't use it if you're not an active lwIP project member + */ +#define LWIP_TCPIP_CORE_LOCKING 0 + +/* + ------------------------------------ + ---------- Socket options ---------- + ------------------------------------ +*/ +/** + * LWIP_SO_SNDTIMEO==1: Enable send timeout for sockets/netconns and + * SO_SNDTIMEO processing. + */ +#define LWIP_SO_SNDTIMEO 1 + +/** + * LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and + * SO_RCVTIMEO processing. + */ +#define LWIP_SO_RCVTIMEO 1 + +/** + * LWIP_SO_LINGER==1: Enable linger option for sockets/netconns + */ +#define LWIP_SO_LINGER 1 + +/** + * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT + * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set + * in seconds. (does not require sockets.c, and will affect tcp.c) + */ +#define LWIP_TCP_KEEPALIVE 1 + +/** + * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing. + */ +#define LWIP_SO_RCVBUF CONFIG_LWIP_SO_RCVBUF + +/** + * SO_REUSE==1: Enable SO_REUSEADDR option. + * This option is set via menuconfig. + */ +#define SO_REUSE CONFIG_LWIP_SO_REUSE + +/** + * SO_REUSE_RXTOALL==1: Pass a copy of incoming broadcast/multicast packets + * to all local matches if SO_REUSEADDR is turned on. + * WARNING: Adds a memcpy for every packet if passing to more than one pcb! + */ +#define SO_REUSE_RXTOALL CONFIG_LWIP_SO_REUSE_RXTOALL + +/* + ---------------------------------------- + ---------- Statistics options ---------- + ---------------------------------------- +*/ + +/** + * LWIP_STATS==1: Enable statistics collection in lwip_stats. + */ +#define LWIP_STATS CONFIG_LWIP_STATS + +#if LWIP_STATS + +/** + * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions. + */ +#define LWIP_STATS_DISPLAY CONFIG_LWIP_STATS +#endif + + +/* + --------------------------------- + ---------- PPP options ---------- + --------------------------------- +*/ + +/** + * PPP_SUPPORT==1: Enable PPP. + */ +#define PPP_SUPPORT CONFIG_PPP_SUPPORT + +#if PPP_SUPPORT + +/** + * PPP_NOTIFY_PHASE==1: Support PPP notify phase. + */ +#define PPP_NOTIFY_PHASE CONFIG_PPP_NOTIFY_PHASE_SUPPORT + +/** + * PAP_SUPPORT==1: Support PAP. + */ +#define PAP_SUPPORT CONFIG_PPP_PAP_SUPPORT + +/** + * CHAP_SUPPORT==1: Support CHAP. + */ +#define CHAP_SUPPORT CONFIG_PPP_CHAP_SUPPORT + +/** + * MSCHAP_SUPPORT==1: Support MSCHAP. + */ +#define MSCHAP_SUPPORT CONFIG_PPP_MSCHAP_SUPPORT + +/** + * CCP_SUPPORT==1: Support CCP. + */ +#define MPPE_SUPPORT CONFIG_PPP_MPPE_SUPPORT + +/** + * PPP_MAXIDLEFLAG: Max Xmit idle time (in ms) before resend flag char. + * TODO: If PPP_MAXIDLEFLAG > 0 and next package is send during PPP_MAXIDLEFLAG time, + * then 0x7E is not added at the begining of PPP package but 0x7E termination + * is always at the end. This behaviour brokes PPP dial with GSM (PPPoS). + * The PPP package should always start and end with 0x7E. + */ + +#define PPP_MAXIDLEFLAG 0 + +/** + * PPP_DEBUG: Enable debugging for PPP. + */ +#define PPP_DEBUG_ON CONFIG_PPP_DEBUG_ON + +#if PPP_DEBUG_ON +#define PPP_DEBUG LWIP_DBG_ON +#else +#define PPP_DEBUG LWIP_DBG_OFF +#endif + +#endif + +/* + -------------------------------------- + ---------- Checksum options ---------- + -------------------------------------- +*/ + +/* + --------------------------------------- + ---------- IPv6 options --------------- + --------------------------------------- +*/ +/** + * LWIP_IPV6==1: Enable IPv6 + */ +#define LWIP_IPV6 1 + +/* + --------------------------------------- + ---------- Hook options --------------- + --------------------------------------- +*/ +#define LWIP_HOOK_IP4_ROUTE_SRC ip4_route_src_hook +/* + --------------------------------------- + ---------- Debugging options ---------- + --------------------------------------- +*/ +/** + * ETHARP_DEBUG: Enable debugging in etharp.c. + */ +#define ETHARP_DEBUG LWIP_DBG_OFF + +/** + * NETIF_DEBUG: Enable debugging in netif.c. + */ +#define NETIF_DEBUG LWIP_DBG_OFF + +/** + * PBUF_DEBUG: Enable debugging in pbuf.c. + */ +#define PBUF_DEBUG LWIP_DBG_OFF + +/** + * API_LIB_DEBUG: Enable debugging in api_lib.c. + */ +#define API_LIB_DEBUG LWIP_DBG_OFF + +/** + * SOCKETS_DEBUG: Enable debugging in sockets.c. + */ +#define SOCKETS_DEBUG LWIP_DBG_OFF + +/** + * ICMP_DEBUG: Enable debugging in icmp.c. + */ +#define ICMP_DEBUG LWIP_DBG_OFF + +/** + * IP_DEBUG: Enable debugging for IP. + */ +#define IP_DEBUG LWIP_DBG_OFF + +/** + * MEMP_DEBUG: Enable debugging in memp.c. + */ +#define MEMP_DEBUG LWIP_DBG_OFF + +/** + * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug. + */ +#define TCP_INPUT_DEBUG LWIP_DBG_OFF + +/** + * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions. + */ +#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF + +/** + * TCPIP_DEBUG: Enable debugging in tcpip.c. + */ +#define TCPIP_DEBUG LWIP_DBG_OFF + +/** + * ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be + * updated with the source MAC and IP addresses supplied in the packet. + * You may want to disable this if you do not trust LAN peers to have the + * correct addresses, or as a limited approach to attempt to handle + * spoofing. If disabled, lwIP will need to make a new ARP request if + * the peer is not already in the ARP table, adding a little latency. + * The peer *is* in the ARP table if it requested our address before. + * Also notice that this slows down input processing of every IP packet! + */ +#define ETHARP_TRUST_IP_MAC CONFIG_LWIP_ETHARP_TRUST_IP_MAC + + +/** + * POSIX I/O functions are mapped to LWIP via the VFS layer + * (see port/vfs_lwip.c) + */ +#define LWIP_POSIX_SOCKETS_IO_NAMES 0 + +/** + * FD_SETSIZE from sys/types.h is the maximum number of supported file + * descriptors and CONFIG_LWIP_MAX_SOCKETS defines the number of sockets; + * LWIP_SOCKET_OFFSET is configured to use the largest numbers of file + * descriptors for sockets. File descriptors from 0 to LWIP_SOCKET_OFFSET-1 + * are non-socket descriptors and from LWIP_SOCKET_OFFSET to FD_SETSIZE are + * socket descriptors. + */ +#define LWIP_SOCKET_OFFSET (FD_SETSIZE - CONFIG_LWIP_MAX_SOCKETS) + +/* Enable all Espressif-only options */ + +#define ESP_LWIP 1 +#define ESP_LWIP_ARP 1 +#define ESP_PER_SOC_TCP_WND 0 +#define ESP_THREAD_SAFE 1 +#define ESP_THREAD_SAFE_DEBUG LWIP_DBG_OFF +#define ESP_DHCP 1 +#define ESP_DNS 1 +#define ESP_IPV6_AUTOCONFIG 1 +#define ESP_PERF 0 +#define ESP_RANDOM_TCP_PORT 1 +#define ESP_IP4_ATON 1 +#define ESP_LIGHT_SLEEP 1 +#define ESP_L2_TO_L3_COPY CONFIG_L2_TO_L3_COPY +#define ESP_STATS_MEM CONFIG_LWIP_STATS +#define ESP_STATS_DROP CONFIG_LWIP_STATS +#define ESP_STATS_TCP 0 +#define ESP_DHCP_TIMER 1 +#define ESP_DHCPS_TIMER 1 +#define ESP_LWIP_LOGI(...) ESP_LOGI("lwip", __VA_ARGS__) +#define ESP_PING 1 +#define ESP_HAS_SELECT 1 +#define ESP_AUTO_RECV 1 +#define ESP_GRATUITOUS_ARP CONFIG_ESP_GRATUITOUS_ARP + +#ifdef ESP_IRAM_ATTR +#undef ESP_IRAM_ATTR +#endif +#define ESP_IRAM_ATTR + +#if ESP_PERF +#define DBG_PERF_PATH_SET(dir, point) +#define DBG_PERF_FILTER_LEN 1000 + +enum { + DBG_PERF_DIR_RX = 0, + DBG_PERF_DIR_TX, +}; + +enum { + DBG_PERF_POINT_INT = 0, + DBG_PERF_POINT_WIFI_IN = 1, + DBG_PERF_POINT_WIFI_OUT = 2, + DBG_PERF_POINT_LWIP_IN = 3, + DBG_PERF_POINT_LWIP_OUT = 4, + DBG_PERF_POINT_SOC_IN = 5, + DBG_PERF_POINT_SOC_OUT = 6, +}; + +#else +#define DBG_PERF_PATH_SET(dir, point) +#define DBG_PERF_FILTER_LEN 1000 +#endif + +#define TCP_SND_BUF CONFIG_TCP_SND_BUF_DEFAULT +#define TCP_WND CONFIG_TCP_WND_DEFAULT + +#if ESP_PER_SOC_TCP_WND +#define TCP_WND_DEFAULT CONFIG_TCP_WND_DEFAULT +#define TCP_SND_BUF_DEFAULT CONFIG_TCP_SND_BUF_DEFAULT +#define TCP_WND(pcb) (pcb->per_soc_tcp_wnd) +#define TCP_SND_BUF(pcb) (pcb->per_soc_tcp_snd_buf) +#define TCP_SND_QUEUELEN(pcb) ((4 * (TCP_SND_BUF((pcb))) + (TCP_MSS - 1))/(TCP_MSS)) +#define TCP_SNDLOWAT(pcb) LWIP_MIN(LWIP_MAX(((TCP_SND_BUF((pcb)))/2), (2 * TCP_MSS) + 1), (TCP_SND_BUF((pcb))) - 1) +#define TCP_SNDQUEUELOWAT(pcb) LWIP_MAX(((TCP_SND_QUEUELEN((pcb)))/2), 5) +#define TCP_WND_UPDATE_THRESHOLD(pcb) LWIP_MIN((TCP_WND((pcb)) / 4), (TCP_MSS * 4)) +#endif + +/** + * DHCP_DEBUG: Enable debugging in dhcp.c. + */ +#define DHCP_DEBUG LWIP_DBG_OFF +#define LWIP_DEBUG LWIP_DBG_OFF +#define TCP_DEBUG LWIP_DBG_OFF + +#define CHECKSUM_CHECK_UDP 0 +#define CHECKSUM_CHECK_IP 0 + +#define LWIP_NETCONN_FULLDUPLEX 1 +#define LWIP_NETCONN_SEM_PER_THREAD 1 + +#define LWIP_DHCP_MAX_NTP_SERVERS CONFIG_LWIP_DHCP_MAX_NTP_SERVERS +#define LWIP_TIMEVAL_PRIVATE 0 + +#define SNTP_SET_SYSTEM_TIME_US(sec, us) \ + do { \ + struct timeval tv = { .tv_sec = sec, .tv_usec = us }; \ + settimeofday(&tv, NULL); \ + } while (0); + +#define SNTP_GET_SYSTEM_TIME(sec, us) \ + do { \ + struct timeval tv = { .tv_sec = 0, .tv_usec = 0 }; \ + gettimeofday(&tv, NULL); \ + (sec) = tv.tv_sec; \ + (us) = tv.tv_usec; \ + } while (0); + +#define SOC_SEND_LOG //printf + +#endif /* __LWIPOPTS_H__ */ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Lwip/nf_api_msg.c b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Lwip/nf_api_msg.c new file mode 100644 index 00000000..b3589fe4 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Lwip/nf_api_msg.c @@ -0,0 +1,2129 @@ +/** + * @file + * Sequential API Internal module + * + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +#include "lwip/opt.h" + +#if LWIP_NETCONN /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/priv/api_msg.h" + +#include "lwip/ip.h" +#include "lwip/ip_addr.h" +#include "lwip/udp.h" +#include "lwip/tcp.h" +#include "lwip/raw.h" + +#include "lwip/memp.h" +#include "lwip/igmp.h" +#include "lwip/dns.h" +#include "lwip/mld6.h" +#include "lwip/priv/tcpip_priv.h" + +#include + +extern void sys_signal_sock_event(); // MS-CHANGE + +/* netconns are polled once per second (e.g. continue write on memory error) */ +#define NETCONN_TCP_POLL_INTERVAL 2 + +#define SET_NONBLOCKING_CONNECT(conn, val) do { if (val) { \ + (conn)->flags |= NETCONN_FLAG_IN_NONBLOCKING_CONNECT; \ +} else { \ + (conn)->flags &= ~ NETCONN_FLAG_IN_NONBLOCKING_CONNECT; }} while(0) +#define IN_NONBLOCKING_CONNECT(conn) (((conn)->flags & NETCONN_FLAG_IN_NONBLOCKING_CONNECT) != 0) + +/* forward declarations */ +#if LWIP_TCP +#if LWIP_TCPIP_CORE_LOCKING +#define WRITE_DELAYED , 1 +#define WRITE_DELAYED_PARAM , u8_t delayed +#else /* LWIP_TCPIP_CORE_LOCKING */ +#define WRITE_DELAYED +#define WRITE_DELAYED_PARAM +#endif /* LWIP_TCPIP_CORE_LOCKING */ +static err_t lwip_netconn_do_writemore(struct netconn *conn WRITE_DELAYED_PARAM); + +#if ESP_LWIP +#define SIG_CLOSE_PARAM , bool sig_close +#define SIG_CLOSE_TRUE true +#define SIG_CLOSE_FALSE false +static err_t lwip_netconn_do_close_internal(struct netconn *conn WRITE_DELAYED_PARAM SIG_CLOSE_PARAM); +#else +static err_t lwip_netconn_do_close_internal(struct netconn *conn WRITE_DELAYED_PARAM); +#endif + +#endif + +#if LWIP_TCPIP_CORE_LOCKING +#define TCPIP_APIMSG_ACK(m) NETCONN_SET_SAFE_ERR((m)->conn, (m)->err) +#else /* LWIP_TCPIP_CORE_LOCKING */ +#define TCPIP_APIMSG_ACK(m) do { NETCONN_SET_SAFE_ERR((m)->conn, (m)->err); sys_sem_signal(LWIP_API_MSG_SEM(m)); } while(0) +#endif /* LWIP_TCPIP_CORE_LOCKING */ + +#if LWIP_TCP +u8_t netconn_aborted; +#endif /* LWIP_TCP */ + +#if LWIP_RAW +/** + * Receive callback function for RAW netconns. + * Doesn't 'eat' the packet, only copies it and sends it to + * conn->recvmbox + * + * @see raw.h (struct raw_pcb.recv) for parameters and return value + */ +static u8_t +recv_raw(void *arg, struct raw_pcb *pcb, struct pbuf *p, + const ip_addr_t *addr) +{ + struct pbuf *q; + struct netbuf *buf; + struct netconn *conn; + + LWIP_UNUSED_ARG(addr); + conn = (struct netconn *)arg; + + if ((conn != NULL) && sys_mbox_valid(&conn->recvmbox)) { +#if LWIP_SO_RCVBUF + int recv_avail; + SYS_ARCH_GET(conn->recv_avail, recv_avail); + if ((recv_avail + (int)(p->tot_len)) > conn->recv_bufsize) { + return 0; + } +#endif /* LWIP_SO_RCVBUF */ + /* copy the whole packet into new pbufs */ + q = pbuf_alloc(PBUF_RAW, p->tot_len, PBUF_RAM); + if (q != NULL) { + if (pbuf_copy(q, p) != ERR_OK) { + pbuf_free(q); + q = NULL; + } + } + + if (q != NULL) { + u16_t len; + buf = (struct netbuf *)memp_malloc(MEMP_NETBUF); + if (buf == NULL) { + pbuf_free(q); + return 0; + } + + buf->p = q; + buf->ptr = q; + ip_addr_copy(buf->addr, *ip_current_src_addr()); + buf->port = pcb->protocol; + + len = q->tot_len; + if (sys_mbox_trypost(&conn->recvmbox, buf) != ERR_OK) { + ESP_STATS_DROP_INC(esp.rx_rawmbox_post_fail); + netbuf_delete(buf); + return 0; + } else { +#if LWIP_SO_RCVBUF + SYS_ARCH_INC(conn->recv_avail, len); +#endif /* LWIP_SO_RCVBUF */ + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, len); + } + } + } + + return 0; /* do not eat the packet */ +} +#endif /* LWIP_RAW*/ + +#if LWIP_UDP +/** + * Receive callback function for UDP netconns. + * Posts the packet to conn->recvmbox or deletes it on memory error. + * + * @see udp.h (struct udp_pcb.recv) for parameters + */ +static void +recv_udp(void *arg, struct udp_pcb *pcb, struct pbuf *p, + const ip_addr_t *addr, u16_t port) +{ + struct netbuf *buf; + struct netconn *conn; + u16_t len; +#if LWIP_SO_RCVBUF + int recv_avail; +#endif /* LWIP_SO_RCVBUF */ + + LWIP_UNUSED_ARG(pcb); /* only used for asserts... */ + LWIP_ASSERT("recv_udp must have a pcb argument", pcb != NULL); + LWIP_ASSERT("recv_udp must have an argument", arg != NULL); + conn = (struct netconn *)arg; + + if (conn == NULL) { + pbuf_free(p); + return; + } + + LWIP_ASSERT("recv_udp: recv for wrong pcb!", conn->pcb.udp == pcb); + +#if LWIP_SO_RCVBUF + SYS_ARCH_GET(conn->recv_avail, recv_avail); + if (!sys_mbox_valid(&conn->recvmbox) || + ((recv_avail + (int)(p->tot_len)) > conn->recv_bufsize)) { +#else /* LWIP_SO_RCVBUF */ + if (!sys_mbox_valid(&conn->recvmbox)) { +#endif /* LWIP_SO_RCVBUF */ + pbuf_free(p); + return; + } + +#if ESP_LWIP +#if LWIP_IPV6 + /* This should be eventually moved to a flag on the UDP PCB, and this drop can happen + more correctly in udp_input(). This will also allow icmp_dest_unreach() to be called. */ + if (conn->flags & NETCONN_FLAG_IPV6_V6ONLY && !ip_current_is_v6()) { + LWIP_DEBUGF(API_MSG_DEBUG, ("recv_udp: Dropping IPv4 UDP packet (IPv6-only socket)")); + pbuf_free(p); + return; + } +#endif +#endif + + buf = (struct netbuf *)memp_malloc(MEMP_NETBUF); + if (buf == NULL) { + pbuf_free(p); + return; + } else { + buf->p = p; + buf->ptr = p; + ip_addr_set(&buf->addr, addr); + buf->port = port; +#if LWIP_NETBUF_RECVINFO + { + /* get the UDP header - always in the first pbuf, ensured by udp_input */ + const struct udp_hdr* udphdr = (const struct udp_hdr*)ip_next_header_ptr(); +#if LWIP_CHECKSUM_ON_COPY + buf->flags = NETBUF_FLAG_DESTADDR; +#endif /* LWIP_CHECKSUM_ON_COPY */ + ip_addr_set(&buf->toaddr, ip_current_dest_addr()); + buf->toport_chksum = udphdr->dest; + } +#endif /* LWIP_NETBUF_RECVINFO */ + } + + len = p->tot_len; + if (sys_mbox_trypost(&conn->recvmbox, buf) != ERR_OK) { + ESP_STATS_DROP_INC(esp.rx_udpmbox_post_fail); + netbuf_delete(buf); + return; + } else { +#if LWIP_SO_RCVBUF + SYS_ARCH_INC(conn->recv_avail, len); +#endif /* LWIP_SO_RCVBUF */ + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, len); + } +} +#endif /* LWIP_UDP */ + +#if LWIP_TCP +/** + * Receive callback function for TCP netconns. + * Posts the packet to conn->recvmbox, but doesn't delete it on errors. + * + * @see tcp.h (struct tcp_pcb.recv) for parameters and return value + */ +static err_t +recv_tcp(void *arg, struct tcp_pcb *pcb, struct pbuf *p, err_t err) +{ + struct netconn *conn; + u16_t len; + + LWIP_UNUSED_ARG(pcb); + LWIP_ASSERT("recv_tcp must have a pcb argument", pcb != NULL); + LWIP_ASSERT("recv_tcp must have an argument", arg != NULL); + conn = (struct netconn *)arg; + + if (conn == NULL) { + return ERR_VAL; + } + LWIP_ASSERT("recv_tcp: recv for wrong pcb!", conn->pcb.tcp == pcb); + + if (!sys_mbox_valid(&conn->recvmbox)) { + /* recvmbox already deleted */ + if (p != NULL) { + tcp_recved(pcb, p->tot_len); + pbuf_free(p); + } + return ERR_OK; + } + /* Unlike for UDP or RAW pcbs, don't check for available space + using recv_avail since that could break the connection + (data is already ACKed) */ + + /* don't overwrite fatal errors! */ + if (err != ERR_OK) { + NETCONN_SET_SAFE_ERR(conn, err); + } + + if (p != NULL) { + len = p->tot_len; + } else { + len = 0; + } + + if (sys_mbox_trypost(&conn->recvmbox, p) != ERR_OK) { + ESP_STATS_DROP_INC(esp.rx_tcpmbox_post_fail); + /* don't deallocate p: it is presented to us later again from tcp_fasttmr! */ + return ERR_MEM; + } else { +#if LWIP_SO_RCVBUF + SYS_ARCH_INC(conn->recv_avail, len); +#endif /* LWIP_SO_RCVBUF */ + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, len); + } + + return ERR_OK; +} + +/** + * Poll callback function for TCP netconns. + * Wakes up an application thread that waits for a connection to close + * or data to be sent. The application thread then takes the + * appropriate action to go on. + * + * Signals the conn->sem. + * netconn_close waits for conn->sem if closing failed. + * + * @see tcp.h (struct tcp_pcb.poll) for parameters and return value + */ +static err_t +poll_tcp(void *arg, struct tcp_pcb *pcb) +{ + struct netconn *conn = (struct netconn *)arg; +#if ESP_LWIP + bool sig_close = false; +#endif + + LWIP_UNUSED_ARG(pcb); + LWIP_ASSERT("conn != NULL", (conn != NULL)); + + if (conn->state == NETCONN_WRITE) { + lwip_netconn_do_writemore(conn WRITE_DELAYED); + } else if (conn->state == NETCONN_CLOSE) { +#if !LWIP_SO_SNDTIMEO && !LWIP_SO_LINGER + if (conn->current_msg && conn->current_msg->msg.sd.polls_left) { + conn->current_msg->msg.sd.polls_left--; + } +#endif /* !LWIP_SO_SNDTIMEO && !LWIP_SO_LINGER */ +#if ESP_LWIP + /* Delay the netconn close until no one use 'conn' because close frees 'conn'*/ + if (ERR_OK == lwip_netconn_do_close_internal(conn WRITE_DELAYED, SIG_CLOSE_FALSE)) { + sig_close = true; + } +#else + lwip_netconn_do_close_internal(conn WRITE_DELAYED); +#endif + } + /* @todo: implement connect timeout here? */ + + /* Did a nonblocking write fail before? Then check available write-space. */ + if (conn->flags & NETCONN_FLAG_CHECK_WRITESPACE) { + /* If the queued byte- or pbuf-count drops below the configured low-water limit, + let select mark this pcb as writable again. */ + if ((conn->pcb.tcp != NULL) && (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) && + (tcp_sndqueuelen(conn->pcb.tcp) < TCP_SNDQUEUELOWAT)) { + conn->flags &= ~NETCONN_FLAG_CHECK_WRITESPACE; + API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0); + } + } + +#if ESP_LWIP + if (sig_close) { + sys_sem_t *op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg); + conn->current_msg = NULL; + sys_sem_signal(op_completed_sem); + return ERR_ABRT; + } +#endif + + return ERR_OK; +} + +/** + * Sent callback function for TCP netconns. + * Signals the conn->sem and calls API_EVENT. + * netconn_write waits for conn->sem if send buffer is low. + * + * @see tcp.h (struct tcp_pcb.sent) for parameters and return value + */ +static err_t +sent_tcp(void *arg, struct tcp_pcb *pcb, u16_t len) +{ + struct netconn *conn = (struct netconn *)arg; +#if ESP_LWIP + bool sig_close = false; +#endif + + LWIP_UNUSED_ARG(pcb); + LWIP_ASSERT("conn != NULL", (conn != NULL)); + + if (conn) { + if (conn->state == NETCONN_WRITE) { + lwip_netconn_do_writemore(conn WRITE_DELAYED); + } else if (conn->state == NETCONN_CLOSE) { +#if ESP_LWIP + /* Delay the netconn close until no one use 'conn' because close frees 'conn'*/ + if (ERR_OK == lwip_netconn_do_close_internal(conn WRITE_DELAYED, SIG_CLOSE_FALSE)) { + sig_close = true; + } +#else + lwip_netconn_do_close_internal(conn WRITE_DELAYED); +#endif + } + + /* If the queued byte- or pbuf-count drops below the configured low-water limit, + let select mark this pcb as writable again. */ + if ((conn->pcb.tcp != NULL) && (tcp_sndbuf(conn->pcb.tcp) > TCP_SNDLOWAT) && + (tcp_sndqueuelen(conn->pcb.tcp) < TCP_SNDQUEUELOWAT)) { + conn->flags &= ~NETCONN_FLAG_CHECK_WRITESPACE; + API_EVENT(conn, NETCONN_EVT_SENDPLUS, len); + } + +#if ESP_LWIP + if (sig_close) { + sys_sem_t *op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg); + conn->current_msg = NULL; + sys_sem_signal(op_completed_sem); + return ERR_ABRT; + } +#endif + } + + return ERR_OK; +} + +/** + * Error callback function for TCP netconns. + * Signals conn->sem, posts to all conn mboxes and calls API_EVENT. + * The application thread has then to decide what to do. + * + * @see tcp.h (struct tcp_pcb.err) for parameters + */ +static void +err_tcp(void *arg, err_t err) +{ + struct netconn *conn; + enum netconn_state old_state; + + conn = (struct netconn *)arg; + LWIP_ASSERT("conn != NULL", (conn != NULL)); + + conn->pcb.tcp = NULL; + + /* reset conn->state now before waking up other threads */ + old_state = conn->state; + conn->state = NETCONN_NONE; + + if (old_state == NETCONN_CLOSE) { + /* RST during close: let close return success & dealloc the netconn */ + err = ERR_OK; + NETCONN_SET_SAFE_ERR(conn, ERR_OK); + } else { + /* no check since this is always fatal! */ + SYS_ARCH_SET(conn->last_err, err); + } + + /* @todo: the type of NETCONN_EVT created should depend on 'old_state' */ + + /* Notify the user layer about a connection error. Used to signal select. */ + API_EVENT(conn, NETCONN_EVT_ERROR, 0); + /* Try to release selects pending on 'read' or 'write', too. + They will get an error if they actually try to read or write. */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); + API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0); + + /* pass NULL-message to recvmbox to wake up pending recv */ + if (sys_mbox_valid(&conn->recvmbox)) { + /* use trypost to prevent deadlock */ +#if ESP_STATS_DROP + if (sys_mbox_trypost(&conn->recvmbox, NULL) != ERR_OK){ + ESP_STATS_DROP_INC(esp.err_tcp_rxmbox_post_fail); + } +#else + sys_mbox_trypost(&conn->recvmbox, NULL); +#endif + } + /* pass NULL-message to acceptmbox to wake up pending accept */ + if (sys_mbox_valid(&conn->acceptmbox)) { + /* use trypost to preven deadlock */ +#if ESP_STATS_DROP + if (sys_mbox_trypost(&conn->acceptmbox, NULL) != ERR_OK) { + ESP_STATS_DROP_INC(esp.err_tcp_rxmbox_post_fail); + } +#else + sys_mbox_trypost(&conn->acceptmbox, NULL); +#endif + } + + if ((old_state == NETCONN_WRITE) || (old_state == NETCONN_CLOSE) || + (old_state == NETCONN_CONNECT)) { + /* calling lwip_netconn_do_writemore/lwip_netconn_do_close_internal is not necessary + since the pcb has already been deleted! */ + int was_nonblocking_connect = IN_NONBLOCKING_CONNECT(conn); + SET_NONBLOCKING_CONNECT(conn, 0); + + if (!was_nonblocking_connect) { + sys_sem_t* op_completed_sem; + /* set error return code */ + LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL); + conn->current_msg->err = err; + op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg); + LWIP_ASSERT("inavlid op_completed_sem", sys_sem_valid(op_completed_sem)); + conn->current_msg = NULL; + /* wake up the waiting task */ + NETCONN_SET_SAFE_ERR(conn, err); + sys_sem_signal(op_completed_sem); + } + } else { + LWIP_ASSERT("conn->current_msg == NULL", conn->current_msg == NULL); + } +} + +/** + * Setup a tcp_pcb with the correct callback function pointers + * and their arguments. + * + * @param conn the TCP netconn to setup + */ +static void +setup_tcp(struct netconn *conn) +{ + struct tcp_pcb *pcb; + + pcb = conn->pcb.tcp; + tcp_arg(pcb, conn); + tcp_recv(pcb, recv_tcp); + tcp_sent(pcb, sent_tcp); + tcp_poll(pcb, poll_tcp, NETCONN_TCP_POLL_INTERVAL); + tcp_err(pcb, err_tcp); +} + +/** + * Accept callback function for TCP netconns. + * Allocates a new netconn and posts that to conn->acceptmbox. + * + * @see tcp.h (struct tcp_pcb_listen.accept) for parameters and return value + */ +static err_t +accept_function(void *arg, struct tcp_pcb *newpcb, err_t err) +{ + struct netconn *newconn; + struct netconn *conn = (struct netconn *)arg; + + if (conn == NULL) { + return ERR_VAL; + } + if (!sys_mbox_valid(&conn->acceptmbox)) { + LWIP_DEBUGF(API_MSG_DEBUG, ("accept_function: acceptmbox already deleted\n")); + return ERR_VAL; + } + + if (newpcb == NULL) { + /* out-of-pcbs during connect: pass on this error to the application */ + if (sys_mbox_trypost(&conn->acceptmbox, &netconn_aborted) == ERR_OK) { + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); + } + return ERR_VAL; + } + + LWIP_DEBUGF(API_MSG_DEBUG, ("accept_function: newpcb->tate: %s\n", tcp_debug_state_str(newpcb->state))); + + /* We have to set the callback here even though + * the new socket is unknown. newconn->socket is marked as -1. */ + newconn = netconn_alloc(conn->type, conn->callback); + if (newconn == NULL) { + /* outof netconns: pass on this error to the application */ + if (sys_mbox_trypost(&conn->acceptmbox, &netconn_aborted) == ERR_OK) { + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); + } + return ERR_MEM; + } + newconn->pcb.tcp = newpcb; + setup_tcp(newconn); + /* no protection: when creating the pcb, the netconn is not yet known + to the application thread */ + newconn->last_err = err; + + /* handle backlog counter */ + tcp_backlog_delayed(newpcb); + + if (sys_mbox_trypost(&conn->acceptmbox, newconn) != ERR_OK) { + ESP_STATS_DROP_INC(esp.acceptmbox_post_fail); + /* When returning != ERR_OK, the pcb is aborted in tcp_process(), + so do nothing here! */ + /* remove all references to this netconn from the pcb */ + struct tcp_pcb* pcb = newconn->pcb.tcp; + tcp_arg(pcb, NULL); + tcp_recv(pcb, NULL); + tcp_sent(pcb, NULL); + tcp_poll(pcb, NULL, 0); + tcp_err(pcb, NULL); + /* remove reference from to the pcb from this netconn */ + newconn->pcb.tcp = NULL; +#if ESP_THREAD_SAFE + sys_mbox_set_owner(&newconn->recvmbox, NULL); +#endif + /* no need to drain since we know the recvmbox is empty. */ + sys_mbox_free(&newconn->recvmbox); + sys_mbox_set_invalid(&newconn->recvmbox); + netconn_free(newconn); + return ERR_MEM; + } else { + /* Register event with callback */ + API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); + } + + return ERR_OK; +} +#endif /* LWIP_TCP */ + +/** + * Create a new pcb of a specific type. + * Called from lwip_netconn_do_newconn(). + * + * @param msg the api_msg_msg describing the connection type + */ +static void +pcb_new(struct api_msg *msg) +{ + enum lwip_ip_addr_type iptype = IPADDR_TYPE_V4; + + LWIP_ASSERT("pcb_new: pcb already allocated", msg->conn->pcb.tcp == NULL); + +#if LWIP_IPV6 && LWIP_IPV4 + /* IPv6: Dual-stack by default, unless netconn_set_ipv6only() is called */ + if(NETCONNTYPE_ISIPV6(netconn_type(msg->conn))) { + iptype = IPADDR_TYPE_ANY; + } +#endif + + /* Allocate a PCB for this connection */ + switch(NETCONNTYPE_GROUP(msg->conn->type)) { +#if LWIP_RAW + case NETCONN_RAW: + msg->conn->pcb.raw = raw_new_ip_type(iptype, msg->msg.n.proto); + if (msg->conn->pcb.raw != NULL) { +#if LWIP_IPV6 + /* ICMPv6 packets should always have checksum calculated by the stack as per RFC 3542 chapter 3.1 */ + if (NETCONNTYPE_ISIPV6(msg->conn->type) && msg->conn->pcb.raw->protocol == IP6_NEXTH_ICMP6) { + msg->conn->pcb.raw->chksum_reqd = 1; + msg->conn->pcb.raw->chksum_offset = 2; + } +#endif /* LWIP_IPV6 */ + raw_recv(msg->conn->pcb.raw, recv_raw, msg->conn); + } + break; +#endif /* LWIP_RAW */ +#if LWIP_UDP + case NETCONN_UDP: + msg->conn->pcb.udp = udp_new_ip_type(iptype); + if (msg->conn->pcb.udp != NULL) { +#if LWIP_UDPLITE + if (NETCONNTYPE_ISUDPLITE(msg->conn->type)) { + udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_UDPLITE); + } +#endif /* LWIP_UDPLITE */ + if (NETCONNTYPE_ISUDPNOCHKSUM(msg->conn->type)) { + udp_setflags(msg->conn->pcb.udp, UDP_FLAGS_NOCHKSUM); + } + udp_recv(msg->conn->pcb.udp, recv_udp, msg->conn); + } + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + msg->conn->pcb.tcp = tcp_new_ip_type(iptype); + if (msg->conn->pcb.tcp != NULL) { + setup_tcp(msg->conn); + } + break; +#endif /* LWIP_TCP */ + default: + /* Unsupported netconn type, e.g. protocol disabled */ + msg->err = ERR_VAL; + return; + } + if (msg->conn->pcb.ip == NULL) { + msg->err = ERR_MEM; + } +#if ESP_LWIP +#if LWIP_IPV4 && LWIP_IPV6 + else { + if (NETCONNTYPE_ISIPV6(msg->conn->type)) { + /* Convert IPv4 PCB manually to an IPv6 PCB */ + IP_SET_TYPE_VAL(msg->conn->pcb.ip->local_ip, IPADDR_TYPE_V6); + IP_SET_TYPE_VAL(msg->conn->pcb.ip->remote_ip, IPADDR_TYPE_V6); + } + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ +#endif +} + +/** + * Create a new pcb of a specific type inside a netconn. + * Called from netconn_new_with_proto_and_callback. + * + * @param m the api_msg_msg describing the connection type + */ +void +lwip_netconn_do_newconn(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + + msg->err = ERR_OK; + if (msg->conn->pcb.tcp == NULL) { + pcb_new(msg); + } + /* Else? This "new" connection already has a PCB allocated. */ + /* Is this an error condition? Should it be deleted? */ + /* We currently just are happy and return. */ + + TCPIP_APIMSG_ACK(msg); +} + +/** + * Create a new netconn (of a specific type) that has a callback function. + * The corresponding pcb is NOT created! + * + * @param t the type of 'connection' to create (@see enum netconn_type) + * @param callback a function to call on status changes (RX available, TX'ed) + * @return a newly allocated struct netconn or + * NULL on memory error + */ +struct netconn* +netconn_alloc(enum netconn_type t, netconn_callback callback) +{ + struct netconn *conn; + int size; + + conn = (struct netconn *)memp_malloc(MEMP_NETCONN); + if (conn == NULL) { + return NULL; + } + + conn->last_err = ERR_OK; + conn->type = t; + conn->pcb.tcp = NULL; + + /* If all sizes are the same, every compiler should optimize this switch to nothing */ + switch(NETCONNTYPE_GROUP(t)) { +#if LWIP_RAW + case NETCONN_RAW: + size = DEFAULT_RAW_RECVMBOX_SIZE; + break; +#endif /* LWIP_RAW */ +#if LWIP_UDP + case NETCONN_UDP: + size = DEFAULT_UDP_RECVMBOX_SIZE; + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + size = DEFAULT_TCP_RECVMBOX_SIZE; + break; +#endif /* LWIP_TCP */ + default: + LWIP_ASSERT("netconn_alloc: undefined netconn_type", 0); + goto free_and_return; + } + + if (sys_mbox_new(&conn->recvmbox, size) != ERR_OK) { + goto free_and_return; + } +#if !LWIP_NETCONN_SEM_PER_THREAD + if (sys_sem_new(&conn->op_completed, 0) != ERR_OK) { + sys_mbox_free(&conn->recvmbox); + goto free_and_return; + } +#endif + +#if ESP_THREAD_SAFE + sys_mbox_set_owner(&conn->recvmbox, conn); +#endif + +#if LWIP_TCP +#if ESP_THREAD_SAFE + /* Init acceptmbox to NULL because sys_mbox_set_invalid is implemented as empty macro */ + conn->acceptmbox = NULL; +#endif + sys_mbox_set_invalid(&conn->acceptmbox); +#endif + conn->state = NETCONN_NONE; +#if LWIP_SOCKET + /* initialize socket to -1 since 0 is a valid socket */ + conn->socket = -1; +#endif /* LWIP_SOCKET */ + conn->callback = callback; +#if LWIP_TCP + conn->current_msg = NULL; + conn->write_offset = 0; +#endif /* LWIP_TCP */ +#if LWIP_SO_SNDTIMEO + conn->send_timeout = 0; +#endif /* LWIP_SO_SNDTIMEO */ +#if LWIP_SO_RCVTIMEO + conn->recv_timeout = 0; +#endif /* LWIP_SO_RCVTIMEO */ +#if LWIP_SO_RCVBUF + conn->recv_bufsize = RECV_BUFSIZE_DEFAULT; + conn->recv_avail = 0; +#endif /* LWIP_SO_RCVBUF */ +#if LWIP_SO_LINGER + conn->linger = -1; +#endif /* LWIP_SO_LINGER */ + conn->flags = 0; + return conn; +free_and_return: + memp_free(MEMP_NETCONN, conn); + return NULL; +} + +/** + * Delete a netconn and all its resources. + * The pcb is NOT freed (since we might not be in the right thread context do this). + * + * @param conn the netconn to free + */ +void +netconn_free(struct netconn *conn) +{ + LWIP_ASSERT("PCB must be deallocated outside this function", conn->pcb.tcp == NULL); +#if !ESP_THREAD_SAFE + LWIP_ASSERT("recvmbox must be deallocated before calling this function", + !sys_mbox_valid(&conn->recvmbox)); + +#if LWIP_TCP + LWIP_ASSERT("acceptmbox must be deallocated before calling this function", + !sys_mbox_valid(&conn->acceptmbox)); +#endif /* LWIP_TCP */ +#else /* !ESP_THREAD_SAFE */ + sys_mbox_free(&conn->recvmbox); + +#if LWIP_TCP + sys_mbox_free(&conn->acceptmbox); +#endif /* LWIP TCP */ +#endif /* !ESP_THREAD_SAFE */ + +#if !LWIP_NETCONN_SEM_PER_THREAD + sys_sem_free(&conn->op_completed); + sys_sem_set_invalid(&conn->op_completed); +#endif + + memp_free(MEMP_NETCONN, conn); +} + +/** + * Delete rcvmbox and acceptmbox of a netconn and free the left-over data in + * these mboxes + * + * @param conn the netconn to free + * @bytes_drained bytes drained from recvmbox + * @accepts_drained pending connections drained from acceptmbox + */ +static void +netconn_drain(struct netconn *conn) +{ + void *mem; +#if LWIP_TCP + struct pbuf *p; +#endif /* LWIP_TCP */ + + /* This runs in tcpip_thread, so we don't need to lock against rx packets */ + + /* Delete and drain the recvmbox. */ + if (sys_mbox_valid(&conn->recvmbox)) { + while (sys_mbox_tryfetch(&conn->recvmbox, &mem) != SYS_MBOX_EMPTY) { +#if LWIP_TCP + if (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP) { + if (mem != NULL) { + p = (struct pbuf*)mem; + /* pcb might be set to NULL already by err_tcp() */ + if (conn->pcb.tcp != NULL) { + tcp_recved(conn->pcb.tcp, p->tot_len); + } + pbuf_free(p); + } + } else +#endif /* LWIP_TCP */ + { + netbuf_delete((struct netbuf *)mem); + } + } + sys_mbox_free(&conn->recvmbox); + sys_mbox_set_invalid(&conn->recvmbox); + } + + /* Delete and drain the acceptmbox. */ +#if LWIP_TCP + if (sys_mbox_valid(&conn->acceptmbox)) { + while (sys_mbox_tryfetch(&conn->acceptmbox, &mem) != SYS_MBOX_EMPTY) { + if (mem != &netconn_aborted) { + struct netconn *newconn = (struct netconn *)mem; + /* Only tcp pcbs have an acceptmbox, so no need to check conn->type */ + /* pcb might be set to NULL already by err_tcp() */ + /* drain recvmbox */ + netconn_drain(newconn); + if (newconn->pcb.tcp != NULL) { + tcp_abort(newconn->pcb.tcp); + newconn->pcb.tcp = NULL; + } + netconn_free(newconn); + } + } + sys_mbox_free(&conn->acceptmbox); + sys_mbox_set_invalid(&conn->acceptmbox); + } +#endif /* LWIP_TCP */ +} + +#if LWIP_TCP +/** + * Internal helper function to close a TCP netconn: since this sometimes + * doesn't work at the first attempt, this function is called from multiple + * places. + * + * @param conn the TCP netconn to close + */ +static err_t +#if ESP_LWIP +lwip_netconn_do_close_internal(struct netconn *conn WRITE_DELAYED_PARAM SIG_CLOSE_PARAM) +#else +lwip_netconn_do_close_internal(struct netconn *conn WRITE_DELAYED_PARAM) +#endif +{ + err_t err; + u8_t shut, shut_rx, shut_tx, close; + u8_t close_finished = 0; + struct tcp_pcb* tpcb; +#if LWIP_SO_LINGER + u8_t linger_wait_required = 0; +#endif /* LWIP_SO_LINGER */ + + LWIP_ASSERT("invalid conn", (conn != NULL)); + LWIP_ASSERT("this is for tcp netconns only", (NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP)); + LWIP_ASSERT("conn must be in state NETCONN_CLOSE", (conn->state == NETCONN_CLOSE)); + LWIP_ASSERT("pcb already closed", (conn->pcb.tcp != NULL)); + LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL); + + tpcb = conn->pcb.tcp; + shut = conn->current_msg->msg.sd.shut; + shut_rx = shut & NETCONN_SHUT_RD; + shut_tx = shut & NETCONN_SHUT_WR; + /* shutting down both ends is the same as closing + (also if RD or WR side was shut down before already) */ + if (shut == NETCONN_SHUT_RDWR) { + close = 1; + } else if (shut_rx && + ((tpcb->state == FIN_WAIT_1) || + (tpcb->state == FIN_WAIT_2) || + (tpcb->state == CLOSING))) { + close = 1; + } else if (shut_tx && ((tpcb->flags & TF_RXCLOSED) != 0)) { + close = 1; + } else { + close = 0; + } + + /* Set back some callback pointers */ + if (close) { + tcp_arg(tpcb, NULL); + } + if (tpcb->state == LISTEN) { + tcp_accept(tpcb, NULL); + } else { + /* some callbacks have to be reset if tcp_close is not successful */ + if (shut_rx) { + tcp_recv(tpcb, NULL); + tcp_accept(tpcb, NULL); + } + if (shut_tx) { + tcp_sent(tpcb, NULL); + } + if (close) { + tcp_poll(tpcb, NULL, 0); + tcp_err(tpcb, NULL); + } + } + /* Try to close the connection */ + if (close) { +#if LWIP_SO_LINGER + /* check linger possibilites before calling tcp_close */ + err = ERR_OK; + /* linger enabled/required at all? (i.e. is there untransmitted data left?) */ + if ((conn->linger >= 0) && (conn->pcb.tcp->unsent || conn->pcb.tcp->unacked)) { + if ((conn->linger == 0)) { + /* data left but linger prevents waiting */ + tcp_abort(tpcb); + tpcb = NULL; + } else if (conn->linger > 0) { + /* data left and linger says we should wait */ + if (netconn_is_nonblocking(conn)) { + /* data left on a nonblocking netconn -> cannot linger */ + err = ERR_WOULDBLOCK; + } else if ((s32_t)(sys_now() - conn->current_msg->msg.sd.time_started) >= + (conn->linger * 1000)) { + /* data left but linger timeout has expired (this happens on further + calls to this function through poll_tcp */ + tcp_abort(tpcb); + tpcb = NULL; + } else { + /* data left -> need to wait for ACK after successful close */ + linger_wait_required = 1; + } + } + } + if ((err == ERR_OK) && (tpcb != NULL)) +#endif /* LWIP_SO_LINGER */ + { + err = tcp_close(tpcb); + } + } else { + err = tcp_shutdown(tpcb, shut_rx, shut_tx); + } + if (err == ERR_OK) { + close_finished = 1; +#if LWIP_SO_LINGER + if (linger_wait_required) { + /* wait for ACK of all unsent/unacked data by just getting called again */ + close_finished = 0; + err = ERR_INPROGRESS; + } +#endif /* LWIP_SO_LINGER */ + } else { + if (err == ERR_MEM) { + /* Closing failed because of memory shortage, try again later. Even for + nonblocking netconns, we have to wait since no standard socket application + is prepared for close failing because of resource shortage. + Check the timeout: this is kind of an lwip addition to the standard sockets: + we wait for some time when failing to allocate a segment for the FIN */ +#if LWIP_SO_SNDTIMEO || LWIP_SO_LINGER + s32_t close_timeout = LWIP_TCP_CLOSE_TIMEOUT_MS_DEFAULT; +#if LWIP_SO_SNDTIMEO + if (conn->send_timeout > 0) { + close_timeout = conn->send_timeout; + } +#endif /* LWIP_SO_SNDTIMEO */ +#if LWIP_SO_LINGER + if (conn->linger >= 0) { + /* use linger timeout (seconds) */ + close_timeout = conn->linger * 1000U; + } +#endif + if ((s32_t)(sys_now() - conn->current_msg->msg.sd.time_started) >= close_timeout) { +#else /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ + if (conn->current_msg->msg.sd.polls_left == 0) { +#endif /* LWIP_SO_SNDTIMEO || LWIP_SO_LINGER */ + close_finished = 1; + if (close) { + /* in this case, we want to RST the connection */ + tcp_abort(tpcb); + err = ERR_OK; + } + } + } else { + /* Closing failed for a non-memory error: give up */ + close_finished = 1; + } + } + if (close_finished) { + /* Closing done (succeeded, non-memory error, nonblocking error or timeout) */ + sys_sem_t* op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg); + conn->current_msg->err = err; + conn->state = NETCONN_NONE; + if (err == ERR_OK) { + if (close) { + /* Set back some callback pointers as conn is going away */ + conn->pcb.tcp = NULL; + /* Trigger select() in socket layer. Make sure everybody notices activity + on the connection, error first! */ + API_EVENT(conn, NETCONN_EVT_ERROR, 0); + } + if (shut_rx) { + API_EVENT(conn, NETCONN_EVT_RCVPLUS, 0); + } + if (shut_tx) { + API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0); + } + } + NETCONN_SET_SAFE_ERR(conn, err); +#if LWIP_TCPIP_CORE_LOCKING + if (delayed) +#endif + { + /* wake up the application task */ +#if ESP_LWIP + if (sig_close) { + conn->current_msg = NULL; + sys_sem_signal(op_completed_sem); + } +#else + sys_sem_signal(op_completed_sem); +#endif + } + return ERR_OK; + } + if (!close_finished) { + /* Closing failed and we want to wait: restore some of the callbacks */ + /* Closing of listen pcb will never fail! */ + LWIP_ASSERT("Closing a listen pcb may not fail!", (tpcb->state != LISTEN)); + if (shut_tx) { + tcp_sent(tpcb, sent_tcp); + } + /* when waiting for close, set up poll interval to 500ms */ + tcp_poll(tpcb, poll_tcp, 1); + tcp_err(tpcb, err_tcp); + tcp_arg(tpcb, conn); + /* don't restore recv callback: we don't want to receive any more data */ + } + /* If closing didn't succeed, we get called again either + from poll_tcp or from sent_tcp */ + LWIP_ASSERT("err != ERR_OK", err != ERR_OK); + return err; +} +#endif /* LWIP_TCP */ + +/** + * Delete the pcb inside a netconn. + * Called from netconn_delete. + * + * @param m the api_msg_msg pointing to the connection + */ +void +lwip_netconn_do_delconn(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + + enum netconn_state state = msg->conn->state; + LWIP_ASSERT("netconn state error", /* this only happens for TCP netconns */ + (state == NETCONN_NONE) || (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP)); +#if ESP_LWIP + msg->err = ERR_OK; +#endif + +#if LWIP_NETCONN_FULLDUPLEX + /* In full duplex mode, blocking write/connect is aborted with ERR_CLSD */ + if (state != NETCONN_NONE) { + if ((state == NETCONN_WRITE) || + ((state == NETCONN_CONNECT) && !IN_NONBLOCKING_CONNECT(msg->conn))) { + /* close requested, abort running write/connect */ + sys_sem_t* op_completed_sem; + LWIP_ASSERT("msg->conn->current_msg != NULL", msg->conn->current_msg != NULL); + op_completed_sem = LWIP_API_MSG_SEM(msg->conn->current_msg); + msg->conn->current_msg->err = ERR_CLSD; + msg->conn->current_msg = NULL; + msg->conn->write_offset = 0; + msg->conn->state = NETCONN_NONE; + NETCONN_SET_SAFE_ERR(msg->conn, ERR_CLSD); +#if ESP_LWIP + msg->err = ERR_INPROGRESS; +#endif + sys_sem_signal(op_completed_sem); + } + } +#else /* LWIP_NETCONN_FULLDUPLEX */ + if (((state != NETCONN_NONE) && + (state != NETCONN_LISTEN) && + (state != NETCONN_CONNECT)) || + ((state == NETCONN_CONNECT) && !IN_NONBLOCKING_CONNECT(msg->conn))) { + /* This means either a blocking write or blocking connect is running + (nonblocking write returns and sets state to NONE) */ + msg->err = ERR_INPROGRESS; + } else +#endif /* LWIP_NETCONN_FULLDUPLEX */ + { +#if !ESP_LWIP + LWIP_ASSERT("blocking connect in progress", + (state != NETCONN_CONNECT) || IN_NONBLOCKING_CONNECT(msg->conn)); + msg->err = ERR_OK; +#endif + /* Drain and delete mboxes */ + netconn_drain(msg->conn); + + if (msg->conn->pcb.tcp != NULL) { + + switch (NETCONNTYPE_GROUP(msg->conn->type)) { +#if LWIP_RAW + case NETCONN_RAW: + raw_remove(msg->conn->pcb.raw); + break; +#endif /* LWIP_RAW */ +#if LWIP_UDP + case NETCONN_UDP: + msg->conn->pcb.udp->recv_arg = NULL; + udp_remove(msg->conn->pcb.udp); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL && + msg->conn->write_offset == 0); + msg->conn->state = NETCONN_CLOSE; + msg->msg.sd.shut = NETCONN_SHUT_RDWR; + msg->conn->current_msg = msg; +#if LWIP_TCPIP_CORE_LOCKING +#if ESP_LWIP + if (lwip_netconn_do_close_internal(msg->conn, 0, SIG_CLOSE_TRUE) != ERR_OK) { +#else + if (lwip_netconn_do_close_internal(msg->conn, 0) != ERR_OK) { +#endif + LWIP_ASSERT("state!", msg->conn->state == NETCONN_CLOSE); + UNLOCK_TCPIP_CORE(); + sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0); + LOCK_TCPIP_CORE(); + LWIP_ASSERT("state!", msg->conn->state == NETCONN_NONE); + } +#else /* LWIP_TCPIP_CORE_LOCKING */ +#if ESP_LWIP + lwip_netconn_do_close_internal(msg->conn, SIG_CLOSE_TRUE); +#else + lwip_netconn_do_close_internal(msg->conn); +#endif +#endif /* LWIP_TCPIP_CORE_LOCKING */ + /* API_EVENT is called inside lwip_netconn_do_close_internal, before releasing + the application thread, so we can return at this point! */ + return; +#endif /* LWIP_TCP */ + default: + break; + } + msg->conn->pcb.tcp = NULL; + } + /* tcp netconns don't come here! */ + + /* @todo: this lets select make the socket readable and writable, + which is wrong! errfd instead? */ + API_EVENT(msg->conn, NETCONN_EVT_RCVPLUS, 0); + API_EVENT(msg->conn, NETCONN_EVT_SENDPLUS, 0); + } + if (sys_sem_valid(LWIP_API_MSG_SEM(msg))) { + TCPIP_APIMSG_ACK(msg); + } +} + +/** + * Bind a pcb contained in a netconn + * Called from netconn_bind. + * + * @param m the api_msg_msg pointing to the connection and containing + * the IP address and port to bind to + */ +void +lwip_netconn_do_bind(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + + if (ERR_IS_FATAL(msg->conn->last_err)) { + msg->err = msg->conn->last_err; + } else { + msg->err = ERR_VAL; + if (msg->conn->pcb.tcp != NULL) { + +#if ESP_LWIP +#if LWIP_IPV4 && LWIP_IPV6 + /* "Socket API like" dual-stack support: If IP to bind to is IP6_ADDR_ANY, + * and NETCONN_FLAG_IPV6_V6ONLY is NOT set, use IP_ANY_TYPE to bind + */ + if (ip_addr_cmp(API_EXPR_REF(msg->msg.bc.ipaddr), IP6_ADDR_ANY) && + (netconn_get_ipv6only(msg->conn) == 0)) { + /* change PCB type to IPADDR_TYPE_ANY */ + IP_SET_TYPE_VAL(msg->conn->pcb.ip->local_ip, IPADDR_TYPE_ANY); + IP_SET_TYPE_VAL(msg->conn->pcb.ip->remote_ip, IPADDR_TYPE_ANY); + + /* bind to IPADDR_TYPE_ANY */ + API_EXPR_REF(msg->msg.bc.ipaddr) = IP_ANY_TYPE; + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ +#endif + + switch (NETCONNTYPE_GROUP(msg->conn->type)) { +#if LWIP_RAW + case NETCONN_RAW: + msg->err = raw_bind(msg->conn->pcb.raw, API_EXPR_REF(msg->msg.bc.ipaddr)); + break; +#endif /* LWIP_RAW */ +#if LWIP_UDP + case NETCONN_UDP: + msg->err = udp_bind(msg->conn->pcb.udp, API_EXPR_REF(msg->msg.bc.ipaddr), msg->msg.bc.port); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + msg->err = tcp_bind(msg->conn->pcb.tcp, API_EXPR_REF(msg->msg.bc.ipaddr), msg->msg.bc.port); + break; +#endif /* LWIP_TCP */ + default: + break; + } + } + } + TCPIP_APIMSG_ACK(msg); +} + +#if LWIP_TCP +/** + * TCP callback function if a connection (opened by tcp_connect/lwip_netconn_do_connect) has + * been established (or reset by the remote host). + * + * @see tcp.h (struct tcp_pcb.connected) for parameters and return values + */ +static err_t +lwip_netconn_do_connected(void *arg, struct tcp_pcb *pcb, err_t err) +{ + struct netconn *conn; + int was_blocking; + sys_sem_t* op_completed_sem = NULL; + + LWIP_UNUSED_ARG(pcb); + + conn = (struct netconn *)arg; + + if (conn == NULL) { + return ERR_VAL; + } + + LWIP_ASSERT("conn->state == NETCONN_CONNECT", conn->state == NETCONN_CONNECT); + LWIP_ASSERT("(conn->current_msg != NULL) || conn->in_non_blocking_connect", + (conn->current_msg != NULL) || IN_NONBLOCKING_CONNECT(conn)); + + if (conn->current_msg != NULL) { + conn->current_msg->err = err; + op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg); + } + if ((NETCONNTYPE_GROUP(conn->type) == NETCONN_TCP) && (err == ERR_OK)) { + setup_tcp(conn); + } + was_blocking = !IN_NONBLOCKING_CONNECT(conn); + SET_NONBLOCKING_CONNECT(conn, 0); + LWIP_ASSERT("blocking connect state error", + (was_blocking && op_completed_sem != NULL) || + (!was_blocking && op_completed_sem == NULL)); + conn->current_msg = NULL; + conn->state = NETCONN_NONE; + NETCONN_SET_SAFE_ERR(conn, ERR_OK); + API_EVENT(conn, NETCONN_EVT_SENDPLUS, 0); + + if (was_blocking) { + sys_sem_signal(op_completed_sem); + } + return ERR_OK; +} +#endif /* LWIP_TCP */ + +/** + * Connect a pcb contained inside a netconn + * Called from netconn_connect. + * + * @param m the api_msg_msg pointing to the connection and containing + * the IP address and port to connect to + */ +void +lwip_netconn_do_connect(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + + if (msg->conn->pcb.tcp == NULL) { + /* This may happen when calling netconn_connect() a second time */ + msg->err = ERR_CLSD; + } else { + switch (NETCONNTYPE_GROUP(msg->conn->type)) { +#if LWIP_RAW + case NETCONN_RAW: + msg->err = raw_connect(msg->conn->pcb.raw, API_EXPR_REF(msg->msg.bc.ipaddr)); + break; +#endif /* LWIP_RAW */ +#if LWIP_UDP + case NETCONN_UDP: + msg->err = udp_connect(msg->conn->pcb.udp, API_EXPR_REF(msg->msg.bc.ipaddr), msg->msg.bc.port); + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + /* Prevent connect while doing any other action. */ + if (msg->conn->state == NETCONN_CONNECT) { + msg->err = ERR_ALREADY; + } else if (msg->conn->state != NETCONN_NONE) { + msg->err = ERR_ISCONN; + } else { + setup_tcp(msg->conn); + msg->err = tcp_connect(msg->conn->pcb.tcp, API_EXPR_REF(msg->msg.bc.ipaddr), + msg->msg.bc.port, lwip_netconn_do_connected); + if (msg->err == ERR_OK) { + u8_t non_blocking = netconn_is_nonblocking(msg->conn); + msg->conn->state = NETCONN_CONNECT; + SET_NONBLOCKING_CONNECT(msg->conn, non_blocking); + if (non_blocking) { + msg->err = ERR_INPROGRESS; + } else { + msg->conn->current_msg = msg; + /* sys_sem_signal() is called from lwip_netconn_do_connected (or err_tcp()), + when the connection is established! */ +#if LWIP_TCPIP_CORE_LOCKING + LWIP_ASSERT("state!", msg->conn->state == NETCONN_CONNECT); + UNLOCK_TCPIP_CORE(); + sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0); + LOCK_TCPIP_CORE(); + LWIP_ASSERT("state!", msg->conn->state != NETCONN_CONNECT); +#endif /* LWIP_TCPIP_CORE_LOCKING */ + return; + } + } + } + break; +#endif /* LWIP_TCP */ + default: + LWIP_ERROR("Invalid netconn type", 0, do{ msg->err = ERR_VAL; }while(0)); + break; + } + } + /* For all other protocols, netconn_connect() calls TCPIP_APIMSG(), + so use TCPIP_APIMSG_ACK() here. */ + TCPIP_APIMSG_ACK(msg); +} + +/** + * Disconnect a pcb contained inside a netconn + * Only used for UDP netconns. + * Called from netconn_disconnect. + * + * @param m the api_msg_msg pointing to the connection to disconnect + */ +void +lwip_netconn_do_disconnect(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + +#if LWIP_UDP + if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_UDP) { + udp_disconnect(msg->conn->pcb.udp); + msg->err = ERR_OK; + } else +#endif /* LWIP_UDP */ + { + msg->err = ERR_VAL; + } + TCPIP_APIMSG_ACK(msg); +} + +#if LWIP_TCP +/** + * Set a TCP pcb contained in a netconn into listen mode + * Called from netconn_listen. + * + * @param m the api_msg_msg pointing to the connection + */ +void +lwip_netconn_do_listen(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + + if (ERR_IS_FATAL(msg->conn->last_err)) { + msg->err = msg->conn->last_err; + } else { + msg->err = ERR_CONN; + if (msg->conn->pcb.tcp != NULL) { + if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) { + if (msg->conn->state == NETCONN_NONE) { + struct tcp_pcb* lpcb; + if (msg->conn->pcb.tcp->state != CLOSED) { + /* connection is not closed, cannot listen */ + msg->err = ERR_VAL; + } else { + err_t err; + u8_t backlog; +#if TCP_LISTEN_BACKLOG + backlog = msg->msg.lb.backlog; +#else /* TCP_LISTEN_BACKLOG */ + backlog = TCP_DEFAULT_LISTEN_BACKLOG; +#endif /* TCP_LISTEN_BACKLOG */ +#if LWIP_IPV4 && LWIP_IPV6 + /* "Socket API like" dual-stack support: If IP to listen to is IP6_ADDR_ANY, + * and NETCONN_FLAG_IPV6_V6ONLY is NOT set, use IP_ANY_TYPE to listen + */ + if (ip_addr_cmp(&msg->conn->pcb.ip->local_ip, IP6_ADDR_ANY) && + (netconn_get_ipv6only(msg->conn) == 0)) { + /* change PCB type to IPADDR_TYPE_ANY */ + IP_SET_TYPE_VAL(msg->conn->pcb.tcp->local_ip, IPADDR_TYPE_ANY); + IP_SET_TYPE_VAL(msg->conn->pcb.tcp->remote_ip, IPADDR_TYPE_ANY); + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + + lpcb = tcp_listen_with_backlog_and_err(msg->conn->pcb.tcp, backlog, &err); + + if (lpcb == NULL) { + /* in this case, the old pcb is still allocated */ + msg->err = err; + } else { + /* delete the recvmbox and allocate the acceptmbox */ + if (sys_mbox_valid(&msg->conn->recvmbox)) { + /** @todo: should we drain the recvmbox here? */ + sys_mbox_free(&msg->conn->recvmbox); + sys_mbox_set_invalid(&msg->conn->recvmbox); + } + msg->err = ERR_OK; + if (!sys_mbox_valid(&msg->conn->acceptmbox)) { + msg->err = sys_mbox_new(&msg->conn->acceptmbox, DEFAULT_ACCEPTMBOX_SIZE); + } + if (msg->err == ERR_OK) { +#if ESP_THREAD_SAFE + sys_mbox_set_owner(&msg->conn->acceptmbox, msg->conn); +#endif + msg->conn->state = NETCONN_LISTEN; + msg->conn->pcb.tcp = lpcb; + tcp_arg(msg->conn->pcb.tcp, msg->conn); + tcp_accept(msg->conn->pcb.tcp, accept_function); + } else { + /* since the old pcb is already deallocated, free lpcb now */ + tcp_close(lpcb); + msg->conn->pcb.tcp = NULL; + } + } + } + } else if (msg->conn->state == NETCONN_LISTEN) { + /* already listening, allow updating of the backlog */ + msg->err = ERR_OK; + tcp_backlog_set(msg->conn->pcb.tcp, msg->msg.lb.backlog); + } + } else { + msg->err = ERR_ARG; + } + } + } + TCPIP_APIMSG_ACK(msg); +} +#endif /* LWIP_TCP */ + +/** + * Send some data on a RAW or UDP pcb contained in a netconn + * Called from netconn_send + * + * @param m the api_msg_msg pointing to the connection + */ +void +lwip_netconn_do_send(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + + if (ERR_IS_FATAL(msg->conn->last_err)) { + msg->err = msg->conn->last_err; +#if ESP_LWIP +#if LWIP_IPV4 && LWIP_IPV6 + } else if ((msg->conn->flags & NETCONN_FLAG_IPV6_V6ONLY) && + IP_IS_V4MAPPEDV6(&msg->msg.b->addr)) { + LWIP_DEBUGF(API_MSG_DEBUG, ("lwip_netconn_do_send: Dropping IPv4 packet on IPv6-only socket")); + msg->err = ERR_VAL; +#endif /* LWIP_IPV4 && LWIP_IPV6 */ +#endif + } else { + msg->err = ERR_CONN; + if (msg->conn->pcb.tcp != NULL) { + switch (NETCONNTYPE_GROUP(msg->conn->type)) { +#if LWIP_RAW + case NETCONN_RAW: + if (ip_addr_isany(&msg->msg.b->addr) || IP_IS_ANY_TYPE_VAL(msg->msg.b->addr)) { + msg->err = raw_send(msg->conn->pcb.raw, msg->msg.b->p); + } else { + msg->err = raw_sendto(msg->conn->pcb.raw, msg->msg.b->p, &msg->msg.b->addr); + } + break; +#endif +#if LWIP_UDP + case NETCONN_UDP: +#if LWIP_CHECKSUM_ON_COPY + if (ip_addr_isany(&msg->msg.b->addr) || IP_IS_ANY_TYPE_VAL(msg->msg.b->addr)) { + msg->err = udp_send_chksum(msg->conn->pcb.udp, msg->msg.b->p, + msg->msg.b->flags & NETBUF_FLAG_CHKSUM, msg->msg.b->toport_chksum); + } else { + msg->err = udp_sendto_chksum(msg->conn->pcb.udp, msg->msg.b->p, + &msg->msg.b->addr, msg->msg.b->port, + msg->msg.b->flags & NETBUF_FLAG_CHKSUM, msg->msg.b->toport_chksum); + } +#else /* LWIP_CHECKSUM_ON_COPY */ + if (ip_addr_isany_val(msg->msg.b->addr) || IP_IS_ANY_TYPE_VAL(msg->msg.b->addr)) { + msg->err = udp_send(msg->conn->pcb.udp, msg->msg.b->p); + } else { + msg->err = udp_sendto(msg->conn->pcb.udp, msg->msg.b->p, &msg->msg.b->addr, msg->msg.b->port); + } +#endif /* LWIP_CHECKSUM_ON_COPY */ + break; +#endif /* LWIP_UDP */ + default: + break; + } + } + } + TCPIP_APIMSG_ACK(msg); +} + +#if LWIP_TCP +/** + * Indicate data has been received from a TCP pcb contained in a netconn + * Called from netconn_recv + * + * @param m the api_msg_msg pointing to the connection + */ +void +lwip_netconn_do_recv(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + + msg->err = ERR_OK; + if (msg->conn->pcb.tcp != NULL) { + if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) { + u32_t remaining = msg->msg.r.len; + do { + u16_t recved = (remaining > 0xffff) ? 0xffff : (u16_t)remaining; + tcp_recved(msg->conn->pcb.tcp, recved); + remaining -= recved; + } while (remaining != 0); + } + } + TCPIP_APIMSG_ACK(msg); +} + +#if TCP_LISTEN_BACKLOG +/** Indicate that a TCP pcb has been accepted + * Called from netconn_accept + * + * @param m the api_msg_msg pointing to the connection + */ +void +lwip_netconn_do_accepted(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + + msg->err = ERR_OK; + if (msg->conn->pcb.tcp != NULL) { + if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) { + tcp_backlog_accepted(msg->conn->pcb.tcp); + } + } + TCPIP_APIMSG_ACK(msg); +} +#endif /* TCP_LISTEN_BACKLOG */ + +/** + * See if more data needs to be written from a previous call to netconn_write. + * Called initially from lwip_netconn_do_write. If the first call can't send all data + * (because of low memory or empty send-buffer), this function is called again + * from sent_tcp() or poll_tcp() to send more data. If all data is sent, the + * blocking application thread (waiting in netconn_write) is released. + * + * @param conn netconn (that is currently in state NETCONN_WRITE) to process + * @return ERR_OK + * ERR_MEM if LWIP_TCPIP_CORE_LOCKING=1 and sending hasn't yet finished + */ +static err_t +lwip_netconn_do_writemore(struct netconn *conn WRITE_DELAYED_PARAM) +{ + err_t err; + const void *dataptr; + u16_t len, available; + u8_t write_finished = 0; + size_t diff; + u8_t dontblock; + u8_t apiflags; + + LWIP_ASSERT("conn != NULL", conn != NULL); + LWIP_ASSERT("conn->state == NETCONN_WRITE", (conn->state == NETCONN_WRITE)); + LWIP_ASSERT("conn->current_msg != NULL", conn->current_msg != NULL); + LWIP_ASSERT("conn->pcb.tcp != NULL", conn->pcb.tcp != NULL); + LWIP_ASSERT("conn->write_offset < conn->current_msg->msg.w.len", + conn->write_offset < conn->current_msg->msg.w.len); + + apiflags = conn->current_msg->msg.w.apiflags; + dontblock = netconn_is_nonblocking(conn) || (apiflags & NETCONN_DONTBLOCK); + +#if LWIP_SO_SNDTIMEO + if ((conn->send_timeout != 0) && + ((s32_t)(sys_now() - conn->current_msg->msg.w.time_started) >= conn->send_timeout)) { + write_finished = 1; + if (conn->write_offset == 0) { + /* nothing has been written */ + err = ERR_WOULDBLOCK; + conn->current_msg->msg.w.len = 0; + } else { + /* partial write */ + err = ERR_OK; + conn->current_msg->msg.w.len = conn->write_offset; + conn->write_offset = 0; + } + } else +#endif /* LWIP_SO_SNDTIMEO */ + { + dataptr = (const u8_t*)conn->current_msg->msg.w.dataptr + conn->write_offset; + diff = conn->current_msg->msg.w.len - conn->write_offset; + if (diff > 0xffffUL) { /* max_u16_t */ + len = 0xffff; + apiflags |= TCP_WRITE_FLAG_MORE; + } else { + len = (u16_t)diff; + } + available = tcp_sndbuf(conn->pcb.tcp); + if (available < len) { + /* don't try to write more than sendbuf */ + len = available; + if (dontblock) { + if (!len) { + err = ERR_WOULDBLOCK; + goto err_mem; + } + } else { + apiflags |= TCP_WRITE_FLAG_MORE; + } + } + LWIP_ASSERT("lwip_netconn_do_writemore: invalid length!", ((conn->write_offset + len) <= conn->current_msg->msg.w.len)); + err = tcp_write(conn->pcb.tcp, dataptr, len, apiflags); + /* if OK or memory error, check available space */ + if ((err == ERR_OK) || (err == ERR_MEM)) { +err_mem: + if (dontblock && (len < conn->current_msg->msg.w.len)) { + /* non-blocking write did not write everything: mark the pcb non-writable + and let poll_tcp check writable space to mark the pcb writable again */ + API_EVENT(conn, NETCONN_EVT_SENDMINUS, len); + conn->flags |= NETCONN_FLAG_CHECK_WRITESPACE; + } else if ((tcp_sndbuf(conn->pcb.tcp) <= TCP_SNDLOWAT) || + (tcp_sndqueuelen(conn->pcb.tcp) >= TCP_SNDQUEUELOWAT)) { + /* The queued byte- or pbuf-count exceeds the configured low-water limit, + let select mark this pcb as non-writable. */ + API_EVENT(conn, NETCONN_EVT_SENDMINUS, len); + } + } + + if (err == ERR_OK) { + err_t out_err; + conn->write_offset += len; + if ((conn->write_offset == conn->current_msg->msg.w.len) || dontblock) { + /* return sent length */ + conn->current_msg->msg.w.len = conn->write_offset; + /* everything was written */ + write_finished = 1; + } + out_err = tcp_output(conn->pcb.tcp); + if (ERR_IS_FATAL(out_err) || (out_err == ERR_RTE)) { + /* If tcp_output fails with fatal error or no route is found, + don't try writing any more but return the error + to the application thread. */ + err = out_err; + write_finished = 1; + conn->current_msg->msg.w.len = 0; + } + } else if (err == ERR_MEM) { + /* If ERR_MEM, we wait for sent_tcp or poll_tcp to be called. + For blocking sockets, we do NOT return to the application + thread, since ERR_MEM is only a temporary error! Non-blocking + will remain non-writable until sent_tcp/poll_tcp is called */ + + /* tcp_write returned ERR_MEM, try tcp_output anyway */ + err_t out_err = tcp_output(conn->pcb.tcp); + if (ERR_IS_FATAL(out_err) || (out_err == ERR_RTE)) { + /* If tcp_output fails with fatal error or no route is found, + don't try writing any more but return the error + to the application thread. */ + err = out_err; + write_finished = 1; + conn->current_msg->msg.w.len = 0; + } else if (dontblock) { + /* non-blocking write is done on ERR_MEM */ + err = ERR_WOULDBLOCK; + write_finished = 1; + conn->current_msg->msg.w.len = 0; + } + } else { + /* On errors != ERR_MEM, we don't try writing any more but return + the error to the application thread. */ + write_finished = 1; + conn->current_msg->msg.w.len = 0; + } + } + if (write_finished) { + /* everything was written: set back connection state + and back to application task */ + sys_sem_t* op_completed_sem = LWIP_API_MSG_SEM(conn->current_msg); + conn->current_msg->err = err; + conn->current_msg = NULL; + conn->write_offset = 0; + conn->state = NETCONN_NONE; + NETCONN_SET_SAFE_ERR(conn, err); +#if LWIP_TCPIP_CORE_LOCKING + if (delayed) +#endif + { + sys_sem_signal(op_completed_sem); + } + } +#if LWIP_TCPIP_CORE_LOCKING + else { + return ERR_MEM; + } +#endif + return ERR_OK; +} +#endif /* LWIP_TCP */ + +/** + * Send some data on a TCP pcb contained in a netconn + * Called from netconn_write + * + * @param m the api_msg_msg pointing to the connection + */ +void +lwip_netconn_do_write(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + + if (ERR_IS_FATAL(msg->conn->last_err)) { + msg->err = msg->conn->last_err; + } else { + if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) { +#if LWIP_TCP + if (msg->conn->state != NETCONN_NONE) { + /* netconn is connecting, closing or in blocking write */ + msg->err = ERR_INPROGRESS; + } else if (msg->conn->pcb.tcp != NULL) { + msg->conn->state = NETCONN_WRITE; + /* set all the variables used by lwip_netconn_do_writemore */ + LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL && + msg->conn->write_offset == 0); + LWIP_ASSERT("msg->msg.w.len != 0", msg->msg.w.len != 0); + msg->conn->current_msg = msg; + msg->conn->write_offset = 0; +#if LWIP_TCPIP_CORE_LOCKING + if (lwip_netconn_do_writemore(msg->conn, 0) != ERR_OK) { + LWIP_ASSERT("state!", msg->conn->state == NETCONN_WRITE); + UNLOCK_TCPIP_CORE(); + sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0); + LOCK_TCPIP_CORE(); + LWIP_ASSERT("state!", msg->conn->state != NETCONN_WRITE); + } +#else /* LWIP_TCPIP_CORE_LOCKING */ + lwip_netconn_do_writemore(msg->conn); +#endif /* LWIP_TCPIP_CORE_LOCKING */ + /* for both cases: if lwip_netconn_do_writemore was called, don't ACK the APIMSG + since lwip_netconn_do_writemore ACKs it! */ + return; + } else { + msg->err = ERR_CONN; + } +#else /* LWIP_TCP */ + msg->err = ERR_VAL; +#endif /* LWIP_TCP */ +#if (LWIP_UDP || LWIP_RAW) + } else { + msg->err = ERR_VAL; +#endif /* (LWIP_UDP || LWIP_RAW) */ + } + } + TCPIP_APIMSG_ACK(msg); +} + +/** + * Return a connection's local or remote address + * Called from netconn_getaddr + * + * @param m the api_msg_msg pointing to the connection + */ +void +lwip_netconn_do_getaddr(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + + if (msg->conn->pcb.ip != NULL) { + if (msg->msg.ad.local) { + ip_addr_copy(API_EXPR_DEREF(msg->msg.ad.ipaddr), + msg->conn->pcb.ip->local_ip); + } else { + ip_addr_copy(API_EXPR_DEREF(msg->msg.ad.ipaddr), + msg->conn->pcb.ip->remote_ip); + } + + msg->err = ERR_OK; + switch (NETCONNTYPE_GROUP(msg->conn->type)) { +#if LWIP_RAW + case NETCONN_RAW: + if (msg->msg.ad.local) { + API_EXPR_DEREF(msg->msg.ad.port) = msg->conn->pcb.raw->protocol; + } else { + /* return an error as connecting is only a helper for upper layers */ + msg->err = ERR_CONN; + } + break; +#endif /* LWIP_RAW */ +#if LWIP_UDP + case NETCONN_UDP: + if (msg->msg.ad.local) { + API_EXPR_DEREF(msg->msg.ad.port) = msg->conn->pcb.udp->local_port; + } else { + if ((msg->conn->pcb.udp->flags & UDP_FLAGS_CONNECTED) == 0) { + msg->err = ERR_CONN; + } else { + API_EXPR_DEREF(msg->msg.ad.port) = msg->conn->pcb.udp->remote_port; + } + } + break; +#endif /* LWIP_UDP */ +#if LWIP_TCP + case NETCONN_TCP: + if ((msg->msg.ad.local == 0) && + ((msg->conn->pcb.tcp->state == CLOSED) || (msg->conn->pcb.tcp->state == LISTEN))) { + /* pcb is not connected and remote name is requested */ + msg->err = ERR_CONN; + } else { + API_EXPR_DEREF(msg->msg.ad.port) = (msg->msg.ad.local ? msg->conn->pcb.tcp->local_port : msg->conn->pcb.tcp->remote_port); + } + break; +#endif /* LWIP_TCP */ + default: + LWIP_ASSERT("invalid netconn_type", 0); + break; + } + } else { + msg->err = ERR_CONN; + } + TCPIP_APIMSG_ACK(msg); +} + +/** + * Close or half-shutdown a TCP pcb contained in a netconn + * Called from netconn_close + * In contrast to closing sockets, the netconn is not deallocated. + * + * @param m the api_msg_msg pointing to the connection + */ +void +lwip_netconn_do_close(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + +#if LWIP_TCP + enum netconn_state state = msg->conn->state; + /* First check if this is a TCP netconn and if it is in a correct state + (LISTEN doesn't support half shutdown) */ + if ((msg->conn->pcb.tcp != NULL) && + (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_TCP) && + ((msg->msg.sd.shut == NETCONN_SHUT_RDWR) || (state != NETCONN_LISTEN))) { + /* Check if we are in a connected state */ + if (state == NETCONN_CONNECT) { + /* TCP connect in progress: cannot shutdown */ + msg->err = ERR_CONN; + } else if (state == NETCONN_WRITE) { +#if LWIP_NETCONN_FULLDUPLEX + if (msg->msg.sd.shut & NETCONN_SHUT_WR) { + /* close requested, abort running write */ + sys_sem_t* write_completed_sem; + LWIP_ASSERT("msg->conn->current_msg != NULL", msg->conn->current_msg != NULL); + write_completed_sem = LWIP_API_MSG_SEM(msg->conn->current_msg); + msg->conn->current_msg->err = ERR_CLSD; + msg->conn->current_msg = NULL; + msg->conn->write_offset = 0; + msg->conn->state = NETCONN_NONE; + state = NETCONN_NONE; + NETCONN_SET_SAFE_ERR(msg->conn, ERR_CLSD); + sys_sem_signal(write_completed_sem); + } else { + LWIP_ASSERT("msg->msg.sd.shut == NETCONN_SHUT_RD", msg->msg.sd.shut == NETCONN_SHUT_RD); + /* In this case, let the write continue and do not interfere with + conn->current_msg or conn->state! */ + msg->err = tcp_shutdown(msg->conn->pcb.tcp, 1, 0); + } + } + if (state == NETCONN_NONE) { +#else /* LWIP_NETCONN_FULLDUPLEX */ + msg->err = ERR_INPROGRESS; + } else { +#endif /* LWIP_NETCONN_FULLDUPLEX */ + if (msg->msg.sd.shut & NETCONN_SHUT_RD) { + /* Drain and delete mboxes */ + netconn_drain(msg->conn); + } + LWIP_ASSERT("already writing or closing", msg->conn->current_msg == NULL && + msg->conn->write_offset == 0); + msg->conn->state = NETCONN_CLOSE; + msg->conn->current_msg = msg; +#if LWIP_TCPIP_CORE_LOCKING +#if ESP_LWIP + if (lwip_netconn_do_close_internal(msg->conn, 0, SIG_CLOSE_TRUE) != ERR_OK) { +#else + if (lwip_netconn_do_close_internal(msg->conn, 0) != ERR_OK) { +#endif + LWIP_ASSERT("state!", msg->conn->state == NETCONN_CLOSE); + UNLOCK_TCPIP_CORE(); + sys_arch_sem_wait(LWIP_API_MSG_SEM(msg), 0); + LOCK_TCPIP_CORE(); + LWIP_ASSERT("state!", msg->conn->state == NETCONN_NONE); + } +#else /* LWIP_TCPIP_CORE_LOCKING */ +#if ESP_LWIP + lwip_netconn_do_close_internal(msg->conn, SIG_CLOSE_TRUE); +#else + lwip_netconn_do_close_internal(msg->conn); +#endif +#endif /* LWIP_TCPIP_CORE_LOCKING */ + /* for tcp netconns, lwip_netconn_do_close_internal ACKs the message */ + return; + } + } else +#endif /* LWIP_TCP */ + { + msg->err = ERR_CONN; + } + TCPIP_APIMSG_ACK(msg); +} + +#if LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) +/** + * Join multicast groups for UDP netconns. + * Called from netconn_join_leave_group + * + * @param m the api_msg_msg pointing to the connection + */ +void +lwip_netconn_do_join_leave_group(void *m) +{ + struct api_msg *msg = (struct api_msg*)m; + + if (ERR_IS_FATAL(msg->conn->last_err)) { + msg->err = msg->conn->last_err; + } else { + if (msg->conn->pcb.tcp != NULL) { + if (NETCONNTYPE_GROUP(msg->conn->type) == NETCONN_UDP) { +#if LWIP_UDP +#if LWIP_IPV6 && LWIP_IPV6_MLD + if (NETCONNTYPE_ISIPV6(msg->conn->type)) { + if (msg->msg.jl.join_or_leave == NETCONN_JOIN) { + msg->err = mld6_joingroup(ip_2_ip6(API_EXPR_REF(msg->msg.jl.netif_addr)), + ip_2_ip6(API_EXPR_REF(msg->msg.jl.multiaddr))); + } else { + msg->err = mld6_leavegroup(ip_2_ip6(API_EXPR_REF(msg->msg.jl.netif_addr)), + ip_2_ip6(API_EXPR_REF(msg->msg.jl.multiaddr))); + } + } + else +#endif /* LWIP_IPV6 && LWIP_IPV6_MLD */ + { +#if LWIP_IGMP + if (msg->msg.jl.join_or_leave == NETCONN_JOIN) { + msg->err = igmp_joingroup(ip_2_ip4(API_EXPR_REF(msg->msg.jl.netif_addr)), + ip_2_ip4(API_EXPR_REF(msg->msg.jl.multiaddr))); + } else { + msg->err = igmp_leavegroup(ip_2_ip4(API_EXPR_REF(msg->msg.jl.netif_addr)), + ip_2_ip4(API_EXPR_REF(msg->msg.jl.multiaddr))); + } +#endif /* LWIP_IGMP */ + } +#endif /* LWIP_UDP */ +#if (LWIP_TCP || LWIP_RAW) + } else { + msg->err = ERR_VAL; +#endif /* (LWIP_TCP || LWIP_RAW) */ + } + } else { + msg->err = ERR_CONN; + } + } + TCPIP_APIMSG_ACK(msg); +} +#endif /* LWIP_IGMP || (LWIP_IPV6 && LWIP_IPV6_MLD) */ + +#if LWIP_DNS +/** + * Callback function that is called when DNS name is resolved + * (or on timeout). A waiting application thread is waked up by + * signaling the semaphore. + */ +static void +lwip_netconn_do_dns_found(const char *name, const ip_addr_t *ipaddr, void *arg) +{ + struct dns_api_msg *msg = (struct dns_api_msg*)arg; + + /* we trust the internal implementation to be correct :-) */ + LWIP_UNUSED_ARG(name); + + if (ipaddr == NULL) { + /* timeout or memory error */ + API_EXPR_DEREF(msg->err) = ERR_VAL; + } else { + /* address was resolved */ + API_EXPR_DEREF(msg->err) = ERR_OK; + API_EXPR_DEREF(msg->addr) = *ipaddr; + } + /* wake up the application task waiting in netconn_gethostbyname */ + sys_sem_signal(API_EXPR_REF_SEM(msg->sem)); + + //[MS_CHANGE] + sys_signal_sock_event(); + //[END_MS_CHANGE] +} + +/** + * Execute a DNS query + * Called from netconn_gethostbyname + * + * @param arg the dns_api_msg pointing to the query + */ +void +lwip_netconn_do_gethostbyname(void *arg) +{ + struct dns_api_msg *msg = (struct dns_api_msg*)arg; + u8_t addrtype = +#if LWIP_IPV4 && LWIP_IPV6 + msg->dns_addrtype; +#else + LWIP_DNS_ADDRTYPE_DEFAULT; +#endif + + API_EXPR_DEREF(msg->err) = dns_gethostbyname_addrtype(msg->name, + API_EXPR_REF(msg->addr), lwip_netconn_do_dns_found, msg, addrtype); + if (API_EXPR_DEREF(msg->err) != ERR_INPROGRESS) { + /* on error or immediate success, wake up the application + * task waiting in netconn_gethostbyname */ + sys_sem_signal(API_EXPR_REF_SEM(msg->sem)); + } +} +#endif /* LWIP_DNS */ + +#endif /* LWIP_NETCONN */ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Lwip/nf_sockets.c b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Lwip/nf_sockets.c new file mode 100644 index 00000000..5ed0f8fc --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Lwip/nf_sockets.c @@ -0,0 +1,3584 @@ +/** + * @file + * Sockets BSD-Like API module + * + * @defgroup socket Socket API + * @ingroup sequential_api + * BSD-style socket API.\n + * Thread-safe, to be called from non-TCPIP threads only.\n + * Can be activated by defining @ref LWIP_SOCKET to 1.\n + * Header is in posix/sys/socket.h\b + */ + +/* + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + * Improved by Marc Boucher and David Haas + * + */ + +#include "lwip/opt.h" + +#if LWIP_SOCKET /* don't build if not configured for use in lwipopts.h */ + +#include "lwip/sockets.h" +#include "lwip/api.h" +#include "lwip/sys.h" +#include "lwip/igmp.h" +#include "lwip/mld6.h" +#include "lwip/inet.h" +#include "lwip/tcp.h" +#include "lwip/raw.h" +#include "lwip/udp.h" +#include "lwip/memp.h" +#include "lwip/pbuf.h" +#include "lwip/priv/tcpip_priv.h" +#include "lwip/priv/api_msg.h" +#if LWIP_CHECKSUM_ON_COPY +#include "lwip/inet_chksum.h" +#endif + +#include + +extern void sys_signal_sock_event(); // MS-CHANGE + +/* If the netconn API is not required publicly, then we include the necessary + files here to get the implementation */ +#if !LWIP_NETCONN +#undef LWIP_NETCONN +#define LWIP_NETCONN 1 +#include "api_msg.c" +#include "api_lib.c" +#include "netbuf.c" +#undef LWIP_NETCONN +#define LWIP_NETCONN 0 +#endif + +#if LWIP_IPV4 +#define IP4ADDR_PORT_TO_SOCKADDR(sin, ipaddr, port) do { \ + (sin)->sin_len = sizeof(struct sockaddr_in); \ + (sin)->sin_family = AF_INET; \ + (sin)->sin_port = lwip_htons((port)); \ + inet_addr_from_ip4addr(&(sin)->sin_addr, ipaddr); \ + memset((sin)->sin_zero, 0, SIN_ZERO_LEN); }while(0) +#define SOCKADDR4_TO_IP4ADDR_PORT(sin, ipaddr, port) do { \ + inet_addr_to_ip4addr(ip_2_ip4(ipaddr), &((sin)->sin_addr)); \ + (port) = lwip_ntohs((sin)->sin_port); }while(0) +#endif /* LWIP_IPV4 */ + +#if LWIP_IPV6 +#define IP6ADDR_PORT_TO_SOCKADDR(sin6, ipaddr, port) do { \ + (sin6)->sin6_len = sizeof(struct sockaddr_in6); \ + (sin6)->sin6_family = AF_INET6; \ + (sin6)->sin6_port = lwip_htons((port)); \ + (sin6)->sin6_flowinfo = 0; \ + inet6_addr_from_ip6addr(&(sin6)->sin6_addr, ipaddr); \ + (sin6)->sin6_scope_id = 0; }while(0) +#define SOCKADDR6_TO_IP6ADDR_PORT(sin6, ipaddr, port) do { \ + inet6_addr_to_ip6addr(ip_2_ip6(ipaddr), &((sin6)->sin6_addr)); \ + (port) = lwip_ntohs((sin6)->sin6_port); }while(0) +#endif /* LWIP_IPV6 */ + +#if LWIP_IPV4 && LWIP_IPV6 +static void sockaddr_to_ipaddr_port(const struct sockaddr* sockaddr, ip_addr_t* ipaddr, u16_t* port); + +#define IS_SOCK_ADDR_LEN_VALID(namelen) (((namelen) == sizeof(struct sockaddr_in)) || \ + ((namelen) == sizeof(struct sockaddr_in6))) +#define IS_SOCK_ADDR_TYPE_VALID(name) (((name)->sa_family == AF_INET) || \ + ((name)->sa_family == AF_INET6)) +#define SOCK_ADDR_TYPE_MATCH(name, sock) \ + ((((name)->sa_family == AF_INET) && !(NETCONNTYPE_ISIPV6((sock)->conn->type))) || \ + (((name)->sa_family == AF_INET6) && (NETCONNTYPE_ISIPV6((sock)->conn->type)))) +#define IPADDR_PORT_TO_SOCKADDR(sockaddr, ipaddr, port) do { \ + if (IP_IS_V6(ipaddr)) { \ + IP6ADDR_PORT_TO_SOCKADDR((struct sockaddr_in6*)(void*)(sockaddr), ip_2_ip6(ipaddr), port); \ + } else { \ + IP4ADDR_PORT_TO_SOCKADDR((struct sockaddr_in*)(void*)(sockaddr), ip_2_ip4(ipaddr), port); \ + } } while(0) +#define SOCKADDR_TO_IPADDR_PORT(sockaddr, ipaddr, port) sockaddr_to_ipaddr_port(sockaddr, ipaddr, &(port)) +#define DOMAIN_TO_NETCONN_TYPE(domain, type) (((domain) == AF_INET) ? \ + (type) : (enum netconn_type)((type) | NETCONN_TYPE_IPV6)) +#elif LWIP_IPV6 /* LWIP_IPV4 && LWIP_IPV6 */ +#define IS_SOCK_ADDR_LEN_VALID(namelen) ((namelen) == sizeof(struct sockaddr_in6)) +#define IS_SOCK_ADDR_TYPE_VALID(name) ((name)->sa_family == AF_INET6) +#define SOCK_ADDR_TYPE_MATCH(name, sock) 1 +#define IPADDR_PORT_TO_SOCKADDR(sockaddr, ipaddr, port) \ + IP6ADDR_PORT_TO_SOCKADDR((struct sockaddr_in6*)(void*)(sockaddr), ip_2_ip6(ipaddr), port) +#define SOCKADDR_TO_IPADDR_PORT(sockaddr, ipaddr, port) \ + SOCKADDR6_TO_IP6ADDR_PORT((const struct sockaddr_in6*)(const void*)(sockaddr), ipaddr, port) +#define DOMAIN_TO_NETCONN_TYPE(domain, netconn_type) (netconn_type) +#else /*-> LWIP_IPV4: LWIP_IPV4 && LWIP_IPV6 */ +#define IS_SOCK_ADDR_LEN_VALID(namelen) ((namelen) == sizeof(struct sockaddr_in)) +#define IS_SOCK_ADDR_TYPE_VALID(name) ((name)->sa_family == AF_INET) +#define SOCK_ADDR_TYPE_MATCH(name, sock) 1 +#define IPADDR_PORT_TO_SOCKADDR(sockaddr, ipaddr, port) \ + IP4ADDR_PORT_TO_SOCKADDR((struct sockaddr_in*)(void*)(sockaddr), ip_2_ip4(ipaddr), port) +#define SOCKADDR_TO_IPADDR_PORT(sockaddr, ipaddr, port) \ + SOCKADDR4_TO_IP4ADDR_PORT((const struct sockaddr_in*)(const void*)(sockaddr), ipaddr, port) +#define DOMAIN_TO_NETCONN_TYPE(domain, netconn_type) (netconn_type) +#endif /* LWIP_IPV6 */ + +#define IS_SOCK_ADDR_TYPE_VALID_OR_UNSPEC(name) (((name)->sa_family == AF_UNSPEC) || \ + IS_SOCK_ADDR_TYPE_VALID(name)) +#define SOCK_ADDR_TYPE_MATCH_OR_UNSPEC(name, sock) (((name)->sa_family == AF_UNSPEC) || \ + SOCK_ADDR_TYPE_MATCH(name, sock)) +#define IS_SOCK_ADDR_ALIGNED(name) ((((mem_ptr_t)(name)) % 4) == 0) + + +#define LWIP_SOCKOPT_CHECK_OPTLEN(optlen, opttype) do { if ((optlen) < sizeof(opttype)) { return EINVAL; }}while(0) +#define LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, opttype) do { \ + LWIP_SOCKOPT_CHECK_OPTLEN(optlen, opttype); \ + if ((sock)->conn == NULL) { return EINVAL; } }while(0) +#define LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, opttype) do { \ + LWIP_SOCKOPT_CHECK_OPTLEN(optlen, opttype); \ + if (((sock)->conn == NULL) || ((sock)->conn->pcb.tcp == NULL)) { return EINVAL; } }while(0) +#define LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, opttype, netconntype) do { \ + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, opttype); \ + if (NETCONNTYPE_GROUP(netconn_type((sock)->conn)) != netconntype) { return ENOPROTOOPT; } }while(0) + + +#define LWIP_SETGETSOCKOPT_DATA_VAR_REF(name) API_VAR_REF(name) +#define LWIP_SETGETSOCKOPT_DATA_VAR_DECLARE(name) API_VAR_DECLARE(struct lwip_setgetsockopt_data, name) +#define LWIP_SETGETSOCKOPT_DATA_VAR_FREE(name) API_VAR_FREE(MEMP_SOCKET_SETGETSOCKOPT_DATA, name) +#if LWIP_MPU_COMPATIBLE +#define LWIP_SETGETSOCKOPT_DATA_VAR_ALLOC(name, sock) do { \ + name = (struct lwip_setgetsockopt_data *)memp_malloc(MEMP_SOCKET_SETGETSOCKOPT_DATA); \ + if (name == NULL) { \ + sock_set_errno(sock, ENOMEM); \ + return -1; \ + } }while(0) +#else /* LWIP_MPU_COMPATIBLE */ +#define LWIP_SETGETSOCKOPT_DATA_VAR_ALLOC(name, sock) +#endif /* LWIP_MPU_COMPATIBLE */ + +#if LWIP_SO_SNDRCVTIMEO_NONSTANDARD +#define LWIP_SO_SNDRCVTIMEO_OPTTYPE int +#define LWIP_SO_SNDRCVTIMEO_SET(optval, val) (*(int *)(optval) = (val)) +#define LWIP_SO_SNDRCVTIMEO_GET_MS(optval) ((s32_t)*(const int*)(optval)) +#else +#define LWIP_SO_SNDRCVTIMEO_OPTTYPE struct timeval +#define LWIP_SO_SNDRCVTIMEO_SET(optval, val) do { \ + s32_t loc = (val); \ + ((struct timeval *)(optval))->tv_sec = (loc) / 1000U; \ + ((struct timeval *)(optval))->tv_usec = ((loc) % 1000U) * 1000U; }while(0) +#define LWIP_SO_SNDRCVTIMEO_GET_MS(optval) ((((const struct timeval *)(optval))->tv_sec * 1000U) + (((const struct timeval *)(optval))->tv_usec / 1000U)) +#endif + +#define NUM_SOCKETS MEMP_NUM_NETCONN + +#if !defined IOV_MAX +#define IOV_MAX 0xFFFF +#elif IOV_MAX > 0xFFFF +#error "IOV_MAX larger than supported by LwIP" +#endif /* IOV_MAX */ + +/** This is overridable for the rare case where more than 255 threads + * select on the same socket... + */ +#ifndef SELWAIT_T +#define SELWAIT_T u8_t +#endif + +/** Contains all internal pointers and states used for a socket */ +struct lwip_sock { + /** sockets currently are built on netconns, each socket has one netconn */ + struct netconn *conn; + /** data that was left from the previous read */ + void *lastdata; + /** offset in the data that was left from the previous read */ + u16_t lastoffset; + /** number of times data was received, set by event_callback(), + tested by the receive and select functions */ + s16_t rcvevent; + /** number of times data was ACKed (free send buffer), set by event_callback(), + tested by select */ + u16_t sendevent; + /** error happened for this socket, set by event_callback(), tested by select */ + u16_t errevent; + /** last error that occurred on this socket (in fact, all our errnos fit into an u8_t) */ + u8_t err; + +#if ESP_THREAD_SAFE + /* lock is used to protect state/ref field, however this lock is not a perfect lock, e.g + * taskA and taskB can access sock X, then taskA freed sock X, before taskB detect + * this, taskC reuse sock X, then when taskB try to access sock X, problem may happen. + * A mitigation solution may be, when allocate a socket, alloc the least frequently used + * socket. + */ + sys_mutex_t lock; + + /* can be LWIP_SOCK_OPEN/LWIP_SOCK_CLOSING/LWIP_SOCK_CLOSED */ + u8_t state; + + /* if ref is 0, the sock need/can to be freed */ + s8_t ref; + + /* indicate how long the sock is in LWIP_SOCK_CLOSED status */ + u8_t age; +#endif + + /** counter of how many threads are waiting for this socket using select */ + SELWAIT_T select_waiting; +}; + +#if ESP_THREAD_SAFE + +#define LWIP_SOCK_OPEN 0 +#define LWIP_SOCK_CLOSING 1 +#define LWIP_SOCK_CLOSED 2 + +#define LWIP_SOCK_LOCK(sock) \ +do{\ + /*LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("l\n"));*/\ + sys_mutex_lock(&sock->lock);\ + /*LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("l ok\n"));*/\ +}while(0) + + +#define LWIP_SOCK_UNLOCK(sock) \ +do{\ + sys_mutex_unlock(&sock->lock);\ + /*LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG1, ("unl\n"));*/\ +}while(0) + +#define LWIP_FREE_SOCK(sock) \ +do{\ + if(sock->conn && NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP){\ + LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("LWIP_FREE_SOCK:free tcp sock\n"));\ + free_socket(sock, 1);\ + } else {\ + LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("LWIP_FREE_SOCK:free non-tcp sock\n"));\ + free_socket(sock, 0);\ + }\ +}while(0) + +#define LWIP_SET_CLOSE_FLAG() \ +do{\ + LWIP_SOCK_LOCK(__sock);\ + LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("mark sock closing\n"));\ + __sock->state = LWIP_SOCK_CLOSING;\ + LWIP_SOCK_UNLOCK(__sock);\ +}while(0) + +#define LWIP_API_LOCK() \ + struct lwip_sock *__sock;\ + int __ret;\ +\ + __sock = get_socket(s);\ + if (!__sock) {\ + return -1;\ + }\ +\ +do{\ + LWIP_SOCK_LOCK(__sock);\ + __sock->ref ++;\ + if (__sock->state != LWIP_SOCK_OPEN) {\ + LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("LWIP_API_LOCK:soc is %d, return\n", __sock->state));\ + __sock->ref --;\ + LWIP_SOCK_UNLOCK(__sock);\ + return -1;\ + }\ +\ + LWIP_SOCK_UNLOCK(__sock);\ +}while(0) + +#define LWIP_API_UNLOCK() \ +do{\ + LWIP_SOCK_LOCK(__sock);\ + __sock->ref --;\ + if (__sock->state == LWIP_SOCK_CLOSING) {\ + if (__sock->ref == 0){\ + LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("LWIP_API_UNLOCK:ref 0, free __sock\n"));\ + LWIP_FREE_SOCK(__sock);\ + LWIP_SOCK_UNLOCK(__sock);\ + return __ret;\ + }\ + LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("LWIP_API_UNLOCK: soc state is closing, return\n"));\ + LWIP_SOCK_UNLOCK(__sock);\ + return __ret;\ + }\ +\ + LWIP_SOCK_UNLOCK(__sock);\ + return __ret;\ +}while(0) + +#endif + +#if LWIP_NETCONN_SEM_PER_THREAD +#define SELECT_SEM_T sys_sem_t* +#define SELECT_SEM_PTR(sem) (sem) +#else /* LWIP_NETCONN_SEM_PER_THREAD */ +#define SELECT_SEM_T sys_sem_t +#define SELECT_SEM_PTR(sem) (&(sem)) +#endif /* LWIP_NETCONN_SEM_PER_THREAD */ + +/** Description for a task waiting in select */ +struct lwip_select_cb { + /** Pointer to the next waiting task */ + struct lwip_select_cb *next; + /** Pointer to the previous waiting task */ + struct lwip_select_cb *prev; + /** readset passed to select */ + fd_set *readset; + /** writeset passed to select */ + fd_set *writeset; + /** unimplemented: exceptset passed to select */ + fd_set *exceptset; + /** don't signal the same semaphore twice: set to 1 when signalled */ + int sem_signalled; + /** semaphore to wake up a task waiting for select */ + SELECT_SEM_T sem; +}; + +/** A struct sockaddr replacement that has the same alignment as sockaddr_in/ + * sockaddr_in6 if instantiated. + */ +union sockaddr_aligned { + struct sockaddr sa; +#if LWIP_IPV6 + struct sockaddr_in6 sin6; +#endif /* LWIP_IPV6 */ +#if LWIP_IPV4 + struct sockaddr_in sin; +#endif /* LWIP_IPV4 */ +}; + +#if LWIP_IGMP +/* Define the number of IPv4 multicast memberships, default is one per socket */ +#ifndef LWIP_SOCKET_MAX_MEMBERSHIPS +#define LWIP_SOCKET_MAX_MEMBERSHIPS NUM_SOCKETS +#endif + +/* This is to keep track of IP_ADD_MEMBERSHIP calls to drop the membership when + a socket is closed */ +#if ESP_LWIP +struct lwip_socket_multicast_pair { + /** the socket (+1 to not require initialization) */ + int sa; + /** the interface address */ + ip_addr_t if_addr; + /** the group address */ + ip_addr_t multi_addr; +}; + +struct lwip_socket_multicast_pair socket_multicast_memberships[LWIP_SOCKET_MAX_MEMBERSHIPS]; + +static int lwip_socket_register_membership(int s, const ip_addr_t *if_addr, const ip_addr_t *multi_addr); +static void lwip_socket_unregister_membership(int s, const ip_addr_t *if_addr, const ip_addr_t *multi_addr); + +#else +struct lwip_socket_multicast_pair { + /** the socket */ + struct lwip_sock* sock; + /** the interface address */ + ip4_addr_t if_addr; + /** the group address */ + ip4_addr_t multi_addr; +}; + +struct lwip_socket_multicast_pair socket_ipv4_multicast_memberships[LWIP_SOCKET_MAX_MEMBERSHIPS]; + +static int lwip_socket_register_membership(int s, const ip4_addr_t *if_addr, const ip4_addr_t *multi_addr); +static void lwip_socket_unregister_membership(int s, const ip4_addr_t *if_addr, const ip4_addr_t *multi_addr); +#endif + +static void lwip_socket_drop_registered_memberships(int s); +#endif /* LWIP_IGMP */ + +/** The global array of available sockets */ +static struct lwip_sock sockets[NUM_SOCKETS]; +#if ESP_THREAD_SAFE +static bool sockets_init_flag = false; +#endif +/** The global list of tasks waiting for select */ +static struct lwip_select_cb *select_cb_list; +/** This counter is increased from lwip_select when the list is changed + and checked in event_callback to see if it has changed. */ +static volatile int select_cb_ctr; + +#if LWIP_SOCKET_SET_ERRNO +#ifndef set_errno +#define set_errno(err) do { if (err) { errno = (err); } } while(0) +#endif +#else /* LWIP_SOCKET_SET_ERRNO */ +#define set_errno(err) +#endif /* LWIP_SOCKET_SET_ERRNO */ + +#define sock_set_errno(sk, e) do { \ + const int sockerr = (e); \ + sk->err = (u8_t)sockerr; \ + set_errno(sockerr); \ +} while (0) + +/* Forward declaration of some functions */ +static void event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len); +#if !LWIP_TCPIP_CORE_LOCKING +static void lwip_getsockopt_callback(void *arg); +static void lwip_setsockopt_callback(void *arg); +#endif +static u8_t lwip_getsockopt_impl(int s, int level, int optname, void *optval, socklen_t *optlen); +static u8_t lwip_setsockopt_impl(int s, int level, int optname, const void *optval, socklen_t optlen); + +#if LWIP_IPV4 && LWIP_IPV6 +static void +sockaddr_to_ipaddr_port(const struct sockaddr* sockaddr, ip_addr_t* ipaddr, u16_t* port) +{ + if ((sockaddr->sa_family) == AF_INET6) { + SOCKADDR6_TO_IP6ADDR_PORT((const struct sockaddr_in6*)(const void*)(sockaddr), ipaddr, *port); + ipaddr->type = IPADDR_TYPE_V6; + } else { + SOCKADDR4_TO_IP4ADDR_PORT((const struct sockaddr_in*)(const void*)(sockaddr), ipaddr, *port); + ipaddr->type = IPADDR_TYPE_V4; + } +} +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + +/** LWIP_NETCONN_SEM_PER_THREAD==1: initialize thread-local semaphore */ +void +lwip_socket_thread_init(void) +{ + netconn_thread_init(); +} + +/** LWIP_NETCONN_SEM_PER_THREAD==1: destroy thread-local semaphore */ +void +lwip_socket_thread_cleanup(void) +{ + netconn_thread_cleanup(); +} + +/** + * Map a externally used socket index to the internal socket representation. + * + * @param s externally used socket index + * @return struct lwip_sock for the socket or NULL if not found + */ +#if ESP_LWIP +static struct lwip_sock * ESP_IRAM_ATTR +#else +static struct lwip_sock * +#endif +get_socket(int s) +{ + struct lwip_sock *sock; + + s -= LWIP_SOCKET_OFFSET; + + if ((s < 0) || (s >= NUM_SOCKETS)) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): invalid\n", s + LWIP_SOCKET_OFFSET)); + set_errno(EBADF); + return NULL; + } + + sock = &sockets[s]; + + if (!sock->conn) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("get_socket(%d): not active\n", s + LWIP_SOCKET_OFFSET)); + set_errno(EBADF); + return NULL; + } + + return sock; +} + +/** + * Same as get_socket but doesn't set errno + * + * @param s externally used socket index + * @return struct lwip_sock for the socket or NULL if not found + */ +static struct lwip_sock * +tryget_socket(int s) +{ + s -= LWIP_SOCKET_OFFSET; + if ((s < 0) || (s >= NUM_SOCKETS)) { + return NULL; + } + if (!sockets[s].conn) { + return NULL; + } + return &sockets[s]; +} + +/** + * Allocate a new socket for a given netconn. + * + * @param newconn the netconn for which to allocate a socket + * @param accepted 1 if socket has been created by accept(), + * 0 if socket has been created by socket() + * @return the index of the new socket; -1 on error + */ +static int +alloc_socket(struct netconn *newconn, int accepted) +{ + int i; + SYS_ARCH_DECL_PROTECT(lev); + +#if ESP_THREAD_SAFE + bool found = false; + int oldest = -1; + + SYS_ARCH_PROTECT(lev); + + if (sockets_init_flag == false){ + sockets_init_flag = true; + memset(sockets, 0, sizeof(sockets)); + } + + for (i = 0; i < NUM_SOCKETS; ++i) { + sockets[i].age ++; + + if (found == true){ + continue; + } + + if (!sockets[i].conn && (sockets[i].state == LWIP_SOCK_OPEN)) { + found = true; + oldest = i; + continue; + } + + if (!sockets[i].conn){ + if (oldest == -1 || sockets[i].age > sockets[oldest].age){ + oldest = i; + } + } + } + + if ((oldest != -1) && !sockets[oldest].conn) { + found = true; + sockets[oldest].conn = newconn; + } + + SYS_ARCH_UNPROTECT(lev); + + if (found == true) { + sockets[oldest].lastdata = NULL; + sockets[oldest].lastoffset = 0; + sockets[oldest].rcvevent = 0; + + /* TCP sendbuf is empty, but the socket is not yet writable until connected + * (unless it has been created by accept()). */ + sockets[oldest].sendevent = (NETCONNTYPE_GROUP(newconn->type) == NETCONN_TCP ? (accepted != 0) : 1); + sockets[oldest].errevent = 0; + sockets[oldest].err = 0; + sockets[oldest].select_waiting = 0; + + sockets[oldest].state = LWIP_SOCK_OPEN; + sockets[oldest].age = 0; + sockets[oldest].ref = 0; + if (!sockets[oldest].lock){ + /* one time init and never free */ + if (sys_mutex_new(&sockets[oldest].lock) != ERR_OK){ + LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("new sock lock fail\n")); + return -1; + } + } + LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("alloc_socket: alloc %d ok\n", oldest)); + + return oldest + LWIP_SOCKET_OFFSET; + } + + LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("alloc_socket: failed\n")); + +#else + + /* allocate a new socket identifier */ + for (i = 0; i < NUM_SOCKETS; ++i) { + /* Protect socket array */ + SYS_ARCH_PROTECT(lev); + if (!sockets[i].conn && (sockets[i].select_waiting == 0)) { + sockets[i].conn = newconn; + /* The socket is not yet known to anyone, so no need to protect + after having marked it as used. */ + SYS_ARCH_UNPROTECT(lev); + sockets[i].lastdata = NULL; + sockets[i].lastoffset = 0; + sockets[i].rcvevent = 0; + /* TCP sendbuf is empty, but the socket is not yet writable until connected + * (unless it has been created by accept()). */ + sockets[i].sendevent = (NETCONNTYPE_GROUP(newconn->type) == NETCONN_TCP ? (accepted != 0) : 1); + sockets[i].errevent = 0; + sockets[i].err = 0; + return i + LWIP_SOCKET_OFFSET; + } + SYS_ARCH_UNPROTECT(lev); + } + +#endif + + return -1; +} + +/** Free a socket. The socket's netconn must have been + * delete before! + * + * @param sock the socket to free + * @param is_tcp != 0 for TCP sockets, used to free lastdata + */ +static void +free_socket(struct lwip_sock *sock, int is_tcp) +{ + void *lastdata; + +#if ESP_THREAD_SAFE + SYS_ARCH_DECL_PROTECT(lev); + LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("free_sockset:free socket s=%p is_tcp=%d\n", sock, is_tcp)); +#endif + + lastdata = sock->lastdata; + sock->lastdata = NULL; + sock->lastoffset = 0; + sock->err = 0; +#if ESP_THREAD_SAFE + if (sock->conn){ + netconn_free(sock->conn); + } + + SYS_ARCH_PROTECT(lev); + sock->age = 0; + sock->conn = NULL; + sock->state = LWIP_SOCK_CLOSED; + SYS_ARCH_UNPROTECT(lev); +#endif + + /* Protect socket array */ + SYS_ARCH_SET(sock->conn, NULL); + /* don't use 'sock' after this line, as another task might have allocated it */ + + if (lastdata != NULL) { + if (is_tcp) { + pbuf_free((struct pbuf *)lastdata); + } else { + netbuf_delete((struct netbuf *)lastdata); + } + } +} + +/* Below this, the well-known socket functions are implemented. + * Use google.com or opengroup.org to get a good description :-) + * + * Exceptions are documented! + */ + +int +lwip_accept(int s, struct sockaddr *addr, socklen_t *addrlen) +{ + struct lwip_sock *sock, *nsock; + struct netconn *newconn; + ip_addr_t naddr; + u16_t port = 0; + int newsock; + err_t err; + SYS_ARCH_DECL_PROTECT(lev); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d)...\n", s)); + sock = get_socket(s); + if (!sock) { + return -1; + } + + if (netconn_is_nonblocking(sock->conn) && (sock->rcvevent <= 0)) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d): returning EWOULDBLOCK\n", s)); + set_errno(EWOULDBLOCK); + return -1; + } + + /* wait for a new connection */ + err = netconn_accept(sock->conn, &newconn); + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d): netconn_acept failed, err=%d\n", s, err)); + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) { + sock_set_errno(sock, EOPNOTSUPP); + } else if (err == ERR_CLSD) { + sock_set_errno(sock, EINVAL); + } else { + sock_set_errno(sock, err_to_errno(err)); + } + return -1; + } + LWIP_ASSERT("newconn != NULL", newconn != NULL); +#if ESP_AUTO_RECV + /* Prevent automatic window updates, we do this on our own! */ + netconn_set_noautorecved(newconn, 1); +#endif + + newsock = alloc_socket(newconn, 1); + if (newsock == -1) { + netconn_delete(newconn); + sock_set_errno(sock, ENFILE); + return -1; + } + LWIP_ASSERT("invalid socket index", (newsock >= LWIP_SOCKET_OFFSET) && (newsock < NUM_SOCKETS + LWIP_SOCKET_OFFSET)); + LWIP_ASSERT("newconn->callback == event_callback", newconn->callback == event_callback); + nsock = &sockets[newsock - LWIP_SOCKET_OFFSET]; + + /* See event_callback: If data comes in right away after an accept, even + * though the server task might not have created a new socket yet. + * In that case, newconn->socket is counted down (newconn->socket--), + * so nsock->rcvevent is >= 1 here! + */ + SYS_ARCH_PROTECT(lev); + nsock->rcvevent += (s16_t)(-1 - newconn->socket); + newconn->socket = newsock; + SYS_ARCH_UNPROTECT(lev); + + /* Note that POSIX only requires us to check addr is non-NULL. addrlen must + * not be NULL if addr is valid. + */ + if (addr != NULL) { + union sockaddr_aligned tempaddr; + /* get the IP address and port of the remote host */ + err = netconn_peer(newconn, &naddr, &port); + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d): netconn_peer failed, err=%d\n", s, err)); + netconn_delete(newconn); + free_socket(nsock, 1); + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + LWIP_ASSERT("addr valid but addrlen NULL", addrlen != NULL); + + IPADDR_PORT_TO_SOCKADDR(&tempaddr, &naddr, port); + if (*addrlen > tempaddr.sa.sa_len) { + *addrlen = tempaddr.sa.sa_len; + } + MEMCPY(addr, &tempaddr, *addrlen); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d addr=", s, newsock)); + ip_addr_debug_print_val(SOCKETS_DEBUG, naddr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F"\n", port)); + } else { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_accept(%d) returning new sock=%d", s, newsock)); + } + + // [MS_CHANGE] - Signal the CLR that a socket event has occured + // TODO: We may want to investigate other ways to signal + // the CLR (maybe based on which socket received the + // event). + if(nsock->rcvevent > 0 ) { + sys_signal_sock_event(); + } + //[END_MS_CHANGE] + + sock_set_errno(sock, 0); + return newsock; +} + +int +lwip_bind(int s, const struct sockaddr *name, socklen_t namelen) +{ + struct lwip_sock *sock; + ip_addr_t local_addr; + u16_t local_port; + err_t err; + + sock = get_socket(s); + if (!sock) { + return -1; + } + + if (!SOCK_ADDR_TYPE_MATCH(name, sock)) { + /* sockaddr does not match socket type (IPv4/IPv6) */ + sock_set_errno(sock, err_to_errno(ERR_VAL)); + return -1; + } + + /* check size, family and alignment of 'name' */ + LWIP_ERROR("lwip_bind: invalid address", (IS_SOCK_ADDR_LEN_VALID(namelen) && + IS_SOCK_ADDR_TYPE_VALID(name) && IS_SOCK_ADDR_ALIGNED(name)), + sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;); + LWIP_UNUSED_ARG(namelen); + + SOCKADDR_TO_IPADDR_PORT(name, &local_addr, local_port); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d, addr=", s)); + ip_addr_debug_print_val(SOCKETS_DEBUG, local_addr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", local_port)); + +#if LWIP_IPV4 && LWIP_IPV6 + /* Dual-stack: Unmap IPv4 mapped IPv6 addresses */ + if (IP_IS_V6_VAL(local_addr) && ip6_addr_isipv4mappedipv6(ip_2_ip6(&local_addr))) { + unmap_ipv4_mapped_ipv6(ip_2_ip4(&local_addr), ip_2_ip6(&local_addr)); + IP_SET_TYPE_VAL(local_addr, IPADDR_TYPE_V4); + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + + err = netconn_bind(sock->conn, &local_addr, local_port); + + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) failed, err=%d\n", s, err)); + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_bind(%d) succeeded\n", s)); + sock_set_errno(sock, 0); + return 0; +} + +int +lwip_close(int s) +{ + struct lwip_sock *sock; + int is_tcp = 0; + err_t err; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_close(%d)\n", s)); + + sock = get_socket(s); + if (!sock) { + return -1; + } + + if (sock->conn != NULL) { + is_tcp = NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP; +#if ESP_THREAD_SAFE + LWIP_DEBUGF(SOCKETS_DEBUG|ESP_THREAD_SAFE_DEBUG, ("lwip_close: is_tcp=%d\n", is_tcp)); +#endif + } else { + LWIP_ASSERT("sock->lastdata == NULL", sock->lastdata == NULL); + } + +#if ESP_LWIP +#if (LWIP_IGMP) || (LWIP_IPV6_MLD && LWIP_MULTICAST_TX_OPTIONS) + /* drop all possibly joined IGMP memberships */ + lwip_socket_drop_registered_memberships(s); +#endif +#else +#if LWIP_IGMP + /* drop all possibly joined IGMP memberships */ + lwip_socket_drop_registered_memberships(s); +#endif /* LWIP_IGMP */ +#endif + + + err = netconn_delete(sock->conn); + if (err != ERR_OK) { + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + +#if !ESP_THREAD_SAFE + free_socket(sock, is_tcp); +#endif + + set_errno(0); + return 0; +} + +int +lwip_connect(int s, const struct sockaddr *name, socklen_t namelen) +{ + struct lwip_sock *sock; + err_t err; + + sock = get_socket(s); + if (!sock) { + return -1; + } + + if (!SOCK_ADDR_TYPE_MATCH_OR_UNSPEC(name, sock)) { + /* sockaddr does not match socket type (IPv4/IPv6) */ + sock_set_errno(sock, err_to_errno(ERR_VAL)); + return -1; + } + + LWIP_UNUSED_ARG(namelen); + if (name->sa_family == AF_UNSPEC) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, AF_UNSPEC)\n", s)); + err = netconn_disconnect(sock->conn); + } else { + ip_addr_t remote_addr; + u16_t remote_port; + + /* check size, family and alignment of 'name' */ + LWIP_ERROR("lwip_connect: invalid address", IS_SOCK_ADDR_LEN_VALID(namelen) && + IS_SOCK_ADDR_TYPE_VALID_OR_UNSPEC(name) && IS_SOCK_ADDR_ALIGNED(name), + sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;); + + SOCKADDR_TO_IPADDR_PORT(name, &remote_addr, remote_port); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d, addr=", s)); + ip_addr_debug_print_val(SOCKETS_DEBUG, remote_addr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", remote_port)); + +#if LWIP_IPV4 && LWIP_IPV6 + /* Dual-stack: Unmap IPv4 mapped IPv6 addresses */ + if (IP_IS_V6_VAL(remote_addr) && ip6_addr_isipv4mappedipv6(ip_2_ip6(&remote_addr))) { + unmap_ipv4_mapped_ipv6(ip_2_ip4(&remote_addr), ip_2_ip6(&remote_addr)); + IP_SET_TYPE_VAL(remote_addr, IPADDR_TYPE_V4); + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + + err = netconn_connect(sock->conn, &remote_addr, remote_port); + } + + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) failed, err=%d\n", s, err)); + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_connect(%d) succeeded\n", s)); + sock_set_errno(sock, 0); + return 0; +} + +/** + * Set a socket into listen mode. + * The socket may not have been used for another connection previously. + * + * @param s the socket to set to listening mode + * @param backlog (ATTENTION: needs TCP_LISTEN_BACKLOG=1) + * @return 0 on success, non-zero on failure + */ +int +lwip_listen(int s, int backlog) +{ + struct lwip_sock *sock; + err_t err; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d, backlog=%d)\n", s, backlog)); + + sock = get_socket(s); + if (!sock) { + return -1; + } + + /* limit the "backlog" parameter to fit in an u8_t */ + backlog = LWIP_MIN(LWIP_MAX(backlog, 0), 0xff); + + err = netconn_listen_with_backlog(sock->conn, (u8_t)backlog); + + if (err != ERR_OK) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_listen(%d) failed, err=%d\n", s, err)); + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) { + sock_set_errno(sock, EOPNOTSUPP); + return -1; + } + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + + sock_set_errno(sock, 0); + return 0; +} + +#if ESP_LWIP +int ESP_IRAM_ATTR +#else +int +#endif +lwip_recvfrom(int s, void *mem, size_t len, int flags, + struct sockaddr *from, socklen_t *fromlen) +{ + struct lwip_sock *sock; + void *buf = NULL; + struct pbuf *p; + u16_t buflen, copylen; + int off = 0; + u8_t done = 0; + err_t err; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d, %p, %"SZT_F", 0x%x, ..)\n", s, mem, len, flags)); + sock = get_socket(s); + if (!sock) { + return -1; + } + + do { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: top while sock->lastdata=%p\n", sock->lastdata)); + /* Check if there is data left from the last recv operation. */ + if (sock->lastdata) { + buf = sock->lastdata; + } else { + /* If this is non-blocking call, then check first */ + if (((flags & MSG_DONTWAIT) || netconn_is_nonblocking(sock->conn)) && + (sock->rcvevent <= 0)) { + if (off > 0) { +#if ESP_AUTO_RECV + /* update receive window */ + netconn_recved(sock->conn, (u32_t)off); +#endif + /* already received data, return that */ + sock_set_errno(sock, 0); + return off; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): returning EWOULDBLOCK\n", s)); +#if ESP_LWIP + sock_set_errno(sock, EWOULDBLOCK); +#else + set_errno(EWOULDBLOCK); +#endif + return -1; + } + + /* No data was left from the previous operation, so we try to get + some from the network. */ + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { + err = netconn_recv_tcp_pbuf(sock->conn, (struct pbuf **)&buf); + } else { + err = netconn_recv(sock->conn, (struct netbuf **)&buf); + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: netconn_recv err=%d, netbuf=%p\n", + err, buf)); + + if (err != ERR_OK) { + if (off > 0) { +#if ESP_AUTO_RECV + /* update receive window */ + netconn_recved(sock->conn, (u32_t)off); +#endif + if (err == ERR_CLSD) { + /* closed but already received data, ensure select gets the FIN, too */ + event_callback(sock->conn, NETCONN_EVT_RCVPLUS, 0); + } + /* already received data, return that */ + sock_set_errno(sock, 0); + return off; + } + /* We should really do some error checking here. */ + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): buf == NULL, error is \"%s\"!\n", + s, lwip_strerr(err))); + sock_set_errno(sock, err_to_errno(err)); + if (err == ERR_CLSD) { + return 0; + } else { + return -1; + } + } + LWIP_ASSERT("buf != NULL", buf != NULL); + sock->lastdata = buf; + } + + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { + p = (struct pbuf *)buf; + } else { + p = ((struct netbuf *)buf)->p; + } + buflen = p->tot_len; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: buflen=%"U16_F" len=%"SZT_F" off=%d sock->lastoffset=%"U16_F"\n", + buflen, len, off, sock->lastoffset)); + + buflen -= sock->lastoffset; + + if (len > buflen) { + copylen = buflen; + } else { + copylen = (u16_t)len; + } + + /* copy the contents of the received buffer into + the supplied memory pointer mem */ + pbuf_copy_partial(p, (u8_t*)mem + off, copylen, sock->lastoffset); + + off += copylen; + + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { + LWIP_ASSERT("invalid copylen, len would underflow", len >= copylen); + len -= copylen; + if ((len <= 0) || + (p->flags & PBUF_FLAG_PUSH) || + (sock->rcvevent <= 0) || + ((flags & MSG_PEEK) != 0)) { + done = 1; + } + } else { + done = 1; + } + + /* Check to see from where the data was.*/ + if (done) { +#if !SOCKETS_DEBUG + if (from && fromlen) +#endif /* !SOCKETS_DEBUG */ + { + u16_t port; + ip_addr_t tmpaddr; + ip_addr_t *fromaddr; + union sockaddr_aligned saddr; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom(%d): addr=", s)); + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { + fromaddr = &tmpaddr; + netconn_getaddr(sock->conn, fromaddr, &port, 0); + } else { + port = netbuf_fromport((struct netbuf *)buf); + fromaddr = netbuf_fromaddr((struct netbuf *)buf); + } + +#if LWIP_IPV4 && LWIP_IPV6 + /* Dual-stack: Map IPv4 addresses to IPv4 mapped IPv6 */ + if (NETCONNTYPE_ISIPV6(netconn_type(sock->conn)) && IP_IS_V4(fromaddr)) { + ip4_2_ipv4_mapped_ipv6(ip_2_ip6(fromaddr), ip_2_ip4(fromaddr)); + IP_SET_TYPE(fromaddr, IPADDR_TYPE_V6); + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + + IPADDR_PORT_TO_SOCKADDR(&saddr, fromaddr, port); + ip_addr_debug_print(SOCKETS_DEBUG, fromaddr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F" len=%d\n", port, off)); +#if SOCKETS_DEBUG + if (from && fromlen) +#endif /* SOCKETS_DEBUG */ + { + if (*fromlen > saddr.sa.sa_len) { + *fromlen = saddr.sa.sa_len; + } + MEMCPY(from, &saddr, *fromlen); + } + } +#if ESP_LWIP + /*fix the code for setting the UDP PROTO's remote infomation by liuh at 2014.8.27*/ + if (!from || !fromlen) { + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_UDP) { + u16_t port; + ip_addr_t *fromaddr; + + port = netbuf_fromport((struct netbuf *)buf); + fromaddr = netbuf_fromaddr((struct netbuf *)buf); + + sock->conn->pcb.udp->remote_ip.u_addr.ip4.addr = fromaddr->u_addr.ip4.addr; + sock->conn->pcb.udp->remote_port = port; + } + } +#endif + } + + /* If we don't peek the incoming message... */ + if ((flags & MSG_PEEK) == 0) { + /* If this is a TCP socket, check if there is data left in the + buffer. If so, it should be saved in the sock structure for next + time around. */ + if ((NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) && (buflen - copylen > 0)) { + sock->lastdata = buf; + sock->lastoffset += copylen; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: lastdata now netbuf=%p\n", buf)); + } else { + sock->lastdata = NULL; + sock->lastoffset = 0; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvfrom: deleting netbuf=%p\n", buf)); + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { + pbuf_free((struct pbuf *)buf); + } else { + netbuf_delete((struct netbuf *)buf); + } + buf = NULL; + } + } + } while (!done); + +#if ESP_AUTO_RECV + if ((off > 0) && (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) && + ((flags & MSG_PEEK) == 0)) { + /* update receive window */ + netconn_recved(sock->conn, (u32_t)off); + } +#endif + sock_set_errno(sock, 0); + return off; +} + +int +lwip_read(int s, void *mem, size_t len) +{ + return lwip_recvfrom(s, mem, len, 0, NULL, NULL); +} + +int +lwip_recv(int s, void *mem, size_t len, int flags) +{ + return lwip_recvfrom(s, mem, len, flags, NULL, NULL); +} + +int +lwip_send(int s, const void *data, size_t size, int flags) +{ + struct lwip_sock *sock; + err_t err; + u8_t write_flags; + size_t written; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d, data=%p, size=%"SZT_F", flags=0x%x)\n", + s, data, size, flags)); + + sock = get_socket(s); + if (!sock) { + return -1; + } + + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) { +#if (LWIP_UDP || LWIP_RAW) + return lwip_sendto(s, data, size, flags, NULL, 0); +#else /* (LWIP_UDP || LWIP_RAW) */ + sock_set_errno(sock, err_to_errno(ERR_ARG)); + return -1; +#endif /* (LWIP_UDP || LWIP_RAW) */ + } + + write_flags = NETCONN_COPY | + ((flags & MSG_MORE) ? NETCONN_MORE : 0) | + ((flags & MSG_DONTWAIT) ? NETCONN_DONTBLOCK : 0); + written = 0; + err = netconn_write_partly(sock->conn, data, size, write_flags, &written); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_send(%d) err=%d written=%"SZT_F"\n", s, err, written)); + sock_set_errno(sock, err_to_errno(err)); + return (err == ERR_OK ? (int)written : -1); +} + +ssize_t +lwip_recvmsg(int s, struct msghdr *message, int flags) +{ + struct lwip_sock *sock; + int i; + ssize_t buflen; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_recvmsg(%d, message=%p, flags=0x%x)\n", s, (void *)message, flags)); + LWIP_ERROR("lwip_recvmsg: invalid message pointer", message != NULL, return ERR_ARG;); + LWIP_ERROR("lwip_recvmsg: unsupported flags", (flags & ~(MSG_PEEK|MSG_DONTWAIT)) == 0, + set_errno(EOPNOTSUPP); return -1;); + + if ((message->msg_iovlen <= 0) || (message->msg_iovlen > IOV_MAX)) { + set_errno(EMSGSIZE); + return -1; + } + + sock = get_socket(s); + if (!sock) { + return -1; + } + + /* check for valid vectors */ + buflen = 0; + for (i = 0; i < message->msg_iovlen; i++) { + if ((message->msg_iov[i].iov_base == NULL) || ((ssize_t)message->msg_iov[i].iov_len <= 0) || + ((size_t)(ssize_t)message->msg_iov[i].iov_len != message->msg_iov[i].iov_len) || + ((ssize_t)(buflen + (ssize_t)message->msg_iov[i].iov_len) <= 0)) { + sock_set_errno(sock, ERR_VAL); + return -1; + } + buflen = (ssize_t)(buflen + (ssize_t)message->msg_iov[i].iov_len); + } + + int recv_flags = flags; + message->msg_flags = 0; + /* recv the data */ + buflen = 0; + for (i = 0; i < message->msg_iovlen; i++) { + /* try to receive into this vector's buffer */ + ssize_t recvd_local = lwip_recvfrom(s, message->msg_iov[i].iov_base, message->msg_iov[i].iov_len, recv_flags, NULL, NULL); + if (recvd_local > 0) { + /* sum up received bytes */ + buflen += recvd_local; + } + if ((recvd_local < 0) || (recvd_local < (int)message->msg_iov[i].iov_len) || + (flags & MSG_PEEK)) { + /* returned prematurely (or peeking, which might actually be limitated to the first iov) */ + if (buflen <= 0) { + /* nothing received at all, propagate the error */ + buflen = recvd_local; + } + break; + } + /* pass MSG_DONTWAIT to lwip_recv_tcp() to prevent waiting for more data */ + recv_flags |= MSG_DONTWAIT; + } + if (buflen > 0) { + /* reset socket error since we have received something */ + sock_set_errno(sock, 0); + } + + return buflen; +} + +int +lwip_sendmsg(int s, const struct msghdr *msg, int flags) +{ + struct lwip_sock *sock; + int i; +#if LWIP_TCP + u8_t write_flags; + size_t written; +#endif + int size = 0; + err_t err = ERR_OK; + + sock = get_socket(s); + if (!sock) { + return -1; + } + + LWIP_ERROR("lwip_sendmsg: invalid msghdr", msg != NULL, + sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;); + + LWIP_UNUSED_ARG(msg->msg_control); + LWIP_UNUSED_ARG(msg->msg_controllen); + LWIP_UNUSED_ARG(msg->msg_flags); + LWIP_ERROR("lwip_sendmsg: invalid msghdr iov", (msg->msg_iov != NULL && msg->msg_iovlen != 0), + sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;); + + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { +#if LWIP_TCP + write_flags = NETCONN_COPY | + ((flags & MSG_MORE) ? NETCONN_MORE : 0) | + ((flags & MSG_DONTWAIT) ? NETCONN_DONTBLOCK : 0); + + for (i = 0; i < msg->msg_iovlen; i++) { + u8_t apiflags = write_flags; + if (i + 1 < msg->msg_iovlen) { + apiflags |= NETCONN_MORE; + } + written = 0; + err = netconn_write_partly(sock->conn, msg->msg_iov[i].iov_base, msg->msg_iov[i].iov_len, write_flags, &written); + if (err == ERR_OK) { + size += written; + /* check that the entire IO vector was accepected, if not return a partial write */ + if (written != msg->msg_iov[i].iov_len) + break; + } + /* none of this IO vector was accepted, but previous was, return partial write and conceal ERR_WOULDBLOCK */ + else if (err == ERR_WOULDBLOCK && size > 0) { + err = ERR_OK; + /* let ERR_WOULDBLOCK persist on the netconn since we are returning ERR_OK */ + break; + } else { + size = -1; + break; + } + } + sock_set_errno(sock, err_to_errno(err)); + return size; +#else /* LWIP_TCP */ + sock_set_errno(sock, err_to_errno(ERR_ARG)); + return -1; +#endif /* LWIP_TCP */ + } + /* else, UDP and RAW NETCONNs */ +#if LWIP_UDP || LWIP_RAW + { + struct netbuf *chain_buf; + + LWIP_UNUSED_ARG(flags); + LWIP_ERROR("lwip_sendmsg: invalid msghdr name", (((msg->msg_name == NULL) && (msg->msg_namelen == 0)) || + IS_SOCK_ADDR_LEN_VALID(msg->msg_namelen)) , + sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;); + + /* initialize chain buffer with destination */ + chain_buf = netbuf_new(); + if (!chain_buf) { + sock_set_errno(sock, err_to_errno(ERR_MEM)); + return -1; + } + if (msg->msg_name) { + u16_t remote_port; + SOCKADDR_TO_IPADDR_PORT((const struct sockaddr *)msg->msg_name, &chain_buf->addr, remote_port); + netbuf_fromport(chain_buf) = remote_port; + } +#if LWIP_NETIF_TX_SINGLE_PBUF + for (i = 0; i < msg->msg_iovlen; i++) { + size += msg->msg_iov[i].iov_len; + } + /* Allocate a new netbuf and copy the data into it. */ + if (netbuf_alloc(chain_buf, (u16_t)size) == NULL) { + err = ERR_MEM; + } else { + /* flatten the IO vectors */ + size_t offset = 0; + for (i = 0; i < msg->msg_iovlen; i++) { + MEMCPY(&((u8_t*)chain_buf->p->payload)[offset], msg->msg_iov[i].iov_base, msg->msg_iov[i].iov_len); + offset += msg->msg_iov[i].iov_len; + } +#if LWIP_CHECKSUM_ON_COPY + { + /* This can be improved by using LWIP_CHKSUM_COPY() and aggregating the checksum for each IO vector */ + u16_t chksum = ~inet_chksum_pbuf(chain_buf->p); + netbuf_set_chksum(chain_buf, chksum); + } +#endif /* LWIP_CHECKSUM_ON_COPY */ + err = ERR_OK; + } +#else /* LWIP_NETIF_TX_SINGLE_PBUF */ + /* create a chained netbuf from the IO vectors. NOTE: we assemble a pbuf chain + manually to avoid having to allocate, chain, and delete a netbuf for each iov */ + for (i = 0; i < msg->msg_iovlen; i++) { + struct pbuf *p = pbuf_alloc(PBUF_TRANSPORT, 0, PBUF_REF); + if (p == NULL) { + err = ERR_MEM; /* let netbuf_delete() cleanup chain_buf */ + break; + } + p->payload = msg->msg_iov[i].iov_base; + LWIP_ASSERT("iov_len < u16_t", msg->msg_iov[i].iov_len <= 0xFFFF); + p->len = p->tot_len = (u16_t)msg->msg_iov[i].iov_len; + /* netbuf empty, add new pbuf */ + if (chain_buf->p == NULL) { + chain_buf->p = chain_buf->ptr = p; + /* add pbuf to existing pbuf chain */ + } else { + pbuf_cat(chain_buf->p, p); + } + } + /* save size of total chain */ + if (err == ERR_OK) { + size = netbuf_len(chain_buf); + } +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + + if (err == ERR_OK) { +#if LWIP_IPV4 && LWIP_IPV6 + /* Dual-stack: Unmap IPv4 mapped IPv6 addresses */ + if (IP_IS_V6_VAL(chain_buf->addr) && ip6_addr_isipv4mappedipv6(ip_2_ip6(&chain_buf->addr))) { + unmap_ipv4_mapped_ipv6(ip_2_ip4(&chain_buf->addr), ip_2_ip6(&chain_buf->addr)); + IP_SET_TYPE_VAL(chain_buf->addr, IPADDR_TYPE_V4); + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + + /* send the data */ + err = netconn_send(sock->conn, chain_buf); + } + + /* deallocated the buffer */ + netbuf_delete(chain_buf); + + sock_set_errno(sock, err_to_errno(err)); + return (err == ERR_OK ? size : -1); + } +#else /* LWIP_UDP || LWIP_RAW */ + sock_set_errno(sock, err_to_errno(ERR_ARG)); + return -1; +#endif /* LWIP_UDP || LWIP_RAW */ +} + +#if ESP_LWIP +int ESP_IRAM_ATTR +#else +int +#endif +lwip_sendto(int s, const void *data, size_t size, int flags, + const struct sockaddr *to, socklen_t tolen) +{ + struct lwip_sock *sock; + err_t err; + u16_t short_size; + u16_t remote_port; + struct netbuf buf; + + sock = get_socket(s); + if (!sock) { + return -1; + } + + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) == NETCONN_TCP) { +#if LWIP_TCP + return lwip_send(s, data, size, flags); +#else /* LWIP_TCP */ + LWIP_UNUSED_ARG(flags); + sock_set_errno(sock, err_to_errno(ERR_ARG)); + return -1; +#endif /* LWIP_TCP */ + } + + /* @todo: split into multiple sendto's? */ + LWIP_ASSERT("lwip_sendto: size must fit in u16_t", size <= 0xffff); + short_size = (u16_t)size; + LWIP_ERROR("lwip_sendto: invalid address", (((to == NULL) && (tolen == 0)) || + (IS_SOCK_ADDR_LEN_VALID(tolen) && + IS_SOCK_ADDR_TYPE_VALID(to) && IS_SOCK_ADDR_ALIGNED(to))), + sock_set_errno(sock, err_to_errno(ERR_ARG)); return -1;); + LWIP_UNUSED_ARG(tolen); + + /* initialize a buffer */ + buf.p = buf.ptr = NULL; +#if LWIP_CHECKSUM_ON_COPY + buf.flags = 0; +#endif /* LWIP_CHECKSUM_ON_COPY */ + if (to) { + SOCKADDR_TO_IPADDR_PORT(to, &buf.addr, remote_port); + } else { + remote_port = 0; + ip_addr_set_any(NETCONNTYPE_ISIPV6(netconn_type(sock->conn)), &buf.addr); + } + netbuf_fromport(&buf) = remote_port; + + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_sendto(%d, data=%p, short_size=%"U16_F", flags=0x%x to=", + s, data, short_size, flags)); + ip_addr_debug_print(SOCKETS_DEBUG, &buf.addr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F"\n", remote_port)); + + /* make the buffer point to the data that should be sent */ +#if LWIP_NETIF_TX_SINGLE_PBUF + /* Allocate a new netbuf and copy the data into it. */ + if (netbuf_alloc(&buf, short_size) == NULL) { + err = ERR_MEM; + } else { +#if LWIP_CHECKSUM_ON_COPY + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_RAW) { + u16_t chksum = LWIP_CHKSUM_COPY(buf.p->payload, data, short_size); + netbuf_set_chksum(&buf, chksum); + } else +#endif /* LWIP_CHECKSUM_ON_COPY */ + { + MEMCPY(buf.p->payload, data, short_size); + } + err = ERR_OK; + } +#else /* LWIP_NETIF_TX_SINGLE_PBUF */ + err = netbuf_ref(&buf, data, short_size); +#endif /* LWIP_NETIF_TX_SINGLE_PBUF */ + if (err == ERR_OK) { +#if LWIP_IPV4 && LWIP_IPV6 + /* Dual-stack: Unmap IPv4 mapped IPv6 addresses */ + if (IP_IS_V6_VAL(buf.addr) && ip6_addr_isipv4mappedipv6(ip_2_ip6(&buf.addr))) { + unmap_ipv4_mapped_ipv6(ip_2_ip4(&buf.addr), ip_2_ip6(&buf.addr)); + IP_SET_TYPE_VAL(buf.addr, IPADDR_TYPE_V4); + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + + /* send the data */ + err = netconn_send(sock->conn, &buf); + } + + /* deallocated the buffer */ + netbuf_free(&buf); + + sock_set_errno(sock, err_to_errno(err)); + return (err == ERR_OK ? short_size : -1); +} + +int +lwip_socket(int domain, int type, int protocol) +{ + struct netconn *conn; + int i; + + LWIP_UNUSED_ARG(domain); /* @todo: check this */ + + /* create a netconn */ + switch (type) { + case SOCK_RAW: + conn = netconn_new_with_proto_and_callback(DOMAIN_TO_NETCONN_TYPE(domain, NETCONN_RAW), + (u8_t)protocol, event_callback); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_RAW, %d) = ", + domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); + break; + case SOCK_DGRAM: + conn = netconn_new_with_callback(DOMAIN_TO_NETCONN_TYPE(domain, + ((protocol == IPPROTO_UDPLITE) ? NETCONN_UDPLITE : NETCONN_UDP)) , + event_callback); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_DGRAM, %d) = ", + domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); + break; + case SOCK_STREAM: + conn = netconn_new_with_callback(DOMAIN_TO_NETCONN_TYPE(domain, NETCONN_TCP), event_callback); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%s, SOCK_STREAM, %d) = ", + domain == PF_INET ? "PF_INET" : "UNKNOWN", protocol)); +#if ESP_AUTO_RECV + if (conn != NULL) { + /* Prevent automatic window updates, we do this on our own! */ + netconn_set_noautorecved(conn, 1); + } +#endif + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_socket(%d, %d/UNKNOWN, %d) = -1\n", + domain, type, protocol)); + set_errno(EINVAL); + return -1; + } + + if (!conn) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("-1 / ENOBUFS (could not create netconn)\n")); + set_errno(ENOBUFS); + return -1; + } + + i = alloc_socket(conn, 0); + + if (i == -1) { + netconn_delete(conn); + set_errno(ENFILE); + return -1; + } + conn->socket = i; + LWIP_DEBUGF(SOCKETS_DEBUG, ("%d\n", i)); + set_errno(0); + return i; +} + +int +lwip_write(int s, const void *data, size_t size) +{ + return lwip_send(s, data, size, 0); +} + +int +lwip_writev(int s, const struct iovec *iov, int iovcnt) +{ + struct msghdr msg; + + msg.msg_name = NULL; + msg.msg_namelen = 0; + /* Hack: we have to cast via number to cast from 'const' pointer to non-const. + Blame the opengroup standard for this inconsistency. */ + msg.msg_iov = LWIP_CONST_CAST(struct iovec *, iov); + msg.msg_iovlen = iovcnt; + msg.msg_control = NULL; + msg.msg_controllen = 0; + msg.msg_flags = 0; + return lwip_sendmsg(s, &msg, 0); +} + +/** + * Go through the readset and writeset lists and see which socket of the sockets + * set in the sets has events. On return, readset, writeset and exceptset have + * the sockets enabled that had events. + * + * @param maxfdp1 the highest socket index in the sets + * @param readset_in set of sockets to check for read events + * @param writeset_in set of sockets to check for write events + * @param exceptset_in set of sockets to check for error events + * @param readset_out set of sockets that had read events + * @param writeset_out set of sockets that had write events + * @param exceptset_out set os sockets that had error events + * @return number of sockets that had events (read/write/exception) (>= 0) + */ +static int +lwip_selscan(int maxfdp1, fd_set *readset_in, fd_set *writeset_in, fd_set *exceptset_in, + fd_set *readset_out, fd_set *writeset_out, fd_set *exceptset_out) +{ + int i, nready = 0; + fd_set lreadset, lwriteset, lexceptset; + struct lwip_sock *sock; + SYS_ARCH_DECL_PROTECT(lev); + + FD_ZERO(&lreadset); + FD_ZERO(&lwriteset); + FD_ZERO(&lexceptset); + + /* Go through each socket in each list to count number of sockets which + currently match */ + for (i = LWIP_SOCKET_OFFSET; i < maxfdp1; i++) { + /* if this FD is not in the set, continue */ + if (!(readset_in && FD_ISSET(i, readset_in)) && + !(writeset_in && FD_ISSET(i, writeset_in)) && + !(exceptset_in && FD_ISSET(i, exceptset_in))) { + continue; + } + /* First get the socket's status (protected)... */ + SYS_ARCH_PROTECT(lev); + sock = tryget_socket(i); + if (sock != NULL) { + void* lastdata = sock->lastdata; + s16_t rcvevent = sock->rcvevent; + u16_t sendevent = sock->sendevent; + u16_t errevent = sock->errevent; + SYS_ARCH_UNPROTECT(lev); + + /* ... then examine it: */ + /* See if netconn of this socket is ready for read */ + if (readset_in && FD_ISSET(i, readset_in) && ((lastdata != NULL) || (rcvevent > 0))) { + FD_SET(i, &lreadset); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for reading\n", i)); + nready++; + } + /* See if netconn of this socket is ready for write */ + if (writeset_in && FD_ISSET(i, writeset_in) && (sendevent != 0)) { + FD_SET(i, &lwriteset); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for writing\n", i)); + nready++; + } + /* See if netconn of this socket had an error */ + if (exceptset_in && FD_ISSET(i, exceptset_in) && (errevent != 0)) { + FD_SET(i, &lexceptset); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_selscan: fd=%d ready for exception\n", i)); + nready++; + } + } else { + SYS_ARCH_UNPROTECT(lev); + /* continue on to next FD in list */ + } + } + /* copy local sets to the ones provided as arguments */ + *readset_out = lreadset; + *writeset_out = lwriteset; + *exceptset_out = lexceptset; + + LWIP_ASSERT("nready >= 0", nready >= 0); + return nready; +} + +int +lwip_select(int maxfdp1, fd_set *readset, fd_set *writeset, fd_set *exceptset, + struct timeval *timeout) +{ + u32_t waitres = 0; + int nready; + fd_set lreadset, lwriteset, lexceptset; + u32_t msectimeout; + struct lwip_select_cb select_cb; + int i; + int maxfdp2; +#if LWIP_NETCONN_SEM_PER_THREAD + int waited = 0; +#endif + SYS_ARCH_DECL_PROTECT(lev); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select(%d, %p, %p, %p, tvsec=%"S32_F" tvusec=%"S32_F")\n", + maxfdp1, (void *)readset, (void *) writeset, (void *) exceptset, + timeout ? (s32_t)timeout->tv_sec : (s32_t)-1, + timeout ? (s32_t)timeout->tv_usec : (s32_t)-1)); + + /* Go through each socket in each list to count number of sockets which + currently match */ + nready = lwip_selscan(maxfdp1, readset, writeset, exceptset, &lreadset, &lwriteset, &lexceptset); + + /* If we don't have any current events, then suspend if we are supposed to */ + if (!nready) { + if (timeout && timeout->tv_sec == 0 && timeout->tv_usec == 0) { + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: no timeout, returning 0\n")); + /* This is OK as the local fdsets are empty and nready is zero, + or we would have returned earlier. */ + goto return_copy_fdsets; + } + + /* None ready: add our semaphore to list: + We don't actually need any dynamic memory. Our entry on the + list is only valid while we are in this function, so it's ok + to use local variables. */ + + select_cb.next = NULL; + select_cb.prev = NULL; + select_cb.readset = readset; + select_cb.writeset = writeset; + select_cb.exceptset = exceptset; + select_cb.sem_signalled = 0; +#if LWIP_NETCONN_SEM_PER_THREAD + select_cb.sem = LWIP_NETCONN_THREAD_SEM_GET(); +#else /* LWIP_NETCONN_SEM_PER_THREAD */ + if (sys_sem_new(&select_cb.sem, 0) != ERR_OK) { + /* failed to create semaphore */ + set_errno(ENOMEM); + return -1; + } +#endif /* LWIP_NETCONN_SEM_PER_THREAD */ + + /* Protect the select_cb_list */ + SYS_ARCH_PROTECT(lev); + + /* Put this select_cb on top of list */ + select_cb.next = select_cb_list; + if (select_cb_list != NULL) { + select_cb_list->prev = &select_cb; + } + select_cb_list = &select_cb; + /* Increasing this counter tells event_callback that the list has changed. */ + select_cb_ctr++; + + /* Now we can safely unprotect */ + SYS_ARCH_UNPROTECT(lev); + + /* Increase select_waiting for each socket we are interested in */ + maxfdp2 = maxfdp1; + for (i = LWIP_SOCKET_OFFSET; i < maxfdp1; i++) { + if ((readset && FD_ISSET(i, readset)) || + (writeset && FD_ISSET(i, writeset)) || + (exceptset && FD_ISSET(i, exceptset))) { + struct lwip_sock *sock; + SYS_ARCH_PROTECT(lev); + sock = tryget_socket(i); + if (sock != NULL) { + sock->select_waiting++; + LWIP_ASSERT("sock->select_waiting > 0", sock->select_waiting > 0); + } else { + /* Not a valid socket */ + nready = -1; + maxfdp2 = i; + SYS_ARCH_UNPROTECT(lev); + break; + } + SYS_ARCH_UNPROTECT(lev); + } + } + + if (nready >= 0) { + /* Call lwip_selscan again: there could have been events between + the last scan (without us on the list) and putting us on the list! */ + nready = lwip_selscan(maxfdp1, readset, writeset, exceptset, &lreadset, &lwriteset, &lexceptset); + if (!nready) { + /* Still none ready, just wait to be woken */ + if (timeout == 0) { + /* Wait forever */ + msectimeout = 0; + } else { + msectimeout = ((timeout->tv_sec * 1000) + ((timeout->tv_usec + 500)/1000)); + if (msectimeout == 0) { + /* Wait 1ms at least (0 means wait forever) */ + msectimeout = 1; + } + } + + waitres = sys_arch_sem_wait(SELECT_SEM_PTR(select_cb.sem), msectimeout); +#if LWIP_NETCONN_SEM_PER_THREAD + waited = 1; +#endif + } + } + + /* Decrease select_waiting for each socket we are interested in */ + for (i = LWIP_SOCKET_OFFSET; i < maxfdp2; i++) { + if ((readset && FD_ISSET(i, readset)) || + (writeset && FD_ISSET(i, writeset)) || + (exceptset && FD_ISSET(i, exceptset))) { + struct lwip_sock *sock; + SYS_ARCH_PROTECT(lev); + sock = tryget_socket(i); + if (sock != NULL) { + /* for now, handle select_waiting==0... */ + LWIP_ASSERT("sock->select_waiting > 0", sock->select_waiting > 0); + if (sock->select_waiting > 0) { + sock->select_waiting--; + } + } else { + /* Not a valid socket */ + nready = -1; + } + SYS_ARCH_UNPROTECT(lev); + } + } + /* Take us off the list */ + SYS_ARCH_PROTECT(lev); + if (select_cb.next != NULL) { + select_cb.next->prev = select_cb.prev; + } + if (select_cb_list == &select_cb) { + LWIP_ASSERT("select_cb.prev == NULL", select_cb.prev == NULL); + select_cb_list = select_cb.next; + } else { + LWIP_ASSERT("select_cb.prev != NULL", select_cb.prev != NULL); + select_cb.prev->next = select_cb.next; + } + /* Increasing this counter tells event_callback that the list has changed. */ + select_cb_ctr++; + SYS_ARCH_UNPROTECT(lev); + +#if LWIP_NETCONN_SEM_PER_THREAD + if (select_cb.sem_signalled && (!waited || (waitres == SYS_ARCH_TIMEOUT))) { + /* don't leave the thread-local semaphore signalled */ + sys_arch_sem_wait(select_cb.sem, 1); + } +#else /* LWIP_NETCONN_SEM_PER_THREAD */ + sys_sem_free(&select_cb.sem); +#endif /* LWIP_NETCONN_SEM_PER_THREAD */ + + if (nready < 0) { + /* This happens when a socket got closed while waiting */ + set_errno(EBADF); + return -1; + } + + if (waitres == SYS_ARCH_TIMEOUT) { + /* Timeout */ + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: timeout expired\n")); + /* This is OK as the local fdsets are empty and nready is zero, + or we would have returned earlier. */ + goto return_copy_fdsets; + } + + /* See what's set */ + nready = lwip_selscan(maxfdp1, readset, writeset, exceptset, &lreadset, &lwriteset, &lexceptset); + } + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_select: nready=%d\n", nready)); +return_copy_fdsets: + set_errno(0); + if (readset) { + *readset = lreadset; + } + if (writeset) { + *writeset = lwriteset; + } + if (exceptset) { + *exceptset = lexceptset; + } + return nready; +} + +/** + * Callback registered in the netconn layer for each socket-netconn. + * Processes recvevent (data available) and wakes up tasks waiting for select. + */ +#if ESP_LWIP +static void ESP_IRAM_ATTR +#else +static void +#endif +event_callback(struct netconn *conn, enum netconn_evt evt, u16_t len) +{ + int s; + struct lwip_sock *sock; + struct lwip_select_cb *scb; + int last_select_cb_ctr; + SYS_ARCH_DECL_PROTECT(lev); + + LWIP_UNUSED_ARG(len); + + /* Get socket */ + if (conn) { + s = conn->socket; + if (s < 0) { + /* Data comes in right away after an accept, even though + * the server task might not have created a new socket yet. + * Just count down (or up) if that's the case and we + * will use the data later. Note that only receive events + * can happen before the new socket is set up. */ + SYS_ARCH_PROTECT(lev); + if (conn->socket < 0) { + if (evt == NETCONN_EVT_RCVPLUS) { + conn->socket--; + } + SYS_ARCH_UNPROTECT(lev); + return; + } + s = conn->socket; + SYS_ARCH_UNPROTECT(lev); + } + + sock = get_socket(s); + if (!sock) { + return; + } + } else { + return; + } + + SYS_ARCH_PROTECT(lev); + /* Set event as required */ + switch (evt) { + case NETCONN_EVT_RCVPLUS: + sock->rcvevent++; + break; + case NETCONN_EVT_RCVMINUS: + sock->rcvevent--; + break; + case NETCONN_EVT_SENDPLUS: + sock->sendevent = 1; + break; + case NETCONN_EVT_SENDMINUS: + sock->sendevent = 0; + break; + case NETCONN_EVT_ERROR: + sock->errevent = 1; + break; + default: + LWIP_ASSERT("unknown event", 0); + break; + } + + if (sock->select_waiting == 0) { + /* noone is waiting for this socket, no need to check select_cb_list */ + SYS_ARCH_UNPROTECT(lev); + // [MS_CHANGE] - Signal the CLR that a socket event has occured + // TODO: We may want to investigate other ways to signal + // the CLR (maybe based on which socket received the + // event). + sys_signal_sock_event(); + //[END_MS_CHANGE] + return; + } + + /* Now decide if anyone is waiting for this socket */ + /* NOTE: This code goes through the select_cb_list list multiple times + ONLY IF a select was actually waiting. We go through the list the number + of waiting select calls + 1. This list is expected to be small. */ + + /* At this point, SYS_ARCH is still protected! */ +again: + for (scb = select_cb_list; scb != NULL; scb = scb->next) { + /* remember the state of select_cb_list to detect changes */ + last_select_cb_ctr = select_cb_ctr; + if (scb->sem_signalled == 0) { + /* semaphore not signalled yet */ + int do_signal = 0; + /* Test this select call for our socket */ + if (sock->rcvevent > 0) { + if (scb->readset && FD_ISSET(s, scb->readset)) { + do_signal = 1; + } + } + if (sock->sendevent != 0) { + if (!do_signal && scb->writeset && FD_ISSET(s, scb->writeset)) { + do_signal = 1; + } + } + if (sock->errevent != 0) { + if (!do_signal && scb->exceptset && FD_ISSET(s, scb->exceptset)) { + do_signal = 1; + } + } + if (do_signal) { + scb->sem_signalled = 1; + /* Don't call SYS_ARCH_UNPROTECT() before signaling the semaphore, as this might + lead to the select thread taking itself off the list, invalidating the semaphore. */ + sys_sem_signal(SELECT_SEM_PTR(scb->sem)); + } + } + /* unlock interrupts with each step */ + SYS_ARCH_UNPROTECT(lev); + /* this makes sure interrupt protection time is short */ + SYS_ARCH_PROTECT(lev); + if (last_select_cb_ctr != select_cb_ctr) { + /* someone has changed select_cb_list, restart at the beginning */ + goto again; + } + } + SYS_ARCH_UNPROTECT(lev); + // [MS_CHANGE] - Signal the CLR that a socket event has occured + // TODO: We may want to investigate other ways to signal + // the CLR (maybe based on which socket received the + // event). + sys_signal_sock_event(); + //[END_MS_CHANGE] +} + +/** + * Close one end of a full-duplex connection. + */ +int +lwip_shutdown(int s, int how) +{ + struct lwip_sock *sock; + err_t err; + u8_t shut_rx = 0, shut_tx = 0; + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_shutdown(%d, how=%d)\n", s, how)); + + sock = get_socket(s); + if (!sock) { + return -1; + } + + if (sock->conn != NULL) { + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) { + sock_set_errno(sock, EOPNOTSUPP); + return -1; + } + } else { + sock_set_errno(sock, ENOTCONN); + return -1; + } + + if (how == SHUT_RD) { + shut_rx = 1; + } else if (how == SHUT_WR) { + shut_tx = 1; + } else if (how == SHUT_RDWR) { + shut_rx = 1; + shut_tx = 1; + } else { + sock_set_errno(sock, EINVAL); + return -1; + } + err = netconn_shutdown(sock->conn, shut_rx, shut_tx); + + sock_set_errno(sock, err_to_errno(err)); + return (err == ERR_OK ? 0 : -1); +} + +static int +lwip_getaddrname(int s, struct sockaddr *name, socklen_t *namelen, u8_t local) +{ + struct lwip_sock *sock; + union sockaddr_aligned saddr; + ip_addr_t naddr; + u16_t port; + err_t err; + + sock = get_socket(s); + if (!sock) { + return -1; + } + + /* get the IP address and port */ + err = netconn_getaddr(sock->conn, &naddr, &port, local); + if (err != ERR_OK) { + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + +#if LWIP_IPV4 && LWIP_IPV6 + /* Dual-stack: Map IPv4 addresses to IPv4 mapped IPv6 */ + if (NETCONNTYPE_ISIPV6(netconn_type(sock->conn)) && + IP_IS_V4_VAL(naddr)) { + ip4_2_ipv4_mapped_ipv6(ip_2_ip6(&naddr), ip_2_ip4(&naddr)); + IP_SET_TYPE_VAL(naddr, IPADDR_TYPE_V6); + } +#endif /* LWIP_IPV4 && LWIP_IPV6 */ + + IPADDR_PORT_TO_SOCKADDR(&saddr, &naddr, port); + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getaddrname(%d, addr=", s)); + ip_addr_debug_print_val(SOCKETS_DEBUG, naddr); + LWIP_DEBUGF(SOCKETS_DEBUG, (" port=%"U16_F")\n", port)); + + if (*namelen > saddr.sa.sa_len) { + *namelen = saddr.sa.sa_len; + } + MEMCPY(name, &saddr, *namelen); + + sock_set_errno(sock, 0); + return 0; +} + +int +lwip_getpeername(int s, struct sockaddr *name, socklen_t *namelen) +{ + return lwip_getaddrname(s, name, namelen, 0); +} + +int +lwip_getsockname(int s, struct sockaddr *name, socklen_t *namelen) +{ + return lwip_getaddrname(s, name, namelen, 1); +} + +int +lwip_getsockopt(int s, int level, int optname, void *optval, socklen_t *optlen) +{ + u8_t err; + struct lwip_sock *sock = get_socket(s); +#if !LWIP_TCPIP_CORE_LOCKING + LWIP_SETGETSOCKOPT_DATA_VAR_DECLARE(data); +#endif /* !LWIP_TCPIP_CORE_LOCKING */ + + if (!sock) { + return -1; + } + + if ((NULL == optval) || (NULL == optlen)) { + sock_set_errno(sock, EFAULT); + return -1; + } + +#if LWIP_TCPIP_CORE_LOCKING + /* core-locking can just call the -impl function */ + LOCK_TCPIP_CORE(); + err = lwip_getsockopt_impl(s, level, optname, optval, optlen); + UNLOCK_TCPIP_CORE(); + +#else /* LWIP_TCPIP_CORE_LOCKING */ + +#if LWIP_MPU_COMPATIBLE + /* MPU_COMPATIBLE copies the optval data, so check for max size here */ + if (*optlen > LWIP_SETGETSOCKOPT_MAXOPTLEN) { + sock_set_errno(sock, ENOBUFS); + return -1; + } +#endif /* LWIP_MPU_COMPATIBLE */ + + LWIP_SETGETSOCKOPT_DATA_VAR_ALLOC(data, sock); + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).s = s; + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).level = level; + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optname = optname; + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optlen = *optlen; +#if !LWIP_MPU_COMPATIBLE + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optval.p = optval; +#endif /* !LWIP_MPU_COMPATIBLE */ + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).err = 0; +#if LWIP_NETCONN_SEM_PER_THREAD + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem = LWIP_NETCONN_THREAD_SEM_GET(); +#else + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem = &sock->conn->op_completed; +#endif + err = tcpip_callback(lwip_getsockopt_callback, &LWIP_SETGETSOCKOPT_DATA_VAR_REF(data)); + if (err != ERR_OK) { + LWIP_SETGETSOCKOPT_DATA_VAR_FREE(data); + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + sys_arch_sem_wait((sys_sem_t*)(LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem), 0); + + /* write back optlen and optval */ + *optlen = LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optlen; +#if LWIP_MPU_COMPATIBLE + MEMCPY(optval, LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optval, + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optlen); +#endif /* LWIP_MPU_COMPATIBLE */ + + /* maybe lwip_getsockopt_internal has changed err */ + err = LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).err; + LWIP_SETGETSOCKOPT_DATA_VAR_FREE(data); +#endif /* LWIP_TCPIP_CORE_LOCKING */ + + sock_set_errno(sock, err); + return err ? -1 : 0; +} + +#if !LWIP_TCPIP_CORE_LOCKING +/** lwip_getsockopt_callback: only used without CORE_LOCKING + * to get into the tcpip_thread + */ +static void +lwip_getsockopt_callback(void *arg) +{ + struct lwip_setgetsockopt_data *data; + LWIP_ASSERT("arg != NULL", arg != NULL); + data = (struct lwip_setgetsockopt_data*)arg; + + data->err = lwip_getsockopt_impl(data->s, data->level, data->optname, +#if LWIP_MPU_COMPATIBLE + data->optval, +#else /* LWIP_MPU_COMPATIBLE */ + data->optval.p, +#endif /* LWIP_MPU_COMPATIBLE */ + &data->optlen); + + sys_sem_signal((sys_sem_t*)(data->completed_sem)); +} +#endif /* LWIP_TCPIP_CORE_LOCKING */ + +/** lwip_getsockopt_impl: the actual implementation of getsockopt: + * same argument as lwip_getsockopt, either called directly or through callback + */ +static u8_t +lwip_getsockopt_impl(int s, int level, int optname, void *optval, socklen_t *optlen) +{ + u8_t err = 0; + struct lwip_sock *sock = tryget_socket(s); + if (!sock) { + return EBADF; + } + + switch (level) { + +/* Level: SOL_SOCKET */ + case SOL_SOCKET: + switch (optname) { + +#if LWIP_TCP + case SO_ACCEPTCONN: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, int); + if (NETCONNTYPE_GROUP(sock->conn->type) != NETCONN_TCP) { + return ENOPROTOOPT; + } + if ((sock->conn->pcb.tcp != NULL) && (sock->conn->pcb.tcp->state == LISTEN)) { + *(int*)optval = 1; + } else { + *(int*)optval = 0; + } + break; +#endif /* LWIP_TCP */ + + /* The option flags */ + case SO_BROADCAST: + case SO_KEEPALIVE: +#if SO_REUSE + case SO_REUSEADDR: +#endif /* SO_REUSE */ + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, int); + *(int*)optval = ip_get_option(sock->conn->pcb.ip, optname); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, optname=0x%x, ..) = %s\n", + s, optname, (*(int*)optval?"on":"off"))); + break; + + case SO_TYPE: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, int); + switch (NETCONNTYPE_GROUP(netconn_type(sock->conn))) { + case NETCONN_RAW: + *(int*)optval = SOCK_RAW; + break; + case NETCONN_TCP: + *(int*)optval = SOCK_STREAM; + break; + case NETCONN_UDP: + *(int*)optval = SOCK_DGRAM; + break; + default: /* unrecognized socket type */ + *(int*)optval = netconn_type(sock->conn); + LWIP_DEBUGF(SOCKETS_DEBUG, + ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE): unrecognized socket type %d\n", + s, *(int *)optval)); + } /* switch (netconn_type(sock->conn)) */ + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_TYPE) = %d\n", + s, *(int *)optval)); + break; + + case SO_ERROR: + LWIP_SOCKOPT_CHECK_OPTLEN(*optlen, int); + /* only overwrite ERR_OK or temporary errors */ + if (((sock->err == 0) || (sock->err == EINPROGRESS)) && (sock->conn != NULL)) { + sock_set_errno(sock, err_to_errno(sock->conn->last_err)); + } + *(int *)optval = (sock->err == 0xFF ? (int)-1 : (int)sock->err); + sock->err = 0; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, SO_ERROR) = %d\n", + s, *(int *)optval)); + break; + +#if LWIP_SO_SNDTIMEO + case SO_SNDTIMEO: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, LWIP_SO_SNDRCVTIMEO_OPTTYPE); + LWIP_SO_SNDRCVTIMEO_SET(optval, netconn_get_sendtimeout(sock->conn)); + break; +#endif /* LWIP_SO_SNDTIMEO */ +#if LWIP_SO_RCVTIMEO + case SO_RCVTIMEO: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, LWIP_SO_SNDRCVTIMEO_OPTTYPE); + LWIP_SO_SNDRCVTIMEO_SET(optval, netconn_get_recvtimeout(sock->conn)); + break; +#endif /* LWIP_SO_RCVTIMEO */ +#if LWIP_SO_RCVBUF + case SO_RCVBUF: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, int); + *(int *)optval = netconn_get_recvbufsize(sock->conn); + break; +#endif /* LWIP_SO_RCVBUF */ +#if LWIP_SO_LINGER + case SO_LINGER: + { + s16_t conn_linger; + struct linger* linger = (struct linger*)optval; + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, struct linger); + conn_linger = sock->conn->linger; + if (conn_linger >= 0) { + linger->l_onoff = 1; + linger->l_linger = (int)conn_linger; + } else { + linger->l_onoff = 0; + linger->l_linger = 0; + } + } + break; +#endif /* LWIP_SO_LINGER */ +#if LWIP_UDP + case SO_NO_CHECK: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, *optlen, int, NETCONN_UDP); +#if LWIP_UDPLITE + if ((udp_flags(sock->conn->pcb.udp) & UDP_FLAGS_UDPLITE) != 0) { + /* this flag is only available for UDP, not for UDP lite */ + return EAFNOSUPPORT; + } +#endif /* LWIP_UDPLITE */ + *(int*)optval = (udp_flags(sock->conn->pcb.udp) & UDP_FLAGS_NOCHKSUM) ? 1 : 0; + break; +#endif /* LWIP_UDP*/ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; + +/* Level: IPPROTO_IP */ + case IPPROTO_IP: + switch (optname) { + case IP_TTL: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, int); + *(int*)optval = sock->conn->pcb.ip->ttl; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TTL) = %d\n", + s, *(int *)optval)); + break; + case IP_TOS: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, int); + *(int*)optval = sock->conn->pcb.ip->tos; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_TOS) = %d\n", + s, *(int *)optval)); + break; +#if LWIP_MULTICAST_TX_OPTIONS + case IP_MULTICAST_TTL: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, u8_t); + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_UDP) { + return ENOPROTOOPT; + } + *(u8_t*)optval = udp_get_multicast_ttl(sock->conn->pcb.udp); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_TTL) = %d\n", + s, *(int *)optval)); + break; + case IP_MULTICAST_IF: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, struct in_addr); + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_UDP) { + return ENOPROTOOPT; + } + inet_addr_from_ip4addr((struct in_addr*)optval, udp_get_multicast_netif_addr(sock->conn->pcb.udp)); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_IF) = 0x%"X32_F"\n", + s, *(u32_t *)optval)); + break; + case IP_MULTICAST_LOOP: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, u8_t); + if ((sock->conn->pcb.udp->flags & UDP_FLAGS_MULTICAST_LOOP) != 0) { + *(u8_t*)optval = 1; + } else { + *(u8_t*)optval = 0; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, IP_MULTICAST_LOOP) = %d\n", + s, *(int *)optval)); + break; +#endif /* LWIP_MULTICAST_TX_OPTIONS */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; + +#if LWIP_TCP +/* Level: IPPROTO_TCP */ + case IPPROTO_TCP: + /* Special case: all IPPROTO_TCP option take an int */ + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, *optlen, int, NETCONN_TCP); + if (sock->conn->pcb.tcp->state == LISTEN) { + return EINVAL; + } + switch (optname) { + case TCP_NODELAY: + *(int*)optval = tcp_nagle_disabled(sock->conn->pcb.tcp); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_NODELAY) = %s\n", + s, (*(int*)optval)?"on":"off") ); + break; + case TCP_KEEPALIVE: + *(int*)optval = (int)sock->conn->pcb.tcp->keep_idle; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) = %d\n", + s, *(int *)optval)); + break; + +#if LWIP_TCP_KEEPALIVE + case TCP_KEEPIDLE: + *(int*)optval = (int)(sock->conn->pcb.tcp->keep_idle/1000); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_KEEPIDLE) = %d\n", + s, *(int *)optval)); + break; + case TCP_KEEPINTVL: + *(int*)optval = (int)(sock->conn->pcb.tcp->keep_intvl/1000); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_KEEPINTVL) = %d\n", + s, *(int *)optval)); + break; + case TCP_KEEPCNT: + *(int*)optval = (int)sock->conn->pcb.tcp->keep_cnt; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, TCP_KEEPCNT) = %d\n", + s, *(int *)optval)); + break; +#endif /* LWIP_TCP_KEEPALIVE */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; +#endif /* LWIP_TCP */ + +#if LWIP_IPV6 +/* Level: IPPROTO_IPV6 */ + case IPPROTO_IPV6: + switch (optname) { + case IPV6_V6ONLY: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, *optlen, int); + *(int*)optval = (netconn_get_ipv6only(sock->conn) ? 1 : 0); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IPV6, IPV6_V6ONLY) = %d\n", + s, *(int *)optval)); + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IPV6, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; + +#if ESP_LWIP +#if LWIP_IPV6_MLD && LWIP_MULTICAST_TX_OPTIONS /* Multicast options, similar to LWIP_IGMP options for IPV4 */ + case IPV6_MULTICAST_IF: /* NB: like IP_MULTICAST_IF, this returns an IP not an index */ + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, struct in6_addr); + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_UDP) { + return ENOPROTOOPT; + } + inet6_addr_from_ip6addr((struct in6_addr*)optval, + udp_get_multicast_netif_ip6addr(sock->conn->pcb.udp)); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IPV6, IPV6_MULTICAST_IF) = 0x%"X32_F"\n", + s, *(u32_t *)optval)); + break; + case IPV6_MULTICAST_HOPS: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, u8_t); + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_UDP) { + return ENOPROTOOPT; + } + *(u8_t*)optval = sock->conn->pcb.udp->mcast_ttl; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IPV6, IP_MULTICAST_LOOP) = %d\n", + s, *(int *)optval)); + break; + case IPV6_MULTICAST_LOOP: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, u8_t); + if ((sock->conn->pcb.udp->flags & UDP_FLAGS_MULTICAST_LOOP) != 0) { + *(u8_t*)optval = 1; + } else { + *(u8_t*)optval = 0; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_IPV6, IP_MULTICAST_LOOP) = %d\n", + s, *(int *)optval)); + break; + +#endif /* LWIP_IPV6_MLD && LWIP_MULTICAST_TX_OPTIONS */ +#endif + +#endif /* LWIP_IPV6 */ + +#if LWIP_UDP && LWIP_UDPLITE + /* Level: IPPROTO_UDPLITE */ + case IPPROTO_UDPLITE: + /* Special case: all IPPROTO_UDPLITE option take an int */ + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, *optlen, int); + /* If this is no UDP lite socket, ignore any options. */ + if (!NETCONNTYPE_ISUDPLITE(netconn_type(sock->conn))) { + return ENOPROTOOPT; + } + switch (optname) { + case UDPLITE_SEND_CSCOV: + *(int*)optval = sock->conn->pcb.udp->chksum_len_tx; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UDPLITE_SEND_CSCOV) = %d\n", + s, (*(int*)optval)) ); + break; + case UDPLITE_RECV_CSCOV: + *(int*)optval = sock->conn->pcb.udp->chksum_len_rx; + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UDPLITE_RECV_CSCOV) = %d\n", + s, (*(int*)optval)) ); + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_UDPLITE, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; +#endif /* LWIP_UDP */ + /* Level: IPPROTO_RAW */ + case IPPROTO_RAW: + switch (optname) { +#if LWIP_IPV6 && LWIP_RAW + case IPV6_CHECKSUM: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, *optlen, int, NETCONN_RAW); + if (sock->conn->pcb.raw->chksum_reqd == 0) { + *(int *)optval = -1; + } else { + *(int *)optval = sock->conn->pcb.raw->chksum_offset; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_RAW, IPV6_CHECKSUM) = %d\n", + s, (*(int*)optval)) ); + break; +#endif /* LWIP_IPV6 && LWIP_RAW */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, IPPROTO_RAW, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_getsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", + s, level, optname)); + err = ENOPROTOOPT; + break; + } /* switch (level) */ + + return err; +} + +int +lwip_setsockopt(int s, int level, int optname, const void *optval, socklen_t optlen) +{ + u8_t err = 0; + struct lwip_sock *sock = get_socket(s); +#if !LWIP_TCPIP_CORE_LOCKING + LWIP_SETGETSOCKOPT_DATA_VAR_DECLARE(data); +#endif /* !LWIP_TCPIP_CORE_LOCKING */ + + if (!sock) { + return -1; + } + + if (NULL == optval) { + sock_set_errno(sock, EFAULT); + return -1; + } + +#if LWIP_TCPIP_CORE_LOCKING + /* core-locking can just call the -impl function */ + LOCK_TCPIP_CORE(); + err = lwip_setsockopt_impl(s, level, optname, optval, optlen); + UNLOCK_TCPIP_CORE(); + +#else /* LWIP_TCPIP_CORE_LOCKING */ + +#if LWIP_MPU_COMPATIBLE + /* MPU_COMPATIBLE copies the optval data, so check for max size here */ + if (optlen > LWIP_SETGETSOCKOPT_MAXOPTLEN) { + sock_set_errno(sock, ENOBUFS); + return -1; + } +#endif /* LWIP_MPU_COMPATIBLE */ + + LWIP_SETGETSOCKOPT_DATA_VAR_ALLOC(data, sock); + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).s = s; + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).level = level; + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optname = optname; + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optlen = optlen; +#if LWIP_MPU_COMPATIBLE + MEMCPY(LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optval, optval, optlen); +#else /* LWIP_MPU_COMPATIBLE */ + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).optval.pc = (const void*)optval; +#endif /* LWIP_MPU_COMPATIBLE */ + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).err = 0; +#if LWIP_NETCONN_SEM_PER_THREAD + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem = LWIP_NETCONN_THREAD_SEM_GET(); +#else + LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem = &sock->conn->op_completed; +#endif + err = tcpip_callback(lwip_setsockopt_callback, &LWIP_SETGETSOCKOPT_DATA_VAR_REF(data)); + if (err != ERR_OK) { + LWIP_SETGETSOCKOPT_DATA_VAR_FREE(data); + sock_set_errno(sock, err_to_errno(err)); + return -1; + } + sys_arch_sem_wait((sys_sem_t*)(LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).completed_sem), 0); + + /* maybe lwip_getsockopt_internal has changed err */ + err = LWIP_SETGETSOCKOPT_DATA_VAR_REF(data).err; + LWIP_SETGETSOCKOPT_DATA_VAR_FREE(data); +#endif /* LWIP_TCPIP_CORE_LOCKING */ + + sock_set_errno(sock, err); + return err ? -1 : 0; +} + +#if !LWIP_TCPIP_CORE_LOCKING +/** lwip_setsockopt_callback: only used without CORE_LOCKING + * to get into the tcpip_thread + */ +static void +lwip_setsockopt_callback(void *arg) +{ + struct lwip_setgetsockopt_data *data; + LWIP_ASSERT("arg != NULL", arg != NULL); + data = (struct lwip_setgetsockopt_data*)arg; + + data->err = lwip_setsockopt_impl(data->s, data->level, data->optname, +#if LWIP_MPU_COMPATIBLE + data->optval, +#else /* LWIP_MPU_COMPATIBLE */ + data->optval.pc, +#endif /* LWIP_MPU_COMPATIBLE */ + data->optlen); + + sys_sem_signal((sys_sem_t*)(data->completed_sem)); +} +#endif /* LWIP_TCPIP_CORE_LOCKING */ + +/** lwip_setsockopt_impl: the actual implementation of setsockopt: + * same argument as lwip_setsockopt, either called directly or through callback + */ +static u8_t +lwip_setsockopt_impl(int s, int level, int optname, const void *optval, socklen_t optlen) +{ + u8_t err = 0; + struct lwip_sock *sock = tryget_socket(s); + if (!sock) { + return EBADF; + } + + switch (level) { + +/* Level: SOL_SOCKET */ + case SOL_SOCKET: + switch (optname) { + + /* SO_ACCEPTCONN is get-only */ + + /* The option flags */ + case SO_BROADCAST: + case SO_KEEPALIVE: +#if SO_REUSE + case SO_REUSEADDR: +#endif /* SO_REUSE */ + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, int); + if (*(const int*)optval) { + ip_set_option(sock->conn->pcb.ip, optname); + } else { + ip_reset_option(sock->conn->pcb.ip, optname); + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, optname=0x%x, ..) -> %s\n", + s, optname, (*(const int*)optval?"on":"off"))); + break; + + /* SO_TYPE is get-only */ + /* SO_ERROR is get-only */ + +#if LWIP_SO_SNDTIMEO + case SO_SNDTIMEO: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, LWIP_SO_SNDRCVTIMEO_OPTTYPE); + netconn_set_sendtimeout(sock->conn, LWIP_SO_SNDRCVTIMEO_GET_MS(optval)); + break; +#endif /* LWIP_SO_SNDTIMEO */ +#if LWIP_SO_RCVTIMEO + case SO_RCVTIMEO: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, LWIP_SO_SNDRCVTIMEO_OPTTYPE); + netconn_set_recvtimeout(sock->conn, (int)LWIP_SO_SNDRCVTIMEO_GET_MS(optval)); + break; +#endif /* LWIP_SO_RCVTIMEO */ +#if LWIP_SO_RCVBUF + case SO_RCVBUF: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, int); + netconn_set_recvbufsize(sock->conn, *(const int*)optval); + break; +#endif /* LWIP_SO_RCVBUF */ +#if LWIP_SO_LINGER + case SO_LINGER: + { + const struct linger* linger = (const struct linger*)optval; + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, struct linger); + if (linger->l_onoff) { + int lingersec = linger->l_linger; + if (lingersec < 0) { + return EINVAL; + } + if (lingersec > 0xFFFF) { + lingersec = 0xFFFF; + } + sock->conn->linger = (s16_t)lingersec; + } else { + sock->conn->linger = -1; + } + } + break; +#endif /* LWIP_SO_LINGER */ +#if LWIP_UDP + case SO_NO_CHECK: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, int, NETCONN_UDP); +#if LWIP_UDPLITE + if ((udp_flags(sock->conn->pcb.udp) & UDP_FLAGS_UDPLITE) != 0) { + /* this flag is only available for UDP, not for UDP lite */ + return EAFNOSUPPORT; + } +#endif /* LWIP_UDPLITE */ + if (*(const int*)optval) { + udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) | UDP_FLAGS_NOCHKSUM); + } else { + udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) & ~UDP_FLAGS_NOCHKSUM); + } + break; +#endif /* LWIP_UDP */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, SOL_SOCKET, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; + +/* Level: IPPROTO_IP */ + case IPPROTO_IP: + switch (optname) { + case IP_TTL: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, int); + sock->conn->pcb.ip->ttl = (u8_t)(*(const int*)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TTL, ..) -> %d\n", + s, sock->conn->pcb.ip->ttl)); + break; + case IP_TOS: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, int); + sock->conn->pcb.ip->tos = (u8_t)(*(const int*)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, IP_TOS, ..)-> %d\n", + s, sock->conn->pcb.ip->tos)); + break; +#if LWIP_MULTICAST_TX_OPTIONS + case IP_MULTICAST_TTL: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, u8_t, NETCONN_UDP); + udp_set_multicast_ttl(sock->conn->pcb.udp, (u8_t)(*(const u8_t*)optval)); + break; + case IP_MULTICAST_IF: + { + ip4_addr_t if_addr; + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, struct in_addr, NETCONN_UDP); + inet_addr_to_ip4addr(&if_addr, (const struct in_addr*)optval); + udp_set_multicast_netif_addr(sock->conn->pcb.udp, &if_addr); + } + break; + case IP_MULTICAST_LOOP: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, u8_t, NETCONN_UDP); + if (*(const u8_t*)optval) { + udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) | UDP_FLAGS_MULTICAST_LOOP); + } else { + udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) & ~UDP_FLAGS_MULTICAST_LOOP); + } + break; +#endif /* LWIP_MULTICAST_TX_OPTIONS */ +#if LWIP_IGMP + case IP_ADD_MEMBERSHIP: + case IP_DROP_MEMBERSHIP: + { + /* If this is a TCP or a RAW socket, ignore these options. */ + /* @todo: assign membership to this socket so that it is dropped when closing the socket */ + err_t igmp_err; + const struct ip_mreq *imr = (const struct ip_mreq *)optval; +#if ESP_LWIP + ip_addr_t if_addr; + ip_addr_t multi_addr; +#else + ip4_addr_t if_addr; + ip4_addr_t multi_addr; +#endif + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, struct ip_mreq, NETCONN_UDP); +#if ESP_LWIP + inet_addr_to_ip4addr(ip_2_ip4(&if_addr), &imr->imr_interface); + inet_addr_to_ip4addr(ip_2_ip4(&multi_addr), &imr->imr_multiaddr); +#else + inet_addr_to_ip4addr(&if_addr, &imr->imr_interface); + inet_addr_to_ip4addr(&multi_addr, &imr->imr_multiaddr); +#endif + if (optname == IP_ADD_MEMBERSHIP) { + if (!lwip_socket_register_membership(s, &if_addr, &multi_addr)) { + /* cannot track membership (out of memory) */ + err = ENOMEM; + igmp_err = ERR_OK; + } else { +#if ESP_LWIP + igmp_err = igmp_joingroup(ip_2_ip4(&if_addr), ip_2_ip4(&multi_addr)); +#else + igmp_err = igmp_joingroup(&if_addr, &multi_addr); +#endif + } + } else { +#if ESP_LWIP + igmp_err = igmp_leavegroup(ip_2_ip4(&if_addr), ip_2_ip4(&multi_addr)); +#else + igmp_err = igmp_leavegroup(&if_addr, &multi_addr); +#endif + lwip_socket_unregister_membership(s, &if_addr, &multi_addr); + } + if (igmp_err != ERR_OK) { + err = EADDRNOTAVAIL; + } + } + break; +#endif /* LWIP_IGMP */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IP, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; + +#if LWIP_TCP +/* Level: IPPROTO_TCP */ + case IPPROTO_TCP: + /* Special case: all IPPROTO_TCP option take an int */ + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, int, NETCONN_TCP); + if (sock->conn->pcb.tcp->state == LISTEN) { + return EINVAL; + } + switch (optname) { + case TCP_NODELAY: + if (*(const int*)optval) { + tcp_nagle_disable(sock->conn->pcb.tcp); + } else { + tcp_nagle_enable(sock->conn->pcb.tcp); + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_NODELAY) -> %s\n", + s, (*(const int *)optval)?"on":"off") ); + break; + case TCP_KEEPALIVE: + sock->conn->pcb.tcp->keep_idle = (u32_t)(*(const int*)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPALIVE) -> %"U32_F"\n", + s, sock->conn->pcb.tcp->keep_idle)); + break; + +#if LWIP_TCP_KEEPALIVE + case TCP_KEEPIDLE: + sock->conn->pcb.tcp->keep_idle = 1000*(u32_t)(*(const int*)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPIDLE) -> %"U32_F"\n", + s, sock->conn->pcb.tcp->keep_idle)); + break; + case TCP_KEEPINTVL: + sock->conn->pcb.tcp->keep_intvl = 1000*(u32_t)(*(const int*)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPINTVL) -> %"U32_F"\n", + s, sock->conn->pcb.tcp->keep_intvl)); + break; + case TCP_KEEPCNT: + sock->conn->pcb.tcp->keep_cnt = (u32_t)(*(const int*)optval); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, TCP_KEEPCNT) -> %"U32_F"\n", + s, sock->conn->pcb.tcp->keep_cnt)); + break; +#endif /* LWIP_TCP_KEEPALIVE */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_TCP, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; +#endif /* LWIP_TCP*/ + +#if LWIP_IPV6 +/* Level: IPPROTO_IPV6 */ + case IPPROTO_IPV6: + switch (optname) { + case IPV6_V6ONLY: +#if ESP_LWIP + LWIP_SOCKOPT_CHECK_OPTLEN_CONN(sock, optlen, int); +#else + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, int, NETCONN_TCP); +#endif + if (*(const int*)optval) { + netconn_set_ipv6only(sock->conn, 1); + } else { + netconn_set_ipv6only(sock->conn, 0); + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IPV6, IPV6_V6ONLY, ..) -> %d\n", + s, (netconn_get_ipv6only(sock->conn) ? 1 : 0))); + break; + +#if ESP_LWIP +#if LWIP_IPV6_MLD && LWIP_MULTICAST_TX_OPTIONS /* Multicast options, similar to LWIP_IGMP options for IPV4 */ + case IPV6_MULTICAST_IF: /* NB: like IP_MULTICAST_IF, this takes an IP not an index */ + { + ip6_addr_t if_addr; + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, struct in6_addr, NETCONN_UDP); + inet6_addr_to_ip6addr(&if_addr, (const struct in6_addr*)optval); + udp_set_multicast_netif_ip6addr(sock->conn->pcb.udp, &if_addr); + } + break; + case IPV6_MULTICAST_HOPS: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, u8_t, NETCONN_UDP); + sock->conn->pcb.udp->mcast_ttl = (u8_t)(*(const u8_t*)optval); + break; + case IPV6_MULTICAST_LOOP: + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, u8_t, NETCONN_UDP); + if (*(const u8_t*)optval) { + udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) | UDP_FLAGS_MULTICAST_LOOP); + } else { + udp_setflags(sock->conn->pcb.udp, udp_flags(sock->conn->pcb.udp) & ~UDP_FLAGS_MULTICAST_LOOP); + } + break; + case IPV6_ADD_MEMBERSHIP: + case IPV6_DROP_MEMBERSHIP: + { + err_t mld_err; + const struct ip6_mreq *imr = (const struct ip6_mreq *)optval; + ip_addr_t if_addr; + ip_addr_t multi_addr; + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, struct ip6_mreq, NETCONN_UDP); + inet6_addr_to_ip6addr(ip_2_ip6(&if_addr), &imr->ipv6mr_interface); + inet6_addr_to_ip6addr(ip_2_ip6(&multi_addr), &imr->ipv6mr_multiaddr); + if (optname == IPV6_ADD_MEMBERSHIP) { + if (!lwip_socket_register_membership(s, &if_addr, &multi_addr)) { + /* cannot track membership (out of memory) */ + err = ENOMEM; + mld_err = ERR_OK; + } else { + mld_err = mld6_joingroup(ip_2_ip6(&if_addr), ip_2_ip6(&multi_addr)); + } + } else { + mld_err = mld6_leavegroup(ip_2_ip6(&if_addr), ip_2_ip6(&multi_addr)); + lwip_socket_unregister_membership(s, &if_addr, &multi_addr); + } + if (mld_err != ERR_OK) { + err = EADDRNOTAVAIL; + } + } + break; +#endif /* LWIP_IPV6_MLD && LWIP_MULTICAST_TX_OPTIONS */ +#endif + + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_IPV6, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; +#endif /* LWIP_IPV6 */ + +#if LWIP_UDP && LWIP_UDPLITE + /* Level: IPPROTO_UDPLITE */ + case IPPROTO_UDPLITE: + /* Special case: all IPPROTO_UDPLITE option take an int */ + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB(sock, optlen, int); + /* If this is no UDP lite socket, ignore any options. */ + if (!NETCONNTYPE_ISUDPLITE(netconn_type(sock->conn))) { + return ENOPROTOOPT; + } + switch (optname) { + case UDPLITE_SEND_CSCOV: + if ((*(const int*)optval != 0) && ((*(const int*)optval < 8) || (*(const int*)optval > 0xffff))) { + /* don't allow illegal values! */ + sock->conn->pcb.udp->chksum_len_tx = 8; + } else { + sock->conn->pcb.udp->chksum_len_tx = (u16_t)*(const int*)optval; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UDPLITE_SEND_CSCOV) -> %d\n", + s, (*(const int*)optval)) ); + break; + case UDPLITE_RECV_CSCOV: + if ((*(const int*)optval != 0) && ((*(const int*)optval < 8) || (*(const int*)optval > 0xffff))) { + /* don't allow illegal values! */ + sock->conn->pcb.udp->chksum_len_rx = 8; + } else { + sock->conn->pcb.udp->chksum_len_rx = (u16_t)*(const int*)optval; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UDPLITE_RECV_CSCOV) -> %d\n", + s, (*(const int*)optval)) ); + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_UDPLITE, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; +#endif /* LWIP_UDP */ + /* Level: IPPROTO_RAW */ + case IPPROTO_RAW: + switch (optname) { +#if LWIP_IPV6 && LWIP_RAW + case IPV6_CHECKSUM: + /* It should not be possible to disable the checksum generation with ICMPv6 + * as per RFC 3542 chapter 3.1 */ + if(sock->conn->pcb.raw->protocol == IPPROTO_ICMPV6) { + return EINVAL; + } + + LWIP_SOCKOPT_CHECK_OPTLEN_CONN_PCB_TYPE(sock, optlen, int, NETCONN_RAW); + if (*(const int *)optval < 0) { + sock->conn->pcb.raw->chksum_reqd = 0; + } else if (*(const int *)optval & 1) { + /* Per RFC3542, odd offsets are not allowed */ + return EINVAL; + } else { + sock->conn->pcb.raw->chksum_reqd = 1; + sock->conn->pcb.raw->chksum_offset = (u16_t)*(const int *)optval; + } + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_RAW, IPV6_CHECKSUM, ..) -> %d\n", + s, sock->conn->pcb.raw->chksum_reqd)); + break; +#endif /* LWIP_IPV6 && LWIP_RAW */ + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, IPPROTO_RAW, UNIMPL: optname=0x%x, ..)\n", + s, optname)); + err = ENOPROTOOPT; + break; + } /* switch (optname) */ + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_setsockopt(%d, level=0x%x, UNIMPL: optname=0x%x, ..)\n", + s, level, optname)); + err = ENOPROTOOPT; + break; + } /* switch (level) */ + + return err; +} + +int +lwip_ioctl(int s, long cmd, void *argp) +{ + struct lwip_sock *sock = get_socket(s); + u8_t val; +#if LWIP_SO_RCVBUF + u16_t buflen = 0; + int recv_avail; +#endif /* LWIP_SO_RCVBUF */ + + if (!sock) { + return -1; + } + + switch (cmd) { +#if LWIP_SO_RCVBUF || LWIP_FIONREAD_LINUXMODE + case FIONREAD: + if (!argp) { + sock_set_errno(sock, EINVAL); + return -1; + } +#if LWIP_FIONREAD_LINUXMODE + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) { + struct pbuf *p; + if (sock->lastdata) { + p = ((struct netbuf *)sock->lastdata)->p; + *((int*)argp) = p->tot_len - sock->lastoffset; + } else { + struct netbuf *rxbuf; + err_t err; + if (sock->rcvevent <= 0) { + *((int*)argp) = 0; + } else { + err = netconn_recv(sock->conn, &rxbuf); + if (err != ERR_OK) { + *((int*)argp) = 0; + } else { + sock->lastdata = rxbuf; + sock->lastoffset = 0; + *((int*)argp) = rxbuf->p->tot_len; + } + } + } + return 0; + } +#endif /* LWIP_FIONREAD_LINUXMODE */ + +#if LWIP_SO_RCVBUF + /* we come here if either LWIP_FIONREAD_LINUXMODE==0 or this is a TCP socket */ + SYS_ARCH_GET(sock->conn->recv_avail, recv_avail); + if (recv_avail < 0) { + recv_avail = 0; + } + *((int*)argp) = recv_avail; + + /* Check if there is data left from the last recv operation. /maq 041215 */ + if (sock->lastdata) { + struct pbuf *p = (struct pbuf *)sock->lastdata; + if (NETCONNTYPE_GROUP(netconn_type(sock->conn)) != NETCONN_TCP) { + p = ((struct netbuf *)p)->p; + } + buflen = p->tot_len; + buflen -= sock->lastoffset; + + *((int*)argp) += buflen; + } + + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONREAD, %p) = %"U16_F"\n", s, argp, *((u16_t*)argp))); + sock_set_errno(sock, 0); + return 0; +#else /* LWIP_SO_RCVBUF */ + break; +#endif /* LWIP_SO_RCVBUF */ +#endif /* LWIP_SO_RCVBUF || LWIP_FIONREAD_LINUXMODE */ + + case (long)FIONBIO: + val = 0; + if (argp && *(u32_t*)argp) { + val = 1; + } + netconn_set_nonblocking(sock->conn, val); + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, FIONBIO, %d)\n", s, val)); + sock_set_errno(sock, 0); + return 0; + + default: + break; + } /* switch (cmd) */ + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_ioctl(%d, UNIMPL: 0x%lx, %p)\n", s, cmd, argp)); + sock_set_errno(sock, ENOSYS); /* not yet implemented */ + return -1; +} + +/** A minimal implementation of fcntl. + * Currently only the commands F_GETFL and F_SETFL are implemented. + * Only the flag O_NONBLOCK is implemented. + */ +int +lwip_fcntl(int s, int cmd, int val) +{ + struct lwip_sock *sock = get_socket(s); + int ret = -1; + + if (!sock) { + return -1; + } + + switch (cmd) { + case F_GETFL: + ret = netconn_is_nonblocking(sock->conn) ? O_NONBLOCK : 0; + sock_set_errno(sock, 0); + break; + case F_SETFL: + if ((val & ~O_NONBLOCK) == 0) { + /* only O_NONBLOCK, all other bits are zero */ + netconn_set_nonblocking(sock->conn, val & O_NONBLOCK); + ret = 0; + sock_set_errno(sock, 0); + } else { + sock_set_errno(sock, ENOSYS); /* not yet implemented */ + } + break; + default: + LWIP_DEBUGF(SOCKETS_DEBUG, ("lwip_fcntl(%d, UNIMPL: %d, %d)\n", s, cmd, val)); + sock_set_errno(sock, ENOSYS); /* not yet implemented */ + break; + } + return ret; +} + +#if ESP_LWIP +#if LWIP_IGMP || (LWIP_IPV6_MLD && LWIP_MULTICAST_TX_OPTIONS) +/** Register a new IGMP membership. On socket close, the membership is dropped automatically. + * + * ATTENTION: this function is called from tcpip_thread (or under CORE_LOCK). + * + * @return 1 on success, 0 on failure + */ +static int +lwip_socket_register_membership(int s, const ip_addr_t *if_addr, const ip_addr_t *multi_addr) +{ + /* s+1 is stored in the array to prevent having to initialize the array + (default initialization is to 0) */ + int sa = s + 1; + int i; + + for (i = 0; i < LWIP_SOCKET_MAX_MEMBERSHIPS; i++) { + if (socket_multicast_memberships[i].sa == 0) { + socket_multicast_memberships[i].sa = sa; + ip_addr_copy(socket_multicast_memberships[i].if_addr, *if_addr); + ip_addr_copy(socket_multicast_memberships[i].multi_addr, *multi_addr); + return 1; + } + } + return 0; +} + +/** Unregister a previously registered membership. This prevents dropping the membership + * on socket close. + * + * ATTENTION: this function is called from tcpip_thread (or under CORE_LOCK). + */ +static void +lwip_socket_unregister_membership(int s, const ip_addr_t *if_addr, const ip_addr_t *multi_addr) +{ + /* s+1 is stored in the array to prevent having to initialize the array + (default initialization is to 0) */ + int sa = s + 1; + int i; + + for (i = 0; i < LWIP_SOCKET_MAX_MEMBERSHIPS; i++) { + if ((socket_multicast_memberships[i].sa == sa) && + ip_addr_cmp(&socket_multicast_memberships[i].if_addr, if_addr) && + ip_addr_cmp(&socket_multicast_memberships[i].multi_addr, multi_addr)) { + socket_multicast_memberships[i].sa = 0; + ip_addr_set_zero(&socket_multicast_memberships[i].if_addr); + ip_addr_set_zero(&socket_multicast_memberships[i].multi_addr); + return; + } + } +} + +/** Drop all memberships of a socket that were not dropped explicitly via setsockopt. + * + * ATTENTION: this function is NOT called from tcpip_thread (or under CORE_LOCK). + */ +static void lwip_socket_drop_registered_memberships(int s) +{ + /* s+1 is stored in the array to prevent having to initialize the array + (default initialization is to 0) */ + int sa = s + 1; + int i; + struct lwip_sock *sock = get_socket(s); + + LWIP_ASSERT("socket has no netconn", sock->conn != NULL); + + for (i = 0; i < LWIP_SOCKET_MAX_MEMBERSHIPS; i++) { + if (socket_multicast_memberships[i].sa == sa) { + socket_multicast_memberships[i].sa = 0; + netconn_join_leave_group(sock->conn, + &socket_multicast_memberships[i].multi_addr, + &socket_multicast_memberships[i].if_addr, + NETCONN_LEAVE); + ip_addr_set_zero(&socket_multicast_memberships[i].if_addr); + ip_addr_set_zero(&socket_multicast_memberships[i].multi_addr); + } + } +} +#endif /* LWIP_IGMP || (LWIP_IPV6_MLD && LWIP_MULTICAST_TX_OPTIONS) */ + +#else +#if LWIP_IGMP +static int +lwip_socket_register_membership(int s, const ip4_addr_t *if_addr, const ip4_addr_t *multi_addr) +{ + struct lwip_sock *sock = get_socket(s); + int i; + + if (!sock) { + return 0; + } + + for (i = 0; i < LWIP_SOCKET_MAX_MEMBERSHIPS; i++) { + if (socket_ipv4_multicast_memberships[i].sock == NULL) { + socket_ipv4_multicast_memberships[i].sock = sock; + ip4_addr_copy(socket_ipv4_multicast_memberships[i].if_addr, *if_addr); + ip4_addr_copy(socket_ipv4_multicast_memberships[i].multi_addr, *multi_addr); + return 1; + } + } + return 0; +} + +/** Unregister a previously registered membership. This prevents dropping the membership + * on socket close. + * + * ATTENTION: this function is called from tcpip_thread (or under CORE_LOCK). + */ +static void +lwip_socket_unregister_membership(int s, const ip4_addr_t *if_addr, const ip4_addr_t *multi_addr) +{ + struct lwip_sock *sock = get_socket(s); + int i; + + if (!sock) { + return; + } + + for (i = 0; i < LWIP_SOCKET_MAX_MEMBERSHIPS; i++) { + if ((socket_ipv4_multicast_memberships[i].sock == sock) && + ip4_addr_cmp(&socket_ipv4_multicast_memberships[i].if_addr, if_addr) && + ip4_addr_cmp(&socket_ipv4_multicast_memberships[i].multi_addr, multi_addr)) { + socket_ipv4_multicast_memberships[i].sock = NULL; + ip4_addr_set_zero(&socket_ipv4_multicast_memberships[i].if_addr); + ip4_addr_set_zero(&socket_ipv4_multicast_memberships[i].multi_addr); + return; + } + } +} + + +/** Drop all memberships of a socket that were not dropped explicitly via setsockopt. + * + * ATTENTION: this function is NOT called from tcpip_thread (or under CORE_LOCK). + */ +static void +lwip_socket_drop_registered_memberships(int s) +{ + struct lwip_sock *sock = get_socket(s); + int i; + + if (!sock) { + return; + } + + for (i = 0; i < LWIP_SOCKET_MAX_MEMBERSHIPS; i++) { + if (socket_ipv4_multicast_memberships[i].sock == sock) { + ip_addr_t multi_addr, if_addr; + ip_addr_copy_from_ip4(multi_addr, socket_ipv4_multicast_memberships[i].multi_addr); + ip_addr_copy_from_ip4(if_addr, socket_ipv4_multicast_memberships[i].if_addr); + socket_ipv4_multicast_memberships[i].sock = NULL; + ip4_addr_set_zero(&socket_ipv4_multicast_memberships[i].if_addr); + ip4_addr_set_zero(&socket_ipv4_multicast_memberships[i].multi_addr); + + netconn_join_leave_group(sock->conn, &multi_addr, &if_addr, NETCONN_LEAVE); + } + } +} +#endif /* LWIP_IGMP */ +#endif /* ESP_LWIP */ + +#if ESP_THREAD_SAFE + +int ESP_IRAM_ATTR +lwip_sendto_r(int s, const void *data, size_t size, int flags, + const struct sockaddr *to, socklen_t tolen) +{ + LWIP_API_LOCK(); + __ret = lwip_sendto(s, data, size, flags, to, tolen); + LWIP_API_UNLOCK(); +} + +int +lwip_send_r(int s, const void *data, size_t size, int flags) +{ + LWIP_API_LOCK(); + __ret = lwip_send(s, data, size, flags); + LWIP_API_UNLOCK(); +} + +int ESP_IRAM_ATTR +lwip_recvfrom_r(int s, void *mem, size_t len, int flags, + struct sockaddr *from, socklen_t *fromlen) +{ + LWIP_API_LOCK(); + __ret = lwip_recvfrom(s, mem, len, flags, from, fromlen); + LWIP_API_UNLOCK(); +} + +int ESP_IRAM_ATTR +lwip_recv_r(int s, void *mem, size_t len, int flags) +{ + return lwip_recvfrom_r(s, mem, len, flags, NULL, NULL); +} + +int +lwip_read_r(int s, void *mem, size_t len) +{ + return lwip_recvfrom_r(s, mem, len, 0, NULL, NULL); +} + +int +lwip_sendmsg_r(int s, const struct msghdr *msg, int flags) +{ + LWIP_API_LOCK(); + __ret = lwip_sendmsg(s, msg, flags); + LWIP_API_UNLOCK(); +} + +int +lwip_write_r(int s, const void *data, size_t size) +{ + return lwip_send_r(s, data, size, 0); +} + +int +lwip_writev_r(int s, const struct iovec *iov, int iovcnt) +{ + struct msghdr msg; + + msg.msg_name = NULL; + msg.msg_namelen = 0; + /* Hack: we have to cast via number to cast from 'const' pointer to non-const. + Blame the opengroup standard for this inconsistency. */ + msg.msg_iov = (struct iovec *)(size_t)iov; + msg.msg_iovlen = iovcnt; + msg.msg_control = NULL; + msg.msg_controllen = 0; + msg.msg_flags = 0; + return lwip_sendmsg_r(s, &msg, 0); +} + +int +lwip_connect_r(int s, const struct sockaddr *name, socklen_t namelen) +{ + LWIP_API_LOCK(); + __ret = lwip_connect(s, name, namelen); + LWIP_API_UNLOCK(); +} + +int +lwip_recvmsg_r(int s, struct msghdr *msg, int flags) +{ + LWIP_API_LOCK(); + __ret = lwip_recvmsg(s, msg, flags); + LWIP_API_UNLOCK(); +} + +int +lwip_listen_r(int s, int backlog) +{ + LWIP_API_LOCK(); + __ret = lwip_listen(s, backlog); + LWIP_API_UNLOCK(); +} + +int +lwip_bind_r(int s, const struct sockaddr *name, socklen_t namelen) +{ + LWIP_API_LOCK(); + __ret = lwip_bind(s, name, namelen); + LWIP_API_UNLOCK(); +} + +int +lwip_accept_r(int s, struct sockaddr *addr, socklen_t *addrlen) +{ + LWIP_API_LOCK(); + __ret = lwip_accept(s, addr, addrlen); + LWIP_API_UNLOCK(); +} + +int +lwip_ioctl_r(int s, long cmd, void *argp) +{ + LWIP_API_LOCK(); + __ret = lwip_ioctl(s, cmd, argp); + LWIP_API_UNLOCK(); +} + +int +lwip_fcntl_r(int s, int cmd, int val) +{ + LWIP_API_LOCK(); + __ret = lwip_fcntl(s, cmd, val); + LWIP_API_UNLOCK(); +} + +int +lwip_setsockopt_r(int s, int level, int optname, const void *optval, socklen_t optlen) +{ + LWIP_API_LOCK(); + __ret = lwip_setsockopt(s, level, optname, optval, optlen); + LWIP_API_UNLOCK(); +} + +int +lwip_getsockopt_r(int s, int level, int optname, void *optval, socklen_t *optlen) +{ + LWIP_API_LOCK(); + __ret = lwip_getsockopt(s, level, optname, optval, optlen); + LWIP_API_UNLOCK(); +} + +int +lwip_getpeername_r(int s, struct sockaddr *name, socklen_t *namelen) +{ + LWIP_API_LOCK(); + __ret = lwip_getpeername(s, name, namelen); + LWIP_API_UNLOCK(); +} + +int +lwip_getsockname_r(int s, struct sockaddr *name, socklen_t *namelen) +{ + LWIP_API_LOCK(); + __ret = lwip_getsockname(s, name, namelen); + LWIP_API_UNLOCK(); +} + +int +lwip_close_r(int s) +{ + LWIP_API_LOCK(); + LWIP_SET_CLOSE_FLAG(); + __ret = lwip_close(s); + LWIP_API_UNLOCK(); +} + +int +lwip_shutdown_r(int s, int how) +{ + LWIP_API_LOCK(); + __ret = lwip_shutdown(s, how); + LWIP_API_UNLOCK(); +} + +#endif + +// get last socket error +// lwIP is clearly missing an API to get the last error from a socket +uint32_t lwip_socket_get_err(int s) +{ + struct lwip_sock *sock = get_socket(s); + return sock->err; +} + +#endif /* LWIP_SOCKET */ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Lwip/nf_sys_arch.c b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Lwip/nf_sys_arch.c new file mode 100644 index 00000000..5f539fcf --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Lwip/nf_sys_arch.c @@ -0,0 +1,565 @@ +/* + * Copyright (c) 2001-2003 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + * + */ + +/* lwIP includes. */ + +#include +#include "lwip/debug.h" +#include "lwip/def.h" +#include "lwip/sys.h" +#include "lwip/mem.h" +#include "arch/sys_arch.h" +#include "lwip/stats.h" +#include "esp_log.h" + +/* This is the number of threads that can be started with sys_thread_new() */ +#define SYS_THREAD_MAX 4 +#define TAG "lwip_arch" + +static sys_mutex_t g_lwip_protect_mutex = NULL; + +static pthread_key_t sys_thread_sem_key; +static void sys_thread_sem_free(void* data); + +#if !LWIP_COMPAT_MUTEX +/** Create a new mutex + * @param mutex pointer to the mutex to create + * @return a new mutex */ +err_t +sys_mutex_new(sys_mutex_t *pxMutex) +{ + err_t xReturn = ERR_MEM; + + *pxMutex = xSemaphoreCreateMutex(); + + if (*pxMutex != NULL) { + xReturn = ERR_OK; + } + + LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("sys_mutex_new: m=%p\n", *pxMutex)); + + return xReturn; +} + +/** Lock a mutex + * @param mutex the mutex to lock */ +void ESP_IRAM_ATTR +sys_mutex_lock(sys_mutex_t *pxMutex) +{ + while (xSemaphoreTake(*pxMutex, portMAX_DELAY) != pdPASS); +} + +err_t +sys_mutex_trylock(sys_mutex_t *pxMutex) +{ + if (xSemaphoreTake(*pxMutex, 0) == pdPASS) return 0; + else return -1; +} + +/** Unlock a mutex + * @param mutex the mutex to unlock */ +void ESP_IRAM_ATTR +sys_mutex_unlock(sys_mutex_t *pxMutex) +{ + xSemaphoreGive(*pxMutex); +} + +/** Delete a semaphore + * @param mutex the mutex to delete */ +void +sys_mutex_free(sys_mutex_t *pxMutex) +{ + LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("sys_mutex_free: m=%p\n", *pxMutex)); + vQueueDelete(*pxMutex); +} +#endif + +/*-----------------------------------------------------------------------------------*/ +// Creates and returns a new semaphore. The "count" argument specifies +// the initial state of the semaphore. TBD finish and test +err_t +sys_sem_new(sys_sem_t *sem, u8_t count) +{ + err_t xReturn = ERR_MEM; + vSemaphoreCreateBinary(*sem); + + if ((*sem) != NULL) { + if (count == 0) { // Means it can't be taken + xSemaphoreTake(*sem, 1); + } + + xReturn = ERR_OK; + } else { + ; // TBD need assert + } + + return xReturn; +} + +/*-----------------------------------------------------------------------------------*/ +// Signals a semaphore +void ESP_IRAM_ATTR +sys_sem_signal(sys_sem_t *sem) +{ + xSemaphoreGive(*sem); +} + +/*-----------------------------------------------------------------------------------*/ +// Signals a semaphore (from ISR) +int sys_sem_signal_isr(sys_sem_t *sem) +{ + BaseType_t woken = pdFALSE; + xSemaphoreGiveFromISR(*sem, &woken); + return woken == pdTRUE; +} + +/*-----------------------------------------------------------------------------------*/ +/* + Blocks the thread while waiting for the semaphore to be + signaled. If the "timeout" argument is non-zero, the thread should + only be blocked for the specified time (measured in + milliseconds). + + If the timeout argument is non-zero, the return value is the number of + milliseconds spent waiting for the semaphore to be signaled. If the + semaphore wasn't signaled within the specified time, the return value is + SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore + (i.e., it was already signaled), the function may return zero. + + Notice that lwIP implements a function with a similar name, + sys_sem_wait(), that uses the sys_arch_sem_wait() function. +*/ +u32_t ESP_IRAM_ATTR +sys_arch_sem_wait(sys_sem_t *sem, u32_t timeout) +{ + portTickType StartTime, EndTime, Elapsed; + unsigned long ulReturn; + + StartTime = xTaskGetTickCount(); + + if (timeout != 0) { + if (xSemaphoreTake(*sem, timeout / portTICK_PERIOD_MS) == pdTRUE) { + EndTime = xTaskGetTickCount(); + Elapsed = (EndTime - StartTime) * portTICK_PERIOD_MS; + + if (Elapsed == 0) { + Elapsed = 1; + } + + ulReturn = Elapsed; + } else { + ulReturn = SYS_ARCH_TIMEOUT; + } + } else { // must block without a timeout + while (xSemaphoreTake(*sem, portMAX_DELAY) != pdTRUE); + + EndTime = xTaskGetTickCount(); + Elapsed = (EndTime - StartTime) * portTICK_PERIOD_MS; + + if (Elapsed == 0) { + Elapsed = 1; + } + + ulReturn = Elapsed; + } + + return ulReturn ; // return time blocked +} + +/*-----------------------------------------------------------------------------------*/ +// Deallocates a semaphore +void +sys_sem_free(sys_sem_t *sem) +{ + vSemaphoreDelete(*sem); +} + +/*-----------------------------------------------------------------------------------*/ +// Creates an empty mailbox. +err_t +sys_mbox_new(sys_mbox_t *mbox, int size) +{ + *mbox = mem_malloc(sizeof(struct sys_mbox_s)); + if (*mbox == NULL){ + LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("fail to new *mbox\n")); + return ERR_MEM; + } + + (*mbox)->os_mbox = xQueueCreate(size, sizeof(void *)); + + if ((*mbox)->os_mbox == NULL) { + LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("fail to new *mbox->os_mbox\n")); + free(*mbox); + return ERR_MEM; + } + +#if ESP_THREAD_SAFE + (*mbox)->owner = NULL; +#endif + + LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("new *mbox ok mbox=%p os_mbox=%p\n", *mbox, (*mbox)->os_mbox)); + return ERR_OK; +} + +/*-----------------------------------------------------------------------------------*/ +// Posts the "msg" to the mailbox. +void ESP_IRAM_ATTR +sys_mbox_post(sys_mbox_t *mbox, void *msg) +{ + while (xQueueSendToBack((*mbox)->os_mbox, &msg, portMAX_DELAY) != pdTRUE); +} + +/*-----------------------------------------------------------------------------------*/ +err_t ESP_IRAM_ATTR +sys_mbox_trypost(sys_mbox_t *mbox, void *msg) +{ + err_t xReturn; + + if (xQueueSend((*mbox)->os_mbox, &msg, (portTickType)0) == pdPASS) { + xReturn = ERR_OK; + } else { + LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("trypost mbox=%p fail\n", (*mbox)->os_mbox)); + xReturn = ERR_MEM; + } + + return xReturn; +} + +/*-----------------------------------------------------------------------------------*/ +/* + Blocks the thread until a message arrives in the mailbox, but does + not block the thread longer than "timeout" milliseconds (similar to + the sys_arch_sem_wait() function). The "msg" argument is a result + parameter that is set by the function (i.e., by doing "*msg = + ptr"). The "msg" parameter maybe NULL to indicate that the message + should be dropped. + + The return values are the same as for the sys_arch_sem_wait() function: + Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a + timeout. + + Note that a function with a similar name, sys_mbox_fetch(), is + implemented by lwIP. +*/ +u32_t ESP_IRAM_ATTR +sys_arch_mbox_fetch(sys_mbox_t *mbox, void **msg, u32_t timeout) +{ + void *dummyptr; + portTickType StartTime, EndTime, Elapsed; + unsigned long ulReturn; + + StartTime = xTaskGetTickCount(); + if (msg == NULL) { + msg = &dummyptr; + } + + if (*mbox == NULL){ + *msg = NULL; + return -1; + } + + if (timeout == 0) { + timeout = portMAX_DELAY; + } else { + timeout = timeout / portTICK_PERIOD_MS; + } + + *msg = NULL; + if (pdTRUE == xQueueReceive((*mbox)->os_mbox, &(*msg), timeout)) { + EndTime = xTaskGetTickCount(); + Elapsed = (EndTime - StartTime) * portTICK_PERIOD_MS; + + if (Elapsed == 0) { + Elapsed = 1; + } + + ulReturn = Elapsed; + } else { // timed out blocking for message + ulReturn = SYS_ARCH_TIMEOUT; + } + + return ulReturn ; // return time blocked TBD test +} + +/*-----------------------------------------------------------------------------------*/ +u32_t +sys_arch_mbox_tryfetch(sys_mbox_t *mbox, void **msg) +{ + void *pvDummy; + unsigned long ulReturn; + + if (msg == NULL) { + msg = &pvDummy; + } + + if (pdTRUE == xQueueReceive((*mbox)->os_mbox, &(*msg), 0)) { + ulReturn = ERR_OK; + } else { + ulReturn = SYS_MBOX_EMPTY; + } + + return ulReturn; +} + +/*-----------------------------------------------------------------------------------*/ + +void +sys_mbox_set_owner(sys_mbox_t *mbox, void* owner) +{ + if (mbox && *mbox) { + (*mbox)->owner = owner; + LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("set mbox=%p owner=%p", *mbox, owner)); + } +} + +/* + Deallocates a mailbox. If there are messages still present in the + mailbox when the mailbox is deallocated, it is an indication of a + programming error in lwIP and the developer should be notified. +*/ +void +sys_mbox_free(sys_mbox_t *mbox) +{ + uint32_t mbox_message_num = 0; + + if ( (NULL == mbox) || (NULL == *mbox) ) { + return; + } + + mbox_message_num = uxQueueMessagesWaiting((*mbox)->os_mbox); + + LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("mbox free: mbox=%p os_mbox=%p owner=%p msg_num=%d\n", + *mbox, (*mbox)->os_mbox, (*mbox)->owner, mbox_message_num)); + +#if ESP_THREAD_SAFE + if ((*mbox)->owner) { + if (0 == mbox_message_num) { + /* + * If mbox->owner is not NULL, it indicates the mbox is recvmbox or acceptmbox, + * we need to post a NULL message to mbox in case some application tasks are blocked + * on this mbox + */ + if (sys_mbox_trypost(mbox, NULL) != ERR_OK) { + /* Should never be here because post a message to empty mbox should always be successful */ + ESP_LOGW(TAG, "WARNING: failed to post NULL msg to mbox\n"); + } else { + LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("mbox free: post null successfully\n")); + } + } + (*mbox)->owner = NULL; + } else { + if (mbox_message_num > 1) { + ESP_LOGW(TAG, "WARNING: mbox has %d message, potential memory leaking\n", mbox_message_num); + } + + if (mbox_message_num > 0) { + LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("mbox free: reset mbox queue\n")); + xQueueReset((*mbox)->os_mbox); + } + + /* For recvmbox or acceptmbox, free them in netconn_free() when all sockets' API are returned */ + vQueueDelete((*mbox)->os_mbox); + free(*mbox); + *mbox = NULL; + } +#else + vQueueDelete((*mbox)->os_mbox); + free(*mbox); + *mbox = NULL; +#endif +} + +/*-----------------------------------------------------------------------------------*/ +/* + Starts a new thread with priority "prio" that will begin its execution in the + function "thread()". The "arg" argument will be passed as an argument to the + thread() function. The id of the new thread is returned. Both the id and + the priority are system dependent. +*/ +sys_thread_t +sys_thread_new(const char *name, lwip_thread_fn thread, void *arg, int stacksize, int prio) +{ + xTaskHandle created_task; + portBASE_TYPE result; + + result = xTaskCreatePinnedToCore(thread, name, stacksize, arg, prio, &created_task, + CONFIG_TCPIP_TASK_AFFINITY); + + if (result != pdPASS) { + return NULL; + } + + return created_task; +} + +/*-----------------------------------------------------------------------------------*/ +// Initialize sys arch +void +sys_init(void) +{ + if (ERR_OK != sys_mutex_new(&g_lwip_protect_mutex)) { + ESP_LOGE(TAG, "sys_init: failed to init lwip protect mutex\n"); + } + + // Create the pthreads key for the per-thread semaphore storage + pthread_key_create(&sys_thread_sem_key, sys_thread_sem_free); + + esp_vfs_lwip_sockets_register(); +} + +// MS-CHANGE for NetMf, extended for nanaoframework so called function +// can be set externally +void (*signal_sock_functionPtr)() = 0; + +void set_signal_sock_function( void (*funcPtr)() ) +{ + signal_sock_functionPtr = funcPtr; +} + + +void sys_signal_sock_event() +{ + if ( signal_sock_functionPtr != 0 ) + signal_sock_functionPtr(); +} + +/*-----------------------------------------------------------------------------------*/ +u32_t +sys_jiffies(void) +{ + return xTaskGetTickCount(); +} + +/*-----------------------------------------------------------------------------------*/ +u32_t +sys_now(void) +{ + return (xTaskGetTickCount()*portTICK_PERIOD_MS); +} + +/* + This optional function does a "fast" critical region protection and returns + the previous protection level. This function is only called during very short + critical regions. An embedded system which supports ISR-based drivers might + want to implement this function by disabling interrupts. Task-based systems + might want to implement this by using a mutex or disabling tasking. This + function should support recursive calls from the same task or interrupt. In + other words, sys_arch_protect() could be called while already protected. In + that case the return value indicates that it is already protected. + + sys_arch_protect() is only required if your port is supporting an operating + system. +*/ +sys_prot_t +sys_arch_protect(void) +{ + sys_mutex_lock(&g_lwip_protect_mutex); + return (sys_prot_t) 1; +} + +/*-----------------------------------------------------------------------------------*/ +/* + This optional function does a "fast" set of critical region protection to the + value specified by pval. See the documentation for sys_arch_protect() for + more information. This function is only required if your port is supporting + an operating system. +*/ +void +sys_arch_unprotect(sys_prot_t pval) +{ + sys_mutex_unlock(&g_lwip_protect_mutex); +} + +/* + * get per thread semphore + */ +sys_sem_t* sys_thread_sem_get(void) +{ + sys_sem_t *sem = pthread_getspecific(sys_thread_sem_key); + + if (!sem) { + sem = sys_thread_sem_init(); + } + LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("sem_get s=%p\n", sem)); + return sem; +} + +static void sys_thread_sem_free(void* data) // destructor for TLS semaphore +{ + sys_sem_t *sem = (sys_sem_t*)(data); + + if (sem && *sem){ + LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("sem del, sem=%p\n", *sem)); + vSemaphoreDelete(*sem); + } + + if (sem) { + LWIP_DEBUGF(ESP_THREAD_SAFE_DEBUG, ("sem pointer del, sem_p=%p\n", sem)); + free(sem); + } +} + +sys_sem_t* sys_thread_sem_init(void) +{ + sys_sem_t *sem = (sys_sem_t*)mem_malloc(sizeof(sys_sem_t*)); + + if (!sem){ + ESP_LOGE(TAG, "thread_sem_init: out of memory"); + return 0; + } + + *sem = xSemaphoreCreateBinary(); + if (!(*sem)){ + free(sem); + ESP_LOGE(TAG, "thread_sem_init: out of memory"); + return 0; + } + + pthread_setspecific(sys_thread_sem_key, sem); + return sem; +} + +void sys_thread_sem_deinit(void) +{ + sys_sem_t *sem = pthread_getspecific(sys_thread_sem_key); + if (sem != NULL) { + sys_thread_sem_free(sem); + pthread_setspecific(sys_thread_sem_key, NULL); + } +} + +void sys_delay_ms(uint32_t ms) +{ + vTaskDelay(ms / portTICK_PERIOD_MS); +} + + diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Network/CMakeLists.txt b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Network/CMakeLists.txt new file mode 100644 index 00000000..35fff0f5 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Network/CMakeLists.txt @@ -0,0 +1,14 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append networking files, if enabled +list(APPEND TARGET_ESP32_NETWORK_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Network.cpp") +list(APPEND TARGET_ESP32_NETWORK_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/target_Network.cpp") +list(APPEND TARGET_ESP32_NETWORK_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Esp32_Ethernet_Lan8720.cpp") +list(APPEND TARGET_ESP32_NETWORK_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Esp32_Wireless.cpp") +list(APPEND TARGET_ESP32_NETWORK_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Esp32_SmartConfig.cpp") + +# make var global +set(TARGET_ESP32_NETWORK_SOURCES ${TARGET_ESP32_NETWORK_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Network/Esp32_Ethernet_Lan8720.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Network/Esp32_Ethernet_Lan8720.cpp new file mode 100644 index 00000000..2553f487 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Network/Esp32_Ethernet_Lan8720.cpp @@ -0,0 +1,138 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +// This file includes the board specific Ethernet Intialisation + +#include +#include "Esp32_os.h" +#include "eth_phy/phy_lan8720.h" +#include "soc/emac_reg_v2.h" + + + +extern "C" +{ +#include "lwip\netif.h" +} + +extern struct netif * Esp32_find_netif(esp_interface_t esp_if); + + +// +// Olimex ESP32-EVB Rev B, OLimex ESP32-Gateway, Generic Lan8270 +// +#define CONFIG_PHY_LAN8720 1 +#define CONFIG_PHY_ADDRESS 0 +#define CONFIG_PHY_SMI_MDC_PIN 23 +#define CONFIG_PHY_SMI_MDIO_PIN 18 + + +// Uncomment one of these following lines to support switching of a power gpio used on some boards +//#define CONFIG_PIN_PHY_POWER 12 // Olimex_POE +//#define CONFIG_PIN_PHY_POWER 5 // Olimex_gateway revs newer than C + + + +#ifdef CONFIG_PHY_LAN8720 +#include "eth_phy/phy_lan8720.h" +#define DEFAULT_ETHERNET_PHY_CONFIG phy_lan8720_default_ethernet_config +#endif + +#ifdef CONFIG_PHY_TLK110 +#include "eth_phy/phy_tlk110.h" +#define DEFAULT_ETHERNET_PHY_CONFIG phy_tlk110_default_ethernet_config +#endif + +#define PIN_SMI_MDC CONFIG_PHY_SMI_MDC_PIN +#define PIN_SMI_MDIO CONFIG_PHY_SMI_MDIO_PIN + +static void eth_gpio_config_rmii(void) +{ + // RMII data pins are fixed: + // TXD0 = GPIO19 + // TXD1 = GPIO22 + // TX_EN = GPIO21 + // RXD0 = GPIO25 + // RXD1 = GPIO26 + // CLK == GPIO0 + phy_rmii_configure_data_interface_pins(); + // MDC is GPIO 23, MDIO is GPIO 18 + phy_rmii_smi_configure_pins(PIN_SMI_MDC, PIN_SMI_MDIO); +} + +#ifdef CONFIG_PIN_PHY_POWER +static void phy_device_power_enable_via_gpio(bool enable) +{ + if (!enable) + phy_lan8720_default_ethernet_config.phy_power_enable(false); + + gpio_pad_select_gpio((gpio_num_t)CONFIG_PIN_PHY_POWER); + gpio_set_direction((gpio_num_t)CONFIG_PIN_PHY_POWER, GPIO_MODE_OUTPUT); + gpio_set_level((gpio_num_t)CONFIG_PIN_PHY_POWER, (int)enable); + + // Allow the power up/down to take effect, min 300us + vTaskDelay(1); + + if (enable) + phy_lan8720_default_ethernet_config.phy_power_enable(true); +} +#endif + + +esp_err_t Esp32_InitialiseEthernet( uint8_t * pMacAdr) +{ + (void)pMacAdr; + + // Config Ethernet interface which will depend on current hardware + eth_config_t config = DEFAULT_ETHERNET_PHY_CONFIG; + /* Set the PHY address in the example configuration */ + config.phy_addr = PHY0; + config.gpio_config = eth_gpio_config_rmii; + config.tcpip_input = tcpip_adapter_eth_input; + +#ifdef CONFIG_PIN_PHY_POWER + config.phy_power_enable = phy_device_power_enable_via_gpio; +#endif + esp_err_t ret = esp_eth_init(&config); + if(ret != ESP_OK) return ret; + + // esp_eth_set_mac( pMacAdr ); // need later IDF + esp_eth_enable(); + + return ESP_OK; +} + +// +// Open Ethernet Network driver +// +int Esp32_Ethernet_Open(int index, HAL_Configuration_NetworkInterface * config) +{ + (void)index; + + if ( Esp32_InitialiseEthernet(config->MacAddress) == ESP_OK ) + { + // Return NetIf number for Esp32 wireless station + + // FIXME find a better way to get the netif ptr + struct netif *pNetIf; + while(true) + { + vTaskDelay(100 / portTICK_PERIOD_MS); + + // Return NetIf number for Esp32 wireless station + pNetIf = Esp32_find_netif(ESP_IF_ETH); + if (pNetIf != NULL) break; + } + if (pNetIf != NULL) return pNetIf->num; + } + + return SOCK_SOCKET_ERROR; +} + +bool Esp32_Ethernet_Close(int index) +{ + (void)index; + return esp_eth_disable() == ESP_OK; +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Network/Esp32_SmartConfig.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Network/Esp32_SmartConfig.cpp new file mode 100644 index 00000000..bf9b46c6 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Network/Esp32_SmartConfig.cpp @@ -0,0 +1,87 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "Esp32_os.h" +#include "esp_smartconfig.h" + +static const int ESPTOUCH_DONE_BIT = BIT1; +static const char *TAG = "sc"; + +static EventGroupHandle_t sc_wifi_event_group; + +static void sc_callback(smartconfig_status_t status, void *pdata) +{ + switch (status) { + case SC_STATUS_WAIT: + ESP_LOGI(TAG, "SC_STATUS_WAIT"); + break; + + case SC_STATUS_FIND_CHANNEL: + ESP_LOGI(TAG, "SC_STATUS_FINDING_CHANNEL"); + break; + + case SC_STATUS_GETTING_SSID_PSWD: + ESP_LOGI(TAG, "SC_STATUS_GETTING_SSID_PSWD"); + break; + + case SC_STATUS_LINK: + ESP_LOGI(TAG, "SC_STATUS_LINK"); + { + wifi_config_t *wifi_config = (wifi_config_t *)pdata; + ESP_LOGI(TAG, "SSID:%s", wifi_config->sta.ssid); + ESP_LOGI(TAG, "PASSWORD:%s", wifi_config->sta.password); + + // Try to connect and Save config + Network_Interface_Connect( 0, + (const char *)wifi_config->sta.ssid, + (const char *)wifi_config->sta.password, + NETWORK_CONNECT_SAVE_CONFIG + NETWORK_CONNECT_RECONNECT + ); + + } + break; + + case SC_STATUS_LINK_OVER: + ESP_LOGI(TAG, "SC_STATUS_LINK_OVER"); + if (pdata != NULL) + { + uint8_t phone_ip[4] = { 0 }; + memcpy(phone_ip, (uint8_t* )pdata, 4); + ESP_LOGI(TAG, "Phone ip: %d.%d.%d.%d\n", phone_ip[0], phone_ip[1], phone_ip[2], phone_ip[3]); + } + xEventGroupSetBits(sc_wifi_event_group, ESPTOUCH_DONE_BIT); + break; + + default: + break; + } +} + +void smartconfig_task(void * parm) +{ + EventBits_t uxBits; + + sc_wifi_event_group = xEventGroupCreate(); + ESP_ERROR_CHECK( esp_smartconfig_set_type(SC_TYPE_ESPTOUCH) ); + ESP_ERROR_CHECK( esp_smartconfig_start(sc_callback) ); + while (1) { + uxBits = xEventGroupWaitBits(sc_wifi_event_group, ESPTOUCH_DONE_BIT, true, false, portMAX_DELAY); + if(uxBits & ESPTOUCH_DONE_BIT) { + ESP_LOGI(TAG, "smartconfig over"); + esp_smartconfig_stop(); + vEventGroupDelete(sc_wifi_event_group); + vTaskDelete(NULL); + } + } +} + + +void Start_wifi_smart_config(void) +{ + xTaskCreate(smartconfig_task, "smartconfig_task", 4096, NULL, 3, NULL); +} + + diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Network/Esp32_Wireless.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Network/Esp32_Wireless.cpp new file mode 100644 index 00000000..79dee5df --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Network/Esp32_Wireless.cpp @@ -0,0 +1,389 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +// This file includes the board specific Ethernet Intialisation + +#include +#include "Esp32_os.h" + +extern "C" +{ +#include "lwip\netif.h" +} + +static const char *TAG = "wifi"; +static bool WifiInitialised = false; +static wifi_mode_t wifiMode; + +// Forward / external references +struct netif * Esp32_find_netif(esp_interface_t esp_if); +int Esp32_Wait_NetNumber(esp_interface_t esp_if); +void Start_wifi_smart_config(); +esp_err_t Esp32_WirelessAP_Configure(HAL_Configuration_NetworkInterface * pConfig ); + +// +// Check what is the required Wifi mode +// Station only or AP only or Station and AP +// +// See what network interfaces are enabled +// +wifi_mode_t Esp32_CheckWifiMode() +{ + wifi_mode_t mode = WIFI_MODE_NULL; + + // Check Wifi station available + if ( g_TargetConfiguration.NetworkInterfaceConfigs->Count >= 1 ) + { + // Check if Station config available + HAL_Configuration_NetworkInterface * pCfgSta = g_TargetConfiguration.NetworkInterfaceConfigs->Configs[0]; + + // Wireless Config with SSID setup + if ( pCfgSta->InterfaceType == NetworkInterfaceType::NetworkInterfaceType_Wireless80211 ) + { + HAL_Configuration_Wireless80211 * pWirelessSta = ConfigurationManager_GetWirelessConfigurationFromId(pCfgSta->SpecificConfigId); + if (pWirelessSta != 0 ) + { + if ( pWirelessSta->Flags & WirelessFlags_Enable ) + { + mode = WIFI_MODE_STA; + } + } + } + } + + // Check if AP config available + if ( g_TargetConfiguration.NetworkInterfaceConfigs->Count >= 2 ) + { + HAL_Configuration_NetworkInterface * pCfgAP = g_TargetConfiguration.NetworkInterfaceConfigs->Configs[1]; + + // Wireless Config with SSID setup + if ( pCfgAP->InterfaceType == NetworkInterfaceType::NetworkInterfaceType_WirelessAP ) + { + HAL_Configuration_WirelessAP * pWirelessAp = ConfigurationManager_GetWirelessAPConfigurationFromId(pCfgAP->SpecificConfigId); + if (pWirelessAp != 0 ) + { + if ( pWirelessAp->Flags & WirelessAPFlags_Enable ) + { + // Use STATION + AP or just AP + mode = ( mode == WIFI_MODE_STA)? WIFI_MODE_APSTA : WIFI_MODE_AP; + } + } + } + } + + return mode; +} + +wifi_mode_t Esp32_GetWifiMode() +{ + wifi_mode_t current_wifi_mode; + esp_wifi_get_mode(¤t_wifi_mode); + return current_wifi_mode; +} + +void Esp32_DeinitWifi() +{ + WifiInitialised = false; + esp_wifi_stop(); + esp_wifi_deinit(); +} + +esp_err_t Esp32_InitaliseWifi() +{ + esp_err_t ec = ESP_OK; + + wifi_mode_t wifi_mode = Esp32_CheckWifiMode(); + + if ( WifiInitialised ) + { + // Check if we are running correct mode + // if not force a new init + if ( Esp32_GetWifiMode() != wifi_mode ) + { + Esp32_DeinitWifi(); + } + } + + if (!WifiInitialised) + { + // Init WiFi Alloc resource for WiFi driver, such as WiFi control structure, + // RX/TX buffer, WiFi NVS structure etc, this WiFi also start WiFi task. + wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT(); + ec = esp_wifi_init(&cfg); + if ( ec != ESP_OK) return ec; + + esp_wifi_set_mode(wifi_mode); + + // We need to start the WIFI stack before the station can Connect + // Also we can only get the NetIf number used by ESP Idf after it has been started. + // Starting will also start the Soft- AP (if we have enabled it). + // So make sure it configured as per wireless config otherwise we will get the default SSID + if (wifi_mode & WIFI_MODE_AP ) + { + HAL_Configuration_NetworkInterface * pConfig = g_TargetConfiguration.NetworkInterfaceConfigs->Configs[1]; + ec = Esp32_WirelessAP_Configure(pConfig); + } + + ec = esp_wifi_start(); + if ( ec != ESP_OK) return ec; + + WifiInitialised = true; + } + + return ec; +} + +esp_err_t Esp32_Wireless_Connect(HAL_Configuration_Wireless80211 * pWireless) +{ + esp_err_t ec; + + // Connect directly + wifi_config_t sta_config = {}; + hal_strncpy_s( (char *)sta_config.sta.ssid, sizeof(sta_config.sta.ssid), (char *)pWireless->Ssid, hal_strlen_s((char *)pWireless->Ssid) ); + hal_strncpy_s( (char*)sta_config.sta.password, sizeof(sta_config.sta.password), (char *)pWireless->Password, hal_strlen_s((char *)pWireless->Password) ); + sta_config.sta.bssid_set = false; + + ec = esp_wifi_set_config(WIFI_IF_STA, &sta_config); + if(ec != ESP_OK) return ec; + + ec = esp_wifi_connect(); + ESP_LOGI(TAG, "WiFi Connect to %s result %d", sta_config.sta.ssid, ec); + if(ec != ESP_OK) return ec; + + return ESP_OK; +} + +esp_err_t Esp32_Wireless_Disconnect() +{ + esp_err_t ec; + + ec = esp_wifi_disconnect(); + if(ec != ESP_OK) return ec; + + return ESP_OK; +} + +int Esp32_Wireless_Open(int index, HAL_Configuration_NetworkInterface * pConfig) +{ + (void)index; + + esp_err_t ec; + + ec = Esp32_InitaliseWifi(); + if(ec != ESP_OK) return SOCK_SOCKET_ERROR; + + // Get Wireless config + HAL_Configuration_Wireless80211 * pWireless = ConfigurationManager_GetWirelessConfigurationFromId(pConfig->SpecificConfigId); + if (pWireless == 0 ) return SOCK_SOCKET_ERROR; + + // Wireless station not enabled + if ( !(Esp32_GetWifiMode() & WIFI_MODE_STA) ) return SOCK_SOCKET_ERROR; + + if ( !(pWireless->Flags & WirelessFlags_Enable)) return SOCK_SOCKET_ERROR; + + // Connect if Auto connect and we have an ssid + if ( (pWireless->Flags & WirelessFlags_Auto) && (hal_strlen_s((const char *)pWireless->Ssid) > 0) ) + { + Esp32_Wireless_Connect(pWireless); + + // Maybe remove SmartConfig flag if conected ok + } + + if ( pWireless->Flags & WirelessFlags_SmartConfig) + { + // FIXME + // Disable for now, When the smart_config starts it scans for wireless AP + // If it doesn't find any AP it ends up with a exception which causes the device to restart + + // Start Smart config (if enabled) + //Start_wifi_smart_config(); + } + + return Esp32_Wait_NetNumber(ESP_IF_WIFI_STA); +} + +bool Esp32_Wireless_Close(int index) +{ + (void)index; + + if ( WifiInitialised ) + { + esp_wifi_deinit(); + WifiInitialised = false; + } + return false; +} + +// Start a scan +int Esp32_Wireless_Scan() +{ + wifi_scan_config_t config = {}; + + config.scan_type = WIFI_SCAN_TYPE_PASSIVE; + config.scan_time.passive = 500; // 500 ms + + // Start a WIFI scan + // When complete a Scan Complete event will be fired + esp_err_t res = esp_wifi_scan_start( &config, false ); + return (int)res; +} + +wifi_auth_mode_t MapAuthentication( AuthenticationType type) +{ + wifi_auth_mode_t mapAuth[] = { + WIFI_AUTH_OPEN, // 0 None + WIFI_AUTH_OPEN, // 1 EAP + WIFI_AUTH_OPEN, // 2 PEAP + WIFI_AUTH_OPEN, // 3 WCN + WIFI_AUTH_OPEN, // 4 Open + WIFI_AUTH_OPEN, // 5 Shared + WIFI_AUTH_WEP, // 6 WEP + WIFI_AUTH_WPA_PSK, // 7 WPA + WIFI_AUTH_WPA_WPA2_PSK // 8 WPA2 + }; + + return mapAuth[type]; +} + +esp_err_t Esp32_WirelessAP_Configure(HAL_Configuration_NetworkInterface * pConfig ) +{ + esp_err_t ec; + + tcpip_adapter_ip_info_t tcpip_info; + + ec = tcpip_adapter_get_ip_info(TCPIP_ADAPTER_IF_AP, &tcpip_info); + + if ( pConfig->IPv4Address != 0 ) + { + tcpip_info.ip.addr = pConfig->IPv4Address; + tcpip_info.netmask.addr = pConfig->IPv4NetMask; + tcpip_info.gw.addr = pConfig->IPv4GatewayAddress; + ec = tcpip_adapter_set_ip_info(TCPIP_ADAPTER_IF_AP, &tcpip_info ); + } + else + { + pConfig->IPv4Address = tcpip_info.ip.addr; + pConfig->IPv4NetMask = tcpip_info.netmask.addr; + pConfig->IPv4GatewayAddress = tcpip_info.gw.addr; + } + + HAL_Configuration_WirelessAP * pWireless = ConfigurationManager_GetWirelessAPConfigurationFromId(pConfig->SpecificConfigId); + if (pWireless == 0 ) return ESP_FAIL; + + wifi_config_t ap_config = { 0 }; + + hal_strncpy_s( (char *)ap_config.ap.ssid, sizeof(ap_config.ap.ssid), (char *)pWireless->Ssid, hal_strlen_s((char *)pWireless->Ssid) ); + hal_strncpy_s( (char*)ap_config.ap.password, sizeof(ap_config.ap.password), (char *)pWireless->Password, hal_strlen_s((char *)pWireless->Password) ); + + ap_config.ap.ssid_len = hal_strlen_s((char *)pWireless->Ssid); + ap_config.ap.channel = pWireless->Channel; + ap_config.ap.ssid_hidden = (pWireless->Flags & WirelessAPFlags_Hidden_SSID)? 1 : 0; + ap_config.ap.authmode = MapAuthentication(pWireless->Authentication); + + if (hal_strlen_s((char *)ap_config.ap.password) == 0) + { + ap_config.ap.authmode = WIFI_AUTH_OPEN; + } + + // Max connections for ESP32 + ap_config.ap.max_connection = pWireless->MaxConnections; + if (ap_config.ap.max_connection > ESP_WIFI_MAX_CONN_NUM) + { + ap_config.ap.max_connection = ESP_WIFI_MAX_CONN_NUM; + } + + ap_config.ap.beacon_interval = 100; + + ec = esp_wifi_set_config(ESP_IF_WIFI_AP, &ap_config); + if (ec != ESP_OK) + { + ESP_LOGE(TAG, "WiFi set AP config - result %d", ec); + } + + return ec; +} + +// +// Open Wireless Soft AP +// +// If AP is enabled it will have been configured and started running when the WiFI stack is initialised +// All we need to do here is return the NetIf number used by ESP IDF +// Also make sure WIfi in initialised correctly if config is changed +int Esp32_WirelessAP_Open(int index, HAL_Configuration_NetworkInterface * pConfig) +{ + (void)index; + esp_err_t ec; + + // Initialise Wifi stack if required + ec = Esp32_InitaliseWifi(); + if(ec != ESP_OK) return SOCK_SOCKET_ERROR; + + // AP mode enabled ? + if ( !(Esp32_GetWifiMode() & WIFI_MODE_AP) ) + { + return SOCK_SOCKET_ERROR; + } + + // Return NetIf number + // FIXME find a better way to get the netif ptr + // This becomes available on the event AP STARTED + // for the moment we just wait for it + return Esp32_Wait_NetNumber(ESP_IF_WIFI_AP); +} + +// +// Closing down AP +// +// Either config being updated or shutdown +// Closing AP will also stop Station +// +bool Esp32_WirelessAP_Close(int index) +{ + (void)index; + + Esp32_DeinitWifi(); + + return true; +} + +// +// Find the netif * for the passed esp_interface_t +// +extern struct netif * Esp32_find_netif(esp_interface_t esp_if) +{ + struct netif *pNetIf; + + for (pNetIf = netif_list; pNetIf != NULL; pNetIf = pNetIf->next) + { + if (esp_if == tcpip_adapter_get_esp_if((void *)pNetIf)) + { + return pNetIf; + } + } + return NULL; +} + +// Esp32_Wait_NetNumber +// +// Find the NetiF number used by esp_interface_t +// If not availbale then loop and wait for interface to start +// +int Esp32_Wait_NetNumber(esp_interface_t esp_if) +{ + int number = 0; + + // FIXME find a better way to get the netif ptr + struct netif *pNetIf; + while(true) + { + // Return NetIf number for Esp32 wireless station + pNetIf = Esp32_find_netif(esp_if); + if (pNetIf != NULL) break; + + vTaskDelay(20 / portTICK_PERIOD_MS); + } + + return pNetIf->num; +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Network/Target_Network.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Network/Target_Network.cpp new file mode 100644 index 00000000..dfe7e736 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Network/Target_Network.cpp @@ -0,0 +1,271 @@ + +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "Esp32_os.h" + + +// +// Works with the Target_NetworkConfig to map the Network_Interface_XXXXX calls to the correct driver + +int Esp32_Wireless_Open(int index, HAL_Configuration_NetworkInterface * config); +bool Esp32_Wireless_Close(int index); +int Esp32_WirelessAP_Open(int index, HAL_Configuration_NetworkInterface * config); +bool Esp32_WirelessAP_Close(int index); +int Esp32_Ethernet_Open(int index, HAL_Configuration_NetworkInterface * config); +bool Esp32_Ethernet_Close(int index); +int Esp32_Wireless_Scan(); +int Esp32_Wireless_Disconnect(); +int Esp32_Wireless_Connect(HAL_Configuration_Wireless80211 * pWireless); + +bool StoreConfigBlock(DeviceConfigurationOption configType, uint32_t configurationIndex, void * pConfigBlock, size_t writeSize ); + + +bool Network_Interface_Bind(int index) +{ + (void)index; + + return true; +} + +int Network_Interface_Open(int configIndex) +{ + HAL_Configuration_NetworkInterface * pConfig; + + // Check index in range + if ( g_TargetConfiguration.NetworkInterfaceConfigs->Count <= configIndex ) return SOCK_SOCKET_ERROR; + + // load network interface configuration from storage + pConfig = g_TargetConfiguration.NetworkInterfaceConfigs->Configs[configIndex]; + + switch((tcpip_adapter_if_t)configIndex) + { + // Wireless + case TCPIP_ADAPTER_IF_STA: + return Esp32_Wireless_Open(configIndex, pConfig); + + // Soft AP + case TCPIP_ADAPTER_IF_AP: + return Esp32_WirelessAP_Open(configIndex, pConfig); + +#if ESP32_ETHERNET_SUPPORT + // Ethernet + case TCPIP_ADAPTER_IF_ETH: + return Esp32_Ethernet_Open(configIndex, pConfig); +#endif + default: + break; + } + return SOCK_SOCKET_ERROR; +} + +bool Network_Interface_Close(int configIndex) +{ + switch((tcpip_adapter_if_t)configIndex) + { + // Wireless + case TCPIP_ADAPTER_IF_STA: + return Esp32_Wireless_Close(configIndex); + + // Soft AP + case TCPIP_ADAPTER_IF_AP: + return Esp32_WirelessAP_Close(configIndex); + +#if ESP32_ETHERNET_SUPPORT + // Ethernet + case TCPIP_ADAPTER_IF_ETH: + return Esp32_Ethernet_Close(configIndex); +#endif + default: + break; + + } + return false; +} + + +bool Network_Interface_Start_Scan(int configIndex) +{ + switch((tcpip_adapter_if_t)configIndex) + { + // Wireless + case TCPIP_ADAPTER_IF_STA: + return (Esp32_Wireless_Scan() == 0); + + } + + return false; +} + +bool GetWirelessConfig(int configIndex, HAL_Configuration_Wireless80211 ** pWireless) +{ + HAL_Configuration_NetworkInterface * pConfig; + + // Check index in range + if ( g_TargetConfiguration.NetworkInterfaceConfigs->Count <= configIndex ) return false; + + // load network interface configuration from storage + pConfig = g_TargetConfiguration.NetworkInterfaceConfigs->Configs[configIndex]; + if ( pConfig->InterfaceType != NetworkInterfaceType_Wireless80211) return false; + + *pWireless = ConfigurationManager_GetWirelessConfigurationFromId(pConfig->SpecificConfigId); + + return true; +} + +// +// Connect to wireless network SSID using passphase +// +int Network_Interface_Connect(int configIndex, const char * ssid, const char * passphase, int options) +{ + HAL_Configuration_Wireless80211 * pWireless; + + if ( GetWirelessConfig(configIndex, & pWireless) == false ) return SOCK_SOCKET_ERROR; + + pWireless->Flags = WirelessFlags_Enable; + + if ( options & NETWORK_CONNECT_RECONNECT) + { + pWireless->Flags |= WirelessFlags_Auto; + } + else + { + pWireless->Flags ^= WirelessFlags_Auto; + } + + // Update Wireless structure with new SSID and passphase + hal_strcpy_s( (char *)pWireless->Ssid, sizeof(pWireless->Ssid), ssid ); + hal_strcpy_s( (char *)pWireless->Password, sizeof(pWireless->Password), passphase ); + + // Option to Save new config + if ( options & NETWORK_CONNECT_SAVE_CONFIG) + { + StoreConfigBlock( DeviceConfigurationOption_Wireless80211Network, configIndex, pWireless, sizeof(HAL_Configuration_Wireless80211) ); + } + + switch((tcpip_adapter_if_t)configIndex) + { + // Wireless + case TCPIP_ADAPTER_IF_STA: + esp_err_t err = Esp32_Wireless_Connect( pWireless); + + return (int)err; + + } + + return SOCK_SOCKET_ERROR; +} + +int Network_Interface_Disconnect(int configIndex) +{ + switch((tcpip_adapter_if_t)configIndex) + { + // Wireless + case TCPIP_ADAPTER_IF_STA: + esp_err_t err = Esp32_Wireless_Disconnect(); + + return (err == ESP_OK); + + } + + return false; +} + + +wifi_sta_info_t wireless_sta[ESP_WIFI_MAX_CONN_NUM] = { 0 }; + +// +// Update save stations with rssi +// +void Network_Interface_update_Stations() +{ + esp_err_t ec; + wifi_sta_list_t stations; + + ec = esp_wifi_ap_get_sta_list(&stations); + + if (ec == ESP_OK) + { + // Find save station and update + for (int x = 0; x < stations.num; x++) + { + for (int y = 0; y < ESP_WIFI_MAX_CONN_NUM; y++) + { + if (wireless_sta[y].reserved) + { + if (memcmp( wireless_sta[y].mac, stations.sta[x].mac, 6) == 0 ) + { + memcpy(&wireless_sta[y], &stations.sta[x], sizeof(wifi_sta_info_t)); + wireless_sta[y].reserved = 1; + break; + } + } + } + } + + } +} + +// +// Add a station to our list of Stations +// +void Network_Interface_Add_Station(uint16_t index, uint8_t * macAddress) +{ + if (index < ESP_WIFI_MAX_CONN_NUM) + { + memcpy( wireless_sta[index].mac, macAddress , 6); + wireless_sta[index].reserved = 1; + Network_Interface_update_Stations(); + } +} + +// +// Remove a station from our list of stations +void Network_Interface_Remove_Station(uint16_t index) +{ + if (index < ESP_WIFI_MAX_CONN_NUM) + { + wireless_sta[index].reserved = 0; + Network_Interface_update_Stations(); + } +} + +// Return the maximum number of stations +int Network_Interface_Max_Stations() +{ + return ESP_WIFI_MAX_CONN_NUM; +} + +// +// +// +bool Network_Interface_Get_Station(uint16_t index, uint8_t * macAddress, uint8_t * rssi, uint32_t * phyModes) +{ + if (wireless_sta[index].reserved) + { + memcpy(macAddress, wireless_sta[index].mac, 6); + *rssi = wireless_sta[index].rssi; + *phyModes = wireless_sta[index].phy_11b | + (wireless_sta[index].phy_11g << 1) | + (wireless_sta[index].phy_11n << 2) | + (wireless_sta[index].phy_lr << 3); + return true; + } + + return false; +} + +// +// De-Auth connected stations +// +void Network_Interface_Deauth_Station(uint16_t stationIndex) +{ + stationIndex++; + if (stationIndex>=1 && stationIndex<= ESP_WIFI_MAX_CONN_NUM) + { + esp_wifi_deauth_sta(stationIndex); + } +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Network/targetHAL_Network.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Network/targetHAL_Network.cpp new file mode 100644 index 00000000..4cc56a0a --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Network/targetHAL_Network.cpp @@ -0,0 +1,261 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +// This file includes the board specific Network Intialisation + +#include +#include "Esp32_os.h" +#include "LWIP_Sockets.h" +#include "apps/sntp.h" +#include + +extern "C" void set_signal_sock_function( void (*funcPtr)() ); + +#define WIFI_EVENT_TYPE_SCAN_COMPLETE 1 + +//#define NetEventPrint 1 + + +// +// Callback from LWIP on event +// +void sys_signal_sock_event() +{ + Events_Set(SYSTEM_EVENT_FLAG_SOCKET); +} + +// +// Dummy Ethernet Initialisation, board specific Initialisation in separate file +__nfweak void InitialiseEthernet() +{ +} + +static void PostAddressChanged(uint netIndex) +{ + Network_PostEvent(NetworkEventType_AddressChanged, 0, netIndex); +} + +static void PostAvailabilityOn(uint netIndex) +{ + Network_PostEvent(NetworkEventType_AvailabilityChanged, 1, netIndex); +} + +static void PostAvailabilityOff(uint netIndex) +{ + Network_PostEvent(NetworkEventType_AvailabilityChanged, 0, netIndex); +} + +static void PostScanComplete(uint netIndex) +{ + PostManagedEvent( EVENT_WIFI, WiFiEventType_ScanComplete, 0, netIndex ); +} + +static void PostAPStationChanged(uint connect, uint netInfo) +{ + Network_PostEvent(NetworkEventType_APClientChanged, connect, netInfo); +} + +static void initialize_sntp() +{ + sntp_stop(); + sntp_setoperatingmode(SNTP_OPMODE_POLL); + sntp_setservername(0, SNTP_SERVER_DEFAULT_ADDRESS); + sntp_init(); +} + +// +// Network event loop handler +// +static esp_err_t event_handler(void *ctx, system_event_t *event) +{ + (void)ctx; + int stationIndex; + + #ifdef NetEventPrint + ets_printf("Network event %d\n", event->event_id); + #endif + + switch(event->event_id) + { + // Wifi station events + case SYSTEM_EVENT_STA_START: + // Smart config commented out as giving exception when running + // xTaskCreate(smartconfig_task, "smartconfig_example_task", 4096, NULL, 3, NULL); + #ifdef NetEventPrint + ets_printf("SYSTEM_EVENT_STA_START\n"); + #endif + break; + + case SYSTEM_EVENT_STA_GOT_IP: + #ifdef NetEventPrint + ets_printf("SYSTEM_EVENT_STA_GOT_IP\n"); + #endif + PostAddressChanged(TCPIP_ADAPTER_IF_STA); + initialize_sntp(); + //xEventGroupSetBits(wifi_event_group, CONNECTED_BIT); + break; + + case SYSTEM_EVENT_STA_LOST_IP: + PostAddressChanged(TCPIP_ADAPTER_IF_STA); + #ifdef NetEventPrint + ets_printf("SYSTEM_EVENT_STA_LOST_IP\n"); + #endif + break; + + case SYSTEM_EVENT_STA_CONNECTED: + #ifdef NetEventPrint + ets_printf("SYSTEM_EVENT_STA_CONNECTED\n"); + #endif + PostAvailabilityOn(TCPIP_ADAPTER_IF_STA); + break; + + case SYSTEM_EVENT_STA_DISCONNECTED: + #ifdef NetEventPrint + ets_printf("SYSTEM_EVENT_STA_DISCONNECTED\n"); + #endif + PostAvailabilityOff(TCPIP_ADAPTER_IF_STA); + esp_wifi_connect(); + //xEventGroupClearBits(wifi_event_group, CONNECTED_BIT); + break; + + // Scan of available Wifi networks complete + case SYSTEM_EVENT_SCAN_DONE: + #ifdef NetEventPrint + ets_printf("SYSTEM_EVENT_SCAN_DONE\n"); + #endif + PostScanComplete(TCPIP_ADAPTER_IF_STA); + break; + + case SYSTEM_EVENT_STA_AUTHMODE_CHANGE: + // system_event_sta_authmode_change_t *auth_change = &event->event_info.auth_change; + #ifdef NetEventPrint + ets_printf("SYSTEM_EVENT_STA_AUTHMODE_CHANGE"); + #endif + break; + + case SYSTEM_EVENT_STA_WPS_ER_SUCCESS: + #ifdef NetEventPrint + ets_printf("SYSTEM_EVENT_STA_WPS_ER_SUCCESS\n"); + #endif + break; + + case SYSTEM_EVENT_STA_WPS_ER_FAILED: + #ifdef NetEventPrint + ets_printf("SYSTEM_EVENT_STA_WPS_ER_FAILED\n"); + #endif + break; + + case SYSTEM_EVENT_STA_WPS_ER_TIMEOUT: + #ifdef NetEventPrint + ets_printf("SYSTEM_EVENT_STA_WPS_ER_TIMEOUT\n"); + #endif + break; + + case SYSTEM_EVENT_STA_WPS_ER_PIN: + #ifdef NetEventPrint + ets_printf("SYSTEM_EVENT_STA_WPS_ER_PIN\n"); + #endif + break; + + // Wireless AP events + case SYSTEM_EVENT_AP_START: + PostAvailabilityOn(TCPIP_ADAPTER_IF_AP); + #ifdef NetEventPrint + ets_printf("SYSTEM_EVENT_AP_START\n"); + #endif + break; + + case SYSTEM_EVENT_AP_STOP: + PostAvailabilityOff(TCPIP_ADAPTER_IF_AP); + #ifdef NetEventPrint + ets_printf("SYSTEM_EVENT_AP_STOP\n"); + #endif + break; + + case SYSTEM_EVENT_AP_STACONNECTED: + stationIndex = event->event_info.sta_connected.aid - 1; + Network_Interface_Add_Station(stationIndex, event->event_info.sta_connected.mac); + + // Post the Network interface + Client ID in top 8 bits + PostAPStationChanged(1, TCPIP_ADAPTER_IF_AP + (stationIndex << 8)); + #ifdef NetEventPrint + ets_printf("SYSTEM_EVENT_AP_STACONNECTED %d\n", event->event_info.sta_connected.aid); + #endif + break; + + case SYSTEM_EVENT_AP_STADISCONNECTED: + stationIndex = event->event_info.sta_connected.aid - 1; + Network_Interface_Remove_Station(stationIndex); + PostAPStationChanged(0, TCPIP_ADAPTER_IF_AP + (stationIndex << 8)); + #ifdef NetEventPrint + ets_printf("SYSTEM_EVENT_AP_STADISCONNECTED %d\n", event->event_info.sta_disconnected.aid); + PrintStations(); + #endif + break; + + case SYSTEM_EVENT_AP_STA_GOT_IP6: + #ifdef NetEventPrint + ets_printf("SYSTEM_EVENT_AP_STA_GOT_IP6\n"); + #endif + break; + + case SYSTEM_EVENT_AP_PROBEREQRECVED: + #ifdef NetEventPrint + ets_printf("SYSTEM_EVENT_AP_PROBEREQRECVEDxz\n"); + #endif + break; + + // Ethernet events + case SYSTEM_EVENT_ETH_START: + #ifdef NetEventPrint + ets_printf("SYSTEM_EVENT_ETH_START\n"); + #endif + break; + + case SYSTEM_EVENT_ETH_STOP: + #ifdef NetEventPrint + ets_printf("SYSTEM_EVENT_ETH_STOP\n"); + #endif + break; + + case SYSTEM_EVENT_ETH_CONNECTED: + #ifdef NetEventPrint + ets_printf("SYSTEM_EVENT_ETH_CONNECTED\n"); + #endif + PostAvailabilityOn(TCPIP_ADAPTER_IF_ETH); + break; + + case SYSTEM_EVENT_ETH_GOT_IP: + #ifdef NetEventPrint + ets_printf("SYSTEM_EVENT_ETH_GOT_IP\n"); + #endif + PostAddressChanged(TCPIP_ADAPTER_IF_ETH); + initialize_sntp(); + break; + + case SYSTEM_EVENT_ETH_DISCONNECTED: + #ifdef NetEventPrint + ets_printf("SYSTEM_EVENT_ETH_DISCONNECTED\n"); + #endif + PostAvailabilityOff(TCPIP_ADAPTER_IF_ETH); + break; + + default: + break; + } + + return ESP_OK; +} + +void nanoHAL_Network_Initialize() +{ + // Initialise the Lwip CLR signal callback + set_signal_sock_function( &sys_signal_sock_event ); + + // Initialise Tcp adpater + tcpip_adapter_init(); + + esp_event_loop_init(event_handler, NULL); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/README.md b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/README.md new file mode 100644 index 00000000..be005778 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/README.md @@ -0,0 +1,10 @@ +# ESP32 WROOM-32 + +This reference target _fits_ all EPS32 boards carrying an ESP32-WROOM-32 module. + +Check the details at the documentation website [here](http://docs.nanoframework.net/articles/reference-targets/esp32-wroom-32.html) + +Getting started guides and build instructions can also be found at the documentation website: + +- [Build instructions](https://docs.nanoframework.net/content/getting-started-guides/build-esp32.html) +- [Getting started with managed code (C#)](https://docs.nanoframework.net/content/getting-started-guides/getting-started-managed.html) diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Target_Windows_Storage.c b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Target_Windows_Storage.c new file mode 100644 index 00000000..557e977d --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/Target_Windows_Storage.c @@ -0,0 +1,161 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +// +// Initialise SD card and mount on VFS +// Supports MMC and SPI SD cards +// MMC supports 4bit or 1 bit + +// == Boards == +// OLimex EVB - 1 bit SD/MMC ( DAT0 - GPIO2, CMD/DI - GPIO15 ), No Card detect, No Write protect +// Wrover V4 - 4 bit SD/MMC ( Card detect ) +// D0 = 2, D1 = 4, D2 = 12, D3 = 13 +// CLK = 14, CMD = 15, DETECT = 21 + + +// SPI test +// MISO = 2, MOSI = 15, CLK = 14, CS = 15 + +// 5 VSPICS0 (cs) +// 18 VSPICLK (clockPin) * +// 19 VSPIQ (miso) * +// 21 VSPIHD (HD) +// 22 VSPIWP (WP) +// 23 VSPID (mosi) * + +#include +#include +#include +#include +#include "esp_err.h" +#include "esp_log.h" +#include "esp_vfs_fat.h" +#include "driver/sdmmc_host.h" +#include "driver/sdspi_host.h" +#include "sdmmc/include/sdmmc_cmd.h" +#include + +static const char *TAG = "SDCard"; + +// Pin mapping when using SPI mode. +// With this mapping, SD card can be used both in SPI and 1-line SD mode. +// Note that a pull-up on CS line is required in SD mode. +//#define PIN_NUM_MISO 2 +//#define PIN_NUM_MOSI 15 +//#define PIN_NUM_CLK 14 +//#define PIN_NUM_CS 13 + +#if defined(HAL_USE_SDC) + +bool Storage_UnMountSDCard() +{ + if (esp_vfs_fat_sdmmc_unmount() != ESP_OK) + return false; + + return true; +} + +// +// Mount the SDCard device as a FAT device on the VFS +// +bool Storage_MountSDCard(char * vfsName, sdmmc_host_t * host, void* slot_config, bool formatOnMount, int maxFiles ) +{ + + esp_vfs_fat_sdmmc_mount_config_t mount_config = { + .format_if_mount_failed = formatOnMount, + .max_files = maxFiles, + .allocation_unit_size = 16 * 1024 + }; + + sdmmc_card_t* card; + esp_err_t ret = esp_vfs_fat_sdmmc_mount(vfsName, host, (sdmmc_slot_config_t*)slot_config, &mount_config, &card); + if (ret == ESP_ERR_INVALID_STATE) + { + // Invalid state means its already mounted, this can happen if you are trying to debug mount from managed code + // and the code has already run & mounted + Storage_UnMountSDCard(); + ret = esp_vfs_fat_sdmmc_mount(vfsName, host, (sdmmc_slot_config_t*)slot_config, &mount_config, &card); + } + + if (ret != ESP_OK) { + if (ret == ESP_FAIL) { + ESP_LOGE(TAG, "Failed to mount filesystem. "); + } + else { + ESP_LOGE(TAG, "Failed to initialize the card (%s). ", esp_err_to_name(ret)); + } + return false; + } + + return true; +} + + +// Storage_InitSDCardMMC +// Initial the SD card Slot 1 - 4/1 bit ( hs2_* signals ) +// +// vfsName - Name of disk for vfs - i.e "/SDSPI" +// maxFiles- Maximum number of open files +// bit1Mode- true to use 1 bit MMC interface +// +// return true if OK +// +bool Storage_InitSDCardMMC(char * vfsName, int maxFiles, bool bit1Mode) +{ + ESP_LOGI(TAG, "Initializing MMC SD card"); + + sdmmc_host_t host = SDMMC_HOST_DEFAULT(); + + // Using 1 bit data ( OLimex EVB etc ) + if (bit1Mode) + { + host.flags = SDMMC_HOST_FLAG_1BIT; + host.max_freq_khz = SDMMC_FREQ_PROBING; + } + + // This initializes the slot without card detect (CD) and write protect (WP) signals. + // Modify slot_config.gpio_cd and slot_config.gpio_wp if your board has these signals. + sdmmc_slot_config_t slot_config = SDMMC_SLOT_CONFIG_DEFAULT(); + + // GPIOs 15, 2, 4, 12, 13 should have external 10k pull-ups. + // Internal pull-ups are not sufficient. However, enabling internal pull-ups + // does make a difference some boards, so we do that here. + gpio_set_pull_mode(15, GPIO_PULLUP_ONLY); // CMD, needed in 4- and 1- line modes + gpio_set_pull_mode(2, GPIO_PULLUP_ONLY); // D0, needed in 4- and 1-line modes + + if (!bit1Mode) + { + gpio_set_pull_mode(4, GPIO_PULLUP_ONLY); // D1, needed in 4-line mode only + gpio_set_pull_mode(12, GPIO_PULLUP_ONLY); // D2, needed in 4-line mode only + gpio_set_pull_mode(13, GPIO_PULLUP_ONLY); // D3, needed in 4-line modes only + } + + return Storage_MountSDCard(vfsName, &host, &slot_config, false, maxFiles); +} + +// Storage_InitSDCardSPI +// Initial the SD card connected by SPI) +// +// vfsName - Name of disk for vfs - i.e "/SDSPI" +// maxFiles- Maximum number of open files +// +// return true if OK +// +bool Storage_InitSDCardSPI(char * vfsName, int maxFiles, int pin_Miso, int pin_Mosi, int pin_Clk, int pin_Cs) +{ + ESP_LOGI(TAG, "Initializing SPI SD card"); + + sdmmc_host_t host = SDSPI_HOST_DEFAULT(); + sdspi_slot_config_t slot_config = SDSPI_SLOT_CONFIG_DEFAULT(); + slot_config.gpio_miso = pin_Miso; + slot_config.gpio_mosi = pin_Mosi; + slot_config.gpio_sck = pin_Clk; + slot_config.gpio_cs = pin_Cs; + + return Storage_MountSDCard(vfsName, &host, &slot_config, false, maxFiles); +} + +#endif + diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/CMakeLists.txt b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/CMakeLists.txt new file mode 100644 index 00000000..c6518ee9 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/CMakeLists.txt @@ -0,0 +1,28 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append target ESP32 source files +list(APPEND TARGET_ESP32_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/platform_heap.c") + +list(APPEND TARGET_ESP32_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_ReceiverThread.c") +list(APPEND TARGET_ESP32_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_HAL_Interface.c") + +list(APPEND TARGET_ESP32_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Target_BlockStorage_ESP32FlashDriver.c") +list(APPEND TARGET_ESP32_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/platform_BlockStorage.c") +list(APPEND TARGET_ESP32_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage.c") + + +list(APPEND TARGET_ESP32_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/FreeRTOS-openocd.c") + +list(APPEND TARGET_ESP32_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Esp32_DeviceMapping.cpp") + +list(APPEND TARGET_ESP32_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/GenericPort.cpp") + +# append nanoHAL +list(APPEND TARGET_ESP32_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL.c") +list(APPEND TARGET_ESP32_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Time.cpp") + +# make vars global +set(TARGET_ESP32_COMMON_SOURCES ${TARGET_ESP32_COMMON_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/Device_BlockStorage.c b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/Device_BlockStorage.c new file mode 100644 index 00000000..f913b4ab --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/Device_BlockStorage.c @@ -0,0 +1,137 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +#include +#include + +// the block ranges mirror the partition table +// spliting each partition on it's own block range is required to use memory mapping + + +const BlockRange BlockRange1[] = +{ + // factory + { BlockRange_BLOCKTYPE_CODE , 0, 0 }, // 0x010000 nanoCLR +}; + +const BlockRange BlockRange2[] = +{ + // deploy + { BlockRange_BLOCKTYPE_DEPLOYMENT, 0, 0 }, // 0x110000 deployment +}; + +const BlockRange BlockRange3[] = +{ + // config + { BlockRange_BLOCKTYPE_CONFIG , 0, 0 } // 0x2D0000 config +}; + +BlockRegionInfo BlockRegions[] = +{ + // nanoCLR + { + (0), // no attributes for this region + 0x010000, // start address for block region + 1, // total number of blocks in this region + 0x100000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + }, + + // Deployment area + { + (BlockRegionAttribute_MemoryMapped), // this region is memory mapped + 0x110000, // start address for block region + 1, // total number of blocks in this region + 0x70000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange2), + BlockRange2, + }, + + // Config, SPIFS partition + { + (0), // no attributes for this region + 0x0, // start address for block region + 1, // total number of blocks in this region + 0x10000, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange3), + BlockRange3, + } +}; + + +const DeviceBlockInfo Device_BlockInfo = +{ + (0), // ESP32 storage doesn't supports XIP, instead it provides memory mapped read access to SPI storage + 1, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; + + + +// +// Fix up Block region info based on current partion layout +// +void FixUpBlockRegionInfo() +{ + // nanoCLR + const esp_partition_t * part_nanoClr = esp_partition_find_first(ESP_PARTITION_TYPE_APP, 0, 0); + if (part_nanoClr) + { + BlockRegions[0].Start = part_nanoClr->address; + BlockRegions[0].BytesPerBlock = part_nanoClr->size; + } + // Deployment + const esp_partition_t * part_deploy = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, 0x84, 0); + if (part_deploy) + { + BlockRegions[1].Start = part_deploy->address; + BlockRegions[1].BytesPerBlock = part_deploy->size; + } + + // Config + const esp_partition_t * part_config = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_SPIFFS, 0); + if (part_config) + { + BlockRegions[2].Start = part_config->address; + BlockRegions[2].BytesPerBlock = part_config->size; + } + +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/Esp32_DeviceMapping.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/Esp32_DeviceMapping.cpp new file mode 100644 index 00000000..c8c637af --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/Esp32_DeviceMapping.cpp @@ -0,0 +1,199 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "Esp32_os.h" +#include "Esp32_DeviceMapping.h" + + +// SPI +// 2 devices +// Map pins mosi, miso, clock +// +int8_t Esp32_SPI_DevicePinMap[2][3] = +{ + {GPIO_NUM_23, GPIO_NUM_25, GPIO_NUM_19}, // SPI1 - Wrover SPI display pins + {-1, -1, -1} // SPI2 - no pins assigned +}; + +// Serial +// 3 devices COM1,COM2, COM3 ( UART_NUM_0, UART_NUM_1, UART_NUM_2 ) +// Map pins Tx, RX, RTS, CTS +// Set default direct pins +int8_t Esp32_SERIAL_DevicePinMap[3][4] = +{ + // COM 1 - pins 1, 3, 19, 22 + {UART_NUM_0_TXD_DIRECT_GPIO_NUM, UART_NUM_0_RXD_DIRECT_GPIO_NUM, UART_NUM_0_RTS_DIRECT_GPIO_NUM, UART_NUM_0_CTS_DIRECT_GPIO_NUM}, + + // COM 2 - 10, 9, 6, 11 + {UART_NUM_1_TXD_DIRECT_GPIO_NUM, UART_NUM_1_RXD_DIRECT_GPIO_NUM, UART_NUM_1_RTS_DIRECT_GPIO_NUM, UART_NUM_1_CTS_DIRECT_GPIO_NUM}, + + // COM3 - 17, 16, 8, 7 + {UART_NUM_2_TXD_DIRECT_GPIO_NUM, UART_NUM_2_RXD_DIRECT_GPIO_NUM, UART_NUM_2_RTS_DIRECT_GPIO_NUM, UART_NUM_2_CTS_DIRECT_GPIO_NUM} + }; + +// ============================================= +// I2C +// 2 devices I2C1 & I2C2 +// Map pins Data & Clock +int8_t Esp32_I2C_DevicePinMap[2][2] = +{ + // I2C1 - pins 18, 19, + {I2C1_DATA, I2C1_CLOCK}, + // I2C2 - pins 25, 26 + {I2C2_DATA, I2C2_CLOCK} +}; + +// ============================================= +// LED PWM +// 16 channels LED1 to LED16 or PWM1 to PWM16 +// Map pins Data & Clock +int8_t Esp32_LED_DevicePinMap[16] = +{ + // Channels ( non assigned ) + -1, // 1 + -1, // 2 + -1, // 3 + -1, // 4 + -1, // 5 + -1, // 6 + -1, // 7 + -1, // 8 + -1, // 9 + -1, // 10 + -1, // 11 + -1, // 12 + -1, // 13 + -1, // 14 + -1, // 15 + -1, // 16 +}; + +// We use "ADC1" for 20 logical channels +// Mapped to ESP32 controllers +// ESP32 ADC1 channels 0 - 7 +// " ADC1 channel 8 - Internal Temperture sensor (VP) +// " ADC1 channel 9 - Internal Hall Sensor (VN) +// " ADC2 channels 10 - 19 +int8_t Esp32_ADC_DevicePinMap[20] = +{ + // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 + 36, 37, 38, 39, 32, 33, 34, 35, 36, 39, 04, 00, 02, 15, 13, 12, 14, 27, 25, 26 +}; + +// +// We use "DAC1" for 2 DAC channels on ESP32 +// These are fixed pins so can't be re-assigned +// +int8_t Esp32_DAC_DevicePinMap[2] = +{ + // 0 1 + 25, 26 +}; + +void Esp32_DecodeAlternateFunction(uint32_t alternateFunction, Esp32_MapDeviceType & deviceType, uint8_t & busIndex, uint16_t & PinIndex) +{ + deviceType = (Esp32_MapDeviceType)((alternateFunction >> 16) & 0x00ff); + busIndex = (uint8_t)((alternateFunction >> 8) & 0x00ff) - 1; + PinIndex = (uint16_t)(alternateFunction & 0x00ff); +} + +int Esp32_GetMappedDevicePins( Esp32_MapDeviceType deviceType, int DevNumber, int PinIndex) +{ + if ( DevNumber >= 0) + { + switch( deviceType ) + { + case DEV_TYPE_SPI: + return (int)Esp32_SPI_DevicePinMap[DevNumber][PinIndex]; + + case DEV_TYPE_I2C: + return (int)Esp32_I2C_DevicePinMap[DevNumber][PinIndex]; + + case DEV_TYPE_SERIAL: + return (int)Esp32_SERIAL_DevicePinMap[DevNumber][PinIndex]; + + case DEV_TYPE_LED_PWM: + return (int)Esp32_LED_DevicePinMap[DevNumber]; + + case DEV_TYPE_ADC: + return (int)Esp32_ADC_DevicePinMap[PinIndex]; + + case DEV_TYPE_DAC: + return (int)Esp32_DAC_DevicePinMap[PinIndex]; + + default: + break; + }; + } + return -1; +} + +int Esp32_GetMappedDevicePinsWithFunction(uint32_t alternateFunction) +{ + Esp32_MapDeviceType deviceType; + uint8_t deviceIndex; + uint16_t pinIndex; + + Esp32_DecodeAlternateFunction(alternateFunction, deviceType, deviceIndex, pinIndex); + + return Esp32_GetMappedDevicePins(deviceType, deviceIndex, pinIndex); +} + + +// Esp32_SetMappedDevicePins +// +// alternateFunction 32 bit integer where 00DDIIFF +// DD= device type +// II= device index 1,2,3 etc +// FF= functional pin i.e data, clock, tx,rx +// +void Esp32_SetMappedDevicePins( uint8_t pin, int32_t alternateFunction ) +{ + Esp32_MapDeviceType deviceType; + uint8_t deviceIndex; + uint16_t mapping; + + Esp32_DecodeAlternateFunction(alternateFunction, deviceType, deviceIndex, mapping); + + // Set the pins used by a device type / index + switch( deviceType ) + { + case DEV_TYPE_GPIO: + // Just opening a GPIO pin will set it to GPIO function + break; + + case DEV_TYPE_SPI: + if (deviceIndex <= 1 && mapping <= 2) + { + Esp32_SPI_DevicePinMap[deviceIndex][mapping] = pin; + } + break; + + case DEV_TYPE_I2C: + if (deviceIndex <= 1 && mapping <= 1) + { + Esp32_I2C_DevicePinMap[deviceIndex][mapping] = pin; + } + break; + + case DEV_TYPE_SERIAL: + if (deviceIndex <= 2 && mapping <= 3) + { + Esp32_SERIAL_DevicePinMap[deviceIndex][mapping] = pin; + } + break; + + case DEV_TYPE_LED_PWM: + if (deviceIndex <= 15 ) + { + Esp32_LED_DevicePinMap[deviceIndex] = pin; + } + break; + + + default: // ignore + break; + } +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/FreeRTOS-openocd.c b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/FreeRTOS-openocd.c new file mode 100644 index 00000000..1960231b --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/FreeRTOS-openocd.c @@ -0,0 +1,24 @@ +/* + * Since at least FreeRTOS V7.5.3 uxTopUsedPriority is no longer + * present in the kernel, so it has to be supplied by other means for + * OpenOCD's threads awareness. + * + * Add this file to your project, and, if you're using --gc-sections, + * ``--undefined=uxTopUsedPriority'' (or + * ``-Wl,--undefined=uxTopUsedPriority'' when using gcc for final + * linking) to your LDFLAGS; same with all the other symbols you need. + */ + +#include "FreeRTOS.h" +#include "esp_attr.h" +#include "sdkconfig.h" + +#ifdef __GNUC__ +#define USED __attribute__((used)) +#else +#define USED +#endif + +//#ifdef CONFIG_ESP32_DEBUG_OCDAWARE +const int USED DRAM_ATTR uxTopUsedPriority = configMAX_PRIORITIES - 1; +//#endif \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/GenericPort.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/GenericPort.cpp new file mode 100644 index 00000000..e219b941 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/GenericPort.cpp @@ -0,0 +1,37 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +#include "nanoCLR_Types.h" +#include "nanoCLR_Runtime.h" + +uint32_t GenericPort_Write( int portNum, const char* data, size_t size ) +{ + // FIXME + // It's only enabled if the C# programm is in running mode and no source level debugger (C# debugger) + // is attached. In all other conditions it's better to be quiet. + // If the debugger is attached we don't output the data because the debugger use the same serial link. + // Maybe later it can also redirect output to the ESP32 app trace + // which is redirected to JTAG/openocd interface + (void)portNum; + if (g_CLR_RT_ExecutionEngine.m_iDebugger_Conditions == CLR_RT_ExecutionEngine::c_fDebugger_StateProgramRunning) + { + char* p = (char*)data; + int counter = 0; + + // send characters directly to the trace port + while(*p != '\0' || counter < (int)size) + { + ets_printf( "%c", *p++); + counter++; + } + return counter; + } + else + { + return (uint32_t)size; + } +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/Target_BlockStorage_ESP32FlashDriver.c b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/Target_BlockStorage_ESP32FlashDriver.c new file mode 100644 index 00000000..1021d492 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/Target_BlockStorage_ESP32FlashDriver.c @@ -0,0 +1,269 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +extern int ets_printf(const char *fmt, ...); + +const DRAM_ATTR esp_partition_t * g_pFlashDriver_partition; +const void * g_esp32_flash_start_ptr; +spi_flash_mmap_handle_t g_esp32_flash_out_handle; + +static const char* TAG = "FlashDriver"; + +bool Esp32FlashDriver_InitializeDevice(void* context) +{ + (void)context; + + //ets_printf("InitializeDevice enter\n"); + + g_esp32_flash_start_ptr = NULL; + + // Find the application partition and save partition entry + g_pFlashDriver_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_NANOCLR, NULL); + if (g_pFlashDriver_partition == NULL) + { + ESP_LOGE(TAG, "InitializeDevice failed\n"); + return false; + } + + //ets_printf("InitializeDevice partition found\n"); + + // Map Partition into memory + if (esp_partition_mmap(g_pFlashDriver_partition, 0, g_pFlashDriver_partition->size, SPI_FLASH_MMAP_DATA, &g_esp32_flash_start_ptr, &g_esp32_flash_out_handle) != ESP_OK) + { + ESP_LOGE(TAG, "Map memory failed\n"); + return false; + } + + //ets_printf("InitializeDevice flash adr %X mapped %X\n", g_pFlashDriver_partition->address, g_esp32_flash_start_ptr); + + return true; +} + +bool Esp32FlashDriver_UninitializeDevice(void* context) +{ + (void)context; + + // Unmap the flash memory + if (g_esp32_flash_start_ptr != NULL) + { + spi_flash_munmap(g_esp32_flash_out_handle); + g_esp32_flash_start_ptr = NULL; + } + + return true; +} + +DeviceBlockInfo* Esp32FlashDriver_GetDeviceInfo(void* context) +{ + MEMORY_MAPPED_NOR_BLOCK_CONFIG* config = context; + + return config->BlockConfig.BlockDeviceInformation; +} + +bool Esp32FlashDriver_Read(void* context, ByteAddress startAddress, unsigned int numBytes, unsigned char* buffer) +{ + // ets_printf("Flash Read adr %X bytes %X target %X\n", startAddress, numBytes, buffer); + + uint32_t regionIndex, rangeIndex; + unsigned char* memStartAdr = NULL; + + MEMORY_MAPPED_NOR_BLOCK_CONFIG* config = (MEMORY_MAPPED_NOR_BLOCK_CONFIG*)context; + DeviceBlockInfo* deviceInfo = config->BlockConfig.BlockDeviceInformation; + + if(!DeviceBlockInfo_FindRegionFromAddress(deviceInfo, startAddress, ®ionIndex, &rangeIndex)) + { + return false; + } + + BlockRegionInfo* region = &deviceInfo->Regions[regionIndex]; + ByteAddress readAddress = BlockRegionInfo_OffsetFromBlock(region, startAddress); + + // setup memory mapped start address + switch(BlockRange_GetBlockUsage(deviceInfo->Regions[regionIndex].BlockRanges[rangeIndex])) + { + case BlockUsage_CODE: + memStartAdr = 0; + break; + + case BlockUsage_DEPLOYMENT: + memStartAdr = (unsigned char *)g_esp32_flash_start_ptr + readAddress; + break; + + default: + return false; + } + + // sanity check for region address overflowing + if ((readAddress + numBytes) > BlockRegionInfo_Size(region) ) + { + ESP_LOGE(TAG, "Invalid Invalid flash address/length\n"); + return false; + } + + // copy from memory mapped address to buffer + memcpy(buffer, memStartAdr, numBytes); + + //ets_printf("Flash Read memStartAdr %X memEndAdr %X Target %X\n", memStartAdr, memStartAdr + numBytes, buffer); + + return true; +} + +bool Esp32FlashDriver_Write(void* context, ByteAddress startAddress, unsigned int numBytes, unsigned char* buffer, bool readModifyWrite) +{ + uint32_t regionIndex, rangeIndex; + + MEMORY_MAPPED_NOR_BLOCK_CONFIG* config = (MEMORY_MAPPED_NOR_BLOCK_CONFIG*)context; + DeviceBlockInfo* deviceInfo = config->BlockConfig.BlockDeviceInformation; + if(!DeviceBlockInfo_FindRegionFromAddress(deviceInfo, startAddress, ®ionIndex, &rangeIndex)) + { + return false; + } + + BlockRegionInfo* region = &deviceInfo->Regions[regionIndex]; + ByteAddress offsetAddress = BlockRegionInfo_OffsetFromBlock(region, startAddress); + + //ets_printf("Flash write adr %X bytes %X src %X\n", startAddress, numBytes, buffer); + + // Check in range of partition + if (numBytes > (BlockRegionInfo_Size(region) - offsetAddress)) + { + ESP_LOGE(TAG, "Invalid Invalid flash address/length\n"); + return false; + } + + if (readModifyWrite) + { + return false; + } + + // write buffer to partition + if (esp_partition_write(g_pFlashDriver_partition, offsetAddress, (const void*)buffer, (size_t)numBytes) != ESP_OK) + { + return false; + } + + return true; +} + +bool Esp32FlashDriver_IsBlockErased(void* context, ByteAddress blockAddress, unsigned int length) +{ + uint32_t regionIndex, rangeIndex; + unsigned char* memStartAdr = NULL; + unsigned char* memEndAdr = NULL; + + MEMORY_MAPPED_NOR_BLOCK_CONFIG* config = (MEMORY_MAPPED_NOR_BLOCK_CONFIG*)context; + DeviceBlockInfo* deviceInfo = config->BlockConfig.BlockDeviceInformation; + if(!DeviceBlockInfo_FindRegionFromAddress(deviceInfo, blockAddress, ®ionIndex, &rangeIndex)) + { + return false; + } + + BlockRegionInfo* region = &deviceInfo->Regions[regionIndex]; + + // get memory mapped start address + switch(BlockRange_GetBlockUsage(deviceInfo->Regions[regionIndex].BlockRanges[rangeIndex])) + { + case BlockUsage_CODE: + memStartAdr = 0; + break; + + case BlockUsage_DEPLOYMENT: + memStartAdr = (unsigned char *)g_esp32_flash_start_ptr; + break; + + default: + return false; + } + + // end address + memEndAdr = memStartAdr + length; + + //ets_printf("IsBlockErased %X %X start mem %X\n", blockAddress, length, g_esp32_flash_start_ptr); + + if ( length > BlockRegionInfo_Size(region)) + { + ESP_LOGE(TAG, "Invalid Invalid flash address/length\n"); + return false; + } + + //ets_printf("IsBlockErased mem start %X end %X\n", memStartAdr, memEndAdr); + + // go through memory anf check for content other than 0xFF (flash erased value) + while (memStartAdr < memEndAdr) + { + if (*memStartAdr != 0xff) + { + //ets_printf("IsBlockErased exit FALSE\n"); + return false; + } + memStartAdr++; + } + + //ets_printf("IsBlockErased exit true\n"); + + return true; +} + +bool Esp32FlashDriver_EraseBlock(void* context, ByteAddress address) +{ + uint32_t regionIndex, rangeIndex; + + MEMORY_MAPPED_NOR_BLOCK_CONFIG* config = (MEMORY_MAPPED_NOR_BLOCK_CONFIG*)context; + DeviceBlockInfo* deviceInfo = config->BlockConfig.BlockDeviceInformation; + if(!DeviceBlockInfo_FindRegionFromAddress(deviceInfo, address, ®ionIndex, &rangeIndex)) + { + return false; + } + + BlockRegionInfo* region = &deviceInfo->Regions[regionIndex]; + ByteAddress startAddress = BlockRegionInfo_OffsetFromBlock(region, address); + uint32_t size = BlockRegionInfo_Size(region); + + //ets_printf("EraseBlock start part adr:%X start mem: %X size:%X erase adr:%X\n", g_pFlashDriver_partition->address, g_esp32_flash_start_ptr, g_pFlashDriver_partition->size, address); + //ets_printf("EraseBlock start addr %X\n", start_addr); + + if (esp_partition_erase_range(g_pFlashDriver_partition, startAddress, size) != ESP_OK) + { + ESP_LOGE(TAG, "EraseBlock Fail\n"); + return false; + } + + //ets_printf("EraseBlock OK\n"); + + return true; +} + +bool Esp32FlashDriver_GetMemoryMappedAddress(void* context, unsigned int blockRegionIndex, unsigned int blockRangeIndex, unsigned int* address) +{ + MEMORY_MAPPED_NOR_BLOCK_CONFIG* config = (MEMORY_MAPPED_NOR_BLOCK_CONFIG*)context; + DeviceBlockInfo* deviceInfo = config->BlockConfig.BlockDeviceInformation; + + #if defined(DEBUG) + // sanity check for non-existent block region + if(blockRegionIndex > (deviceInfo->NumRegions + 1)) + { + return false; + } + #endif + + switch(BlockRange_GetBlockUsage(deviceInfo->Regions[blockRegionIndex].BlockRanges[blockRangeIndex])) + { + case BlockUsage_CODE: + *address = 0; + break; + + case BlockUsage_DEPLOYMENT: + *address = (unsigned int)g_esp32_flash_start_ptr; + break; + + default: + return false; + } + + return true; +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/WireProtocol_HAL_Interface.c b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/WireProtocol_HAL_Interface.c new file mode 100644 index 00000000..ce87a44d --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/WireProtocol_HAL_Interface.c @@ -0,0 +1,142 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// +#include + +#include +#include +#include +#include + +WP_Message inboundMessage; + +bool WP_Initialise(COM_HANDLE port); + +//////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////// +// The functions below are the ones that need to be ported to new channels/HALs when required +// These are to be considered as a reference implementations when working on new ports +// +// This reference implementation provides communication through: +// - serial port (UART/USART) +// +//////////////////////////////////////////////////////////////////////////////////////////////// +#if (HAL_USE_SERIAL == TRUE) + +static bool WP_Port_Intitialised = false; +static uart_port_t WP_Port = UART_NUM_0; + +#define ESP32_UART_RXD_PINS {3,32,16} +#define ESP32_UART_TXD_PINS {1,33,17} +#define ESP32_UART_CTS_PINS {19,6,8} +#define ESP32_UART_RTS_PINS {22,11,7} + + +// Pins +static const char g_ESP32_Uart_RxD_Pins[] = ESP32_UART_RXD_PINS; +static const char g_ESP32_Uart_TxD_Pins[] = ESP32_UART_TXD_PINS; + + +bool WP_Initialise(COM_HANDLE port) +{ + (void)port; + + if ( WP_Port > UART_NUM_2 ) return false; + + uart_config_t uart_config = { + .baud_rate = 921600, //baudrate + .data_bits = UART_DATA_8_BITS, //data bit mode + .parity = UART_PARITY_DISABLE, //parity mode + .stop_bits = UART_STOP_BITS_1, //stop bit mode + .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, //hardware flow control(cts/rts) + .rx_flow_ctrl_thresh = 120, //flow control threshold + }; + + uart_param_config(WP_Port, &uart_config); + + uart_set_pin(WP_Port, g_ESP32_Uart_TxD_Pins[WP_Port], g_ESP32_Uart_RxD_Pins[WP_Port], UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE); + + // Setup UART driver(without UART queue) + uart_driver_install(WP_Port, 1024 * 2, 512, 0, NULL, 0); + + WP_Port_Intitialised = true; + + return true; +} + + +int WP_ReceiveBytes(uint8_t* ptr, uint16_t* size) +{ + // TODO: Initialise Port if not already done, Wire Protocol should be calling this directly at startup + if (!WP_Port_Intitialised) WP_Initialise(WP_Port); + + // save for latter comparison + uint16_t requestedSize = *size; + + //int readData = 0; + // sanity check for request of 0 size + if(*size) + { + ////////////////////////////////////////////////////////// + // PORTING CHANGE REQUIRED HERE // + ////////////////////////////////////////////////////////// + // change here to read (size) bytes from the input stream + // preferably with read timeout and being able to check + // if the requested number of bytes was actually read + ////////////////////////////////////////////////////////// + + // non blocking read from serial port with 100ms timeout + volatile size_t read = uart_read_bytes( WP_Port, ptr, (uint32_t)requestedSize, (TickType_t) 100 / portTICK_PERIOD_MS); + + ptr += read; + *size -= read; + + // check if the requested read matches the actual read count + return (requestedSize == read); + } + + return true; +} + +#else +#error "Wire Protocol needs a transport. Please make sure that HAL_USE_SERIAL and/or HAL_USE_SERIAL_USB are set to TRUE in 'halconf.h'" +#endif + +#if (HAL_USE_SERIAL == TRUE) + +int WP_TransmitMessage(WP_Message* message) +{ + /////////////////////////////////////////////////////////// + // PORTING CHANGE REQUIRED HERE // + /////////////////////////////////////////////////////////// + // change here to write (size) bytes to the output stream + // preferably with timeout and being able to check + // if the write was sucessfull or at least buffered + ////////////////////////////////////////////////////////// + + if (!WP_Port_Intitialised) WP_Initialise(WP_Port); + + //TODO Check if timeout required + // write header to output stream + + if ( uart_write_bytes( WP_Port, (const char*)&message->m_header, sizeof(message->m_header) ) != sizeof(message->m_header)) return false; + + // if there is anything on the payload send it to the output stream + if(message->m_header.m_size && message->m_payload) + { + /////////////////////////////////////////////////////////// + // PORTING CHANGE REQUIRED HERE // + /////////////////////////////////////////////////////////// + // see description above + ////////////////////////////////////////////////////////// + if (uart_write_bytes(WP_Port, (const char*)message->m_payload, message->m_header.m_size ) != (int)message->m_header.m_size ) return false; + } + + return true; +} + +#else +#error "Wire Protocol needs a transport. Please make sure that HAL_USE_SERIAL and/or HAL_USE_SERIAL_USB are set to TRUE in 'halconf.h'" +#endif + diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/WireProtocol_ReceiverThread.c b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/WireProtocol_ReceiverThread.c new file mode 100644 index 00000000..ba1c1292 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/WireProtocol_ReceiverThread.c @@ -0,0 +1,33 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "WireProtocol_HAL_Interface.h" + +extern WP_Message inboundMessage; + +void WP_Message_Initialize(WP_Message* a); +void WP_Message_PrepareReception(WP_Message* a); +void WP_Message_Process(WP_Message* a); + + +void ReceiverThread(void const * argument) +{ + (void)argument; + + // loop forever + while (1) { + + WP_Message_Initialize(&inboundMessage); + WP_Message_PrepareReception(&inboundMessage); + + WP_Message_Process(&inboundMessage); + + // Allow other tasks a chance to run + vTaskDelay(0); + } + + // nothing to deinitialize or cleanup, so it's safe to return +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/mbedtls_entropy_hardware_pool.c b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/mbedtls_entropy_hardware_pool.c new file mode 100644 index 00000000..542b3ddb --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/mbedtls_entropy_hardware_pool.c @@ -0,0 +1,25 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// Get len bytes of entropy from the hardware RNG. +int mbedtls_hardware_poll( void *data, unsigned char *output, size_t len, size_t *olen ) +{ + (void)data; + + for(size_t i = 0; i < len; i++) + { + // our generator returns 32bits numbers + *output = (unsigned char)esp_random(); + + output++; + } + + // callers require this to be set + *olen = len; + + return 0; +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/platform_BlockStorage.c b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/platform_BlockStorage.c new file mode 100644 index 00000000..f1e22e9c --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/platform_BlockStorage.c @@ -0,0 +1,22 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// map here the Block Storage Interface to the ESP32 driver +IBlockStorageDevice ESP32Flash_BlockStorageInterface = +{ + &Esp32FlashDriver_InitializeDevice, + &Esp32FlashDriver_UninitializeDevice, + &Esp32FlashDriver_GetDeviceInfo, + &Esp32FlashDriver_Read, + &Esp32FlashDriver_Write, + NULL, + &Esp32FlashDriver_IsBlockErased, + &Esp32FlashDriver_EraseBlock, + NULL, + &Esp32FlashDriver_GetMemoryMappedAddress, +}; diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/platform_heap.c b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/platform_heap.c new file mode 100644 index 00000000..6eaecdac --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/platform_heap.c @@ -0,0 +1,18 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +void* platform_malloc(size_t size) { + return malloc(size); +} + +void platform_free(void* ptr) { + free(ptr); +} + +void* platform_realloc(void* ptr, size_t size) { + return realloc(ptr, size); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/targetHAL.c b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/targetHAL.c new file mode 100644 index 00000000..35dac5ad --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/targetHAL.c @@ -0,0 +1,50 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +inline void HAL_AssertEx() +{ + asm("break.n 1"); + while(true) { /*nop*/ } +} + +#if !defined(BUILD_RTM) + +inline void HARD_Breakpoint() +{ + asm("break.n 1"); + while(true) { /*nop*/ } +}; + +#endif // !defined(BUILD_RTM) + +// Provides information whether the configuration block storage requires erase command before sending the update command +// ESP32 is storing this using its non-volatile storage therefore no erase is required. +__nfweak bool Target_ConfigUpdateRequiresErase() +{ + return false; +}; + +inline bool Target_HasNanoBooter() +{ + return false; +}; + +// declarations of platform capabilities +uint32_t GetPlatformCapabilities() +{ + return 0; +}; + +// declarations of target capabilities +// If a target has something to declare it has to provide a 'strong' implementation of this. +__nfweak uint32_t GetTargetCapabilities() +{ + return 0; +}; + diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/targetHAL_Time.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/targetHAL_Time.cpp new file mode 100644 index 00000000..1de75c87 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/common/targetHAL_Time.cpp @@ -0,0 +1,25 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include + +// Converts FreeRTOS Tickcount to .NET ticks (100 nanoseconds) +uint64_t HAL_Time_SysTicksToTime(unsigned int sysTicks) +{ + return (((int64_t)sysTicks * (int64_t)1000000 + (int64_t)configTICK_RATE_HZ - 1) / (int64_t)configTICK_RATE_HZ) * 10; +} + +// because HAL_Time_SysTicksToTime needs to be called from C we need a proxy to allow it to be called from 'C' code +extern "C" { + + uint64_t HAL_Time_SysTicksToTime_C(unsigned int sysTicks) + { + return HAL_Time_SysTicksToTime(sysTicks); + } +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/esp32.project.ld b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/esp32.project.ld new file mode 100644 index 00000000..c1b973dd --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/esp32.project.ld @@ -0,0 +1,620 @@ +/* Automatically generated file; DO NOT EDIT */ +/* Espressif IoT Development Framework Linker Script */ +/* Generated from: C:/esp32_tools/esp-idf-v3.3/components/esp32/ld/esp32.project.ld.in */ + +/* Default entry point: */ +ENTRY(call_start_cpu0); + +SECTIONS +{ + /* RTC fast memory holds RTC wake stub code, + including from any source file named rtc_wake_stub*.c + */ + .rtc.text : + { + . = ALIGN(4); + + *( .rtc.literal .rtc.text .rtc.text.*) + + *rtc_wake_stub*.*(.literal .text .literal.* .text.*) + _rtc_text_end = ABSOLUTE(.); + } > rtc_iram_seg + + /* + This section is required to skip rtc.text area because rtc_iram_seg and + rtc_data_seg are reflect the same address space on different buses. + */ + .rtc.dummy : + { + _rtc_dummy_start = ABSOLUTE(.); + _rtc_fast_start = ABSOLUTE(.); + . = SIZEOF(.rtc.text); + _rtc_dummy_end = ABSOLUTE(.); + } > rtc_data_seg + + /* This section located in RTC FAST Memory area. + It holds data marked with RTC_FAST_ATTR attribute. + See the file "esp_attr.h" for more information. + */ + .rtc.force_fast : + { + . = ALIGN(4); + _rtc_force_fast_start = ABSOLUTE(.); + *(.rtc.force_fast .rtc.force_fast.*) + . = ALIGN(4) ; + _rtc_force_fast_end = ABSOLUTE(.); + } > rtc_data_seg + + /* RTC data section holds RTC wake stub + data/rodata, including from any source file + named rtc_wake_stub*.c and the data marked with + RTC_DATA_ATTR, RTC_RODATA_ATTR attributes. + The memory location of the data is dependent on + CONFIG_ESP32_RTCDATA_IN_FAST_MEM option. + */ + .rtc.data : + { + _rtc_data_start = ABSOLUTE(.); + + *( .rtc.data .rtc.data.* .rtc.rodata .rtc.rodata.*) + + *rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .bss .bss.*) + _rtc_data_end = ABSOLUTE(.); + } > rtc_data_location + + /* RTC bss, from any source file named rtc_wake_stub*.c */ + .rtc.bss (NOLOAD) : + { + _rtc_bss_start = ABSOLUTE(.); + *rtc_wake_stub*.*(.bss .bss.*) + *rtc_wake_stub*.*(COMMON) + + *( .rtc.bss) + + _rtc_bss_end = ABSOLUTE(.); + } > rtc_data_location + + /* This section holds data that should not be initialized at power up + and will be retained during deep sleep. + User data marked with RTC_NOINIT_ATTR will be placed + into this section. See the file "esp_attr.h" for more information. + The memory location of the data is dependent on + CONFIG_ESP32_RTCDATA_IN_FAST_MEM option. + */ + .rtc_noinit (NOLOAD): + { + . = ALIGN(4); + _rtc_noinit_start = ABSOLUTE(.); + *(.rtc_noinit .rtc_noinit.*) + . = ALIGN(4) ; + _rtc_noinit_end = ABSOLUTE(.); + } > rtc_data_location + + /* This section located in RTC SLOW Memory area. + It holds data marked with RTC_SLOW_ATTR attribute. + See the file "esp_attr.h" for more information. + */ + .rtc.force_slow : + { + . = ALIGN(4); + _rtc_force_slow_start = ABSOLUTE(.); + *(.rtc.force_slow .rtc.force_slow.*) + . = ALIGN(4) ; + _rtc_force_slow_end = ABSOLUTE(.); + } > rtc_slow_seg + + /* Get size of rtc slow data based on rtc_data_location alias */ + _rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location)) + ? (_rtc_force_slow_end - _rtc_data_start) + : (_rtc_force_slow_end - _rtc_force_slow_start); + + _rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location)) + ? (_rtc_force_fast_end - _rtc_fast_start) + : (_rtc_noinit_end - _rtc_fast_start); + + ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)), + "RTC_SLOW segment data does not fit.") + + ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)), + "RTC_FAST segment data does not fit.") + + /* Send .iram0 code to iram */ + .iram0.vectors : + { + _iram_start = ABSOLUTE(.); + /* Vectors go to IRAM */ + _init_start = ABSOLUTE(.); + /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ + . = 0x0; + KEEP(*(.WindowVectors.text)); + . = 0x180; + KEEP(*(.Level2InterruptVector.text)); + . = 0x1c0; + KEEP(*(.Level3InterruptVector.text)); + . = 0x200; + KEEP(*(.Level4InterruptVector.text)); + . = 0x240; + KEEP(*(.Level5InterruptVector.text)); + . = 0x280; + KEEP(*(.DebugExceptionVector.text)); + . = 0x2c0; + KEEP(*(.NMIExceptionVector.text)); + . = 0x300; + KEEP(*(.KernelExceptionVector.text)); + . = 0x340; + KEEP(*(.UserExceptionVector.text)); + . = 0x3C0; + KEEP(*(.DoubleExceptionVector.text)); + . = 0x400; + *(.*Vector.literal) + + *(.UserEnter.literal); + *(.UserEnter.text); + . = ALIGN (16); + *(.entry.text) + *(.init.literal) + *(.init) + _init_end = ABSOLUTE(.); + } > iram0_0_seg + + .iram0.text : + { + /* Code marked as runnning out of IRAM */ + _iram_text_start = ABSOLUTE(.); + + *( .iram1 .iram1.*) + *libspi_flash.a:spi_flash_rom_patch.*( .literal .literal.* .text .text.*) + *libesp_ringbuf.a:( .literal .literal.* .text .text.*) + *libhal.a:( .literal .literal.* .text .text.*) + *libapp_trace.a:( .literal .literal.* .text .text.*) + *libesp32.a:panic.*( .literal .literal.* .text .text.*) + *libespcoredump.a:core_dump_port.*( .literal .literal.* .text .text.*) + *libespcoredump.a:core_dump_common.*( .literal .literal.* .text .text.*) + *libespcoredump.a:core_dump_flash.*( .literal .literal.* .text .text.*) + *libespcoredump.a:core_dump_uart.*( .literal .literal.* .text .text.*) + *librtc.a:( .literal .literal.* .text .text.*) + *libgcc.a:lib2funcs.*( .literal .literal.* .text .text.*) + *libsoc.a:cpu_util.*( .literal .literal.* .text .text.*) + *libsoc.a:rtc_clk.*( .literal .literal.* .text .text.*) + *libsoc.a:rtc_init.*( .literal .literal.* .text .text.*) + *libsoc.a:rtc_periph.*( .literal .literal.* .text .text.*) + *libsoc.a:rtc_clk_init.*( .literal .literal.* .text .text.*) + *libsoc.a:rtc_wdt.*( .literal .literal.* .text .text.*) + *libsoc.a:rtc_sleep.*( .literal .literal.* .text .text.*) + *libsoc.a:rtc_pm.*( .literal .literal.* .text .text.*) + *libsoc.a:rtc_time.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strftime.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-timelocal.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strtoul.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strtol.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strlwr.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-gettzinfo.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strndup.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-tzset_r.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-atoi.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-isblank.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strlcpy.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-ispunct.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-impure.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-fflush.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-systimes.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-open.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-ctime_r.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-rand.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-lcltime_r.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strdup.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strsep.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-asctime_r.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-isdigit.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-utoa.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-memmove.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-toupper.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-memcmp.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strlen.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strcmp.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strnlen.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-toascii.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lock.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-wsetup.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-month_lengths.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-environ.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-memset.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strspn.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-memcpy.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-sf_nan.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-memchr.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strncat.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-longjmp.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strncasecmp.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-envlock.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-wctomb_r.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strcasecmp.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-memccpy.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-isprint.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-ungetc.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-rshift.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-syswrite.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-stdio.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-sbrk.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-tzcalc_limits.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-syssbrk.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strcat.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-fclose.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-sccl.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strdup_r.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strrchr.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-isascii.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-rand_r.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strupr.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-read.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-itoa.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-asctime.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-sysread.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-ctype_.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strtok_r.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-ldiv.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-atol.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-fputwc.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-system.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-setjmp.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-isgraph.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-wcrtomb.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-wbuf.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-fwalk.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-gmtime.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strptime.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strncpy.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strndup_r.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strlcat.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-getenv_r.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strstr.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-gmtime_r.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-quorem.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-s_fpclassify.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strcasestr.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strcpy.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-isalpha.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-lcltime.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-makebuf.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-time.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-refill.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-labs.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-isupper.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-bzero.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:isatty.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-findfp.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-fvwrite.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-mktime.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-sysclose.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-abs.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-raise.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-tzset.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-iscntrl.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-srand.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strcspn.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-ctime.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strchr.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-tolower.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strncmp.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-isalnum.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-tzlock.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-islower.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-isspace.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-tzvars.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-memrchr.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-close.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-div.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-strcoll.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:creat.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-sysopen.*( .literal .literal.* .text .text.*) + *libc-psram-workaround.a:lib_a-creat.*( .literal .literal.* .text .text.*) + *libpp.a:( .wifi0iram .wifi0iram.*) + *libfreertos.a:( .literal .literal.* .text .text.*) + *libgcov.a:( .literal .literal.* .text .text.*) + *libxtensa-debug-module.a:eri.*( .literal .literal.* .text .text.*) + *libheap.a:multi_heap_poisoning.*( .literal .literal.* .text .text.*) + *libheap.a:multi_heap.*( .literal .literal.* .text .text.*) + *libnet80211.a:( .wifi0iram .wifi0iram.*) + + _iram_text_end = ABSOLUTE(.); + _iram_end = ABSOLUTE(.); + } > iram0_0_seg + + ASSERT(((_iram_text_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), + "IRAM0 segment data does not fit.") + + .dram0.data : + { + _data_start = ABSOLUTE(.); + _bt_data_start = ABSOLUTE(.); + *libbt.a:(.data .data.*) + . = ALIGN (4); + _bt_data_end = ABSOLUTE(.); + _btdm_data_start = ABSOLUTE(.); + *libbtdm_app.a:(.data .data.*) + . = ALIGN (4); + _btdm_data_end = ABSOLUTE(.); + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.jcr) + + *( .data .data.* .dram1 .dram1.*) + *libapp_trace.a:( .rodata .rodata.*) + *libesp32.a:panic.*( .rodata .rodata.*) + *libphy.a:( .rodata .rodata.*) + *libsoc.a:rtc_clk.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strftime.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-timelocal.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strtoul.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strtol.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strlwr.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-gettzinfo.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strndup.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-tzset_r.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-atoi.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-isblank.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strlcpy.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-ispunct.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-impure.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-fflush.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-systimes.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-open.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-ctime_r.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-rand.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-lcltime_r.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strdup.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strsep.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-asctime_r.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-isdigit.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-utoa.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-memmove.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-toupper.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-memcmp.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strlen.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strcmp.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strnlen.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-toascii.*( .rodata .rodata.*) + *libc-psram-workaround.a:lock.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-wsetup.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-month_lengths.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-environ.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-memset.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strspn.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-memcpy.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-sf_nan.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-memchr.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strncat.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-longjmp.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strncasecmp.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-envlock.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-wctomb_r.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strcasecmp.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-memccpy.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-isprint.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-ungetc.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-rshift.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-syswrite.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-stdio.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-sbrk.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-tzcalc_limits.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-syssbrk.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strcat.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-fclose.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-sccl.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strdup_r.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strrchr.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-isascii.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-rand_r.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strupr.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-read.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-itoa.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-asctime.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-sysread.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-ctype_.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strtok_r.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-ldiv.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-atol.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-fputwc.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-system.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-setjmp.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-isgraph.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-wcrtomb.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-wbuf.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-fwalk.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-gmtime.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strptime.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strncpy.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strndup_r.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strlcat.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-getenv_r.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strstr.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-gmtime_r.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-quorem.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-s_fpclassify.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strcasestr.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strcpy.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-isalpha.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-lcltime.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-makebuf.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-time.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-refill.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-labs.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-isupper.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-bzero.*( .rodata .rodata.*) + *libc-psram-workaround.a:isatty.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-findfp.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-fvwrite.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-mktime.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-sysclose.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-abs.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-raise.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-tzset.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-iscntrl.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-srand.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strcspn.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-ctime.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strchr.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-tolower.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strncmp.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-isalnum.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-tzlock.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-islower.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-isspace.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-tzvars.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-memrchr.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-close.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-div.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-strcoll.*( .rodata .rodata.*) + *libc-psram-workaround.a:creat.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-sysopen.*( .rodata .rodata.*) + *libc-psram-workaround.a:lib_a-creat.*( .rodata .rodata.*) + *libgcov.a:( .rodata .rodata.*) + *libheap.a:multi_heap_poisoning.*( .rodata .rodata.*) + *libheap.a:multi_heap.*( .rodata .rodata.*) + + _data_end = ABSOLUTE(.); + . = ALIGN(4); + } > dram0_0_seg + + /*This section holds data that should not be initialized at power up. + The section located in Internal SRAM memory region. The macro _NOINIT + can be used as attribute to place data into this section. + See the esp_attr.h file for more information. + */ + .noinit (NOLOAD): + { + . = ALIGN(4); + _noinit_start = ABSOLUTE(.); + *(.noinit .noinit.*) + . = ALIGN(4) ; + _noinit_end = ABSOLUTE(.); + } > dram0_0_seg + + /* Shared RAM */ + .dram0.bss (NOLOAD) : + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); + *(.ext_ram.bss*) + _bt_bss_start = ABSOLUTE(.); + *libbt.a:(.bss .bss.* COMMON) + . = ALIGN (4); + _bt_bss_end = ABSOLUTE(.); + _btdm_bss_start = ABSOLUTE(.); + *libbtdm_app.a:(.bss .bss.* COMMON) + . = ALIGN (4); + _btdm_bss_end = ABSOLUTE(.); + + *( .bss .bss.* COMMON) + + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.share.mem) + *(.gnu.linkonce.b.*) + + . = ALIGN (8); + _bss_end = ABSOLUTE(.); + /* The heap starts right after end of this section */ + _heap_start = ABSOLUTE(.); + } > dram0_0_seg + + ASSERT(((_bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), + "DRAM segment data does not fit.") + + .flash.rodata : + { + _rodata_start = ABSOLUTE(.); + + *(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */ + *(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */ + + *(EXCLUDE_FILE(*libapp_trace.a *libesp32.a:panic.* *libphy.a *libsoc.a:rtc_clk.* *libc-psram-workaround.a:lib_a-creat.* *libc-psram-workaround.a:lib_a-sysopen.* *libc-psram-workaround.a:creat.* *libc-psram-workaround.a:lib_a-strcoll.* *libc-psram-workaround.a:lib_a-div.* *libc-psram-workaround.a:lib_a-close.* *libc-psram-workaround.a:lib_a-memrchr.* *libc-psram-workaround.a:lib_a-tzvars.* *libc-psram-workaround.a:lib_a-isspace.* *libc-psram-workaround.a:lib_a-islower.* *libc-psram-workaround.a:lib_a-tzlock.* *libc-psram-workaround.a:lib_a-isalnum.* *libc-psram-workaround.a:lib_a-strncmp.* *libc-psram-workaround.a:lib_a-tolower.* *libc-psram-workaround.a:lib_a-strchr.* *libc-psram-workaround.a:lib_a-ctime.* *libc-psram-workaround.a:lib_a-strcspn.* *libc-psram-workaround.a:lib_a-srand.* *libc-psram-workaround.a:lib_a-iscntrl.* *libc-psram-workaround.a:lib_a-tzset.* *libc-psram-workaround.a:lib_a-raise.* *libc-psram-workaround.a:lib_a-abs.* *libc-psram-workaround.a:lib_a-sysclose.* *libc-psram-workaround.a:lib_a-mktime.* *libc-psram-workaround.a:lib_a-fvwrite.* *libc-psram-workaround.a:lib_a-findfp.* *libc-psram-workaround.a:isatty.* *libc-psram-workaround.a:lib_a-bzero.* *libc-psram-workaround.a:lib_a-isupper.* *libc-psram-workaround.a:lib_a-labs.* *libc-psram-workaround.a:lib_a-refill.* *libc-psram-workaround.a:lib_a-time.* *libc-psram-workaround.a:lib_a-makebuf.* *libc-psram-workaround.a:lib_a-lcltime.* *libc-psram-workaround.a:lib_a-isalpha.* *libc-psram-workaround.a:lib_a-strcpy.* *libc-psram-workaround.a:lib_a-strcasestr.* *libc-psram-workaround.a:lib_a-s_fpclassify.* *libc-psram-workaround.a:lib_a-quorem.* *libc-psram-workaround.a:lib_a-gmtime_r.* *libc-psram-workaround.a:lib_a-strstr.* *libc-psram-workaround.a:lib_a-getenv_r.* *libc-psram-workaround.a:lib_a-strlcat.* *libc-psram-workaround.a:lib_a-strndup_r.* *libc-psram-workaround.a:lib_a-strncpy.* *libc-psram-workaround.a:lib_a-strptime.* *libc-psram-workaround.a:lib_a-gmtime.* *libc-psram-workaround.a:lib_a-fwalk.* *libc-psram-workaround.a:lib_a-wbuf.* *libc-psram-workaround.a:lib_a-wcrtomb.* *libc-psram-workaround.a:lib_a-isgraph.* *libc-psram-workaround.a:lib_a-setjmp.* *libc-psram-workaround.a:lib_a-system.* *libc-psram-workaround.a:lib_a-fputwc.* *libc-psram-workaround.a:lib_a-atol.* *libc-psram-workaround.a:lib_a-ldiv.* *libc-psram-workaround.a:lib_a-strtok_r.* *libc-psram-workaround.a:lib_a-ctype_.* *libc-psram-workaround.a:lib_a-sysread.* *libc-psram-workaround.a:lib_a-asctime.* *libc-psram-workaround.a:lib_a-itoa.* *libc-psram-workaround.a:lib_a-read.* *libc-psram-workaround.a:lib_a-strupr.* *libc-psram-workaround.a:lib_a-rand_r.* *libc-psram-workaround.a:lib_a-isascii.* *libc-psram-workaround.a:lib_a-strrchr.* *libc-psram-workaround.a:lib_a-strdup_r.* *libc-psram-workaround.a:lib_a-sccl.* *libc-psram-workaround.a:lib_a-fclose.* *libc-psram-workaround.a:lib_a-strcat.* *libc-psram-workaround.a:lib_a-syssbrk.* *libc-psram-workaround.a:lib_a-tzcalc_limits.* *libc-psram-workaround.a:lib_a-sbrk.* *libc-psram-workaround.a:lib_a-stdio.* *libc-psram-workaround.a:lib_a-syswrite.* *libc-psram-workaround.a:lib_a-rshift.* *libc-psram-workaround.a:lib_a-ungetc.* *libc-psram-workaround.a:lib_a-isprint.* *libc-psram-workaround.a:lib_a-memccpy.* *libc-psram-workaround.a:lib_a-strcasecmp.* *libc-psram-workaround.a:lib_a-wctomb_r.* *libc-psram-workaround.a:lib_a-envlock.* *libc-psram-workaround.a:lib_a-strncasecmp.* *libc-psram-workaround.a:lib_a-longjmp.* *libc-psram-workaround.a:lib_a-strncat.* *libc-psram-workaround.a:lib_a-memchr.* *libc-psram-workaround.a:lib_a-sf_nan.* *libc-psram-workaround.a:lib_a-memcpy.* *libc-psram-workaround.a:lib_a-strspn.* *libc-psram-workaround.a:lib_a-memset.* *libc-psram-workaround.a:lib_a-environ.* *libc-psram-workaround.a:lib_a-month_lengths.* *libc-psram-workaround.a:lib_a-wsetup.* *libc-psram-workaround.a:lock.* *libc-psram-workaround.a:lib_a-toascii.* *libc-psram-workaround.a:lib_a-strnlen.* *libc-psram-workaround.a:lib_a-strcmp.* *libc-psram-workaround.a:lib_a-strlen.* *libc-psram-workaround.a:lib_a-memcmp.* *libc-psram-workaround.a:lib_a-toupper.* *libc-psram-workaround.a:lib_a-memmove.* *libc-psram-workaround.a:lib_a-utoa.* *libc-psram-workaround.a:lib_a-isdigit.* *libc-psram-workaround.a:lib_a-asctime_r.* *libc-psram-workaround.a:lib_a-strsep.* *libc-psram-workaround.a:lib_a-strdup.* *libc-psram-workaround.a:lib_a-lcltime_r.* *libc-psram-workaround.a:lib_a-rand.* *libc-psram-workaround.a:lib_a-ctime_r.* *libc-psram-workaround.a:lib_a-open.* *libc-psram-workaround.a:lib_a-systimes.* *libc-psram-workaround.a:lib_a-fflush.* *libc-psram-workaround.a:lib_a-impure.* *libc-psram-workaround.a:lib_a-ispunct.* *libc-psram-workaround.a:lib_a-strlcpy.* *libc-psram-workaround.a:lib_a-isblank.* *libc-psram-workaround.a:lib_a-atoi.* *libc-psram-workaround.a:lib_a-tzset_r.* *libc-psram-workaround.a:lib_a-strndup.* *libc-psram-workaround.a:lib_a-gettzinfo.* *libc-psram-workaround.a:lib_a-strlwr.* *libc-psram-workaround.a:lib_a-strtol.* *libc-psram-workaround.a:lib_a-strtoul.* *libc-psram-workaround.a:lib_a-timelocal.* *libc-psram-workaround.a:lib_a-strftime.* *libgcov.a *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.*) .rodata EXCLUDE_FILE(*libapp_trace.a *libesp32.a:panic.* *libphy.a *libsoc.a:rtc_clk.* *libc-psram-workaround.a:lib_a-creat.* *libc-psram-workaround.a:lib_a-sysopen.* *libc-psram-workaround.a:creat.* *libc-psram-workaround.a:lib_a-strcoll.* *libc-psram-workaround.a:lib_a-div.* *libc-psram-workaround.a:lib_a-close.* *libc-psram-workaround.a:lib_a-memrchr.* *libc-psram-workaround.a:lib_a-tzvars.* *libc-psram-workaround.a:lib_a-isspace.* *libc-psram-workaround.a:lib_a-islower.* *libc-psram-workaround.a:lib_a-tzlock.* *libc-psram-workaround.a:lib_a-isalnum.* *libc-psram-workaround.a:lib_a-strncmp.* *libc-psram-workaround.a:lib_a-tolower.* *libc-psram-workaround.a:lib_a-strchr.* *libc-psram-workaround.a:lib_a-ctime.* *libc-psram-workaround.a:lib_a-strcspn.* *libc-psram-workaround.a:lib_a-srand.* *libc-psram-workaround.a:lib_a-iscntrl.* *libc-psram-workaround.a:lib_a-tzset.* *libc-psram-workaround.a:lib_a-raise.* *libc-psram-workaround.a:lib_a-abs.* *libc-psram-workaround.a:lib_a-sysclose.* *libc-psram-workaround.a:lib_a-mktime.* *libc-psram-workaround.a:lib_a-fvwrite.* *libc-psram-workaround.a:lib_a-findfp.* *libc-psram-workaround.a:isatty.* *libc-psram-workaround.a:lib_a-bzero.* *libc-psram-workaround.a:lib_a-isupper.* *libc-psram-workaround.a:lib_a-labs.* *libc-psram-workaround.a:lib_a-refill.* *libc-psram-workaround.a:lib_a-time.* *libc-psram-workaround.a:lib_a-makebuf.* *libc-psram-workaround.a:lib_a-lcltime.* *libc-psram-workaround.a:lib_a-isalpha.* *libc-psram-workaround.a:lib_a-strcpy.* *libc-psram-workaround.a:lib_a-strcasestr.* *libc-psram-workaround.a:lib_a-s_fpclassify.* *libc-psram-workaround.a:lib_a-quorem.* *libc-psram-workaround.a:lib_a-gmtime_r.* *libc-psram-workaround.a:lib_a-strstr.* *libc-psram-workaround.a:lib_a-getenv_r.* *libc-psram-workaround.a:lib_a-strlcat.* *libc-psram-workaround.a:lib_a-strndup_r.* *libc-psram-workaround.a:lib_a-strncpy.* *libc-psram-workaround.a:lib_a-strptime.* *libc-psram-workaround.a:lib_a-gmtime.* *libc-psram-workaround.a:lib_a-fwalk.* *libc-psram-workaround.a:lib_a-wbuf.* *libc-psram-workaround.a:lib_a-wcrtomb.* *libc-psram-workaround.a:lib_a-isgraph.* *libc-psram-workaround.a:lib_a-setjmp.* *libc-psram-workaround.a:lib_a-system.* *libc-psram-workaround.a:lib_a-fputwc.* *libc-psram-workaround.a:lib_a-atol.* *libc-psram-workaround.a:lib_a-ldiv.* *libc-psram-workaround.a:lib_a-strtok_r.* *libc-psram-workaround.a:lib_a-ctype_.* *libc-psram-workaround.a:lib_a-sysread.* *libc-psram-workaround.a:lib_a-asctime.* *libc-psram-workaround.a:lib_a-itoa.* *libc-psram-workaround.a:lib_a-read.* *libc-psram-workaround.a:lib_a-strupr.* *libc-psram-workaround.a:lib_a-rand_r.* *libc-psram-workaround.a:lib_a-isascii.* *libc-psram-workaround.a:lib_a-strrchr.* *libc-psram-workaround.a:lib_a-strdup_r.* *libc-psram-workaround.a:lib_a-sccl.* *libc-psram-workaround.a:lib_a-fclose.* *libc-psram-workaround.a:lib_a-strcat.* *libc-psram-workaround.a:lib_a-syssbrk.* *libc-psram-workaround.a:lib_a-tzcalc_limits.* *libc-psram-workaround.a:lib_a-sbrk.* *libc-psram-workaround.a:lib_a-stdio.* *libc-psram-workaround.a:lib_a-syswrite.* *libc-psram-workaround.a:lib_a-rshift.* *libc-psram-workaround.a:lib_a-ungetc.* *libc-psram-workaround.a:lib_a-isprint.* *libc-psram-workaround.a:lib_a-memccpy.* *libc-psram-workaround.a:lib_a-strcasecmp.* *libc-psram-workaround.a:lib_a-wctomb_r.* *libc-psram-workaround.a:lib_a-envlock.* *libc-psram-workaround.a:lib_a-strncasecmp.* *libc-psram-workaround.a:lib_a-longjmp.* *libc-psram-workaround.a:lib_a-strncat.* *libc-psram-workaround.a:lib_a-memchr.* *libc-psram-workaround.a:lib_a-sf_nan.* *libc-psram-workaround.a:lib_a-memcpy.* *libc-psram-workaround.a:lib_a-strspn.* *libc-psram-workaround.a:lib_a-memset.* *libc-psram-workaround.a:lib_a-environ.* *libc-psram-workaround.a:lib_a-month_lengths.* *libc-psram-workaround.a:lib_a-wsetup.* *libc-psram-workaround.a:lock.* *libc-psram-workaround.a:lib_a-toascii.* *libc-psram-workaround.a:lib_a-strnlen.* *libc-psram-workaround.a:lib_a-strcmp.* *libc-psram-workaround.a:lib_a-strlen.* *libc-psram-workaround.a:lib_a-memcmp.* *libc-psram-workaround.a:lib_a-toupper.* *libc-psram-workaround.a:lib_a-memmove.* *libc-psram-workaround.a:lib_a-utoa.* *libc-psram-workaround.a:lib_a-isdigit.* *libc-psram-workaround.a:lib_a-asctime_r.* *libc-psram-workaround.a:lib_a-strsep.* *libc-psram-workaround.a:lib_a-strdup.* *libc-psram-workaround.a:lib_a-lcltime_r.* *libc-psram-workaround.a:lib_a-rand.* *libc-psram-workaround.a:lib_a-ctime_r.* *libc-psram-workaround.a:lib_a-open.* *libc-psram-workaround.a:lib_a-systimes.* *libc-psram-workaround.a:lib_a-fflush.* *libc-psram-workaround.a:lib_a-impure.* *libc-psram-workaround.a:lib_a-ispunct.* *libc-psram-workaround.a:lib_a-strlcpy.* *libc-psram-workaround.a:lib_a-isblank.* *libc-psram-workaround.a:lib_a-atoi.* *libc-psram-workaround.a:lib_a-tzset_r.* *libc-psram-workaround.a:lib_a-strndup.* *libc-psram-workaround.a:lib_a-gettzinfo.* *libc-psram-workaround.a:lib_a-strlwr.* *libc-psram-workaround.a:lib_a-strtol.* *libc-psram-workaround.a:lib_a-strtoul.* *libc-psram-workaround.a:lib_a-timelocal.* *libc-psram-workaround.a:lib_a-strftime.* *libgcov.a *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.*) .rodata.*) + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + /* C++ constructor and destructor tables, properly ordered: */ + __init_array_start = ABSOLUTE(.); + KEEP (*crtbegin.*(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __init_array_end = ABSOLUTE(.); + KEEP (*crtbegin.*(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + /* Addresses of memory regions reserved via + SOC_RESERVE_MEMORY_REGION() */ + soc_reserved_memory_region_start = ABSOLUTE(.); + KEEP (*(.reserved_memory_address)) + soc_reserved_memory_region_end = ABSOLUTE(.); + _rodata_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + _thread_local_start = ABSOLUTE(.); + *(.tdata) + *(.tdata.*) + *(.tbss) + *(.tbss.*) + _thread_local_end = ABSOLUTE(.); + . = ALIGN(4); + } >drom0_0_seg + + .flash.text : + { + _stext = .; + _text_start = ABSOLUTE(.); + + *(EXCLUDE_FILE(*libspi_flash.a:spi_flash_rom_patch.* *libesp_ringbuf.a *libhal.a *libapp_trace.a *libesp32.a:panic.* *libespcoredump.a:core_dump_uart.* *libespcoredump.a:core_dump_flash.* *libespcoredump.a:core_dump_common.* *libespcoredump.a:core_dump_port.* *librtc.a *libgcc.a:lib2funcs.* *libsoc.a:rtc_time.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_clk_init.* *libsoc.a:rtc_periph.* *libsoc.a:rtc_init.* *libsoc.a:rtc_clk.* *libsoc.a:cpu_util.* *libc-psram-workaround.a:lib_a-creat.* *libc-psram-workaround.a:lib_a-sysopen.* *libc-psram-workaround.a:creat.* *libc-psram-workaround.a:lib_a-strcoll.* *libc-psram-workaround.a:lib_a-div.* *libc-psram-workaround.a:lib_a-close.* *libc-psram-workaround.a:lib_a-memrchr.* *libc-psram-workaround.a:lib_a-tzvars.* *libc-psram-workaround.a:lib_a-isspace.* *libc-psram-workaround.a:lib_a-islower.* *libc-psram-workaround.a:lib_a-tzlock.* *libc-psram-workaround.a:lib_a-isalnum.* *libc-psram-workaround.a:lib_a-strncmp.* *libc-psram-workaround.a:lib_a-tolower.* *libc-psram-workaround.a:lib_a-strchr.* *libc-psram-workaround.a:lib_a-ctime.* *libc-psram-workaround.a:lib_a-strcspn.* *libc-psram-workaround.a:lib_a-srand.* *libc-psram-workaround.a:lib_a-iscntrl.* *libc-psram-workaround.a:lib_a-tzset.* *libc-psram-workaround.a:lib_a-raise.* *libc-psram-workaround.a:lib_a-abs.* *libc-psram-workaround.a:lib_a-sysclose.* *libc-psram-workaround.a:lib_a-mktime.* *libc-psram-workaround.a:lib_a-fvwrite.* *libc-psram-workaround.a:lib_a-findfp.* *libc-psram-workaround.a:isatty.* *libc-psram-workaround.a:lib_a-bzero.* *libc-psram-workaround.a:lib_a-isupper.* *libc-psram-workaround.a:lib_a-labs.* *libc-psram-workaround.a:lib_a-refill.* *libc-psram-workaround.a:lib_a-time.* *libc-psram-workaround.a:lib_a-makebuf.* *libc-psram-workaround.a:lib_a-lcltime.* *libc-psram-workaround.a:lib_a-isalpha.* *libc-psram-workaround.a:lib_a-strcpy.* *libc-psram-workaround.a:lib_a-strcasestr.* *libc-psram-workaround.a:lib_a-s_fpclassify.* *libc-psram-workaround.a:lib_a-quorem.* *libc-psram-workaround.a:lib_a-gmtime_r.* *libc-psram-workaround.a:lib_a-strstr.* *libc-psram-workaround.a:lib_a-getenv_r.* *libc-psram-workaround.a:lib_a-strlcat.* *libc-psram-workaround.a:lib_a-strndup_r.* *libc-psram-workaround.a:lib_a-strncpy.* *libc-psram-workaround.a:lib_a-strptime.* *libc-psram-workaround.a:lib_a-gmtime.* *libc-psram-workaround.a:lib_a-fwalk.* *libc-psram-workaround.a:lib_a-wbuf.* *libc-psram-workaround.a:lib_a-wcrtomb.* *libc-psram-workaround.a:lib_a-isgraph.* *libc-psram-workaround.a:lib_a-setjmp.* *libc-psram-workaround.a:lib_a-system.* *libc-psram-workaround.a:lib_a-fputwc.* *libc-psram-workaround.a:lib_a-atol.* *libc-psram-workaround.a:lib_a-ldiv.* *libc-psram-workaround.a:lib_a-strtok_r.* *libc-psram-workaround.a:lib_a-ctype_.* *libc-psram-workaround.a:lib_a-sysread.* *libc-psram-workaround.a:lib_a-asctime.* *libc-psram-workaround.a:lib_a-itoa.* *libc-psram-workaround.a:lib_a-read.* *libc-psram-workaround.a:lib_a-strupr.* *libc-psram-workaround.a:lib_a-rand_r.* *libc-psram-workaround.a:lib_a-isascii.* *libc-psram-workaround.a:lib_a-strrchr.* *libc-psram-workaround.a:lib_a-strdup_r.* *libc-psram-workaround.a:lib_a-sccl.* *libc-psram-workaround.a:lib_a-fclose.* *libc-psram-workaround.a:lib_a-strcat.* *libc-psram-workaround.a:lib_a-syssbrk.* *libc-psram-workaround.a:lib_a-tzcalc_limits.* *libc-psram-workaround.a:lib_a-sbrk.* *libc-psram-workaround.a:lib_a-stdio.* *libc-psram-workaround.a:lib_a-syswrite.* *libc-psram-workaround.a:lib_a-rshift.* *libc-psram-workaround.a:lib_a-ungetc.* *libc-psram-workaround.a:lib_a-isprint.* *libc-psram-workaround.a:lib_a-memccpy.* *libc-psram-workaround.a:lib_a-strcasecmp.* *libc-psram-workaround.a:lib_a-wctomb_r.* *libc-psram-workaround.a:lib_a-envlock.* *libc-psram-workaround.a:lib_a-strncasecmp.* *libc-psram-workaround.a:lib_a-longjmp.* *libc-psram-workaround.a:lib_a-strncat.* *libc-psram-workaround.a:lib_a-memchr.* *libc-psram-workaround.a:lib_a-sf_nan.* *libc-psram-workaround.a:lib_a-memcpy.* *libc-psram-workaround.a:lib_a-strspn.* *libc-psram-workaround.a:lib_a-memset.* *libc-psram-workaround.a:lib_a-environ.* *libc-psram-workaround.a:lib_a-month_lengths.* *libc-psram-workaround.a:lib_a-wsetup.* *libc-psram-workaround.a:lock.* *libc-psram-workaround.a:lib_a-toascii.* *libc-psram-workaround.a:lib_a-strnlen.* *libc-psram-workaround.a:lib_a-strcmp.* *libc-psram-workaround.a:lib_a-strlen.* *libc-psram-workaround.a:lib_a-memcmp.* *libc-psram-workaround.a:lib_a-toupper.* *libc-psram-workaround.a:lib_a-memmove.* *libc-psram-workaround.a:lib_a-utoa.* *libc-psram-workaround.a:lib_a-isdigit.* *libc-psram-workaround.a:lib_a-asctime_r.* *libc-psram-workaround.a:lib_a-strsep.* *libc-psram-workaround.a:lib_a-strdup.* *libc-psram-workaround.a:lib_a-lcltime_r.* *libc-psram-workaround.a:lib_a-rand.* *libc-psram-workaround.a:lib_a-ctime_r.* *libc-psram-workaround.a:lib_a-open.* *libc-psram-workaround.a:lib_a-systimes.* *libc-psram-workaround.a:lib_a-fflush.* *libc-psram-workaround.a:lib_a-impure.* *libc-psram-workaround.a:lib_a-ispunct.* *libc-psram-workaround.a:lib_a-strlcpy.* *libc-psram-workaround.a:lib_a-isblank.* *libc-psram-workaround.a:lib_a-atoi.* *libc-psram-workaround.a:lib_a-tzset_r.* *libc-psram-workaround.a:lib_a-strndup.* *libc-psram-workaround.a:lib_a-gettzinfo.* *libc-psram-workaround.a:lib_a-strlwr.* *libc-psram-workaround.a:lib_a-strtol.* *libc-psram-workaround.a:lib_a-strtoul.* *libc-psram-workaround.a:lib_a-timelocal.* *libc-psram-workaround.a:lib_a-strftime.* *libfreertos.a *libgcov.a *libxtensa-debug-module.a:eri.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.*) .literal EXCLUDE_FILE(*libspi_flash.a:spi_flash_rom_patch.* *libesp_ringbuf.a *libhal.a *libapp_trace.a *libesp32.a:panic.* *libespcoredump.a:core_dump_uart.* *libespcoredump.a:core_dump_flash.* *libespcoredump.a:core_dump_common.* *libespcoredump.a:core_dump_port.* *librtc.a *libgcc.a:lib2funcs.* *libsoc.a:rtc_time.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_clk_init.* *libsoc.a:rtc_periph.* *libsoc.a:rtc_init.* *libsoc.a:rtc_clk.* *libsoc.a:cpu_util.* *libc-psram-workaround.a:lib_a-creat.* *libc-psram-workaround.a:lib_a-sysopen.* *libc-psram-workaround.a:creat.* *libc-psram-workaround.a:lib_a-strcoll.* *libc-psram-workaround.a:lib_a-div.* *libc-psram-workaround.a:lib_a-close.* *libc-psram-workaround.a:lib_a-memrchr.* *libc-psram-workaround.a:lib_a-tzvars.* *libc-psram-workaround.a:lib_a-isspace.* *libc-psram-workaround.a:lib_a-islower.* *libc-psram-workaround.a:lib_a-tzlock.* *libc-psram-workaround.a:lib_a-isalnum.* *libc-psram-workaround.a:lib_a-strncmp.* *libc-psram-workaround.a:lib_a-tolower.* *libc-psram-workaround.a:lib_a-strchr.* *libc-psram-workaround.a:lib_a-ctime.* *libc-psram-workaround.a:lib_a-strcspn.* *libc-psram-workaround.a:lib_a-srand.* *libc-psram-workaround.a:lib_a-iscntrl.* *libc-psram-workaround.a:lib_a-tzset.* *libc-psram-workaround.a:lib_a-raise.* *libc-psram-workaround.a:lib_a-abs.* *libc-psram-workaround.a:lib_a-sysclose.* *libc-psram-workaround.a:lib_a-mktime.* *libc-psram-workaround.a:lib_a-fvwrite.* *libc-psram-workaround.a:lib_a-findfp.* *libc-psram-workaround.a:isatty.* *libc-psram-workaround.a:lib_a-bzero.* *libc-psram-workaround.a:lib_a-isupper.* *libc-psram-workaround.a:lib_a-labs.* *libc-psram-workaround.a:lib_a-refill.* *libc-psram-workaround.a:lib_a-time.* *libc-psram-workaround.a:lib_a-makebuf.* *libc-psram-workaround.a:lib_a-lcltime.* *libc-psram-workaround.a:lib_a-isalpha.* *libc-psram-workaround.a:lib_a-strcpy.* *libc-psram-workaround.a:lib_a-strcasestr.* *libc-psram-workaround.a:lib_a-s_fpclassify.* *libc-psram-workaround.a:lib_a-quorem.* *libc-psram-workaround.a:lib_a-gmtime_r.* *libc-psram-workaround.a:lib_a-strstr.* *libc-psram-workaround.a:lib_a-getenv_r.* *libc-psram-workaround.a:lib_a-strlcat.* *libc-psram-workaround.a:lib_a-strndup_r.* *libc-psram-workaround.a:lib_a-strncpy.* *libc-psram-workaround.a:lib_a-strptime.* *libc-psram-workaround.a:lib_a-gmtime.* *libc-psram-workaround.a:lib_a-fwalk.* *libc-psram-workaround.a:lib_a-wbuf.* *libc-psram-workaround.a:lib_a-wcrtomb.* *libc-psram-workaround.a:lib_a-isgraph.* *libc-psram-workaround.a:lib_a-setjmp.* *libc-psram-workaround.a:lib_a-system.* *libc-psram-workaround.a:lib_a-fputwc.* *libc-psram-workaround.a:lib_a-atol.* *libc-psram-workaround.a:lib_a-ldiv.* *libc-psram-workaround.a:lib_a-strtok_r.* *libc-psram-workaround.a:lib_a-ctype_.* *libc-psram-workaround.a:lib_a-sysread.* *libc-psram-workaround.a:lib_a-asctime.* *libc-psram-workaround.a:lib_a-itoa.* *libc-psram-workaround.a:lib_a-read.* *libc-psram-workaround.a:lib_a-strupr.* *libc-psram-workaround.a:lib_a-rand_r.* *libc-psram-workaround.a:lib_a-isascii.* *libc-psram-workaround.a:lib_a-strrchr.* *libc-psram-workaround.a:lib_a-strdup_r.* *libc-psram-workaround.a:lib_a-sccl.* *libc-psram-workaround.a:lib_a-fclose.* *libc-psram-workaround.a:lib_a-strcat.* *libc-psram-workaround.a:lib_a-syssbrk.* *libc-psram-workaround.a:lib_a-tzcalc_limits.* *libc-psram-workaround.a:lib_a-sbrk.* *libc-psram-workaround.a:lib_a-stdio.* *libc-psram-workaround.a:lib_a-syswrite.* *libc-psram-workaround.a:lib_a-rshift.* *libc-psram-workaround.a:lib_a-ungetc.* *libc-psram-workaround.a:lib_a-isprint.* *libc-psram-workaround.a:lib_a-memccpy.* *libc-psram-workaround.a:lib_a-strcasecmp.* *libc-psram-workaround.a:lib_a-wctomb_r.* *libc-psram-workaround.a:lib_a-envlock.* *libc-psram-workaround.a:lib_a-strncasecmp.* *libc-psram-workaround.a:lib_a-longjmp.* *libc-psram-workaround.a:lib_a-strncat.* *libc-psram-workaround.a:lib_a-memchr.* *libc-psram-workaround.a:lib_a-sf_nan.* *libc-psram-workaround.a:lib_a-memcpy.* *libc-psram-workaround.a:lib_a-strspn.* *libc-psram-workaround.a:lib_a-memset.* *libc-psram-workaround.a:lib_a-environ.* *libc-psram-workaround.a:lib_a-month_lengths.* *libc-psram-workaround.a:lib_a-wsetup.* *libc-psram-workaround.a:lock.* *libc-psram-workaround.a:lib_a-toascii.* *libc-psram-workaround.a:lib_a-strnlen.* *libc-psram-workaround.a:lib_a-strcmp.* *libc-psram-workaround.a:lib_a-strlen.* *libc-psram-workaround.a:lib_a-memcmp.* *libc-psram-workaround.a:lib_a-toupper.* *libc-psram-workaround.a:lib_a-memmove.* *libc-psram-workaround.a:lib_a-utoa.* *libc-psram-workaround.a:lib_a-isdigit.* *libc-psram-workaround.a:lib_a-asctime_r.* *libc-psram-workaround.a:lib_a-strsep.* *libc-psram-workaround.a:lib_a-strdup.* *libc-psram-workaround.a:lib_a-lcltime_r.* *libc-psram-workaround.a:lib_a-rand.* *libc-psram-workaround.a:lib_a-ctime_r.* *libc-psram-workaround.a:lib_a-open.* *libc-psram-workaround.a:lib_a-systimes.* *libc-psram-workaround.a:lib_a-fflush.* *libc-psram-workaround.a:lib_a-impure.* *libc-psram-workaround.a:lib_a-ispunct.* *libc-psram-workaround.a:lib_a-strlcpy.* *libc-psram-workaround.a:lib_a-isblank.* *libc-psram-workaround.a:lib_a-atoi.* *libc-psram-workaround.a:lib_a-tzset_r.* *libc-psram-workaround.a:lib_a-strndup.* *libc-psram-workaround.a:lib_a-gettzinfo.* *libc-psram-workaround.a:lib_a-strlwr.* *libc-psram-workaround.a:lib_a-strtol.* *libc-psram-workaround.a:lib_a-strtoul.* *libc-psram-workaround.a:lib_a-timelocal.* *libc-psram-workaround.a:lib_a-strftime.* *libfreertos.a *libgcov.a *libxtensa-debug-module.a:eri.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.*) .literal.* EXCLUDE_FILE(*libspi_flash.a:spi_flash_rom_patch.* *libesp_ringbuf.a *libhal.a *libapp_trace.a *libesp32.a:panic.* *libespcoredump.a:core_dump_uart.* *libespcoredump.a:core_dump_flash.* *libespcoredump.a:core_dump_common.* *libespcoredump.a:core_dump_port.* *librtc.a *libgcc.a:lib2funcs.* *libsoc.a:rtc_time.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_clk_init.* *libsoc.a:rtc_periph.* *libsoc.a:rtc_init.* *libsoc.a:rtc_clk.* *libsoc.a:cpu_util.* *libc-psram-workaround.a:lib_a-creat.* *libc-psram-workaround.a:lib_a-sysopen.* *libc-psram-workaround.a:creat.* *libc-psram-workaround.a:lib_a-strcoll.* *libc-psram-workaround.a:lib_a-div.* *libc-psram-workaround.a:lib_a-close.* *libc-psram-workaround.a:lib_a-memrchr.* *libc-psram-workaround.a:lib_a-tzvars.* *libc-psram-workaround.a:lib_a-isspace.* *libc-psram-workaround.a:lib_a-islower.* *libc-psram-workaround.a:lib_a-tzlock.* *libc-psram-workaround.a:lib_a-isalnum.* *libc-psram-workaround.a:lib_a-strncmp.* *libc-psram-workaround.a:lib_a-tolower.* *libc-psram-workaround.a:lib_a-strchr.* *libc-psram-workaround.a:lib_a-ctime.* *libc-psram-workaround.a:lib_a-strcspn.* *libc-psram-workaround.a:lib_a-srand.* *libc-psram-workaround.a:lib_a-iscntrl.* *libc-psram-workaround.a:lib_a-tzset.* *libc-psram-workaround.a:lib_a-raise.* *libc-psram-workaround.a:lib_a-abs.* *libc-psram-workaround.a:lib_a-sysclose.* *libc-psram-workaround.a:lib_a-mktime.* *libc-psram-workaround.a:lib_a-fvwrite.* *libc-psram-workaround.a:lib_a-findfp.* *libc-psram-workaround.a:isatty.* *libc-psram-workaround.a:lib_a-bzero.* *libc-psram-workaround.a:lib_a-isupper.* *libc-psram-workaround.a:lib_a-labs.* *libc-psram-workaround.a:lib_a-refill.* *libc-psram-workaround.a:lib_a-time.* *libc-psram-workaround.a:lib_a-makebuf.* *libc-psram-workaround.a:lib_a-lcltime.* *libc-psram-workaround.a:lib_a-isalpha.* *libc-psram-workaround.a:lib_a-strcpy.* *libc-psram-workaround.a:lib_a-strcasestr.* *libc-psram-workaround.a:lib_a-s_fpclassify.* *libc-psram-workaround.a:lib_a-quorem.* *libc-psram-workaround.a:lib_a-gmtime_r.* *libc-psram-workaround.a:lib_a-strstr.* *libc-psram-workaround.a:lib_a-getenv_r.* *libc-psram-workaround.a:lib_a-strlcat.* *libc-psram-workaround.a:lib_a-strndup_r.* *libc-psram-workaround.a:lib_a-strncpy.* *libc-psram-workaround.a:lib_a-strptime.* *libc-psram-workaround.a:lib_a-gmtime.* *libc-psram-workaround.a:lib_a-fwalk.* *libc-psram-workaround.a:lib_a-wbuf.* *libc-psram-workaround.a:lib_a-wcrtomb.* *libc-psram-workaround.a:lib_a-isgraph.* *libc-psram-workaround.a:lib_a-setjmp.* *libc-psram-workaround.a:lib_a-system.* *libc-psram-workaround.a:lib_a-fputwc.* *libc-psram-workaround.a:lib_a-atol.* *libc-psram-workaround.a:lib_a-ldiv.* *libc-psram-workaround.a:lib_a-strtok_r.* *libc-psram-workaround.a:lib_a-ctype_.* *libc-psram-workaround.a:lib_a-sysread.* *libc-psram-workaround.a:lib_a-asctime.* *libc-psram-workaround.a:lib_a-itoa.* *libc-psram-workaround.a:lib_a-read.* *libc-psram-workaround.a:lib_a-strupr.* *libc-psram-workaround.a:lib_a-rand_r.* *libc-psram-workaround.a:lib_a-isascii.* *libc-psram-workaround.a:lib_a-strrchr.* *libc-psram-workaround.a:lib_a-strdup_r.* *libc-psram-workaround.a:lib_a-sccl.* *libc-psram-workaround.a:lib_a-fclose.* *libc-psram-workaround.a:lib_a-strcat.* *libc-psram-workaround.a:lib_a-syssbrk.* *libc-psram-workaround.a:lib_a-tzcalc_limits.* *libc-psram-workaround.a:lib_a-sbrk.* *libc-psram-workaround.a:lib_a-stdio.* *libc-psram-workaround.a:lib_a-syswrite.* *libc-psram-workaround.a:lib_a-rshift.* *libc-psram-workaround.a:lib_a-ungetc.* *libc-psram-workaround.a:lib_a-isprint.* *libc-psram-workaround.a:lib_a-memccpy.* *libc-psram-workaround.a:lib_a-strcasecmp.* *libc-psram-workaround.a:lib_a-wctomb_r.* *libc-psram-workaround.a:lib_a-envlock.* *libc-psram-workaround.a:lib_a-strncasecmp.* *libc-psram-workaround.a:lib_a-longjmp.* *libc-psram-workaround.a:lib_a-strncat.* *libc-psram-workaround.a:lib_a-memchr.* *libc-psram-workaround.a:lib_a-sf_nan.* *libc-psram-workaround.a:lib_a-memcpy.* *libc-psram-workaround.a:lib_a-strspn.* *libc-psram-workaround.a:lib_a-memset.* *libc-psram-workaround.a:lib_a-environ.* *libc-psram-workaround.a:lib_a-month_lengths.* *libc-psram-workaround.a:lib_a-wsetup.* *libc-psram-workaround.a:lock.* *libc-psram-workaround.a:lib_a-toascii.* *libc-psram-workaround.a:lib_a-strnlen.* *libc-psram-workaround.a:lib_a-strcmp.* *libc-psram-workaround.a:lib_a-strlen.* *libc-psram-workaround.a:lib_a-memcmp.* *libc-psram-workaround.a:lib_a-toupper.* *libc-psram-workaround.a:lib_a-memmove.* *libc-psram-workaround.a:lib_a-utoa.* *libc-psram-workaround.a:lib_a-isdigit.* *libc-psram-workaround.a:lib_a-asctime_r.* *libc-psram-workaround.a:lib_a-strsep.* *libc-psram-workaround.a:lib_a-strdup.* *libc-psram-workaround.a:lib_a-lcltime_r.* *libc-psram-workaround.a:lib_a-rand.* *libc-psram-workaround.a:lib_a-ctime_r.* *libc-psram-workaround.a:lib_a-open.* *libc-psram-workaround.a:lib_a-systimes.* *libc-psram-workaround.a:lib_a-fflush.* *libc-psram-workaround.a:lib_a-impure.* *libc-psram-workaround.a:lib_a-ispunct.* *libc-psram-workaround.a:lib_a-strlcpy.* *libc-psram-workaround.a:lib_a-isblank.* *libc-psram-workaround.a:lib_a-atoi.* *libc-psram-workaround.a:lib_a-tzset_r.* *libc-psram-workaround.a:lib_a-strndup.* *libc-psram-workaround.a:lib_a-gettzinfo.* *libc-psram-workaround.a:lib_a-strlwr.* *libc-psram-workaround.a:lib_a-strtol.* *libc-psram-workaround.a:lib_a-strtoul.* *libc-psram-workaround.a:lib_a-timelocal.* *libc-psram-workaround.a:lib_a-strftime.* *libfreertos.a *libgcov.a *libxtensa-debug-module.a:eri.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.*) .text EXCLUDE_FILE(*libspi_flash.a:spi_flash_rom_patch.* *libesp_ringbuf.a *libhal.a *libapp_trace.a *libesp32.a:panic.* *libespcoredump.a:core_dump_uart.* *libespcoredump.a:core_dump_flash.* *libespcoredump.a:core_dump_common.* *libespcoredump.a:core_dump_port.* *librtc.a *libgcc.a:lib2funcs.* *libsoc.a:rtc_time.* *libsoc.a:rtc_pm.* *libsoc.a:rtc_sleep.* *libsoc.a:rtc_wdt.* *libsoc.a:rtc_clk_init.* *libsoc.a:rtc_periph.* *libsoc.a:rtc_init.* *libsoc.a:rtc_clk.* *libsoc.a:cpu_util.* *libc-psram-workaround.a:lib_a-creat.* *libc-psram-workaround.a:lib_a-sysopen.* *libc-psram-workaround.a:creat.* *libc-psram-workaround.a:lib_a-strcoll.* *libc-psram-workaround.a:lib_a-div.* *libc-psram-workaround.a:lib_a-close.* *libc-psram-workaround.a:lib_a-memrchr.* *libc-psram-workaround.a:lib_a-tzvars.* *libc-psram-workaround.a:lib_a-isspace.* *libc-psram-workaround.a:lib_a-islower.* *libc-psram-workaround.a:lib_a-tzlock.* *libc-psram-workaround.a:lib_a-isalnum.* *libc-psram-workaround.a:lib_a-strncmp.* *libc-psram-workaround.a:lib_a-tolower.* *libc-psram-workaround.a:lib_a-strchr.* *libc-psram-workaround.a:lib_a-ctime.* *libc-psram-workaround.a:lib_a-strcspn.* *libc-psram-workaround.a:lib_a-srand.* *libc-psram-workaround.a:lib_a-iscntrl.* *libc-psram-workaround.a:lib_a-tzset.* *libc-psram-workaround.a:lib_a-raise.* *libc-psram-workaround.a:lib_a-abs.* *libc-psram-workaround.a:lib_a-sysclose.* *libc-psram-workaround.a:lib_a-mktime.* *libc-psram-workaround.a:lib_a-fvwrite.* *libc-psram-workaround.a:lib_a-findfp.* *libc-psram-workaround.a:isatty.* *libc-psram-workaround.a:lib_a-bzero.* *libc-psram-workaround.a:lib_a-isupper.* *libc-psram-workaround.a:lib_a-labs.* *libc-psram-workaround.a:lib_a-refill.* *libc-psram-workaround.a:lib_a-time.* *libc-psram-workaround.a:lib_a-makebuf.* *libc-psram-workaround.a:lib_a-lcltime.* *libc-psram-workaround.a:lib_a-isalpha.* *libc-psram-workaround.a:lib_a-strcpy.* *libc-psram-workaround.a:lib_a-strcasestr.* *libc-psram-workaround.a:lib_a-s_fpclassify.* *libc-psram-workaround.a:lib_a-quorem.* *libc-psram-workaround.a:lib_a-gmtime_r.* *libc-psram-workaround.a:lib_a-strstr.* *libc-psram-workaround.a:lib_a-getenv_r.* *libc-psram-workaround.a:lib_a-strlcat.* *libc-psram-workaround.a:lib_a-strndup_r.* *libc-psram-workaround.a:lib_a-strncpy.* *libc-psram-workaround.a:lib_a-strptime.* *libc-psram-workaround.a:lib_a-gmtime.* *libc-psram-workaround.a:lib_a-fwalk.* *libc-psram-workaround.a:lib_a-wbuf.* *libc-psram-workaround.a:lib_a-wcrtomb.* *libc-psram-workaround.a:lib_a-isgraph.* *libc-psram-workaround.a:lib_a-setjmp.* *libc-psram-workaround.a:lib_a-system.* *libc-psram-workaround.a:lib_a-fputwc.* *libc-psram-workaround.a:lib_a-atol.* *libc-psram-workaround.a:lib_a-ldiv.* *libc-psram-workaround.a:lib_a-strtok_r.* *libc-psram-workaround.a:lib_a-ctype_.* *libc-psram-workaround.a:lib_a-sysread.* *libc-psram-workaround.a:lib_a-asctime.* *libc-psram-workaround.a:lib_a-itoa.* *libc-psram-workaround.a:lib_a-read.* *libc-psram-workaround.a:lib_a-strupr.* *libc-psram-workaround.a:lib_a-rand_r.* *libc-psram-workaround.a:lib_a-isascii.* *libc-psram-workaround.a:lib_a-strrchr.* *libc-psram-workaround.a:lib_a-strdup_r.* *libc-psram-workaround.a:lib_a-sccl.* *libc-psram-workaround.a:lib_a-fclose.* *libc-psram-workaround.a:lib_a-strcat.* *libc-psram-workaround.a:lib_a-syssbrk.* *libc-psram-workaround.a:lib_a-tzcalc_limits.* *libc-psram-workaround.a:lib_a-sbrk.* *libc-psram-workaround.a:lib_a-stdio.* *libc-psram-workaround.a:lib_a-syswrite.* *libc-psram-workaround.a:lib_a-rshift.* *libc-psram-workaround.a:lib_a-ungetc.* *libc-psram-workaround.a:lib_a-isprint.* *libc-psram-workaround.a:lib_a-memccpy.* *libc-psram-workaround.a:lib_a-strcasecmp.* *libc-psram-workaround.a:lib_a-wctomb_r.* *libc-psram-workaround.a:lib_a-envlock.* *libc-psram-workaround.a:lib_a-strncasecmp.* *libc-psram-workaround.a:lib_a-longjmp.* *libc-psram-workaround.a:lib_a-strncat.* *libc-psram-workaround.a:lib_a-memchr.* *libc-psram-workaround.a:lib_a-sf_nan.* *libc-psram-workaround.a:lib_a-memcpy.* *libc-psram-workaround.a:lib_a-strspn.* *libc-psram-workaround.a:lib_a-memset.* *libc-psram-workaround.a:lib_a-environ.* *libc-psram-workaround.a:lib_a-month_lengths.* *libc-psram-workaround.a:lib_a-wsetup.* *libc-psram-workaround.a:lock.* *libc-psram-workaround.a:lib_a-toascii.* *libc-psram-workaround.a:lib_a-strnlen.* *libc-psram-workaround.a:lib_a-strcmp.* *libc-psram-workaround.a:lib_a-strlen.* *libc-psram-workaround.a:lib_a-memcmp.* *libc-psram-workaround.a:lib_a-toupper.* *libc-psram-workaround.a:lib_a-memmove.* *libc-psram-workaround.a:lib_a-utoa.* *libc-psram-workaround.a:lib_a-isdigit.* *libc-psram-workaround.a:lib_a-asctime_r.* *libc-psram-workaround.a:lib_a-strsep.* *libc-psram-workaround.a:lib_a-strdup.* *libc-psram-workaround.a:lib_a-lcltime_r.* *libc-psram-workaround.a:lib_a-rand.* *libc-psram-workaround.a:lib_a-ctime_r.* *libc-psram-workaround.a:lib_a-open.* *libc-psram-workaround.a:lib_a-systimes.* *libc-psram-workaround.a:lib_a-fflush.* *libc-psram-workaround.a:lib_a-impure.* *libc-psram-workaround.a:lib_a-ispunct.* *libc-psram-workaround.a:lib_a-strlcpy.* *libc-psram-workaround.a:lib_a-isblank.* *libc-psram-workaround.a:lib_a-atoi.* *libc-psram-workaround.a:lib_a-tzset_r.* *libc-psram-workaround.a:lib_a-strndup.* *libc-psram-workaround.a:lib_a-gettzinfo.* *libc-psram-workaround.a:lib_a-strlwr.* *libc-psram-workaround.a:lib_a-strtol.* *libc-psram-workaround.a:lib_a-strtoul.* *libc-psram-workaround.a:lib_a-timelocal.* *libc-psram-workaround.a:lib_a-strftime.* *libfreertos.a *libgcov.a *libxtensa-debug-module.a:eri.* *libheap.a:multi_heap.* *libheap.a:multi_heap_poisoning.*) .text.* EXCLUDE_FILE(*libpp.a *libnet80211.a) .wifi0iram EXCLUDE_FILE(*libpp.a *libnet80211.a) .wifi0iram.*) + + *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + _text_end = ABSOLUTE(.); + _etext = .; + + /* Similar to _iram_start, this symbol goes here so it is + resolved by addr2line in preference to the first symbol in + the flash.text segment. + */ + _flash_cache_start = ABSOLUTE(0); + } >iram0_2_seg +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/esp32_out.ld b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/esp32_out.ld new file mode 100644 index 00000000..21c516fc --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/esp32_out.ld @@ -0,0 +1,74 @@ +/* ESP32 Linker Script Memory Layout + + This file describes the memory layout (memory blocks) as virtual + memory addresses. + + esp32.project.ld contains output sections to link compiler output + into these memory blocks. + + *** + + This linker script is passed through the C preprocessor to include + configuration options. + + Please use preprocessor features sparingly! Restrict + to simple macros with numeric values, and/or #if/#endif blocks. +*/ +/* + * + * Automatically generated file; DO NOT EDIT. + * Espressif IoT Development Framework Configuration + * + */ +/* If BT is not built at all */ +MEMORY +{ + /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length + of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but + are connected to the data port of the CPU and eg allow bytewise access. */ + /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */ + iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 + /* Even though the segment name is iram, it is actually mapped to flash + */ + iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000-0x18 + /* + (0x18 offset above is a convenience for the app binary image generation. Flash cache has 64KB pages. The .bin file + which is flashed to the chip has a 0x18 byte file header. Setting this offset makes it simple to meet the flash + cache MMU's constraint that (paddr % 64KB == vaddr % 64KB).) + */ + /* Shared data RAM, excluding memory reserved for ROM bss/data/stack. + + Enabling Bluetooth & Trace Memory features in menuconfig will decrease + the amount of RAM available. + + Note: Length of this section *should* be 0x50000, and this extra DRAM is available + in heap at runtime. However due to static ROM memory usage at this 176KB mark, the + additional static memory temporarily cannot be used. + */ + dram0_0_seg (RW) : org = 0x3FFB0000 + 0xdb5c, + len = 0x2c200 - 0xdb5c + /* Flash mapped constant data */ + drom0_0_seg (R) : org = 0x3F400018, len = 0x400000-0x18 + /* (See iram0_2_seg for meaning of 0x18 offset in the above.) */ + /* RTC fast memory (executable). Persists over deep sleep. + */ + rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000 + /* RTC fast memory (same block as above), viewed from data bus */ + rtc_data_seg(RW) : org = 0x3ff80000, len = 0x2000 + /* RTC slow memory (data accessible). Persists over deep sleep. + + Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled. + */ + rtc_slow_seg(RW) : org = 0x50000000 + 512, + len = 0x1000 - 512 + /* external memory ,including data and text */ + extern_ram_seg(RWX) : org = 0x3F800000, + len = 0x400000 +} +/* Heap ends at top of dram0_0_seg */ +_heap_end = 0x40000000 - 0x0; +_data_seg_org = ORIGIN(rtc_data_seg); +/* The lines below define location alias for .rtc.data section based on Kconfig option. + When the option is not defined then use slow memory segment + else the data will be placed in fast memory segment */ +REGION_ALIAS("rtc_data_location", rtc_slow_seg ); diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/mbedtls_config.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/mbedtls_config.h new file mode 100644 index 00000000..ab0f8731 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/mbedtls_config.h @@ -0,0 +1,53 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) 2006-2015, ARM Limited, All Rights Reserved +// See LICENSE file in the project root for full license information. +// + +#ifndef MBEDTLS_CONFIG_H +#define MBEDTLS_CONFIG_H + +/* For test certificates */ +// #define MBEDTLS_CERTS_C +// #define MBEDTLS_PEM_PARSE_C + +// #define SSL_DEBUG_BUF MBEDTLS_SSL_DEBUG_BUF +// #define SSL_DEBUG_CRT MBEDTLS_SSL_DEBUG_CRT +// #define SSL_DEBUG_ECP MBEDTLS_SSL_DEBUG_ECP +// #define SSL_DEBUG_MPI MBEDTLS_SSL_DEBUG_MPI +// #define SSL_DEBUG_MSG MBEDTLS_SSL_DEBUG_MSG +// #define SSL_DEBUG_RET MBEDTLS_SSL_DEBUG_RET + +// #define MBEDTLS_SSL_ALL_ALERT_MESSAGES +// #define MBEDTLS_SSL_DEBUG_ALL +// #define MBEDTLS_VERSION_FEATURES +// #define MBEDTLS_CERTS_C +// #define MBEDTLS_ERROR_C +// #define MBEDTLS_VERSION_C + +// uncomment the defines below to enable static memory allocation feature +#if 0 +#define MBEDTLS_MEMORY_BUFFER_ALLOC_C +#define MBEDTLS_PLATFORM_MEMORY +#endif + +#ifdef USE_LCD +#include "lcd_log.h" +#define MBEDTLS_PLATFORM_PRINTF_MACRO LCD_UsrLog +#endif + +// uncomment the defines bellow to generate debug output +// set below the threshold level for debug messages +// check mbed TLS mbedtls/debug.h header for details. +// Debug levels: +// 0 No debug +// 1 Error +// 2 State change +// 3 Informational +// 4 Verbose + +// #define MBEDTLS_DEBUG_C +// #define MBEDTLS_SSL_ALL_ALERT_MESSAGES +#define MBEDTLS_DEBUG_THRESHOLD 2 + +#endif // MBEDTLS_CONFIG_H diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoBooter/readme.md b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoBooter/readme.md new file mode 100644 index 00000000..776e0449 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoBooter/readme.md @@ -0,0 +1,4 @@ + +//////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET HAVE IT'S OWN BOOTER // +//////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/CLR_Startup_Thread.c b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/CLR_Startup_Thread.c new file mode 100644 index 00000000..aa7140dc --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/CLR_Startup_Thread.c @@ -0,0 +1,21 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +#include +#include +#include + +void CLRStartupThread(void const * argument) +{ + CLR_SETTINGS* clrSettings = (CLR_SETTINGS*)argument; + + nanoHAL_Initialize_C(); + + ClrStartup(*clrSettings); + + // nothing to deinitialize or cleanup, so it's safe to return +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/CMakeLists.txt b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/CMakeLists.txt new file mode 100644 index 00000000..026e8a57 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/CMakeLists.txt @@ -0,0 +1,71 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +include(NF_NativeAssemblies) + +# add header file with common target definitions +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_platform.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/target_platform.h" @ONLY) + +# append target Esp32 nanoCLR source files +list(APPEND TARGET_ESP32_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/app_main.c) +list(APPEND TARGET_ESP32_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_App_Interface.c) +list(APPEND TARGET_ESP32_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_MonitorCommands.c) +list(APPEND TARGET_ESP32_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/CLR_Startup_Thread.c") +list(APPEND TARGET_ESP32_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetPAL.c") +list(APPEND TARGET_ESP32_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") + +# append target HAL source files +list(APPEND TARGET_ESP32_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Power.c") +list(APPEND TARGET_ESP32_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Time.cpp") + +# Either NVS or SPIFSS storage for config, NVS is unable to store large Certificate bundles(over 1864 bytes) +#list(APPEND TARGET_ESP32_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_ConfigStorageNVS.cpp") + +list(APPEND TARGET_ESP32_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_ConfigStorageSPIFFS.cpp") + +# alternative to using NVS or Spiffs but requires minimum of 528K partition size +#list(APPEND TARGET_ESP32_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_ConfigStorageFATFS.cpp") + +list(APPEND TARGET_ESP32_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_ConfigurationManager.cpp") + +# append target PAL source files +list(APPEND TARGET_ESP32_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetPAL_Events.cpp") +list(APPEND TARGET_ESP32_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetPAL_Time.cpp") + +# append other CLR core files +list(APPEND TARGET_ESP32_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Memory.cpp") + +# append nanoCRT +list(APPEND TARGET_ESP32_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoCRT.cpp") + +# append nanoHAL +list(APPEND TARGET_ESP32_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL.cpp") + +# append files from Runtime.Native +list(APPEND TARGET_ESP32_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Native_Rtc.cpp") + +# append nanoHAL +list(APPEND TARGET_ESP32_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetRandom.cpp") + +# add native assemblies +ParseNativeAssemblies() + +# make var global +set(TARGET_ESP32_NANOCLR_SOURCES ${TARGET_ESP32_NANOCLR_SOURCES} CACHE INTERNAL "make global") + +# append target nanoCLR include directory +list(APPEND TARGET_ESP32_NANOCLR_INCLUDE_DIRS ${CMAKE_CURRENT_SOURCE_DIR}) +list(APPEND TARGET_ESP32_NANOCLR_INCLUDE_DIRS ${CMAKE_CURRENT_BINARY_DIR}) +list(APPEND TARGET_ESP32_NANOCLR_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Core) + +# append PAL include directory +list(APPEND TARGET_ESP32_NANOCLR_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/PAL/Include) + +# append Runtime.Native include directory +list(APPEND TARGET_ESP32_NANOCLR_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Runtime.Native) + +# make var global +set(TARGET_ESP32_NANOCLR_INCLUDE_DIRS ${TARGET_ESP32_NANOCLR_INCLUDE_DIRS} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Memory.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Memory.cpp new file mode 100644 index 00000000..a0b8ab80 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Memory.cpp @@ -0,0 +1,84 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include + +// +// Allocate Memory for Managed heap +// +// if spiRam is available then use all available ram - SPI_ALLOW_FREE +// +// if no spiRam or spiRam malloc fails then malloc from normal ram +// +// The CLR calls this multiple times. Once memory is allocated return the same memory for all +// subsequent calls. + + +static const char* TAG = "Memory"; + +// Space to leave free in spiRam +#define SPI_ALLOW_FREE (256 * 1024) + +// You can't go much bigger than this when allocating in normal memory to +// get memory in one continous lump. +#define NORMAL_MEMORY_SIZE (64 * 1024) + + +// Saved memory allocation for when heap is reset so we can return same value. +unsigned char* pManagedHeap = NULL; +size_t managedHeapSize = 0; + +// +// Return the location and size of the managed heap +// If called a 2nd time then always return same value +// +void HeapLocation(unsigned char*& baseAddress, unsigned int& sizeInBytes) +{ + NATIVE_PROFILE_PAL_HEAP(); + + // Memory allocated yet ? + if (pManagedHeap == NULL) + { + // Memory size to allocate in normal memory if spiRam not available + managedHeapSize = NORMAL_MEMORY_SIZE; + + // See if we have any SPIRAM + size_t spiramMaxSize = heap_caps_get_largest_free_block(MALLOC_CAP_8BIT | MALLOC_CAP_32BIT | MALLOC_CAP_SPIRAM); + + // Sanity check - Make sure there is at least managedHeapSize available in SPIRAM + if (spiramMaxSize > (SPI_ALLOW_FREE + managedHeapSize)) + { + // Allocate heap from SPIRAM + managedHeapSize = spiramMaxSize - SPI_ALLOW_FREE; + pManagedHeap = (unsigned char *)heap_caps_malloc(managedHeapSize, MALLOC_CAP_8BIT | MALLOC_CAP_32BIT | MALLOC_CAP_SPIRAM); + if (pManagedHeap) + ESP_LOGI(TAG, "Managed heap allocated, spiRam size:%d max:%d", managedHeapSize, spiramMaxSize); + } + + while(pManagedHeap == NULL) + { + // Allocate heap from Internal RAM + pManagedHeap = (unsigned char *)heap_caps_malloc(managedHeapSize, MALLOC_CAP_8BIT | MALLOC_CAP_32BIT); + if (pManagedHeap) + { + ESP_LOGI(TAG, "Managed heap allocated, internal size:%d", managedHeapSize); + } + else + { + // Subtract 1K and try again + managedHeapSize -= 1024; + if (managedHeapSize <= 0) + { + ESP_LOGE(TAG, "Unable to allocate any Managed heap"); + return; + } + } + } + } + + baseAddress = pManagedHeap; + sizeInBytes = managedHeapSize; +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/System.Devices.Dac/sys_dev_dac_native_System_Devices_Dac_DacChannel.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/System.Devices.Dac/sys_dev_dac_native_System_Devices_Dac_DacChannel.cpp new file mode 100644 index 00000000..a2ff1286 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/System.Devices.Dac/sys_dev_dac_native_System_Devices_Dac_DacChannel.cpp @@ -0,0 +1,98 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "sys_dev_dac_native_target.h" + + + +HRESULT Library_sys_dev_dac_native_System_Devices_Dac_DacChannel::NativeWriteValue___VOID__U2(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* dacController = NULL; + int channelNumber; + int controllerId; + dac_channel_t dacChannel = DAC_CHANNEL_1; + + // Get value argumant and mask to 0 - 255 range + uint16_t value = (stack.Arg1().NumericByRefConst().u2 & 0xff); + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Get channel from _channelNumber field + channelNumber = pThis[FIELD___channelNumber].NumericByRef().s4; + + // need to get the controllerId for the DAC controller of this channel + // get pointer to DacController field + dacController = pThis[FIELD___dacController].Dereference(); + + // get pointer to _controllerId field in DacController + controllerId = dacController[Library_sys_dev_dac_native_System_Devices_Dac_DacController::FIELD___controllerId].NumericByRef().s4; + + // only one DAC controller, but check it anyways + if (controllerId != 1) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + switch(channelNumber) + { + case 0: + dacChannel = DAC_CHANNEL_1; + break; + + case 1: + dacChannel = DAC_CHANNEL_2; + break; + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + dac_output_voltage(dacChannel, value); + + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_dac_native_System_Devices_Dac_DacChannel::NativeDispose___VOID__BOOLEAN(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + + int channelNumber; + bool disposeController = false; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get disposeController flag + disposeController = (bool)stack.Arg1().NumericByRef().u1; + + + if (disposeController) + { + // Get channel from _channelNumber field + channelNumber = pThis[FIELD___channelNumber].NumericByRef().s4; + + switch (channelNumber) + { + case 1: + dac_output_disable(DAC_CHANNEL_1); + break; + + case 2: + dac_output_disable(DAC_CHANNEL_2); + break; + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + } + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/System.Devices.Dac/sys_dev_dac_native_System_Devices_Dac_DacController.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/System.Devices.Dac/sys_dev_dac_native_System_Devices_Dac_DacController.cpp new file mode 100644 index 00000000..dc97db1a --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/System.Devices.Dac/sys_dev_dac_native_System_Devices_Dac_DacController.cpp @@ -0,0 +1,124 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "sys_dev_dac_native_target.h" + +HRESULT Library_sys_dev_dac_native_System_Devices_Dac_DacController::NativeOpenChannel___VOID__I4(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + { + int controllerId; + int channelNumber; + dac_channel_t dacChannel = DAC_CHANNEL_1; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Get channel from argument + channelNumber = stack.Arg1().NumericByRef().s4; + + // get controller ID + controllerId = pThis[FIELD___controllerId].NumericByRef().s4; + + // only one DAC controller for now, but check it anyways + if(controllerId != 1) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + switch(channelNumber) + { + case 0: + dacChannel = DAC_CHANNEL_1; + break; + + case 1: + dacChannel = DAC_CHANNEL_2; + break; + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // Enable DAC for this channel + dac_output_enable(dacChannel); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_dac_native_System_Devices_Dac_DacController::NativeGetChannelCount___I4(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + { + int controllerId; + int channelCount = 0; + + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + controllerId = pThis[ FIELD___controllerId ].NumericByRefConst().s4; + + switch(controllerId) + { + case 1: + channelCount = DacChannelCount; + break; + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // Return value to the managed application + stack.SetResult_I4(channelCount); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_dac_native_System_Devices_Dac_DacController::NativeGetResolutionInBits___I4(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + { + // Fixed at 8 bit + stack.SetResult_I4(DacResolutionInBits); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_sys_dev_dac_native_System_Devices_Dac_DacController::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + int controllerId; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get pointer to _controllerId field in AdcController + controllerId = pThis[FIELD___controllerId].NumericByRef().s4; + + // all required initialization for DAC is already handled in ChibiOS driver + + switch(controllerId) + { + case 1: + break; + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_sys_dev_dac_native_System_Devices_Dac_DacController::GetDeviceSelector___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // because the caller is expecting a result to be returned + // we need set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + stack.SetResult_String("DAC1"); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/System.Devices.Dac/sys_dev_dac_native_target.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/System.Devices.Dac/sys_dev_dac_native_target.h new file mode 100644 index 00000000..1c8b7616 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/System.Devices.Dac/sys_dev_dac_native_target.h @@ -0,0 +1,17 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#ifndef _SYS_DEV_DAC_NATIVE_TARGET_H_ +#define _SYS_DEV_DAC_NATIVE_TARGET_H_ + +#include +#include + + +#define DacChannelCount 2 +#define DacResolutionInBits 8 + +#endif //_SYS_DEV_DAC_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcChannel.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcChannel.cpp new file mode 100644 index 00000000..049be349 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcChannel.cpp @@ -0,0 +1,68 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_adc_native_target.h" + +extern "C" uint8_t temprature_sens_read(); + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcChannel::NativeReadValue___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + int reading = 0; + esp_err_t result; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Get channel from _channelNumber field + int channelNumber = pThis[FIELD___channelNumber].NumericByRef().s4; + + // need to get the controllerId for the ADC controller of this channel + // get pointer to AdcController field + //CLR_RT_HeapBlock* adcController = pThis[FIELD___adcController].Dereference(); + + // get pointer to _controllerId field +// int adcNumber = adcController[Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::FIELD___controllerId].NumericByRef().s4; + int adcNumber = channelNumber <= 9 ? 1 : 2; + + if ( adcNumber == 1) + { + switch(channelNumber) + { + case 8: + reading = temprature_sens_read(); break; + case 9: + reading = hall_sensor_read(); break; + default: + reading = adc1_get_raw( (adc1_channel_t)channelNumber); break; + } + } + else if ( adcNumber == 2) + { + result = adc2_get_raw( (adc2_channel_t)channelNumber, ADC_WIDTH_12Bit, &reading); + if ( result != ESP_OK) + NANOCLR_SET_AND_LEAVE(CLR_E_PIN_UNAVAILABLE); + } + else + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + stack.SetResult_I4(reading); + + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcChannel::NativeDisposeChannel___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + + // left empty on purpose, nothing to do here + + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcController.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcController.cpp new file mode 100644 index 00000000..53a45bad --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcController.cpp @@ -0,0 +1,183 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_adc_native_target.h" + +// ESP32 ADC controller +// +// Contains ADC1 and ADC2 +// ADC1 with 8 channels ( GPIO 32 - 39 ) 0=36, 1=37, 2=38, 3=39, 4=32, 5=33, 6=34, 7=35 +// channel 8/9 are logical channles for temperture sensor and is the built in Esp32 Hall sensor. +// For hall sensor there is a restriction channel 0 and 3 must be unused +// ADC2 with 10 channels (GPIO 0,2,4,12-15 and 25-27) +// Note : ADC2 cannot be used if Wifi started and other restrictions as pins used for other things. +// +// ESP_DevKitC Gpio 0 cannot be used +// ESP-Wrover_kit V3 GPIO 0,2,4 and 15 can't be used + +// Typical marked inputs on boards +// VP - GPIO36 ( channel 0 ) +// VN - GPIO39 ( channel 3 ) + +// From managed code we treat all ADC channels as 1 logical ADC unit (ADC1) +// Logical channels +// ADC1 / 0 - 7 - 8 channels - ( GPIO 32 - 39 ) 0=36, 1=37, 2=38, 3=39, 4=32, 5=33, 6=34, 7=35 +// 8 - Internal Temperture sensor +// 9 - Internal Hall Sensor +// ADC2 / 10 - 19 - 10 Channels -( GPIOs 0, 2, 4, 12 - 15 and 25 - 27. ) + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeOpenChannel___VOID__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + esp_err_t result; + adc_bits_width_t width_bit = ADC_WIDTH_BIT_12; // default to 12 + adc_atten_t atten = ADC_ATTEN_DB_11; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Get channel from argument + int channel = stack.Arg1().NumericByRef().s4; + + if ( channel < ADC_CHANNEL_0 || channel > 19 ) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + // Get ADC device number from channel + int adcUnit = channel <= 9 ? 1 : 2; + + adc_power_on(); // Make sure powered on + + switch(adcUnit) + { + case 1: + // Normal channel 0-7 ? + if ( channel <= 7 ) + { + adc1_config_width( width_bit ); + + result = adc1_config_channel_atten( (adc1_channel_t)channel, atten); + if ( result != ESP_OK ) + { + NANOCLR_SET_AND_LEAVE(CLR_E_PIN_UNAVAILABLE); + } + } + break; + + case 2: + result = adc2_config_channel_atten( (adc2_channel_t)channel, atten ); + if ( result != ESP_OK ) + { + NANOCLR_SET_AND_LEAVE(CLR_E_PIN_UNAVAILABLE); + } + break; + } + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeGetChannelCount___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + int channelCount = 20; + + // Return value to the managed application + stack.SetResult_I4(channelCount); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeGetMaxValue___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // Currently fixed 12 bit so return 4095 + stack.SetResult_I4(4095); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeGetMinValue___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + // Return 0 for now, is this signed ? + stack.SetResult_I4(0); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeIsChannelModeSupported___BOOLEAN__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + int mode = stack.Arg1().NumericByRef().s4; + + // Only support Single ended mode for now + AdcChannelMode singleEndedMode = SingleEnded; + stack.SetResult_Boolean( (mode == (int)singleEndedMode) ) ; + } + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeGetResolutionInBits___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // Fixed at 12 bit for now + stack.SetResult_I4(12); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + int controllerId; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get pointer to _controllerId field in AdcController + controllerId = pThis[FIELD___controllerId].NumericByRef().s4; + + // all required initialization for ADC are already handled + // this is only to check if the requested controllerId is available in hardware + + // expect only 1 + if(controllerId == 1) + { + // we are OK + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::GetDeviceSelector___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // declare the device selector string + // ADC1 and ADC2 + // ADC1 with 8 channels + Temperture sensor and and internal hall sensor + // ADC2 with 10 channeld but cannot be used if Wifi started + // + // These are now combined into 1 logical ADC (ADC1) + char deviceSelectorString[] = + "ADC1"; + + // because the caller is expecting a result to be returned + // we need set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + stack.SetResult_String(deviceSelectorString); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_target.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_target.h new file mode 100644 index 00000000..ed808e7e --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_target.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIN_DEV_ADC_NATIVE_TARGET_H_ +#define _WIN_DEV_ADC_NATIVE_TARGET_H_ + +#include + +#endif //_WIN_DEV_ADC_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter.cpp new file mode 100644 index 00000000..3bdc6d4b --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter.cpp @@ -0,0 +1,303 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_gpio_native.h" + +// Map Gpio pin number to 1 of 8 ESP32 counters, -1 = not mapped +// Each pulse counter is a 16 bit signed value. +// The managed code requires a 64 bit counter so we accumulate the overflows in an interrupt when count gets to 0x7fff + +static int8_t IsrInstalled = 0; +static int8_t GpioCounterMap[8] = { -1,-1,-1,-1,-1,-1,-1,-1 }; +static uint64_t OverflowCount[8]; + +#define MAX_COUNTER_VALUE 0x7fff + +extern void Remove_Gpio_Interrupt(gpio_num_t pinNumber); + + +// Interrupt routine used to catch overflows so we can have a 64 bit counter +static void IRAM_ATTR pcnt_intr_handler(void *arg) +{ + (void)arg; + + uint32_t intr_status = PCNT.int_st.val; + + for (int i = 0; i < PCNT_UNIT_MAX; i++) + { + if (intr_status & (BIT(i))) + { + + uint32_t status = PCNT.status_unit[i].val; + // Hit high limit MAX_COUNTER_VALUE + if (status & PCNT_STATUS_H_LIM_M) + { + OverflowCount[i] += MAX_COUNTER_VALUE; + } + + PCNT.int_clr.val = BIT(i); + } + } +} + + +// Find an unused counter, returns counter index or -1 if not found +static int FindFreeCounter(int gpioPin) +{ + int counterIndex; + + for (counterIndex = 0; counterIndex < 8; counterIndex++) + { + if (GpioCounterMap[counterIndex] == -1) + { + GpioCounterMap[counterIndex] = gpioPin; + return counterIndex; + } + } + return -1; +} + +// Find the index of counter for a gpio pin, returns index or -1 if not found +static int FindCounterForGpio(int gpioPin) +{ + int counterIndex; + + for (counterIndex = 0; counterIndex < 8; counterIndex++) + { + if (GpioCounterMap[counterIndex] == gpioPin) return counterIndex; + } + return -1; +} + +// Initalise the ESP32 counter +// return true if ok +static bool InitialiseCounter(int counterIndex, int gpioNum, bool countRising, bool countFalling) +{ + esp_err_t ec; + + // Prepare configuration for the PCNT unit */ + pcnt_config_t pcnt_config; + + // Set PCNT input signal and control GPIOs + pcnt_config.pulse_gpio_num = gpioNum; + pcnt_config.ctrl_gpio_num = PCNT_PIN_NOT_USED; // ignore + + pcnt_config.channel = PCNT_CHANNEL_0; + pcnt_config.unit = (pcnt_unit_t)counterIndex; + + // What to do on the positive / negative edge of pulse input? + pcnt_config.pos_mode = countRising ? PCNT_COUNT_INC : PCNT_COUNT_DIS; // positive edge count ? + pcnt_config.neg_mode = countFalling ? PCNT_COUNT_INC : PCNT_COUNT_DIS; // falling edge count ? + + // What to do when control input is low or high? + pcnt_config.lctrl_mode = PCNT_MODE_KEEP; // Keep the primary counter mode if low + pcnt_config.hctrl_mode = PCNT_MODE_KEEP; // Keep the primary counter mode if high + + // Set the maximum and minimum limit values to watch + pcnt_config.counter_h_lim = MAX_COUNTER_VALUE; + pcnt_config.counter_l_lim = 0; + + //* Initialize PCNT unit + ec = pcnt_unit_config(&pcnt_config); + if (ec != ESP_OK) return false; + + return true; +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter::NativeInit___VOID(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + int16_t pinNumber = pThis[FIELD___pinNumber].NumericByRefConst().s4; + + bool InputMode = (bool)pThis[FIELD___inputMode].NumericByRefConst().u1; + if (InputMode) + { + int index = FindFreeCounter(pinNumber); + if (index == -1) + { + // No free counters + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + } + + // Make sure GPIO pin doesn't have a GPIO Isr asscoiatted with it otherwise it will not support + // faster count frequencies + Remove_Gpio_Interrupt((gpio_num_t)pinNumber); + } + else + { + // Output not currently supported + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + } + + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter::NativeRead___U8__BOOLEAN(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // check if object has been disposed + if (pThis[Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter::FIELD___disposedValue].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + int pinNumber = pThis[FIELD___pinNumber].NumericByRefConst().s4; + + int counterIndex = FindCounterForGpio(pinNumber); + if (counterIndex == -1) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + bool resetAfterRead = (bool)stack.Arg0().NumericByRef().u1; + + int16_t counter; + + pcnt_get_counter_value((pcnt_unit_t)counterIndex, &counter); + + // relativeTime Read Time, Number of micro seconds since boot + int64_t relativeTime = esp_timer_get_time(); + + // Combine to make a 64 bit value + uint64_t totalCount = OverflowCount[counterIndex] + (uint64_t)counter; + + if (resetAfterRead) + { + pcnt_counter_clear((pcnt_unit_t)counterIndex); + OverflowCount[counterIndex] = 0; + } + + + // Return results + // Update the Relative _readTime field (convert micro sec to 100ns ticks) + *&pThis[FIELD___readTime].NumericByRef().s8 = (relativeTime * 10); + + // Return value to the managed application + stack.SetResult_U8(totalCount); + + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter::NativeStart___VOID(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + { + bool countRising = false; + bool countFalling = false; + + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // check if object has been disposed + if (pThis[Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter::FIELD___disposedValue].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + int pinNumber = pThis[FIELD___pinNumber].NumericByRefConst().s4; + + int counterIndex = FindCounterForGpio(pinNumber); + if (counterIndex == -1) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + GpioChangePolarity polarity = (GpioChangePolarity)pThis[FIELD___polarity].NumericByRefConst().s4; + + switch (polarity) + { + case Both: countRising = true; countFalling = true; break; + case Rising: countRising = true; break; + case Falling: countFalling = true; break; + } + + if (!InitialiseCounter(counterIndex, pinNumber, countRising, countFalling)) + { + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + } + + // Posible filter ( debounce ) future. + // pcnt_set_filter_value((pcnt_unit_t)counterIndex, 10); + // pcnt_filter_enable((pcnt_unit_t)counterIndex); + + pcnt_event_enable((pcnt_unit_t)counterIndex, PCNT_EVT_H_LIM); + + pcnt_counter_pause((pcnt_unit_t)counterIndex); + + pcnt_counter_clear((pcnt_unit_t)counterIndex); + OverflowCount[counterIndex] = 0; + + // Register ISR handler and enable interrupts for PCNT unit */ + if (IsrInstalled == 0) + { + pcnt_isr_register(pcnt_intr_handler, NULL, 0, NULL); + IsrInstalled = 1; + } + + // enable interrupts for PCNT unit + pcnt_intr_enable((pcnt_unit_t)counterIndex); + + pcnt_counter_resume((pcnt_unit_t)counterIndex); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter::NativeStop___VOID(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // check if object has been disposed + if (pThis[Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter::FIELD___disposedValue].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + int pinNumber = pThis[FIELD___pinNumber].NumericByRefConst().s4; + + int counterIndex = FindCounterForGpio(pinNumber); + if (counterIndex == -1) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + pcnt_counter_pause((pcnt_unit_t)counterIndex); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter::NativeDispose___VOID(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + int pinNumber = pThis[FIELD___pinNumber].NumericByRefConst().s4; + + int counterIndex = FindCounterForGpio(pinNumber); + if (counterIndex == -1) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + pcnt_intr_disable((pcnt_unit_t)counterIndex); + + // Disable counter, remove gpio pin + InitialiseCounter(counterIndex, PCNT_PIN_NOT_USED, false, false); + + // Clear counter / gpio mapping + GpioCounterMap[counterIndex] = -1; + } + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioController.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioController.cpp new file mode 100644 index 00000000..a2fc54c1 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioController.cpp @@ -0,0 +1,21 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#include "win_dev_gpio_native_target.h" + + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioController::get_PinCount___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Return value to the managed application + stack.SetResult_I4( GPIO_PIN_COUNT ); + } + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioPin.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioPin.cpp new file mode 100644 index 00000000..7aafaade --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioPin.cpp @@ -0,0 +1,369 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +// ESP32 GPIO ( 40 physical GPIO pads) +// +// GPIO6-11 used for PSI flash +// +// GPIO34-39 Only input mode +// + +#include +#include "win_dev_gpio_native_target.h" +#include "nf_rt_events_native.h" + +#include "Esp32_DeviceMapping.h" + +static const char* TAG = "GpioPin"; +static bool Gpio_Initialised = false; + +// this array keeps track of the Gpio pins that are assigned to each channel +CLR_RT_HeapBlock* channelPinMapping[] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL }; + + +void Initialize_gpio() +{ + esp_err_t ret = gpio_install_isr_service( 0); + if ( ret != ESP_OK ) + { + ESP_LOGE( TAG, "Install isr service"); + } +} + +void Gpio_Interupt_ISR(void * args) +{ + uint32_t pinNumber = (uint32_t)args; + + NATIVE_INTERRUPT_START + + CLR_RT_HeapBlock* pThis = channelPinMapping[pinNumber]; + if ( pThis == NULL ) + { + NATIVE_INTERRUPT_END + + return; + } + + // check if object has been disposed + if( pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + // object has been disposed, leave now + NATIVE_INTERRUPT_END + return; + } + + // flag to determine if there are any callbacks registered in managed code + bool callbacksRegistered = (pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___callbacks ].Dereference() != NULL); + if ( callbacksRegistered ) + { + // if handle registed then post a managed event with the current pin reading + PostManagedEvent( EVENT_GPIO, 0, pinNumber, gpio_get_level((gpio_num_t)pinNumber) ); + } + + NATIVE_INTERRUPT_END +} + +void Add_Gpio_Interrupt(gpio_num_t pinNumber) +{ + if ( !Gpio_Initialised ) + { + Initialize_gpio(); + Gpio_Initialised = true; + } + + esp_err_t ret = gpio_isr_handler_add( pinNumber, Gpio_Interupt_ISR, (void *)pinNumber); + if ( ret != ESP_OK ) + { + ESP_LOGE( TAG, "Add interrupt to pin"); + } +} + + +void Remove_Gpio_Interrupt(gpio_num_t pinNumber) +{ + if (channelPinMapping[pinNumber] != NULL) + { + // Remove from interrupts + gpio_isr_handler_remove((gpio_num_t)pinNumber); + + // clear this channel in channel pin mapping + channelPinMapping[pinNumber] = NULL; + } +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::Read___WindowsDevicesGpioGpioPinValue( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + if(pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + gpio_num_t pinNumber = (gpio_num_t)pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + + stack.SetResult_I4( gpio_get_level(pinNumber) ); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::Toggle___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // check if object has been disposed + if(pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + int16_t pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + GpioPinDriveMode driveMode = (GpioPinDriveMode)pThis[ FIELD___driveMode ].NumericByRefConst().s4; + + // sanity check for drive mode set to output so we don't mess up writing to an input pin + if ((driveMode == GpioPinDriveMode_Output) || + (driveMode == GpioPinDriveMode_OutputOpenDrain) || + (driveMode == GpioPinDriveMode_OutputOpenDrainPullUp) || + (driveMode == GpioPinDriveMode_OutputOpenSource) || + (driveMode == GpioPinDriveMode_OutputOpenSourcePullDown)) + { + // ESP32 GPIO API doesn't offer a 'toggle', so need to rely on the last output value field and toggle that one + GpioPinValue newState = (GpioPinValue)(GpioPinValue_High ^ (GpioPinValue)pThis[ FIELD___lastOutputValue ].NumericByRef().s4); + + // ...write back to the GPIO... + gpio_set_level((gpio_num_t)pinNumber, newState); + + // ... and finally store it + pThis[ FIELD___lastOutputValue ].NumericByRef().s4 = newState; + } + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::DisposeNative___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // set pin to input to save power + // clear interrupts + // releases the pin + int16_t pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + + Remove_Gpio_Interrupt((gpio_num_t)pinNumber); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeIsDriveModeSupported___BOOLEAN__WindowsDevicesGpioGpioPinDriveMode( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + GpioPinDriveMode driveMode = (GpioPinDriveMode)stack.Arg1().NumericByRef().s4; + + bool driveModeSupported = false; + + // check if the requested drive mode is support by ChibiOS config + if ((driveMode == GpioPinDriveMode_Input) || + (driveMode == GpioPinDriveMode_InputPullDown) || + (driveMode == GpioPinDriveMode_InputPullUp) || + (driveMode == GpioPinDriveMode_Output) || + (driveMode == GpioPinDriveMode_OutputOpenDrain)) + { + driveModeSupported = true; + } + + // Return value to the managed application + stack.SetResult_Boolean( driveModeSupported ) ; + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeSetDriveMode___VOID__WindowsDevicesGpioGpioPinDriveMode( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + if(pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + signed int pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + signed int driveMode = stack.Arg1().NumericByRef().s4; + + // Valid PinNumber + if ( ! GPIO_IS_VALID_GPIO(pinNumber) ) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // Check Pin is output capable + if ( driveMode >= 3 && !GPIO_IS_VALID_OUTPUT_GPIO(pinNumber) ) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + gpio_mode_t mode = GPIO_MODE_DISABLE; + gpio_pullup_t pull_up_en = GPIO_PULLUP_DISABLE; + gpio_pulldown_t pull_down_en = GPIO_PULLDOWN_DISABLE; + gpio_int_type_t intr_type = GPIO_INTR_ANYEDGE; + + switch (driveMode) + { + case GpioPinDriveMode_Input : + mode = GPIO_MODE_INPUT; + break; + case GpioPinDriveMode_InputPullDown : + mode = GPIO_MODE_INPUT; + pull_down_en = GPIO_PULLDOWN_ENABLE; + break; + case GpioPinDriveMode_InputPullUp : + mode = GPIO_MODE_INPUT; + pull_up_en = GPIO_PULLUP_ENABLE; + break; + case GpioPinDriveMode_Output : + mode = GPIO_MODE_OUTPUT; + break; + case GpioPinDriveMode_OutputOpenDrain : + mode = GPIO_MODE_OUTPUT_OD; + break; + case GpioPinDriveMode_OutputOpenDrainPullUp : + mode = GPIO_MODE_OUTPUT_OD; + pull_up_en = GPIO_PULLUP_ENABLE; + break; + case GpioPinDriveMode_OutputOpenSource: + mode = GPIO_MODE_OUTPUT_OD; + break; + case GpioPinDriveMode_OutputOpenSourcePullDown: + mode = GPIO_MODE_OUTPUT_OD; + pull_down_en = GPIO_PULLDOWN_ENABLE; + break; + } + + gpio_config_t GPIOConfig; + + GPIOConfig.pin_bit_mask = (1ULL << pinNumber); + GPIOConfig.mode = mode; + GPIOConfig.pull_up_en = pull_up_en; + GPIOConfig.pull_down_en = pull_down_en; + GPIOConfig.intr_type = intr_type; + + gpio_config( &GPIOConfig ); + + // Enable interrupts for all pins + Add_Gpio_Interrupt( (gpio_num_t)pinNumber ); + + // save pin reference + channelPinMapping[pinNumber] = pThis; + + // protect this from GC so that the callback is where it's supposed to + CLR_RT_ProtectFromGC gc( *pThis ); + + + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeInit___BOOLEAN__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + int16_t pinNumber = stack.Arg1().NumericByRef().s4; + + // TODO is probably a good idea keep track of the used pins, so we can check that here + // TODO is probably a good idea to check if this pin exists + + if ( !GPIO_IS_VALID_GPIO((gpio_num_t)pinNumber) ) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // Return value to the managed application + stack.SetResult_Boolean(true ); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeSetDebounceTimeout___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + + // nothing to do here as the debounce timeout is grabbed from the managed object when required + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::WriteNative___VOID__WindowsDevicesGpioGpioPinValue( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // check if object has been disposed + if(pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + int16_t pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + GpioPinDriveMode driveMode = (GpioPinDriveMode)pThis[ FIELD___driveMode ].NumericByRefConst().s4; + + GpioPinValue state = (GpioPinValue)stack.Arg1().NumericByRef().s4; + + // sanity check for drive mode set to output so we don't mess up writing to an input pin + if ((driveMode == GpioPinDriveMode_Output) || + (driveMode == GpioPinDriveMode_OutputOpenDrain) || + (driveMode == GpioPinDriveMode_OutputOpenDrainPullUp) || + (driveMode == GpioPinDriveMode_OutputOpenSource) || + (driveMode == GpioPinDriveMode_OutputOpenSourcePullDown)) + { + gpio_set_level( (gpio_num_t)pinNumber, state); + + // store the output value in the field + pThis[ FIELD___lastOutputValue ].NumericByRef().s4 = state; + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeSetAlternateFunction___VOID__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // check if object has been disposed + if(pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + // get pin number and take the port and pad references from that one + int16_t pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + + // get alternate function argument + int32_t alternateFunction = stack.Arg1().NumericByRef().s4; + + Esp32_SetMappedDevicePins( (uint8_t)pinNumber, alternateFunction ); + } + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_target.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_target.h new file mode 100644 index 00000000..7666fe1c --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_target.h @@ -0,0 +1,13 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#ifndef _WIN_DEV_GPIO_NATIVE_TARGET_H_ +#define _WIN_DEV_GPIO_NATIVE_TARGET_H_ + +#include + +#endif //_WIN_DEV_GPIO_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2C_I2cDevice.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2C_I2cDevice.cpp new file mode 100644 index 00000000..896e2190 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2C_I2cDevice.cpp @@ -0,0 +1,228 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include "win_dev_i2c_native_target.h" +#include "Esp32_DeviceMapping.h" + +static const char* TAG = "I2C"; + +typedef Library_win_dev_i2c_native_Windows_Devices_I2c_I2cConnectionSettings I2cConnectionSettings; + +static char Esp_I2C_Initialised_Flag[I2C_NUM_MAX] = {0,0}; + +void Esp32_I2c_UnitializeAll() +{ + for (int c = 0; c < I2C_NUM_MAX; c++) + { + if (Esp_I2C_Initialised_Flag[c]) + { + // Delete bus driver + i2c_driver_delete((i2c_port_t)c); + Esp_I2C_Initialised_Flag[c] = 0; + } + } +} + +void SetConfig(i2c_port_t bus, CLR_RT_HeapBlock* config) +{ + int busSpeed = config[ I2cConnectionSettings::FIELD___busSpeed ].NumericByRef().s4; + + gpio_num_t DataPin = (gpio_num_t)Esp32_GetMappedDevicePins( DEV_TYPE_I2C, bus, 0); + gpio_num_t ClockPin = (gpio_num_t)Esp32_GetMappedDevicePins( DEV_TYPE_I2C, bus, 1); + + i2c_config_t conf; + conf.mode = I2C_MODE_MASTER; + conf.sda_io_num = DataPin; + conf.sda_pullup_en = GPIO_PULLUP_ENABLE; + conf.scl_io_num = ClockPin; + conf.scl_pullup_en = GPIO_PULLUP_ENABLE; + conf.master.clk_speed = (busSpeed==0)? 100000 : 400000; + + i2c_param_config(bus, &conf); +} + + +HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get bus index + // this is coded with a multiplication, need to perform and int division to get the number + // see the comments in the SpiDevice() constructor in managed code for details, subtract 1 to get ESP32 bus number + i2c_port_t bus = (i2c_port_t)((pThis[ FIELD___deviceId ].NumericByRef().s4 / 1000) - 1); + if ( bus != I2C_NUM_0 && bus != I2C_NUM_1) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // get a pointer to the managed spi connectionSettings object instance + CLR_RT_HeapBlock* pConfig = pThis[ FIELD___connectionSettings ].Dereference(); + + // Set the Bus parameters + SetConfig( bus, pConfig); + + // If this is first devcie on Bus then init driver + if ( Esp_I2C_Initialised_Flag[bus] == 0 ) + { + esp_err_t res = i2c_driver_install( bus, I2C_MODE_MASTER, 0, 0, 0); + if ( res != ESP_OK) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // Ensure driver gets unitialized during soft reboot + HAL_AddSoftRebootHandler(Esp32_I2c_UnitializeAll); + Esp_I2C_Initialised_Flag[bus]++; + } + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::NativeDispose___VOID__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + i2c_port_t bus = (i2c_port_t)((pThis[ FIELD___deviceId ].NumericByRef().s4 / 1000) - 1); + + Esp_I2C_Initialised_Flag[bus]--; + + if ( Esp_I2C_Initialised_Flag[bus] <= 0 ) + { + i2c_driver_delete(bus); + + Esp_I2C_Initialised_Flag[bus] = 0; + } + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::NativeTransmit___WindowsDevicesI2cI2cTransferResult__SZARRAY_U1__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + unsigned char * writeData = NULL; + unsigned char * readData = NULL; + int writeSize = 0; + int readSize = 0; + esp_err_t i2cStatus; + + CLR_RT_HeapBlock* result; + // create the return object (I2cTransferResult) + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the managed spi connectionSettings object instance + CLR_RT_HeapBlock* pConfig = pThis[ FIELD___connectionSettings ].Dereference(); + + // get bus index + // this is coded with a multiplication, need to perform and int division to get the number + // see the comments in the SpiDevice() constructor in managed code for details, subtract 1 to get ESP32 bus number + i2c_port_t bus = (i2c_port_t)((pThis[ FIELD___deviceId ].NumericByRef().s4 / 1000) - 1); + + int slaveAddress = pConfig[ I2cConnectionSettings::FIELD___slaveAddress ].NumericByRef().s4; + + // dereference the write and read buffers from the arguments + CLR_RT_HeapBlock_Array* writeBuffer = stack.Arg1().DereferenceArray(); + if (writeBuffer != NULL) + { + // grab the pointer to the array by getting the first element of the array + writeData = writeBuffer->GetFirstElement(); + + // get the size of the buffer by reading the number of elements in the HeapBlock array + writeSize = writeBuffer->m_numOfElements; + } + + CLR_RT_HeapBlock_Array* readBuffer = stack.Arg2().DereferenceArray(); + if (readBuffer != NULL) + { + // grab the pointer to the array by getting the first element of the array + readData = readBuffer->GetFirstElement(); + + // get the size of the buffer by reading the number of elements in the HeapBlock array + readSize = readBuffer->m_numOfElements; + } + + i2c_cmd_handle_t cmd = i2c_cmd_link_create(); + + if ( writeSize != 0 ) // Write + { + i2c_master_start(cmd); + i2c_master_write_byte( cmd, ( slaveAddress << 1 ) | I2C_MASTER_WRITE, 1); + i2cStatus = i2c_master_write(cmd, &writeData[0], writeSize, true); + if (i2cStatus != ESP_OK) ESP_LOGE( TAG, "i2c_master_write error:%d", i2cStatus ); + + } + if (readSize != 0) // Read + { + i2c_master_start(cmd); + i2c_master_write_byte(cmd, (slaveAddress << 1) | I2C_MASTER_READ, 1); + if (readSize > 1) + { + // Additional read bytes with ACK + i2c_master_read(cmd, &readData[0], readSize - 1, I2C_MASTER_ACK); + } + // Last read byte with NACK + i2c_master_read_byte(cmd, &readData[readSize - 1], I2C_MASTER_NACK); + } + + i2c_master_stop(cmd); + + i2cStatus = i2c_master_cmd_begin(bus, cmd, 1000 / portTICK_RATE_MS); + i2c_cmd_link_delete(cmd); + + // create return object + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_I2cTransferResult)); + result = top.Dereference(); FAULT_ON_NULL(result); + + if (i2cStatus != ESP_OK) + { + uint32_t transferResult = I2cTransferStatus_FullTransfer; + + // set the result field + if ( i2cStatus == ESP_FAIL ) + { + transferResult = I2cTransferStatus_SlaveAddressNotAcknowledged; + } + else if (i2cStatus == ESP_ERR_TIMEOUT ) + { + transferResult = I2cTransferStatus_ClockStretchTimeout; + } + else + { + transferResult = I2cTransferStatus_UnknownError; + } + + result[ Library_win_dev_i2c_native_Windows_Devices_I2c_I2cTransferResult::FIELD___status ].SetInteger((CLR_UINT32)transferResult); + + // set the bytes transferred field + result[ Library_win_dev_i2c_native_Windows_Devices_I2c_I2cTransferResult::FIELD___bytesTransferred ].SetInteger(0); + } + else + { + result[ Library_win_dev_i2c_native_Windows_Devices_I2c_I2cTransferResult::FIELD___status ].SetInteger((CLR_UINT32)I2cTransferStatus_FullTransfer); + + // set the bytes transferred field + result[ Library_win_dev_i2c_native_Windows_Devices_I2c_I2cTransferResult::FIELD___bytesTransferred ].SetInteger((CLR_UINT32)(writeSize + readSize)); + + if(readSize > 0) + { + // because this was a Read transaction, need to copy from DMA buffer to managed buffer + memcpy(readBuffer->GetFirstElement(), &readData[0], readSize); + } + } + } + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2c_I2cController.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2c_I2cController.cpp new file mode 100644 index 00000000..0552f96c --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2c_I2cController.cpp @@ -0,0 +1,37 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include "win_dev_i2c_native_target.h" +#include "Esp32_DeviceMapping.h" + + +HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cController::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + { + + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cController::GetDeviceSelector___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // declare the device selector string whose max size is "I2C1,I2C2,I2C3," + terminator and init with the terminator + char deviceSelectorString[ 15 + 1] = { 0 }; + + strcat(deviceSelectorString, "I2C1,I2C2"); + + // because the caller is expecting a result to be returned + // we need set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + stack.SetResult_String(deviceSelectorString); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_target.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_target.h new file mode 100644 index 00000000..8dd64a47 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_target.h @@ -0,0 +1,11 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIN_DEV_I2C_NATIVE_TARGET_H_ +#define _WIN_DEV_I2C_NATIVE_TARGET_H_ + +#include + +#endif //_WIN_DEV_I2C_NATIVE_TARGET_H_ \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp new file mode 100644 index 00000000..c85e0e0b --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp @@ -0,0 +1,113 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "win_dev_pwm_native_target.h" + +uint32_t PwmController_Timer_resolution[8]; + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_MaxFrequency___R8( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // 40mhz with 1 bit duty cycle (50% fixed duty) + double maxFrequency = 40000000.0; + + stack.SetResult_R8(maxFrequency); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_MinFrequency___R8( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // FIXME : how can this value be determined ? + stack.SetResult_R8(1.0); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_PinCount___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // Returns number of pins for Pwm ( number of channels for Led Pwm) + int pinCount = 16; + + stack.SetResult_I4(pinCount); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::NativeSetDesiredFrequency___U4__U4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties ( 0 - 7 ) + int timerId = (int)(pThis[ FIELD___controllerId ].NumericByRef().u4); + + unsigned int desiredFrequency = (unsigned int)stack.Arg1().NumericByRef().u4; + + ledc_timer_t timer = (ledc_timer_t)(timerId & 0x03); + ledc_mode_t mode = (timerId <= 4) ? LEDC_HIGH_SPEED_MODE : LEDC_LOW_SPEED_MODE; + + // Work out the optimumal duty resolution based on current frequency, default to 1 if not found + // Working from 15 bit duty resolution down until we have a valid divisor + int optimumDutyResolution = 1; + for( int dutyResolution=15; dutyResolution>0; dutyResolution--) + { + uint32_t precision = ( 0x1 << dutyResolution ); // 2**depth + + uint64_t divParam = ( (uint64_t) LEDC_APB_CLK_HZ << 8 ) / desiredFrequency / precision; + if ( divParam > 256) + { + optimumDutyResolution = dutyResolution; + break; + } + } + + ledc_timer_bit_t duty_res = (ledc_timer_bit_t)optimumDutyResolution; + + // Save resolution for working out values for percent duty cycle + PwmController_Timer_resolution[timerId] = ( 0x1 << optimumDutyResolution ); + + ledc_timer_config_t timer_conf { + mode, + duty_res, + timer, + desiredFrequency + }; + + esp_err_t result = ledc_timer_config( &timer_conf); + if ( result != ESP_OK ) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + stack.SetResult_R8((double)desiredFrequency); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::GetDeviceSelector___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // declare the device selector string + // TIM0 to TIM3 are hish speed timers + // TIM4 to TIM7 are low speed timers + char deviceSelectorString[] = + "TIM0,TIM1,TIME2,TIM3,TIM4,TIM5,TIM6,TIM7"; + + // because the caller is expecting a result to be returned + // we need set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + stack.SetResult_String(deviceSelectorString); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp new file mode 100644 index 00000000..a599d594 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp @@ -0,0 +1,233 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "win_dev_pwm_native_target.h" + +// Used to map a PWM channel number to a pin number for High and low speed channels +static char HighSpeedPinMap[8] = { 255,255,255,255,255,255,255,255 }; +static char LowSpeedPinMap[8] = { 255,255,255,255,255,255,255,255 }; + +#define GetSpeedMode(timer) (ledc_mode_t)((timer>3) ? LEDC_LOW_SPEED_MODE : LEDC_HIGH_SPEED_MODE ) +#define IDF_ERROR(result) if ( result != ESP_OK ) { NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); } + +extern uint32_t PwmController_Timer_resolution[8]; + + +// +// Look up Pin number to find channel, if create true and not present then add pin +// return channel number or -1 if error +// +int GetChannel (int pin, int timerId, bool create) +{ + int channel = -1; // Return if not found + + // Selct map depending if high or low speed timers + char * pMap = (timerId > 3)? LowSpeedPinMap: HighSpeedPinMap; + char * pMap2 = pMap; + + //look for pin in map + for( int index=0; index<8; index++, pMap++ ) + { + if (*pMap == pin ) { channel = index; break; } + } + + if ( create && channel == -1) + { + // if pin/channel not found then allocate one + for( int index=0; index<8; index++, pMap2++ ) + { + if (*pMap2 == 255 ) { channel = index; *pMap2 = pin; break; } + } + } + + return channel; +} + +// +// Work out the duty Cycle for the current duty resolution and polarity +// +uint32_t CalculateDuty(int timerId, uint32_t dutyCycle, PwmPulsePolarity polarity) +{ + // if polarity Active low then reverse duty cycle + if (polarity == ActiveLow ) dutyCycle = 10000 - dutyCycle; + + // Return a duy cycle in the range of the current timer duty resolution + return PwmController_Timer_resolution[timerId] * dutyCycle / 10000; +} + +HRESULT ConfigureAndStart(CLR_RT_HeapBlock* pThis, bool create, bool noStart) +{ + NANOCLR_HEADER(); + { + // Retrieves the needed parameters from private class properties or method parameters + int timerId = (int)(pThis[ Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::FIELD___pwmTimer ].NumericByRef().u4); + int pinNumber = (int)(pThis[ Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::FIELD___pinNumber ].NumericByRef().u4); + uint32_t dutyCycle = (uint32_t)(pThis[ Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::FIELD___dutyCycle ].NumericByRef().u4); + PwmPulsePolarity polarity = (PwmPulsePolarity)(pThis[ Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::FIELD___polarity ].NumericByRef().u4); + + // Configure channel + ledc_mode_t mode = GetSpeedMode(timerId); + ledc_channel_t channel = (ledc_channel_t)GetChannel(pinNumber, timerId, create); + if ( channel == -1 ) + { + // Unable to create a new channel, all channels used up ? + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_RANGE); + } + + ledc_timer_t timer_sel = (ledc_timer_t)(timerId & 0x03); + + // Work out the duty Cycle for the current duty resolution + dutyCycle = CalculateDuty( timerId, dutyCycle, polarity ); + + ledc_channel_config_t ledc_conf { + pinNumber, + mode, + channel, + LEDC_INTR_DISABLE, + timer_sel, + dutyCycle, + 0 + }; + + // Configure Channel which will also start it + IDF_ERROR( ledc_channel_config(&ledc_conf) ); + + // Because it is started from the configure we optionally stop it and set idle level based on polarity + if ( noStart) ledc_stop(mode, channel, polarity); + + } + NANOCLR_NOCLEANUP(); +} + +// +// Pwmpin created +// Validate pin and create an entry in Channel/Pin map +// +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Check pin number is a valid for output + int pinNumber = (int)(pThis[ FIELD___pinNumber ].NumericByRef().u4); + if ( !GPIO_IS_VALID_OUTPUT_GPIO(pinNumber) ) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // Create a new entry in channel table and configure channel which will also start channel + NANOCLR_CHECK_HRESULT( ConfigureAndStart(pThis, true, true) ); + } + NANOCLR_NOCLEANUP(); +} + + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeSetActiveDutyCyclePercentage___VOID__U4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties or method parameters + int timerId = (int)(pThis[ FIELD___pwmTimer ].NumericByRef().u4); + int pinNumber = (int)(pThis[ FIELD___pinNumber ].NumericByRef().u4); + PwmPulsePolarity polarity = (PwmPulsePolarity)(pThis[ FIELD___polarity ].NumericByRef().u4); + + // retrieve Percents as 0 to 10000 ( 0% to 100%) + uint32_t dutyCycle = (uint32_t)stack.Arg1().NumericByRef().u4; + + // Get channel number usd for this pinNumber + // FIXME check result + ledc_channel_t channel = (ledc_channel_t)GetChannel (pinNumber, timerId, false); + + // Get speed mode based on Timer used + ledc_mode_t speed_mode = GetSpeedMode(timerId); + + // Work out the duty Cycle for the current duty resolution + dutyCycle = CalculateDuty( timerId, dutyCycle, polarity ); + + // Update duty on channel + IDF_ERROR( ledc_set_duty(speed_mode, channel, dutyCycle) ); + + // Activate duty on channel + IDF_ERROR( ledc_update_duty( speed_mode, channel) ); + + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeSetPolarity___VOID__U1( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + { + // Nothing to do here, we handle it other places + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeStart___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Call configure to start PWM channel + NANOCLR_CHECK_HRESULT( ConfigureAndStart(pThis, false, false) ); + + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeStop___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties or method parameters + int timerId = (int)(pThis[ FIELD___pwmTimer ].NumericByRef().u4); + int pinNumber = (int)(pThis[ FIELD___pinNumber ].NumericByRef().u4); + int polarity = (int)(pThis[ FIELD___polarity ].NumericByRef().u4); + + ledc_mode_t speed_mode = GetSpeedMode(timerId); + + // FIX ME check result + ledc_channel_t channel = (ledc_channel_t)GetChannel(pinNumber, timerId, false); + + ledc_stop(speed_mode, channel, (uint32_t)polarity); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::DisposeNative___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties or method parameters + int timerId = (int)(pThis[ FIELD___pwmTimer ].NumericByRef().u4); + int pinNumber = (int)(pThis[ FIELD___pinNumber ].NumericByRef().u4); + + // Remove pin from pin/channel Map + char * pMap = (timerId > 3)? LowSpeedPinMap: HighSpeedPinMap; + + for( int index=0; index<8; index++, pMap++ ) + { + if (*pMap == pinNumber ) { *pMap = 255; break; } + } + } + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_target.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_target.h new file mode 100644 index 00000000..b102b091 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_target.h @@ -0,0 +1,23 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIN_DEV_PWM_NATIVE_TARGET_H_ +#define _WIN_DEV_PWM_NATIVE_TARGET_H_ + +#include + +enum PwmPulsePolarity +{ + /// + /// Configures the PWM signal to start in the active high state. + /// + ActiveHigh, + /// + /// Configures the PWM signal to start in the active low state. + /// + ActiveLow +}; + +#endif //_WIN_DEV_PWM_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.SerialCommunication/win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.SerialCommunication/win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice.cpp new file mode 100644 index 00000000..fee59e23 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.SerialCommunication/win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice.cpp @@ -0,0 +1,547 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "win_dev_serial_native_target.h" +#include "Esp32_DeviceMapping.h" + +// buffers size +// tx buffer size: 256 bytes +#define UART_TX_BUFER_SIZE 256 +// rx buffer size: 256 bytes +#define UART_RX_BUFER_SIZE 256 + +// in UWP the COM ports are named COM1, COM2, COM3. But ESP32 uses internally UART0, UART1, UART2. This maps the port index 1, 2 or 3 to the uart number 0, 1 or 2 +#define PORT_INDEX_TO_UART_NUM(portIndex) ((portIndex) - 1) +// in UWP the COM ports are named COM1, COM2, COM3. But ESP32 uses internally UART0, UART1, UART2. This maps the uart number 0, 1 or 2 to the port index 1, 2 or 3 +#define UART_NUM_TO_PORT_INDEX(uart_num) ((uart_num) + 1) + +static const char* TAG = "SerialDevice"; + +static char Esp_Serial_Initialised_Flag[UART_NUM_MAX] = {0, 0, 0}; +static QueueHandle_t Uart_Event_Queue[UART_NUM_MAX]; +static bool Uart_Post_SerialData_Chars_Event[UART_NUM_MAX] = {true, true, true}; +CLR_RT_HeapBlock* Serial_Device_Instance[UART_NUM_MAX]; +static int Uart_writeLength[UART_NUM_MAX]; + +void Esp32_Serial_UnitializeAll() +{ + for (int uart_num = 0; uart_num < UART_NUM_MAX; uart_num++) + { + if (Esp_Serial_Initialised_Flag[uart_num]) + { + // Delete uart driver and send the exit signal to the UART event handling queue + uart_driver_delete((uart_port_t)uart_num); + xQueueSend(Uart_Event_Queue[uart_num], (void*)UART_EVENT_MAX, (portTickType)0); + Uart_Post_SerialData_Chars_Event[uart_num] = false; + Serial_Device_Instance[uart_num] = NULL; + Esp_Serial_Initialised_Flag[uart_num] = 0; + } + } +} + +static void uart_event_task(void *pvParameters) +{ + int uart_num = (int)pvParameters; + uart_event_t event; + bool run = true; + + while(run) + { + // Waiting for UART event. + if(xQueueReceive(Uart_Event_Queue[uart_num], (void*)&event, (portTickType)portMAX_DELAY)) { + switch(event.type) { + // Data received + case UART_DATA: + // only if no one is reading the chars already and only if an event handler is attached + if (Uart_Post_SerialData_Chars_Event[uart_num] && Serial_Device_Instance[uart_num][Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::FIELD___callbacksDataReceivedEvent].Dereference() != NULL) + { + // post a managed event with the port index and the chars event code; uart_num + 1 because UART0 maps to COM1 + PostManagedEvent(EVENT_SERIAL, 0, UART_NUM_TO_PORT_INDEX(uart_num), SerialData_Chars); + // supress the event for the following chars; prevents spamming with the SerialData_Chars event + // the flag will be reset if NativeRead will be called + Uart_Post_SerialData_Chars_Event[uart_num] = false; + } + break; + // Pattern detection used for the WatchChar + case UART_PATTERN_DET: + // only if an event handler is attached + if (Serial_Device_Instance[uart_num][Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::FIELD___callbacksDataReceivedEvent].Dereference() != NULL) + { + // post a managed event with the port index and the watch char event code; uart_num + 1 because UART0 maps to COM1 + PostManagedEvent(EVENT_SERIAL, 0, UART_NUM_TO_PORT_INDEX(uart_num), SerialData_WatchChar); + } + break; + // signal to end the task (UART_EVENT_MAX used) + case UART_EVENT_MAX: + run = false; + break; + // Others + default: + break; + } + } + } + vQueueDelete(Uart_Event_Queue[uart_num]); + vTaskDelete(NULL); +} + +HRESULT Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::NativeDispose___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Get Uart number for serial device + uart_port_t uart_num = (uart_port_t)PORT_INDEX_TO_UART_NUM(pThis[ FIELD___portIndex ].NumericByRef().s4); + // uninstall the driver and send the exit signal to the UART event handling queue + uart_driver_delete(uart_num); + xQueueSend(Uart_Event_Queue[uart_num], (void*)UART_EVENT_MAX, (portTickType)portMAX_DELAY); + Uart_Post_SerialData_Chars_Event[uart_num] = false; + Serial_Device_Instance[uart_num] = NULL; + Esp_Serial_Initialised_Flag[uart_num] = 0; + } + NANOCLR_NOCLEANUP(); +} + +// +// Initialise a new Serial port +// +HRESULT Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Get Uart number for serial device + uart_port_t uart_num = (uart_port_t)PORT_INDEX_TO_UART_NUM(pThis[ FIELD___portIndex ].NumericByRef().s4); + if ( uart_num > UART_NUM_2 || uart_num < 0 ) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // call the configure and abort if not OK + HRESULT res = NativeConfig___VOID(stack); + if (res != S_OK) + { + NANOCLR_SET_AND_LEAVE(res); + } + + // Install driver + esp_err_t esp_err = uart_driver_install(uart_num, + UART_RX_BUFER_SIZE, // rx_buffer_size, + UART_TX_BUFER_SIZE, // tx_buffer_size, not buffered + 20, // queue_size + &Uart_Event_Queue[uart_num], // QueueHandle_t *uart_queue ( none for now ) + 0 // intr_alloc_flags + ); + if ( esp_err != ESP_OK ) + { + ESP_LOGE( TAG, "Failed to install uart driver"); + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // receive the SerialData_Chars events and store the SerialDevice instance + Uart_Post_SerialData_Chars_Event[uart_num] = true; + Serial_Device_Instance[uart_num] = pThis; + + // Create a task to handle UART event from ISR + char task_name[16]; + sprintf(task_name, "uart%d_events", uart_num); + xTaskCreate(uart_event_task, task_name, 2048, (void*)uart_num, 12, NULL); + + // Ensure driver gets unitialized during soft reboot + HAL_AddSoftRebootHandler(Esp32_Serial_UnitializeAll); + Esp_Serial_Initialised_Flag[uart_num] = 1; + + Uart_writeLength[uart_num] = 0; + } + NANOCLR_NOCLEANUP(); +} + +// +// Set up serial port Configuration +// +HRESULT Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::NativeConfig___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + uart_config_t uart_config; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Get Uart number for serial device + uart_port_t uart_num = (uart_port_t)PORT_INDEX_TO_UART_NUM(pThis[ FIELD___portIndex ].NumericByRef().s4); + if ( uart_num > UART_NUM_2 || uart_num < 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // setup configuration + // data bits / baud rate + uart_config.baud_rate = (uart_word_length_t)pThis[ FIELD___baudRate ].NumericByRef().s4; //baudrate + + switch( pThis[ FIELD___dataBits ].NumericByRef().s4 ) //data bit mode + { + case 5: + uart_config.data_bits = UART_DATA_5_BITS; break; + case 6: + uart_config.data_bits = UART_DATA_6_BITS; break; + case 7: + uart_config.data_bits = UART_DATA_7_BITS; break; + case 8: + uart_config.data_bits = UART_DATA_8_BITS; break; + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // parity + switch ((SerialParity)pThis[ FIELD___parity ].NumericByRef().s4) + { + default: + case SerialParity_None : + uart_config.parity = UART_PARITY_DISABLE ; + break; + case SerialParity_Even : + uart_config.parity = UART_PARITY_EVEN ; + break; + case SerialParity_Odd : + uart_config.parity = UART_PARITY_ODD ; + break; + } + + // stop bits + switch ((SerialStopBitCount)pThis[ FIELD___stopBits ].NumericByRef().s4) + { + default: + case SerialStopBitCount_One : + uart_config.stop_bits = UART_STOP_BITS_1; + break; + case SerialStopBitCount_OnePointFive : + uart_config.stop_bits = UART_STOP_BITS_1_5; + break; + case SerialStopBitCount_Two : + uart_config.stop_bits = UART_STOP_BITS_2; + break; + } + + uart_config.rx_flow_ctrl_thresh = 0; + + bool EnableXonXoff = false; + switch ((SerialHandshake)pThis[ FIELD___handshake ].NumericByRef().s4) + { + default: + case SerialHandshake_None : + uart_config.flow_ctrl = UART_HW_FLOWCTRL_DISABLE; + break; + case SerialHandshake_RequestToSend : + uart_config.flow_ctrl = UART_HW_FLOWCTRL_RTS ; + uart_config.rx_flow_ctrl_thresh = 122; + break; + + case SerialHandshake_RequestToSendXOnXOff : + uart_config.flow_ctrl = UART_HW_FLOWCTRL_RTS ; + uart_config.rx_flow_ctrl_thresh = 122; + EnableXonXoff = true; + break; + + case SerialHandshake_XOnXOff : + EnableXonXoff = true; + break; + } + + uart_param_config(uart_num, &uart_config); + + if ( EnableXonXoff ) + uart_set_sw_flow_ctrl(uart_num, true, 20, 40); + + // Map to currently assigned pins + int txPin = Esp32_GetMappedDevicePins(DEV_TYPE_SERIAL, uart_num, 0); + int rxPin = Esp32_GetMappedDevicePins(DEV_TYPE_SERIAL, uart_num, 1); + int rtsPin = Esp32_GetMappedDevicePins(DEV_TYPE_SERIAL, uart_num, 2); + int ctsPin = Esp32_GetMappedDevicePins(DEV_TYPE_SERIAL, uart_num, 3); + + // Don't use RTS/CTS if no hardware handshake enabled + if ( uart_config.flow_ctrl == UART_HW_FLOWCTRL_DISABLE ) + { + rtsPin = UART_PIN_NO_CHANGE; + ctsPin = UART_PIN_NO_CHANGE; + } + + uart_set_pin(uart_num, txPin, rxPin, rtsPin, ctsPin); + + // null pointers and vars + pThis = NULL; + } + NANOCLR_NOCLEANUP(); +} + +// +// Write data into buffer +// +HRESULT Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::NativeWrite___VOID__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + uint8_t* data; + size_t length = 0; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + if(pThis[ FIELD___disposed ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + // dereference the data buffer from the argument + CLR_RT_HeapBlock_Array* dataBuffer = stack.Arg1().DereferenceArray(); + + // get a the pointer to the array by using the first element of the array + data = dataBuffer->GetFirstElement(); + + // get the size of the buffer + length = (size_t)dataBuffer->m_numOfElements; + + // Get Uart number for serial device + uart_port_t uart_num = (uart_port_t)PORT_INDEX_TO_UART_NUM(pThis[ FIELD___portIndex ].NumericByRef().s4); + + + // Write data to ring bufferand start sending + size_t bytesWritten = uart_write_bytes( uart_num, (const char*)data, length); + + // check if all requested bytes were written + if(bytesWritten != length) + { + // not sure if this is the best exception to throw here... + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + + Uart_writeLength[uart_num] += bytesWritten; + + // // need to update the _unstoredBufferLength field in the SerialDeviceOutputStream + // // get pointer to outputStream field + // CLR_RT_HeapBlock* outputStream = pThis[Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::FIELD___outputStream].Dereference(); + + // // get pointer to _unstoredBufferLength field and udpate field value + // outputStream[Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDeviceOutputStream::FIELD___unstoredBufferLength].NumericByRef().s4 = palUart->TxRingBuffer.Length(); + + // null pointers and vars + pThis = NULL; + } + NANOCLR_NOCLEANUP(); +} + +// +// Store - Send buffer and wait +// +HRESULT Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::NativeStore___U4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + if(pThis[ FIELD___disposed ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + // Get Uart number for serial device + uart_port_t uart_num = (uart_port_t)PORT_INDEX_TO_UART_NUM(pThis[ FIELD___portIndex ].NumericByRef().s4); + + // get value for writetimeout + // the way to access this it's somewhat convoluted but it is what it is + // get pointer to the field + CLR_RT_HeapBlock* timeout = &pThis[ Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::FIELD___writeTimeout ]; + + // now get a pointer to the actual value + int64_t* timeoutTicks = Library_corlib_native_System_TimeSpan::GetValuePtr( *timeout ); + + // now get the value in ticks and convert it to milliseconds + int64_t timeoutMillisecondsValue = *timeoutTicks / TIME_CONVERSION__TICKUNITS; + + // Wait for max. writetimeout timespan for data to be sent + esp_err_t esp_err = uart_wait_tx_done( uart_num, (TickType_t) timeoutMillisecondsValue / portTICK_PERIOD_MS); + if (esp_err == ESP_ERR_TIMEOUT) + { + NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); + } + else if (esp_err != ESP_OK) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // return how many bytes were send to the UART + stack.SetResult_U4(Uart_writeLength[uart_num]); + + Uart_writeLength[uart_num] = 0; + + // null pointers and vars + pThis = NULL; + } + NANOCLR_NOCLEANUP(); +} + + +HRESULT Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::NativeRead___U4__SZARRAY_U1__I4__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + uint8_t* data; + size_t dataLength = 0; + + size_t count = 0; + int bytesRead = 0; + size_t toRead = 0; + + InputStreamOptions options = InputStreamOptions_None; + + CLR_RT_HeapBlock* timeout; + int64_t* timeoutTicks; + int64_t timeoutMillisecondsValue; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + if(pThis[ FIELD___disposed ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + // dereference the data buffer from the argument + CLR_RT_HeapBlock_Array* dataBuffer = stack.Arg1().DereferenceArray(); + + // get a the pointer to the array by using the first element of the array + data = dataBuffer->GetFirstElement(); + + // get the length of the data buffer + dataLength = dataBuffer->m_numOfElements; + + // get how many bytes are requested to read + count = stack.Arg2().NumericByRef().s4; + + // get the InputStreamOptions option + options = (InputStreamOptions)stack.Arg3().NumericByRef().s4; + + // Get Uart number for serial device + uart_port_t uart_num = (uart_port_t)PORT_INDEX_TO_UART_NUM(pThis[ FIELD___portIndex ].NumericByRef().s4); + + // Bytes requested to read + toRead = count; + + // is the read ahead option enabled? + if(options == InputStreamOptions_ReadAhead) + { + // yes + // check how many bytes we can store in the buffer argument + size_t bufferedLength = 0; + uart_get_buffered_data_len(uart_num, &bufferedLength); + + if(dataLength < bufferedLength ) + { + // read as many bytes has the buffer can hold + toRead = dataLength; + } + else + { + // read everything that's available in the ring buffer + toRead = bufferedLength; + } + } + + // get value for readtimeout + // the way to access this it's somewhat convoluted but it is what it is + // get pointer to the field + timeout = &pThis[ Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::FIELD___readTimeout ]; + + // now get a pointer to the actual value + timeoutTicks = Library_corlib_native_System_TimeSpan::GetValuePtr( *timeout ); + + // now get the value in ticks and convert it to miliseconds + timeoutMillisecondsValue = *timeoutTicks / TIME_CONVERSION__TICKUNITS; + + // suppress the SerialData_Chars event during the reading of the chars; prevents spamming with the SerialData_Chars event + Uart_Post_SerialData_Chars_Event[uart_num] = false; + bytesRead = uart_read_bytes(uart_num, data, toRead, timeoutMillisecondsValue / portTICK_RATE_MS); + Uart_Post_SerialData_Chars_Event[uart_num] = true; + + if ( bytesRead < 0 ) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + + // return how many bytes were read from the Rx buffer and/or UART + stack.SetResult_U4(bytesRead); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::NativeSetWatchChar___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + if(pThis[ FIELD___disposed ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + // Get Uart number for serial device + uart_port_t uart_num = (uart_port_t)PORT_INDEX_TO_UART_NUM(pThis[ FIELD___portIndex ].NumericByRef().s4); + + // Get the watch char + uint8_t watchChar = (uint8_t)pThis[ FIELD___watchChar ].NumericByRef().u1; + + // Enable pattern detection for the serial device + uart_enable_pattern_det_intr(uart_num, watchChar, 1, 10000, 10, 10); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::get_BytesToRead___U4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + if(pThis[ FIELD___disposed ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + // Get Uart number for serial device + uart_port_t uart_num = (uart_port_t)PORT_INDEX_TO_UART_NUM(pThis[ FIELD___portIndex ].NumericByRef().s4); + + // check how many bytes are in the buffer + size_t bufferedLength = 0; + uart_get_buffered_data_len(uart_num, &bufferedLength); + + // return how many bytes can be read from the Rx buffer + stack.SetResult_U4(bufferedLength); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_serial_native_Windows_Devices_SerialCommunication_SerialDevice::GetDeviceSelector___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // declare the device selector string whose max size is "COM1,COM2,COM3" + terminator + char deviceSelectorString[ 15 ] = "COM1,COM2,COM3"; + + // because the caller is expecting a result to be returned + // we need set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + stack.SetResult_String(deviceSelectorString); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.SerialCommunication/win_dev_serial_native_target.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.SerialCommunication/win_dev_serial_native_target.h new file mode 100644 index 00000000..18bad9df --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.SerialCommunication/win_dev_serial_native_target.h @@ -0,0 +1,11 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIN_DEV_SERIAL_NATIVE_TARGET_H_ +#define _WIN_DEV_SERIAL_NATIVE_TARGET_H_ + +#include + +#endif //_WIN_DEV_SERIAL_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo.cpp new file mode 100644 index 00000000..f6ee56c6 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo.cpp @@ -0,0 +1,26 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#include "win_dev_spi_native_target.h" + + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo::get_MaxClockFrequency___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + stack.SetResult_I4 ( MAX_CLOCK_FREQUENCY ); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo::get_MinClockFrequency___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + stack.SetResult_I4 ( 1000000 ); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiController.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiController.cpp new file mode 100644 index 00000000..f3ed2f04 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiController.cpp @@ -0,0 +1,20 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_spi_native_target.h" + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiController::GetDeviceSelector___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // declare the device selector string whose max size is "SPI1,SPI2" + terminator and init with the terminator + char deviceSelectorString[ 15 ] = { "SPI1,SPI2" }; // HSPI & VSPI + + // because the caller is expecting a result to be returned + // we need set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + stack.SetResult_String(deviceSelectorString); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiDevice.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiDevice.cpp new file mode 100644 index 00000000..13000258 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiDevice.cpp @@ -0,0 +1,437 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +// Esp32 has 4 SPI devices called SPI0, SPI1, HSPI and VSPI +// SPIO, SPI1 are dedicated entirely to flash +// +// HSPI("SPI1") and VSPI("SPI2") are free to use +// +// For maximum speed access the IOMUX must be used ( 80mhz ) +// if pins are through the GPIO matrix the speed is limited to 26.6mhz ( 40mhz half duplex and no dma ) +// +// SPI IOMUX ( direct pins ) +// GPIO Function +// 2 HSPIWP (WP) +// 4 HSPIHD (HD) +// 12 HSPIQ (miso) * +// 13 HSPID (mosi) * +// 14 HSPICLK (clockPin) * +// 15 HSPICS0 (cs) +// +// 5 VSPICS0 (cs) +// 18 VSPICLK (clockPin) * +// 19 VSPIQ (miso) * +// 21 VSPIHD (HD) +// 22 VSPIWP (WP) +// 23 VSPID (mosi) * +// +// The defaults pins for SPI1 are the Wrover SPI display pins +// mosiPin = GPIO_NUM_23, misoPin = GPIO_NUM_25, clockPin = GPIO_NUM_19 +// +// SPI2 - The pins are not assigned so need to be assigned. + +#include +#include +#include +#include +#include "win_dev_spi_native_target.h" +#include "Esp32_DeviceMapping.h" + +static nfSpiBusConfig spiconfig[NUM_SPI_BUSES]; +static bool nfSpiInited = false; + + +// define this type here to make it shorter and improve code readability +typedef Library_win_dev_spi_native_Windows_Devices_Spi_SpiConnectionSettings SpiConnectionSettings; + +// Tag for ESP32 logging +static const char* TAG = "SpiDevice"; + + +// Define this to allow access to device config in spi master driver +struct spi_device_t { + QueueHandle_t trans_queue; + QueueHandle_t ret_queue; + spi_device_interface_config_t cfg; +}; + + +void Remove_Spi_Device(int bus, int deviceIndex) +{ + // Remove device from bus + spi_bus_remove_device( spiconfig[bus].deviceHandles[deviceIndex] ); + spiconfig[bus].deviceHandles[deviceIndex] = 0; + spiconfig[bus].deviceId[deviceIndex] = 0; +} + +int FindFreeDeviceSlotSpi(int bus) +{ + for (int deviceIndex = 0; deviceIndex < MAX_SPI_DEVICES; deviceIndex++) + { + if (spiconfig[bus].deviceHandles[deviceIndex] == 0) return deviceIndex; + } + return -1; +} + +// Unitialise SPI on restart +void Esp32_Spi_UnitializeAll() +{ + for (int bus = 0; bus < NUM_SPI_BUSES; bus++) + { + if (spiconfig[bus].spiBusInited) + { + // Remove any devices + for( int deviceIndex=0; deviceIndex < MAX_SPI_DEVICES; deviceIndex++) + { + if ( spiconfig[bus].deviceHandles[deviceIndex] != 0 ) + Remove_Spi_Device(bus, deviceIndex); + } + + // Delete bus driver + spi_bus_free((spi_host_device_t)bus); + spiconfig[bus].spiBusInited = false; + } + } +} + +// Inialise the SPI Bus +static void InitSpiBus( spi_host_device_t bus) +{ + int busIndex = bus - 1; + + gpio_num_t mosiPin = (gpio_num_t)Esp32_GetMappedDevicePins( DEV_TYPE_SPI, busIndex, 0); + gpio_num_t misoPin = (gpio_num_t)Esp32_GetMappedDevicePins( DEV_TYPE_SPI, busIndex, 1); + gpio_num_t clockPin = (gpio_num_t)Esp32_GetMappedDevicePins( DEV_TYPE_SPI, busIndex, 2); + + spi_bus_config_t bus_config + { + mosi_io_num: mosiPin, // mosi pin + miso_io_num : misoPin, // miso pin + sclk_io_num : clockPin, // Clock + quadwp_io_num : -1, // Quad Write protect + quadhd_io_num : -1, // Quad Hold + max_transfer_sz : 0, // Default max transfer size ( 4096 ) + flags : 0, // SPICOMMON_BUSFLAG_* flags + intr_flags : 0 // Interrupt flags + }; + + esp_err_t ret = spi_bus_initialize(bus, &bus_config, 1); + if ( ret != ESP_OK ) + { + ESP_LOGE( TAG, "Unable to init SPI bus"); + return; + } +} + +// Give a complete low-level SPI configuration from user's managed connectionSettings +spi_device_interface_config_t GetConfig( int bus, CLR_RT_HeapBlock* config) +{ + (void)bus; + + int csPin = config[ SpiConnectionSettings::FIELD___csLine ].NumericByRef().s4; + uint8_t spiMode = (uint8_t)config[ SpiConnectionSettings::FIELD___spiMode ].NumericByRef().s4; + int bitOrder = config[ SpiConnectionSettings::FIELD___bitOrder ].NumericByRef().s4; + int clockHz = config[ SpiConnectionSettings::FIELD___clockFrequency ].NumericByRef().s4; + + // if clock frequency is unset use the maximum frequency + if (clockHz == 0) + { + clockHz = MAX_CLOCK_FREQUENCY; + } + + //ets_printf( "Spi config cspin:%d spiMode:%d bitorder:%d clockHz:%d\n", csPin, spiMode, bitOrder, clockHz); + uint32_t flags = (bitOrder == 1) ? (SPI_DEVICE_TXBIT_LSBFIRST | SPI_DEVICE_RXBIT_LSBFIRST) : 0; + + // Fill in device config + spi_device_interface_config_t dev_config + { + 0, // Command bits + 0, // Address bits + 0, // Dummy bits + spiMode, // SPi Mode + 0, // Duty cycle 50/50 + 0, // cs_ena_pretrans + 0, // cs_ena_posttrans + clockHz, // Clock speed in Hz + 0, // Input_delay_ns + csPin, // Chip select + flags, // SPI_DEVICE flags + 1, // Queue size + 0, // Callback before + 0, // Callback after + }; + + return dev_config; +} + +// +// Add new device and return device index +// return -1 if no more devices avalaible +// +int Add_Spi_Device(int bus, CLR_RT_HeapBlock* pThis) +{ + spi_device_interface_config_t dev_config; + nfSpiBusConfig * pBusConfig = &spiconfig[bus]; + + int deviceIndex = FindFreeDeviceSlotSpi(bus); + // Check if all device slots used + if (deviceIndex < 0) return -1; + + // Get a complete low-level SPI configuration, depending on user's managed parameters + dev_config = GetConfig(bus, pThis[ Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::FIELD___connectionSettings ].Dereference()); + + // Add device to bus + spi_device_handle_t deviceHandle; + if ( spi_bus_add_device( (spi_host_device_t)bus, &dev_config, &deviceHandle ) != ESP_OK ) + { + ESP_LOGE( TAG, "Unable to init SPI device"); + return -1; + } + + // Add next Device + pBusConfig->deviceId[deviceIndex] = pThis[ Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::FIELD___deviceId ].NumericByRef().s4; + pBusConfig->deviceHandles[deviceIndex] = deviceHandle; + + return deviceIndex; +} + +// +// Get the Bus and device index +// return false if error +// +bool GetDevice( CLR_RT_HeapBlock* pThis, uint8_t * pBus, int * pDeviceIndex) +{ + int32_t deviceId = pThis[ Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::FIELD___deviceId ].NumericByRef().s4; + *pBus = (uint8_t)(deviceId / 1000); + + // Find device in spiconfig + for( int index=0; index < MAX_SPI_DEVICES; index++) + { + if ( spiconfig[*pBus].deviceId[index] == deviceId ) + { + // Device found with same deviceId + *pDeviceIndex = index; + return true; + } + } + return false; +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer___VOID__SZARRAY_U1__SZARRAY_U1__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + return NativeTransfer( stack, false ); +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer___VOID__SZARRAY_U2__SZARRAY_U2__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + return NativeTransfer( stack, true ); +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer( CLR_RT_StackFrame& stack, bool data16 ) +{ + NANOCLR_HEADER(); + { + unsigned char * writeData = NULL; + unsigned char * originalReadData = NULL; + unsigned char * readData = NULL; + int writeSize = 0; + int readSize = 0; + + stack.m_customState = 1; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the managed spi connectionSettings object instance + CLR_RT_HeapBlock* pConfig = pThis[ FIELD___connectionSettings ].Dereference(); + + // get bus index and Device index + uint8_t bus; + int deviceIndex; + if ( GetDevice( pThis, &bus, &deviceIndex) == false ) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // get data bit length + int databitLength = pConfig[ SpiConnectionSettings::FIELD___databitLength ].NumericByRef().s4; + if (databitLength <= 0) databitLength = 8; + if ( data16 ) databitLength = 16; + + // dereference the write and read buffers from the arguments + CLR_RT_HeapBlock_Array* writeBuffer = stack.Arg1().DereferenceArray(); + if (writeBuffer != NULL) + { + // grab the pointer to the array by getting the first element of the array + if ( data16 ) + writeData = (unsigned char * )writeBuffer->GetFirstElementUInt16(); + else + writeData = writeBuffer->GetFirstElement(); + + // get the size of the buffer by reading the number of elements in the HeapBlock array + writeSize = writeBuffer->m_numOfElements; + } + + CLR_RT_HeapBlock_Array* readBuffer = stack.Arg2().DereferenceArray(); + if (readBuffer != NULL) + { + // grab the pointer to the array by getting the first element of the array + if ( data16 ) + originalReadData = (unsigned char * )readBuffer->GetFirstElementUInt16(); + else + originalReadData = readBuffer->GetFirstElement(); + + // get the size of the buffer by reading the number of elements in the HeapBlock array + readSize = readBuffer->m_numOfElements; + } + + // Are we using SPI full-duplex for transfer ? + // The SPI doesn't support half duplex operation with DMA and without DMA the receive length is limited to 4 bytes + // So we run in full duplex mode all the time and simulate half duplex mode by creating a larger receive buffer for + // the whole of the transaction and then copying the rx part to original buffer + // For full duplex we just use passed buffers. + bool fullDuplex = (bool)stack.Arg3().NumericByRef().u1; + + int MaxDatalength; + if (fullDuplex) + { + // for full duplex just use largest element + MaxDatalength= (readSize > writeSize)? readSize: writeSize; + readData = originalReadData; + } + else + { + // for Halfduplex its the length of both items + MaxDatalength = writeSize + readSize; + + if (readSize) + { + // Allocate a new read buffer to include total length(DMA capable) + readData = (unsigned char *)heap_caps_malloc(MaxDatalength, MALLOC_CAP_DMA); + if ( readData == 0) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + } + + // Set up SPI Transaction + spi_transaction_t trans_desc; + + trans_desc.flags = 0; + trans_desc.cmd = 0; + trans_desc.addr = 0; + // length - Full duplex is total length, half duplex the TX length + trans_desc.length = databitLength * MaxDatalength; + // rxlength - Full duplex is same as length or 0, half duplex is read length + trans_desc.rxlength = 0; + trans_desc.user = NULL; + trans_desc.tx_buffer = writeData; + trans_desc.rx_buffer = readData; + + // Start tranfer ( this calls spi_device_queue_trans & spi_device_get_trans_result) + // Next release of IDF has a direct plling mode that should be faster + esp_err_t ret = spi_device_transmit( spiconfig[bus].deviceHandles[deviceIndex], &trans_desc); + if ( ret != ESP_OK ) + { + if (!fullDuplex) heap_caps_free(readData); + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // Finish up half duplex + if (!fullDuplex) + { + if (readSize) + { + // Copy the read data + memcpy( originalReadData, readData + writeSize, readSize); + heap_caps_free(readData); + } + } + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); //FAULT_ON_NULL(pThis); + + // get bus index + // this is coded with a multiplication, need to perform and int division to get the number + // see the comments in the SpiDevice() constructor in managed code for details ( 1 or 2 ) + int32_t deviceId = pThis[ FIELD___deviceId ].NumericByRef().s4; + + spi_host_device_t bus = (spi_host_device_t)( deviceId / 1000 ); + + // Check valid bus + if ( bus < HSPI_HOST || bus > VSPI_HOST ) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + if ( !nfSpiInited ) + { + for( int i=0; i +#include + +// # buses but first can't be used as SPI flash +#define NUM_SPI_BUSES 3 +#define MAX_SPI_DEVICES 3 + +// Max clock frequency is 20 MHz +#define MAX_CLOCK_FREQUENCY 20000000 + +struct nfSpiBusConfig +{ + bool spiBusInited; + int deviceId[MAX_SPI_DEVICES]; // Used to find correct device in config + spi_device_handle_t deviceHandles[MAX_SPI_DEVICES]; // Max 3 devices per bus (IDF limit ) +}; + +#endif //_WIN_DEV_SPI_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Wifi/win_dev_wifi_native.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Wifi/win_dev_wifi_native.h new file mode 100644 index 00000000..42fe779c --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Wifi/win_dev_wifi_native.h @@ -0,0 +1,89 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#ifndef _WIN_DEV_WIFI_NATIVE_TARGET_H_ +#define _WIN_DEV_WIFI_NATIVE_TARGET_H_ + +#include +#include +#include +#include + + +struct Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiAdapter +{ + static const int FIELD_STATIC__s_eventListener = 0; + + static const int FIELD___networkInterface = 1; + static const int FIELD___syncLock = 2; + static const int FIELD__AvailableNetworksChanged = 3; + static const int FIELD___disposedValue = 4; + + NANOCLR_NATIVE_DECLARE(DisposeNative___VOID); + NANOCLR_NATIVE_DECLARE(NativeInit___VOID); + NANOCLR_NATIVE_DECLARE(NativeConnect___WindowsDevicesWiFiWiFiConnectionStatus__STRING__STRING__WindowsDevicesWiFiWiFiReconnectionKind); + NANOCLR_NATIVE_DECLARE(NativeDisconnect___VOID); + NANOCLR_NATIVE_DECLARE(NativeScanAsync___VOID); + NANOCLR_NATIVE_DECLARE(GetNativeScanReport___SZARRAY_U1); + NANOCLR_NATIVE_DECLARE(NativeFindWirelessAdapters___STATIC__SZARRAY_U1); + + //--// + + static HRESULT GetNetInterfaceIndex(CLR_RT_StackFrame& stack, int * pNetIndex); +}; + +struct Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiAvailableNetwork +{ + static const int FIELD___bsid = 1; + static const int FIELD___ssid = 2; + static const int FIELD___rssi = 3; + static const int FIELD___networkKind = 4; + + + //--// + +}; + +struct Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiConnectionResult +{ + static const int FIELD___ConnectionStatus = 1; + + + //--// + +}; + +struct Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiEvent +{ + static const int FIELD__EventType = 3; + static const int FIELD__Time = 4; + + + //--// + +}; + +struct Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiEventListener +{ + static const int FIELD__wifiAdapters = 1; + + + //--// + +}; + +struct Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiNetworkReport +{ + static const int FIELD___wifiNetworks = 1; + + + //--// + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Wifi; + +#endif //_WIN_DEV_WIFI_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Wifi/win_dev_wifi_native_Windows_Devices_WIFI_WifiAdapter.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Wifi/win_dev_wifi_native_Windows_Devices_WIFI_WifiAdapter.cpp new file mode 100644 index 00000000..f40c3f9f --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Devices.Wifi/win_dev_wifi_native_Windows_Devices_WIFI_WifiAdapter.cpp @@ -0,0 +1,315 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "win_dev_wifi_native.h" +#include "nf_rt_events_native.h" + +/////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.WiFi (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////// +struct ScanRecord +{ + uint8_t bssid[6]; + uint8_t ssid[33]; + uint8_t rssi; + uint8_t authMode; + uint8_t cypherType; +}; + +/////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.WiFi (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////// +enum WiFiConnectionStatus +{ + AccessRevoked = 0, + InvalidCredential, + NetworkNotAvailable, + Success, + Timeout, + UnspecifiedFailure, + UnsupportedAuthenticationProtocol +}; + +/////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.WiFi (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////// +enum WiFiNetworkKind +{ + Adhoc = 0, + Any, + Infrastructure +}; + + /////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.WiFi (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////// +enum WiFiReconnectionKind +{ + Automatic = 0, + Manual +}; + +HRESULT Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiAdapter::DisposeNative___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + (void)stack; + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiAdapter::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + (void)stack; + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +// +// Pickup Net interface index and do checks +// +HRESULT Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiAdapter::GetNetInterfaceIndex(CLR_RT_StackFrame& stack, int * pNetIndex) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + if(pThis[ Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiAdapter::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + *pNetIndex = pThis[ FIELD___networkInterface ].NumericByRefConst().s4; + } + NANOCLR_NOCLEANUP(); +} + +// +// Connect to Wireless connection to passed SSID / passPhase +// +HRESULT Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiAdapter::NativeConnect___WindowsDevicesWiFiWiFiConnectionStatus__STRING__STRING__WindowsDevicesWiFiWiFiReconnectionKind( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + const char* szSsid; + const char* szPassPhase; + int reconnectionKind; + esp_err_t res; + int netIndex; + + NANOCLR_CHECK_HRESULT( GetNetInterfaceIndex(stack, &netIndex ) ); + + WiFiConnectionStatus Status = Success; + + // Get SSID + szSsid = stack.Arg1().RecoverString(); FAULT_ON_NULL(szSsid); + + // Get Password + szPassPhase = stack.Arg2().RecoverString(); FAULT_ON_NULL(szPassPhase); + + // Reconnect kind + reconnectionKind = stack.Arg3().NumericByRef().s4; + + res = (esp_err_t)Network_Interface_Connect(netIndex, szSsid, szPassPhase, reconnectionKind); + switch(res) + { + case ESP_OK: + Status = Success; + break; + case ESP_ERR_WIFI_SSID: + Status = NetworkNotAvailable; + break; + case ESP_ERR_WIFI_PASSWORD: + Status = InvalidCredential; + break; + case ESP_ERR_WIFI_TIMEOUT: + Status = Timeout; + break; + + default: + case ESP_ERR_WIFI_NOT_INIT: + case ESP_ERR_WIFI_NOT_STARTED: + case ESP_ERR_WIFI_CONN: + Status = UnspecifiedFailure; + break; + } + + // Return value to the managed application + stack.SetResult_I4( Status ); + } + NANOCLR_NOCLEANUP(); +} + +// +// Disconnect WiFi connection +// +HRESULT Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiAdapter::NativeDisconnect___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + int netIndex; + + NANOCLR_CHECK_HRESULT( GetNetInterfaceIndex(stack, &netIndex ) ); + + Network_Interface_Disconnect(netIndex); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiAdapter::NativeScanAsync___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + int netIndex; + + NANOCLR_CHECK_HRESULT( GetNetInterfaceIndex(stack, &netIndex ) ); + + // Start scan + if ( Network_Interface_Start_Scan(netIndex) == false) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + } + } + NANOCLR_NOCLEANUP(); +} + +// +// Stores Ap records to target string. +// if pTarget == 0 then just calculates length of target +// +// unint_8[6] MAC; +// unint_8[33] SSID +// unit8_t RSSI +// +// Return : length in pTarget +int StoreApRecordsToString( uint8_t * pTarget, wifi_ap_record_t * apRecords, uint16_t recordCount ) +{ + int index; + + if ( pTarget != 0 ) + { + // Store record count as first of returned byte[] + *pTarget++ = (uint8_t)recordCount; + + ScanRecord * pScanRec = (ScanRecord *)pTarget; + + for( index=0; index < recordCount; index++) + { + memcpy(pScanRec->bssid, apRecords[index].bssid, 6); + memcpy(pScanRec->ssid, apRecords[index].ssid, 33); + pScanRec->rssi = apRecords[index].rssi; + pScanRec->authMode = apRecords[index].authmode; + pScanRec->cypherType = apRecords[index].pairwise_cipher; + pScanRec++; + } + } + + // Fixed length records so we can calculate length + return (recordCount * sizeof(ScanRecord) + sizeof(uint16_t)); +} + +// private extern WiFiNetworkReport NativeNetworkReport(); +HRESULT Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiAdapter::GetNativeScanReport___SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + // Temporary ap record storage + wifi_ap_record_t * ap_records = 0; + { + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + CLR_RT_HeapBlock_Array* array; + CLR_UINT8* buf; + uint16_t number = 0; + int rlen = 2; + + esp_err_t res = esp_wifi_scan_get_ap_num( &number ); + if ( res != ESP_OK) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + if ( number != 0 ) + { + // Allocate room for ap records + ap_records = (wifi_ap_record_t *)platform_malloc(sizeof(wifi_ap_record_t) * number ); + if (ap_records == 0) NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + + res = esp_wifi_scan_get_ap_records( &number, ap_records); + if ( res != ESP_OK) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // Store AP records in string and return to managed code to sort out + // MAC, SSID, RSSI, Auth mode, + + // Find out how big a string is required + rlen = StoreApRecordsToString( 0, ap_records, number ); + } + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( top, rlen, g_CLR_RT_WellKnownTypes.m_UInt8 )); + array = top.DereferenceArray(); + buf = array->GetFirstElement(); + + // Store into returned uint8 array + StoreApRecordsToString( buf, ap_records, number ); + } + + NANOCLR_CLEANUP(); + + if(ap_records) + { + platform_free(ap_records); + } + + NANOCLR_CLEANUP_END(); +} + +// +// Find wireless adapters in network config +// return count of adapters found +// +int FindWirelessAdaptersStore( uint8_t * pTarget ) +{ + int wirelessCount = 0; + + for( int index=0; index < g_TargetConfiguration.NetworkInterfaceConfigs->Count; index++) + { + HAL_Configuration_NetworkInterface* pNetInterface = g_TargetConfiguration.NetworkInterfaceConfigs->Configs[index]; + + if (pNetInterface->InterfaceType == NetworkInterfaceType_Wireless80211) + { + wirelessCount++; + if ( pTarget != 0) *pTarget++ = (uint8_t)index; + } + } + + return wirelessCount; +} + +HRESULT Library_win_dev_wifi_native_Windows_Devices_WiFi_WiFiAdapter::NativeFindWirelessAdapters___STATIC__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + CLR_RT_HeapBlock_Array* array; + CLR_UINT8* buf; + int rlen; + + // Find number of wireless adapters so we can allocated return array + rlen = FindWirelessAdaptersStore( 0 ); + + // Return interface indexes + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( top, rlen, g_CLR_RT_WellKnownTypes.m_UInt8 )); + array = top.DereferenceArray(); + buf = array->GetFirstElement(); + + // Store adapters indexes in to returned array + FindWirelessAdaptersStore( buf ); + } + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Networking.Sockets/win_net_sockets_native_Windows_Networking_Sockets_SocketNative.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Networking.Sockets/win_net_sockets_native_Windows_Networking_Sockets_SocketNative.cpp new file mode 100644 index 00000000..3492d2bf --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Networking.Sockets/win_net_sockets_native_Windows_Networking_Sockets_SocketNative.cpp @@ -0,0 +1,594 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#include "win_net_sockets_native_target.h" + +// TODO - Check if required, for now just ignore +#define SwapEndianIfBEc16(x) (x) + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::socket___STATIC__I4__I4__I4__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_INT32 family = stack.Arg0().NumericByRef().s4; + CLR_INT32 type = stack.Arg1().NumericByRef().s4; + CLR_INT32 protocol = stack.Arg2().NumericByRef().s4; + + CLR_INT32 nonBlocking = 1; + CLR_INT32 sock = SOCK_socket( family, type, protocol ); + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, sock )); + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, SOCK_ioctl( sock, SOCK_FIONBIO, &nonBlocking ) )); + + stack.SetResult_I4( sock ); + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::bind___STATIC__VOID__OBJECT__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + return BindConnectHelper( stack, true ); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::connect___STATIC__VOID__OBJECT__SZARRAY_U1__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + return BindConnectHelper( stack, false ); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::send___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::recv___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::close___STATIC__I4__OBJECT( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_INT32 handle, ret; + + CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); FAULT_ON_NULL(socket); + + handle = socket[ FIELD__m_Handle ].NumericByRef().s4; + + ret = SOCK_close( handle ); + + //If a socket gets closed, we need to make sure to wake up any threads that are waiting on it. + Events_Set( SYSTEM_EVENT_FLAG_SOCKET ); + + stack.SetResult_I4( ret ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::listen___STATIC__VOID__OBJECT__I4( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); + CLR_INT32 handle; + CLR_INT32 backlog = stack.Arg1().NumericByRef().s4; + CLR_INT32 ret; + + FAULT_ON_NULL(socket); + handle = socket[ FIELD__m_Handle ].NumericByRef().s4; + + ret = SOCK_listen( handle, backlog ); + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, ret )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::accept___STATIC__I4__OBJECT( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); + CLR_INT32 handle; + CLR_INT32 ret; + CLR_INT32 nonBlocking = 1; + + FAULT_ON_NULL(socket); + handle = socket[ FIELD__m_Handle ].NumericByRef().s4; + + + /* Because we could have been a rescheduled call due to a prior call that would have blocked, we need to see + * if our handle has been shutdown before continuing. */ + if (handle == DISPOSED_HANDLE) + { + ThrowError(stack, CLR_E_OBJECT_DISPOSED); + NANOCLR_SET_AND_LEAVE (CLR_E_PROCESS_EXCEPTION); + } + + ret = SOCK_accept( handle, NULL, NULL ); + + if(ret != SOCK_SOCKET_ERROR) + { + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, SOCK_ioctl( ret, SOCK_FIONBIO, &nonBlocking ) )); + } + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, ret )); + + stack.SetResult_I4( ret ); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::getaddrinfo___STATIC__VOID__STRING__BYREF_STRING__BYREF_SZARRAY_SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::shutdown___STATIC__VOID__OBJECT__I4__BYREF_I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::sendto___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::recvfrom___STATIC__I4__OBJECT__SZARRAY_U1__I4__I4__I4__I4__BYREF_SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::getpeername___STATIC__VOID__OBJECT__BYREF_SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::getsockname___STATIC__VOID__OBJECT__BYREF_SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::getsockopt___STATIC__VOID__OBJECT__I4__I4__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::setsockopt___STATIC__VOID__OBJECT__I4__I4__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::poll___STATIC__BOOLEAN__OBJECT__I4__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::ioctl___STATIC__VOID__OBJECT__U4__BYREF_U4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + + + +//--// + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::BindConnectHelper( CLR_RT_StackFrame& stack, bool fBind ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); + CLR_INT32 handle; + SOCK_sockaddr addr; + CLR_UINT32 addrLen = sizeof(addr); + CLR_INT32 ret; + bool fThrowOnWouldBlock = false; + + FAULT_ON_NULL(socket); + handle = socket[ FIELD__m_Handle ].NumericByRef().s4; + + NANOCLR_CHECK_HRESULT(MarshalSockAddress( &addr, addrLen, stack.Arg1() )); + + if(fBind) + { + ret = SOCK_bind( handle, &addr, addrLen ); + } + else + { + ret = SOCK_connect( handle, &addr, addrLen ); + + fThrowOnWouldBlock = (stack.Arg2().NumericByRefConst().s4 != 0); + + if(!fThrowOnWouldBlock && SOCK_getlasterror() == SOCK_EWOULDBLOCK) + { + NANOCLR_SET_AND_LEAVE(S_OK); + } + } + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, ret )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::MarshalSockAddress( CLR_RT_HeapBlock& blkDst, const struct SOCK_sockaddr* addrSrc, CLR_UINT32 addrLenSrc ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* arr = NULL; + + CLR_RT_HeapBlock blkArr; blkArr.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc( blkArr ); + SOCK_sockaddr_in* dst; + SOCK_sockaddr_in* src = (SOCK_sockaddr_in*)addrSrc; + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( blkArr, addrLenSrc, g_CLR_RT_WellKnownTypes.m_UInt8 )); + + arr = blkArr.DereferenceArray(); + + _ASSERTE(arr); + + dst = (SOCK_sockaddr_in*)arr->GetFirstElement(); + + dst->sin_family = SwapEndianIfBEc16(src->sin_family); + dst->sin_port = src->sin_port; + dst->sin_addr.S_un.S_addr = src->sin_addr.S_un.S_addr; + + memcpy(dst->sin_zero, src->sin_zero, sizeof(dst->sin_zero)); + + _ASSERTE(blkDst.DataType() == DATATYPE_BYREF || blkDst.DataType() == DATATYPE_ARRAY_BYREF); + + NANOCLR_CHECK_HRESULT(blkArr.StoreToReference( blkDst, 0 )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::MarshalSockAddress( struct SOCK_sockaddr* addrDst, CLR_UINT32& addrLen, const CLR_RT_HeapBlock& blkSockAddress ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* ptrSockAddress; + SOCK_sockaddr_in* dst = (SOCK_sockaddr_in*)addrDst; + SOCK_sockaddr_in* src; + + ptrSockAddress = blkSockAddress.DereferenceArray(); + FAULT_ON_NULL(ptrSockAddress); + + if(ptrSockAddress->m_numOfElements > addrLen) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + src = (SOCK_sockaddr_in*)ptrSockAddress->GetFirstElement(); + + dst->sin_family = SwapEndianIfBEc16(src->sin_family); + dst->sin_port = src->sin_port; + dst->sin_addr.S_un.S_addr = src->sin_addr.S_un.S_addr; //already in network byte order + + memcpy(dst->sin_zero, src->sin_zero, sizeof(dst->sin_zero)); + + addrLen = ptrSockAddress->m_numOfElements; + + NANOCLR_NOCLEANUP(); +} + +// HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::SendRecvHelper( CLR_RT_StackFrame& stack, bool fSend, bool fAddress ) +// { +// NATIVE_PROFILE_CLR_NETWORK(); +// NANOCLR_HEADER(); + +// CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); +// CLR_INT32 handle; +// CLR_RT_HeapBlock_Array* arrData = stack.Arg1().DereferenceArray(); +// CLR_UINT32 offset = stack.Arg2().NumericByRef().u4; +// CLR_UINT32 count = stack.Arg3().NumericByRef().u4; +// CLR_INT32 flags = stack.Arg4().NumericByRef().s4; +// CLR_INT32 timeout_ms = stack.Arg5().NumericByRef().s4; +// CLR_RT_HeapBlock hbTimeout; + +// CLR_INT64* timeout; +// CLR_UINT8* buf; +// bool fRes = true; +// CLR_INT32 totReadWrite; +// CLR_INT32 ret = 0; + +// FAULT_ON_NULL(socket); +// FAULT_ON_NULL(arrData); + +// handle = socket[ FIELD__m_Handle ].NumericByRef().s4; + +// /* Because we could have been a rescheduled call due to a prior call that would have blocked, we need to see +// * if our handle has been shutdown before continuing. */ +// if (handle == DISPOSED_HANDLE) +// { +// ThrowError( stack, CLR_E_OBJECT_DISPOSED ); +// NANOCLR_SET_AND_LEAVE (CLR_E_PROCESS_EXCEPTION); +// } + +// if(offset + count > arrData->m_numOfElements) NANOCLR_SET_AND_LEAVE(CLR_E_INDEX_OUT_OF_RANGE); + + +// hbTimeout.SetInteger( timeout_ms ); + +// NANOCLR_CHECK_HRESULT(stack.SetupTimeout( hbTimeout, timeout )); + +// // +// // Push "totReadWrite" onto the eval stack. +// // +// if(stack.m_customState == 1) +// { +// stack.PushValueI4( 0 ); + +// stack.m_customState = 2; +// } + +// totReadWrite = stack.m_evalStack[ 1 ].NumericByRef().s4; + +// buf = arrData->GetElement( offset + totReadWrite ); +// count -= totReadWrite; + +// while(count > 0) +// { +// CLR_INT32 bytes = 0; + +// // first make sure we have data to read or ability to write +// while(fRes) +// { +// ret = Helper__SelectSocket( handle, fSend ? 1 : 0 ); + +// if(ret != 0) break; + +// // non-blocking - allow other threads to run while we wait for handle activity +// NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_Socket, fRes )); +// } + +// // timeout expired +// if(!fRes) +// { +// ret = SOCK_SOCKET_ERROR; + +// ThrowError( stack, SOCK_ETIMEDOUT ); + +// NANOCLR_SET_AND_LEAVE( CLR_E_PROCESS_EXCEPTION ); +// } + +// // socket is in the excepted state, so let's bail out +// if(SOCK_SOCKET_ERROR == ret) +// { +// break; +// } + +// if(fAddress) +// { +// struct SOCK_sockaddr addr; +// CLR_UINT32 addrLen = sizeof(addr); +// CLR_RT_HeapBlock& blkAddr = stack.Arg6(); + +// if(fSend) +// { +// NANOCLR_CHECK_HRESULT(MarshalSockAddress( &addr, addrLen, blkAddr )); + +// bytes = SOCK_sendto( handle, (const char*)buf, count, flags, &addr, addrLen ); +// } +// else +// { +// CLR_RT_HeapBlock* pBlkAddr = blkAddr.Dereference(); + +// NANOCLR_CHECK_HRESULT(MarshalSockAddress( &addr, addrLen, *pBlkAddr )); + +// bytes = SOCK_recvfrom( handle, (char*)buf, count, flags, &addr, (int*)&addrLen ); + +// if(bytes != SOCK_SOCKET_ERROR) +// { +// NANOCLR_CHECK_HRESULT(MarshalSockAddress( blkAddr, &addr, addrLen )); +// } +// } +// } +// else +// { +// if(fSend) +// { +// bytes = SOCK_send( handle, (const char*)buf, count, flags ); +// } +// else +// { +// bytes = SOCK_recv( handle, (char*)buf, count, flags ); +// } +// } + +// // send/recv/sendto/recvfrom failed +// if(bytes == SOCK_SOCKET_ERROR) +// { +// CLR_INT32 err = SOCK_getlasterror(); + +// if(err != SOCK_EWOULDBLOCK) +// { +// ret = SOCK_SOCKET_ERROR; +// break; +// } + +// continue; +// } +// // zero recv bytes indicates the handle has been closed. +// else if(!fSend && (bytes == 0)) +// { +// break; +// } + +// buf += bytes; +// totReadWrite += bytes; +// count -= bytes; + +// stack.m_evalStack[ 1 ].NumericByRef().s4 = totReadWrite; + +// // receive returns immediately after receiving bytes. +// if(!fSend && (totReadWrite > 0)) +// { +// break; +// } + +// } + +// stack.PopValue(); // totReadWrite +// stack.PopValue(); // Timeout + +// NANOCLR_CHECK_HRESULT(ThrowOnError( stack, ret )); + +// stack.SetResult_I4( totReadWrite ); + +// NANOCLR_NOCLEANUP(); +// } + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::SockOptHelper( CLR_RT_StackFrame& stack, bool fGet ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); + CLR_INT32 handle; + CLR_INT32 level = stack.Arg1().NumericByRef().s4; + CLR_INT32 optname = stack.Arg2().NumericByRef().s4; + CLR_RT_HeapBlock_Array* arrOpt = stack.Arg3().DereferenceArray(); + char* optval; + CLR_INT32 optlen; + CLR_INT32 ret; + + FAULT_ON_NULL(socket); + handle = socket[ FIELD__m_Handle ].NumericByRef().s4; + + FAULT_ON_NULL(arrOpt); + + optval = (char*)arrOpt->GetFirstElement(); + optlen = arrOpt->m_numOfElements; + + if(fGet) + { + ret = SOCK_getsockopt( handle, level, optname, optval, &optlen ); + _ASSERTE( optlen <= (CLR_INT32)arrOpt->m_numOfElements ); + } + else + { + ret = SOCK_setsockopt( handle, level, optname, optval, optlen ); + } + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, ret )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::SockNameHelper( CLR_RT_StackFrame& stack, bool fPeer ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + CLR_RT_HeapBlock* socket = stack.Arg0().Dereference(); + CLR_INT32 handle; + CLR_INT32 ret; + + struct SOCK_sockaddr addr; + CLR_INT32 addrLen = sizeof(addr); + + FAULT_ON_NULL(socket); + handle = socket[ FIELD__m_Handle ].NumericByRef().s4; + + if(fPeer) + { + ret = SOCK_getpeername( handle, &addr, &addrLen ); + } + else + { + ret = SOCK_getsockname( handle, &addr, &addrLen ); + } + + NANOCLR_CHECK_HRESULT(ThrowOnError( stack, ret )); + + NANOCLR_CHECK_HRESULT(MarshalSockAddress( stack.Arg1(), &addr, addrLen )); + + NANOCLR_NOCLEANUP(); +} + + + + +void Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::ThrowError( CLR_RT_StackFrame& stack, CLR_INT32 errorCode ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + // CLR_RT_HeapBlock& res = stack.m_owningThread->m_currentException; + + // if((Library_corlib_native_System_Exception::CreateInstance( res, g_CLR_RT_WellKnownTypes.m_SocketException, CLR_E_FAIL, &stack )) == S_OK) + // { + // res.Dereference()[ Library_system_sockets_System_Net_Sockets_SocketException::FIELD___errorCode ].SetInteger( errorCode ); + // } +} + +HRESULT Library_win_net_sockets_native_Windows_Networking_Sockets_SocketNative::ThrowOnError( CLR_RT_StackFrame& stack, CLR_INT32 res ) +{ + NATIVE_PROFILE_CLR_NETWORK(); + NANOCLR_HEADER(); + + if(res == SOCK_SOCKET_ERROR) + { + CLR_INT32 err = SOCK_getlasterror(); + + ThrowError( stack, err ); + + NANOCLR_SET_AND_LEAVE( CLR_E_PROCESS_EXCEPTION ); + } + + NANOCLR_NOCLEANUP(); +} \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Networking.Sockets/win_net_sockets_native_target.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Networking.Sockets/win_net_sockets_native_target.h new file mode 100644 index 00000000..e885142e --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Networking.Sockets/win_net_sockets_native_target.h @@ -0,0 +1,13 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#ifndef _WIN_NET_SOCKETS_NATIVE_TARGET_H_ +#define _WIN_NET_SOCKETS_NATIVE_TARGET_H_ + +#include + +#endif //_WIN_NET_SOCKETS_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Storage/win_storage_native_Windows_Storage_Devices_SDCard.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Storage/win_storage_native_Windows_Storage_Devices_SDCard.cpp new file mode 100644 index 00000000..d92723aa --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Storage/win_storage_native_Windows_Storage_Devices_SDCard.cpp @@ -0,0 +1,104 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_storage_native_target.h" +#include +#include +#include + +#include "Esp32_DeviceMapping.h" + +// Defines for Windows.Storage.c +extern "C" +{ + bool Storage_InitSDCardSPI(char * vfsName, int maxFiles, int pin_Miso, int pin_Mosi, int pin_Clk, int pin_Cs); + bool Storage_InitSDCardMMC(char * vfsName, int maxFiles, bool bit1Mode); + bool Storage_UnMountSDCard(); +} + +HRESULT Library_win_storage_native_Windows_Storage_Devices_SDCard::MountMMCNative___STATIC__VOID__BOOLEAN(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + +#if defined(HAL_USE_SDC) + bool bit1Mode = stack.Arg0().NumericByRef().s4; + char mountPoint[] = INDEX0_DRIVE_LETTER; + + // Change fatfs drive letter to mount point D: -> /D + mountPoint[1] = mountPoint[0]; + mountPoint[0] = '/'; + + // Try mounting + if (!Storage_InitSDCardMMC(mountPoint, SDC_MAX_OPEN_FILES, bit1Mode) ) + { + NANOCLR_SET_AND_LEAVE(CLR_E_VOLUME_NOT_FOUND); + } +#else + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); +#endif + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_storage_native_Windows_Storage_Devices_SDCard::MountSpiNative___STATIC__VOID__I4__I4(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + +#if defined(HAL_USE_SDC) + + int spiBus; + uint32_t CSPin; + char mountPoint[] = INDEX0_DRIVE_LETTER; + + // Change fatfs drive letter to mount point D: -> /D + mountPoint[1] = mountPoint[0]; + mountPoint[0] = '/'; + + // Get passed SPi bus number 1 or 2 + spiBus = stack.Arg0().NumericByRef().s4; + + // get Gpio pin for Chip select + CSPin = stack.Arg1().NumericByRef().s4; + + // Get current gpio pins used by SPI device + spiBus--; // Spi devnumber 0 & 1 + int mosiPin = Esp32_GetMappedDevicePins(DEV_TYPE_SPI, spiBus, 0); + int misoPin = Esp32_GetMappedDevicePins(DEV_TYPE_SPI, spiBus, 1); + int clockPin = Esp32_GetMappedDevicePins(DEV_TYPE_SPI, spiBus, 2); + + // Try mounting + if ( !Storage_InitSDCardSPI(mountPoint, SDC_MAX_OPEN_FILES, misoPin, mosiPin, clockPin, CSPin) ) + { + NANOCLR_SET_AND_LEAVE(CLR_E_VOLUME_NOT_FOUND); + } +#else + (void)stack; + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); +#endif + + NANOCLR_NOCLEANUP(); +} + + +HRESULT Library_win_storage_native_Windows_Storage_Devices_SDCard::UnmountNative___STATIC__VOID(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + (void)stack; + +#if defined(HAL_USE_SDC) + + // Unmount SPI device + if (!Storage_UnMountSDCard()) + { + // SDcard not mounted + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + } + +#else + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); +#endif + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Storage/win_storage_native_Windows_Storage_FileIO.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Storage/win_storage_native_Windows_Storage_FileIO.cpp new file mode 100644 index 00000000..4a8bf2c4 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Storage/win_storage_native_Windows_Storage_FileIO.cpp @@ -0,0 +1,677 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "win_storage_native_target.h" +#include +#include +#include + + +// defining these types here to make it shorter and improve code readability +typedef Library_win_storage_native_Windows_Storage_StorageFolder StorageFolder; +typedef Library_win_storage_native_Windows_Storage_StorageFile StorageFile; + +extern "C" +{ + bool Storage_InitSDCardMMC(char * vfsName, int maxFiles, bool bit1Mode); + bool Storage_InitSDCardSPI(char * vfsName, int maxFiles, int pin_Miso, int pin_Mosi, int pin_Clk, int pin_Cs); +}; + +// Queue length for IO task +#define StorageQueueLength 4 + + +////////////////////////////////////////// + +enum FileOperationType { READ_TEXT, WRITE_TEXT, READ_BINARY, WRITE_BINARY, EXIT }; + +struct FileOperation +{ + FileOperationType Operation; + FILE* File; + char* Content; + uint32_t ContentLength; +}; + +struct OperationResult +{ + FRESULT result; +}; + + +// Queues for passing Storage IO operations to thread abd returning results +static QueueHandle_t StorageInputQueue; +static QueueHandle_t StorageResultQueue; + + +char * ConvertToESP32Path(const char * filepath); + + +// Send IO operation to Queue +BaseType_t SendIOtoQueue(FileOperationType type, FILE *file, char * content, uint32_t contentLength) +{ + FileOperation fileIoOperation; + + // setup FileIO operation + fileIoOperation.Operation = type; + fileIoOperation.File = file; + fileIoOperation.Content = content; + fileIoOperation.ContentLength = contentLength; + + return xQueueSendToBack(StorageInputQueue, &fileIoOperation, portMAX_DELAY); +} + +// Wait for Result of IO operation +FRESULT WaitIOResult() +{ + OperationResult result; + + xQueueReceive(StorageResultQueue, &result, portMAX_DELAY); + + return result.result; +} + +// All file IO is serialised by queue job to this IO thread. +// + +// this is the FileIO working thread +// because FatFS is supposed to be atomic we won't have any concurrent threads + +// ReadText working thread +static FRESULT StorageReadText(FileOperation* fileIoOperation ) +{ + FRESULT operationResult; + + // need an extra one for the terminator + uint32_t readLength = fileIoOperation->ContentLength + 1; + + // read string + if (fgets(fileIoOperation->Content, readLength, fileIoOperation->File) ) + { + operationResult = FR_OK; + } + else + { + operationResult = FR_DISK_ERR; + } + + // close file + fclose(fileIoOperation->File); + + return operationResult; +} + + +// WriteBinary working thread +static FRESULT StorageWriteBinary(FileOperation* fileIoOperation) +{ + FRESULT operationResult = FR_DISK_ERR; + size_t bytesWritten; + + bytesWritten = fwrite(fileIoOperation->Content, 1, fileIoOperation->ContentLength, fileIoOperation->File); + if( bytesWritten == fileIoOperation->ContentLength ) + { + // expected number of bytes written + operationResult = FR_OK; + } + + // close file + fclose(fileIoOperation->File); + + return operationResult; +} + +// ReadBinary working thread +static FRESULT StorageReadBinary(FileOperation* fileIoOperation) +{ + FRESULT operationResult = FR_DISK_ERR; + UINT bytesRead; + + bytesRead = fread( fileIoOperation->Content, 1, fileIoOperation->ContentLength, fileIoOperation->File); + + + if( bytesRead == fileIoOperation->ContentLength) + { + // expected number of bytes read + operationResult = FR_OK; + } + + // close file + fclose(fileIoOperation->File); + + return operationResult; +} + + +void StorageIOTask(void *pvParameters) +{ + (void)pvParameters; + + bool bExit = false; + struct FileOperation fileOpMessage; + struct OperationResult operationResult; + + while (!bExit) + { + // Wait for message on Storage Queue + if (xQueueReceive(StorageInputQueue, &fileOpMessage, (TickType_t)10)) + { + switch (fileOpMessage.Operation) + { + case EXIT: + bExit = true; + operationResult.result = FR_OK; + break; + + case READ_TEXT: + operationResult.result = StorageReadText(&fileOpMessage); + break; + + case READ_BINARY: + operationResult.result = StorageReadBinary(&fileOpMessage); + break; + + case WRITE_TEXT: + case WRITE_BINARY: + operationResult.result = StorageWriteBinary(&fileOpMessage); + break; + + default: + operationResult.result = FR_OK; + break; + }; + + // Queue result and fire event + xQueueSend(StorageResultQueue, &operationResult, portMAX_DELAY); + + // fire event for FileIO operation complete + if (fileOpMessage.Operation != EXIT) + Events_Set(SYSTEM_EVENT_FLAG_STORAGE_IO); + } + } + + vTaskDelete(NULL); +} + +void CreateStorageIOTask() +{ + StorageInputQueue = xQueueCreate(StorageQueueLength, sizeof(FileOperation)); + StorageResultQueue = xQueueCreate(StorageQueueLength, sizeof(OperationResult)); + + xTaskCreate(StorageIOTask, "StorageIOTask", 2500, 0, 6, NULL); +} + +void DeleteQueues() +{ + vQueueDelete(StorageInputQueue); + vQueueDelete(StorageResultQueue); +} + +void Storage_Initialize() +{ + // Start IO Task + CreateStorageIOTask(); +} + +void Storage_Uninitialize() +{ + // Close down IO task + SendIOtoQueue(EXIT, 0, 0, 0); + WaitIOResult(); + + DeleteQueues(); +} + +//////////////////////////////////////////////// +// Developer notes: +// Depending on the content size these operations have the potential to be a long running ones as the string or buffer is written to the storage. +// Despite we are not (yet!) async this is better handled by spawning a thread where the actual data transfer occurs and not blocking the execution. +// The underlying RTOS inheritably takes care of making this happen "in the background". +// When the operation is completed a CLR event is fired and the thread execution resumes. +// Being hard to estimate the expected duration of the operation (depends on storage hardware, CPU clock, transfer speed, etc) +// the timeout is set to an infinite timeout +// the catch is that the working thread MUST ALWAYS return at some point +//////////////////////////////////////////////// + +HRESULT Library_win_storage_native_Windows_Storage_FileIO::WriteBytes___STATIC__VOID__WindowsStorageIStorageFile__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_Array* bufferArray; + CLR_RT_HeapBlock hbTimeout; + CLR_INT64* timeout; + bool eventResult = true; + + char* buffer; + uint32_t bufferLength; + + const TCHAR* filePath; + char * workingPath = NULL; + FILE* file; + FRESULT operationResult; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the buffer + bufferArray = stack.Arg1().DereferenceArray(); + + buffer = (char*)bufferArray->GetFirstElement(); + + bufferLength = bufferArray->m_numOfElements; + + // get a pointer to the file path + filePath = (TCHAR*)pThis[ StorageFile::FIELD___path ].DereferenceString()->StringText(); + + // !! need to cast to CLR_INT64 otherwise it wont setup a proper timeout infinite + hbTimeout.SetInteger((CLR_INT64)-1); + + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks( hbTimeout, timeout )); + + if(stack.m_customState == 1) + { + // open file (which is supposed to already exist) + // need to use FA_OPEN_ALWAYS("w+") because we are writting the file content from start + workingPath = ConvertToESP32Path(filePath); + file = fopen(workingPath, "w+"); + if(file == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + } + else + { + // protect the StorageFile and the content buffer from GC so the working thread can access those + CLR_RT_ProtectFromGC gcStorageFile( *pThis ); + CLR_RT_ProtectFromGC gcContent( *bufferArray ); + + // setup FileIO operation + if ( SendIOtoQueue(WRITE_BINARY, file, buffer, bufferLength) == errQUEUE_FULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } + + // bump custom state + stack.m_customState = 2; + } + } + + while(eventResult) + { + // non-blocking wait allowing other threads to run while we wait for the write operation to complete + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_StorageIo, eventResult )); + + if(eventResult) + { + // event occurred + operationResult = WaitIOResult(); + + if(operationResult == FR_DISK_ERR) + { + NANOCLR_SET_AND_LEAVE( CLR_E_FILE_IO ); + } + else if(operationResult == FR_NO_FILE) + { + NANOCLR_SET_AND_LEAVE( CLR_E_FILE_NOT_FOUND ); + } + else if(operationResult == FR_INVALID_DRIVE) + { + // failed to change drive + NANOCLR_SET_AND_LEAVE(CLR_E_VOLUME_NOT_FOUND); + } + + // done here + break; + } + else + { + NANOCLR_SET_AND_LEAVE( CLR_E_TIMEOUT ); + } + } + + // pop timeout heap block from stack + stack.PopValue(); + + NANOCLR_CLEANUP(); + + // free buffer memory, if allocated + if (workingPath != NULL) + { + platform_free(workingPath); + } + + NANOCLR_CLEANUP_END(); +} + +HRESULT Library_win_storage_native_Windows_Storage_FileIO::WriteText___STATIC__VOID__WindowsStorageIStorageFile__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_String* content; + CLR_RT_HeapBlock hbTimeout; + CLR_INT64* timeout; + bool eventResult = true; + + const TCHAR* filePath; + char * workingPath = NULL; + FILE * file; + FRESULT operationResult; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the content + content = stack.Arg1().DereferenceString(); + + // get a pointer to the file path + filePath = (TCHAR*)pThis[ StorageFile::FIELD___path ].DereferenceString()->StringText(); + + // !! need to cast to CLR_INT64 otherwise it wont setup a proper timeout infinite + hbTimeout.SetInteger((CLR_INT64)-1); + + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks( hbTimeout, timeout )); + + if(stack.m_customState == 1) + { + + // open file (which is supposed to already exist) + // need to use FA_OPEN_ALWAYS("w+") because we are writting the file content from start + workingPath = ConvertToESP32Path(filePath); + file = fopen(workingPath, "w+" ); + if(file == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + } + else + { + // protect the StorageFile and the content buffer from GC so the working thread can access those + CLR_RT_ProtectFromGC gcStorageFile( *pThis ); + CLR_RT_ProtectFromGC gcContent( *content ); + + if (SendIOtoQueue(WRITE_TEXT, file, (char*)content->StringText(), hal_strlen_s(content->StringText())) == errQUEUE_FULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } + + // bump custom state + stack.m_customState = 2; + } + } + + while(eventResult) + { + // non-blocking wait allowing other threads to run while we wait for the write operation to complete + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_StorageIo, eventResult )); + + if(eventResult) + { + // event occurred + operationResult = WaitIOResult(); + + if(operationResult == FR_DISK_ERR) + { + NANOCLR_SET_AND_LEAVE( CLR_E_FILE_IO ); + } + else if(operationResult == FR_NO_FILE) + { + NANOCLR_SET_AND_LEAVE( CLR_E_FILE_NOT_FOUND ); + } + else if(operationResult == FR_INVALID_DRIVE) + { + // failed to change drive + NANOCLR_SET_AND_LEAVE(CLR_E_VOLUME_NOT_FOUND); + } + + // done here + break; + } + else + { + NANOCLR_SET_AND_LEAVE( CLR_E_TIMEOUT ); + } + } + + // pop timeout heap block from stack + stack.PopValue(); + + NANOCLR_CLEANUP(); + + // free buffer memory, if allocated + if (workingPath != NULL) + { + platform_free(workingPath); + } + + NANOCLR_CLEANUP_END(); +} + +HRESULT Library_win_storage_native_Windows_Storage_FileIO::ReadBufferNative___STATIC__VOID__WindowsStorageIStorageFile__BYREF_SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock hbTimeout; + CLR_INT64* timeout; + bool eventResult = true; + + const TCHAR* filePath; + char * workingPath = NULL; + + FILE* file; + struct stat fileStat; + FRESULT operationResult; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // !! need to cast to CLR_INT64 otherwise it wont setup a proper timeout infinite + hbTimeout.SetInteger((CLR_INT64)-1); + + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks( hbTimeout, timeout )); + + // get a pointer to the file path + filePath = (TCHAR*)pThis[ StorageFile::FIELD___path ].DereferenceString()->StringText(); + + if(stack.m_customState == 1) + { + // protect the StorageFile from GC + CLR_RT_ProtectFromGC gcStorageFile( *pThis ); + + // open file (which is supposed to already exist) + // need to use FA_OPEN_EXISTING("r") because we are reading an existing file content from start + workingPath = ConvertToESP32Path(filePath); + file = fopen(workingPath, "r"); + if(file == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + } + else + { + // get file details + stat(workingPath, &fileStat); + + CLR_RT_HeapBlock buffer; + buffer.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc2( buffer ); + + // create a new byte array with the appropriate size (and type) + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance(buffer, (CLR_INT32)fileStat.st_size, g_CLR_RT_WellKnownTypes.m_UInt8)); + + // store this to the argument passed byref + NANOCLR_CHECK_HRESULT(buffer.StoreToReference( stack.Arg1(), 0 )); + + // get a pointer to the buffer array to improve readability on the code ahead + CLR_RT_HeapBlock_Array* bufferArray = buffer.DereferenceArray(); + + if (SendIOtoQueue(READ_BINARY, file, (char*)bufferArray->GetFirstElement(), bufferArray->m_numOfElements) == errQUEUE_FULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } + + // bump custom state + stack.m_customState = 2; + } + } + + while(eventResult) + { + // non-blocking wait allowing other threads to run while we wait for the write operation to complete + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_StorageIo, eventResult )); + + if(eventResult) + { + // event occurred + operationResult = WaitIOResult(); + + if(operationResult == FR_DISK_ERR) + { + NANOCLR_SET_AND_LEAVE( CLR_E_FILE_IO ); + } + else if(operationResult == FR_NO_FILE) + { + NANOCLR_SET_AND_LEAVE( CLR_E_FILE_NOT_FOUND ); + } + else if(operationResult == FR_INVALID_DRIVE) + { + // failed to change drive + NANOCLR_SET_AND_LEAVE(CLR_E_VOLUME_NOT_FOUND); + } + + // done here + break; + } + else + { + NANOCLR_SET_AND_LEAVE( CLR_E_TIMEOUT ); + } + } + + // pop timeout heap block from stack + stack.PopValue(); + + NANOCLR_CLEANUP(); + + // free buffer memory, if allocated + if (workingPath != NULL) + { + platform_free(workingPath); + } + + NANOCLR_CLEANUP_END(); +} + +HRESULT Library_win_storage_native_Windows_Storage_FileIO::ReadTextNative___STATIC__VOID__WindowsStorageIStorageFile__BYREF_STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock hbTimeout; + CLR_INT64* timeout; + bool eventResult = true; + + const TCHAR* filePath; + char * workingPath = NULL; + + FILE * file; + struct stat fileStat; + FRESULT operationResult; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // !! need to cast to CLR_INT64 otherwise it wont setup a proper timeout infinite + hbTimeout.SetInteger((CLR_INT64)-1); + + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks( hbTimeout, timeout )); + + // get a pointer to the file path + filePath = (TCHAR*)pThis[ StorageFile::FIELD___path ].DereferenceString()->StringText(); + + if(stack.m_customState == 1) + { + // protect the StorageFile and the content buffer from GC so the working thread can access those + CLR_RT_ProtectFromGC gcStorageFile( *pThis ); + + // open file (which is supposed to already exist) + // need to use FA_OPEN_EXISTING("r") because we are reading an existing file content from start + workingPath = ConvertToESP32Path(filePath); + file = fopen(workingPath, "r"); + if(file == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + } + else + { + // get file details + stat(workingPath, &fileStat); + + // create a new string object with the appropriate size + CLR_RT_HeapBlock hbText; + hbText.SetObjectReference( NULL ); + CLR_RT_ProtectFromGC gc( hbText ); + + CLR_RT_HeapBlock_String* textString = CLR_RT_HeapBlock_String::CreateInstance( hbText, (CLR_UINT32)fileStat.st_size ); + FAULT_ON_NULL(textString); + + // store this to the argument passed byref + NANOCLR_CHECK_HRESULT(hbText.StoreToReference( stack.Arg1(), 0 )); + + // get a pointer to the buffer array to improve readability on the code ahead + hbText.DereferenceString(); + + if ( SendIOtoQueue(READ_TEXT, file, (char*)textString->StringText(), fileStat.st_size) == errQUEUE_FULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_PROCESS_EXCEPTION); + } + + // bump custom state + stack.m_customState = 2; + } + } + + while(eventResult) + { + // non-blocking wait allowing other threads to run while we wait for the write operation to complete + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_StorageIo, eventResult )); + + if(eventResult) + { + // event occurred + operationResult = WaitIOResult(); + + if(operationResult == FR_DISK_ERR) + { + NANOCLR_SET_AND_LEAVE( CLR_E_FILE_IO ); + } + else if(operationResult == FR_NO_FILE) + { + NANOCLR_SET_AND_LEAVE( CLR_E_FILE_NOT_FOUND ); + } + else if(operationResult == FR_INVALID_DRIVE) + { + // failed to change drive + NANOCLR_SET_AND_LEAVE(CLR_E_VOLUME_NOT_FOUND); + } + + // done here + break; + } + else + { + NANOCLR_SET_AND_LEAVE( CLR_E_TIMEOUT ); + } + } + + // pop timeout heap block from stack + stack.PopValue(); + + NANOCLR_CLEANUP(); + + // free buffer memory, if allocated + if (workingPath != NULL) + { + platform_free(workingPath); + } + + NANOCLR_CLEANUP_END(); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Storage/win_storage_native_Windows_Storage_StorageFile.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Storage/win_storage_native_Windows_Storage_StorageFile.cpp new file mode 100644 index 00000000..7ab328fb --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Storage/win_storage_native_Windows_Storage_StorageFile.cpp @@ -0,0 +1,194 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_storage_native_target.h" + +extern char * ConvertToESP32Path(const char * filepath); +extern uint64_t GetFileTimeFromPath(char * path); + +HRESULT Library_win_storage_native_Windows_Storage_StorageFile::DeleteFileNative___VOID(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + + char* workingPath = NULL; + const char* managedPath; + int operationResult; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the path in managed field + managedPath = pThis[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___path].DereferenceString()->StringText(); + + // Convert to ESP32 form path ( linux like ) + // return allocated converted path, must be freed + workingPath = ConvertToESP32Path(managedPath); + + // Delete folder, 0=succesfull + operationResult = unlink(workingPath); + if (operationResult < 0) operationResult = errno; + if (operationResult != 0) + { + // folder doesn't exist + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + } + + NANOCLR_CLEANUP(); + + // free buffer memory, if allocated + if (workingPath != NULL) + { + platform_free(workingPath); + } + + NANOCLR_CLEANUP_END(); + +} + +HRESULT Library_win_storage_native_Windows_Storage_StorageFile::RenameFileNative___VOID__STRING(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + + char* workingPath = NULL; + char* desiredWorkingPath = NULL; + const char* managedPath; + const char* desiredPath; + int operationResult; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the path in managed field + managedPath = pThis[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___path].DereferenceString()->StringText(); + + // Convert to ESP32 form path ( linux like ) + // return allocated converted path, must be freed + workingPath = ConvertToESP32Path(managedPath); + + // get a pointer to the desired folder path + desiredPath = stack.Arg1().DereferenceString()->StringText(); + desiredWorkingPath = ConvertToESP32Path(desiredPath); + + // rename folder, 0=succesfull + operationResult = rename(workingPath, desiredWorkingPath); + if (operationResult < 0) operationResult = errno; + if (operationResult == ENOENT) + { + // Invalid path/file not found + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + } + else if (operationResult == EEXIST) + { + // file already exists + NANOCLR_SET_AND_LEAVE(CLR_E_PATH_ALREADY_EXISTS); + } + else if (operationResult != 0) + { + // Some other error + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_IO); + } + + NANOCLR_CLEANUP(); + + // free buffer memory, if allocated + if (workingPath != NULL) + { + platform_free(workingPath); + } + if (desiredWorkingPath != NULL) + { + platform_free(desiredWorkingPath); + } + + NANOCLR_CLEANUP_END(); +} + +HRESULT Library_win_storage_native_Windows_Storage_StorageFile::GetFileFromPathNative___STATIC__WindowsStorageStorageFile__STRING__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Index storageFileTypeDef; + CLR_RT_HeapBlock* storageFile; + + const char* fileName; + const char* managedfilePath; + char * workingPath = NULL; + + static struct stat fileInfo; + + int operationResult; + + // get a pointer to the file path + managedfilePath = stack.Arg0().DereferenceString()->StringText(); + + // get a pointer to the file name + fileName = stack.Arg1().DereferenceString()->StringText(); + + workingPath = ConvertToESP32Path(managedfilePath); + + // check if path exists + operationResult = stat(workingPath, &fileInfo); + if(operationResult < 0) + { + operationResult = errno; + } + + if( operationResult == ENOENT ) + { + // path doesn't exist + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + } + + + if( operationResult == 0 ) + { + // Is this a file + if (fileInfo.st_mode & S_IFREG) + { + // path represents a file, we are good + + // compose return object + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef("StorageFile", "Windows.Storage", storageFileTypeDef); + + // create a + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(stack.PushValue(), storageFileTypeDef)); + + // get a handle to the storage file + storageFile = stack.TopValue().Dereference(); + + // file name + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance(storageFile[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___name], fileName)); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance(storageFile[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___path], managedfilePath)); + + // get the date time details and fill in the managed field + // get a reference to the dateCreated managed field... + CLR_RT_HeapBlock& dateFieldRef = storageFile[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___dateCreated]; + CLR_INT64* pRes = (CLR_INT64*)&dateFieldRef.NumericByRef().s8; + + // get the date time details and fill in the managed field + // compute file date + // ...and set it + *pRes = GetFileTimeFromPath(workingPath); + } + else + { + // path exists but it's a folder + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + } + } + + + NANOCLR_CLEANUP(); + + // free buffer memory, if allocated + if (workingPath != NULL) + { + platform_free(workingPath); + } + + NANOCLR_CLEANUP_END(); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Storage/win_storage_native_Windows_Storage_StorageFolder.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Storage/win_storage_native_Windows_Storage_StorageFolder.cpp new file mode 100644 index 00000000..754adc4e --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Storage/win_storage_native_Windows_Storage_StorageFolder.cpp @@ -0,0 +1,1158 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_storage_native_target.h" +#include +#include +#include +#include +#include "dirent.h" + +// +// Converts from windows type path "c:\folder\folder\file.ext" +// to linux type path used in ESP32 VFS "/c/folder/folder/file.exe +// where /c is the mount point +// +char * ConvertToESP32Path(const char * filepath) +{ + char * startPath = NULL; + char * path = NULL; + + int pathlen = hal_strlen_s(filepath); + startPath = (char*)platform_malloc(pathlen + 1); + path = startPath; + hal_strcpy_s(path, pathlen + 1, filepath); + + if (hal_strlen_s(path) >= 2) + { + // Map Drive: -> /C + char drive = *path; + *path++ = '/'; + *path++ = drive; + + // Convert '\' to '/' + while (*path) + { + if (*path == '\\') + *path++ = '/'; + else + path++; + } + } + + return startPath; +} + +void CombinePath(char * outpath, const char * path1, const char * path2) +{ + strcat(outpath, path1); + + // Add "\" to path if required + if (outpath[hal_strlen_s(outpath) - 1] != '\\') + { + strcat(outpath, "\\"); + } + strcat(outpath, path2); +} + +SYSTEMTIME GetDateTime(time_t * time) +{ + SYSTEMTIME fileTime; + + memset(&fileTime, 0, sizeof(SYSTEMTIME)); + + tm * ptm = gmtime(time); + + // Year from 1601 + fileTime.wYear = ptm->tm_year + 1900; // from Year based 1900 + // Month 1-12 + fileTime.wMonth = ptm->tm_mon + 1; // from Month 0-11 + // Day of month 1 - 31 + fileTime.wDay = ptm->tm_mday; + // Day of week 0 = Sunday + fileTime.wDayOfWeek = ptm->tm_wday; // 0 = Sunday + // Hour 0 to 23. + fileTime.wHour = ptm->tm_hour; + // Minutes 0 to 59. + fileTime.wMinute = ptm->tm_min; + // seconds 0 to 59 + fileTime.wSecond = ptm->tm_sec; + + return fileTime; +} + +uint64_t GetFileTimeFromPath(char * path) +{ + char * workingPath = NULL; + struct stat fileInfo; + SYSTEMTIME fileInfoTime; + + // Convert folder path back to ESP32 VFS format so + // we can stat folder + workingPath = ConvertToESP32Path(path); + + memset(&fileInfo, 0, sizeof(fileInfo)); + + // compute folder/file date/time + if (stat(workingPath, &fileInfo) == 0) + { + fileInfoTime = GetDateTime(&fileInfo.st_ctime); + } + else + { + // Spiffs don't have stat so zero date/time + memset(&fileInfoTime, 0, sizeof(SYSTEMTIME)); + // Make it a valid date + fileInfoTime.wYear = 1900; + fileInfoTime.wMonth = 1; + fileInfoTime.wDay = 1; + } + + if (workingPath != NULL) + { + platform_free(workingPath); + } + + return HAL_Time_ConvertFromSystemTime(&fileInfoTime); +} + + +HRESULT Library_win_storage_native_Windows_Storage_StorageFolder::GetRemovableStorageFoldersNative___SZARRAY_WindowsStorageStorageFolder( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + char* stringBuffer; + uint32_t driveCount = 0; + char workingDrive[sizeof(DRIVE_PATH_LENGTH)]; + uint16_t driveIterator = 0; + + bool sdCardDrivePresent = false; + + CLR_RT_HeapBlock* storageFolder; + CLR_RT_TypeDef_Index storageFolderTypeDef; + CLR_RT_HeapBlock* hbObj; + CLR_RT_HeapBlock& top = stack.PushValue(); + + + #if HAL_USE_SDC + // add count + driveCount++; + + // Esp32 doesn't currently have card present so make always true + sdCardDrivePresent = true; + #endif + + // start composing the reply + // find type definition, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef( "StorageFolder", "Windows.Storage", storageFolderTypeDef ); + + // create an array of + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( top, driveCount, storageFolderTypeDef )); + + if(driveCount > 0) + { + // there are driver present and enumerated + + // get a pointer to the first object in the array (which is of type ) + storageFolder = (CLR_RT_HeapBlock*)top.DereferenceArray()->GetFirstElement(); + + // create an instance of + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*storageFolder, storageFolderTypeDef)); + + // loop until we've loaded all the possible drives + // because we are iterating through an enum, need to use its integer values + for(; driveIterator < SUPPORTED_DRIVES_COUNT; driveIterator++ ) + { + // fill the folder name and path + if (driveIterator == 0 && sdCardDrivePresent == true ) + { + memcpy(workingDrive, INDEX0_DRIVE_PATH, DRIVE_PATH_LENGTH); + } + else + { + // skip this drive type + continue; + } + + // dereference the object in order to reach its fields + hbObj = storageFolder->Dereference(); + + // set the managed fields + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( hbObj[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___name ], workingDrive )); + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( hbObj[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path ], workingDrive )); + + // malloc stringBuffer to work with FS + stringBuffer = (char*)platform_malloc(FF_LFN_BUF + 1); + + // sanity check for successfull malloc + if(stringBuffer == NULL) + { + // failed to allocate memory + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + else + { + // clear buffer + memset(stringBuffer, 0, FF_LFN_BUF + 1); + + // TODO call FATFS method for this as function not present in VFS + // read the drive volume label + // don't bother checking the result, if anything goes wrong we'll end up with an empty string which is OK +// f_getlabel(workingDrive, stringBuffer, NULL); + + // add the driver letter separated it with an empty space, if the volume label isn't empty + if(*stringBuffer != '\0') + { + strcat(stringBuffer, " "); + } + strcat(stringBuffer, "("); + strcat(stringBuffer, workingDrive); + strcat(stringBuffer, ")"); + + // set the field with the volume label + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( hbObj[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___name ], stringBuffer )); + + + // free stringBuffer + platform_free(stringBuffer); + } + + // move pointer to the next folder item + storageFolder++; + } + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_storage_native_Windows_Storage_StorageFolder::GetInternalStorageFoldersNative___SZARRAY_WindowsStorageStorageFolder(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + { + char workingDrive[sizeof(DRIVE_PATH_LENGTH)]; + + uint32_t driveCount = 0; + + CLR_RT_HeapBlock* storageFolder; + CLR_RT_TypeDef_Index storageFolderTypeDef; + CLR_RT_HeapBlock* hbObj; + CLR_RT_HeapBlock& top = stack.PushValue(); + + // One internal drive + driveCount++; + + // start composing the reply + // find type definition, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef("StorageFolder", "Windows.Storage", storageFolderTypeDef); + + // create an array of + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance(top, driveCount, storageFolderTypeDef)); + + if (driveCount > 0) + { + // get a pointer to the first object in the array (which is of type ) + storageFolder = (CLR_RT_HeapBlock*)top.DereferenceArray()->GetFirstElement(); + + // create an instance of + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*storageFolder, storageFolderTypeDef)); + + // dereference the object in order to reach its fields + hbObj = storageFolder->Dereference(); + + memcpy(workingDrive, INTERNAL_DRIVE_PATH, DRIVE_PATH_LENGTH); + + // set the managed fields + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance(hbObj[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___name], workingDrive)); + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance(hbObj[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path], workingDrive)); + } + } + NANOCLR_NOCLEANUP(); +} + + +HRESULT Library_win_storage_native_Windows_Storage_StorageFolder::GetStorageFoldersNative___SZARRAY_WindowsStorageStorageFolder( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Index storageFolderTypeDef; + CLR_RT_HeapBlock* storageFolder; + CLR_RT_HeapBlock* hbObj; + + const char* managedPath; + + DIR * dir = NULL; + struct dirent * dirInfo; + + uint16_t directoryCount = 0; + char* stringBuffer = NULL; + char* workingBuffer = NULL; + char * workingPath = NULL; + + CLR_RT_HeapBlock& top = stack.PushValue(); + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the path in managed field + managedPath = pThis[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path ].DereferenceString()->StringText(); + + // Convert to ESP32 form path for VFS ( linux like ) + // returns allocated converted path, must be freed + workingPath = ConvertToESP32Path(managedPath); + + // open directory + dir = opendir(workingPath); + if(dir) + { + // need to perform this in two steps + // 1st: count the directory objects + // 2nd: create the array items with each directory object + + // perform 1st pass + for (;;) + { + // read next directory item + dirInfo = readdir(dir); + + // break on error or at end of dir + if (dirInfo == NULL) + { + break; + } + + // check if this is a directory + // but skip if: + if (dirInfo->d_type == DT_DIR) + { + directoryCount++; + } + } + + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef( "StorageFolder", "Windows.Storage", storageFolderTypeDef ); + + // create an array of + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance( top, directoryCount, storageFolderTypeDef )); + + // get a pointer to the first object in the array (which is of type ) + storageFolder = (CLR_RT_HeapBlock*)top.DereferenceArray()->GetFirstElement(); + + if(directoryCount > 0) + { + // allocate memory for buffers + stringBuffer = (char*)platform_malloc(FF_LFN_BUF + 1); + workingBuffer = (char*)platform_malloc(2 * FF_LFN_BUF + 1); + + // sanity check for successfull malloc + if(stringBuffer == NULL || workingBuffer == NULL) + { + // failed to allocate memory + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // perform 2nd pass + // need to rewind the directory read index first + rewinddir(dir); + + for (;;) + { + // read next directory item + dirInfo = readdir(dir); + + // break on error or at end of dir + if (dirInfo == NULL) + { + break; + } + + // check if this is a directory + // but skip if: + if (dirInfo->d_type == DT_DIR) + { + // create an instance of + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*storageFolder, storageFolderTypeDef)); + + // dereference the object in order to reach its fields + hbObj = storageFolder->Dereference(); + + // directory name + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( hbObj[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___name ], dirInfo->d_name)); + + // clear working buffer + memset(workingBuffer, 0, 2 * FF_LFN_BUF + 1); + + // compose return directory path + CombinePath(workingBuffer, managedPath, (const char*)dirInfo->d_name); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( hbObj[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path ], workingBuffer )); + + // get a reference to the dateCreated managed field... + CLR_RT_HeapBlock& dateFieldRef = hbObj[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___dateCreated ]; + CLR_INT64* pRes = (CLR_INT64*)&dateFieldRef.NumericByRef().s8; + // ...and set it + *pRes = GetFileTimeFromPath(workingBuffer); + + // move the storage folder pointer to the next item in the array + storageFolder++; + } + } + } + + + } + else + { + // error or directory empty + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef("StorageFolder", "Windows.Storage", storageFolderTypeDef); + + // create an array of + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance(top, directoryCount, storageFolderTypeDef)); + } + + NANOCLR_CLEANUP(); + + if (dir) + { + // close directory + closedir(dir); + } + + // free buffers memory, if allocated + if(stringBuffer != NULL) + { + platform_free(stringBuffer); + } + if(workingBuffer != NULL) + { + platform_free(workingBuffer); + } + if (workingPath != NULL) + { + platform_free(workingPath); + } + + NANOCLR_CLEANUP_END(); +} + + + +HRESULT Library_win_storage_native_Windows_Storage_StorageFolder::GetStorageFilesNative___SZARRAY_WindowsStorageStorageFile__U4__U4(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Index storageFileTypeDef; + CLR_RT_HeapBlock* storageFile; + CLR_RT_HeapBlock* hbObj; + + const char* managedPath; + char * workingPath = NULL; + + uint32_t startIndex; + uint32_t maxItemsToRetrieve; + uint32_t itemIndex = 0; + + DIR * dir = NULL; + struct dirent * dirInfo; + uint16_t fileCount = 0; + char* stringBuffer = NULL; + char* workingBuffer = NULL; + + CLR_RT_HeapBlock& top = stack.PushValue(); + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get start index + startIndex = stack.Arg1().NumericByRef().u4; + + // get max items to retrieve + maxItemsToRetrieve = stack.Arg2().NumericByRef().u4; + + + // get a pointer to the path in managed field + managedPath = pThis[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path].DereferenceString()->StringText(); + + // Convert to ESP32 form path ( linux like ) + // return allocated converted path, must be freed + workingPath = ConvertToESP32Path(managedPath); + + dir = opendir(workingPath); + if (dir) + { + // need to perform this in two steps + // 1st: count the file objects + // 2nd: create the array items with each file object + + // perform 1st pass + for (;;) + { + // read next directory item + dirInfo = readdir(dir); + + // break on error or at end of dir + if (dirInfo == NULL) + { + break; + } + + // check if this is a file + // but skip if diretory: + if (dirInfo->d_type == DT_REG) + { + // check if this file is within the requested parameters + if ((itemIndex >= startIndex) && + (fileCount < maxItemsToRetrieve)) + { + fileCount++; + } + + itemIndex++; + } + } + + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef("StorageFile", "Windows.Storage", storageFileTypeDef); + + // create an array of + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance(top, fileCount, storageFileTypeDef)); + + // get a pointer to the first object in the array (which is of type ) + storageFile = (CLR_RT_HeapBlock*)top.DereferenceArray()->GetFirstElement(); + + if (fileCount > 0) + { + // allocate memory for buffers + stringBuffer = (char*)platform_malloc(FF_LFN_BUF + 1); + workingBuffer = (char*)platform_malloc(2 * FF_LFN_BUF + 1); + + // sanity check for successfull malloc + if (stringBuffer == NULL || workingBuffer == NULL) + { + // failed to allocate memory + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // perform 2nd pass + // need to rewind the directory read index first + rewinddir(dir); + + // and reset the file iterator vars too + itemIndex = 0; + fileCount = 0; + + + for (;;) + { + // read next directory item + dirInfo = readdir(dir); + + // break on error or at end of dir + if (dirInfo == NULL) + { + break; + } + + // check if this is a file + // but skip if diretory: + if (dirInfo->d_type == DT_REG) + { + // check if this file is within the requested parameters + if ((itemIndex >= startIndex) && + (fileCount < maxItemsToRetrieve)) + { + // create an instance of + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(*storageFile, storageFileTypeDef)); + + // dereference the object in order to reach its fields + hbObj = storageFile->Dereference(); + + // file name + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance(hbObj[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___name], dirInfo->d_name)); + + // clear working buffer + memset(workingBuffer, 0, 2 * FF_LFN_BUF + 1); + + // compose file path + CombinePath(workingBuffer, managedPath, (const char*)dirInfo->d_name); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance(hbObj[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___path], workingBuffer)); + + // get a reference to the dateCreated managed field... + CLR_RT_HeapBlock& dateFieldRef = hbObj[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___dateCreated]; + CLR_INT64* pRes = (CLR_INT64*)&dateFieldRef.NumericByRef().s8; + // ...and set it + *pRes = GetFileTimeFromPath(workingBuffer); + + // move the storage folder pointer to the next item in the array + storageFile++; + + // update iterator var + fileCount++; + } + + // update iterator var + itemIndex++; + } + } + } + else + { + // empty directory + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef("StorageFile", "Windows.Storage", storageFileTypeDef); + + // create an array of + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance(top, fileCount, storageFileTypeDef)); + } + } + else + { + // error or directory empty + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef("StorageFile", "Windows.Storage", storageFileTypeDef); + + // create an array of + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_Array::CreateInstance(top, fileCount, storageFileTypeDef)); + } + + NANOCLR_CLEANUP(); + + // close directory + if (dir) + { + closedir(dir); + } + + // free buffers memory, if allocated + if(stringBuffer != NULL) + { + platform_free(stringBuffer); + } + if(workingBuffer != NULL) + { + platform_free(workingBuffer); + } + if (workingPath != NULL) + { + platform_free(workingPath); + } + + NANOCLR_CLEANUP_END(); +} + + +HRESULT Library_win_storage_native_Windows_Storage_StorageFolder::CreateFileNative___WindowsStorageStorageFile__STRING__U4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Index storageFileTypeDef; + CLR_RT_HeapBlock* storageFile; + + const char* fileName; + const char* managedPath; + char * workingPath = NULL; + + CreationCollisionOption options; + bool fileExists = false; + + FILE * file; + char mode[5] = { 'r' }; + char* filePath = NULL; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get creation collision options + options = (CreationCollisionOption)stack.Arg2().NumericByRef().u4; + + // get a pointer to the StorageFolder path in managed field + managedPath = pThis[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path ].DereferenceString()->StringText(); + + // get a pointer to the desired file name + fileName = stack.Arg1().DereferenceString()->StringText(); + + // setup file path + filePath = (char*)platform_malloc(2 * FF_LFN_BUF + 1); + + // sanity check for successfull malloc + if(filePath == NULL) + { + // failed to allocate memory + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // clear working buffer + memset(filePath, 0, 2 * FF_LFN_BUF + 1); + + // compose file path + CombinePath(filePath, managedPath, fileName); + + // Convert to ESP32 VFS path + // return allocated converted path, must be freed + workingPath = ConvertToESP32Path(filePath); + + // Check if file exists + file = fopen(workingPath, "r"); + if (file) + { + fclose(file); + fileExists = true; + } + + // compute mode flags from CreationCollisionOption + switch (options) + { + case CreationCollisionOption_ReplaceExisting: + mode[0] = 'w'; + mode[1] = '+'; + break; + + case CreationCollisionOption_FailIfExists: + // Check if it exists + if (fileExists) + { + // file already exists + NANOCLR_SET_AND_LEAVE(CLR_E_PATH_ALREADY_EXISTS); + } + + //modeFlags = FA_CREATE_NEW; + mode[0] = 'w'; + break; + + case CreationCollisionOption_OpenIfExists: + if (fileExists) + { + // Open existing file + mode[0] = 'r'; + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + } + break; + + case CreationCollisionOption_GenerateUniqueName: + // this operation is not supported in nanoFramework + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + + default: + break; + } + + // open file + file = fopen(workingPath, mode); + if (file) + { + // file created (or opened) succesfully + // OK to close it + fclose(file); + + // compose return object + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef( "StorageFile", "Windows.Storage", storageFileTypeDef ); + + // create a + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(stack.PushValue(), storageFileTypeDef)); + + // get a handle to the storage file + storageFile = stack.TopValue().Dereference(); + + // file name + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( storageFile[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___name ], fileName )); + + // file path + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( storageFile[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___path ], filePath )); + + // get a reference to the dateCreated managed field... + CLR_RT_HeapBlock& dateFieldRef = storageFile[Library_win_storage_native_Windows_Storage_StorageFile::FIELD___dateCreated ]; + CLR_INT64* pRes = (CLR_INT64*)&dateFieldRef.NumericByRef().s8; + + // ...and set it + *pRes = GetFileTimeFromPath(workingPath); + } + else + { + // file doesn't exist + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_NOT_FOUND); + } + + NANOCLR_CLEANUP(); + + // free buffer memory, if allocated + if(filePath != NULL) + { + platform_free(filePath); + } + + if (workingPath != NULL) + { + platform_free(workingPath); + } + + NANOCLR_CLEANUP_END(); +} + + + +HRESULT Library_win_storage_native_Windows_Storage_StorageFolder::CreateFolderNative___WindowsStorageStorageFolder__STRING__U4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Index storageFolderTypeDef; + CLR_RT_HeapBlock* storageFolder; + + const char* folderName; + char* workingPath = NULL; + const char* managedPath; + + CreationCollisionOption options; + + static struct stat fileInfo; + + int operationResult; + char* folderPath = NULL; + bool folderAlreadyExists = false; + + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get creation collision options + options = (CreationCollisionOption)stack.Arg2().NumericByRef().u4; + + // get a pointer to the path in managed field + managedPath = pThis[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path ].DereferenceString()->StringText(); + + // get a pointer to the desired folder name + folderName = stack.Arg1().DereferenceString()->StringText(); + + folderPath = (char*)platform_malloc(2 * FF_LFN_BUF + 1); + + // sanity check for successfull malloc + if(folderPath == NULL) + { + // failed to allocate memory + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // clear working buffer + memset(folderPath, 0, 2 * FF_LFN_BUF + 1); + + // compose folder path + CombinePath(folderPath, managedPath, folderName); + + // Convert to ESP32 form path ( linux like ) + // return allocated converted path, must be freed + workingPath = ConvertToESP32Path(folderPath); + + //First check if folder already exists + operationResult = stat(workingPath, &fileInfo); + if (operationResult == 0) folderAlreadyExists = true; + + + // Folder doesn't exist so create it + if ( !folderAlreadyExists ) + { + // create directory + operationResult = mkdir(workingPath,0); + if (operationResult < 0) operationResult = errno; + } + else + { + // Folder already exists + if ( options == CreationCollisionOption_FailIfExists ) + { + // folder already exists - fail + operationResult = EEXIST; + } + + // handle request for open if it exists and replace existing + if ((options == CreationCollisionOption_OpenIfExists) || + (options == CreationCollisionOption_ReplaceExisting)) + { + operationResult = 0; + } + else + { + operationResult = EEXIST; + } + } + + if(operationResult == 0) + { + // compose return object + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef( "StorageFolder", "Windows.Storage", storageFolderTypeDef ); + + // create a + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(stack.PushValue(), storageFolderTypeDef)); + + // get a handle to the storage folder + storageFolder = stack.TopValue().Dereference(); + + // folder name + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( storageFolder[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___name ], folderName )); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance( storageFolder[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path ], folderPath )); + + // get the date time details and fill in the managed field + // get a reference to the dateCreated managed field... + CLR_RT_HeapBlock& dateFieldRef = storageFolder[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___dateCreated ]; + CLR_INT64* pRes = (CLR_INT64*)&dateFieldRef.NumericByRef().s8; + + // get the date time details and fill in the managed field + // compute directory date + // ...and set it + *pRes = GetFileTimeFromPath(workingPath); + } + else + { + switch(operationResult) + { + case ENOTSUP: + // Folders not supported, SPIFFS volume + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + case ENOENT: + // Invalid path + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + case EEXIST: + NANOCLR_SET_AND_LEAVE(CLR_E_PATH_ALREADY_EXISTS); + + default: + // failed to create the folder + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_IO); + } + } + + NANOCLR_CLEANUP(); + + // free buffer memory, if allocated + if(folderPath != NULL) + { + platform_free(folderPath); + } + if (workingPath != NULL) + { + platform_free(workingPath); + } + + NANOCLR_CLEANUP_END(); +} + +HRESULT Library_win_storage_native_Windows_Storage_StorageFolder::DeleteFolderNative___VOID(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + + char* workingPath = NULL; + const char* managedPath; + int operationResult; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the path in managed field + managedPath = pThis[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path].DereferenceString()->StringText(); + + // Convert to ESP32 form path ( linux like ) + // return allocated converted path, must be freed + workingPath = ConvertToESP32Path(managedPath); + + // Delete folder, 0=succesfull + operationResult = rmdir(workingPath); + if (operationResult < 0) operationResult = errno; + if (operationResult == ENOENT) + { + // Invalid path + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + else if (operationResult == EACCES) + { + // folder not empty + NANOCLR_SET_AND_LEAVE(CLR_E_DIRECTORY_NOT_EMPTY); + } + + else if (operationResult != 0) + { + // folder doesn't exist + NANOCLR_SET_AND_LEAVE(CLR_E_DIRECTORY_NOT_FOUND); + } + + NANOCLR_CLEANUP(); + + // free buffer memory, if allocated + if (workingPath != NULL) + { + platform_free(workingPath); + } + + NANOCLR_CLEANUP_END(); +} + +HRESULT Library_win_storage_native_Windows_Storage_StorageFolder::RenameFolderNative___VOID__STRING(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + + char* workingPath = NULL; + char* desiredWorkingPath = NULL; + const char* managedPath; + const char* desiredPath; + int operationResult; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the path in managed field + managedPath = pThis[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path].DereferenceString()->StringText(); + + // Convert to ESP32 form path ( linux like ) + // return allocated converted path, must be freed + workingPath = ConvertToESP32Path(managedPath); + + // get a pointer to the desired folder name + desiredPath = stack.Arg1().DereferenceString()->StringText(); + desiredWorkingPath = ConvertToESP32Path(desiredPath); + + // rename folder, 0=succesfull + operationResult = rename(workingPath, desiredWorkingPath); + if (operationResult < 0) operationResult = errno; + if (operationResult == ENOENT) + { + // Invalid path + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + else if (operationResult != 0) + { + // folder doesn't exist + NANOCLR_SET_AND_LEAVE(CLR_E_DIRECTORY_NOT_FOUND); + } + + NANOCLR_CLEANUP(); + + // free buffer memory, if allocated + if (workingPath != NULL) + { + platform_free(workingPath); + } + if (desiredWorkingPath != NULL) + { + platform_free(desiredWorkingPath); + } + + NANOCLR_CLEANUP_END(); +} + +HRESULT Library_win_storage_native_Windows_Storage_StorageFolder::GetFolderNative___WindowsStorageStorageFolder__STRING(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + + CLR_RT_TypeDef_Index storageFolderTypeDef; + CLR_RT_HeapBlock* storageFolder; + + const char* folderName; + char* workingPath = NULL; + const char* managedPath; + + static struct stat fileInfo; + + int operationResult; + char* folderPath = NULL; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the path in managed field + managedPath = pThis[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path].DereferenceString()->StringText(); + + // get a pointer to the desired folder name + folderName = stack.Arg1().DereferenceString()->StringText(); + + folderPath = (char*)platform_malloc(2 * FF_LFN_BUF + 1); + + // sanity check for successfull malloc + if (folderPath == NULL) + { + // failed to allocate memory + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + + // clear working buffer + memset(folderPath, 0, 2 * FF_LFN_BUF + 1); + + // compose folder path + CombinePath(folderPath, managedPath, folderName); + + // Convert to ESP32 form path ( linux like ) + // return allocated converted path, must be freed + workingPath = ConvertToESP32Path(folderPath); + + // Check Directory exists directory + operationResult = stat(workingPath, &fileInfo); + if (operationResult < 0) operationResult = errno; + + if ( operationResult == ENOENT ) + { + // folder doesn't exist + NANOCLR_SET_AND_LEAVE(CLR_E_DIRECTORY_NOT_FOUND); + } + + if (operationResult == 0) + { + // Is this a file + if (fileInfo.st_mode & S_IFREG) + { + // Path represents a file + NANOCLR_SET_AND_LEAVE(CLR_E_DIRECTORY_NOT_FOUND); + } + + + // compose return object + // find type, don't bother checking the result as it exists for sure + g_CLR_RT_TypeSystem.FindTypeDef("StorageFolder", "Windows.Storage", storageFolderTypeDef); + + // create a + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(stack.PushValue(), storageFolderTypeDef)); + + // get a handle to the storage folder + storageFolder = stack.TopValue().Dereference(); + + // folder name + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance(storageFolder[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___name], folderName)); + + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_String::CreateInstance(storageFolder[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___path], folderPath)); + + // get the date time details and fill in the managed field + // get a reference to the dateCreated managed field... + CLR_RT_HeapBlock& dateFieldRef = storageFolder[Library_win_storage_native_Windows_Storage_StorageFolder::FIELD___dateCreated]; + CLR_INT64* pRes = (CLR_INT64*)&dateFieldRef.NumericByRef().s8; + + // get the date time details and fill in the managed field + // compute directory date + // ...and set it + *pRes = GetFileTimeFromPath(workingPath); + } + else + { + // failed to create the folder + NANOCLR_SET_AND_LEAVE(CLR_E_FILE_IO); + } + + NANOCLR_CLEANUP(); + + // free buffer memory, if allocated + if (folderPath != NULL) + { + platform_free(folderPath); + } + if (workingPath != NULL) + { + platform_free(workingPath); + } + + NANOCLR_CLEANUP_END(); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Storage/win_storage_native_target.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Storage/win_storage_native_target.h new file mode 100644 index 00000000..ed4998bf --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/Windows.Storage/win_storage_native_target.h @@ -0,0 +1,11 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIN_STORAGE_NATIVE_TARGET_H_ +#define _WIN_STORAGE_NATIVE_TARGET_H_ + +#include + +#endif //_WIN_STORAGE_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/WireProtocol_App_Interface.c b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/WireProtocol_App_Interface.c new file mode 100644 index 00000000..327686c3 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/WireProtocol_App_Interface.c @@ -0,0 +1,68 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + + +// declaration for wrapper function +extern bool CLR_Messaging_ProcessPayload(WP_Message* msg); + +// defining this array here makes is local helping reduce the image size because of compiler opmitizations +static const CommandHandlerLookup c_Lookup_Request[] = +{ + /*******************************************************************************************************************************************************************/ +#define DEFINE_CMD(cmd) { CLR_DBG_Commands_c_Monitor_##cmd, &Monitor_##cmd } + DEFINE_CMD(Ping ), + // DEFINE_CMD(Reboot ), + // // + // DEFINE_CMD(ReadMemory ), + // DEFINE_CMD(WriteMemory), + // DEFINE_CMD(CheckMemory), + // DEFINE_CMD(EraseMemory), + // // + // DEFINE_CMD(Execute ), + // DEFINE_CMD(MemoryMap ), + // // + // DEFINE_CMD(CheckSignature), + // // + // DEFINE_CMD(FlashSectorMap ), + // DEFINE_CMD(SignatureKeyUpdate), + + DEFINE_CMD(OemInfo), + +#undef DEFINE_CMD + /*******************************************************************************************************************************************************************/ +}; + +//////////////////////////////////////////////////// + +// defining this array here makes is local helping reduce the image size because of compiler optimizations +static const CommandHandlerLookup c_Lookup_Reply[] = +{ + /*******************************************************************************************************************************************************************/ +#define DEFINE_CMD(cmd) { CLR_DBG_Commands_c_Monitor_##cmd, &Monitor_##cmd } + DEFINE_CMD(Ping), +#undef DEFINE_CMD + /*******************************************************************************************************************************************************************/ +}; + +int WP_App_ProcessHeader(WP_Message* message) +{ + // check for reception buffer overflow + if(message->m_header.m_size > sizeof(receptionBuffer)) + { + return false; + } + + message->m_payload = receptionBuffer; + return true; +} + +int WP_App_ProcessPayload(WP_Message* message) +{ + return CLR_Messaging_ProcessPayload(message); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/WireProtocol_MonitorCommands.c b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/WireProtocol_MonitorCommands.c new file mode 100644 index 00000000..3a3646b0 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/WireProtocol_MonitorCommands.c @@ -0,0 +1,7 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +// file empty on purpose +// in nanoCLR the MonitorCommands are implemented in Debugger diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/app_main.c b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/app_main.c new file mode 100644 index 00000000..65d746a8 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/app_main.c @@ -0,0 +1,60 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +#include +#include +#include +#include +#include + +extern void CLRStartupThread(void const * argument); + +// Mutex for GLOBAL_LOCK / GLOBAL_UNLOCK +portMUX_TYPE globalLockMutex = portMUX_INITIALIZER_UNLOCKED; + +void receiver_task(void *pvParameter) +{ + (void)pvParameter; + + ReceiverThread( 0); + + vTaskDelete(NULL); +} + +// Main task start point +void main_task(void *pvParameter) +{ + (void)pvParameter; + + // CLR settings to launch CLR thread + CLR_SETTINGS clrSettings; + (void)memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.EnterDebuggerLoopAfterExit = true; + + CLRStartupThread(&clrSettings); + + vTaskDelete(NULL); +} + +// App_main +// Called from Esp32 IDF start up code before scheduler starts +// +void app_main() +{ + // Switch off logging so as not to interfere with WireProtocol over Uart0 + esp_log_level_set("*", ESP_LOG_NONE); + + ESP_ERROR_CHECK( nvs_flash_init() ); + + xTaskCreatePinnedToCore(&receiver_task, "ReceiverThread", 2048, NULL, 5, NULL, 1); + + // Start the main task pinned to 2nd core + xTaskCreatePinnedToCore(&main_task, "main_task", 15000, NULL, 5, NULL, 1); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/mbedtls_entropy_hardware_pool.c b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/mbedtls_entropy_hardware_pool.c new file mode 100644 index 00000000..542b3ddb --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/mbedtls_entropy_hardware_pool.c @@ -0,0 +1,25 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// Get len bytes of entropy from the hardware RNG. +int mbedtls_hardware_poll( void *data, unsigned char *output, size_t len, size_t *olen ) +{ + (void)data; + + for(size_t i = 0; i < len; i++) + { + // our generator returns 32bits numbers + *output = (unsigned char)esp_random(); + + output++; + } + + // callers require this to be set + *olen = len; + + return 0; +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoCRT.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoCRT.cpp new file mode 100644 index 00000000..2a780218 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoCRT.cpp @@ -0,0 +1,206 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include + +//--// +/* STDIO stubs */ +//--// + +#if !defined(BUILD_RTM) + +void hal_fprintf_SetLoggingCallback( LOGGING_CALLBACK fpn ) +{ + (void)fpn; + NATIVE_PROFILE_PAL_CRT(); + +} + +#endif + +//--// + +#if defined(PLATFORM_EMULATED_FLOATINGPOINT) + +// no floating point, fixed point + +int hal_snprintf_float( char* buffer, size_t len, const char* format, int32_t f ) +{ + NATIVE_PROFILE_PAL_CRT(); + + uint32_t i ; + uint32_t dec; + + if ( f < 0 ) + { + // negative number + i = (uint32_t) -f ; + dec = i & (( 1<>HAL_FLOAT_SHIFT); + + if (dec !=0) dec = (dec * (uint32_t)HAL_FLOAT_PRECISION + (1<< (HAL_FLOAT_SHIFT-1))) >>HAL_FLOAT_SHIFT; + + return hal_snprintf( buffer, len, "-%d.%03u", i, (uint32_t)dec); + + } + else + { + // positive number + i = (uint32_t) f ; + dec = f & (( 1<>HAL_FLOAT_SHIFT); + + if (dec !=0) dec = (dec * (uint32_t)HAL_FLOAT_PRECISION + (1<< (HAL_FLOAT_SHIFT-1))) >>HAL_FLOAT_SHIFT; + + return hal_snprintf( buffer, len, "%d.%03u", i, (uint32_t)dec); + } +} + +int hal_snprintf_double( char* buffer, size_t len, const char* format, int64_t& d ) +{ + NATIVE_PROFILE_PAL_CRT(); + + uint64_t i; + uint32_t dec; // 32 bit is enough for decimal part + + if ( d < 0 ) + { + // negative number + i = (uint64_t)-d; + + i += ((1 << (HAL_DOUBLE_SHIFT-1)) / HAL_DOUBLE_PRECISION); // add broad part of rounding increment before split + + dec = i & (( 1<> HAL_DOUBLE_SHIFT ; + + if (dec !=0) dec = (dec * HAL_DOUBLE_PRECISION + ((1 << (HAL_DOUBLE_SHIFT-1)) % HAL_DOUBLE_PRECISION)) >> HAL_DOUBLE_SHIFT; + + return hal_snprintf( buffer, len, "-%lld.%04u", (int64_t)i, (uint32_t)dec); + + } + else + { + + // positive number + i = (uint64_t)d; + + i += ((1 << (HAL_DOUBLE_SHIFT-1)) / HAL_DOUBLE_PRECISION); // add broad part of rounding increment before split + + dec = i & (( 1<> HAL_DOUBLE_SHIFT; + + if (dec !=0) dec = (dec * HAL_DOUBLE_PRECISION + ((1 << (HAL_DOUBLE_SHIFT-1)) % HAL_DOUBLE_PRECISION)) >> HAL_DOUBLE_SHIFT; + + return hal_snprintf( buffer, len, "%lld.%04u", (int64_t)i, (uint32_t)dec); + } +} + +#else + +#endif + +// because debug_printf needs to be called in both C and C++ we need a proxy to allow it to be called in 'C' +extern "C" { + +#if !defined(BUILD_RTM) + + void debug_printf(const char* format, ...) + { + char buffer[256]; + va_list arg_ptr; + + va_start( arg_ptr, format ); + + int len = vsnprintf( buffer, sizeof(buffer)-1, format, arg_ptr ); + + DebuggerPort_Write( HalSystemConfig.stdio, buffer, len, 0 ); // skip null terminator + + va_end( arg_ptr ); + } + +#else + __inline void debug_printf( const char *format, ... ) {} +#endif // !defined(BUILD_RTM) +} + +int hal_strcpy_s ( char* strDst, size_t sizeInBytes, const char* strSrc ) +{ + NATIVE_PROFILE_PAL_CRT(); +#undef strcpy + + size_t len; + if(strDst == NULL || strSrc == NULL || sizeInBytes == 0) {_ASSERTE(FALSE); return 1;} + + len = hal_strlen_s(strSrc); + if(sizeInBytes < len + 1) {_ASSERTE(FALSE); return 1;} + + strcpy( strDst, strSrc ); + return 0; + +#define strcpy DoNotUse_*strcpy [] +} + +int hal_strncpy_s ( char* strDst, size_t sizeInBytes, const char* strSrc, size_t count ) +{ + NATIVE_PROFILE_PAL_CRT(); +#undef strncpy + if(strDst == NULL || strSrc == NULL || sizeInBytes == 0) {_ASSERTE(FALSE); return 1;} + + if (sizeInBytes < count + 1) + { + _ASSERTE(FALSE); + strDst[0] = 0; + return 1; + } + + strDst[count] = 0; + strncpy( strDst, strSrc, count ); + return 0; + +#define strncpy DoNotUse_*strncpy [] +} + +size_t hal_strlen_s (const char * str) +{ + NATIVE_PROFILE_PAL_CRT(); + + const char *eos = str; + while( *eos++ ) ; + return( eos - str - 1 ); +} + +int hal_strncmp_s ( const char* str1, const char* str2, size_t num ) +{ + NATIVE_PROFILE_PAL_CRT(); +#undef strncmp + if(str1 == NULL || str2 == NULL) {_ASSERTE(FALSE); return 1;} + + return strncmp( str1, str2, num ); + +#define strncmp DoNotUse_*strncmp [] +} + +// Compares 2 ASCII strings case insensitive. Does not take locale into account. +int hal_stricmp( const char * dst, const char * src ) +{ + int f = 0, l = 0; + + do + { + if ( ((f = (unsigned char)(*(dst++))) >= 'A') && (f <= 'Z') ) + { + f -= 'A' - 'a'; + } + if ( ((l = (unsigned char)(*(src++))) >= 'A') && (l <= 'Z') ) + { + l -= 'A' - 'a'; + } + } + while ( f && (f == l) ); + + return(f - l); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoFramework.Devices.OneWire/nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoFramework.Devices.OneWire/nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController.cpp new file mode 100644 index 00000000..eb8929e0 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoFramework.Devices.OneWire/nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController.cpp @@ -0,0 +1,579 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "nf_devices_onewire_native_target.h" +#include "target_nf_devices_onewire_config.h" + +// struct for working threads +static OneWireFindStruct FindStruct; +static bool OneWireOperationResult; +static TaskHandle_t WaitingTask; +static uint8_t LastDiscrepancy; +static uint8_t LastFamilyDiscrepancy; +static uint8_t LastDevice; +static uint8_t SerialNum[8]; +// UART to use for 1-Wire comm +static uart_port_t UartDriver; +// Driver state. +static oneWireState DriverState; + +#if ONEWIRE_USE_MUTUAL_EXCLUSION +// Mutex protecting the peripheral +static mutex_t DriverLock; +#endif // ONEWIRE_USE_MUTUAL_EXCLUSION + +bool oneWireInit() +{ + // TODO: make configurable + DriverState = ONEWIRE_STOP; + UartDriver = NF_ONEWIRE_ESP32_UART_NUM; + + uart_config_t uart_config = { + .baud_rate = 115200, + .data_bits = UART_DATA_8_BITS, + .parity = UART_PARITY_DISABLE, + .stop_bits = UART_STOP_BITS_1, + .flow_ctrl = UART_HW_FLOWCTRL_DISABLE, + .rx_flow_ctrl_thresh = 0, + .use_ref_tick = false + }; + + if (uart_param_config(UartDriver, &uart_config) != ESP_OK) return false; + if (uart_set_pin(UartDriver, NF_ONEWIRE_ESP32_UART_TX_PIN, NF_ONEWIRE_ESP32_UART_RX_PIN, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE) != ESP_OK) return false; + if (uart_driver_install(UartDriver, UART_FIFO_LEN*2, 0, 0, NULL, 0) != ESP_OK) return false; + + #if (ONEWIRE_USE_MUTUAL_EXCLUSION == TRUE) + osalMutexObjectInit(&DriverLock); + #endif + + DriverState = ONEWIRE_READY; + return true; +} + +void oneWireStop() +{ + // stop UART + uart_driver_delete(UartDriver); + + // driver is stopped + DriverState = ONEWIRE_STOP; +} + +uint8_t oneWireTouchReset(void) +{ + char reset = 0xF0; + uint8_t presence; + + // flush DMA buffer to ensure cache coherency + uart_flush(UartDriver); + // set UART baud rate to 9600bps (required to send the RESET condition to the 1-Wire bus) + uart_set_baudrate(UartDriver, 9600); + + uart_write_bytes(UartDriver, (const char *)&reset, 1); + uart_read_bytes(UartDriver, &presence, 1, 20 / portTICK_RATE_MS); + + // set UART baud rate to 115200bps (normal comm is performed at this baud rate) + uart_set_baudrate(UartDriver, 115200); + + // check for presence pulse + return (presence != reset); +} + +bool oneWireTouchBit(bool sendbit) +{ + // need to send 1-Wire write 1 or 0 according to sendbit + char write = sendbit ? IWIRE_WR1 : IWIRE_WR0; + uint8_t reply; + + // flush DMA buffer to ensure cache coherency + uart_flush(UartDriver); + + uart_write_bytes(UartDriver, (const char *)&write, 1); + uart_read_bytes(UartDriver, &reply, 1, 20 / portTICK_RATE_MS); + + // interpret 1-Wire reply + return (reply == IWIRE_RD); +} + +uint8_t oneWireTouchByte(uint8_t sendbyte) +{ + uint8_t send_mask = 0x01, result = 0; + uint8_t i = 0; + char writeBuffer[8]; + uint8_t readBuffer[8]; + + // send byte + while (send_mask) + { + writeBuffer[i] = (sendbyte & send_mask) ? IWIRE_WR1 : IWIRE_WR0; + i++; + // rotates the position mask transmit bit + send_mask<<=1; + }; + + + // flush DMA buffer to ensure cache coherency + uart_flush(UartDriver); + + uart_write_bytes(UartDriver, (const char *)writeBuffer, 8); + uart_read_bytes(UartDriver, readBuffer, 8, 20 / portTICK_RATE_MS); + + // reset send mask to interpret the reply + send_mask = 0x01; + + for (uint32_t i = 0; i < 8; i++) + { + if (readBuffer[i] == IWIRE_RD) + { + result |= send_mask; + } + send_mask<<=1; + } + + return result; +} + +void oneWireAquire() +{ +#if (ONEWIRE_USE_MUTUAL_EXCLUSION == TRUE) + osalMutexLock(&Driver.Lock); +#endif +} + +void oneWireRelease() +{ +#if (ONEWIRE_USE_MUTUAL_EXCLUSION == TRUE) + osalMutexUnlock(&Driver.Lock); +#endif +} + +// compute CRC8 using running algorith (slower but saves FLASH) +uint8_t doCrc8(uint8_t oldCrc, uint8_t x) +{ + uint8_t crc = oldCrc; + + for (uint8_t i = 8; i; i--) + { + uint8_t mix = (crc ^ x) & 0x01; + crc >>= 1; + if (mix) crc ^= 0x8C; + x >>= 1; + } + + return crc; +} + +/******************************************************************************* +** NAME: oneWireSerialNum ************************************************** +******************************************************************************** + +DESCRIPTION: + // The 'oneWireSerialNum' function either reads or sets the SerialNum buffer + // that is used in the search functions 'owFirst' and 'owNext'. + // This function contains two parameters, 'serialnum_buf' is a pointer + // to a buffer provided by the caller. 'serialnum_buf' should point to + // an array of 8 unsigned chars. The second parameter is a flag called + // 'do_read' that is TRUE (1) if the operation is to read and FALSE + // (0) if the operation is to set the internal SerialNum buffer from + // the data in the provided buffer. + // + // 'serialnum_buf' - buffer to that contains the serial number to set + // when do_read = FALSE (0) and buffer to get the serial + // number when do_read = TRUE (1). + // 'do_read' - flag to indicate reading (1) or setting (0) the current + // serial number. + // + +USAGE EXAMPLES: + +AUTHOR: jassimoes + +COMMENTS: + +*******************************************************************************/ +void oneWireSerialNum(uint8_t* serialnum_buf, uint8_t do_read) +{ + uint8_t i; + + //-------------------------------------------------// + // read the internal buffer and place in 'serialnum_buf' + if (do_read) + { + for (i = 0; i < 8; i++) + { + serialnum_buf[i] = SerialNum[i]; + } + } + // set the internal buffer from the data in 'serialnum_buf' + else + { + for (i = 0; i < 8; i++) + { + SerialNum[i] = serialnum_buf[i]; + } + } +} + +/******************************************************************************* +** NAME: oneWireFindNext ******************************************************* +********************************************************************************/ +// The 'oneWireFindNext' function does a general search. +// This function continues from the previos search state. The search state +// can be reset by using the 'oneWireFindFirst' function. +// This function contains one parameter 'alarmOnly'. +// When 'alarmOnly' is TRUE (1) the find alarm command +// 0xEC is sent instead of the normal search command 0xF0. +// Using the find alarm command 0xEC will limit the search to only +// 1-Wire devices that are in an 'alarm' state. +// +// 'doReset' - TRUE (1) perform reset before search, FALSE (0) do not +// perform reset before search. +// 'alarmOnly' - TRUE (1) the find alarm command 0xEC is +// sent instead of the normal search command 0xF0 +// +// Returns: TRUE (1) : when a 1-Wire device was found and it's +// Serial Number placed in the global SerialNum +// FALSE (0): when no new device was found. Either the +// last search was the last device or there +// are no devices on the 1-Wire Net. +bool oneWireFindNext (bool doReset, bool alarmOnly) +{ + uint8_t romBitIndex = 1; + uint8_t romByteIndex = 0; + uint8_t bitMask = 1; + uint8_t attempt = 0; + uint8_t discrepMarker = 0; + bool outBit = 0; + bool result = FALSE; + uint8_t lastcrc8 = 0; + + // clear serial number buffer for new search + memset(SerialNum, 0, 8); + + // if the last call was the last one + if (LastDevice) + { + // reset the search + LastDiscrepancy = 0; + LastDevice = FALSE; + LastFamilyDiscrepancy = 0; + + return FALSE; + } + + // check if reset bus was requested + if (doReset) + { + // reset the 1-Wire bus + // if there is no presence pulse there is nothing to do here, return FALSE + if (!oneWireTouchReset()) + { + // reset the search + LastDiscrepancy = 0; + LastFamilyDiscrepancy = 0; + return FALSE; + } + } + + // send search command + if (alarmOnly) + { + // conditional search command (devices in alarm condition) + oneWireTouchByte(COND_SEARCH_ROM); + } + else + { + // ROM search command + oneWireTouchByte(SEARCH_ROM); + } + + do + { + attempt = 0; + + if (oneWireTouchBit(TRUE) == 1) + { + attempt = 2; + } + + if (oneWireTouchBit(TRUE) == 1) + { + attempt |= 1; + } + + if (attempt == 3) + { + // no devices present, done here + break; + } + else + { + if (attempt > 0) + { + // all connected devices reply with 0 or 1 + // write bit to perform search + outBit = attempt >> 1; + } + else + { + if (romBitIndex < LastDiscrepancy) + { + outBit = ((SerialNum[romByteIndex] & bitMask) > 0); + } + else + { + // set to 1 if it's the same, otherwise 0 + outBit = (romBitIndex == LastDiscrepancy); + } + + // on 0 record position on bitMask + if (outBit == 0) + { + discrepMarker = romBitIndex; + } + } + + // isolate bit in ROM[n] with bitMask + if (outBit == 1) + { + SerialNum[romByteIndex] |= bitMask; + } + else + { + SerialNum[romByteIndex] &= ~bitMask; + } + + // ROM search write + oneWireTouchBit(outBit); + + romBitIndex++; + + bitMask = bitMask << 1; + + // if the mask has reached 0 then go for a new ROM + if (bitMask == 0) + { + // reset mask and perform CRC8 + lastcrc8 = doCrc8(lastcrc8, SerialNum[romByteIndex]); + + romByteIndex++; + bitMask++; + } + } + + } + while (romByteIndex < 8); // loop until we have all ROM bytes + + if ((romBitIndex < 65) || (lastcrc8 != 0)) + { + // search was unsuccessful reset the last discrepancy + LastDiscrepancy = 0; + } + else + { + // search was successful: set last discrepancy, device and result + LastDiscrepancy = discrepMarker; + LastDevice = (LastDiscrepancy == 0); + + // search isn't completed there are more devices present in the bus + result = TRUE; + } + + return result; +} + +/******************************************************************************* +** NAME: oneWireFindFirst ****************************************************** +********************************************************************************/ +// The 'oneWireFindFirst' finds the first device on the 1-Wire Net. +// This function contains one parameter 'alarmOnly'. When +// 'alarmOnly' is TRUE (1) the find alarm command 0xEC is +// sent instead of the normal search command 0xF0. +// Using the find alarm command 0xEC will limit the search to only +// 1-Wire devices that are in an 'alarm' state. +// +// 'portnum' - number 0 to MAX_PORTNUM-1. This number is provided to +// indicate the symbolic port number. +// 'doReset' - TRUE (1) perform reset before search, FALSE (0) do not +// perform reset before search. +// 'alarmOnly' - TRUE (1) the find alarm command 0xEC is +// sent instead of the normal search command 0xF0 +// +// Returns: TRUE (1) : when a 1-Wire device was found and it's +// Serial Number placed in the global SerialNum +// FALSE (0): There are no devices on the 1-Wire Net. +bool oneWireFindFirst (bool doReset, bool alarmOnly) +{ + // reset the search state + LastDiscrepancy = 0; + LastDevice = FALSE; + LastFamilyDiscrepancy = 0; + + // Call Next and return it's return value; + return oneWireFindNext(doReset, alarmOnly); +} + +// OneWire Find First/Next working thread +static void OneWireFindWorkingThread(void *pvParameters) +{ + OneWireFindStruct* findStruct = (OneWireFindStruct*)pvParameters; + + OneWireOperationResult = findStruct->FindFirst ? + oneWireFindFirst(findStruct->DoReset, findStruct->AlarmOnly) : + oneWireFindNext(findStruct->DoReset, findStruct->AlarmOnly); + + // fire event for 1-Wire operation completed + xTaskNotifyGive(WaitingTask); + vTaskDelete(NULL); +} + +HRESULT FindOneDevice(CLR_RT_StackFrame& stack, bool findFirst) +{ + uint8_t* serialNumberPointer; + CLR_RT_HeapBlock hbTimeout; + CLR_INT64* timeout; + TaskHandle_t task; + + // ensure the device is initialized + if (DriverState != ONEWIRE_READY && !oneWireInit()) return CLR_E_INVALID_PARAMETER; + + // set an infinite timeout to wait forever for the operation to complete + // this value has to be in ticks to be properly loaded by SetupTimeoutFromTicks() below + hbTimeout.SetInteger((CLR_INT64)-1); + HRESULT result = stack.SetupTimeoutFromTicks(hbTimeout, timeout); + if (result != S_OK) return result; + + // this is going to be used to check for the right event in case of simultaneous 1-Wire operations + if(stack.m_customState == 1) + { + FindStruct.DoReset = stack.Arg1().NumericByRefConst().u1 != 0; + FindStruct.AlarmOnly = stack.Arg2().NumericByRefConst().u1 != 0; + FindStruct.FindFirst = findFirst; + + // because the 1-Wire bus is shared, acquire the module + oneWireAquire(); + + // spawn working thread to perform the 1-Wire operations + WaitingTask = xTaskGetCurrentTaskHandle(); + xTaskCreate(OneWireFindWorkingThread, "OWWT", 2048, &FindStruct, 12, &task); + + // bump custom state + stack.m_customState = 2; + } + + // wait for 1-Wire operation complete + ulTaskNotifyTake(pdTRUE, portMAX_DELAY); + + oneWireRelease(); + + // get the result from the working thread execution + if(OneWireOperationResult) + { + // update serialNumber field + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); + if (pThis == NULL) return CLR_E_NULL_REFERENCE; + + // get a pointer to the serial number field in the OneWireController instance + CLR_RT_HeapBlock_Array* serialNumberField = pThis[Library_nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController::FIELD___serialNumber].DereferenceArray(); + + _ASSERTE(serialNumberField->m_numOfElements == 8); + + // get a pointer to the first element of the byte array + serialNumberPointer = (uint8_t*)serialNumberField->GetFirstElement(); + + oneWireSerialNum(serialNumberPointer, TRUE); + } + + // pop timeout heap block from stack + stack.PopValue(); + + // set result + stack.SetResult_Boolean(OneWireOperationResult); + + return S_OK; +} + +HRESULT Library_nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController::TouchReset___BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + // ensure the device is initialized + if (DriverState != ONEWIRE_READY && !oneWireInit()) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + stack.SetResult_Boolean(oneWireTouchReset()) ; + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController::TouchBit___BOOLEAN__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + // ensure the device is initialized + if (DriverState != ONEWIRE_READY && !oneWireInit()) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + stack.SetResult_Boolean(oneWireTouchBit(stack.Arg1().NumericByRefConst().u1 != 0)); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController::TouchByte___U1__U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + // ensure the device is initialized + if (DriverState != ONEWIRE_READY && !oneWireInit()) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + stack.SetResult_U1(oneWireTouchByte((uint8_t)stack.Arg1().NumericByRefConst().u1)); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController::WriteByte___U1__U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + uint8_t sendbyte; + + // ensure the device is initialized + if (DriverState != ONEWIRE_READY && !oneWireInit()) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + sendbyte = (uint8_t)stack.Arg1().NumericByRefConst().u1; + stack.SetResult_U1(oneWireTouchByte(sendbyte) == sendbyte ? TRUE : FALSE); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController::ReadByte___U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + // ensure the device is initialized + if (DriverState != ONEWIRE_READY && !oneWireInit()) NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + + stack.SetResult_U1(oneWireTouchByte(0xFF)); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController::FindFirstDevice___BOOLEAN__BOOLEAN__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_CHECK_HRESULT(FindOneDevice(stack, true)); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_devices_onewire_native_nanoFramework_Devices_OneWire_OneWireController::FindNextDevice___BOOLEAN__BOOLEAN__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_CHECK_HRESULT(FindOneDevice(stack, false)); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoFramework.Devices.OneWire/nf_devices_onewire_native_target.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoFramework.Devices.OneWire/nf_devices_onewire_native_target.h new file mode 100644 index 00000000..c2979ffa --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoFramework.Devices.OneWire/nf_devices_onewire_native_target.h @@ -0,0 +1,38 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _NF_DEVICES_ONEWIRE_NATIVE_TARGET_H_ +#define _NF_DEVICES_ONEWIRE_NATIVE_TARGET_H_ + +#include + +// struct with parameters for 1-Wire working thread +struct OneWireFindStruct +{ + bool DoReset; + bool AlarmOnly; + bool FindFirst; +}; + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + ONEWIRE_UNINIT, /* Not initialized. */ + ONEWIRE_STOP, /* Stopped. */ + ONEWIRE_READY, /* Ready. */ + ONEWIRE_ACTIVE /* Generating random number. */ +} oneWireState; + +//character to send on the UART to mimic 1-Wire bus signals +#define IWIRE_WR0 0x00 // 1-Wire write 0 time slot +#define IWIRE_WR1 0xFF // 1-Wire write 1 time slot +#define IWIRE_RD 0xFF // 1-Wire read time slot + +// ROM commands +#define SEARCH_ROM 0xF0 /* search ROM */ +#define COND_SEARCH_ROM 0xEC /* conditional search ROM */ + +#endif //_NF_DEVICES_ONEWIRE_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoFramework.Hardware.ESP32/nanoFramework_hardware_esp32_native.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoFramework.Hardware.ESP32/nanoFramework_hardware_esp32_native.cpp new file mode 100644 index 00000000..2365024e --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoFramework.Hardware.ESP32/nanoFramework_hardware_esp32_native.cpp @@ -0,0 +1,76 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "nanoFramework_hardware_esp32_native.h" + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Logging::NativeSetLogLevel___STATIC__VOID__STRING__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Sleep::NativeEnableWakeupByTimer___STATIC__nanoFrameworkHardwareEsp32EspNativeError__U8, + Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Sleep::NativeEnableWakeupByPin___STATIC__nanoFrameworkHardwareEsp32EspNativeError__nanoFrameworkHardwareEsp32SleepWakeupGpioPin__I4, + Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Sleep::NativeEnableWakeupByMultiPins___STATIC__nanoFrameworkHardwareEsp32EspNativeError__nanoFrameworkHardwareEsp32SleepWakeupGpioPin__nanoFrameworkHardwareEsp32SleepWakeupMode, + Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Sleep::NativeEnableWakeupByTouchPad___STATIC__nanoFrameworkHardwareEsp32EspNativeError, + Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Sleep::NativeStartLightSleep___STATIC__nanoFrameworkHardwareEsp32EspNativeError, + Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Sleep::NativeStartDeepSleep___STATIC__nanoFrameworkHardwareEsp32EspNativeError, + Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Sleep::NativeGetWakeupCause___STATIC__nanoFrameworkHardwareEsp32SleepWakeupCause, + Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Sleep::NativeGetWakeupGpioPin___STATIC__nanoFrameworkHardwareEsp32SleepWakeupGpioPin, + Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Sleep::NativeGetWakeupTouchpad___STATIC__nanoFrameworkHardwareEsp32SleepTouchPad, + NULL, + NULL, + NULL, + Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Configuration::NativeSetPinFunction___STATIC__VOID__I4__I4, + Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Configuration::NativeGetPinFunction___STATIC__I4__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_HighResTimer::NativeEspTimerCreate___I4, + Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_HighResTimer::NativeEspTimerDispose___VOID, + Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_HighResTimer::NativeStop___VOID, + Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_HighResTimer::NativeStartOneShot___VOID__U8, + Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_HighResTimer::NativeStartPeriodic___VOID__U8, + NULL, + Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_HighResTimer::NativeGetCurrent___STATIC__U8, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Hardware_Esp32 = +{ + "nanoFramework.Hardware.Esp32", + 0xC16385A2, + method_lookup, + { 100, 0, 7, 0 } +}; diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoFramework.Hardware.ESP32/nanoFramework_hardware_esp32_native.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoFramework.Hardware.ESP32/nanoFramework_hardware_esp32_native.h new file mode 100644 index 00000000..802bb31c --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoFramework.Hardware.ESP32/nanoFramework_hardware_esp32_native.h @@ -0,0 +1,89 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _NANOFRAMEWORK_HARDWARE_ESP32_NATIVE_H_ +#define _NANOFRAMEWORK_HARDWARE_ESP32_NATIVE_H_ + +#include +#include +#include +#include + +struct Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Logging +{ + NANOCLR_NATIVE_DECLARE(NativeSetLogLevel___STATIC__VOID__STRING__I4); + + //--// + +}; + +struct Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Sleep +{ + NANOCLR_NATIVE_DECLARE(NativeEnableWakeupByTimer___STATIC__nanoFrameworkHardwareEsp32EspNativeError__U8); + NANOCLR_NATIVE_DECLARE(NativeEnableWakeupByPin___STATIC__nanoFrameworkHardwareEsp32EspNativeError__nanoFrameworkHardwareEsp32SleepWakeupGpioPin__I4); + NANOCLR_NATIVE_DECLARE(NativeEnableWakeupByMultiPins___STATIC__nanoFrameworkHardwareEsp32EspNativeError__nanoFrameworkHardwareEsp32SleepWakeupGpioPin__nanoFrameworkHardwareEsp32SleepWakeupMode); + NANOCLR_NATIVE_DECLARE(NativeEnableWakeupByTouchPad___STATIC__nanoFrameworkHardwareEsp32EspNativeError); + NANOCLR_NATIVE_DECLARE(NativeStartLightSleep___STATIC__nanoFrameworkHardwareEsp32EspNativeError); + NANOCLR_NATIVE_DECLARE(NativeStartDeepSleep___STATIC__nanoFrameworkHardwareEsp32EspNativeError); + NANOCLR_NATIVE_DECLARE(NativeGetWakeupCause___STATIC__nanoFrameworkHardwareEsp32SleepWakeupCause); + NANOCLR_NATIVE_DECLARE(NativeGetWakeupGpioPin___STATIC__nanoFrameworkHardwareEsp32SleepWakeupGpioPin); + NANOCLR_NATIVE_DECLARE(NativeGetWakeupTouchpad___STATIC__nanoFrameworkHardwareEsp32SleepTouchPad); + + //--// + +}; + +struct Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Configuration +{ + NANOCLR_NATIVE_DECLARE(NativeSetPinFunction___STATIC__VOID__I4__I4); + NANOCLR_NATIVE_DECLARE(NativeGetPinFunction___STATIC__I4__I4); + + //--// + +}; + +struct Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_HighResEventListener +{ + static const int FIELD__HighResTimers = 1; + + + //--// + +}; + +struct Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_HighResTimer +{ + static const int FIELD_STATIC__s_eventListener = 0; + + static const int FIELD___timerHandle = 1; + static const int FIELD___disposedValue = 2; + static const int FIELD___syncLock = 3; + static const int FIELD__OnHighResTimerExpired = 4; + + NANOCLR_NATIVE_DECLARE(NativeEspTimerCreate___I4); + NANOCLR_NATIVE_DECLARE(NativeEspTimerDispose___VOID); + NANOCLR_NATIVE_DECLARE(NativeStop___VOID); + NANOCLR_NATIVE_DECLARE(NativeStartOneShot___VOID__U8); + NANOCLR_NATIVE_DECLARE(NativeStartPeriodic___VOID__U8); + NANOCLR_NATIVE_DECLARE(NativeGetCurrent___STATIC__U8); + + //--// + +}; + +struct Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_HighResTimerEvent +{ + static const int FIELD__EventType = 3; + static const int FIELD__TimerHandle = 4; + + + //--// + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Hardware_Esp32; + +#endif //_NANOFRAMEWORK_HARDWARE_ESP32_NATIVE_H_ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoFramework.Hardware.ESP32/nanoFramework_hardware_esp32_native_Hardware_Esp32_Configuration.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoFramework.Hardware.ESP32/nanoFramework_hardware_esp32_native_Hardware_Esp32_Configuration.cpp new file mode 100644 index 00000000..df996b8b --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoFramework.Hardware.ESP32/nanoFramework_hardware_esp32_native_Hardware_Esp32_Configuration.cpp @@ -0,0 +1,38 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "nanoFramework_hardware_esp32_native.h" + +#include +#include "Esp32_DeviceMapping.h" + +HRESULT Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Configuration::NativeSetPinFunction___STATIC__VOID__I4__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + uint32_t pin = (int32_t)stack.Arg0().NumericByRef().s4; + int32_t function = (int32_t)stack.Arg1().NumericByRef().s4; + + Esp32_SetMappedDevicePins(pin, function); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Configuration::NativeGetPinFunction___STATIC__I4__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + int32_t function = (int32_t)stack.Arg0().NumericByRef().s4; + + // Return current pin used for function + int32_t pin = (int32_t)Esp32_GetMappedDevicePinsWithFunction(function); + stack.SetResult_I4(pin); + } + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoFramework.Hardware.ESP32/nanoFramework_hardware_esp32_native_Hardware_Esp32_HighResTimer.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoFramework.Hardware.ESP32/nanoFramework_hardware_esp32_native_Hardware_Esp32_HighResTimer.cpp new file mode 100644 index 00000000..c13242f9 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoFramework.Hardware.ESP32/nanoFramework_hardware_esp32_native_Hardware_Esp32_HighResTimer.cpp @@ -0,0 +1,145 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "nanoFramework_hardware_esp32_native.h" + +#define MAX_HRTIMERS 10 + +esp_timer_handle_t hrtimers[MAX_HRTIMERS] = {}; + +////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH nanoFramework.Hardware.Esp32.HighResTimerEventType (in managed code) !!! // +////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +enum HighResTimerEventType +{ + TimerExpired = 101 +}; + +static int FindNextTimerIndex() +{ + for( int index=0; index +#include +#include + +#include "nanoFramework_hardware_esp32_native.h" + +HRESULT Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Sleep::NativeEnableWakeupByTimer___STATIC__nanoFrameworkHardwareEsp32EspNativeError__U8( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + uint64_t time_us = (uint64_t)stack.Arg0().NumericByRef().s8; + + esp_err_t err = esp_sleep_enable_timer_wakeup(time_us); + + // Return err to the managed application + stack.SetResult_I4( (int)err ) ; + + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Sleep::NativeEnableWakeupByPin___STATIC__nanoFrameworkHardwareEsp32EspNativeError__nanoFrameworkHardwareEsp32SleepWakeupGpioPin__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + gpio_num_t gpio_num = (gpio_num_t)stack.Arg0().NumericByRef().s4; + int level = stack.Arg1().NumericByRef().s4; + + esp_err_t err = esp_sleep_enable_ext0_wakeup( gpio_num, level); + + // Return err to the managed application + stack.SetResult_I4( (int)err ) ; + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Sleep::NativeEnableWakeupByMultiPins___STATIC__nanoFrameworkHardwareEsp32EspNativeError__nanoFrameworkHardwareEsp32SleepWakeupGpioPin__nanoFrameworkHardwareEsp32SleepWakeupMode( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + uint64_t mask = (uint64_t)stack.Arg0().NumericByRef().s8; + esp_sleep_ext1_wakeup_mode_t mode = (esp_sleep_ext1_wakeup_mode_t)stack.Arg1().NumericByRef().s4; + + esp_err_t err = esp_sleep_enable_ext1_wakeup(mask, mode); + + // Return err to the managed application + stack.SetResult_I4( (int)err ) ; + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Sleep::NativeEnableWakeupByTouchPad___STATIC__nanoFrameworkHardwareEsp32EspNativeError( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + esp_err_t err = esp_sleep_enable_touchpad_wakeup(); + + // Return err to the managed application + stack.SetResult_I4( (int)err ) ; + + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Sleep::NativeStartLightSleep___STATIC__nanoFrameworkHardwareEsp32EspNativeError( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + esp_err_t err = esp_light_sleep_start(); + + // Return err to the managed application + stack.SetResult_I4( (int)err ) ; + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Sleep::NativeStartDeepSleep___STATIC__nanoFrameworkHardwareEsp32EspNativeError( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + + // set flags to stop debug... + CLR_EE_DBG_SET( RebootPending ); + // ... reboot CLR so execution ends gracefully ... + CLR_EE_REBOOT_CLR; + // ... and set power level to OFF + g_CLR_HW_Hardware.m_powerLevel = PowerLevel__Off; + + // no error here, always OK + stack.SetResult_I4( 0 ) ; + + ////////////////////////////////////////////////////////// + // developer notes: + // - the "goto sleep" is actually handled in ClrStartup() loop when calling CPU_SetPowerMode() + // - the execution engine has to exit the current thread execution to be able to check the reboot flags set above and shutdown gracefully + // - a clean approach to accomplish this is to add a Thread.Sleep(Inifinite) in the caller + ////////////////////////////////////////////////////////// + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Sleep::NativeGetWakeupCause___STATIC__nanoFrameworkHardwareEsp32SleepWakeupCause( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + esp_sleep_wakeup_cause_t cause = esp_sleep_get_wakeup_cause(); + + // Return value to the managed application + stack.SetResult_I4( (int32_t)cause ) ; + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Sleep::NativeGetWakeupGpioPin___STATIC__nanoFrameworkHardwareEsp32SleepWakeupGpioPin( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + int64_t pin = (int64_t)esp_sleep_get_ext1_wakeup_status(); + + // Return value to the managed application + stack.SetResult_I8( pin ) ; + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_nanoFramework_hardware_esp32_native_nanoFramework_Hardware_Esp32_Sleep::NativeGetWakeupTouchpad___STATIC__nanoFrameworkHardwareEsp32SleepTouchPad( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + touch_pad_t touch_pad = esp_sleep_get_touchpad_wakeup_status(); + + // Return value to the managed application + stack.SetResult_I4( (int)touch_pad ) ; + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Native_Rtc.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Native_Rtc.cpp new file mode 100644 index 00000000..e1056671 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Native_Rtc.cpp @@ -0,0 +1,38 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "nf_rt_native.h" + + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// these functions are the real implementation of the 'weak' ones declared at src\CLR\Runtime.Native\nf_rt_native_nanoFramework_Runtime_Native_Rtc_stubs.cpp // +// the stubs for this class are generated by nanoFramework.Runtime.Native // +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + + +HRESULT Library_nf_rt_native_nanoFramework_Runtime_Native_Rtc::Native_RTC_SetSystemTime___STATIC__BOOLEAN__I4__U1__U1__U1__U1__U1__U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + struct tm newTime; + + newTime.tm_year = stack.Arg0().NumericByRef().s4 - 1900; // years since 1900 + newTime.tm_mon = (uint8_t)stack.Arg1().NumericByRef().u1 - 1; // months since January 0-11 + newTime.tm_mday = stack.Arg2().NumericByRef().u1; // day of the month 1-31 + newTime.tm_wday = stack.Arg3().NumericByRef().u1; // days since Sunday 0-6 + newTime.tm_hour = (uint32_t)stack.Arg4().NumericByRef().u1; // hours since midnight 0-23 + newTime.tm_min = (uint32_t)stack.Arg5().NumericByRef().u1; // minutes after the hour 0-59 + newTime.tm_sec = (uint32_t)stack.Arg6().NumericByRef().u1; // seconds after the minute 0-59 + + time_t t = mktime(&newTime); + struct timeval now = { .tv_sec = t, .tv_usec = 0 }; + settimeofday(&now, NULL); + + // Return value to the managed application + stack.SetResult_Boolean(true); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoHAL.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoHAL.cpp new file mode 100644 index 00000000..175e9e31 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/nanoHAL.cpp @@ -0,0 +1,12 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +void HAL_EnterBooterMode() +{ +} + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL.cpp new file mode 100644 index 00000000..06278a2a --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL.cpp @@ -0,0 +1,180 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include +#include +#include + +void Storage_Initialize(); +void Storage_Uninitialize(); + + +extern "C" void FixUpHalSystemConfig(); +extern "C" void FixUpBlockRegionInfo(); + + +// +// Reboot handlers clean up on reboot +// +static ON_SOFT_REBOOT_HANDLER s_rebootHandlers[16] = {NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}; + +void HAL_AddSoftRebootHandler(ON_SOFT_REBOOT_HANDLER handler) +{ + for(unsigned int i=0; i 0) ? true : false; +} + +void SystemState_Set(SYSTEM_STATE_type state) +{ + GLOBAL_LOCK(); + + SystemState_SetNoLock(state); + + GLOBAL_UNLOCK(); +} + +void SystemState_Clear(SYSTEM_STATE_type state) +{ + GLOBAL_LOCK(); + + SystemState_ClearNoLock(state ); + + GLOBAL_UNLOCK(); +} + +bool SystemState_Query(SYSTEM_STATE_type state) +{ + GLOBAL_LOCK(); + + bool systemStateCopy = SystemState_QueryNoLock(state); + + GLOBAL_UNLOCK(); + + return systemStateCopy; +} + + +// Just in case storage is not configured +__nfweak void Storage_Initialize() {}; +__nfweak void Storage_Uninitialize() {}; \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL_ConfigStorage.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL_ConfigStorage.h new file mode 100644 index 00000000..1b15a7eb --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL_ConfigStorage.h @@ -0,0 +1,93 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include "Esp32_os.h" + +#define CONFIG_ERROR 0xffffffff + +#define CONFIG_TYPE_NETWORK 'C' +#define CONFIG_TYPE_WIRELESS 'W' +#define CONFIG_TYPE_WIRELESSAP 'A' +#define CONFIG_TYPE_CERTIFICATE 'X' + + +// Config_Initialise +// +// Initialise underlying filesystem +// +void Config_Initialise(); + +// +// Config_OpenFile - +// +// Open file for configuration / index +// For the case of NVS we just open the NVS partition, save file details, handle +// +// Parameters:- +// configuration : Type of configuration block to open +// configurationIndex : Index of type to open +// write : True to create/overwrite file +// +// Return :- +// true : returns handle +// false -1 +// +uint32_t Config_OpenFile( DeviceConfigurationOption configuration, uint32_t configurationIndex, bool write ); + +// +// Config_CloseFile - Close opened file / NVS system +// +// Parameters:- +// handle : Handle returned from Config_openFile +// +// return:- +// true - File closed ok +// false- Error/File not open/Invalid handle +// +bool Config_CloseFile( uint32_t handle ); + +// +// Config_FileSize - Return size of file +// +// Parameters:- +// handle : Handle returned from Config_openFile +// +// return:- +// File size +// -1 = Error/Not found/Invalid handle +// +int32_t Config_FileSize( uint32_t handle ); + +// +// Config_WriteFile - Write data to file system +// +// Parameters:- +// handle : Handle returned from Config_openFile +// pData : Pointer data to write +// writeSize : Size of data to write +// +// return:- +// true - OK +// false- Error/Not found +// +bool Config_WriteFile(uint32_t handle, uint8_t * pData, int32_t writeSize ); + + +// +// Config_ReadFile - Read the data from opened file +// +// Parameters:- +// handle : Handle returned from Config_openFile +// pData : Ponter to where data is to be stored +// +// return:- +// true - read length +// false- -1 , Error/Not found/Invalid handle +// +int32_t Config_ReadFile( uint32_t handle, uint8_t * pData, int32_t maxSizeData ); + diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL_ConfigStorageFatfs.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL_ConfigStorageFatfs.cpp new file mode 100644 index 00000000..a9569403 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL_ConfigStorageFatfs.cpp @@ -0,0 +1,249 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +// Allocate a FATFS for config +// +// minimum size is 528K wih 4096 allocation unit size +// minimum size is 128K wih 512 allocation unit size +// CONFIG_WL_SECTOR_SIZE +// +#include +#include +#include +#include "Esp32_os.h" +#include "targetHAL_ConfigStorage.h" + +#include "esp_vfs.h" +#include "esp_vfs_fat.h" + +// FATFS config +#define FATFS_Base_Path "/I" +#define FATFS_Base_Config_Name "con_" +#define FATFS_Partition_Label "config" +#define FATFS_MaxFileNameLen 30 + +static const char *TAG = "Config"; + +enum ConfigIoType { Read, Write, GetSize }; + +// Handle of the wear levelling library instance +static wl_handle_t s_wl_handle = WL_INVALID_HANDLE; + +// Initialise SPIFFS +void Config_Initialise() +{ + esp_err_t ret; + + esp_vfs_fat_mount_config_t mount_config = { + .format_if_mount_failed = true, + .max_files = 5, + .allocation_unit_size = CONFIG_WL_SECTOR_SIZE + }; + + ret = esp_vfs_fat_spiflash_mount(FATFS_Base_Path, FATFS_Partition_Label, &mount_config, &s_wl_handle); + if (ret != ESP_OK) { + if (ret == ESP_FAIL) { + ESP_LOGE(TAG, "Failed to mount or format filesystem"); + } else if (ret == ESP_ERR_NOT_FOUND) { + ESP_LOGE(TAG, "Failed to find config FATFS partition"); + } else if (ret == ESP_ERR_NO_MEM) { + ESP_LOGE(TAG, "Failed to mount FATFS partition as no memory"); + } + else { + ESP_LOGE(TAG, "Failed to initialize SPIFFS (%s)", esp_err_to_name(ret)); + } + } +} + +// Create config name in NVS from option/index +// return name in configName +// +// Return filename +// "/config/" +void Config_GetConfigFileName(DeviceConfigurationOption configuration, uint32_t configurationIndex, char * configName) +{ + char * startName = configName; + + // Add filesystem name + hal_strcpy_s(configName, FATFS_MaxFileNameLen, FATFS_Base_Path ); + configName += hal_strlen_s(configName); + + *configName++ = '/'; + + // Add basename + hal_strcpy_s( configName, FATFS_MaxFileNameLen - (int)(configName-startName), FATFS_Base_Config_Name ); + configName += hal_strlen_s(configName); + + switch (configuration) + { + case DeviceConfigurationOption_Network: + *configName++ = CONFIG_TYPE_NETWORK; + break; + + case DeviceConfigurationOption_Wireless80211Network: + *configName++ = CONFIG_TYPE_WIRELESS; + break; + + case DeviceConfigurationOption_WirelessNetworkAP: + *configName++ = CONFIG_TYPE_WIRELESSAP; + break; + + case DeviceConfigurationOption_X509CaRootBundle: + *configName++ = CONFIG_TYPE_CERTIFICATE; + break; + + default: + *configName++ = '?'; + break; + } + + itoa(configurationIndex, configName, 10); +} + +// +// Config_OpenFile - +// +// Open file for configuration / index +// For the case of NVS we just open the NVS partition, save file details, handle +// +// Parameters:- +// configuration : Type of configuration block to open +// configurationIndex : Index of type to open +// +// Return :- +// true : returns handle +// false -1 +// +uint32_t Config_OpenFile(DeviceConfigurationOption configuration, uint32_t configurationIndex, bool write) +{ + char FileName[FATFS_MaxFileNameLen + 1] = { 0 }; + + Config_GetConfigFileName(configuration, configurationIndex, FileName); + + // Open FATFS config storage + FILE * file = fopen(FileName, write ? "wb" : "rb"); + if (file != NULL) + { + return (uint32_t)file; + } + + ESP_LOGE(TAG, "Failed to open file (%s) %d", FileName, errno); + return CONFIG_ERROR; +} + + +// +// Config_CloseFile - Close opened file +// +// Parameters:- +// handle : Handle returned from Config_openFile +// +// return:- +// true - File closed ok +// false- Error/File not open/Invalid handle +// +bool Config_CloseFile( uint32_t handle ) +{ + fclose( (FILE *)handle); + return true; +} + +// +// Shared IO +// +uint32_t Config_IO(uint32_t handle, ConfigIoType ioType, uint8_t * pData, int32_t size ) +{ + FILE * file = (FILE *)handle; + int32_t result = CONFIG_ERROR; + size_t ret; + long blobSize; + + while(true) + { + if ( ioType == GetSize || ioType == Read ) + { + // Get size of blob before we read it + fseek(file, 0, SEEK_END); + blobSize = ftell(file); + + result = (int32_t)blobSize; + + // If GetSize then finnish + if ( ioType == GetSize) break; + + // Do read + // Check room in buffer + if ( (int32_t)blobSize > size ) break; // error + + // Read blob into pData + fseek(file, 0, SEEK_SET); + ret = fread( (void *)pData, 1, (size_t)blobSize, file); + if (ret != (size_t)blobSize) + result = CONFIG_ERROR; + + break; + } + else if ( ioType == Write ) + { + ret = fwrite( (const void *)pData, 1, (size_t)size, file); + if ( ret == (size_t)size ) result = 0; + break; + } + else + break; + + } // while + + return result; +} + +// +// Config_FileSize - Return size of file +// +// Parameters:- +// handle : Handle returned from Config_openFile +// +// return:- +// File size +// -1 = Error/Not found/Invalid handle +// +int32_t Config_FileSize( uint32_t handle ) +{ + return Config_IO( handle, GetSize, 0, 0); +} + +// +// Config_WriteFile - Write data to file +// +// Parameters:- +// handle : Handle returned from Config_openFile +// pData : Pointer data to write +// writeSize : Size of data to write +// +// return:- +// true - OK +// false- Error/Not found +// +bool Config_WriteFile(uint32_t handle, uint8_t * pData, int32_t writeSize ) +{ + return ( Config_IO( handle, Write, pData, writeSize) != CONFIG_ERROR); +} + +// +// Config_ReadFile - Read the data from file +// +// Parameters:- +// handle : Handle returned from Config_openFile +// pData : Ponter to where data is to be stored +// +// return:- +// Read size +// -1 = Error/Not found/Invalid handle +// +int32_t Config_ReadFile( uint32_t handle, uint8_t * pData, int32_t maxSizeData ) +{ + return Config_IO( handle, Read, pData, maxSizeData); +} + diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL_ConfigStorageNVS.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL_ConfigStorageNVS.cpp new file mode 100644 index 00000000..6f756370 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL_ConfigStorageNVS.cpp @@ -0,0 +1,216 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include "Esp32_os.h" +#include "targetHAL_ConfigStorage.h" + +// NVS parameters for Interface config +#define NVS_NAMESPACE "nanoF" + + +// Save File details +static nvs_handle configHandle = -1; +static DeviceConfigurationOption configType; +static uint32_t configIndex; + +enum ConfigIoType { Read, Write, GetSize }; + +void Config_Initialise() +{ + +} + + +// Create config name in NVS from option/index +// return name in configName +void Config_GetConfigFileName(DeviceConfigurationOption configuration, uint32_t configurationIndex, char * configName) +{ + switch (configuration) + { + case DeviceConfigurationOption_Network: + *configName++ = CONFIG_TYPE_NETWORK; + break; + + case DeviceConfigurationOption_Wireless80211Network: + *configName++ = CONFIG_TYPE_WIRELESS; + break; + + case DeviceConfigurationOption_WirelessNetworkAP: + *configName++ = CONFIG_TYPE_WIRELESSAP; + break; + + case DeviceConfigurationOption_X509CaRootBundle: + *configName++ = CONFIG_TYPE_CERTIFICATE; + break; + + default: + *configName++ = '?'; + break; + } + + itoa(configurationIndex, configName, 10); +} + +// +// Config_OpenFile - +// +// Open file for configuration / index +// For the case of NVS we just open the NVS partition, save file details, handle +// +// Parameters:- +// configuration : Type of configuration block to open +// configurationIndex : Index of type to open +// +// Return :- +// true : returns handle +// false -1 +// +uint32_t Config_OpenFile( DeviceConfigurationOption configuration, uint32_t configurationIndex ) +{ + // Open NVS storage using NanoFramework namespace + esp_err_t ret = nvs_open( NVS_NAMESPACE, NVS_READWRITE, &configHandle); + if ( ret == ESP_OK ) + { + configType = configuration; + configIndex = configurationIndex; + return configHandle; + } + + return CONFIG_ERROR; +} + + +// +// Config_CloseFile - Close opened file / NVS system +// +// Parameters:- +// handle : Handle returned from Config_openFile +// +// return:- +// true - File closed ok +// false- Error/File not open/Invalid handle +// +bool Config_CloseFile( uint32_t handle ) +{ + // Check valid handle + if ( handle != configHandle) return false; + + nvs_close(configHandle); + configHandle = CONFIG_ERROR; + return true; +} + +// +// Shared IO +// +uint32_t Config_IO(uint32_t handle, ConfigIoType ioType, uint8_t * pData, int32_t size ) +{ + int32_t result = CONFIG_ERROR; + char configName[10]; + esp_err_t ret; + size_t blobSize; + + // Check valid handle + if ( handle != configHandle) return CONFIG_ERROR; + + // Build file system name + Config_GetConfigFileName( configType, configIndex, configName); + + while(true) + { + if ( ioType == GetSize || ioType == Read ) + { + // Get size of blob before we read it + ret = nvs_get_blob(configHandle, configName, (void *)0, &blobSize); + if (ret != ESP_OK) break; + result = (int32_t)blobSize; + + // If GetSize then finnish + if ( ioType == GetSize) break; + + // Do read + // Check room in buffer + if ( (int32_t)blobSize > size ) break; // error + + // Read blob into pData + + ret = nvs_get_blob(configHandle, configName, (void *)pData, &blobSize); + if (ret == ESP_OK) + result = (int32_t)blobSize; + else + result = CONFIG_ERROR; + + break; + } + else if ( ioType == Write ) + { + ret = nvs_set_blob(configHandle, configName, (const void *)pData, (size_t)size); + if ( ret == ESP_OK ) + { + // Write OK so commit it + ret = nvs_commit(configHandle); + if (ret == ESP_OK) result = 0; + } + break; + } + else + break; + + } // while + + return result; +} + +// +// Config_FileSize - Return size of file +// +// Parameters:- +// handle : Handle returned from Config_openFile +// +// return:- +// File size +// -1 = Error/Not found/Invalid handle +// +int32_t Config_FileSize( uint32_t handle ) +{ + return Config_IO( handle, GetSize, 0, 0); +} + +// +// Config_WriteFile - Write data to NVS system +// +// Parameters:- +// handle : Handle returned from Config_openFile +// pData : Pointer data to write +// writeSize : Size of data to write +// +// return:- +// true - OK +// false- Error/Not found +// +bool Config_WriteFile(uint32_t handle, uint8_t * pData, int32_t writeSize ) +{ + return ( Config_IO( handle, Write, pData, writeSize) != CONFIG_ERROR); +} + +// +// Config_ReadFile - Read the data from file opened in NVS +// +// Parameters:- +// handle : Handle returned from Config_openFile +// pData : Ponter to where data is to be stored +// +// return:- +// Read size +// -1 = Error/Not found/Invalid handle +// +int32_t Config_ReadFile( uint32_t handle, uint8_t * pData, int32_t maxSizeData ) +{ + return Config_IO( handle, Read, pData, maxSizeData); +} + diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL_ConfigStorageSPIFFS.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL_ConfigStorageSPIFFS.cpp new file mode 100644 index 00000000..d1c2e4b5 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL_ConfigStorageSPIFFS.cpp @@ -0,0 +1,243 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include "Esp32_os.h" +#include "targetHAL_ConfigStorage.h" + +// SPIFFS config +#define SPIFFS_Base_Path "/I" +//#define SPIFFS_Base_Path "/config" +#define SPIFFS_Base_Config_Name "con_" +#define SPIFFS_Partition_Label "config" +#define SPIFFS_MaxFileNameLen 20 + +static const char *TAG = "Config"; + +enum ConfigIoType { Read, Write, GetSize }; + +// Initialise SPIFFS +void Config_Initialise() +{ + esp_err_t ret; + + esp_vfs_spiffs_conf_t conf = { + .base_path = SPIFFS_Base_Path, + .partition_label = SPIFFS_Partition_Label, + .max_files = 5, + .format_if_mount_failed = true + }; + + ret = esp_vfs_spiffs_register(&conf); + if (ret != ESP_OK) { + if (ret == ESP_FAIL) { + ESP_LOGE(TAG, "Failed to mount or format filesystem"); + } else if (ret == ESP_ERR_NOT_FOUND) { + ESP_LOGE(TAG, "Failed to find SPIFFS partition"); + } else { + ESP_LOGE(TAG, "Failed to initialize SPIFFS (%s)", esp_err_to_name(ret)); + } + } + + size_t total = 0, used = 0; + ret = esp_spiffs_info(SPIFFS_Partition_Label, &total, &used); + if (ret == ESP_OK) + { + ESP_LOGI(TAG, "SPIFFS Partition size: total: %d, used: %d", total, used); + } +} + +// Create config name in NVS from option/index +// return name in configName +// +// Return filename +// "/config/" +void Config_GetConfigFileName(DeviceConfigurationOption configuration, uint32_t configurationIndex, char * configName) +{ + char * startName = configName; + + // Add filesystem name + hal_strcpy_s(configName, SPIFFS_MaxFileNameLen, SPIFFS_Base_Path ); + configName += hal_strlen_s(configName); + + *configName++ = '/'; + + // Add basename + hal_strcpy_s( configName, SPIFFS_MaxFileNameLen - (int)(configName-startName), SPIFFS_Base_Config_Name ); + configName += hal_strlen_s(configName); + + switch (configuration) + { + case DeviceConfigurationOption_Network: + *configName++ = CONFIG_TYPE_NETWORK; + break; + + case DeviceConfigurationOption_Wireless80211Network: + *configName++ = CONFIG_TYPE_WIRELESS; + break; + + case DeviceConfigurationOption_WirelessNetworkAP: + *configName++ = CONFIG_TYPE_WIRELESSAP; + break; + + case DeviceConfigurationOption_X509CaRootBundle: + *configName++ = CONFIG_TYPE_CERTIFICATE; + break; + + default: + *configName++ = '?'; + break; + } + + itoa(configurationIndex, configName, 10); +} + +// +// Config_OpenFile - +// +// Open file for configuration / index +// For the case of NVS we just open the NVS partition, save file details, handle +// +// Parameters:- +// configuration : Type of configuration block to open +// configurationIndex : Index of type to open +// +// Return :- +// true : returns handle +// false -1 +// +uint32_t Config_OpenFile( DeviceConfigurationOption configuration, uint32_t configurationIndex, bool write ) +{ + char FileName[SPIFFS_MaxFileNameLen+1] = {0}; + + Config_GetConfigFileName( configuration, configurationIndex, FileName); + + // Open SPIFFS config storage + FILE * file = fopen( FileName, write?"wb":"rb" ); + if ( file != NULL ) + { + return (uint32_t)file; + } + + ESP_LOGE(TAG, "Failed to open file (%s)", FileName ); + return CONFIG_ERROR; +} + + +// +// Config_CloseFile - Close opened file / NVS system +// +// Parameters:- +// handle : Handle returned from Config_openFile +// +// return:- +// true - File closed ok +// false- Error/File not open/Invalid handle +// +bool Config_CloseFile( uint32_t handle ) +{ + fclose( (FILE *)handle); + return true; +} + +// +// Shared IO +// +uint32_t Config_IO(uint32_t handle, ConfigIoType ioType, uint8_t * pData, int32_t size ) +{ + FILE * file = (FILE *)handle; + int32_t result = CONFIG_ERROR; + size_t ret; + long blobSize; + + while(true) + { + if ( ioType == GetSize || ioType == Read ) + { + // Get size of blob before we read it + fseek(file, 0, SEEK_END); + blobSize = ftell(file); + + result = (int32_t)blobSize; + + // If GetSize then finnish + if ( ioType == GetSize) break; + + // Do read + // Check room in buffer + if ( (int32_t)blobSize > size ) break; // error + + // Read blob into pData + fseek(file, 0, SEEK_SET); + ret = fread( (void *)pData, 1, (size_t)blobSize, file); + if (ret != (size_t)blobSize) + result = CONFIG_ERROR; + + break; + } + else if ( ioType == Write ) + { + ret = fwrite( (const void *)pData, 1, (size_t)size, file); + if ( ret == (size_t)size ) result = 0; + break; + } + else + break; + + } // while + + return result; +} + +// +// Config_FileSize - Return size of file +// +// Parameters:- +// handle : Handle returned from Config_openFile +// +// return:- +// File size +// -1 = Error/Not found/Invalid handle +// +int32_t Config_FileSize( uint32_t handle ) +{ + return Config_IO( handle, GetSize, 0, 0); +} + +// +// Config_WriteFile - Write data to NVS system +// +// Parameters:- +// handle : Handle returned from Config_openFile +// pData : Pointer data to write +// writeSize : Size of data to write +// +// return:- +// true - OK +// false- Error/Not found +// +bool Config_WriteFile(uint32_t handle, uint8_t * pData, int32_t writeSize ) +{ + return ( Config_IO( handle, Write, pData, writeSize) != CONFIG_ERROR); +} + +// +// Config_ReadFile - Read the data from file opened in NVS +// +// Parameters:- +// handle : Handle returned from Config_openFile +// pData : Ponter to where data is to be stored +// +// return:- +// Read size +// -1 = Error/Not found/Invalid handle +// +int32_t Config_ReadFile( uint32_t handle, uint8_t * pData, int32_t maxSizeData ) +{ + return Config_IO( handle, Read, pData, maxSizeData); +} + diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL_ConfigurationManager.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL_ConfigurationManager.cpp new file mode 100644 index 00000000..a04458d1 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL_ConfigurationManager.cpp @@ -0,0 +1,749 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include "Esp32_os.h" +#include "targetHAL_ConfigStorage.h" +#include + +// NVS parameters for Interface config +#define NVS_NAMESPACE "nanoF" + + +// #define DEBUG_CONFIG 1 + +// Saves the remaining bundle size for multiple block cert configs +static int32_t savedBundleSize; +static int32_t remainingBundleSize; +static int32_t savedBundleOffset; + +#ifdef DEBUG_CONFIG +void PrintBlock(char * pBlock, int bsize) +{ + char * pCurrStart; + char * pCurrPos; + char * pCurrEnd; + char * pCurrEndBlock = pBlock + bsize; + + pCurrStart = pBlock; + + while (pCurrStart <= pCurrEndBlock) + { + pCurrPos = pCurrStart; + pCurrEnd = pCurrStart + 32; + + while (pCurrPos < pCurrEnd && pCurrPos <= pCurrEndBlock) + { + ets_printf("%02X ", *pCurrPos); + pCurrPos++; + } + + ets_printf(" "); + + pCurrPos = pCurrStart; + while (pCurrPos < pCurrEnd && pCurrPos <= pCurrEndBlock) + { + if (*pCurrPos < 32) + ets_printf("."); + else + ets_printf("%c", *pCurrPos); + pCurrPos++; + } + ets_printf("\n"); + + pCurrStart = pCurrEnd; + } +} +#endif + +// initialization of configuration manager +// provided as weak so it can be replaced at target level, if required because of the target implementing the storage with a mechanism other then saving to flash +void ConfigurationManager_Initialize() +{ + memset((void*)&g_TargetConfiguration, 0, sizeof(g_TargetConfiguration)); + + Config_Initialise(); + + // enumerate the blocks + ConfigurationManager_EnumerateConfigurationBlocks(); +}; + + +int32_t ConfigurationManager_FindConfigurationBlockSize(DeviceConfigurationOption configuration, uint32_t configurationIndex) +{ + uint32_t handle; + int32_t configSize = 0; + + handle = Config_OpenFile(configuration, configurationIndex, false); + if (handle != CONFIG_ERROR) + { + configSize = Config_FileSize(handle); +#ifdef DEBUG_CONFIG + ets_printf("Find type %d index %d, length %d\n", (int)configuration, configurationIndex, configSize); +#endif + Config_CloseFile(handle); + } + + return configSize; +} + +bool ConfigurationManager_GetConfigurationBlockFromStorage(DeviceConfigurationOption configuration, uint32_t configurationIndex, void* configurationBlock, int32_t maxBlockSize) +{ + uint32_t handle; + uint32_t readSize = CONFIG_ERROR; + +#ifdef DEBUG_CONFIG + ets_printf("GetConfigFromStorage %d, %d\n", (int)configuration, configurationIndex); +#endif + + handle = Config_OpenFile(configuration, configurationIndex, false); + if (handle != CONFIG_ERROR) + { + readSize = Config_ReadFile(handle, (uint8_t *)configurationBlock, maxBlockSize); + +#ifdef DEBUG_CONFIG + ets_printf("GetConfigFromStorage read %d, %d size %d\n", (int)configuration, configurationIndex, readSize); +#endif + + Config_CloseFile(handle); + } + + return (readSize != CONFIG_ERROR); +} + + + +// Allocate HAL_CONFIGURATION_NETWORK block if required +void ConfigurationManager_allocate_network(uint32_t configCount) +{ + if (g_TargetConfiguration.NetworkInterfaceConfigs == 0) + { + uint32_t sizeOfNetworkInterfaceConfigs = offsetof(HAL_CONFIGURATION_NETWORK, Configs) + configCount * sizeof(HAL_Configuration_NetworkInterface *); + g_TargetConfiguration.NetworkInterfaceConfigs = (HAL_CONFIGURATION_NETWORK*)platform_malloc(sizeOfNetworkInterfaceConfigs); + memset((void *)g_TargetConfiguration.NetworkInterfaceConfigs, 0, sizeOfNetworkInterfaceConfigs); + } +} + +// Allocate HAL_CONFIGURATION_WIRELESS80211 block if required +void ConfigurationManager_allocate_wireless(uint32_t configCount) +{ + if (g_TargetConfiguration.Wireless80211Configs == 0) + { + uint32_t sizeOfWireless80211Configs = offsetof(HAL_CONFIGURATION_NETWORK_WIRELESS80211, Configs) + configCount * sizeof(HAL_Configuration_Wireless80211 *); + g_TargetConfiguration.Wireless80211Configs = (HAL_CONFIGURATION_NETWORK_WIRELESS80211*)platform_malloc(sizeOfWireless80211Configs); + memset((void *)g_TargetConfiguration.Wireless80211Configs, 0, sizeOfWireless80211Configs); + } +} + +void ConfigurationManager_allocate_wirelessAP(uint32_t configCount) +{ + if (g_TargetConfiguration.WirelessAPConfigs == 0) + { + uint32_t sizeOfWirelessAPConfigs = offsetof(HAL_CONFIGURATION_NETWORK_WIRELESSAP, Configs) + configCount * sizeof(HAL_Configuration_WirelessAP *); + g_TargetConfiguration.WirelessAPConfigs = (HAL_CONFIGURATION_NETWORK_WIRELESSAP*)platform_malloc(sizeOfWirelessAPConfigs); + memset((void *)g_TargetConfiguration.WirelessAPConfigs, 0, sizeOfWirelessAPConfigs); + } +} + +// Allocate HAL_CONFIGURATION_X509_CERTIFICATE block if required +void ConfigurationManager_allocate_certificates(uint32_t certificateCount) +{ + if (g_TargetConfiguration.CertificateStore == 0) + { + uint32_t sizeOfX509CertificateStore = offsetof(HAL_CONFIGURATION_X509_CERTIFICATE, Certificates) + certificateCount * sizeof(g_TargetConfiguration.CertificateStore->Certificates[0]); + g_TargetConfiguration.CertificateStore = (HAL_CONFIGURATION_X509_CERTIFICATE*)platform_malloc(sizeOfX509CertificateStore); + memset((void *)g_TargetConfiguration.CertificateStore, 0, sizeOfX509CertificateStore); + } + + // Init pointers to cert bundles to 0 ( not allocated ) + for (uint32_t index = 0; index < certificateCount; index++) + g_TargetConfiguration.CertificateStore->Certificates[index] = 0; +} + +bool StoreConfigBlock(DeviceConfigurationOption configType, uint32_t configurationIndex, void * pConfigBlock, size_t writeSize) +{ + bool result = false; + uint32_t fileHandle; + + fileHandle = Config_OpenFile(configType, configurationIndex, true); + if (fileHandle != CONFIG_ERROR) + { + result = Config_WriteFile(fileHandle, (uint8_t*)pConfigBlock, writeSize); +#ifdef DEBUG_CONFIG + ets_printf("store type %d index %d, length %d result %d\n", (int)configType, configurationIndex, writeSize, (int)result); +#endif + Config_CloseFile(fileHandle); + } + + return result; +} + +// Enumerates the configuration blocks from the configuration flash sector +// it's implemented with 'weak' attribute so it can be replaced at target level if a different persistance mechanism is used +void ConfigurationManager_EnumerateConfigurationBlocks() +{ + // Fix adapter counts - will get these from NVS + // Still need to do wireless AP + int networkCount = 3; // Esp32 has 3 network interfaces, Ethernet, Wireless Station & Wireless APn + int wirelessCount = 1; + int wirelessAPCount = 1; + int certificateCount = 1; + + // Allocate main structures for each type + ConfigurationManager_allocate_network(networkCount); + ConfigurationManager_allocate_wireless(wirelessCount); + ConfigurationManager_allocate_wirelessAP(wirelessAPCount); + ConfigurationManager_allocate_certificates(certificateCount); + + // For each network interface allocate Network config if required and load from storage + for (int configIndex = 0; configIndex < networkCount; configIndex++) + { + if (g_TargetConfiguration.NetworkInterfaceConfigs->Configs[configIndex] == 0) + { + g_TargetConfiguration.NetworkInterfaceConfigs->Configs[configIndex] = (HAL_Configuration_NetworkInterface*)platform_malloc(sizeof(HAL_Configuration_NetworkInterface)); + } + + if (ConfigurationManager_GetConfigurationBlockFromStorage( + DeviceConfigurationOption_Network, + configIndex, + g_TargetConfiguration.NetworkInterfaceConfigs->Configs[configIndex], + sizeof(HAL_Configuration_NetworkInterface) + ) == false) + { + // No config saved so init default block + HAL_Configuration_NetworkInterface* configPtr = g_TargetConfiguration.NetworkInterfaceConfigs->Configs[configIndex]; + InitialiseNetworkDefaultConfig(configPtr, configIndex); + StoreConfigBlock(DeviceConfigurationOption_Network, configIndex, configPtr, sizeof(HAL_Configuration_NetworkInterface)); + } + } + + g_TargetConfiguration.NetworkInterfaceConfigs->Count = networkCount; + + // For each Wireless interface allocate Wireless config if required and load from storage + for (int configIndex = 0; configIndex < wirelessCount; configIndex++) + { + if (g_TargetConfiguration.Wireless80211Configs->Configs[configIndex] == 0) + { + g_TargetConfiguration.Wireless80211Configs->Configs[configIndex] = (HAL_Configuration_Wireless80211*)platform_malloc(sizeof(HAL_Configuration_Wireless80211)); + } + if (ConfigurationManager_GetConfigurationBlockFromStorage( + DeviceConfigurationOption_Wireless80211Network, + configIndex, + g_TargetConfiguration.Wireless80211Configs->Configs[configIndex], + sizeof(HAL_Configuration_Wireless80211) + ) == false) + { + HAL_Configuration_Wireless80211* configPtr = g_TargetConfiguration.Wireless80211Configs->Configs[configIndex]; + InitialiseWirelessDefaultConfig(configPtr, configIndex); + StoreConfigBlock(DeviceConfigurationOption_Wireless80211Network, configIndex, configPtr, sizeof(HAL_Configuration_Wireless80211)); + } + } + g_TargetConfiguration.Wireless80211Configs->Count = wirelessCount; + + + // For each Wireless AP interface allocate Wireless AP config if required and load from storage + for (int configIndex = 0; configIndex < wirelessAPCount; configIndex++) + { + if (g_TargetConfiguration.WirelessAPConfigs->Configs[configIndex] == 0) + { + g_TargetConfiguration.WirelessAPConfigs->Configs[configIndex] = (HAL_Configuration_WirelessAP*)platform_malloc(sizeof(HAL_Configuration_WirelessAP)); + } + if (ConfigurationManager_GetConfigurationBlockFromStorage( + DeviceConfigurationOption_WirelessNetworkAP, + configIndex, + g_TargetConfiguration.WirelessAPConfigs->Configs[configIndex], + sizeof(HAL_Configuration_WirelessAP) + ) == false) + { + HAL_Configuration_WirelessAP* configPtr = g_TargetConfiguration.WirelessAPConfigs->Configs[configIndex]; + InitialiseWirelessAPDefaultConfig(configPtr, configIndex); + StoreConfigBlock(DeviceConfigurationOption_WirelessNetworkAP, configIndex, configPtr, sizeof(HAL_Configuration_WirelessAP)); + } + } + g_TargetConfiguration.WirelessAPConfigs->Count = wirelessCount; + + // For each Certificate bundle allocate memory and load from storage + for (int certificateIndex = 0; certificateIndex < certificateCount; certificateIndex++) + { + // Free any existing bundles first, we need to reallocate as bundles are variable size + if (g_TargetConfiguration.CertificateStore->Certificates[certificateIndex] != 0) + { + platform_free(g_TargetConfiguration.CertificateStore->Certificates[certificateIndex]); + g_TargetConfiguration.CertificateStore->Certificates[certificateIndex] = 0; + } + + // Find size of saved cert bundle + int32_t bundleSize = ConfigurationManager_FindConfigurationBlockSize(DeviceConfigurationOption_X509CaRootBundle, certificateIndex); + if (bundleSize > 0) + { + // Bundle exits + g_TargetConfiguration.CertificateStore->Count = certificateIndex + 1; + g_TargetConfiguration.CertificateStore->Certificates[certificateIndex] = (HAL_Configuration_X509CaRootBundle*)platform_malloc(bundleSize); + ConfigurationManager_GetConfigurationBlockFromStorage(DeviceConfigurationOption_X509CaRootBundle, certificateIndex, g_TargetConfiguration.CertificateStore->Certificates[certificateIndex], bundleSize); + } + } +} + +// Build AP default ssid based on last 3 bytes of MAC addr +// nano_xxxxxx +// +void CreateDefaultApSSID(HAL_Configuration_WirelessAP * pconfig) +{ + uint8_t mac[6]; + esp_efuse_mac_get_default(mac); + + hal_strcpy_s((char *)pconfig->Ssid, sizeof(pconfig->Ssid), "nano_"); + char * pMac = (char*)pconfig->Ssid + 5; + // Last 3 bytes of MAC address + for (int index = 3; index < 6; index++) + { + sprintf(pMac, "%02X", (int)mac[index]); + pMac += 2; + } +} + +// Default initialisation of wireless config blocks for ESP32 targets +void InitialiseWirelessDefaultConfig(HAL_Configuration_Wireless80211 * pconfig, uint32_t configurationIndex) +{ + memset(pconfig, 0, sizeof(HAL_Configuration_Wireless80211)); + + // Wireless station + pconfig->Id = configurationIndex; + + // test default data for AP + // hal_strcpy_s( (char*)pconfig->Ssid, sizeof(pconfig->Ssid), "MySSID" ); + // hal_strcpy_s( (char*)pconfig->Password, sizeof(pconfig->Password), "MyPassword" ); + + // Set default to Auto Connect + Enable + WirelessFlags_SmartConfig so station can be started by default + // Once smart config has run will start up automatically and reconnect of disconnected + // Application will have to disable wifi to save power etc + pconfig->Flags = (WirelessFlags)(WirelessFlags_Auto | WirelessFlags_Enable | WirelessFlags_SmartConfig); +} + +// Default initialisation of wireless config blocks for ESP32 targets +void InitialiseWirelessAPDefaultConfig(HAL_Configuration_WirelessAP * pconfig, uint32_t configurationIndex) +{ + memset(pconfig, 0, sizeof(HAL_Configuration_WirelessAP)); + + pconfig->Id = configurationIndex; + + // Build AP default ssid/password based on MAC addr + // but don't enable by default + CreateDefaultApSSID(pconfig); + + hal_strcpy_s((char *)pconfig->Password, sizeof(pconfig->Password), "nanoframework"); + + pconfig->Authentication = AuthenticationType_WPA2; + pconfig->Encryption = EncryptionType_WPA2; + pconfig->Radio = RadioType_802_11n; + pconfig->Channel = 11; + pconfig->MaxConnections = 4; + + // Disable Soft AP (default) + pconfig->Flags = WirelessAPFlags_None; +} + +// Default initialisation of Network interface config blocks for ESP32 targets +bool InitialiseNetworkDefaultConfig(HAL_Configuration_NetworkInterface * pconfig, uint32_t configurationIndex) +{ + memset(pconfig, 0, sizeof(HAL_Configuration_NetworkInterface)); + + // make sure the config block marker is set + memcpy(pconfig->Marker, c_MARKER_CONFIGURATION_NETWORK_V1, sizeof(c_MARKER_CONFIGURATION_NETWORK_V1)); + + switch (configurationIndex) + { + case 0: // Wireless Station + pconfig->InterfaceType = NetworkInterfaceType_Wireless80211; + pconfig->StartupAddressMode = AddressMode_DHCP; + pconfig->AutomaticDNS = 1; + pconfig->SpecificConfigId = 0; + break; + + case 1: // Wireless AP + pconfig->InterfaceType = NetworkInterfaceType_WirelessAP; + pconfig->StartupAddressMode = AddressMode_Static; + pconfig->SpecificConfigId = 0; + // Set default address 192.168.1.1 + //pconfig->IPv4Address + //pconfig->IPv4NetMask + // pconfig->IPv4GatewayAddress + break; + + case 2: // Ethernet + pconfig->InterfaceType = NetworkInterfaceType_Ethernet; + pconfig->StartupAddressMode = AddressMode_DHCP; + pconfig->AutomaticDNS = 1; + break; + } + + // get default MAC + esp_efuse_mac_get_default(pconfig->MacAddress); + + // always good + return TRUE; +} + + +// +// Get the specified configuration block from global memory ( g_TargetConfiguration ) +// +// Parameters:- +// configurationBlock : Destination to copy configuration data +// configuration : Type of configuration block to copy +// configurationIndex : Index of type to copy +// +// return:- +// true - OK +// false- Error/Not found +// +bool ConfigurationManager_GetConfigurationBlock(void* configurationBlock, DeviceConfigurationOption configuration, uint32_t configurationIndex) +{ + int sizeOfBlock = 0; + uint8_t* blockAddress = NULL; + +#ifdef DEBUG_CONFIG + ets_printf("GetConfig %d, %d\n", (int)configuration, configurationIndex); +#endif + + // validate if the requested block exists + if (configuration == DeviceConfigurationOption_Network) + { + if (g_TargetConfiguration.NetworkInterfaceConfigs->Count == 0 || + (configurationIndex + 1) > g_TargetConfiguration.NetworkInterfaceConfigs->Count) + { + // there is no network config blocks, init one with default settings +#ifdef DEBUG_CONFIG + ets_printf("GetConfig CN exit false\n"); +#endif + return FALSE; + } + + // set block size + sizeOfBlock = sizeof(HAL_Configuration_NetworkInterface); + + // get block address + blockAddress = (uint8_t*)g_TargetConfiguration.NetworkInterfaceConfigs->Configs[configurationIndex]; + } + else if (configuration == DeviceConfigurationOption_Wireless80211Network) + { + if (g_TargetConfiguration.Wireless80211Configs->Count == 0 || + (configurationIndex + 1) > g_TargetConfiguration.Wireless80211Configs->Count) + { +#ifdef DEBUG_CONFIG + ets_printf("GetConfig WN exit false\n"); +#endif + return FALSE; + } + + // set block size + sizeOfBlock = sizeof(HAL_Configuration_Wireless80211); + + // get block address + blockAddress = (uint8_t*)g_TargetConfiguration.Wireless80211Configs->Configs[configurationIndex]; + } + else if (configuration == DeviceConfigurationOption_WirelessNetworkAP) + { + if (g_TargetConfiguration.WirelessAPConfigs->Count == 0 || + (configurationIndex + 1) > g_TargetConfiguration.WirelessAPConfigs->Count) + { +#ifdef DEBUG_CONFIG + ets_printf("GetConfig AP exit false\n"); +#endif + return FALSE; + } + + // set block size + sizeOfBlock = sizeof(HAL_Configuration_WirelessAP); + + // get block address + blockAddress = (uint8_t*)g_TargetConfiguration.WirelessAPConfigs->Configs[configurationIndex]; + } + else if (configuration == DeviceConfigurationOption_X509CaRootBundle) + { + if (g_TargetConfiguration.CertificateStore->Count == 0 || + (configurationIndex + 1) > g_TargetConfiguration.CertificateStore->Count) + { +#ifdef DEBUG_CONFIG + ets_printf("GetConfig XC exit false\n"); +#endif + return FALSE; + } + + // get block address + blockAddress = (uint8_t*)g_TargetConfiguration.CertificateStore->Certificates[configurationIndex]; + + // set block size + // because X509 certificate has a variable length need to compute the block size in two steps + sizeOfBlock = offsetof(HAL_Configuration_X509CaRootBundle, Certificate); + sizeOfBlock += ((HAL_Configuration_X509CaRootBundle*)blockAddress)->CertificateSize; + } + + // copy the config block content to the pointer in the argument + memcpy(configurationBlock, blockAddress, sizeOfBlock); + + return TRUE; +} + + + + +DeviceConfigurationOption GetConfigOption(char * pConfig) +{ + switch (*pConfig) + { + case CONFIG_TYPE_NETWORK: return DeviceConfigurationOption::DeviceConfigurationOption_Network; + case CONFIG_TYPE_WIRELESS: return DeviceConfigurationOption::DeviceConfigurationOption_Wireless80211Network; + case CONFIG_TYPE_WIRELESSAP: return DeviceConfigurationOption::DeviceConfigurationOption_WirelessNetworkAP; + case CONFIG_TYPE_CERTIFICATE: return DeviceConfigurationOption::DeviceConfigurationOption_X509CaRootBundle; + } + return DeviceConfigurationOption_Network; +} + +bool ConfigurationManager_StoreConfigurationBlockAll(void* configurationBlock, uint32_t blockSize, uint32_t offset) +{ + size_t chunkSize = 0; + uint32_t certificateIndex = 0; + bool result = false; + uint32_t configurationIndex = 0; + + // All configuration blocks in one block + // Separate and update + +#ifdef DEBUG_CONFIG + ets_printf("Block size %d\n", blockSize); + + ets_printf("sizeof HAL_Configuration_NetworkInterface %d\n", sizeof(HAL_Configuration_NetworkInterface)); + ets_printf("sizeof HAL_Configuration_Wireless80211 %d\n", sizeof(HAL_Configuration_Wireless80211)); + ets_printf("sizeof of X509Certificate varies\n"); +#endif + + configurationIndex = 0; + + char * pConfig = (char *)configurationBlock; + char * pEndConfig = (pConfig + blockSize); + DeviceConfigurationOption currentConfigType; + + while (pConfig < pEndConfig) + { + int remainingBlockSize = pEndConfig - pConfig; + +#ifdef DEBUG_CONFIG + ets_printf("Parse block %d:%d\n", pConfig, pEndConfig); + PrintBlock((char *)pConfig, 16); +#endif + currentConfigType = GetConfigOption(pConfig); + + // X509 certificate block ? + if (currentConfigType == DeviceConfigurationOption_X509CaRootBundle || offset > 0) + { + if (offset == 0) + { + HAL_Configuration_X509CaRootBundle * pX509Certificate = (HAL_Configuration_X509CaRootBundle*)pConfig; + + // First block of certificate bundle + // set total bundle size including header + // because X509 certificate has a variable length need to compute the block size in two steps + savedBundleSize = offsetof(HAL_Configuration_X509CaRootBundle, Certificate); + savedBundleSize += pX509Certificate->CertificateSize; + remainingBundleSize = savedBundleSize; + savedBundleOffset = 0; + + // Free if already allocated ( could be different size ) + if (g_TargetConfiguration.CertificateStore->Certificates[certificateIndex] != 0) + platform_free((void*)g_TargetConfiguration.CertificateStore->Certificates); + + g_TargetConfiguration.CertificateStore->Certificates[certificateIndex] = (HAL_Configuration_X509CaRootBundle *)platform_malloc(savedBundleSize); + +#ifdef DEBUG_CONFIG + ets_printf("X509 certificate block total size:%d\n", pX509Certificate->CertificateSize); +#endif + } + + // The current chunk size is what remains in current block + // we can't use offset as it relates to flash memory offset, not useful + chunkSize = remainingBlockSize; + + // Copy into correct position in memory + memcpy((void *)(g_TargetConfiguration.CertificateStore->Certificates[0] + savedBundleOffset), + (const void *)pConfig, + chunkSize); +#ifdef DEBUG_CONFIG + ets_printf("X509 certificate chunksize:%d reminaing:%d\n", chunkSize, savedBundleSize); + PrintBlock((char *)pConfig, 32); +#endif + pConfig += chunkSize; + remainingBundleSize -= chunkSize; + savedBundleOffset += chunkSize; + // Return true for partial blocks + result = true; + + if (remainingBundleSize <= 0) + { + // Save Certificate Bundle to storage + result = StoreConfigBlock(DeviceConfigurationOption_X509CaRootBundle, + certificateIndex, + (void*)g_TargetConfiguration.CertificateStore->Certificates[certificateIndex], + savedBundleSize); + certificateIndex++; +#ifdef DEBUG_CONFIG + ets_printf("X509 certificate complete, saving\n"); +#endif + } + +#ifdef DEBUG_CONFIG + ets_printf("X509 certificate block ret:%d\n", result); +#endif + } + // Network interface block ? + else if (currentConfigType == DeviceConfigurationOption_Network) + { + HAL_Configuration_NetworkInterface * pNetConfig = (HAL_Configuration_NetworkInterface*)pConfig; + pConfig += sizeof(HAL_Configuration_NetworkInterface); + + result = StoreConfigBlock(currentConfigType, configurationIndex, (void*)pNetConfig, sizeof(HAL_Configuration_NetworkInterface)); + configurationIndex++; + +#ifdef DEBUG_CONFIG + ets_printf("Network block %X %X ret:%d\n", pNetConfig->InterfaceType, pNetConfig->SpecificConfigId, result); + PrintBlock((char *)pNetConfig, sizeof(HAL_Configuration_NetworkInterface)); +#endif + } + // Wireless block ? + else if (currentConfigType == DeviceConfigurationOption_Wireless80211Network) + { + HAL_Configuration_Wireless80211 * pWirelessConfig = (HAL_Configuration_Wireless80211*)pConfig; + pConfig += sizeof(HAL_Configuration_Wireless80211); + + result = StoreConfigBlock(currentConfigType, pWirelessConfig->Id, (void*)pWirelessConfig, sizeof(HAL_Configuration_Wireless80211)); + +#ifdef DEBUG_CONFIG + ets_printf("Wireless block %d ssid:%s password:%s ret:%d\n", pWirelessConfig->Id, pWirelessConfig->Ssid, pWirelessConfig->Password, result); + PrintBlock((char *)pWirelessConfig, sizeof(HAL_Configuration_Wireless80211)); +#endif + } + else + break; + } // while + +#ifdef DEBUG_CONFIG + ets_printf("StoreConfig ALL exit %d\n", (int)result); +#endif + return result; +} + + +// +// Stores the configuration block to the storage +// +// Parameters:- +// configurationBlock : Pointer to block to store +// configuration : Type of configuration block to store or All for block with multiple types +// configurationIndex : Index of type to store ( not used for All ) +// blockSize : Size of data pointed to by configurationBlock +// offset : Offset of data when multiple blocks ( currently Certificate Bundles only ), For single type this is offset withing the type +// For ALL type blocks this is the offset in the total data of multiple types. +// Return:- +// true - OK +// false- Error/Not found +// +bool ConfigurationManager_StoreConfigurationBlock(void* configurationBlock, DeviceConfigurationOption configuration, uint32_t configurationIndex, uint32_t blockSize, uint32_t offset) +{ + bool result = false; + bool requiresEnumeration = false; + size_t blobSize = 0; + +#ifdef DEBUG_CONFIG + ets_printf("StoreConfig config:%d, index:%d size:%d offset:%d\n", (int)configuration, configurationIndex, blockSize, offset); +#endif + + if (configuration == DeviceConfigurationOption_All) + return ConfigurationManager_StoreConfigurationBlockAll(configurationBlock, blockSize, offset); + + if (configuration == DeviceConfigurationOption_Network) + { + // set blob size + blobSize = sizeof(HAL_Configuration_NetworkInterface); + } + else if (configuration == DeviceConfigurationOption_Wireless80211Network) + { + // set blob size + blobSize = sizeof(HAL_Configuration_Wireless80211); + } + else if (configuration == DeviceConfigurationOption_WirelessNetworkAP) + { + // set blob size + blobSize = sizeof(HAL_Configuration_WirelessAP); + } + else if (configuration == DeviceConfigurationOption_X509CaRootBundle) + { + // set blob size ( Total size of X509 certificate ) + // because X509 certificate has a variable length need to compute the block size in two steps + blobSize = offsetof(HAL_Configuration_X509CaRootBundle, Certificate); + blobSize += ((HAL_Configuration_X509CaRootBundle*)configurationBlock)->CertificateSize; + +#ifdef DEBUG_CONFIG + ets_printf("StoreConfig x509 blobSize:%d, certsize:%d", blobSize, ((HAL_Configuration_X509CaRootBundle*)configurationBlock)->CertificateSize); +#endif + } + else + { + // Invalid Config + return false; + } + + // Anything to save + if (blobSize != 0) + { + result = StoreConfigBlock(configuration, configurationIndex, configurationBlock, blobSize); + } + + if (requiresEnumeration) + { + // perform enumeration of configuration blocks + ConfigurationManager_EnumerateConfigurationBlocks(); + } + +#ifdef DEBUG_CONFIG + ets_printf("StoreConfig exit %d", result); +#endif + + return result; +} + +// Updates a configuration block in the configuration storage +bool ConfigurationManager_UpdateConfigurationBlock(void* configurationBlock, DeviceConfigurationOption configuration, uint32_t configurationIndex) +{ + // figure out the block size first + uint32_t blockSize = 0; + + switch (configuration) + { + case DeviceConfigurationOption_Network: + blockSize = sizeof(HAL_Configuration_NetworkInterface); + break; + + case DeviceConfigurationOption_Wireless80211Network: + blockSize = sizeof(HAL_Configuration_Wireless80211); + break; + + case DeviceConfigurationOption_WirelessNetworkAP: + blockSize = sizeof(HAL_Configuration_WirelessAP); + break; + + case DeviceConfigurationOption_X509CaRootBundle: + blockSize = offsetof(HAL_Configuration_X509CaRootBundle, Certificate); + blockSize += ((HAL_Configuration_X509CaRootBundle*)configurationBlock)->CertificateSize; + break; + + default: + // shouldn't ever reach here + return FALSE; + } + + return ConfigurationManager_StoreConfigurationBlock(configurationBlock, configuration, configurationIndex, blockSize, 0); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL_Power.c b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL_Power.c new file mode 100644 index 00000000..a0ff214e --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL_Power.c @@ -0,0 +1,43 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +inline void CPU_Reset() +{ + esp_restart(); +}; + +// CPU sleep is not currently implemented in this target +inline void CPU_Sleep(SLEEP_LEVEL_type level, uint64_t wakeEvents) +{ + (void)level; + (void)wakeEvents; + +}; + +inline bool CPU_IsSoftRebootSupported() +{ + return true; +}; + +void CPU_SetPowerMode(PowerLevel_type powerLevel) +{ + switch(powerLevel) + { + case PowerLevel__Off: + // gracefully shutdown everything + nanoHAL_Uninitialize_C(); + + esp_deep_sleep_start(); + + break; + + default: + // all the other power modes are unsupported here + break; + } +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL_Time.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL_Time.cpp new file mode 100644 index 00000000..b631c7fa --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetHAL_Time.cpp @@ -0,0 +1,129 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include +#include + +#define TIME_CONVERSION__TO_USECS 10 + +// Returns the current date time from the RTC +uint64_t HAL_Time_CurrentDateTime(bool datePartOnly) +{ + SYSTEMTIME st; + + struct timeval tv; + + gettimeofday(&tv, NULL); + + // Convert from Unix time(year since 1900) to SYSTEMTIME(Years since 1601) + int64_t time = ((int64_t)tv.tv_sec * (int64_t)TIME_CONVERSION__TO_SECONDS) + ((int64_t)tv.tv_usec * (int64_t)TIME_CONVERSION__TO_USECS) + TIME_UNIX_EPOCH_AS_TICKS; + + // zero 'time' fields if date part only is required + if(datePartOnly) + { + HAL_Time_ToSystemTime(time, &st); + + st.wMilliseconds = 0; + st.wSecond = 0; + st.wMinute = 0; + st.wHour = 0; + + time = HAL_Time_ConvertFromSystemTime(&st); + } + + return time; +}; + +void HAL_Time_SetUtcTime(uint64_t utcTime) +{ + SYSTEMTIME systemTime; + + HAL_Time_ToSystemTime(utcTime, &systemTime); + + struct tm newTime; + + newTime.tm_year = systemTime.wYear - 1900; // years since 1900 + newTime.tm_mon = systemTime.wMonth - 1; // months since January 0-11 + newTime.tm_mday = systemTime.wDay; // day of the month 1-31 + newTime.tm_wday = systemTime.wDayOfWeek; // days since Sunday 0-6 + newTime.tm_hour = (uint32_t)systemTime.wHour; // hours since midnight 0-23 + newTime.tm_min = (uint32_t)systemTime.wMinute; // minutes after the hour 0-59 + newTime.tm_sec = (uint32_t)systemTime.wSecond; // seconds after the minute 0-59 + + time_t t = mktime(&newTime); + struct timeval now = { .tv_sec = t, .tv_usec = 0 }; + settimeofday(&now, NULL); +} + +bool HAL_Time_TimeSpanToStringEx( const int64_t& ticks, char*& buf, size_t& len ) +{ + uint64_t ticksAbs; + uint64_t rest; + + if(ticks < 0) + { + ticksAbs = -ticks; + + CLR_SafeSprintf( buf, len, "-" ); + } + else + { + ticksAbs = ticks; + } + + rest = ticksAbs % ( 1000 * TIME_CONVERSION__TICKUNITS); + ticksAbs = ticksAbs / ( 1000 * TIME_CONVERSION__TICKUNITS); // Convert to seconds. + + if(ticksAbs > TIME_CONVERSION__ONEDAY) // More than one day. + { + CLR_SafeSprintf( buf, len, "%d.", (int32_t)(ticksAbs / TIME_CONVERSION__ONEDAY) ); ticksAbs %= TIME_CONVERSION__ONEDAY; + } + + CLR_SafeSprintf( buf, len, "%02d:", (int32_t)(ticksAbs / TIME_CONVERSION__ONEHOUR) ); ticksAbs %= TIME_CONVERSION__ONEHOUR ; + CLR_SafeSprintf( buf, len, "%02d:", (int32_t)(ticksAbs / TIME_CONVERSION__ONEMINUTE)); ticksAbs %= TIME_CONVERSION__ONEMINUTE; + CLR_SafeSprintf( buf, len, "%02d" , (int32_t)(ticksAbs / TIME_CONVERSION__ONESECOND)); ticksAbs %= TIME_CONVERSION__ONESECOND; + + ticksAbs = (uint32_t)rest; + if(ticksAbs) + { + CLR_SafeSprintf( buf, len, ".%07d", (uint32_t)ticksAbs ); + } + + return len != 0; +} + +bool DateTimeToString(const int64_t& time, char*& buf, size_t& len ) +{ + SYSTEMTIME st; + + HAL_Time_ToSystemTime( time, &st ); + + return CLR_SafeSprintf(buf, len, "%4d/%02d/%02d %02d:%02d:%02d.%03d", st.wYear, st.wMonth, st.wDay, st.wHour, st.wMinute, st.wSecond, st.wMilliseconds ); +} + +char* DateTimeToString(const int64_t& time) +{ + static char rgBuffer[128]; + char* szBuffer = rgBuffer; + size_t iBuffer = ARRAYSIZE(rgBuffer); + + DateTimeToString( time, szBuffer, iBuffer ); + + return rgBuffer; +} + +const char* HAL_Time_CurrentDateTimeToString() +{ + return DateTimeToString(HAL_Time_CurrentDateTime(false)); +} + +uint64_t CPU_MillisecondsToTicks(uint64_t ticks) +{ + return ESP32_TICKS_PER_MS(ticks); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetPAL.c b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetPAL.c new file mode 100644 index 00000000..973fe28c --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetPAL.c @@ -0,0 +1,10 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetPAL_Events.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetPAL_Events.cpp new file mode 100644 index 00000000..c83b1736 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetPAL_Events.cpp @@ -0,0 +1,178 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include + +uint64_t CPU_MillisecondsToTicks(uint64_t ticks); + +// timer for bool events +static TimerHandle_t boolEventsTimer; + +volatile uint32_t systemEvents; + +static void local_Events_SetBoolTimer_Callback( TimerHandle_t xTimer ); + +set_Event_Callback g_Event_Callback = NULL; +void* g_Event_Callback_Arg = NULL; + +bool Events_Initialize() +{ + NATIVE_PROFILE_PAL_EVENTS(); + + // init events + GLOBAL_LOCK(); + systemEvents = 0; + GLOBAL_UNLOCK(); + + boolEventsTimer = xTimerCreate( "boolEventsTimer", 10, pdFALSE, (void *)0, local_Events_SetBoolTimer_Callback); + + return true; +} + +bool Events_Uninitialize() +{ + NATIVE_PROFILE_PAL_EVENTS(); + + xTimerDelete(boolEventsTimer,0); + + return true; +} + +void Events_Set( uint32_t events ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + + // set events + GLOBAL_LOCK(); + systemEvents |= events; + GLOBAL_UNLOCK(); + + if( g_Event_Callback != NULL ) + { + g_Event_Callback( g_Event_Callback_Arg ); + } +} + +uint32_t Events_Get( uint32_t eventsOfInterest ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + + // get the requested flags from system events state and... + uint32_t returnEvents = (systemEvents & eventsOfInterest); + + // ... clear the requested flags atomically + GLOBAL_LOCK(); + systemEvents &= ~eventsOfInterest; + GLOBAL_UNLOCK(); + + // give the caller notice of just the events they asked for ( and were cleared already ) + return returnEvents; +} + +uint32_t Events_MaskedRead( uint32_t eventsOfInterest ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + return (systemEvents & eventsOfInterest); +} + +static void local_Events_SetBoolTimer_Callback( TimerHandle_t xTimer ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + + bool* timerCompleteFlag = (bool*)pvTimerGetTimerID( xTimer ); + *timerCompleteFlag = true; +} + +void Events_SetCallback( set_Event_Callback pfn, void* arg ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + + g_Event_Callback = pfn; + g_Event_Callback_Arg = arg; +} + +void Events_SetBoolTimer( bool* timerCompleteFlag, uint32_t millisecondsFromNow ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + + // we assume only 1 can be active, abort previous just in case + xTimerStop( boolEventsTimer, 0 ); + + if(timerCompleteFlag != NULL) + { + vTimerSetTimerID( boolEventsTimer, (void*) timerCompleteFlag ); + xTimerChangePeriod( boolEventsTimer, millisecondsFromNow / portTICK_PERIOD_MS, 0 ); + } +} + +uint32_t Events_WaitForEvents( uint32_t powerLevel, uint32_t wakeupSystemEvents, uint32_t timeoutMilliseconds ) +{ + // schedule an interrupt for this far in the future + // timeout is in milliseconds, need to convert to ticks + uint64_t countsRemaining = CPU_MillisecondsToTicks(timeoutMilliseconds); + + #if defined(HAL_PROFILE_ENABLED) + Events_WaitForEvents_Calls++; + #endif + + uint64_t expireTimeInTicks = HAL_Time_CurrentTime() + countsRemaining; + bool runContinuations = true; + + while(true) + { + EVENTS_HEART_BEAT; + + uint32_t events = Events_MaskedRead( wakeupSystemEvents ); + if(events) + { + return events; + } + + if(expireTimeInTicks <= HAL_Time_CurrentTime()) + { + break; + } + + // first check and possibly run any continuations + // but only if we have slept after stalling + if(runContinuations && !SystemState_QueryNoLock(SYSTEM_STATE_NO_CONTINUATIONS)) + { + // if we stall on time, don't check again until after we sleep + runContinuations = HAL_CONTINUATION::Dequeue_And_Execute(); + } + else + { + // try stalled continuations again after sleeping + runContinuations = true; + + HAL_COMPLETION::WaitForInterrupts(expireTimeInTicks, powerLevel, wakeupSystemEvents ); + } + + // no events, pass control to the OS + taskYIELD(); + + // check if reboot or exit flags were set when the other OS threads executed + if(CLR_EE_DBG_IS(RebootPending) || CLR_EE_DBG_IS(ExitPending)) + { + break; + } + } + + return 0; +} + +void FreeManagedEvent(uint8_t category, uint8_t subCategory, uint16_t data1, uint32_t data2) +{ + (void)category; + (void)subCategory; + (void)data1; + (void)data2; + + NATIVE_PROFILE_PAL_EVENTS(); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetPAL_Events.cpp.groups.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetPAL_Events.cpp.groups.cpp new file mode 100644 index 00000000..4594c310 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetPAL_Events.cpp.groups.cpp @@ -0,0 +1,146 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include + +#define ESP32_AVAILABLE_EVENTBITS 0x00ffffff + +static void local_Events_SetBoolTimer_Callback( TimerHandle_t xTimer ); + +// events timer +static TimerHandle_t boolEventsTimer; +static bool* saveTimerCompleteFlag = 0; + +EventGroupHandle_t systemEventsHigh; +EventGroupHandle_t systemEventsLow; + +set_Event_Callback g_Event_Callback = NULL; +void* g_Event_Callback_Arg = NULL; + +bool Events_Initialize() +{ + NATIVE_PROFILE_PAL_EVENTS(); + + // init events + // The Eps32 Event group is 24 bits, top 8 bits used by system + // Currently Nanoframework only uses 21 bits, see nanoHal.h + systemEventsHigh = xEventGroupCreate(); + systemEventsLow = xEventGroupCreate(); + + boolEventsTimer = xTimerCreate( "boolEventsTimer", 10, pdFALSE, (void *)0, local_Events_SetBoolTimer_Callback); + + return true; +} + +bool Events_Uninitialize() +{ + NATIVE_PROFILE_PAL_EVENTS(); + + vEventGroupDelete( systemEventsHigh ); + vEventGroupDelete( systemEventsLow); + + return true; +} + +void Events_Set( uint32_t events ) +{ + NATIVE_PROFILE_PAL_EVENTS(); +ets_printf( "Events_set %X\n", events); + // set events + xEventGroupSetBits( systemEventsHigh, events >> 16 ); + xEventGroupSetBits( systemEventsLow, events & 0x00ffff ); + + if( g_Event_Callback != NULL ) + { + g_Event_Callback( g_Event_Callback_Arg ); + } +} + +uint32_t Events_Get( uint32_t eventsOfInterest ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + + // get the requested flags from system events state and... + + uint32_t returnEvents = (xEventGroupGetBits(systemEventsHigh) << 16) & xEventGroupGetBits(systemEventsLow) + + // Make off top 8 bits otherwise get exception when calling xEventGroupClearBits + uint32_t eventstoClear = ~eventsOfInterest; + + // ... clear the requested flags atomically + xEventGroupClearBits(systemEventsHigh, eventstoClear >> 16 ); + xEventGroupClearBits(systemEventsLow, eventstoClear & 0x00ffff ); + + // give the caller notice of just the events they asked for ( and were cleared already ) + return returnEvents; +} + +uint32_t Events_MaskedRead( uint32_t eventsOfInterest ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + + uint32_t returnEvents = (xEventGroupGetBits(systemEventsHigh) << 16) & xEventGroupGetBits(systemEventsLow) + + return ( returnEvents & eventsOfInterest); +} + +static void local_Events_SetBoolTimer_Callback( TimerHandle_t xTimer ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + + *saveTimerCompleteFlag = true; +} + +void Events_SetCallback( set_Event_Callback pfn, void* arg ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + + g_Event_Callback = pfn; + g_Event_Callback_Arg = arg; +} + +void Events_SetBoolTimer( bool* timerCompleteFlag, uint32_t millisecondsFromNow ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + + // we assume only 1 can be active, abort previous just in case + xTimerStop( boolEventsTimer, 0 ); + + if(timerCompleteFlag != NULL) + { + + xTimerChangePeriod( boolEventsTimer, millisecondsFromNow / portTICK_PERIOD_MS, 0 ); + +// Was going to just change existing timer but vTimerSetTimerID() does not exist in this version of FreeRTOS +// As only one timer running at a time we will just save it in global memory + saveTimerCompleteFlag = timerCompleteFlag; + // vTimerSetTimerID( boolEventsTimer, (void *)timerCompleteFlag ); + xTimerStart(boolEventsTimer, 0); + } +} + +uint32_t Events_WaitForEvents( uint32_t powerLevel, uint32_t wakeupSystemEvents, uint32_t timeoutMilliseconds ) +{ + +#if defined(HAL_PROFILE_ENABLED) + Events_WaitForEvents_Calls++; +#endif + + EventBits_t events = (xEventGroupGetBits(systemEventsHigh) << 16) & xEventGroupGetBits(systemEventsLow) + if( events == 0) { + // no events, wait for timeoutMilliseconds + vTaskDelay( timeoutMilliseconds / portTICK_PERIOD_MS ); + } + + return (uint32_t)events; +} + +void FreeManagedEvent(uint8_t category, uint8_t subCategory, uint16_t data1, uint32_t data2) +{ + NATIVE_PROFILE_PAL_EVENTS(); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetPAL_Time.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetPAL_Time.cpp new file mode 100644 index 00000000..30ec2936 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetPAL_Time.cpp @@ -0,0 +1,66 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +static TimerHandle_t nextEventTimer; + +static void NextEventTimer_Callback( TimerHandle_t xTimer ) +{ + (void)xTimer; + + // this call also schedules the next one, if there is one + HAL_COMPLETION::DequeueAndExec(); +} + +HRESULT Time_Initialize() +{ + nextEventTimer = xTimerCreate( "NextEventTimer", 10, pdFALSE, (void *)0, NextEventTimer_Callback); + + return S_OK; +} + +HRESULT Time_Uninitialize() +{ + xTimerDelete(nextEventTimer, 0); + + return S_OK; +} + +void Time_SetCompare ( uint64_t compareValueTicks ) +{ + if(compareValueTicks == 0) + { + // compare value is 0 so dequeue and schedule immediately + HAL_COMPLETION::DequeueAndExec(); + } + else if(compareValueTicks == HAL_COMPLETION_IDLE_VALUE) + { + // wait for infinity, don't need to do anything here + return; + } + else + { + if (HAL_Time_CurrentTime() >= compareValueTicks) + { + // already missed the event, dequeue and execute immediately + HAL_COMPLETION::DequeueAndExec(); + } + else + { + xTimerStop( nextEventTimer, 0 ); + + // compareValueTicks is the time (in sys ticks) that is being requested to fire an HAL_COMPLETION::DequeueAndExec() + // need to subtract the current system time to set when the timer will fire + compareValueTicks -= HAL_Time_CurrentTime(); + + // no need to stop the timer even if it's running because the API does it anyway + // need to convert from nF ticks to milliseconds and then to FreeRTOS sys ticks to load the timer + xTimerChangePeriod(nextEventTimer, compareValueTicks, 0); + } + } +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetRandom.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetRandom.cpp new file mode 100644 index 00000000..061993b0 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/targetRandom.cpp @@ -0,0 +1,35 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// +#include "Core.h" + +void CLR_RT_Random::Initialize() +{ +} + +void CLR_RT_Random::Initialize( int seed ) +{ + (void)seed; +} + +uint32_t CLR_RT_Random::Next() +{ + return esp_random(); +} + +double CLR_RT_Random::NextDouble() +{ + // the hardware generator returns a value between 0 - 0xFFFFFFFF + return ((double)esp_random()) / ((double)0xFFFFFFFF); +} + +void CLR_RT_Random::NextBytes(unsigned char* buffer, unsigned int count) +{ + unsigned int i; + + for(i = 0; i < count; i++) + { + buffer[i] = (unsigned char)esp_random(); + } +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/target_board.h.in b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/target_board.h.in new file mode 100644 index 00000000..825bc90d --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/target_board.h.in @@ -0,0 +1,18 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include + +#define OEMSYSTEMINFOSTRING "nanoFramework running ESP32 built with IDF v3.3" + +#endif /* _TARGET_BOARD_NANOCLR_H_ */ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/target_platform.h.in b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/target_platform.h.in new file mode 100644 index 00000000..a495f6da --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/nanoCLR/target_platform.h.in @@ -0,0 +1,27 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_ESP32_NANOCLR_H_ +#define _TARGET_ESP32_NANOCLR_H_ + + +// set when SD card is enabled +#define HAL_USE_SDC @HAL_USE_SDC_OPTION@ +#if defined(HAL_USE_SDC) + +#define SDC_MAX_OPEN_FILES 5 + + + +#endif + + + +#endif /* _TARGET_ESP32_NANOCLR_H_ */ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/sdkconfig.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/sdkconfig.h new file mode 100644 index 00000000..3156288d --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/sdkconfig.h @@ -0,0 +1,297 @@ +/* + * Automatically generated file. DO NOT EDIT. + * Espressif IoT Development Framework (ESP-IDF) Configuration Header + */ +#pragma once +#define CONFIG_IDF_CMAKE 1 +#define CONFIG_IDF_TARGET "esp32" +#define CONFIG_TOOLPREFIX "xtensa-esp32-elf-" +#define CONFIG_MAKE_WARN_UNDEFINED_VARIABLES 1 +#define CONFIG_APP_COMPILE_TIME_DATE 1 +#define CONFIG_LOG_BOOTLOADER_LEVEL_INFO 1 +#define CONFIG_LOG_BOOTLOADER_LEVEL 3 +#define CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V 1 +#define CONFIG_BOOTLOADER_WDT_ENABLE 1 +#define CONFIG_BOOTLOADER_WDT_TIME_MS 9000 +#define CONFIG_ESPTOOLPY_BAUD_OTHER_VAL 115200 +#define CONFIG_FLASHMODE_DIO 1 +#define CONFIG_ESPTOOLPY_FLASHMODE "dio" +#define CONFIG_ESPTOOLPY_FLASHFREQ_40M 1 +#define CONFIG_ESPTOOLPY_FLASHFREQ "40m" +#define CONFIG_ESPTOOLPY_FLASHSIZE_4MB 1 +#define CONFIG_ESPTOOLPY_FLASHSIZE "4MB" +#define CONFIG_ESPTOOLPY_FLASHSIZE_DETECT 1 +#define CONFIG_ESPTOOLPY_BEFORE_RESET 1 +#define CONFIG_ESPTOOLPY_BEFORE "default_reset" +#define CONFIG_ESPTOOLPY_AFTER_RESET 1 +#define CONFIG_ESPTOOLPY_AFTER "hard_reset" +#define CONFIG_MONITOR_BAUD_115200B 1 +#define CONFIG_MONITOR_BAUD_OTHER_VAL 115200 +#define CONFIG_MONITOR_BAUD 115200 +#define CONFIG_PARTITION_TABLE_SINGLE_APP 1 +#define CONFIG_PARTITION_TABLE_CUSTOM_FILENAME "partitions.csv" +#define CONFIG_PARTITION_TABLE_FILENAME "partitions_singleapp.csv" +#define CONFIG_PARTITION_TABLE_OFFSET 0x8000 +#define CONFIG_PARTITION_TABLE_MD5 1 +#define CONFIG_OPTIMIZATION_LEVEL_DEBUG 1 +#define CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED 1 +#define CONFIG_STACK_CHECK_NONE 1 +#define CONFIG_ESP32_APPTRACE_DEST_NONE 1 +#define CONFIG_ESP32_APPTRACE_LOCK_ENABLE 1 +#define CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF 0 +#define CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF 0 +#define CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF 0 +#define CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE 0 +#define CONFIG_BT_RESERVE_DRAM 0x0 +#define CONFIG_ADC2_DISABLE_DAC 1 +#define CONFIG_SPI_MASTER_ISR_IN_IRAM 1 +#define CONFIG_SPI_SLAVE_ISR_IN_IRAM 1 +#define CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4 1 +#define CONFIG_EFUSE_MAX_BLK_LEN 192 +#define CONFIG_IDF_TARGET_ESP32 1 +#define CONFIG_ESP32_REV_MIN_0 1 +#define CONFIG_ESP32_REV_MIN 0 +#define CONFIG_ESP32_DPORT_WORKAROUND 1 +#define CONFIG_ESP32_DEFAULT_CPU_FREQ_160 1 +#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 160 +#define CONFIG_SPIRAM_SUPPORT 1 +#define CONFIG_SPIRAM_BOOT_INIT 1 +#define CONFIG_SPIRAM_IGNORE_NOTFOUND 1 +#define CONFIG_SPIRAM_USE_MALLOC 1 +#define CONFIG_SPIRAM_TYPE_AUTO 1 +#define CONFIG_SPIRAM_SIZE -1 +#define CONFIG_SPIRAM_SPEED_40M 1 +#define CONFIG_SPIRAM_MEMTEST 1 +#define CONFIG_SPIRAM_CACHE_WORKAROUND 1 +#define CONFIG_SPIRAM_BANKSWITCH_ENABLE 1 +#define CONFIG_SPIRAM_BANKSWITCH_RESERVE 8 +#define CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL 16384 +#define CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL 32768 +#define CONFIG_D0WD_PSRAM_CLK_IO 17 +#define CONFIG_D0WD_PSRAM_CS_IO 16 +#define CONFIG_D2WD_PSRAM_CLK_IO 9 +#define CONFIG_D2WD_PSRAM_CS_IO 10 +#define CONFIG_PICO_PSRAM_CS_IO 10 +#define CONFIG_SPIRAM_SPIWP_SD3_PIN 7 +#define CONFIG_TRACEMEM_RESERVE_DRAM 0x0 +#define CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS 1 +#define CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS 4 +#define CONFIG_SYSTEM_EVENT_QUEUE_SIZE 32 +#define CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE 2304 +#define CONFIG_MAIN_TASK_STACK_SIZE 3584 +#define CONFIG_IPC_TASK_STACK_SIZE 1024 +#define CONFIG_TIMER_TASK_STACK_SIZE 3584 +#define CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF 1 +#define CONFIG_NEWLIB_STDIN_LINE_ENDING_CR 1 +#define CONFIG_CONSOLE_UART_DEFAULT 1 +#define CONFIG_CONSOLE_UART_NUM 0 +#define CONFIG_CONSOLE_UART_BAUDRATE 115200 +#define CONFIG_ULP_COPROC_RESERVE_MEM 0 +#define CONFIG_ESP32_PANIC_PRINT_REBOOT 1 +#define CONFIG_ESP32_DEBUG_OCDAWARE 1 +#define CONFIG_ESP32_DEBUG_STUBS_ENABLE 1 +#define CONFIG_INT_WDT 1 +#define CONFIG_INT_WDT_TIMEOUT_MS 300 +#define CONFIG_INT_WDT_CHECK_CPU1 1 +#define CONFIG_TASK_WDT 1 +#define CONFIG_TASK_WDT_TIMEOUT_S 5 +#define CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0 1 +#define CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1 1 +#define CONFIG_BROWNOUT_DET 1 +#define CONFIG_BROWNOUT_DET_LVL_SEL_0 1 +#define CONFIG_BROWNOUT_DET_LVL 0 +#define CONFIG_REDUCE_PHY_TX_POWER 1 +#define CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1 1 +#define CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC 1 +#define CONFIG_ESP32_RTC_CLK_CAL_CYCLES 1024 +#define CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY 2000 +#define CONFIG_ESP32_XTAL_FREQ_40 1 +#define CONFIG_ESP32_XTAL_FREQ 40 +#define CONFIG_ESP_ERR_TO_NAME_LOOKUP 1 +#define CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM 10 +#define CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM 32 +#define CONFIG_ESP32_WIFI_STATIC_TX_BUFFER 1 +#define CONFIG_ESP32_WIFI_TX_BUFFER_TYPE 0 +#define CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM 16 +#define CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED 1 +#define CONFIG_ESP32_WIFI_TX_BA_WIN 6 +#define CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED 1 +#define CONFIG_ESP32_WIFI_RX_BA_WIN 6 +#define CONFIG_ESP32_WIFI_NVS_ENABLED 1 +#define CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0 1 +#define CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN 752 +#define CONFIG_ESP32_WIFI_MGMT_SBUF_NUM 32 +#define CONFIG_ESP32_WIFI_IRAM_OPT 1 +#define CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE 1 +#define CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER 20 +#define CONFIG_ESP32_PHY_MAX_TX_POWER 20 +#define CONFIG_PM_ENABLE 1 +#define CONFIG_ADC_CAL_EFUSE_TP_ENABLE 1 +#define CONFIG_ADC_CAL_EFUSE_VREF_ENABLE 1 +#define CONFIG_ADC_CAL_LUT_ENABLE 1 +#define CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS 1 +#define CONFIG_HTTPD_MAX_REQ_HDR_LEN 512 +#define CONFIG_HTTPD_MAX_URI_LEN 512 +#define CONFIG_HTTPD_ERR_RESP_NO_DELAY 1 +#define CONFIG_HTTPD_PURGE_BUF_LEN 32 +#define CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE 1 +#define CONFIG_DMA_RX_BUF_NUM 10 +#define CONFIG_DMA_TX_BUF_NUM 10 +#define CONFIG_EMAC_L2_TO_L3_RX_BUF_MODE 1 +#define CONFIG_EMAC_CHECK_LINK_PERIOD_MS 2000 +#define CONFIG_EMAC_TASK_PRIORITY 20 +#define CONFIG_EMAC_TASK_STACK_SIZE 3072 +#define CONFIG_FATFS_CODEPAGE_437 1 +#define CONFIG_FATFS_CODEPAGE 437 +#define CONFIG_FATFS_LFN_NONE 1 +#define CONFIG_FATFS_FS_LOCK 0 +#define CONFIG_FATFS_TIMEOUT_MS 10000 +#define CONFIG_FATFS_PER_FILE_CACHE 1 +#define CONFIG_FATFS_ALLOC_PREFER_EXTRAM 1 +#define CONFIG_MB_QUEUE_LENGTH 20 +#define CONFIG_MB_SERIAL_TASK_STACK_SIZE 2048 +#define CONFIG_MB_SERIAL_BUF_SIZE 256 +#define CONFIG_MB_SERIAL_TASK_PRIO 10 +#define CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT 20 +#define CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE 20 +#define CONFIG_MB_CONTROLLER_STACK_SIZE 4096 +#define CONFIG_MB_EVENT_QUEUE_TIMEOUT 20 +#define CONFIG_MB_TIMER_PORT_ENABLED 1 +#define CONFIG_MB_TIMER_GROUP 0 +#define CONFIG_MB_TIMER_INDEX 0 +#define CONFIG_FREERTOS_NO_AFFINITY 0x7FFFFFFF +#define CONFIG_FREERTOS_CORETIMER_0 1 +#define CONFIG_FREERTOS_HZ 100 +#define CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION 1 +#define CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY 1 +#define CONFIG_FREERTOS_INTERRUPT_BACKTRACE 1 +#define CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS 1 +#define CONFIG_FREERTOS_ASSERT_FAIL_ABORT 1 +#define CONFIG_FREERTOS_IDLE_TASK_STACKSIZE 1536 +#define CONFIG_FREERTOS_ISR_STACKSIZE 1536 +#define CONFIG_FREERTOS_MAX_TASK_NAME_LEN 16 +#define CONFIG_SUPPORT_STATIC_ALLOCATION 1 +#define CONFIG_TIMER_TASK_PRIORITY 1 +#define CONFIG_TIMER_TASK_STACK_DEPTH 2048 +#define CONFIG_TIMER_QUEUE_LENGTH 10 +#define CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE 0 +#define CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER 1 +#define CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER 1 +#define CONFIG_HEAP_POISONING_DISABLED 1 +#define CONFIG_LIBSODIUM_USE_MBEDTLS_SHA 1 +#define CONFIG_LOG_DEFAULT_LEVEL_INFO 1 +#define CONFIG_LOG_DEFAULT_LEVEL 3 +#define CONFIG_LOG_COLORS 1 +#define CONFIG_LWIP_MAX_SOCKETS 16 +#define CONFIG_LWIP_SO_REUSE 1 +#define CONFIG_LWIP_SO_REUSE_RXTOALL 1 +#define CONFIG_LWIP_DHCP_MAX_NTP_SERVERS 1 +#define CONFIG_ESP_GRATUITOUS_ARP 1 +#define CONFIG_GARP_TMR_INTERVAL 60 +#define CONFIG_TCPIP_RECVMBOX_SIZE 32 +#define CONFIG_LWIP_DHCP_DOES_ARP_CHECK 1 +#define CONFIG_LWIP_DHCPS_LEASE_UNIT 60 +#define CONFIG_LWIP_DHCPS_MAX_STATION_NUM 8 +#define CONFIG_LWIP_NETIF_LOOPBACK 1 +#define CONFIG_LWIP_LOOPBACK_MAX_PBUFS 8 +#define CONFIG_LWIP_MAX_ACTIVE_TCP 16 +#define CONFIG_LWIP_MAX_LISTENING_TCP 16 +#define CONFIG_TCP_MAXRTX 12 +#define CONFIG_TCP_SYNMAXRTX 6 +#define CONFIG_TCP_MSS 1436 +#define CONFIG_TCP_MSL 60000 +#define CONFIG_TCP_SND_BUF_DEFAULT 5744 +#define CONFIG_TCP_WND_DEFAULT 5744 +#define CONFIG_TCP_RECVMBOX_SIZE 6 +#define CONFIG_TCP_QUEUE_OOSEQ 1 +#define CONFIG_TCP_OVERSIZE_MSS 1 +#define CONFIG_LWIP_MAX_UDP_PCBS 16 +#define CONFIG_UDP_RECVMBOX_SIZE 6 +#define CONFIG_TCPIP_TASK_STACK_SIZE 3072 +#define CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY 1 +#define CONFIG_TCPIP_TASK_AFFINITY 0x7FFFFFFF +#define CONFIG_LWIP_MULTICAST_PING 1 +#define CONFIG_LWIP_MAX_RAW_PCBS 16 +#define CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC 1 +#define CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN 16384 +#define CONFIG_MBEDTLS_HARDWARE_AES 1 +#define CONFIG_MBEDTLS_HAVE_TIME 1 +#define CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT 1 +#define CONFIG_MBEDTLS_TLS_SERVER 1 +#define CONFIG_MBEDTLS_TLS_CLIENT 1 +#define CONFIG_MBEDTLS_TLS_ENABLED 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_RSA 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA 1 +#define CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA 1 +#define CONFIG_MBEDTLS_SSL_RENEGOTIATION 1 +#define CONFIG_MBEDTLS_SSL_PROTO_TLS1 1 +#define CONFIG_MBEDTLS_SSL_PROTO_TLS1_1 1 +#define CONFIG_MBEDTLS_SSL_PROTO_TLS1_2 1 +#define CONFIG_MBEDTLS_SSL_ALPN 1 +#define CONFIG_MBEDTLS_SSL_SESSION_TICKETS 1 +#define CONFIG_MBEDTLS_AES_C 1 +#define CONFIG_MBEDTLS_RC4_DISABLED 1 +#define CONFIG_MBEDTLS_CCM_C 1 +#define CONFIG_MBEDTLS_GCM_C 1 +#define CONFIG_MBEDTLS_PEM_PARSE_C 1 +#define CONFIG_MBEDTLS_PEM_WRITE_C 1 +#define CONFIG_MBEDTLS_X509_CRL_PARSE_C 1 +#define CONFIG_MBEDTLS_X509_CSR_PARSE_C 1 +#define CONFIG_MBEDTLS_ECP_C 1 +#define CONFIG_MBEDTLS_ECDH_C 1 +#define CONFIG_MBEDTLS_ECDSA_C 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED 1 +#define CONFIG_MBEDTLS_ECP_NIST_OPTIM 1 +#define CONFIG_MDNS_MAX_SERVICES 10 +#define CONFIG_MQTT_PROTOCOL_311 1 +#define CONFIG_MQTT_TRANSPORT_SSL 1 +#define CONFIG_MQTT_TRANSPORT_WEBSOCKET 1 +#define CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE 1 +#define CONFIG_OPENSSL_ASSERT_DO_NOTHING 1 +#define CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT 5 +#define CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT 3072 +#define CONFIG_PTHREAD_STACK_MIN 768 +#define CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY 1 +#define CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT -1 +#define CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT "pthread" +#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1 +#define CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS 1 +#define CONFIG_SPI_FLASH_YIELD_DURING_ERASE 1 +#define CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS 20 +#define CONFIG_SPI_FLASH_ERASE_YIELD_TICKS 1 +#define CONFIG_SPIFFS_MAX_PARTITIONS 3 +#define CONFIG_SPIFFS_CACHE 1 +#define CONFIG_SPIFFS_CACHE_WR 1 +#define CONFIG_SPIFFS_PAGE_CHECK 1 +#define CONFIG_SPIFFS_GC_MAX_RUNS 10 +#define CONFIG_SPIFFS_PAGE_SIZE 256 +#define CONFIG_SPIFFS_OBJ_NAME_LEN 32 +#define CONFIG_SPIFFS_USE_MAGIC 1 +#define CONFIG_SPIFFS_USE_MAGIC_LENGTH 1 +#define CONFIG_SPIFFS_META_LENGTH 4 +#define CONFIG_SPIFFS_USE_MTIME 1 +#define CONFIG_IP_LOST_TIMER_INTERVAL 120 +#define CONFIG_TCPIP_LWIP 1 +#define CONFIG_UNITY_ENABLE_FLOAT 1 +#define CONFIG_UNITY_ENABLE_DOUBLE 1 +#define CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER 1 +#define CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT 1 +#define CONFIG_SUPPORT_TERMIOS 1 +#define CONFIG_WL_SECTOR_SIZE_4096 1 +#define CONFIG_WL_SECTOR_SIZE 4096 +#define CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES 16 diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/sdkconfig.txt b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/sdkconfig.txt new file mode 100644 index 00000000..3c4da6c8 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/sdkconfig.txt @@ -0,0 +1,737 @@ +# +# Automatically generated file. DO NOT EDIT. +# Espressif IoT Development Framework (ESP-IDF) Project Configuration +# +CONFIG_IDF_TARGET="esp32" + +# +# SDK tool configuration +# +CONFIG_TOOLPREFIX="xtensa-esp32-elf-" +CONFIG_MAKE_WARN_UNDEFINED_VARIABLES=y +CONFIG_APP_COMPILE_TIME_DATE=y +# CONFIG_APP_EXCLUDE_PROJECT_VER_VAR is not set +# CONFIG_APP_EXCLUDE_PROJECT_NAME_VAR is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_NONE is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_ERROR is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_WARN is not set +CONFIG_LOG_BOOTLOADER_LEVEL_INFO=y +# CONFIG_LOG_BOOTLOADER_LEVEL_DEBUG is not set +# CONFIG_LOG_BOOTLOADER_LEVEL_VERBOSE is not set +CONFIG_LOG_BOOTLOADER_LEVEL=3 +# CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_8V is not set +CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V=y +# CONFIG_BOOTLOADER_FACTORY_RESET is not set +# CONFIG_BOOTLOADER_APP_TEST is not set +CONFIG_BOOTLOADER_WDT_ENABLE=y +# CONFIG_BOOTLOADER_WDT_DISABLE_IN_USER_CODE is not set +CONFIG_BOOTLOADER_WDT_TIME_MS=9000 +# CONFIG_APP_ROLLBACK_ENABLE is not set +# CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT is not set +# CONFIG_SECURE_BOOT_ENABLED is not set +# CONFIG_FLASH_ENCRYPTION_ENABLED is not set +CONFIG_ESPTOOLPY_BAUD_OTHER_VAL=115200 +# CONFIG_FLASHMODE_QIO is not set +# CONFIG_FLASHMODE_QOUT is not set +CONFIG_FLASHMODE_DIO=y +# CONFIG_FLASHMODE_DOUT is not set +CONFIG_ESPTOOLPY_FLASHMODE="dio" +# CONFIG_ESPTOOLPY_FLASHFREQ_80M is not set +CONFIG_ESPTOOLPY_FLASHFREQ_40M=y +# CONFIG_ESPTOOLPY_FLASHFREQ_26M is not set +# CONFIG_ESPTOOLPY_FLASHFREQ_20M is not set +CONFIG_ESPTOOLPY_FLASHFREQ="40m" +# CONFIG_ESPTOOLPY_FLASHSIZE_1MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_2MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE_4MB=y +# CONFIG_ESPTOOLPY_FLASHSIZE_8MB is not set +# CONFIG_ESPTOOLPY_FLASHSIZE_16MB is not set +CONFIG_ESPTOOLPY_FLASHSIZE="4MB" +CONFIG_ESPTOOLPY_FLASHSIZE_DETECT=y +CONFIG_ESPTOOLPY_BEFORE_RESET=y +# CONFIG_ESPTOOLPY_BEFORE_NORESET is not set +CONFIG_ESPTOOLPY_BEFORE="default_reset" +CONFIG_ESPTOOLPY_AFTER_RESET=y +# CONFIG_ESPTOOLPY_AFTER_NORESET is not set +CONFIG_ESPTOOLPY_AFTER="hard_reset" +# CONFIG_MONITOR_BAUD_9600B is not set +# CONFIG_MONITOR_BAUD_57600B is not set +CONFIG_MONITOR_BAUD_115200B=y +# CONFIG_MONITOR_BAUD_230400B is not set +# CONFIG_MONITOR_BAUD_921600B is not set +# CONFIG_MONITOR_BAUD_2MB is not set +# CONFIG_MONITOR_BAUD_OTHER is not set +CONFIG_MONITOR_BAUD_OTHER_VAL=115200 +CONFIG_MONITOR_BAUD=115200 +CONFIG_PARTITION_TABLE_SINGLE_APP=y +# CONFIG_PARTITION_TABLE_TWO_OTA is not set +# CONFIG_PARTITION_TABLE_CUSTOM is not set +CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.csv" +CONFIG_PARTITION_TABLE_FILENAME="partitions_singleapp.csv" +CONFIG_PARTITION_TABLE_OFFSET=0x8000 +CONFIG_PARTITION_TABLE_MD5=y +CONFIG_OPTIMIZATION_LEVEL_DEBUG=y +# CONFIG_OPTIMIZATION_LEVEL_RELEASE is not set +CONFIG_OPTIMIZATION_ASSERTIONS_ENABLED=y +# CONFIG_OPTIMIZATION_ASSERTIONS_SILENT is not set +# CONFIG_OPTIMIZATION_ASSERTIONS_DISABLED is not set +# CONFIG_CXX_EXCEPTIONS is not set +CONFIG_STACK_CHECK_NONE=y +# CONFIG_STACK_CHECK_NORM is not set +# CONFIG_STACK_CHECK_STRONG is not set +# CONFIG_STACK_CHECK_ALL is not set +# CONFIG_STACK_CHECK is not set +# CONFIG_WARN_WRITE_STRINGS is not set +# CONFIG_DISABLE_GCC8_WARNINGS is not set +# CONFIG_ESP32_APPTRACE_DEST_TRAX is not set +CONFIG_ESP32_APPTRACE_DEST_NONE=y +# CONFIG_ESP32_APPTRACE_ENABLE is not set +CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y +# CONFIG_AWS_IOT_SDK is not set +CONFIG_BT_ENABLED=y +CONFIG_BTDM_CONTROLLER_MODE_BLE_ONLY=y +# CONFIG_BTDM_CONTROLLER_MODE_BR_EDR_ONLY is not set +# CONFIG_BTDM_CONTROLLER_MODE_BTDM is not set +CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN=3 +CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF=3 +CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF=0 +CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE_0=y +# CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE_1 is not set +CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE=0 +CONFIG_BTDM_CONTROLLER_HCI_MODE_VHCI=y +# CONFIG_BTDM_CONTROLLER_HCI_MODE_UART_H4 is not set +CONFIG_BTDM_CONTROLLER_MODEM_SLEEP=y +CONFIG_BTDM_MODEM_SLEEP_MODE_ORIG=y +# CONFIG_BTDM_MODEM_SLEEP_MODE_EVED is not set +CONFIG_BTDM_LPCLK_SEL_MAIN_XTAL=y +CONFIG_BLE_SCAN_DUPLICATE=y +CONFIG_SCAN_DUPLICATE_BY_DEVICE_ADDR=y +# CONFIG_SCAN_DUPLICATE_BY_ADV_DATA is not set +# CONFIG_SCAN_DUPLICATE_BY_ADV_DATA_AND_DEVICE_ADDR is not set +CONFIG_SCAN_DUPLICATE_TYPE=0 +CONFIG_DUPLICATE_SCAN_CACHE_SIZE=200 +# CONFIG_BLE_MESH_SCAN_DUPLICATE_EN is not set +# CONFIG_BTDM_CONTROLLER_FULL_SCAN_SUPPORTED is not set +CONFIG_BLE_ADV_REPORT_FLOW_CONTROL_SUPPORTED=y +CONFIG_BLE_ADV_REPORT_FLOW_CONTROL_NUM=100 +CONFIG_BLE_ADV_REPORT_DISCARD_THRSHOLD=20 +CONFIG_BLUEDROID_ENABLED=y +CONFIG_BLUEDROID_PINNED_TO_CORE_0=y +# CONFIG_BLUEDROID_PINNED_TO_CORE_1 is not set +CONFIG_BLUEDROID_PINNED_TO_CORE=0 +CONFIG_BTC_TASK_STACK_SIZE=3072 +CONFIG_BTU_TASK_STACK_SIZE=4096 +# CONFIG_BLUEDROID_MEM_DEBUG is not set +# CONFIG_CLASSIC_BT_ENABLED is not set +CONFIG_GATTS_ENABLE=y +# CONFIG_GATTS_SEND_SERVICE_CHANGE_MANUAL is not set +CONFIG_GATTS_SEND_SERVICE_CHANGE_AUTO=y +CONFIG_GATTS_SEND_SERVICE_CHANGE_MODE=0 +CONFIG_GATTC_ENABLE=y +# CONFIG_GATTC_CACHE_NVS_FLASH is not set +CONFIG_BLE_SMP_ENABLE=y +# CONFIG_SMP_SLAVE_CON_PARAMS_UPD_ENABLE is not set +# CONFIG_BT_STACK_NO_LOG is not set +# CONFIG_HCI_TRACE_LEVEL_NONE is not set +# CONFIG_HCI_TRACE_LEVEL_ERROR is not set +CONFIG_HCI_TRACE_LEVEL_WARNING=y +# CONFIG_HCI_TRACE_LEVEL_API is not set +# CONFIG_HCI_TRACE_LEVEL_EVENT is not set +# CONFIG_HCI_TRACE_LEVEL_DEBUG is not set +# CONFIG_HCI_TRACE_LEVEL_VERBOSE is not set +CONFIG_HCI_INITIAL_TRACE_LEVEL=2 +# CONFIG_BTM_TRACE_LEVEL_NONE is not set +# CONFIG_BTM_TRACE_LEVEL_ERROR is not set +CONFIG_BTM_TRACE_LEVEL_WARNING=y +# CONFIG_BTM_TRACE_LEVEL_API is not set +# CONFIG_BTM_TRACE_LEVEL_EVENT is not set +# CONFIG_BTM_TRACE_LEVEL_DEBUG is not set +# CONFIG_BTM_TRACE_LEVEL_VERBOSE is not set +CONFIG_BTM_INITIAL_TRACE_LEVEL=2 +# CONFIG_L2CAP_TRACE_LEVEL_NONE is not set +# CONFIG_L2CAP_TRACE_LEVEL_ERROR is not set +CONFIG_L2CAP_TRACE_LEVEL_WARNING=y +# CONFIG_L2CAP_TRACE_LEVEL_API is not set +# CONFIG_L2CAP_TRACE_LEVEL_EVENT is not set +# CONFIG_L2CAP_TRACE_LEVEL_DEBUG is not set +# CONFIG_L2CAP_TRACE_LEVEL_VERBOSE is not set +CONFIG_L2CAP_INITIAL_TRACE_LEVEL=2 +# CONFIG_RFCOMM_TRACE_LEVEL_NONE is not set +# CONFIG_RFCOMM_TRACE_LEVEL_ERROR is not set +CONFIG_RFCOMM_TRACE_LEVEL_WARNING=y +# CONFIG_RFCOMM_TRACE_LEVEL_API is not set +# CONFIG_RFCOMM_TRACE_LEVEL_EVENT is not set +# CONFIG_RFCOMM_TRACE_LEVEL_DEBUG is not set +# CONFIG_RFCOMM_TRACE_LEVEL_VERBOSE is not set +CONFIG_RFCOMM_INITIAL_TRACE_LEVEL=2 +# CONFIG_SDP_TRACE_LEVEL_NONE is not set +# CONFIG_SDP_TRACE_LEVEL_ERROR is not set +CONFIG_SDP_TRACE_LEVEL_WARNING=y +# CONFIG_SDP_TRACE_LEVEL_API is not set +# CONFIG_SDP_TRACE_LEVEL_EVENT is not set +# CONFIG_SDP_TRACE_LEVEL_DEBUG is not set +# CONFIG_SDP_TRACE_LEVEL_VERBOSE is not set +CONFIG_SDP_INITIAL_TRACE_LEVEL=2 +# CONFIG_GAP_TRACE_LEVEL_NONE is not set +# CONFIG_GAP_TRACE_LEVEL_ERROR is not set +CONFIG_GAP_TRACE_LEVEL_WARNING=y +# CONFIG_GAP_TRACE_LEVEL_API is not set +# CONFIG_GAP_TRACE_LEVEL_EVENT is not set +# CONFIG_GAP_TRACE_LEVEL_DEBUG is not set +# CONFIG_GAP_TRACE_LEVEL_VERBOSE is not set +CONFIG_GAP_INITIAL_TRACE_LEVEL=2 +# CONFIG_BNEP_TRACE_LEVEL_NONE is not set +# CONFIG_BNEP_TRACE_LEVEL_ERROR is not set +CONFIG_BNEP_TRACE_LEVEL_WARNING=y +# CONFIG_BNEP_TRACE_LEVEL_API is not set +# CONFIG_BNEP_TRACE_LEVEL_EVENT is not set +# CONFIG_BNEP_TRACE_LEVEL_DEBUG is not set +# CONFIG_BNEP_TRACE_LEVEL_VERBOSE is not set +CONFIG_BNEP_INITIAL_TRACE_LEVEL=2 +# CONFIG_PAN_TRACE_LEVEL_NONE is not set +# CONFIG_PAN_TRACE_LEVEL_ERROR is not set +CONFIG_PAN_TRACE_LEVEL_WARNING=y +# CONFIG_PAN_TRACE_LEVEL_API is not set +# CONFIG_PAN_TRACE_LEVEL_EVENT is not set +# CONFIG_PAN_TRACE_LEVEL_DEBUG is not set +# CONFIG_PAN_TRACE_LEVEL_VERBOSE is not set +CONFIG_PAN_INITIAL_TRACE_LEVEL=2 +# CONFIG_A2D_TRACE_LEVEL_NONE is not set +# CONFIG_A2D_TRACE_LEVEL_ERROR is not set +CONFIG_A2D_TRACE_LEVEL_WARNING=y +# CONFIG_A2D_TRACE_LEVEL_API is not set +# CONFIG_A2D_TRACE_LEVEL_EVENT is not set +# CONFIG_A2D_TRACE_LEVEL_DEBUG is not set +# CONFIG_A2D_TRACE_LEVEL_VERBOSE is not set +CONFIG_A2D_INITIAL_TRACE_LEVEL=2 +# CONFIG_AVDT_TRACE_LEVEL_NONE is not set +# CONFIG_AVDT_TRACE_LEVEL_ERROR is not set +CONFIG_AVDT_TRACE_LEVEL_WARNING=y +# CONFIG_AVDT_TRACE_LEVEL_API is not set +# CONFIG_AVDT_TRACE_LEVEL_EVENT is not set +# CONFIG_AVDT_TRACE_LEVEL_DEBUG is not set +# CONFIG_AVDT_TRACE_LEVEL_VERBOSE is not set +CONFIG_AVDT_INITIAL_TRACE_LEVEL=2 +# CONFIG_AVCT_TRACE_LEVEL_NONE is not set +# CONFIG_AVCT_TRACE_LEVEL_ERROR is not set +CONFIG_AVCT_TRACE_LEVEL_WARNING=y +# CONFIG_AVCT_TRACE_LEVEL_API is not set +# CONFIG_AVCT_TRACE_LEVEL_EVENT is not set +# CONFIG_AVCT_TRACE_LEVEL_DEBUG is not set +# CONFIG_AVCT_TRACE_LEVEL_VERBOSE is not set +CONFIG_AVCT_INITIAL_TRACE_LEVEL=2 +# CONFIG_AVRC_TRACE_LEVEL_NONE is not set +# CONFIG_AVRC_TRACE_LEVEL_ERROR is not set +CONFIG_AVRC_TRACE_LEVEL_WARNING=y +# CONFIG_AVRC_TRACE_LEVEL_API is not set +# CONFIG_AVRC_TRACE_LEVEL_EVENT is not set +# CONFIG_AVRC_TRACE_LEVEL_DEBUG is not set +# CONFIG_AVRC_TRACE_LEVEL_VERBOSE is not set +CONFIG_AVRC_INITIAL_TRACE_LEVEL=2 +# CONFIG_MCA_TRACE_LEVEL_NONE is not set +# CONFIG_MCA_TRACE_LEVEL_ERROR is not set +CONFIG_MCA_TRACE_LEVEL_WARNING=y +# CONFIG_MCA_TRACE_LEVEL_API is not set +# CONFIG_MCA_TRACE_LEVEL_EVENT is not set +# CONFIG_MCA_TRACE_LEVEL_DEBUG is not set +# CONFIG_MCA_TRACE_LEVEL_VERBOSE is not set +CONFIG_MCA_INITIAL_TRACE_LEVEL=2 +# CONFIG_HID_TRACE_LEVEL_NONE is not set +# CONFIG_HID_TRACE_LEVEL_ERROR is not set +CONFIG_HID_TRACE_LEVEL_WARNING=y +# CONFIG_HID_TRACE_LEVEL_API is not set +# CONFIG_HID_TRACE_LEVEL_EVENT is not set +# CONFIG_HID_TRACE_LEVEL_DEBUG is not set +# CONFIG_HID_TRACE_LEVEL_VERBOSE is not set +CONFIG_HID_INITIAL_TRACE_LEVEL=2 +# CONFIG_APPL_TRACE_LEVEL_NONE is not set +# CONFIG_APPL_TRACE_LEVEL_ERROR is not set +CONFIG_APPL_TRACE_LEVEL_WARNING=y +# CONFIG_APPL_TRACE_LEVEL_API is not set +# CONFIG_APPL_TRACE_LEVEL_EVENT is not set +# CONFIG_APPL_TRACE_LEVEL_DEBUG is not set +# CONFIG_APPL_TRACE_LEVEL_VERBOSE is not set +CONFIG_APPL_INITIAL_TRACE_LEVEL=2 +# CONFIG_GATT_TRACE_LEVEL_NONE is not set +# CONFIG_GATT_TRACE_LEVEL_ERROR is not set +CONFIG_GATT_TRACE_LEVEL_WARNING=y +# CONFIG_GATT_TRACE_LEVEL_API is not set +# CONFIG_GATT_TRACE_LEVEL_EVENT is not set +# CONFIG_GATT_TRACE_LEVEL_DEBUG is not set +# CONFIG_GATT_TRACE_LEVEL_VERBOSE is not set +CONFIG_GATT_INITIAL_TRACE_LEVEL=2 +# CONFIG_SMP_TRACE_LEVEL_NONE is not set +# CONFIG_SMP_TRACE_LEVEL_ERROR is not set +CONFIG_SMP_TRACE_LEVEL_WARNING=y +# CONFIG_SMP_TRACE_LEVEL_API is not set +# CONFIG_SMP_TRACE_LEVEL_EVENT is not set +# CONFIG_SMP_TRACE_LEVEL_DEBUG is not set +# CONFIG_SMP_TRACE_LEVEL_VERBOSE is not set +CONFIG_SMP_INITIAL_TRACE_LEVEL=2 +# CONFIG_BTIF_TRACE_LEVEL_NONE is not set +# CONFIG_BTIF_TRACE_LEVEL_ERROR is not set +CONFIG_BTIF_TRACE_LEVEL_WARNING=y +# CONFIG_BTIF_TRACE_LEVEL_API is not set +# CONFIG_BTIF_TRACE_LEVEL_EVENT is not set +# CONFIG_BTIF_TRACE_LEVEL_DEBUG is not set +# CONFIG_BTIF_TRACE_LEVEL_VERBOSE is not set +CONFIG_BTIF_INITIAL_TRACE_LEVEL=2 +# CONFIG_BTC_TRACE_LEVEL_NONE is not set +# CONFIG_BTC_TRACE_LEVEL_ERROR is not set +CONFIG_BTC_TRACE_LEVEL_WARNING=y +# CONFIG_BTC_TRACE_LEVEL_API is not set +# CONFIG_BTC_TRACE_LEVEL_EVENT is not set +# CONFIG_BTC_TRACE_LEVEL_DEBUG is not set +# CONFIG_BTC_TRACE_LEVEL_VERBOSE is not set +CONFIG_BTC_INITIAL_TRACE_LEVEL=2 +# CONFIG_OSI_TRACE_LEVEL_NONE is not set +# CONFIG_OSI_TRACE_LEVEL_ERROR is not set +CONFIG_OSI_TRACE_LEVEL_WARNING=y +# CONFIG_OSI_TRACE_LEVEL_API is not set +# CONFIG_OSI_TRACE_LEVEL_EVENT is not set +# CONFIG_OSI_TRACE_LEVEL_DEBUG is not set +# CONFIG_OSI_TRACE_LEVEL_VERBOSE is not set +CONFIG_OSI_INITIAL_TRACE_LEVEL=2 +# CONFIG_BLUFI_TRACE_LEVEL_NONE is not set +# CONFIG_BLUFI_TRACE_LEVEL_ERROR is not set +CONFIG_BLUFI_TRACE_LEVEL_WARNING=y +# CONFIG_BLUFI_TRACE_LEVEL_API is not set +# CONFIG_BLUFI_TRACE_LEVEL_EVENT is not set +# CONFIG_BLUFI_TRACE_LEVEL_DEBUG is not set +# CONFIG_BLUFI_TRACE_LEVEL_VERBOSE is not set +CONFIG_BLUFI_INITIAL_TRACE_LEVEL=2 +CONFIG_BT_ACL_CONNECTIONS=4 +# CONFIG_BT_ALLOCATION_FROM_SPIRAM_FIRST is not set +# CONFIG_BT_BLE_DYNAMIC_ENV_MEMORY is not set +# CONFIG_BLE_HOST_QUEUE_CONGESTION_CHECK is not set +CONFIG_SMP_ENABLE=y +# CONFIG_BLE_ACTIVE_SCAN_REPORT_ADV_SCAN_RSP_INDIVIDUALLY is not set +CONFIG_BLE_ESTABLISH_LINK_CONNECTION_TIMEOUT=30 +CONFIG_BT_RESERVE_DRAM=0xdb5c +# CONFIG_ADC_FORCE_XPD_FSM is not set +CONFIG_ADC2_DISABLE_DAC=y +CONFIG_SPI_MASTER_IN_IRAM=y +CONFIG_SPI_MASTER_ISR_IN_IRAM=y +# CONFIG_SPI_SLAVE_IN_IRAM is not set +CONFIG_SPI_SLAVE_ISR_IN_IRAM=y +# CONFIG_EFUSE_CUSTOM_TABLE is not set +# CONFIG_EFUSE_VIRTUAL is not set +# CONFIG_EFUSE_CODE_SCHEME_COMPAT_NONE is not set +CONFIG_EFUSE_CODE_SCHEME_COMPAT_3_4=y +# CONFIG_EFUSE_CODE_SCHEME_COMPAT_REPEAT is not set +CONFIG_EFUSE_MAX_BLK_LEN=192 +CONFIG_IDF_TARGET_ESP32=y +# CONFIG_ESP32_REV_MIN_0 is not set +CONFIG_ESP32_REV_MIN_1=y +# CONFIG_ESP32_REV_MIN_2 is not set +# CONFIG_ESP32_REV_MIN_3 is not set +CONFIG_ESP32_REV_MIN=1 +CONFIG_ESP32_DPORT_WORKAROUND=y +# CONFIG_ESP32_DEFAULT_CPU_FREQ_80 is not set +CONFIG_ESP32_DEFAULT_CPU_FREQ_160=y +# CONFIG_ESP32_DEFAULT_CPU_FREQ_240 is not set +CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ=160 +CONFIG_SPIRAM_SUPPORT=y +CONFIG_SPIRAM_BOOT_INIT=y +CONFIG_SPIRAM_IGNORE_NOTFOUND=y +# CONFIG_SPIRAM_USE_MEMMAP is not set +# CONFIG_SPIRAM_USE_CAPS_ALLOC is not set +CONFIG_SPIRAM_USE_MALLOC=y +CONFIG_SPIRAM_TYPE_AUTO=y +# CONFIG_SPIRAM_TYPE_ESPPSRAM32 is not set +# CONFIG_SPIRAM_TYPE_ESPPSRAM64 is not set +CONFIG_SPIRAM_SIZE=-1 +CONFIG_SPIRAM_SPEED_40M=y +CONFIG_SPIRAM_MEMTEST=y +CONFIG_SPIRAM_CACHE_WORKAROUND=y +CONFIG_SPIRAM_BANKSWITCH_ENABLE=y +CONFIG_SPIRAM_BANKSWITCH_RESERVE=8 +CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=16384 +# CONFIG_WIFI_LWIP_ALLOCATION_FROM_SPIRAM_FIRST is not set +CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL=32768 +# CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is not set +# CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY is not set +CONFIG_D0WD_PSRAM_CLK_IO=17 +CONFIG_D0WD_PSRAM_CS_IO=16 +CONFIG_D2WD_PSRAM_CLK_IO=9 +CONFIG_D2WD_PSRAM_CS_IO=10 +CONFIG_PICO_PSRAM_CS_IO=10 +CONFIG_SPIRAM_SPIWP_SD3_PIN=7 +# CONFIG_MEMMAP_TRACEMEM is not set +# CONFIG_MEMMAP_TRACEMEM_TWOBANKS is not set +# CONFIG_ESP32_TRAX is not set +CONFIG_TRACEMEM_RESERVE_DRAM=0x0 +# CONFIG_TWO_UNIVERSAL_MAC_ADDRESS is not set +CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS=y +CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS=4 +CONFIG_SYSTEM_EVENT_QUEUE_SIZE=32 +CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE=2304 +CONFIG_MAIN_TASK_STACK_SIZE=3584 +CONFIG_IPC_TASK_STACK_SIZE=1024 +CONFIG_TIMER_TASK_STACK_SIZE=3584 +CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF=y +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_LF is not set +# CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF is not set +# CONFIG_NEWLIB_STDIN_LINE_ENDING_LF is not set +CONFIG_NEWLIB_STDIN_LINE_ENDING_CR=y +# CONFIG_NEWLIB_NANO_FORMAT is not set +CONFIG_CONSOLE_UART_DEFAULT=y +# CONFIG_CONSOLE_UART_CUSTOM is not set +# CONFIG_CONSOLE_UART_NONE is not set +CONFIG_CONSOLE_UART_NUM=0 +CONFIG_CONSOLE_UART_BAUDRATE=115200 +# CONFIG_ULP_COPROC_ENABLED is not set +CONFIG_ULP_COPROC_RESERVE_MEM=0 +# CONFIG_ESP32_PANIC_PRINT_HALT is not set +CONFIG_ESP32_PANIC_PRINT_REBOOT=y +# CONFIG_ESP32_PANIC_SILENT_REBOOT is not set +# CONFIG_ESP32_PANIC_GDBSTUB is not set +CONFIG_ESP32_DEBUG_OCDAWARE=y +CONFIG_ESP32_DEBUG_STUBS_ENABLE=y +CONFIG_INT_WDT=y +CONFIG_INT_WDT_TIMEOUT_MS=300 +CONFIG_INT_WDT_CHECK_CPU1=y +# CONFIG_TASK_WDT is not set +CONFIG_BROWNOUT_DET=y +CONFIG_BROWNOUT_DET_LVL_SEL_0=y +# CONFIG_BROWNOUT_DET_LVL_SEL_1 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_2 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_3 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_4 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_5 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_6 is not set +# CONFIG_BROWNOUT_DET_LVL_SEL_7 is not set +CONFIG_BROWNOUT_DET_LVL=0 +CONFIG_REDUCE_PHY_TX_POWER=y +CONFIG_ESP32_TIME_SYSCALL_USE_RTC_FRC1=y +# CONFIG_ESP32_TIME_SYSCALL_USE_RTC is not set +# CONFIG_ESP32_TIME_SYSCALL_USE_FRC1 is not set +# CONFIG_ESP32_TIME_SYSCALL_USE_NONE is not set +CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_RC=y +# CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL is not set +# CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_OSC is not set +# CONFIG_ESP32_RTC_CLOCK_SOURCE_INTERNAL_8MD256 is not set +CONFIG_ESP32_RTC_CLK_CAL_CYCLES=1024 +CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY=2000 +CONFIG_ESP32_XTAL_FREQ_40=y +# CONFIG_ESP32_XTAL_FREQ_26 is not set +# CONFIG_ESP32_XTAL_FREQ_AUTO is not set +CONFIG_ESP32_XTAL_FREQ=40 +# CONFIG_DISABLE_BASIC_ROM_CONSOLE is not set +# CONFIG_ESP_TIMER_PROFILING is not set +# CONFIG_COMPATIBLE_PRE_V2_1_BOOTLOADERS is not set +CONFIG_ESP_ERR_TO_NAME_LOOKUP=y +CONFIG_SW_COEXIST_ENABLE=y +# CONFIG_SW_COEXIST_PREFERENCE_WIFI is not set +# CONFIG_SW_COEXIST_PREFERENCE_BT is not set +CONFIG_SW_COEXIST_PREFERENCE_BALANCE=y +CONFIG_SW_COEXIST_PREFERENCE_VALUE=2 +CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 +CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 +CONFIG_ESP32_WIFI_STATIC_TX_BUFFER=y +CONFIG_ESP32_WIFI_TX_BUFFER_TYPE=0 +CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM=16 +# CONFIG_ESP32_WIFI_CSI_ENABLED is not set +CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED=y +CONFIG_ESP32_WIFI_TX_BA_WIN=6 +CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED=y +CONFIG_ESP32_WIFI_RX_BA_WIN=6 +CONFIG_ESP32_WIFI_NVS_ENABLED=y +CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0=y +# CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_1 is not set +CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN=752 +CONFIG_ESP32_WIFI_MGMT_SBUF_NUM=32 +# CONFIG_ESP32_WIFI_DEBUG_LOG_ENABLE is not set +CONFIG_ESP32_WIFI_IRAM_OPT=y +CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE=y +# CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION is not set +CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER=20 +CONFIG_ESP32_PHY_MAX_TX_POWER=20 +CONFIG_PM_ENABLE=y +# CONFIG_PM_DFS_INIT_AUTO is not set +# CONFIG_PM_USE_RTC_TIMER_REF is not set +# CONFIG_PM_PROFILING is not set +# CONFIG_PM_TRACE is not set +CONFIG_ADC_CAL_EFUSE_TP_ENABLE=y +CONFIG_ADC_CAL_EFUSE_VREF_ENABLE=y +CONFIG_ADC_CAL_LUT_ENABLE=y +# CONFIG_EVENT_LOOP_PROFILING is not set +CONFIG_ESP_HTTP_CLIENT_ENABLE_HTTPS=y +CONFIG_HTTPD_MAX_REQ_HDR_LEN=512 +CONFIG_HTTPD_MAX_URI_LEN=512 +CONFIG_HTTPD_ERR_RESP_NO_DELAY=y +CONFIG_HTTPD_PURGE_BUF_LEN=32 +# CONFIG_HTTPD_LOG_PURGE_DATA is not set +# CONFIG_OTA_ALLOW_HTTP is not set +# CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set +# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set +CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y +# CONFIG_ESP32_ENABLE_COREDUMP is not set +CONFIG_DMA_RX_BUF_NUM=10 +CONFIG_DMA_TX_BUF_NUM=10 +CONFIG_EMAC_L2_TO_L3_RX_BUF_MODE=y +CONFIG_EMAC_CHECK_LINK_PERIOD_MS=2000 +CONFIG_EMAC_TASK_PRIORITY=20 +CONFIG_EMAC_TASK_STACK_SIZE=3072 +# CONFIG_FATFS_CODEPAGE_DYNAMIC is not set +CONFIG_FATFS_CODEPAGE_437=y +# CONFIG_FATFS_CODEPAGE_720 is not set +# CONFIG_FATFS_CODEPAGE_737 is not set +# CONFIG_FATFS_CODEPAGE_771 is not set +# CONFIG_FATFS_CODEPAGE_775 is not set +# CONFIG_FATFS_CODEPAGE_850 is not set +# CONFIG_FATFS_CODEPAGE_852 is not set +# CONFIG_FATFS_CODEPAGE_855 is not set +# CONFIG_FATFS_CODEPAGE_857 is not set +# CONFIG_FATFS_CODEPAGE_860 is not set +# CONFIG_FATFS_CODEPAGE_861 is not set +# CONFIG_FATFS_CODEPAGE_862 is not set +# CONFIG_FATFS_CODEPAGE_863 is not set +# CONFIG_FATFS_CODEPAGE_864 is not set +# CONFIG_FATFS_CODEPAGE_865 is not set +# CONFIG_FATFS_CODEPAGE_866 is not set +# CONFIG_FATFS_CODEPAGE_869 is not set +# CONFIG_FATFS_CODEPAGE_932 is not set +# CONFIG_FATFS_CODEPAGE_936 is not set +# CONFIG_FATFS_CODEPAGE_949 is not set +# CONFIG_FATFS_CODEPAGE_950 is not set +CONFIG_FATFS_CODEPAGE=437 +CONFIG_FATFS_LFN_NONE=y +# CONFIG_FATFS_LFN_HEAP is not set +# CONFIG_FATFS_LFN_STACK is not set +CONFIG_FATFS_FS_LOCK=0 +CONFIG_FATFS_TIMEOUT_MS=10000 +CONFIG_FATFS_PER_FILE_CACHE=y +CONFIG_FATFS_ALLOC_PREFER_EXTRAM=y +CONFIG_MB_QUEUE_LENGTH=20 +CONFIG_MB_SERIAL_TASK_STACK_SIZE=2048 +CONFIG_MB_SERIAL_BUF_SIZE=256 +CONFIG_MB_SERIAL_TASK_PRIO=10 +# CONFIG_MB_CONTROLLER_SLAVE_ID_SUPPORT is not set +CONFIG_MB_CONTROLLER_NOTIFY_TIMEOUT=20 +CONFIG_MB_CONTROLLER_NOTIFY_QUEUE_SIZE=20 +CONFIG_MB_CONTROLLER_STACK_SIZE=4096 +CONFIG_MB_EVENT_QUEUE_TIMEOUT=20 +CONFIG_MB_TIMER_PORT_ENABLED=y +CONFIG_MB_TIMER_GROUP=0 +CONFIG_MB_TIMER_INDEX=0 +# CONFIG_FREERTOS_UNICORE is not set +CONFIG_FREERTOS_NO_AFFINITY=0x7FFFFFFF +CONFIG_FREERTOS_CORETIMER_0=y +# CONFIG_FREERTOS_CORETIMER_1 is not set +CONFIG_FREERTOS_HZ=100 +CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION=y +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_NONE is not set +# CONFIG_FREERTOS_CHECK_STACKOVERFLOW_PTRVAL is not set +CONFIG_FREERTOS_CHECK_STACKOVERFLOW_CANARY=y +# CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK is not set +CONFIG_FREERTOS_INTERRUPT_BACKTRACE=y +CONFIG_FREERTOS_THREAD_LOCAL_STORAGE_POINTERS=1 +CONFIG_FREERTOS_ASSERT_FAIL_ABORT=y +# CONFIG_FREERTOS_ASSERT_FAIL_PRINT_CONTINUE is not set +# CONFIG_FREERTOS_ASSERT_DISABLE is not set +CONFIG_FREERTOS_IDLE_TASK_STACKSIZE=1536 +CONFIG_FREERTOS_ISR_STACKSIZE=1536 +# CONFIG_FREERTOS_LEGACY_HOOKS is not set +CONFIG_FREERTOS_MAX_TASK_NAME_LEN=16 +CONFIG_SUPPORT_STATIC_ALLOCATION=y +# CONFIG_ENABLE_STATIC_TASK_CLEAN_UP_HOOK is not set +CONFIG_TIMER_TASK_PRIORITY=1 +CONFIG_TIMER_TASK_STACK_DEPTH=2048 +CONFIG_TIMER_QUEUE_LENGTH=10 +CONFIG_FREERTOS_QUEUE_REGISTRY_SIZE=0 +# CONFIG_FREERTOS_USE_TRACE_FACILITY is not set +# CONFIG_FREERTOS_GENERATE_RUN_TIME_STATS is not set +# CONFIG_FREERTOS_USE_TICKLESS_IDLE is not set +# CONFIG_FREERTOS_DEBUG_INTERNALS is not set +CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER=y +CONFIG_FREERTOS_CHECK_MUTEX_GIVEN_BY_OWNER=y +# CONFIG_FREERTOS_CHECK_PORT_CRITICAL_COMPLIANCE is not set +CONFIG_HEAP_POISONING_DISABLED=y +# CONFIG_HEAP_POISONING_LIGHT is not set +# CONFIG_HEAP_POISONING_COMPREHENSIVE is not set +# CONFIG_HEAP_TRACING is not set +CONFIG_LIBSODIUM_USE_MBEDTLS_SHA=y +# CONFIG_LOG_DEFAULT_LEVEL_NONE is not set +# CONFIG_LOG_DEFAULT_LEVEL_ERROR is not set +# CONFIG_LOG_DEFAULT_LEVEL_WARN is not set +CONFIG_LOG_DEFAULT_LEVEL_INFO=y +# CONFIG_LOG_DEFAULT_LEVEL_DEBUG is not set +# CONFIG_LOG_DEFAULT_LEVEL_VERBOSE is not set +CONFIG_LOG_DEFAULT_LEVEL=3 +CONFIG_LOG_COLORS=y +# CONFIG_L2_TO_L3_COPY is not set +# CONFIG_LWIP_IRAM_OPTIMIZATION is not set +CONFIG_LWIP_MAX_SOCKETS=16 +# CONFIG_USE_ONLY_LWIP_SELECT is not set +CONFIG_LWIP_SO_REUSE=y +CONFIG_LWIP_SO_REUSE_RXTOALL=y +# CONFIG_LWIP_SO_RCVBUF is not set +CONFIG_LWIP_DHCP_MAX_NTP_SERVERS=1 +# CONFIG_LWIP_IP_FRAG is not set +# CONFIG_LWIP_IP_REASSEMBLY is not set +# CONFIG_LWIP_STATS is not set +# CONFIG_LWIP_ETHARP_TRUST_IP_MAC is not set +CONFIG_ESP_GRATUITOUS_ARP=y +CONFIG_GARP_TMR_INTERVAL=60 +CONFIG_TCPIP_RECVMBOX_SIZE=32 +CONFIG_LWIP_DHCP_DOES_ARP_CHECK=y +# CONFIG_LWIP_DHCP_RESTORE_LAST_IP is not set +CONFIG_LWIP_DHCPS_LEASE_UNIT=60 +CONFIG_LWIP_DHCPS_MAX_STATION_NUM=8 +# CONFIG_LWIP_AUTOIP is not set +CONFIG_LWIP_NETIF_LOOPBACK=y +CONFIG_LWIP_LOOPBACK_MAX_PBUFS=8 +CONFIG_LWIP_MAX_ACTIVE_TCP=16 +CONFIG_LWIP_MAX_LISTENING_TCP=16 +CONFIG_TCP_MAXRTX=12 +CONFIG_TCP_SYNMAXRTX=6 +CONFIG_TCP_MSS=1436 +CONFIG_TCP_MSL=60000 +CONFIG_TCP_SND_BUF_DEFAULT=5744 +CONFIG_TCP_WND_DEFAULT=5744 +CONFIG_TCP_RECVMBOX_SIZE=6 +CONFIG_TCP_QUEUE_OOSEQ=y +# CONFIG_ESP_TCP_KEEP_CONNECTION_WHEN_IP_CHANGES is not set +CONFIG_TCP_OVERSIZE_MSS=y +# CONFIG_TCP_OVERSIZE_QUARTER_MSS is not set +# CONFIG_TCP_OVERSIZE_DISABLE is not set +CONFIG_LWIP_MAX_UDP_PCBS=16 +CONFIG_UDP_RECVMBOX_SIZE=6 +CONFIG_TCPIP_TASK_STACK_SIZE=3072 +CONFIG_TCPIP_TASK_AFFINITY_NO_AFFINITY=y +# CONFIG_TCPIP_TASK_AFFINITY_CPU0 is not set +# CONFIG_TCPIP_TASK_AFFINITY_CPU1 is not set +CONFIG_TCPIP_TASK_AFFINITY=0x7FFFFFFF +# CONFIG_PPP_SUPPORT is not set +CONFIG_LWIP_MULTICAST_PING=y +# CONFIG_LWIP_BROADCAST_PING is not set +CONFIG_LWIP_MAX_RAW_PCBS=16 +CONFIG_MBEDTLS_INTERNAL_MEM_ALLOC=y +# CONFIG_MBEDTLS_EXTERNAL_MEM_ALLOC is not set +# CONFIG_MBEDTLS_DEFAULT_MEM_ALLOC is not set +# CONFIG_MBEDTLS_CUSTOM_MEM_ALLOC is not set +CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN=16384 +# CONFIG_MBEDTLS_ASYMMETRIC_CONTENT_LEN is not set +# CONFIG_MBEDTLS_DEBUG is not set +CONFIG_MBEDTLS_HARDWARE_AES=y +# CONFIG_MBEDTLS_HARDWARE_MPI is not set +# CONFIG_MBEDTLS_HARDWARE_SHA is not set +CONFIG_MBEDTLS_HAVE_TIME=y +# CONFIG_MBEDTLS_HAVE_TIME_DATE is not set +CONFIG_MBEDTLS_TLS_SERVER_AND_CLIENT=y +# CONFIG_MBEDTLS_TLS_SERVER_ONLY is not set +# CONFIG_MBEDTLS_TLS_CLIENT_ONLY is not set +# CONFIG_MBEDTLS_TLS_DISABLED is not set +CONFIG_MBEDTLS_TLS_SERVER=y +CONFIG_MBEDTLS_TLS_CLIENT=y +CONFIG_MBEDTLS_TLS_ENABLED=y +# CONFIG_MBEDTLS_PSK_MODES is not set +CONFIG_MBEDTLS_KEY_EXCHANGE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ELLIPTIC_CURVE=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA=y +CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA=y +CONFIG_MBEDTLS_SSL_RENEGOTIATION=y +# CONFIG_MBEDTLS_SSL_PROTO_SSL3 is not set +CONFIG_MBEDTLS_SSL_PROTO_TLS1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_1=y +CONFIG_MBEDTLS_SSL_PROTO_TLS1_2=y +# CONFIG_MBEDTLS_SSL_PROTO_DTLS is not set +CONFIG_MBEDTLS_SSL_ALPN=y +CONFIG_MBEDTLS_SSL_SESSION_TICKETS=y +CONFIG_MBEDTLS_AES_C=y +# CONFIG_MBEDTLS_CAMELLIA_C is not set +# CONFIG_MBEDTLS_DES_C is not set +CONFIG_MBEDTLS_RC4_DISABLED=y +# CONFIG_MBEDTLS_RC4_ENABLED_NO_DEFAULT is not set +# CONFIG_MBEDTLS_RC4_ENABLED is not set +# CONFIG_MBEDTLS_BLOWFISH_C is not set +# CONFIG_MBEDTLS_XTEA_C is not set +CONFIG_MBEDTLS_CCM_C=y +CONFIG_MBEDTLS_GCM_C=y +# CONFIG_MBEDTLS_RIPEMD160_C is not set +CONFIG_MBEDTLS_PEM_PARSE_C=y +CONFIG_MBEDTLS_PEM_WRITE_C=y +CONFIG_MBEDTLS_X509_CRL_PARSE_C=y +CONFIG_MBEDTLS_X509_CSR_PARSE_C=y +CONFIG_MBEDTLS_ECP_C=y +CONFIG_MBEDTLS_ECDH_C=y +CONFIG_MBEDTLS_ECDSA_C=y +CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED=y +CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED=y +CONFIG_MBEDTLS_ECP_NIST_OPTIM=y +CONFIG_MDNS_MAX_SERVICES=10 +CONFIG_MQTT_PROTOCOL_311=y +CONFIG_MQTT_TRANSPORT_SSL=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET=y +CONFIG_MQTT_TRANSPORT_WEBSOCKET_SECURE=y +# CONFIG_MQTT_USE_CUSTOM_CONFIG is not set +# CONFIG_MQTT_TASK_CORE_SELECTION_ENABLED is not set +# CONFIG_MQTT_CUSTOM_OUTBOX is not set +# CONFIG_OPENSSL_DEBUG is not set +CONFIG_OPENSSL_ASSERT_DO_NOTHING=y +# CONFIG_OPENSSL_ASSERT_EXIT is not set +CONFIG_ESP32_PTHREAD_TASK_PRIO_DEFAULT=5 +CONFIG_ESP32_PTHREAD_TASK_STACK_SIZE_DEFAULT=3072 +CONFIG_PTHREAD_STACK_MIN=768 +CONFIG_ESP32_DEFAULT_PTHREAD_CORE_NO_AFFINITY=y +# CONFIG_ESP32_DEFAULT_PTHREAD_CORE_0 is not set +# CONFIG_ESP32_DEFAULT_PTHREAD_CORE_1 is not set +CONFIG_ESP32_PTHREAD_TASK_CORE_DEFAULT=-1 +CONFIG_ESP32_PTHREAD_TASK_NAME_DEFAULT="pthread" +# CONFIG_SPI_FLASH_VERIFY_WRITE is not set +# CONFIG_SPI_FLASH_ENABLE_COUNTERS is not set +CONFIG_SPI_FLASH_ROM_DRIVER_PATCH=y +CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ABORTS=y +# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_FAILS is not set +# CONFIG_SPI_FLASH_WRITING_DANGEROUS_REGIONS_ALLOWED is not set +CONFIG_SPI_FLASH_YIELD_DURING_ERASE=y +CONFIG_SPI_FLASH_ERASE_YIELD_DURATION_MS=20 +CONFIG_SPI_FLASH_ERASE_YIELD_TICKS=1 +CONFIG_SPIFFS_MAX_PARTITIONS=3 +CONFIG_SPIFFS_CACHE=y +CONFIG_SPIFFS_CACHE_WR=y +# CONFIG_SPIFFS_CACHE_STATS is not set +CONFIG_SPIFFS_PAGE_CHECK=y +CONFIG_SPIFFS_GC_MAX_RUNS=10 +# CONFIG_SPIFFS_GC_STATS is not set +CONFIG_SPIFFS_PAGE_SIZE=256 +CONFIG_SPIFFS_OBJ_NAME_LEN=32 +CONFIG_SPIFFS_USE_MAGIC=y +CONFIG_SPIFFS_USE_MAGIC_LENGTH=y +CONFIG_SPIFFS_META_LENGTH=4 +CONFIG_SPIFFS_USE_MTIME=y +# CONFIG_SPIFFS_DBG is not set +# CONFIG_SPIFFS_API_DBG is not set +# CONFIG_SPIFFS_GC_DBG is not set +# CONFIG_SPIFFS_CACHE_DBG is not set +# CONFIG_SPIFFS_CHECK_DBG is not set +# CONFIG_SPIFFS_TEST_VISUALISATION is not set +CONFIG_IP_LOST_TIMER_INTERVAL=120 +CONFIG_TCPIP_LWIP=y +CONFIG_UNITY_ENABLE_FLOAT=y +CONFIG_UNITY_ENABLE_DOUBLE=y +# CONFIG_UNITY_ENABLE_COLOR is not set +CONFIG_UNITY_ENABLE_IDF_TEST_RUNNER=y +# CONFIG_UNITY_ENABLE_FIXTURE is not set +CONFIG_SUPPRESS_SELECT_DEBUG_OUTPUT=y +CONFIG_SUPPORT_TERMIOS=y +# CONFIG_WL_SECTOR_SIZE_512 is not set +CONFIG_WL_SECTOR_SIZE_4096=y +CONFIG_WL_SECTOR_SIZE=4096 +CONFIG_WIFI_PROV_SCAN_MAX_ENTRIES=16 diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_BlockStorage.c b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_BlockStorage.c new file mode 100644 index 00000000..6b185982 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_BlockStorage.c @@ -0,0 +1,19 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice ESP32Flash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + // add device AND request initialization + // required to setup flash partitions memory mapping + BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &ESP32Flash_BlockStorageInterface, &Device_BlockStorageConfig, true); +} diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_BlockStorage.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_BlockStorage.h new file mode 100644 index 00000000..aa50b1b7 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_common.c b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_common.c new file mode 100644 index 00000000..022af372 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_common.c @@ -0,0 +1,32 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include "target_common.h" + +#include + +HAL_SYSTEM_CONFIG HalSystemConfig = +{ + { true }, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, //ConvertCOM_DebugHandle(1), + 0, //ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + { RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size }, + { FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size } +}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; + + +void FixUpHalSystemConfig() +{ + HalSystemConfig.FLASH1.Size = g_rom_flashchip.chip_size; +} \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_common.h.in b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_common.h.in new file mode 100644 index 00000000..74d44824 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_common.h.in @@ -0,0 +1,41 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress (0x200000C0) +// RAM size +#define RAM1_MEMORY_Size (0x00020000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress (0x08000000) +// FLASH size +#define FLASH1_MEMORY_Size (0x00080000) + +///////////////////////////////////////////////////////////////////////////////////////// + +////////////////////////////////////////////// +#define TARGETNAMESTRING "ESP32_WROOM_32" +#define PLATFORMNAMESTRING "ESP32" +////////////////////////////////////////////// + +///////////////////////////////////// +// #define EVENTS_HEART_BEAT +///////////////////////////////////// + +#endif /* _TARGET_COMMON_H_ */ diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_lwip_sntp_opts.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_lwip_sntp_opts.h new file mode 100644 index 00000000..30007664 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_lwip_sntp_opts.h @@ -0,0 +1,18 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#define SNTP_SERVER_DEFAULT_ADDRESS "0.pool.ntp.org" + +// update delay (default 1 hour) +// (value in milliseconds) +#define SNTP_UPDATE_DELAY 3600000 + +// better have a startup delay because we can have DHCP enabled, value in milliseconds. +// As we automatically start SNTP when we get the IP address then only a small delay +#define SNTP_STARTUP_DELAY 1000 + +// retry timeout (15 minutes) +// value in milliseconds +#define SNTP_RETRY_TIMEOUT 900000 diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_nf_devices_onewire_config.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_nf_devices_onewire_config.cpp new file mode 100644 index 00000000..76238dbe --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_nf_devices_onewire_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_nf_devices_onewire_config.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_nf_devices_onewire_config.h new file mode 100644 index 00000000..33de9b0a --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_nf_devices_onewire_config.h @@ -0,0 +1,10 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +// use UART 2 for the 1-wire interface +#define NF_ONEWIRE_ESP32_UART_NUM UART_NUM_2 +// use GPIO port 16 for RX and 17 for TX +#define NF_ONEWIRE_ESP32_UART_RX_PIN UART_NUM_2_RXD_DIRECT_GPIO_NUM +#define NF_ONEWIRE_ESP32_UART_TX_PIN UART_NUM_2_TXD_DIRECT_GPIO_NUM diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_system_devices_dac_config.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_system_devices_dac_config.cpp new file mode 100644 index 00000000..d7b7376b --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_system_devices_dac_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_windows_devices_adc_config.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_windows_devices_adc_config.cpp new file mode 100644 index 00000000..76238dbe --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_windows_devices_adc_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_windows_devices_i2c_config.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_windows_devices_i2c_config.cpp new file mode 100644 index 00000000..76238dbe --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_windows_devices_i2c_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_windows_devices_serialcommunication_config.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_windows_devices_serialcommunication_config.cpp new file mode 100644 index 00000000..4845bf12 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_windows_devices_serialcommunication_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_windows_devices_spi_config.cpp b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_windows_devices_spi_config.cpp new file mode 100644 index 00000000..76238dbe --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_windows_devices_spi_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_windows_storage_config.h b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_windows_storage_config.h new file mode 100644 index 00000000..4fe92098 --- /dev/null +++ b/source/native/nf-interpreter/targets/FreeRTOS_ESP32/ESP32_WROOM_32/target_windows_storage_config.h @@ -0,0 +1,5 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/CMakeLists.txt b/source/native/nf-interpreter/targets/TI-SimpleLink/CMakeLists.txt new file mode 100644 index 00000000..504dbd22 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/CMakeLists.txt @@ -0,0 +1,233 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# set target base location +# this has to be set before the class library modules are pulled in +if(EXISTS ${PROJECT_SOURCE_DIR}/targets/TI-SimpleLink/${TI_BOARD}) + # set target base location + set(TARGET_BASE_LOCATION "${PROJECT_SOURCE_DIR}/targets/TI-SimpleLink/${TI_BOARD}") + message(STATUS "Support for target board '${TI_BOARD}' found") +else() + # board NOT found + # can't continue + message(FATAL_ERROR "\n\nSorry but support for ${TI_BOARD} target is not available...\n\nYou can wait for that to be added or you might want to contribute and start working on a PR for that.\n\n") +endif() + +# Define base path for the class libraries +set(BASE_PATH_FOR_CLASS_LIBRARIES_MODULES "${PROJECT_SOURCE_DIR}/targets/TI-SimpleLink/nanoCLR") + +# add target TI SimpleLink dirs +add_subdirectory(common) +add_subdirectory(Include) +add_subdirectory(nanoCLR) + +if("${TARGET_SERIES}" STREQUAL "CC32xx") + + # CC32xx series is using TI SimpleLink CC32xx SDK and FreeRTOS + + # check if TI_SL_CC32xx_SDK_SOURCE was specified or if it's empty (default is empty) + set(NO_TI_SL_CC32xx_SDK_SOURCE TRUE) + if(TI_SL_CC32xx_SDK_SOURCE) + if(NOT "${TI_SL_CC32xx_SDK_SOURCE}" STREQUAL "") + set(NO_TI_SL_CC32xx_SDK_SOURCE FALSE) + endif() + endif() + + if(NO_TI_SL_CC32xx_SDK_SOURCE) + # no TI SimpleLink CC32xx SDK source specified, download it from our repo + + # check for Git (needed here for advanced warning to user if it's not installed) + find_package(Git) + + # check if Git was found, if not report to user and abort + if(NOT GIT_EXECUTABLE) + message(FATAL_ERROR "error: could not find Git, make sure you have it installed.") + endif() + + message(STATUS "TI SimpleLink CC32xx SDK (latest available code from v3.10.00.04") + set(TI_SL_CC32xx_SDK_TAG "3.10.00.04") + + # need to setup a separate CMake project to download the code from the GitHub repository + # otherwise it won't be available before the actual build step + configure_file("${PROJECT_SOURCE_DIR}/CMake/SimpleLinkCC32xxSdk.CMakeLists.cmake.in" + "${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Download/CMakeLists.txt") + + # setup CMake project for TI SimpleLink CC32xx SDK download + execute_process(COMMAND ${CMAKE_COMMAND} -G "${CMAKE_GENERATOR}" . + RESULT_VARIABLE result + WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Download") + + # run build on TI SimpleLink CC32xx SDK download CMake project to perform the download + execute_process(COMMAND ${CMAKE_COMMAND} --build . + RESULT_VARIABLE result + WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Download") + + # add TI SimpleLink CC32xx SDK as external project + ExternalProject_Add( + SimpleLinkCC32xxSDK + PREFIX SimpleLinkCC32xxSdk + SOURCE_DIR ${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Source + GIT_REPOSITORY https://github.com/nanoframework/SimpleLink_CC32xx_SDK + GIT_TAG ${TI_SL_CC32xx_SDK_TAG} # target specified branch + GIT_SHALLOW 1 # download only the tip of the branch, not the complete history + TIMEOUT 10 + LOG_DOWNLOAD 1 + + # Disable all other steps + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND "" + ) + + # get source dir for TI SimpleLink CC32xx SDK CMake project + ExternalProject_Get_Property(SimpleLinkCC32xxSDK SOURCE_DIR) + + else() + # TI SimpleLink CC32xx SDK source was specified + + # sanity check is source path exists + if(EXISTS "${TI_SL_CC32xx_SDK_SOURCE}/") + message(STATUS "TI SimpleLink CC32xx SDK source from: ${TI_SL_CC32xx_SDK_SOURCE}") + + # check if we already have the sources, no need to copy again + if(NOT EXISTS "${CMAKE_BINARY_DIR}/TI_SL_CC32xx_SDK_SOURCE") + file(COPY "${TI_SL_CC32xx_SDK_SOURCE}/" DESTINATION "${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Source") + else() + message(STATUS "Using local cache of TI SimpleLink CC32xx SDK source from ${TI_SL_CC32xx_SDK_SOURCE}") + endif() + + set(SimpleLinkCC32xxSDK_INCLUDE_DIR ${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdkS_Source/ti/devices/cc32xx) + else() + message(FATAL_ERROR "Couldn't find TI SimpleLink CC32xx SDK source at ${TI_SL_CC32xx_SDK_SOURCE}/") + endif() + + # add TI SimpleLink CC32xx SDK as external project + ExternalProject_Add( + SimpleLinkCC32xxSDK + PREFIX SimpleLinkCC32xxSdk + SOURCE_DIR ${CMAKE_BINARY_DIR}/SimpleLinkCC32xxSdk_Source + + # Disable all other steps + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND "" + ) + + # get source dir for TI SimpleLink CC32xx SDK CMake project + ExternalProject_Get_Property(SimpleLinkCC32xxSDK SOURCE_DIR) + endif() + + # check if FREERTOS_SOURCE was specified or if it's empty (default is empty) + set(NO_FREERTOS_SOURCE TRUE) + if(FREERTOS_SOURCE) + if(NOT "${FREERTOS_SOURCE}" STREQUAL "") + set(NO_FREERTOS_SOURCE FALSE) + endif() + endif() + + if(NO_FREERTOS_SOURCE) + # no FreeRTOS source specified, download it from it's repo + + # check for Git (needed here for advanced warning to user if it's not installed) + find_package(Git) + + # check if Git was found, if not report to user and abort + if(NOT GIT_EXECUTABLE) + message(FATAL_ERROR "error: could not find Git, make sure you have it installed.") + endif() + + # FreeRTOS version + set(FREERTOS_VERSION_EMPTY TRUE) + + # check if build was requested with a specifc FreeRTOS version + if(DEFINED FREERTOS_VERSION) + if(NOT "${FREERTOS_VERSION}" STREQUAL "") + set(FREERTOS_VERSION_EMPTY FALSE) + endif() + endif() + + # FreeRTOS version + set(FREERTOS_VERSION_EMPTY TRUE) + + # check if build was requested with a specifc FreeRTOS version + if(FREERTOS_VERSION_EMPTY) + # no FreeRTOS version actualy specified, must be empty which is fine, we'll default to a known good version + set(FREERTOS_VERSION_TAG "v1.4.8") + else() + # set SVN tag + set(FREERTOS_VERSION_TAG "${FREERTOS_VERSION}") + endif() + + message(STATUS "RTOS is: FreeRTOS ${FREERTOS_VERSION} from GitHub repo") + + # need to setup a separate CMake project to download the code from the GitHub repository + # otherwise it won't be available before the actual build step + configure_file("${PROJECT_SOURCE_DIR}/CMake/FreeRTOS.CMakeLists.cmake.in" + "${CMAKE_BINARY_DIR}/FreeRTOS_Download/CMakeLists.txt") + + # setup CMake project for FreeRTOS download + execute_process(COMMAND ${CMAKE_COMMAND} -G "${CMAKE_GENERATOR}" . + RESULT_VARIABLE result + WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/FreeRTOS_Download") + + # run build on FreeRTOS download CMake project to perform the download + execute_process(COMMAND ${CMAKE_COMMAND} --build . + RESULT_VARIABLE result + WORKING_DIRECTORY "${CMAKE_BINARY_DIR}/FreeRTOS_Download") + + # add FreeRTOS as external project + ExternalProject_Add( + FreeRTOS + PREFIX FreeRTOS + SOURCE_DIR ${CMAKE_BINARY_DIR}/FreeRTOS_Source + GIT_REPOSITORY https://github.com/aws/amazon-freertos.git + GIT_TAG ${FREERTOS_VERSION_TAG} # target specified branch + GIT_SHALLOW 1 # download only the tip of the branch, not the complete history + TIMEOUT 10 + LOG_DOWNLOAD 1 + # Disable all other steps + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND "" + ) + + else() + # FreeRTOS source was specified + + # sanity check is source path exists + if(EXISTS "${FREERTOS_SOURCE}/") + message(STATUS "RTOS is: FreeRTOS (source from: ${FREERTOS_SOURCE})") + + # check if we already have the sources, no need to copy again + if(NOT EXISTS "${CMAKE_BINARY_DIR}/FreeRTOS_Source") + file(COPY "${FREERTOS_SOURCE}/" DESTINATION "${CMAKE_BINARY_DIR}/FreeRTOS_Source") + else() + message(STATUS "Using local cache of FreeRTOS source from ${FREERTOS_SOURCE}") + endif() + + set(FREERTOS_INCLUDE_DIR ${CMAKE_BINARY_DIR}/FreeRTOS_Source/include) + else() + message(FATAL_ERROR "Couldn't find FreeRTOS source at ${FREERTOS_SOURCE}/") + endif() + + # add FreeRTOS as external project + ExternalProject_Add( + FreeRTOS + PREFIX FreeRTOS + SOURCE_DIR ${CMAKE_BINARY_DIR}/FreeRTOS_Source + # Disable all other steps + INSTALL_COMMAND "" + CONFIGURE_COMMAND "" + BUILD_COMMAND "" + ) + + # get source dir for FreeRTOS CMake project + ExternalProject_Get_Property(FreeRTOS SOURCE_DIR) + + endif() + + add_subdirectory(${TI_BOARD}) + +endif() diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/Include/CLR_Startup_Thread.h b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/CLR_Startup_Thread.h new file mode 100644 index 00000000..3c394ef4 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/CLR_Startup_Thread.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _CLRSTARTUPTHREAD_ +#define _CLRSTARTUPTHREAD_ + +// declaration of RTOS thread +void CLRStartupThread(void const * argument); + +#endif //_CLRSTARTUPTHREAD_ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/Include/CMakeLists.txt b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/CMakeLists.txt new file mode 100644 index 00000000..38729eda --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/CMakeLists.txt @@ -0,0 +1,14 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append include directory for target TI SimpleLink +list(APPEND TARGET_TI_SimpleLink_COMMON_INCLUDE_DIRS "${CMAKE_CURRENT_SOURCE_DIR}") + +# make var global +set(TARGET_TI_SimpleLink_COMMON_INCLUDE_DIRS ${TARGET_TI_SimpleLink_COMMON_INCLUDE_DIRS} CACHE INTERNAL "make global") + +# add header with target platform definitions +configure_file("${CMAKE_SOURCE_DIR}/CMake/TI_SimpleLink_target_os.h.in" + "${CMAKE_BINARY_DIR}/targets/TI-SimpleLink/${TI_BOARD}/target_os.h" @ONLY) diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/Include/TargetPAL_BlockStorage.h b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/TargetPAL_BlockStorage.h new file mode 100644 index 00000000..1828f750 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/TargetPAL_BlockStorage.h @@ -0,0 +1,11 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_PAL_BLOCKSTORAGE_H_ +#define _TARGET_PAL_BLOCKSTORAGE_H_ 1 + +#include + +#endif // _TARGET_PAL_BLOCKSTORAGE_H_ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/Include/Target_BlockStorage_CC32xxFlashDriver.h b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/Target_BlockStorage_CC32xxFlashDriver.h new file mode 100644 index 00000000..7097fd80 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/Target_BlockStorage_CC32xxFlashDriver.h @@ -0,0 +1,28 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_CC32XXFLASH_DRIVER_H_ +#define _TARGET_CC32XXFLASH_DRIVER_H_ 1 + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +bool CC32xxFlashDriver_InitializeDevice(void*); +bool CC32xxFlashDriver_UninitializeDevice(void*); +DeviceBlockInfo* CC32xxFlashDriver_GetDeviceInfo(void*); +bool CC32xxFlashDriver_Read(void*, ByteAddress startAddress, unsigned int numBytes, unsigned char* buffer); +bool CC32xxFlashDriver_Write(void*, ByteAddress startAddress, unsigned int numBytes, unsigned char* buffer, bool readModifyWrite); +bool CC32xxFlashDriver_IsBlockErased(void*, ByteAddress blockAddress, unsigned int length); +bool CC32xxFlashDriver_EraseBlock(void*, ByteAddress address); +void CC32xxFlashDriver_SetPowerState(void*, unsigned int state); + +#ifdef __cplusplus +} +#endif + +#endif //_TARGET_CC32XXFLASH_DRIVER_H_ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/Include/Target_Windows_Storage.h b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/Target_Windows_Storage.h new file mode 100644 index 00000000..888c34fe --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/Target_Windows_Storage.h @@ -0,0 +1,9 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_WINDOWS_STORAGE_H_ +#define _TARGET_WINDOWS_STORAGE_H_ 1 + +#endif //_TARGET_WINDOWS_STORAGE_H_ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/Include/WireProtocol_ReceiverThread.h b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/WireProtocol_ReceiverThread.h new file mode 100644 index 00000000..2ab358a6 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/WireProtocol_ReceiverThread.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIREPROTOCOL_RECEIVERTHREAD_H_ +#define _WIREPROTOCOL_RECEIVERTHREAD_H_ + +// declaration of RTOS thread +void* ReceiverThread(void* argument); + +#endif //_WIREPROTOCOL_RECEIVERTHREAD_H_ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/Include/platform_target_capabilities.h b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/platform_target_capabilities.h new file mode 100644 index 00000000..b44fe07a --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/platform_target_capabilities.h @@ -0,0 +1,25 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _PLATFORM_TARGET_CAPABILITIES_H_ +#define _PLATFORM_TARGET_CAPABILITIES_H_ 1 + +////////////////////////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH nanoFramework.Tools.Debugger.TiCc32xx.TargetCapabilities (in managed code) !!! // +////////////////////////////////////////////////////////////////////////////////////////////////////////// + +#ifdef __cplusplus +extern "C" { +#endif + +// this platform doesn't have any declared capabilities + +// the targets of this platform don't have any declared capabilities + +#ifdef __cplusplus +} +#endif + +#endif //_PLATFORM_TARGET_CAPABILITIES_H_ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/Include/ssl_simplelink.h b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/ssl_simplelink.h new file mode 100644 index 00000000..063d426c --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/ssl_simplelink.h @@ -0,0 +1,18 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _SSL_SIMPLELINK_H_ +#define _SSL_SIMPLELINK_H_ 1 + +#include + +struct SlSSL_Context +{ + SlNetSockSecAttrib_t* SecurityAttributes; + uint32_t SocketFd; + bool IsServer; +}; + +#endif //_SSL_SIMPLELINK_H_ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/Include/targetHAL.h b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/targetHAL.h new file mode 100644 index 00000000..7d5746e5 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/targetHAL.h @@ -0,0 +1,103 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_HAL_H_ +#define _TARGET_HAL_H_ + +#include +#include +#include +#include + +#define GLOBAL_LOCK() vPortEnterCritical(); +#define GLOBAL_UNLOCK() vPortExitCritical(); + +// platform dependent delay +#define PLATFORM_DELAY(milliSecs) ClockP_usleep(milliSecs * 1000); + +// Definitions for Sockets/Network +#define GLOBAL_LOCK_SOCKETS(x) + +#define PLATFORM_DEPENDENT__SOCKETS_MAX_COUNT 16 + +#define LPCSTR const char* + +// these macros are to be used at entry/exit of native interrupt handlers +#define NATIVE_INTERRUPT_START SystemState_SetNoLock( SYSTEM_STATE_ISR ); \ + SystemState_SetNoLock( SYSTEM_STATE_NO_CONTINUATIONS ); +#define NATIVE_INTERRUPT_END SystemState_ClearNoLock( SYSTEM_STATE_NO_CONTINUATIONS ); \ + SystemState_ClearNoLock( SYSTEM_STATE_ISR ); + +#define TRUE true +#define FALSE false + +#if !defined(BUILD_RTM) + +#define HARD_BREAKPOINT() HARD_Breakpoint() + +// #if defined(_DEBUG) +// #define DEBUG_HARD_BREAKPOINT() HARD_Breakpoint() +// #else +// #define DEBUG_HARD_BREAKPOINT() +// #endif + +// #else + +// #define HARD_BREAKPOINT() +// #define DEBUG_HARD_BREAKPOINT() + +#endif // !defined(BUILD_RTM) + +// map TI SimpleLink calls to UART output to nanoFramework API +// this is valid only for debug buils +// release and RTM build don't call these +#if defined(BUILD_RTM) + +#define UART_PRINT(x,...) +#define INFO_PRINT(x,...) + +#else + +#if defined(DEBUG) || defined(_DEBUG) + +#define UART_PRINT DebuggerPort_WriteProxy +#define INFO_PRINT DebuggerPort_WriteProxy + +#else + +#define UART_PRINT(x,...) +#define INFO_PRINT(x,...) + +#endif // DEBUG + +#endif // defined(BUILD_RTM) + +#define NANOCLR_STOP() HARD_BREAKPOINT() + +///////////////////////////////////////////////////////////////////////////////////////////////////// +// DEBUGGER HELPER // +// The line below is meant to be used as helper on checking that the execution engine is running. // +// This can be inferred by checking if Events_WaitForEvents loop is running. // +// The implementation should is to be provided by each target at target_common.h.in // +//////////////////////////////////////////////////////////////////////////////////////////////////// +#if defined(BUILD_RTM) + #define EVENTS_HEART_BEAT +#else + #ifndef EVENTS_HEART_BEAT + #define EVENTS_HEART_BEAT __asm__ __volatile__ ("nop") + #endif // EVENTS_HEART_BEAT +#endif + +extern int HeapBegin; +extern int HeapEnd; + +extern uint32_t __nanoImage_start__; +extern uint32_t __nanoImage_end__; +extern uint32_t __nanoConfig_start__; +extern uint32_t __nanoConfig_end__; +extern uint32_t __deployment_start__; +extern uint32_t __deployment_end__; + +#endif //_TARGET_HAL_H_ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/Include/targetHAL_ConfigurationManager_CC32xx.h b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/targetHAL_ConfigurationManager_CC32xx.h new file mode 100644 index 00000000..4a931362 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/targetHAL_ConfigurationManager_CC32xx.h @@ -0,0 +1,19 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_CONFIGURATIONMANAGER_CC32XX_H_ +#define _TARGET_CONFIGURATIONMANAGER_CC32XX_H_ 1 + +// we'll store up to 4 network configuration blocks +#define NETWORK_CONFIG_MAX_COUNT (4) +// files with network configuration have this namming patter "network-config-N.bin" +#define NETWORK_CONFIG_FILE_NAME "nf/network-config0.bin" +// position of the index in the file name above (that's the 0) +#define NETWORK_CONFIG_FILE_INDEX_POSITION (17) + +// CA (Certificate Authority) root file name +#define CA_ROOT_CERT_FILE_NAME "ca-cert.pem" + +#endif //_TARGET_CONFIGURATIONMANAGER_CC32XX_H_ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/Include/targetHAL_Time.h b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/targetHAL_Time.h new file mode 100644 index 00000000..a456444d --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/targetHAL_Time.h @@ -0,0 +1,14 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_HAL_TIME_H_ +#define _TARGET_HAL_TIME_H_ 1 + +#include +#include + +#define HAL_Time_CurrentSysTicks xTaskGetTickCount + +#endif //_TARGET_HAL_TIME_H_ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/Include/targetPAL_Time.h b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/targetPAL_Time.h new file mode 100644 index 00000000..815979a7 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/targetPAL_Time.h @@ -0,0 +1,9 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_PAL_TIME_H_ +#define _TARGET_PAL_TIME_H_ 1 + +#endif //_TARGET_PAL_TIME_H_ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_LinkLocalTask.h b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_LinkLocalTask.h new file mode 100644 index 00000000..f799a3b1 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_LinkLocalTask.h @@ -0,0 +1,239 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _SIMPLELINK_CC32XX_LINKLOCAL_TASK_H_ +#define _SIMPLELINK_CC32XX_LINKLOCAL_TASK_H_ + +/* TI-DRIVERS Header files */ +#include + +/* POSIX Header files */ +#include +#include + +#define OOB_IS_NETAPP_MORE_DATA(flags) ((flags & \ + SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION) \ + == \ + SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION) +#define OOB_IS_NETAPP_ERROR(flags) ((flags & \ + SL_NETAPP_REQUEST_RESPONSE_FLAGS_ERROR) \ + == \ + SL_NETAPP_REQUEST_RESPONSE_FLAGS_ERROR) + +/* header fields definitions */ +#define WEB_SERVER_VERSION "HTTP Version:" +#define WEB_SERVER_REQUEST_URI "Request URI:" +#define WEB_SERVER_QUERY_STRING "Query String:" +#define WEB_SERVER_HEADER_CONTENT_TYPE "Content-Type: " +#define WEB_SERVER_HEADER_CONTENT_LEN "Content-Length: " +#define WEB_SERVER_HEADER_LOCATION "Location: " +#define WEB_SERVER_HEADER_SERVER "Server: " +#define WEB_SERVER_HEADER_USER_AGENT "User-Agent: " +#define WEB_SERVER_HEADER_COOKIE "Cookie:" +#define WEB_SERVER_HEADER_SET_COOKIE "Set-Cookie: " +#define WEB_SERVER_HEADER_UPGRADE "Upgrade: " +#define WEB_SERVER_HEADER_REFERER "Referer: " +#define WEB_SERVER_HEADER_ACCEPT "Accept: " +#define WEB_SERVER_HEADER_CONTENT_ENCODING "Content-Encoding: " +#define WEB_SERVER_HEADER_CONTENT_DISPOSITION "Content-Disposition: " +#define WEB_SERVER_HEADER_CONNECTION "Connection: " +#define WEB_SERVER_HEADER_ETAG "Etag: " +#define WEB_SERVER_HEADER_DATE "Date: " +#define WEB_SERVER_HEADER_HOST "Host: " +#define WEB_SERVER_HEADER_ACCEPT_ENCODING "Accept-Encoding: " +#define WEB_SERVER_HEADER_ACCEPT_LANGUAGE "Accept-Language: " +#define WEB_SERVER_HEADER_CONTENT_LANGUAGE "Content-Language: " + +/* Content types list */ +#define TEXT_HTML "text/html" +#define TEXT_CSS "text/css" +#define TEXT_XML "text/xml" +#define APPLICATION_JSON "application/json" +#define IMAGE_PNG "image/png" +#define IMAGE_GIF "image/gif" +#define TEXT_PLAIN "text/plain" +#define TEXT_CSV "text/csv" +#define APPLICATION_JAVASCRIPT "application/javascript" +#define IMAGE_JPEG "image/jpeg" +#define APPLICATION_PDF "application/pdf" +#define APPLICATION_ZIP "application/zip" +#define SHOCKWAVE_FLASH "application/x-shockwave-flash" +#define AUDIO_X_AAC "audio/x-aac" +#define IMAGE_X_ICON "image/x-icon" +#define TEXT_VCARD "text/vcard" +#define APPLICATION_OCTEC_STREAM "application/octet-stream" +#define VIDEO_AVI "video/avi" +#define VIDEO_MPEG "video/mpeg" +#define VIDEO_MP4 "video/mp4" +#define FORM_URLENCODED "application/x-www-form-urlencoded" + +/* MIME types list */ +#define TEXT_HTML_MIME ".html" +#define TEXT_CSS_MIME ".css" +#define TEXT_XML_MIME ".xml" +#define APPLICATION_JSON_MIME ".json" +#define IMAGE_PNG_MIME ".png" +#define IMAGE_GIF_MIME ".gif" +#define TEXT_PLAIN_MIME ".txt" +#define TEXT_CSV_MIME ".csv" +#define APPLICATION_JAVASCRIPT_MIME ".js" +#define IMAGE_JPEG_MIME ".jpg" +#define APPLICATION_PDF_MIME ".pdf" +#define APPLICATION_ZIP_MIME ".zip" +#define SHOCKWAVE_FLASH_MIME ".swf" +#define AUDIO_X_AAC_MIME ".aac" +#define IMAGE_X_ICON_MIME ".ico" +#define TEXT_VCARD_MIME ".vcf" +#define APPLICATION_OCTEC_STREAM_MIME ".bin" +#define VIDEO_AVI_MIME ".avi" +#define VIDEO_MPEG_MIME ".mpeg" +#define VIDEO_MP4_MIME ".mp4" +/* dummy - no such extension */ + +#define URL_ENCODED_MIME ".form" +typedef enum +{ +/* Content types list */ + HttpContentTypeList_TextHtml, + HttpContentTypeList_TextCSS, + HttpContentTypeList_TextXML, + HttpContentTypeList_ApplicationJson, + HttpContentTypeList_ImagePNG, + HttpContentTypeList_ImageGIF, + HttpContentTypeList_TextPlain, + HttpContentTypeList_TextCSV, + HttpContentTypeList_ApplicationJavascript, + HttpContentTypeList_ImageJPEG, + HttpContentTypeList_ApplicationPDF, + HttpContentTypeList_ApplicationZIP, + HttpContentTypeList_ShokewaveFlash, + HttpContentTypeList_AudioXAAC, + HttpContentTypeList_ImageXIcon, + HttpContentTypeList_TextVcard, + HttpContentTypeList_ApplicationOctecStream, + HttpContentTypeList_VideoAVI, + HttpContentTypeList_VideoMPEG, + HttpContentTypeList_VideoMP4, + HttpContentTypeList_UrlEncoded, +}HttpContentTypeList; + +#define CONTENT_LEN_TYPE 0xFF + +/* offsets of TLV structure of parameters parsed in NetApp request */ +#define ARGV_TYPE_OFFSET 0 +#define ARGV_LEN_OFFSET 2 +#define ARGV_VALUE_OFFSET 3 + +typedef struct _http_headerFieldType_t_ +{ + SlNetAppMetadataHTTPTypes_e headerType; + char * headerText; +}http_headerFieldType_t; + +typedef struct _http_contentTypeMapping_t_ +{ + HttpContentTypeList contentType; + char *contentTypeText; + char *mimeExt; +}http_contentTypeMapping_t; + +typedef struct _http_charValuesPair_t_ +{ + char *characteristic; + char *value[5]; +}http_charValuesPair_t; + +typedef struct _http_RequestObj_t_ +{ + uint8_t requestIdx; + uint8_t httpMethod; + char *service; + http_charValuesPair_t charValues[10]; + int32_t (*serviceCallback)(uint8_t, + uint8_t *, + uint8_t **, + SlNetAppRequest_t *); +}http_RequestObj_t; + +typedef enum +{ + LedIdx_RedLed, + LedIdx_OrangeLed, + LedIdx_GreenLed, + LedIdx_MaxLed, +}LedIdx; + +typedef enum +{ + LedValues_Off, + LedValues_On, + LedValues_Toggle, + LedValues_MaxLed, +}LedValues; + +typedef enum +{ + SensorIdx_XAxis, + SensorIdx_YAxis, + SensorIdx_ZAxis, + SensorIdx_FarnTemp, + SensorIdx_MaxSensor, +}SensorIdx; + +typedef enum +{ + DeviceIdx_Ssid, + DeviceIdx_IpAddress, + DeviceIdx_MacAddress, + DeviceIdx_AppID, + DeviceIdx_MaxDevice, +}DeviceIdx; + +typedef enum +{ + OtaIdx_Version, + OtaIdx_MaxOTA, +}OtaIdx; + +typedef struct LinkLocal_ControlBlock_t +{ + sem_t otaReportServerStartSignal; + sem_t otaReportServerStopSignal; + mqd_t reportServerMQueue; +}LinkLocal_CB; + +/**************************************************************************** + GLOBAL VARIABLES +****************************************************************************/ +extern LinkLocal_CB LinkLocal_ControlBlock; + +//**************************************************************************** +// FUNCTION PROTOTYPES +//**************************************************************************** + +//***************************************************************************** +// +//! \brief This function fetches the device type and prints it +//! +//! \param[in] None +//! +//! \return device type +//! +//**************************************************************************** +uint32_t getDeviceType(); + +//***************************************************************************** +// +//! \brief This task handles LinkLocal transactions with the client +//! +//! \param[in] None +//! +//! \return None +//! +//**************************************************************************** +void * linkLocalTask(void *pvParameters); + +#endif //_SIMPLELINK_CC32XX_LINKLOCAL_TASK_H_ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_ProvisioningTask.h b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_ProvisioningTask.h new file mode 100644 index 00000000..3b13f6ee --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_ProvisioningTask.h @@ -0,0 +1,145 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _SIMPLELINK_CC32XX_PROVISIONING_TASK_H_ +#define _SIMPLELINK_CC32XX_PROVISIONING_TASK_H_ + +#include + +/* POSIX Header files */ +#include +#include +#include + +#include +// #include +// #include + +/*! + * \brief Provisioning events + */ +typedef enum +{ + PrvnEvent_Triggered, + PrvnEvent_Started, + PrvnEvent_StartFailed, + PrvnEvent_ConfirmationSuccess, + PrvnEvent_ConfirmationFailed, + PrvnEvent_Stopped, + PrvnEvent_WaitForConn, + PrvnEvent_Timeout, + PrvnEvent_Error, + PrvnEvent_Max, +}PrvnEvent; + +/*! + * \brief Provisioning states + */ +typedef enum +{ + PrvnState_Init, + PrvnState_Idle, + PrvnState_WaitForConfirmation, + PrvnState_Completed, + PrvnState_Error, + PrvnState_Max +}PrvnState; + +typedef struct Provisioning_ControlBlock_t +{ + sem_t connectionAsyncEvent; + sem_t provisioningDoneSignal; + sem_t provisioningConnDoneToOtaServerSignal; +}Provisioning_CB; + + +/**************************************************************************** + GLOBAL VARIABLES +****************************************************************************/ +extern Provisioning_CB Provisioning_ControlBlock; + +//**************************************************************************** +// FUNCTION PROTOTYPES +//**************************************************************************** + +//***************************************************************************** +// +//! \brief This function signals the application events +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +_i16 SignalProvisioningEvent(PrvnEvent event); + +//***************************************************************************** +// +//! \brief This function gets the current provisioning state +//! +//! \param[in] None +//! +//! \return provisioning state +//! +//**************************************************************************** +PrvnState GetProvisioningState(); + +//***************************************************************************** +// +//! \brief The interrupt handler for the LED timer +//! +//! \param[in] None +//! +//! \return None +//! +//**************************************************************************** +void LedTimerIntHandler(sigval val); + +//***************************************************************************** +// +//! \brief This function starts the led toggling timer +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +int32_t StartLedEvtTimer(uint32_t timeout); + +//***************************************************************************** +// +//! \brief This function stops the led toggling timer +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +int32_t StopLedEvtTimer(void); + +//***************************************************************************** +// +//! \brief This function stops provisioning process +//! +//! \param[in] None +//! +//! \return SL_RET_CODE_PROVISIONING_IN_PROGRESS if provisioning was running, otherwise 0 +//! +//**************************************************************************** +int32_t provisioningStop(void); + +//***************************************************************************** +// +//! \brief This is the main provisioning task +//! +//! \param[in] None +//! +//! \return None +//! +//**************************************************************************** +void * provisioningTask(void *pvParameters); + +#endif //_SIMPLELINK_CC32XX_PROVISIONING_TASK_H_ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Sntp.h b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Sntp.h new file mode 100644 index 00000000..29ee5425 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Sntp.h @@ -0,0 +1,153 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_SNTP_H_ +#define _TARGET_SNTP_H_ 1 + +#include +#include +#include + +#include +#include + +// default SNTP server address +#ifndef SNTP_SERVER_DEFAULT_ADDRESS +#define SNTP_SERVER_DEFAULT_ADDRESS "0.pool.ntp.org" +#endif + +// Must wait at least 15 sec to retry NTP server (RFC 4330) +#ifndef SNTP_UPDATE_DELAY +#define SNTP_UPDATE_DELAY (15) +#endif + +// better have a startup delay because we can have DHCP enabled (default 30 seconds) +// value in seconds +#ifndef SNTP_STARTUP_DELAY +#define SNTP_STARTUP_DELAY (30) +#endif + +// retry timeout (15 minutes) +// value in seconds +#ifndef SNTP_RETRY_TIMEOUT +#define SNTP_RETRY_TIMEOUT (15 * 60) +#endif + +#define NTP_SERVERS 1 +#define NTP_SERVER_PORT 123 + +// Time to wait for reply from server (seconds) +#define NTP_REPLY_WAIT_TIME 5 + +#define TIME_BASEDIFF ((((uint32_t)70 * 365 + 17) * 24 * 3600)) +#define TIME_NTP_TO_LOCAL(t) ((t) - TIME_BASEDIFF) + +// SNTP Error Codes +// Failed to resolve Host address +#define SNTP_EGETHOSTBYNAMEFAIL (-100) + +// Input arguments are invalid +#define SNTP_EINVALIDARGS (-101) + +// Failed to create a socket +#define SNTP_ESOCKCREATEFAIL (-102) + +// The input socket address is not of AF_INET (IPv4) or AF_INET6 +// (IPv6) family type +#define SNTP_EINVALIDFAMILY (-103) + +// Failed to set receive timeout on socket +#define SNTP_ESOCKOPTFAIL (-104) + +// Failed to connect to the NTP server +#define SNTP_ECONNECTFAIL (-105) + +// Failed to send a time request to the NTP server +#define SNTP_ESENDFAIL (-106) + +// Failed to recieve the new time from the NTP server +#define SNTP_ERECVFAIL (-107) + +// NTP Server requests to reduce the update rate (RFC 5905 kiss code RATE) + +#define SNTP_ERATEBACKOFF (-108) + +// NTP Server invalid or server requests to end all communications (RFC +// 5905 kiss code DENY or RSTR) +#define SNTP_EFATALNORETRY (-109) + +// Server response with stratum == 0, with no kiss code +#define SNTP_EINVALIDRESP (-110) + +// KOD error code: rate exceeded, server requesting NTP client to back off +#define SNTP_KOD_RATE_STR "RATE" +#define SNTP_KOD_RATE_CODE 3 + +// KOD error code: access denied, server requests client to end all comm +#define SNTP_KOD_DENY_STR "DENY" +#define SNTP_KOD_DENY_CODE 2 + +// KOD error code: access denied, server requests client to end all comm +#define SNTP_KOD_RSTR_STR "RSTR" +#define SNTP_KOD_RSTR_CODE 1 + +// Size of KOD error codes +#define SNTP_KOD_ERROR_CODE_SIZE 4 + +// Use NTP version 4 +#define SNTP_VERSION 4 + +// Flag value for unsync'ed leap indicator field, signifying server error +#define SNTP_NOSYNC 3 + +// NTP mode defined in RFC 4330 +#define SNTP_MODE_CLIENT 3 + +// SNTP Header (as specified in RFC 4330) +typedef struct _SNTP_Header_t_ +{ + // + // 'flags' stores three values: + // + // - 2 bit Leap Indicator (LI) + // - 3 bit Version Number (VN) + // - 3 bit Mode. + + uint8_t flags; + uint8_t stratum; + uint8_t poll; + int8_t precision; + int32_t rootDelay; + uint32_t rootDispersion; + uint32_t referenceID; + + // NTP time stamps + uint32_t referenceTS[2]; + uint32_t originateTS[2]; + uint32_t receiveTS[2]; + uint32_t transmitTS[2]; +} SNTP_Header_t; + +struct sntp_server +{ + char* name; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +void sntp_init(void); +void sntp_stop(void); +bool sntp_enabled(void); +char* sntp_getservername(int index); +void sntp_setservername(int index, char* server); + +#ifdef __cplusplus +} +#endif + +#endif //_TARGET_SNTP_H_ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Threads.h b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Threads.h new file mode 100644 index 00000000..28f1f622 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/Include/targetSimpleLinkCC32xx_Threads.h @@ -0,0 +1,127 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _SIMPLELINK_CC32XX_THREADS_H_ +#define _SIMPLELINK_CC32XX_THREADS_H_ + +#include + +/* POSIX Header files */ +#include +#include +#include +#include + +#include +// #include +// #include + + +#define SL_STOP_TIMEOUT (200) +#define NF_TASK_PRIORITY (5) + + +#define ERR_PRINT(x) + +/* check the error code and handle it */ +#define ASSERT_ON_ERROR(error_code) \ + { \ + if(error_code < 0) \ + { \ + ERR_PRINT(error_code); \ + return error_code; \ + } \ + } + +#define SET_STATUS_BIT(status_variable, bit) status_variable |= (1 << (bit)) + +#define CLR_STATUS_BIT(status_variable, bit) status_variable &= ~(1 << (bit)) + +#define GET_STATUS_BIT(status_variable, bit) \ + (0 != (status_variable & (1 << (bit)))) + +#define APPS_WDT_START_KEY 0xAE42DB15 +#define HWREG(x) (*((volatile unsigned long *)(x))) + +#define IS_CONNECTED(status_variable) \ + GET_STATUS_BIT(status_variable, AppStatusBits_Connection) + +#define IS_IP_ACQUIRED(status_variable) \ + GET_STATUS_BIT(status_variable, AppStatusBits_IpAcquired) + +#define IS_IPV6L_ACQUIRED(status_variable) \ + GET_STATUS_BIT(status_variable, AppStatusBits_Ipv6lAcquired) + +#define IS_IPV6G_ACQUIRED(status_variable) \ + GET_STATUS_BIT(status_variable, AppStatusBits_Ipv6gAcquired) + +typedef struct +{ + _u8 Sd; + _u8 Type; +} nFSlSocketAsyncEvent_t; + +typedef enum +{ + /* If this bit is set: Network Processor is powered up */ + AppStatusBits_NwpInit = 0, + /* If this bit is set: the device is connected to + the AP or client is connected to device (AP) */ + AppStatusBits_Connection = 1, + /* If this bit is set: the device has leased IP to + any connected client */ + AppStatusBits_IpLeased = 2, + /* If this bit is set: the device has acquired an IP */ + AppStatusBits_IpAcquired = 3, + /* If this bit is set: the SmartConfiguration process is + started from SmartConfig app */ + AppStatusBits_SmartconfigStart = 4, + /* If this bit is set: the device (P2P mode) found any + p2p-device in scan */ + AppStatusBits_P2pDevFound = 5, + /* If this bit is set: the device (P2P mode) found any + p2p-negotiation request */ + AppStatusBits_P2pReqReceived = 6, + /* If this bit is set: the device(P2P mode) + connection to client(or reverse way) is failed */ + AppStatusBits_ConnectionFailed = 7, + /* If this bit is set: the device has completed the ping operation */ + AppStatusBits_PingDone = 8, + /* If this bit is set: the device has acquired an IPv6 address */ + AppStatusBits_Ipv6lAcquired = 9, + /* If this bit is set: the device has acquired an IPv6 address */ + AppStatusBits_Ipv6gAcquired = 10, + + AppStatusBits_AuthenticationFailed = 11, + AppStatusBits_ResetRequired = 12, +}AppStatusBits; + +// nF Control block for SimpleLink +typedef struct nanoFramework_ControlBlock_t +{ + // This bit-wise status variable shows the state of the NWP + uint32_t Status; + // This field keeps the device's role (STA, P2P or AP) + uint32_t Role; + + uint8_t configurationDone; + + mqd_t socketAsyncEvent; + + // uint32_t gatewayIP;/* Network Gateway IP address */ + + // uint8_t connectionSSID[SL_WLAN_SSID_MAX_LENGTH + 1];/* Connection SSID */ + + // uint8_t ssidLen;/* Connection SSID */ + + // uint8_t connectionBSSID[SL_WLAN_BSSID_LENGTH];/* Connection BSSID */ + +}nanoFramework_CB; + +extern nanoFramework_CB nF_ControlBlock; + + +#endif //_SIMPLELINK_CC32XX_THREADS_H_ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/Board.h b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/Board.h new file mode 100644 index 00000000..0866af85 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/Board.h @@ -0,0 +1,81 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef __BOARD_H +#define __BOARD_H + +#define Board_CC3220SF_LAUNCHXL + +#ifdef __cplusplus +extern "C" { +#endif + +#include "CC3220SF_LAUNCHXL.h" + +#define Board_init CC3220SF_LAUNCHXL_initGeneral +#define Board_initGeneral CC3220SF_LAUNCHXL_initGeneral + +#define Board_ADC0 CC3220SF_LAUNCHXL_ADC0 +#define Board_ADC1 CC3220SF_LAUNCHXL_ADC1 + +#define Board_CAPTURE0 CC3220SF_LAUNCHXL_CAPTURE0 +#define Board_CAPTURE1 CC3220SF_LAUNCHXL_CAPTURE1 + +#define Board_CRYPTO0 CC3220SF_LAUNCHXL_CRYPTO0 + +#define Board_GPIO_LED_ON CC3220SF_LAUNCHXL_GPIO_LED_ON +#define Board_GPIO_LED_OFF CC3220SF_LAUNCHXL_GPIO_LED_OFF +#define Board_GPIO_LED0 CC3220SF_LAUNCHXL_GPIO_LED_D10 +/* + * CC3220SF_LAUNCHXL_GPIO_LED_D8 and CC3220SF_LAUNCHXL_GPIO_LED_D9 are shared with the I2C + * and PWM peripherals. In order for those examples to work, these LEDs are + * taken out of gpioPinCOnfig[] + */ +#define Board_GPIO_LED1 CC3220SF_LAUNCHXL_GPIO_LED_D10 +#define Board_GPIO_LED2 CC3220SF_LAUNCHXL_GPIO_LED_D10 + +#define Board_GPIO_BUTTON0 CC3220SF_LAUNCHXL_GPIO_SW2 +#define Board_GPIO_BUTTON1 CC3220SF_LAUNCHXL_GPIO_SW3 + +#define Board_GPIO_TMP116_EN CC3220SF_LAUNCHXL_GPIO_TMP116_EN + +#define Board_I2C0 CC3220SF_LAUNCHXL_I2C0 +#define Board_I2C_TMP CC3220SF_LAUNCHXL_I2C0 + +#define Board_I2S0 CC3220SF_LAUNCHXL_I2S0 + +#define Board_PWM0 CC3220SF_LAUNCHXL_PWM6 +#define Board_PWM1 CC3220SF_LAUNCHXL_PWM7 + +#define Board_SD0 CC3220SF_LAUNCHXL_SD0 + +#define Board_SDFatFS0 CC3220SF_LAUNCHXL_SD0 + +/* CC3220SF_LAUNCHXL_SPI0 is reserved for the NWP */ +#define Board_SPI0 CC3220SF_LAUNCHXL_SPI1 +#define Board_SPI_MASTER CC3220SF_LAUNCHXL_SPI1 +#define Board_SPI_SLAVE CC3220SF_LAUNCHXL_SPI1 +#define Board_SPI_MASTER_READY CC3220SF_LAUNCHXL_SPI_MASTER_READY +#define Board_SPI_SLAVE_READY CC3220SF_LAUNCHXL_SPI_SLAVE_READY + +#define Board_TIMER0 CC3220SF_LAUNCHXL_TIMER0 +#define Board_TIMER1 CC3220SF_LAUNCHXL_TIMER1 +#define Board_TIMER2 CC3220SF_LAUNCHXL_TIMER2 + +#define Board_UART0 CC3220SF_LAUNCHXL_UART0 +#define Board_UART1 CC3220SF_LAUNCHXL_UART1 + +#define Board_WATCHDOG0 CC3220SF_LAUNCHXL_WATCHDOG0 + +/* Board specific I2C address */ +#define Board_TMP006_ADDR (0x41) +#define Board_I2C_TMP006_ADDR Board_TMP006_ADDR + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H */ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c new file mode 100644 index 00000000..8c9e9c29 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.c @@ -0,0 +1,831 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +// This file is responsible for setting up the board specific items for the +// CC3220SF_LAUNCHXL board + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "CC3220SF_LAUNCHXL.h" + +/* + * This define determines whether to use the UARTCC32XXDMA driver + * or the UARTCC32XX (no DMA) driver. Set to 1 to use the UARTCC32XXDMA + * driver. + */ +#ifndef TI_DRIVERS_UART_DMA +#define TI_DRIVERS_UART_DMA 0 +#endif + +/* + * =============================== ADC =============================== + */ +#include +#include + +ADCCC32XX_Object adcCC3220SObjects[CC3220SF_LAUNCHXL_ADCCOUNT]; + +const ADCCC32XX_HWAttrsV1 adcCC3220SHWAttrs[CC3220SF_LAUNCHXL_ADCCOUNT] = { + { + .adcPin = ADCCC32XX_PIN_59_CH_2 + }, + { + .adcPin = ADCCC32XX_PIN_60_CH_3 + } +}; + +const ADC_Config ADC_config[CC3220SF_LAUNCHXL_ADCCOUNT] = { + { + .fxnTablePtr = &ADCCC32XX_fxnTable, + .object = &adcCC3220SObjects[CC3220SF_LAUNCHXL_ADC0], + .hwAttrs = &adcCC3220SHWAttrs[CC3220SF_LAUNCHXL_ADC0] + }, + { + .fxnTablePtr = &ADCCC32XX_fxnTable, + .object = &adcCC3220SObjects[CC3220SF_LAUNCHXL_ADC1], + .hwAttrs = &adcCC3220SHWAttrs[CC3220SF_LAUNCHXL_ADC1] + } +}; + +const uint_least8_t ADC_count = CC3220SF_LAUNCHXL_ADCCOUNT; + +/* + * =============================== Capture =============================== + */ +#include +#include + +CaptureCC32XX_Object captureCC3220SFObjects[CC3220SF_LAUNCHXL_CAPTURECOUNT]; + +const CaptureCC32XX_HWAttrs captureCC3220SFHWAttrs[CC3220SF_LAUNCHXL_CAPTURECOUNT] = +{ + { + .capturePin = CaptureCC32XX_PIN_04, + .intPriority = ~0 + }, + { + .capturePin = CaptureCC32XX_PIN_05, + .intPriority = ~0 + }, +}; + +const Capture_Config Capture_config[CC3220SF_LAUNCHXL_CAPTURECOUNT] = { + { + .fxnTablePtr = &CaptureCC32XX_fxnTable, + .object = &captureCC3220SFObjects[CC3220SF_LAUNCHXL_CAPTURE0], + .hwAttrs = &captureCC3220SFHWAttrs[CC3220SF_LAUNCHXL_CAPTURE0] + }, + { + .fxnTablePtr = &CaptureCC32XX_fxnTable, + .object = &captureCC3220SFObjects[CC3220SF_LAUNCHXL_CAPTURE1], + .hwAttrs = &captureCC3220SFHWAttrs[CC3220SF_LAUNCHXL_CAPTURE1] + } +}; + +const uint_least8_t Capture_count = CC3220SF_LAUNCHXL_CAPTURECOUNT; + +/* + * =============================== Crypto =============================== + */ +#include + +CryptoCC32XX_Object cryptoCC3220SObjects[CC3220SF_LAUNCHXL_CRYPTOCOUNT]; + +const CryptoCC32XX_Config CryptoCC32XX_config[CC3220SF_LAUNCHXL_CRYPTOCOUNT] = { + { + .object = &cryptoCC3220SObjects[CC3220SF_LAUNCHXL_CRYPTO0] + } +}; + +const uint_least8_t CryptoCC32XX_count = CC3220SF_LAUNCHXL_CRYPTOCOUNT; + +/* + * =============================== DMA =============================== + */ +#include + +static tDMAControlTable dmaControlTable[64] __attribute__ ((aligned (1024))); + +/* + * ======== dmaErrorFxn ======== + * This is the handler for the uDMA error interrupt. + */ +static void dmaErrorFxn(uintptr_t arg) +{ + int status = MAP_uDMAErrorStatusGet(); + MAP_uDMAErrorStatusClear(); + + /* Suppress unused variable warning */ + (void)status; + + while (1); +} + +UDMACC32XX_Object udmaCC3220SObject; + +const UDMACC32XX_HWAttrs udmaCC3220SHWAttrs = { + .controlBaseAddr = (void *)dmaControlTable, + .dmaErrorFxn = (UDMACC32XX_ErrorFxn)dmaErrorFxn, + .intNum = INT_UDMAERR, + .intPriority = (~0) +}; + +const UDMACC32XX_Config UDMACC32XX_config = { + .object = &udmaCC3220SObject, + .hwAttrs = &udmaCC3220SHWAttrs +}; + +/* + * =============================== General =============================== + */ +/* + * ======== CC3220SF_LAUNCHXL_initGeneral ======== + */ +void CC3220SF_LAUNCHXL_initGeneral(void) +{ + PRCMCC3200MCUInit(); + Power_init(); + + // enable clock on the DTHE + MAP_PRCMPeripheralClkEnable(PRCM_DTHE, PRCM_RUN_MODE_CLK); + + // init CRC engine + MAP_CRCConfigSet(DTHE_BASE, (CRC_CFG_INIT_SEED | CRC_CFG_SIZE_8BIT | CRC_CFG_TYPE_P4C11DB7) ); + + // Mux Pin62 to mode 1 for outputing NWP logs + //MAP_PinTypeUART(PIN_62, PIN_MODE_1); +} + +/* + * =============================== GPIO =============================== + */ +#include +#include + +/* + * Array of Pin configurations + * NOTE: The order of the pin configurations must coincide with what was + * defined in CC3220SF_LAUNCHXL.h + * NOTE: Pins not used for interrupts should be placed at the end of the + * array. Callback entries can be omitted from callbacks array to + * reduce memory usage. + */ +GPIO_PinConfig gpioPinConfigs[] = { + /* input pins with callbacks */ + /* CC3220SF_LAUNCHXL_GPIO_SW2 */ + GPIOCC32XX_GPIO_13 | GPIO_CFG_INPUT | GPIO_CFG_IN_INT_RISING, + /* CC3220SF_LAUNCHXL_GPIO_SW3 */ + GPIOCC32XX_GPIO_22 | GPIO_CFG_INPUT | GPIO_CFG_IN_INT_RISING, + + /* CC3220SF_LAUNCHXL_SPI_MASTER_READY */ + GPIOCC32XX_GPIO_28 | GPIO_DO_NOT_CONFIG, + /* CC3220SF_LAUNCHXL_SPI_SLAVE_READY */ + GPIOCC32XX_GPIO_12 | GPIO_DO_NOT_CONFIG, + + /* output pins */ + /* CC3220SF_LAUNCHXL_GPIO_LED_D10 */ + GPIOCC32XX_GPIO_09 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, + + /* + * CC3220SF_LAUNCHXL_GPIO_LED_D8 and CC3220SF_LAUNCHXL_GPIO_LED_D9 are shared with the + * I2C and PWM peripherals. In order for those examples to work, these + * LEDs are taken out of gpioPinConfig[] + */ + /* CC3220SF_LAUNCHXL_GPIO_LED_D9 */ + GPIOCC32XX_GPIO_10 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, + /* CC3220SF_LAUNCHXL_GPIO_LED_D8 */ + GPIOCC32XX_GPIO_11 | GPIO_CFG_OUT_STD | GPIO_CFG_OUT_STR_HIGH | GPIO_CFG_OUT_LOW, + + GPIOCC32XX_GPIO_30 | GPIO_DO_NOT_CONFIG, /* TMP116 EN */ + + /* Sharp Display - GPIO configurations will be done in the Display files */ + GPIOCC32XX_GPIO_12 | GPIO_DO_NOT_CONFIG, /* SPI chip select */ + GPIOCC32XX_GPIO_06 | GPIO_DO_NOT_CONFIG, /* LCD power control */ + GPIOCC32XX_GPIO_03 | GPIO_DO_NOT_CONFIG, /*LCD enable */ +}; + +/* + * Array of callback function pointers + * NOTE: The order of the pin configurations must coincide with what was + * defined in CC3220SF_LAUNCHXL.h + * NOTE: Pins not used for interrupts can be omitted from callbacks array to + * reduce memory usage (if placed at end of gpioPinConfigs array). + */ +GPIO_CallbackFxn gpioCallbackFunctions[] = { + NULL, /* CC3220SF_LAUNCHXL_GPIO_SW2 */ + NULL, /* CC3220SF_LAUNCHXL_GPIO_SW3 */ + NULL, /* CC3220SF_LAUNCHXL_SPI_MASTER_READY */ + NULL /* CC3220SF_LAUNCHXL_SPI_SLAVE_READY */ +}; + +/* The device-specific GPIO_config structure */ +const GPIOCC32XX_Config GPIOCC32XX_config = { + .pinConfigs = (GPIO_PinConfig *)gpioPinConfigs, + .callbacks = (GPIO_CallbackFxn *)gpioCallbackFunctions, + .numberOfPinConfigs = sizeof(gpioPinConfigs)/sizeof(GPIO_PinConfig), + .numberOfCallbacks = sizeof(gpioCallbackFunctions)/sizeof(GPIO_CallbackFxn), + .intPriority = (~0) +}; + +/* + * ============================= Display ============================= + */ +#include +#include +#include +#define MAXPRINTLEN 1024 + +/* This value can be changed to 96 for use with the 430BOOST-SHARP96 BoosterPack. */ +#define BOARD_DISPLAY_SHARP_SIZE 128 + +DisplayUart_Object displayUartObject; +DisplaySharp_Object displaySharpObject; + +static char displayBuf[MAXPRINTLEN]; +static uint_least8_t sharpDisplayBuf[BOARD_DISPLAY_SHARP_SIZE * BOARD_DISPLAY_SHARP_SIZE / 8]; + +const DisplayUart_HWAttrs displayUartHWAttrs = { + .uartIdx = 0, + .baudRate = 921600, + .mutexTimeout = (unsigned int)(-1), + .strBuf = displayBuf, + .strBufLen = MAXPRINTLEN +}; + +const DisplaySharp_HWAttrsV1 displaySharpHWattrs = { + .spiIndex = CC3220SF_LAUNCHXL_SPI1, + .csPin = CC3220SF_LAUNCHXL_LCD_CS, + .powerPin = CC3220SF_LAUNCHXL_LCD_POWER, + .enablePin = CC3220SF_LAUNCHXL_LCD_ENABLE, + .pixelWidth = BOARD_DISPLAY_SHARP_SIZE, + .pixelHeight = BOARD_DISPLAY_SHARP_SIZE, + .displayBuf = sharpDisplayBuf, +}; + +#ifndef BOARD_DISPLAY_USE_UART +#define BOARD_DISPLAY_USE_UART 1 +#endif +#ifndef BOARD_DISPLAY_USE_UART_ANSI +#define BOARD_DISPLAY_USE_UART_ANSI 0 +#endif +#ifndef BOARD_DISPLAY_USE_LCD +#define BOARD_DISPLAY_USE_LCD 0 +#endif + +const Display_Config Display_config[] = { + { +# if (BOARD_DISPLAY_USE_UART_ANSI) + .fxnTablePtr = &DisplayUartAnsi_fxnTable, +# else /* Default to minimal UART with no cursor placement */ + .fxnTablePtr = &DisplayUartMin_fxnTable, +# endif + .object = &displayUartObject, + .hwAttrs = &displayUartHWAttrs + }, +#if (BOARD_DISPLAY_USE_LCD) + { + .fxnTablePtr = &DisplaySharp_fxnTable, + .object = &displaySharpObject, + .hwAttrs = &displaySharpHWattrs + }, +#endif +}; + +const uint_least8_t Display_count = sizeof(Display_config) / sizeof(Display_Config); + + + +/* + * =============================== I2C =============================== + */ +#include +#include + +I2CCC32XX_Object i2cCC3220SObjects[CC3220SF_LAUNCHXL_I2CCOUNT]; + +const I2CCC32XX_HWAttrsV1 i2cCC3220SHWAttrs[CC3220SF_LAUNCHXL_I2CCOUNT] = { + { + .baseAddr = I2CA0_BASE, + .intNum = INT_I2CA0, + .intPriority = (~0), + .clkPin = I2CCC32XX_PIN_01_I2C_SCL, + .dataPin = I2CCC32XX_PIN_02_I2C_SDA + } +}; + +const I2C_Config I2C_config[CC3220SF_LAUNCHXL_I2CCOUNT] = { + { + .fxnTablePtr = &I2CCC32XX_fxnTable, + .object = &i2cCC3220SObjects[CC3220SF_LAUNCHXL_I2C0], + .hwAttrs = &i2cCC3220SHWAttrs[CC3220SF_LAUNCHXL_I2C0] + } +}; + +const uint_least8_t I2C_count = CC3220SF_LAUNCHXL_I2CCOUNT; + +/* + * =============================== I2S =============================== + */ +#include +#include + +I2SCC32XX_Object i2sCC3220SObjects[CC3220S_LAUNCHXL_I2SCOUNT]; + +const I2SCC32XX_HWAttrs i2sCC3220SHWAttrs[CC3220S_LAUNCHXL_I2SCOUNT] = { + { + .pinSD1 = I2SCC32XX_PIN_50_SD1, + .pinSD0 = I2SCC32XX_PIN_64_SD0, + .pinSCK = I2SCC32XX_PIN_53_SCK, + .pinSCKX = I2SCC32XX_PIN_UNUSED, + .pinWS = I2SCC32XX_PIN_63_WS, + .rxChannelIndex = UDMA_CH4_I2S_RX, + .txChannelIndex = UDMA_CH5_I2S_TX, + .intPriority = 0x40, + } +}; + +const I2S_Config I2S_config[CC3220S_LAUNCHXL_I2SCOUNT] = { + { + .object = &i2sCC3220SObjects[CC3220S_LAUNCHXL_I2S0], + .hwAttrs = &i2sCC3220SHWAttrs[CC3220S_LAUNCHXL_I2S0] + } +}; + +const uint_least8_t I2S_count = CC3220S_LAUNCHXL_I2SCOUNT; + +/* + * =============================== Power =============================== + */ +/* + * This table defines the parking state to be set for each parkable pin + * during LPDS. (Device pins must be parked during LPDS to achieve maximum + * power savings.) If the pin should be left unparked, specify the state + * PowerCC32XX_DONT_PARK. For example, for a UART TX pin, the device + * will automatically park the pin in a high state during transition to LPDS, + * so the Power Manager does not need to explictly park the pin. So the + * corresponding entries in this table should indicate PowerCC32XX_DONT_PARK. + */ +PowerCC32XX_ParkInfo parkInfo[] = { +/* PIN PARK STATE PIN ALIAS (FUNCTION) + ----------------- ------------------------------ -------------------- */ + {PowerCC32XX_PIN01, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO10 */ + {PowerCC32XX_PIN02, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO11 */ + {PowerCC32XX_PIN03, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO12 */ + {PowerCC32XX_PIN04, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO13 */ + {PowerCC32XX_PIN05, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO14 */ + {PowerCC32XX_PIN06, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO15 */ + {PowerCC32XX_PIN07, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO16 */ + {PowerCC32XX_PIN08, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO17 */ + {PowerCC32XX_PIN13, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* FLASH_SPI_DIN */ + {PowerCC32XX_PIN15, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO22 */ + {PowerCC32XX_PIN16, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TDI (JTAG DEBUG) */ + {PowerCC32XX_PIN17, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TDO (JTAG DEBUG) */ + {PowerCC32XX_PIN19, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TCK (JTAG DEBUG) */ + {PowerCC32XX_PIN20, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* TMS (JTAG DEBUG) */ + {PowerCC32XX_PIN18, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO28 */ + {PowerCC32XX_PIN21, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* SOP2 */ + {PowerCC32XX_PIN29, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* ANTSEL1 */ + {PowerCC32XX_PIN30, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* ANTSEL2 */ + {PowerCC32XX_PIN45, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* DCDC_ANA2_SW_P */ + {PowerCC32XX_PIN50, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO0 */ + {PowerCC32XX_PIN52, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* RTC_XTAL_N */ + {PowerCC32XX_PIN53, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO30 */ + {PowerCC32XX_PIN55, PowerCC32XX_WEAK_PULL_UP_STD}, /* GPIO1 (XDS_UART_RX) */ + {PowerCC32XX_PIN57, PowerCC32XX_WEAK_PULL_UP_STD}, /* GPIO2 (XDS_UART_TX) */ + {PowerCC32XX_PIN58, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO3 */ + {PowerCC32XX_PIN59, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO4 */ + {PowerCC32XX_PIN60, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO5 */ + {PowerCC32XX_PIN61, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO6 */ + {PowerCC32XX_PIN62, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO7 */ + {PowerCC32XX_PIN63, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO8 */ + {PowerCC32XX_PIN64, PowerCC32XX_WEAK_PULL_DOWN_STD}, /* GPIO9 */ +}; + +/* + * This structure defines the configuration for the Power Manager. + * + * In this configuration the Power policy is disabled by default (because + * enablePolicy is set to false). The Power policy can be enabled dynamically + * at runtime by calling Power_enablePolicy(), or at build time, by changing + * enablePolicy to true in this structure. + */ +const PowerCC32XX_ConfigV1 PowerCC32XX_config = { + .policyInitFxn = &PowerCC32XX_initPolicy, + .policyFxn = &PowerCC32XX_sleepPolicy, + .enterLPDSHookFxn = NULL, + .resumeLPDSHookFxn = NULL, + .enablePolicy = false, + .enableGPIOWakeupLPDS = true, + .enableGPIOWakeupShutdown = true, + .enableNetworkWakeupLPDS = true, + .wakeupGPIOSourceLPDS = PRCM_LPDS_GPIO13, + .wakeupGPIOTypeLPDS = PRCM_LPDS_FALL_EDGE, + .wakeupGPIOFxnLPDS = NULL, + .wakeupGPIOFxnLPDSArg = 0, + .wakeupGPIOSourceShutdown = PRCM_HIB_GPIO13, + .wakeupGPIOTypeShutdown = PRCM_HIB_RISE_EDGE, + .ramRetentionMaskLPDS = PRCM_SRAM_COL_1 | PRCM_SRAM_COL_2 | + PRCM_SRAM_COL_3 | PRCM_SRAM_COL_4, + .keepDebugActiveDuringLPDS = false, + .ioRetentionShutdown = PRCM_IO_RET_GRP_1, + .pinParkDefs = parkInfo, + .numPins = sizeof(parkInfo) / sizeof(PowerCC32XX_ParkInfo) +}; + +/* + * =============================== PWM =============================== + */ +#include +#include + +PWMTimerCC32XX_Object pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWMCOUNT]; + +const PWMTimerCC32XX_HWAttrsV2 pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWMCOUNT] = { + { /* CC3220SF_LAUNCHXL_PWM6 */ + .pwmPin = PWMTimerCC32XX_PIN_01 + }, + { /* CC3220SF_LAUNCHXL_PWM7 */ + .pwmPin = PWMTimerCC32XX_PIN_02 + } +}; + +const PWM_Config PWM_config[CC3220SF_LAUNCHXL_PWMCOUNT] = { + { + .fxnTablePtr = &PWMTimerCC32XX_fxnTable, + .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM6], + .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM6] + }, + { + .fxnTablePtr = &PWMTimerCC32XX_fxnTable, + .object = &pwmTimerCC3220SObjects[CC3220SF_LAUNCHXL_PWM7], + .hwAttrs = &pwmTimerCC3220SHWAttrs[CC3220SF_LAUNCHXL_PWM7] + } +}; + +const uint_least8_t PWM_count = CC3220SF_LAUNCHXL_PWMCOUNT; + +/* + * =============================== SDFatFS =============================== + */ +#include +#include + +/* + * Note: The SDFatFS driver provides interface functions to enable FatFs + * but relies on the SD driver to communicate with SD cards. Opening a + * SDFatFs driver instance will internally try to open a SD driver instance + * reusing the same index number (opening SDFatFs driver at index 0 will try to + * open SD driver at index 0). This requires that all SDFatFs driver instances + * have an accompanying SD driver instance defined with the same index. It is + * acceptable to have more SD driver instances than SDFatFs driver instances + * but the opposite is not supported & the SDFatFs will fail to open. + */ +SDFatFS_Object sdfatfsObjects[CC3220SF_LAUNCHXL_SDFatFSCOUNT]; + +const SDFatFS_Config SDFatFS_config[CC3220SF_LAUNCHXL_SDFatFSCOUNT] = { + { + .object = &sdfatfsObjects[CC3220SF_LAUNCHXL_SDFatFS0] + } +}; + +const uint_least8_t SDFatFS_count = CC3220SF_LAUNCHXL_SDFatFSCOUNT; + +/* + * =============================== SD =============================== + */ +#include +#include + +SDHostCC32XX_Object sdhostCC3220SObjects[CC3220SF_LAUNCHXL_SDCOUNT]; + +/* SDHost configuration structure, describing which pins are to be used */ +const SDHostCC32XX_HWAttrsV1 sdhostCC3220SHWattrs[CC3220SF_LAUNCHXL_SDCOUNT] = { + { + .clkRate = 8000000, + .intPriority = ~0, + .baseAddr = SDHOST_BASE, + .rxChIdx = UDMA_CH23_SDHOST_RX, + .txChIdx = UDMA_CH24_SDHOST_TX, + .dataPin = SDHostCC32XX_PIN_06_SDCARD_DATA, + .cmdPin = SDHostCC32XX_PIN_08_SDCARD_CMD, + .clkPin = SDHostCC32XX_PIN_07_SDCARD_CLK + } +}; + +const SD_Config SD_config[CC3220SF_LAUNCHXL_SDCOUNT] = { + { + .fxnTablePtr = &sdHostCC32XX_fxnTable, + .object = &sdhostCC3220SObjects[CC3220SF_LAUNCHXL_SD0], + .hwAttrs = &sdhostCC3220SHWattrs[CC3220SF_LAUNCHXL_SD0] + }, +}; + +const uint_least8_t SD_count = CC3220SF_LAUNCHXL_SDCOUNT; + +/* + * =============================== SPI =============================== + */ +#include +#include + +SPICC32XXDMA_Object spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPICOUNT]; + +uint32_t spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPICOUNT]; + +const SPICC32XXDMA_HWAttrsV1 spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPICOUNT] = { + /* index 0 is reserved for LSPI that links to the NWP */ + { + .baseAddr = LSPI_BASE, + .intNum = INT_LSPI, + .intPriority = (~0), + .spiPRCM = PRCM_LSPI, + .csControl = SPI_SW_CTRL_CS, + .csPolarity = SPI_CS_ACTIVEHIGH, + .pinMode = SPI_4PIN_MODE, + .turboMode = SPI_TURBO_OFF, + .scratchBufPtr = &spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPI0], + .defaultTxBufValue = 0, + .rxChannelIndex = UDMA_CH12_LSPI_RX, + .txChannelIndex = UDMA_CH13_LSPI_TX, + .minDmaTransferSize = 100, + .mosiPin = SPICC32XXDMA_PIN_NO_CONFIG, + .misoPin = SPICC32XXDMA_PIN_NO_CONFIG, + .clkPin = SPICC32XXDMA_PIN_NO_CONFIG, + .csPin = SPICC32XXDMA_PIN_NO_CONFIG + }, + { + .baseAddr = GSPI_BASE, + .intNum = INT_GSPI, + .intPriority = (~0), + .spiPRCM = PRCM_GSPI, + .csControl = SPI_HW_CTRL_CS, + .csPolarity = SPI_CS_ACTIVELOW, + .pinMode = SPI_4PIN_MODE, + .turboMode = SPI_TURBO_OFF, + .scratchBufPtr = &spiCC3220SDMAscratchBuf[CC3220SF_LAUNCHXL_SPI1], + .defaultTxBufValue = 0, + .rxChannelIndex = UDMA_CH6_GSPI_RX, + .txChannelIndex = UDMA_CH7_GSPI_TX, + .minDmaTransferSize = 10, + .mosiPin = SPICC32XXDMA_PIN_07_MOSI, + .misoPin = SPICC32XXDMA_PIN_06_MISO, + .clkPin = SPICC32XXDMA_PIN_05_CLK, + .csPin = SPICC32XXDMA_PIN_08_CS + } +}; + +const SPI_Config SPI_config[CC3220SF_LAUNCHXL_SPICOUNT] = { + { + .fxnTablePtr = &SPICC32XXDMA_fxnTable, + .object = &spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPI0], + .hwAttrs = &spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPI0] + }, + { + .fxnTablePtr = &SPICC32XXDMA_fxnTable, + .object = &spiCC3220SDMAObjects[CC3220SF_LAUNCHXL_SPI1], + .hwAttrs = &spiCC3220SDMAHWAttrs[CC3220SF_LAUNCHXL_SPI1] + } +}; + +const uint_least8_t SPI_count = CC3220SF_LAUNCHXL_SPICOUNT; + +/* + * =============================== Timer =============================== + */ +#include +#include + +TimerCC32XX_Object timerCC3220SFObjects[CC3220SF_LAUNCHXL_TIMERCOUNT]; + +const TimerCC32XX_HWAttrs timerCC3220SFHWAttrs[CC3220SF_LAUNCHXL_TIMERCOUNT] = { + { + .baseAddress = TIMERA0_BASE, + .subTimer = TimerCC32XX_timer32, + .intNum = INT_TIMERA0A, + .intPriority = ~0 + }, + { + .baseAddress = TIMERA1_BASE, + .subTimer = TimerCC32XX_timer16A, + .intNum = INT_TIMERA1A, + .intPriority = ~0 + }, + { + .baseAddress = TIMERA1_BASE, + .subTimer = TimerCC32XX_timer16B, + .intNum = INT_TIMERA1B, + .intPriority = ~0 + }, +}; + +const Timer_Config Timer_config[CC3220SF_LAUNCHXL_TIMERCOUNT] = { + { + .fxnTablePtr = &TimerCC32XX_fxnTable, + .object = &timerCC3220SFObjects[CC3220SF_LAUNCHXL_TIMER0], + .hwAttrs = &timerCC3220SFHWAttrs[CC3220SF_LAUNCHXL_TIMER0] + }, + { + .fxnTablePtr = &TimerCC32XX_fxnTable, + .object = &timerCC3220SFObjects[CC3220SF_LAUNCHXL_TIMER1], + .hwAttrs = &timerCC3220SFHWAttrs[CC3220SF_LAUNCHXL_TIMER1] + }, + { + .fxnTablePtr = &TimerCC32XX_fxnTable, + .object = &timerCC3220SFObjects[CC3220SF_LAUNCHXL_TIMER2], + .hwAttrs = &timerCC3220SFHWAttrs[CC3220SF_LAUNCHXL_TIMER2] + }, +}; + +const uint_least8_t Timer_count = CC3220SF_LAUNCHXL_TIMERCOUNT; + +/* + * =============================== UART =============================== + */ +#include +#if TI_DRIVERS_UART_DMA +#include + +UARTCC32XXDMA_Object uartCC3220SDmaObjects[CC3220SF_LAUNCHXL_UARTCOUNT]; + +/* UART configuration structure */ +const UARTCC32XXDMA_HWAttrsV1 uartCC3220SDmaHWAttrs[CC3220SF_LAUNCHXL_UARTCOUNT] = { + { + .baseAddr = UARTA0_BASE, + .intNum = INT_UARTA0, + .intPriority = (~0), + .flowControl = UARTCC32XXDMA_FLOWCTRL_NONE, + .rxChannelIndex = UDMA_CH8_UARTA0_RX, + .txChannelIndex = UDMA_CH9_UARTA0_TX, + .rxPin = UARTCC32XXDMA_PIN_57_UART0_RX, + .txPin = UARTCC32XXDMA_PIN_55_UART0_TX, + .ctsPin = UARTCC32XXDMA_PIN_UNASSIGNED, + .rtsPin = UARTCC32XXDMA_PIN_UNASSIGNED, + .errorFxn = NULL + }, + { + .baseAddr = UARTA1_BASE, + .intNum = INT_UARTA1, + .intPriority = (~0), + .flowControl = UARTCC32XXDMA_FLOWCTRL_NONE, + .rxChannelIndex = UDMA_CH10_UARTA1_RX, + .txChannelIndex = UDMA_CH11_UARTA1_TX, + .rxPin = UARTCC32XXDMA_PIN_08_UART1_RX, + .txPin = UARTCC32XXDMA_PIN_07_UART1_TX, + .ctsPin = UARTCC32XXDMA_PIN_UNASSIGNED, + .rtsPin = UARTCC32XXDMA_PIN_UNASSIGNED, + .errorFxn = NULL + } +}; + +const UART_Config UART_config[CC3220SF_LAUNCHXL_UARTCOUNT] = { + { + .fxnTablePtr = &UARTCC32XXDMA_fxnTable, + .object = &uartCC3220SDmaObjects[CC3220SF_LAUNCHXL_UART0], + .hwAttrs = &uartCC3220SDmaHWAttrs[CC3220SF_LAUNCHXL_UART0] + }, + { + .fxnTablePtr = &UARTCC32XXDMA_fxnTable, + .object = &uartCC3220SDmaObjects[CC3220SF_LAUNCHXL_UART1], + .hwAttrs = &uartCC3220SDmaHWAttrs[CC3220SF_LAUNCHXL_UART1] + } +}; + +#else +#include + +UARTCC32XX_Object uartCC3220SObjects[CC3220SF_LAUNCHXL_UARTCOUNT]; +unsigned char uartCC3220SRingBuffer[CC3220SF_LAUNCHXL_UARTCOUNT][32]; + +/* UART configuration structure */ +const UARTCC32XX_HWAttrsV1 uartCC3220SHWAttrs[CC3220SF_LAUNCHXL_UARTCOUNT] = { + { + .baseAddr = UARTA0_BASE, + .intNum = INT_UARTA0, + .intPriority = (~0), + .flowControl = UARTCC32XX_FLOWCTRL_NONE, + .ringBufPtr = uartCC3220SRingBuffer[CC3220SF_LAUNCHXL_UART0], + .ringBufSize = sizeof(uartCC3220SRingBuffer[CC3220SF_LAUNCHXL_UART0]), + .rxPin = UARTCC32XX_PIN_57_UART0_RX, + .txPin = UARTCC32XX_PIN_55_UART0_TX, + .ctsPin = UARTCC32XX_PIN_UNASSIGNED, + .rtsPin = UARTCC32XX_PIN_UNASSIGNED, + .errorFxn = NULL + }, + { + .baseAddr = UARTA1_BASE, + .intNum = INT_UARTA1, + .intPriority = (~0), + .flowControl = UARTCC32XX_FLOWCTRL_NONE, + .ringBufPtr = uartCC3220SRingBuffer[CC3220SF_LAUNCHXL_UART1], + .ringBufSize = sizeof(uartCC3220SRingBuffer[CC3220SF_LAUNCHXL_UART1]), + .rxPin = UARTCC32XX_PIN_08_UART1_RX, + .txPin = UARTCC32XX_PIN_07_UART1_TX, + .ctsPin = UARTCC32XX_PIN_UNASSIGNED, + .rtsPin = UARTCC32XX_PIN_UNASSIGNED, + .errorFxn = NULL + } +}; + +const UART_Config UART_config[CC3220SF_LAUNCHXL_UARTCOUNT] = { + { + .fxnTablePtr = &UARTCC32XX_fxnTable, + .object = &uartCC3220SObjects[CC3220SF_LAUNCHXL_UART0], + .hwAttrs = &uartCC3220SHWAttrs[CC3220SF_LAUNCHXL_UART0] + }, + { + .fxnTablePtr = &UARTCC32XX_fxnTable, + .object = &uartCC3220SObjects[CC3220SF_LAUNCHXL_UART1], + .hwAttrs = &uartCC3220SHWAttrs[CC3220SF_LAUNCHXL_UART1] + } +}; +#endif /* TI_DRIVERS_UART_DMA */ + +const uint_least8_t UART_count = CC3220SF_LAUNCHXL_UARTCOUNT; + +/* + * =============================== Watchdog =============================== + */ +#include +#include + +WatchdogCC32XX_Object watchdogCC3220SObjects[CC3220SF_LAUNCHXL_WATCHDOGCOUNT]; + +const WatchdogCC32XX_HWAttrs watchdogCC3220SHWAttrs[CC3220SF_LAUNCHXL_WATCHDOGCOUNT] = { + { + .baseAddr = WDT_BASE, + .intNum = INT_WDT, + .intPriority = (~0), + .reloadValue = 80000000 /* 1 second period at default CPU clock freq */ + } +}; + +const Watchdog_Config Watchdog_config[CC3220SF_LAUNCHXL_WATCHDOGCOUNT] = { + { + .fxnTablePtr = &WatchdogCC32XX_fxnTable, + .object = &watchdogCC3220SObjects[CC3220SF_LAUNCHXL_WATCHDOG0], + .hwAttrs = &watchdogCC3220SHWAttrs[CC3220SF_LAUNCHXL_WATCHDOG0] + } +}; + +const uint_least8_t Watchdog_count = CC3220SF_LAUNCHXL_WATCHDOGCOUNT; + +/* + * ======== Board_debugHeader ======== + * This structure prevents the CC32XXSF bootloader from overwriting the + * internal FLASH; this allows us to flash a program that will not be + * overwritten by the bootloader with the encrypted program saved in + * "secure/serial flash". + * + * This structure must be placed at the beginning of internal FLASH (so + * the bootloader is able to recognize that it should not overwrite + * internal FLASH). + */ +#if defined (__SF_DEBUG__) || defined(__SF_NODEBUG__) +#if defined(__TI_COMPILER_VERSION__) +#pragma DATA_SECTION(Board_debugHeader, ".dbghdr") +#pragma RETAIN(Board_debugHeader) +#elif defined(__IAR_SYSTEMS_ICC__) +#pragma location=".dbghdr" +#elif defined(__GNUC__) +__attribute__ ((section (".dbghdr"))) +#endif +#if defined(__SF_DEBUG__) +const uint32_t Board_debugHeader[] = { + 0x5AA5A55A, + 0x000FF800, + 0xEFA3247D +}; +#elif defined (__SF_NODEBUG__) +const uint32_t Board_debugHeader[] = { + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF +}; +#endif +#endif diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h new file mode 100644 index 00000000..c107c3e6 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CC3220SF_LAUNCHXL.h @@ -0,0 +1,186 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +// CC3220 Board Specific APIs + +#ifndef __CC3220SF_LAUNCHXL_H +#define __CC3220SF_LAUNCHXL_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define CC3220SF_LAUNCHXL_GPIO_LED_OFF (0) +#define CC3220SF_LAUNCHXL_GPIO_LED_ON (1) + +/*! + * @def CC3220SF_LAUNCHXL_ADCName + * @brief Enum of ADC names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_ADCName { + CC3220SF_LAUNCHXL_ADC0 = 0, + CC3220SF_LAUNCHXL_ADC1, + + CC3220SF_LAUNCHXL_ADCCOUNT +} CC3220SF_LAUNCHXL_ADCName; + +/*! + * @def CC3220SF_LAUNCHXL_CaptureName + * @brief Enum of Capture names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_CaptureName { + CC3220SF_LAUNCHXL_CAPTURE0 = 0, + CC3220SF_LAUNCHXL_CAPTURE1, + + CC3220SF_LAUNCHXL_CAPTURECOUNT +} CC3220SF_LAUNCHXL_CaptureName; + +/*! + * @def CC3220SF_LAUNCHXL_CryptoName + * @brief Enum of Crypto names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_CryptoName { + CC3220SF_LAUNCHXL_CRYPTO0 = 0, + + CC3220SF_LAUNCHXL_CRYPTOCOUNT +} CC3220SF_LAUNCHXL_CryptoName; + +/*! + * @def CC3220SF_LAUNCHXL_GPIOName + * @brief Enum of GPIO names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_GPIOName { + CC3220SF_LAUNCHXL_GPIO_SW2 = 0, + CC3220SF_LAUNCHXL_GPIO_SW3, + CC3220SF_LAUNCHXL_SPI_MASTER_READY, + CC3220SF_LAUNCHXL_SPI_SLAVE_READY, + CC3220SF_LAUNCHXL_GPIO_LED_D10, + + /* + * CC3220SF_LAUNCHXL_GPIO_LED_D8 and CC3220SF_LAUNCHXL_GPIO_LED_D9 are shared with the + * I2C and PWM peripherals. In order for those examples to work, these + * LEDs are taken out of gpioPinCOnfig[] + */ + CC3220SF_LAUNCHXL_GPIO_LED_D9, + CC3220SF_LAUNCHXL_GPIO_LED_D8, + + CC3220SF_LAUNCHXL_GPIO_TMP116_EN, + + /* Sharp LCD Pins */ + CC3220SF_LAUNCHXL_LCD_CS, + CC3220SF_LAUNCHXL_LCD_POWER, + CC3220SF_LAUNCHXL_LCD_ENABLE, + + CC3220SF_LAUNCHXL_GPIOCOUNT +} CC3220SF_LAUNCHXL_GPIOName; + +/*! + * @def CC3220SF_LAUNCHXL_I2CName + * @brief Enum of I2C names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_I2CName { + CC3220SF_LAUNCHXL_I2C0 = 0, + + CC3220SF_LAUNCHXL_I2CCOUNT +} CC3220SF_LAUNCHXL_I2CName; + +/*! + * @def CC3220S_LAUNCHXL_I2SName + * @brief Enum of I2S names on the CC3220S_LAUNCHXL dev board + */ +typedef enum CC3220S_LAUNCHXL_I2SName { + CC3220S_LAUNCHXL_I2S0 = 0, + + CC3220S_LAUNCHXL_I2SCOUNT +} CC3220S_LAUNCHXL_I2SName; + +/*! + * @def CC3220SF_LAUNCHXL_PWMName + * @brief Enum of PWM names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_PWMName { + CC3220SF_LAUNCHXL_PWM6 = 0, + CC3220SF_LAUNCHXL_PWM7, + + CC3220SF_LAUNCHXL_PWMCOUNT +} CC3220SF_LAUNCHXL_PWMName; + +/*! + * @def CC3220SF_LAUNCHXL_SDFatFSName + * @brief Enum of SDFatFS names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_SDFatFSName { + CC3220SF_LAUNCHXL_SDFatFS0 = 0, + + CC3220SF_LAUNCHXL_SDFatFSCOUNT +} CC3220SF_LAUNCHXL_SDFatFSName; + +/*! + * @def CC3220SF_LAUNCHXL_SDName + * @brief Enum of SD names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_SDName { + CC3220SF_LAUNCHXL_SD0 = 0, + + CC3220SF_LAUNCHXL_SDCOUNT +} CC3220SF_LAUNCHXL_SDName; + +/*! + * @def CC3220SF_LAUNCHXL_SPIName + * @brief Enum of SPI names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_SPIName { + CC3220SF_LAUNCHXL_SPI0 = 0, + CC3220SF_LAUNCHXL_SPI1, + + CC3220SF_LAUNCHXL_SPICOUNT +} CC3220SF_LAUNCHXL_SPIName; + +/*! + * @def CC3220SF_LAUNCHXL_TimerName + * @brief Enum of Timer names on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_TimerName { + CC3220SF_LAUNCHXL_TIMER0 = 0, + CC3220SF_LAUNCHXL_TIMER1, + CC3220SF_LAUNCHXL_TIMER2, + + CC3220SF_LAUNCHXL_TIMERCOUNT +} CC3220SF_LAUNCHXL_TimerName; + +/*! + * @def CC3220SF_LAUNCHXL_UARTName + * @brief Enum of UARTs on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_UARTName { + CC3220SF_LAUNCHXL_UART0 = 0, + CC3220SF_LAUNCHXL_UART1, + + CC3220SF_LAUNCHXL_UARTCOUNT +} CC3220SF_LAUNCHXL_UARTName; + +/*! + * @def CC3220SF_LAUNCHXL_WatchdogName + * @brief Enum of Watchdogs on the CC3220SF_LAUNCHXL dev board + */ +typedef enum CC3220SF_LAUNCHXL_WatchdogName { + CC3220SF_LAUNCHXL_WATCHDOG0 = 0, + + CC3220SF_LAUNCHXL_WATCHDOGCOUNT +} CC3220SF_LAUNCHXL_WatchdogName; + +/*! + * @brief Initialize the general board specific settings + * + * This function initializes the general board specific settings. + */ +extern void CC3220SF_LAUNCHXL_initGeneral(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __CC3220SF_LAUNCHXL_H */ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CMakeLists.txt b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CMakeLists.txt new file mode 100644 index 00000000..fd38d737 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/CMakeLists.txt @@ -0,0 +1,131 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +cmake_minimum_required(VERSION 3.0) +ENABLE_LANGUAGE(ASM) + +# add header files with common OS definitions and board definitions specific for each image +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/target_board.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/nanoCLR/target_board.h" @ONLY) +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_common.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/target_common.h" @ONLY) + +set(NANOCLR_PROJECT_NAME "nanoCLR") + +find_package(BuildUtils REQUIRED) +find_package(TI_SimpleLink REQUIRED) +find_package(WireProtocol REQUIRED) + +# packages for nanoFramework libraries +####################################### +# mandatory +find_package(NF_CoreCLR REQUIRED) + +####################################### +# optional + +# nF feature: debugger +if(NF_FEATURE_DEBUGGER) + find_package(NF_Debugger REQUIRED) + find_package(NF_Diagnostics REQUIRED) +endif() + +####################################### + +add_subdirectory("common") +add_subdirectory("nanoCLR") + +####################### +# nanoCLR executable + +add_executable( + # executables for project, project sources + ${NANOCLR_PROJECT_NAME}.elf + + "${CMAKE_CURRENT_SOURCE_DIR}/target_common.c" + "${CMAKE_CURRENT_SOURCE_DIR}/CC3220SF_LAUNCHXL.c" + + ${COMMON_PROJECT_SOURCES} + ${NANOCLR_PROJECT_SOURCES} + + ${TARGET_TI_SimpleLink_COMMON_SOURCES} + + ${TARGET_TI_SimpleLink_NANOCLR_SOURCES} + + ${TI_SimpleLink_SOURCES} + + ${WireProtocol_SOURCES} + + # sources for nanoFramework libraries + ${NF_CoreCLR_SOURCES} + ${NF_Debugger_SOURCES} + ${NF_Diagnostics_SOURCES} + + # sources for nanoFramework APIs + ${TARGET_NANO_APIS_SOURCES} +) + +# add dependency from TI SimpleLink CC32xx SDK and FreeRTOS (this is required to make sure that those repos are downloaded before the build starts) +add_dependencies(${NANOCLR_PROJECT_NAME}.elf FreeRTOS) +add_dependencies(${NANOCLR_PROJECT_NAME}.elf SimpleLinkCC32xxSDK) + +# include common directories +include_directories( + ${CMAKE_CURRENT_BINARY_DIR} + "${CMAKE_CURRENT_SOURCE_DIR}" + "${CMAKE_CURRENT_SOURCE_DIR}/common" + "${PROJECT_SOURCE_DIR}/src/CLR/Core" + "${PROJECT_SOURCE_DIR}/src/CLR/Include" + "${PROJECT_SOURCE_DIR}/src/HAL/Include" + "${PROJECT_SOURCE_DIR}/src/PAL/Include" + + "${WireProtocol_INCLUDE_DIRS}" + "${TI_SimpleLink_INCLUDE_DIRS}" + + "${TARGET_TI_SimpleLink_COMMON_INCLUDE_DIRS}" +) + +# include directories for nanoCLR +target_include_directories(${NANOCLR_PROJECT_NAME}.elf PUBLIC + ${CMAKE_CURRENT_BINARY_DIR}/nanoCLR + "${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR" + + "${TARGET_TI_SimpleLink_NANOCLR_INCLUDE_DIRS}" + + # directories for nanoFramework libraries + ${NF_CoreCLR_INCLUDE_DIRS} + ${NF_Debugger_INCLUDE_DIRS} + ${NF_Diagnostics_INCLUDE_DIRS} + + # includes for nanoFramework APIs + ${TARGET_NANO_APIS_INCLUDES} +) + +# set compiler options +nf_set_compiler_options(${NANOCLR_PROJECT_NAME}.elf) + +# set compiler definitions +############################################### +# add -DUSE_CC3220_ROM_DRV_API to use ROM API # +############################################### +nf_set_compiler_definitions(${NANOCLR_PROJECT_NAME}.elf -DDeviceFamily_CC3220) + +# set linker files +if(CMAKE_BUILD_TYPE MATCHES Debug OR CMAKE_BUILD_TYPE MATCHES RelWithDebInfo) + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/CC3220SF_CLR-DEBUG.ld) +else() + nf_set_linker_file(${NANOCLR_PROJECT_NAME}.elf ${CMAKE_CURRENT_SOURCE_DIR}/nanoCLR/CC3220SF_CLR.ld) +endif() + +# set linker options +nf_set_linker_options(${NANOCLR_PROJECT_NAME}.elf) + +# add other linker flags +########################################################### +# the size of CRT heap stacks is defined here +set_property(TARGET ${NANOCLR_PROJECT_NAME}.elf APPEND_STRING PROPERTY LINK_FLAGS ",--defsym=__crt_heap_size__=0x0") + +# generate output files +nf_generate_build_output_files(${NANOCLR_PROJECT_NAME}.elf) diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/FreeRTOSConfig.h b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/FreeRTOSConfig.h new file mode 100644 index 00000000..6e7fc379 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/FreeRTOSConfig.h @@ -0,0 +1,207 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +/****************************************************************************** + See http://www.freertos.org/a00110.html for an explanation of the + definitions contained in this file. +******************************************************************************/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * http://www.freertos.org/a00110.html + *----------------------------------------------------------*/ + +/* Constants related to the behaviour or the scheduler. */ +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) +#define configUSE_PREEMPTION 1 +#define configUSE_TIME_SLICING 0 +#define configMAX_PRIORITIES ( 10UL ) +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_16_BIT_TICKS 0 /* Only for 8 and 16-bit hardware. */ + +/* Constants used to specify if only static allocation is to be supported (in +which case a heap_n.c file is not required), only dynamic allocation is to be +supported, or if both static and dynamic allocation are supported. */ +#define configSUPPORT_STATIC_ALLOCATION 0 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 + +/* Constants that describe the hardware and memory usage. */ +#define configCPU_CLOCK_HZ ( ( unsigned long ) 80000000 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 256 ) +#define configMAX_TASK_NAME_LEN ( 12 ) + +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 0x8000 ) ) + +/* Default stack size for TI-POSIX threads (in words) */ +#define configPOSIX_STACK_SIZE ( ( unsigned short ) 512 ) + +/* Constants that build features in or out. */ +#define configUSE_MUTEXES 1 +#define configUSE_TICKLESS_IDLE 1 +#define configUSE_APPLICATION_TASK_TAG 1 /* Need by POSIX/pthread */ +#define configUSE_CO_ROUTINES 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TASK_NOTIFICATIONS 1 + +/* Constants that define which hook (callback) functions should be used. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 1 + +/* Constants provided for debugging and optimisation assistance. */ +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } +#define configQUEUE_REGISTRY_SIZE 0 + +/* + * Minimum number of full tick periods of idle time required to run Power + * sleep policy function. + */ +#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 5 + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (5) +#define configTIMER_QUEUE_LENGTH (20) +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE * 2) + +#define configENABLE_BACKWARD_COMPATIBILITY 0 + +#if defined(__TI_COMPILER_VERSION__) +#include +#define traceTASK_DELETE( pxTCB ) PTLS_taskDeleteHook( pxTCB ) +#elif defined(__IAR_SYSTEMS_ICC__) +#ifndef __IAR_SYSTEMS_ASM__ +#include +#define traceTASK_DELETE( pxTCB ) Mtx_taskDeleteHook( pxTCB ) +#endif +#endif + +/* + * Enable thread local storage + * + * Assign TLS array index ownership here to avoid collisions. + * TLS storage is needed to implement thread-safe errno with + * TI and IAR compilers. With GNU compiler, we enable newlib. + */ +#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) + +#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 1 + +#if defined(__TI_COMPILER_VERSION__) +#define PTLS_TLS_INDEX 0 /* ti.posix.freertos.PTLS */ +#elif defined(__IAR_SYSTEMS_ICC__) +#define MTX_TLS_INDEX 0 /* ti.posix.freertos.Mtx */ +#endif + +#elif defined(__GNUC__) +/* note: system locks required by newlib are not implemented */ +#define configUSE_NEWLIB_REENTRANT 1 +#endif + +/* + * Set the following definitions to 1 to include the API function, or zero + * to exclude the API function. NOTE: Setting an INCLUDE_ parameter to 0 is only + * necessary if the linker does not automatically remove functions that are not + * referenced anyway. + */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTaskResumeFromISR 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xSemaphoreGetMutexHolder 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* Cortex-M3/4 interrupt priority configuration follows...................... */ + +/* Use the system definition, if there is one. */ +#ifdef __NVIC_PRIO_BITS + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #define configPRIO_BITS 3 /* 8 priority levels */ +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x07 + +/* + * The highest interrupt priority that can be used by any interrupt service + * routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL + * INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER + * PRIORITY THAN THIS! (higher priorities are lower numeric values. + */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 1 + +/* + * Priority 7 (shifted 5 since only the top 3 bits are implemented). + * Priority 7 is the lowest priority. + */ +#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* + * Priority 1 (shifted 5 since only the top 3 bits are implemented). + * Priority 1 is the second highest priority. + * Priority 0 is the highest priority. + * !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! + * See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. + */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS)) + +/* The trace facility is turned on to make some functions available for use in +CLI commands. */ +#define configUSE_TRACE_FACILITY 1 + +/* Constants related to the generation of run time stats. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() +#define portGET_RUN_TIME_COUNTER_VALUE() 0 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/README.md b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/README.md new file mode 100644 index 00000000..79a98a08 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/README.md @@ -0,0 +1,74 @@ +# TI CC3220SF LAUNCHXL + +The CC3220SF LAUNCHXL board contains a TI CC3220SF device. + +## Jumper Settings + +* Set __RX__ and __TX__ to provide UART communications via the onboard USB debugger. + +## Board Resources + +The following table lists the Board names of the resources and their corresponding pins. + + |Board Resource|Pins| + |--------------|:---| + |`Board_ADC0`|P59 (Connect to analog signal)| + |`Board_ADC1`|P60 (Connect to analog signal)| + |`Board_CAPTURE0`|P04 | + |`Board_CAPTURE1`|P05 | + |`Board_GPIO_LED0`|P64 (__LED EN__ must be jumpered)| + |`Board_GPIO_LED1`|P01 (__LED EN__ must be jumpered)| + |`Board_GPIO_LED2`|P02 (__LED EN__ must be jumpered)| + |`Board_GPIO_BUTTON0`|P04 (`SW2`)| + |`Board_GPIO_BUTTON1`|P15 (`SW3`)| + |`Board_I2C0`|P01 - `SCL`, P02 - `SDA`| + |`Board_I2C_TMP`|P01 - `SCL`, P02 - `SDA` (__SCL__ and __SDA__ must be jumpered)| + |`Board_I2S0`|P50 - `XR1`, P53 - `CLK`, P62 - `CLKX`, P63 - `FSX`, P64 - `XR0`| + |`Board_PWM0`|P01 (__LED EN__ must be jumpered)| + |`Board_PWM1`|P02 (__LED EN__ must be jumpered)| + |`Board_SD0`|P06 - `DATA`, P07 - `CLK`, P08 - `CMD`| + |`Board_SDFatFS0`|P06 - `DATA`, P07 - `CLK`, P08 - `CMD`| + |`Board_SPI0`|P05 - `CLK`, P06 - `MISO`, P07 - `MOSI`, P08 - `CS`| + |`Board_SPI_MASTER`|P05 - `CLK`, P06 - `MISO`, P07 - `MOSI`, P08 - `CS`| + |`Board_SPI_SLAVE`|P05 - `CLK`, P06 - `MISO`, P07 - `MOSI`, P08 - `CS`| + |`Board_SPI_MASTER_READY`|P18| + |`Board_SPI_SLAVE_READY`|P03| + |`Board_UART0`|P57 - `RX`, P55 - `TX` (UART provided through emulation, __RX__ and __TX__ must be jumpered)| + |`Board_UART1`|P08 - `RX`, P07 - `TX`| + +## ADC Examples Pin Connections + +>__Important:__ The inputs to the ADC are required to be well within 1.4 VDC to avoid clipping, which will cause distortion. +The ADC inputs can be damaged if an input voltage higher than 1.8 VDC is applied to these pin. The 1.8 VDC hard limit must be considered from both the SW and HW points of view. +Always add a resistor divider/buffer to bring down the measurement signal voltage to within the ADC limits. See the [CC32xx ADC Appnote](http://processors.wiki.ti.com/index.php/CC32xx_ADC_Appnote) +for more details. + +The __CC3220SF LAUNCHXL__ has a protective circuit to allow an input of 3.3 VDC. +The `5V` should NOT be used for this may damage the ADC inputs. For testing, the following jumpers must be present: +`J5` = `OPAMP EN`, `J10` = `GND`, `J13` = `BRD`. + +>__Note:__ There are duplicate pins P59 and P60 on the board. Choose the ones connected to the BoosterPack headers (the pins not connected to the BoosterPack headers have an asterisk next to them). + +## Reset Behavior + +By default, the application is not retained after a power reset. To enable +retention of the application for debug purposes, the application should +add the following pre-defined symbol: `__SF_DEBUG__`. This will place a header, +`Board_debugHeader`, into flash. This header is defined in the Board.c file. + +>__Note:__ The user should ensure the `Board_debugHeader` is erased if +retention of the application is no longer desired. The Board.c file +will erase the `Board_debugHeader` if `__SF_NODEBUG__` is defined. + +## Floating point + +The current build is set to add support for single-precision floating point. +Meaning that `System.Math` API supports only the `float` overloads. The `double` ones will throw a `NotImplementedException`. + +## nanoBooter + +Because this CPU uses a proprietary boot mechanism that copies the application from the SPI flash memory to the Cortex-M application core, it does not use nanoBooter. + +## Flashing nanoCLR + +Follow the instructions [here](http://docs.nanoframework.net/articles/ti-cc32xx/flash-nanoclr.html) on how to flash nanoCLR image in the board. diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/CMakeLists.txt b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/CMakeLists.txt new file mode 100644 index 00000000..42be0d5f --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) 2017 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append common source files +list(APPEND COMMON_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Device_BlockStorage$<$,$>:-DEBUG>.c") + +# make var global +set(COMMON_PROJECT_SOURCES ${COMMON_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c new file mode 100644 index 00000000..b3904523 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage-DEBUG.c @@ -0,0 +1,67 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2k blocks +const BlockRange BlockRange1[] = +{ + // the 1st block is reserved for the flash header + // so we don't take it into account for the map + { BlockRange_BLOCKTYPE_CODE , 0 , 125 }, // 0x01000800 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT , 126, 510 }, // 0x0103F000 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x01000800, // start address for block region + 511, // total number of blocks in this region + 0x800, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + } +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage.c b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage.c new file mode 100644 index 00000000..acdd399c --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/common/Device_BlockStorage.c @@ -0,0 +1,67 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// 2k blocks +const BlockRange BlockRange1[] = +{ + // the 1st block is reserved for the flash header + // so we don't take it into account for the map + { BlockRange_BLOCKTYPE_CODE , 0 , 93 }, // 0x01000800 nanoCLR + { BlockRange_BLOCKTYPE_DEPLOYMENT , 94, 510 }, // 0x0102F800 deployment +}; + +const BlockRegionInfo BlockRegions[] = +{ + { + (0), // no attributes for this region + 0x01000800, // start address for block region + 511, // total number of blocks in this region + 0x800, // total number of bytes per block + ARRAYSIZE_CONST_EXPR(BlockRange1), + BlockRange1, + } +}; + +const DeviceBlockInfo Device_BlockInfo = +{ + (MediaAttribute_SupportsXIP), + 2, // UINT32 BytesPerSector + ARRAYSIZE_CONST_EXPR(BlockRegions), // UINT32 NumRegions; + (BlockRegionInfo*)BlockRegions, // const BlockRegionInfo* pRegions; +}; + +MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig = +{ + { // BLOCK_CONFIG + { + 0, // GPIO_PIN Pin; + false, // BOOL ActiveState; + }, + + (DeviceBlockInfo*)&Device_BlockInfo, // BlockDeviceinfo + }, + + { // CPU_MEMORY_CONFIG + 0, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; + true, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; + 0, // UINT32 CPU_MEMORY_CONFIG::WaitStates; + 0, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; + 16, // UINT32 CPU_MEMORY_CONFIG::BitWidth; + 0x08000000, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; + 0x00200000, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable + }, + + 0, // UINT32 ChipProtection; + 0, // UINT32 ManufacturerCode; + 0, // UINT32 DeviceCode; +}; + +BlockStorageDevice Device_BlockStorage; diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/README.md b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/README.md new file mode 100644 index 00000000..3fedf328 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/README.md @@ -0,0 +1,5 @@ +## Managed code helpers + +This folder contains helper classes to make developers life easier when coding for this target board. + +* [Adc](TI_CC3220SF_LAUNCHXL.Adc.cs) diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/TI_CC3220SF_LAUNCHXL.Gpio.cs b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/TI_CC3220SF_LAUNCHXL.Gpio.cs new file mode 100644 index 00000000..1a9adc02 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/TI_CC3220SF_LAUNCHXL.Gpio.cs @@ -0,0 +1,38 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +namespace nanoFramework.Targets.TI_CC3220SF_LAUNCHXL +{ + /// + /// Enumeration of GPIO pins in TI_CC3220SF_LAUNCHXL + /// + public static class GpioPins + { + /// + /// Switch 2, connected to CC32XX GPIO 13 + /// + public const int SW2 = 0; + + /// + /// Switch 3, connected to CC32XX GPIO 22 + /// + public const int SW3 = 1; + + /// + /// LED D10, connected to CC32XX GPIO 09 + /// + public const int LED_D10 = 4; + + /// + /// LED D9, connected to CC32XX GPIO 10 + /// + public const int LED_D9 = 5; + + /// + /// LED D8, connected to CC32XX GPIO 11 + /// + public const int LED_D8 = 6; + } +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/package.nuspec b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/package.nuspec new file mode 100644 index 00000000..8553a224 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/managed_helpers/package.nuspec @@ -0,0 +1,28 @@ + + + + nanoFramework.Targets.TI_CC3220SF_LAUNCHXL + nanoFramework.Targets.TI_CC3220SF_LAUNCHXL + 1.0.0 + nanoFramework project contributors + nanoFramework project contributors + false + + Helper classes to use TI_CC3220SF_LAUNCHXL target in C# applications. + + + + + This is an extension for .NET nanoFramework providing the GPIO pins when coding for the TI_CC3220SF_LAUNCHXL. + + https://github.com/nanoframework + https://secure.gravatar.com/avatar/97d0e092247f0716db6d4b47b7d1d1ad + https://github.com/nanoframework/nf-interpreter/blob/develop/LICENSE.md + Copyright (c) 2019 The nanoFramework project contributors + + nanoFramework, nano Framework, NETNF, NETMF, Micro Framework,.net + + + + + diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld new file mode 100644 index 00000000..5987d6c5 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR-DEBUG.ld @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2016-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +STACKSIZE = 0x800; + +MEMORY +{ + FLASH_HDR (RX) : ORIGIN = 0x01000000, LENGTH = 0x7FF + FLASH (RX) : ORIGIN = 0x01000800, LENGTH = 0x03F000 + SRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00040000 +} + +REGION_ALIAS("REGION_HDR", FLASH_HDR); +REGION_ALIAS("REGION_TEXT", FLASH); +REGION_ALIAS("REGION_BSS", SRAM); +REGION_ALIAS("REGION_DATA", SRAM); +REGION_ALIAS("REGION_STACK", SRAM); +REGION_ALIAS("REGION_HEAP", SRAM); +REGION_ALIAS("REGION_ARM_EXIDX", FLASH); +REGION_ALIAS("REGION_ARM_EXTAB", FLASH); + +SECTIONS { + + .dbghdr : ALIGN (2048) { + KEEP (*(.dbghdr)) + } > REGION_HDR + + PROVIDE (_resetVecs_base_address = + DEFINED(_resetVecs_base_address) ? _resetVecs_base_address : 0x01000800); + + .resetVecs (_resetVecs_base_address) : AT (_resetVecs_base_address) { + KEEP (*(.resetVecs)) + } > REGION_TEXT + + .ramVecs (NOLOAD) : ALIGN(1024) { + KEEP (*(.ramVecs)) + } > REGION_DATA + + .text : { + CREATE_OBJECT_SYMBOLS + *(.text) + *(.text.*) + . = ALIGN(0x4); + KEEP (*(.ctors)) + . = ALIGN(0x4); + KEEP (*(.dtors)) + . = ALIGN(0x4); + __init_array_start = .; + KEEP (*(.init_array*)) + __init_array_end = .; + *(.init) + *(.fini*) + } > REGION_TEXT AT> REGION_TEXT + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : { + *(.rodata) + *(.rodata*) + } > REGION_TEXT AT> REGION_TEXT + + .data : ALIGN (4) { + __data_load__ = LOADADDR (.data); + __data_start__ = .; + *(.data) + *(.data*) + . = ALIGN (4); + __data_end__ = .; + } > REGION_DATA AT> REGION_TEXT + + .ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX + + .ARM.extab : { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB + + .bss : { + __bss_start__ = .; + *(.shbss) + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN (4); + __bss_end__ = .; + } > REGION_BSS AT> REGION_BSS + + .heap : { + __heap_start__ = .; + end = __heap_start__; + _end = end; + __end = end; + KEEP(*(.heap)) + __heap_end__ = .; + __HeapLimit = __heap_end__; + } > REGION_HEAP AT> REGION_HEAP + + .stack (NOLOAD) : ALIGN(0x8) { + _stack = .; + __stack = .; + KEEP(*(.stack)) + . += STACKSIZE; + _stack_end = .; + __stack_end = .; + } > REGION_STACK AT> REGION_STACK +} + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", SRAM); + +/* nanoCLR rules inclusion.*/ +INCLUDE rules_clr.ld + +ENTRY(resetISR) diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld new file mode 100644 index 00000000..88f978a6 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CC3220SF_CLR.ld @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2016-2017, Texas Instruments Incorporated + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +STACKSIZE = 0x800; + +MEMORY +{ + FLASH_HDR (RX) : ORIGIN = 0x01000000, LENGTH = 0x7FF + FLASH (RX) : ORIGIN = 0x01000800, LENGTH = 0x02F000 + SRAM (RWX) : ORIGIN = 0x20000000, LENGTH = 0x00040000 +} + +REGION_ALIAS("REGION_HDR", FLASH_HDR); +REGION_ALIAS("REGION_TEXT", FLASH); +REGION_ALIAS("REGION_BSS", SRAM); +REGION_ALIAS("REGION_DATA", SRAM); +REGION_ALIAS("REGION_STACK", SRAM); +REGION_ALIAS("REGION_HEAP", SRAM); +REGION_ALIAS("REGION_ARM_EXIDX", FLASH); +REGION_ALIAS("REGION_ARM_EXTAB", FLASH); + +SECTIONS { + + .dbghdr : ALIGN (2048) { + KEEP (*(.dbghdr)) + } > REGION_HDR + + PROVIDE (_resetVecs_base_address = + DEFINED(_resetVecs_base_address) ? _resetVecs_base_address : 0x01000800); + + .resetVecs (_resetVecs_base_address) : AT (_resetVecs_base_address) { + KEEP (*(.resetVecs)) + } > REGION_TEXT + + .ramVecs (NOLOAD) : ALIGN(1024) { + KEEP (*(.ramVecs)) + } > REGION_DATA + + .text : { + CREATE_OBJECT_SYMBOLS + *(.text) + *(.text.*) + . = ALIGN(0x4); + KEEP (*(.ctors)) + . = ALIGN(0x4); + KEEP (*(.dtors)) + . = ALIGN(0x4); + __init_array_start = .; + KEEP (*(.init_array*)) + __init_array_end = .; + *(.init) + *(.fini*) + } > REGION_TEXT AT> REGION_TEXT + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : { + *(.rodata) + *(.rodata*) + } > REGION_TEXT AT> REGION_TEXT + + .data : ALIGN (4) { + __data_load__ = LOADADDR (.data); + __data_start__ = .; + *(.data) + *(.data*) + . = ALIGN (4); + __data_end__ = .; + } > REGION_DATA AT> REGION_TEXT + + .ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX + + .ARM.extab : { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB + + .bss : { + __bss_start__ = .; + *(.shbss) + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN (4); + __bss_end__ = .; + } > REGION_BSS AT> REGION_BSS + + .heap : { + __heap_start__ = .; + end = __heap_start__; + _end = end; + __end = end; + KEEP(*(.heap)) + __heap_end__ = .; + __HeapLimit = __heap_end__; + } > REGION_HEAP AT> REGION_HEAP + + .stack (NOLOAD) : ALIGN(0x8) { + _stack = .; + __stack = .; + KEEP(*(.stack)) + . += STACKSIZE; + _stack_end = .; + __stack_end = .; + } > REGION_STACK AT> REGION_STACK +} + +/* RAM region to be used for the nanoFramework CLR managed heap.*/ +REGION_ALIAS("CLR_MANAGED_HEAP_RAM", SRAM); + +/* nanoCLR rules inclusion.*/ +INCLUDE rules_clr.ld + +ENTRY(resetISR) diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt new file mode 100644 index 00000000..605070bb --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/CMakeLists.txt @@ -0,0 +1,14 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append nanoCLR source files +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/main.c") +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoHAL.cpp") + +# default Wi-Fi configuration for this target +list(APPEND NANOCLR_PROJECT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/ti_drivers_net_wifi_Config.c") + +# make var global +set(NANOCLR_PROJECT_SOURCES ${NANOCLR_PROJECT_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c new file mode 100644 index 00000000..9283109b --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/main.c @@ -0,0 +1,67 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +// POSIX Header files +#include +#include + +// RTOS header files +#include "FreeRTOS.h" +#include "task.h" + +// board Header files +#include "Board.h" + +////////////////////////////// + +// Stack size in bytes +#define THREADSTACKSIZE 2024 + +extern void * mainThread(void *arg0); + +int main(void) +{ + pthread_t thread; + pthread_attr_t threadAttributes; + struct sched_param priorityParameters; + + int retc; + + // Call board init functions + Board_initGeneral(); + + // CLR settings to launch CLR thread + CLR_SETTINGS clrSettings; + (void)memset(&clrSettings, 0, sizeof(CLR_SETTINGS)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.EnterDebuggerLoopAfterExit = true; + + // Set priority and stack size attributes + pthread_attr_init(&threadAttributes); + priorityParameters.sched_priority = 1; + + retc = pthread_attr_setdetachstate(&threadAttributes, PTHREAD_CREATE_DETACHED); + + pthread_attr_setschedparam(&threadAttributes, &priorityParameters); + retc |= pthread_attr_setstacksize(&threadAttributes, THREADSTACKSIZE); + retc |= pthread_create(&thread, &threadAttributes, mainThread, &clrSettings); + if(retc != 0) + { + // pthread_create() + while(1) + { + ; + } + } + + // Start the FreeRTOS scheduler + vTaskStartScheduler(); + + return (0); +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/nanoHAL.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/nanoHAL.cpp new file mode 100644 index 00000000..076a50fc --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/nanoHAL.cpp @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +void HAL_EnterBooterMode() +{ +} + +bool g_fDoNotUninitializeDebuggerPort = false; diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/target_board.h.in b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/target_board.h.in new file mode 100644 index 00000000..25bf6abd --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/target_board.h.in @@ -0,0 +1,16 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_BOARD_NANOCLR_H_ +#define _TARGET_BOARD_NANOCLR_H_ + +#include + +#endif /* _TARGET_BOARD_NANOCLR_H_ */ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/ti_drivers_net_wifi_Config.c b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/ti_drivers_net_wifi_Config.c new file mode 100644 index 00000000..8806c8f0 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/nanoCLR/ti_drivers_net_wifi_Config.c @@ -0,0 +1,31 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +// TI-DRIVERS Header files +#include + + +///////////////////////////////////////////////// +// Default Wi-Fi configuration for this target // +///////////////////////////////////////////////// + +const SlWifiCC32XXConfig_t SimpleLinkWifiCC32XX_config = { + + .Mode = ROLE_STA, + .Ipv4Mode = SL_NETCFG_IPV4_STA_ADDR_MODE, + .ConnectionPolicy = SL_WLAN_CONNECTION_POLICY(1,0,0,1), + .PMPolicy = SL_WLAN_ALWAYS_ON_POLICY,//SL_WLAN_NORMAL_POLICY, + .MaxSleepTimeMS = 0, + .ScanPolicy = SL_WLAN_SCAN_POLICY(0,0), + .ScanIntervalInSeconds = 0, + .Ipv4Config = SL_NETCFG_ADDR_DHCP, + .Ipv4 = 0, + .IpMask = 0, + .IpGateway = 0, + .IpDnsServer = 0, + .ProvisioningStop = 0, + .DeleteAllProfile = 0 +}; diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_BlockStorage.c b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_BlockStorage.c new file mode 100644 index 00000000..ab075246 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_BlockStorage.c @@ -0,0 +1,15 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +extern struct BlockStorageDevice Device_BlockStorage; +extern struct MEMORY_MAPPED_NOR_BLOCK_CONFIG Device_BlockStorageConfig; +extern IBlockStorageDevice CC32xxFlash_BlockStorageInterface; + +void BlockStorage_AddDevices() +{ + BlockStorageList_AddDevice( (BlockStorageDevice*)&Device_BlockStorage, &CC32xxFlash_BlockStorageInterface, &Device_BlockStorageConfig, true); +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_BlockStorage.h b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_BlockStorage.h new file mode 100644 index 00000000..74d115d3 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 2 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 2 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.c b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.c new file mode 100644 index 00000000..7aabc922 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.c @@ -0,0 +1,28 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "target_board.h" +#include "target_common.h" + +HAL_SYSTEM_CONFIG HalSystemConfig = +{ + { true }, // HAL_DRIVER_CONFIG_HEADER Header; + + 1, //ConvertCOM_DebugHandle(1), + 0,//ConvertCOM_DebugHandle(0), + 921600, + 0, // STDIO = COM2 or COM1 + + { RAM1_MEMORY_StartAddress, RAM1_MEMORY_Size }, + { FLASH1_MEMORY_StartAddress, FLASH1_MEMORY_Size } +}; + +HAL_TARGET_CONFIGURATION g_TargetConfiguration; + +// these addresses are the start and end address of flash region FLASH +uint32_t __nanoImage_start__ = FLASH1_MEMORY_StartAddress; +uint32_t __nanoImage_end__ = (FLASH1_MEMORY_StartAddress + FLASH1_MEMORY_Size); diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.h.in b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.h.in new file mode 100644 index 00000000..fd6f12cf --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_common.h.in @@ -0,0 +1,53 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_COMMON_H_ +#define _TARGET_COMMON_H_ + +#include + +///////////////////////////////////////////////////////////////////////////////////////// +// The following addresses and sizes should be filled in according to the SoC data-sheet +// they also must be coherent with what's in the linker file for nanoBooter and nanoCLR + +// RAM base address +#define RAM1_MEMORY_StartAddress ((uint32_t)0x20000000) +// RAM size +#define RAM1_MEMORY_Size ((uint32_t)0x00040000) + +// FLASH base address +#define FLASH1_MEMORY_StartAddress ((uint32_t)0x01000800) +// FLASH size +#define FLASH1_MEMORY_Size ((uint32_t)0x000FF800) + +///////////////////////////////////////////////////////////////////////////////////////// + +///////////////////////////////////// +#define PLATFORM_HAS_RNG TRUE +///////////////////////////////////// + +////////////////////////////////////////////// +#define OEMSYSTEMINFOSTRING "nanoCLR running @ @TI_BOARD@ built with TI SL CC32xx SDK v3.10.00.04" +#define TARGETNAMESTRING "@TI_BOARD@" +#define PLATFORMNAMESTRING "TI_SL_CC32xx" +////////////////////////////////////////////// + +////////////////////////////////////////////// +// set Wire Protocol packet size +// valid sizes are 1024, 512, 256, 128 +// check Monitor_Ping_Source_Flags enum +#define WP_PACKET_SIZE 256U +////////////////////////////////////////////// + +///////////////////////////////////// +//#define EVENTS_HEART_BEAT GPIO_toggle(Board_GPIO_LED0) +///////////////////////////////////// + +#endif /* _TARGET_COMMON_H_ */ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_sntp_opts.h b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_sntp_opts.h new file mode 100644 index 00000000..ecd95c61 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_sntp_opts.h @@ -0,0 +1,24 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_SNTP_OPTS_H_ +#define _TARGET_SNTP_OPTS_H_ 1 + +#define SNTP_SERVER_DEFAULT_ADDRESS "0.pool.ntp.org" + +// update delay (default 1 hour) +// (value in seconds) +// Must wait at least 15 sec to retry NTP server (RFC 4330) +#define SNTP_UPDATE_DELAY (60 * 60) + +// no startup delay for SNTP +// value in seconds +#define SNTP_STARTUP_DELAY (0) + +// retry timeout +// value in seconds +#define SNTP_RETRY_TIMEOUT (10) + +#endif // _TARGET_SNTP_OPTS_H_ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_adc_config.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_adc_config.cpp new file mode 100644 index 00000000..d7b7376b --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_adc_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_i2c_config.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_i2c_config.cpp new file mode 100644 index 00000000..76238dbe --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_i2c_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_pwm_config.h b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_pwm_config.h new file mode 100644 index 00000000..e3c11018 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_pwm_config.h @@ -0,0 +1,7 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +// number of PWM pins available in this target +#define PWM_PIN_COUNT (2) diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_spi_config.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_spi_config.cpp new file mode 100644 index 00000000..76238dbe --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/TI_CC3220SF_LAUNCHXL/target_windows_devices_spi_config.cpp @@ -0,0 +1,8 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +/////////////////////////////////////////////////////////////////////////////////////////////////// +// THIS FILE IS BLANK ON PURPOSE BECAUSE THIS TARGET DOESN'T REQUIRE THIS SPECIFIC CONFIGURATION // +/////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/common/CMakeLists.txt b/source/native/nf-interpreter/targets/TI-SimpleLink/common/CMakeLists.txt new file mode 100644 index 00000000..f8696b1a --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/common/CMakeLists.txt @@ -0,0 +1,37 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +# append target TI SimpleLink common source files +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/platform_heap.c") + +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_ReceiverThread.c") +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_HAL_Interface.c") + +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Target_BlockStorage_CC32xxFlashDriver.c") +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/platform_BlockStorage.c") + +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/FreeRTOS-openocd.c") + +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/GenericPort.cpp") +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/syscalls.c") +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoSupport_CRC32.c") + +# append nanoHAL +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/platformHAL.c") +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/platformHAL_Time.cpp") + +# append configuration manager according to target +if("${TARGET_SERIES}" STREQUAL "CC32xx") + list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_ConfigurationManager_CC32xx.cpp") +endif() + +# append sockets and SSL driver +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/simplelink_sockets_functions.cpp") +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/simplelink_sockets.cpp") +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/sockets_simplelink.cpp") +list(APPEND TARGET_TI_SimpleLink_COMMON_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/ssl_simplelink.cpp") + +# make var global +set(TARGET_TI_SimpleLink_COMMON_SOURCES ${TARGET_TI_SimpleLink_COMMON_SOURCES} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/common/FreeRTOS-openocd.c b/source/native/nf-interpreter/targets/TI-SimpleLink/common/FreeRTOS-openocd.c new file mode 100644 index 00000000..81a3ab77 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/common/FreeRTOS-openocd.c @@ -0,0 +1,20 @@ +/* + * Since at least FreeRTOS V7.5.3 uxTopUsedPriority is no longer + * present in the kernel, so it has to be supplied by other means for + * OpenOCD's threads awareness. + * + * Add this file to your project, and, if you're using --gc-sections, + * ``--undefined=uxTopUsedPriority'' (or + * ``-Wl,--undefined=uxTopUsedPriority'' when using gcc for final + * linking) to your LDFLAGS; same with all the other symbols you need. + */ + +#include "FreeRTOS.h" + +#ifdef __GNUC__ +#define USED __attribute__((used)) +#else +#define USED +#endif + +const int USED uxTopUsedPriority = configMAX_PRIORITIES - 1; diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/common/GenericPort.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/common/GenericPort.cpp new file mode 100644 index 00000000..5629083b --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/common/GenericPort.cpp @@ -0,0 +1,53 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include + +extern UART_Handle uart; +extern SemaphoreP_Handle uartMutex; + +// developer note: +// Outputing to board UART can be done only if there is no debugger attached, because it uses the same UART. + +extern "C" uint32_t DebuggerPort_WriteProxy(const char *format, ...) +{ + va_list arg; + uint32_t chars = 0; + + if( CLR_EE_DBG_IS_NOT( Enabled ) ) + { + if(SemaphoreP_pend(uartMutex, UART_WAIT_FOREVER) == SemaphoreP_OK) + { + va_start( arg, format ); + + chars = CLR_Debug::PrintfV( format, arg ); + + va_end( arg ); + + SemaphoreP_post(uartMutex); + } + } + + return chars; +} + +uint32_t GenericPort_Write( int portNum, const char* data, size_t size ) +{ + (void)portNum; + + if( CLR_EE_DBG_IS_NOT( Enabled ) ) + { + // debugger port is NOT in use, OK to output to UART + // send characters directly to the UART port + UART_write(uart, data, size); + + return size; + } + + return (uint32_t)size; +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/common/Target_BlockStorage_CC32xxFlashDriver.c b/source/native/nf-interpreter/targets/TI-SimpleLink/common/Target_BlockStorage_CC32xxFlashDriver.c new file mode 100644 index 00000000..41f07d89 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/common/Target_BlockStorage_CC32xxFlashDriver.c @@ -0,0 +1,91 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// includes from SimpleLink +#include "inc/hw_types.h" +#include + +// local defines +#define FLASH_ERASED_WORD 0x0FFFFFFFFU + +bool CC32xxFlashDriver_InitializeDevice(void* context) +{ + (void)context; + + // SimpleLink driver takes care of this, so always true + return true; +} + +bool CC32xxFlashDriver_UninitializeDevice(void* context) +{ + (void)context; + + // SimpleLink driver takes care of this, so always true + return true; +} + +DeviceBlockInfo* CC32xxFlashDriver_GetDeviceInfo(void* context) +{ + MEMORY_MAPPED_NOR_BLOCK_CONFIG* config = context; + + return config->BlockConfig.BlockDeviceInformation; +} + +bool CC32xxFlashDriver_Read(void* context, ByteAddress startAddress, unsigned int numBytes, unsigned char* buffer) +{ + (void)context; + + // ... and always return true + return true; +} + +bool CC32xxFlashDriver_Write(void* context, ByteAddress startAddress, unsigned int numBytes, unsigned char* buffer, bool readModifyWrite) +{ + (void)context; + (void)readModifyWrite; + + if(FlashProgram((unsigned long*)buffer, (unsigned long) startAddress, (unsigned long) numBytes) == 0) + { + return true; + } + + return false; +} + +bool CC32xxFlashDriver_IsBlockErased(void* context, ByteAddress blockAddress, unsigned int length) +{ + (void)context; + + unsigned long* cursor = (unsigned long *)blockAddress; + unsigned long* endAddress = (unsigned long *)(blockAddress + length); + + // an erased flash address has to read FLASH_ERASED_WORD + // OK to check by word (32 bits) because the erase is performed by 'block' whose size is word multiple + while(cursor < endAddress) + { + if(*cursor++ != FLASH_ERASED_WORD) + { + // found an address with something other than FLASH_ERASED_WORD!! + return false; + } + } + + // reached here so the block must be erased + return true; +} + +bool CC32xxFlashDriver_EraseBlock(void* context, ByteAddress address) +{ + (void)context; + + if(FlashErase((unsigned long) address) == 0) + { + return true; + } + + return false; +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/common/WireProtocol_HAL_Interface.c b/source/native/nf-interpreter/targets/TI-SimpleLink/common/WireProtocol_HAL_Interface.c new file mode 100644 index 00000000..5e5904a3 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/common/WireProtocol_HAL_Interface.c @@ -0,0 +1,104 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include +#include +#include + +UART_Handle uart = NULL; + +WP_Message inboundMessage; + +//////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////// +// The functions below are the ones that need to be ported to new channels/HALs when required +// These are to be considered as a reference implementations when working on new ports +// +// This reference implementation provides communication through: +// - serial port (UART/USART) +// +//////////////////////////////////////////////////////////////////////////////////////////////// + +int WP_ReceiveBytes(uint8_t* ptr, uint16_t* size) +{ + // save for latter comparison + uint16_t requestedSize = *size; + + //int readData = 0; + // sanity check for request of 0 size + if(*size) + { + ////////////////////////////////////////////////////////// + // PORTING CHANGE REQUIRED HERE // + ////////////////////////////////////////////////////////// + // change here to read (size) bytes from the input stream + // preferably with read timeout and being able to check + // if the requested number of bytes was actually read + ////////////////////////////////////////////////////////// + + // non blocking read from serial port with 500ms timeout + size_t read = UART_read(uart, ptr, requestedSize); + + ptr += read; + *size -= read; + + // check if the requested read matches the actual read count + return (requestedSize == read); + } + + return true; +} + +int WP_TransmitMessage(WP_Message* message) +{ + uint32_t writeResult; + bool operationResult = false; + + /////////////////////////////////////////////////////////// + // PORTING CHANGE REQUIRED HERE // + /////////////////////////////////////////////////////////// + // change here to write (size) bytes to the output stream + // preferably with timeout and being able to check + // if the write was successfull or at least buffered + ////////////////////////////////////////////////////////// + + TRACE( TRACE_HEADERS, "TXMSG: 0x%08X, 0x%08X, 0x%08X\n", message->m_header.m_cmd, message->m_header.m_flags, message->m_header.m_size ); + + // write header to uart + writeResult = UART_write(uart, (const void *)&message->m_header, sizeof(message->m_header)); + + if(writeResult == sizeof(message->m_header)) + { + operationResult = true; + + // if there is anything on the payload send it to the output stream + if(message->m_header.m_size && message->m_payload) + { + /////////////////////////////////////////////////////////// + // PORTING CHANGE REQUIRED HERE // + /////////////////////////////////////////////////////////// + // see description above + ////////////////////////////////////////////////////////// + + // reset flag + operationResult = false; + + writeResult = UART_write(uart, (const void *)message->m_payload, message->m_header.m_size); + + if(writeResult == message->m_header.m_size) + { + operationResult = true; + + TRACE0( TRACE_ERRORS, "TXMSG: OK\n"); + } + } + } + + return operationResult; +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/common/WireProtocol_ReceiverThread.c b/source/native/nf-interpreter/targets/TI-SimpleLink/common/WireProtocol_ReceiverThread.c new file mode 100644 index 00000000..8943333d --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/common/WireProtocol_ReceiverThread.c @@ -0,0 +1,31 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "WireProtocol_HAL_Interface.h" +#include +#include + +extern WP_Message inboundMessage; + +void WP_Message_Initialize(WP_Message* a); +void WP_Message_PrepareReception(WP_Message* a); +void WP_Message_Process(WP_Message* a); + +void* ReceiverThread(void* argument) +{ + (void)argument; + + // loop forever + while (1) + { + WP_Message_Initialize(&inboundMessage); + WP_Message_PrepareReception(&inboundMessage); + + WP_Message_Process(&inboundMessage); + + // Allow other tasks a chance to run + taskYIELD(); + } +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/common/nanoSupport_CRC32.c b/source/native/nf-interpreter/targets/TI-SimpleLink/common/nanoSupport_CRC32.c new file mode 100644 index 00000000..0f7b0e60 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/common/nanoSupport_CRC32.c @@ -0,0 +1,21 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include + +// strong implementation of this function specific to the TI Simple Link targets +unsigned int SUPPORT_ComputeCRC(const void* rgBlock, int nLength, unsigned int crc) +{ + MAP_CRCSeedSet(DTHE_BASE, crc); + + crc = MAP_CRCDataProcess(DTHE_BASE, rgBlock, nLength, CRC_CFG_SIZE_8BIT); + + return crc; +}; diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/common/platformHAL.c b/source/native/nf-interpreter/targets/TI-SimpleLink/common/platformHAL.c new file mode 100644 index 00000000..92fc4de2 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/common/platformHAL.c @@ -0,0 +1,51 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +void HAL_AssertEx() +{ + __asm__("BKPT"); + while(true) { /*nop*/ } +} + +#if !defined(BUILD_RTM) + +void HARD_Breakpoint() +{ + __asm__("BKPT"); + while(true) { /*nop*/ } +}; + +#endif // !defined(BUILD_RTM) + + +// Provides information whether the configuration block storage requires erase command before sending the update command +// The 'weak' implementation for TI SimpleLink targets is false +// If a target implements the store differently it has to provide a 'strong' implementation of this. +__nfweak bool Target_ConfigUpdateRequiresErase() +{ + return false; +}; + +bool Target_HasNanoBooter() +{ + return false; +}; + +// declarations of platform capabilities +uint32_t GetPlatformCapabilities() +{ + return 0; +}; + +// declarations of target capabilities +// If a target has something to declare it has to provide a 'strong' implementation of this. +__nfweak uint32_t GetTargetCapabilities() +{ + return 0; +}; diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/common/platformHAL_Time.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/common/platformHAL_Time.cpp new file mode 100644 index 00000000..bcb18568 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/common/platformHAL_Time.cpp @@ -0,0 +1,21 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +// Converts FreeRTOS Tickcount to .NET ticks (100 nanoseconds) +uint64_t HAL_Time_SysTicksToTime(unsigned int sysTicks) +{ + return (((int64_t)sysTicks * (int64_t)1000000 + (int64_t)configTICK_RATE_HZ - 1) / (int64_t)configTICK_RATE_HZ) * 10; +} + +// because HAL_Time_SysTicksToTime needs to be called from C we need a proxy to allow it to be called from 'C' code +extern "C" { + + uint64_t HAL_Time_SysTicksToTime_C(unsigned int sysTicks) + { + return HAL_Time_SysTicksToTime(sysTicks); + } +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/common/platform_BlockStorage.c b/source/native/nf-interpreter/targets/TI-SimpleLink/common/platform_BlockStorage.c new file mode 100644 index 00000000..0af51e54 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/common/platform_BlockStorage.c @@ -0,0 +1,22 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// map here the Block Storage Interface to the CC32xx driver +IBlockStorageDevice CC32xxFlash_BlockStorageInterface = +{ + &CC32xxFlashDriver_InitializeDevice, + &CC32xxFlashDriver_UninitializeDevice, + &CC32xxFlashDriver_GetDeviceInfo, + &CC32xxFlashDriver_Read, + &CC32xxFlashDriver_Write, + NULL, + &CC32xxFlashDriver_IsBlockErased, + &CC32xxFlashDriver_EraseBlock, + NULL, + NULL +}; diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/common/platform_heap.c b/source/native/nf-interpreter/targets/TI-SimpleLink/common/platform_heap.c new file mode 100644 index 00000000..d2507def --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/common/platform_heap.c @@ -0,0 +1,18 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +void* platform_malloc(size_t size) { + return malloc(size); +} + +void platform_free(void* ptr) { + free(ptr); +} + +void* platform_realloc(void* ptr, size_t size) { + return realloc(ptr, size); +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/common/rules_clr.ld b/source/native/nf-interpreter/targets/TI-SimpleLink/common/rules_clr.ld new file mode 100644 index 00000000..e9359385 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/common/rules_clr.ld @@ -0,0 +1,15 @@ + SECTIONS +{ + + /* nanoFramework CLR managed heap section at the specified RAM section.*/ + .clr_managed_heap (NOLOAD) : + { + . = ALIGN(8); + __clr_managed_heap_base__ = .; + PROVIDE(HeapBegin = LOADADDR(.clr_managed_heap)); + . = ORIGIN(CLR_MANAGED_HEAP_RAM) + LENGTH(CLR_MANAGED_HEAP_RAM); + . = ALIGN(8); + __clr_managed_heap_end__ = .; + PROVIDE(HeapEnd = .); + } > CLR_MANAGED_HEAP_RAM +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/common/simplelink_sockets.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/common/simplelink_sockets.cpp new file mode 100644 index 00000000..57704aa7 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/common/simplelink_sockets.cpp @@ -0,0 +1,129 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "simplelink_sockets.h" + +//--// + +#if defined(DEBUG) +#define DEBUG_HANDLE_SOCKET_ERROR(t,a) +// assume there is something to add in later?? +#else +#define DEBUG_HANDLE_SOCKET_ERROR(t,a) +#endif + +//--// + +//--// +static HAL_CONTINUATION PostAddressChangedContinuation; +static HAL_CONTINUATION PostAvailabilityOnContinuation; +static HAL_CONTINUATION PostAvailabilityOffContinuation; + +void PostAddressChanged(void* arg) +{ + (void)arg; + + Network_PostEvent(NetworkEventType_AddressChanged, 0, 0); +} + +void PostAvailabilityOn(void* arg) +{ + (void)arg; + + Network_PostEvent(NetworkEventType_AvailabilityChanged, NetworkEventFlags_NetworkAvailable, 0); +} + +void PostAvailabilityOff(void* arg) +{ + (void)arg; + + Network_PostEvent(NetworkEventType_AvailabilityChanged, NetworkEventFlags_NetworkNOTAvailable, 0); +} + +void Link_callback(bool linkUp) +{ + if (linkUp) + { + if (!PostAvailabilityOnContinuation.IsLinked()) + PostAvailabilityOnContinuation.Enqueue(); + } + else + { + if (!PostAvailabilityOffContinuation.IsLinked()) + PostAvailabilityOffContinuation.Enqueue(); + } + + Events_Set(SYSTEM_EVENT_FLAG_SOCKET); + Events_Set(SYSTEM_EVENT_FLAG_NETWORK); +} + +void Status_callback() +{ + if (!PostAddressChangedContinuation.IsLinked()) + PostAddressChangedContinuation.Enqueue(); + +#if !defined(BUILD_RTM) + // lcd_printf("\f\n\n\n\n\n\nLink Update: %s\n", (netif_is_up(netif) ? "UP " : "DOWN")); + // lcd_printf(" IP: %d.%d.%d.%d\n", (netif->ip_addr.addr >> 0) & 0xFF, + // (netif->ip_addr.addr >> 8) & 0xFF, + // (netif->ip_addr.addr >> 16) & 0xFF, + // (netif->ip_addr.addr >> 24) & 0xFF); + // lcd_printf(" SM: %d.%d.%d.%d\n", (netif->netmask.addr >> 0) & 0xFF, + // (netif->netmask.addr >> 8) & 0xFF, + // (netif->netmask.addr >> 16) & 0xFF, + // (netif->netmask.addr >> 24) & 0xFF); + // lcd_printf(" GW: %d.%d.%d.%d\n", (netif->gw.addr >> 0) & 0xFF, + // (netif->gw.addr >> 8) & 0xFF, + // (netif->gw.addr >> 16) & 0xFF, + // (netif->gw.addr >> 24) & 0xFF); + +//FIXME debug_printf("IP Address: %d.%d.%d.%d\n", (netif->ip_addr.u_addr.ip4.addr >> 0) & 0xFF, +// (netif->ip_addr.u_addr.ip4.addr >> 8) & 0xFF, +// (netif->ip_addr.u_addr.ip4.addr >> 16) & 0xFF, +// (netif->ip_addr.u_addr.ip4.addr >> 24) & 0xFF); +#if LWIP_DNS + if (netif->flags & NETIF_FLAG_ETHARP) + { + //ip_addr_t * dns1 = dns_getserver(0); + //ip_addr_t * dns2 = dns_getserver(1); + + // lcd_printf(" dns1: %d.%d.%d.%d\n", (dns1.addr >> 0) & 0xFF, + // (dns1.addr >> 8) & 0xFF, + // (dns1.addr >> 16) & 0xFF, + // (dns1.addr >> 24) & 0xFF); + + // lcd_printf(" dns2: %d.%d.%d.%d\n", (dns2.addr >> 0) & 0xFF, + // (dns2.addr >> 8) & 0xFF, + // (dns2.addr >> 16) & 0xFF, + // (dns2.addr >> 24) & 0xFF); + } +#endif + Events_Set(SYSTEM_EVENT_FLAG_SOCKET); + Events_Set(SYSTEM_EVENT_FLAG_NETWORK); +} +#endif + +bool SimpleLink_SOCKETS_Initialize() +{ + NATIVE_PROFILE_PAL_NETWORK(); + + PostAddressChangedContinuation.InitializeCallback(PostAddressChanged, NULL); + PostAvailabilityOnContinuation.InitializeCallback(PostAvailabilityOn, NULL); + PostAvailabilityOffContinuation.InitializeCallback(PostAvailabilityOff, NULL); + + return true; +} + +bool SimpleLink_SOCKETS_Uninitialize() +{ + NATIVE_PROFILE_PAL_NETWORK(); + + PostAddressChangedContinuation.Abort(); + PostAvailabilityOnContinuation.Abort(); + PostAvailabilityOffContinuation.Abort(); + + return true; +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/common/simplelink_sockets.h b/source/native/nf-interpreter/targets/TI-SimpleLink/common/simplelink_sockets.h new file mode 100644 index 00000000..d7cf7465 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/common/simplelink_sockets.h @@ -0,0 +1,32 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#ifndef _SIMPLELINK_SOCKETS_H_ +#define _SIMPLELINK_SOCKETS_H_ + +#include +#include + +#define NATIVE_PROFILE_PAL_NETWORK() + +#ifdef __cplusplus +extern "C" { +#endif + +bool SimpleLink_SOCKETS_Initialize(); +bool SimpleLink_SOCKETS_Uninitialize(); + +void Status_callback(); +void Link_callback(bool linkUp); +// void PostAddressChanged(void* arg); +// void PostAvailabilityOn(void* arg); +// void PostAvailabilityOff(void* arg); + +#ifdef __cplusplus +} +#endif + +#endif // _SIMPLELINK_SOCKETS_H_ 1 diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/common/simplelink_sockets_functions.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/common/simplelink_sockets_functions.cpp new file mode 100644 index 00000000..9f8dbcb9 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/common/simplelink_sockets_functions.cpp @@ -0,0 +1,178 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include "simplelink_sockets.h" + +#include + +#define NATIVE_PROFILE_PAL_NETWORK() + +bool HAL_SOCK_Initialize() +{ + NATIVE_PROFILE_PAL_NETWORK(); + return SimpleLink_SOCKETS_Initialize(); +} + +bool HAL_SOCK_Uninitialize() +{ + NATIVE_PROFILE_PAL_NETWORK(); + return SimpleLink_SOCKETS_Uninitialize(); +} + +HRESULT HAL_SOCK_CONFIGURATION_LoadAdapterConfiguration(HAL_Configuration_NetworkInterface* config, uint32_t interfaceIndex) +{ + NATIVE_PROFILE_PAL_NETWORK(); + + uint16_t configOptions; + uint16_t ipLen = sizeof(SlNetCfgIpV4Args_t); + SlNetCfgIpV4Args_t ipV4 = {0}; + + if(config->StartupAddressMode == AddressMode_DHCP) + { + // if this is on DHCP we need to load whatever we have on top of the stored configuration +#if LWIP_IPV6 + { + // FIXME IPV6 + // config->IPv6Address = networkInterface->ip_addr.u_addr.ip6.addr; + // config->IPv6NetMask = networkInterface->netmask.u_addr.ip6.addr; + // config->IPv6GatewayAddress = networkInterface->gw.u_addr.ip6.addr; + } +#else + if (sl_NetCfgGet(SL_NETCFG_IPV4_STA_ADDR_MODE, &configOptions, &ipLen, (uint8_t *)&ipV4) >= 0) + { + config->IPv4Address = sl_Ntohl(ipV4.Ip); + config->IPv4NetMask = sl_Ntohl(ipV4.IpMask); + config->IPv4GatewayAddress = sl_Ntohl(ipV4.IpGateway); + config->IPv4DNSAddress1 = sl_Ntohl(ipV4.IpDnsServer); + config->IPv4DNSAddress2 = 0; + } + else + { + config->IPv4Address = 0; + config->IPv4NetMask = 0; + config->IPv4GatewayAddress = 0; + config->IPv4DNSAddress1 = 0; + config->IPv4DNSAddress2 = 0; + } +#endif + } + + return S_OK; +} + +HRESULT HAL_SOCK_CONFIGURATION_UpdateAdapterConfiguration(HAL_Configuration_NetworkInterface* config, uint32_t interfaceIndex, uint32_t updateFlags) +{ + NATIVE_PROFILE_PAL_NETWORK(); + + uint16_t configOptions; + uint16_t ipLen = sizeof(SlNetCfgIpV4Args_t); + SlNetCfgIpV4Args_t ipV4 = {0}; + + bool enableDHCP = (config->StartupAddressMode == AddressMode_DHCP); + + if (sl_NetCfgGet(SL_NETCFG_IPV4_STA_ADDR_MODE, &configOptions, &ipLen, (uint8_t *)&ipV4) >= 0) + { + // when using DHCP do not use the static settings + if(0 != (updateFlags & UpdateOperation_Dns)) + { + // FIXME IPV6 + if(config->AutomaticDNS == 0) + { + // user defined DNS addresses + if(config->IPv4DNSAddress1 != 0) + { + ipV4.IpDnsServer = sl_Htonl(config->IPv4DNSAddress1); + } + + // this interface doesn't have a secondary DNS + + // update configuration + if(sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE, SL_NETCFG_ADDR_STATIC, sizeof(SlNetCfgIpV4Args_t), (uint8_t*)&ipV4) < 0) + { + return CLR_E_FAIL; + } + } + } + + if(0 != (updateFlags & UpdateOperation_Dhcp)) + { + if(enableDHCP) + { + // need to start DHCP + if(sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE, SL_NETCFG_ADDR_DHCP ,0 ,0 ) < 0) + { + return CLR_E_FAIL; + } + } + else + { + // we should be polite and let the DHCP server that we are now using a static IP + sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE, SL_NETCFG_ADDR_RELEASE_IP_SET, 0, 0); + + ipV4.Ip = sl_Htonl(config->IPv4Address); + ipV4.IpMask = sl_Htonl(config->IPv4NetMask); + ipV4.IpGateway = sl_Htonl(config->IPv4GatewayAddress); + ipV4.IpDnsServer = sl_Htonl(config->IPv4DNSAddress1); + + if(sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE, SL_NETCFG_ADDR_STATIC, sizeof(SlNetCfgIpV4Args_t), (uint8_t*)&ipV4) < 0) + { + return CLR_E_FAIL; + } + + } + } + + if(enableDHCP) + { + if(0 != (updateFlags & UpdateOperation_DhcpRelease)) + { + sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE, SL_NETCFG_ADDR_RELEASE_IP_SET, 0, 0); + } + else if(0 != (updateFlags & UpdateOperation_DhcpRenew)) + { + //dhcp_renew(networkInterface); + } + else if(0 != (updateFlags & (UpdateOperation_DhcpRelease | UpdateOperation_DhcpRenew)) ) + { + return CLR_E_INVALID_PARAMETER; + } + } + + if(0 != (updateFlags & UpdateOperation_Mac)) + { + uint8_t macAddress[SL_MAC_ADDR_LEN]; + + memcpy(macAddress, config->MacAddress, SL_MAC_ADDR_LEN); + + if(sl_NetCfgSet(SL_NETCFG_MAC_ADDRESS_SET, 1, SL_MAC_ADDR_LEN, (uint8_t*)macAddress) < 0) + { + return CLR_E_FAIL; + } + } + } + + // all changes require SL reinit + sl_Stop(0); + sl_Start(NULL,NULL,NULL); + + return S_OK; +} + +void HAL_SOCK_EventsSet( uint32_t events ) +{ + NATIVE_PROFILE_PAL_NETWORK(); + ASSERT( (events == SOCKET_EVENT_FLAG_SOCKET) || (events == SOCKET_EVENT_FLAG_SOCKETS_READY)); + + Events_Set( SYSTEM_EVENT_FLAG_SOCKET ); +} + +void * HAL_SOCK_GlobalLockContext() +{ + NATIVE_PROFILE_PAL_NETWORK(); + return NULL; +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/common/sockets_simplelink.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/common/sockets_simplelink.cpp new file mode 100644 index 00000000..6d7ad04c --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/common/sockets_simplelink.cpp @@ -0,0 +1,900 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include "simplelink_sockets.h" + +#include +#include +#include + +//--// + +// this is to store the return value of the calls to sockets APIs +int socketErrorCode; + +static int MARSHAL_SOCK_FDSET_TO_SL_SDSET(SOCK_fd_set* sf, SlNetSock_SdSet_t* f) +{ + if(f != NULL && sf != NULL) + { + SlNetSock_sdsClrAll(f); + + for(unsigned int i=0; i < sf->fd_count; i++) + { + SlNetSock_sdsSet(sf->fd_array[i], f); + } + + return sf->fd_count; + } + + return 0; +} + +static void MARSHAL_SL_SDSET_TO_SOCK_FDSET(SOCK_fd_set* sf, SlNetSock_SdSet_t* f) +{ + if(sf != NULL && f != NULL) + { + int cnt = sf->fd_count; + sf->fd_count = 0; + + for(int i=0; ifd_array[i], f)) + { + sf->fd_array[sf->fd_count] = sf->fd_array[i]; + sf->fd_count++; + } + } + } +} + +int GetNativeTcpOption (int optname) +{ + int nativeOptionName = 0; + + switch(optname) + { + case SOCK_TCP_NODELAY: + nativeOptionName = SLNETSOCK_TCP_NODELAY; + break; + + // case SOCK_SOCKO_KEEPALIVE: + // nativeOptionName = TCP_KEEPALIVE; + // break; + + // allow the C# user to specify LWIP options that our managed enum + // doesn't support + default: + nativeOptionName = optname; + break; + } + return nativeOptionName; +} + +int GetNativeSockOption (int optname) +{ + int nativeOptionName = 0; + + switch(optname) + { + case SOCK_SOCKO_DONTLINGER: + case SOCK_SOCKO_LINGER: + nativeOptionName = SLNETSOCK_OPSOCK_LINGER; + break; + // case SOCK_SOCKO_SENDTIMEOUT: + // nativeOptionName = SO_SNDTIMEO; + // break; + case SOCK_SOCKO_RECEIVETIMEOUT: + nativeOptionName = SLNETSOCK_OPSOCK_RCV_TIMEO; + break; + // case SOCK_SOCKO_EXCLUSIVEADDRESSUSE: + // case SOCK_SOCKO_REUSEADDRESS: + // nativeOptionName = SO_REUSEADDR; + // break; + case SOCK_SOCKO_KEEPALIVE: + nativeOptionName = SLNETSOCK_OPSOCK_KEEPALIVE; + break; + case SOCK_SOCKO_ERROR: + nativeOptionName = SLNETSOCK_OPSOCK_ERROR; + break; + case SOCK_SOCKO_BROADCAST: + nativeOptionName = SLNETSOCK_OPSOCK_BROADCAST; + break; + case SOCK_SOCKO_RECEIVEBUFFER: + nativeOptionName = SLNETSOCK_OPSOCK_RCV_BUF; + break; + // case SOCK_SOCKO_SENDBUFFER: + // nativeOptionName = SO_SNDBUF; + // break; + // case SOCK_SOCKO_ACCEPTCONNECTION: + // nativeOptionName = SO_ACCEPTCONN; + // break; + // case SOCK_SOCKO_USELOOPBACK: + // nativeOptionName = SO_USELOOPBACK; + // break; + // case SOCK_SOCKO_DONTROUTE: + // nativeOptionName = SO_DONTROUTE; + // break; + // case SOCK_SOCKO_OUTOFBANDINLINE: + // nativeOptionName = SO_OOBINLINE; + // break; + + // case SOCK_SOCKO_DEBUG: + // nativeOptionName = SO_DEBUG; + // break; + + // case SOCK_SOCKO_SENDLOWWATER: + // nativeOptionName = SO_SNDLOWAT; + // break; + + // case SOCK_SOCKO_RECEIVELOWWATER: + // nativeOptionName = SO_RCVLOWAT; + // break; + + // case SOCK_SOCKO_MAXCONNECTIONS: //don't support + // case SOCK_SOCKO_UPDATE_ACCEPT_CTX: + // case SOCK_SOCKO_UPDATE_CONNECT_CTX: + // nativeOptionName = 0; + // break; + + // allow the C# user to specify LWIP options that our managed enum + // doesn't support + default: + nativeOptionName = optname; + break; + + } + + return nativeOptionName; +} + +int GetNativeIPOption (int optname) +{ + int nativeOptionName = 0; + + switch(optname) + { + // case SOCK_IPO_TTL: + // nativeOptionName = IP_TTL; + // break; + // case SOCK_IPO_TOS: + // nativeOptionName = IP_TOS; + // break; + + // case SOCK_IPO_MULTICAST_IF: + // nativeOptionName = IP_MULTICAST_IF; + // break; + // case SOCK_IPO_MULTICAST_TTL: + // nativeOptionName = SLNETSOCK_OPIP_MULTICAST_TTL; + // break; + // case SOCK_IPO_MULTICAST_LOOP: + // nativeOptionName = IP_MULTICAST_LOOP; + // break; + case SOCK_IPO_ADD_MEMBERSHIP: + nativeOptionName = SLNETSOCK_OPIP_ADD_MEMBERSHIP; + break; + case SOCK_IPO_DROP_MEMBERSHIP: + nativeOptionName = SLNETSOCK_OPIP_DROP_MEMBERSHIP; + break; + + // case SOCK_IPO_ADD_SOURCE_MEMBERSHIP: + // case SOCK_IPO_DROP_SOURCE_MEMBERSHIP: + // case SOCK_IPO_OPTIONS: + // case SOCK_IPO_HDRINCL: + // case SOCK_IPO_IP_DONTFRAGMENT: + // case SOCK_IPO_BLOCK_SOURCE: + // case SOCK_IPO_UBLOCK_SOURCE: + // case SOCK_IPO_PACKET_INFO: + // nativeOptionName = 0; + // break; + + // allow the C# user to specify LWIP options that our managed enum + // doesn't support + default: + nativeOptionName = optname; + break; + } + + return nativeOptionName; +} + +SOCK_SOCKET SOCK_socket( int family, int type, int protocol ) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_create(family, type, protocol, 0, 0); + + return socketErrorCode; +} + +int SOCK_bind( SOCK_SOCKET socket, const struct SOCK_sockaddr* address, int addressLen ) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_bind( socket, (const SlNetSock_Addr_t*)address, addressLen ); + + return socketErrorCode; +} + +int SOCK_connect(SOCK_SOCKET socket, const struct SOCK_sockaddr* address, int addressLen) +{ + NATIVE_PROFILE_PAL_COM(); + + // Simple Link connect API requires it to be called over and over until connection is established (or fails!) + // See chapter 6.7.1 of CC3X20 Programmer's Guide (doc SWRU455G). + // Our current sockets implementation handles this as blocking connect, so we have to deal with it here + // it's not optimal because it prevents the execution engine from performing task switching + // this should be addressed at the caller level be implementing a timeout execution within the connect code. + + socketErrorCode = -1; + + // loop until socket is connected (or error is returned) + while(socketErrorCode < 0) + { + socketErrorCode = SlNetSock_connect(socket, (const SlNetSock_Addr_t*)address, addressLen); + + if( socketErrorCode == SL_ERROR_BSD_EALREADY ) + { + ClockP_usleep(10*1000); + continue; + } + else if(socketErrorCode < 0) + { + sl_Close(socket); + } + break; + } + + return socketErrorCode; +} + +int SOCK_send(SOCK_SOCKET socket, const char* buf, int len, int flags) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_send(socket, buf, len, flags); + + return socketErrorCode; +} + +int SOCK_recv(SOCK_SOCKET socket, char* buf, int len, int flags) +{ + NATIVE_PROFILE_PAL_COM(); + + // check for SOCKET_READ_PEEK_OPTION because Simple Link doesn't support this flag + if(flags == SOCKET_READ_PEEK_OPTION) + { + socketErrorCode = SLNETERR_BSD_EINVAL; + } + else + { + socketErrorCode = SlNetSock_recv(socket, buf, len, flags); + } + + return socketErrorCode; +} + +int SOCK_close(SOCK_SOCKET socket) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_close(socket); + + return socketErrorCode; +} + +int SOCK_listen( SOCK_SOCKET socket, int backlog ) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_listen( socket, backlog ); + + return socketErrorCode; +} + +SOCK_SOCKET SOCK_accept( SOCK_SOCKET socket, struct SOCK_sockaddr* address, int* addressLen ) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_accept( socket, (SlNetSock_Addr_t*)address, (SlNetSocklen_t*)addressLen ); + + return socketErrorCode; +} + +int SOCK_shutdown( SOCK_SOCKET socket, int how ) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_shutdown( socket, how ); + + return socketErrorCode; +} + +int SOCK_getaddrinfo( const char* nodename, char* servname, const struct SOCK_addrinfo* hints, struct SOCK_addrinfo** res ) +{ + NATIVE_PROFILE_PAL_COM(); + + SOCK_addrinfo *ai; + SOCK_sockaddr_in *sa = NULL; + int total_size = sizeof(SOCK_addrinfo) + sizeof(SOCK_sockaddr_in); + struct SlNetUtil_addrInfo_t* addrInfo = NULL; + + if(res == NULL) return SOCK_SOCKET_ERROR; + + *res = NULL; + + // if the nodename == "" then return the IP address of this device + if(nodename[0] == 0 && servname == NULL) + { + uint16_t configOptions; + uint16_t ipLen = sizeof(SlNetCfgIpV4Args_t); + SlNetCfgIpV4Args_t ipV4 = {0}; + + if (sl_NetCfgGet(SL_NETCFG_IPV4_STA_ADDR_MODE, &configOptions, &ipLen, (uint8_t *)&ipV4) >= 0) + { + ai = (SOCK_addrinfo*)platform_malloc(total_size); + + if (ai != NULL) + { + memset(ai, 0, total_size); + sa = (SOCK_sockaddr_in*)((uint8_t*)ai + sizeof(SOCK_addrinfo)); + + /* set up sockaddr */ + #if LWIP_IPV6 + // TODO + //sa->sin_addr.S_un.S_addr = networkInterface->ip_addr.u_addr.ip4.addr; + #else + sa->sin_addr.S_un.S_addr = sl_Ntohl(ipV4.Ip); + #endif + + sa->sin_family = SL_AF_INET; + sa->sin_port = 0; + + // set up addrinfo + ai->ai_family = SL_AF_INET; + if (hints != NULL) + { + // copy socktype & protocol from hints if specified + ai->ai_socktype = hints->ai_socktype; + ai->ai_protocol = hints->ai_protocol; + } + + ai->ai_addrlen = sizeof(SOCK_sockaddr_in); + ai->ai_addr = (SOCK_sockaddr*)sa; + + *res = ai; + + return 0; + } + } + } + else + { + int err = SlNetUtil_getAddrInfo(0, nodename, servname, (SlNetUtil_addrInfo_t*)hints, &addrInfo ); + socketErrorCode = err; + + if(err >= 0) + { + /// + /// Marshal addrinfo data + /// + SlNetSock_AddrIn_t* sockaddr_in; + + ai = (SOCK_addrinfo*)platform_malloc(total_size); + if (ai == NULL) + { + SlNetUtil_freeAddrInfo(addrInfo); + } + else + { + memset(ai, 0, total_size); + + sockaddr_in = (SlNetSock_AddrIn_t*)addrInfo->ai_addr; + + sa = (SOCK_sockaddr_in*)((uint8_t*)ai + sizeof(SOCK_addrinfo)); + /* set up sockaddr */ + sa->sin_addr.S_un.S_addr = sockaddr_in->sin_addr.s_addr; + sa->sin_family = sockaddr_in->sin_family; + sa->sin_port = sockaddr_in->sin_port; + + /* set up addrinfo */ + ai->ai_family = addrInfo->ai_family; + if (hints != NULL) + { + /* copy socktype & protocol from hints if specified */ + ai->ai_socktype = hints->ai_socktype; + ai->ai_protocol = hints->ai_protocol; + } + + ai->ai_addrlen = sizeof(SOCK_sockaddr_in); + ai->ai_addr = (SOCK_sockaddr*)sa; + + *res = ai; + + // free marshalled addrinfo + SlNetUtil_freeAddrInfo(addrInfo); + + return 0; + } + } + } + + return SOCK_SOCKET_ERROR; +} + +void SOCK_freeaddrinfo( struct SOCK_addrinfo* ai ) +{ + NATIVE_PROFILE_PAL_COM(); + SlNetUtil_freeAddrInfo( (SlNetUtil_addrInfo_t*)ai ); +} + +int SOCK_ioctl( SOCK_SOCKET socket, int cmd, int* data ) +{ + NATIVE_PROFILE_PAL_COM(); + + if(cmd == SOCK_FIONBIO) + { + // adjust setting for socket blocking/non-blocking + SlNetSock_Nonblocking_t enableOption; + enableOption.nonBlockingEnabled = *data; + + socketErrorCode = SlNetSock_setOpt(socket, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_NON_BLOCKING, (uint8_t *)&enableOption, sizeof(enableOption)); + + return socketErrorCode; + } + else if(cmd == SOCK_IPPROTO_TCP) + { + // TODO + HAL_AssertEx(); + } + else if(cmd == SOCK_SOL_SOCKET) + { + // TODO + HAL_AssertEx(); + } + + // unknown command + return -1; +} + +int SOCK_getlasterror() +{ + NATIVE_PROFILE_PAL_COM(); + // FIXME + return 0;//SlNetSock_getlasterror(); +} + +int SOCK_getsocklasterror(SOCK_SOCKET socket) +{ + NATIVE_PROFILE_PAL_COM(); + + int errorNo; + + if(socketErrorCode >= 0) + { + return socketErrorCode; + } + + /* This switch case block is necessary for translating the SlNetSock error codes + * to BSD ones. The #ifdef in each case are made in order to reduce code footprint: + * This cases are compiled if and only if there's a discrepancy between the BSD error + * number and the error code returned by the SlNetSock layer. + */ + switch(socketErrorCode) + { +#if EBADF != SLNETERR_BSD_EBADF + case SLNETERR_BSD_EBADF: + errorNo = EBADF; + break; +#endif +#if ENFILE != SLNETERR_BSD_ENSOCK + case SLNETERR_BSD_ENSOCK: + errorNo = ENFILE; + break; +#endif +#if EAGAIN != SLNETERR_BSD_EAGAIN + case SLNETERR_BSD_EAGAIN: + errorNo = EAGAIN; + break; +#endif +#if ENOMEM != SLNETERR_BSD_ENOMEM + case SLNETERR_BSD_ENOMEM: + errorNo = ENOMEM; + break; +#endif +#if EACCES != SLNETERR_BSD_EACCES + case SLNETERR_BSD_EACCES: + errorNo = EACCES; + break; +#endif +#if EFAULT != SLNETERR_BSD_EFAULT + case SLNETERR_BSD_EFAULT: + errorNo = EFAULT; + break; +#endif +#if EINVAL != SLNETERR_BSD_EINVAL + case SLNETERR_BSD_EINVAL: + errorNo = EINVAL; + break; +#endif +#if EDESTADDRREQ != SLNETERR_BSD_EDESTADDRREQ + case SLNETERR_BSD_EDESTADDRREQ: + errorNo = EDESTADDRREQ; + break; +#endif +#if EPROTOTYPE != SLNETERR_BSD_EPROTOTYPE + case SLNETERR_BSD_EPROTOTYPE: + errorNo = EPROTOTYPE; + break; +#endif +#if ENOPROTOOPT != SLNETERR_BSD_ENOPROTOOPT + case SLNETERR_BSD_ENOPROTOOPT: + errorNo = ENOPROTOOPT; + break; +#endif +#if EPROTONOSUPPORT != SLNETERR_BSD_EPROTONOSUPPORT + case SLNETERR_BSD_EPROTONOSUPPORT: + errorNo = EPROTONOSUPPORT; + break; +#endif +#if EOPNOTSUPP != SLNETERR_BSD_EOPNOTSUPP + case SLNETERR_BSD_EOPNOTSUPP: + errorNo = EOPNOTSUPP; + break; +#endif +#if EAFNOSUPPORT != SLNETERR_BSD_EAFNOSUPPORT + case SLNETERR_BSD_EAFNOSUPPORT: + errorNo = EAFNOSUPPORT; + break; +#endif +#if EADDRINUSE != SLNETERR_BSD_EADDRINUSE + case SLNETERR_BSD_EADDRINUSE: + errorNo = EADDRINUSE; + break; +#endif +#if EADDRNOTAVAIL != SLNETERR_BSD_EADDRNOTAVAIL + case SLNETERR_BSD_EADDRNOTAVAIL: + errorNo = EADDRNOTAVAIL; + break; +#endif +#if ENETDOWN != SLNETERR_BSD_ENETDOWN + case SLNETERR_BSD_ENETDOWN: + errorNo = ENETDOWN; + break; +#endif +#if ENETUNREACH != SLNETERR_BSD_ENETUNREACH + case SLNETERR_BSD_ENETUNREACH: + errorNo = ENETUNREACH; + break; +#endif +#if ENOBUFS != SLNETERR_BSD_ENOBUFS + case SLNETERR_BSD_ENOBUFS: + errorNo = ENOBUFS; + break; +#endif +#if EISCONN != SLNETERR_BSD_EISCONN + case SLNETERR_BSD_EISCONN: + errorNo = EISCONN; + break; +#endif +#if ENOTCONN != SLNETERR_BSD_ENOTCONN + case SLNETERR_BSD_ENOTCONN: + errorNo = ENOTCONN; + break; +#endif +#if ETIMEDOUT != SLNETERR_BSD_ETIMEDOUT + case SLNETERR_BSD_ETIMEDOUT: + errorNo = ETIMEDOUT; + break; +#endif +#if ECONNREFUSED != SLNETERR_BSD_ECONNREFUSED + case SLNETERR_BSD_ECONNREFUSED: + errorNo = ECONNREFUSED; + break; +#endif + case SL_ERROR_BSD_EALREADY: + errorNo = SOCK_EWOULDBLOCK; + break; + + /* The cases below are propriety driver errors, which can + * be returned by the SimpleLink Driver, in various cases of failure. + * Each is mapped to the corresponding BSD error. + */ + case SLNETERR_POOL_IS_EMPTY: + case SLNETERR_RET_CODE_NO_FREE_SPACE: + case SLNETERR_RET_CODE_MUTEX_CREATION_FAILED: + case SLNETERR_RET_CODE_MALLOC_ERROR: + errorNo = ENOMEM; + break; + case SLNETERR_RET_CODE_INVALID_INPUT: + case SLNETERR_EZEROLEN: + case SLNETERR_ESMALLBUF: + case SLNETERR_INVALPARAM: + errorNo = EINVAL; + break; + case SLNETERR_RET_CODE_DOESNT_SUPPORT_NON_MANDATORY_FXN: + errorNo = EOPNOTSUPP; + break; + case SLNETERR_RET_CODE_COULDNT_FIND_RESOURCE: + errorNo = EBADF; + break; + default: + /* Do nothing .. + * If no case is true, that means that the BSD error + * code and the code returned by the NWP are either identical, + * or no propriety error has occurred. + */ + break; + } + + return errorNo; +} + +int SOCK_select( int nfds, SOCK_fd_set* readfds, SOCK_fd_set* writefds, SOCK_fd_set* exceptfds, const struct SOCK_timeval* timeout ) +{ + NATIVE_PROFILE_PAL_COM(); + + int ret = 0; + uint32_t networkInterfaceID; + + // If the network goes down then we should alert any pending socket actions + if(exceptfds != NULL && exceptfds->fd_count > 0) + { + // find the network interface for this socket + // the socket handle is "burried" inside the exceptfds struct (see the caller code in Helper__SelectSocket) + networkInterfaceID = SlNetSock_getIfID(exceptfds->fd_array[0]); + if ( networkInterfaceID == SLNETERR_RET_CODE_INVALID_INPUT ) + { + socketErrorCode = ENOTSOCK; + + return SOCK_SOCKET_ERROR; + } + + if ( SlNetIf_getConnectionStatus(networkInterfaceID) == SLNETIF_STATUS_DISCONNECTED ) + { + if(readfds != NULL) + { + readfds->fd_count = 0; + } + if(writefds != NULL) + { + writefds->fd_count = 0; + } + + socketErrorCode = ENETDOWN; + + return exceptfds->fd_count; + } + } + + // developer note: + // The original code, being lwIP based, uses the convention that 0 is infinite timeout + // Because SimpleLink infinite timeout is negative or NULL we need to translate it. + SlNetSock_Timeval_t timeoutCopy; + bool isInfiniteTimeout = false; + + if(timeout->tv_sec > 0 || timeout->tv_usec > 0) + { + timeoutCopy.tv_sec = timeout->tv_sec; + timeoutCopy.tv_usec = timeout->tv_usec; + } + else + { + isInfiniteTimeout = true; + } + + ret = SlNetSock_select( + SLNETSOCK_MAX_CONCURRENT_SOCKETS, + (SlNetSock_SdSet_t*)readfds, + (SlNetSock_SdSet_t*)writefds, + (SlNetSock_SdSet_t*)exceptfds, + isInfiniteTimeout ? NULL : &timeoutCopy ); + + socketErrorCode = ret; + + // developer notes: + // SlNetSock_select() call doesn't touch the exception SDSET. + // In SimpleLink socket exceptions are handled differently. + // We need to clear that one here because the way the caller is implemented it will think there is an exception + // because it has forced it. + SlNetSock_sdsClrAll((SlNetSock_SdSet_t*)exceptfds); + + return ret; +} + +int SOCK_setsockopt( SOCK_SOCKET socket, int level, int optname, const char* optval, int optlen ) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_setOpt( socket, level, optname, (void *) optval, optlen ); + + return socketErrorCode; +} + +int SOCK_getsockopt( SOCK_SOCKET socket, int level, int optname, char* optval, int* optlen ) +{ + NATIVE_PROFILE_PAL_COM(); + + int nativeLevel; + int nativeOptionName; + char* pNativeOptval = optval; + int ret; + + switch(level) + { + case SOCK_IPPROTO_IP: + nativeLevel = SLNETSOCK_LVL_PHY; + nativeOptionName = GetNativeIPOption(optname); + break; + case SOCK_IPPROTO_TCP: + nativeLevel = SLNETSOCK_PROTO_TCP; + nativeOptionName = GetNativeTcpOption(optname); + break; + case SOCK_IPPROTO_UDP: + case SOCK_IPPROTO_ICMP: + case SOCK_IPPROTO_IGMP: + case SOCK_IPPROTO_IPV4: + case SOCK_SOL_SOCKET: + nativeLevel = SLNETSOCK_LVL_SOCKET; + nativeOptionName = GetNativeSockOption(optname); + break; + default: + nativeLevel = level; + nativeOptionName = optname; + break; + } + + socketErrorCode = SlNetSock_getOpt( socket, nativeLevel, nativeOptionName, (void *)pNativeOptval, (SlNetSocklen_t *)optlen ); + + if(socketErrorCode == 0) + { + switch(level) + { + case SOCK_SOL_SOCKET: + switch(optname) + { + case SOCK_SOCKO_EXCLUSIVEADDRESSUSE: + case SOCK_SOCKO_DONTLINGER: + *optval = !(*(int*)optval != 0); + break; + + case SOCK_SOCKO_ACCEPTCONNECTION: + case SOCK_SOCKO_BROADCAST: + case SOCK_SOCKO_KEEPALIVE: + *optval = (*(int*)optval != 0); + break; + } + break; + } + } + + return socketErrorCode; +} + +int SOCK_getpeername( SOCK_SOCKET socket, struct SOCK_sockaddr* name, int* namelen ) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_getPeerName( socket, (SlNetSock_Addr_t*)name, (SlNetSocklen_t*)namelen ); + + return socketErrorCode; +} + +int SOCK_getsockname( SOCK_SOCKET socket, struct SOCK_sockaddr* name, int* namelen ) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_getSockName( socket, (SlNetSock_Addr_t*)name, (SlNetSocklen_t*)namelen ); + + return socketErrorCode; +} + +int SOCK_recvfrom( SOCK_SOCKET s, char* buf, int len, int flags, struct SOCK_sockaddr* from, int* fromlen ) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_recvFrom( s, buf, len, flags, (SlNetSock_Addr_t*)from, (SlSocklen_t*)fromlen ); + + return socketErrorCode; +} + +int SOCK_sendto( SOCK_SOCKET s, const char* buf, int len, int flags, const struct SOCK_sockaddr* to, int tolen ) +{ + NATIVE_PROFILE_PAL_COM(); + + socketErrorCode = SlNetSock_sendTo( s, buf, len, flags, (SlNetSock_Addr_t*)to, (SlSocklen_t)tolen ); + + return socketErrorCode; +} + +bool Network_Initialize() +{ + NATIVE_PROFILE_PAL_COM(); + + // call our equivalent to lwIP driver + return SimpleLink_SOCKETS_Initialize(); + + // network initialization is taken care of by SimpleLink + return true; +} + +bool Network_Uninitialize() +{ + NATIVE_PROFILE_PAL_COM(); + + // not required SimpleLink + return true; +} + +void SOCKETS_CloseConnections() +{ + NATIVE_PROFILE_PAL_COM(); + // FIXME + //Sockets_SimpleLink_Driver::CloseConnections(FALSE); +} + +HRESULT SOCK_CONFIGURATION_LoadAdapterConfiguration(HAL_Configuration_NetworkInterface* config, uint32_t interfaceIndex) +{ + NATIVE_PROFILE_PAL_COM(); + return HAL_SOCK_CONFIGURATION_LoadAdapterConfiguration(config, interfaceIndex); +} + +HRESULT SOCK_CONFIGURATION_UpdateAdapterConfiguration(HAL_Configuration_NetworkInterface* config, uint32_t interfaceIndex, uint32_t updateFlags) +{ + NATIVE_PROFILE_PAL_COM(); + HRESULT hr = S_OK; + bool success = FALSE; + + const uint32_t c_reInitFlag = UpdateOperation_Dhcp | + UpdateOperation_DhcpRenew | + UpdateOperation_Mac; + + const uint32_t c_uninitFlag = c_reInitFlag | UpdateOperation_DhcpRelease; + + if(0 != (updateFlags & c_uninitFlag)) + { + success = SOCKETS_DbgUninitialize(COM_SOCKET_DBG); + } + + hr = HAL_SOCK_CONFIGURATION_UpdateAdapterConfiguration(config, interfaceIndex, updateFlags); + + if(!SUCCEEDED(hr)) + { + return S_FALSE; + } + + if(0 != (updateFlags & c_reInitFlag)) + { + if(success) SOCKETS_DbgInitialize(COM_SOCKET_DBG); + } + + return hr; +} + +HRESULT SOCK_CONFIGURATION_LoadConfiguration(HAL_Configuration_NetworkInterface* config, uint32_t interfaceIndex) +{ + NATIVE_PROFILE_PAL_COM(); + HRESULT hr = S_OK; + + // load current DCHP settings + hr = SOCK_CONFIGURATION_LoadAdapterConfiguration(config, interfaceIndex); + + return hr; +} + +bool SOCKETS_DbgInitialize( int ComPortNum ) +{ + NATIVE_PROFILE_PAL_COM(); + + return true; +} + +bool SOCKETS_DbgUninitialize( int ComPortNum ) +{ + NATIVE_PROFILE_PAL_COM(); + + return true; +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/common/ssl_simplelink.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/common/ssl_simplelink.cpp new file mode 100644 index 00000000..8b2935df --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/common/ssl_simplelink.cpp @@ -0,0 +1,416 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include + +#include +#include +#include + +//--// + +// need to declare this here because the SimpleLink header doesn't have the appropriate C++ wrappers +extern "C" +{ + int32_t ClockSync_convert(uint32_t gmTime, struct tm *localTime); +} + +// TODO +bool ssl_parse_certificate_internal( + void* buf, + size_t size, + void* pwd, + void* x509 ) +{ + (void)buf; + (void)size; + (void)pwd; + (void)x509; +} + +int ssl_decode_private_key_internal( + const unsigned char *key, + size_t keyLength, + const unsigned char *password, + size_t passwordLength) +{ + (void)key; + (void)keyLength; + (void)password; + (void)passwordLength; + + return 0; +} + +int ssl_accept_internal( + int socket, + int contextHandle ) +{ + (void)socket; + (void)contextHandle; +} + +bool ssl_add_cert_auth_internal( + int contextHandle, + const char* certificate, + int certLength, + const char* certPassword ) +{ + (void)contextHandle; + (void)certificate; + (void)certLength; + (void)certPassword; + +} + +// declared at sockets_simplelink +extern int socketErrorCode; + +extern "C" +{ +void ssl_rand_seed( + const void *seed, + int length) +{ + (void)seed; + (void)length; +} +} + +bool ssl_initialize_internal() +{ + memset(&g_SSL_Driver, 0, sizeof(g_SSL_Driver)); + + return true; +} + +bool ssl_generic_init_internal( + int sslMode, + int sslVerify, + const char* certificate, + int certLength, + const uint8_t* privateKey, + int privateKeyLength, + const char* password, + int passwordLength, + int& contextHandle, + bool isServer ) +{ + (void)password; + (void)passwordLength; + (void)privateKey; + (void)privateKeyLength; + + int sslContexIndex = -1; + + SlSSL_Context* context; + SlNetSockSecAttrib_e attribName; + int32_t status; + uint32_t dummyVal = 1; + uint8_t securityMethod; + uint32_t securityCypher = SLNETSOCK_SEC_CIPHER_FULL_LIST; + + // we only have one CA root bundle, so this is fixed to 0 + uint32_t configIndex = 0; + + /////////////////////// + for(uint32_t i=0; iSecurityAttributes = SlNetSock_secAttribCreate(); + if (context->SecurityAttributes == NULL) + { + goto error; + } + + context->IsServer = isServer; + + // configure protocol + switch((SslProtocols)sslMode) + { + case SslProtocols_TLSv1: + securityMethod = SLNETSOCK_SEC_METHOD_TLSV1; + break; + + case SslProtocols_TLSv11: + securityMethod = SLNETSOCK_SEC_METHOD_TLSV1_1; + break; + + case SslProtocols_TLSv12: + securityMethod = SLNETSOCK_SEC_METHOD_TLSV1_2; + break; + + default: + // shouldn't reach here! + goto error; + } + + status = SlNetSock_secAttribSet(context->SecurityAttributes, SLNETSOCK_SEC_ATTRIB_METHOD, (void *)&(securityMethod), sizeof(securityMethod)); + if (status < 0) + { + goto error; + } + + // enable all cyphers (this is Simple Link default, so nothing to do about this) + + // CA root certs are taken from Simple Link trusted root-certificate catalog, so nothing to do here + + // // parse "own" certificate if passed + // if(certificate != NULL && certLength > 0) + // { + // // TODO + // // this isn't required for client authentication + + // // mbedtls_x509_crt_init( &clicert ); + + // // ///////////////////////////////////////////////////////////////////////////////////////////////// + // // // developer notes: // + // // // this call parses certificates in both string and binary formats // + // // // when the formart is a string it has to include the terminator otherwise the parse will fail // + // // ///////////////////////////////////////////////////////////////////////////////////////////////// + // // if(mbedtls_x509_crt_parse( &clicert, (const unsigned char*)certificate, certLength ) != 0) + // // { + // // // x509_crt_parse_failed + // // goto error; + // // } + + // // if( mbedtls_pk_parse_key( &pkey, (const unsigned char *) mbedtls_test_cli_key, mbedtls_test_cli_key_len, NULL, 0 ) != 0) + // // { + // // // failed parsing the + // // } + + // // if( mbedtls_tls_conf_own_cert( &conf, &clicert, &pkey ) != 0 ) + // // { + // // // configuring own certificate failed + // // goto error; + // // } + // } + + // set certificate verification + // the current options provided by Simple Link API are only verify or don't verify + if((SslVerification)sslVerify == SslVerification_NoVerification) + { + status = SlNetSock_secAttribSet(context->SecurityAttributes, SLNETSOCK_SEC_ATTRIB_DISABLE_CERT_STORE, (void *)&dummyVal, sizeof(dummyVal)); + if (status < 0) + { + goto error; + } + } + + ////////////////////////////////////// + + // the equivalent of SSL contex in Simple Link is the Security Attribute that we've been building + g_SSL_Driver.ContextArray[sslContexIndex].Context = context; + g_SSL_Driver.ContextCount++; + + contextHandle = sslContexIndex; + + return true; + + error: + + // check for any memory allocation that needs to be freed before exiting + if(context != NULL) + { + platform_free(context); + } + + if(context->SecurityAttributes != NULL) + { + SlNetSock_secAttribDelete(context->SecurityAttributes); + } + + return false; +} + +bool ssl_exit_context_internal(int contextHandle) +{ + SlSSL_Context* context = NULL; + + // Check contextHandle range + if((contextHandle >= (int)ARRAYSIZE(g_SSL_Driver.ContextArray)) || (contextHandle < 0) || (g_SSL_Driver.ContextArray[contextHandle].Context == NULL)) + { + return false; + } + + context = (SlSSL_Context*)g_SSL_Driver.ContextArray[contextHandle].Context; + if (context == NULL) + { + return false; + } + + SlNetSock_secAttribDelete(context->SecurityAttributes); + + platform_free(context); + + memset(&g_SSL_Driver.ContextArray[contextHandle], 0, sizeof(g_SSL_Driver.ContextArray[contextHandle])); + + g_SSL_Driver.ContextCount --; + + return true; +} + +int ssl_connect_internal( + int sd, + const char* szTargetHost, + int contextHandle) +{ + SlSSL_Context* context; + int32_t status; + struct timespec ts; + struct tm rtcTime; + + // Check contextHandle range + if((contextHandle >= (int)ARRAYSIZE(g_SSL_Driver.ContextArray)) || (contextHandle < 0)) + { + return SOCK_SOCKET_ERROR; + } + + // Retrieve SSL context from g_SSL_Driver + // sd should already have been created + // Now do the SSL negotiation + context = (SlSSL_Context*)g_SSL_Driver.ContextArray[contextHandle].Context; + if (context == NULL) + { + return SOCK_SOCKET_ERROR; + } + + // set socket in network context + context->SocketFd = sd; + + if(szTargetHost != NULL && szTargetHost[0] != 0) + { + status = SlNetSock_secAttribSet( + context->SecurityAttributes, + SLNETSOCK_SEC_ATTRIB_DOMAIN_NAME, + (void *)szTargetHost, + hal_strlen_s(szTargetHost)); + if (status < 0) + { + // hostname_failed + return status; + } + } + + // in order to validate certificates, the device has to have it's date/time set + // get current time + clock_gettime(CLOCK_REALTIME, &ts); + + // need to convert between structs + ClockSync_convert(ts.tv_sec, &rtcTime); + + SlDateTime_t dateTime; + dateTime.tm_sec = rtcTime.tm_sec; + dateTime.tm_min = rtcTime.tm_min; + dateTime.tm_hour = rtcTime.tm_hour; + dateTime.tm_day = rtcTime.tm_mday; + // tm_mon starts month 0 + dateTime.tm_mon = rtcTime.tm_mon + 1; + // tm_year starts in 1970 + dateTime.tm_year = rtcTime.tm_year + 1970; + + sl_DeviceSet( + SL_DEVICE_GENERAL, + SL_DEVICE_GENERAL_DATE_TIME, + sizeof(SlDateTime_t), + (uint8_t *)(&dateTime)); + + // DON'T setup socket for blocking operation + + // start security context on socket + status = SlNetSock_startSec( + context->SocketFd, + context->SecurityAttributes, context->IsServer ? + (SLNETSOCK_SEC_START_SECURITY_SESSION_ONLY | SLNETSOCK_SEC_IS_SERVER) : + (SLNETSOCK_SEC_START_SECURITY_SESSION_ONLY | SLNETSOCK_SEC_BIND_CONTEXT_ONLY)); + + if ( (status < 0) && + (status != SLNETERR_ESEC_UNKNOWN_ROOT_CA) && + (status != SLNETERR_ESEC_HAND_SHAKE_TIMED_OUT) && + (status != SLNETERR_ESEC_DATE_ERROR) && + (status != SLNETERR_ESEC_SNO_VERIFY)) + { + return status; + } + + // got here, handshake is completed + + return 0; +} + +int ssl_pending_internal( int sd ) +{ + // Simple Link doesn't have an API to check for pending data + // just return 0 + return 0; +} + +int ssl_write_internal( + int sd, + const char* data, + size_t req_len) +{ + int32_t status; + + socketErrorCode = SlNetSock_send( + sd, + (const void*)data, + req_len, + 0); + + // anything below 0 is considered an error, so we have to report that no bytes were sent + if (socketErrorCode < 0) + { + return 0; + } + + return req_len; +} + +int ssl_read_internal( + int sd, + char* data, + size_t size ) +{ + socketErrorCode = SlNetSock_recv( + sd, + (unsigned char *)(data), + size, + 0); + + return socketErrorCode; +} + +int ssl_close_socket_internal( int sd ) +{ + // Simple Link takes care of everything for us, just call close socket + SOCK_close( sd ); + + return true; +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/common/syscalls.c b/source/native/nf-interpreter/targets/TI-SimpleLink/common/syscalls.c new file mode 100644 index 00000000..e56deb95 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/common/syscalls.c @@ -0,0 +1,45 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +// these are stubs to keep the linker happy when these are pulled in + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * _gettimeofday primitive (Stub function) + * */ + +/* + * Structure used in select() call, taken from the BSD file sys/time.h. + */ +struct timeval { + long tv_sec; /* seconds */ + long tv_usec; /* and microseconds */ +}; + +struct timezone { + int tz_minuteswest; /* minutes west of Greenwich */ + int tz_dsttime; /* type of dst correction */ +}; + +int _gettimeofday (struct timeval * tp, struct timezone * tzp) +{ + (void)tp; + + /* Return fixed data for the timezone. */ + if (tzp) + { + tzp->tz_minuteswest = 0; + tzp->tz_dsttime = 0; + } + + return 0; +} + +#ifdef __cplusplus +} +#endif diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp new file mode 100644 index 00000000..15808c7e --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/common/targetHAL_ConfigurationManager_CC32xx.cpp @@ -0,0 +1,512 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +#include +#include + +typedef struct +{ + SlFileAttributes_t attribute; + char fileName[SL_FS_MAX_FILE_NAME_LENGTH]; +}slGetfileList_t; + +// This configuration manager implementation is valid for CC32xx devices. +// Because everything that is meant to be stored in the configure block is handled by the SimpleLink +// persistent storage, this code is either empty or acts as a proxy to the SimpleLink API + +// network configuration blocks are stored as files in file storage +void* ConfigurationManagerCC32xx_FindNetworkConfigurationBlocks() +{ + int32_t ret = 1; + int32_t retGetFileList = 1; + slGetfileList_t* fileList; + int32_t index = -1; + + int32_t i; + uint32_t fileCount = 0; + + // allocate memory for file list buffer + fileList = (slGetfileList_t*)platform_malloc(sizeof(slGetfileList_t) * NETWORK_CONFIG_MAX_COUNT); + + // check succesfull malloc + if (fileList == NULL) + { + return NULL; + } + + // clear memory + memset(fileList, 0x0, sizeof(sizeof(SlFileAttributes_t) * NETWORK_CONFIG_MAX_COUNT)); + + // first pass: find out how many files of this type we have + while(retGetFileList > 0) + { + retGetFileList = sl_FsGetFileList( &index, NETWORK_CONFIG_MAX_COUNT, + (uint8_t)(SL_FS_MAX_FILE_NAME_LENGTH + sizeof(SlFileAttributes_t)), + (unsigned char*)fileList, SL_FS_GET_FILE_ATTRIBUTES); + if (retGetFileList < 0) + { + // error getting file list, or no more files + break; + } + + for (i = 0; i < retGetFileList; i++) + { + // check file name + if(memcmp(fileList[i].fileName, NETWORK_CONFIG_FILE_NAME, sizeof(NETWORK_CONFIG_FILE_NAME)) == 0) + { + fileCount++; + } + } + } + + // allocate config struct + HAL_CONFIGURATION_NETWORK *networkConfigs = (HAL_CONFIGURATION_NETWORK *)platform_malloc(offsetof(HAL_CONFIGURATION_NETWORK, Configs) + fileCount * sizeof(networkConfigs->Configs[0])); + // set collection count + networkConfigs->Count = fileCount; + + // clear memory for file list + platform_free(fileList); + + return networkConfigs; +} + +// wireless profiles are stored as SimpleLink WLAN profile +void* ConfigurationManagerCC32xx_FindNetworkWireless80211ConfigurationBlocks() +{ + int16_t index, status; + signed char name[32]; + int16_t nameLength; + unsigned char macAddr[6]; + SlWlanSecParams_t secParams; + SlWlanGetSecParamsExt_t secExtParams; + uint32_t priority; + uint16_t profileCount = 0; + + // first pass: find out how many profiles are stored + for(index = 0; index < SL_WLAN_MAX_PROFILES; index++) + { + status = sl_WlanProfileGet(index, name, &nameLength, macAddr, &secParams, &secExtParams, &priority); + if( status >= 0) + { + profileCount++; + } + } + + // allocate config struct + HAL_CONFIGURATION_NETWORK_WIRELESS80211 *networkWirelessConfigs = (HAL_CONFIGURATION_NETWORK_WIRELESS80211 *)platform_malloc(offsetof(HAL_CONFIGURATION_NETWORK_WIRELESS80211, Configs) + profileCount * sizeof(networkWirelessConfigs->Configs[0])); + + // set collection count + networkWirelessConfigs->Count = profileCount; + + return networkWirelessConfigs; +} + +// initialization of configuration manager +void ConfigurationManager_Initialize() +{ + memset( (void*)&g_TargetConfiguration, 0, sizeof(g_TargetConfiguration)); + + // enumerate the blocks + ConfigurationManager_EnumerateConfigurationBlocks(); +}; + +// Enumerates the configuration blocks from the configuration flash sector +void ConfigurationManager_EnumerateConfigurationBlocks() +{ + // find network configuration blocks + HAL_CONFIGURATION_NETWORK* networkConfigs = (HAL_CONFIGURATION_NETWORK*)ConfigurationManagerCC32xx_FindNetworkConfigurationBlocks(); + + // check network configs count + if(networkConfigs->Count == 0) + { + // there is no network config block available, get a default + HAL_Configuration_NetworkInterface* networkConfig = (HAL_Configuration_NetworkInterface*)platform_malloc(sizeof(HAL_Configuration_NetworkInterface)); + if(InitialiseNetworkDefaultConfig(networkConfig, 0)) + { + // config block created, store it + ConfigurationManager_StoreConfigurationBlock(networkConfig, DeviceConfigurationOption_Network, 0, sizeof(HAL_Configuration_NetworkInterface), 0); + + // have to enumerate again to pick it up + networkConfigs = (HAL_CONFIGURATION_NETWORK*)ConfigurationManagerCC32xx_FindNetworkConfigurationBlocks(); + } + + platform_free(networkConfig); + } + + // find wireless 80211 network configuration blocks + HAL_CONFIGURATION_NETWORK_WIRELESS80211* networkWirelessConfigs = (HAL_CONFIGURATION_NETWORK_WIRELESS80211*)ConfigurationManagerCC32xx_FindNetworkWireless80211ConfigurationBlocks(); + + // // find X509 certificate blocks + // HAL_CONFIGURATION_X509_CERTIFICATE* certificateStore = (HAL_CONFIGURATION_X509_CERTIFICATE*)ConfigurationManager_FindX509CertificateConfigurationBlocks((uint32_t)&__nanoConfig_start__, (uint32_t)&__nanoConfig_end__); + + // alloc memory for g_TargetConfiguration + // because this is a struct of structs that use flexible members the memory has to be allocated from the heap + // the malloc size for each struct is computed separately + uint32_t sizeOfNetworkInterfaceConfigs = offsetof(HAL_CONFIGURATION_NETWORK, Configs) + networkConfigs->Count * sizeof(networkConfigs->Configs[0]); + uint32_t sizeOfWireless80211Configs = offsetof(HAL_CONFIGURATION_NETWORK_WIRELESS80211, Configs) + networkWirelessConfigs->Count * sizeof(networkWirelessConfigs->Configs[0]); + // uint32_t sizeOfX509CertificateStore = offsetof(HAL_CONFIGURATION_X509_CERTIFICATE, Certificates) + certificateStore->Count * sizeof(certificateStore->Certificates[0]); + + g_TargetConfiguration.NetworkInterfaceConfigs = (HAL_CONFIGURATION_NETWORK*)platform_malloc(sizeOfNetworkInterfaceConfigs); + g_TargetConfiguration.Wireless80211Configs = (HAL_CONFIGURATION_NETWORK_WIRELESS80211*)platform_malloc(sizeOfWireless80211Configs); + // g_TargetConfiguration.CertificateStore = (HAL_CONFIGURATION_X509_CERTIFICATE*)platform_malloc(sizeOfX509CertificateStore); + + // copy structs to g_TargetConfiguration + memcpy((HAL_CONFIGURATION_NETWORK*)g_TargetConfiguration.NetworkInterfaceConfigs, networkConfigs, sizeOfNetworkInterfaceConfigs); + memcpy((HAL_CONFIGURATION_NETWORK_WIRELESS80211*)g_TargetConfiguration.Wireless80211Configs, networkWirelessConfigs, sizeOfWireless80211Configs); + // memcpy((HAL_CONFIGURATION_X509_CERTIFICATE*)g_TargetConfiguration.CertificateStore, certificateStore, sizeOfX509CertificateStore); + + // now free the memory of the original structs + platform_free(networkConfigs); + platform_free(networkWirelessConfigs); + // platform_free(certificateStore); +} + +EncryptionType GetEncryption(SlWlanSecParams_t secParams) +{ + switch (secParams.Type) + { + case SL_WLAN_SEC_TYPE_WEP: + return EncryptionType_WEP; + + // deprecated + // case SL_WLAN_SEC_TYPE_WPA: + // return EncryptionType_WPA; + + case SL_WLAN_SEC_TYPE_WPA_WPA2: + return EncryptionType_WPA2; + + default: + return EncryptionType_None; + } +} + +AuthenticationType GetAuthentication(SlWlanSecParams_t secParams) +{ + switch (secParams.Type) + { + case SL_WLAN_SEC_TYPE_OPEN: + return AuthenticationType_Open; + + case SL_WLAN_SEC_TYPE_WEP: + return AuthenticationType_WEP; + + // deprecated + // case SL_WLAN_SEC_TYPE_WPA: + // return AuthenticationType_WPA; + + case SL_WLAN_SEC_TYPE_WPA_WPA2: + return AuthenticationType_WPA2; + + case SL_WLAN_SEC_TYPE_WEP_SHARED: + return AuthenticationType_Shared; + + default: + return AuthenticationType_None; + } +} + +// Gets the network configuration block from the configuration flash sector +bool ConfigurationManager_GetConfigurationBlock(void* configurationBlock, DeviceConfigurationOption configuration, uint32_t configurationIndex) +{ + unsigned char* fileName = NULL; + + int32_t fileHandle; + uint32_t token = 0; + int32_t retVal; + SlWlanSecParams_t secParams; + int16_t dummyNameLen; + uint8_t dummyMAC[SL_MAC_ADDR_LEN]; + uint32_t dummyPriority; + + HAL_Configuration_Wireless80211* wirelessConfigBlock = NULL; + + + // validate if the requested block exists + // Count has to be non zero + // requested Index has to exist (array index starts at zero, so need to add one) + if(configuration == DeviceConfigurationOption_Network) + { + if( g_TargetConfiguration.NetworkInterfaceConfigs->Count == 0 || + (configurationIndex + 1) > g_TargetConfiguration.NetworkInterfaceConfigs->Count) + { + // the requested config block is beyond the available count + return false; + } + } + else if(configuration == DeviceConfigurationOption_Wireless80211Network) + { + if(g_TargetConfiguration.Wireless80211Configs->Count == 0 || + (configurationIndex + 1) > g_TargetConfiguration.Wireless80211Configs->Count) + { + return false; + } + } + else if(configuration == DeviceConfigurationOption_X509CaRootBundle) + { + if(g_TargetConfiguration.CertificateStore->Count == 0 || + (configurationIndex + 1) > g_TargetConfiguration.CertificateStore->Count) + { + return false; + } + + // // get block address + // blockAddress = (uint8_t*)g_TargetConfiguration.CertificateStore->Certificates[configurationIndex]; + + // // set block size + // // because X509 certificate has a variable length need to compute the block size in two steps + // sizeOfBlock = offsetof(HAL_Configuration_X509CaRootBundle, Certificate); + // sizeOfBlock += ((HAL_Configuration_X509CaRootBundle*)blockAddress)->CertificateSize; + } + + if(configuration == DeviceConfigurationOption_Network) + { + // network config blocks are stored as files + + // compose file name + fileName = (unsigned char*)platform_malloc(sizeof(NETWORK_CONFIG_FILE_NAME)); + memcpy(fileName, NETWORK_CONFIG_FILE_NAME, sizeof(NETWORK_CONFIG_FILE_NAME)); + // insert index number at position N as char + fileName[NETWORK_CONFIG_FILE_INDEX_POSITION] = '0' + configurationIndex; + + fileHandle = sl_FsOpen( fileName, + SL_FS_READ, + (uint32_t *)&token); + + // on error there is no file handle, rather a negative error code + if(fileHandle > 0) + { + retVal = sl_FsRead(fileHandle, 0, (unsigned char*)configurationBlock, sizeof(HAL_Configuration_NetworkInterface)); + + // on success the return value is the amount of bytes written + if(retVal == sizeof(HAL_Configuration_NetworkInterface)) + { + retVal = sl_FsClose(fileHandle, 0, 0, 0); + + if( retVal < 0 ) + { + // error closing file, API ceremony suggests calling "abort" operation + uint8_t signature = 'A'; + sl_FsClose(fileHandle, 0, &signature, 1); + } + } + } + + if(fileName != NULL) + { + platform_free(fileName); + } + + // done! + return true; + } + else if(configuration == DeviceConfigurationOption_Wireless80211Network) + { + wirelessConfigBlock = (HAL_Configuration_Wireless80211*)configurationBlock; + + // make sure the config block marker is set + memcpy(configurationBlock, c_MARKER_CONFIGURATION_WIRELESS80211_V1, sizeof(c_MARKER_CONFIGURATION_WIRELESS80211_V1)); + + // get profile from SimpleLink + retVal = sl_WlanProfileGet(configurationIndex, (signed char *)wirelessConfigBlock->Ssid, &dummyNameLen, &dummyMAC[0], &secParams, NULL, &dummyPriority); + if(retVal == SL_ERROR_WLAN_GET_PROFILE_INVALID_INDEX) + { + return false; + } + + // fill struct fields + wirelessConfigBlock->Id = configurationIndex; + wirelessConfigBlock->Authentication = GetAuthentication(secParams); + wirelessConfigBlock->Encryption = GetEncryption(secParams); + + // password is hidden, NULL the string + memset(wirelessConfigBlock->Password, 0, sizeof(wirelessConfigBlock->Password)); + //wirelessConfigBlock->Radio + + + // done + return true; + } + + return false; +} + +uint8_t GetSecurityType(AuthenticationType authentication) +{ + switch (authentication) + { + case AuthenticationType_Open: + return SL_WLAN_SEC_TYPE_OPEN; + + case AuthenticationType_WEP: + return SL_WLAN_SEC_TYPE_WEP; + + case AuthenticationType_WPA: + case AuthenticationType_WPA2: + return SL_WLAN_SEC_TYPE_WPA_WPA2; + + case AuthenticationType_Shared: + return SL_WLAN_SEC_TYPE_WEP_SHARED; + + default: + return SL_WLAN_SEC_TYPE_OPEN; + } +} + +// Stores the configuration block to the file system +bool ConfigurationManager_StoreConfigurationBlock(void* configurationBlock, DeviceConfigurationOption configuration, uint32_t configurationIndex, uint32_t blockSize, uint32_t offset) +{ + bool requiresEnumeration = false; + bool success = false; + + unsigned char* fileName = NULL; + + int32_t fileHandle; + uint32_t token = 0; + int32_t retVal; + SlWlanSecParams_t secParams; + + if(configuration == DeviceConfigurationOption_Network) + { + // network config blocks are stored as files + + // compose file name + fileName = (unsigned char*)platform_malloc(sizeof(NETWORK_CONFIG_FILE_NAME)); + memcpy(fileName, NETWORK_CONFIG_FILE_NAME, sizeof(NETWORK_CONFIG_FILE_NAME)); + // insert index number at position N as char + fileName[NETWORK_CONFIG_FILE_INDEX_POSITION] = '0' + configurationIndex; + + fileHandle = sl_FsOpen( fileName, + SL_FS_CREATE | SL_FS_OVERWRITE | + SL_FS_CREATE_MAX_SIZE(sizeof(HAL_Configuration_NetworkInterface)) | + SL_FS_CREATE_PUBLIC_WRITE | SL_FS_CREATE_NOSIGNATURE, + (uint32_t *)&token); + + // on error there is no file handle, rather a negative error code + if(fileHandle > 0) + { + // make sure the config block marker is set + memcpy(configurationBlock, c_MARKER_CONFIGURATION_NETWORK_V1, sizeof(c_MARKER_CONFIGURATION_NETWORK_V1)); + + retVal = sl_FsWrite(fileHandle, 0, (unsigned char*)configurationBlock, sizeof(HAL_Configuration_NetworkInterface)); + + // on success the return value is the amount of bytes written + if(retVal == sizeof(HAL_Configuration_NetworkInterface)) + { + retVal = sl_FsClose(fileHandle, 0, 0, 0); + + if( retVal < 0 ) + { + // error closing file, API ceremony suggests calling "abort" operation + uint8_t signature = 'A'; + sl_FsClose(fileHandle, 0, &signature, 1); + } + else + { + // configuration stored + success = true; + requiresEnumeration = true; + } + } + } + + if(fileName != NULL) + { + platform_free(fileName); + } + } + else if(configuration == DeviceConfigurationOption_Wireless80211Network) + { + HAL_Configuration_Wireless80211* wirelessConfigBlock = (HAL_Configuration_Wireless80211*)configurationBlock; + + secParams.Type = GetSecurityType(wirelessConfigBlock->Authentication); + secParams.Key = (signed char *)wirelessConfigBlock->Password; + secParams.KeyLen = hal_strlen_s((const char *)secParams.Key); + + // add profile to SimpleLink + // TODO - default priority is 0 + retVal = sl_WlanProfileAdd((const signed char *)wirelessConfigBlock->Ssid, hal_strlen_s((const char *)(wirelessConfigBlock->Ssid)), NULL, &secParams, NULL, 0, 0); + if(retVal < 0) + { + return false; + } + + // done + success = true; + requiresEnumeration = true; + } + else if(configuration == DeviceConfigurationOption_X509CaRootBundle) + { + // CA root certificate bundle is stored as a file /sys/certstore.lst + // currently we don't support updating this + success = false; + } + + if(success == true && requiresEnumeration) + { + // free the current allocation(s) + platform_free(g_TargetConfiguration.NetworkInterfaceConfigs); + platform_free(g_TargetConfiguration.Wireless80211Configs); + platform_free(g_TargetConfiguration.CertificateStore); + + // perform enumeration of configuration blocks + ConfigurationManager_EnumerateConfigurationBlocks(); + } + + return success; +} + +// Updates a configuration block +bool ConfigurationManager_UpdateConfigurationBlock(void* configurationBlock, DeviceConfigurationOption configuration, uint32_t configurationIndex) +{ + // CC32xx stores the config blocks on the file system so we don't care about sizes + + switch(configuration) + { + case DeviceConfigurationOption_Network: + case DeviceConfigurationOption_Wireless80211Network: + return ConfigurationManager_StoreConfigurationBlock(configurationBlock, configuration, configurationIndex, 0, 0); + + // this configuration option is not supported + case DeviceConfigurationOption_X509CaRootBundle: + default: + // shouldn't ever reach here + return FALSE; + } +} + +// Default initialisation for wireless config block +void InitialiseWirelessDefaultConfig(HAL_Configuration_Wireless80211 * pconfig, uint32_t configurationIndex) +{ + (void)pconfig; + (void)configurationIndex; + + // TODO +} + +// Default initialisation for Network interface config blocks +bool InitialiseNetworkDefaultConfig(HAL_Configuration_NetworkInterface * pconfig, uint32_t configurationIndex) +{ + (void)configurationIndex; + + uint16_t macAddressLen = SL_MAC_ADDR_LEN; + + memset(pconfig, 0, sizeof(HAL_Configuration_NetworkInterface)); + + // make sure the config block marker is set + memcpy(pconfig->Marker, c_MARKER_CONFIGURATION_NETWORK_V1, sizeof(c_MARKER_CONFIGURATION_NETWORK_V1)); + + pconfig->InterfaceType = NetworkInterfaceType_Wireless80211; + pconfig->StartupAddressMode = AddressMode_DHCP; + pconfig->AutomaticDNS = 1; + pconfig->SpecificConfigId = 0; + + sl_NetCfgGet(SL_NETCFG_MAC_ADDRESS_GET, 0, &macAddressLen, pconfig->MacAddress); + + return true; +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/CLR_Startup_Thread.c b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/CLR_Startup_Thread.c new file mode 100644 index 00000000..fa09cebf --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/CLR_Startup_Thread.c @@ -0,0 +1,19 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +void* CLRStartupThread(void* argument) +{ + CLR_SETTINGS* clrSettings = (CLR_SETTINGS*)argument; + + nanoHAL_Initialize_C(); + + ClrStartup(*clrSettings); + + // nothing to deinitialize or cleanup, so it's safe to return +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/CMakeLists.txt b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/CMakeLists.txt new file mode 100644 index 00000000..fbb86360 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/CMakeLists.txt @@ -0,0 +1,91 @@ +# +# Copyright (c) 2019 The nanoFramework project contributors +# See LICENSE file in the project root for full license information. +# + +include(NF_NativeAssemblies) + +# add header file with common target definitions +configure_file("${CMAKE_CURRENT_SOURCE_DIR}/target_platform.h.in" + "${CMAKE_CURRENT_BINARY_DIR}/target_platform.h" @ONLY) + +# append nanoHAL +list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL.cpp") + +# append target nanoCLR source files +list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_App_Interface.c) +list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES ${CMAKE_CURRENT_SOURCE_DIR}/WireProtocol_MonitorCommands.c) +list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/CLR_Startup_Thread.c") +list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetPAL.c") + +# append target HAL source files +list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Power.c") +list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Time.cpp") + +# append watchdog only if option is ON +# if(HAL_USE_WDG_OPTION) +# list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetHAL_Watchdog.c") +# endif() + +# append SNTP only if option is ON +if(NF_NETWORKING_SNTP) + list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetSimpleLinkCC32xx_Sntp.c") +endif() + +# append target PAL source files +list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetPAL_Events.cpp") +list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetPAL_Time.cpp") + +# append other CLR core files +list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/Memory.cpp") + +# append nanoCRT +list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoCRT.cpp") + +# append SimpleLink target specific files +if("${TARGET_SERIES}" STREQUAL "CC32xx") + list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetSimpleLinkCC32xx_Threads.c") + list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetSimpleLinkCC32xx_LinkLocalTask.c") + list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetSimpleLinkCC32xx_ProvisioningTask.c") +endif() + +# append files from Runtime.Native +# list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/nanoFramework.Runtime.Native/nf_rt_native_nanoFramework_Runtime_Native_Rtc.cpp") + +# append TRNG only if option is ON +if(USE_RNG) + + # # append random implementation for all series, except F0 + # if( ${TARGET_SERIES} STREQUAL "STM32L0xx" OR + # ${TARGET_SERIES} STREQUAL "STM32F4xx" OR + # ${TARGET_SERIES} STREQUAL "STM32F7xx" OR + # ${TARGET_SERIES} STREQUAL "STM32H7xx") + + # list(APPEND TARGET_TI_SimpleLink_NANOCLR_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/targetRandom.cpp") + + # else() + # # this series doesn't feature hardware TRNG, report + # message(ERROR "This CPU doesn't have a Random Number Generation. Please change USE_RNG option to OFF.") + # endif() + +endif() + +# add native assemblies +ParseNativeAssemblies() + +# make var global +set(TARGET_TI_SimpleLink_NANOCLR_SOURCES ${TARGET_TI_SimpleLink_NANOCLR_SOURCES} CACHE INTERNAL "make global") + +# append target ChibiOS nanoCLR include directory +list(APPEND TARGET_TI_SimpleLink_NANOCLR_INCLUDE_DIRS ${CMAKE_CURRENT_SOURCE_DIR}) +list(APPEND TARGET_TI_SimpleLink_NANOCLR_INCLUDE_DIRS ${CMAKE_CURRENT_BINARY_DIR}) +list(APPEND TARGET_TI_SimpleLink_NANOCLR_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Core) + +# append PAL include directory +list(APPEND TARGET_TI_SimpleLink_NANOCLR_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/PAL/Include) + +# append Runtime.Native include directory +list(APPEND TARGET_TI_SimpleLink_NANOCLR_INCLUDE_DIRS ${PROJECT_SOURCE_DIR}/src/CLR/Runtime.Native) + +# make var global +set(TARGET_TI_SimpleLink_NANOCLR_INCLUDE_DIRS ${TARGET_TI_SimpleLink_NANOCLR_INCLUDE_DIRS} CACHE INTERNAL "make global") diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Memory.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Memory.cpp new file mode 100644 index 00000000..e488b377 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Memory.cpp @@ -0,0 +1,30 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include + +// void HeapLocation(unsigned char*& baseAddress, unsigned int& sizeInBytes) +// { +// NATIVE_PROFILE_PAL_HEAP(); + +// baseAddress = (unsigned char*) &HeapBegin; +// sizeInBytes = (unsigned int)((size_t)&HeapEnd - (size_t)&HeapBegin); +// } + +// Define an area for the CLR managed heap +#if !defined(MANAGED_HEAP_SIZE) +#define MANAGED_HEAP_SIZE (64*1024) +#endif + +uint32_t managedHeap[MANAGED_HEAP_SIZE/ sizeof(uint32_t)]; + +void HeapLocation(unsigned char*& baseAddress, unsigned int& sizeInBytes) +{ + NATIVE_PROFILE_PAL_HEAP(); + + baseAddress = (unsigned char*)&managedHeap; + sizeInBytes = sizeof(managedHeap); +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcChannel.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcChannel.cpp new file mode 100644 index 00000000..85b09785 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcChannel.cpp @@ -0,0 +1,74 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_adc_native_target.h" + +// // this has to be an array because ChibiOS ADC API expects that +// static adcsample_t sampleBuffer[1 * 1]; + +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-function" +#endif + +// // not used, just left here if needed for debugging purposes +// static void adcerrorcallback(ADCDriver *adcp, adcerror_t err) +// { +// (void)adcp; +// (void)err; +// } + +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcChannel::NativeReadValue___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Get channel from _channelNumber field + int channelNumber = pThis[FIELD___channelNumber].NumericByRef().s4; + + uint16_t adcValue0; + uint32_t adcValue0MicroVolt; + + ADC_Params params; + ADC_Params_init(¶ms); + ADC_Handle adcHandler = ADC_open(channelNumber, ¶ms); FAULT_ON_NULL(adcHandler); + + int_fast16_t res = ADC_convert(adcHandler, &adcValue0); + + if (res == ADC_STATUS_SUCCESS) + { + adcValue0MicroVolt = ADC_convertRawToMicroVolts(adcHandler, adcValue0); + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + + + ADC_close(adcHandler); + + stack.SetResult_I4(adcValue0MicroVolt); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcChannel::NativeDisposeChannel___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + + // left empty on purpose, nothing to do here + + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcController.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcController.cpp new file mode 100644 index 00000000..de4b4c17 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_Windows_Devices_Adc_AdcController.cpp @@ -0,0 +1,124 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_adc_native_target.h" + +extern const uint_least8_t ADC_count; + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeOpenChannel___VOID__I4( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + + // left empty on purpose, nothing to do here + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeGetChannelCount___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + int channelCount; + + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + int controllerId = pThis[ FIELD___controllerId ].NumericByRefConst().s4; + + switch(controllerId) + { + case 1: + channelCount = ADC_count; + break; + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + // Return value to the managed application + stack.SetResult_I4(channelCount); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeGetMaxValue___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // Currently fixed at 12 bit so return 4095 = ((2^12) - 1) + stack.SetResult_I4(4095); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeGetMinValue___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + stack.SetResult_I4(0); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeIsChannelModeSupported___BOOLEAN__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + int mode = stack.Arg1().NumericByRef().s4; + + // Only support Single ended mode for now + stack.SetResult_Boolean( (mode == (int)AdcChannelMode::SingleEnded) ) ; + } + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeGetResolutionInBits___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // Fixed at 12 bit + stack.SetResult_I4(12); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + int controllerId; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get pointer to _controllerId field in AdcController + controllerId = pThis[FIELD___controllerId].NumericByRef().s4; + + switch(controllerId) + { + case 1: + ADC_init(); + break; + + default: + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_adc_native_Windows_Devices_Adc_AdcController::GetDeviceSelector___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // because the caller is expecting a result to be returned + // we need set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + stack.SetResult_String("ADC1"); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_target.h b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_target.h new file mode 100644 index 00000000..6aaa808f --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Adc/win_dev_adc_native_target.h @@ -0,0 +1,14 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#ifndef _WIN_DEV_ADC_NATIVE_TARGET_H_ +#define _WIN_DEV_ADC_NATIVE_TARGET_H_ + +#include "Board.h" +#include +#include + +#endif //_WIN_DEV_ADC_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter.cpp new file mode 100644 index 00000000..87c7fcd4 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter.cpp @@ -0,0 +1,86 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_gpio_native.h" + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter::NativeInit___VOID(CLR_RT_StackFrame& stack) +{ + (void)stack; + + NANOCLR_HEADER(); + { + //CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + //int16_t pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + //bool InputMode = (bool)pThis[FIELD___inputMode].NumericByRefConst().u1; + + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter::NativeRead___U8__BOOLEAN(CLR_RT_StackFrame& stack) +{ + (void)stack; + + NANOCLR_HEADER(); + { + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter::NativeStart___VOID(CLR_RT_StackFrame& stack) +{ + (void)stack; + + NANOCLR_HEADER(); + { + //CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + //int pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + + //GpioChangePolarity polarity = (GpioChangePolarity)pThis[ FIELD___Polarity ].NumericByRefConst().s4; + + + // TODO + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter::NativeStop___VOID(CLR_RT_StackFrame& stack) +{ + (void)stack; + + NANOCLR_HEADER(); + { + //CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + //int pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioChangeCounter::NativeDispose___VOID(CLR_RT_StackFrame& stack) +{ + (void)stack; + + NANOCLR_HEADER(); + { + //CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + //int pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + + } + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioController.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioController.cpp new file mode 100644 index 00000000..c1ed62f8 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioController.cpp @@ -0,0 +1,19 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#include "win_dev_gpio_native_target.h" + + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioController::get_PinCount___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // return count ot available GPIO pins + stack.SetResult_I4( 256 ); // Fixme: temporary arbitrary value + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioPin.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioPin.cpp new file mode 100644 index 00000000..e79db908 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioPin.cpp @@ -0,0 +1,418 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_gpio_native_target.h" +#include "nf_rt_events_native.h" + +#include + +// this array points to the GPIO managed object that has interrupt active +CLR_RT_HeapBlock* indexPinMapping[] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL }; + +// this array points to the active debounce timers +TimerHandle_t debounceTimerMapping[ARRAYSIZE_CONST_EXPR(indexPinMapping)]; + +// this arrays points to the last read value to be used by the debounce timers +uint_fast8_t lastReadValueMapping[ARRAYSIZE_CONST_EXPR(indexPinMapping)]; + +static void debounceTimer_Callback(TimerHandle_t xTimer) +{ + (void)xTimer; + + int16_t index; + + // loop through timers to find the index for this + for(index = 0; index < ARRAYSIZE_CONST_EXPR(indexPinMapping); index++) + { + if(debounceTimerMapping[index] == xTimer) + { + // found it! + + // get current value + uint_fast8_t currentValue = GPIO_read(index); + + // get last read value + uint_fast8_t lastRead = (uint_fast8_t) pvTimerGetTimerID( xTimer ); + + if(lastRead == currentValue) + { + // value hasn't change during debounce interval so this is a valid change + + // get managed GPIO object + CLR_RT_HeapBlock* pThis = (CLR_RT_HeapBlock*)indexPinMapping[index]; + + // flag to determine if there are any callbacks registered in managed code + bool callbacksRegistered = (pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___callbacks ].Dereference() != NULL); + + // post a managed event with the current pin value, only if there is anyone listening otherwise don't bother + if(callbacksRegistered) + { + PostManagedEvent( EVENT_GPIO, 0, index, currentValue ); + } + } + + xTimerDelete(xTimer, 0); + } + } +} + +static void GpioEventCallback(uint_least8_t index) +{ + NATIVE_INTERRUPT_START + + CLR_RT_HeapBlock* pThis = indexPinMapping[index]; + + if(pThis == NULL) + { + // no Gpio pin here, leave now + NATIVE_INTERRUPT_END + return; + } + + // check if object has been disposed + if( pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + // object has been disposed, leave now + NATIVE_INTERRUPT_END + return; + } + + // check if there is a debounce time set + int64_t debounceTimeoutMilsec = (CLR_INT64_TEMP_CAST) pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___debounceTimeout ].NumericByRefConst().s8 / TIME_CONVERSION__TO_MILLISECONDS; + + // store current value + uint_fast8_t lastRead = GPIO_read(index); + + if(debounceTimeoutMilsec > 0) + { + // debounce set, need to handle it + + if(debounceTimerMapping[index] != NULL) + { + // there is a debounce timer already running so this change in pin value should be discarded + NATIVE_INTERRUPT_END + return; + } + + // setup timer + debounceTimerMapping[index] = xTimerCreate( NULL, (debounceTimeoutMilsec / portTICK_PERIOD_MS), pdFALSE, (void*)lastRead, debounceTimer_Callback); + xTimerStart(debounceTimerMapping[index], 0); + } + else + { + // read pin + pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___lastInputValue ].NumericByRef().s4 = lastRead; + + // flag to determine if there are any callbacks registered in managed code + bool callbacksRegistered = (pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___callbacks ].Dereference() != NULL); + + // post a managed event with the current pin reading, only if there is anyone listening otherwise don't bother + if(callbacksRegistered) + { + PostManagedEvent( EVENT_GPIO, 0, index, lastRead ); + } + } + + NATIVE_INTERRUPT_END +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::Read___WindowsDevicesGpioGpioPinValue( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // check if object has been disposed + if(pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + int32_t pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + + stack.SetResult_I4(GPIO_read(pinNumber)); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::Toggle___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // check if object has been disposed + if(pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + int32_t pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + + GpioPinDriveMode driveMode = (GpioPinDriveMode)pThis[ FIELD___driveMode ].NumericByRefConst().s4; + + // sanity check for drive mode set to output so we don't mess up writing to an input pin + if ((driveMode == GpioPinDriveMode_Output) || + (driveMode == GpioPinDriveMode_OutputOpenDrain) || + (driveMode == GpioPinDriveMode_OutputOpenDrainPullUp) || + (driveMode == GpioPinDriveMode_OutputOpenSourcePullDown)) + { + GPIO_toggle(pinNumber); + + // store new state + pThis[ FIELD___lastOutputValue ].NumericByRef().s4 = (GpioPinValue)(GpioPinValue_High ^ (GpioPinValue)pThis[ FIELD___lastOutputValue ].NumericByRef().s4); + } + + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::DisposeNative___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + int32_t pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + + // it's OK to do always this, no matter if interrupts are enabled or not + // disable interrupts + GPIO_disableInt(pinNumber); + + // clear assignment + indexPinMapping[pinNumber] = NULL; + + // set pin to input to save power + GPIO_setConfig(pinNumber, GPIO_CFG_IN_NOPULL | GPIO_CFG_IN_INT_NONE); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeIsDriveModeSupported___BOOLEAN__WindowsDevicesGpioGpioPinDriveMode( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + GpioPinDriveMode driveMode = (GpioPinDriveMode)stack.Arg1().NumericByRef().s4; + + bool driveModeSupported = false; + + // check if the requested drive mode is supported by SimpleLink + if ((driveMode == GpioPinDriveMode_Input) || + (driveMode == GpioPinDriveMode_InputPullDown) || + (driveMode == GpioPinDriveMode_InputPullUp) || + (driveMode == GpioPinDriveMode_Output) || + (driveMode == GpioPinDriveMode_OutputOpenDrain) || + (driveMode == GpioPinDriveMode_OutputOpenDrainPullUp) || + (driveMode == GpioPinDriveMode_OutputOpenSourcePullDown)) + { + driveModeSupported = true; + } + + // Return value to the managed application + stack.SetResult_Boolean( driveModeSupported ) ; + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeSetDriveMode___VOID__WindowsDevicesGpioGpioPinDriveMode( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + if(pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + // get pin number + int32_t pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + + // it's better cast this this to the appropriate enum + GpioPinDriveMode driveMode = (GpioPinDriveMode)stack.Arg1().NumericByRef().s4; + + // check if drive mode is input + bool driveModeIsInput = false; + + if( driveMode == GpioPinDriveMode_Input || + driveMode == GpioPinDriveMode_InputPullDown || + driveMode == GpioPinDriveMode_InputPullUp) + { + driveModeIsInput = true; + } + + // flag to signal that interrupts need to be setup + bool setupInterrupt = false; + + // flag to determine if there are any callbacks registered in managed code + bool callbacksRegistered = (pThis[ FIELD___callbacks ].Dereference() != NULL); + + // disable interrupt as default + GPIO_disableInt(pinNumber); + + switch (driveMode) + { + case GpioPinDriveMode_Input: + GPIO_setConfig(pinNumber, GPIO_CFG_IN_NOPULL); + setupInterrupt = true; + break; + + case GpioPinDriveMode_InputPullDown: + GPIO_setConfig(pinNumber, GPIO_CFG_IN_PD); + setupInterrupt = true; + break; + + case GpioPinDriveMode_InputPullUp: + GPIO_setConfig(pinNumber, GPIO_CFG_IN_PU); + setupInterrupt = true; + break; + + case GpioPinDriveMode_Output: + GPIO_setConfig(pinNumber, GPIO_CFG_OUT_STD | GPIO_CFG_OUT_LOW); + break; + + case GpioPinDriveMode_OutputOpenDrain: + GPIO_setConfig(pinNumber, GPIO_CFG_OUT_OD_NOPULL); + break; + + case GpioPinDriveMode_OutputOpenDrainPullUp: + GPIO_setConfig(pinNumber, GPIO_CFG_OUT_OD_PU); + break; + + case GpioPinDriveMode_OutputOpenSourcePullDown: + GPIO_setConfig(pinNumber, GPIO_CFG_OUT_OD_PD); + break; + + default: + // all other modes are NOT supported + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // if drive mode is output, read the pad to update the managed field _lastOutputValue + if(!driveModeIsInput) + { + pThis[ FIELD___lastOutputValue ].NumericByRef().s4 = GPIO_read(pinNumber); + } + + if(callbacksRegistered && setupInterrupt) + { + // there are callbacks registered and... + // the drive mode is input so need to setup the interrupt + + // save pin + indexPinMapping[pinNumber] = pThis; + + // get current config + GPIO_PinConfig currentPinConfig; + GPIO_getConfig(pinNumber, ¤tPinConfig); + + // set interrupt on both edges + GPIO_setConfig(pinNumber, currentPinConfig | GPIO_CFG_IN_INT_BOTH_EDGES); + GPIO_setCallback(pinNumber, GpioEventCallback); + + GPIO_enableInt(pinNumber); + + // protect this from GC so that the callback is where it's supposed to + CLR_RT_ProtectFromGC gc( *pThis ); + } + else + { + // clear assignment + indexPinMapping[pinNumber] = NULL; + } + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeInit___BOOLEAN__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + int16_t pinNumber = stack.Arg1().NumericByRef().s4; + + // TODO is probably a good idea keep track of the used pins, so we can check that here + // TODO is probably a good idea to check if this pin exists + + // clear assignment, to make sure it's empty + indexPinMapping[pinNumber] = NULL; + + // Return value to the managed application + stack.SetResult_Boolean(true ); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeSetDebounceTimeout___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + + // nothing to do here as the debounce timeout is grabbed from the managed object when required + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::WriteNative___VOID__WindowsDevicesGpioGpioPinValue( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // check if object has been disposed + if(pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + int32_t pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + + GpioPinDriveMode driveMode = (GpioPinDriveMode)pThis[ FIELD___driveMode ].NumericByRefConst().s4; + + GpioPinValue state = (GpioPinValue)stack.Arg1().NumericByRef().s4; + + // sanity check for drive mode set to output so we don't mess up writing to an input pin + if ((driveMode == GpioPinDriveMode_Output) || + (driveMode == GpioPinDriveMode_OutputOpenDrain) || + (driveMode == GpioPinDriveMode_OutputOpenDrainPullUp) || + (driveMode == GpioPinDriveMode_OutputOpenSourcePullDown)) + { + GPIO_write(pinNumber, state); + + // store new state + pThis[ FIELD___lastOutputValue ].NumericByRef().s4 = state; + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeSetAlternateFunction___VOID__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // check if object has been disposed + if(pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + int32_t pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + + // get alternate function argument + int32_t alternateFunction = stack.Arg1().NumericByRef().s4; + + GPIO_setConfig(pinNumber, alternateFunction); + + } + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_target.h b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_target.h new file mode 100644 index 00000000..311d0569 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_target.h @@ -0,0 +1,22 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#ifndef _WIN_DEV_GPIO_NATIVE_TARGET_H_ +#define _WIN_DEV_GPIO_NATIVE_TARGET_H_ + +#include + +#include "rom.h" +#include "rom_map.h" +#include +#include +#include +#include +#include +#include + +#endif //_WIN_DEV_GPIO_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2C_I2cDevice.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2C_I2cDevice.cpp new file mode 100644 index 00000000..99ec20d4 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2C_I2cDevice.cpp @@ -0,0 +1,244 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "win_dev_i2c_native_target.h" + +typedef Library_win_dev_i2c_native_Windows_Devices_I2c_I2cConnectionSettings I2cConnectionSettings; + +///////////////////////////////////////////////////// +// I2C PAL strucs declared in win_dev_i2c_native.h // +///////////////////////////////////////////////////// +NF_PAL_I2C I2C1_PAL; + +void HostI2C_CallbackFxn(I2C_Handle handle, I2C_Transaction *transaction, bool transferStatus) +{ + NATIVE_INTERRUPT_START + + // fire event for I2C transaction complete + Events_Set(SYSTEM_EVENT_FLAG_I2C_MASTER); + + NATIVE_INTERRUPT_END +} + +HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + NF_PAL_I2C* palI2c = NULL; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the managed I2C connectionSettings object instance + CLR_RT_HeapBlock* pConfig = pThis[ FIELD___connectionSettings ].Dereference(); + + // get bus index + // this is coded with a multiplication, need to perform and int division to get the number + // see the comments in the I2cDevice() constructor in managed code for details + uint8_t busIndex = (uint8_t)(pThis[ FIELD___deviceId ].NumericByRef().s4 / 1000); + + // config GPIO pins used by the I2C peripheral + // init the PAL struct for this I2C bus and assign the respective driver + // all this occurs if not already done + // why do we need to check if this is already done? because several I2cDevice objects can be created associated to the same bus just using different addresses + switch (busIndex) + { + case 1: + if(I2C1_PAL.i2c == NULL) + { + palI2c = &I2C1_PAL; + } + break; + + default: + // this I2C bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // Create I2C for usage + I2C_Params_init(&palI2c->i2cParams); + palI2c->i2cParams.bitRate = (I2cBusSpeed)pConfig[ I2cConnectionSettings::FIELD___busSpeed ].NumericByRef().s4 == I2cBusSpeed_StandardMode ? I2C_100kHz : I2C_400kHz; + palI2c->i2cParams.transferMode = I2C_MODE_CALLBACK; + palI2c->i2cParams.transferCallbackFxn = HostI2C_CallbackFxn; + palI2c->i2c = I2C_open(Board_I2C0, &palI2c->i2cParams); FAULT_ON_NULL(palI2c->i2c); + palI2c->i2cTransaction.slaveAddress = (I2cBusSpeed)pConfig[ I2cConnectionSettings::FIELD___slaveAddress ].NumericByRef().s4; + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::NativeDispose___VOID__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + uint8_t busIndex; + NF_PAL_I2C* palI2c = NULL; + bool disposeController = false; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get disposeController + disposeController = (bool)stack.Arg0().NumericByRef().u1; + + if(disposeController) + { + // get bus index + // this is coded with a multiplication, need to perform and int division to get the number + // see the comments in the I2cDevice() constructor in managed code for details + busIndex = (uint8_t)(pThis[ FIELD___deviceId ].NumericByRef().s4 / 1000); + + // get the driver for the I2C bus + switch (busIndex) + { + case 1: + // deactivates the I2C peripheral + I2C_close(palI2c->i2c); + I2C1_PAL.i2c == NULL; + break; + + default: + // this I2C bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cDevice::NativeTransmit___WindowsDevicesI2cI2cTransferResult__SZARRAY_U1__SZARRAY_U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + uint8_t busIndex; + NF_PAL_I2C* palI2c = NULL; + + CLR_RT_HeapBlock hbTimeout; + CLR_INT64* timeout; + bool eventResult = true; + uint32_t estimatedDurationMiliseconds; + + CLR_RT_HeapBlock_Array* writeBuffer; + CLR_RT_HeapBlock_Array* readBuffer; + CLR_RT_HeapBlock* result; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // // get pointer to connection settings field + // CLR_RT_HeapBlock* connectionSettings = pThis[ FIELD___connectionSettings ].Dereference(); + + // get bus index + // this is coded with a multiplication, need to perform and int division to get the number + // see the comments in the I2cDevice() constructor in managed code for details + busIndex = (uint8_t)(pThis[ FIELD___deviceId ].NumericByRef().s4 / 1000); + + // get the driver for the I2C bus + switch (busIndex) + { + case 1 : + palI2c = &I2C1_PAL; + break; + default: + // the requested I2C bus is not valid + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + break; + } + + // dereference the write and read buffers from the arguments + writeBuffer = stack.Arg1().DereferenceArray(); + if (writeBuffer != NULL) + { + // get the size of the buffer by reading the number of elements in the CLR_RT_HeapBlock_Array + palI2c->i2cTransaction.writeCount = writeBuffer->m_numOfElements; + } + else + { + // nothing to write, have to zero this + palI2c->i2cTransaction.writeCount = 0; + } + + readBuffer = stack.Arg2().DereferenceArray(); + if (readBuffer != NULL) + { + // get the size of the buffer by reading the number of elements in the CLR_RT_HeapBlock_Array + palI2c->i2cTransaction.readCount = readBuffer->m_numOfElements; + } + else + { + // nothing to read, have to zero this + palI2c->i2cTransaction.readCount = 0; + } + + // set a timeout to an infinite timeout + // the catch is that the working thread MUST ALWAYS return at some point + // !! need to cast to CLR_INT64 otherwise it wont setup a proper timeout infinite + hbTimeout.SetInteger((CLR_INT64)-1); + + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks( hbTimeout, timeout )); + + // protect the buffers from GC so DMA can find them where they are supposed to be + CLR_RT_ProtectFromGC gcWriteBuffer( *writeBuffer ); + CLR_RT_ProtectFromGC gcReadBuffer( *readBuffer ); + + if (writeBuffer != NULL) + { + palI2c->i2cTransaction.writeBuf = (uint8_t*)writeBuffer->GetFirstElement(); + } + + if (readBuffer != NULL) + { + palI2c->i2cTransaction.readBuf = (uint8_t*)readBuffer->GetFirstElement(); + } + + // perform I2C transaction using driver's callback which will set the appropriate event on completion + if(stack.m_customState == 1) + { + I2C_transfer(palI2c->i2c, &palI2c->i2cTransaction); + + // bump custom state + stack.m_customState = 2; + } + + while(eventResult) + { + // non-blocking wait allowing other threads to run while we wait for the I2C transaction to complete + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_I2cMaster, eventResult )); + + if(eventResult) + { + // event occurred + + // create the return object (I2cTransferResult) + // only at this point we are sure that there will be a return from this thread so it's OK to use the managed stack + CLR_RT_HeapBlock& top = stack.PushValueAndClear(); + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.NewObjectFromIndex(top, g_CLR_RT_WellKnownTypes.m_I2cTransferResult)); + result = top.Dereference(); FAULT_ON_NULL(result); + + // successfull transaction + // set the result field + result[ Library_win_dev_i2c_native_Windows_Devices_I2c_I2cTransferResult::FIELD___status ].SetInteger((CLR_UINT32)I2cTransferStatus_FullTransfer); + + // set the bytes transferred field + result[ Library_win_dev_i2c_native_Windows_Devices_I2c_I2cTransferResult::FIELD___bytesTransferred ].SetInteger((CLR_UINT32)(palI2c->i2cTransaction.writeCount + palI2c->i2cTransaction.readCount)); + + // done here + break; + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); + } + } + + // pop timeout heap block from stack + stack.PopValue(); + + } + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2c_I2cController.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2c_I2cController.cpp new file mode 100644 index 00000000..c3006aa3 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_Windows_Devices_I2c_I2cController.cpp @@ -0,0 +1,33 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include "win_dev_i2c_native_target.h" + + +HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cController::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + { + + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_i2c_native_Windows_Devices_I2c_I2cController::GetDeviceSelector___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // declare the device selector string whose max size is "I2C1,I2C2,I2C3,I2C4," + terminator and init with the terminator + char deviceSelectorString[] = { "I2C1" }; + + // because the caller is expecting a result to be returned + // we need set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + stack.SetResult_String(deviceSelectorString); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_target.h b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_target.h new file mode 100644 index 00000000..853b5523 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.I2c/win_dev_i2c_native_target.h @@ -0,0 +1,26 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIN_DEV_I2C_NATIVE_TARGET_H_ +#define _WIN_DEV_I2C_NATIVE_TARGET_H_ + +#include +#include "Board.h" +#include + +// struct representing the I2C +struct NF_PAL_I2C +{ + I2C_Handle i2c; + I2C_Params i2cParams; + I2C_Transaction i2cTransaction; +}; + +/////////////////////////////////////////// +// declaration of the the I2C PAL strucs // +/////////////////////////////////////////// +extern NF_PAL_I2C I2C1_PAL; + +#endif //_WIN_DEV_I2C_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp new file mode 100644 index 00000000..9b11039a --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmController.cpp @@ -0,0 +1,73 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_pwm_native_target.h" + +// PWMConfig _pwmConfig; + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_MaxFrequency___R8( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + // FIXME : how can this value be determined ? + stack.SetResult_R8(1.0); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_MinFrequency___R8( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + // FIXME : how can this value be determined ? + stack.SetResult_R8(1.0); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::get_PinCount___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + // TODO + // this is now hardcoded to TWO because this is the available PWM outputs in CC3220SF launchpad + // ideally it should come from the PWM config file at target level + stack.SetResult_I4(2); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::NativeSetDesiredFrequency___U4__U4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // the SimpleLink PWM driver doesn't require any general setting + // so there is nothing to do here, just keeping the ceremony for the managed API + unsigned int desiredFrequency = (unsigned int)stack.Arg1().NumericByRef().u4; + + stack.SetResult_R8(desiredFrequency); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::GetDeviceSelector___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // this is now hardcoded to ONE because there is only one PWM controller in CC3220SF launchpad + // ideally it should come from the PWM config file at target level + char deviceSelectorString[] = "TIM0"; + + // because the caller is expecting a result to be returned + // we need set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + stack.SetResult_String(deviceSelectorString); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp new file mode 100644 index 00000000..7c6bf15b --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_Windows_Devices_Pwm_PwmPin.cpp @@ -0,0 +1,120 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "win_dev_pwm_native_target.h" + +//////////////////////////////////////////////////////////////////// + + +PWM_Handle PwmPins[PWM_PIN_COUNT]; + + +int GetChannel (int pin, int timerId) +{ + // TODO + return -1; +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeSetActiveDutyCyclePercentage___VOID__U4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties + int pinNumber = (int)(pThis[ FIELD___pinNumber ].NumericByRef().u4); + + // Retrieves the needed parameters from method parameters + unsigned int dutyCycle = (unsigned int)stack.Arg1().NumericByRef().u4; + + PWM_setDuty(PwmPins[pinNumber], dutyCycle); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeSetPolarity___VOID__U1( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(stack.NotImplementedStub()); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeStart___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties + int pinNumber = (int)(pThis[ FIELD___pinNumber ].NumericByRef().u4); + + // get the controller + CLR_RT_HeapBlock* controller = pThis[ FIELD___pwmController ].Dereference(); + + // get the frequency from the controller + double frequency = controller[ Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmController::FIELD___actualFrequency ].NumericByRef().r8; + + PWM_Params params; + PWM_Params_init(¶ms); + params.dutyUnits = PWM_DUTY_US; + params.dutyValue = 0; + params.periodUnits = PWM_PERIOD_HZ; + params.periodValue = frequency; + PwmPins[pinNumber] = PWM_open(pinNumber, ¶ms); + if (PwmPins[pinNumber] == NULL) + { + // Board_PWM did not open + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + PWM_start(PwmPins[pinNumber]); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeStop___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties + int pinNumber = (int)(pThis[ FIELD___pinNumber ].NumericByRef().u4); + + // Stops PWM output on the channel associated with this handler + PWM_stop(PwmPins[pinNumber]); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_pwm_native_Windows_Devices_Pwm_PwmPin::DisposeNative___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Retrieves the needed parameters from private class properties + int pinNumber = (int)(pThis[ FIELD___pinNumber ].NumericByRef().u4); + + PWM_close(PwmPins[pinNumber]); + } + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_target.h b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_target.h new file mode 100644 index 00000000..b6f2523a --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Pwm/win_dev_pwm_native_target.h @@ -0,0 +1,21 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _WIN_DEV_PWM_NATIVE_TARGET_H_ +#define _WIN_DEV_PWM_NATIVE_TARGET_H_ + +#include "Board.h" +#include + +#include +#include + +///////////////////////////////////// +// Array of PWM handlers // +// these live in the target folder // +///////////////////////////////////// +extern PWM_Handle PwmPins[PWM_PIN_COUNT]; + +#endif //_WIN_DEV_PWM_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo.cpp new file mode 100644 index 00000000..7754a7e7 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo.cpp @@ -0,0 +1,28 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#include "win_dev_spi_native_target.h" + + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo::get_MaxClockFrequency___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // return dummy value + stack.SetResult_I4 (0); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo::get_MinClockFrequency___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // return dummy value + stack.SetResult_I4 (0); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiController.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiController.cpp new file mode 100644 index 00000000..ba60fb41 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiController.cpp @@ -0,0 +1,22 @@ +// +// Copyright (c) 2018 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#include "win_dev_spi_native_target.h" + + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiController::GetDeviceSelector___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // declare the device selector string whose max size is "SPI1" + terminator and init with the terminator + char deviceSelectorString[] = { "SPI1" }; + + // because the caller is expecting a result to be returned + // we need set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + stack.SetResult_String(deviceSelectorString); + } + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiDevice.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiDevice.cpp new file mode 100644 index 00000000..85fdfd46 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiDevice.cpp @@ -0,0 +1,262 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#include +#include "win_dev_spi_native_target.h" + +// define this type here to make it shorter and improve code readability +typedef Library_win_dev_spi_native_Windows_Devices_Spi_SpiConnectionSettings SpiConnectionSettings; + + +///////////////////////////////////////////////////// +// SPI PAL strucs declared in win_dev_spi_native.h // +///////////////////////////////////////////////////// +NF_PAL_SPI SPI1_PAL; + + +void SpiCallback(SPI_Handle handle, SPI_Transaction *transaction) +{ + NATIVE_INTERRUPT_START + + // are there any other transactions pending? + if(SPI1_PAL.transactionCount) + { + // start transfer of 1st transaction + SPI_transfer(SPI1_PAL.masterSpi, &SPI1_PAL.transactions[SPI1_PAL.transactionCount--]); + } + else + { + // no more transactions + // fire event for SPI transaction complete + Events_Set( SYSTEM_EVENT_FLAG_SPI_MASTER ); + } + + NATIVE_INTERRUPT_END +} + +// Give a complete low-level SPI configuration from user's managed connectionSettings +void GetSPIConfig(int busIndex, CLR_RT_HeapBlock* config, bool bufferIs16bits) +{ + SPI_Params spiParams; + + // Open SPI as slave (default) + SPI_Params_init(&spiParams); + spiParams.frameFormat = (SPI_FrameFormat)config[ SpiConnectionSettings::FIELD___spiMode ].NumericByRef().s4; + spiParams.transferMode = SPI_MODE_CALLBACK; + spiParams.mode = SPI_SLAVE; + spiParams.transferCallbackFxn = SpiCallback; + spiParams.dataSize = bufferIs16bits ? 16 : 8; + spiParams.bitRate = (uint32_t)config[ SpiConnectionSettings::FIELD___clockFrequency ].NumericByRef().s4; + SPI1_PAL.masterSpi = SPI_open(Board_SPI_SLAVE, &spiParams); +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer___VOID__SZARRAY_U1__SZARRAY_U1__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + return NativeTransfer( stack, false ); +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer___VOID__SZARRAY_U2__SZARRAY_U2__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + return NativeTransfer( stack, true ); +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer( CLR_RT_StackFrame& stack, bool bufferIs16bits ) +{ + NANOCLR_HEADER(); + { + bool fullDuplex; + + CLR_RT_HeapBlock hbTimeout; + CLR_INT64* timeout; + bool eventResult = true; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the managed spi connectionSettings object instance + CLR_RT_HeapBlock* pConfig = pThis[ FIELD___connectionSettings ].Dereference(); + + // Are we using SPI full-duplex for transfer? + fullDuplex = (bool)stack.Arg3().NumericByRef().u1; + + // dereference the write and read buffers from the arguments + CLR_RT_HeapBlock_Array* writeBuffer = stack.Arg1().DereferenceArray(); + CLR_RT_HeapBlock_Array* readBuffer = stack.Arg2().DereferenceArray(); + + // set a timeout to an infinite timeout + // the catch is that the working thread MUST ALWAYS return at some point + // !! need to cast to CLR_INT64 otherwise it wont setup a proper timeout infinite + hbTimeout.SetInteger((CLR_INT64)-1); + + NANOCLR_CHECK_HRESULT(stack.SetupTimeoutFromTicks( hbTimeout, timeout )); + + // protect the buffers from GC so DMA can find them where they are supposed to be + CLR_RT_ProtectFromGC gcWriteBuffer( *writeBuffer ); + CLR_RT_ProtectFromGC gcReadBuffer( *readBuffer ); + + // setup the operation and init buffers + if(stack.m_customState == 1) + { + // get the LL SPI configuration, depending on user's managed parameters and buffer element size + GetSPIConfig(0, pConfig, bufferIs16bits); // index '0' in this case is a dummy value... there is only one SPI available + + // alloc mem for transactions + if(fullDuplex) + { + // we'll be doing this on a single transaction + SPI1_PAL.transactions = (SPI_Transaction*)platform_malloc(sizeof(SPI_Transaction)); + SPI1_PAL.transactionCount = 1; + } + else + { + // we need two transactions + SPI1_PAL.transactions = (SPI_Transaction*)platform_malloc(sizeof(SPI_Transaction) * 2); + SPI1_PAL.transactionCount = 2; + } + + // check allocation + if(SPI1_PAL.transactions == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + else + { + if(fullDuplex) + { + if (writeBuffer != NULL) + { + // get the size of the buffer by reading the number of elements in the CLR_RT_HeapBlock_Array + SPI1_PAL.transactions[0].count = writeBuffer->m_numOfElements; + + // set DMA write buffer + if(bufferIs16bits) + { + // buffer data width is 16bits + // get the pointer to the write buffer as UINT16 because it's really an UINT16 (2 bytes) + SPI1_PAL.transactions[0].txBuf = (uint16_t*)writeBuffer->GetFirstElementUInt16(); + } + else + { + // buffer data width is 8bits + // get the pointer to the write buffer as BYTE + SPI1_PAL.transactions[0].txBuf = (uint8_t*)writeBuffer->GetFirstElement(); + } + } + + if (readBuffer != NULL) + { + // we are in full duplex, the count for the SPI transaction was already set on the write + + if(bufferIs16bits) + { + // buffer data width is 16bits + SPI1_PAL.transactions[0].rxBuf = (uint16_t*)readBuffer->GetFirstElementUInt16(); + } + else + { + // buffer data width is 8bits + // get the pointer to the read buffer as BYTE + SPI1_PAL.transactions[0].rxBuf = (uint8_t*)readBuffer->GetFirstElement(); + } + } + } + else + { + // on a sequential transmition we TX first and then RX + + // TX on 1st transaction + if (writeBuffer != NULL) + { + // get the size of the buffer by reading the number of elements in the CLR_RT_HeapBlock_Array + SPI1_PAL.transactions[0].count = writeBuffer->m_numOfElements; + + // set DMA write buffer + if(bufferIs16bits) + { + // buffer data width is 16bits + // get the pointer to the write buffer as UINT16 because it's really an UINT16 (2 bytes) + SPI1_PAL.transactions[0].txBuf = (uint16_t*)writeBuffer->GetFirstElementUInt16(); + } + else + { + // buffer data width is 8bits + // get the pointer to the write buffer as BYTE + SPI1_PAL.transactions[0].txBuf = (uint8_t*)writeBuffer->GetFirstElement(); + } + } + + // RX on 2nd transaction + if (readBuffer != NULL) + { + // get the size of the buffer by reading the number of elements in the CLR_RT_HeapBlock_Array + SPI1_PAL.transactions[1].count = readBuffer->m_numOfElements; + + if(bufferIs16bits) + { + // buffer data width is 16bits + SPI1_PAL.transactions[1].rxBuf = (uint16_t*)readBuffer->GetFirstElementUInt16(); + } + else + { + // buffer data width is 8bits + // get the pointer to the read buffer as BYTE + SPI1_PAL.transactions[1].rxBuf = (uint8_t*)readBuffer->GetFirstElement(); + } + } + } + + // start transfer of 1st transaction + SPI_transfer(SPI1_PAL.masterSpi, &SPI1_PAL.transactions[0]); + + // take one from pending transcations counter + SPI1_PAL.transactionCount--; + + // bump custom state + stack.m_customState = 2; + } + } + + while(eventResult) + { + // non-blocking wait allowing other threads to run while we wait for the Spi transaction to complete + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.WaitEvents( stack.m_owningThread, *timeout, CLR_RT_ExecutionEngine::c_Event_SpiMaster, eventResult )); + + if(!eventResult) + { + // timeout occurred + NANOCLR_SET_AND_LEAVE(CLR_E_TIMEOUT); + } + } + + // pop timeout heap block from stack + stack.PopValue(); + + // null pointers and vars + pThis = NULL; + pConfig = NULL; + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::DisposeNative___VOID( CLR_RT_StackFrame& stack ) +{ + (void)stack; + + NANOCLR_HEADER(); + + SPI_close(SPI1_PAL.masterSpi); + + NANOCLR_NOCLEANUP_NOLABEL(); +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_target.h b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_target.h new file mode 100644 index 00000000..59a2c758 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_target.h @@ -0,0 +1,28 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#ifndef _WIN_DEV_SPI_NATIVE_TARGET_H_ +#define _WIN_DEV_SPI_NATIVE_TARGET_H_ + +#include +#include "Board.h" +#include + +// struct representing the SPI +struct NF_PAL_SPI +{ + SPI_Handle masterSpi; + SPI_Params spiParams; + SPI_Transaction* transactions; + uint8_t transactionCount; +}; + +/////////////////////////////////////////// +// declaration of the the SPI PAL strucs // +/////////////////////////////////////////// +extern NF_PAL_SPI SPI1_PAL; + +#endif //_WIN_DEV_SPI_NATIVE_TARGET_H_ diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/WireProtocol_App_Interface.c b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/WireProtocol_App_Interface.c new file mode 100644 index 00000000..21259693 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/WireProtocol_App_Interface.c @@ -0,0 +1,30 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +// declaration for wrapper function +extern int CLR_Messaging_ProcessPayload(WP_Message* msg); + +//////////////////////////////////////////////////// + +int WP_App_ProcessHeader(WP_Message* message) +{ + // check for reception buffer overflow + if(message->m_header.m_size > sizeof(receptionBuffer)) + { + return false; + } + + message->m_payload = receptionBuffer; + return true; +} + +int WP_App_ProcessPayload(WP_Message* message) +{ + return CLR_Messaging_ProcessPayload(message); +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/WireProtocol_MonitorCommands.c b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/WireProtocol_MonitorCommands.c new file mode 100644 index 00000000..74e05b66 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/WireProtocol_MonitorCommands.c @@ -0,0 +1,7 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +// file empty on purpose +// in nanoCLR the MonitorCommands are implemented in Debugger diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/nanoCRT.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/nanoCRT.cpp new file mode 100644 index 00000000..45e1fa3e --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/nanoCRT.cpp @@ -0,0 +1,205 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include + +//--// +/* STDIO stubs */ +//--// + +#if !defined(BUILD_RTM) + +void hal_fprintf_SetLoggingCallback( LOGGING_CALLBACK fpn ) +{ + (void)fpn; + NATIVE_PROFILE_PAL_CRT(); + +} + +#endif + +//--// + +#if defined(PLATFORM_EMULATED_FLOATINGPOINT) + +// no floating point, fixed point + +int hal_snprintf_float( char* buffer, size_t len, const char* format, int32_t f ) +{ + NATIVE_PROFILE_PAL_CRT(); + + uint32_t i ; + uint32_t dec; + + if ( f < 0 ) + { + // negative number + i = (uint32_t) -f ; + dec = i & (( 1<>HAL_FLOAT_SHIFT); + + if (dec !=0) dec = (dec * (uint32_t)HAL_FLOAT_PRECISION + (1<< (HAL_FLOAT_SHIFT-1))) >>HAL_FLOAT_SHIFT; + + return hal_snprintf( buffer, len, "-%d.%03u", i, (uint32_t)dec); + + } + else + { + // positive number + i = (uint32_t) f ; + dec = f & (( 1<>HAL_FLOAT_SHIFT); + + if (dec !=0) dec = (dec * (uint32_t)HAL_FLOAT_PRECISION + (1<< (HAL_FLOAT_SHIFT-1))) >>HAL_FLOAT_SHIFT; + + return hal_snprintf( buffer, len, "%d.%03u", i, (uint32_t)dec); + } +} + +int hal_snprintf_double( char* buffer, size_t len, const char* format, int64_t& d ) +{ + NATIVE_PROFILE_PAL_CRT(); + + uint64_t i; + uint32_t dec; // 32 bit is enough for decimal part + + if ( d < 0 ) + { + // negative number + i = (uint64_t)-d; + + i += ((1 << (HAL_DOUBLE_SHIFT-1)) / HAL_DOUBLE_PRECISION); // add broad part of rounding increment before split + + dec = i & (( 1<> HAL_DOUBLE_SHIFT ; + + if (dec !=0) dec = (dec * HAL_DOUBLE_PRECISION + ((1 << (HAL_DOUBLE_SHIFT-1)) % HAL_DOUBLE_PRECISION)) >> HAL_DOUBLE_SHIFT; + + return hal_snprintf( buffer, len, "-%lld.%04u", (int64_t)i, (uint32_t)dec); + + } + else + { + + // positive number + i = (uint64_t)d; + + i += ((1 << (HAL_DOUBLE_SHIFT-1)) / HAL_DOUBLE_PRECISION); // add broad part of rounding increment before split + + dec = i & (( 1<> HAL_DOUBLE_SHIFT; + + if (dec !=0) dec = (dec * HAL_DOUBLE_PRECISION + ((1 << (HAL_DOUBLE_SHIFT-1)) % HAL_DOUBLE_PRECISION)) >> HAL_DOUBLE_SHIFT; + + return hal_snprintf( buffer, len, "%lld.%04u", (int64_t)i, (uint32_t)dec); + } +} + +#else + +#endif + +// because debug_printf needs to be called in both C and C++ we need a proxy to allow it to be called in 'C' +extern "C" { + +#if !defined(BUILD_RTM) + + void debug_printf(const char* format, ...) + { + char buffer[256]; + va_list arg_ptr; + + va_start( arg_ptr, format ); + + int len = vsnprintf( buffer, sizeof(buffer)-1, format, arg_ptr ); + + DebuggerPort_Write( HalSystemConfig.stdio, buffer, len, 0 ); // skip null terminator + + va_end( arg_ptr ); + } + +#else + __inline void debug_printf( const char *format, ... ) {} +#endif // !defined(BUILD_RTM) +} + +int hal_strcpy_s ( char* strDst, size_t sizeInBytes, const char* strSrc ) +{ + NATIVE_PROFILE_PAL_CRT(); +#undef strcpy + + size_t len; + if(strDst == NULL || strSrc == NULL || sizeInBytes == 0) {_ASSERTE(FALSE); return 1;} + + len = hal_strlen_s(strSrc); + if(sizeInBytes < len + 1) {_ASSERTE(FALSE); return 1;} + + strcpy( strDst, strSrc ); + return 0; + +#define strcpy DoNotUse_*strcpy [] +} + +int hal_strncpy_s ( char* strDst, size_t sizeInBytes, const char* strSrc, size_t count ) +{ + NATIVE_PROFILE_PAL_CRT(); +#undef strncpy + if(strDst == NULL || strSrc == NULL || sizeInBytes == 0) {_ASSERTE(FALSE); return 1;} + + if (sizeInBytes < count + 1) + { + _ASSERTE(FALSE); + strDst[0] = 0; + return 1; + } + + strDst[count] = 0; + strncpy( strDst, strSrc, count ); + return 0; + +#define strncpy DoNotUse_*strncpy [] +} + +size_t hal_strlen_s (const char * str) +{ + NATIVE_PROFILE_PAL_CRT(); + + const char *eos = str; + while( *eos++ ) ; + return( eos - str - 1 ); +} + +int hal_strncmp_s ( const char* str1, const char* str2, size_t num ) +{ + NATIVE_PROFILE_PAL_CRT(); +#undef strncmp + if(str1 == NULL || str2 == NULL) {_ASSERTE(FALSE); return 1;} + + return strncmp( str1, str2, num ); + +#define strncmp DoNotUse_*strncmp [] +} + +// Compares 2 ASCII strings case insensitive. Does not take locale into account. +int hal_stricmp( const char * dst, const char * src ) +{ + int f = 0, l = 0; + + do + { + if ( ((f = (unsigned char)(*(dst++))) >= 'A') && (f <= 'Z') ) + { + f -= 'A' - 'a'; + } + if ( ((l = (unsigned char)(*(src++))) >= 'A') && (l <= 'Z') ) + { + l -= 'A' - 'a'; + } + } + while ( f && (f == l) ); + + return(f - l); +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetHAL.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetHAL.cpp new file mode 100644 index 00000000..b1d5dd80 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetHAL.cpp @@ -0,0 +1,155 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include +#include +#include + +// +// Reboot handlers clean up on reboot +// +static ON_SOFT_REBOOT_HANDLER s_rebootHandlers[16] = {NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}; + +void HAL_AddSoftRebootHandler(ON_SOFT_REBOOT_HANDLER handler) +{ + for(unsigned int i=0; i 0) ? true : false; +} + +void SystemState_Set(SYSTEM_STATE_type state) +{ + GLOBAL_LOCK(); + + SystemState_SetNoLock(state); + + GLOBAL_UNLOCK(); +} + +void SystemState_Clear(SYSTEM_STATE_type state) +{ + GLOBAL_LOCK(); + + SystemState_ClearNoLock(state ); + + GLOBAL_UNLOCK(); +} + +bool SystemState_Query(SYSTEM_STATE_type state) +{ + GLOBAL_LOCK(); + + bool systemStateCopy = SystemState_QueryNoLock(state); + + GLOBAL_UNLOCK(); + + return systemStateCopy; +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetHAL_Power.c b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetHAL_Power.c new file mode 100644 index 00000000..d81f534d --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetHAL_Power.c @@ -0,0 +1,39 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include + +#define SL_STOP_TIMEOUT (200) +extern uint16_t sl_Stop(const uint16_t Timeout); + +// FIXME TODO +void CPU_Reset() +{ + // stop network processor activities before reseting the MCU + sl_Stop(SL_STOP_TIMEOUT); + + // Reset the MCU + PRCMHibernateCycleTrigger(); +}; + +// CPU sleep is not currently implemented in this target +inline void CPU_Sleep(SLEEP_LEVEL_type level, uint64_t wakeEvents){ (void)level; (void)wakeEvents; }; + +inline bool CPU_IsSoftRebootSupported() { return true; }; + +void CPU_SetPowerMode(PowerLevel_type powerLevel) +{ + switch(powerLevel) + { + case PowerLevel__Off: + // gracefully shutdown everything + // FIXME TODO + break; + + default: + // all the other power modes are unsupported here + break; + } +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetHAL_Time.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetHAL_Time.cpp new file mode 100644 index 00000000..397c0866 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetHAL_Time.cpp @@ -0,0 +1,128 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include +#include +#include +#include + +// Returns the current date time from the RTC +uint64_t HAL_Time_CurrentDateTime(bool datePartOnly) +{ + SYSTEMTIME st; + struct timespec tspec; + + clock_gettime(CLOCK_REALTIME, &tspec); + + // Convert from Unix time(year since 1900) to SYSTEMTIME(Years since 1601) + int64_t time = ((int64_t)tspec.tv_sec * (int64_t)TIME_CONVERSION__TO_SECONDS) + TIME_UNIX_EPOCH_AS_TICKS; + + HAL_Time_ToSystemTime(time, &st ); + + // zero 'time' fields if date part only is required + if(datePartOnly) + { + st.wMilliseconds = 0; + st.wSecond = 0; + st.wMinute = 0; + st.wHour = 0; + } + + return HAL_Time_ConvertFromSystemTime( &st ); +}; + +void HAL_Time_SetUtcTime(uint64_t utcTime) +{ + SYSTEMTIME systemTime; + struct tm newTime; + struct timespec tspec; + + HAL_Time_ToSystemTime(utcTime, &systemTime); + + newTime.tm_year = systemTime.wYear - 1900; // years since 1900 + newTime.tm_mon = systemTime.wMonth - 1; // months since January 0-11 + newTime.tm_mday = systemTime.wDay; // day of the month 1-31 + newTime.tm_wday = systemTime.wDayOfWeek; // days since Sunday 0-6 + newTime.tm_hour = (uint32_t)systemTime.wHour; // hours since midnight 0-23 + newTime.tm_min = (uint32_t)systemTime.wMinute; // minutes after the hour 0-59 + newTime.tm_sec = (uint32_t)systemTime.wSecond; // seconds after the minute 0-59 + + time_t t = mktime(&newTime); + tspec.tv_sec = t; + tspec.tv_nsec = 0; + + clock_settime(CLOCK_REALTIME, &tspec); +} + +bool HAL_Time_TimeSpanToStringEx( const int64_t& ticks, char*& buf, size_t& len ) +{ + uint64_t ticksAbs; + uint64_t rest; + + if(ticks < 0) + { + ticksAbs = -ticks; + + CLR_SafeSprintf( buf, len, "-" ); + } + else + { + ticksAbs = ticks; + } + + rest = ticksAbs % ( 1000 * TIME_CONVERSION__TICKUNITS); + ticksAbs = ticksAbs / ( 1000 * TIME_CONVERSION__TICKUNITS); // Convert to seconds. + + if(ticksAbs > TIME_CONVERSION__ONEDAY) // More than one day. + { + CLR_SafeSprintf( buf, len, "%d.", (int32_t)(ticksAbs / TIME_CONVERSION__ONEDAY) ); ticksAbs %= TIME_CONVERSION__ONEDAY; + } + + CLR_SafeSprintf( buf, len, "%02d:", (int32_t)(ticksAbs / TIME_CONVERSION__ONEHOUR) ); ticksAbs %= TIME_CONVERSION__ONEHOUR ; + CLR_SafeSprintf( buf, len, "%02d:", (int32_t)(ticksAbs / TIME_CONVERSION__ONEMINUTE)); ticksAbs %= TIME_CONVERSION__ONEMINUTE; + CLR_SafeSprintf( buf, len, "%02d" , (int32_t)(ticksAbs / TIME_CONVERSION__ONESECOND)); ticksAbs %= TIME_CONVERSION__ONESECOND; + + ticksAbs = (uint32_t)rest; + if(ticksAbs) + { + CLR_SafeSprintf( buf, len, ".%07d", (uint32_t)ticksAbs ); + } + + return len != 0; +} + +bool DateTimeToString(const int64_t& time, char*& buf, size_t& len ) +{ + SYSTEMTIME st; + + HAL_Time_ToSystemTime( time, &st ); + + return CLR_SafeSprintf(buf, len, "%4d/%02d/%02d %02d:%02d:%02d.%03d", st.wYear, st.wMonth, st.wDay, st.wHour, st.wMinute, st.wSecond, st.wMilliseconds ); +} + +char* DateTimeToString(const int64_t& time) +{ + static char rgBuffer[128]; + char* szBuffer = rgBuffer; + size_t iBuffer = ARRAYSIZE(rgBuffer); + + DateTimeToString( time, szBuffer, iBuffer ); + + return rgBuffer; +} + +const char* HAL_Time_CurrentDateTimeToString() +{ + return DateTimeToString(HAL_Time_CurrentDateTime(false)); +} + +uint64_t CPU_MillisecondsToTicks(uint64_t ticks) +{ + return ((ticks * (uint64_t)configTICK_RATE_HZ) / 1000); +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetPAL.c b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetPAL.c new file mode 100644 index 00000000..a4d0c627 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetPAL.c @@ -0,0 +1,68 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +extern UART_Handle uart; + +SemaphoreP_Handle uartMutex; + +// Need to have calls to these two functions in C code. +// Because they are called only on asm code, GCC linker with LTO option thinks they are not used and just removes them. +// Having them called from a dummy function that is never called it a workaround for this. +// The clean alternative would be to add the GCC attribute used in those functions, but that's not our code to touch. + +void dummyFunction(void) __attribute__((used)); + +// Never called. +void dummyFunction(void) { + vTaskSwitchContext(); + localProgramStart(); +} + +// configure UART +void ConfigUART() +{ + UART_Params uartParams; + + // Create a UART with data processing off + UART_Params_init(&uartParams); + + uartParams.writeDataMode = UART_DATA_BINARY; + uartParams.readDataMode = UART_DATA_BINARY; + uartParams.readReturnMode = UART_RETURN_FULL; + uartParams.readEcho = UART_ECHO_OFF; + uartParams.baudRate = 921600; + uartParams.readTimeout = 500; + + uart = UART_open(Board_UART0, &uartParams); + + if (uart == NULL) + { + // UART_open() failed + while (1); + } + + uartMutex = SemaphoreP_createBinary(1); + if (uartMutex == NULL) + { + // failed to create semaphore + while (1); + } +} + +void __error__(char *pcFilename, unsigned long ulLine) +{ + // + // Something horrible happened! You need to look + // at file "pcFilename" at line "ulLine" to see + // what error is being reported. + // + while(1) + { + } +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetPAL_Events.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetPAL_Events.cpp new file mode 100644 index 00000000..702f7fec --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetPAL_Events.cpp @@ -0,0 +1,179 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include +#include +#include + +uint64_t CPU_MillisecondsToTicks(uint64_t ticks); + +// timer for bool events +static TimerHandle_t boolEventsTimer; + +volatile uint32_t systemEvents; + +static void local_Events_SetBoolTimer_Callback( TimerHandle_t xTimer ); + +set_Event_Callback g_Event_Callback = NULL; +void* g_Event_Callback_Arg = NULL; + +bool Events_Initialize() +{ + NATIVE_PROFILE_PAL_EVENTS(); + + // init events + GLOBAL_LOCK(); + systemEvents = 0; + GLOBAL_UNLOCK(); + + boolEventsTimer = xTimerCreate( "boolEventsTimer", 10, pdFALSE, (void *)0, local_Events_SetBoolTimer_Callback); + + return true; +} + +bool Events_Uninitialize() +{ + NATIVE_PROFILE_PAL_EVENTS(); + + xTimerDelete(boolEventsTimer,0); + + return true; +} + +void Events_Set( uint32_t events ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + + // set events + GLOBAL_LOCK(); + systemEvents |= events; + GLOBAL_UNLOCK(); + + if( g_Event_Callback != NULL ) + { + g_Event_Callback( g_Event_Callback_Arg ); + } +} + +uint32_t Events_Get( uint32_t eventsOfInterest ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + + // get the requested flags from system events state and... + uint32_t returnEvents = (systemEvents & eventsOfInterest); + + // ... clear the requested flags atomically + GLOBAL_LOCK(); + systemEvents &= ~eventsOfInterest; + GLOBAL_UNLOCK(); + + // give the caller notice of just the events they asked for ( and were cleared already ) + return returnEvents; +} + +uint32_t Events_MaskedRead( uint32_t eventsOfInterest ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + return (systemEvents & eventsOfInterest); +} + +static void local_Events_SetBoolTimer_Callback( TimerHandle_t xTimer ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + + bool* timerCompleteFlag = (bool*)pvTimerGetTimerID( xTimer ); + *timerCompleteFlag = true; +} + +void Events_SetCallback( set_Event_Callback pfn, void* arg ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + + g_Event_Callback = pfn; + g_Event_Callback_Arg = arg; +} + +void Events_SetBoolTimer( bool* timerCompleteFlag, uint32_t millisecondsFromNow ) +{ + NATIVE_PROFILE_PAL_EVENTS(); + + // we assume only 1 can be active, abort previous just in case + xTimerStop( boolEventsTimer, 0 ); + + if(timerCompleteFlag != NULL) + { + vTimerSetTimerID( boolEventsTimer, (void*) timerCompleteFlag ); + xTimerChangePeriod( boolEventsTimer, millisecondsFromNow / portTICK_PERIOD_MS, 0 ); + } +} + +uint32_t Events_WaitForEvents( uint32_t powerLevel, uint32_t wakeupSystemEvents, uint32_t timeoutMilliseconds ) +{ + // schedule an interrupt for this far in the future + // timeout is in milliseconds, need to convert to ticks + uint64_t countsRemaining = CPU_MillisecondsToTicks(timeoutMilliseconds); + + #if defined(HAL_PROFILE_ENABLED) + Events_WaitForEvents_Calls++; + #endif + + uint64_t expireTimeInTicks = HAL_Time_CurrentTime() + countsRemaining; + bool runContinuations = true; + + while(true) + { + EVENTS_HEART_BEAT; + + uint32_t events = Events_MaskedRead( wakeupSystemEvents ); + if(events) + { + return events; + } + + if(expireTimeInTicks <= HAL_Time_CurrentTime()) + { + break; + } + + // first check and possibly run any continuations + // but only if we have slept after stalling + if(runContinuations && !SystemState_QueryNoLock(SYSTEM_STATE_NO_CONTINUATIONS)) + { + // if we stall on time, don't check again until after we sleep + runContinuations = HAL_CONTINUATION::Dequeue_And_Execute(); + } + else + { + // try stalled continuations again after sleeping + runContinuations = true; + + HAL_COMPLETION::WaitForInterrupts(expireTimeInTicks, powerLevel, wakeupSystemEvents ); + } + + // no events, pass control to the OS + taskYIELD(); + + // check if reboot or exit flags were set when the other OS threads executed + if(CLR_EE_DBG_IS(RebootPending) || CLR_EE_DBG_IS(ExitPending)) + { + break; + } + } + + return 0; +} + +void FreeManagedEvent(uint8_t category, uint8_t subCategory, uint16_t data1, uint32_t data2) +{ + (void)category; + (void)subCategory; + (void)data1; + (void)data2; + + NATIVE_PROFILE_PAL_EVENTS(); +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetPAL_Time.cpp b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetPAL_Time.cpp new file mode 100644 index 00000000..283f34ad --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetPAL_Time.cpp @@ -0,0 +1,67 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include +#include + +static TimerHandle_t nextEventTimer; + +static void NextEventTimer_Callback( TimerHandle_t xTimer ) +{ + (void)xTimer; + + // this call also schedules the next one, if there is one + HAL_COMPLETION::DequeueAndExec(); +} + +HRESULT Time_Initialize() +{ + nextEventTimer = xTimerCreate( "NextEventTimer", 10, pdFALSE, (void *)0, NextEventTimer_Callback); + + return S_OK; +} + +HRESULT Time_Uninitialize() +{ + xTimerDelete(nextEventTimer, 0); + + return S_OK; +} + +void Time_SetCompare ( uint64_t compareValueTicks ) +{ + if(compareValueTicks == 0) + { + // compare value is 0 so dequeue and schedule immediately + HAL_COMPLETION::DequeueAndExec(); + } + else if(compareValueTicks == HAL_COMPLETION_IDLE_VALUE) + { + // wait for infinity, don't need to do anything here + return; + } + else + { + if (HAL_Time_CurrentTime() >= compareValueTicks) + { + // already missed the event, dequeue and execute immediately + HAL_COMPLETION::DequeueAndExec(); + } + else + { + xTimerStop( nextEventTimer, 0 ); + + // compareValueTicks is the time (in sys ticks) that is being requested to fire an HAL_COMPLETION::DequeueAndExec() + // need to subtract the current system time to set when the timer will fire + compareValueTicks -= HAL_Time_CurrentTime(); + + // no need to stop the timer even if it's running because the API does it anyway + // need to convert from nF ticks to milliseconds and then to FreeRTOS sys ticks to load the timer + xTimerChangePeriod(nextEventTimer, compareValueTicks, 0); + } + } +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_LinkLocalTask.c b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_LinkLocalTask.c new file mode 100644 index 00000000..58e2f7cb --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_LinkLocalTask.c @@ -0,0 +1,2840 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +/* standard includes */ +#include +#include + +/* TI-DRIVERS Header files */ +#include +#include +#include + +/* Example/Board Header files */ +#include +#include +#include + +/* driverlib Header files */ +#include +#include + +// nanoFramework header files +#include + +#define NETAPP_MAX_RX_FRAGMENT_LEN SL_NETAPP_REQUEST_MAX_DATA_LEN +#define NETAPP_MAX_METADATA_LEN (100) +#define NETAPP_MAX_ARGV_TO_CALLBACK SL_FS_MAX_FILE_NAME_LENGTH + 50 +#define NUMBER_OF_URI_SERVICES (6) + +#define LED_TOGGLE_OTA_PROCESS_TIMEOUT (100) /* In msecs */ + +#define DEV_TYPE_CC3220R (0x010) +#define DEV_TYPE_CC3220RS (0x018) +#define DEV_TYPE_CC3220FS (0x019) +#define DEV_TYPE_CC323XR (0x110) +#define DEV_TYPE_CC323XRS (0x118) +#define DEV_TYPE_CC323XFS (0x119) + +#define MAC_ADDR_STR_LEN (18) +#define IP_ADDR_STR_LEN (16) +#define SENSOR_VALUE_STR_LEN (4) + + +/**************************************************************************** + LOCAL FUNCTION PROTOTYPES +****************************************************************************/ + +//***************************************************************************** +// +//! \brief This function prepare error netapp response in case memory could +//! not be allocated +//! +//! \param[in] pNetAppResponse netapp response structure +//! +//! \return none +//! +//**************************************************************************** +void NetAppRequestErrorResponse(SlNetAppResponse_t *pNetAppResponse); + +//***************************************************************************** +// +//! \brief This function fetches the device MAC address +//! +//! \param[out] buffer to occupy the MAC address in string format +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t getDeviceMacAddress(uint8_t *macAddress); + +//***************************************************************************** +// +//! Function to read accelarometer +//! +//! \param none +//! +//! \return SUCCESS or FAILURE +//! +//***************************************************************************** +uint8_t accelarometerReading(void); + +//***************************************************************************** +// +//! Function to read temperature +//! +//! \param none +//! +//! \return SUCCESS or FAILURE +//! +//***************************************************************************** +uint8_t temperatureReading(void); + +//***************************************************************************** +// +//! \brief this function composes an element type from metadata/payload +//!(TLV structure) +//! +//! \param[in] isAnswer states whether this is a value or a parameter +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] elementVal value of element +//! +//! \return element type +//! +//**************************************************************************** +uint16_t setElementType(uint8_t isValue, + uint8_t requestIdx, + uint8_t elementVal); + +//***************************************************************************** +// +//! \brief This function prepares metadata for HTTP GET requests +//! +//! \param[in] parsingStatus validity of HTTP GET request +//! +//! \param[in] contentLen content length in respond to +//! HTTP GET request +//! +//! \return metadataLen +//! +//**************************************************************************** +uint16_t prepareGetMetadata(int32_t parsingStatus, + uint32_t contentLen, + HttpContentTypeList contentTypeId); + +//***************************************************************************** +// +//! \brief This function prepares metadata for HTTP POST/PUT requests +//! +//! \param[in] parsingStatus validity of HTTP POST/PUT request +//! +//! \return metadataLen +//! +//**************************************************************************** +uint16_t preparePostMetadata(int32_t parsingStatus); + +//***************************************************************************** +// +//! \brief This function fetches the device IP address +//! +//! \param[in] none +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t getDeviceIpAddress(void); + +//***************************************************************************** +// +//! \brief This function fetches the SSID the device is connected to +//! +//! \param[in] none +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t getDeviceSSID(void); + +//***************************************************************************** +// +//! \brief This function flushes the netapp data from the client +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \param[in] flags netapp flags for more data +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t otaFlushNetappReq(SlNetAppRequest_t *netAppRequest, + uint32_t *flags); + +//***************************************************************************** +// +//! \brief This is a filesystem service callback function for HTTP PUT +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] argcCallback count of input params to the service callback +//! +//! \param[in] argvCallback set of input params to the service callback +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t otaPutCallback(uint8_t requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback, + SlNetAppRequest_t *netAppRequest); + +//***************************************************************************** +// +//! \brief This is the ota service callback function for HTTP GET +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] argcCallback count of input params to the service callback +//! +//! \param[in] argvCallback set of input params to the service callback +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t otaGetCallback(uint8_t requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback, + SlNetAppRequest_t *netAppRequest); + +//***************************************************************************** +// +//! \brief This is a light service callback function for HTTP GET +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] argcCallback count of input params to the service callback +//! +//! \param[in] argvCallback set of input params to the service callback +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t lightGetCallback(uint8_t requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback, + SlNetAppRequest_t *netAppRequest); + +//***************************************************************************** +// +//! \brief This is a light service callback function for HTTP POST +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] argcCallback count of input params to the service callback +//! +//! \param[in] argvCallback set of input params to the service callback +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t lightPostCallback(uint8_t requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback, + SlNetAppRequest_t *netAppRequest); + +//***************************************************************************** +// +//! \brief This is a sensors service callback function for HTTP GET +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] argcCallback count of input params to the service callback +//! +//! \param[in] argvCallback set of input params to the service callback +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t sensorGetCallback(uint8_t requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback, + SlNetAppRequest_t *netAppRequest); + +//***************************************************************************** +// +//! \brief This is a generic device service callback function for HTTP GET +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] argcCallback count of input params to the service callback +//! +//! \param[in] argvCallback set of input params to the service callback +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t deviceGetCallback(uint8_t requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback, + SlNetAppRequest_t *netAppRequest); + +//***************************************************************************** +// +//! \brief This function create mailbox message queue between linkLocal task +//! and driver task +//! +//! \param[in] None +//! +//! \return 0 on success or -ve on error +//! +//**************************************************************************** +void initLinkLocalDB(void); + +//***************************************************************************** +// +//! \brief This function scan netapp request and parse the payload +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] pPhrase pointer to HTTP metadata payload +//! +//! \param[in] payloadLen HTTP metadata or payload length +//! +//! \param[out] argcCallback count of input params to the service callback +//! +//! \param[out] argvCallback set of input params to the service callback +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t parseUrlEncoded(uint8_t requestIdx, + uint8_t * pPhrase, + uint16_t phraseLen, + uint8_t *argcCallback, + uint8_t **argvCallback); + +//***************************************************************************** +// +//! \brief This function maps header type to its string value +//! +//! \param[in] httpHeaderType http header type +//! +//! \param[out] httpHeaderText http header text +//! +//! \return none +//! +//**************************************************************************** +void convertHeaderType2Text(uint8_t httpHeaderType, + uint8_t **httpHeaderText); + +//***************************************************************************** +// +//! \brief This function scan netapp request and parse the metadata +//! +//! \param[in] requestType HTTP method (GET, POST, PUT or DEL) +//! +//! \param[in] pMetadata pointer to HTTP metadata +//! +//! \param[in] metadataLen HTTP metadata length +//! +//! \param[out] requestIdx request index to indicate the message +//! +//! \param[out] argcCallback count of input params to the service callback +//! +//! \param[out] argvCallback set of input params to the service callback +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t parseHttpRequestMetadata(uint8_t requestType, + uint8_t * pMetadata, + uint16_t metadataLen, + uint8_t *requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback); + +//***************************************************************************** +// +//! \brief This function scan netapp request and parse the payload +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] pPayload pointer to HTTP payload +//! +//! \param[in] payloadLen HTTP payload length +//! +//! \param[out] argcCallback count of input params to the service callback +//! +//! \param[out] argvCallback set of input params to the service callback +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t parseHttpRequestPayload(uint8_t requestIdx, + uint8_t * pPayload, + uint16_t payloadLen, + uint8_t *argcCallback, + uint8_t **argvCallback); + +//***************************************************************************** +// +//! \brief This function checks that the content requested via HTTP message exists +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \param[out] requestIdx request index to indicate the message +//! +//! \param[out] argcCallback count of input params to the service callback +//! +//! \param[out] argvCallback set of input params to the service callback +//! +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t httpCheckContentInDB(SlNetAppRequest_t *netAppRequest, + uint8_t *requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback); + +//***************************************************************************** +// +//! \brief This function parse and execute HTTP GET requests +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return None +//! +//**************************************************************************** +void httpGetHandler(SlNetAppRequest_t *netAppRequest); + +//***************************************************************************** +// +//! \brief This function parse and execute HTTP POST/PUT requests +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return None +//! +//**************************************************************************** +void httpPostHandler(SlNetAppRequest_t *netAppRequest); + +/**************************************************************************** + GLOBAL VARIABLES +****************************************************************************/ + +const uint8_t pageNotFound[] = "404 - Sorry page not found"; + +/* metadata and content buffer are allocated + static as these are shared in all use cases*/ +/* however, it is possible to set those dynamically as well */ +uint8_t gMetadataBuffer[NETAPP_MAX_METADATA_LEN]; +uint8_t gPayloadBuffer[NETAPP_MAX_RX_FRAGMENT_LEN]; +//uint8_t gOtaVersion[VERSION_STR_SIZE + 1]; + +uint8_t gHttpPostBuffer[NETAPP_MAX_ARGV_TO_CALLBACK]; +uint8_t gHttpGetBuffer[NETAPP_MAX_ARGV_TO_CALLBACK]; + +int8_t xVal, yVal, zVal; +float temperatureVal; +I2C_Handle i2cHandle; + +/* database to hold ota archive */ +//OtaArchive_t gOtaArcive; + +/* message queue for http messages between server and client */ +mqd_t linkLocalMQueue; +pthread_mutex_t *sensorLockObj = NULL; /* Lock Object for sensor readings */ + +http_RequestObj_t httpRequest[NUMBER_OF_URI_SERVICES] = +{ + {0, SL_NETAPP_REQUEST_HTTP_GET, "/ota", { + {NULL} + }, NULL}, + {1, SL_NETAPP_REQUEST_HTTP_PUT, "/ota", { + {NULL} + }, NULL}, + {2, SL_NETAPP_REQUEST_HTTP_GET, "/light", { + {NULL} + }, NULL}, + {3, SL_NETAPP_REQUEST_HTTP_POST, "/light", { + {NULL} + }, NULL}, + {4, SL_NETAPP_REQUEST_HTTP_GET, "/sensor", { + {NULL} + }, NULL}, + {5, SL_NETAPP_REQUEST_HTTP_GET, "/device", { + {NULL} + }, NULL}, +}; + +http_headerFieldType_t g_HeaderFields [] = +{ + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_VERSION, WEB_SERVER_VERSION}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_REQUEST_URI, WEB_SERVER_REQUEST_URI}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_QUERY_STRING, + WEB_SERVER_QUERY_STRING}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_TYPE, + WEB_SERVER_HEADER_CONTENT_TYPE}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_LEN, + WEB_SERVER_HEADER_CONTENT_LEN}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_LOCATION, + WEB_SERVER_HEADER_LOCATION}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_SERVER, WEB_SERVER_HEADER_SERVER}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_USER_AGENT, + WEB_SERVER_HEADER_USER_AGENT}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_COOKIE, WEB_SERVER_HEADER_COOKIE}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_SET_COOKIE, + WEB_SERVER_HEADER_SET_COOKIE}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_UPGRADE, WEB_SERVER_HEADER_UPGRADE}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_REFERER, WEB_SERVER_HEADER_REFERER}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_ACCEPT, WEB_SERVER_HEADER_ACCEPT}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_ENCODING, + WEB_SERVER_HEADER_CONTENT_ENCODING}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_DISPOSITION, + WEB_SERVER_HEADER_CONTENT_DISPOSITION}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONNECTION, + WEB_SERVER_HEADER_CONNECTION}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_ETAG, WEB_SERVER_HEADER_ETAG}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_DATE, WEB_SERVER_HEADER_DATE}, + {SL_NETAPP_REQUEST_METADATA_TYPE_HEADER_HOST, WEB_SERVER_HEADER_HOST}, + {SL_NETAPP_REQUEST_METADATA_TYPE_ACCEPT_ENCODING, + WEB_SERVER_HEADER_ACCEPT_ENCODING}, + {SL_NETAPP_REQUEST_METADATA_TYPE_ACCEPT_LANGUAGE, + WEB_SERVER_HEADER_ACCEPT_LANGUAGE}, + {SL_NETAPP_REQUEST_METADATA_TYPE_CONTENT_LANGUAGE, + WEB_SERVER_HEADER_CONTENT_LANGUAGE} +}; + +http_contentTypeMapping_t g_ContentTypes [] = +{ + {HttpContentTypeList_TextHtml, TEXT_HTML, TEXT_HTML_MIME}, + {HttpContentTypeList_TextCSS, TEXT_CSS, TEXT_CSS_MIME}, + {HttpContentTypeList_TextXML, TEXT_XML, TEXT_XML_MIME}, + {HttpContentTypeList_ApplicationJson, APPLICATION_JSON, + APPLICATION_JSON_MIME}, + {HttpContentTypeList_ImagePNG, IMAGE_PNG, IMAGE_PNG_MIME}, + {HttpContentTypeList_ImageGIF, IMAGE_GIF, IMAGE_GIF_MIME}, + {HttpContentTypeList_TextPlain, TEXT_PLAIN, TEXT_PLAIN_MIME}, + {HttpContentTypeList_TextCSV, TEXT_CSV, TEXT_CSV_MIME}, + {HttpContentTypeList_ApplicationJavascript, APPLICATION_JAVASCRIPT, + APPLICATION_JAVASCRIPT_MIME}, + {HttpContentTypeList_ImageJPEG, IMAGE_JPEG, IMAGE_JPEG_MIME}, + {HttpContentTypeList_ApplicationPDF, APPLICATION_PDF, + APPLICATION_PDF_MIME}, + {HttpContentTypeList_ApplicationZIP, APPLICATION_ZIP, + APPLICATION_ZIP_MIME}, + {HttpContentTypeList_ShokewaveFlash, SHOCKWAVE_FLASH, + SHOCKWAVE_FLASH_MIME}, + {HttpContentTypeList_AudioXAAC, AUDIO_X_AAC, AUDIO_X_AAC_MIME}, + {HttpContentTypeList_ImageXIcon, IMAGE_X_ICON, IMAGE_X_ICON_MIME}, + {HttpContentTypeList_TextVcard, TEXT_VCARD, TEXT_VCARD_MIME}, + {HttpContentTypeList_ApplicationOctecStream, APPLICATION_OCTEC_STREAM, + APPLICATION_OCTEC_STREAM_MIME}, + {HttpContentTypeList_VideoAVI, VIDEO_AVI, VIDEO_AVI_MIME}, + {HttpContentTypeList_VideoMPEG, VIDEO_MPEG, VIDEO_MPEG_MIME}, + {HttpContentTypeList_VideoMP4, VIDEO_MP4, VIDEO_MP4_MIME}, + {HttpContentTypeList_UrlEncoded, FORM_URLENCODED, URL_ENCODED_MIME} +}; + +LinkLocal_CB LinkLocal_ControlBlock; + +extern int snprintf(char *_string, + size_t _n, + const char *_format, + ...); + +/***************************************************************************** + Callback Functions +*****************************************************************************/ + +//***************************************************************************** +// +//! \brief This function is registered as netapp request callback +//! +//! \param[in] pNetAppRequest netapp request structure +//! +//! \param[out] pNetAppResponse netapp response structure +//! +//! \return none +//! +//**************************************************************************** +void SimpleLinkNetAppRequestEventHandler(SlNetAppRequest_t *pNetAppRequest, + SlNetAppResponse_t *pNetAppResponse) +{ + SlNetAppRequest_t *netAppRequest; + int32_t msgqRetVal; + + INFO_PRINT( + "[Link local task] NetApp Request Received - AppId = %d, Type = %d," + "Handle = %d\n\r", + pNetAppRequest->AppId, pNetAppRequest->Type, pNetAppRequest->Handle); + + if((pNetAppRequest->Type == SL_NETAPP_REQUEST_HTTP_GET) || + (pNetAppRequest->Type == SL_NETAPP_REQUEST_HTTP_DELETE) || + (pNetAppRequest->Type == SL_NETAPP_REQUEST_HTTP_POST) || + (pNetAppRequest->Type == SL_NETAPP_REQUEST_HTTP_PUT)) + { + /* Prepare pending response */ + pNetAppResponse->Status = SL_NETAPP_RESPONSE_PENDING; + pNetAppResponse->ResponseData.pMetadata = NULL; + pNetAppResponse->ResponseData.MetadataLen = 0; + pNetAppResponse->ResponseData.pPayload = NULL; + pNetAppResponse->ResponseData.PayloadLen = 0; + pNetAppResponse->ResponseData.Flags = 0; + } + else + { + NetAppRequestErrorResponse(pNetAppResponse); + + return; + } + + netAppRequest = (SlNetAppRequest_t *) malloc (sizeof(SlNetAppRequest_t)); + if(NULL == netAppRequest) + { + NetAppRequestErrorResponse(pNetAppResponse); + + return; + } + + memset(netAppRequest,0,sizeof(SlNetAppRequest_t)); + netAppRequest->AppId = pNetAppRequest->AppId; + netAppRequest->Type = pNetAppRequest->Type; + netAppRequest->Handle = pNetAppRequest->Handle; + netAppRequest->requestData.Flags = pNetAppRequest->requestData.Flags; + + /* Copy Metadata */ + if(pNetAppRequest->requestData.MetadataLen > 0) + { + netAppRequest->requestData.pMetadata = (uint8_t *) malloc ( + pNetAppRequest->requestData.MetadataLen); + if(NULL == netAppRequest->requestData.pMetadata) + { + NetAppRequestErrorResponse(pNetAppResponse); + free(netAppRequest); + return; + } + sl_Memcpy(netAppRequest->requestData.pMetadata, + pNetAppRequest->requestData.pMetadata, + pNetAppRequest->requestData.MetadataLen); + netAppRequest->requestData.MetadataLen = + pNetAppRequest->requestData.MetadataLen; + } + else + { + netAppRequest->requestData.MetadataLen = 0; + } + + /* Copy the payload */ + if(pNetAppRequest->requestData.PayloadLen > 0) + { + netAppRequest->requestData.pPayload = (uint8_t *) malloc ( + pNetAppRequest->requestData.PayloadLen); + if(NULL == netAppRequest->requestData.pPayload) + { + NetAppRequestErrorResponse(pNetAppResponse); + + if(netAppRequest->requestData.pMetadata != NULL) + { + free(netAppRequest->requestData.pMetadata); + } + free(netAppRequest); + return; + } + sl_Memcpy (netAppRequest->requestData.pPayload, + pNetAppRequest->requestData.pPayload, + pNetAppRequest->requestData.PayloadLen); + netAppRequest->requestData.PayloadLen = + pNetAppRequest->requestData.PayloadLen; + } + else + { + netAppRequest->requestData.PayloadLen = 0; + } + + msgqRetVal = mq_send(linkLocalMQueue, (char *)&netAppRequest, 1, 0); + if(msgqRetVal < 0) + { + UART_PRINT("[Link local task] could not send element to msg queue\n\r"); + while(1) + { + ; + } + } +} + +//***************************************************************************** +// +//! \brief This is a filesystem service callback function for HTTP PUT +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] argcCallback count of input params to the +//! service callback +//! +//! \param[in] argvCallback set of input params to the service callback +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t otaPutCallback(uint8_t requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback, + SlNetAppRequest_t *netAppRequest) +{ + uint8_t *argvArray; + uint16_t metadataLen; + uint8_t *filename; + int32_t Status; + uint32_t flags; + uint32_t fileLen = 0; + uint16_t elementType; + int16_t otaState, processedBytes, unprocessedBytes, chunkLen, otaChunkLen; + int32_t accumulatedLen; + uint8_t otaProgressBar; + uint32_t deviceType; + struct timespec ts; + + StartLedEvtTimer(LED_TOGGLE_OTA_PROCESS_TIMEOUT); + + Status = 0; + accumulatedLen = 0; + deviceType = getDeviceType(); + argvArray = *argvCallback; + + /* get the filename */ + filename = argvArray + 2 * ARGV_VALUE_OFFSET + 1; + + elementType = setElementType(1, requestIdx, CONTENT_LEN_TYPE); + + /* search for the file length */ + while((*argcCallback > 0) && (*((uint16_t *)argvArray) != elementType)) + { + argvArray += ARGV_LEN_OFFSET; /* skip the type */ + argvArray += *argvArray; /* add the length */ + argvArray++; /* skip the length */ + + (*argcCallback)--; + } + + if(*((uint16_t *)argvArray) == elementType) + { + sl_Memcpy ((uint8_t*)&fileLen, (argvArray + ARGV_VALUE_OFFSET), + *(argvArray + ARGV_LEN_OFFSET)); + } + + UART_PRINT("[Link local task] Received OTA filename %s, len = %lu \n\r", + filename, + fileLen); + + /* Init the Tar parser module */ + //OtaArchive_Init(&gOtaArcive); + + otaProgressBar = 0; + + /* at this point start the report server in the background */ + /* signal to ota task */ + sem_post(&LinkLocal_ControlBlock.otaReportServerStartSignal); + + /* set the flags to check for more data */ + flags = netAppRequest->requestData.Flags; + + /* must be archive file name */ + if(strstr((const char *)filename, ".tar") == NULL) + { + UART_PRINT( + "[Link local task] OTA filename should be in *.tar format\n\r"); + Status = -1; + goto exit_ota_put; + } + + /* updating versions */ + // OtaArchive_CheckVersion(&gOtaArcive, filename); + + sl_Memcpy(gPayloadBuffer, netAppRequest->requestData.pPayload, + netAppRequest->requestData.PayloadLen); + // Status = + // (int32_t)OtaArchive_Process(&gOtaArcive, gPayloadBuffer, + // netAppRequest->requestData.PayloadLen, + // &processedBytes); + INFO_PRINT("[Link local task] Received OTA payload %d. Processed %d \n\r", + netAppRequest->requestData.PayloadLen, + processedBytes); + + // if(Status < 0) + // { + // goto exit_ota_put; + // } + // else if(Status == ARCHIVE_STATUS_DOWNLOAD_DONE) + // { + // otaProgressBar = 100; + // mq_send(LinkLocal_ControlBlock.reportServerMQueue, + // (char *)&otaProgressBar, 1, + // 0); + + // /* Tar file parsing completed */ + // //UART_PRINT( + // // "[Link local task] sl_extLib_OtaRun: ---- " + // // "Download file completed %s\r\n", + // // filename); + + // Status = 0; + + // goto exit_ota_put; + // } + unprocessedBytes = netAppRequest->requestData.PayloadLen - processedBytes; + accumulatedLen += processedBytes; + otaProgressBar = (accumulatedLen * 100) / fileLen; + mq_send(LinkLocal_ControlBlock.reportServerMQueue, (char *)&otaProgressBar, + 1, + 0); + + while(OOB_IS_NETAPP_MORE_DATA(flags) || + ((unprocessedBytes > 0) && + ((fileLen - accumulatedLen) < NETAPP_MAX_RX_FRAGMENT_LEN))) + { + /* copy the unprocessed part to the start of the buffer */ + if(unprocessedBytes > 0) + { + sl_Memcpy(&gPayloadBuffer[0], &gPayloadBuffer[processedBytes], + unprocessedBytes); + } + + if(OOB_IS_NETAPP_MORE_DATA(flags)) + { + chunkLen = NETAPP_MAX_RX_FRAGMENT_LEN - unprocessedBytes; + Status = + sl_NetAppRecv(netAppRequest->Handle, (uint16_t *)&chunkLen, + &gPayloadBuffer[unprocessedBytes], + (unsigned long *)&flags); + INFO_PRINT( + "[Link local task] sl_NetAppRecv payload=%d, flags=%d \n\r", + chunkLen, flags); + if(Status < 0) + { + UART_PRINT( + "[Link local task] sl_NetAppRecv error=%d, flags=%d \n\r", + Status, flags); + /* Stop the parsing of the archive file */ + // OtaArchive_Abort(&gOtaArcive); + + goto exit_ota_put; + } + } + else + { + /* cover cases where netapp has no more data and + download is close to 100%. + Archive module needs more processing time to complete */ + INFO_PRINT( + "[Link local task] No more data in NetApp but archive module " + "still has processing to do \n\r"); + Status = 0; + chunkLen = 0; + } + + //otaState = OtaArchive_GetSktatus(&gOtaArcive); + //INFO_PRINT("[Link local task] OTA state is %d \n\r", otaState); + // if(otaState == OtaArchiveState_OpenFile) + // { + // //INFO_PRINT("[Link local task] File size is %d \n\r", + // // gOtaArcive.CurrTarObj.FileSize); + // } + + // if(otaState == OtaArchiveState_OpenFile) + // { + // if(strstr((const char *)gOtaArcive.CurrTarObj.pFileName, + // "mcuimg.bin") != NULL) + // { + // if((deviceType == DEV_TYPE_CC3220FS) || + // (deviceType == DEV_TYPE_CC323XFS)) + // { + // //UART_PRINT( + // // "[Link local task] mcu image of CC32xxR or CC32xxRS " + // // "cannot be programmed onto CC32xxSF\n\r"); + + // /* Stop the parsing of the archive file */ + // OtaArchive_Abort(&gOtaArcive); + + // goto exit_ota_put; + // } + // } + + // if(strstr((const char *)gOtaArcive.CurrTarObj.pFileName, + // "mcuflashimg.bin") != NULL) + // { + // if((deviceType == DEV_TYPE_CC3220R) || + // (deviceType == DEV_TYPE_CC3220RS) || + // (deviceType == DEV_TYPE_CC323XR) || + // (deviceType == DEV_TYPE_CC323XRS)) + // { + // //UART_PRINT( + // // "[Link local task] mcu image of CC32xxSF cannot be " + // // "programmed onto CC32xxR or CC32xxRS\n\r"); + + // /* Stop the parsing of the archive file */ + // OtaArchive_Abort(&gOtaArcive); + + // goto exit_ota_put; + // } + // } + // } + + otaChunkLen = chunkLen + unprocessedBytes; + // Status = + // (int32_t)OtaArchive_Process(&gOtaArcive, gPayloadBuffer, + // otaChunkLen, + // &processedBytes); + + INFO_PRINT( + "[Link local task] Received OTA payload=%d. Processed=%d \n\r", + otaChunkLen, processedBytes); + if(Status < 0) + { + UART_PRINT("[Link local task] OtaArchive error %d \n\r", Status); + goto exit_ota_put; + } + // else if(Status == ARCHIVE_STATUS_DOWNLOAD_DONE) + // { + // clock_gettime(CLOCK_REALTIME, &ts); + // ts.tv_nsec += 1000000; + // if(ts.tv_nsec > 1000000000) + // { + // ts.tv_nsec -= 1000000000; + // ts.tv_sec++; + // } + + // otaProgressBar = 100; + // mq_timedsend(LinkLocal_ControlBlock.reportServerMQueue, + // (char *)&otaProgressBar, 1, 0, + // &ts); + // /* Tar file parsing completed */ + // //UART_PRINT( + // // "[Link local task] sl_extLib_OtaRun: ---- Download " + // // "file completed %s\r\n", + // // filename); + + // Status = 0; + + // goto exit_ota_put; + // } + unprocessedBytes = otaChunkLen - processedBytes; + accumulatedLen += processedBytes; + otaProgressBar = (accumulatedLen * 100) / fileLen; + + clock_gettime(CLOCK_REALTIME, &ts); + ts.tv_nsec += 1000000; + if(ts.tv_nsec > 1000000000) + { + ts.tv_nsec -= 1000000000; + ts.tv_sec++; + } + + mq_timedsend(LinkLocal_ControlBlock.reportServerMQueue, + (char *)&otaProgressBar, 1, 0, + &ts); + } + +exit_ota_put: + + + + /* several use cases can occur at this point + + + ▼use case▼| good | bad | no rx bufer | internal error | + --------------------------------------------------------------- + Status | 0 | <0 | 0 | 0 | + --------------------------------------------------------------- + progress bar| 100 | <100 | <100 | <100 | + --------------------------------------------------------------- + flags | 0 | N/A | 0 | 80000000 | + --------------------------------------------------------------- + send metada?| yes | yes | yes | no | + --------------------------------------------------------------- + notes | | | bad case | bad case | + --------------------------------------------------------------- + + + */ + + /* progress bar is not yet 100% - bad case*/ + if(otaProgressBar != 100) + { + Status = -1; + } + UART_PRINT("[Link local task] ota put done. Status=%d \r\n", Status); + if(Status == 0) + { + /* flush the netapp data from client */ + otaFlushNetappReq(netAppRequest, &flags); + } + + /* sending metadata is not allowed in case of internal error */ + if(OOB_IS_NETAPP_ERROR(flags)) + { + UART_PRINT("[Link local task] sl_NetAppRecv error, flags=%d \n\r", + flags); + } + else + { + metadataLen = preparePostMetadata(Status); + + INFO_PRINT("[Link local task] ota put, sending metadata \r\n"); + sl_NetAppSend (netAppRequest->Handle, metadataLen, gMetadataBuffer, + SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA); + } + + if(Status != 0) + { + /* mark progress bar to 0xFF so ota task + would get restarted to reopen socket */ + otaProgressBar = 0xFF; + + clock_gettime(CLOCK_REALTIME, &ts); + ts.tv_nsec += 1000000; + if(ts.tv_nsec > 1000000000) + { + ts.tv_nsec -= 1000000000; + ts.tv_sec++; + } + + mq_timedsend(LinkLocal_ControlBlock.reportServerMQueue, + (char *)&otaProgressBar, 1, 0, + &ts); + } + + UART_PRINT("[Link local task] waiting for signal from report server\r\n"); + + /* waits for ota response server to + finish sending report messages to client */ + sem_wait(&LinkLocal_ControlBlock.otaReportServerStopSignal); + + StopLedEvtTimer(); + if(Status == 0) + { + //GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_ON); + } + else + { + //GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); + } + + if(Status == 0) + { + /* it means Tar file is downloaded and parsed correctly. + Need to reset the MCU */ + mcuReboot(); + } + + return(Status); +} + +//***************************************************************************** +// +//! \brief This is the ota service callback function for HTTP GET +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] argcCallback count of input params to the service callback +//! +//! \param[in] argvCallback set of input params to the service callback +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t otaGetCallback(uint8_t requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback, + SlNetAppRequest_t *netAppRequest) +{ + uint8_t *argvArray, *pPayload; + uint16_t metadataLen, elementType; + int32_t Status = 0; + + argvArray = *argvCallback; + pPayload = gPayloadBuffer; + + while(*argcCallback > 0) + { + elementType = setElementType(1, requestIdx, CONTENT_LEN_TYPE); + /* content length is irrelevant for GET */ + if(*((uint16_t *)argvArray) != elementType) + { + switch(*(argvArray + ARGV_VALUE_OFFSET)) + { + case OtaIdx_Version: + + // Status = OtaArchive_GetCurrentVersion(gOtaVersion); + // if(Status < 0) + // { + // //UART_PRINT( + // // "[Link local task] ota bundle version file does " + // // "not exist\r\n"); + // strcpy((char *)gMetadataBuffer, "no version file exists"); + // Status = 0; + // } + // else + // { + // //sl_Memcpy(gMetadataBuffer, gOtaVersion, VERSION_STR_SIZE); + // gMetadataBuffer[VERSION_STR_SIZE] = '\0'; + // } + + break; + } + + sl_Memcpy ( + pPayload, + httpRequest[requestIdx].charValues[*(argvArray + + ARGV_VALUE_OFFSET)]. + characteristic, + strlen((const char *)httpRequest[requestIdx]. + charValues[*(argvArray+ARGV_VALUE_OFFSET)] + .characteristic)); + pPayload += strlen( + (const char *)httpRequest[requestIdx]. + charValues[*(argvArray +ARGV_VALUE_OFFSET)]. + characteristic); + *pPayload++ = '='; + sl_Memcpy (pPayload, gMetadataBuffer, + strlen((const char *)gMetadataBuffer)); + pPayload += strlen((const char *)gMetadataBuffer); + *pPayload++ = '&'; + } + + (*argcCallback)--; + argvArray += ARGV_LEN_OFFSET; /* skip the type */ + argvArray += *argvArray; /* add the length */ + argvArray++; /* skip the length */ + } + + /* NULL terminate the payload */ + *(pPayload - 1) = '\0'; + + metadataLen = + prepareGetMetadata(Status, strlen( + (const char *)gPayloadBuffer), + HttpContentTypeList_UrlEncoded); + + sl_NetAppSend (netAppRequest->Handle, metadataLen, gMetadataBuffer, + (SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION | + SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA)); + INFO_PRINT("[Link local task] Metadata Sent, len = %d \n\r", metadataLen); + /* mark as last segment */ + sl_NetAppSend(netAppRequest->Handle, + strlen ((const char *)gPayloadBuffer), + gPayloadBuffer, + 0); + INFO_PRINT("[Link local task] Data Sent, len = %d\n\r", + strlen ((const char *)gPayloadBuffer)); + + return(Status); +} + +//***************************************************************************** +// +//! \brief This is a light service callback function for HTTP GET +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] argcCallback count of input params to the service callback +//! +//! \param[in] argvCallback set of input params to the service callback +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t lightGetCallback(uint8_t requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback, + SlNetAppRequest_t *netAppRequest) +{ + uint8_t *argvArray, *pPayload; + //uint8_t ledIdx = Board_GPIO_LED0; + uint16_t ledState, metadataLen, elementType; + + argvArray = *argvCallback; + pPayload = gPayloadBuffer; + + while(*argcCallback > 0) + { + elementType = setElementType(1, requestIdx, CONTENT_LEN_TYPE); + // /* content length is irrelevant for GET */ + // if(*((uint16_t *)argvArray) != elementType) + // { + // switch(*(argvArray + ARGV_VALUE_OFFSET)) + // { + // case LedIdx_RedLed: + // ledIdx = Board_GPIO_LED0; + // break; + // case LedIdx_OrangeLed: + // ledIdx = Board_GPIO_LED0; + // break; + // case LedIdx_GreenLed: + // ledIdx = Board_GPIO_LED0; + // break; + // } + + // ledState = GPIO_read(ledIdx); + // sl_Memcpy ( + // pPayload, + // httpRequest[requestIdx].charValues[*(argvArray + + // ARGV_VALUE_OFFSET)]. + // characteristic, + // strlen((const char *)httpRequest[requestIdx]. + // charValues[*(argvArray+ARGV_VALUE_OFFSET)] + // .characteristic)); + // pPayload += strlen( + // (const char *)httpRequest[requestIdx]. + // charValues[*(argvArray + ARGV_VALUE_OFFSET)] + // .characteristic); + // *pPayload++ = '='; + // sl_Memcpy ( + // pPayload, + // httpRequest[requestIdx]. + // charValues[*(argvArray +ARGV_VALUE_OFFSET)]. + // value[ledState],strlen((const char *)httpRequest[requestIdx]. + // charValues[*(argvArray + + // ARGV_VALUE_OFFSET)]. + // value[ledState])); + + // pPayload += strlen( + // (const char *)httpRequest[requestIdx]. + // charValues[*(argvArray +ARGV_VALUE_OFFSET)]. + // value[ledState]); + // *pPayload++ = '&'; + // } + + (*argcCallback)--; + argvArray += ARGV_LEN_OFFSET; /* skip the type */ + argvArray += *argvArray; /* add the length */ + argvArray++; /* skip the length */ + } + + /* NULL terminate the payload */ + *(pPayload - 1) = '\0'; + + metadataLen = prepareGetMetadata(0, + strlen((const char *)gPayloadBuffer), + HttpContentTypeList_UrlEncoded); + sl_NetAppSend (netAppRequest->Handle, metadataLen, gMetadataBuffer, + (SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION | + SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA)); + INFO_PRINT("[Link local task] Metadata Sent, len = %d \n\r", metadataLen); + /* mark as last segment */ + sl_NetAppSend ( netAppRequest->Handle, + strlen ((const char *)gPayloadBuffer), + gPayloadBuffer, 0); + INFO_PRINT("[Link local task] Data Sent, len = %d\n\r", + strlen ((const char *)gPayloadBuffer)); + + return(0); +} + +//***************************************************************************** +// +//! \brief This is a light service callback function for HTTP POST +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] argcCallback count of input params to the service callback +//! +//! \param[in] argvCallback set of input params to the service callback +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t lightPostCallback(uint8_t requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback, + SlNetAppRequest_t *netAppRequest) +{ + uint8_t *argvArray; + uint16_t metadataLen, elementType; + uint16_t ledState = 0xFF; + //uint16_t ledIdx = Board_GPIO_LED0; + argvArray = *argvCallback; + + while(*argcCallback > 0) + { + elementType = setElementType(1, requestIdx, CONTENT_LEN_TYPE); + // /* content length is irrelevant for POST */ + // if(*((uint16_t *)argvArray) != elementType) + // { + // /* means it is the value, not the parameter */ + // if(*(argvArray + 1) & 0x80) + // { + // /* get the light operation */ + // switch(*(argvArray + ARGV_VALUE_OFFSET)) + // { + // case LedValues_Off: + // ledState = Board_GPIO_LED_OFF; + // break; + // case LedValues_On: + // ledState = Board_GPIO_LED_ON; + // break; + // case LedValues_Toggle: + // ledState = 0xFF; + // break; + // } + + // if(ledState == 0xFF) + // { + // GPIO_toggle(ledIdx); + // } + // else + // { + // GPIO_write(ledIdx, ledState); + // } + // } + // else /* means it is the parameter, not the value */ + // { + // /* apply to the right light */ + // switch(*(argvArray + ARGV_VALUE_OFFSET)) + // { + // case LedIdx_RedLed: + // ledIdx = Board_GPIO_LED0; + // break; + // } + // } + // } + + (*argcCallback)--; + argvArray += ARGV_LEN_OFFSET; /* skip the type */ + argvArray += *argvArray; /* add the length */ + argvArray++; /* skip the length */ + } + + metadataLen = preparePostMetadata(0); + + sl_NetAppSend (netAppRequest->Handle, metadataLen, gMetadataBuffer, + SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA); + + return(0); +} + +//***************************************************************************** +// +//! \brief This is a sensors service callback function for HTTP GET +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] argcCallback count of input params to the service callback +//! +//! \param[in] argvCallback set of input params to the service callback +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t sensorGetCallback(uint8_t requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback, + SlNetAppRequest_t *netAppRequest) +{ + uint8_t *argvArray, *pPayload; + uint16_t metadataLen, elementType; + int16_t value = 0; + int32_t Status; + + argvArray = *argvCallback; + pPayload = gPayloadBuffer; + + /* Read accelerometer axis values */ + Status = accelarometerReading(); + if(Status != 0) + { + UART_PRINT( + "[Link local task] Failed to read data from accelerometer\n\r"); + } + + /* Read temperature sensor values */ + Status = temperatureReading(); + if(Status != 0) + { + UART_PRINT( + "[Link local task] Failed to" + " read data from temperature sensor\n\r"); + } + + while(*argcCallback > 0) + { + elementType = setElementType(1, requestIdx, CONTENT_LEN_TYPE); + /* content length is irrelevant for GET */ + if(*((uint16_t *)argvArray) != elementType) + { + switch(*(argvArray + ARGV_VALUE_OFFSET)) + { + case SensorIdx_XAxis: + value = xVal; + break; + case SensorIdx_YAxis: + value = yVal; + break; + case SensorIdx_ZAxis: + value = zVal; + break; + case SensorIdx_FarnTemp: + value = (int16_t)temperatureVal; + break; + } + + sl_Memcpy ( + pPayload, + httpRequest[requestIdx].charValues[*(argvArray + + ARGV_VALUE_OFFSET)]. + characteristic, + strlen((const char *)httpRequest[requestIdx]. + charValues[*(argvArray+ARGV_VALUE_OFFSET)]. + characteristic)); + pPayload += strlen( + (const char *)httpRequest[requestIdx]. + charValues[*(argvArray +ARGV_VALUE_OFFSET)]. + characteristic); + *pPayload++ = '='; + + snprintf((char *)pPayload, SENSOR_VALUE_STR_LEN, "%d", value); + /* add the value length */ + pPayload += strlen((const char *)pPayload); + *pPayload++ = '&'; + } + + (*argcCallback)--; + argvArray += ARGV_LEN_OFFSET; /* skip the type */ + argvArray += *argvArray; /* add the length */ + argvArray++; /* skip the length */ + } + + /* NULL terminate the payload */ + *(pPayload - 1) = '\0'; + + metadataLen = prepareGetMetadata(0, + strlen((const char *)gPayloadBuffer), + HttpContentTypeList_UrlEncoded); + + sl_NetAppSend (netAppRequest->Handle, metadataLen, gMetadataBuffer, + (SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION | + SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA)); + INFO_PRINT("[Link local task] Metadata Sent, len = %d \n\r", metadataLen); + /* mark as last segment */ + sl_NetAppSend (netAppRequest->Handle, strlen ( + (const char *)gPayloadBuffer), gPayloadBuffer, 0); + INFO_PRINT("[Link local task] Data Sent, len = %d\n\r", + strlen ((const char *)gPayloadBuffer)); + + return(0); +} + +//***************************************************************************** +// +//! \brief This is a generic device service callback function for HTTP GET +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] argcCallback count of input params to the service callback +//! +//! \param[in] argvCallback set of input params to the service callback +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t deviceGetCallback(uint8_t requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback, + SlNetAppRequest_t *netAppRequest) +{ + uint8_t *argvArray, *pPayload; + uint16_t metadataLen, elementType; + int32_t Status; + uint32_t deviceType; + + argvArray = *argvCallback; + pPayload = gPayloadBuffer; + deviceType = getDeviceType(); + + while(*argcCallback > 0) + { + elementType = setElementType(1, requestIdx, CONTENT_LEN_TYPE); + /* content length is irrelevant for GET */ + if(*((uint16_t *)argvArray) != elementType) + { + switch(*(argvArray + ARGV_VALUE_OFFSET)) + { + case DeviceIdx_Ssid: + Status = getDeviceSSID(); + if(Status != 0) + { + // UART_PRINT( + // "[Link local task] failed to get SSID. IP_ACQ=%d, " + // "IP_LEASED=%d\n\r", + // GET_STATUS_BIT(OutOfBox_ControlBlock.Status, + // AppStatusBits_IpAcquired), + // GET_STATUS_BIT(OutOfBox_ControlBlock.Status, + // AppStatusBits_IpLeased)); + goto exit_device_get; + } + break; + case DeviceIdx_IpAddress: + Status = getDeviceIpAddress(); + if(Status != 0) + { + goto exit_device_get; + } + break; + case DeviceIdx_MacAddress: + Status = getDeviceMacAddress(gMetadataBuffer); + if(Status != 0) + { + goto exit_device_get; + } + break; + case DeviceIdx_AppID: + /* 3235 applies for both CC3230 and CC3235 */ + if(deviceType == DEV_TYPE_CC323XFS) + { + strcpy((char *)gMetadataBuffer, "out_of_box_3235_fs"); + } + else if(deviceType == DEV_TYPE_CC323XRS) + { + strcpy((char *)gMetadataBuffer, "out_of_box_3235_rs"); + } + else if(deviceType == DEV_TYPE_CC323XR) + { + strcpy((char *)gMetadataBuffer, "out_of_box_3235_r"); + } + else if(deviceType == DEV_TYPE_CC3220FS) + { + strcpy((char *)gMetadataBuffer, "out_of_box_fs"); + } + else if(deviceType == DEV_TYPE_CC3220RS) + { + strcpy((char *)gMetadataBuffer, "out_of_box_rs"); + } + else if(deviceType == DEV_TYPE_CC3220R) + { + strcpy((char *)gMetadataBuffer, "out_of_box_r"); + } + else + { + UART_PRINT( + "[Link local task] device type %d is not supported\n\r", + deviceType); + Status = -1; + + goto exit_device_get; + } + + Status = 0; + + break; + } + + sl_Memcpy ( + pPayload, + httpRequest[requestIdx].charValues[*(argvArray + + ARGV_VALUE_OFFSET)]. + characteristic, + strlen((const char *)httpRequest[requestIdx]. + charValues[*(argvArray+ARGV_VALUE_OFFSET)]. + characteristic)); + pPayload += strlen( + (const char *)httpRequest[requestIdx]. + charValues[*(argvArray +ARGV_VALUE_OFFSET)]. + characteristic); + *pPayload++ = '='; + sl_Memcpy (pPayload, gMetadataBuffer, + strlen((const char *)gMetadataBuffer)); + pPayload += strlen((const char *)gMetadataBuffer); + *pPayload++ = '&'; + } + + (*argcCallback)--; + argvArray += ARGV_LEN_OFFSET; /* skip the type */ + argvArray += *argvArray; /* add the length */ + argvArray++; /* skip the length */ + } + + /* NULL terminate the payload */ + *(pPayload - 1) = '\0'; + + Status = 0; + +exit_device_get: + if(Status != 0) + { + strcpy((char *)gPayloadBuffer, (const char *)pageNotFound); + } + + metadataLen = + prepareGetMetadata(Status, + strlen((const char *)gPayloadBuffer), + HttpContentTypeList_UrlEncoded); + + sl_NetAppSend (netAppRequest->Handle, metadataLen, gMetadataBuffer, + (SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION | + SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA)); + INFO_PRINT("[Link local task] Metadata Sent, len = %d \n\r", metadataLen); + /* mark as last segment */ + sl_NetAppSend (netAppRequest->Handle, strlen ( + (const char *)gPayloadBuffer), gPayloadBuffer, 0); + INFO_PRINT("[Link local task] Data Sent, len = %d\n\r", + strlen ((const char *)gPayloadBuffer)); + + return(Status); +} + +//***************************************************************************** +// Local Functions +//***************************************************************************** + +//***************************************************************************** +// +//! \brief This function prepare error netapp response in case memory could +//! not be allocated +//! +//! \param[in] pNetAppResponse netapp response structure +//! +//! \return none +//! +//**************************************************************************** +void NetAppRequestErrorResponse(SlNetAppResponse_t *pNetAppResponse) +{ + UART_PRINT( + "[Link local task] could not allocate memory for netapp request\n\r"); + + /* Prepare error response */ + pNetAppResponse->Status = SL_NETAPP_RESPONSE_NONE; + pNetAppResponse->ResponseData.pMetadata = NULL; + pNetAppResponse->ResponseData.MetadataLen = 0; + pNetAppResponse->ResponseData.pPayload = NULL; + pNetAppResponse->ResponseData.PayloadLen = 0; + pNetAppResponse->ResponseData.Flags = 0; +} + +//***************************************************************************** +// +//! \brief This function fetches the device MAC address +//! +//! \param[out] buffer to occupy the MAC address in string format +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t getDeviceMacAddress(uint8_t *macAddress) +{ + uint8_t macAddressVal[6]; + uint16_t macAddressLen; + int32_t Status; + + macAddress[0] = '\0'; + + /* Get the device's MAC address */ + macAddressLen = 6; + Status = + sl_NetCfgGet(SL_NETCFG_MAC_ADDRESS_GET,NULL,&macAddressLen, + (uint8_t *)macAddressVal); + if(Status < 0) + { + return(Status); + } + + snprintf((char *)macAddress, MAC_ADDR_STR_LEN, + "%02x:%02x:%02x:%02x:%02x:%02x", + macAddressVal[0], + macAddressVal[1], + macAddressVal[2], + macAddressVal[3], + macAddressVal[4], + macAddressVal[5]); + + return(0); +} + +//***************************************************************************** +// +//! Function to read accelarometer +//! +//! \param none +//! +//! \return SUCCESS or FAILURE +//! +//***************************************************************************** +uint8_t accelarometerReading(void) +{ + int8_t xValRead, yValRead, zValRead; + int32_t Status; + + if(sensorLockObj != NULL) + { + pthread_mutex_lock(sensorLockObj); + } + + /* Read accelarometer axis values */ + Status = BMA2xxReadNew(i2cHandle, &xValRead, &yValRead, &zValRead); + if(Status != 0) + { + /* try to read again */ + Status = BMA2xxReadNew(i2cHandle, &xValRead, &yValRead, &zValRead); + if(Status != 0) /* leave previous values */ + { + UART_PRINT( + "[Link local task] Failed to read data from accelarometer\n\r"); + } + } + + if(Status == 0) + { + xVal = xValRead; + yVal = yValRead; + zVal = zValRead; + } + + if(sensorLockObj != NULL) + { + pthread_mutex_unlock(sensorLockObj); + } + + return(Status); +} + +//***************************************************************************** +// +//! Function to read temperature +//! +//! \param none +//! +//! \return SUCCESS or FAILURE +//! +//***************************************************************************** +uint8_t temperatureReading(void) +{ + int32_t Status; + float fTempRead; + + /* Read temperature axis values */ + Status = TMP006DrvGetTemp(i2cHandle, &fTempRead); + if(Status != 0) + { + /* try to read again */ + Status = TMP006DrvGetTemp(i2cHandle, &fTempRead); + if(Status != 0) /* leave previous values */ + { + UART_PRINT( + "[Link local task] Failed to read data from" + " temperature sensor\n\r"); + } + } + + if(Status == 0) + { + fTempRead = (fTempRead > 100) ? 100 : fTempRead; + temperatureVal = fTempRead; + } + + return(Status); +} + +//***************************************************************************** +// +//! \brief this function composes an element type from metadata/payload +//! (TLV structure) +//! +//! \param[in] isAnswer states whether this is a value or a parameter +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] elementVal value of element +//! +//! \return element type +//! +//**************************************************************************** +uint16_t setElementType(uint8_t isValue, + uint8_t requestIdx, + uint8_t elementVal) +{ + uint16_t elementType; + + elementType = elementVal; + elementType |= (((isValue << 7) | (requestIdx & 0x7F)) << 8); + + return(elementType); +} + +//***************************************************************************** +// +//! \brief This function prepares metadata for HTTP GET requests +//! +//! \param[in] parsingStatus validity of HTTP GET request +//! +//! \param[in] contentLen content length in respond to +//! HTTP GET request +//! +//! \return metadataLen +//! +//**************************************************************************** +uint16_t prepareGetMetadata(int32_t parsingStatus, + uint32_t contentLen, + HttpContentTypeList contentTypeId) +{ + char *contentType; + uint8_t *pMetadata; + uint16_t metadataLen; + + contentType = g_ContentTypes[contentTypeId].contentTypeText; + + pMetadata = gMetadataBuffer; + + /* http Status */ + *pMetadata = (uint8_t) SL_NETAPP_REQUEST_METADATA_TYPE_STATUS; + pMetadata++; + *(uint16_t *)pMetadata = (uint16_t) 2; + pMetadata += 2; + + if(parsingStatus < 0) + { + *(uint16_t *)pMetadata = + (uint16_t) SL_NETAPP_HTTP_RESPONSE_404_NOT_FOUND; + } + else + { + *(uint16_t *)pMetadata = (uint16_t) SL_NETAPP_HTTP_RESPONSE_200_OK; + } + + pMetadata += 2; + + /* Content type */ + *pMetadata = (uint8_t) SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_TYPE; + pMetadata++; + (*(uint16_t *)pMetadata) = (uint16_t) strlen ((const char *)contentType); + pMetadata += 2; + sl_Memcpy (pMetadata, contentType, strlen((const char *)contentType)); + pMetadata += strlen((const char *)contentType); + + /* Content len */ + *pMetadata = SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_LEN; + pMetadata++; + *(uint16_t *)pMetadata = (uint16_t) 4; + pMetadata += 2; + *(uint32_t *)pMetadata = (uint32_t) contentLen; + + metadataLen = 5 + 7 + strlen ((const char *)contentType) + 3; + + return(metadataLen); +} + +//***************************************************************************** +// +//! \brief This function prepares metadata for HTTP POST/PUT requests +//! +//! \param[in] parsingStatus validity of HTTP POST/PUT request +//! +//! \return metadataLen +//! +//**************************************************************************** +uint16_t preparePostMetadata(int32_t parsingStatus) +{ + uint8_t *pMetadata; + uint16_t metadataLen; + + pMetadata = gMetadataBuffer; + + /* http Status */ + *pMetadata = (uint8_t) SL_NETAPP_REQUEST_METADATA_TYPE_STATUS; + pMetadata++; + *(uint16_t *)pMetadata = (uint16_t) 2; + pMetadata += 2; + + if(parsingStatus < 0) + { + *(uint16_t *)pMetadata = + (uint16_t) SL_NETAPP_HTTP_RESPONSE_404_NOT_FOUND; + } + else + {/* no need for content so browser stays on the same page */ + *(uint16_t *)pMetadata = + (uint16_t) SL_NETAPP_HTTP_RESPONSE_204_OK_NO_CONTENT; + } + + pMetadata += 2; + + metadataLen = 5; + + return(metadataLen); +} + +//***************************************************************************** +// +//! \brief This function fetches the device IP address +//! +//! \param[in] none +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t getDeviceIpAddress(void) +{ + uint16_t ConfigOpt; + uint16_t ipLen; + SlNetCfgIpV4Args_t ipV4 = {0}; + int32_t Status; + + gMetadataBuffer[0] = '\0'; + + /* Get the device's IP address */ + ipLen = sizeof(SlNetCfgIpV4Args_t); + ConfigOpt = 0; + Status = + sl_NetCfgGet(SL_NETCFG_IPV4_STA_ADDR_MODE,&ConfigOpt,&ipLen, + (uint8_t *)&ipV4); + if(Status < 0) + { + return(Status); + } + + snprintf((char *)gMetadataBuffer, IP_ADDR_STR_LEN, "%d.%d.%d.%d", + (int)SL_IPV4_BYTE(ipV4.Ip,3), + (int)SL_IPV4_BYTE(ipV4.Ip,2), + (int)SL_IPV4_BYTE(ipV4.Ip,1), + (int)SL_IPV4_BYTE(ipV4.Ip,0)); + + return(0); +} + +//***************************************************************************** +// +//! \brief This function fetches the SSID the device is connected to +//! +//! \param[in] none +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t getDeviceSSID(void) +{ + uint16_t len = 32; + uint16_t config_opt = SL_WLAN_AP_OPT_SSID; + /* simplelink as station connected to AP */ + if(GET_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_IpAcquired) && + GET_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_Connection)) + { + // sl_Memcpy ((uint8_t *)gMetadataBuffer, + // (const uint8_t *)nF_ControlBlock.connectionSSID, + // nF_ControlBlock.ssidLen); + // gMetadataBuffer[nF_ControlBlock.ssidLen] = '\0'; + } + /* simplelink as AP with connected client */ + else if(GET_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_IpAcquired) && + GET_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpLeased)) + { + // sl_WlanGet(SL_WLAN_CFG_AP_ID, &config_opt, &len, + // (uint8_t *)nF_ControlBlock.connectionSSID); + // nF_ControlBlock.ssidLen = len - 1; + // sl_Memcpy ((uint8_t *)gMetadataBuffer, + // (const uint8_t *)nF_ControlBlock.connectionSSID, + // nF_ControlBlock.ssidLen); + // gMetadataBuffer[nF_ControlBlock.ssidLen] = '\0'; + } + else + { + return(-1); + } + + return(0); +} + +//***************************************************************************** +// +//! \brief This function flushes the netapp data from the client +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \param[in] flags netapp flags for more data +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t otaFlushNetappReq(SlNetAppRequest_t *netAppRequest, + uint32_t *flags) +{ + int32_t Status; + int32_t chunkLen; + + Status = 0; + + while((*flags & SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION) == + SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION) + { + chunkLen = NETAPP_MAX_RX_FRAGMENT_LEN; + Status = + sl_NetAppRecv(netAppRequest->Handle, (uint16_t *)&chunkLen, + gPayloadBuffer, + (_u32 *)flags); + INFO_PRINT("[Link local task] flushing NetApp packet, len=%d \n\r", + chunkLen); + if(Status < 0) + { + return(Status); + } + + if(*flags == 0) + { + break; + } + } + + return(Status); +} + +//***************************************************************************** +// +//! \brief This function create mailbox message queue between linkLocal task +//! and driver task +//! +//! \param[in] None +//! +//! \return 0 on success or -ve on error +//! +//**************************************************************************** +void initLinkLocalDB(void) +{ + httpRequest[0].charValues[0].characteristic = "version"; + httpRequest[0].serviceCallback = otaGetCallback; + + httpRequest[1].charValues[0].characteristic = "filename"; + httpRequest[1].serviceCallback = otaPutCallback; + + httpRequest[2].charValues[0].characteristic = "redled"; + httpRequest[2].charValues[0].value[0] = "off"; + httpRequest[2].charValues[0].value[1] = "on"; + httpRequest[2].charValues[0].value[2] = "toggle"; + httpRequest[2].charValues[1].characteristic = "orangeled"; + httpRequest[2].charValues[1].value[0] = "off"; + httpRequest[2].charValues[1].value[1] = "on"; + httpRequest[2].charValues[1].value[2] = "toggle"; + httpRequest[2].charValues[2].characteristic = "greenled"; + httpRequest[2].charValues[2].value[0] = "off"; + httpRequest[2].charValues[2].value[1] = "on"; + httpRequest[2].charValues[2].value[2] = "toggle"; + httpRequest[2].serviceCallback = lightGetCallback; + + httpRequest[3].charValues[0].characteristic = "redled"; + httpRequest[3].charValues[0].value[0] = "off"; + httpRequest[3].charValues[0].value[1] = "on"; + httpRequest[3].charValues[0].value[2] = "toggle"; + httpRequest[3].serviceCallback = lightPostCallback; + + httpRequest[4].charValues[0].characteristic = "axisx"; + httpRequest[4].charValues[1].characteristic = "axisy"; + httpRequest[4].charValues[2].characteristic = "axisz"; + httpRequest[4].charValues[3].characteristic = "temp"; + httpRequest[4].serviceCallback = sensorGetCallback; + + httpRequest[5].charValues[0].characteristic = "ssid"; + httpRequest[5].charValues[1].characteristic = "ipaddress"; + httpRequest[5].charValues[2].characteristic = "macaddress"; + httpRequest[5].charValues[3].characteristic = "appname"; + httpRequest[5].serviceCallback = deviceGetCallback; +} + +//***************************************************************************** +// +//! \brief This function scan netapp request and parse the payload +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] pPhrase pointer to HTTP metadata payload +//! +//! \param[in] payloadLen HTTP metadata or payload length +//! +//! \param[out] argcCallback count of input params to the service callback +//! +//! \param[out] argvCallback set of input params to the service callback +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t parseUrlEncoded(uint8_t requestIdx, + uint8_t * pPhrase, + uint16_t phraseLen, + uint8_t *argcCallback, + uint8_t **argvCallback) +{ + uint8_t *token; + uint8_t characteristic, value, isValueExpected, loopIdx; + int32_t Status = -1; + uint8_t *argvArray; + uint8_t remainingLen, actualLen; + uint16_t elementType; + + argvArray = *argvCallback; + /* it means parameters already exist - fast forward to the end of argv */ + if(*argcCallback > 0) + { + loopIdx = *argcCallback; + while(loopIdx > 0) + { + argvArray += ARGV_LEN_OFFSET; /* skip the type */ + argvArray += *argvArray; /* add the length */ + argvArray++; /* skip the length */ + + loopIdx--; + } + } + + /* check if values are expected per characteristic */ + /* it is a 2 steps procedure: */ + /* 1) check that '=' sign exists */ + /* 2) check that the value is not NULL */ + /* if not, return */ + isValueExpected = 0; + token = (uint8_t *)strchr((char *)pPhrase, '='); + if(token != NULL) + { /* it means no value supplied */ + if((*(token + 1) == '&') || (*(token + 1) == '\0')) + { + return(-1); + } + else + { + isValueExpected = 1; + } + } + + /* Parse payload list */ + token = (uint8_t *)strtok((char *)pPhrase, "=&"); + + if(NULL == token) /* it means there is no url encoded data */ + { + return(0); + } + + while(token && ((pPhrase + phraseLen) > token)) + { + Status = -1; + characteristic = 0; + + /* run over all possible characteristics, if exist */ + while(httpRequest[requestIdx].charValues[characteristic].characteristic + != NULL) + { + if(!strncmp((const char *)token, + (const char *)httpRequest[requestIdx].charValues[ + characteristic]. + characteristic, + strlen((const char *)httpRequest[requestIdx].charValues + [ + characteristic].characteristic))) + { + Status = 0; + + /* found a characteristic. save its index number */ + (*argcCallback)++; + elementType = setElementType(0, requestIdx, characteristic); + sl_Memcpy ((uint8_t*)argvArray, (uint8_t*)&elementType, + ARGV_LEN_OFFSET); + argvArray += ARGV_LEN_OFFSET; + *argvArray++ = 1; /* length field */ + *argvArray++ = characteristic; + /* remaining length is for cases where the last value is of + string type */ + remainingLen =(uint8_t) + (phraseLen -(uint8_t)(token -pPhrase) - + strlen((const char *)token) - 1); + + UART_PRINT ( + "[Link local task] characteristic is: %s\n\r", + (int8_t *)httpRequest[requestIdx]. + charValues[characteristic]. + characteristic); + break; + } + else + { + characteristic++; + } + } + /* it means the characteristics is not valid/known */ + if(-1 == Status) + { + return(Status); + } + + token = (uint8_t *)strtok(NULL, "=&"); + + if(isValueExpected) + { + Status = -1; + value = 0; + + if(token != NULL) + { + /* it means any value is OK */ + if(NULL == + httpRequest[requestIdx]. + charValues[characteristic].value[value]) + { + Status = 0; + + /* found a string value. copy its content */ + (*argcCallback)++; + elementType = setElementType(1, requestIdx, value); + sl_Memcpy ((uint8_t*)argvArray, (uint8_t*)&elementType, + ARGV_LEN_OFFSET); + argvArray += ARGV_LEN_OFFSET; + if(strlen((const char *)token) > remainingLen) + { + actualLen = remainingLen; + } + else + { + actualLen = strlen((const char *)token); + } + + *argvArray++ = (actualLen + 1); + sl_Memcpy(argvArray, token, actualLen); + argvArray += actualLen; + *argvArray++ = '\0'; + + UART_PRINT ("[Link local task] value is: %s\n\r", + (int8_t *)(argvArray - actualLen - 1)); + } + else + { + /* run over all possible values, if exist */ + while(httpRequest[requestIdx].charValues[characteristic]. + value[value] != NULL) + { + if(!strncmp((const char *)token, + (const char *)httpRequest[requestIdx]. + charValues[ + characteristic].value[value], + strlen((const char *)httpRequest[requestIdx + ].charValues[ + characteristic].value[value]))) + { + Status = 0; + + /* found a value. save its index number */ + (*argcCallback)++; + elementType = setElementType(1, requestIdx, value); + sl_Memcpy ((uint8_t*)argvArray, + (uint8_t*)&elementType, + ARGV_LEN_OFFSET); + argvArray += ARGV_LEN_OFFSET; + *argvArray++ = 1; /* length field */ + *argvArray++ = value; + + UART_PRINT ( + "[Link local task] value is: %s\n\r", + (int8_t *)httpRequest[requestIdx]. + charValues[ + characteristic].value[value]); + + break; + } + else + { + value++; + } + } + /* it means the value is not valid/known */ + if(-1 == Status) + { + return(Status); + } + } + } + token = (uint8_t *)strtok(NULL, (const char *)"=&"); + } + } + + return(Status); +} + +//***************************************************************************** +// +//! \brief This function maps header type to its string value +//! +//! \param[in] httpHeaderType http header type +//! +//! \param[out] httpHeaderText http header text +//! +//! \return none +//! +//**************************************************************************** +void convertHeaderType2Text(uint8_t httpHeaderType, + uint8_t **httpHeaderText) +{ + int i; + *httpHeaderText = NULL; + + for(i = 0; i < sizeof (g_HeaderFields) / sizeof(http_headerFieldType_t); + i++) + { + if(g_HeaderFields[i].headerType == httpHeaderType) + { + *httpHeaderText = (uint8_t *)(g_HeaderFields[i].headerText); + break; + } + } +} + +//***************************************************************************** +// +//! \brief This function scan netapp request and parse the metadata +//! +//! \param[in] requestType HTTP method (GET, POST, PUT or DEL) +//! +//! \param[in] pMetadata pointer to HTTP metadata +//! +//! \param[in] metadataLen HTTP metadata length +//! +//! \param[out] requestIdx request index to indicate the message +//! +//! \param[out] argcCallback count of input params to +//! the service callback +//! +//! \param[out] argvCallback set of input params to the service callback +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t parseHttpRequestMetadata(uint8_t requestType, + uint8_t * pMetadata, + uint16_t metadataLen, + uint8_t *requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback) +{ + uint8_t *pTlv; + uint8_t *pEnd; + + int32_t Status = -1; + uint8_t loopIdx; + uint8_t type; + uint16_t len; + uint32_t value; + uint8_t *typeText; + uint8_t nullTerminator; + uint8_t *argvArray; + uint16_t elementType; + + argvArray = *argvCallback; + + *requestIdx = 0xFF; + pTlv = pMetadata; + pEnd = pMetadata + metadataLen; + + if(metadataLen < 3) + { + UART_PRINT("[Link local task] Metadata parsing error\n\r"); + + return(-1); + } + + INFO_PRINT ("[Link local task] Metadata:\n\r"); + + while(pTlv < pEnd) + { + type = *pTlv; + pTlv++; + len = *(uint16_t *)pTlv; + pTlv += 2; + + convertHeaderType2Text(type, &typeText); + + if(typeText != NULL) + { + INFO_PRINT ("[Link local task] %s ", typeText); + } + + switch(type) + { + case SL_NETAPP_REQUEST_METADATA_TYPE_STATUS: + /* there are browsers that seem to send many 0 type for no reason */ + /* in this case, do not print anything */ + break; + + case SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_CONTENT_LEN: + /* it means there is a content length and URI is OK. Add it to the argv */ + if(0 == Status) + { + /* it means parameters already exist from query type */ + if(*argcCallback > 0) + { + loopIdx = *argcCallback; + while(loopIdx > 0) + { + argvArray += ARGV_LEN_OFFSET; /* skip the type */ + argvArray += *argvArray; /* add the length */ + argvArray++; /* skip the length */ + + loopIdx--; + } + } + + (*argcCallback)++; + /* add content type */ + elementType = setElementType(1, *requestIdx, CONTENT_LEN_TYPE); + sl_Memcpy ((uint8_t*)argvArray, (uint8_t*)&elementType, + ARGV_LEN_OFFSET); + argvArray += ARGV_LEN_OFFSET; + *argvArray++ = len; /* add content length */ + sl_Memcpy ((uint8_t*)argvArray, pTlv, len); + sl_Memcpy ((uint8_t*)&value, pTlv, len); + + INFO_PRINT ("%d\n\r", (uint32_t)value); + } + + break; + + case SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_REQUEST_URI: + /* this is the 1st stop in every http method. + zero out the character counter argument */ + *argcCallback = 0; + + for(loopIdx = 0; loopIdx < NUMBER_OF_URI_SERVICES; loopIdx++) + { + if((strncmp((const char *)pTlv, + (const char *)httpRequest[loopIdx].service, + strlen((const char *)httpRequest[loopIdx].service))) + == 0) + { + if(requestType == httpRequest[loopIdx].httpMethod) + { + Status = 0; + *requestIdx = httpRequest[loopIdx].requestIdx; + INFO_PRINT ("%s\n\r", httpRequest[loopIdx].service); + + break; + } + } + } + + if(Status != 0) + { + INFO_PRINT ("unknown service\n\r"); + } + + break; + + case SL_NETAPP_REQUEST_METADATA_TYPE_HTTP_QUERY_STRING: + if(0 == Status) + { + Status = parseUrlEncoded(*requestIdx, pTlv, len, argcCallback, + argvCallback); + + if(Status != 0) + { + INFO_PRINT ( + "query string in metadata section is not" + " valid/known\n\r"); + } + } + + break; + + default: + nullTerminator = *(pTlv + len); + *(pTlv + len) = '\0'; + INFO_PRINT("%s\n\r", pTlv); + *(pTlv + len) = nullTerminator; + + break; + } + pTlv += len; + } + + return(Status); +} + +//***************************************************************************** +// +//! \brief This function scan netapp request and parse the payload +//! +//! \param[in] requestIdx request index to indicate the message +//! +//! \param[in] pPayload pointer to HTTP payload +//! +//! \param[in] payloadLen HTTP payload length +//! +//! \param[out] argcCallback count of input params to the +//! service callback +//! +//! \param[out] argvCallback set of input params to the service callback +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t parseHttpRequestPayload(uint8_t requestIdx, + uint8_t * pPayload, + uint16_t payloadLen, + uint8_t *argcCallback, + uint8_t **argvCallback) +{ + int32_t Status = -1; + + Status = parseUrlEncoded(requestIdx, pPayload, payloadLen, argcCallback, + argvCallback); + + if(Status != 0) + { + UART_PRINT ( + "[Link local task] query string in payload section is " + "not valid/known\n\r"); + } + + return(Status); +} + +//***************************************************************************** +// +//! \brief This function checks that the content requested via HTTP +//! message exists +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \param[out] requestIdx request index to indicate the message +//! +//! \param[out] argcCallback count of input params to the service +//! callback +//! +//! \param[out] argvCallback set of input params to the service +//! callback +//! +//! +//! \return 0 on success else negative +//! +//**************************************************************************** +int32_t httpCheckContentInDB(SlNetAppRequest_t *netAppRequest, + uint8_t *requestIdx, + uint8_t *argcCallback, + uint8_t **argvCallback) +{ + int32_t Status = -1; + + if(netAppRequest->AppId != SL_NETAPP_HTTP_SERVER_ID) + { + return(Status); + } + + Status = + parseHttpRequestMetadata(netAppRequest->Type, + netAppRequest->requestData.pMetadata, + netAppRequest->requestData.MetadataLen, + requestIdx, argcCallback, + argvCallback); + + /* PUT does not contain parseable data - only POST does */ + if((0 == Status) && (netAppRequest->requestData.PayloadLen != 0) && + (netAppRequest->Type != SL_NETAPP_REQUEST_HTTP_PUT)) + { + Status = + parseHttpRequestPayload(*requestIdx, + netAppRequest->requestData.pPayload, + netAppRequest->requestData.PayloadLen, + argcCallback, + argvCallback); + } + + return(Status); +} + +//***************************************************************************** +// +//! \brief This function parse and execute HTTP GET requests +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return None +//! +//**************************************************************************** +void httpGetHandler(SlNetAppRequest_t *netAppRequest) +{ + uint16_t metadataLen; + int32_t Status; + uint8_t requestIdx; + + uint8_t argcCallback; + uint8_t *argvArray; + uint8_t **argvCallback = &argvArray; + + argvArray = gHttpGetBuffer; + + Status = httpCheckContentInDB(netAppRequest, &requestIdx, &argcCallback, + argvCallback); + + if(Status < 0) + { + metadataLen = + prepareGetMetadata(Status, strlen ( + (const char *)pageNotFound), + HttpContentTypeList_TextHtml); + + sl_NetAppSend (netAppRequest->Handle, metadataLen, gMetadataBuffer, + (SL_NETAPP_REQUEST_RESPONSE_FLAGS_CONTINUATION | + SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA)); + INFO_PRINT("[Link local task] Metadata Sent, len = %d \n\r", + metadataLen); +/* mark as last segment */ + sl_NetAppSend (netAppRequest->Handle, + strlen ((const char *)pageNotFound), + (uint8_t *)pageNotFound,0); + + INFO_PRINT("[Link local task] Data Sent, len = %d\n\r", + strlen ((const char *)pageNotFound)); + } + else + { + httpRequest[requestIdx].serviceCallback(requestIdx, &argcCallback, + argvCallback, + netAppRequest); + } +} + +//***************************************************************************** +// +//! \brief This function parse and execute HTTP POST/PUT requests +//! +//! \param[in] netAppRequest netapp request structure +//! +//! \return None +//! +//**************************************************************************** +void httpPostHandler(SlNetAppRequest_t *netAppRequest) +{ + uint16_t metadataLen; + int32_t Status; + uint8_t requestIdx; + + uint8_t argcCallback; + uint8_t *argvArray; + uint8_t **argvCallback = &argvArray; + + argvArray = gHttpPostBuffer; + + Status = httpCheckContentInDB(netAppRequest,&requestIdx,&argcCallback, + argvCallback); + + if(Status < 0) + { + metadataLen = preparePostMetadata(Status); + + sl_NetAppSend (netAppRequest->Handle, metadataLen, gMetadataBuffer, + SL_NETAPP_REQUEST_RESPONSE_FLAGS_METADATA); + } + else + { + httpRequest[requestIdx].serviceCallback(requestIdx, &argcCallback, + argvCallback, + netAppRequest); + } +} + +//**************************************************************************** +// MAIN FUNCTION +//**************************************************************************** + +//***************************************************************************** +// +//! \brief This function fetches the device type and prints it +//! +//! \param[in] None +//! +//! \return device type +//! +//**************************************************************************** +uint32_t getDeviceType(void) +{ + uint32_t deviceType; + uint16_t configSize = 0; + uint8_t configOpt = SL_DEVICE_GENERAL_VERSION; + SlDeviceVersion_t ver = {0}; + configSize = sizeof(SlDeviceVersion_t); + + /* Print device version info. */ + sl_DeviceGet(SL_DEVICE_GENERAL, &configOpt, &configSize, (uint8_t*)(&ver)); + + deviceType = ver.ChipId & 0xFF; + /* Update deviceType to 323XX or 3220X */ + if((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_DIEID_READ_REG4) >> 24) & 0x02) + { + deviceType |= (0x01 << 8); + } + + switch(deviceType) + { + case DEV_TYPE_CC323XR: // 323xR + UART_PRINT("[Provisioning task] detected device is CC323xR\n\r"); + break; + case DEV_TYPE_CC323XRS: // 323xRS + UART_PRINT("[Provisioning task] detected device is CC323xRS\n\r"); + break; + case DEV_TYPE_CC323XFS: // 323xFS + UART_PRINT("[Provisioning task] detected device is CC323xSF\n\r"); + break; + case DEV_TYPE_CC3220R: // 3220R + UART_PRINT("[Provisioning task] detected device is CC3220R\n\r"); + break; + case DEV_TYPE_CC3220RS: // 3220RS + UART_PRINT("[Provisioning task] detected device is CC3220RS\n\r"); + break; + case DEV_TYPE_CC3220FS: // 3220FS + UART_PRINT("[Provisioning task] detected device is CC3220SF\n\r"); + break; + default: + break; + } + + return(deviceType); +} + +//***************************************************************************** +// +//! \brief This task handles LinkLocal transactions with the client +//! +//! \param[in] None +//! +//! \return None +//! +//**************************************************************************** +void * linkLocalTask(void *pvParameters) +{ + mq_attr attr; + int32_t msgqRetVal; + I2C_Params i2cParams; + + /* initializes I2C */ + I2C_Params_init(&i2cParams); + i2cParams.bitRate = I2C_400kHz; + // i2cHandle = I2C_open(Board_I2C0, &i2cParams); + // if(i2cHandle == NULL) + // { + // //UART_PRINT("[Link local task] Error Initializing I2C\n\r"); + // } + + /* Setup mutex operations for sensors reading */ + sensorLockObj = malloc(sizeof(pthread_mutex_t)); + pthread_mutex_init(sensorLockObj, (pthread_mutexattr_t*)NULL); + + /* initializes mailbox for http messages */ + attr.mq_maxmsg = 10; /* queue size */ + attr.mq_msgsize = sizeof(SlNetAppRequest_t*); /* Size of message */ + linkLocalMQueue = mq_open("linklocal msg q", O_CREAT, 0, &attr); + if(linkLocalMQueue == NULL) + { + UART_PRINT("[Link local task] could not create msg queue\n\r"); + while(1) + { + ; + } + } + + initLinkLocalDB(); + + /* waits for valid local connection - via provisioning task */ + sem_wait(&Provisioning_ControlBlock.provisioningDoneSignal); + + while(1) + { + SlNetAppRequest_t *netAppRequest; + + msgqRetVal = + mq_receive(linkLocalMQueue, (char *)&netAppRequest, + sizeof(SlNetAppRequest_t*), NULL); + if(msgqRetVal < 0) + { + UART_PRINT( + "[Link local task] could not receive element from msg \ + queue\n\r"); + while(1) + { + ; + } + } + + INFO_PRINT( + "[Link local task] NetApp Request Received - handle from main " + "context AppId = %d, Type = %d, Handle = %d\n\r", + netAppRequest->AppId, netAppRequest->Type, netAppRequest->Handle); + + INFO_PRINT("[Link local task] Metadata len = %d\n\r", + netAppRequest->requestData.MetadataLen); + + if((netAppRequest->Type == SL_NETAPP_REQUEST_HTTP_GET) || + (netAppRequest->Type == SL_NETAPP_REQUEST_HTTP_DELETE)) + { + if(netAppRequest->Type == SL_NETAPP_REQUEST_HTTP_GET) + { + UART_PRINT("[Link local task] HTTP GET Request\n\r"); + } + else + { + UART_PRINT("[Link local task] HTTP DELETE Request\n\r"); + } + + httpGetHandler(netAppRequest); + } + else if((netAppRequest->Type == SL_NETAPP_REQUEST_HTTP_POST) || + (netAppRequest->Type == SL_NETAPP_REQUEST_HTTP_PUT)) + { + if(netAppRequest->Type == SL_NETAPP_REQUEST_HTTP_POST) + { + UART_PRINT("[Link local task] HTTP POST Request\n\r"); + } + else + { + UART_PRINT("[Link local task] HTTP PUT Request\n\r"); + } + + INFO_PRINT( + "[Link local task] Data received, len = %d, flags= %x\n\r", + netAppRequest->requestData.PayloadLen, + netAppRequest->requestData.Flags); + + httpPostHandler(netAppRequest); + } + + if(netAppRequest->requestData.MetadataLen > 0) + { + free (netAppRequest->requestData.pMetadata); + } + if(netAppRequest->requestData.PayloadLen > 0) + { + free (netAppRequest->requestData.pPayload); + } + + free (netAppRequest); + } +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_ProvisioningTask.c b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_ProvisioningTask.c new file mode 100644 index 00000000..53422724 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_ProvisioningTask.c @@ -0,0 +1,1547 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +/* standard includes */ +#include +#include + +/* driverlib Header files */ +#include +#include +#include + +/* TI-DRIVERS Header files */ +#include +#include +#include +#include +#include + +/* Example/Board Header files */ +#include +#include +#include +// #include "platform.h" +// #include "ota_archive.h" + +/* POSIX Header files */ +#include +#include + +/* In msecs. Used to detect good/bad sl_start() */ +#define ASYNC_EVT_TIMEOUT (5000) +/*In sec. Used for connecting to stored profile */ +#define PROFILE_ASYNC_EVT_TIMEOUT (5) +#define LED_TOGGLE_CONFIGURATION_TIMEOUT (1000) /* In msecs */ +#define LED_TOGGLE_CONFIRMATION_TIMEOUT (500) /* In msecs */ +#define LED_TOGGLE_CONNECTION_TIMEOUT (250) /* In msecs */ +/* Provisioning inactivity timeout in seconds */ +#define PROVISIONING_INACTIVITY_TIMEOUT (600) + +#define ROLE_SELECTION_BY_SL (0xFF) + +/* OCP register used to store device role when coming out of hibernate */ +#define OCP_REGISTER_INDEX (0) +/* if ocpRegOffset is set -> AP role, otherwise -> STATION role */ +#define OCP_REGISTER_OFFSET (10) + +/*! + * \brief Provisioning modes + */ +typedef enum +{ + PrvsnMode_AP, /* AP provisioning (AP role) */ + PrvsnMode_SC, /* Smart Config provisioning (STA role) */ + PrvsnMode_APSC /* AP + Smart Config provisioning (AP role) */ +}PrvsnMode; + +/** By default, setting the provisioning mode to AP + Smart Config. + * Other values could be PrvsnMode_SC or PrvsnMode_AP + */ +#define PROVISIONING_MODE PrvsnMode_APSC + +/*! + * \brief Provisioning status + */ +typedef enum +{ + PrvsnStatus_Stopped, + PrvsnStatus_InProgress +}PrvsnStatus; + +/* + * \brief Application state's context + */ +typedef struct _Provisioning_AppContext_t_ +{ + PrvnState currentState; /* Current state of provisioning */ + uint32_t pendingEvents; /* Events pending to be processed */ +/* SimpleLink's role - STATION/AP/P2P */ + uint8_t role; +/* SimpleLink's default role, try not to change this */ + uint8_t defaultRole; + PrvsnMode provisioningMode; /* Provisioning Mode */ + PrvsnStatus provisioningStatus; /* */ + + uint32_t asyncEvtTimeout; /* Timeout value*/ + + uint32_t ledToggleTimeout; /* Timeout value */ +}Provisioning_AppContext; + +/*! + * \brief Function pointer to the event handler + */ +typedef int32_t (*fptr_EventHandler)(void); + +/*! + * \brief Entry in the lookup table + */ +typedef struct +{ + fptr_EventHandler p_evtHndl; /* Pointer to the event handler */ + PrvnState nextState; /* Next state of provisioning */ +}s_TblEntry; + + + +/**************************************************************************** + LOCAL FUNCTION PROTOTYPES +****************************************************************************/ + +//***************************************************************************** +// +//! \brief This function initializes provisioning process +//! +//! \param[in] None +//! +//! \return None +//! +//**************************************************************************** +void provisioningInit(void); + +//***************************************************************************** +// +//! \brief This function starts provisioning process +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +int32_t provisioningStart(void); + +//***************************************************************************** +// +//! \brief main provisioning loop +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t provisioningAppTask(void); + +//***************************************************************************** +//! \brief This function puts the device in its default state. It: +//! - Set the mode to AP +//! - Configures connection policy to Auto +//! - Deletes all the stored profiles +//! - Enables DHCP +//! - Disable IPV6 +//! - Disables Scan policy +//! - Sets Tx power to maximum +//! - Sets power policy to normal +//! - Unregister mDNS services +//! - Remove all filters +//! +//! IMPORTANT NOTE - This is an example reset function, user must +//! update this function to match the application settings. +//! +//! \param none +//! \return On success, zero is returned. On error, negative is returned +//***************************************************************************** +static int32_t ConfigureSimpleLinkToDefaultState(void); + +//***************************************************************************** +// +//! \brief This function starts the SimpleLink in the configured role. +//! The device notifies the host asynchronously +//! when the initialization is +//! completed +//! +//! \param[in] role Device shall be configured in this role +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t InitSimplelink(uint8_t const role); + +//***************************************************************************** +// +//! \brief This function handles 'APP_EVENT_STARTED' event +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t HandleStrtdEvt(void); + +//***************************************************************************** +// +//! \brief This function starts the async-event timer +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t StartAsyncEvtTimer(uint32_t timeout); + +//***************************************************************************** +// +//! \brief This function stops the async-event timer +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t StopAsyncEvtTimer(void); + +//***************************************************************************** +// +//! \brief internal error detection during provisioning process +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t ReportError(void); + +//***************************************************************************** +// +//! \brief internal report current state during provisioning process +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t ReportSM(void); + +//***************************************************************************** +// +//! \brief steps following a successful provisioning process +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t ReportSuccess(void); + +//***************************************************************************** +// +//! \brief wait for connection following a successful provisioning process +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t WaitForConn(void); + +//***************************************************************************** +// +//! \brief checks for local link connecion to peer device +//! when set as Station, checks for AP connection +//! when set as Access Point, no check is required +//! +//! \param[out] deviceRole role of the device +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t validateLocalLinkConnection(SlWlanMode_e *deviceRole); + +//***************************************************************************** +// +//! Notify if device return to factory image +//! +//! \param None +//! +//! \return None +// +//***************************************************************************** +static void NotifyReturnToFactoryImage(void); + +/**************************************************************************** + GLOBAL VARIABLES +****************************************************************************/ +/*! + * \brief Application state's context + */ +Provisioning_AppContext gAppCtx; + +timer_t gAsyncEventTimer; +timer_t gLedTimer; +/*! + * \brief Application lookup/transition table + */ +const s_TblEntry gProvisioningTransitionTable[PrvnState_Max][PrvnEvent_Max] = +{ + /* PrvnState_Init */ + { + /* Event: PrvnEvent_Triggered */ + {provisioningStart, PrvnState_Idle }, + /* Event: PrvnEvent_Started */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_StartFailed */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_ConfirmationSuccess */ + /* special case where confirmation is received after application is + restarted and NWP is still in provisioning */ + {ReportSM, PrvnState_Completed }, + /* in this case, need to move to COMPLETED state */ + /* Event: PrvnEvent_ConfirmationFailed */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Stopped */ + /* in case of auto provisioning */ + {ReportSM, PrvnState_Init }, + /* Event: PrvnEvent_WaitForConn */ + {ReportSM, PrvnState_Error }, + /* Event: PrvnEvent_Timeout */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Error */ + {ReportError, PrvnState_Error }, + }, + /* PrvnState_Idle */ + { + /* Event: PrvnEvent_Triggered */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Started */ + {HandleStrtdEvt, PrvnState_WaitForConfirmation }, + /* Event: PrvnEvent_StartFailed */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_ConfirmationSuccess */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_ConfirmationFailed */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Stopped */ + {ReportSM, PrvnState_Init }, + /* Event: PrvnEvent_WaitForConn */ + {ReportSM, PrvnState_Error }, + /* Event: PrvnEvent_Timeout */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Error */ + {ReportError, PrvnState_Error }, + }, + /* PrvnState_WaitForConfirmation */ + { + /* Event: PrvnEvent_Triggered */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Started */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_StartFailed */ + {ReportSM, PrvnState_Idle }, + /* Event: PrvnEvent_ConfirmationSuccess */ + {ReportSM, PrvnState_Completed }, + /* Event: PrvnEvent_ConfirmationFailed */ + {ReportSM, PrvnState_WaitForConfirmation }, + /* Event: PrvnEvent_Stopped */ + {ReportSM, PrvnState_Init }, + /* Event: PrvnEvent_WaitForConn */ + {ReportSM, PrvnState_Error }, + /* Event: PrvnEvent_Timeout */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Error */ + {ReportError, PrvnState_Error }, + }, + /* PrvnState_Completed */ + { + /* Event: PrvnEvent_Triggered */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Started */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_StartFailed */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_ConfirmationSuccess */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_ConfirmationFailed */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Stopped */ + {ReportSuccess, PrvnState_Init }, + /* Event: PrvnEvent_WaitForConn */ + /* this state should cover cases where + feedback failed but profile exists */ + {WaitForConn, PrvnState_Init }, + /* Event: PrvnEvent_Timeout */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Error */ + {ReportError, PrvnState_Error }, + }, + /* PrvnState_Error */ + { + /* Event: PrvnEvent_Triggered */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Started */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_StartFailed */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_ConfirmationSuccess */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_ConfirmationFailed */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Stopped */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_WaitForConn */ + {ReportSM, PrvnState_Error }, + /* Event: PrvnEvent_Timeout */ + {ReportError, PrvnState_Error }, + /* Event: PrvnEvent_Error */ + {ReportError, PrvnState_Error }, + } +}; + +Provisioning_CB Provisioning_ControlBlock; + +/***************************************************************************** + Callback Functions +*****************************************************************************/ + +//***************************************************************************** +// +//! \brief The device init callback +//! +//! \param[in] status Mode the device is configured in +//! +//! \return None +//! +//**************************************************************************** +void SimpleLinkInitCallback(uint32_t status, + SlDeviceInitInfo_t *DeviceInitInfo) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + + // UART_PRINT("[Provisioning task] Device started in %s role\n\r", + // (0 == status) ? "Station" : \ + // ((2 == status) ? "AP" : "P2P")); + + /** While provisioning is ongoing, the appropriate role is choosen by the + * device itself, and host can remain agnostic to these details + */ + if(pCtx->role == ROLE_SELECTION_BY_SL) + { + SignalProvisioningEvent(PrvnEvent_Started); + } + else + { + /* Either trigger an error/started event here */ + if(pCtx->role == status) + { + SignalProvisioningEvent(PrvnEvent_Started); + } + else + { + // UART_PRINT("[Provisioning task] But the intended role is %s \n\r", \ + // (0 == pCtx->role) ? "Station" : \ + // ((2 == pCtx->role) ? "AP" : "P2P")); + SignalProvisioningEvent(PrvnEvent_Error); + } + } +} + +//***************************************************************************** +// +//! \brief The interrupt handler for the async-evt timer +//! +//! \param[in] None +//! +//! \return None +//! +//**************************************************************************** +void AsyncEvtTimerIntHandler(sigval val) +{ + /* Clear the timer interrupt. */ + Platform_TimerInterruptClear(); + + /* One Shot */ + /* TBD - Check role for One-shot/periodic */ + StopAsyncEvtTimer(); + SignalProvisioningEvent(PrvnEvent_Timeout); +} + +//***************************************************************************** +// +//! \brief The interrupt handler for the LED timer +//! +//! \param[in] None +//! +//! \return None +//! +//**************************************************************************** +void LedTimerIntHandler(sigval val) +{ + /* Clear the timer interrupt. */ + Platform_TimerInterruptClear(); + + GPIO_toggle(Board_GPIO_LED0); +} + +//***************************************************************************** +// Local Functions +//***************************************************************************** + +//***************************************************************************** +// +//! \brief This function initializes provisioning process +//! +//! \param[in] None +//! +//! \return None +//! +//**************************************************************************** +void provisioningInit(void) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + + Platform_TimerInit(AsyncEvtTimerIntHandler, &gAsyncEventTimer); + + /** By default, setting the provisioning mode to AP + Smart Config. + * Other values could be PrvsnMode_SC or PrvsnMode_AP + */ + pCtx->provisioningMode = PROVISIONING_MODE; + switch(pCtx->provisioningMode) + { + case PrvsnMode_APSC: pCtx->defaultRole = ROLE_AP; + break; + + case PrvsnMode_AP: pCtx->defaultRole = ROLE_AP; + break; + + case PrvsnMode_SC: pCtx->defaultRole = ROLE_STA; + break; + } + + /* Provisioning has not started yet */ + pCtx->provisioningStatus = PrvsnStatus_Stopped; + pCtx->currentState = PrvnState_Init; +} + +//***************************************************************************** +// +//! \brief This function starts provisioning process +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +int32_t provisioningStart(void) +{ + int32_t retVal = 0; + Provisioning_AppContext *const pCtx = &gAppCtx; + SlDeviceVersion_t ver = {0}; + uint8_t configOpt = 0; + uint16_t configLen = 0; + + /* check if provisioning is running */ + /* if auto provisioning - the command stops it automatically */ + /* in case host triggered provisioning - need to stop it explicitly */ + configOpt = SL_DEVICE_GENERAL_VERSION; + configLen = sizeof(ver); + retVal = + sl_DeviceGet(SL_DEVICE_GENERAL, &configOpt, &configLen, + (uint8_t *)(&ver)); + if(SL_RET_CODE_PROVISIONING_IN_PROGRESS == retVal) + { + // UART_PRINT( + // "[Provisioning task] Provisioning is already running," + // " stopping it...\r\n"); + retVal = + sl_WlanProvisioning(SL_WLAN_PROVISIONING_CMD_STOP,ROLE_STA,0,NULL, + 0); + + /* return SL_RET_CODE_PROVISIONING_IN_PROGRESS to indicate the SM + to stay in the same state*/ + return(SL_RET_CODE_PROVISIONING_IN_PROGRESS); + } + + /* + IMPORTANT NOTE - This is an example reset function, user must update + this function to match the application settings. + */ + retVal = ConfigureSimpleLinkToDefaultState(); + + if(retVal < 0) + { + // UART_PRINT( + // "[Provisioning task] Failed to configure the device in its default " + // "state \n\r"); + return(retVal); + } + + // UART_PRINT( + // "[Provisioning task] Device is configured \ + // in default state \n\r" ); + + /* Provisioning has not started yet */ + pCtx->provisioningStatus = PrvsnStatus_Stopped; + + /* Set the LED toggling timeout before starting the timer */ + pCtx->ledToggleTimeout = LED_TOGGLE_CONFIGURATION_TIMEOUT; + StartLedEvtTimer(pCtx->ledToggleTimeout); + + retVal = InitSimplelink(pCtx->defaultRole); + if(retVal < 0) + { + // UART_PRINT("[Provisioning task] Failed to initialize the device\n\r"); + return(retVal); + } + + return(retVal); +} + +//***************************************************************************** +// +//! \brief main provisioning loop +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t provisioningAppTask(void) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + s_TblEntry *pEntry = NULL; + uint16_t eventIdx = 0; + int32_t retVal = 0; + + for(eventIdx = 0; eventIdx < PrvnEvent_Max; eventIdx++) + { + if(0 != (pCtx->pendingEvents & (1 << eventIdx))) + { + if(eventIdx != PrvnEvent_Triggered) + { + /** Events received - Stop the respective timer if its still + * running + */ + StopAsyncEvtTimer(); + } + + pEntry = + (s_TblEntry *)&gProvisioningTransitionTable[pCtx->currentState] + [ + eventIdx]; + if(NULL != pEntry->p_evtHndl) + { + /* no state transition is required */ + retVal = pEntry->p_evtHndl(); + if(retVal == SL_RET_CODE_PROVISIONING_IN_PROGRESS) + { + pCtx->pendingEvents &= ~(1 << eventIdx); + continue; + } + else if(retVal < 0) + { + // UART_PRINT( + // "[Provisioning task]" + // " Event handler failed, error=%d\n\r", + // retVal); + while(1) /*this is to let other tasks recover by + mcu reset, e.g. in case of switching + to AP mode */ + { + usleep(1000); + } + } + } + + if(pEntry->nextState != pCtx->currentState) + { + pCtx->currentState = pEntry->nextState; + } + + pCtx->pendingEvents &= ~(1 << eventIdx); + } + + /* No more events to handle. Break.! */ + if(0 == pCtx->pendingEvents) + { + break; + } + } + + usleep(1000); + + return(0); +} + +//***************************************************************************** +//! \brief This function puts the device in its default state. It: +//! - Set the mode to AP +//! - Configures connection policy to Auto +//! - Deletes all the stored profiles +//! - Enables DHCP +//! - Disable IPV6 +//! - Disables Scan policy +//! - Sets Tx power to maximum +//! - Sets power policy to normal +//! - Unregister mDNS services +//! - Remove all filters +//! +//! IMPORTANT NOTE - This is an example reset function, user must +//! update this function to match the application settings. +//! +//! \param none +//! \return On success, zero is returned. On error, negative is returned +//***************************************************************************** +static int32_t ConfigureSimpleLinkToDefaultState(void) +{ + SlWlanRxFilterOperationCommandBuff_t RxFilterIdMask; + + uint8_t ucConfigOpt = 0; + uint16_t ifBitmap = 0; + uint8_t ucPower = 0; + + int32_t ret = -1; + int32_t mode = -1; + + memset(&RxFilterIdMask,0,sizeof(SlWlanRxFilterOperationCommandBuff_t)); + + /* Start Simplelink - Blocking mode */ + mode = sl_Start(0, 0, 0); + if(SL_RET_CODE_DEV_ALREADY_STARTED != mode) + { + ASSERT_ON_ERROR(mode); + } + + /* If the device is not in AP mode, try configuring it in AP mode + in case device is already started + (got SL_RET_CODE_DEV_ALREADY_STARTED error code), then mode would remain + -1 and in this case we do not know the role. Move to AP role anyway */ + if(ROLE_AP != mode) + { + /* Switch to AP role and restart */ + ret = sl_WlanSetMode(ROLE_AP); + ASSERT_ON_ERROR(ret); + + ret = sl_Stop(SL_STOP_TIMEOUT); + ASSERT_ON_ERROR(ret); + + ret = sl_Start(0, 0, 0); + ASSERT_ON_ERROR(ret); + + /* Check if the device is in AP again */ + if(ROLE_AP != ret) + { + return(ret); + } + } + + /* Set connection policy to Auto (no AutoProvisioning) */ + ret = sl_WlanPolicySet(SL_WLAN_POLICY_CONNECTION, + SL_WLAN_CONNECTION_POLICY(1, 0, 0, 0), NULL, 0); + ASSERT_ON_ERROR(ret); + + /* Remove all profiles */ + ret = sl_WlanProfileDel(0xFF); + ASSERT_ON_ERROR(ret); + + /* Enable DHCP client */ + ret = sl_NetCfgSet(SL_NETCFG_IPV4_STA_ADDR_MODE,SL_NETCFG_ADDR_DHCP,0,0); + ASSERT_ON_ERROR(ret); + + /* Disable IPV6 */ + ifBitmap = 0; + ret = + sl_NetCfgSet(SL_NETCFG_IF, SL_NETCFG_IF_STATE, sizeof(ifBitmap), + (uint8_t *)&ifBitmap); + ASSERT_ON_ERROR(ret); + + /* Disable scan */ + ucConfigOpt = SL_WLAN_SCAN_POLICY(0, 0); + ret = sl_WlanPolicySet(SL_WLAN_POLICY_SCAN, ucConfigOpt, NULL, 0); + ASSERT_ON_ERROR(ret); + + /* Set Tx power level for station mode + Number between 0-15, as dB offset from max power - 0 will + set max power */ + ucPower = 0; + ret = sl_WlanSet(SL_WLAN_CFG_GENERAL_PARAM_ID, + SL_WLAN_GENERAL_PARAM_OPT_STA_TX_POWER, 1, + (uint8_t *)&ucPower); + ASSERT_ON_ERROR(ret); + + /* Set PM policy to normal */ + ret = sl_WlanPolicySet(SL_WLAN_POLICY_PM, SL_WLAN_NORMAL_POLICY, NULL, 0); + ASSERT_ON_ERROR(ret); + + /* Unregister mDNS services */ + ret = sl_NetAppMDNSUnRegisterService(0, 0, 0); + ASSERT_ON_ERROR(ret); + + /* Remove all 64 filters (8*8) */ + memset(RxFilterIdMask.FilterBitmap, 0xFF, 8); + ret = sl_WlanSet(SL_WLAN_RX_FILTERS_ID, + SL_WLAN_RX_FILTER_REMOVE, + sizeof(SlWlanRxFilterOperationCommandBuff_t), + (uint8_t *)&RxFilterIdMask); + ASSERT_ON_ERROR(ret); + + ret = sl_Stop(SL_STOP_TIMEOUT); + ASSERT_ON_ERROR(ret); + + return(ret); +} + +//***************************************************************************** +// +//! \brief This function starts the SimpleLink in the configured role. +//! The device notifies the host asynchronously +//! when the initialization is +//! completed +//! +//! \param[in] role Device shall be configured in this role +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t InitSimplelink(uint8_t const role) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + int32_t retVal = -1; + + pCtx->role = role; + pCtx->pendingEvents = 0; + + retVal = sl_Start(0, 0, (P_INIT_CALLBACK)SimpleLinkInitCallback); + ASSERT_ON_ERROR(retVal); + + /* Start timer */ + pCtx->asyncEvtTimeout = ASYNC_EVT_TIMEOUT; + retVal = StartAsyncEvtTimer(pCtx->asyncEvtTimeout); + ASSERT_ON_ERROR(retVal); + + return(retVal); +} + +//***************************************************************************** +// +//! \brief This function handles 'APP_EVENT_STARTED' event +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** + +static int32_t HandleStrtdEvt(void) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + int32_t retVal = 0; + + /** If provisioning has already started, don't do anything here + * The state-machine shall keep waiting for the provisioning status + */ + if(PrvsnStatus_Stopped == pCtx->provisioningStatus) + { + SlDeviceVersion_t firmwareVersion = {0}; + + uint8_t ucConfigOpt = 0; + uint16_t ucConfigLen = 0; + + /* Get the device's version-information */ + ucConfigOpt = SL_DEVICE_GENERAL_VERSION; + ucConfigLen = sizeof(firmwareVersion); + retVal = sl_DeviceGet(SL_DEVICE_GENERAL, &ucConfigOpt, \ + &ucConfigLen, + (unsigned char *)(&firmwareVersion)); + ASSERT_ON_ERROR(retVal); + + // UART_PRINT("[Provisioning task] Host Driver Version: %s\n\r", + // SL_DRIVER_VERSION); + // UART_PRINT( + // "[Provisioning task] Build Version " + // "%d.%d.%d.%d.31.%d.%d.%d.%d.%d.%d.%d.%d\n\r", \ + // firmwareVersion.NwpVersion[0], \ + // firmwareVersion.NwpVersion[1], \ + // firmwareVersion.NwpVersion[2], \ + // firmwareVersion.NwpVersion[3], \ + // firmwareVersion.FwVersion[0], \ + // firmwareVersion.FwVersion[1], \ + // firmwareVersion.FwVersion[2], \ + // firmwareVersion.FwVersion[3], \ + // firmwareVersion.PhyVersion[0], \ + // firmwareVersion.PhyVersion[1], \ + // firmwareVersion.PhyVersion[2], \ + // firmwareVersion.PhyVersion[3]); + + /* Start provisioning process */ + // UART_PRINT("[Provisioning task] Starting Provisioning - "); + // UART_PRINT( + // "[Provisioning task] in mode %d (0 = AP, 1 = SC, 2 = AP+SC)\r\n", + // pCtx->provisioningMode); + + retVal = sl_WlanProvisioning(pCtx->provisioningMode, ROLE_STA, + PROVISIONING_INACTIVITY_TIMEOUT, NULL,0); + ASSERT_ON_ERROR(retVal); + + pCtx->provisioningStatus = PrvsnStatus_InProgress; + // UART_PRINT( + // "[Provisioning task] Provisioning Started. Waiting to " + // "be provisioned..!! \r\n"); + } + + return(retVal); +} + +//***************************************************************************** +// +//! \brief This function starts the async-event timer +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t StartAsyncEvtTimer(uint32_t timeout) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + + pCtx->asyncEvtTimeout = timeout; + Platform_TimerStart(pCtx->asyncEvtTimeout, gAsyncEventTimer, 0); + return(0); +} + +//***************************************************************************** +// +//! \brief This function stops the async-event timer +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t StopAsyncEvtTimer(void) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + + if(0 != pCtx->asyncEvtTimeout) + { + Platform_TimerStop(gAsyncEventTimer); + pCtx->asyncEvtTimeout = 0; + } + + return(0); +} + +//***************************************************************************** +// +//! \brief internal error detection during provisioning process +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t ReportError(void) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + uint16_t eventIdx = 0; + + for(eventIdx = 0; eventIdx < PrvnEvent_Max; eventIdx++) + { + if(0 != (pCtx->pendingEvents & (1 << eventIdx))) + { + break; + } + } + + // UART_PRINT("[Provisioning task]" + // " Unexpected SM: State = %d, Event = %d\n\r",\ + // pCtx->currentState, eventIdx); + return(-1); +} + +//***************************************************************************** +// +//! \brief internal report current state during provisioning process +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t ReportSM(void) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + uint16_t eventIdx = 0; + + for(eventIdx = 0; eventIdx < PrvnEvent_Max; eventIdx++) + { + if(0 != (pCtx->pendingEvents & (1 << eventIdx))) + { + break; + } + } + + if(PrvnEvent_Stopped == eventIdx) + { + StopLedEvtTimer(); + GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); + } + + return(0); +} + +//***************************************************************************** +// +//! \brief steps following a successful provisioning process +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t ReportSuccess(void) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + uint16_t ConfigOpt; + uint16_t ipLen; + SlNetCfgIpV4Args_t ipV4 = {0}; + int32_t retVal; + + // UART_PRINT("[Provisioning task] " + // "Provisioning completed successfully..!\n\r"); + pCtx->provisioningStatus = PrvsnStatus_Stopped; + StopLedEvtTimer(); + + /* Get the device's IP address */ + ipLen = sizeof(SlNetCfgIpV4Args_t); + ConfigOpt = 0; + retVal = + sl_NetCfgGet(SL_NETCFG_IPV4_STA_ADDR_MODE,&ConfigOpt,&ipLen, + (uint8_t *)&ipV4); + if(retVal == 0) + { + // UART_PRINT("[Provisioning task] IP address is %d.%d.%d.%d\n\r", \ + // SL_IPV4_BYTE(ipV4.Ip,3), \ + // SL_IPV4_BYTE(ipV4.Ip,2), \ + // SL_IPV4_BYTE(ipV4.Ip,1), \ + // SL_IPV4_BYTE(ipV4.Ip,0)); + } + + GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_ON); + + /* signal to linklocal task */ + sem_post(&Provisioning_ControlBlock.provisioningDoneSignal); + + /* signal to report server task */ + sem_post(&Provisioning_ControlBlock.provisioningConnDoneToOtaServerSignal); + + return(0); +} + +//***************************************************************************** +// +//! \brief wait for connection following a successful provisioning process +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t WaitForConn(void) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + struct timespec ts; + int32_t retVal; + + // while(((!IS_IPV6L_ACQUIRED(OutOfBox_ControlBlock.status) || + // !IS_IPV6G_ACQUIRED(OutOfBox_ControlBlock.status)) && + // !IS_IP_ACQUIRED(OutOfBox_ControlBlock.status)) || + // !IS_CONNECTED(OutOfBox_ControlBlock.status)) + // { + // clock_gettime(CLOCK_REALTIME, &ts); + // ts.tv_sec += PROFILE_ASYNC_EVT_TIMEOUT; + + // retVal = sem_timedwait(&Provisioning_ControlBlock.connectionAsyncEvent, + // &ts); + // /* freertos return -1 in case of timeout */ + // if((retVal == 116) || (retVal == -1)) + // { + // UART_PRINT( + // "[Provisioning task] Cannot connect to AP or profile does" + // " not exist\n\r"); + // GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); + // /* this state is set so that PrvnEvent_Triggered + // would invoke provisioning again */ + // pCtx->currentState = PrvnState_Init; + // SignalProvisioningEvent(PrvnEvent_Triggered); + + // return(0); + // } + // } + + // UART_PRINT("[Provisioning task] Connection to AP succeeded\n\r"); + + return(ReportSuccess()); +} + +//***************************************************************************** +// +//! \brief checks for local link connecion to peer device +//! when set as Station, checks for AP connection +//! when set as Access Point, no check is required +//! +//! \param[out] deviceRole role of the device +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +static int32_t validateLocalLinkConnection(SlWlanMode_e *deviceRole) +{ + uint16_t ConfigOpt; + uint16_t ipLen; + SlNetCfgIpV4Args_t ipV4 = {0}; + int32_t retVal; + uint32_t ocpRegVal; + + struct timespec ts; + + retVal = sl_Start(0, 0, 0); + /* when calibration fails, reboot is required */ + if(SL_ERROR_CALIB_FAIL == retVal) + { + mcuReboot(); + } + else + { + ASSERT_ON_ERROR(retVal); + } + + /* if in AP role + * 1) check OCP register value + * 2) if set, it means user set AP mode via switch. + * check for IP_ACQUIRED to indicate NWP is running + * 4) if not set, procede with STATION role + */ + if(retVal == ROLE_AP) + { + *deviceRole = ROLE_AP; + ocpRegVal = MAP_PRCMOCRRegisterRead(OCP_REGISTER_INDEX); + ocpRegVal &= (1 << OCP_REGISTER_OFFSET); + if(ocpRegVal) + { + if(IS_IP_ACQUIRED(nF_ControlBlock.Status)) + { + return(0); + } + else + { + clock_gettime(CLOCK_REALTIME, &ts); + ts.tv_sec += PROFILE_ASYNC_EVT_TIMEOUT; + + retVal = sem_timedwait( + &Provisioning_ControlBlock.connectionAsyncEvent, &ts); + /* freertos return -1 in case of timeout */ + if((retVal == 116) || (retVal == -1)) + { + // UART_PRINT("[Provisioning task] AP role failed to initialize\n\r"); + GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); + retVal = -1; + } + return(retVal); + } + } + } + + if(retVal != ROLE_STA) + { + retVal = sl_WlanSetMode(ROLE_STA); + ASSERT_ON_ERROR(retVal); + + retVal = sl_Stop(SL_STOP_TIMEOUT); + ASSERT_ON_ERROR(retVal); + + retVal = sl_Start(0, 0, 0); + if(retVal < 0 || (retVal != ROLE_STA)) + { + ASSERT_ON_ERROR(retVal); + } + // UART_PRINT("[Provisioning task] Device started as STATION \n\r"); + } + + *deviceRole = ROLE_STA; + + while(((!IS_IPV6L_ACQUIRED(nF_ControlBlock.Status) || + !IS_IPV6G_ACQUIRED(nF_ControlBlock.Status)) && + !IS_IP_ACQUIRED(nF_ControlBlock.Status)) || + !IS_CONNECTED(nF_ControlBlock.Status)) + { + clock_gettime(CLOCK_REALTIME, &ts); + ts.tv_sec += PROFILE_ASYNC_EVT_TIMEOUT; + + retVal = sem_timedwait(&Provisioning_ControlBlock.connectionAsyncEvent, &ts); + // freertos return -1 in case of timeout + if((retVal == 116) || (retVal == -1)) + { + // UART_PRINT( + // "[Provisioning task] Cannot connect to AP or" + // " profile does not exist\n\r"); + GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); + retVal = -1; + + return(retVal); + } + } + + // UART_PRINT("[Provisioning task] Connection to AP succeeded\n\r"); + + // Get the device's IP address + ipLen = sizeof(SlNetCfgIpV4Args_t); + ConfigOpt = 0; + sl_NetCfgGet(SL_NETCFG_IPV4_STA_ADDR_MODE, &ConfigOpt, &ipLen, (uint8_t *)&ipV4); + if(retVal < 0) + { + return(retVal); + } + + // UART_PRINT("[Provisioning task] IP address is %d.%d.%d.%d\n\r", \ + // SL_IPV4_BYTE(ipV4.Ip,3), \ + // SL_IPV4_BYTE(ipV4.Ip,2), \ + // SL_IPV4_BYTE(ipV4.Ip,1), \ + // SL_IPV4_BYTE(ipV4.Ip,0)); + + return(0); +} + +//***************************************************************************** +// +//! Notify if device return to factory image +//! +//! \param None +//! +//! \return None +// +//***************************************************************************** +static void NotifyReturnToFactoryImage(void) +{ + if(((HWREG(HIB3P3_BASE + 0x00000418) & (1 << 7)) != 0) && + ((HWREG(0x4402F0C8) & 0x01) != 0)) + { + // UART_PRINT("Return To Factory Image successful, Do a power cycle(POR)" + // " of the device using switch SW1-Reset\n\r"); + while(1) + { + ; + } + } +} + +//**************************************************************************** +// MAIN FUNCTION +//**************************************************************************** + +//***************************************************************************** +// +//! \brief This function signals the application events +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +int16_t SignalProvisioningEvent(PrvnEvent event) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + pCtx->pendingEvents |= (1 << event); + + return(0); +} + +//***************************************************************************** +// +//! \brief This function gets the current provisioning state +//! +//! \param[in] None +//! +//! \return provisioning state +//! +//**************************************************************************** +PrvnState GetProvisioningState() +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + + return(pCtx->currentState); +} + +//***************************************************************************** +// +//! \brief This function starts the led toggling timer +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +int32_t StartLedEvtTimer(uint32_t timeout) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + + pCtx->ledToggleTimeout = timeout; + Platform_TimerStart(pCtx->ledToggleTimeout, gLedTimer, 1); + + return(0); +} + +//***************************************************************************** +// +//! \brief This function stops the led toggling timer +//! +//! \param[in] None +//! +//! \return 0 on success, negative value otherwise +//! +//**************************************************************************** +int32_t StopLedEvtTimer(void) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + + if(0 != pCtx->ledToggleTimeout) + { + Platform_TimerStop(gLedTimer); + pCtx->ledToggleTimeout = 0; + } + + return(0); +} + +//***************************************************************************** +// +//! \brief This function stops provisioning process +//! +//! \param[in] None +//! +//! \return SL_RET_CODE_PROVISIONING_IN_PROGRESS if provisioning was running, +//! otherwise 0 +//! +//**************************************************************************** +int32_t provisioningStop(void) +{ + Provisioning_AppContext *const pCtx = &gAppCtx; + int32_t retVal; + PrvnState provisioningState; + SlDeviceVersion_t ver = {0}; + uint8_t configOpt = 0; + uint16_t configLen = 0; + + /* check if provisioning is running */ + configOpt = SL_DEVICE_GENERAL_VERSION; + configLen = sizeof(ver); + retVal = + sl_DeviceGet(SL_DEVICE_GENERAL, &configOpt, &configLen, + (uint8_t *)(&ver)); + if(SL_RET_CODE_PROVISIONING_IN_PROGRESS == retVal) + { + // UART_PRINT( + // "[Provisioning task] Provisioning is already running, " + // "stopping it...\r\n"); + retVal = + sl_WlanProvisioning(SL_WLAN_PROVISIONING_CMD_STOP,ROLE_STA,0,NULL, + 0); + + /* wait for the stopped event to arrive - wait for PrvnState_Init */ + do + { + provisioningState = GetProvisioningState(); + usleep(1000); + } + while(provisioningState != PrvnState_Init); + + pCtx->provisioningStatus = PrvsnStatus_Stopped; + + retVal = SL_RET_CODE_PROVISIONING_IN_PROGRESS; + } + else if(retVal < 0) + { + return(retVal); + } + else + { + retVal = 0; + } + + return(retVal); +} + +//***************************************************************************** +// +//! \brief This is the main provisioning task +//! +//! \param[in] None +//! +//! \return None +//! +//**************************************************************************** +void * provisioningTask(void *pvParameters) +{ + int32_t retVal = -1; + Provisioning_AppContext *const pCtx = &gAppCtx; + SlWlanMode_e deviceRole; + SlFsControl_t FsControl; + int32_t status; + + /* Check the wakeup source. If first time entry or wakeup from HIB */ + if(MAP_PRCMSysResetCauseGet() == 0) + { + //UART_PRINT("[Provisioning task] Wake up on Power ON\n\r"); + } + else if(MAP_PRCMSysResetCauseGet() == PRCM_HIB_EXIT) + { + //UART_PRINT("[Provisioning task] Woken up from Hibernate\n\r"); + } + + /* + Following function first try to connect to a stored profile. + If fails, it first configure the device to default state by cleaning + the persistent settings stored in NVMEM (viz. connection profiles & + policies, power policy etc) + + Applications may choose to skip this step if the developer is sure + that the device is in its desired state at start of applicaton + + Note that all profiles and persistent settings that were done on the + device will be lost */ + + /* initialize one-time parameters for provisioning */ + provisioningInit(); + + /* Configure Provisioning Toggle LED */ + GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); + + Platform_TimerInit(LedTimerIntHandler, &gLedTimer); + + /* Set the LED toggling timeout before starting the timer */ + pCtx->ledToggleTimeout = LED_TOGGLE_CONFIRMATION_TIMEOUT; + + StartLedEvtTimer(pCtx->ledToggleTimeout); + + /* check whether return-to-default occured */ + NotifyReturnToFactoryImage(); + + /* 1) try to connect to a stored profile if in STATION mode + * 2) if successful, procede and validate ota bundle and then try to connect + to cloud + * 3) if unsuccessful when in STATION mode, procede to provisioning + * 4) if in AP mode, procede and validate ota bundle + */ + retVal = validateLocalLinkConnection(&deviceRole); + getDeviceType(); + /* at this point, provisioning has not started yet, unless auto provisioning + is running */ + /* in this case, if provisioning from mobile app is running, it would not be + possible to send most of the commands to the device */ + /* need to stop provisioning */ + provisioningStop(); + + StopLedEvtTimer(); + + /* 1) in case coming from ota procedure, a profile should reside on serial + flash and connect immediately + * 2) check if pending commit and set commit the bundle + * 3) On failure, reset the MCU to rollback */ + /* it means OtaArchive is in + SL_FS_BUNDLE_STATE_PENDING_COMMIT */ + // if(OtaArchive_GetPendingCommit()) + // {/* validation of new ota bundle failed, + // reverting to previous bundle */ + // if(retVal != 0) + // { + // /* rollback is not required for production devices + // - but it is not harmfull */ + // FsControl.IncludeFilters = 0; + // status = + // sl_FsCtl(SL_FS_CTL_BUNDLE_ROLLBACK, 0, NULL, + // (uint8_t *)&FsControl, + // sizeof(SlFsControl_t), NULL, 0, + // NULL); + // if(status < 0) + // { + // //UART_PRINT( + // // "[Provisioning task] Rollback error sl_FsCtl, status=%d\n\r", + // // status); + // } + + // mcuReboot(); + // } + // /* validation of new ota bundle succeeded, + // commit the new ota bundle */ + // else + // { + // //UART_PRINT( + // // "[Provisioning task] committing new ota download... \n\r"); + // if(OtaArchive_Commit() < 0) + // { + // //UART_PRINT( + // // "[Provisioning task] failed to commit new download, " + // // "reverting to previous copy by reseting the device \n\r"); + // mcuReboot(); + // } + // //UART_PRINT("[Provisioning task] commit succeeded \n\r"); + + // /* need to stop the WDT so MCU is not reset */ + // PowerCC32XX_reset(PowerCC32XX_PERIPH_WDT); + // } + // } + + if(deviceRole == ROLE_STA) + { + /* it means a connection to AP has been established, + no need to trigger provisioning */ + if(retVal == 0) + { + GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_ON); + + /* signal to linklocal task */ + sem_post(&Provisioning_ControlBlock.provisioningDoneSignal); + + /* signal to report server task */ + sem_post( + &Provisioning_ControlBlock. + provisioningConnDoneToOtaServerSignal); + } + /* it means a connection to AP failed, trigger provisioning */ + else if(retVal < 0) + { + SignalProvisioningEvent(PrvnEvent_Triggered); + } + } + /* it means device is initialized as AP, no need to trigger provisioning */ + if((retVal == 0) && (deviceRole == ROLE_AP)) + { + GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_ON); + + /* signal to linklocal task */ + sem_post(&Provisioning_ControlBlock.provisioningDoneSignal); + + /* signal to report server task */ + sem_post( + &Provisioning_ControlBlock.provisioningConnDoneToOtaServerSignal); + } + + do + { + retVal = provisioningAppTask(); + } + while(!retVal); /* Exit on failure */ + + return(0); +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Sntp.c b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Sntp.c new file mode 100644 index 00000000..81fccbc3 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Sntp.c @@ -0,0 +1,407 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include +#include + +// POSIX Header files +#include +#include +#include + +// RTOS header files +#include "FreeRTOS.h" +#include "task.h" + +#include +#include + +// nanoFramework header files +#include + +static struct sntp_server SNTP_ServersList[NTP_SERVERS]; + +pthread_t sntpWorkingThread = (pthread_t)NULL; +void * SntpWorkingThread(void *arg0); + +void sntp_init(void) +{ + struct sched_param priorityParams; + pthread_attr_t threadAttributes; + int retc; + + if(sntpWorkingThread == NULL) + { + pthread_attr_init(&threadAttributes); + priorityParams.sched_priority = NF_TASK_PRIORITY; + retc = pthread_attr_setschedparam(&threadAttributes, &priorityParams); + retc |= pthread_attr_setstacksize(&threadAttributes, 1024); + if (retc != 0) + { + // failed to set attributes + while (1) {} + } + + retc = pthread_create(&sntpWorkingThread, &threadAttributes, SntpWorkingThread, NULL); + if(retc != 0) + { + // pthread_create() failed + HAL_AssertEx(); + UART_PRINT("Unable to create SNTP thread \n"); + + while(1) + { + ; + } + } + } +} + +void sntp_stop(void) +{ + pthread_cancel(sntpWorkingThread); + sntpWorkingThread = NULL; +} + +bool sntp_enabled(void) +{ + return (sntpWorkingThread != NULL)? true : false; +} + +char* sntp_getservername(int index) +{ + if(index < NTP_SERVERS) + { + return SNTP_ServersList[index].name; + } + + return NULL; +} + +void sntp_setservername(int index, char* server) +{ + if(index < NTP_SERVERS) + { + SNTP_ServersList[index].name = server; + } +} + +static int32_t getAddrByName(const char *name, uint32_t *addr, uint16_t *family) +{ + int32_t ifID; + uint16_t addrLen = 1; + + /* Query DNS for IPv4 address. */ + ifID = SlNetUtil_getHostByName(0, (char *)name, strlen(name), addr, &addrLen, SLNETSOCK_AF_INET); + + if(ifID < 0) + { + /* If call fails, try again for IPv6. */ + ifID = SlNetUtil_getHostByName(0, (char *)name, strlen(name), addr, &addrLen, SLNETSOCK_AF_INET6); + if(ifID < 0) + { + /* return an error */ + return -1; + } + else + { + *family = SLNETSOCK_AF_INET6; + } + } + else + { + *family = SLNETSOCK_AF_INET; + } + + /* Return the interface ID */ + return (ifID); +} + +static int32_t hasKissCode(char *str) +{ + if (strncmp((char *)SNTP_KOD_RATE_STR, str, SNTP_KOD_ERROR_CODE_SIZE) == 0) + { + return (SNTP_KOD_RATE_CODE); + } + else if (strncmp((char *)SNTP_KOD_DENY_STR, str, SNTP_KOD_ERROR_CODE_SIZE) == 0) + { + return (SNTP_KOD_DENY_CODE); + } + else if (strncmp((char *)SNTP_KOD_RSTR_STR, str, SNTP_KOD_ERROR_CODE_SIZE) == 0) + { + return (SNTP_KOD_RSTR_CODE); + } + else + { + return (0); + } +} + +static int32_t getTime(SlNetSock_Addr_t *server, uint16_t ifID, + SlNetSock_Timeval_t *timeout, uint64_t *ntpTimeStamp) +{ + SNTP_Header_t sntpPkt; + int32_t ret = 0; + int16_t sd = -1; + SlNetSocklen_t saLen; + uint32_t integrityCheck; + struct timespec tspec; + + if (server->sa_family == SLNETSOCK_AF_INET) + { + saLen = sizeof(SlNetSock_AddrIn_t); + } + else if (server->sa_family == SLNETSOCK_AF_INET6) + { + saLen = sizeof(SlNetSock_AddrIn6_t); + } + else + { + return (SNTP_EINVALIDFAMILY); + } + + /* Create a UDP socket to communicate with NTP server */ + sd = SlNetSock_create(server->sa_family, SLNETSOCK_SOCK_DGRAM, SLNETSOCK_PROTO_UDP, ifID, 0); + if (sd < 0) + { + return (SNTP_ESOCKCREATEFAIL); + } + + ret = SlNetSock_connect(sd, server, saLen); + if (ret < 0) + { + SlNetSock_close(sd); + return (SNTP_ECONNECTFAIL); + } + + if (timeout != NULL) + { + /* Set the timeout for the server response to the user's value */ + ret = SlNetSock_setOpt(sd, SLNETSOCK_LVL_SOCKET, SLNETSOCK_OPSOCK_RCV_TIMEO, timeout, sizeof(SlNetSock_Timeval_t)); + if (ret < 0) + { + SlNetSock_close(sd); + return (SNTP_ESOCKOPTFAIL); + } + } + + /* Initialize the SNTP packet, setting version and mode = client */ + memset(&sntpPkt, 0, sizeof(SNTP_Header_t)); + sntpPkt.flags = SNTP_VERSION << 3; + sntpPkt.flags |= SNTP_MODE_CLIENT; + + /* Set packet's transmit time as integrity check value */ + clock_gettime(CLOCK_REALTIME, &tspec); + integrityCheck = tspec.tv_sec; + sntpPkt.transmitTS[0] = integrityCheck; + + /* Send out our SNTP request to the current server */ + ret = SlNetSock_send(sd, (void *)&sntpPkt, sizeof(SNTP_Header_t), 0); + if (ret < 0) + { + SlNetSock_close(sd); + return (SNTP_ESENDFAIL); + } + + memset(&sntpPkt, 0, sizeof(SNTP_Header_t)); + + /* Retrieve the NTP packet from the socket and update our time. */ + ret = SlNetSock_recv(sd, &sntpPkt, sizeof(SNTP_Header_t), 0); + if ((ret < 0) || (ret != sizeof(SNTP_Header_t)) || (sntpPkt.originateTS[0] != integrityCheck)) + { + SlNetSock_close(sd); + return (SNTP_ERECVFAIL); + } + + /* Check for errors in server response */ + if (sntpPkt.stratum == 0) + { + /* Per RFC5905, we MUST handle Kiss O' Death packet */ + if ((sntpPkt.flags >> 6) == SNTP_NOSYNC) + { + /* KOD recv'd. Inspect kiss code & handle accordingly */ + ret = hasKissCode((char *)&sntpPkt.referenceID); + + if (ret == SNTP_KOD_RATE_CODE) + { + SlNetSock_close(sd); + return (SNTP_ERATEBACKOFF); + } + /* Check for fatal kiss codes */ + else if ((ret == SNTP_KOD_DENY_CODE) || (ret == SNTP_KOD_RSTR_CODE)) + { + SlNetSock_close(sd); + return (SNTP_EFATALNORETRY); + } + /* Per RFC5905, other kiss codes are ignored */ + } + else + { + /* + * A server response with stratum == 0, with no kiss + * code, is a fatal error. Mark server as invalid + */ + SlNetSock_close(sd); + return (SNTP_EINVALIDRESP); + } + } + + /* return the time in seconds */ + sntpPkt.transmitTS[0] = SlNetUtil_ntohl(sntpPkt.transmitTS[0]); + sntpPkt.transmitTS[1] = SlNetUtil_ntohl(sntpPkt.transmitTS[1]); + + *ntpTimeStamp = ((uint64_t)sntpPkt.transmitTS[0] << 32) | sntpPkt.transmitTS[1]; + + SlNetSock_close(sd); + return (0); +} + +int32_t SNTP_getTime(SlNetSock_Timeval_t *timeout, uint64_t *ntpTimeStamp) +{ + int32_t ret = 0; + int32_t ifID; + SlNetSock_AddrIn_t sa4; + SlNetSock_AddrIn6_t sa6; + SlNetSock_Addr_t *sa; + uint32_t addr[4]; + uint16_t family; + uint32_t i; + size_t count = NTP_SERVERS; + + for (i = 0; i < count; i++) + { + memset(&addr, 0, sizeof(addr)); + ifID = getAddrByName(SNTP_ServersList[i].name, addr, &family); + if(ifID >= 0) + { + if (family == SLNETSOCK_AF_INET) + { + sa4.sin_family = SLNETSOCK_AF_INET; + sa4.sin_port = SlNetUtil_htons(NTP_SERVER_PORT); + sa4.sin_addr.s_addr = SlNetUtil_htonl(addr[0]); + sa = (SlNetSock_Addr_t *)&sa4; + } + else + { + sa6.sin6_family = SLNETSOCK_AF_INET6; + sa6.sin6_port = SlNetUtil_htons(NTP_SERVER_PORT); + sa6.sin6_addr._S6_un._S6_u32[0] = SlNetUtil_htonl(addr[0]); + sa6.sin6_addr._S6_un._S6_u32[1] = SlNetUtil_htonl(addr[1]); + sa6.sin6_addr._S6_un._S6_u32[2] = SlNetUtil_htonl(addr[2]); + sa6.sin6_addr._S6_un._S6_u32[3] = SlNetUtil_htonl(addr[3]); + sa = (SlNetSock_Addr_t *)&sa6; + } + } + else + { + ret = SNTP_EGETHOSTBYNAMEFAIL; + continue; + } + + ret = getTime(sa, ifID, timeout, ntpTimeStamp); + if (ret == 0) + { + break; + } + } + + return (ret); +} + +//////////////////////////////////////////////////////////////////////////////// +// SNTP working thread +//////////////////////////////////////////////////////////////////////////////// +void* SntpWorkingThread(void* argument) +{ + (void)argument; + + uint64_t ntpTimeStamp; + uint32_t currentTime; + int32_t retval; + time_t ts; + SlNetSock_Timeval_t timeval; + struct timespec tspec; + + // Set timeout value for NTP server reply + timeval.tv_sec = NTP_REPLY_WAIT_TIME; + timeval.tv_usec = 0; + + UART_PRINT("[SNTP task] started\n\r"); + + // delay 1st request, if configured + if(SNTP_STARTUP_DELAY > 0) + { + UART_PRINT("[SNTP task] start delay: %d\n\r", SNTP_STARTUP_DELAY); + + ClockP_sleep(SNTP_STARTUP_DELAY); + } + + while(1) + { + // need to be connected and have an IP + if(!IS_IP_ACQUIRED(nF_ControlBlock.Status)) + { + UART_PRINT("[SNTP task] not connected. Retrying in %d seconds.\n\r", SNTP_RETRY_TIMEOUT); + + clock_gettime(CLOCK_REALTIME, &tspec); + tspec.tv_sec += SNTP_RETRY_TIMEOUT; + + // wait for connection event with retry timeout + // don't bother checking if it exited on timeout or event + // because the loop is restarted and the check for connection & address is performed + sem_timedwait(&Provisioning_ControlBlock.connectionAsyncEvent, &tspec); + + // retrying: start over + continue; + } + + UART_PRINT("[SNTP task] getting time...\n\r"); + + // Get the time use the SNTP_ServersList + retval = SNTP_getTime(&timeval, &ntpTimeStamp); + + if (retval != 0) + { + UART_PRINT("[SNTP task] failed to get time. Error: %d\n\r", retval); + + clock_gettime(CLOCK_REALTIME, &tspec); + tspec.tv_sec += SNTP_RETRY_TIMEOUT; + + // wait for connection event with retry timeout + // don't bother checking if it exited on timeout or event + // because the loop is restarted and the check for connection & address is performed + sem_timedwait(&Provisioning_ControlBlock.connectionAsyncEvent, &tspec); + + // retrying: start over + continue; + } + + currentTime = ntpTimeStamp >> 32; + currentTime = TIME_NTP_TO_LOCAL(currentTime); + + tspec.tv_nsec = 0; + tspec.tv_sec = currentTime; + + UART_PRINT("[SNTP task] updated time: %d\n\r", currentTime); + + if (clock_settime(CLOCK_REALTIME, &tspec) != 0) + { + // failed to set current time + // don't do anything, just wait for the next attempt + } + + // wait for connection event with retry timeout + // don't bother checking if it exited on timeout or event + // because the loop is restarted and the check for connection & address is performed + clock_gettime(CLOCK_REALTIME, &tspec); + tspec.tv_sec += SNTP_UPDATE_DELAY; + + sem_timedwait(&Provisioning_ControlBlock.connectionAsyncEvent, &tspec); + } + + pthread_exit(0); +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c new file mode 100644 index 00000000..c6cab4e5 --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/targetSimpleLinkCC32xx_Threads.c @@ -0,0 +1,1062 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// Portions Copyright (c) Texas Instruments Incorporated. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include +#include + +// POSIX Header files +#include +#include +#include + +// RTOS header files +#include "FreeRTOS.h" +#include "task.h" + +// TI-RTOS Header files +#include +#include +#include + +#include + +// Board Header files +#include "Board.h" + +#include +#include +#include +#include +#include +#include + +// externals from Simple Link sockets +extern void Status_callback(); +extern void Link_callback(bool linkUp); + +extern void * CLRStartupThread(void *arg0); +extern void * ReceiverThread(void *arg0); +extern void sntp_init(void); + +// other externals +extern void ConfigUART(); + +////////////////////////////// +#define SL_STOP_TIMEOUT (200) + +#define SPAWN_TASK_PRIORITY (9) +#define TASK_STACK_SIZE (2048) + +#define SLNET_IF_WIFI_PRIO (5) + +////////////////////////////// + +// Stack size in bytes +#define THREADSTACKSIZE 4096 + +pthread_t provisioningThread = (pthread_t)NULL; +pthread_t slThread = (pthread_t)NULL; +pthread_t receiverThread = (pthread_t)NULL; +pthread_t nanoCLRThread = (pthread_t)NULL; + +nanoFramework_CB nF_ControlBlock; + +/***************************************************************************** + Callback Functions +*****************************************************************************/ + +//***************************************************************************** +// +//! The Function Handles WLAN Events +//! +//! \param[in] pWlanEvent - Pointer to WLAN Event Info +//! +//! \return None +//! +//***************************************************************************** +void SimpleLinkWlanEventHandler(SlWlanEvent_t *pWlanEvent) +{ + switch(pWlanEvent->Id) + { + case SL_WLAN_EVENT_CONNECT: + { + SET_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_Connection); + CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpAcquired); + CLR_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Ipv6lAcquired); + CLR_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Ipv6gAcquired); + + // Information about the connected AP (like name, MAC etc) will be + // available in 'slWlanConnectAsyncResponse_t'-Applications + // can use it if required: + + // slWlanConnectAsyncResponse_t *pEventData = NULL; + // pEventData = &pWlanEvent->EventData.STAandP2PModeWlanConnected; + + // Copy new connection SSID and BSSID to global parameters + // memcpy(nF_ControlBlock.connectionSSID, + // pWlanEvent->Data.Connect.SsidName, + // pWlanEvent->Data.Connect.SsidLen); + + // nF_ControlBlock.ssidLen = pWlanEvent->Data.Connect.SsidLen; + + // memcpy(nF_ControlBlock.connectionBSSID, + // pWlanEvent->Data.Connect.Bssid, + // SL_WLAN_BSSID_LENGTH); + + UART_PRINT( + "[WLAN EVENT] STA Connected to the AP: %s ," + "BSSID: %x:%x:%x:%x:%x:%x\n\r", + pWlanEvent->Data.Connect.SsidName, + pWlanEvent->Data.Connect.Bssid[0], + pWlanEvent->Data.Connect.Bssid[1], + pWlanEvent->Data.Connect.Bssid[2], + pWlanEvent->Data.Connect.Bssid[3], + pWlanEvent->Data.Connect.Bssid[4], + pWlanEvent->Data.Connect.Bssid[5]); + + sem_post(&Provisioning_ControlBlock.connectionAsyncEvent); + + Link_callback(true); + } + break; + + case SL_WLAN_EVENT_DISCONNECT: + { + SlWlanEventDisconnect_t* pEventData = NULL; + + CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_Connection); + CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpAcquired); + CLR_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Ipv6lAcquired); + CLR_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Ipv6gAcquired); + + pEventData = &pWlanEvent->Data.Disconnect; + + // If the user has initiated 'Disconnect' request, + // 'reason_code' is SL_WLAN_DISCONNECT_USER_INITIATED. + + if(SL_WLAN_DISCONNECT_USER_INITIATED == pEventData->ReasonCode) + { + UART_PRINT("[WLAN EVENT]Device disconnected from the AP"); + } + else + { + UART_PRINT("[WLAN ERROR]Device disconnected from the AP"); + } + // memset(nF_ControlBlock.connectionSSID, 0, + // sizeof(nF_ControlBlock.connectionSSID)); + // memset(nF_ControlBlock.connectionBSSID, 0, + // sizeof(nF_ControlBlock.connectionBSSID)); + + Link_callback(false); + } + break; + + case SL_WLAN_EVENT_STA_ADDED: + { + UART_PRINT( + "[WLAN EVENT] External Station connected to SimpleLink AP\r\n"); + + UART_PRINT("[WLAN EVENT] STA BSSID: %02x:%02x:%02x:%02x:%02x:%02x\r\n", + pWlanEvent->Data.STAAdded.Mac[0], + pWlanEvent->Data.STAAdded.Mac[1], + pWlanEvent->Data.STAAdded.Mac[2], + pWlanEvent->Data.STAAdded.Mac[3], + pWlanEvent->Data.STAAdded.Mac[4], + pWlanEvent->Data.STAAdded.Mac[5]); + } + break; + + case SL_WLAN_EVENT_STA_REMOVED: + { + UART_PRINT( + "[WLAN EVENT] External Station disconnected from SimpleLink AP\r\n"); + } + break; + + case SL_WLAN_EVENT_PROVISIONING_PROFILE_ADDED: + { + UART_PRINT("[WLAN EVENT] Profile Added\r\n"); + } + break; + + case SL_WLAN_EVENT_PROVISIONING_STATUS: + { + uint16_t status = + pWlanEvent->Data.ProvisioningStatus.ProvisioningStatus; + switch(status) + { + case SL_WLAN_PROVISIONING_GENERAL_ERROR: + case SL_WLAN_PROVISIONING_ERROR_ABORT: + { + // SignalProvisioningEvent(PrvnEvent_Error); + } + break; + + case SL_WLAN_PROVISIONING_ERROR_ABORT_INVALID_PARAM: + case SL_WLAN_PROVISIONING_ERROR_ABORT_HTTP_SERVER_DISABLED: + case SL_WLAN_PROVISIONING_ERROR_ABORT_PROFILE_LIST_FULL: + { + UART_PRINT("[WLAN EVENT] Provisioning Error status=%d\r\n", status); + // SignalProvisioningEvent(PrvnEvent_StartFailed); + } + break; + + case SL_WLAN_PROVISIONING_ERROR_ABORT_PROVISIONING_ALREADY_STARTED: + { + UART_PRINT("[WLAN EVENT] Provisioning already started"); + } + break; + + case SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_FAIL_NETWORK_NOT_FOUND: + { + UART_PRINT("[WLAN EVENT] Confirmation fail: network not found\r\n"); + // SignalProvisioningEvent(PrvnEvent_ConfirmationFailed); + } + break; + + case SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_FAIL_CONNECTION_FAILED: + { + UART_PRINT("[WLAN EVENT] Confirmation fail: Connection failed\r\n"); + // SignalProvisioningEvent(PrvnEvent_ConfirmationFailed); + } + break; + + case + SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_CONNECTION_SUCCESS_IP_NOT_ACQUIRED + : + { + UART_PRINT( + "[WLAN EVENT] Confirmation fail: IP address not acquired\r\n"); + // SignalProvisioningEvent(PrvnEvent_ConfirmationFailed); + } + break; + + case SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_SUCCESS_FEEDBACK_FAILED: + { + UART_PRINT( + "[WLAN EVENT] Connection Success " + "(feedback to Smartphone app failed)\r\n"); + // SignalProvisioningEvent(PrvnEvent_ConfirmationFailed); + } + break; + + case SL_WLAN_PROVISIONING_CONFIRMATION_STATUS_SUCCESS: + { + UART_PRINT("[WLAN EVENT] Confirmation Success!\r\n"); + // SignalProvisioningEvent(PrvnEvent_ConfirmationSuccess); + } + break; + + case SL_WLAN_PROVISIONING_AUTO_STARTED: + { + UART_PRINT("[WLAN EVENT] Auto-Provisioning Started\r\n"); + + // stop auto provisioning - + // may trigger in case of returning to default + // SignalProvisioningEvent(PrvnEvent_Stopped); + } + break; + + case SL_WLAN_PROVISIONING_STOPPED: + { + if(ROLE_STA == pWlanEvent->Data.ProvisioningStatus.Role) + { + UART_PRINT(" [WLAN EVENT] - WLAN Connection Status:%d\r\n", + pWlanEvent->Data.ProvisioningStatus.WlanStatus); + + if(SL_WLAN_STATUS_CONNECTED == + pWlanEvent->Data.ProvisioningStatus.WlanStatus) + { + UART_PRINT(" [WLAN EVENT] - Connected to SSID:%s\r\n", + pWlanEvent->Data.ProvisioningStatus.Ssid); + // memcpy (nF_ControlBlock.connectionSSID, + // pWlanEvent->Data.ProvisioningStatus.Ssid, + // pWlanEvent->Data.ProvisioningStatus.Ssidlen); + // nF_ControlBlock.ssidLen = + // pWlanEvent->Data.ProvisioningStatus.Ssidlen; + + // Provisioning is stopped by the device and + // provisioning is done successfully + // SignalProvisioningEvent(PrvnEvent_Stopped); + + break; + } + else + { + CLR_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Connection); + CLR_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_IpAcquired); + CLR_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Ipv6lAcquired); + CLR_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Ipv6gAcquired); + + // Provisioning is stopped by the device and provisioning + // is not done yet, still need to connect to AP + // SignalProvisioningEvent(PrvnEvent_WaitForConn); + + break; + } + } + } + // SignalProvisioningEvent(PrvnEvent_Stopped); + break; + + case SL_WLAN_PROVISIONING_SMART_CONFIG_SYNCED: + { + UART_PRINT("[WLAN EVENT] Smart Config Synced!\r\n"); + } + break; + + case SL_WLAN_PROVISIONING_CONFIRMATION_WLAN_CONNECT: + { + SET_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Connection); + CLR_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_IpAcquired); + CLR_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Ipv6lAcquired); + CLR_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Ipv6gAcquired); + + UART_PRINT("[WLAN EVENT] Connection to AP succeeded\r\n"); + } + break; + + case SL_WLAN_PROVISIONING_CONFIRMATION_IP_ACQUIRED: + { + SET_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_IpAcquired); + + UART_PRINT("[WLAN EVENT] IP address acquired\r\n"); + } + break; + + case SL_WLAN_PROVISIONING_SMART_CONFIG_SYNC_TIMEOUT: + { + UART_PRINT("[WLAN EVENT] Smart Config Sync timeout\r\n"); + } + break; + + default: + { + UART_PRINT("[WLAN EVENT] Unknown Provisioning Status: %d\r\n", + pWlanEvent->Data.ProvisioningStatus.ProvisioningStatus); + } + break; + } + } + break; + + default: + { + UART_PRINT("[WLAN EVENT] Unexpected event [0x%x]\n\r", + pWlanEvent->Id); + + // SignalProvisioningEvent(PrvnEvent_Error); + } + break; + } +} + +//***************************************************************************** +// +//! The Function Handles the Fatal errors +//! +//! \param[in] slFatalErrorEvent - Pointer to Fatal Error Event info +//! +//! \return None +//! +//***************************************************************************** +void SimpleLinkFatalErrorEventHandler(SlDeviceFatal_t *slFatalErrorEvent) +{ + uint8_t msg = 4; + int32_t msgqRetVal; + + switch(slFatalErrorEvent->Id) + { + case SL_DEVICE_EVENT_FATAL_DEVICE_ABORT: + { + } + break; + + case SL_DEVICE_EVENT_FATAL_DRIVER_ABORT: + { + } + break; + + case SL_DEVICE_EVENT_FATAL_NO_CMD_ACK: + { + } + break; + + case SL_DEVICE_EVENT_FATAL_SYNC_LOSS: + { + } + break; + + case SL_DEVICE_EVENT_FATAL_CMD_TIMEOUT: + { + } + break; + + default: + break; + } + + // msgqRetVal = mq_send(controlMQueue, (char *)&msg, 1, 0); + // if(msgqRetVal < 0) + // { + // //UART_PRINT("[Control task] could not send element to msg queue\n\r"); + // while(1) + // { + // ; + // } + // } +} + +//***************************************************************************** +// +//! This function handles network events such as IP acquisition, IP +//! leased, IP released etc. +//! +//! \param[in] pNetAppEvent - Pointer to NetApp Event Info +//! +//! \return None +//! +//***************************************************************************** +void SimpleLinkNetAppEventHandler(SlNetAppEvent_t *pNetAppEvent) +{ + SlNetAppEventData_u *pNetAppEventData = NULL; + + if(NULL == pNetAppEvent) + { + return; + } + + pNetAppEventData = &pNetAppEvent->Data; + + switch(pNetAppEvent->Id) + { + case SL_NETAPP_EVENT_IPV4_ACQUIRED: + { + SlIpV4AcquiredAsync_t *pEventData = NULL; + + SET_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpAcquired); + + // Ip Acquired Event Data + pEventData = &pNetAppEvent->Data.IpAcquiredV4; + + // Gateway IP address + // nF_ControlBlock.gatewayIP = pEventData->Gateway; + + sem_post(&Provisioning_ControlBlock.connectionAsyncEvent); + + Status_callback(); + } + break; + + case SL_NETAPP_EVENT_IPV6_ACQUIRED: + { + if(!GET_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Ipv6lAcquired)) + { + SET_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Ipv6lAcquired); + } + else + { + SET_STATUS_BIT(nF_ControlBlock.Status, + AppStatusBits_Ipv6gAcquired); + } + + sem_post(&Provisioning_ControlBlock.connectionAsyncEvent); + + Status_callback(); + } + break; + + case SL_NETAPP_EVENT_DHCPV4_LEASED: + { + SET_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpLeased); + } + break; + + case SL_NETAPP_EVENT_DHCPV4_RELEASED: + { + CLR_STATUS_BIT(nF_ControlBlock.Status, AppStatusBits_IpLeased); + + switch(pNetAppEventData->IpReleased.Reason) + { + case SL_IP_LEASE_PEER_RELEASE: + break; + + case SL_IP_LEASE_PEER_DECLINE: + break; + + case SL_IP_LEASE_EXPIRED: + break; + } + } + break; + + case SL_NETAPP_EVENT_DHCP_IPV4_ACQUIRE_TIMEOUT: + { + } + break; + + default: + { + } + break; + } +} + +//***************************************************************************** +// +//! This function handles HTTP server events +//! +//! \param[in] pServerEvent - Contains the relevant event information +//! \param[in] pServerResponse - Should be filled by the user with the +//! relevant response information +//! +//! \return None +//! +//**************************************************************************** +void SimpleLinkHttpServerEventHandler(SlNetAppHttpServerEvent_t *pHttpEvent, + SlNetAppHttpServerResponse_t * + pHttpResponse) +{ + // Unused in this application +} + +//***************************************************************************** +// +//! This function handles General Events +//! +//! \param[in] pDevEvent - Pointer to General Event Info +//! +//! \return None +//! +//***************************************************************************** +void SimpleLinkGeneralEventHandler(SlDeviceEvent_t *pDevEvent) +{ + uint8_t msg = 4; + int32_t msgqRetVal; + + // Most of the general errors are not FATAL are are to be handled + // appropriately by the application. + + if(NULL == pDevEvent) + { + return; + } + switch(pDevEvent->Id) + { + case SL_DEVICE_EVENT_RESET_REQUEST: + { + } + break; + + default: + { + // msgqRetVal = mq_send(controlMQueue, (char *)&msg, 1, 0); + // if(msgqRetVal < 0) + // { + // //UART_PRINT("[Control task] could not send element to msg queue\n\r"); + // while(1) + // { + // ; + // } + // } + } + break; + } +} + +//***************************************************************************** +// +//! This function handles socket events indication +//! +//! \param[in] pSock - Pointer to Socket Event Info +//! +//! \return None +//! +//***************************************************************************** +void SimpleLinkSockEventHandler(SlSockEvent_t *pSock) +{ + if(SL_SOCKET_ASYNC_EVENT == pSock->Event) + { + nFSlSocketAsyncEvent_t event; + event.Sd = pSock->SocketAsyncEvent.SockAsyncData.Sd; + event.Type = pSock->SocketAsyncEvent.SockAsyncData.Type; + + mq_send(nF_ControlBlock.socketAsyncEvent, + (char *)&event, sizeof(nFSlSocketAsyncEvent_t), 0); + + switch(pSock->SocketAsyncEvent.SockAsyncData.Type) + { + case SL_SSL_NOTIFICATION_CONNECTED_SECURED: + break; + case SL_SSL_NOTIFICATION_HANDSHAKE_FAILED: + break; + case SL_SSL_ACCEPT: + break; + case SL_OTHER_SIDE_CLOSE_SSL_DATA_NOT_ENCRYPTED: + break; + case SL_SSL_NOTIFICATION_WRONG_ROOT_CA: + break; + default: + break; + } + } + + // This application doesn't work w/ socket - Events are not expected + switch(pSock->Event) + { + case SL_SOCKET_TX_FAILED_EVENT: + switch(pSock->SocketAsyncEvent.SockTxFailData.Status) + { + case SL_ERROR_BSD_ECLOSE: + break; + default: + break; + } + break; + + default: + break; + } +} + +void SimpleLinkNetAppRequestMemFreeEventHandler(uint8_t *buffer) +{ + // Unused in this application +} + + +//////////// these are coming from link task, they probably don't belong here + +void SimpleLinkSocketTriggerEventHandler(SlSockTriggerEvent_t *pSlTriggerEvent) +{ + // Unused in this application + (void)pSlTriggerEvent; +} + +void * mainThread(void *arg) +{ + struct sched_param priorityParams; + + pthread_attr_t threadAttributes; + + int retc; + struct timespec ts = {0}; + + // peripherals initialization + // make this dependent on having the corresponding NF FEATURE enabled + GPIO_init(); + UART_init(); + SPI_init(); + I2C_init(); + ADC_init(); + PWM_init(); + + // initialize UART (need UART to be functional ASAP in order to output to terminal, if required) + ConfigUART(); + + // Initialize SlNetSock layer + SlNetIf_init(0); + SlNetIf_add(SLNETIF_ID_1, "nF", + (const SlNetIf_Config_t *)&SlNetIfConfigWifi, + SLNET_IF_WIFI_PRIO); + + SlNetSock_init(0); + SlNetUtil_init(0); + + // initialize the realtime clock + clock_settime(CLOCK_REALTIME, &ts); + + // Switch off all LEDs on boards + GPIO_write(Board_GPIO_LED0, Board_GPIO_LED_OFF); + + // clear SimpleLink Status + nF_ControlBlock.Status = 0; + + // reset control block vars + nF_ControlBlock.configurationDone = 0; + + // Create sockets Async event queue + mq_attr attr; + attr.mq_maxmsg = SLNETSOCK_MAX_CONCURRENT_SOCKETS; + attr.mq_msgsize = sizeof(nFSlSocketAsyncEvent_t); + nF_ControlBlock.socketAsyncEvent = mq_open("", O_CREAT, 0, &attr); + + // initializes signals for all tasks + sem_init(&Provisioning_ControlBlock.connectionAsyncEvent, 0, 0); + sem_init(&Provisioning_ControlBlock.provisioningDoneSignal, 0, 0); + sem_init(&Provisioning_ControlBlock.provisioningConnDoneToOtaServerSignal, + 0, + 0); + sem_init(&LinkLocal_ControlBlock.otaReportServerStartSignal, 0, 0); + sem_init(&LinkLocal_ControlBlock.otaReportServerStopSignal, 0, 0); + + // Create the sl_Task internal spawn thread + pthread_attr_init(&threadAttributes); + priorityParams.sched_priority = SPAWN_TASK_PRIORITY; + retc = pthread_attr_setschedparam(&threadAttributes, &priorityParams); + retc |= pthread_attr_setstacksize(&threadAttributes, 2 * TASK_STACK_SIZE); + + // The SimpleLink host driver architecture mandate spawn + // thread to be created prior to calling Sl_start (turning the NWP on). + // The purpose of this thread is to handle + // asynchronous events sent from the NWP. + // Every event is classified and later handled + // by the Host driver event handlers. + retc = pthread_create(&slThread, &threadAttributes, sl_Task, NULL); + if(retc) + { + // Handle Error + UART_PRINT("Unable to create sl_Task thread \n"); + HAL_AssertEx(); + while(1) + { + ; + } + } + + // Before turning on the NWP on, reset any previously configured parameters + // TODO: check if we should have a better reset implementation instead of using the standard one + retc = sl_WifiConfig(); + if(retc < 0) + { + // Handle Error + UART_PRINT("Network Terminal - Couldn't configure Network Processor - %d\n", retc); + HAL_AssertEx(); + return(NULL); + } + + // need to setup the network interface to enable IPv6 otherwise there are errors in socket + // when IPv6 addresses are brought in (for example on a response to a DNS query) + // this can probably go away when support for IPv6 is official + uint32_t ifBitmap = 0; + ifBitmap = SL_NETCFG_IF_IPV6_LOCAL_STATEFUL | SL_NETCFG_IF_IPV6_GLOBAL_STATEFUL; + sl_NetCfgSet(SL_NETCFG_IF, SL_NETCFG_IF_STATE, sizeof(ifBitmap), &ifBitmap); + + // start network processor + retc = sl_Start(NULL, NULL, NULL); + if(retc >= 0) + { + // we are good! + // sl_Start returns on success the role that device started on + nF_ControlBlock.Role = retc; + ////////////////////////////////////// **** uncomment this if using provisioning + // retc = sl_Stop(SL_STOP_TIMEOUT); + // if(retc < 0) + // { + // /* Handle Error */ + // // UART_PRINT("\n sl_Stop failed\n"); + // while(1) + // { + // ; + // } + // } + ////////////////////////////////////// **** + } + else if((retc < 0) && (retc != SL_ERROR_RESTORE_IMAGE_COMPLETE)) + { + // Handle Error + HAL_AssertEx(); + while(1) + { + ; + } + } + + // // provisioning task + // pthread_attr_init(&threadAttributes); + // priorityParams.sched_priority = NF_TASK_PRIORITY; + // retc = pthread_attr_setschedparam(&threadAttributes, &priorityParams); + // retc |= pthread_attr_setstacksize(&threadAttributes, TASK_STACK_SIZE); + // if(retc) + // { + // // Handle Error + // // UART_PRINT("Unable to configure provisioningTask thread parameters \n"); + // while(1) + // { + // ; + // } + // } + // retc = pthread_create(&provisioningThread, &threadAttributes, provisioningTask, NULL); + // if (retc != 0) { + // // Unable to create provisioningTask thread + // while (1) {} + // } + + // retc |= pthread_attr_setstacksize(&threadAttributes, 2048); + // if(retc) + // { + // // Handle Error + // // UART_PRINT("Unable to create provisioningTask thread \n"); + // while(1) + // { + // ; + // } + // } + + // receiver thread + pthread_attr_init(&threadAttributes); + priorityParams.sched_priority = NF_TASK_PRIORITY + 1; + retc = pthread_attr_setschedparam(&threadAttributes, &priorityParams); + retc |= pthread_attr_setstacksize(&threadAttributes, 2048); + if (retc != 0) + { + // failed to set attributes + while (1) {} + } + + retc = pthread_create(&receiverThread, &threadAttributes, ReceiverThread, NULL); + if(retc != 0) + { + // pthread_create() failed + UART_PRINT("Unable to create receiver thread \n"); + HAL_AssertEx(); + while(1) + { + ; + } + } + + // CLR thread + pthread_attr_init(&threadAttributes); + priorityParams.sched_priority = NF_TASK_PRIORITY; + retc = pthread_attr_setschedparam(&threadAttributes, &priorityParams); + retc |= pthread_attr_setstacksize(&threadAttributes, 5116); + if (retc != 0) + { + // failed to set attributes + while (1) {} + } + + // forward CLR_SETTINGS to CLR startup thread + retc = pthread_create(&nanoCLRThread, &threadAttributes, CLRStartupThread, arg); + if(retc != 0) + { + // pthread_create() failed + UART_PRINT("Unable to create CLR thread \n"); + HAL_AssertEx(); + while(1) + { + ; + } + } + + #ifdef SL_APP_SNTP + sntp_setservername(0, SNTP_SERVER_DEFAULT_ADDRESS); + sntp_init(); + #endif + + return (0); +} + +//***************************************************************************** +// +//! \brief Application defined malloc failed hook +//! +//! \param none +//! +//! \return none +//! +//***************************************************************************** +void vApplicationMallocFailedHook() +{ + // Handle Memory Allocation Errors + while(1) + { + } +} + +//***************************************************************************** +// +//! \brief Application defined stack overflow hook +//! +//! \param none +//! +//! \return none +//! +//***************************************************************************** +void vApplicationStackOverflowHook(TaskHandle_t pxTask, + char *pcTaskName) +{ + //Handle FreeRTOS Stack Overflow + while(1) + { + } +} + +void vApplicationTickHook(void) +{ + // This function will be called by each tick interrupt if + // configUSE_TICK_HOOK is set to 1 in FreeRTOSConfig.h. User code can be + // added here, but the tick hook is called from an interrupt context, so + // code must not attempt to block, and only the interrupt safe FreeRTOS API + // functions can be used (those that end in FromISR()). + +} + +void vPreSleepProcessing(uint32_t ulExpectedIdleTime) +{ +} + +//***************************************************************************** +// +//! \brief Application defined idle task hook +//! +//! \param none +//! +//! \return none +//! +//***************************************************************************** +void +vApplicationIdleHook(void) +{ + // Handle Idle Hook for Profiling, Power Management etc +} + +//***************************************************************************** +// +//! \brief Overwrite the GCC _sbrk function which check the heap limit related +//! to the stack pointer. +//! In case of freertos this checking will fail. +//! \param none +//! +//! \return none +//! +//***************************************************************************** +void * _sbrk(uint32_t delta) +{ + extern char _end; // Defined by the linker + extern char __HeapLimit; + static char *heap_end; + static char *heap_limit; + char *prev_heap_end; + + if(heap_end == 0) + { + heap_end = &_end; + heap_limit = &__HeapLimit; + } + + prev_heap_end = heap_end; + if(prev_heap_end + delta > heap_limit) + { + return((void *) -1L); + } + heap_end += delta; + return((void *) prev_heap_end); +} + + +// /***************************************************************************** +// Local Functions +// *****************************************************************************/ + +//***************************************************************************** +// +//! This function clears and enables a GPIO pin interrupt flag +//! +//! \param index - GPIO index +//! +//! \return None +//! +//***************************************************************************** +static void GPIO_clearAndEnable(uint8_t index) +{ + GPIO_clearInt(index); + GPIO_enableInt(index); +} + +void Platform_TimerInit(void (*timerIntHandler)(sigval val), + timer_t *timerId) +{ + sigevent sev; + + // Create Timer + sev.sigev_notify = SIGEV_SIGNAL; + sev.sigev_notify_function = timerIntHandler; + timer_create(CLOCK_MONOTONIC, &sev, timerId); +} + +void Platform_TimerStart(uint32_t asyncEvtTimeoutMsec, + timer_t timerId, + uint8_t periodic) +{ + struct itimerspec value; + + // set the timeout + value.it_value.tv_sec = (asyncEvtTimeoutMsec / 1000); + value.it_value.tv_nsec = (asyncEvtTimeoutMsec % 1000) * 1000000; + + value.it_value.tv_sec += (value.it_value.tv_nsec / 1000000000); + value.it_value.tv_nsec = value.it_value.tv_nsec % 1000000000; + + if(periodic) + { + // set as periodic timer + value.it_interval.tv_sec = value.it_value.tv_sec; + value.it_interval.tv_nsec = value.it_value.tv_nsec; + } + else + { + // set as one shot timer + value.it_interval.tv_sec = 0; + value.it_interval.tv_nsec = 0; + } + + // kick the timer + timer_settime(timerId, 0, &value, NULL); +} + +void Platform_TimerStop(timer_t timerId) +{ + struct itimerspec value; + + // stop timer + value.it_interval.tv_sec = 0; + value.it_interval.tv_nsec = 0; + value.it_value.tv_sec = 0; + value.it_value.tv_nsec = 0; + timer_settime(timerId, 0, &value, NULL); +} + +void Platform_TimerInterruptClear(void) +{ + // Do nothing... +} + +//***************************************************************************** +// +//! \brief This function reboot the M4 host processor +//! +//! \param[in] none +//! +//! \return none +//! +//**************************************************************************** +void mcuReboot(void) +{ + // stop network processor activities before reseting the MCU + sl_Stop(SL_STOP_TIMEOUT); + + // UART_PRINT("[Common] CC32xx MCU reset request\r\n"); + + // Reset the MCU in order to test the bundle + PRCMHibernateCycleTrigger(); +} diff --git a/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/target_platform.h.in b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/target_platform.h.in new file mode 100644 index 00000000..bfb0d3eb --- /dev/null +++ b/source/native/nf-interpreter/targets/TI-SimpleLink/nanoCLR/target_platform.h.in @@ -0,0 +1,17 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +////////////////////////////////////////////////////////////////////////////// +// This file was automatically generated by a tool. // +// Any changes you make here will be overwritten when it's generated again. // +////////////////////////////////////////////////////////////////////////////// + +#ifndef _TARGET_TI_SIMPLELINK_NANOCLR_H_ +#define _TARGET_TI_SIMPLELINK_NANOCLR_H_ + +// enable SNTP app +#define SL_APP_SNTP @NF_NETWORKING_SNTP@ + +#endif /* _TARGET_TI_SIMPLELINK_NANOCLR_H_ */ diff --git a/source/native/nf-interpreter/targets/os/win32/Include/TargetPAL_BlockStorage.h b/source/native/nf-interpreter/targets/os/win32/Include/TargetPAL_BlockStorage.h new file mode 100644 index 00000000..c18cb808 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/Include/TargetPAL_BlockStorage.h @@ -0,0 +1,767 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _TARGET_PAL_BLOCKSTORAGE_H_ +#define _TARGET_PAL_BLOCKSTORAGE_H_ 1 + +//--// + +#include +#include + +#if defined(__GNUC__) +#define HAL_Time_Sleep_MicroSeconds_BS(x) HAL_Time_Sleep_MicroSeconds_InRam(x) + +#else +#define HAL_Time_Sleep_MicroSeconds_BS(x) HAL_Time_Sleep_MicroSeconds(x) + +#endif + + + + +// for convert byte size to storage sector size +#define CONVERTBYTETOSECTORSIZE(x,y) ( (size_t)x + (size_t)y-1)/(size_t)y + +#define CONVERTBYTETOSECTORSIZE_2(x,y,z) ( (size_t)x + (size_t)y-1)/(size_t)z + +///////////////////////////////////////////////////////// +// Description: +// Definitions for the Block Storage device interface +// for the .NET Micro Framework +// +// Remarks: +// The general design of the API is strongly influenced +// by the Windows Embedded CE Flash Media Driver (FMD) +// API. However, It is not intended to be a direct port +// of the FMD architecture to the .NET MF. This design +// overcomes some of the limitations of the CE design +// and includes functionalty an support that is specific +// to the .NET MF. +// +// In particular this design adds the following: +// * Generalized block storage rather than assuming +// a Resident Flash Array (RFA) +// * Support for multiple instances of block storage +// devices instead of only one +// * Support for legacy CLR Block usage information to +// Identify for the system where various types of +// information reside in the storage device. +// * Support for direct use of NOR flash without forcing +// additional layering for metadata if an FS is not +// needed or desired on the NOR flash. +// * Support for XIP storage media like NOR and ROM. +// * Use of an interface (as a structure of function +// pointers) to allow layering and standardized support +// for various common functionality. (e.g. treating +// NOR flash with varying sized sectors and no metadata +// as if it was NAND with fixed sized sectors including +// metadata. Thus this kind functionality need only be +// implemented once) +// +// Terminology: +// Block Storage Device - device that stores data addressable +// as a chunk as opposed to byte or unsigned short level +// +// Sector - smallest unit of storage for a Block device. Data is +// read or written as a complete sector(unless the device +// supports XIP which allows byte addresssing and reading +// directly from the processor memory bus) +// +// Block - smallest eraseable unit of the storage device. A block +// contains one or more sectors that are erased as a whole. +// All sectors within a block are always the same size. +// +// Region - Group of adjacent blocks that all contain sectors of the +// same size. +// +// Execute-In-Place (XIP) - Attribute of some storage types, NOR, ROM, +// RAM, that allows direct execution of code from the device. +// XIP capable devices are at least read-only and byte addresable +// on the CPU memory bus. +// + + +// struct BlockRange +// { + + +// public: + +// static bool IsBlocknanoBooterAgnostic( uint32_t BlockType ) +// { +// // The only blocks that should be distinguished by nanoBooter are CONFIG, +// // Bootstrap and reserved blocks (DirtyBit is another version of CONFIG). +// if( BlockType == BlockRange_BLOCKTYPE_BOOTSTRAP || +// BlockType == BlockRange_BLOCKTYPE_CONFIG || +// BlockType == BlockRange_BLOCKTYPE_RESERVED || +// BlockType == BlockRange_BLOCKTYPE_DIRTYBIT) +// { +// return FALSE; +// } + +// return TRUE; +// } + +// bool IsReserved() const { return ((RangeType & BlockRange_RESERVED) == BlockRange_RESERVED); } +// bool IsReadOnly() const { return ((RangeType & BlockRange_READONLY) == BlockRange_READONLY); } + +// bool IsReservedData() const { return ((RangeType & (BlockRange_RESERVED | BlockRange_DATATYPE_RAW )) == (BlockRange_RESERVED | BlockRange_DATATYPE_RAW )); } +// bool HasManagedCode() const { return ((RangeType & (BlockRange_DATATYPE_MANAGEDCODE )) == (BlockRange_DATATYPE_MANAGEDCODE )); } + +// bool IsCode() const { return ((RangeType & BlockRange_USAGE_MASK) == BlockUsage_CODE); } +// bool IsBootstrap() const { return ((RangeType & BlockRange_USAGE_MASK) == BlockUsage_BOOTSTRAP);} +// bool IsDirtyBit() const { return ((RangeType & BlockRange_BLOCKTYPE_CONFIG) == BlockRange_BLOCKTYPE_DIRTYBIT);} +// bool IsConfig() const { return ((RangeType & BlockRange_BLOCKTYPE_CONFIG) == BlockRange_BLOCKTYPE_CONFIG); } +// bool IsDeployment() const { return ((RangeType & BlockRange_USAGE_MASK) == BlockUsage_DEPLOYMENT);} +// bool IsFileSystem() const { return ((RangeType & BlockRange_USAGE_MASK) == BlockUsage_FILESYSTEM); } +// uint32_t GetBlockCount() const { return (EndBlock - StartBlock + 1); } + +// // NOTE: This is the application native code only (not including the managed DAT section) +// // and thus is different from the old MEMORY_USAGE_CODE which contained both +// // the Native code application and the DAT section. Obviously these inlines can be +// // altered or added upon to test for any combination of the flags as desired but seperating +// // the DAT region out on it's own allows for locating ANY managed code sections of storage +// bool IsLegacyCode() const { return (IsCode()); } +// uint32_t GetBlockUsage() const { return (RangeType & BlockRange_USAGE_MASK); } + + +// /* +// Due to the lack of a defined bit ordering for bit fields in the C/C++ +// languages a bit field structure isn't actually used but this should +// help clarify the layout and intent of the constant declarations below. + +// //MSB +// unsigned EXECUTABLE:1; +// unsigned RESERVED:1; +// unsigned READONLY:1; +// unsigned UNUSEDBITS:13; + +// // The lower 16 bits are used to define the specific +// // usage for blocks when the RESERVED bit set +// unsigned BlockType:4 +// unsigned Usage:12; +// //LSB +// */ +// uint32_t RangeType; +// uint32_t StartBlock; +// uint32_t EndBlock; +// }; + +// ///////////////////////////////////////////////////////// +// // Description: +// // This structure defines characteristics of a particular +// // region of a block device. +// // +// // Remarks: +// // There is often more than one instance of this structure for each +// // block device. +// // +// // The BytesPerBlock value is an optimization to prevent the need +// // to routinely caclulate it from SectorsPerBlock * DataBytesPerSector +// // +// struct BlockRegionInfo +// { +// uint32_t Size() const { return (NumBlocks * BytesPerBlock); } +// ByteAddress BlockAddress(uint32_t blockIndex) const { return (Start + (blockIndex * BytesPerBlock)); } +// uint32_t OffsetFromBlock(uint32_t Address) const { return ((Address - Start) % BytesPerBlock); } +// uint32_t BlockIndexFromAddress(uint32_t Address) const { return ((Address - Start) / BytesPerBlock); } + +// ByteAddress Start; // Starting Sector address +// uint32_t NumBlocks; // total number of blocks in this region +// uint32_t BytesPerBlock; // Total number of bytes per block + +// uint32_t NumBlockRanges; +// const BlockRange *BlockRanges; +// }; + +// ///////////////////////////////////////////////////////// +// // Description: +// // This structure defines characteristics of a particular +// // block device. +// // +// // Remarks: +// // THere is only one instance of this structure for each +// // block device. +// // + +// struct MediaAttribute +// { +// bool Removable :1; +// bool SupportsXIP:1; +// bool WriteProtected:1; +// bool SupportsCopyBack:1; +// bool ErasedBitsAreZero:1; +// }; + +// /////////////////////////////////////////////////////////// + +// struct DeviceBlockInfo +// { +// // indicates if the storage media is removeable + +// MediaAttribute Attribute; + +// // Maximum Sector Write Time. +// uint32_t MaxSectorWrite_uSec; + +// // Maximum erase time for the a block +// uint32_t MaxBlockErase_uSec; + +// // Bytes Per Sector +// uint32_t BytesPerSector; + +// // Total Size +// ByteAddress Size; + +// // count of regions in the flash. +// uint32_t NumRegions; + +// // pointer to an array (NumRegions long) of region information +// const BlockRegionInfo *Regions; + +// __nfweak SectorAddress PhysicalToSectorAddress( const BlockRegionInfo* pRegion, ByteAddress phyAddress ) const; + +// __nfweak bool FindRegionFromAddress(ByteAddress Address, uint32_t &BlockRegionIndex, uint32_t &BlockRangeIndex ) const; + +// __nfweak bool FindForBlockUsage(uint32_t BlockUsage, ByteAddress &Address, uint32_t &BlockRegionIndex, uint32_t &BlockRangeIndex ) const; + +// __nfweak bool FindNextUsageBlock(uint32_t BlockUsage, ByteAddress &Address, uint32_t &BlockRegionIndex, uint32_t &BlockRangeIndex ) const; +// }; + +// /////////////////////////////////////////////////////////////// +// // Description: +// // This structure describes the sector Metadata used for wear +// // leveling. +// // +// // Remarks: +// // This structure emulates the typical physical layout of the +// // extra area of flash. The wear leveling layer for NAND and +// // NOR flash supplied by Microsoft for Windows CE makes use +// // of 8 bytes of the Sector Extra Info area. +// // +// // This information is designed to match that used in +// // Windows Embedded CE systems so that the FAL algorithms from +// // CE can be more easily ported to the .NET MF. +// // +// // The following is a typical representation of how the extra area +// // is utilized: +// //- - - - - - - - - - - - - - - - +// //|R|R|R|R|O|V|R|R|E|E|E|E|E|E|E|E| +// //- - - - - - - - - - - - - - - - +// // +// //The following table describes each element. +// // +// //Element Description +// // R Reserved bytes used by the FAL +// // O Byte for use by the OEM +// // V Byte indicating if the block is valid (a.k.a. bad) +// // E Bytes typically used for by a NAND driver for ECC +// // +// struct GNU_PACKED SectorMetadata +// { +// unsigned long dwReserved1; // Used by the FAL to hold the logical to physical sector mapping information. +// unsigned char bOEMReserved; // For use by OEM. See OEMReservedBits for more information. +// unsigned char bBadBlock; // Indicates if a block is bad. +// unsigned short wReserved2; // Used by the FAL to maintain state information about the sector. + +// // TODO: Check ECC algorithm implementations on CE to see what data type works most conveniently for this +// uint32_t ECC[2]; // Error Correction Code [Should be all 0xFF if not used] + +// // Remarks: +// // Any sectors that the OEM does not want the wear leveling +// // code to touch should have both of these bits set. This +// // includes the sectors that include the boot loader and any +// // other flash data that exists at fixed locations. +// // +// // Note: +// // Because only full blocks can be erased, all sectors within +// // a block should have the same values for these flags. +// // +// static const unsigned char OEM_BLOCK_RESERVED = 0x01; +// static const unsigned char OEM_BLOCK_READONLY = 0x02; +// }; + +//--// + +// struct BLOCK_CONFIG +// { +// GPIO_FLAG WriteProtectionPin; +// const DeviceBlockInfo* BlockDeviceInformation; +// }; + +// UNDONE: FIXME: struct MEMORY_MAPPED_NOR_BLOCK_CONFIG +//{ +// BLOCK_CONFIG BlockConfig; +// CPU_MEMORY_CONFIG Memory; +// uint32_t ChipProtection; +// uint32_t ManufacturerCode; +// uint32_t DeviceCode; +//}; + +// ///////////////////////////////////////////////////////// +// // Description: +// // This structure defines an interface for block devices +// // +// // Remarks: +// // It is possible a given system might have more than one +// // storage device type. This interface abstracts the +// // hardware sepcifics from the rest of the system. +// // +// // All of the functions take at least one void* parameter +// // that normally points to a driver specific data structure +// // containing hardware specific settings to use. This +// // allows a single driver to support multiple instances of +// // the same type of storage device in the system. +// // +// // The sector read and write functions provide a parameter +// // for Sector Metadata. The metadata is used for flash arrays +// // without special controllers to manage wear leveling etc... +// // (mostly for directly attached NOR and NAND). The metadata +// // is used by upper layers for wear leveling to ensure that +// // data is moved around on the flash when writing to prevent +// // failure of the device from too many erase cycles on a sector. +// // +// // TODO: +// // Define standard method of notification that media is +// // removed for all removeable media. This will likely +// // be a continuation so that the FS Manager can mount +// // an FS and then notify the managed app of the new FS. +// // +// struct IBlockStorageDevice +// { +// ///////////////////////////////////////////////////////// +// // Description: +// // Initializes a given block device for use +// // +// // Input: +// // +// // Returns: +// // true if succesful; false if not +// // +// // Remarks: +// // No other functions in this interface may be called +// // until after Init returns. +// // +// bool (*InitializeDevice)(void*); + +// ///////////////////////////////////////////////////////// +// // Description: +// // Initializes a given block device for use +// // +// // Returns: +// // true if succesful; false if not +// // +// // Remarks: +// // De initializes the device when no longer needed +// // +// bool (*UninitializeDevice)(void*); + +// ///////////////////////////////////////////////////////// +// // Description: +// // Gets the information describing the device +// // +// const DeviceBlockInfo* (*GetDeviceInfo)(void*); + +// ///////////////////////////////////////////////////////// +// // Description: +// // Reads data from a set of sectors +// // +// // Input: +// // StartSector - Starting Sector for the read +// // NumSectors - Number of sectors to read +// // pSectorBuff - pointer to buffer to read the data into. +// // Must be large enough to hold all of the data +// // being read. +// // +// // pSectorMetadata - pointer to an array of structured (one for each sector) +// // for the extra sector information. +// // +// // Returns: +// // true if succesful; false if not +// // +// // Remarks: +// // This function reads the number of sectors specified from the device. +// // +// // pSectorBuff may be NULL. This is to allow for reading just the metadata. +// // +// // pSectorMetadata can be set to NULL if the caller does not need the extra +// // data. +// // +// // If the device does not support sector Metadata it should fail if the +// // pSectorMetadata parameter is not NULL. +// // +// bool (*Read)(void*, ByteAddress StartSector, uint32_t NumBytes, unsigned char* pSectorBuff); + +// ///////////////////////////////////////////////////////// +// // Description: +// // Writes data to a set of sectors +// // +// // Input: +// // StartSector - Starting Sector for the write +// // NumSectors - Number of sectors to write +// // pSectorBuff - pointer to data to write. +// // Must be large enough to hold complete sectors +// // for the number of sectors being written. +// // +// // pSectorMetadata - pointer to an array of structures (one for each sector) +// // for the extra sector information. +// // +// // Returns: +// // true if succesful; false if not +// // +// // Remarks: +// // This function reads the number of sectors specified from the device. +// // The SectorMetadata is used for flash arrays without special controllers +// // to manage wear leveling etc... (mostly for NOR and NAND). The metadata +// // is used by upper layers to ensure that data is moved around on the flash +// // when writing to prevent failure of the device from too many erase cycles +// // on a sector. +// // +// // If the device does not support sector Metadata it should fail if the +// // pSectorMetadata parameter is not NULL. +// // +// // pSectorMetadata can be set to NULL if the caller does not need the extra +// // data. Implementations must not attempt to write data through a NULL pointer! +// // +// bool (*Write)(void*, ByteAddress Address, uint32_t NumBytes, unsigned char* pSectorBuf, bool ReadModifyWrite); + +// bool (*Memset)(void*, ByteAddress Address, unsigned char Data, uint32_t NumBytes); + +// bool (*GetSectorMetadata)(void*, ByteAddress SectorStart, SectorMetadata* pSectorMetadata); + +// bool (*SetSectorMetadata)(void*, ByteAddress SectorStart, SectorMetadata* pSectorMetadata); + +// ///////////////////////////////////////////////////////// +// // Description: +// // Check a block is erased or not. +// // +// // Input: +// // BlockStartAddress - Logical Sector Address +// // +// // Returns: +// // true if it is erassed, otherwise false +// // +// // Remarks: +// // Check the block containing the sector address specified. +// // +// bool (*IsBlockErased)(void*, ByteAddress BlockStartAddress, uint32_t BlockLength); + +// ///////////////////////////////////////////////////////// +// // Description: +// // Erases a block +// // +// // Input: +// // Address - Logical Sector Address +// // +// // Returns: +// // true if succesful; false if not +// // +// // Remarks: +// // Erases the block containing the sector address specified. +// // +// bool (*EraseBlock)(void*, ByteAddress Address); + +// ///////////////////////////////////////////////////////// +// // Description: +// // Changes the power state of the device +// // +// // Input: +// // State - true= power on; false = power off +// // +// // Remarks: +// // This function allows systems to conserve power by +// // shutting down the hardware when the system is +// // going into low power states. +// // +// void (*SetPowerState)(void*, uint32_t State); + +// uint32_t (*MaxSectorWrite_uSec)(void*); + +// uint32_t (*MaxBlockErase_uSec)(void*); +// }; + + +// //////////////////////////////////////////////// +// // Description: +// // Binding context for a driver and the physical device +// // +// // Remarks: +// // The design pattern here effectively mimics a C++ class +// // with virtuals. The reason virtuals are not used is that +// // the .NET MF supports a wide variety of compiler/Linker +// // tool chains and some of them bring in a large Run-time +// // library footprint when Certain C++ language features are +// // used. Since a major goal of the .NET MF is to reduce +// // code footprint we avoid anything that brings in additional +// // library code. +// // + +// struct BlockStorageDevice : public HAL_DblLinkedNode +// { + +// public: + +// ///////////////////////////////////////////////////////// +// // Description: +// // Initializes a given block device for use +// // +// // Returns: +// // true if succesful; false if not +// // +// // Remarks: +// // No other functions in this interface may be called +// // until after Init returns. +// // +// bool InitializeDevice() { return this->m_BSD->InitializeDevice( this->m_context ); } + +// ///////////////////////////////////////////////////////// +// // Description: +// // Initializes a given block device for use +// // +// // Returns: +// // true if succesful; false if not +// // +// // Remarks: +// // De initializes the device when no longer needed +// // +// bool UninitializeDevice() { return this->m_BSD->UninitializeDevice( this->m_context ); } + +// ///////////////////////////////////////////////////////// +// // Description: +// // Gets the information describing the device +// // +// const DeviceBlockInfo* GetDeviceInfo() { return this->m_BSD->GetDeviceInfo( this->m_context ); } + +// ///////////////////////////////////////////////////////// +// // Description: +// // Reads data from a set of sectors +// // +// // Input: +// // StartSector - Starting Sector for the read +// // NumSectors - Number of sectors to read +// // pSectorBuff - pointer to buffer to read the data into. +// // Must be large enough to hold all of the data +// // being read. +// // +// // pSectorMetadata - pointer to an array of structured (one for each sector) +// // for the extra sector information. +// // +// // Returns: +// // true if succesful; false if not +// // +// // Remarks: +// // This function reads the number of sectors specified from the device. +// // +// // pSectorBuff may be NULL. This is to allow for reading just the metadata. +// // +// // pSectorMetadata can be set to NULL if the caller does not need the extra +// // data. +// // +// // If the device does not support sector Metadata it should fail if the +// // pSectorMetadata parameter is not NULL. +// // +// bool Read(ByteAddress Address, uint32_t NumBytes, unsigned char* pSectorBuff) +// { +// return this->m_BSD->Read(this->m_context, Address, NumBytes, pSectorBuff); +// } + +// ///////////////////////////////////////////////////////// +// // Description: +// // Writes data to a set of sectors +// // +// // Input: +// // StartSector - Starting Sector for the write +// // NumSectors - Number of sectors to write +// // pSectorBuff - pointer to data to write. +// // Must be large enough to hold complete sectors +// // for the number of sectors being written. +// // +// // pSectorMetadata - pointer to an array of structures (one for each sector) +// // for the extra sector information. +// // +// // Returns: +// // true if succesful; false if not +// // +// // Remarks: +// // This function reads the number of sectors specified from the device. +// // The SectorMetadata is used for flash arrays without special controllers +// // to manage wear leveling etc... (mostly for NOR and NAND). The metadata +// // is used by upper layers to ensure that data is moved around on the flash +// // when writing to prevent failure of the device from too many erase cycles +// // on a sector. +// // +// // If the device does not support sector Metadata it should fail if the +// // pSectorMetadata parameter is not NULL. +// // +// // pSectorMetadata can be set to NULL if the caller does not need the extra +// // data. Implementations must not attempt to write data through a NULL pointer! +// // +// bool Write(ByteAddress Address, uint32_t NumBytes, unsigned char* pSectorBuf, bool ReadModifyWrite) +// { +// return this->m_BSD->Write(this->m_context, Address, NumBytes, pSectorBuf, ReadModifyWrite); +// } + +// bool Memset(ByteAddress Address, unsigned char Data, uint32_t NumBytes) +// { +// return this->m_BSD->Memset(this->m_context, Address, Data, NumBytes); +// } + +// bool GetSectorMetadata(ByteAddress SectorStart, SectorMetadata* pSectorMetadata) +// { +// return this->m_BSD->GetSectorMetadata(this->m_context, SectorStart, pSectorMetadata); +// } + +// bool SetSectorMetadata(ByteAddress SectorStart, SectorMetadata* pSectorMetadata) +// { +// return this->m_BSD->SetSectorMetadata(this->m_context, SectorStart, pSectorMetadata); +// } + +// ///////////////////////////////////////////////////////// +// // Description: +// // Check a block is erased or not +// // +// // Input: +// // Address - Logical Sector Address +// // +// // Returns: +// // true it is erased; false if not +// // +// // Remarks: +// // check the block containing the sector address specified. +// // +// bool IsBlockErased(ByteAddress BlockStartAddress, uint32_t BlockLength) { return this->m_BSD->IsBlockErased(this->m_context, BlockStartAddress, BlockLength); } + + +// ///////////////////////////////////////////////////////// +// // Description: +// // Erases a block +// // +// // Input: +// // Address - Logical Sector Address +// // +// // Returns: +// // true if succesful; false if not +// // +// // Remarks: +// // Erases the block containing the sector address specified. +// // +// bool EraseBlock(ByteAddress Address) const { return this->m_BSD->EraseBlock(this->m_context, Address); } + + +// ///////////////////////////////////////////////////////// +// // Description: +// // Changes the power state of the device +// // +// // Input: +// // State - true= power on; false = power off +// // +// // Remarks: +// // This function allows systems to conserve power by +// // shutting down the hardware when the system is +// // going into low power states. +// // +// void SetPowerState( uint32_t State ) { this->m_BSD->SetPowerState(this->m_context, State); } + +// bool FindRegionFromAddress(ByteAddress Address, uint32_t &BlockRegionIndex, uint32_t &BlockRangeIndex ) +// { +// const DeviceBlockInfo* pDevInfo = GetDeviceInfo(); + +// return pDevInfo->FindRegionFromAddress( Address, BlockRegionIndex, BlockRangeIndex ); +// } + +// bool FindForBlockUsage(uint32_t blockUsage, ByteAddress &Address, uint32_t &BlockRegionIndex, uint32_t &BlockRangeIndex ) +// { +// const DeviceBlockInfo* pDevInfo = GetDeviceInfo(); + +// return pDevInfo->FindForBlockUsage( blockUsage, Address, BlockRegionIndex, BlockRangeIndex ); +// } + +// bool FindNextUsageBlock(uint32_t blockUsage, ByteAddress &Address, uint32_t &BlockRegionIndex, uint32_t &BlockRangeIndex ) +// { +// const DeviceBlockInfo* pDevInfo = GetDeviceInfo(); + +// return pDevInfo->FindNextUsageBlock( blockUsage, Address, BlockRegionIndex, BlockRangeIndex ); +// } + + +// uint32_t MaxSectorWrite_uSec() +// { +// return this->m_BSD->MaxSectorWrite_uSec(this->m_context); +// } + +// uint32_t MaxBlockErase_uSec() +// { +// return this->m_BSD->MaxBlockErase_uSec(this->m_context); +// } + +// IBlockStorageDevice* m_BSD; // Vtable for this device +// void* m_context; // configuration for this instance of this driver + +// }; + +// -- global List + +// struct BlockStorageList +// { +// // initailize the storage +// __nfweak static void Initialize(); + +// // walk through list of devices and calls Init() function +// __nfweak static bool InitializeDevices(); + +// // walk through list of devices and calls UnInit() function +// __nfweak static bool UnInitializeDevices(); + +// // add pBSD to the list +// // If Init=true, the Init() will be called. +// __nfweak static bool AddDevice( BlockStorageDevice* pBSD, IBlockStorageDevice* vtable, void* config, bool Init); + +// // remove pBSD from the list +// // Uninit = true, UnInit() will be called. +// __nfweak static bool RemoveDevice( BlockStorageDevice* pBSD, bool UnInit); + +// // Find the right Device with the corresponding phyiscal address. +// // +// __nfweak static bool FindDeviceForPhysicalAddress( BlockStorageDevice** pBSD, uint32_t PhysicalAddress, ByteAddress &BlockAddress); + +// __nfweak static BlockStorageDevice* GetFirstDevice(); + +// __nfweak static BlockStorageDevice* GetNextDevice( BlockStorageDevice& device ); + +// // returns number of devices has been declared in the system +// __nfweak static uint32_t GetNumDevices(); + +// // pointer to the BlockStorageDevice which is the primary device with CONFIG block +// static BlockStorageDevice* s_primaryDevice; + +// private: +// // global pointer of all the storage devices +// static HAL_DblLinkedList s_deviceList; + +// static bool s_Initialized; +// }; + +//////////////////////////////////////////////////////////////////////////////// + +// functions to included all the devices to be added in the system +void BlockStorage_AddDevices(); + +/////////////////////////////////////////////////////////////////////////////// + +#define FLASH_PROTECTION_KEY 0x1055AADD + + + +#define FLASH_BEGIN_PROGRAMMING_FAST() { GLOBAL_LOCK(FlashIrq) +#define FLASH_BEGIN_PROGRAMMING(x) { uint32_t FlashOperationStatus = Flash_StartOperation( x ) +#define FLASH_END_PROGRAMMING(banner,address) Flash_EndOperation( FlashOperationStatus ); } +#define FLASH_END_PROGRAMMING_FAST(banner,address) } + + +//--// + +#endif // _TARGET_PAL_BLOCKSTORAGE_H_ + diff --git a/source/native/nf-interpreter/targets/os/win32/Include/Target_Windows_Storage.h b/source/native/nf-interpreter/targets/os/win32/Include/Target_Windows_Storage.h new file mode 100644 index 00000000..888c34fe --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/Include/Target_Windows_Storage.h @@ -0,0 +1,9 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_WINDOWS_STORAGE_H_ +#define _TARGET_WINDOWS_STORAGE_H_ 1 + +#endif //_TARGET_WINDOWS_STORAGE_H_ diff --git a/source/native/nf-interpreter/targets/os/win32/Include/targetHAL.h b/source/native/nf-interpreter/targets/os/win32/Include/targetHAL.h new file mode 100644 index 00000000..287b1d37 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/Include/targetHAL.h @@ -0,0 +1,59 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_HAL_H_ +#define _TARGET_HAL_H_ + +// #include + +#if defined(_WIN32) +#define NANOCLR_STOP() ::DebugBreak() +#pragma warning( error : 4706 ) // error C4706: assignment within conditional expression +#endif + +#if !defined(BUILD_RTM) + +inline void __cdecl HARD_Breakpoint() +{ + if(::IsDebuggerPresent()) + { + ::DebugBreak(); + } +} + +#define HARD_BREAKPOINT() HARD_Breakpoint() + +inline bool Target_ConfigUpdateRequiresErase() +{ + return true; +} + +// #if defined(_DEBUG) +// #define DEBUG_HARD_BREAKPOINT() HARD_Breakpoint() +// #else +// #define DEBUG_HARD_BREAKPOINT() +// #endif + +// #else + +// #define HARD_BREAKPOINT() +// #define DEBUG_HARD_BREAKPOINT() + +#endif // !defined(BUILD_RTM) + + +inline bool Target_HasNanoBooter() { return false; }; + +inline uint32_t GetPlatformCapabilities() +{ + return 0; +}; + +inline uint32_t GetTargetCapabilities() +{ + return 0; +}; + +#endif //_TARGET_HAL_H_ diff --git a/source/native/nf-interpreter/targets/os/win32/Include/targetHAL_Power.h b/source/native/nf-interpreter/targets/os/win32/Include/targetHAL_Power.h new file mode 100644 index 00000000..30060ef3 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/Include/targetHAL_Power.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _TARGET_HAL_POWER_H_ +#define _TARGET_HAL_POWER_H_ 1 + +inline void CPU_Reset(){ ::ExitProcess( 0 ); }; +inline bool CPU_IsSoftRebootSupported() { return true; }; + +#endif //_TARGET_HAL_POWER_H_ diff --git a/source/native/nf-interpreter/targets/os/win32/Include/targetHAL_Time.h b/source/native/nf-interpreter/targets/os/win32/Include/targetHAL_Time.h new file mode 100644 index 00000000..0c580877 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/Include/targetHAL_Time.h @@ -0,0 +1,74 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _TARGET_HAL_TIME_H_ +#define _TARGET_HAL_TIME_H_ 1 + + +#define HAL_Time_CurrentSysTicks HAL_Time_CurrentSysTicks +unsigned int HAL_Time_CurrentSysTicks(); + + + + + + +///// +///// Converts 64bit time value to SystemTime structure. 64bit time is assumed as an offset from 1/1/1601:00:00:00.000 in 100ns. +///// +///// True if conversion is successful. +//bool Time_ToSystemTime(TIME time, SYSTEMTIME* systemTime); +// +///// +///// Converts SystemTime structure to 64bit time, which is assumed as an offset from 1/1/1601:00:00:00.000 in 100ns. +///// +///// Time value. +//TIME Time_FromSystemTime(const SYSTEMTIME* systemTime); +// +///// +///// Retrieves time since device was booted. +///// +///// Time in 100ns. +//signed __int64 HAL_Time_GetMachineTime(); +// +///// +///// Offset from GMT. +///// +///// In minutes, for example Pacific Time would be GMT-8 = -480. +//signed int Time_GetTimeZoneOffset(); +// +///// +///// UTC time according to this system. +///// +///// Returns current UTC time in 100ns elapsed since 1/1/1601:00:00:00.000 UTC. +//signed __int64 Time_GetUtcTime(); +// +///// +///// Local time according to the Time subsystem. +///// +///// Local time in 100ns elapsed since 1/1/1601:00:00:00.000 local time. +//signed __int64 Time_GetLocalTime(); +// +///// +///// Retrieves number of days since the beginning of the year given a month and a year. Calculates for leap years. +///// +///// S_OK if successful. +//HRESULT Time_AccDaysInMonth(signed int year, signed int month, signed int* days); +// +///// +///// Retrieves number of days given a month and a year. Calculates for leap years. +///// +///// S_OK if successful. +//HRESULT Time_DaysInMonth(signed int year, signed int month, signed int* days); +// +///// APIs to convert between types +//bool Time_TimeSpanToStringEx( const signed __int64& ticks, char*& buf, size_t& len ); +//const char* Time_TimeSpanToString( const signed __int64& ticks ); +//bool Time_DateTimeToStringEx( const signed __int64& time, char*& buf, size_t& len ); +//const char* Time_DateTimeToString( const signed __int64& time); +//const char* Time_CurrentDateTimeToString(); + + +#endif //_TARGET_HAL_TIME_H_ diff --git a/source/native/nf-interpreter/targets/os/win32/Include/targetPAL_time.h b/source/native/nf-interpreter/targets/os/win32/Include/targetPAL_time.h new file mode 100644 index 00000000..5e999482 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/Include/targetPAL_time.h @@ -0,0 +1,9 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGET_PAL_TIME_H_ +#define _TARGET_PAL_TIME_H_ 1 + +#endif //_TARGET_PAL_TIME_H_ diff --git a/source/native/nf-interpreter/targets/os/win32/Include/target_BlockStorage.h b/source/native/nf-interpreter/targets/os/win32/Include/target_BlockStorage.h new file mode 100644 index 00000000..aa50b1b7 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/Include/target_BlockStorage.h @@ -0,0 +1,12 @@ +// +// Copyright (c) 2019 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#ifndef _TARGETPAL_BLOCKSTORAGE_H_ +#define _TARGETPAL_BLOCKSTORAGE_H_ 1 + +// this device has 1 block storage devices +#define TARGET_BLOCKSTORAGE_COUNT 1 + +#endif //_TARGETPAL_BLOCKSTORAGE_H_ diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR.sln b/source/native/nf-interpreter/targets/os/win32/nanoCLR.sln new file mode 100644 index 00000000..89b08188 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR.sln @@ -0,0 +1,319 @@ + +Microsoft Visual Studio Solution File, Format Version 12.00 +# Visual Studio 15 +VisualStudioVersion = 15.0.27130.2027 +MinimumVisualStudioVersion = 10.0.40219.1 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "nanoCLR", "nanoCLR\nanoCLR.vcxproj", "{B5515C8A-B056-4320-8EA4-8CACE21A7D2E}" + ProjectSection(ProjectDependencies) = postProject + {247F9798-E240-4D5B-956D-35E5EAD21CE2} = {247F9798-E240-4D5B-956D-35E5EAD21CE2} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Core", "..\..\..\src\CLR\Core\Core.vcxproj", "{89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "CorLib", "..\..\..\src\CLR\CorLib\CorLib.vcxproj", "{58E950CC-2FF6-423C-B006-A70A19272F20}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Diagnostics", "..\..\..\src\CLR\Diagnostics\Diagnostics.vcxproj", "{A5E9AE41-F4FA-40CE-AD82-A7861EBA007B}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Startup", "..\..\..\src\CLR\Startup\StartUp.vcxproj", "{2A840DC3-FFA8-4562-BD13-AB2B0BA02CB6}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Messaging", "..\..\..\src\CLR\Messaging\Messaging.vcxproj", "{131001E3-0201-451F-A87B-951D1C5C3EEE}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Debugger", "..\..\..\src\CLR\Debugger\Debugger.vcxproj", "{DD397EC4-844B-4B59-A67B-CAD6B46F1F00}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "WireProtocol", "..\..\..\src\CLR\WireProtocol\WireProtocol.vcxproj", "{2337C4A4-3AB4-4014-9C29-9EBE32F4510E}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Hardware", "..\..\..\src\CLR\Core\Hardware\Hardware.vcxproj", "{5D50772E-DAC8-407D-972F-37DEB4450B72}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "InterruptHandler", "..\..\..\src\CLR\Core\InterruptHandler\InterruptHandler.vcxproj", "{D32EE397-7E49-452D-AC95-AFCB3C962E3D}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "RPC", "..\..\..\src\CLR\Core\RPC\RPC.vcxproj", "{ED4C887A-EC09-465B-B5D9-075450ADC52D}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Serialization", "..\..\..\src\CLR\Core\Serialization\Serialization.vcxproj", "{16BF6131-A3B8-4B97-B867-E45669FB48BD}" +EndProject +Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "Features", "Features", "{76169580-0DE3-48D0-9545-8FC438C54094}" +EndProject +Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "Stubs", "Stubs", "{2662E293-2538-40C2-9472-D936B1220EC2}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Debugger_stub", "..\..\..\src\CLR\Debugger\Debugger_stub.vcxproj", "{6DABCBF1-245A-4E76-BD36-8BC300C7DD82}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Diagnostics_stub", "..\..\..\src\CLR\Diagnostics\Diagnostics_stub.vcxproj", "{C97A9845-02DC-46E4-B219-BF5EA8FB28E3}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "InterruptHandler_stub", "..\..\..\src\CLR\Core\InterruptHandler\InterruptHandler_stub.vcxproj", "{5772D362-7277-49CF-9B49-42335A3154BD}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "NativeEventDispatcher_stub", "..\..\..\src\CLR\Core\NativeEventDispatcher\NativeEventDispatcher_stub.vcxproj", "{5406EB0C-2243-47E1-9F21-F2D7CA277092}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Messaging_stub", "..\..\..\src\CLR\Messaging\Messaging_stub.vcxproj", "{8ACD05E8-42FB-4A49-9D8B-79239F0EED25}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "RPC_stub", "..\..\..\src\CLR\Core\RPC\RPC_stub.vcxproj", "{D0B2ADFE-3347-4D73-9364-9C36935D12F8}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Serialization_stub", "..\..\..\src\CLR\Core\Serialization\Serialization_stub.vcxproj", "{C337041D-344D-49FE-AD99-B137E7FD0188}" +EndProject +Project("{11A8DD76-328B-46DF-9F39-F559912D0360}") = "NF.TestApplication", "netnf\TestApplication\NF.TestApplication.nfproj", "{247F9798-E240-4D5B-956D-35E5EAD21CE2}" +EndProject +Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = ".nuget", ".nuget", "{A5089650-2C81-4C04-ABA9-AABCEBDA3AA4}" + ProjectSection(SolutionItems) = preProject + packages.config = packages.config + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "Hardware_stub", "..\..\..\src\CLR\Core\Hardware\Hardware_stub.vcxproj", "{31253D7F-147E-49A3-BC0D-E0ADE6CF040B}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "NativeEventDispatcher", "..\..\..\src\CLR\Core\NativeEventDispatcher\NativeEventDispatcher.vcxproj", "{6DD5CA4F-2AE9-44D3-B9D7-A2A4A35FC5B2}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|Any CPU = Debug|Any CPU + Debug|x64 = Debug|x64 + Debug|x86 = Debug|x86 + Release|Any CPU = Release|Any CPU + Release|x64 = Release|x64 + Release|x86 = Release|x86 + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {B5515C8A-B056-4320-8EA4-8CACE21A7D2E}.Debug|Any CPU.ActiveCfg = Debug|Win32 + {B5515C8A-B056-4320-8EA4-8CACE21A7D2E}.Debug|x64.ActiveCfg = Debug|x64 + {B5515C8A-B056-4320-8EA4-8CACE21A7D2E}.Debug|x64.Build.0 = Debug|x64 + {B5515C8A-B056-4320-8EA4-8CACE21A7D2E}.Debug|x86.ActiveCfg = Debug|Win32 + {B5515C8A-B056-4320-8EA4-8CACE21A7D2E}.Debug|x86.Build.0 = Debug|Win32 + {B5515C8A-B056-4320-8EA4-8CACE21A7D2E}.Release|Any CPU.ActiveCfg = Release|Win32 + {B5515C8A-B056-4320-8EA4-8CACE21A7D2E}.Release|x64.ActiveCfg = Release|x64 + {B5515C8A-B056-4320-8EA4-8CACE21A7D2E}.Release|x64.Build.0 = Release|x64 + {B5515C8A-B056-4320-8EA4-8CACE21A7D2E}.Release|x86.ActiveCfg = Release|Win32 + {B5515C8A-B056-4320-8EA4-8CACE21A7D2E}.Release|x86.Build.0 = Release|Win32 + {89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}.Debug|Any CPU.ActiveCfg = Debug|Win32 + {89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}.Debug|x64.ActiveCfg = Debug|x64 + {89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}.Debug|x64.Build.0 = Debug|x64 + {89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}.Debug|x86.ActiveCfg = Debug|Win32 + {89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}.Debug|x86.Build.0 = Debug|Win32 + {89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}.Release|Any CPU.ActiveCfg = Release|Win32 + {89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}.Release|x64.ActiveCfg = Release|x64 + {89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}.Release|x64.Build.0 = Release|x64 + {89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}.Release|x86.ActiveCfg = Release|Win32 + {89CF8BDB-9C8A-4D18-BC3E-4312C5BD34B1}.Release|x86.Build.0 = Release|Win32 + {58E950CC-2FF6-423C-B006-A70A19272F20}.Debug|Any CPU.ActiveCfg = Debug|Win32 + {58E950CC-2FF6-423C-B006-A70A19272F20}.Debug|x64.ActiveCfg = Debug|x64 + {58E950CC-2FF6-423C-B006-A70A19272F20}.Debug|x64.Build.0 = Debug|x64 + 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{247F9798-E240-4D5B-956D-35E5EAD21CE2}.Debug|x64.ActiveCfg = Debug|Any CPU + {247F9798-E240-4D5B-956D-35E5EAD21CE2}.Debug|x64.Build.0 = Debug|Any CPU + {247F9798-E240-4D5B-956D-35E5EAD21CE2}.Debug|x86.ActiveCfg = Debug|Any CPU + {247F9798-E240-4D5B-956D-35E5EAD21CE2}.Debug|x86.Build.0 = Debug|Any CPU + {247F9798-E240-4D5B-956D-35E5EAD21CE2}.Release|Any CPU.ActiveCfg = Release|Any CPU + {247F9798-E240-4D5B-956D-35E5EAD21CE2}.Release|Any CPU.Build.0 = Release|Any CPU + {247F9798-E240-4D5B-956D-35E5EAD21CE2}.Release|x64.ActiveCfg = Release|Any CPU + {247F9798-E240-4D5B-956D-35E5EAD21CE2}.Release|x64.Build.0 = Release|Any CPU + {247F9798-E240-4D5B-956D-35E5EAD21CE2}.Release|x86.ActiveCfg = Release|Any CPU + {31253D7F-147E-49A3-BC0D-E0ADE6CF040B}.Debug|Any CPU.ActiveCfg = Debug|Win32 + {31253D7F-147E-49A3-BC0D-E0ADE6CF040B}.Debug|x64.ActiveCfg = Debug|x64 + {31253D7F-147E-49A3-BC0D-E0ADE6CF040B}.Debug|x64.Build.0 = Debug|x64 + {31253D7F-147E-49A3-BC0D-E0ADE6CF040B}.Debug|x86.ActiveCfg = Debug|Win32 + {31253D7F-147E-49A3-BC0D-E0ADE6CF040B}.Debug|x86.Build.0 = Debug|Win32 + {31253D7F-147E-49A3-BC0D-E0ADE6CF040B}.Release|Any CPU.ActiveCfg = Release|Win32 + {31253D7F-147E-49A3-BC0D-E0ADE6CF040B}.Release|x64.ActiveCfg = Release|x64 + {31253D7F-147E-49A3-BC0D-E0ADE6CF040B}.Release|x64.Build.0 = Release|x64 + {31253D7F-147E-49A3-BC0D-E0ADE6CF040B}.Release|x86.ActiveCfg = Release|Win32 + {31253D7F-147E-49A3-BC0D-E0ADE6CF040B}.Release|x86.Build.0 = Release|Win32 + {6DD5CA4F-2AE9-44D3-B9D7-A2A4A35FC5B2}.Debug|Any CPU.ActiveCfg = Debug|Win32 + {6DD5CA4F-2AE9-44D3-B9D7-A2A4A35FC5B2}.Debug|x64.ActiveCfg = Debug|x64 + {6DD5CA4F-2AE9-44D3-B9D7-A2A4A35FC5B2}.Debug|x64.Build.0 = Debug|x64 + {6DD5CA4F-2AE9-44D3-B9D7-A2A4A35FC5B2}.Debug|x86.ActiveCfg = Debug|Win32 + {6DD5CA4F-2AE9-44D3-B9D7-A2A4A35FC5B2}.Debug|x86.Build.0 = Debug|Win32 + {6DD5CA4F-2AE9-44D3-B9D7-A2A4A35FC5B2}.Release|Any CPU.ActiveCfg = Release|Win32 + {6DD5CA4F-2AE9-44D3-B9D7-A2A4A35FC5B2}.Release|x64.ActiveCfg = Release|x64 + {6DD5CA4F-2AE9-44D3-B9D7-A2A4A35FC5B2}.Release|x64.Build.0 = Release|x64 + {6DD5CA4F-2AE9-44D3-B9D7-A2A4A35FC5B2}.Release|x86.ActiveCfg = Release|Win32 + {6DD5CA4F-2AE9-44D3-B9D7-A2A4A35FC5B2}.Release|x86.Build.0 = Release|Win32 + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection + GlobalSection(NestedProjects) = preSolution + {A5E9AE41-F4FA-40CE-AD82-A7861EBA007B} = {76169580-0DE3-48D0-9545-8FC438C54094} + {131001E3-0201-451F-A87B-951D1C5C3EEE} = {76169580-0DE3-48D0-9545-8FC438C54094} + {DD397EC4-844B-4B59-A67B-CAD6B46F1F00} = {76169580-0DE3-48D0-9545-8FC438C54094} + {2337C4A4-3AB4-4014-9C29-9EBE32F4510E} = {76169580-0DE3-48D0-9545-8FC438C54094} + {5D50772E-DAC8-407D-972F-37DEB4450B72} = {76169580-0DE3-48D0-9545-8FC438C54094} + {D32EE397-7E49-452D-AC95-AFCB3C962E3D} = {76169580-0DE3-48D0-9545-8FC438C54094} + {ED4C887A-EC09-465B-B5D9-075450ADC52D} = {76169580-0DE3-48D0-9545-8FC438C54094} + {16BF6131-A3B8-4B97-B867-E45669FB48BD} = {76169580-0DE3-48D0-9545-8FC438C54094} + {6DABCBF1-245A-4E76-BD36-8BC300C7DD82} = {2662E293-2538-40C2-9472-D936B1220EC2} + {C97A9845-02DC-46E4-B219-BF5EA8FB28E3} = {2662E293-2538-40C2-9472-D936B1220EC2} + {5772D362-7277-49CF-9B49-42335A3154BD} = {2662E293-2538-40C2-9472-D936B1220EC2} + {5406EB0C-2243-47E1-9F21-F2D7CA277092} = {2662E293-2538-40C2-9472-D936B1220EC2} + {8ACD05E8-42FB-4A49-9D8B-79239F0EED25} = {2662E293-2538-40C2-9472-D936B1220EC2} + {D0B2ADFE-3347-4D73-9364-9C36935D12F8} = {2662E293-2538-40C2-9472-D936B1220EC2} + {C337041D-344D-49FE-AD99-B137E7FD0188} = {2662E293-2538-40C2-9472-D936B1220EC2} + {31253D7F-147E-49A3-BC0D-E0ADE6CF040B} = {2662E293-2538-40C2-9472-D936B1220EC2} + {6DD5CA4F-2AE9-44D3-B9D7-A2A4A35FC5B2} = {76169580-0DE3-48D0-9545-8FC438C54094} + EndGlobalSection + GlobalSection(ExtensibilityGlobals) = postSolution + SolutionGuid = {432A3A35-F7BC-47DA-B887-9F18A369A065} + EndGlobalSection +EndGlobal diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/CLRStartup.cpp b/source/native/nf-interpreter/targets/os/win32/nanoCLR/CLRStartup.cpp new file mode 100644 index 00000000..d4686e7e --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/CLRStartup.cpp @@ -0,0 +1,736 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "stdafx.h" + +#if defined(_WIN32) + + +#endif + +//////////////////////////////////////////////////////////////////////////////// + +struct Settings +#if defined(_WIN32) +: CLR_RT_ParseOptions +#endif +{ + CLR_SETTINGS m_clrOptions; +#if defined(_WIN32) + CLR_RT_ParseOptions::BufferMap m_assemblies; +#endif + bool m_fInitialized; + + //--// + + HRESULT Initialize(CLR_SETTINGS params) + { + NANOCLR_HEADER(); + + m_clrOptions = params; + +#if defined(PLATFORM_WINDOWS_EMULATOR) + g_CLR_RT_ExecutionEngine.m_fPerformGarbageCollection = params.PerformGarbageCollection; + g_CLR_RT_ExecutionEngine.m_fPerformHeapCompaction = params.PerformHeapCompaction; + + CLR_UINT32 clockFrequencyBaseline = 27000000; + CLR_UINT32 clockFrequency = CPU_SystemClock(); + double clockFrequencyRatio = 1; + + if(clockFrequency > 0) + { + clockFrequencyRatio = (double)clockFrequencyBaseline / (double)clockFrequency; + } + + g_HAL_Configuration_Windows.ProductType = HAL_Configuration_Windows::Product_Aux; + g_HAL_Configuration_Windows.SlowClockPerSecond = 32768; + g_HAL_Configuration_Windows.TicksPerMethodCall = (CLR_UINT64)(45.0*clockFrequencyRatio); + g_HAL_Configuration_Windows.TicksPerOpcode = (CLR_UINT64)( 5.0*clockFrequencyRatio); + g_HAL_Configuration_Windows.GraphHeapEnabled = false; +#endif + + NANOCLR_CHECK_HRESULT(CLR_RT_ExecutionEngine::CreateInstance()); +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Created EE.\r\n" ); +#endif + +#if !defined(BUILD_RTM) + if(params.WaitForDebugger) + { +#if defined(_WIN32) + CLR_EE_DBG_SET( Enabled ); +#endif + CLR_EE_DBG_SET( Stopped ); + } +#endif + + NANOCLR_CHECK_HRESULT(g_CLR_RT_ExecutionEngine.StartHardware()); +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Started Hardware.\r\n" ); +#endif + + m_fInitialized = true; + + + NANOCLR_NOCLEANUP(); + } + + + HRESULT LoadAssembly( const CLR_RECORD_ASSEMBLY* header, CLR_RT_Assembly*& assm ) + { + NANOCLR_HEADER(); + + const CLR_RT_NativeAssemblyData *pNativeAssmData; + + NANOCLR_CHECK_HRESULT(CLR_RT_Assembly::CreateInstance( header, assm )); + + // Get handlers for native functions in assembly + pNativeAssmData = GetAssemblyNativeData( assm->m_szName ); + + // If pNativeAssmData not NULL- means this assembly has native calls and there is pointer to table with native calls. + if ( pNativeAssmData != NULL ) + { + // First verify that check sum in assembly object matches hardcoded check sum. + if ( assm->m_header->nativeMethodsChecksum != pNativeAssmData->m_checkSum ) + { + CLR_Debug::Printf("***********************************************************************\r\n"); + CLR_Debug::Printf("* *\r\n"); + CLR_Debug::Printf("* ERROR!!!! Firmware version does not match managed code version!!!! *\r\n"); + CLR_Debug::Printf("* *\r\n"); + CLR_Debug::Printf("* *\r\n"); + CLR_Debug::Printf("* Invalid native checksum: %s 0x%08X!=0x%08X *\r\n", + assm->m_szName, + assm->m_header->nativeMethodsChecksum, + pNativeAssmData->m_checkSum + ); + CLR_Debug::Printf("* *\r\n"); + CLR_Debug::Printf("***********************************************************************\r\n"); + + NANOCLR_SET_AND_LEAVE(CLR_E_ASSM_WRONG_CHECKSUM); + } + + // Assembly has valid pointer to table with native methods. Save it. + assm->m_nativeCode = (const CLR_RT_MethodHandler *)pNativeAssmData->m_pNativeMethods; + } + g_CLR_RT_TypeSystem.Link( assm ); + NANOCLR_NOCLEANUP(); + } + + + HRESULT Load() + { + NANOCLR_HEADER(); + + // clear flag (in case EE wasn't restarted) + CLR_EE_DBG_CLR(StateResolutionFailed); + +#if defined(_WIN32) + CLR_RT_StringVector vec; + + vec.push_back(L"-load"); +#if defined _DEBUG + vec.push_back(L"..\\netnf\\TestApplication\\bin\\Debug\\TestApplication.pe"); +#else + vec.push_back(L"..\\netnf\\TestApplication\\bin\\Release\\TestApplication.pe"); +#endif + + // grab mscorlib.pe from the packages folder (it has to be there because the NF.TestApplication has just build) + // ************************************************************************* // + // just need to update the path on the package folder as the version changes // + // ************************************************************************* // + vec.push_back(L"-load"); + vec.push_back(L"..\\packages\\nanoFramework.CoreLibrary.1.0.0-preview038\\lib\\mscorlib.pe"); + + // grab Windows.Devices.Gpio.pe from the packages folder (it has to be there because the NF.TestApplication has just build) + // ************************************************************************* // + // just need to update the path on the package folder as the version changes // + // ************************************************************************* // + vec.push_back(L"-load"); + vec.push_back(L"..\\packages\\nanoFramework.Windows.Devices.Gpio.1.0.0-preview164\\lib\\Windows.Devices.Gpio.pe"); + + // grab nanoFramework.Runtime.Events.pe from the packages folder (it has to be there because the NF.TestApplication has just build) + // ************************************************************************* // + // just need to update the path on the package folder as the version changes // + // ************************************************************************* // + vec.push_back(L"-load"); + vec.push_back(L"..\\packages\\nanoFramework.Runtime.Events.1.0.0-preview165\\lib\\nanoFramework.Runtime.Events.pe"); + + // grab Windows.Devices.Spi.pe from the packages folder (it has to be there because the NF.TestApplication has just build) + // ************************************************************************* // + // just need to update the path on the package folder as the version changes // + // ************************************************************************* // + vec.push_back(L"-load"); + vec.push_back(L"..\\packages\\nanoFramework.Windows.Devices.Spi.1.0.0-preview164\\lib\\Windows.Devices.Spi.pe"); + + + //vec.push_back(L"-load"); + //vec.push_back(L"C:\\Program Files (x86)\\Microsoft .NET Micro Framework\\v4.4\\Assemblies\\le\\Microsoft.SPOT.Native.pe"); + + //wchar_t* pContext = NULL; + //wchar_t* pch = wcstok_s(emulatorArgs, L" ", &pContext); // UNDONE: FIXME: wcstok_s(this->m_clrOptions.EmulatorArgs, L" ", &pContext); + + //while (pch != NULL) + //{ + // //printf ("%s\n",pch); + // vec.push_back(pch); + + // pch = wcstok_s(NULL, L" ", &pContext); + //} + + ProcessOptions(vec); + + for(CLR_RT_ParseOptions::BufferMapIter it = m_assemblies.begin(); it != m_assemblies.end(); it++) + { + CLR_RT_Assembly* assm; + const CLR_RT_Buffer* buffer = (const CLR_RT_Buffer*)it->second; + const CLR_RECORD_ASSEMBLY* header = (CLR_RECORD_ASSEMBLY*)&(*buffer)[0]; + + // Creates instance of assembly, sets pointer to native functions, links to g_CLR_RT_TypeSystem + NANOCLR_CHECK_HRESULT( LoadAssembly( header, assm ) ); + } +#else + +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Create TS.\r\n" ); +#endif + + NANOCLR_CHECK_HRESULT(LoadKnownAssemblies( nanoCLR_Dat_Start, nanoCLR_Dat_End )); + +#endif // defined(PLATFORM_WINDOWS_EMULATOR) + +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Loading Deployment Assemblies.\r\n" ); +#endif + + LoadDeploymentAssemblies( BlockUsage_DEPLOYMENT ); + + //--// + +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Resolving.\r\n" ); +#endif + NANOCLR_CHECK_HRESULT(g_CLR_RT_TypeSystem.ResolveAll()); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_TypeSystem.PrepareForExecution()); + +#if defined(NANOCLR_PROFILE_HANDLER) + CLR_PROF_Handler::Calibrate(); +#endif + + NANOCLR_CLEANUP(); + +#if !defined(BUILD_RTM) + if(FAILED(hr)) + { + CLR_Debug::Printf( "Error: %08x\r\n", hr ); + + if(hr == CLR_E_TYPE_UNAVAILABLE) + { + // exception occurred during type resolution + CLR_EE_DBG_SET(StateResolutionFailed); + } + } +#endif + + NANOCLR_CLEANUP_END(); + } + + HRESULT CheckKnownAssembliesForNonXIP( char** start, char** end ) + { + //--// + NANOCLR_HEADER(); + + BlockStorageDevice *device; + ByteAddress datByteAddress; + unsigned int datSize = ROUNDTOMULTIPLE((unsigned int)(*end)- (unsigned int)(*start), CLR_UINT32); + + if (BlockStorageList_FindDeviceForPhysicalAddress( &device, (unsigned int)(*start), &datByteAddress ) && device != NULL) + { + const DeviceBlockInfo * deviceInfo= BlockStorageDevice_GetDeviceInfo(device); + + if (deviceInfo->Attribute & MediaAttribute_SupportsXIP) + { + unsigned char * datAssembliesBuffer = (unsigned char*)CLR_RT_Memory::Allocate_And_Erase( datSize, CLR_RT_HeapBlock ::HB_Unmovable ); CHECK_ALLOCATION(datAssembliesBuffer); + + if ( !BlockStorageDevice_Read(device, datByteAddress, datSize, datAssembliesBuffer )) + { + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + } + *start = (char *)datAssembliesBuffer; + *end = (char *)((unsigned int) datAssembliesBuffer + (unsigned int)datSize); + + } + } + + // else data in RAM + NANOCLR_NOCLEANUP(); + } + + + HRESULT LoadKnownAssemblies( char* start, char* end ) + { + //--// + NANOCLR_HEADER(); + char *assStart = start; + char *assEnd = end; + const CLR_RECORD_ASSEMBLY* header; + + NANOCLR_CHECK_HRESULT(CheckKnownAssembliesForNonXIP( &assStart, &assEnd )); +#if !defined(BUILD_RTM) + CLR_Debug::Printf(" Loading start at %x, end %x\r\n", (unsigned int)assStart, (unsigned int)assEnd); +#endif + + g_buildCRC = SUPPORT_ComputeCRC( assStart, (unsigned int)assEnd -(unsigned int) assStart, 0 ); + + + header = (const CLR_RECORD_ASSEMBLY*)assStart; + + while((char*)header + sizeof(CLR_RECORD_ASSEMBLY) < assEnd && header->GoodAssembly()) + { + CLR_RT_Assembly* assm; + + // Creates instance of assembly, sets pointer to native functions, links to g_CLR_RT_TypeSystem + NANOCLR_CHECK_HRESULT(LoadAssembly( header, assm )); + + header = (const CLR_RECORD_ASSEMBLY*)ROUNDTOMULTIPLE((size_t)header + header->TotalSize(), CLR_UINT32); + } + + NANOCLR_NOCLEANUP(); + } + + + HRESULT ContiguousBlockAssemblies( BlockStorageStream stream, bool isXIP ) + { + NANOCLR_HEADER(); + + const CLR_RECORD_ASSEMBLY* header; + unsigned char * assembliesBuffer ; + signed int headerInBytes = sizeof(CLR_RECORD_ASSEMBLY); + unsigned char * headerBuffer = NULL; + + if(!isXIP) + { + headerBuffer = (unsigned char*)CLR_RT_Memory::Allocate( headerInBytes, true ); CHECK_ALLOCATION(headerBuffer); + CLR_RT_Memory::ZeroFill( headerBuffer, headerInBytes ); + } + + while(TRUE) + { + if(!BlockStorageStream_Read(&stream, &headerBuffer, headerInBytes )) break; + + header = (const CLR_RECORD_ASSEMBLY*)headerBuffer; + + // check header first before read + if(!header->GoodHeader()) + { + break; + } + + unsigned int AssemblySizeInByte = ROUNDTOMULTIPLE(header->TotalSize(), CLR_UINT32); + + if(!isXIP) + { + // read the assemblies + assembliesBuffer = (unsigned char*)CLR_RT_Memory::Allocate_And_Erase( AssemblySizeInByte, CLR_RT_HeapBlock ::HB_Unmovable ); + + if (!assembliesBuffer) + { + // release the headerbuffer which has being used and leave + CLR_RT_Memory::Release( headerBuffer ); + + NANOCLR_SET_AND_LEAVE(CLR_E_OUT_OF_MEMORY); + } + } + + BlockStorageStream_Seek(&stream, -headerInBytes, BlockStorageStream_SeekCurrent); + + if(!BlockStorageStream_Read(&stream, &assembliesBuffer, AssemblySizeInByte )) break; + + header = (const CLR_RECORD_ASSEMBLY*)assembliesBuffer; + + if(!header->GoodAssembly()) + { + if(!isXIP) CLR_RT_Memory::Release( assembliesBuffer ); + break; + } + + // we have good Assembly + CLR_RT_Assembly* assm; + +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Attaching deployed file.\r\n" ); +#endif + + // Creates instance of assembly, sets pointer to native functions, links to g_CLR_RT_TypeSystem + if (FAILED(LoadAssembly( header, assm ) )) + { + if(!isXIP) CLR_RT_Memory::Release( assembliesBuffer ); + break; + } + assm->m_flags |= CLR_RT_Assembly::Deployed; + } + if(!isXIP) CLR_RT_Memory::Release( headerBuffer ); + + NANOCLR_NOCLEANUP(); + } + + + HRESULT LoadDeploymentAssemblies( unsigned int memoryUsage ) + { + NANOCLR_HEADER(); + + BlockStorageStream stream; + const DeviceBlockInfo* deviceInfo; + + // find the block + if (!BlockStorageStream_Initialize(&stream, memoryUsage )) + { +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "ERROR: Could not find device for DEPLOYMENT usage\r\n" ); +#endif + NANOCLR_SET_AND_LEAVE(CLR_E_NOT_SUPPORTED); + } + + do + { + deviceInfo = BlockStorageDevice_GetDeviceInfo(stream.Device); + + ContiguousBlockAssemblies( stream, (deviceInfo->Attribute & MediaAttribute_SupportsXIP)); + } + while(BlockStorageStream_NextStream(&stream)); + + NANOCLR_NOCLEANUP(); + } + + void Cleanup() + { + CLR_RT_ExecutionEngine::DeleteInstance(); + + memset( &g_CLR_RT_ExecutionEngine, 0, sizeof(g_CLR_RT_ExecutionEngine)); + memset( &g_CLR_RT_WellKnownTypes, 0, sizeof(g_CLR_RT_WellKnownTypes)); + memset( &g_CLR_RT_WellKnownMethods, 0, sizeof(g_CLR_RT_WellKnownMethods)); + memset( &g_CLR_RT_TypeSystem, 0, sizeof(g_CLR_RT_TypeSystem)); + memset( &g_CLR_RT_EventCache, 0, sizeof(g_CLR_RT_EventCache)); + memset( &g_CLR_RT_GarbageCollector, 0, sizeof(g_CLR_RT_GarbageCollector)); + memset( &g_CLR_HW_Hardware, 0, sizeof(g_CLR_HW_Hardware)); + + m_fInitialized = false; + } + + Settings() + { + m_fInitialized = false; +#if defined(_WIN32) + BuildOptions(); +#endif + } + +#if defined(_WIN32) + ~Settings() + { + for(CLR_RT_ParseOptions::BufferMapIter it = m_assemblies.begin(); it != m_assemblies.end(); it++) + { + delete it->second; + } + + m_assemblies.clear(); // CLR_RT_ParseOptions::BufferMap m_assemblies; + } + + struct Command_Call : CLR_RT_ParseOptions::Command + { + typedef HRESULT (Settings::*FPN)( CLR_RT_ParseOptions::ParameterList* params ); + + Settings& m_parent; + FPN m_call; + + Command_Call( Settings& parent, FPN call, const wchar_t* szName, const wchar_t* szDescription ) + : CLR_RT_ParseOptions::Command( szName, szDescription ), m_parent(parent), m_call(call) + { + } + + virtual HRESULT Execute() + { + return (m_parent.*m_call)( &m_params ); + } + }; + +#define PARAM_GENERIC(parm1Name,parm1Desc) param = new CLR_RT_ParseOptions::Parameter_Generic( parm1Name, parm1Desc ); cmd->m_params.push_back( param ) +#define OPTION_CALL(fpn,optName,optDesc) cmd = new Command_Call( *this, &Settings::fpn, optName, optDesc ); m_commands.push_back( cmd ) +#define PARAM_EXTRACT_STRING(lst,idx) ((CLR_RT_ParseOptions::Parameter_Generic*)(*lst)[idx])->m_data.c_str() + + void BuildOptions() + { + CLR_RT_ParseOptions::Command* cmd; + CLR_RT_ParseOptions::Parameter* param; + + OPTION_CALL( Cmd_Load, L"-load", L"Loads an assembly formatted for nanoCLR" ); + PARAM_GENERIC( L"", L"File to load" ); + + OPTION_CALL( Cmd_LoadDatabase, L"-loadDatabase", L"Loads a set of assemblies" ); + PARAM_GENERIC( L"", L"Image to load" ); + + OPTION_CALL( Cmd_Resolve, L"-resolve", L"Tries to resolve cross-assembly references" ); + } + + HRESULT CheckAssemblyFormat( CLR_RECORD_ASSEMBLY* header, const wchar_t* src ) + { + NANOCLR_HEADER(); + + if(header->GoodAssembly() == false) + { + wprintf( L"Invalid assembly format for '%s': ", src ); + for(int i=0; imarker); i++) + { + wprintf( L"%02x", header->marker[i] ); + } + wprintf( L"\n" ); + + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + + NANOCLR_NOCLEANUP(); + } + + HRESULT Cmd_Load( CLR_RT_ParseOptions::ParameterList* params = NULL ) + { + NANOCLR_HEADER(); + + const wchar_t* szName = PARAM_EXTRACT_STRING( params, 0 ); + CLR_RT_Buffer* buffer = new CLR_RT_Buffer(); + CLR_RECORD_ASSEMBLY* header; + + NANOCLR_CHECK_HRESULT(CLR_RT_FileStore::LoadFile( szName, *buffer )); + + header = (CLR_RECORD_ASSEMBLY*)&(*buffer)[0]; NANOCLR_CHECK_HRESULT(CheckAssemblyFormat( header, szName )); + + m_assemblies[szName] = buffer; + + NANOCLR_CLEANUP(); + + if(FAILED(hr)) + { + delete buffer; + } + + NANOCLR_CLEANUP_END(); + } + + + HRESULT Cmd_LoadDatabase( CLR_RT_ParseOptions::ParameterList* params = NULL ) + { + NANOCLR_HEADER(); + + if(!m_fInitialized) + { + CLR_RT_ExecutionEngine::CreateInstance(); + } + + { + const wchar_t* szFile = PARAM_EXTRACT_STRING( params, 0 ); + CLR_RT_Buffer buffer; + CLR_RECORD_ASSEMBLY* header; + CLR_RECORD_ASSEMBLY* headerEnd; + std::wstring strName; + + NANOCLR_CHECK_HRESULT(CLR_RT_FileStore::LoadFile( szFile, buffer )); + + header = (CLR_RECORD_ASSEMBLY*)&buffer[0 ]; + headerEnd = (CLR_RECORD_ASSEMBLY*)&buffer[buffer.size()-1]; + + while(header + 1 <= headerEnd && header->GoodAssembly()) + { + CLR_RT_Buffer* bufferSub = new CLR_RT_Buffer(); + CLR_RECORD_ASSEMBLY* headerSub; + CLR_RT_Assembly* assm; + + bufferSub->resize( header->TotalSize() ); + + headerSub = (CLR_RECORD_ASSEMBLY*)&(*bufferSub)[0]; + + if((CLR_UINT8*)header + header->TotalSize() > (CLR_UINT8*)headerEnd) + { + //checksum passed, but not enough data in assembly + _ASSERTE(FALSE); + delete bufferSub; + break; + } + memcpy( headerSub, header, header->TotalSize() ); + + m_assemblies[strName] = bufferSub; + + if(FAILED(hr = CLR_RT_Assembly::CreateInstance( headerSub, assm ))) + { + delete bufferSub; + break; + } + + CLR_RT_UnicodeHelper::ConvertFromUTF8( assm->m_szName, strName ); m_assemblies[strName] = bufferSub; + + assm->DestroyInstance(); + + header = (CLR_RECORD_ASSEMBLY*)ROUNDTOMULTIPLE( (size_t)header + header->TotalSize(), CLR_UINT32 ); + } + } + + NANOCLR_CLEANUP(); + + if(!m_fInitialized) + { + CLR_RT_ExecutionEngine::DeleteInstance(); + } + + NANOCLR_CLEANUP_END(); + } + + HRESULT Cmd_Resolve( CLR_RT_ParseOptions::ParameterList* params = NULL ) + { + NANOCLR_HEADER(); + + bool fError = false; + + NANOCLR_FOREACH_ASSEMBLY(g_CLR_RT_TypeSystem) + { + const CLR_RECORD_ASSEMBLYREF* src = (const CLR_RECORD_ASSEMBLYREF*)pASSM->GetTable( TBL_AssemblyRef ); + for(int i=0; im_pTablesSize[TBL_AssemblyRef]; i++, src++) + { + const char* szName = pASSM->GetString( src->name ); + + if(g_CLR_RT_TypeSystem.FindAssembly( szName, &src->version, true ) == NULL) + { + printf( "Missing assembly: %s (%d.%d.%d.%d)\n", szName, src->version.iMajorVersion, src->version.iMinorVersion, src->version.iBuildNumber, src->version.iRevisionNumber ); + + fError = true; + } + } + } + NANOCLR_FOREACH_ASSEMBLY_END(); + + if(fError) NANOCLR_SET_AND_LEAVE(CLR_E_ENTRY_NOT_FOUND); + + NANOCLR_CHECK_HRESULT(g_CLR_RT_TypeSystem.ResolveAll()); + + NANOCLR_NOCLEANUP(); + } +#endif //#if defined(_WIN32) + +}; + +static Settings s_ClrSettings; + +//--// + +#if defined(_WIN32) +HRESULT ClrLoadPE( const wchar_t* szPeFilePath ) +{ + CLR_RT_StringVector vec; + + vec.push_back(L"-load"); + + vec.push_back(szPeFilePath); + + return s_ClrSettings.ProcessOptions(vec); +} + +HRESULT ClrLoadDAT( const wchar_t* szDatFilePath ) +{ + CLR_RT_StringVector vec; + + vec.push_back(L"-loadDatabase"); + + vec.push_back(szDatFilePath); + + return s_ClrSettings.ProcessOptions(vec); +} +#endif + + +void ClrStartup( CLR_SETTINGS params ) +{ + NATIVE_PROFILE_CLR_STARTUP(); + //Settings settings; + ASSERT(sizeof(CLR_RT_HeapBlock_Raw) == sizeof(CLR_RT_HeapBlock)); + bool softReboot; + + do + { + softReboot = false; + + CLR_RT_Assembly::InitString(); + +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "\r\nnanoCLR (Build %d.%d.%d.%d)\r\n\r\n", VERSION_MAJOR, VERSION_MINOR, VERSION_BUILD, VERSION_REVISION ); +#endif + + CLR_RT_Memory::Reset (); + +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Starting...\r\n" ); +#endif + + HRESULT hr; + + if(SUCCEEDED(hr = s_ClrSettings.Initialize(params))) + { + if(SUCCEEDED(hr = s_ClrSettings.Load())) + { +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Ready.\r\n" ); +#endif + +//#if defined(_WIN32) +// (void)g_CLR_RT_ExecutionEngine.Execute( params.EmulatorArgs, params.MaxContextSwitches ); +//#else + (void)g_CLR_RT_ExecutionEngine.Execute( NULL, params.MaxContextSwitches ); +//#endif + +#if !defined(BUILD_RTM) + CLR_Debug::Printf( "Done.\r\n" ); +#endif + } + } + + // process setting of power mode, if reboot was requested along with a power mode "higher" then PowerLevel__Active + if(CLR_EE_REBOOT_IS( ClrOnly ) && g_CLR_HW_Hardware.m_powerLevel > PowerLevel__Active) + { + CPU_SetPowerMode(g_CLR_HW_Hardware.m_powerLevel); + } + + if( CLR_EE_DBG_IS_NOT( RebootPending )) + { +#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + CLR_EE_DBG_SET_MASK(StateProgramExited, StateMask); + CLR_EE_DBG_EVENT_BROADCAST(CLR_DBG_Commands::c_Monitor_ProgramExit, 0, NULL,WP_Flags_c_NonCritical); +#endif //#if defined(NANOCLR_ENABLE_SOURCELEVELDEBUGGING) + + if(params.EnterDebuggerLoopAfterExit) + { + CLR_DBG_Debugger::Debugger_WaitForCommands(); + } + } + + // DO NOT USE 'ELSE IF' here because the state can change in Debugger_WaitForCommands() call + + if( CLR_EE_DBG_IS( RebootPending )) + { + if(CLR_EE_REBOOT_IS( ClrOnly )) + { + softReboot = true; + + params.WaitForDebugger = CLR_EE_REBOOT_IS(WaitForDebugger); + + s_ClrSettings.Cleanup(); + + //nanoHAL_Uninitialize(); + + //re-init the hal for the reboot (initially it is called in bootentry) + //nanoHAL_Initialize(); + } + else + { + CPU_Reset(); + } + } + } while( softReboot ); +} diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/Events.cpp b/source/native/nf-interpreter/targets/os/win32/nanoCLR/Events.cpp new file mode 100644 index 00000000..32da6a67 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/Events.cpp @@ -0,0 +1,64 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "stdafx.h" + +//using namespace Microsoft::SPOT::Emulator; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +//--// + +bool Events_Initialize() +{ + return TRUE; // UNDONE: FIXME: EmulatorNative::GetIEventsDriver()->Initialize(); +} + +bool Events_Uninitialize() +{ + return TRUE; // UNDONE: FIXME: EmulatorNative::GetIEventsDriver()->Uninitialize(); +} + +void Events_Set( uint32_t events ) +{ + // UNDONE: FIXME: EmulatorNative::GetIEventsDriver()->Set( Events ); +} + +uint32_t Events_Get( uint32_t eventsOfInterest ) +{ + return 0; // UNDONE: FIXME: EmulatorNative::GetIEventsDriver()->Get( EventsOfInterest ); +} + +void Events_Clear( uint32_t Events ) +{ + // UNDONE: FIXME: return EmulatorNative::GetIEventsDriver()->Clear( Events ); +} + +uint32_t Events_MaskedRead( uint32_t Events ) +{ + return 0; // UNDONE: FIXME: EmulatorNative::GetIEventsDriver()->MaskedRead( Events ); +} + +uint32_t Events_WaitForEvents( uint32_t powerLevel, uint32_t WakeupSystemEvents, uint32_t TimeoutMilliseconds ) +{ + return 0; // UNDONE: FIXME: EmulatorNative::GetIEventsDriver()->WaitForEvents( powerLevel, WakeupSystemEvents, TimeoutMilliseconds ); +} + +void Events_SetBoolTimer( bool* TimerCompleteFlag, uint32_t MillisecondsFromNow ) +{ + // UNDONE: FIXME: return EmulatorNative::GetIEventsDriver()->SetBoolTimer( (IntPtr)TimerCompleteFlag, MillisecondsFromNow ); +} + +void Events_SetCallback( set_Event_Callback pfn, void* arg ) +{ + _ASSERTE(FALSE); +} + +void FreeManagedEvent(UINT8 category, UINT8 subCategory, UINT16 data1, UINT32 data2) +{ + +} + + diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/FileStore_Win32.cpp b/source/native/nf-interpreter/targets/os/win32/nanoCLR/FileStore_Win32.cpp new file mode 100644 index 00000000..9dea424a --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/FileStore_Win32.cpp @@ -0,0 +1,237 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "stdafx.h" + + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +HRESULT CLR_RT_FileStore::LoadFile( const wchar_t* szFile, CLR_RT_Buffer& vec ) +{ + NANOCLR_HEADER(); + + FILE* stream; + if(_wfopen_s(&stream, szFile, L"rb" ) != 0) + { + wprintf( L"Cannot open '%s'!\n", szFile ); + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + + /*********/ fseek( stream, 0, SEEK_END ); + long size = ftell( stream ); + /*********/ fseek( stream, 0, SEEK_SET ); + + vec.resize( size ); + + if(vec.size() && fread( &vec[ 0 ], vec.size(), 1, stream ) != 1) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + + + NANOCLR_CLEANUP(); + + if(stream) + { + fclose( stream ); + } + + NANOCLR_CLEANUP_END(); +} + +HRESULT CLR_RT_FileStore::SaveFile( const wchar_t* szFile, const CLR_RT_Buffer& vec ) +{ + NANOCLR_HEADER(); + + const CLR_UINT8* buf = NULL; + size_t size = vec.size(); + + if(size > 0) + { + buf = &vec[ 0 ]; + } + + NANOCLR_SET_AND_LEAVE(SaveFile( szFile, buf, size )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_FileStore::SaveFile( const wchar_t* szFile, const CLR_UINT8* buf, size_t size ) +{ + NANOCLR_HEADER(); + FILE* stream; + + if(_wfopen_s(&stream, szFile, L"wb" ) != 0) + { + wprintf( L"Cannot open '%s' for writing!\n", szFile ); + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + + if(buf != NULL && size != 0) + { + if(fwrite( buf, size, 1, stream ) != 1) + { + NANOCLR_SET_AND_LEAVE(CLR_E_FAIL); + } + } + + NANOCLR_CLEANUP(); + + if(stream) + { + fclose( stream ); + } + + NANOCLR_CLEANUP_END(); +} + +//--// + +HRESULT CLR_RT_FileStore::ExtractTokensFromFile( const wchar_t* szFileName, std::vector< std::wstring >& vec, const wchar_t* separators, bool fNoComments ) +{ + NANOCLR_HEADER(); + + CLR_RT_Buffer buf; + + NANOCLR_CHECK_HRESULT(LoadFile( szFileName, buf )); + + ExtractTokens( buf, vec, separators, fNoComments ); + + NANOCLR_NOCLEANUP(); +} + +void CLR_RT_FileStore::ExtractTokens( const CLR_RT_Buffer& buf, CLR_RT_StringVector& vec, const wchar_t* separators, bool fNoComments ) +{ + std::wstring tmp; + char* szBufA = NULL; + wchar_t* szBufW = NULL; + const wchar_t* src; + size_t len; + + if (buf.size() == 0) { return; } + else if(buf.size() >= 2 && buf[ 0 ] == 0xFF && buf[ 1 ] == 0xFE) + { + len = (buf.size() - 2) / sizeof(wchar_t); + + src = (const wchar_t*)&buf[ 2 ]; + } + else + { + len = buf.size() / sizeof(char); + + szBufA = new char[ len+1 ]; memcpy( szBufA, &buf[ 0 ], len ); szBufA[ len ] = 0; + CLR_RT_UnicodeHelper::ConvertFromUTF8( szBufA, tmp ); + + src = tmp.c_str(); + len = tmp.size(); + } + + //--// + + szBufW = new wchar_t[ len+1 ]; memcpy( szBufW, src, len * sizeof(wchar_t) ); szBufW[ len ] = 0; + + vec.reserve( len / 60 ); + + ExtractTokensFromBuffer( szBufW, vec, separators, fNoComments ); + + //--// + + delete[] szBufW; + delete[] szBufA; +} + +void CLR_RT_FileStore::ExtractTokensFromBuffer( wchar_t* szLine, CLR_RT_StringVector& vec, const wchar_t* separators, bool fNoComments ) +{ + while(*szLine) + { + wchar_t* szNextLine = szLine; + + while(*szNextLine) + { + if(*szNextLine == '\r' || *szNextLine == '\n') + { + while(*szNextLine == '\r' || *szNextLine == '\n') + { + *szNextLine++ = 0; + } + + break; + } + + szNextLine++; + } + + if(fNoComments == false || szLine[ 0 ] != '#') + { + CLR_RT_FileStore::ExtractTokensFromString( szLine, vec, separators ); + } + + szLine = szNextLine; + } +} + +void CLR_RT_FileStore::ExtractTokensFromString( const wchar_t* szLine, CLR_RT_StringVector& vec, const wchar_t* separators ) +{ + if(separators) + { + while(szLine[ 0 ] && wcschr( separators, szLine[0] )) szLine++; + + while(szLine[ 0 ]) + { + wchar_t token [ 2048 ]; + wchar_t tokenExpanded[ 2048 ]; + bool fQuote = false; + size_t pos; + + for(pos=0; pos +#include +#include + +#define NATIVE_PROFILE_PAL_COM() + +////////////////////////////////////////////////////////////////////////////////// + +__nfweak bool DebuggerPort_Initialize( COM_HANDLE ComPortNum ) +{ + NATIVE_PROFILE_PAL_COM(); + return true; +} + +__nfweak bool DebuggerPort_Uninitialize( COM_HANDLE ComPortNum ) +{ + NATIVE_PROFILE_PAL_COM(); + return true; +} + +__nfweak int DebuggerPort_Write( COM_HANDLE ComPortNum, const char* Data, size_t size ) +{ + NATIVE_PROFILE_PAL_COM(); + return DebuggerPort_Write( ComPortNum, Data, size, COM_MAX_RETRIES ); +} + +__nfweak int DebuggerPort_Write( COM_HANDLE ComPortNum, const char* Data, size_t size, int maxRetries ) +{ + NATIVE_PROFILE_PAL_COM(); + return 0; +} + + +__nfweak int DebuggerPort_Read( COM_HANDLE ComPortNum, char* Data, size_t size ) +{ + NATIVE_PROFILE_PAL_COM(); + return 0; +} + +__nfweak bool DebuggerPort_Flush( COM_HANDLE ComPortNum ) +{ + NATIVE_PROFILE_PAL_COM(); + return true; +} + +__nfweak bool DebuggerPort_IsSslSupported( COM_HANDLE ComPortNum ) +{ + NATIVE_PROFILE_PAL_COM(); + return FALSE; +} + +__nfweak bool DebuggerPort_UpgradeToSsl( COM_HANDLE ComPortNum, unsigned int flags ) +{ + NATIVE_PROFILE_PAL_COM(); + return FALSE; +} + +__nfweak bool DebuggerPort_IsUsingSsl( COM_HANDLE ComPortNum ) +{ + NATIVE_PROFILE_PAL_COM(); + return FALSE; +} + +////////////////////////////////////////////////////////////////////////////////// + +void CPU_InitializeCommunication() +{ + NATIVE_PROFILE_PAL_COM(); +} + +void CPU_UninitializeCommunication() +{ + NATIVE_PROFILE_PAL_COM(); +} + + +void CPU_ProtectCommunicationGPIOs( bool On ) +{ + NATIVE_PROFILE_PAL_COM(); +} diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/PAL/ConfigHelper_stubs.cpp b/source/native/nf-interpreter/targets/os/win32/nanoCLR/PAL/ConfigHelper_stubs.cpp new file mode 100644 index 00000000..bf4258b0 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/PAL/ConfigHelper_stubs.cpp @@ -0,0 +1,76 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "stdafx.h" + +//--// + +//bool HAL_CONFIG_BLOCK::IsGoodBlock() const +//{ +// return TRUE; +//} +// +//bool HAL_CONFIG_BLOCK::IsGoodData() const +//{ +// return TRUE; +//} +// +//bool HAL_CONFIG_BLOCK::IsGood() const +//{ +// return TRUE; +//} +// +//const HAL_CONFIG_BLOCK* HAL_CONFIG_BLOCK::Next() const +//{ +// return NULL; +//} +// +//const void* HAL_CONFIG_BLOCK::Data() const +//{ +// return NULL; +//} +// +////--// +// +//bool HAL_CONFIG_BLOCK::Prepare( const char* Name, void* Data, unsigned int Size ) +//{ +// return TRUE; +//} +// +////--// +// +//const HAL_CONFIG_BLOCK* HAL_CONFIG_BLOCK::Find( const char* Name, bool fSkipCurrent, bool fAppend ) const +//{ +// return NULL; +//} +// +////--// +// +//bool HAL_CONFIG_BLOCK::GetConfigSectorAddress(HAL_CONFIG_BLOCK_STORAGE_DATA& blData) +//{ +// return FALSE; +//} +// +//bool HAL_CONFIG_BLOCK::CompactBlock(HAL_CONFIG_BLOCK_STORAGE_DATA& blData, const ConfigurationSector* cfgStatic, const HAL_CONFIG_BLOCK* cfgEnd) +//{ +// return FALSE; +//} +// +// +//bool HAL_CONFIG_BLOCK::UpdateBlock( const HAL_CONFIG_BLOCK_STORAGE_DATA &blData, const void* pAddress, const HAL_CONFIG_BLOCK *Header, void* Data, size_t Length, const void* LastConfigAddress, bool isChipRO ) +//{ +// return FALSE; +//} +// +//bool HAL_CONFIG_BLOCK::UpdateBlockWithName( const char* Name, void* Data, size_t Length, bool isChipRO ) +//{ +// return FALSE; +//} +// + +bool GetHalSystemInfo(HalSystemInfo& systemInfo) +{ + return FALSE; +} diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/PAL/Target_BlockStorage.cpp b/source/native/nf-interpreter/targets/os/win32/nanoCLR/PAL/Target_BlockStorage.cpp new file mode 100644 index 00000000..3d7d7349 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/PAL/Target_BlockStorage.cpp @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include +#include + +bool BlockStorageStream_Initialize(BlockStorageStream* stream, uint32_t blockUsage) +{ + return false; +} diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/PAL/Watchdog_stubs.cpp b/source/native/nf-interpreter/targets/os/win32/nanoCLR/PAL/Watchdog_stubs.cpp new file mode 100644 index 00000000..3c5522ad --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/PAL/Watchdog_stubs.cpp @@ -0,0 +1,12 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "stdafx.h" + +//--// + +void Watchdog_Init(){} + +void Watchdog_Reset(){} diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/PAL/blockstorageList_stubs.cpp b/source/native/nf-interpreter/targets/os/win32/nanoCLR/PAL/blockstorageList_stubs.cpp new file mode 100644 index 00000000..d924b548 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/PAL/blockstorageList_stubs.cpp @@ -0,0 +1,151 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "stdafx.h" + +//--// + +//HAL_DblLinkedList BlockStorageList::s_deviceList; +//BlockStorageDevice* BlockStorageList::s_primaryDevice = NULL; +static BlockStorageDevice* s_primaryDevice = NULL; + +//--// + +//void BlockStorageList::Initialize() +//{ +//} +// +//bool BlockStorageList::InitializeDevices() +//{ +// return TRUE; +//} +// +//bool BlockStorageList::UnInitializeDevices() +//{ +// return TRUE; +//} +// +//bool BlockStorageList::AddDevice( BlockStorageDevice* pBSD, IBlockStorageDevice* vtable, void* config, bool Init) +//{ +// return TRUE; +//} +bool BlockStorageList_AddDevice(BlockStorageDevice* pBSD, IBlockStorageDevice* vtable, void* config, bool init) +{ + s_primaryDevice = pBSD; + + // TODO what to do with vtable and config?? + return true; +} +// +//bool BlockStorageList::RemoveDevice( BlockStorageDevice* pBSD, bool UnInit) +//{ +// return TRUE; +//} + +//BlockStorageDevice* BlockStorageList::GetFirstDevice() +//{ +// return NULL; +//} +BlockStorageDevice* BlockStorageList_GetFirstDevice() +{ + return s_primaryDevice; +} + +//BlockStorageDevice* BlockStorageList::GetNextDevice( BlockStorageDevice& device ) +//{ +// return NULL; +//} + +//unsigned int BlockStorageList::GetNumDevices() +//{ +// return 0; +//} + +//bool BlockStorageList::FindDeviceForPhysicalAddress( BlockStorageDevice** pBSD, unsigned int PhysicalAddress, ByteAddress &SectAddress) +//{ +// *pBSD = NULL; +// return FALSE; +//} +bool BlockStorageList_FindDeviceForPhysicalAddress(BlockStorageDevice** pBSD, unsigned int physicalAddress, ByteAddress* blockAddress) +{ + return false; +} + +//bool BlockStorageStream::Initialize(unsigned int blockUsage) +//{ +// return FALSE; +//} +// +//bool BlockStorageStream::Initialize(unsigned int usage, BlockStorageDevice* pDevice) +//{ +// return FALSE; +//} +// +// +//unsigned int BlockStorageStream::CurrentAddress() +//{ +// return 0xFFFFFFFF; +//} +// +//bool BlockStorageStream::PrevStream() +//{ +// return FALSE; +//} +// +//bool BlockStorageStream::NextStream() +//{ +// return FALSE; +//} +// +//bool BlockStorageStream::Seek( signed int offset, SeekOrigin origin ) +//{ +// return TRUE; +//} +// +//bool BlockStorageStream::Erase( unsigned int length ) +//{ +// return TRUE; +//} +// +//bool BlockStorageStream::Write( unsigned char* data , unsigned int length ) +//{ +// return TRUE; +//} +// +//bool BlockStorageStream::ReadIntoBuffer( unsigned char* pBuffer, unsigned int length ) +//{ +// return TRUE; +//} +// +//bool BlockStorageStream::Read( unsigned char** ppBuffer, unsigned int length ) +//{ +// return TRUE; +//} +// + +//--// + +//SectorAddress DeviceBlockInfo::PhysicalToSectorAddress( const BlockRegionInfo* pRegion, ByteAddress phyAddress ) const +//{ +// return phyAddress; +//} +// +//bool DeviceBlockInfo::FindRegionFromAddress(ByteAddress Address, unsigned int &BlockRegionIndex, unsigned int &BlockRangeIndex ) const +//{ +// return FALSE; +//} +// +//bool DeviceBlockInfo::FindNextUsageBlock(unsigned int BlockUsage, ByteAddress &Address, unsigned int &BlockRegionIndex, unsigned int &BlockRangeIndex ) const +//{ +// return FALSE; +//} +// +//bool DeviceBlockInfo::FindForBlockUsage(unsigned int BlockUsage, ByteAddress &Address, unsigned int &BlockRegionIndex, unsigned int &BlockRangeIndex ) const +//{ +// return FALSE; +//} + + +//--// diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/PAL/time_stubs.cpp b/source/native/nf-interpreter/targets/os/win32/nanoCLR/PAL/time_stubs.cpp new file mode 100644 index 00000000..db709752 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/PAL/time_stubs.cpp @@ -0,0 +1,101 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "stdafx.h" + +HRESULT Time_Initialize() +{ + return CLR_E_NOTIMPL; +} + +HRESULT Time_Uninitialize() +{ + return CLR_E_NOTIMPL; +} + +// signed __int64 Time_GetUtcTime() +// { +// return 0; +// } + +signed __int64 Time_SetUtcTime( signed __int64 UtcTime, bool calibrate ) +{ + return 0; +} + +signed __int64 Time_GetLocalTime() +{ + return 0; +} + +signed int Time_GetTimeZoneOffset() +{ + return 0; +} + +signed int Time_SetTimeZoneOffset(signed int offset) +{ + return 0; +} + +signed __int64 Time_GetTickCount() +{ + return 0; +} + +bool HAL_Time_ToSystemTime(unsigned long long time, SYSTEMTIME* systemTime) +{ + return FALSE; +} + +uint64_t HAL_Time_ConvertFromSystemTime(const SYSTEMTIME* systemTime) +{ + return 0; +} + +HRESULT HAL_Time_DaysInMonth(signed int year, signed int month, signed int* days) +{ + return CLR_E_NOTIMPL; +} + +HRESULT HAL_Time_AccDaysInMonth(signed int year, signed int month, signed int* days) +{ + return CLR_E_NOTIMPL; +} + +bool Utility_SafeSprintfV( char*& szBuffer, size_t& iBuffer, const char* format, va_list arg ) +{ + return FALSE; +} + +bool Utility_SafeSprintf( char*& szBuffer, size_t& iBuffer, const char* format, ... ) +{ + return FALSE; +} + +bool HAL_Time_TimeSpanToStringEx( const signed __int64& ticks, char*& buf, size_t& len ) +{ + return FALSE; +} + +const char* HAL_Time_TimeSpanToString( const signed __int64& ticks ) +{ + return NULL; +} + +bool Time_DateTimeToStringEx( const signed __int64& time, char*& buf, size_t& len ) +{ + return FALSE; +} + +const char* Time_DateTimeToString( const signed __int64& time) +{ + return NULL; +} + +const char* HAL_Time_CurrentDateTimeToString() +{ + return NULL; +} diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/ParseOptions_Win32.cpp b/source/native/nf-interpreter/targets/os/win32/nanoCLR/ParseOptions_Win32.cpp new file mode 100644 index 00000000..a4e31d4d --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/ParseOptions_Win32.cpp @@ -0,0 +1,317 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "stdafx.h" + + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +CLR_RT_ParseOptions::Parameter::Parameter( const wchar_t* szName, const wchar_t* szDescription ) +{ + m_szName = szName; + m_szDescription = szDescription; +} + +//--// + +CLR_RT_ParseOptions::Parameter_Generic::Parameter_Generic( const wchar_t* szName, const wchar_t* szDescription ) : CLR_RT_ParseOptions::Parameter( szName, szDescription ) +{ +} + +bool CLR_RT_ParseOptions::Parameter_Generic::Parse( const wchar_t* arg ) +{ + m_data = arg; + + return true; +} + +//--// + +CLR_RT_ParseOptions::Parameter_String::Parameter_String( std::wstring* data, const wchar_t* szName, const wchar_t* szDescription ) : CLR_RT_ParseOptions::Parameter( szName, szDescription ) +{ + m_dataPtr = data ? data : &m_dataParsed; +} + +bool CLR_RT_ParseOptions::Parameter_String::Parse( const wchar_t* arg ) +{ + *m_dataPtr = arg; + + return true; +} + +//--// + +CLR_RT_ParseOptions::Parameter_Boolean::Parameter_Boolean( bool* data, const wchar_t* szName, const wchar_t* szDescription ) : CLR_RT_ParseOptions::Parameter( szName, szDescription ) +{ + m_dataPtr = data ? data : &m_dataParsed; +} + +bool CLR_RT_ParseOptions::Parameter_Boolean::Parse( const wchar_t* arg ) +{ + int num; + + if(!_wcsicmp( arg, L"true" ) || + !_wcsicmp( arg, L"on" ) ) + { + *m_dataPtr = true; + return true; + } + + if(!_wcsicmp( arg, L"false" ) || + !_wcsicmp( arg, L"off" ) ) + { + *m_dataPtr = false; + return true; + } + + if(swscanf_s( arg, L"%d", &num ) == 0) + { + wprintf( L"Expecting a boolean for parameter '%s': %s\n\n", m_szName, arg ); + return false; + } + + *m_dataPtr = (num != 0); + return true; +} + +//--// + +CLR_RT_ParseOptions::Parameter_Integer::Parameter_Integer( int* data, const wchar_t* szName, const wchar_t* szDescription ) : CLR_RT_ParseOptions::Parameter( szName, szDescription ) +{ + m_dataPtr = data ? data : &m_dataParsed; +} + +bool CLR_RT_ParseOptions::Parameter_Integer::Parse( const wchar_t* arg ) +{ + if(swscanf_s( arg, L"%d", m_dataPtr ) == 0) + { + wprintf( L"Expecting a number for parameter '%s': %s\n\n", m_szName, arg ); + return false; + } + + return true; +} + +//--// + +CLR_RT_ParseOptions::Parameter_Float::Parameter_Float( float* data, const wchar_t* szName, const wchar_t* szDescription ) : CLR_RT_ParseOptions::Parameter( szName, szDescription ) +{ + m_dataPtr = data ? data : &m_dataParsed; +} + +bool CLR_RT_ParseOptions::Parameter_Float::Parse( const wchar_t* arg ) +{ + if(swscanf_s( arg, L"%f", m_dataPtr ) == 0) + { + wprintf( L"Expecting a number for parameter '%s': %s\n\n", m_szName, arg ); + return false; + } + + return true; +} + +//--// + +CLR_RT_ParseOptions::Command::Command( const wchar_t* szName, const wchar_t* szDescription ) +{ + m_szName = szName; + m_szDescription = szDescription; +} + +bool CLR_RT_ParseOptions::Command::Parse( CLR_RT_StringVector& argv, size_t& pos, CLR_RT_ParseOptions& options ) +{ + size_t argc = argv.size(); + + for(ParameterListIter it = m_params.begin(); it != m_params.end(); it++) + { + Parameter* param = *it; + + if(pos >= argc) + { + if(options.m_commands.size() > 1) + { + wprintf( L"Missing parameter for option '%s': %s\n\n", m_szName, param->m_szName ); + } + else + { + wprintf( L"Missing parameter for option '%s'\n\n", param->m_szName ); + } + + return false; + } + else + { + if(param->Parse( argv[ pos++ ].c_str() ) == false) + { + return false; + } + } + } + + return true; +} + +HRESULT CLR_RT_ParseOptions::Command::Execute() +{ + NANOCLR_HEADER(); + + NANOCLR_NOCLEANUP_NOLABEL(); +} + +//--// + +CLR_RT_ParseOptions::Command_SetFlag::Command_SetFlag( bool* data, const wchar_t* szName, const wchar_t* szDescription ) : CLR_RT_ParseOptions::Command( szName, szDescription ) +{ + m_dataPtr = data ? data : &m_dataParsed; +} + +bool CLR_RT_ParseOptions::Command_SetFlag::Parse( CLR_RT_StringVector& argv, size_t& pos, CLR_RT_ParseOptions& options) +{ + *m_dataPtr = true; + return true; +} + +//--// + +CLR_RT_ParseOptions::CLR_RT_ParseOptions() +{ + m_fVerbose = false; +} + +HRESULT CLR_RT_ParseOptions::ExtractOptionsFromFile( const wchar_t* szFileName ) +{ + NANOCLR_HEADER(); + + CLR_RT_StringVector vec; + + NANOCLR_CHECK_HRESULT(CLR_RT_FileStore::ExtractTokensFromFile( szFileName, vec )); + + NANOCLR_CHECK_HRESULT(ProcessOptions( vec )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_ParseOptions::ReprocessOptions() +{ + NANOCLR_HEADER(); + + if(CommandLineArgs.size() == 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_NULL_REFERENCE); + } + + NANOCLR_SET_AND_LEAVE(ProcessOptions( CommandLineArgs )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT CLR_RT_ParseOptions::ProcessOptions( CLR_RT_StringVector& argv ) +{ + NANOCLR_HEADER(); + + if(CommandLineArgs.size() == 0) + { + CommandLineArgs = CLR_RT_StringVector(argv); + } + + size_t argc = argv.size(); + + for(size_t i=0; im_szName )) + { + if(m_fVerbose) + { + size_t len = cmd->m_params.size(); + size_t pos = i; + + wprintf( L"Processing" ); + + wprintf( L" %s", arg ); + while(len-- > 0 && pos < argc) wprintf( L" %s", argv[ ++pos ].c_str() ); + wprintf( L"\n" ); + } + + i++; + + if(cmd->Parse( argv, i, *this ) == false) + { + Usage(); + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + + NANOCLR_CHECK_HRESULT(cmd->Execute()); + break; + } + } + + if(it == m_commands.end()) + { + wprintf( L"Unknown option '%s'\n\n", arg ); + + Usage(); + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + } + + NANOCLR_NOCLEANUP(); +} + +void CLR_RT_ParseOptions::Usage() +{ + CommandListIter it; + ParameterListIter it2; + size_t maxCmdLen = 0; + + for(it = m_commands.begin(); it != m_commands.end(); it++) + { + Command* cmd = *it; + std::wstring option = cmd->m_szName; + size_t cmdLen = wcslen( cmd->m_szName ); + size_t maxLen = 0; + + wprintf( L" %s\n", cmd->m_szDescription ); + for(it2 = cmd->m_params.begin(); it2 != cmd->m_params.end(); it2++) + { + Parameter* param = *it2; + size_t len = wcslen( param->m_szName ); + + option += L" "; + option += param->m_szName; + + if(maxLen < len) maxLen = len; + } + + if(m_commands.size() > 1) + { + wprintf( L" %s\n", option.c_str()); + } + + for(it2 = cmd->m_params.begin(); it2 != cmd->m_params.end(); it2++) + { + Parameter* param = *it2; + + wprintf( L" %-*s = %s\n", maxLen, param->m_szName, param->m_szDescription ); + } + wprintf( L"\n" ); + } +} + +void CLR_RT_ParseOptions::PushArguments( int argc, wchar_t* argv[], CLR_RT_StringVector& vec ) +{ + for(int i=0; iDevice == NULL || BlockStorageDevice_Prev(stream->Device) == NULL) return false; + + const BlockRegionInfo* pRegion; + const DeviceBlockInfo* pDevInfo;// UNDONE: FIXME: = stream->Device->GetDeviceInfo(); + + BlockStorageStream orig; + + memcpy(&orig, stream, sizeof(orig)); + + do + { + bool fLastIndex = false; + + if (stream->RangeIndex == 0) + { + if (stream->RegionIndex == 0) + { + stream->Device = BlockStorageDevice_Prev(stream->Device); + + if (stream->Device == NULL || BlockStorageDevice_Prev(stream->Device) == NULL) + { + memcpy(stream, &orig, sizeof(orig)); + return false; + } + + // UNDONE: FIXME: pDevInfo = stream->Device->GetDeviceInfo(); + + stream->RegionIndex = pDevInfo->NumRegions - 1; + } + else + { + stream->RegionIndex--; + } + + fLastIndex = true; + } + else + { + stream->RangeIndex--; + } + + pRegion = &pDevInfo->Regions[stream->RegionIndex]; + + if (fLastIndex) + { + stream->RangeIndex = pRegion->NumBlockRanges - 1; + } + + } while (BlockRange_GetBlockUsage(pRegion->BlockRanges[stream->RangeIndex]) != stream->Usage); + + // if( pDevInfo->Attribute.SupportsXIP ) Flags |= c_BlockStorageStream__XIP; + // else Flags &= ~c_BlockStorageStream__XIP; + + stream->BlockLength = pRegion->BytesPerBlock; + stream->BaseAddress = pRegion->Start + pRegion->BlockRanges[stream->RangeIndex].StartBlock * stream->BlockLength; + stream->Length = BlockRange_GetBlockCount(pRegion->BlockRanges[stream->RangeIndex]) * stream->BlockLength; + stream->CurrentIndex = 0; + + return true; +} + +bool BlockStorageStream_PrevStream(BlockStorageStream* stream) +{ + if (stream->Device == NULL || BlockStorageDevice_Prev(stream->Device) == NULL) return false; + + const BlockRegionInfo* pRegion; + const DeviceBlockInfo* pDevInfo;// UNDONE: FIXME: = this->Device->GetDeviceInfo(); + + BlockStorageStream orig; + + memcpy(&orig, stream, sizeof(orig)); + + do + { + bool fLastIndex = false; + + if (stream->RangeIndex == 0) + { + if (stream->RegionIndex == 0) + { + stream->Device = BlockStorageDevice_Prev(stream->Device); + + if (stream->Device == NULL || BlockStorageDevice_Prev(stream->Device) == NULL) + { + memcpy(stream, &orig, sizeof(orig)); + return false; + } + + // UNDONE: FIXME: pDevInfo = this->Device->GetDeviceInfo(); + + stream->RegionIndex = pDevInfo->NumRegions - 1; + } + else + { + stream->RegionIndex--; + } + + fLastIndex = true; + } + else + { + stream->RangeIndex--; + } + + pRegion = &pDevInfo->Regions[stream->RegionIndex]; + + if (fLastIndex) + { + stream->RangeIndex = pRegion->NumBlockRanges - 1; + } + + } while (BlockRange_GetBlockUsage(pRegion->BlockRanges[stream->RangeIndex]) != stream->Usage); + + // if( pDevInfo->Attribute.SupportsXIP ) Flags |= c_BlockStorageStream__XIP; + // else Flags &= ~c_BlockStorageStream__XIP; + + stream->BlockLength = pRegion->BytesPerBlock; + stream->BaseAddress = pRegion->Start + pRegion->BlockRanges[stream->RangeIndex].StartBlock * stream->BlockLength; + stream->Length = BlockRange_GetBlockCount(pRegion->BlockRanges[stream->RangeIndex]) * stream->BlockLength; + stream->CurrentIndex = 0; + + return true; +} + +bool BlockStorageStream_Seek(BlockStorageStream *stream, unsigned int offset, SeekOrigin origin) +{ + unsigned int seekIndex; + + switch (origin) + { + case BlockStorageStream_SeekBegin: + seekIndex = 0; + break; + + case BlockStorageStream_SeekCurrent: + seekIndex = stream->CurrentIndex; + break; + + case BlockStorageStream_SeekEnd: + seekIndex = stream->Length; + break; + + default: + + return false; + } + + seekIndex += offset; + + while (seekIndex >= (int32_t)stream->Length) + { + // out of region address space + return false; + } + + while (seekIndex < 0) + { + // out of region address space + return false; + } + + stream->CurrentIndex = seekIndex; + + return true; +} + +__nfweak bool BlockStorageStream_Write(BlockStorageStream *stream, unsigned char *data, unsigned int length) +{ + return false; +} + +__nfweak bool BlockStorageStream_Erase(BlockStorageStream *stream, unsigned int length) +{ + return false; +} + +__nfweak bool BlockStorageStream_ReadIntoBuffer(BlockStorageStream *stream, unsigned char *buffer, unsigned int length) +{ + return false; +} + +bool BlockStorageStream_Read(BlockStorageStream* stream, unsigned char** buffer, unsigned int length) +{ + if (stream == NULL || !buffer) return false; + + unsigned char* pBuffer = *buffer; + bool fXIPFound = false; + + while (length > 0) + { + int readLen = length; + + if ((stream->CurrentIndex + readLen) > stream->Length) + { + readLen = stream->Length - stream->CurrentIndex; + } + + if (!fXIPFound) + { + *buffer = (unsigned char*)(BlockStorageStream_CurrentAddress(stream)); + + fXIPFound = true; + } + + length -= readLen; + pBuffer += readLen; + stream->CurrentIndex += readLen; + } + + return true; +} + +unsigned int BlockStorageStream_CurrentAddress(BlockStorageStream *stream) +{ + return stream->BaseAddress + stream->CurrentIndex; +} + +__nfweak bool BlockStorageStream_IsErased(BlockStorageStream *stream, unsigned int length) +{ + return false; +} + +///////////////////////////////////////////////////// +// BlockStorageDevice stubs + + +__nfweak BlockStorageDevice* BlockStorageDevice_Next(BlockStorageDevice* device) +{ + return NULL; +} + +__nfweak BlockStorageDevice* BlockStorageDevice_Prev(BlockStorageDevice* device) +{ + return NULL; +} + +__nfweak bool BlockStorageDevice_InitializeDevice(BlockStorageDevice* device) +{ + return false; +} + +__nfweak bool BlockStorageDevice_UninitializeDevice(BlockStorageDevice* device) +{ + return false; +} + +__nfweak DeviceBlockInfo* BlockStorageDevice_GetDeviceInfo(BlockStorageDevice* device) +{ + return NULL; +} + +__nfweak bool BlockStorageDevice_Read(BlockStorageDevice* device, unsigned int address, unsigned int numBytes, unsigned char* pSectorBuff) +{ + return false; +} + +__nfweak bool BlockStorageDevice_Write(BlockStorageDevice* device, unsigned int address, unsigned int numBytes, unsigned char* pSectorBuf, bool readModifyWrite) +{ + return false; +} + +__nfweak bool BlockStorageDevice_Memset(BlockStorageDevice* device, unsigned int address, unsigned char data, unsigned int NumBytes) +{ + return false; +} + +//__nfweak bool BlockStorageDevice_GetSectorMetadata(BlockStorageDevice* device, unsigned int sectorStart, SectorMetadata* pSectorMetadata); +//__nfweak bool BlockStorageDevice_SetSectorMetadata(BlockStorageDevice* device, unsigned int sectorStart, SectorMetadata* pSectorMetadata); + +__nfweak bool BlockStorageDevice_IsBlockErased(BlockStorageDevice* device, unsigned int blockStartAddress, unsigned int blockLength) +{ + return false; +} + +__nfweak bool BlockStorageDevice_EraseBlock(BlockStorageDevice* device, unsigned int address) +{ + return false; +} + +__nfweak void BlockStorageDevice_SetPowerState(BlockStorageDevice* device, unsigned int state) +{ + return; +} + +__nfweak bool BlockStorageDevice_FindRegionFromAddress(BlockStorageDevice* device, unsigned int address, unsigned int* blockRegionIndex, unsigned int* blockRangeIndex) +{ + return false; +} + +__nfweak bool BlockStorageDevice_FindForBlockUsage(BlockStorageDevice* device, unsigned int blockUsage, unsigned int* address, unsigned int* blockRegionIndex, unsigned int* blockRangeIndex) +{ + return false; +} + +__nfweak bool BlockStorageDevice_FindNextUsageBlock(BlockStorageDevice* device, unsigned int blockUsage, unsigned int* address, unsigned int* blockRegionIndex, unsigned int* blockRangeIndex) +{ + return false; +} + +///////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/Various.cpp b/source/native/nf-interpreter/targets/os/win32/nanoCLR/Various.cpp new file mode 100644 index 00000000..d0dca907 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/Various.cpp @@ -0,0 +1,617 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "stdafx.h" + +#include "platform_selector.h" +//--// + +//using namespace System; +//using namespace System::Diagnostics; +//using namespace Microsoft::SPOT::Emulator; + +bool HAL_Windows_IsShutdownPending() +{ + return false; //return EmulatorNative::GetEmulatorNative()->IsShuttingDown(); +} + +void HAL_Windows_AcquireGlobalLock() +{ + // UNDONE: FIXME: EmulatorNative::GetEmulatorNative()->DisableInterrupts(); +} + +void HAL_Windows_ReleaseGlobalLock() +{ + // UNDONE: FIXME: EmulatorNative::GetEmulatorNative()->EnableInterrupts(); +} + +bool HAL_Windows_HasGlobalLock() +{ + return false; // UNDONE: FIXME: !EmulatorNative::GetEmulatorNative()->AreInterruptsEnabled(); +} + +uint64_t HAL_Windows_GetPerformanceTicks() +{ + return 0; // UNDONE: FIXME: return EmulatorNative::GetEmulatorNative()->GetCurrentTicks(); +} + +void HAL_Windows_Debug_Print( char* szText ) +{ + // UNDONE: FIXME: System::Diagnostics::Debug::Print( gcnew System::String(szText) ); +} + + +//HAL_Configuration_Windows g_HAL_Configuration_Windows; + +//unsigned int LOAD_IMAGE_CalcCRC; + +//OEM_MODEL_SKU OEM_Model_SKU = { 1, 2, 3 }; + +HAL_SYSTEM_CONFIG HalSystemConfig = +{ + { true }, // HAL_DRIVER_CONFIG_HEADER Header; + + //--// + + // unsigned int DebuggerPorts[MAX_DEBUGGERS]; + DEBUGGER_PORT, + + DEBUG_TEXT_PORT, + 921600, + 0, // STDIO = COM2 or COM1 + + { 0, 0 }, // { SRAM1_MEMORY_Base, SRAM1_MEMORY_Size }, + { 0, 0 }, // { FLASH_MEMORY_Base, FLASH_MEMORY_Size }, +}; + +bool ConfigurationManager_GetConfigurationBlock(void* configurationBlock, DeviceConfigurationOption configuration, uint32_t configurationIndex) +{ + return true; +} + +bool ConfigurationManager_StoreConfigurationBlock(void* configurationBlock, DeviceConfigurationOption configuration, uint32_t configurationIndex, uint32_t blockSize) +{ + return true; +} + +int mbedtls_base64_encode(unsigned char *dst, size_t dlen, size_t *olen, + const unsigned char *src, size_t slen) +{ + return 0; +} + +int mbedtls_base64_decode(unsigned char *dst, size_t dlen, size_t *olen, + const unsigned char *src, size_t slen) +{ + return 0; +} + +//const ConfigurationSector g_ConfigurationSector = +//{ +// // ConfigurationLength +// offsetof(ConfigurationSector, FirstConfigBlock), +// +// //CONFIG_SECTOR_VERSION +// { +// ConfigurationSector::c_CurrentVersionMajor, +// ConfigurationSector::c_CurrentVersionMinor, +// ConfigurationSector::c_CurrentVersionBooter, +// 0, // extra +// }, +// +// // backwards compatibility buffer (88 bytes to put booterflagarray at offset 96) +// { +// 0x0, +// }, +// +// // BooterFlagArray - determines if we enter the bootloader or not +// { +// 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, +// 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, +// 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, +// 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, +// 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, +// }, +// +// // unsigned int SectorSignatureCheck[9*8]; // 287 sectors max * 8 changes before erase +// { +// 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, +// 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, +// 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, +// 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, +// 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, +// 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, +// 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, +// 0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF,0xFFFFFFFF, +// }, +// +// //NANOBOOTER_KEY_CONFIG DeploymentKey = +// { +// {// ODM key configuration for programming firmware (non deployment sectors) +// { // ODM public key for firware sectors +// // exponent length +// 0xFF,0xFF,0xFF, 0xFF, +// +// // module +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// +// // exponent +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// } +// }, +// {// OEM key configuration for programming Deployment sector +// { // OEM public key for Deployment sector +// // exponent length +// 0xFF,0xFF,0xFF, 0xFF, +// +// // module +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// +// // exponent +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, +// } +// } +// }, +// +// //--//--//--// +// +// // OEM_MODEL_SKU OEM_Model_SKU; +// { +// 1, // unsigned char OEM; +// 2, // unsigned char Model; +// 3, // unsigned short int SKU; +// }, +// +// //--//--//--// +// +// // OEM_SERIAL_NUMBERS OemSerialNumbers +// { +// { 0, }, +// { 0, } // unsigned char system_serial_number[16]; +// }, +// +// // CLR Config Data +// { +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, +// }, +// +// //--//--//--// +// +// // HAL_CONFIG_BLOCK FirstConfigBlock; +// { +// HAL_CONFIG_BLOCK::c_Version_V2, // unsigned int Signature; +// 0x8833794c, // unsigned int HeaderCRC; +// 0x00000000, // unsigned int DataCRC; +// 0x00000000, // unsigned int Size; +// // char DriverName[64]; +// }, +//}; + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +static ON_SOFT_REBOOT_HANDLER s_rebootHandlers[5] = {NULL, NULL, NULL, NULL, NULL}; + +void __cdecl HAL_AddSoftRebootHandler(ON_SOFT_REBOOT_HANDLER handler) +{ + for(int i=0; i 0) + { + ::QueryPerformanceFrequency( &frequency ); + + ::QueryPerformanceCounter ( &countStart ); + + double ratio = (double)TIME_CONVERSION__TO_SECONDS / (double)frequency.QuadPart; + + countEnd.QuadPart = (signed __int64)(((countStart.QuadPart * ratio) + ticks) / ratio); + + while(countStart.QuadPart < countEnd.QuadPart) + { + ::QueryPerformanceCounter( &countStart ); + } + } +} + +//////////////////////////////////////////////////////////////////////////////////////////////////// + +#pragma managed(push, off) + + +int hal_printf( const char* format, ... ) +{ + va_list arg_ptr; + + va_start(arg_ptr, format); + + int chars = hal_vprintf( format, arg_ptr ); + + va_end( arg_ptr ); + + return chars; +} + +int hal_vprintf( const char* format, va_list arg ) +{ + return vprintf( format, arg ); +} + + +int hal_fprintf( COM_HANDLE stream, const char* format, ... ) +{ + va_list arg_ptr; + int chars; + + va_start( arg_ptr, format ); + + chars = hal_vfprintf( stream, format, arg_ptr ); + + va_end( arg_ptr ); + + return chars; +} + +int hal_vfprintf( COM_HANDLE stream, const char* format, va_list arg ) +{ + char buffer[512]; + int chars = 0; + + chars = hal_vsnprintf( buffer, sizeof(buffer), format, arg ); + + //switch(ExtractTransport(stream)) + //{ + //default: + DebuggerPort_Write( stream, buffer, chars); // skip null terminator + // break; + + //case FLASH_WRITE_TRANSPORT: + // _ASSERTE(FALSE); + //} + + return chars; +} + +int hal_snprintf( char* buffer, size_t len, const char* format, ... ) +{ + va_list arg_ptr; + int chars; + + va_start( arg_ptr, format ); + + chars = hal_vsnprintf( buffer, len, format, arg_ptr ); + + va_end( arg_ptr ); + + return chars; +} + +int hal_vsnprintf( char* buffer, size_t len, const char* format, va_list arg ) +{ + return _vsnprintf_s( buffer, len, len-1/* force space for trailing zero*/, format, arg ); +} + + +// Compares 2 ASCII strings case insensitive. Does not take locale into account. +int hal_stricmp(const char * dst, const char * src) +{ + int f = 0, l = 0; + + do + { + if (((f = (unsigned char)(*(dst++))) >= 'A') && (f <= 'Z')) + { + f -= 'A' - 'a'; + } + if (((l = (unsigned char)(*(src++))) >= 'A') && (l <= 'Z')) + { + l -= 'A' - 'a'; + } + } while (f && (f == l)); + + return(f - l); +} + +#pragma managed(pop) + +///////////////////////////////////////////////////////////////////////////// +// +// CRC 32 table for use under ZModem protocol, IEEE 802 +// G(x) = x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 +// +static const unsigned int c_CRCTable[256] = +{ + 0x00000000, 0x04C11DB7, 0x09823B6E, 0x0D4326D9, 0x130476DC, 0x17C56B6B, 0x1A864DB2, 0x1E475005, + 0x2608EDB8, 0x22C9F00F, 0x2F8AD6D6, 0x2B4BCB61, 0x350C9B64, 0x31CD86D3, 0x3C8EA00A, 0x384FBDBD, + 0x4C11DB70, 0x48D0C6C7, 0x4593E01E, 0x4152FDA9, 0x5F15ADAC, 0x5BD4B01B, 0x569796C2, 0x52568B75, + 0x6A1936C8, 0x6ED82B7F, 0x639B0DA6, 0x675A1011, 0x791D4014, 0x7DDC5DA3, 0x709F7B7A, 0x745E66CD, + 0x9823B6E0, 0x9CE2AB57, 0x91A18D8E, 0x95609039, 0x8B27C03C, 0x8FE6DD8B, 0x82A5FB52, 0x8664E6E5, + 0xBE2B5B58, 0xBAEA46EF, 0xB7A96036, 0xB3687D81, 0xAD2F2D84, 0xA9EE3033, 0xA4AD16EA, 0xA06C0B5D, + 0xD4326D90, 0xD0F37027, 0xDDB056FE, 0xD9714B49, 0xC7361B4C, 0xC3F706FB, 0xCEB42022, 0xCA753D95, + 0xF23A8028, 0xF6FB9D9F, 0xFBB8BB46, 0xFF79A6F1, 0xE13EF6F4, 0xE5FFEB43, 0xE8BCCD9A, 0xEC7DD02D, + 0x34867077, 0x30476DC0, 0x3D044B19, 0x39C556AE, 0x278206AB, 0x23431B1C, 0x2E003DC5, 0x2AC12072, + 0x128E9DCF, 0x164F8078, 0x1B0CA6A1, 0x1FCDBB16, 0x018AEB13, 0x054BF6A4, 0x0808D07D, 0x0CC9CDCA, + 0x7897AB07, 0x7C56B6B0, 0x71159069, 0x75D48DDE, 0x6B93DDDB, 0x6F52C06C, 0x6211E6B5, 0x66D0FB02, + 0x5E9F46BF, 0x5A5E5B08, 0x571D7DD1, 0x53DC6066, 0x4D9B3063, 0x495A2DD4, 0x44190B0D, 0x40D816BA, + 0xACA5C697, 0xA864DB20, 0xA527FDF9, 0xA1E6E04E, 0xBFA1B04B, 0xBB60ADFC, 0xB6238B25, 0xB2E29692, + 0x8AAD2B2F, 0x8E6C3698, 0x832F1041, 0x87EE0DF6, 0x99A95DF3, 0x9D684044, 0x902B669D, 0x94EA7B2A, + 0xE0B41DE7, 0xE4750050, 0xE9362689, 0xEDF73B3E, 0xF3B06B3B, 0xF771768C, 0xFA325055, 0xFEF34DE2, + 0xC6BCF05F, 0xC27DEDE8, 0xCF3ECB31, 0xCBFFD686, 0xD5B88683, 0xD1799B34, 0xDC3ABDED, 0xD8FBA05A, + 0x690CE0EE, 0x6DCDFD59, 0x608EDB80, 0x644FC637, 0x7A089632, 0x7EC98B85, 0x738AAD5C, 0x774BB0EB, + 0x4F040D56, 0x4BC510E1, 0x46863638, 0x42472B8F, 0x5C007B8A, 0x58C1663D, 0x558240E4, 0x51435D53, + 0x251D3B9E, 0x21DC2629, 0x2C9F00F0, 0x285E1D47, 0x36194D42, 0x32D850F5, 0x3F9B762C, 0x3B5A6B9B, + 0x0315D626, 0x07D4CB91, 0x0A97ED48, 0x0E56F0FF, 0x1011A0FA, 0x14D0BD4D, 0x19939B94, 0x1D528623, + 0xF12F560E, 0xF5EE4BB9, 0xF8AD6D60, 0xFC6C70D7, 0xE22B20D2, 0xE6EA3D65, 0xEBA91BBC, 0xEF68060B, + 0xD727BBB6, 0xD3E6A601, 0xDEA580D8, 0xDA649D6F, 0xC423CD6A, 0xC0E2D0DD, 0xCDA1F604, 0xC960EBB3, + 0xBD3E8D7E, 0xB9FF90C9, 0xB4BCB610, 0xB07DABA7, 0xAE3AFBA2, 0xAAFBE615, 0xA7B8C0CC, 0xA379DD7B, + 0x9B3660C6, 0x9FF77D71, 0x92B45BA8, 0x9675461F, 0x8832161A, 0x8CF30BAD, 0x81B02D74, 0x857130C3, + 0x5D8A9099, 0x594B8D2E, 0x5408ABF7, 0x50C9B640, 0x4E8EE645, 0x4A4FFBF2, 0x470CDD2B, 0x43CDC09C, + 0x7B827D21, 0x7F436096, 0x7200464F, 0x76C15BF8, 0x68860BFD, 0x6C47164A, 0x61043093, 0x65C52D24, + 0x119B4BE9, 0x155A565E, 0x18197087, 0x1CD86D30, 0x029F3D35, 0x065E2082, 0x0B1D065B, 0x0FDC1BEC, + 0x3793A651, 0x3352BBE6, 0x3E119D3F, 0x3AD08088, 0x2497D08D, 0x2056CD3A, 0x2D15EBE3, 0x29D4F654, + 0xC5A92679, 0xC1683BCE, 0xCC2B1D17, 0xC8EA00A0, 0xD6AD50A5, 0xD26C4D12, 0xDF2F6BCB, 0xDBEE767C, + 0xE3A1CBC1, 0xE760D676, 0xEA23F0AF, 0xEEE2ED18, 0xF0A5BD1D, 0xF464A0AA, 0xF9278673, 0xFDE69BC4, + 0x89B8FD09, 0x8D79E0BE, 0x803AC667, 0x84FBDBD0, 0x9ABC8BD5, 0x9E7D9662, 0x933EB0BB, 0x97FFAD0C, + 0xAFB010B1, 0xAB710D06, 0xA6322BDF, 0xA2F33668, 0xBCB4666D, 0xB8757BDA, 0xB5365D03, 0xB1F740B4 +}; + +unsigned int SUPPORT_ComputeCRC(const void* rgBlock, int nLength, unsigned int crc) +{ + const unsigned char* ptr = (const unsigned char*)rgBlock; + + while (nLength-- > 0) + { + crc = c_CRCTable[((crc >> 24) ^ (*ptr++)) & 0xFF] ^ (crc << 8); + } + + return crc; +}; + +/////////////////////////////////////////////////////////////// + +size_t CPU_GetCachableAddress( size_t address ) +{ + return address; +} + +//--// + +size_t CPU_GetUncachableAddress( size_t address ) +{ + return address; +} + +/////////////////////////////////////////////////////////////// diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/WatchDog.cpp b/source/native/nf-interpreter/targets/os/win32/nanoCLR/WatchDog.cpp new file mode 100644 index 00000000..9303b20e --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/WatchDog.cpp @@ -0,0 +1,9 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "stdafx.h" +//--// + +// EMPTY ON PURPOSE diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native.cpp b/source/native/nf-interpreter/targets/os/win32/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native.cpp new file mode 100644 index 00000000..72405284 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native.cpp @@ -0,0 +1,87 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "stdafx.h" +#include "win_dev_gpio_native.h" + + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioController::get_PinCount___I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::Read___WindowsDevicesGpioGpioPinValue, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::Toggle___VOID, + NULL, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::DisposeNative___VOID, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeIsDriveModeSupported___BOOLEAN__WindowsDevicesGpioGpioPinDriveMode, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeSetDriveMode___VOID__WindowsDevicesGpioGpioPinDriveMode, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeInit___BOOLEAN__I4, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeSetDebounceTimeout___VOID, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::WriteNative___VOID__WindowsDevicesGpioGpioPinValue, + Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeSetAlternateFunction___VOID__I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Gpio = +{ + "Windows.Devices.Gpio", + 0xB1F30A6A, + method_lookup, + { 1, 1, 0, 0 } +}; diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native.h b/source/native/nf-interpreter/targets/os/win32/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native.h new file mode 100644 index 00000000..5b795fbb --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native.h @@ -0,0 +1,81 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#ifndef _WIN_DEV_GPIO_NATIVE_H_ +#define _WIN_DEV_GPIO_NATIVE_H_ + +#include "stdafx.h" + + +struct Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioController +{ + static const int FIELD_STATIC__s_instance = 0; + + NANOCLR_NATIVE_DECLARE(get_PinCount___I4); + + //--// + +}; + +struct Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin +{ + static const int FIELD_STATIC__s_eventListener = 1; + + static const int FIELD___syncLock = 1; + static const int FIELD___pinNumber = 2; + static const int FIELD___driveMode = 3; + static const int FIELD___debounceTimeout = 4; + static const int FIELD___callbacks = 5; + static const int FIELD___lastOutputValue = 6; + static const int FIELD___lastInputValue = 7; + static const int FIELD___disposedValue = 8; + + NANOCLR_NATIVE_DECLARE(Read___WindowsDevicesGpioGpioPinValue); + NANOCLR_NATIVE_DECLARE(Toggle___VOID); + NANOCLR_NATIVE_DECLARE(DisposeNative___VOID); + NANOCLR_NATIVE_DECLARE(NativeIsDriveModeSupported___BOOLEAN__WindowsDevicesGpioGpioPinDriveMode); + NANOCLR_NATIVE_DECLARE(NativeSetDriveMode___VOID__WindowsDevicesGpioGpioPinDriveMode); + NANOCLR_NATIVE_DECLARE(NativeInit___BOOLEAN__I4); + NANOCLR_NATIVE_DECLARE(NativeSetDebounceTimeout___VOID); + NANOCLR_NATIVE_DECLARE(WriteNative___VOID__WindowsDevicesGpioGpioPinValue); + NANOCLR_NATIVE_DECLARE(NativeSetAlternateFunction___VOID__I4); + + //--// + +}; + +struct Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPinEvent +{ + static const int FIELD__PinNumber = 3; + static const int FIELD__Edge = 4; + + + //--// + +}; + +struct Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPinEventListener +{ + static const int FIELD___pinMap = 1; + + + //--// + +}; + +struct Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPinValueChangedEventArgs +{ + static const int FIELD___edge = 1; + + + //--// + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Gpio; + +#endif //_WIN_DEV_GPIO_NATIVE_H_ diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioController.cpp b/source/native/nf-interpreter/targets/os/win32/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioController.cpp new file mode 100644 index 00000000..d97752d4 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioController.cpp @@ -0,0 +1,21 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "stdafx.h" +#include "win_dev_gpio_native.h" + + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioController::get_PinCount___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Return value to the managed application + stack.SetResult_I4( 144 ); // Fixme: temporary arbitrary value + } + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioPin.cpp b/source/native/nf-interpreter/targets/os/win32/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioPin.cpp new file mode 100644 index 00000000..bb88eeb3 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/Windows.Devices.Gpio/win_dev_gpio_native_Windows_Devices_Gpio_GpioPin.cpp @@ -0,0 +1,197 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#include "stdafx.h" +#include "win_dev_gpio_native.h" + +/////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.Gpio.GpioPinDriveMode (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////// + +enum GpioPinDriveMode +{ + GpioPinDriveMode_Input = 0, + GpioPinDriveMode_InputPullDown, + GpioPinDriveMode_InputPullUp, + GpioPinDriveMode_Output, + GpioPinDriveMode_OutputOpenDrain, + GpioPinDriveMode_OutputOpenDrainPullUp, + GpioPinDriveMode_OutputOpenSource, + GpioPinDriveMode_OutputOpenSourcePullDown, +}; + +/////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.Gpio.GpioPinValue (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////// + +enum GpioPinValue +{ + GpioPinValue_Low = 0, + GpioPinValue_High, +}; + +/////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////// + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::Read___WindowsDevicesGpioGpioPinValue( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + if(pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + signed int pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + + //stack.SetResult_I4(palReadPad(GPIO_PORT(pinNumber), pinNumber % 16)); + stack.SetResult_I4(1); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::Toggle___VOID(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + { + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::DisposeNative___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeIsDriveModeSupported___BOOLEAN__WindowsDevicesGpioGpioPinDriveMode( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + signed int driveMode = stack.Arg1().NumericByRef().s4; + + // Return value to the managed application + stack.SetResult_Boolean( driveMode < 5 ) ; + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeSetDriveMode___VOID__WindowsDevicesGpioGpioPinDriveMode( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + if(pThis[ Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue ].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + signed int pinNumber = pThis[ FIELD___pinNumber ].NumericByRefConst().s4; + signed int driveMode = stack.Arg1().NumericByRef().s4; + + // switch (driveMode) + // { + // case 0 : palSetPadMode(GPIO_PORT(pinNumber), pinNumber % 16, PAL_MODE_INPUT); + // break; + // case 1 : palSetPadMode(GPIO_PORT(pinNumber), pinNumber % 16, PAL_MODE_INPUT_PULLDOWN); + // break; + // case 2 : palSetPadMode(GPIO_PORT(pinNumber), pinNumber % 16, PAL_MODE_INPUT_PULLUP); + // break; + // case 3 : palSetPadMode(GPIO_PORT(pinNumber), pinNumber % 16, PAL_MODE_OUTPUT_PUSHPULL); + // break; + // case 4 : palSetPadMode(GPIO_PORT(pinNumber), pinNumber % 16, PAL_MODE_OUTPUT_OPENDRAIN); + // break; + // default : palSetPadMode(GPIO_PORT(pinNumber), pinNumber % 16, PAL_MODE_INPUT_PULLDOWN); + // break; + // } + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeInit___BOOLEAN__I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + signed int pinNumber = stack.Arg1().NumericByRef().s4; + + // TODO is probably a good idea keep track of the used pins, so we can check that here + // TODO is probably a good idea to check if this pin exists + + // TODO initialize the pin INT + + // Return value to the managed application + stack.SetResult_Boolean(true ); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeSetDebounceTimeout___VOID(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + + // nothing to do here + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::WriteNative___VOID__WindowsDevicesGpioGpioPinValue(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + if (pThis[Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::FIELD___disposedValue].NumericByRef().u1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + signed int pinNumber = pThis[FIELD___pinNumber].NumericByRefConst().s4; + GpioPinDriveMode driveMode = (GpioPinDriveMode)pThis[FIELD___driveMode].NumericByRefConst().s4; + + GpioPinValue state = (GpioPinValue)stack.Arg1().NumericByRef().s4; + + + // sanity check for drive mode set to output so we don't mess up writing to an input pin + if ((driveMode == GpioPinDriveMode_Output) || + (driveMode == GpioPinDriveMode_OutputOpenDrain) || + (driveMode == GpioPinDriveMode_OutputOpenDrainPullUp) || + (driveMode == GpioPinDriveMode_OutputOpenSource) || + (driveMode == GpioPinDriveMode_OutputOpenSourcePullDown)) + { + if (state == GpioPinValue_Low) + { + //palClearPad(GPIO_PORT(pinNumber), pinNumber % 16); + } + else + { + //palSetPad(GPIO_PORT(pinNumber), pinNumber % 16); + } + } + else + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_PARAMETER); + } + + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_gpio_native_Windows_Devices_Gpio_GpioPin::NativeSetAlternateFunction___VOID__I4(CLR_RT_StackFrame& stack) +{ + NANOCLR_HEADER(); + + NANOCLR_NOCLEANUP(); +} \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/Windows.Devices.Spi/win_dev_spi_native.cpp b/source/native/nf-interpreter/targets/os/win32/nanoCLR/Windows.Devices.Spi/win_dev_spi_native.cpp new file mode 100644 index 00000000..120dedcb --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/Windows.Devices.Spi/win_dev_spi_native.cpp @@ -0,0 +1,74 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#include "stdafx.h" +#include "win_dev_spi_native.h" + + +static const CLR_RT_MethodHandler method_lookup[] = +{ + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo::get_MaxClockFrequency___I4, + Library_win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo::get_MinClockFrequency___I4, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer___VOID__SZARRAY_U1__SZARRAY_U1__BOOLEAN, + Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer___VOID__SZARRAY_U2__SZARRAY_U2__BOOLEAN, + Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeInit___VOID, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::DisposeNative___VOID, + NULL, + NULL, + Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::GetDeviceSelector___STATIC__STRING, + NULL, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Spi = +{ + "Windows.Devices.Spi", + 0x083DBB79, + method_lookup, + { 1, 1, 3, 0 } +}; diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/Windows.Devices.Spi/win_dev_spi_native.h b/source/native/nf-interpreter/targets/os/win32/nanoCLR/Windows.Devices.Spi/win_dev_spi_native.h new file mode 100644 index 00000000..e86272f6 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/Windows.Devices.Spi/win_dev_spi_native.h @@ -0,0 +1,70 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#ifndef _WIN_DEV_SPI_NATIVE_H_ +#define _WIN_DEV_SPI_NATIVE_H_ + + +#include "stdafx.h" + + +struct Library_win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo +{ + static const int FIELD___ChipSelectLineCount = 1; + + NANOCLR_NATIVE_DECLARE(get_MaxClockFrequency___I4); + NANOCLR_NATIVE_DECLARE(get_MinClockFrequency___I4); + + //--// + +}; + +struct Library_win_dev_spi_native_Windows_Devices_Spi_SpiConnectionSettings +{ + static const int FIELD___csLine = 1; + static const int FIELD___clockFrequency = 2; + static const int FIELD___databitLength = 3; + static const int FIELD___spiMode = 4; + static const int FIELD___spiSharingMode = 5; + static const int FIELD___bitOrder = 6; + + + //--// + +}; + +struct Library_win_dev_spi_native_Windows_Devices_Spi_SpiController +{ + static const int FIELD_STATIC__DeviceCollection = 0; + + + //--// + +}; + +struct Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice +{ + static const int FIELD___syncLock = 1; + static const int FIELD___spiBus = 2; + static const int FIELD___deviceId = 3; + static const int FIELD___connectionSettings = 4; + static const int FIELD___disposedValue = 5; + + NANOCLR_NATIVE_DECLARE(NativeTransfer___VOID__SZARRAY_U1__SZARRAY_U1__BOOLEAN); + NANOCLR_NATIVE_DECLARE(NativeTransfer___VOID__SZARRAY_U2__SZARRAY_U2__BOOLEAN); + NANOCLR_NATIVE_DECLARE(NativeInit___VOID); + NANOCLR_NATIVE_DECLARE(DisposeNative___VOID); + NANOCLR_NATIVE_DECLARE(GetDeviceSelector___STATIC__STRING); + + //--// + + //static uint16_t ComputePrescaler (uint8_t bus, int32_t requestedFrequency); + //static nfSPIConfig GetConfig(int bus, CLR_RT_HeapBlock* config); +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_Windows_Devices_Spi; + +#endif //_WIN_DEV_SPI_NATIVE_H_ diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo.cpp b/source/native/nf-interpreter/targets/os/win32/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo.cpp new file mode 100644 index 00000000..2df23f29 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo.cpp @@ -0,0 +1,43 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "stdafx.h" +#include "win_dev_spi_native.h" + + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo::get_MaxClockFrequency___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pArg = &(stack.Arg1()); + + // spiBus is an ASCII string with the bus name in format 'SPIn' + // need to grab 'n' from the string and convert to the integer value from the ASCII code + uint8_t bus = (uint8_t)pArg[0].RecoverString()[3] - 48; + + // According to STM : "At a minimum, the clock frequency should be twice the required communication frequency." + // So maximum useable frequency is CoreClock / 2. + // SPI2 or SPI3 are on APB1, so divide max frequency by four. + stack.SetResult_I4 (987654321); + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiBusInfo::get_MinClockFrequency___I4( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_HeapBlock* pArg = &(stack.Arg1()); + + // spiBus is an ASCII string with the bus name in format 'SPIn' + // need to grab 'n' from the string and convert to the integer value from the ASCII code + uint8_t bus = (uint8_t)pArg[0].RecoverString()[3] - 48; + + // Max prescaler value = 256 + // SPI2 or SPI3 are on APB1, so divide max frequency by four. + stack.SetResult_I4 (123456789); + } + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiDevice.cpp b/source/native/nf-interpreter/targets/os/win32/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiDevice.cpp new file mode 100644 index 00000000..ed5f1205 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/Windows.Devices.Spi/win_dev_spi_native_Windows_Devices_Spi_SpiDevice.cpp @@ -0,0 +1,380 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + + +#include "stdafx.h" +#include "win_dev_spi_native.h" + +//SPIConfig spi_cfg; + +/////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.Spi.SpiMode (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////// + +enum DataBitOrder +{ + DataBitOrder_MSB = 0, + DataBitOrder_LSB +}; + +/////////////////////////////////////////////////////////////////////////////////////// +// !!! KEEP IN SYNC WITH Windows.Devices.Spi.SpiMode (in managed code) !!! // +/////////////////////////////////////////////////////////////////////////////////////// + +enum SpiModes +{ + SpiModes_Mode0 = 0, + SpiModes_Mode1, + SpiModes_Mode2, + SpiModes_Mode3 +}; + +/////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////// + +// define this type here to make it shorter and improve code readability +typedef Library_win_dev_spi_native_Windows_Devices_Spi_SpiConnectionSettings SpiConnectionSettings; + +// Computes the prescaler registers given a frequency +// uint16_t Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::ComputePrescaler (uint8_t bus, int32_t requestedFrequency) +// { +// uint16_t pre = 0; +// int32_t clock = STM32_SPII2S_MAX >> 1; // SP1, SPI4, SPI5 and SPI6 on APB2 +// if (bus == 2 || bus == 3) clock >>= 1; // SPI2 and SPI3 on APB1 + +// if (clock > requestedFrequency << 3) +// { +// clock >>= 4; +// pre |= SPI_CR1_BR_2; +// } +// if (clock > requestedFrequency << 1) +// { +// clock >>= 2; +// pre |= SPI_CR1_BR_1; +// } +// if (clock > requestedFrequency) pre |= SPI_CR1_BR_0; + +// return pre; +// } + +// Give a complete low-level SPI configuration from user's managed connectionSettings +// nfSPIConfig Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::GetConfig(int bus, CLR_RT_HeapBlock* config) +// { +// SPIDriver * _drv; + +// int csPin = config[ SpiConnectionSettings::FIELD___csLine ].NumericByRef().s4; +// uint16_t CR1 = SPI_CR1_SSI | SPI_CR1_MSTR | SPI_CR1_SPE; + +// switch (config[ SpiConnectionSettings::FIELD___spiMode ].NumericByRef().s4) +// { +// case SpiModes_Mode1 : +// CR1 |= SPI_CR1_CPHA; +// break; +// case SpiModes_Mode2 : +// CR1 |= SPI_CR1_CPOL; +// break; +// case SpiModes_Mode3 : +// CR1 |= SPI_CR1_CPHA | SPI_CR1_CPOL; +// break; +// default : // Default to Mode0 if invalid mode specified +// break; +// } + +// if (config[ SpiConnectionSettings::FIELD___databitLength ].NumericByRef().s4 == 16) +// { +// // data length is 16 bits +// CR1 |= SPI_CR1_DFF; + +// // Sets the order of bytes transmission : MSB first or LSB first +// int bitOrder = config[ SpiConnectionSettings::FIELD___bitOrder ].NumericByRef().s4; +// if (bitOrder == DataBitOrder_LSB) CR1 |= SPI_CR1_LSBFIRST; +// } + +// // SPI on STM32 needs a prescaler value to set the frequency used +// CR1 |= ComputePrescaler(bus, config[ SpiConnectionSettings::FIELD___clockFrequency ].NumericByRef().s4); + +// // Choose the driver that is mapped to the chosen bus +// switch (bus) +// { +// #if STM32_SPI_USE_SPI1 +// case 1 : _drv = &SPID1; +// break; +// #endif +// #if STM32_SPI_USE_SPI2 +// case 2 : _drv = &SPID2; +// break; +// #endif +// #if STM32_SPI_USE_SPI3 +// case 3 : _drv = &SPID3; +// break; +// #endif +// #if STM32_SPI_USE_SPI4 +// case 4 : _drv = &SPID4; +// break; +// #endif +// #if STM32_SPI_USE_SPI5 +// case 5 : _drv = &SPID5; +// break; +// #endif +// #if STM32_SPI_USE_SPI6 +// case 6 : _drv = &SPID6; +// break; +// #endif +// } + +// // Create the final configuration +// nfSPIConfig cfg = +// { +// { +// NULL, +// GPIO_PORT(csPin), +// csPin % 16, +// CR1, +// 0 +// }, +// _drv +// }; + +// return cfg; +// } + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer___VOID__SZARRAY_U1__SZARRAY_U1__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + unsigned char * writeData = NULL; + unsigned char * readData = NULL; + int writeSize = 0; + int readSize = 0; + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the managed spi connectionSettings object instance + CLR_RT_HeapBlock* pConfig = pThis[ FIELD___connectionSettings ].Dereference(); + + // get bus index + // this is coded with a multiplication, need to perform and int division to get the number + // see the comments in the SpiDevice() constructor in managed code for details + uint8_t bus = (uint8_t)(pThis[ FIELD___deviceId ].NumericByRef().s4 / 1000); + + // // Get a complete low-level SPI configuration, depending on user's managed parameters + // nfSPIConfig cfg = GetConfig(bus, pThis[ FIELD___connectionSettings ].Dereference()); + + // If databitLength is set to 16 bit, then temporarily set it to 8 bit + int databitLength = pConfig[ SpiConnectionSettings::FIELD___databitLength ].NumericByRef().s4; + //if (databitLength == 16) cfg.Configuration.cr1 &= ~SPI_CR1_DFF; + + // dereference the write and read buffers from the arguments + CLR_RT_HeapBlock_Array* writeBuffer = stack.Arg1().DereferenceArray(); + if (writeBuffer != NULL) + { + // grab the pointer to the array by getting the first element of the array + writeData = writeBuffer->GetFirstElement(); + + // get the size of the buffer by reading the number of elements in the HeapBlock array + writeSize = writeBuffer->m_numOfElements; + } + + CLR_RT_HeapBlock_Array* readBuffer = stack.Arg2().DereferenceArray(); + if (readBuffer != NULL) + { + // grab the pointer to the array by getting the first element of the array + readData = readBuffer->GetFirstElement(); + + // get the size of the buffer by reading the number of elements in the HeapBlock array + readSize = readBuffer->m_numOfElements; + } + + // // because the bus access is shared, acquire and select the appropriate bus + // spiStart(cfg.Driver, &cfg.Configuration); + // spiAcquireBus(cfg.Driver); + // spiSelect(cfg.Driver); + + // // Are we using SPI full-duplex for transfer ? + // bool fullDuplex = (bool)stack.Arg3().NumericByRef().u1; + + // if (writeSize != 0 && readSize != 0) + // { + // // Transmit+Receive + // if (fullDuplex) + // { + // // Full duplex + // spiExchange(cfg.Driver, writeSize, &writeData[0], &readData[0]); + // } + // else + // { + // spiSend(cfg.Driver, writeSize, &writeData[0]); + // spiReceive(cfg.Driver, readSize, &readData[0]); + // } + // } + // else + // { + // // Transmit only or Receive only + // if (readSize != 0) + // { + // spiReceive(cfg.Driver, readSize, &readData[0]); + // } + // else + // { + // spiSend(cfg.Driver, writeSize, &writeData[0]); + // } + // } + + // // Release the bus + // spiUnselect(cfg.Driver); + // spiReleaseBus(cfg.Driver); + // spiStop(cfg.Driver); + + // // If databitLength was set to 16 bit above, then set it back to 16 bit + // if (databitLength == 16) cfg.Configuration.cr1 |= SPI_CR1_DFF; + + // null pointers and vars + writeData = NULL; + readData = NULL; + writeBuffer = NULL; + readBuffer = NULL; + pThis = NULL; + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeTransfer___VOID__SZARRAY_U2__SZARRAY_U2__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + CLR_RT_TypedArray writeData; + CLR_RT_TypedArray readData; + + // marshal the write and read buffers + Interop_Marshal_UINT16_ARRAY(stack, 1, writeData); + Interop_Marshal_UINT16_ARRAY(stack, 2, readData); + int writeSize = writeData.GetSize(); + int readSize = readData.GetSize(); + + // get a pointer to the managed object instance and check that it's not NULL + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // get a pointer to the managed spi connectionSettings object instance + CLR_RT_HeapBlock* pConfig = pThis[ FIELD___connectionSettings ].Dereference(); + + // get bus index + // this is coded with a multiplication, need to perform and int division to get the number + // see the comments in the SpiDevice() constructor in managed code for details + uint8_t bus = (uint8_t)(pThis[ FIELD___deviceId ].NumericByRef().s4 / 1000); + + // // Gets a complete low-level SPI configuration, depending on user's managed parameters + // nfSPIConfig cfg = GetConfig(bus, pConfig); + + // If current config databitLength is 8bit, then set it temporarily to 16bit + int databitLength = pConfig[ SpiConnectionSettings::FIELD___databitLength ].NumericByRef().s4; + //if (databitLength == 8) cfg.Configuration.cr1 |= SPI_CR1_DFF; + + // // because the bus access is shared, acquire and select the appropriate bus + // spiStart(cfg.Driver, &cfg.Configuration); + // spiAcquireBus(cfg.Driver); + // spiSelect(cfg.Driver); + + // // Are we using SPI full-duplex for transfer ? + // bool fullDuplex = (bool)stack.Arg3().NumericByRef().u1; + + // if (writeSize != 0 && readSize != 0) + // { + // // Transmit+Receive + // if (fullDuplex) + // { + // // Full duplex + // spiExchange(cfg.Driver, writeSize, &writeData[0], &readData[0]); + // } + // else + // { + // spiSend(cfg.Driver, writeSize, &writeData[0]); + // spiReceive(cfg.Driver, readSize, &readData[0]); + // } + // } + // else + // { + // // Transmit only or Receive only + // if (readSize != 0) + // { + // spiReceive(cfg.Driver, readSize, &readData[0]); + // } + // else + // { + // spiSend(cfg.Driver, writeSize, (const void*)&buffer[0]); + // } + // } + + // // Release the bus + // spiUnselect(cfg.Driver); + // spiReleaseBus(cfg.Driver); + // spiStop(cfg.Driver); + + // // If current config databitLength was 8bit, then set it back to 8bit + // if (databitLength == 8) cfg.Configuration.cr1 &= ~SPI_CR1_DFF; + + // null pointers and vars + pThis = NULL; + pConfig = NULL; + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::NativeInit___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + // nothing to do in the native init + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::DisposeNative___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // set pin to input to save power + // clear interrupts + // release the pin + } + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_win_dev_spi_native_Windows_Devices_Spi_SpiDevice::GetDeviceSelector___STATIC__STRING( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + { + // declare the device selector string whose max size is "SPI1,SPI2,SPI3,SPI4,SPI5,SPI6," + terminator and init with the terminator + char deviceSelectorString[ 30 + 1] = { 0 }; + + #if STM32_SPI_USE_SPI1 + strcat(deviceSelectorString, "SPI1,"); + #endif + #if STM32_SPI_USE_SPI2 + strcat(deviceSelectorString, "SPI2,"); + #endif + #if STM32_SPI_USE_SPI3 + strcat(deviceSelectorString, "SPI3,"); + #endif + #if STM32_SPI_USE_SPI4 + strcat(deviceSelectorString, "SPI4,"); + #endif + #if STM32_SPI_USE_SPI5 + strcat(deviceSelectorString, "SPI5,"); + #endif + #if STM32_SPI_USE_SPI6 + strcat(deviceSelectorString, "SPI6,"); + #endif + + // replace the last comma with a terminator + deviceSelectorString[hal_strlen_s(deviceSelectorString) - 1] = '\0'; + + // because the caller is expecting a result to be returned + // we need set a return result in the stack argument using the appropriate SetResult according to the variable type (a string here) + stack.SetResult_String(deviceSelectorString); + } + NANOCLR_NOCLEANUP(); +} + diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/main.cpp b/source/native/nf-interpreter/targets/os/win32/nanoCLR/main.cpp new file mode 100644 index 00000000..87cada1a --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/main.cpp @@ -0,0 +1,100 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// +#include "stdafx.h" + +#include + + +// +// UNDONE: Feature configuration +// + +#define NF_CLR_FEATURE_ALL + +#if defined(NF_CLR_FEATURE_ALL) + +#pragma comment(lib, "WireProtocol.lib") + +#pragma comment(lib, "Debugger.lib") +#pragma comment(lib, "Diagnostics.lib") +#pragma comment(lib, "Hardware.lib") +#pragma comment(lib, "InterruptHandler.lib") +#pragma comment(lib, "Messaging.lib") +#pragma comment(lib, "RPC.lib") +#pragma comment(lib, "Serialization.lib") + +#else + +#pragma comment(lib, "WireProtocol.lib") // UNDONE: FIXME: SUPPORT_ComputeCRC required by TypeSystem.cpp, CLR_RT_HeapBlock + +#pragma comment(lib, "Debugger_stub.lib") +#pragma comment(lib, "Diagnostics_stub.lib") +#pragma comment(lib, "Hardware_stub.lib") +#pragma comment(lib, "InterruptHandler_stub.lib") +#pragma comment(lib, "IOPort_stub.lib") +#pragma comment(lib, "Messaging_stub.lib") +#pragma comment(lib, "RPC_stub.lib") +#pragma comment(lib, "Serialization_stub.lib") + + +#endif + + + + + + + +///////////////////////////////////////////////////////////////////////////// + + +// All solutions are expected to provide an implementation of this +bool Target_GetReleaseInfo(NFReleaseInfo& releaseInfo) +{ + NFReleaseInfo::Init( + releaseInfo, + VERSION_MAJOR, + VERSION_MINOR, + VERSION_BUILD, + VERSION_REVISION, + OEMSYSTEMINFOSTRING, + hal_strlen_s(OEMSYSTEMINFOSTRING), + TARGETNAMESTRING, + hal_strlen_s(TARGETNAMESTRING), + PLATFORMNAMESTRING, + hal_strlen_s(PLATFORMNAMESTRING) + ); + + return true; // alternatively, return false if you didn't initialize the releaseInfo structure. +} + +///////////////////////////////////////////////////////////////////////////// +// + +int main() +{ + //void ApplicationEntryPoint() + + // initialize nanoHAL + nanoHAL_Initialize(); + + CLR_SETTINGS clrSettings; + ZeroMemory(&clrSettings, sizeof(clrSettings)); + + clrSettings.MaxContextSwitches = 50; + clrSettings.WaitForDebugger = false; + clrSettings.EnterDebuggerLoopAfterExit = true; + + ClrStartup(clrSettings); + +//#if !defined(BUILD_RTM) +// debug_printf( "Exiting.\r\n" ); +//#else + //::CPU_Reset(); +//#endif + + return 0; +} + diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/nanoCLR.vcxproj b/source/native/nf-interpreter/targets/os/win32/nanoCLR/nanoCLR.vcxproj new file mode 100644 index 00000000..033615f6 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/nanoCLR.vcxproj @@ -0,0 +1,280 @@ + + + + + Debug + Win32 + + + Release + Win32 + + + Debug + x64 + + + Release + x64 + + + + {B5515C8A-B056-4320-8EA4-8CACE21A7D2E} + Win32Proj + nanoCLR + 10.0.17763.0 + + + + Application + true + v141 + Unicode + + + Application + false + v141 + true + Unicode + + + Application + true + v141 + Unicode + + + Application + false + v141 + true + Unicode + + + + + + + + + + + + + + + + + + + + + + + + + true + $(BinDir) + $(IntDir) + + + true + $(BinDir) + $(IntDir) + + + false + $(BinDir) + $(IntDir) + + + false + $(BinDir) + $(IntDir) + + + + Use + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;VERSION_MAJOR=0;VERSION_MINOR=0;VERSION_BUILD=0;VERSION_REVISION=0;OEMSYSTEMINFOSTRING="WIN_32 PLAYGROUND APP";TARGETNAMESTRING="CLR_WIN32";PLATFORMNAMESTRING="WIN32";%(PreprocessorDefinitions) + ..\..\..\..\src\CLR\Helpers\Base64;.;..\Include;..\..\..\..\src\CLR\Include;..\..\..\..\src\HAL\Include;..\..\..\..\src\PAL\Include;nanoFramework.Runtime.Events + + + Console + $(BinDir) + + + + + Use + Level3 + Disabled + _DEBUG;_CONSOLE;%(PreprocessorDefinitions) + + + Console + $(BinDir) + + + + + Level3 + Use + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;VERSION_MAJOR=0;VERSION_MINOR=0;VERSION_BUILD=0;VERSION_REVISION=0;OEMSYSTEMINFOSTRING="WIN_32 PLAYGROUND APP";TARGETNAMESTRING="CLR_WIN32";PLATFORMNAMESTRING="WIN32";%(PreprocessorDefinitions) + ..\..\..\..\src\CLR\Helpers\Base64;.;..\Include;..\..\..\..\src\CLR\Include;..\..\..\..\src\HAL\Include;..\..\..\..\src\PAL\Include;nanoFramework.Runtime.Events + + + Console + true + true + $(BinDir) + + + + + Level3 + Use + MaxSpeed + true + true + NDEBUG;_CONSOLE;%(PreprocessorDefinitions) + + + Console + true + true + $(BinDir) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Create + Create + Create + Create + + + + + + Use + + + + + + + + + + + + {89cf8bdb-9c8a-4d18-bc3e-4312c5bd34b1} + + + {5d50772e-dac8-407d-972f-37deb4450b72} + + + {d32ee397-7e49-452d-ac95-afcb3c962e3d} + + + {5772d362-7277-49cf-9b49-42335a3154bd} + false + false + false + + + {5406eb0c-2243-47e1-9f21-f2d7ca277092} + false + false + false + + + {ed4c887a-ec09-465b-b5d9-075450adc52d} + + + {d0b2adfe-3347-4d73-9364-9c36935d12f8} + false + false + false + + + {16bf6131-a3b8-4b97-b867-e45669fb48bd} + + + {c337041d-344d-49fe-ad99-b137e7fd0188} + false + false + false + + + {58e950cc-2ff6-423c-b006-a70a19272f20} + + + {dd397ec4-844b-4b59-a67b-cad6b46f1f00} + + + {6dabcbf1-245a-4e76-bd36-8bc300c7dd82} + false + false + false + + + {a5e9ae41-f4fa-40ce-ad82-a7861eba007b} + + + {c97a9845-02dc-46e4-b219-bf5ea8fb28e3} + false + false + false + + + {131001e3-0201-451f-a87b-951d1c5c3eee} + + + {8acd05e8-42fb-4a49-9d8b-79239f0eed25} + false + false + false + + + {2a840dc3-ffa8-4562-bd13-ab2b0ba02cb6} + + + {2337c4a4-3ab4-4014-9c29-9ebe32f4510e} + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/nanoCLR.vcxproj.filters b/source/native/nf-interpreter/targets/os/win32/nanoCLR/nanoCLR.vcxproj.filters new file mode 100644 index 00000000..5e298b89 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/nanoCLR.vcxproj.filters @@ -0,0 +1,141 @@ + + + + + {4FC737F1-C7A5-4376-A066-2A32D752A2FF} + cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx + + + {93995380-89BD-4b04-88EB-625FBE52EBFB} + h;hh;hpp;hxx;hm;inl;inc;xsd + + + {67DA6AB6-F800-4c08-8B7A-83BB121AAD01} + rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms + + + {4a8f1020-5d97-4a6f-b9c1-1460ae41f71b} + + + {917f0887-d239-439f-b246-e18c1f726304} + + + {7d83b23d-05f7-4660-9f84-a6fcdb0a0cf3} + + + {27c2cf5b-4789-40b1-b760-fc55c60546f0} + + + {a6b77d6f-6169-46dc-9bd2-dac8fdef5518} + + + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + Header Files + + + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files + + + Source Files\Generated + + + Source Files + + + Source Files\PAL + + + Source Files\PAL + + + Source Files\PAL + + + Source Files\PAL + + + Source Files\PAL + + + Source Files\PAL + + + Source Files + + + Source Files\PAL + + + Source Files + + + Source Files\Windows.Devices.Gpio + + + Source Files\Windows.Devices.Gpio + + + Source Files\Windows.Devices.Gpio + + + Source Files\nanoFramework.Runtime.Events + + + Source Files\nanoFramework.Runtime.Events + + + Source Files\nanoFramework.Runtime.Events + + + Source Files\nanoFramework.Runtime.Events + + + Source Files\PAL + + + Source Files\Windows.Devices.Spi + + + Source Files\Windows.Devices.Spi + + + Source Files\Windows.Devices.Spi + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/nanoFramework.Runtime.Events/nf_rt_events_native.cpp b/source/native/nf-interpreter/targets/os/win32/nanoCLR/nanoFramework.Runtime.Events/nf_rt_events_native.cpp new file mode 100644 index 00000000..f43fd3ef --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/nanoFramework.Runtime.Events/nf_rt_events_native.cpp @@ -0,0 +1,59 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "stdafx.h" +#include "nf_rt_events_native.h" + + +static const CLR_RT_MethodHandler method_lookup[] = +{ + Library_nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher::EnableInterrupt___VOID, + Library_nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher::DisableInterrupt___VOID, + Library_nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher::Dispose___VOID__BOOLEAN, + NULL, + NULL, + Library_nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher::_ctor___VOID__STRING__U8, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_nf_rt_events_native_nanoFramework_Runtime_Events_EventSink::EventConfig___VOID, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + NULL, + Library_nf_rt_events_native_nanoFramework_Runtime_Events_WeakDelegate::Combine___STATIC__mscorlibSystemDelegate__mscorlibSystemDelegate__mscorlibSystemDelegate, + Library_nf_rt_events_native_nanoFramework_Runtime_Events_WeakDelegate::Remove___STATIC__mscorlibSystemDelegate__mscorlibSystemDelegate__mscorlibSystemDelegate, +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Runtime_Events = +{ + "nanoFramework.Runtime.Events", + 0xBFF88292, + method_lookup, + { 1, 0, 5, 0 } +}; diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/nanoFramework.Runtime.Events/nf_rt_events_native.h b/source/native/nf-interpreter/targets/os/win32/nanoCLR/nanoFramework.Runtime.Events/nf_rt_events_native.h new file mode 100644 index 00000000..17961374 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/nanoFramework.Runtime.Events/nf_rt_events_native.h @@ -0,0 +1,99 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + + +#ifndef _NF_RT_EVENTS_NATIVE_H_ +#define _NF_RT_EVENTS_NATIVE_H_ + + +#include "stdafx.h" + + +struct Library_nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher +{ + static const int FIELD__threadSpawn = 1; + static const int FIELD__callbacks = 2; + static const int FIELD__disposed = 3; + static const int FIELD___NativeEventDispatcher = 4; + + NANOCLR_NATIVE_DECLARE(EnableInterrupt___VOID); + NANOCLR_NATIVE_DECLARE(DisableInterrupt___VOID); + NANOCLR_NATIVE_DECLARE(Dispose___VOID__BOOLEAN); + NANOCLR_NATIVE_DECLARE(_ctor___VOID__STRING__U8); + + //--// + static CLR_RT_ObjectToEvent_Source* GetEventDispReference( CLR_RT_StackFrame& stack ); + static HRESULT GetEventDispatcher ( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock_NativeEventDispatcher*& event ); + static CLR_RT_HeapBlock_NativeEventDispatcher* GetEventDispatcher ( CLR_RT_StackFrame& stack ); +}; + +struct Library_nf_rt_events_native_nanoFramework_Runtime_Events_EventSink +{ + static const int FIELD_STATIC__s_eventSink = 0; + static const int FIELD_STATIC__s_eventInfoTable = 1; + + NANOCLR_NATIVE_DECLARE(EventConfig___VOID); + + //--// + +}; + +struct Library_nf_rt_events_native_nanoFramework_Runtime_Events_EventSink__EventInfo +{ + static const int FIELD__EventListener = 1; + static const int FIELD__EventFilter = 2; + static const int FIELD__EventProcessor = 3; + static const int FIELD__Category = 4; + + + //--// + +}; + +struct Library_nf_rt_events_native_nanoFramework_Runtime_Events_BaseEvent +{ + static const int FIELD__Source = 1; + static const int FIELD__Message = 2; + + + //--// + +}; + +struct Library_nf_rt_events_native_nanoFramework_Runtime_Events_EventArgs +{ + static const int FIELD_STATIC__Empty = 2; + + + //--// + +}; + +struct Library_nf_rt_events_native_nanoFramework_Runtime_Events_GenericEvent +{ + static const int FIELD__Category = 3; + static const int FIELD__Data = 4; + static const int FIELD__Time = 5; + + + //--// + +}; + +struct Library_nf_rt_events_native_nanoFramework_Runtime_Events_WeakDelegate +{ + NANOCLR_NATIVE_DECLARE(Combine___STATIC__mscorlibSystemDelegate__mscorlibSystemDelegate__mscorlibSystemDelegate); + NANOCLR_NATIVE_DECLARE(Remove___STATIC__mscorlibSystemDelegate__mscorlibSystemDelegate__mscorlibSystemDelegate); + + //--// + +}; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Runtime_Events_EventSink_DriverProcs; + +extern const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Runtime_Events; + +#endif //_NF_RT_EVENTS_NATIVE_H_ diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/nanoFramework.Runtime.Events/nf_rt_events_native_nanoFramework_Runtime_Events_EventSink.cpp b/source/native/nf-interpreter/targets/os/win32/nanoCLR/nanoFramework.Runtime.Events/nf_rt_events_native_nanoFramework_Runtime_Events_EventSink.cpp new file mode 100644 index 00000000..f5e33661 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/nanoFramework.Runtime.Events/nf_rt_events_native_nanoFramework_Runtime_Events_EventSink.cpp @@ -0,0 +1,61 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "stdafx.h" +#include "nf_rt_events_native.h" + +static CLR_RT_HeapBlock_NativeEventDispatcher *g_Context = NULL; + +void PostManagedEvent(uint8_t category, uint8_t subCategory, uint16_t data1, uint32_t data2) +{ + if(g_Context != NULL) + { + uint16_t d = ((uint16_t)data1 << 16) | (category << 8) | subCategory; + + SaveNativeEventToHALQueue( g_Context, d, data2 ); + } +} + +static HRESULT InitializeEventSink( CLR_RT_HeapBlock_NativeEventDispatcher *pContext, uint64_t userData ) +{ + g_Context = pContext; + + return S_OK; +} + +static HRESULT EnableDisableEventSink( CLR_RT_HeapBlock_NativeEventDispatcher *pContext, bool fEnable ) +{ + return S_OK; +} + +static HRESULT CleanupEventSink( CLR_RT_HeapBlock_NativeEventDispatcher *pContext ) +{ + g_Context = NULL; + + CleanupNativeEventsFromHALQueue( pContext ); + + return S_OK; +} + +HRESULT Library_nf_rt_events_native_nanoFramework_Runtime_Events_EventSink::EventConfig___VOID( CLR_RT_StackFrame& stack ) +{ + return S_OK; +} + +static const CLR_RT_DriverInterruptMethods g_CLR_AssemblyNative_nanoFramework_Runtime_Events_EventSink = +{ + InitializeEventSink, + EnableDisableEventSink, + CleanupEventSink +}; + +const CLR_RT_NativeAssemblyData g_CLR_AssemblyNative_nanoFramework_Runtime_Events_EventSink_DriverProcs = +{ + "EventSink", + DRIVER_INTERRUPT_METHODS_CHECKSUM, + &g_CLR_AssemblyNative_nanoFramework_Runtime_Events_EventSink, + { 1, 0, 0, 0 } +}; diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/nanoFramework.Runtime.Events/nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher.cpp b/source/native/nf-interpreter/targets/os/win32/nanoCLR/nanoFramework.Runtime.Events/nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher.cpp new file mode 100644 index 00000000..2948ced2 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/nanoFramework.Runtime.Events/nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher.cpp @@ -0,0 +1,176 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "stdafx.h" +#include "nf_rt_events_native.h" + + +HRESULT Library_nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher::EnableInterrupt___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_NativeEventDispatcher *pNativeDisp = NULL; + + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + if(pThis[ FIELD__disposed ].NumericByRef().s1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + NANOCLR_CHECK_HRESULT(GetEventDispatcher( stack, pNativeDisp )); + + // Calls driver to enable interrupts. Consider that there could be no driver + // associated to this object so check that the driver methods are set + if(pNativeDisp->driverMethods == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_INVALID_OPERATION); + } + + NANOCLR_CHECK_HRESULT(pNativeDisp->driverMethods->enableProcessor( pNativeDisp, true )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher::DisableInterrupt___VOID( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_NativeEventDispatcher *pNativeDisp = NULL; + + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + if(pThis[ FIELD__disposed ].NumericByRef().s1 != 0) + { + NANOCLR_SET_AND_LEAVE(CLR_E_OBJECT_DISPOSED); + } + + NANOCLR_CHECK_HRESULT(GetEventDispatcher( stack, pNativeDisp )); + + // Calls driver to enable interrupts. Consider that there could be no driver + // associated to this object so check that the driver methods are set + // we will be tolerant in this case and not throw any exception + if(pNativeDisp->driverMethods != NULL) + { + NANOCLR_CHECK_HRESULT(pNativeDisp->driverMethods->enableProcessor( pNativeDisp, false )); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher::Dispose___VOID__BOOLEAN( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_HeapBlock_NativeEventDispatcher *pNativeDisp = NULL; + + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + NANOCLR_CHECK_HRESULT(GetEventDispatcher( stack, pNativeDisp )); + + // Cleanup the HAL queue from the instance of associated CLR_RT_HeapBlock_NativeEventDispatcher + pNativeDisp->RemoveFromHALQueue(); + + // Calls driver to enable interrupts. Consider that there could be no driver + // associated to this object so check that the driver methods are set + // we will be tolerant in this case and not throw any exception + if(pNativeDisp->driverMethods != NULL) + { + NANOCLR_CHECK_HRESULT(pNativeDisp->driverMethods->cleanupProcessor( pNativeDisp )); + } + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher::_ctor___VOID__STRING__U8( CLR_RT_StackFrame& stack ) +{ + NANOCLR_HEADER(); + + CLR_RT_DriverInterruptMethods* pDriverMethods; + const CLR_RT_NativeAssemblyData* pNativeDriverData; + CLR_RT_HeapBlock_NativeEventDispatcher* pNativeDisp = NULL; + + const char * driverName; + uint64_t driverData; + + CLR_RT_HeapBlock* pThis = stack.This(); FAULT_ON_NULL(pThis); + + // Retrieve paramenters; + if (stack.Arg1().DataType() != DATATYPE_OBJECT) + { NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + driverName = stack.Arg1().RecoverString(); FAULT_ON_NULL(driverName); + + driverData = stack.Arg2().NumericByRef().u8; + + // Throw NULL exception if string is empty. + if(hal_strlen_s( driverName ) == 0) + { + NANOCLR_CHECK_HRESULT(CLR_E_ARGUMENT_NULL); + } + + // Retrives pointers to driver implemented functions. + pNativeDriverData = GetAssemblyNativeData( driverName ); + + // Validates check sum and presence of the structure. + if(pNativeDriverData == NULL || pNativeDriverData->m_checkSum != DRIVER_INTERRUPT_METHODS_CHECKSUM) + { + NANOCLR_CHECK_HRESULT(CLR_E_DRIVER_NOT_REGISTERED); + } + + // Get pointer to CLR_RT_DriverInterruptMethods + pDriverMethods = (CLR_RT_DriverInterruptMethods *)pNativeDriverData->m_pNativeMethods; + + // Check that all methods are present: + if(pDriverMethods->initProcessor == NULL || pDriverMethods->enableProcessor == NULL || pDriverMethods->cleanupProcessor == NULL) + { + NANOCLR_CHECK_HRESULT(CLR_E_DRIVER_NOT_REGISTERED); + } + + // So we found driver by name and now we create instance of CLR_RT_HeapBlock_NativeEventDispatcher + NANOCLR_CHECK_HRESULT(CLR_RT_HeapBlock_NativeEventDispatcher::CreateInstance( *pThis, pThis[ FIELD___NativeEventDispatcher ] )); + + // Initialize the driver with and provide the instance of CLR_RT_HeapBlock_NativeEventDispatcher + NANOCLR_CHECK_HRESULT(GetEventDispatcher( stack, pNativeDisp )); + + // Now call the driver. First save pointer to driver data. + pNativeDisp->driverMethods = pDriverMethods; + NANOCLR_CHECK_HRESULT(pDriverMethods->initProcessor( pNativeDisp, driverData )); + + NANOCLR_NOCLEANUP(); +} + +//--// + +CLR_RT_ObjectToEvent_Source* Library_nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher::GetEventDispReference( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_HARDWARE(); + CLR_RT_HeapBlock* pThis = stack.This(); + + return CLR_RT_ObjectToEvent_Source::ExtractInstance( pThis[ FIELD___NativeEventDispatcher ] ); +} + +HRESULT Library_nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher::GetEventDispatcher( CLR_RT_StackFrame& stack, CLR_RT_HeapBlock_NativeEventDispatcher*& event ) +{ + NATIVE_PROFILE_CLR_HARDWARE(); + NANOCLR_HEADER(); + + event = GetEventDispatcher( stack ); + if(event == NULL) + { + NANOCLR_SET_AND_LEAVE(CLR_E_WRONG_TYPE); + } + + NANOCLR_NOCLEANUP(); +} + +CLR_RT_HeapBlock_NativeEventDispatcher* Library_nf_rt_events_native_nanoFramework_Runtime_Events_NativeEventDispatcher::GetEventDispatcher( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_HARDWARE(); + CLR_RT_ObjectToEvent_Source* src = GetEventDispReference( stack ); + + return (src == NULL) ? NULL : (CLR_RT_HeapBlock_NativeEventDispatcher*)src->m_eventPtr; +} diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/nanoFramework.Runtime.Events/nf_rt_events_native_nanoFramework_Runtime_Events_WeakDelegate.cpp b/source/native/nf-interpreter/targets/os/win32/nanoCLR/nanoFramework.Runtime.Events/nf_rt_events_native_nanoFramework_Runtime_Events_WeakDelegate.cpp new file mode 100644 index 00000000..0ec99f71 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/nanoFramework.Runtime.Events/nf_rt_events_native_nanoFramework_Runtime_Events_WeakDelegate.cpp @@ -0,0 +1,29 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// + +#include "stdafx.h" +#include "nf_rt_events_native.h" + + +HRESULT Library_nf_rt_events_native_nanoFramework_Runtime_Events_WeakDelegate::Combine___STATIC__mscorlibSystemDelegate__mscorlibSystemDelegate__mscorlibSystemDelegate( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(CLR_RT_HeapBlock_Delegate_List::Combine( stack.PushValue(), stack.Arg0(), stack.Arg1(), true )); + + NANOCLR_NOCLEANUP(); +} + +HRESULT Library_nf_rt_events_native_nanoFramework_Runtime_Events_WeakDelegate::Remove___STATIC__mscorlibSystemDelegate__mscorlibSystemDelegate__mscorlibSystemDelegate( CLR_RT_StackFrame& stack ) +{ + NATIVE_PROFILE_CLR_CORE(); + NANOCLR_HEADER(); + + NANOCLR_SET_AND_LEAVE(CLR_RT_HeapBlock_Delegate_List::Remove( stack.PushValue(), stack.Arg0(), stack.Arg1() )); + + NANOCLR_NOCLEANUP(); +} diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/platform_heap.cpp b/source/native/nf-interpreter/targets/os/win32/nanoCLR/platform_heap.cpp new file mode 100644 index 00000000..42706d94 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/platform_heap.cpp @@ -0,0 +1,18 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// + +#include "stdafx.h" + +void* platform_malloc(size_t size) { + return malloc(size); +} + +void platform_free(void* ptr) { + free(ptr); +} + +void* platform_realloc(void* ptr, size_t size) { + return ptr; +} diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/platform_selector.h b/source/native/nf-interpreter/targets/os/win32/nanoCLR/platform_selector.h new file mode 100644 index 00000000..97cfc5a2 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/platform_selector.h @@ -0,0 +1,68 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#ifndef _PLATFORM_WINDOWS_SELECTOR_H_ +#define _PLATFORM_WINDOWS_SELECTOR_H_ 1 + +#define PLATFORM_WINDOWS_EMULATOR 1 + +///////////////////////////////////////////////////////// +// +// macros +// + +#define FAT_FS__VALIDATE_READONLY_CACHELINE 1 +//#define FAT_FS__DO_NOT_UPDATE_FILE_ACCESS_TIME 1 +#define FAT_FS__CACHE_FLUSH_TIMEOUT_USEC (5*1000*1000) + +// +// macros +// +///////////////////////////////////////////////////////// + +///////////////////////////////////////////////////////// +// +// constants +// +#define PRODUCT_WATCH 1 +#define PRODUCT_AUXDISPLAY 1 + +// Port definitions +#define TOTAL_USART_PORT 2 +#define COM1 ConvertCOM_ComHandle(0) +#define COM2 ConvertCOM_ComHandle(1) + +#define TOTAL_USB_CONTROLLER 1 +#define USB1 ConvertCOM_UsbHandle(0) + +#define TOTAL_DEBUG_PORT 1 +#define COM_DEBUG ConvertCOM_DebugHandle(0) + +#define TOTAL_MESSAGING_PORT 1 +#define COM_MESSAGING ConvertCOM_MessagingHandle(0) + +#define DEBUG_TEXT_PORT COM_DEBUG +#define DEBUGGER_PORT COM_DEBUG +#define MESSAGING_PORT COM_DEBUG + +#define PLATFORM_DEPENDENT_TX_USART_BUFFER_SIZE 512 // there is one TX for each usart port +#define PLATFORM_DEPENDENT_RX_USART_BUFFER_SIZE 512 // there is one RX for each usart port +#define PLATFORM_DEPENDENT_USB_QUEUE_PACKET_COUNT 2 // there is one queue for each pipe of each endpoint and the size of a single packet is sizeof(USB_PACKET64) == 68 bytes + + +// These are configuration for FATFS, uncomment if non-default values are needed +//#define PLATFORM_DEPENDENT_FATFS_SECTORCACHE_MAXSIZE 8 +//#define PLATFORM_DEPENDENT_FATFS_SECTORCACHE_LINESIZE 2048 +//#define PLATFORM_DEPENDENT_FATFS_MAX_OPEN_HANDLES 8 +#define PLATFORM_DEPENDENT_FATFS_MAX_VOLUMES 8 +// +// constants +// +///////////////////////////////////////////////////////// + +//#include + +#endif // _PLATFORM_WINDOWS_SELECTOR_H_ 1 + diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/stdafx.cpp b/source/native/nf-interpreter/targets/os/win32/nanoCLR/stdafx.cpp new file mode 100644 index 00000000..968af34d --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/stdafx.cpp @@ -0,0 +1,13 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// +// stdafx.cpp : source file that includes just the standard includes +// test.pch will be the pre-compiled header +// stdafx.obj will contain the pre-compiled type information + +#include "stdafx.h" + +// TODO: reference any additional headers you need in STDAFX.H +// and not in this file + diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/stdafx.h b/source/native/nf-interpreter/targets/os/win32/nanoCLR/stdafx.h new file mode 100644 index 00000000..9678d3eb --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/stdafx.h @@ -0,0 +1,28 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// +// stdafx.h : include file for standard system include files, +// or project specific include files that are used frequently, but +// are changed infrequently +// + +#pragma once + +#include "targetver.h" + +#include +#include + +//#include + +// TODO: reference additional headers your program requires here + +#include +#include +#include +#include +#include + +#include "nanoCLR_ParseOptions.h" + diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/targetHAL_Time.cpp b/source/native/nf-interpreter/targets/os/win32/nanoCLR/targetHAL_Time.cpp new file mode 100644 index 00000000..8ca94f92 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/targetHAL_Time.cpp @@ -0,0 +1,155 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// Portions Copyright (c) Microsoft Corporation. All rights reserved. +// See LICENSE file in the project root for full license information. +// +#include "stdafx.h" + + +//using namespace Microsoft::SPOT::Emulator; + +void HAL_Time_Sleep_MicroSeconds( unsigned int uSec ) +{ + // UNDONE: FIXME: return EmulatorNative::GetITimeDriver()->Sleep_MicroSeconds( uSec ); +} + +void HAL_Time_Sleep_MicroSeconds_InterruptEnabled( unsigned int uSec ) +{ + // UNDONE: FIXME: return EmulatorNative::GetITimeDriver()->Sleep_MicroSecondsInterruptsEnabled( uSec ); +} + +unsigned int HAL_Time_CurrentSysTicks() +{ + // TODO need to check if using the Win32 100ns ticks works + return 0; // UNDONE: FIXME: EmulatorNative::GetITimeDriver()->CurrentTicks(); +} + +uint64_t HAL_Time_SysTicksToTime( unsigned int sysTicks ) +{ + _ASSERTE(sysTicks <= 0x7FFFFFFF); + + //No need to go to managed code just to return Time. + + // TODO need to convert from whatever ticks are these to Win32 100ns ticks + return sysTicks; +} + +uint64_t HAL_Time_CurrentTime() +{ + return 0; // UNDONE: FIXME: EmulatorNative::GetITimeDriver()->CurrentTime(); +} + +uint64_t HAL_Time_CurrentDateTime(bool datePartOnly) +{ + if (datePartOnly) + { + SYSTEMTIME st; + HAL_Time_ToSystemTime(HAL_Time_CurrentTime(), &st); + + st.wHour = 0; + st.wMinute = 0; + st.wSecond = 0; + st.wMilliseconds = 0; + + return HAL_Time_ConvertFromSystemTime(&st); + } + else + { + // on Windows we'll just return what is the current time from HAL + return HAL_Time_CurrentTime(); + } +} + +void HAL_Time_GetDriftParameters ( signed int* a, signed int* b, signed __int64* c ) +{ + *a = 1; + *b = 1; + *c = 0; +} + +unsigned int CPU_SystemClock() +{ + return 0; // UNDONE: FIXME: EmulatorNative::GetITimeDriver()->SystemClock; +} + +unsigned int CPU_TicksPerSecond() +{ + return 0; // UNDONE: FIXME: EmulatorNative::GetITimeDriver()->TicksPerSecond; +} + +//Completions + +void HAL_COMPLETION::InitializeList() +{ +} + +void HAL_COMPLETION::EnqueueDelta( unsigned int uSecFromNow ) +{ + // UNDONE: FIXME: EmulatorNative::GetITimeDriver()->EnqueueCompletion( (IntPtr)this, uSecFromNow ); +} + +void HAL_COMPLETION::EnqueueTicks( uint64_t EventTimeTicks ) +{ + _ASSERTE(FALSE); +} + +void HAL_COMPLETION::Abort() +{ + // UNDONE: FIXME: EmulatorNative::GetITimeDriver()->AbortCompletion( (IntPtr)this ); +} + +void HAL_COMPLETION::Execute() +{ + if(this->ExecuteInISR) + { + HAL_CONTINUATION* cont = this; + + cont->Execute(); + } + else + { + this->Enqueue(); + } +} + +//Continuations +void HAL_CONTINUATION::InitializeList() +{ +} + +bool HAL_CONTINUATION::IsLinked() +{ + return false; // UNDONE: FIXME: EmulatorNative::GetITimeDriver()->IsLinked( (IntPtr)this ); +} + +bool HAL_CONTINUATION::Dequeue_And_Execute() +{ + return 0; // UNDONE: FIXME: EmulatorNative::GetITimeDriver()->DequeueAndExecuteContinuation(); +} + +void HAL_CONTINUATION::InitializeCallback( HAL_CALLBACK_FPN EntryPoint, void* Argument ) +{ + Initialize(); + + Callback.Initialize( EntryPoint, Argument ); +} + +void HAL_CONTINUATION::Enqueue() +{ + _ASSERTE(this->GetEntryPoint() != NULL); + + // UNDONE: FIXME: EmulatorNative::GetITimeDriver()->EnqueueContinuation( (IntPtr) this ); +} + +void HAL_CONTINUATION::Abort() +{ + // UNDONE: FIXME: EmulatorNative::GetITimeDriver()->AbortContinuation( (IntPtr) this ); +} + +//various + +//void CLR_RT_EmulatorHooks::Notify_ExecutionStateChanged() +//{ +// // UNDONE: FIXME: EmulatorNative::GetITimeDriver()->IsExecutionPaused = ClrIsDebuggerStopped(); +//} + diff --git a/source/native/nf-interpreter/targets/os/win32/nanoCLR/targetver.h b/source/native/nf-interpreter/targets/os/win32/nanoCLR/targetver.h new file mode 100644 index 00000000..357aac41 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/nanoCLR/targetver.h @@ -0,0 +1,13 @@ +// +// Copyright (c) 2017 The nanoFramework project contributors +// See LICENSE file in the project root for full license information. +// +#pragma once + +// Including SDKDDKVer.h defines the highest available Windows platform. + +// If you wish to build your application for a previous Windows platform, include WinSDKVer.h and +// set the _WIN32_WINNT macro to the platform you wish to support before including SDKDDKVer.h. + +#include + diff --git a/source/native/nf-interpreter/targets/os/win32/netnf/TestApplication/NF.TestApplication.nfproj b/source/native/nf-interpreter/targets/os/win32/netnf/TestApplication/NF.TestApplication.nfproj new file mode 100644 index 00000000..766d6142 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/netnf/TestApplication/NF.TestApplication.nfproj @@ -0,0 +1,56 @@ + + + + $(MSBuildToolsPath)..\..\..\nanoFramework\v1.0\ + + + + Debug + AnyCPU + {11A8DD76-328B-46DF-9F39-F559912D0360};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + 247f9798-e240-4d5b-956d-35e5ead21ce2 + Exe + Properties + 512 + TestApplication + TestApplication + v1.0 + TestApplication + + + + + + + + + ..\..\packages\nanoFramework.CoreLibrary.1.0.0-preview038\lib\mscorlib.dll + True + True + + + ..\..\packages\nanoFramework.Runtime.Events.1.0.0-preview165\lib\nanoFramework.Runtime.Events.dll + True + True + + + ..\..\packages\nanoFramework.Windows.Devices.Gpio.1.0.0-preview164\lib\Windows.Devices.Gpio.dll + True + True + + + ..\..\packages\nanoFramework.Windows.Devices.Spi.1.0.0-preview164\lib\Windows.Devices.Spi.dll + True + True + + + + + + + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/os/win32/netnf/TestApplication/Program.cs b/source/native/nf-interpreter/targets/os/win32/netnf/TestApplication/Program.cs new file mode 100644 index 00000000..f21a544c --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/netnf/TestApplication/Program.cs @@ -0,0 +1,104 @@ +using System; +using System.Threading; +using Windows.Devices.Gpio; +using Windows.Devices.Spi; + +namespace NF.TestApplication_NEW +{ + public class Program + { + // For F4-Discovery -> Off board LED is on PB7 = 1 * 16 + 7 = 23 + // For F429I-Discovery -> Off board LED is on PG13 = 6 * 16 + 13 = 109 + // For F769I-DISCO -> LED2_GREEN is on PJ5 = 9 * 16 + 5 = 149 + // For F769I-DISCO -> LED2_RED is on PJ13 = 9 * 16 + 13 = 157 + // For F769I-DISCO -> USER_BUTTON is on PA0 = 0 * 16 + 0 = 0 + // For F746ZG-NUCLEO -> Off board LED is on PC10 = 2 * 16 + 10 = 42 + private const int LED_PIN = 149; + private const int LED_RED_PIN = 157; + private const int USER_BUTTON_PIN = 0; + + // Set up the LED + private static GpioPin LED; + private static GpioPin LED1; + private static GpioPin UserButton; + + private static SpiDevice MemsSensor; + + private static int dummyIntForTimer = 0; + private static int dummyIntForGpio = 0; + + public static void Main() + { + //////////////////////////////////////////////////////////////////////////////////// + // ToString() test + int thisIsAnInteger = 64; + var testString = thisIsAnInteger.ToString(); + + + //////////////////////////////////////////////////////////////////////////////////// + // timer test + Timer t = new Timer(TimerCb, null, 5000, 5000); + + + //////////////////////////////////////////////////////////////////////////////////// + // Gpio test + + var gpio = GpioController.GetDefault(); + + // red LED + LED1 = gpio.OpenPin(109); + LED1.SetDriveMode(GpioPinDriveMode.Output); + + // user button + UserButton = gpio.OpenPin(USER_BUTTON_PIN); + UserButton.SetDriveMode(GpioPinDriveMode.Input); + UserButton.ValueChanged += UserButton_ValueChanged; + + + //////////////////////////////////////////////////////////////////////////////////// + // Spi test + + var settings = new SpiConnectionSettings(3) // PA3:CS1 + { + Mode = SpiMode.Mode1, + ClockFrequency = 12 * 1000 * 1000, // 12Mhz + DataBitLength = 8 + }; + + MemsSensor = SpiDevice.FromId("SPI5", settings); + + //ushort[] redBuffer = new ushort[4]; + //MemsSensor.TransferFullDuplex(new ushort[] { 0x100, 0x200, 0x300, 0x400 }, redBuffer); + + MemsSensor.Write(new ushort[] { 0x100, 0x200, 0x300, 0x400 }); + + //////////////////////////////////////////////////////////////////////////////////// + while (true) + { + Thread.Sleep(1000); + } + } + + private static void TimerCb(object state) + { + // doing stuff + dummyIntForTimer++; + + Console.WriteLine(dummyIntForTimer.ToString()); + } + + static void UserButton_ValueChanged(object sender, GpioPinValueChangedEventArgs e) + { + dummyIntForGpio++; + + if (e.Edge == GpioPinEdge.RisingEdge) + { + LED1.Write(GpioPinValue.High); + } + else + { + LED1.Write(GpioPinValue.Low); + } + } + } +} diff --git a/source/native/nf-interpreter/targets/os/win32/netnf/TestApplication/Properties/AssemblyInfo.cs b/source/native/nf-interpreter/targets/os/win32/netnf/TestApplication/Properties/AssemblyInfo.cs new file mode 100644 index 00000000..262254df --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/netnf/TestApplication/Properties/AssemblyInfo.cs @@ -0,0 +1,33 @@ +using System.Reflection; +using System.Runtime.CompilerServices; +using System.Runtime.InteropServices; + +// General Information about an assembly is controlled through the following +// set of attributes. Change these attribute values to modify the information +// associated with an assembly. +[assembly: AssemblyTitle("CSharp.BlankApplication")] +[assembly: AssemblyDescription("")] +[assembly: AssemblyConfiguration("")] +[assembly: AssemblyCompany("")] +[assembly: AssemblyProduct("CSharp.BlankApplication")] +[assembly: AssemblyCopyright("Copyright © ")] +[assembly: AssemblyTrademark("")] +[assembly: AssemblyCulture("")] + +// Setting ComVisible to false makes the types in this assembly not visible +// to COM components. If you need to access a type in this assembly from +// COM, set the ComVisible attribute to true on that type. +[assembly: ComVisible(false)] + +// Version information for an assembly consists of the following four values: +// +// Major Version +// Minor Version +// Build Number +// Revision +// +// You can specify all the values or you can default the Build and Revision Numbers +// by using the '*' as shown below: +// [assembly: AssemblyVersion("1.0.*")] +[assembly: AssemblyVersion("1.0.0.0")] +[assembly: AssemblyFileVersion("1.0.0.0")] diff --git a/source/native/nf-interpreter/targets/os/win32/netnf/TestApplication/TestApplication.sln b/source/native/nf-interpreter/targets/os/win32/netnf/TestApplication/TestApplication.sln new file mode 100644 index 00000000..7f7c627f --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/netnf/TestApplication/TestApplication.sln @@ -0,0 +1,25 @@ + +Microsoft Visual Studio Solution File, Format Version 12.00 +# Visual Studio 15 +VisualStudioVersion = 15.0.27130.2003 +MinimumVisualStudioVersion = 10.0.40219.1 +Project("{11A8DD76-328B-46DF-9F39-F559912D0360}") = "NF.TestApplication", "NF.TestApplication.nfproj", "{247F9798-E240-4D5B-956D-35E5EAD21CE2}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|Any CPU = Debug|Any CPU + Release|Any CPU = Release|Any CPU + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {247F9798-E240-4D5B-956D-35E5EAD21CE2}.Debug|Any CPU.ActiveCfg = Debug|Any CPU + {247F9798-E240-4D5B-956D-35E5EAD21CE2}.Debug|Any CPU.Build.0 = Debug|Any CPU + {247F9798-E240-4D5B-956D-35E5EAD21CE2}.Release|Any CPU.ActiveCfg = Release|Any CPU + {247F9798-E240-4D5B-956D-35E5EAD21CE2}.Release|Any CPU.Build.0 = Release|Any CPU + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection + GlobalSection(ExtensibilityGlobals) = postSolution + SolutionGuid = {62117BDC-3FD8-42D4-9171-A4B4F12F46BB} + EndGlobalSection +EndGlobal diff --git a/source/native/nf-interpreter/targets/os/win32/netnf/TestApplication/packages.config b/source/native/nf-interpreter/targets/os/win32/netnf/TestApplication/packages.config new file mode 100644 index 00000000..7a4b9592 --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/netnf/TestApplication/packages.config @@ -0,0 +1,7 @@ + + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/targets/os/win32/packages.config b/source/native/nf-interpreter/targets/os/win32/packages.config new file mode 100644 index 00000000..2bc6cdfa --- /dev/null +++ b/source/native/nf-interpreter/targets/os/win32/packages.config @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/source/native/nf-interpreter/version.json b/source/native/nf-interpreter/version.json new file mode 100644 index 00000000..edb657ad --- /dev/null +++ b/source/native/nf-interpreter/version.json @@ -0,0 +1,24 @@ +{ + "$schema": "https://raw.githubusercontent.com/AArnott/Nerdbank.GitVersioning/master/src/NerdBank.GitVersioning/version.schema.json", + "version": "1.4.0-preview.{height}", + "assemblyVersion": { + "precision": "revision" + }, + "publicReleaseRefSpec": [ + "^refs/heads/master$", + "^refs/heads/v\\d+(?:\\.\\d+)?$" + ], + "cloudBuild": { + "setAllVariables": true, + "buildNumber": { + "enabled": true, + "includeCommitId": { + "when": "always" + } + } + }, + "release": { + "branchName": "release-v{version}", + "firstUnstableTag": "preview" + } +} diff --git a/source/version.json b/source/version.json index ca7341a5..80b78f94 100644 --- a/source/version.json +++ b/source/version.json @@ -1,6 +1,6 @@ { "$schema": "https://raw.githubusercontent.com/AArnott/Nerdbank.GitVersioning/master/src/NerdBank.GitVersioning/version.schema.json", - "version": "1.15", + "version": "2.0", "assemblyVersion": { "precision": "build" },